Updated the scalar regsiter assginment in indirect send

Use round robin to avoid WAR dependence

Author: bcheng0127

visa/BuildIR.h

@@ -758,10 +758,6 @@ class IR_Builder {
   G4_Declare *getBuiltinHWTID() const { return builtinHWTID; }
   G4_Declare *getBuiltinSR0Dot1() const { return builtinSR0Dot1; }
 
-  // The first part of s0 is reserved for Xe3+ Gather Send (indirect send)
-  // This tests if an operand refers to Gather Send or something else
-  bool isBuiltinSendIndirectS0(G4_Operand *op) const;
-
   G4_Declare *getBuiltinT252() const { return builtinT252; }
   G4_Declare *getBuiltinBindlessSampler() const {
     return builtinBindlessSampler;

visa/BuildIRImpl.cpp

@@ -1908,24 +1908,6 @@ G4_INST *IR_Builder::createInternalBfnInst(
   return ii;
 }
 
-bool IR_Builder::isBuiltinSendIndirectS0(G4_Operand *op) const
-{
-  const G4_Declare *d = op->getTopDcl();
-  if (d == nullptr || d->getRegFile() != G4_SCALAR)
-    return false;
-  unsigned rightBound = 0;
-  if (op->isDstRegRegion()) {
-    G4_DstRegRegion *dst = op->asDstRegRegion();
-    rightBound = dst->getRightBound();
-  } else if (op->isSrcRegRegion()) {
-    G4_SrcRegRegion *dst = op->asSrcRegRegion();
-    rightBound = dst->getRightBound();
-  } else {
-    return false;
-  }
-  return rightBound < 8 * FIRST_SURFACE_S0_QW;
-}
-
 // scratch surfaces, write the content of T251 to extended message descriptor
 // exdesc holds the value of the extended message descriptor for bit [0:11]
 // add (1) a0.2<1>:ud T251<1>:ud exDesc:ud {NoMask}

visa/Passes/SRSubstitution.cpp

@@ -39,7 +39,8 @@ static bool regSortCompareAfterRA(regMapBRA map1, regMapBRA map2) {
   return false;
 }
 
-void changeToIndirectSend(G4_INST *inst, G4_Declare *s0Var, int totalRegs,
+void changeToIndirectSend(G4_INST *inst, G4_Declare *s0Var,
+                          unsigned short S0Sub, int totalRegs,
                           IR_Builder &builder, bool isLargeGRF) {
   // Change the send instruction to sendi
   G4_InstSend *Send = inst->asSendInst();
@@ -56,7 +57,7 @@ void changeToIndirectSend(G4_INST *inst, G4_Declare *s0Var, int totalRegs,
   // Replace source 0 with scalar register
   G4_SrcRegRegion *headerOpnd =
       builder.createSrcRegRegion(Mod_src_undef, IndirGRF, s0Var->getRegVar(), 0,
-                                 0, builder.getRegionScalar(), Type_UB);
+                                 S0Sub * 8, builder.getRegionScalar(), Type_UB);
   // Replace source 1 with null.
   G4_SrcRegRegion *payloadToUse = builder.createNullSrc(Type_UD);
 
@@ -286,7 +287,7 @@ bool SRSubPass::replaceWithSendi(G4_BB *bb, INST_LIST_ITER instIter,
     bb->insertBefore(instIter, movInst);
   }
 
-  changeToIndirectSend(inst, s0Var, totalRegs, builder, false);
+  changeToIndirectSend(inst, s0Var, 0, totalRegs, builder, false);
 
   return true;
 }
@@ -762,6 +763,54 @@ bool SRSubPassAfterRA::isSRCandidateAfterRA(G4_INST *inst,
 }
 
 
+unsigned short SRSubPassAfterRA::allocateS0(unsigned short UQNum) {
+  unsigned short freeSRSub = S0Index;
+  bool find = false;
+  for (; freeSRSub < S0SubRegNum;
+       freeSRSub++) {
+    if (UQNum > 1 && (freeSRSub + 1) < S0SubRegNum) {
+      if (!UsedS0SubReg.isSet(freeSRSub) &&
+          !UsedS0SubReg.isSet(freeSRSub + 1)) {
+        find = true;
+        S0Index += 2;
+        break;
+      }
+    } else if ((UQNum == 1) && !UsedS0SubReg.isSet(freeSRSub)) {
+      find = true;
+      S0Index++;
+      break;
+    }
+    S0Index++;
+  }
+
+  if (find) {
+    return freeSRSub;
+  }
+
+  for (freeSRSub = 0; freeSRSub < S0Index; freeSRSub++) {
+    if (UQNum > 1 && (freeSRSub + 1) < S0SubRegNum) {
+      if (!UsedS0SubReg.isSet(freeSRSub) &&
+          !UsedS0SubReg.isSet(freeSRSub + 1)) {
+        find = true;
+        S0Index += 2;
+        break;
+      }
+    } else if ((UQNum == 1) && !UsedS0SubReg.isSet(freeSRSub)) {
+      find = true;
+      S0Index++;
+      break;
+    }
+    S0Index++;
+  }
+
+  if (S0Index >= S0SubRegNum) {
+    S0Index = 0;
+  }
+  // At most 2 Qwords required, since we reserved two QWords, should always find
+  assert(find);
+  return freeSRSub;
+}
+
 // Replace the send instruction with the payload of
 // Insert the scalar register intialization mov instructions.
 bool SRSubPassAfterRA::replaceWithSendiAfterRA(G4_BB *bb,
@@ -873,10 +922,11 @@ bool SRSubPassAfterRA::replaceWithSendiAfterRA(G4_BB *bb,
   if (dstSrcRegs.isLargeGRF) {
     UQNum = totalRegs > (TypeSize(Type_UQ) / TypeSize(Type_UW)) ? 2 : 1;
   }
+  unsigned short S0Sub = allocateS0(UQNum);
   G4_Declare *s0Var = builder.createTempScalar(UQNum, "S0_");
   s0Var->getRegVar()->setPhyReg(builder.phyregpool.getScalarReg(), 0);
   G4_DstRegRegion *dst =
-      builder.createDst(s0Var->getRegVar(), 0, 0, 1, Type_UQ);
+      builder.createDst(s0Var->getRegVar(), 0, S0Sub, 1, Type_UQ);
   G4_INST *movInst = nullptr;
   if (!dstSrcRegs.isLargeGRF) {
     movInst = builder.createIntrinsicAddrMovInst(
@@ -891,7 +941,7 @@ bool SRSubPassAfterRA::replaceWithSendiAfterRA(G4_BB *bb,
 
   if (UQNum > 1) {
     G4_DstRegRegion *dst1 =
-        builder.createDst(s0Var->getRegVar(), 0, 1, 1, Type_UQ);
+        builder.createDst(s0Var->getRegVar(), 0, S0Sub + 1, 1, Type_UQ);
     G4_INST *movInst1 = nullptr;
     if (!dstSrcRegs.isLargeGRF) {
       movInst1 = builder.createIntrinsicAddrMovInst(
@@ -916,7 +966,8 @@ bool SRSubPassAfterRA::replaceWithSendiAfterRA(G4_BB *bb,
     }
   }
 
-  changeToIndirectSend(inst, s0Var, totalRegs, builder, dstSrcRegs.isLargeGRF);
+  changeToIndirectSend(inst, s0Var, S0Sub, totalRegs, builder,
+                       dstSrcRegs.isLargeGRF);
 
   return true;
 }
@@ -933,12 +984,15 @@ void SRSubPassAfterRA::SRSubAfterRA(G4_BB *bb) {
   std::map<G4_INST *, regCandidatesBRA> candidates;
   std::map<G4_INST *, regCandidatesBRA>::iterator candidatesIt;
 
+  S0SubRegNum = builder.getScalarRegisterSizeInBytes() / 8;
+  UsedS0SubReg.resize(S0SubRegNum);
+  S0Index = 0;
+
   INST_LIST_ITER ii = bb->begin(), iend(bb->end());
   unsigned candidateStart = builder.getuint32Option(vISA_IndirectInstStart);
   unsigned candidateEnd = builder.getuint32Option(vISA_IndirectInstEnd);
   while (ii != iend) {
     G4_INST *inst = *ii;
-
     regCandidatesBRA dstSrcRegs;
     if (!isSRCandidateAfterRA(inst, dstSrcRegs)) {
       ii++;

visa/Passes/SRSubstitution.hpp

@@ -94,6 +94,9 @@ class SRSubPass {
 class SRSubPassAfterRA {
   IR_Builder &builder;
   G4_Kernel &kernel;
+  BitSet UsedS0SubReg;
+  unsigned short S0SubRegNum = 0;
+  unsigned short S0Index = 0;
   unsigned candidateID = 0;
 
 public:
@@ -110,6 +113,7 @@ class SRSubPassAfterRA {
     }
   }
   bool isSRCandidateAfterRA(G4_INST *inst, regCandidatesBRA &dstSrcRegs);
+  unsigned short allocateS0(unsigned short UQNum);
   bool replaceWithSendiAfterRA(G4_BB *bb, INST_LIST_ITER instIter,
                                regCandidatesBRA &dstSrcRegs);
   void SRSubAfterRA(G4_BB *bb);