@whitneywhtsang what device properties should we look at first? Could you please advise?

The reason why scaled_dot tests are not working is likely because DPAS is not used. Below are some reasons why DPAS is not used:

• PyTorch doesn't pass device properties (e.g. LTS driver)
• device property cl_intel_subgroup_matrix_multiply_accumulate is not supported on the platform
• device minimum subgroup size is not 16 (https://github.com/intel/intel-xpu-backend-for-triton/blob/main/third_party/intel/lib/TritonAnnotateModule/TritonAnnotateModule.cpp#L52)

@whitneywhtsang what device properties should we look at first? Could you please advise?

The reason why scaled_dot tests are not working is likely because DPAS is not used. Below are some reasons why DPAS is not used:

• PyTorch doesn't pass device properties (e.g. LTS driver)
• device property cl_intel_subgroup_matrix_multiply_accumulate is not supported on the platform
• device minimum subgroup size is not 16 (https://github.com/intel/intel-xpu-backend-for-triton/blob/main/third_party/intel/lib/TritonAnnotateModule/TritonAnnotateModule.cpp#L52)

Surprising if that is the case. For lowering tt.dot we should already use DPAS and 2D block reads and we have unit tests to check the codegen.

A770 and MTL do not have DPAS (A770 only supports 8 threads per warp, MTL does not have the hardware support at all).

@LiyangLingIntel Can you please look into the xe2 scaled_dot failures?

I tried to reproduce the scaled_dot failures on BMG, but only one fail test/unit/language/test_core.py::test_scaled_dot[128-32-64-False-False-True-e4m3-bf16-4-16-1] which is the known issue in #2968.
Just removed test_scaled_dot from xe2 skiplist and triggered CI, https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/13279132310/job/37073967686 shows they are all passed.
It seems no extra work needs to be done.

@anmyachev can you help confirm this?

There is no DPAS support for A770 and MTL, we should keep it in the skiplist.

Created PR(#3403) to remove the most scaled_dot cases from the Xe2 skiplist, the remaining one will be covered in #2968.
If there is no further comment, #3403 will close this issue.

Hi @LiyangLingIntel

Just removed test_scaled_dot from xe2 skiplist and triggered CI, https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/13279132310/job/37073967686 shows they are all passed.

This CI doesn't use Xe2 skiplist and runs on PVC, right? To check, you need to run CI on LNL (also uses this skiplist) or on BMG, this can be done in the internal repository. On the other hand, if you manually checked that the tests are working, then it is quite possible that there could be some instability in the runner.

There is no DPAS support for A770 and MTL, we should keep it in the skiplist.

DPAS is about performance, right? Why isn't it expected that these tests will at least work correctly on these devices?

DPAS is about performance, right? Why isn't it expected that these tests will at least work correctly on these devices?

Not exactly, the most of our features are enabled on DPAS. If not going to the DPAS path, we have to go to the FMA Dot which only support the basic dot, and this should be same to NV and AMD.
If we want to enable these on FMA path, corresponding changes should also be made on the common files.

DPAS is about performance, right? Why isn't it expected that these tests will at least work correctly on these devices?

Not exactly, the most of our features are enabled on DPAS. If not going to the DPAS path, we have to go to the FMA Dot which only support the basic dot, and this should be same to NV and AMD. If we want to enable these on FMA path, corresponding changes should also be made on the common files.

I see

It seems no extra work needs to be done.

@anmyachev can you help confirm this?

These tests are still falling in CI.