Lean: fix assign_rename_bug.sail

Author: javra

test/c/assign_rename_bug.sail

@@ -11,6 +11,7 @@ $option -undefined_gen
 val sub_vec_int = {
   c: "sub_bits_int",
   systemverilog: "sub_bits_int",
+  lean: "BitVec.subInt",
   _: "sub_vec_int"
 } : forall 'n. (bits('n), int) -> bits('n)
 

test/lean/run_tests.py

@@ -25,7 +25,6 @@
     'outcome_impl', # custom outcome types (not expected to work)
     'outcome_impl_int', # custom outcome types (not expected to work)
     'outcome_impl_bool', # custom outcome types (not expected to work)
-    'assign_rename_bug',
     'union_variant_names',
     'varswap',
     'real',