refactor(ReentrantSpinlock): core_id from generics

Author: n1tram1

hal_aarch64/src/lib.rs

@@ -42,3 +42,18 @@ unsafe extern "C" fn _start() -> ! {
         options(noreturn)
     );
 }
+
+pub struct Aarch64CoreInfo;
+
+impl hal_core::CoreInfo for Aarch64CoreInfo {
+    fn init(_core_id: usize) {
+        // We just read MPIDR_EL1 on aarch64.
+    }
+
+    fn core_id() -> usize {
+        let mpidr = MPIDR_EL1.get() as usize;
+        assert!(mpidr < usize::MAX);
+
+        mpidr
+    }
+}

hal_core/src/hal.rs

@@ -4,20 +4,25 @@ use super::Error;
 use super::{IrqOps, TimerCallbackFn};
 use super::ReentrantSpinlock;
 use super::once_lock::OnceLock;
+use super::CoreInfo;
 
-pub struct Hal<P: PageMap + 'static, I: IrqOps> {
-    kpt: OnceLock<ReentrantSpinlock<&'static mut P>>,
+pub struct Hal<P: PageMap + 'static, I: IrqOps, G: CoreInfo> {
+    kpt: OnceLock<ReentrantSpinlock<G, &'static mut P>>,
     irq_ops: I,
 }
 
-impl<P: PageMap + Mmu + 'static, I: IrqOps> Hal<P, I> {
-    pub const fn new(irq_ops: I) -> Hal<P, I> {
+impl<P: PageMap + Mmu + 'static, I: IrqOps, G: CoreInfo> Hal<P, I, G> {
+    pub const fn new(irq_ops: I) -> Hal<P, I, G> {
         Self {
             kpt: OnceLock::new(),
             irq_ops,
         }
     }
 
+    pub fn init_core_info(&self, core_id: usize) {
+        G::init(core_id)
+    }
+
     pub fn init_irqs(&'static self) {
         self.irq_ops.init();
     }
@@ -82,7 +87,7 @@ impl<P: PageMap + Mmu + 'static, I: IrqOps> Hal<P, I> {
         mm::align_down(val, self.page_size())
     }
 
-    pub fn kpt(&'static self) -> &ReentrantSpinlock<&'static mut P> {
+    pub fn kpt(&'static self) -> &ReentrantSpinlock<G, &'static mut P> {
         self.kpt.get().unwrap()
     }
 }

hal_core/src/lib.rs

@@ -13,6 +13,11 @@ pub mod once_lock;
 mod reentrant_spinlock;
 pub use reentrant_spinlock::ReentrantSpinlock;
 
+pub trait CoreInfo {
+    fn init(core_id: usize);
+    fn core_id() -> usize;
+}
+
 pub trait IrqOps {
     fn init(&'static self);
     fn init_irq_chip(&self, allocator: &impl mm::PageAlloc) -> Result<(), Error>;

hal_core/src/reentrant_spinlock.rs

@@ -1,30 +1,20 @@
 use core::sync::atomic::{AtomicBool, AtomicUsize, Ordering};
+use core::marker::PhantomData;
 use lock_api::{GuardSend, RawMutex};
 
-pub struct RawReentrantSpinlock {
+use crate::CoreInfo;
+
+pub struct RawReentrantSpinlock<G> {
     user: AtomicUsize,
     lock: AtomicBool,
+    _marker: PhantomData<G>,
 }
 
-fn core_id() -> usize {
-    let mut id: u64;
-
-#[cfg(target_arch="aarch64")]
-    unsafe { core::arch::asm!("mrs {:x}, mpidr_el1", out(reg) id) };
-
-#[cfg(target_arch="riscv64")]
-    {
-        // unsafe { core::arch::asm!("csrr {}, mhartid", out(reg) id) };
-        id = 0;
-    }
-
-    id as usize
-}
-
-unsafe impl RawMutex for RawReentrantSpinlock {
-    const INIT: RawReentrantSpinlock = RawReentrantSpinlock {
+unsafe impl<G: CoreInfo> RawMutex for RawReentrantSpinlock<G> {
+    const INIT: RawReentrantSpinlock<G> = RawReentrantSpinlock::<G> {
         user: AtomicUsize::new(usize::MAX),
         lock: AtomicBool::new(false),
+        _marker: PhantomData,
     };
 
     // A spinlock guard can be sent to another thread and unlocked there
@@ -37,7 +27,7 @@ unsafe impl RawMutex for RawReentrantSpinlock {
     }
 
     fn try_lock(&self) -> bool {
-        let my_id = core_id();
+        let my_id = G::core_id();
 
         if self.user.load(Ordering::Acquire) == my_id {
             assert_eq!(self.lock.load(Ordering::Relaxed), true);
@@ -53,7 +43,7 @@ unsafe impl RawMutex for RawReentrantSpinlock {
             .is_ok()
             && self
                 .user
-                .compare_exchange(usize::MAX, core_id(), Ordering::Acquire, Ordering::Relaxed)
+                .compare_exchange(usize::MAX, my_id, Ordering::Acquire, Ordering::Relaxed)
                 .is_ok()
     }
 
@@ -63,4 +53,4 @@ unsafe impl RawMutex for RawReentrantSpinlock {
     }
 }
 
-pub type ReentrantSpinlock<T> = lock_api::Mutex<RawReentrantSpinlock, T>;
+pub type ReentrantSpinlock<G, T> = lock_api::Mutex<RawReentrantSpinlock<G>, T>;

hal_riscv64/src/lib.rs

@@ -17,3 +17,16 @@ pub fn panic_info() {}
 unsafe extern "C" fn _start() -> ! {
     asm!("la sp, STACK_START", "call k_main", options(noreturn));
 }
+
+pub struct Riscv64CoreInfo;
+
+impl hal_core::CoreInfo for Riscv64CoreInfo {
+    fn init(core_id: usize) {
+        // The core_id is the value in the mhartid CSR we got from the machine-level firmware.
+        registers::set_sscratch(core_id);
+    }
+    fn core_id() -> usize {
+        // Early kernel code called Self::init and putthe core_id argument into the sscratch.
+        registers::get_sscratch()
+    }
+}

hal_riscv64/src/registers.rs

@@ -29,3 +29,19 @@ pub fn set_stvec(addr: usize) {
         asm!("csrw stvec, {}", in(reg)(addr));
     }
 }
+
+pub fn set_sscratch(val: usize) {
+    unsafe {
+        asm!("csrw sscratch, {}", in(reg)(val));
+    }
+}
+
+pub fn get_sscratch() -> usize {
+    let mut val: usize;
+
+    unsafe {
+        asm!("csrr {}, sscratch", out(reg)(val));
+    }
+
+    val
+}

kernel/src/lib.rs

@@ -38,17 +38,19 @@ cfg_if::cfg_if! {
         use hal_aarch64::{
             mm::pgt48,
             irq::Aarch64Irqs,
+            Aarch64CoreInfo,
         };
         use hal_core::Hal;
-        pub static HAL: Hal<pgt48::PageTable, Aarch64Irqs> = Hal::new(Aarch64Irqs::new());
+        pub static HAL: Hal<pgt48::PageTable, Aarch64Irqs, Aarch64CoreInfo> = Hal::new(Aarch64Irqs::new());
     } else if #[cfg(target_arch = "riscv64")] {
         pub type ConsoleImpl = drivers::ns16550::Ns16550;
         use hal_riscv64::{
             mm::sv39,
             irq::Riscv64Irqs,
+            Riscv64CoreInfo,
         };
         use hal_core::Hal;
-        pub static HAL: Hal<sv39::PageTable, Riscv64Irqs> = Hal::new(Riscv64Irqs::new());
+        pub static HAL: Hal<sv39::PageTable, Riscv64Irqs, Riscv64CoreInfo> = Hal::new(Riscv64Irqs::new());
     }
 }
 

riscv64_qemuvirt/src/main.rs

@@ -15,16 +15,18 @@ pub const UART_INTERRUPT_NUMBER: u16 = 10;
 const LAUNCH_TESTS: bool = cfg!(feature = "launch_tests");
 
 #[no_mangle]
-extern "C" fn k_main(_core_id: usize, device_tree_ptr: usize) -> ! {
+extern "C" fn k_main(core_id: usize, device_tree_ptr: usize) -> ! {
+    kernel::HAL.init_core_info(core_id);
+    kernel::HAL.init_irqs();
+
     static NS16550: Ns16550 = Ns16550::new(UART_ADDR);
     kernel::kernel_console::set_earlyinit_console(&NS16550);
 
     kernel::kernel_console::init_logging().unwrap();
 
+    assert_eq!(core_id, 0, "Kernel must be booted on the first core with id == 0");
     info!("GoOSe is booting");
 
-    kernel::HAL.init_irqs();
-
     let device_tree = kernel::device_tree::DeviceTree::new(device_tree_ptr).unwrap();
     kernel::generic_main::generic_main::<LAUNCH_TESTS>(device_tree, &[&NS16550]);
 }