Branch prediction is currently disabled. To work around this issue, branches have to take 4 cycles for now.
This happens because on Leon3's pipeline branch prediction used integer flags C,V,N,Z (previously set), this way branch instruction just had to evaluate if the condition flags already set matched branch condition. RISC-V branch needs to read 2 registers, evaluate a condition and then decide to branch or not.
This issue will require more significant changes on pipeline to be solved.