GRMON2 and RISCV

[lcbcFoo]

We currently use GRMON2 to debug the processor since it was made for Leon3 and is part of the support we aimed to gain changing its ISA. However, GRMON2 expects a SPARC program and does not support RISC-V. This causes some inconveniences, such as:

• GRMON2 assumes processor is using big endian, even though we are not. Therefore it displays bytes of a word backwards, for example:
  Number 974169 in RISC-V convention is 0x 00 0E DD 59, GRMON2 shows it as 0x 59 DD 0E 00. This is only a visual inconvenience that must be kept in mind when reading values from memory while using GRMON2. When dumping values using dump, bytes are on correct order.

• GRMON2, again, expects SPARC not RISC-V. This means it translates instructions using SPARC ISA as base, for example, when disassembling memory:

grmon2> disassemble 0x43000000                           

       0x43000000: 01000000  nop                         
       0x43000004: 01000000  nop                                                     
       0x43000008: 02000000  unimp                                                           
       0x4300000c: 03000000  sethi  %hi(0x0), %g1                                          
       0x43000010: 05000000  sethi  %hi(0x0), %g2                                        
       0x43000014: 08000000  unimp
       0x43000018: 0d000000  sethi  %hi(0x0), %g6
       0x4300001c: 15000000  sethi  %hi(0x0), %o2        
       0x43000020: 01000000  nop                         
       0x43000024: 01000000  nop
       0x43000028: 02000000  unimp
       0x4300002c: 03000000  sethi  %hi(0x0), %g1
       0x43000030: 05000000  sethi  %hi(0x0), %g2
       0x43000034: 08000000  unimp
       0x43000038: 0d000000  sethi  %hi(0x0), %g6
       0x4300003c: 15000000  sethi  %hi(0x0), %o2     

This is annoying, but can be ignored.

• Since SPARC used register windows, we need to run 2 commands to see all 32 registers RISC-V uses:

grmon2> reg         # Columns INS, LOCALS and OUTS represents registers 8-31 (8 is OUTS 0, 16 is LOCALS 0, 24 is INS 0)

         INS        LOCALS     OUTS       GLOBALS 
     0:  00000000   00000000   43FFFFF0   00000000
     1:  00000000   00000000   00000000   00000000
     2:  00000000   00000000   00000000   00000000
     3:  00000000   00000000   43FFFFC8   00000000 
     4:  00000000   00000000   00000004   00000000
     5:  00000000   00000000   44000020   00000000 
     6:  00000000   00000000   44000024   00000000 
     7:  00000000   00000000   00000000   00000000  
     
   psr: F35000E0   wim: 00000002   tbr: 40001000   y: 00000000
   pc:   400010B8  call  0x0C0050B8 
   npc:  400010BC  sethi  %hi(0x0), %o1  
   
grmon2> reg w7      # The LOCALS column shows our registers 0-7 (LOCALS 0 is our 0)

         INS        LOCALS     OUTS       GLOBALS
     0:  43FFFFF0   00000000   00000000   00000000                                           
     1:  00000000   4000108C   00000000   00000000
     2:  00000000   43FFFFD0   00000000   00000000                                  
     3:  43FFFFC8   00000000   00000000   00000000                                    
     4:  00000004   00000000   00000000   00000000                                     
     5:  44000020   00000000   00000000   00000000                                   
     6:  44000024   00000000   00000000   00000000                                    
     7:  00000000   00000000   00000000   00000000  

The processor only uses 32 registers (although synthesis is still made with eight 32 registers windows), but GRMON2 displays them using SPARC convention. Again, only annoying visual issues.

There are other minor issues with GRMON2, but we can load, run and debug RISC-V programs with some restrictions. It clearly is not the ideal debug system, but we are still looking for better solutions.

[jeandet]

Hi,
I wrote a quite basic GPL tool called SocExplorer to develop and debug an embedded analyser for the SolarOrbiter probe.
It's definitely not finished and needs a lot of work but it exists.
I would be happy to collaborate if you are interested in this tool :)

[lcbcFoo]

Hi Jeandet,
This seems promising, I will try it out later this week, thanks for sharing!

[hgurbuzz]

Hi,
When I try to connect to the nexys 4 ddr card with the last version of grmon, I get an error like this:

JTAG chain (1): xc7a100t
ERROR! Bad vendor ID in AMBA Plug n' Play area!
ERROR! Grmon Evaluation version does not support this hardware desing. If a desing contains GRLIP IP cores that are not distributed under GPL licence, then an upgrade to GRMON professional version is required.
Is the problem related to the GRMON version? Can't you contain?

[lcbcFoo]

Hello @hgurbuzz

When I created ReonV only GRMON2 existed and it only supported SPARC (NOEL-V was not released yet so Gaisler had no reason to have a RISC-V debugger). Now that GRMON3 officially supports RISC-V the inconveniences listed in this ticket may have been solved, however I never tried to use GRMON3 so there may indeed be some issue to be adjusted in the design.

I will take a look into this, hopefully it should work without many issues. =)

[hgurbuzz]

I tried again with the latest versions for grmon and leon and worked. I think I got such an error because they are not in the same version or a mistake of mine. Right now everything is normal, thank you :)