Skip to content

Commit 42c3847

Browse files
author
brad
committed
latest
1 parent 3089f7b commit 42c3847

18 files changed

+492
-1965
lines changed

‎hw/74151.v

-26
Original file line numberDiff line numberDiff line change
@@ -27,30 +27,4 @@ module part_74S151 ( I0, I1, I2, I3, I4, I5, I6, I7,
2727

2828
assign Q_N = ! Q;
2929

30-
/*
31-
wire[2:0] d_bar,d_sel;
32-
33-
not #(`REG_DELAY)
34-
n0(d_bar[0],SEL0),
35-
n1(d_bar[1],SEL1),
36-
n2(d_bar[2],SEL2),
37-
n3(d_sel[0],d_bar[0]),
38-
n4(d_sel[1],d_bar[1]),
39-
n5(d_sel[2],d_bar[2]),
40-
n6(Q_N,Q),
41-
n7(str,CE_N);
42-
and #(`REG_DELAY)
43-
a0(wa0,I0,d_bar[2],d_bar[1],d_bar[0],str),
44-
a1(wa1,I1,d_bar[2],d_bar[1],d_sel[0],str),
45-
a2(wa2,I2,d_bar[2],d_sel[1],d_bar[0],str),
46-
a3(wa3,I3,d_bar[2],d_sel[1],d_sel[0],str),
47-
a4(wa4,I4,d_sel[2],d_bar[1],d_bar[0],str),
48-
a5(wa5,I5,d_sel[2],d_bar[1],d_sel[0],str),
49-
a6(wa6,I6,d_sel[2],d_sel[1],d_bar[0],str),
50-
a7(wa7,I7,d_sel[2],d_sel[1],d_sel[0],str);
51-
// nor #(`REG_DELAY)
52-
or #(`REG_DELAY)
53-
nr(Q,wa0,wa1,wa2,wa3,wa4,wa5,wa6,wa7);
54-
*/
55-
5630
endmodule

‎hw/74240.v

+14-2
Original file line numberDiff line numberDiff line change
@@ -13,14 +13,15 @@ module part_74S240(AIN0, AIN1, AIN2, AIN3,
1313

1414
input AIN0, AIN1, AIN2, AIN3;
1515
output AOUT0, AOUT1, AOUT2, AOUT3;
16-
reg AOUT0, AOUT1, AOUT2, AOUT3;
16+
// reg AOUT0, AOUT1, AOUT2, AOUT3;
1717
input AENB_N;
1818

1919
input BIN0, BIN1, BIN2, BIN3;
2020
output BOUT0, BOUT1, BOUT2, BOUT3;
21-
reg BOUT0, BOUT1, BOUT2, BOUT3;
21+
// reg BOUT0, BOUT1, BOUT2, BOUT3;
2222
input BENB_N;
2323

24+
/*
2425
always @(AENB_N)
2526
begin
2627
if (AENB_N)
@@ -60,5 +61,16 @@ module part_74S240(AIN0, AIN1, AIN2, AIN3,
6061
// assign {BOUT0, BOUT1, BOUT2, BOUT3} = ! {BIN0, BIN1, BIN2, BIN3};
6162
end
6263
end
64+
*/
65+
66+
assign AOUT0 = AENB_N ? 1'bz : !AIN0;
67+
assign AOUT1 = AENB_N ? 1'bz : !AIN1;
68+
assign AOUT2 = AENB_N ? 1'bz : !AIN2;
69+
assign AOUT3 = AENB_N ? 1'bz : !AIN3;
70+
71+
assign BOUT0 = BENB_N ? 1'bz : !BIN0;
72+
assign BOUT1 = BENB_N ? 1'bz : !BIN1;
73+
assign BOUT2 = BENB_N ? 1'bz : !BIN2;
74+
assign BOUT3 = BENB_N ? 1'bz : !BIN3;
6375

6476
endmodule

‎hw/74258.v

+21-14
Original file line numberDiff line numberDiff line change
@@ -10,32 +10,39 @@ module part_74S258 (A0, A1, B0, B1, C0, C1, D0, D1,
1010
input A0, A1, B0, B1, C0, C1, D0, D1;
1111
input SEL, ENB_N;
1212
output AY, BY, CY, DY;
13-
reg AY, BY, CY, DY;
1413

15-
always @(ENB_N or SEL)
14+
reg AY, BY, CY, DY;
15+
always @(ENB_N or SEL or A0 or A1 or B0 or B1 or C0 or C1 or D0 or D1)
1616
begin
1717
if (ENB_N)
1818
begin
19-
assign AY = 1'bz;
20-
assign BY = 1'bz;
21-
assign CY = 1'bz;
22-
assign DY = 1'bz;
19+
AY = 1'bz;
20+
BY = 1'bz;
21+
CY = 1'bz;
22+
DY = 1'bz;
2323
end
2424
else
2525
if (SEL)
2626
begin
27-
assign AY = ! A1;
28-
assign BY = ! B1;
29-
assign CY = ! C1;
30-
assign DY = ! D1;
27+
AY = ! A1;
28+
BY = ! B1;
29+
CY = ! C1;
30+
DY = ! D1;
3131
end
3232
else
3333
begin
34-
assign AY = ! A0;
35-
assign BY = ! B0;
36-
assign CY = ! C0;
37-
assign DY = ! D0;
34+
AY = ! A0;
35+
BY = ! B0;
36+
CY = ! C0;
37+
DY = ! D0;
3838
end
3939
end
4040

41+
/*
42+
assign AY = ENB_N ? 1'bz : (SEL ? !A1 : !A0);
43+
assign BY = ENB_N ? 1'bz : (SEL ? !B1 : !B0);
44+
assign CY = ENB_N ? 1'bz : (SEL ? !C1 : !C0);
45+
assign DY = ENB_N ? 1'bz : (SEL ? !D1 : !D0);
46+
*/
47+
4148
endmodule

‎hw/74283.v

-21
Original file line numberDiff line numberDiff line change
@@ -14,27 +14,6 @@ module part_74S283 (C0, A0, A1, A2, A3, B0, B1, B2, B3, S0, S1, S2, S3, C4);
1414
input C0, A0, A1, A2, A3, B0, B1, B2, B3;
1515
output S0, S1, S2, S3, C4;
1616

17-
/*
18-
wire[3:0] AA, BB, SS;
19-
20-
assign AA[0] = A0;
21-
assign AA[1] = A1;
22-
assign AA[2] = A2;
23-
assign AA[3] = A3;
24-
25-
assign BB[0] = B0;
26-
assign BB[1] = B1;
27-
assign BB[2] = B2;
28-
assign BB[3] = B3;
29-
30-
ic_74S283 blah (C0, AA, BB, SS, C4);
31-
32-
assign S0 = SS[0];
33-
assign S1 = SS[1];
34-
assign S2 = SS[2];
35-
assign S3 = SS[3];
36-
*/
37-
3817
ic_74S283 add (C0, {A3,A2,A1,A0}, {B3,B2,B1,B0}, {S3,S2,S1,S0}, C4);
3918

4019
endmodule

‎hw/74373.v

+12-35
Original file line numberDiff line numberDiff line change
@@ -12,49 +12,26 @@ module part_74S373 (
1212
input I0, I1, I2, I3, I4, I5, I6, I7;
1313
input HOLD_N, OENB_N;
1414
output O0, O1, O2, O3, O4, O5, O6, O7;
15-
reg O0, O1, O2, O3, O4, O5, O6, O7;
1615
reg q0, q1, q2, q3, q4, q5, q6, q7;
1716

1817
initial
1918
begin
20-
{ q0, q1, q2, q3, q4, q5, q6, q7} <= 8'b00000000;
19+
{q0, q1, q2, q3, q4, q5, q6, q7} <= 8'b0;
2120
end
2221

23-
always @(OENB_N)
24-
if (OENB_N)
25-
begin
26-
assign O0 = 1'bz;
27-
assign O1 = 1'bz;
28-
assign O2 = 1'bz;
29-
assign O3 = 1'bz;
30-
assign O4 = 1'bz;
31-
assign O5 = 1'bz;
32-
assign O6 = 1'bz;
33-
assign O7 = 1'bz;
34-
end
35-
else
36-
begin
37-
assign O0 = q0;
38-
assign O1 = q1;
39-
assign O2 = q2;
40-
assign O3 = q3;
41-
assign O4 = q4;
42-
assign O5 = q5;
43-
assign O6 = q6;
44-
assign O7 = q7;
45-
46-
if (HOLD_N)
47-
begin
48-
{ q0, q1, q2, q3, q4, q5, q6, q7 } <=
49-
{ I0, I1, I2, I3, I4, I5, I6, I7 };
50-
end
51-
end
52-
53-
always @(I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7 or HOLD_N or OENB_N)
22+
always @(I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7 or HOLD_N)
5423
if (HOLD_N)
5524
begin
56-
{ q0, q1, q2, q3, q4, q5, q6, q7 } <=
57-
{ I0, I1, I2, I3, I4, I5, I6, I7 };
25+
{q0,q1,q2,q3,q4,q5,q6,q7} <= {I0,I1,I2,I3,I4,I5,I6,I7};
5826
end
5927

28+
assign O0 = OENB_N ? 1'bz : q0;
29+
assign O1 = OENB_N ? 1'bz : q1;
30+
assign O2 = OENB_N ? 1'bz : q2;
31+
assign O3 = OENB_N ? 1'bz : q3;
32+
assign O4 = OENB_N ? 1'bz : q4;
33+
assign O5 = OENB_N ? 1'bz : q5;
34+
assign O6 = OENB_N ? 1'bz : q6;
35+
assign O7 = OENB_N ? 1'bz : q7;
36+
6037
endmodule

‎hw/74374.v

+11-52
Original file line numberDiff line numberDiff line change
@@ -15,64 +15,23 @@ module part_74S374 (
1515
input I0, I1, I2, I3, I4, I5, I6, I7;
1616
input CLK, OENB_N;
1717
output O0, O1, O2, O3, O4, O5, O6, O7;
18-
reg O0, O1, O2, O3, O4, O5, O6, O7;
1918
reg q0, q1, q2, q3, q4, q5, q6, q7;
2019

21-
/*
22-
not #(`REG_DELAY)
23-
g1(l1,OENB_N);
24-
buf #(`REG_DELAY)
25-
g2(l2,CLK);
26-
dff_no_rs
27-
ff0(q0,lf0,I0,l2),
28-
ff1(q1,lf1,I1,l2),
29-
ff2(q2,lf2,I2,l2),
30-
ff3(q3,lf3,I3,l2),
31-
ff4(q4,lf4,I4,l2),
32-
ff5(q5,lf5,I5,l2),
33-
ff6(q6,lf6,I6,l2),
34-
ff7(q7,lf7,I7,l2);
35-
notif1 #(`REG_DELAY)
36-
g3(O0,lf0,l1),
37-
g4(O1,lf1,l1),
38-
g5(O2,lf2,l1),
39-
g6(O3,lf3,l1),
40-
g7(O4,lf4,l1),
41-
g8(O5,lf5,l1),
42-
g9(O6,lf6,l1),
43-
g10(O7,lf7,l1);
44-
*/
45-
4620
initial
4721
begin
48-
{ q0, q1, q2, q3, q4, q5, q6, q7 } <= 8'b00000000;
22+
{q0,q1,q2,q3,q4,q5,q6,q7} <= 8'b0;
4923
end
5024

51-
always @(OENB_N)
52-
if (OENB_N)
53-
begin
54-
assign O0 = 1'bz;
55-
assign O1 = 1'bz;
56-
assign O2 = 1'bz;
57-
assign O3 = 1'bz;
58-
assign O4 = 1'bz;
59-
assign O5 = 1'bz;
60-
assign O6 = 1'bz;
61-
assign O7 = 1'bz;
62-
end
63-
else
64-
begin
65-
assign O0 = q0;
66-
assign O1 = q1;
67-
assign O2 = q2;
68-
assign O3 = q3;
69-
assign O4 = q4;
70-
assign O5 = q5;
71-
assign O6 = q6;
72-
assign O7 = q7;
73-
end
74-
7525
always @(posedge CLK)
76-
{ q0, q1, q2, q3, q4, q5, q6, q7 } <= { I0, I1, I2, I3, I4, I5, I6, I7 };
26+
{q0,q1,q2,q3,q4,q5,q6,q7} <= {I0,I1,I2,I3,I4,I5,I6,I7};
27+
28+
assign O0 = OENB_N ? 1'bz : q0;
29+
assign O1 = OENB_N ? 1'bz : q1;
30+
assign O2 = OENB_N ? 1'bz : q2;
31+
assign O3 = OENB_N ? 1'bz : q3;
32+
assign O4 = OENB_N ? 1'bz : q4;
33+
assign O5 = OENB_N ? 1'bz : q5;
34+
assign O6 = OENB_N ? 1'bz : q6;
35+
assign O7 = OENB_N ? 1'bz : q7;
7736

7837
endmodule

‎hw/Makefile

-70
This file was deleted.

0 commit comments

Comments
 (0)