added README.md

Author: lisper

README.md

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+# cpus-cadr
+Verilog FPGA implementation of MIT CADR lisp machine
+
+This is my initial implementation of the CADR, along with the
+simulator.  It's a direct port of the original netlist and as such it
+suffers from a lot of issues.
+
+I rewrote most of it in the cpus-caddr project, which actually boots.
+
+