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Added prefetch extensions for MIPS RV64 P8700 and enable with xmipscbop option.
Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide" for more info on the extension at https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
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17 files changed

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17 files changed

+198
-7
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‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,7 @@
169169
// CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
170170
// CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
171171
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
172+
// CHECK-NEXT: xmipscbop 1.0 'XMIPSCBOP' (MIPS Software Prefetch)
172173
// CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
173174
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
174175
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)

‎llvm/docs/RISCVUsage.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -498,6 +498,9 @@ The current vendor extensions supported are:
498498
``experimental-Xqcisync``
499499
LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
500500

501+
``Xmipscbop``
502+
LLVM implements MIPS prefetch extension `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
503+
501504
``Xmipscmov``
502505
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
503506

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -732,6 +732,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
732732
bool isUImm6() const { return isUImm<6>(); }
733733
bool isUImm7() const { return isUImm<7>(); }
734734
bool isUImm8() const { return isUImm<8>(); }
735+
bool isUImm9() const { return isUImm<9>(); }
735736
bool isUImm10() const { return isUImm<10>(); }
736737
bool isUImm11() const { return isUImm<11>(); }
737738
bool isUImm16() const { return isUImm<16>(); }
@@ -1523,6 +1524,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15231524
return generateImmOutOfRangeError(
15241525
Operands, ErrorInfo, 0, (1 << 8) - 8,
15251526
"immediate must be a multiple of 8 bytes in the range");
1527+
case Match_InvalidUImm9:
1528+
return generateImmOutOfRangeError(
1529+
Operands, ErrorInfo, 0, (1 << 9) - 1,
1530+
"immediate must be a multiple of 9 bytes in the range");
15261531
case Match_InvalidBareSImm9Lsb0:
15271532
return generateImmOutOfRangeError(
15281533
Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -535,6 +535,19 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
535535
Inst.addOperand(MCOperand::createImm(Imm));
536536
return MCDisassembler::Success;
537537
}
538+
template <int Bits>
539+
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
540+
const MCDisassembler *Decoder) {
541+
if (Imm & ~((1LL << Bits) - 1))
542+
return MCDisassembler::Fail;
543+
544+
// Imm is a signed immediate, so sign extend it.
545+
if (Imm & (1 << (Bits - 1)))
546+
Imm |= ~((1LL << Bits) - 1);
547+
548+
Inst.addOperand(MCOperand::createImm(Imm));
549+
return MCDisassembler::Success;
550+
}
538551

539552
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
540553
uint64_t Address,
@@ -576,6 +589,9 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
576589
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
577590
uint64_t Address,
578591
const MCDisassembler *Decoder);
592+
template <int Bits>
593+
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
594+
const MCDisassembler *Decoder);
579595

580596
#include "RISCVGenDisassemblerTables.inc"
581597

@@ -790,6 +806,8 @@ static constexpr DecoderListEntry DecoderList32[]{
790806
{DecoderTableXmipscmov32,
791807
{RISCV::FeatureVendorXMIPSCMov},
792808
"MIPS mips.ccmov"},
809+
{DecoderTableXmipscbop32, {RISCV::FeatureVendorXMIPSCBOP},
810+
"MIPS mips.pref"},
793811
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
794812
// Standard Extensions
795813
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,7 @@ enum OperandType : unsigned {
316316
OPERAND_UIMM8_LSB000,
317317
OPERAND_UIMM8_GE32,
318318
OPERAND_UIMM9_LSB000,
319+
OPERAND_UIMM9,
319320
OPERAND_UIMM10,
320321
OPERAND_UIMM10_LSB00_NONZERO,
321322
OPERAND_UIMM11,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1411,6 +1411,13 @@ def HasVendorXMIPSLSP
14111411
: Predicate<"Subtarget->hasVendorXMIPSLSP()">,
14121412
AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
14131413
"'Xmipslsp' (load and store pair instructions)">;
1414+
def FeatureVendorXMIPSCBOP
1415+
: RISCVExtension<1, 0, "MIPS Software Prefetch">;
1416+
def HasVendorXMIPSCBOP
1417+
: Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
1418+
AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
1419+
"'Xmipscbop' (MIPS hardware prefetch)">;
1420+
def NotHasVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
14141421

14151422
// WCH / Nanjing Qinheng Microelectronics Extension(s)
14161423

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2925,6 +2925,54 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
29252925
return true;
29262926
}
29272927

2928+
/// Similar to SelectAddrRegImm, except that the offset restricted for
2929+
/// nine bits.
2930+
bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
2931+
SDValue &Offset) {
2932+
if (SelectAddrFrameIndex(Addr, Base, Offset))
2933+
return true;
2934+
2935+
SDLoc DL(Addr);
2936+
MVT VT = Addr.getSimpleValueType();
2937+
2938+
if (CurDAG->isBaseWithConstantOffset(Addr)) {
2939+
2940+
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
2941+
if (isUInt<9>(CVal)) {
2942+
Base = Addr.getOperand(0);
2943+
2944+
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
2945+
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
2946+
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
2947+
return true;
2948+
}
2949+
2950+
// Handle with 12 bit ofset immediates with ADDI.
2951+
else if (Addr.getOpcode() == ISD::ADD &&
2952+
isa<ConstantSDNode>(Addr.getOperand(1))) {
2953+
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
2954+
assert(!isUInt<9>(CVal) && "uimm9 not already handled?");
2955+
2956+
if (isUInt<12>(CVal)) {
2957+
Base = SDValue(CurDAG->getMachineNode(
2958+
RISCV::ADDI, DL, VT, Addr.getOperand(0),
2959+
CurDAG->getSignedTargetConstant(CVal, DL, VT)),
2960+
0);
2961+
Offset = CurDAG->getTargetConstant(0, DL, VT);
2962+
return true;
2963+
}
2964+
}
2965+
}
2966+
// Immediates more than 12 bits i.e LUI,ADDI,ADD
2967+
if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
2968+
/*IsPrefetch=*/true))
2969+
return true;
2970+
2971+
Base = Addr;
2972+
Offset = CurDAG->getTargetConstant(0, DL, VT);
2973+
return true;
2974+
}
2975+
29282976
/// Similar to SelectAddrRegImm, except that the least significant 5 bits of
29292977
/// Offset should be all zeros.
29302978
bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,12 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
4545
InlineAsm::ConstraintCode ConstraintID,
4646
std::vector<SDValue> &OutOps) override;
4747

48+
bool SelectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
49+
unsigned OffsetBits,
50+
unsigned ShiftAmount);
4851
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
4952
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
53+
bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
5054
bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
5155

5256
bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
682682
if (Subtarget.is64Bit())
683683
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
684684

685-
if (Subtarget.hasStdExtZicbop()) {
685+
if (Subtarget.hasStdExtZicbop() || Subtarget.hasVendorXMIPSCBOP()) {
686686
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
687687
}
688688

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2742,6 +2742,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
27422742
case RISCVOp::OPERAND_UIMM9_LSB000:
27432743
Ok = isShiftedUInt<6, 3>(Imm);
27442744
break;
2745+
case RISCVOp::OPERAND_UIMM9:
2746+
Ok = isUInt<9>(Imm);
2747+
break;
27452748
case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
27462749
Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
27472750
break;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,12 @@ def uimm7_lsb000 : RISCVOp,
2929
}];
3030
}
3131

32+
// A 9-bit unsigned offset
33+
def uimm9 : RISCVUImmOp<9>;
34+
35+
// Custom prefetch ADDR selector
36+
def AddrRegImm9 : ComplexPattern<iPTR, 2, "SelectAddrRegImm9">;
37+
3238
//===----------------------------------------------------------------------===//
3339
// MIPS custom instruction formats
3440
//===----------------------------------------------------------------------===//
@@ -103,9 +109,41 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
103109
let Inst{6-0} = OPC_CUSTOM_0.Value;
104110
}
105111

112+
// Prefetch format.
113+
let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in
114+
class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
115+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
116+
bits<9> imm9;
117+
bits<5> rs1;
118+
bits<5> hint;
119+
120+
let Inst{31 - 29} = 0b000;
121+
let Inst{28 - 20} = imm9{8 - 0};
122+
let Inst{19 - 15} = rs1;
123+
let Inst{14 - 12} = 0b000;
124+
let Inst{11 - 7} = hint;
125+
let Inst{6 - 0} = OPC_CUSTOM_0.Value;
126+
}
127+
106128
//===----------------------------------------------------------------------===//
107129
// MIPS extensions
108130
//===----------------------------------------------------------------------===//
131+
let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
132+
def MIPSPREFETCH : Mips_prefetch_ri<(outs),(ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
133+
"mips.perf", "$hint, ${imm9}(${rs1})">,
134+
Sched<[]>;
135+
}
136+
137+
let Predicates = [HasVendorXMIPSCBOP] in {
138+
// Prefetch Data Write.
139+
def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
140+
(i32 1), timm, (i32 1)),
141+
(MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
142+
// Prefetch Data Read.
143+
def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
144+
(i32 0), timm, (i32 1)),
145+
(MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
146+
}
109147

110148
let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
111149
DecoderNamespace = "Xmipscmov" in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ let Predicates = [HasStdExtZicboz] in {
5757
def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
5858
} // Predicates = [HasStdExtZicboz]
5959

60-
let Predicates = [HasStdExtZicbop] in {
60+
let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
6161
def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
6262
def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
6363
def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
@@ -69,7 +69,7 @@ def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
6969

7070
def AddrRegImmLsb00000 : ComplexPattern<iPTR, 2, "SelectAddrRegImmLsb00000">;
7171

72-
let Predicates = [HasStdExtZicbop] in {
72+
let Predicates = [HasStdExtZicbop, NotHasVendorXMIPSCBOP] in {
7373
def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
7474
timm, timm, (i32 0)),
7575
(PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>;

‎llvm/test/CodeGen/RISCV/features-info.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -184,6 +184,7 @@
184184
; CHECK-NEXT: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate).
185185
; CHECK-NEXT: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store).
186186
; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).
187+
; CHECK-NEXT: xmipscbop - 'XMIPSCBOP' (MIPS Software Prefetch).
187188
; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
188189
; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
189190
; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).

‎llvm/test/CodeGen/RISCV/xmips-cbop.ll

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
4+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
5+
; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
6+
7+
define dso_local void @prefetch_read(ptr noundef %a) {
8+
; RV32XMIPSPREFETCH-LABEL: prefetch_read:
9+
; RV32XMIPSPREFETCH: mips.perf 8, 511(a0)
10+
;
11+
; RV64XMIPSPREFETCH-LABEL: prefetch_read:
12+
; RV64XMIPSPREFETCH: mips.perf 8, 511(a0)
13+
entry:
14+
%a.addr = alloca ptr, align 8
15+
store ptr %a, ptr %a.addr, align 8
16+
%0 = load ptr, ptr %a.addr, align 8
17+
%arrayidx = getelementptr inbounds i8, ptr %0, i64 511
18+
call void @llvm.prefetch.p0(ptr %arrayidx, i32 0, i32 0, i32 1)
19+
ret void
20+
}
21+
22+
declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg, i32 immarg, i32 immarg)
23+
24+
define dso_local void @prefetch_write(ptr noundef %a) {
25+
entry:
26+
; RV32XMIPSPREFETCH-LABEL: prefetch_write:
27+
; RV32XMIPSPREFETCH: addi a1, a0, 512
28+
; RV32XMIPSPREFETCH-NEXT: mips.perf 9, 0(a1)
29+
;
30+
; RV64XMIPSPREFETCH-LABEL: prefetch_write:
31+
; RV64XMIPSPREFETCH: addi a1, a0, 512
32+
; RV64XMIPSPREFETCH-NEXT: mips.perf 9, 0(a1)
33+
%a.addr = alloca ptr, align 8
34+
store ptr %a, ptr %a.addr, align 8
35+
%0 = load ptr, ptr %a.addr, align 8
36+
%arrayidx = getelementptr inbounds i8, ptr %0, i64 512
37+
call void @llvm.prefetch.p0(ptr %arrayidx, i32 1, i32 0, i32 1)
38+
ret void
39+
}
40+

‎llvm/test/MC/RISCV/xmips-invalid.s

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,14 @@
11
# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
2-
# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s 2>&1 | FileCheck %s
2+
# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipsbcop < %s 2>&1 | FileCheck %s
3+
4+
mips.perf 8, 512(a0)
5+
# CHECK: error: invalid operand for instruction
6+
7+
mips.perf 8
8+
# CHECK: error: too few operands for instruction
9+
10+
mips.perf 8, 511(a0)
11+
# CHECK-FEATURE: error: instruction requires the following: 'Xmipscbop' (MIPS hardware prefetch)
312

413
mips.ccmov x0, x1, 0x10
514
# CHECK: error: invalid operand for instruction

‎llvm/test/MC/RISCV/xmips-valid.s

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,21 @@
1-
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov -M no-aliases -show-encoding \
1+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -show-encoding \
22
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
3-
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov < %s \
4-
# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov -M no-aliases -d - \
3+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop < %s \
4+
# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
55
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
66

7+
# CHECK-INST: mips.perf 8, 511(a0)
8+
# CHECK-ENC: encoding: [0x0b,0x04,0xf5,0x1f]
9+
mips.perf 8, 511(a0)
10+
11+
# CHECK-DIS: mips.perf 0x8, 0x1ff(a0)
12+
13+
# CHECK-INST: mips.perf 9, 0(a0)
14+
# CHECK-ENC: encoding: [0x8b,0x04,0x05,0x00]
15+
mips.perf 9, 0(a0)
16+
17+
# CHECK-DIS: mips.perf 0x9, 0x0(a0)
18+
719
# CHECK-INST: mips.ccmov s0, s1, s2, s3
820
# CHECK-ENC: encoding: [0x0b,0x34,0x99,0x9e]
921
mips.ccmov s0, s1, s2, s3

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1142,6 +1142,7 @@ R"(All available -march extensions for RISC-V
11421142
xcvsimd 1.0
11431143
xmipscmov 1.0
11441144
xmipslsp 1.0
1145+
xmipscbop 1.0
11451146
xsfcease 1.0
11461147
xsfmm128t 0.6
11471148
xsfmm16t 0.6

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