[PreCommit] Unaligned load/store realigned after offset

Author: Acthinks

llvm/test/CodeGen/RISCV/unaligned-load-store-with-aligned.ll

@@ -0,0 +1,157 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define void @store_b32_basealign2_offset1(ptr align 2 %p, i32 %v) {
+; CHECK-LABEL: store_b32_basealign2_offset1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srli a2, a1, 24
+; CHECK-NEXT:    srli a3, a1, 16
+; CHECK-NEXT:    srli a4, a1, 8
+; CHECK-NEXT:    sb a1, 1(a0)
+; CHECK-NEXT:    sb a4, 2(a0)
+; CHECK-NEXT:    sb a3, 3(a0)
+; CHECK-NEXT:    sb a2, 4(a0)
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 1
+  store i32 %v, ptr %len, align 1
+  ret void
+}
+
+define void @store_b32_basealign2_offset3(ptr align 2 %p, i32 %v) {
+; CHECK-LABEL: store_b32_basealign2_offset3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srli a2, a1, 24
+; CHECK-NEXT:    srli a3, a1, 16
+; CHECK-NEXT:    srli a4, a1, 8
+; CHECK-NEXT:    sb a1, 3(a0)
+; CHECK-NEXT:    sb a4, 4(a0)
+; CHECK-NEXT:    sb a3, 5(a0)
+; CHECK-NEXT:    sb a2, 6(a0)
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 3
+  store i32 %v, ptr %len, align 1
+  ret void
+}
+
+define void @store_b64_basealign4_offset1(ptr align 4 %p) {
+; CHECK-LABEL: store_b64_basealign4_offset1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sb zero, 5(a0)
+; CHECK-NEXT:    sb zero, 6(a0)
+; CHECK-NEXT:    sb zero, 7(a0)
+; CHECK-NEXT:    sb zero, 8(a0)
+; CHECK-NEXT:    sb zero, 1(a0)
+; CHECK-NEXT:    sb zero, 2(a0)
+; CHECK-NEXT:    sb zero, 3(a0)
+; CHECK-NEXT:    sb zero, 4(a0)
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 1
+  store i64 0, ptr %len, align 1
+  ret void
+}
+
+define void @store_b64_basealign4_offset2(ptr align 4 %p) {
+; CHECK-LABEL: store_b64_basealign4_offset2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sh zero, 2(a0)
+; CHECK-NEXT:    sh zero, 4(a0)
+; CHECK-NEXT:    sh zero, 6(a0)
+; CHECK-NEXT:    sh zero, 8(a0)
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 2
+  store i64 0, ptr %len, align 2
+  ret void
+}
+
+define i32 @load_b32_base_align2_offset1(ptr align 2 %p) {
+; CHECK-LABEL: load_b32_base_align2_offset1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lbu a1, 2(a0)
+; CHECK-NEXT:    lbu a2, 1(a0)
+; CHECK-NEXT:    lbu a3, 3(a0)
+; CHECK-NEXT:    lbu a0, 4(a0)
+; CHECK-NEXT:    slli a1, a1, 8
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    slli a3, a3, 16
+; CHECK-NEXT:    slli a0, a0, 24
+; CHECK-NEXT:    or a0, a0, a3
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 1
+  %v = load i32, ptr %len, align 1
+  ret i32 %v
+}
+
+define i32 @load_b32_base_align2_offset3(ptr align 2 %p) {
+; CHECK-LABEL: load_b32_base_align2_offset3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lbu a1, 4(a0)
+; CHECK-NEXT:    lbu a2, 3(a0)
+; CHECK-NEXT:    lbu a3, 5(a0)
+; CHECK-NEXT:    lbu a0, 6(a0)
+; CHECK-NEXT:    slli a1, a1, 8
+; CHECK-NEXT:    or a1, a1, a2
+; CHECK-NEXT:    slli a3, a3, 16
+; CHECK-NEXT:    slli a0, a0, 24
+; CHECK-NEXT:    or a0, a0, a3
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 3
+  %v = load i32, ptr %len, align 1
+  ret i32 %v
+}
+
+define i64 @load_b64_base_align2_offset1(ptr align 4 %p) {
+; CHECK-LABEL: load_b64_base_align2_offset1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lbu a1, 3(a0)
+; CHECK-NEXT:    lbu a2, 4(a0)
+; CHECK-NEXT:    lbu a3, 5(a0)
+; CHECK-NEXT:    lbu a4, 2(a0)
+; CHECK-NEXT:    slli a1, a1, 8
+; CHECK-NEXT:    slli a2, a2, 16
+; CHECK-NEXT:    slli a3, a3, 24
+; CHECK-NEXT:    or a1, a1, a4
+; CHECK-NEXT:    or a2, a3, a2
+; CHECK-NEXT:    lbu a3, 7(a0)
+; CHECK-NEXT:    lbu a4, 6(a0)
+; CHECK-NEXT:    lbu a5, 8(a0)
+; CHECK-NEXT:    lbu a0, 9(a0)
+; CHECK-NEXT:    slli a3, a3, 8
+; CHECK-NEXT:    or a3, a3, a4
+; CHECK-NEXT:    slli a5, a5, 16
+; CHECK-NEXT:    slli a0, a0, 24
+; CHECK-NEXT:    or a5, a0, a5
+; CHECK-NEXT:    or a0, a2, a1
+; CHECK-NEXT:    or a1, a5, a3
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 2
+  %v = load i64, ptr %len, align 1
+  ret i64 %v
+}
+
+define i64 @load_b64_base_align2_offset2(ptr align 4 %p) {
+; CHECK-LABEL: load_b64_base_align2_offset2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lhu a1, 4(a0)
+; CHECK-NEXT:    lhu a2, 2(a0)
+; CHECK-NEXT:    lhu a3, 8(a0)
+; CHECK-NEXT:    lhu a4, 6(a0)
+; CHECK-NEXT:    slli a0, a1, 16
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    slli a1, a3, 16
+; CHECK-NEXT:    or a1, a1, a4
+; CHECK-NEXT:    ret
+entry:
+  %len = getelementptr inbounds nuw i8, ptr %p, i32 2
+  %v = load i64, ptr %len, align 2
+  ret i64 %v
+}