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24 | 24 | #include "llvm/CodeGen/MachineJumpTableInfo.h"
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25 | 25 | #include "llvm/CodeGen/MachineModuleInfo.h"
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26 | 26 | #include "llvm/CodeGen/MachineRegisterInfo.h"
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| 27 | +#include "llvm/CodeGen/SDPatternMatch.h" |
27 | 28 | #include "llvm/CodeGen/SelectionDAG.h"
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28 | 29 | #include "llvm/CodeGen/SelectionDAGNodes.h"
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29 | 30 | #include "llvm/IR/DiagnosticInfo.h"
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|
35 | 36 | #include "llvm/Support/ErrorHandling.h"
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36 | 37 | #include "llvm/Support/KnownBits.h"
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37 | 38 | #include "llvm/Support/MathExtras.h"
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| 39 | +#include "llvm/Support/raw_ostream.h" |
38 | 40 | #include "llvm/Target/TargetOptions.h"
|
39 | 41 | using namespace llvm;
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40 |
| - |
| 42 | +using namespace llvm::SDPatternMatch; |
41 | 43 | #define DEBUG_TYPE "wasm-lower"
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42 | 44 |
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43 | 45 | WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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@@ -3248,29 +3250,24 @@ static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
|
3248 | 3250 | if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
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3249 | 3251 | return SDValue();
|
3250 | 3252 |
|
3251 |
| - SDValue SetCC = N->getOperand(1); |
3252 |
| - if (SetCC.getOpcode() != ISD::SETCC) |
| 3253 | + SDValue LHS; |
| 3254 | + if (!sd_match(N->getOperand(1), m_c_SetCC(m_Value(LHS), m_Zero(), |
| 3255 | + m_SpecificCondCode(ISD::SETEQ)))) |
3253 | 3256 | return SDValue();
|
3254 | 3257 |
|
3255 |
| - SDValue LHS = SetCC->getOperand(0); |
3256 |
| - SDValue RHS = SetCC->getOperand(1); |
3257 |
| - ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); |
3258 | 3258 | EVT LT = LHS.getValueType();
|
3259 | 3259 | unsigned NumElts = LT.getVectorNumElements();
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3260 |
| - if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) |
| 3260 | + if (LT.getScalarSizeInBits() > 128 / NumElts) |
3261 | 3261 | return SDValue();
|
3262 | 3262 |
|
3263 | 3263 | EVT Width = MVT::getIntegerVT(128 / NumElts);
|
3264 | 3264 |
|
3265 |
| - if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ) |
3266 |
| - return SDValue(); |
3267 |
| - |
3268 | 3265 | SDValue Ret = DAG.getZExtOrTrunc(
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3269 | 3266 | DAG.getNode(
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3270 | 3267 | ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
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3271 |
| - {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32), |
3272 |
| - DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}), |
| 3268 | + {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32), LHS}), |
3273 | 3269 | DL, MVT::i1);
|
| 3270 | + |
3274 | 3271 | Ret = DAG.getNOT(DL, Ret, MVT::i1);
|
3275 | 3272 | return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
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3276 | 3273 | }
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@@ -3437,7 +3434,7 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
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3437 | 3434 | case ISD::TRUNCATE:
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3438 | 3435 | return performTruncateCombine(N, DCI);
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3439 | 3436 | case ISD::INTRINSIC_WO_CHAIN: {
|
3440 |
| - if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG)) |
| 3437 | + if (SDValue AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG)) |
3441 | 3438 | return AnyTrueCombine;
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3442 | 3439 | return performLowerPartialReduction(N, DCI.DAG);
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3443 | 3440 | }
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