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RKSimonRKSimon
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Remove insert_subvector(freeze(undef),sub,idx) -> insert_subvector(undef,sub,idx) hack
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2 files changed

+18
-3
lines changed

2 files changed

+18
-3
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11336,9 +11336,6 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
1133611336

1133711337
if (OrigIdx == 0 && Vec.isUndef())
1133811338
return Op;
11339-
if (OrigIdx == 0 && Vec.getOpcode() == ISD::FREEZE &&
11340-
Vec.getOperand(0).isUndef())
11341-
return DAG.getInsertSubvector(DL, DAG.getUNDEF(VecVT), SubVec, OrigIdx);
1134211339

1134311340
// We don't have the ability to slide mask vectors up indexed by their i1
1134411341
// elements; the smallest we can do is i8. Often we are able to bitcast to

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3927,6 +3927,7 @@ define void @trunc_v8f16(ptr %x) {
39273927
; ZVFH-NEXT: vle16.v v8, (a0)
39283928
; ZVFH-NEXT: lui a1, %hi(.LCPI171_0)
39293929
; ZVFH-NEXT: flh fa5, %lo(.LCPI171_0)(a1)
3930+
; ZVFH-NEXT: vmv.v.v v8, v8
39303931
; ZVFH-NEXT: vfabs.v v9, v8
39313932
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
39323933
; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -4007,6 +4008,7 @@ define void @trunc_v4f32(ptr %x) {
40074008
; CHECK-NEXT: vle32.v v8, (a0)
40084009
; CHECK-NEXT: lui a1, 307200
40094010
; CHECK-NEXT: fmv.w.x fa5, a1
4011+
; CHECK-NEXT: vmv.v.v v8, v8
40104012
; CHECK-NEXT: vfabs.v v9, v8
40114013
; CHECK-NEXT: vmflt.vf v0, v9, fa5
40124014
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -4028,6 +4030,7 @@ define void @trunc_v2f64(ptr %x) {
40284030
; CHECK-NEXT: vle64.v v8, (a0)
40294031
; CHECK-NEXT: lui a1, %hi(.LCPI174_0)
40304032
; CHECK-NEXT: fld fa5, %lo(.LCPI174_0)(a1)
4033+
; CHECK-NEXT: vmv.v.v v8, v8
40314034
; CHECK-NEXT: vfabs.v v9, v8
40324035
; CHECK-NEXT: vmflt.vf v0, v9, fa5
40334036
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -4103,6 +4106,7 @@ define void @ceil_v8f16(ptr %x) {
41034106
; ZVFH-NEXT: vle16.v v8, (a0)
41044107
; ZVFH-NEXT: lui a1, %hi(.LCPI177_0)
41054108
; ZVFH-NEXT: flh fa5, %lo(.LCPI177_0)(a1)
4109+
; ZVFH-NEXT: vmv.v.v v8, v8
41064110
; ZVFH-NEXT: vfabs.v v9, v8
41074111
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
41084112
; ZVFH-NEXT: fsrmi a1, 3
@@ -4191,6 +4195,7 @@ define void @ceil_v4f32(ptr %x) {
41914195
; CHECK-NEXT: vle32.v v8, (a0)
41924196
; CHECK-NEXT: lui a1, 307200
41934197
; CHECK-NEXT: fmv.w.x fa5, a1
4198+
; CHECK-NEXT: vmv.v.v v8, v8
41944199
; CHECK-NEXT: vfabs.v v9, v8
41954200
; CHECK-NEXT: vmflt.vf v0, v9, fa5
41964201
; CHECK-NEXT: fsrmi a1, 3
@@ -4214,6 +4219,7 @@ define void @ceil_v2f64(ptr %x) {
42144219
; CHECK-NEXT: vle64.v v8, (a0)
42154220
; CHECK-NEXT: lui a1, %hi(.LCPI180_0)
42164221
; CHECK-NEXT: fld fa5, %lo(.LCPI180_0)(a1)
4222+
; CHECK-NEXT: vmv.v.v v8, v8
42174223
; CHECK-NEXT: vfabs.v v9, v8
42184224
; CHECK-NEXT: vmflt.vf v0, v9, fa5
42194225
; CHECK-NEXT: fsrmi a1, 3
@@ -4291,6 +4297,7 @@ define void @floor_v8f16(ptr %x) {
42914297
; ZVFH-NEXT: vle16.v v8, (a0)
42924298
; ZVFH-NEXT: lui a1, %hi(.LCPI183_0)
42934299
; ZVFH-NEXT: flh fa5, %lo(.LCPI183_0)(a1)
4300+
; ZVFH-NEXT: vmv.v.v v8, v8
42944301
; ZVFH-NEXT: vfabs.v v9, v8
42954302
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
42964303
; ZVFH-NEXT: fsrmi a1, 2
@@ -4379,6 +4386,7 @@ define void @floor_v4f32(ptr %x) {
43794386
; CHECK-NEXT: vle32.v v8, (a0)
43804387
; CHECK-NEXT: lui a1, 307200
43814388
; CHECK-NEXT: fmv.w.x fa5, a1
4389+
; CHECK-NEXT: vmv.v.v v8, v8
43824390
; CHECK-NEXT: vfabs.v v9, v8
43834391
; CHECK-NEXT: vmflt.vf v0, v9, fa5
43844392
; CHECK-NEXT: fsrmi a1, 2
@@ -4402,6 +4410,7 @@ define void @floor_v2f64(ptr %x) {
44024410
; CHECK-NEXT: vle64.v v8, (a0)
44034411
; CHECK-NEXT: lui a1, %hi(.LCPI186_0)
44044412
; CHECK-NEXT: fld fa5, %lo(.LCPI186_0)(a1)
4413+
; CHECK-NEXT: vmv.v.v v8, v8
44054414
; CHECK-NEXT: vfabs.v v9, v8
44064415
; CHECK-NEXT: vmflt.vf v0, v9, fa5
44074416
; CHECK-NEXT: fsrmi a1, 2
@@ -4479,6 +4488,7 @@ define void @round_v8f16(ptr %x) {
44794488
; ZVFH-NEXT: vle16.v v8, (a0)
44804489
; ZVFH-NEXT: lui a1, %hi(.LCPI189_0)
44814490
; ZVFH-NEXT: flh fa5, %lo(.LCPI189_0)(a1)
4491+
; ZVFH-NEXT: vmv.v.v v8, v8
44824492
; ZVFH-NEXT: vfabs.v v9, v8
44834493
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
44844494
; ZVFH-NEXT: fsrmi a1, 4
@@ -4567,6 +4577,7 @@ define void @round_v4f32(ptr %x) {
45674577
; CHECK-NEXT: vle32.v v8, (a0)
45684578
; CHECK-NEXT: lui a1, 307200
45694579
; CHECK-NEXT: fmv.w.x fa5, a1
4580+
; CHECK-NEXT: vmv.v.v v8, v8
45704581
; CHECK-NEXT: vfabs.v v9, v8
45714582
; CHECK-NEXT: vmflt.vf v0, v9, fa5
45724583
; CHECK-NEXT: fsrmi a1, 4
@@ -4590,6 +4601,7 @@ define void @round_v2f64(ptr %x) {
45904601
; CHECK-NEXT: vle64.v v8, (a0)
45914602
; CHECK-NEXT: lui a1, %hi(.LCPI192_0)
45924603
; CHECK-NEXT: fld fa5, %lo(.LCPI192_0)(a1)
4604+
; CHECK-NEXT: vmv.v.v v8, v8
45934605
; CHECK-NEXT: vfabs.v v9, v8
45944606
; CHECK-NEXT: vmflt.vf v0, v9, fa5
45954607
; CHECK-NEXT: fsrmi a1, 4
@@ -4638,6 +4650,7 @@ define void @rint_v8f16(ptr %x) {
46384650
; ZVFH-NEXT: vle16.v v8, (a0)
46394651
; ZVFH-NEXT: lui a1, %hi(.LCPI194_0)
46404652
; ZVFH-NEXT: flh fa5, %lo(.LCPI194_0)(a1)
4653+
; ZVFH-NEXT: vmv.v.v v8, v8
46414654
; ZVFH-NEXT: vfabs.v v9, v8
46424655
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
46434656
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
@@ -4678,6 +4691,7 @@ define void @rint_v4f32(ptr %x) {
46784691
; CHECK-NEXT: vle32.v v8, (a0)
46794692
; CHECK-NEXT: lui a1, 307200
46804693
; CHECK-NEXT: fmv.w.x fa5, a1
4694+
; CHECK-NEXT: vmv.v.v v8, v8
46814695
; CHECK-NEXT: vfabs.v v9, v8
46824696
; CHECK-NEXT: vmflt.vf v0, v9, fa5
46834697
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
@@ -4699,6 +4713,7 @@ define void @rint_v2f64(ptr %x) {
46994713
; CHECK-NEXT: vle64.v v8, (a0)
47004714
; CHECK-NEXT: lui a1, %hi(.LCPI196_0)
47014715
; CHECK-NEXT: fld fa5, %lo(.LCPI196_0)(a1)
4716+
; CHECK-NEXT: vmv.v.v v8, v8
47024717
; CHECK-NEXT: vfabs.v v9, v8
47034718
; CHECK-NEXT: vmflt.vf v0, v9, fa5
47044719
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
@@ -4747,6 +4762,7 @@ define void @nearbyint_v8f16(ptr %x) {
47474762
; ZVFH-NEXT: vle16.v v8, (a0)
47484763
; ZVFH-NEXT: lui a1, %hi(.LCPI198_0)
47494764
; ZVFH-NEXT: flh fa5, %lo(.LCPI198_0)(a1)
4765+
; ZVFH-NEXT: vmv.v.v v8, v8
47504766
; ZVFH-NEXT: vfabs.v v9, v8
47514767
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
47524768
; ZVFH-NEXT: frflags a1
@@ -4791,6 +4807,7 @@ define void @nearbyint_v4f32(ptr %x) {
47914807
; CHECK-NEXT: vle32.v v8, (a0)
47924808
; CHECK-NEXT: lui a1, 307200
47934809
; CHECK-NEXT: fmv.w.x fa5, a1
4810+
; CHECK-NEXT: vmv.v.v v8, v8
47944811
; CHECK-NEXT: vfabs.v v9, v8
47954812
; CHECK-NEXT: vmflt.vf v0, v9, fa5
47964813
; CHECK-NEXT: frflags a1
@@ -4814,6 +4831,7 @@ define void @nearbyint_v2f64(ptr %x) {
48144831
; CHECK-NEXT: vle64.v v8, (a0)
48154832
; CHECK-NEXT: lui a1, %hi(.LCPI200_0)
48164833
; CHECK-NEXT: fld fa5, %lo(.LCPI200_0)(a1)
4834+
; CHECK-NEXT: vmv.v.v v8, v8
48174835
; CHECK-NEXT: vfabs.v v9, v8
48184836
; CHECK-NEXT: vmflt.vf v0, v9, fa5
48194837
; CHECK-NEXT: frflags a1

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