Use SDPatternMatching and remove truncate...

Use SDPatternMatching and remove truncation. Also added 4xi64 case to
reflect that.

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -24,6 +24,7 @@
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SDPatternMatch.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/IR/DiagnosticInfo.h"
@@ -37,7 +38,6 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
-
 #define DEBUG_TYPE "wasm-lower"
 
 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
@@ -3243,34 +3243,29 @@ static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
   // any_true (setcc <X>, 0, eq)
   // => not (all_true X)
 
+  using namespace llvm::SDPatternMatch;
+
   SDLoc DL(N);
   assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
   if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
     return SDValue();
 
-  SDValue SetCC = N->getOperand(1);
-  if (SetCC.getOpcode() != ISD::SETCC)
+  SDValue LHS;
+  if (!sd_match(N->getOperand(1), m_c_SetCC(m_Value(LHS), m_Zero(),
+                                            m_SpecificCondCode(ISD::SETEQ))))
     return SDValue();
 
-  SDValue LHS = SetCC->getOperand(0);
-  SDValue RHS = SetCC->getOperand(1);
-  ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
   EVT LT = LHS.getValueType();
   unsigned NumElts = LT.getVectorNumElements();
-  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
-    return SDValue();
-
-  EVT Width = MVT::getIntegerVT(128 / NumElts);
-
-  if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ)
+  if (LT.getScalarSizeInBits() > 128 / NumElts)
     return SDValue();
 
   SDValue Ret = DAG.getZExtOrTrunc(
       DAG.getNode(
           ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
-          {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
-           DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}),
+          {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32), LHS}),
       DL, MVT::i1);
+
   Ret = DAG.getNOT(DL, Ret, MVT::i1);
   return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
 }
@@ -3437,7 +3432,7 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::TRUNCATE:
     return performTruncateCombine(N, DCI);
   case ISD::INTRINSIC_WO_CHAIN: {
-    if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
+    if (SDValue AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
       return AnyTrueCombine;
     return performLowerPartialReduction(N, DCI.DAG);
   }

llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll

@@ -57,3 +57,26 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
   %conv3 = zext i1 %3 to i32
   ret i32 %conv3
 }
+
+
+define i32 @all_true_4_i64(<4 x i64> %v) {
+; CHECK-LABEL: all_true_4_i64:
+; CHECK:         .functype all_true_4_i64 (v128, v128) -> (i32)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.const $push9=, 0, 0
+; CHECK-NEXT:    local.tee $push8=, $2=, $pop9
+; CHECK-NEXT:    i64x2.eq $push1=, $0, $pop8
+; CHECK-NEXT:    i64x2.eq $push0=, $1, $2
+; CHECK-NEXT:    i8x16.shuffle $push2=, $pop1, $pop0, 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27
+; CHECK-NEXT:    v128.any_true $push3=, $pop2
+; CHECK-NEXT:    i32.const $push4=, -1
+; CHECK-NEXT:    i32.xor $push5=, $pop3, $pop4
+; CHECK-NEXT:    i32.const $push6=, 1
+; CHECK-NEXT:    i32.and $push7=, $pop5, $pop6
+; CHECK-NEXT:    return $pop7
+  %1 = icmp eq <4 x i64> %v, zeroinitializer
+  %2 = bitcast <4 x i1> %1 to i4
+  %3 = icmp eq i4 %2, 0
+  %conv3 = zext i1 %3 to i32
+  ret i32 %conv3
+}