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Issues list

TL-UL: bus watchdog question Further information is requested
#7 opened Dec 1, 2023 by marnovandermaas
1
Check screen UART functionality todo
#30 opened Mar 22, 2024 by HU90m
@HU90m
I2C documentation discrepancy todo
#146 opened Jul 25, 2024 by djlowther
2
SECDED errors from the SRAM can not be signalled for ReadModifyWrite operations.
#179 opened Sep 3, 2024 by ColinDBates
2
Wavedrom rendering broken in sonata documentation
#199 opened Sep 20, 2024 by GregAC
@HU90m
CHERI sanity test has an illegal instruction
#206 opened Sep 25, 2024 by marnovandermaas
[CI] Enable cherirtos testsuite on the FPGA Job
#250 opened Oct 16, 2024 by engdoreis
Ethernet smoke test
#253 opened Oct 16, 2024 by marnovandermaas
Rename xbar_main.json to xbar_main.json.tpl. Then rename xbar_main_generated.hjson to xbar_main.json.
#348 opened Nov 12, 2024 by marnovandermaas
IP to suspend/reset on both FPGA and sim
#380 opened Jan 17, 2025 by marnovandermaas
Hardware acceleration for CHERIoT revocation sweeps enhancement New feature or request
#386 opened Feb 21, 2025 by marnovandermaas
1
Unique board ID
#392 opened Mar 25, 2025 by marnovandermaas
HyperRAM burst support
#393 opened Mar 26, 2025 by marnovandermaas
GPIO change notification IRQ(s)?
#394 opened Mar 26, 2025 by nwf
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