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kakkala
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2 parents 0f9d256 + 4759b53 commit 3de12ef

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‎board/mathworks/zynq/boards/adrv9361/boot/ccfmc_lvds.bit

12.7 MB
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‎board/mathworks/zynq/boards/adrv9361/boot/ccfmc_lvds_handoff/ps7_init_gpl.c

+12,936
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‎board/mathworks/zynq/boards/adrv9361/boot/ccfmc_lvds_handoff/ps7_init_gpl.h

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/******************************************************************************
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*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this
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* software and associated documentation files (the "Software"), to deal in the Software
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* without restriction, including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
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* persons to whom the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or
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* otherwise to promote the sale, use or other dealings in this Software without prior written
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* authorization from Xilinx.
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*
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*******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file ps7_init.h
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*
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* This file can be included in FSBL code
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* to get prototype of ps7_init() function
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* and error codes
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*
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*****************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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//typedef unsigned int u32;
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/** do we need to make this name more unique ? **/
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//extern u32 ps7_init_data[];
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extern unsigned long * ps7_ddr_init_data;
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extern unsigned long * ps7_mio_init_data;
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extern unsigned long * ps7_pll_init_data;
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extern unsigned long * ps7_clock_init_data;
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extern unsigned long * ps7_peripherals_init_data;
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#define OPCODE_EXIT 0U
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#define OPCODE_CLEAR 1U
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#define OPCODE_WRITE 2U
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#define OPCODE_MASKWRITE 3U
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#define OPCODE_MASKPOLL 4U
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#define OPCODE_MASKDELAY 5U
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#define NEW_PS7_ERR_CODE 1
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/* Encode number of arguments in last nibble */
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#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
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#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
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#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
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#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
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#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
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#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
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/* Returns codes of PS7_Init */
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#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
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#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
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#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
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#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
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#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
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#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
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/* Silicon Versions */
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#define PCW_SILICON_VERSION_1 0
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#define PCW_SILICON_VERSION_2 1
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#define PCW_SILICON_VERSION_3 2
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/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
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#define PS7_POST_CONFIG
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/* Freq of all peripherals */
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#define APU_FREQ 666666687
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#define DDR_FREQ 533333374
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#define DCI_FREQ 10158730
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#define QSPI_FREQ 200000000
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#define SMC_FREQ 10000000
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#define ENET0_FREQ 125000000
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#define ENET1_FREQ 125000000
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#define USB0_FREQ 60000000
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#define USB1_FREQ 60000000
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#define SDIO_FREQ 50000000
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#define UART_FREQ 100000000
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#define SPI_FREQ 166666672
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#define I2C_FREQ 111111115
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#define WDT_FREQ 111111115
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#define TTC_FREQ 50000000
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#define CAN_FREQ 10000000
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#define PCAP_FREQ 200000000
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#define TPIU_FREQ 200000000
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#define FPGA0_FREQ 100000000
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#define FPGA1_FREQ 200000000
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#define FPGA2_FREQ 200000000
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#define FPGA3_FREQ 10000000
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/* For delay calculation using global registers*/
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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int ps7_config( unsigned long*);
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int ps7_init();
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int ps7_post_config();
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int ps7_debug();
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char* getPS7MessageInfo(unsigned key);
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void perf_start_clock(void);
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void perf_disable_clock(void);
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void perf_reset_clock(void);
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void perf_reset_and_start_timer();
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int get_number_of_cycles_for_delay(unsigned int delay);
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#ifdef __cplusplus
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}
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#endif
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‎board/mathworks/zynq/boards/adrv9361/catalog.xml

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<board name="adrv9361" platform="zynq">
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<default>
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<app name="default">
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</app>
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<dtsi dir="../../dts"/>
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<fsbl dir="ccfmc_lvds_handoff"/>
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</default>
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<image name="zynqsdr">
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<app name="fmc_axis">
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<dts file="fmc_axis.dts"/>
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<bit file="ccfmc_lvds.bit"/>
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</app>
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<app name="fmc">
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<dts file="fmc.dts"/>
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</app>
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<app name="fmc_axis64">
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<dts file="fmc_axis64.dts"/>
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</app>
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<app name="fmc_axis_XIL_DMA">
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<dts file="fmc_axis_XIL_DMA.dts"/>
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</app>
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<app name="fmc_axis64_XIL_DMA">
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<dts file="fmc_axis64_XIL_DMA.dts"/>
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</app>
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</image>
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</board>

‎board/mathworks/zynq/boards/adrv9361/defconfig

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###########################################
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# ZC706 Options
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###########################################
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BR2_TARGET_UBOOT_BOARD_DEFCONFIG="zynq_picozed_sdr2"
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BR2_PACKAGE_XILINX_BOOTLOADER_UBOOT_TARGET_DIR="board/xilinx/zynq/zynq-picozed-sdr2"

‎board/mathworks/zynq/boards/adrv9361/dts/AXIS_DataSize.h

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#ifndef __MW_AXI_DATASIZE_DMA__
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#define __MW_AXI_DATASIZE_DMA__
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#define MW_DATAWIDTH_SELECT 64
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#endif /* __MW_AXI_DATASIZE_DMA__ */

‎board/mathworks/zynq/boards/adrv9361/dts/adrv9361-fmc-cleanup-adv7511.dtsi

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/delete-node/ &adv7511;
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/delete-node/ &axi_vdma_0;
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/delete-node/ &hdmi_clock;
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/delete-node/ &axi_spdif_tx_0;
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/ {
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/delete-node/ adv7511_hdmi_snd;
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};
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&fpga_axi {
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/delete-node/ axi_hdmi@70e00000;
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};
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‎board/mathworks/zynq/boards/adrv9361/dts/fmc.dts

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#include "zynq-adrv9361-z7035-fmc.dts"
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#include "zynq-mw-ad9361.dtsi"
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#include "adrv9361-fmc-cleanup-adv7511.dtsi"
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‎board/mathworks/zynq/boards/adrv9361/dts/fmc_axis.dts

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#include "fmc.dts"
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#include "zynq-mw-ad9361-axis.dtsi"

‎board/mathworks/zynq/boards/adrv9361/dts/fmc_axis64.dts

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#include "AXIS_DataSize.h"
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#include "fmc.dts"
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#include "zynq-mw-ad9361-axis.dtsi"

‎board/mathworks/zynq/boards/adrv9361/dts/fmc_axis64_XIL_DMA.dts

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#include "AXIS_DataSize.h"
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#include "fmc.dts"
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#include "zynq-mw-ad9361-axis-xil.dtsi"

‎board/mathworks/zynq/boards/adrv9361/dts/fmc_axis_XIL_DMA.dts

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#include "fmc.dts"
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#include "zynq-mw-ad9361-axis-xil.dtsi"

‎board/mathworks/zynq/boards/picozed/boot/axilite_7z030.bit

5.7 MB
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‎board/mathworks/zynq/boards/picozed/boot/fsbl.elf

424 KB
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