Fix RVC compression constrants

- c.jr and c.jalr were missing imm_eq_zero
- c.srli, c.srai, c.andi were missing imm_5
- c.li and c.addiw need simm_6 instead of imm_6
- c.beqz and c.bnez need simm_9 instead of imm_9
- c.addi16sp needs simm_10 instead of imm_10
- c.addi needs nz_imm
- c.j needs simm_12 instead of imm_12
- Fix unsigned compression constraint clauses

Author: michaeljclark

compression

@@ -14,31 +14,31 @@ c.fsd        fsd    imm_8  imm_x8        rs1_b3 rs2_b3
 c.sw         sw     imm_7  imm_x4        rs1_b3 rs2_b3
 c.fsw        fsw    imm_7  imm_x4        rs1_b3 rs2_b3
 c.nop        addi                        rd_eq_x0 rs1_eq_x0 rs2_eq_x0
-c.addi       addi   simm_6               rd_ne_x0 rd_eq_rs1
+c.addi       addi   simm_6 imm_nz        rd_ne_x0 rd_eq_rs1
 c.jal        jal    imm_12 imm_x2        rd_eq_ra
-c.li         addi   imm_6                rd_ne_x0 rs1_eq_x0
+c.li         addi   simm_6               rd_ne_x0 rs1_eq_x0
 c.lui        lui    imm_18 imm_nz        rd_ne_x0_x2
-c.addi16sp   addi   imm_10 imm_x4 imm_nz rd_eq_sp rs1_eq_sp
-c.srli       srli   imm_nz               rd_eq_rs1 rd_b3 rs1_b3
-c.srai       srai   imm_nz               rd_eq_rs1 rd_b3 rs1_b3
-c.andi       andi   imm_nz               rd_eq_rs1 rd_b3 rs1_b3
+c.addi16sp   addi   simm_10 imm_x4 imm_nz rd_eq_sp rs1_eq_sp
+c.srli       srli   imm_5 imm_nz         rd_eq_rs1 rd_b3 rs1_b3
+c.srai       srai   imm_5 imm_nz         rd_eq_rs1 rd_b3 rs1_b3
+c.andi       andi   imm_5 imm_nz         rd_eq_rs1 rd_b3 rs1_b3
 c.sub        sub                         rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
 c.xor        xor                         rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
 c.or         or                          rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
 c.and        and                         rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
 c.subw       subw                        rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
 c.addw       addw                        rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
-c.j          jal    imm_12 imm_x2        rd_eq_x0
-c.beqz       beq    imm_9  imm_x2        rs1_b3 rs2_eq_x0
-c.bnez       bne    imm_9  imm_x2        rs1_b3 rs2_eq_x0
-c.slli       slli   imm_nz               rd_ne_x0 rd_eq_rs1
+c.j          jal    simm_12 imm_x2       rd_eq_x0
+c.beqz       beq    simm_9 imm_x2        rs1_b3 rs2_eq_x0
+c.bnez       bne    simm_9 imm_x2        rs1_b3 rs2_eq_x0
+c.slli       slli   imm_5 imm_nz         rd_ne_x0 rd_eq_rs1
 c.fldsp      fld    imm_9  imm_x8        rs1_eq_sp
 c.lwsp       lw     imm_8  imm_x4        rd_ne_x0 rs1_eq_sp
 c.flwsp      flw    imm_8  imm_x4        rs1_eq_sp
-c.jr         jalr                        rd_eq_x0 rs1_ne_x0
+c.jr         jalr   imm_eq_zero          rd_eq_x0 rs1_ne_x0
 c.mv         addi   imm_eq_zero          rd_ne_x0
 c.ebreak     ebreak
-c.jalr       jalr                        rd_eq_ra rs1_ne_x0
+c.jalr       jalr   imm_eq_zero          rd_eq_ra rs1_ne_x0
 c.add        add                         rd_eq_rs1 rd_ne_x0 rs2_ne_x0
 c.fsdsp      fsd    imm_9  imm_x8        rs1_eq_sp
 c.swsp       sw     imm_8  imm_x4        rs1_eq_sp
@@ -47,7 +47,7 @@ c.ld         ld     imm_8  imm_x8        rd_b3 rs1_b3
 c.sd         sd     imm_8  imm_x8        rs1_b3 rs2_b3
 c.lq         lq     imm_9  imm_x16
 c.sq         sq     imm_9  imm_x16
-c.addiw      addiw  imm_6                rd_ne_x0 rd_eq_rs1
+c.addiw      addiw  simm_6               rd_ne_x0 rd_eq_rs1
 c.ldsp       ld     imm_9  imm_x8        rd_ne_x0 rs1_eq_sp
 c.sdsp       sd     imm_9  imm_x8        rs1_eq_sp
 c.lqsp       lq     imm_10 imm_x16       rs1_eq_sp

constraints

@@ -2,13 +2,17 @@
 # <constraint name> <constraint expression> <hint>
 
 simm_6        "imm >= -32 && imm < 32"
-imm_6         "imm <= 0b111111"
-imm_7         "imm <= 0b1111111"
-imm_8         "imm <= 0b11111111"
-imm_9         "imm <= 0b111111111"
-imm_10        "imm <= 0b1111111111"
-imm_12        "imm <= 0b111111111111"
-imm_18        "imm <= 0b111111111111111111"
+simm_9        "imm >= -256 && imm < 256"
+simm_10       "imm >= -512 && imm < 512"
+simm_12       "imm >= -2048 && imm < 2048"
+imm_5         "imm >= 0 && imm <= 0b11111"
+imm_6         "imm >= 0 && imm <= 0b111111"
+imm_7         "imm >= 0 && imm <= 0b1111111"
+imm_8         "imm >= 0 && imm <= 0b11111111"
+imm_9         "imm >= 0 && imm <= 0b111111111"
+imm_10        "imm >= 0 && imm <= 0b1111111111"
+imm_12        "imm >= 0 && imm <= 0b111111111111"
+imm_18        "imm >= 0 && imm <= 0b111111111111111111"
 imm_nz        "imm != 0"
 imm_x2        "(imm & 0b1) == 0"
 imm_x4        "(imm & 0b11) == 0"