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‎LICENSE

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Copyright (c) 2013, The Regents of the University of California (Regents).
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All Rights Reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Regents nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
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SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
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OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
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BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
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HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
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MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

‎README.md

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# RISC-V Metadata
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This directory contains metadata for the RISC-V Instruction Set
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|File|Description|
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|:---|:----------|
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|`codecs` |Instruction encodings|
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|`compression` |Compressed instruction|
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|`constraints` |Constraint definitions|
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|`csrs` |Control and status registers|
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|`csr-fields` |Control and status register fields|
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|`enums` |Enumerated types|
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|`extensions` |Instruction set extensions|
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|`formats` |Disassembly formats|
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|`opcodes` |Opcode encoding information|
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|`opcode-classes` |Instruction classes|
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|`opcode-descriptions` |Instruction descriptions|
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|`opcode-fullnames` |Instruction full names|
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|`opcode-majors` |Major opcodes|
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|`opcode-pseudocode-c` |Instruction pseudo code (C)|
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|`opcode-pseudocode-alt`|Instruction pseudo code (Alternative)|
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|`operands` |Operand bit encodings|
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|`pseudos` |Pseudo instructions|
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|`registers` |Registers ABI definitions|
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|`types` |Instruction types|

‎codecs

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# format of a line in this file:
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# <codec> <format> [<arg> ... ]
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#
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# <codec> denotes a distinct instruction type, subtype and format
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#
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# [<arg> ... ] lists operands declared in opcodes as a cross-check
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#
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# Codecs with a · sign denote a subtype of the higher level type
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# Codecs with a + sign denote a format variant for the same type
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# i.e. <type(·subtype+format)?> where codec is the distinct codec
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none none
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u rd,imm rd imm20
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u+o rd,offset rd oimm20
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uj rd,offset rd jimm20
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i+o rd,rs1,offset rd rs1 imm12
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i rd,rs1,imm rd rs1 imm12
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i·sh5 rd,rs1,imm rd rs1 shamt5
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i·sh6 rd,rs1,imm rd rs1 shamt6
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i·sh7 rd,rs1,imm rd rs1 shamt7
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i·csr rd,csr,rs1 rd rs1 csr12
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i·csr+i rd,csr,zimm rd zimm csr12
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i+l rd,offset(rs1) rd rs1 oimm12
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i+lf frd,offset(rs1) frd rs1 oimm12
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s rs2,offset(rs1) rs1 rs2 simm12
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sb rs1,rs2,offset rs1 rs2 sbimm12
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s+f frs2,offset(rs1) rs1 frs2 simm12
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r rd,rs1,rs2 rd rs1 rs2
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r+fr frd,rs1 frd rs1
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r+rf rd,frs1 rd frs1
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r+rff rd,frs1,frs2 rd frs1 frs2
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r+3f frd,frs1,frs2 frd frs1 frs2
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r·m+ff rm,frd,frs1 frd frs1 rm
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r·m+fr rm,frd,rs1 frd rs1 rm
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r·m+rf rm,rd,frs1 rd frs1 rm
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r·m+3f rm,frd,frs1,frs2 frd frs1 frs2 rm
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r4·m rm,frd,frs1,frs2,frs3 frd frs1 frs2 frs3 rm
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r·a aqrl,rd,rs2,(rs1) rd rs1 rs2 aq rl
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r·l aqrl,rd,(rs1) rd rs1 aq rl
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r·f pred,succ pred succ
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r+sf rs1 rs1
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cb rs1,rs2,offset crs1q cimmb
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cb·imm rd,rs1,imm crs1rdq cnzimmi
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cb·sh5 rd,rs1,imm crs1rdq cimmsh5
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cb·sh6 rd,rs1,imm crs1rdq cimmsh6
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ci rd,rs1,imm crs1rd cnzimmi
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ci·sh5 rd,rs1,imm crs1rd cimmsh5
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ci·sh6 rd,rs1,imm crs1rd cimmsh6
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ci·16sp rd,rs1,imm crs1rd cimm16sp
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ci·lwsp rd,offset(rs1) crd cimmlwsp
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ci·ldsp rd,offset(rs1) crd cimmldsp
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ci·lqsp rd,offset(rs1) crd cimmlqsp
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ci·lwsp+f frd,offset(rs1) cfrd cimmlwsp
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ci·ldsp+f frd,offset(rs1) cfrd cimmldsp
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ci·li rd,rs1,imm crs1rd cimmi
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ci·lui rd,imm crd cimmui
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ci·none none
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ciw·4spn rd,rs1,imm crdq cimm4spn
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cj rd,offset cimmj
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cj·jal rd,offset cimmj
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cl·lw rd,offset(rs1) crdq crs1q cimmw
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cl·ld rd,offset(rs1) crdq crs1q cimmd
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cl·lq rd,offset(rs1) crdq crs1q cimmq
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cl·lw+f frd,offset(rs1) cfrdq crs1q cimmw
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cl·ld+f frd,offset(rs1) cfrdq crs1q cimmd
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cr rd,rs1,rs2 crs1rd crs2
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cr·mv rd,rs1,rs2 crd crs2
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cr·jalr rd,rs1,offset crd0 crs1
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cr·jr rd,rs1,offset crd0 crs1
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cs rd,rs1,rs2 crs1rdq crs2q
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cs·sw+f frs2,offset(rs1) crs1q cfrs2q cimmw
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cs·sd+f frs2,offset(rs1) crs1q cfrs2q cimmd
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cs·sw rs2,offset(rs1) crs1q crs2q cimmw
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cs·sd rs2,offset(rs1) crs1q crs2q cimmd
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cs·sq rs2,offset(rs1) crs1q crs2q cimmq
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css·swsp rs2,offset(rs1) crs2 cimmswsp
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css·sdsp rs2,offset(rs1) crs2 cimmsdsp
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css·sqsp rs2,offset(rs1) crs2 cimmsqsp
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css·swsp+f frs2,offset(rs1) cfrs2 cimmswsp
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css·sdsp+f frs2,offset(rs1) cfrs2 cimmsdsp

‎compression

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# format of a line in this file:
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# <compressed opcode> <decompressed opcode> [<constraint name> ...]
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#
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# <constraint> is one of imm_6, imm_7, imm_8, imm_9, imm_10, imm_12,
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# imm_18, imm_nz, imm_x2, imm_x4, imm_x8, rd_b3, rs1_b3, rs2_b3,
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# rs1_eq_sp, rd_eq_x0, rs1_eq_x0, rs2_eq_x0, rd_ne_x0, rs1_ne_x0,
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# rs2_ne_x0, rd_eq_rs1, rd_eq_ra, rd_ne_x0_x2, rd_eq_sp
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c.addi4spn addi imm_10 imm_x4 imm_nz rd_b3 rs1_eq_sp
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c.fld fld imm_8 imm_x8 rd_b3 rs1_b3
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c.lw lw imm_7 imm_x4 rd_b3 rs1_b3
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c.flw flw imm_7 imm_x4 rd_b3 rs1_b3
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c.fsd fsd imm_8 imm_x8 rs1_b3 rs2_b3
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c.sw sw imm_7 imm_x4 rs1_b3 rs2_b3
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c.fsw fsw imm_7 imm_x4 rs1_b3 rs2_b3
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c.nop addi rd_eq_x0 rs1_eq_x0 rs2_eq_x0
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c.addi addi simm_6 rd_ne_x0 rd_eq_rs1
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c.jal jal imm_12 imm_x2 rd_eq_ra
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c.li addi imm_6 rd_ne_x0 rs1_eq_x0
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c.lui lui imm_18 imm_nz rd_ne_x0_x2
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c.addi16sp addi imm_10 imm_x4 imm_nz rd_eq_sp rs1_eq_sp
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c.srli srli imm_nz rd_eq_rs1 rd_b3 rs1_b3
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c.srai srai imm_nz rd_eq_rs1 rd_b3 rs1_b3
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c.andi andi imm_nz rd_eq_rs1 rd_b3 rs1_b3
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c.sub sub rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.xor xor rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.or or rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.and and rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.subw subw rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.addw addw rd_eq_rs1 rd_b3 rs1_b3 rs2_b3
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c.j jal imm_12 imm_x2 rd_eq_x0
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c.beqz beq imm_9 imm_x2 rs1_b3 rs2_eq_x0
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c.bnez bne imm_9 imm_x2 rs1_b3 rs2_eq_x0
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c.slli slli imm_nz rd_ne_x0 rd_eq_rs1
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c.fldsp fld imm_9 imm_x8 rs1_eq_sp
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c.lwsp lw imm_8 imm_x4 rd_ne_x0 rs1_eq_sp
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c.flwsp flw imm_8 imm_x4 rs1_eq_sp
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c.jr jalr rd_eq_x0 rs1_ne_x0
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c.mv addi imm_eq_zero rd_ne_x0
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c.ebreak ebreak
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c.jalr jalr rd_eq_ra rs1_ne_x0
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c.add add rd_eq_rs1 rd_ne_x0 rs2_ne_x0
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c.fsdsp fsd imm_9 imm_x8 rs1_eq_sp
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c.swsp sw imm_8 imm_x4 rs1_eq_sp
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c.fswsp fsw imm_8 imm_x4 rs1_eq_sp
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c.ld ld imm_8 imm_x8 rd_b3 rs1_b3
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c.sd sd imm_8 imm_x8 rs1_b3 rs2_b3
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c.lq lq imm_9 imm_x16
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c.sq sq imm_9 imm_x16
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c.addiw addiw imm_6 rd_ne_x0 rd_eq_rs1
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c.ldsp ld imm_9 imm_x8 rd_ne_x0 rs1_eq_sp
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c.sdsp sd imm_9 imm_x8 rs1_eq_sp
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c.lqsp lq imm_10 imm_x16 rs1_eq_sp
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c.sqsp sq imm_10 imm_x16 rs1_eq_sp

‎constraints

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# format of a line in this file:
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# <constraint name> <constraint expression> <hint>
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simm_6 "imm >= -32 && imm < 32"
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imm_6 "imm <= 0b111111"
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imm_7 "imm <= 0b1111111"
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imm_8 "imm <= 0b11111111"
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imm_9 "imm <= 0b111111111"
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imm_10 "imm <= 0b1111111111"
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imm_12 "imm <= 0b111111111111"
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imm_18 "imm <= 0b111111111111111111"
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imm_nz "imm != 0"
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imm_x2 "(imm & 0b1) == 0"
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imm_x4 "(imm & 0b11) == 0"
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imm_x8 "(imm & 0b111) == 0"
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imm_x16 "(imm & 0b1111) == 0"
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rd_b3 "rd >= 8 && rd <= 15"
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rs1_b3 "rs1 >= 8 && rs1 <= 15"
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rs2_b3 "rs2 >= 8 && rs2 <= 15"
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rd_eq_rs1 "rd == rs1"
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rd_eq_ra "rd == 1" "rd=1"
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rd_eq_sp "rd == 2" "rd=2"
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rd_eq_x0 "rd == 0" "rd=0"
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rs1_eq_sp "rs1 == 2"
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rs1_eq_x0 "rs1 == 0"
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rs2_eq_x0 "rs2 == 0" "rs2=0"
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rd_ne_x0_x2 "rd != 0 && rd != 2" "rd≠{0,2}"
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rd_ne_x0 "rd != 0" "rd≠0"
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rs1_ne_x0 "rs1 != 0"
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rs2_ne_x0 "rs2 != 0" "rs2≠0"
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rs2_eq_rs1 "rs2 == rs1"
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rs1_eq_ra "rs1 == 1"
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imm_eq_zero "imm == 0"
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imm_eq_n1 "imm == -1"
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imm_eq_p1 "imm == 1"
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csr_eq_0x001 "imm == 0x001"
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csr_eq_0x002 "imm == 0x002"
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csr_eq_0x003 "imm == 0x003"
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csr_eq_0xc00 "imm == 0xc00"
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csr_eq_0xc01 "imm == 0xc01"
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csr_eq_0xc02 "imm == 0xc02"
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csr_eq_0xc80 "imm == 0xc80"
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csr_eq_0xc81 "imm == 0xc81"
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csr_eq_0xc82 "imm == 0xc82"

‎csr-fields

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# format of a line in this file:
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# <csr> <field> <bitspec> <modes> "<field description>" <version>
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#
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# machine status
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status ie 0 m "Interrupt Enable Stack 0" 1.7
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status prv 2:1 m "Privilege Mode Stack 0" 1.7
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status ie1 3 m "Interrupt Enable Stack 1" 1.7
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status prv1 5:4 m "Privilege Mode Stack 1" 1.7
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status ie2 6 m "Interrupt Enable Stack 2" 1.7
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status prv2 8:7 m "Privilege Mode Stack 2" 1.7
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status ie3 9 m "Interrupt Enable Stack 3" 1.7
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status prv3 11:10 m "Privilege Mode Stack 3" 1.7
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status fs 13:12 mhs "FPU register status" 1.7
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status xs 15:14 mhs "Extension status" 1.7
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status mprv 16 m "Data access at prv1 privilege level" 1.7
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status vm 21:17 m "Virtual Memory Mode" 1.7
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status uie 0 mhsu "User mode Interrupt Enable" 1.9-
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status sie 1 mhs "Supervisor mode Interrupt Enable" 1.9-
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status hie 2 mh "Hypervisor mode Interrupt Enable" 1.9-
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status mie 3 m "Machine mode Interrupt Enable" 1.9-
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status upie 4 mhsu "Prior User mode Interrupt Enable" 1.9-
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status spie 5 mhs "Prior Supervisor mode Interrupt Enable" 1.9-
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status hpie 6 mh "Prior Hypervisor mode Interrupt Enable" 1.9-
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status mpie 7 m "Prior Machine mode Interrupt Enable" 1.9-
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status spp 8 mhs "SRET pop privilege" 1.9-
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status hpp 10:9 mh "HRET pop privilege" 1.9-
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status mpp 12:11 m "MRET pop privilege" 1.9-
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status fs 14:13 mhs "FPU register status" 1.9-
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status xs 16:15 mhs "Extension status" 1.9-
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status mprv 17 m "Data access at mpp privilege level" 1.9-
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status pum 18 mhs "Protect User Memory" 1.9-1.9.1
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status sum 18 mhs "Supervisor User Memory" 1.10-
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status mxr 19 m "Make eXecute Readable" 1.9-
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status tvm 20 mhs "Trap Virtual Memory" 1.10-
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status tw 21 mhs "Timeout Wait" 1.10-
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status tsr 22 mhs "Trap SRET" 1.10-
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status vm 28:24 m "Virtual Memory Mode" 1.9-1.9.1
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# address translation
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ptbr base 31:12 s "Page Table Base Register" 1.7,rv32
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ptbr base 63:12 s "Page Table Base Register" 1.7,rv64
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ptbr ppn 21:0 s "Page Table Base Register (PPN)" 1.9-1.9.1,rv32
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ptbr asid 31:22 s "Page Table Base Register (ASID)" 1.9-1.9.1,rv32
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ptbr ppn 37:0 s "Page Table Base Register (PPN)" 1.9-1.9.1,rv64
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ptbr asid 63:38 s "Page Table Base Register (ASID)" 1.9-1.9.1,rv64
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atp ppn 21:0 s "Address Translation Register (PPN)" 1.10,rv32
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atp asid 30:22 s "Address Translation Register (ASID)" 1.10,rv32
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atp mode 31 s "Address Translation Register (Mode)" 1.10,rv32
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atp ppn 43:0 s "Address Translation Register (PPN)" 1.10,rv64
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atp asid 59:44 s "Address Translation Register (ASID)" 1.10,rv64
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atp mode 63:60 s "Address Translation Register (Mode)" 1.10,rv64
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# machine interrupt pending
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ip usip 0 mhsu "User Software Interrupt Pending" 1.9-
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ip ssip 1 mhs "Supervisor Software Interrupt Pending" 1.9-
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ip hsip 2 mh "Hypervisor Software Interrupt Pending" 1.9-
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ip msip 3 m "Machine Software Interrupt Pending" 1.9-
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ip utip 4 mhsu "User Timer Interrupt Pending" 1.9-
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ip stip 5 mhs "Supervisor Timer Interrupt Pending" 1.9-
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ip htip 6 mh "Hypervisor Timer Interrupt Pending" 1.9-
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ip mtip 7 m "Machine Timer Interrupt Pending" 1.9-
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ip ueip 8 mhsu "User External Interrupt Pending" 1.9-
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ip seip 9 mhs "Supervisor External Interrupt Pending" 1.9-
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ip heip 10 mh "Hypervisor External Interrupt Pending" 1.9-
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ip meip 11 m "Machine External Interrupt Pending" 1.9-
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# machine interrupt enable
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ie usie 0 mhsu "User Software Interrupt Enable" 1.9-
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ie ssie 1 mhs "Supervisor Software Interrupt Enable" 1.9-
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ie hsie 2 mh "Hypervisor Software Interrupt Enable" 1.9-
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ie msie 3 m "Machine Software Interrupt Enable" 1.9-
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ie utie 4 mhsu "User Timer Interrupt Enable" 1.9-
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ie stie 5 mhs "Supervisor Timer Interrupt Enable" 1.9-
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ie htie 6 mh "Hypervisor Timer Interrupt Enable" 1.9-
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ie mtie 7 m "Machine Timer Interrupt Enable" 1.9-
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ie ueie 8 mhsu "User External Interrupt Enable" 1.9-
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ie seie 9 mhs "Supervisor External Interrupt Enable" 1.9-
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ie heie 10 mh "Hypervisor External Interrupt Enable" 1.9-
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ie meie 11 m "Machine External Interrupt Enable" 1.9-

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