diff --git a/fsbl/plat/cv180x/bl2/bl2_main.c b/fsbl/plat/cv180x/bl2/bl2_main.c
index c19ad1f8ad..d48416d3bf 100644
--- a/fsbl/plat/cv180x/bl2/bl2_main.c
+++ b/fsbl/plat/cv180x/bl2/bl2_main.c
@@ -46,8 +46,34 @@ int dec_verify_image(const void *image, size_t size, size_t dec_skip, struct fip
 }
 #endif
 
+// Start of addition
+#define UART_DLL 0x04140000
+#define UART_DLH 0x04140004
+#define UART_LCR 0x0414000C
+
+void set_baudrate()
+{
+	// 14 for 115200, 13 for 128000
+	int baud_divisor = 14;
+
+	// set DLAB to 1 to set dll and dlh
+	*(volatile uint32_t*)(UART_LCR) |= (uint32_t)0x80;
+
+	// set divisor
+	*(volatile uint32_t*)(UART_DLL) = (uint32_t)(baud_divisor & 0xff);
+	*(volatile uint32_t*)(UART_DLH) = (uint32_t)((baud_divisor >> 8) & 0xff);
+
+	// set DLAB back to 0
+	*(volatile uint32_t*)(UART_LCR) &= (uint32_t)(~0x80);
+}
+// End of addition
+
 void bl2_main(void)
 {
+	// Start of addition
+	set_baudrate();
+	// End of addition
+	
 	ATF_STATE = ATF_STATE_BL2_MAIN;
 	time_records->fsbl_start = read_time_ms();
 
diff --git a/opensbi/lib/utils/serial/uart8250.c b/opensbi/lib/utils/serial/uart8250.c
index 1cf6624d83..ccc7aa09df 100644
--- a/opensbi/lib/utils/serial/uart8250.c
+++ b/opensbi/lib/utils/serial/uart8250.c
@@ -101,7 +101,7 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
 	uart8250_in_freq   = in_freq;
 	uart8250_baudrate  = baudrate;
 
-	bdiv = uart8250_in_freq / (16 * uart8250_baudrate);
+	bdiv = (uart8250_in_freq + 8 * uart8250_baudrate) / (16 * uart8250_baudrate);
 
 	/* Disable all interrupts */
 	set_reg(UART_IER_OFFSET, 0x00);