## Overall objectives - low power LLM deployment ## What to be done next - [ ] Vector ALU - [ ] Instruction Issue - [ ] Better ISA Polish: Less instructions that is more extensible and efficient - [ ] Open source placing and routing with rough PPA estimation (OpenROAD) - [ ] FPGA Verificatio No sponsor at all, everything will stay before sign-off and everything here will be leveraging open source stack except the FPGA under [`ip/vivado`](https://github.com/mpskex/chisel-npu/tree/fangrui/valu_isa_design/ip/vivado).
Overall objectives
What to be done next
No sponsor at all, everything will stay before sign-off and everything here will be leveraging open source stack except the FPGA under
ip/vivado.