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corefreq-cli.c
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/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define _GNU_SOURCE
#include <math.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <unistd.h>
#include <fcntl.h>
#include <time.h>
#include <signal.h>
#include <locale.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <sched.h>
#include <pwd.h>
#include "bitasm.h"
#include "coretypes.h"
#include "corefreq.h"
#include "corefreq-ui.h"
#include "corefreq-cli-rsc.h"
#include "corefreq-cli.h"
#include "corefreq-cli-json.h"
#include "corefreq-cli-extra.h"
#define StrFormat( _str, _size, _fmt, ... ) \
snprintf((char*) _str, (size_t) _size, (char*) _fmt, __VA_ARGS__)
#define CONV( _ret, _func, ... ) \
({ \
int lret = _func ( __VA_ARGS__ ); \
_ret = lret > 0 ? (__typeof__ (_ret)) lret : 0; \
})
SHM_STRUCT *Shm = NULL;
static Bit64 Shutdown __attribute__ ((aligned (8))) = 0x0;
SERVICE_PROC localService = {.Proc = -1};
UBENCH_DECLARE()
struct SETTING_ST Setting = {
.fahrCels = 0,
.jouleWatt= 1,
.secret = 1,
._padding = 0
};
char ConfigFQN[1+4095] = {[0] = 0};
char *BuildConfigFQN(char *dirPath)
{
if (ConfigFQN[0] == 0)
{
char *homePath, *dotted;
if ((homePath = secure_getenv("XDG_CONFIG_HOME")) == NULL)
{
struct stat cfgStat;
if ((homePath = secure_getenv("HOME")) == NULL) {
struct passwd *pwd = getpwuid(getuid());
if (pwd != NULL) {
homePath = pwd->pw_dir;
} else {
homePath = ".";
}
}
StrFormat(&ConfigFQN[1], 4095, "%s/.config", homePath);
if ((stat(&ConfigFQN[1], &cfgStat) == 0)
&& (cfgStat.st_mode & S_IFDIR))
{
dotted = "/.config/";
} else {
dotted = "/.";
}
} else {
dotted = "/";
}
StrFormat(&ConfigFQN[1], 4095, "%s%s%s/corefreq.cfg",
homePath, dotted, dirPath);
ConfigFQN[0] = 1;
}
return &ConfigFQN[1];
}
int ClientFollowService(SERVICE_PROC *pSlave, SERVICE_PROC *pMaster, pid_t pid)
{
if (pSlave->Proc != pMaster->Proc) {
pSlave->Proc = pMaster->Proc;
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
CPU_SET(pSlave->Core, &cpuset);
if (pSlave->Thread != -1) {
CPU_SET((unsigned int) pSlave->Thread, &cpuset);
}
return sched_setaffinity(pid, sizeof(cpu_set_t), &cpuset);
}
return 0;
}
struct RULER_ST Ruler = {
.Count = 0
};
#define GetTopOfRuler() (Shm->Cpu[Ruler.TopOf.Top].Boost[Ruler.TopOf.Boost])
#define SetTopOfRuler(_cpu, _boost) \
( \
Ruler.TopOf = (struct TOPOF) { .Top = _cpu , .Boost = _boost} \
)
void AggregateRatio(void)
{
const unsigned int highestFactory = MAXCLOCK_TO_RATIO(
unsigned int, Shm->Proc.Features.Factory.Clock.Hz
);
enum RATIO_BOOST lt, rt;
unsigned int cpu,
lowest = Shm->Cpu[Shm->Proc.Service.Core].Boost[BOOST(MAX)],
highest = Shm->Cpu[Shm->Proc.Service.Core].Boost[BOOST(MIN)];
Ruler.Count = 0;
for (lt = BOOST(MIN); lt < BOOST(SIZE); lt++) {
Ruler.Top[lt] = Shm->Proc.Service.Core;
Ruler.Uniq[lt] = 0.0;
}
SetTopOfRuler(Shm->Proc.Service.Core, BOOST(MIN));
for (cpu = 0; cpu < Shm->Proc.CPU.Count; cpu++)
{
if (!BITVAL(Shm->Cpu[cpu].OffLine, OS))
{
for (lt = BOOST(MIN); lt < BOOST(SIZE); lt++)
{
if (Shm->Cpu[cpu].Boost[lt] > 0)
{
switch (lt) {
case BOOST(HWP_MIN):
case BOOST(MIN):
if(Shm->Cpu[cpu].Boost[lt] < Shm->Cpu[ Ruler.Top[lt] ].Boost[lt])
{
Ruler.Top[lt] = cpu;
}
if (Shm->Cpu[cpu].Boost[lt] < lowest)
{
lowest = Shm->Cpu[cpu].Boost[lt];
SetTopOfRuler(Ruler.Top[lt], lt);
}
break;
default:
if(Shm->Cpu[cpu].Boost[lt] > Shm->Cpu[ Ruler.Top[lt] ].Boost[lt])
{
Ruler.Top[lt] = cpu;
}
if (Shm->Cpu[cpu].Boost[lt] > highest)
{
highest = Shm->Cpu[cpu].Boost[lt];
SetTopOfRuler(Ruler.Top[lt], lt);
}
break;
}
for (rt = BOOST(MIN); rt < Ruler.Count; rt++)
{
if (Ruler.Uniq[rt] == Shm->Cpu[cpu].Boost[lt])
{
break;
}
}
if (rt == Ruler.Count)
{
if (Shm->Cpu[cpu].Boost[lt] <= highestFactory) {
Ruler.Uniq[Ruler.Count] = Shm->Cpu[cpu].Boost[lt];
}
Ruler.Count++;
}
}
}
}
}
Ruler.Minimum = (double) lowest;
Ruler.Maximum = (double) highest;
Ruler.Median=(double) Shm->Cpu[Ruler.Top[BOOST(ACT)]].Boost[BOOST(ACT)];
if (Ruler.Median == 0.0) {
Ruler.Median = (Ruler.Minimum + Ruler.Maximum) / 2.0;
}
}
ATTRIBUTE *StateToSymbol(short int state, char stateStr[])
{
ATTRIBUTE *symbAttr[14] = {
/* R */ RSC(RUN_STATE_COLOR).ATTR(),
/* S */ RSC(SLEEP_STATE_COLOR).ATTR(),
/* D */ RSC(UNINT_STATE_COLOR).ATTR(),
/* T */ RSC(WAIT_STATE_COLOR).ATTR(),
/* t */ RSC(WAIT_STATE_COLOR).ATTR(),
/* X */ RSC(WAIT_STATE_COLOR).ATTR(),
/* Z */ RSC(ZOMBIE_STATE_COLOR).ATTR(),
/* P */ RSC(WAIT_STATE_COLOR).ATTR(),
/* I */ RSC(WAIT_STATE_COLOR).ATTR(),
/* K */ RSC(SLEEP_STATE_COLOR).ATTR(),
/* W */ RSC(RUN_STATE_COLOR).ATTR(),
/* i */ RSC(WAIT_STATE_COLOR).ATTR(),
/* N */ RSC(RUN_STATE_COLOR).ATTR(),
/* m */ RSC(OTHER_STATE_COLOR).ATTR()
}, *stateAttr = RSC(OTHER_STATE_COLOR).ATTR();
const char symbol[14] = "RSDTtXZPIKWiNm";
unsigned short idx, jdx = 0;
if (BITBSR(state, idx) == 1) {
stateStr[jdx++] = symbol[0];
stateAttr = symbAttr[0];
} else
do {
BITCLR(LOCKLESS, state, (unsigned int) idx);
stateStr[jdx++] = symbol[1 + idx];
stateAttr = symbAttr[1 + idx];
} while (!BITBSR(state, idx));
stateStr[jdx] = '\0';
return stateAttr;
}
unsigned int Dec2Digit( const unsigned int length, unsigned int decimal,
unsigned int thisDigit[] )
{
memset(thisDigit, 0, length * sizeof(unsigned int));
register unsigned int j = length, dec = decimal;
while (dec > 0) {
thisDigit[--j] = dec % 10;
dec /= 10;
}
return length - j;
}
#define Cels2Fahr(cels) (((cels * 117965) >> 16) + 32)
const char *Indent[2][4] = {
{"", "|", "|- ", " |- "},
{"", " ", " ", " "}
};
TGrid *Print_v1(CELL_FUNC OutFunc,
Window *win,
unsigned long long key,
ATTRIBUTE *attrib,
CUINT width,
int tab,
char *fmt, ...)
{
TGrid *pGrid = NULL;
char *line = malloc(width + 1);
if (line != NULL)
{
va_list ap;
va_start(ap, fmt);
if (vsnprintf(line, width + 1, fmt, ap) < 0) {
goto EXIT_v1;
}
if (OutFunc == NULL) {
printf("%s%s%.*s\n", Indent[0][tab], line,
(int)(width - strlen(line) - strlen(Indent[0][tab])), hSpace);
} else {
ASCII *item = malloc(width + 1);
if (item != NULL) {
if (0 < StrFormat(item, width + 1, "%s%s%.*s", Indent[1][tab], line,
(int)(width - strlen(line) - strlen(Indent[1][tab])), hSpace))
{
pGrid = OutFunc(win, key, attrib, item);
}
free(item);
}
}
EXIT_v1:
va_end(ap);
free(line);
}
return pGrid;
}
TGrid *Print_v2(CELL_FUNC OutFunc,
Window *win,
CUINT *nl,
ATTRIBUTE *attrib, ...)
{
TGrid *pGrid = NULL;
ASCII *item = malloc(MIN_WIDTH);
if (item != NULL)
{
char *fmt;
va_list ap;
va_start(ap, attrib);
if ((fmt = va_arg(ap, char*)) != NULL)
{
if (vsnprintf((char*) item, MIN_WIDTH, fmt, ap) < 0) {
goto EXIT_v2;
}
if (OutFunc == NULL) {
(*nl)--;
if ((*nl) == 0) {
(*nl) = win->matrix.size.wth;
printf("%s\n", item);
} else
printf("%s", item);
} else {
pGrid = OutFunc(win, SCANKEY_NULL, attrib, item);
}
}
EXIT_v2:
va_end(ap);
free(item);
}
return pGrid;
}
TGrid *Print_v3(CELL_FUNC OutFunc,
Window *win,
CUINT *nl,
ATTRIBUTE *attrib, ...)
{
TGrid *pGrid = NULL;
ASCII *item = malloc(MIN_WIDTH);
if (item != NULL)
{
char *fmt;
va_list ap;
va_start(ap, attrib);
if ((fmt = va_arg(ap, char*)) != NULL)
{
if (!(vsnprintf((char*) item, MIN_WIDTH, fmt, ap) < 0))
{
if (OutFunc == NULL) {
(*nl)--;
if ((*nl) == (win->matrix.size.wth - 1)) {
printf("|-%s", item);
} else if ((*nl) == 0) {
(*nl) = win->matrix.size.wth;
printf("%s\n", item);
} else {
printf("%s", item);
}
} else {
pGrid = OutFunc(win, SCANKEY_NULL, attrib, item);
}
}
}
va_end(ap);
free(item);
}
return pGrid;
}
#define PUT(key, attrib, width, tab, fmt, ...) \
Print_v1(OutFunc, win, key, attrib, width, tab, fmt, __VA_ARGS__)
#define Print_REG Print_v2
#define Print_MAP Print_v2
#define Print_IMC Print_v2
#define Print_ISA Print_v3
#define PRT(FUN, attrib, ...) \
Print_##FUN(OutFunc, win, nl, attrib, __VA_ARGS__)
REASON_CODE SysInfoCPUID(Window *win, CUINT width, CELL_FUNC OutFunc)
{
REASON_INIT(reason);
ATTRIBUTE *attrib[4] = {
RSC(SYSINFO_CPUID_COND0).ATTR(),
RSC(SYSINFO_CPUID_COND1).ATTR(),
RSC(SYSINFO_CPUID_COND2).ATTR(),
RSC(SYSINFO_CPUID_COND3).ATTR()
};
char format[] = "%08x:%08x%.*s%08x %08x %08x %08x";
unsigned int cpu;
for (cpu = 0; cpu < Shm->Proc.CPU.Count; cpu++) {
if (OutFunc == NULL) {
PUT(SCANKEY_NULL, attrib[0], width, 0,
"CPU #%-3u function" \
" EAX EBX ECX EDX",
cpu);
} else {
PUT(SCANKEY_NULL,
attrib[BITVAL(Shm->Cpu[cpu].OffLine, OS)],
width, 0, "CPU #%-3u", cpu);
}
if (!BITVAL(Shm->Cpu[cpu].OffLine, OS)) {
PUT(SCANKEY_NULL, attrib[3], width, 2, format,
0x00000000, 0x00000000,
4, hSpace,
Shm->Cpu[cpu].Query.StdFunc.LargestStdFunc,
Shm->Cpu[cpu].Query.StdFunc.BX,
Shm->Cpu[cpu].Query.StdFunc.CX,
Shm->Cpu[cpu].Query.StdFunc.DX);
PUT(SCANKEY_NULL, attrib[2], width, 3,
"%.*s""=%08x",
25, RSC(LARGEST_STD_FUNC).CODE(),
Shm->Cpu[cpu].Query.StdFunc.LargestStdFunc);
PUT(SCANKEY_NULL, attrib[3], width, 2, format,
0x80000000, 0x00000000,
4, hSpace,
Shm->Cpu[cpu].Query.ExtFunc.LargestExtFunc,
Shm->Cpu[cpu].Query.ExtFunc.EBX,
Shm->Cpu[cpu].Query.ExtFunc.ECX,
Shm->Cpu[cpu].Query.ExtFunc.EDX);
PUT(SCANKEY_NULL, attrib[2], width, 3,
"%.*s""=%08x",
25, RSC(LARGEST_EXT_FUNC).CODE(),
Shm->Cpu[cpu].Query.ExtFunc.LargestExtFunc);
enum CPUID_ENUM i;
for (i = 0; i < CPUID_MAX_FUNC; i++) {
if (Shm->Cpu[cpu].CpuID[i].func) {
PUT(SCANKEY_NULL, attrib[3], width, 2,
format,
Shm->Cpu[cpu].CpuID[i].func,
Shm->Cpu[cpu].CpuID[i].sub,
4, hSpace,
Shm->Cpu[cpu].CpuID[i].reg[0],
Shm->Cpu[cpu].CpuID[i].reg[1],
Shm->Cpu[cpu].CpuID[i].reg[2],
Shm->Cpu[cpu].CpuID[i].reg[3]);
}
}
}
}
return reason;
}
REASON_CODE SystemRegisters(Window *win, CELL_FUNC OutFunc)
{
REASON_INIT(reason);
ATTRIBUTE *attrib[5] = {
RSC(SYSTEM_REGISTERS_COND0).ATTR(),
RSC(SYSTEM_REGISTERS_COND1).ATTR(),
RSC(SYSTEM_REGISTERS_COND2).ATTR(),
RSC(SYSTEM_REGISTERS_COND3).ATTR(),
RSC(SYSTEM_REGISTERS_COND4).ATTR()
};
enum AUTOMAT {
DO_END, DO_SPC, DO_CPU, DO_FLAG,
DO_CR0, DO_CR3, DO_CR4, DO_CR8,
DO_EFCR, DO_EFER
};
const struct SR_ST {
struct SR_HDR {
const ASCII *flag,
*comm;
} *header;
struct SR_BIT {
enum AUTOMAT automat;
unsigned int *CRC;
enum SYS_REG pos;
unsigned int len;
} *flag;
} SR[] = \
{
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REGS_HDR_CPU).CODE(), NULL},
[ 1] = {RSC(SYS_REG_HDR_FLAGS).CODE(), NULL},
[ 2] = {RSC(SYS_REG_HDR_TF).CODE(), RSC(SYS_REG_FLAGS_TF).CODE()},
[ 3] = {RSC(SYS_REG_HDR_IF).CODE(), RSC(SYS_REG_FLAGS_IF).CODE()},
[ 4] = {RSC(SYS_REG_HDR_IOPL).CODE(), RSC(SYS_REG_FLAGS_IOPL).CODE()},
[ 5] = {RSC(SYS_REG_HDR_NT).CODE(), RSC(SYS_REG_FLAGS_NT).CODE()},
[ 6] = {RSC(SYS_REG_HDR_RF).CODE(), RSC(SYS_REG_FLAGS_RF).CODE()},
[ 7] = {RSC(SYS_REG_HDR_VM).CODE(), RSC(SYS_REG_FLAGS_VM).CODE()},
[ 8] = {RSC(SYS_REG_HDR_AC).CODE(), RSC(SYS_REG_FLAGS_AC).CODE()},
[ 9] = {RSC(SYS_REG_HDR_VIF).CODE(), RSC(SYS_REG_FLAGS_VIF).CODE()},
[10] = {RSC(SYS_REG_HDR_VIP).CODE(), RSC(SYS_REG_FLAGS_VIP).CODE()},
[11] = {RSC(SYS_REG_HDR_ID).CODE(), RSC(SYS_REG_FLAGS_ID).CODE()},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_SPC , NULL , UNDEF_CR , 0 },
[ 2] = {DO_FLAG, NULL , RFLAG_TF , 1 },
[ 3] = {DO_FLAG, NULL , RFLAG_IF , 1 },
[ 4] = {DO_FLAG, NULL , RFLAG_IOPL , 2 },
[ 5] = {DO_FLAG, NULL , RFLAG_NT , 1 },
[ 6] = {DO_FLAG, NULL , RFLAG_RF , 1 },
[ 7] = {DO_FLAG, NULL , RFLAG_VM , 1 },
[ 8] = {DO_FLAG, NULL , RFLAG_AC , 1 },
[ 9] = {DO_FLAG, NULL , RFLAG_VIF , 1 },
[10] = {DO_FLAG, NULL , RFLAG_VIP , 1 },
[11] = {DO_FLAG, NULL , RFLAG_ID , 1 },
[12] = {DO_SPC , NULL , UNDEF_CR , 0 },
[13] = {DO_SPC , NULL , UNDEF_CR , 0 },
[14] = {DO_SPC , NULL , UNDEF_CR , 0 },
[15] = {DO_SPC , NULL , UNDEF_CR , 0 },
[16] = {DO_SPC , NULL , UNDEF_CR , 0 },
{DO_END , NULL , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REG_HDR_CR0).CODE(), RSC(SYS_REGS_CR0).CODE()},
[ 1] = {RSC(SYS_REG_HDR_CR0_PE).CODE(), RSC(SYS_REG_CR0_PE).CODE()},
[ 2] = {RSC(SYS_REG_HDR_CR0_MP).CODE(), RSC(SYS_REG_CR0_MP).CODE()},
[ 3] = {RSC(SYS_REG_HDR_CR0_EM).CODE(), RSC(SYS_REG_CR0_EM).CODE()},
[ 4] = {RSC(SYS_REG_HDR_CR0_TS).CODE(), RSC(SYS_REG_CR0_TS).CODE()},
[ 5] = {RSC(SYS_REG_HDR_CR0_ET).CODE(), RSC(SYS_REG_CR0_ET).CODE()},
[ 6] = {RSC(SYS_REG_HDR_CR0_NE).CODE(), RSC(SYS_REG_CR0_NE).CODE()},
[ 7] = {RSC(SYS_REG_HDR_CR0_WP).CODE(), RSC(SYS_REG_CR0_WP).CODE()},
[ 8] = {RSC(SYS_REG_HDR_CR0_AM).CODE(), RSC(SYS_REG_CR0_AM).CODE()},
[ 9] = {RSC(SYS_REG_HDR_CR0_NW).CODE(), RSC(SYS_REG_CR0_NW).CODE()},
[10] = {RSC(SYS_REG_HDR_CR0_CD).CODE(), RSC(SYS_REG_CR0_CD).CODE()},
[11] = {RSC(SYS_REG_HDR_CR0_PG).CODE(), RSC(SYS_REG_CR0_PG).CODE()},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REG_HDR_CR3).CODE(), RSC(SYS_REGS_CR3).CODE()},
[15] = {RSC(SYS_REG_HDR_CR3_PWT).CODE(), RSC(SYS_REG_CR3_PWT).CODE()},
[16] = {RSC(SYS_REG_HDR_CR3_PCD).CODE(), RSC(SYS_REG_CR3_PCD).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_CR0 , NULL , CR0_PE , 1 },
[ 2] = {DO_CR0 , NULL , CR0_MP , 1 },
[ 3] = {DO_CR0 , NULL , CR0_EM , 1 },
[ 4] = {DO_CR0 , NULL , CR0_TS , 1 },
[ 5] = {DO_CR0 , NULL , CR0_ET , 1 },
[ 6] = {DO_CR0 , NULL , CR0_NE , 1 },
[ 7] = {DO_CR0 , NULL , CR0_WP , 1 },
[ 8] = {DO_CR0 , NULL , CR0_AM , 1 },
[ 9] = {DO_CR0 , NULL , CR0_NW , 1 },
[10] = {DO_CR0 , NULL , CR0_CD , 1 },
[11] = {DO_CR0 , NULL , CR0_PG , 1 },
[12] = {DO_SPC , NULL , UNDEF_CR , 0 },
[13] = {DO_SPC , NULL , UNDEF_CR , 0 },
[14] = {DO_SPC , NULL , UNDEF_CR , 4 },
[15] = {DO_CR3 , NULL , CR3_PWT , 1 },
[16] = {DO_CR3 , NULL , CR3_PCD , 1 },
{DO_END , NULL , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REG_HDR_CR4).CODE(), RSC(SYS_REGS_CR4).CODE()},
[ 1] = {RSC(SYS_REG_HDR_CR4_VME).CODE(),RSC(SYS_REG_CR4_VME).CODE()},
[ 2] = {RSC(SYS_REG_HDR_CR4_PVI).CODE(),RSC(SYS_REG_CR4_PVI).CODE()},
[ 3] = {RSC(SYS_REG_HDR_CR4_TSD).CODE(),RSC(SYS_REG_CR4_TSD).CODE()},
[ 4] = {RSC(SYS_REG_HDR_CR4_DE).CODE(), RSC(SYS_REG_CR4_DE).CODE()},
[ 5] = {RSC(SYS_REG_HDR_CR4_PSE).CODE(),RSC(SYS_REG_CR4_PSE).CODE()},
[ 6] = {RSC(SYS_REG_HDR_CR4_PAE).CODE(),RSC(SYS_REG_CR4_PAE).CODE()},
[ 7] = {RSC(SYS_REG_HDR_CR4_MCE).CODE(),RSC(SYS_REG_CR4_MCE).CODE()},
[ 8] = {RSC(SYS_REG_HDR_CR4_PGE).CODE(),RSC(SYS_REG_CR4_PGE).CODE()},
[ 9] = {RSC(SYS_REG_HDR_CR4_PCE).CODE(),RSC(SYS_REG_CR4_PCE).CODE()},
[10] = {RSC(SYS_REG_HDR_CR4_FX).CODE(), RSC(SYS_REG_CR4_FX).CODE()},
[11] = {RSC(SYS_REG_HDR_CR4_XMM).CODE(),RSC(SYS_REG_CR4_XMM).CODE()},
[12] = {RSC(SYS_REG_HDR_CR4_UMIP).CODE(),RSC(SYS_REG_CR4_UMIP).CODE()},
[13] = {RSC(SYS_REG_HDR_CR4_5LP).CODE(),RSC(SYS_REG_CR4_5LP).CODE()},
[14] = {RSC(SYS_REG_HDR_CR4_VMX).CODE(),RSC(SYS_REG_CR4_VMX).CODE()},
[15] = {RSC(SYS_REG_HDR_CR4_SMX).CODE(),RSC(SYS_REG_CR4_SMX).CODE()},
[16] = {RSC(SYS_REG_HDR_CR4_FS).CODE(), RSC(SYS_REG_CR4_FS).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_CR4 , NULL , CR4_VME , 1 },
[ 2] = {DO_CR4 , NULL , CR4_PVI , 1 },
[ 3] = {DO_CR4 , NULL , CR4_TSD , 1 },
[ 4] = {DO_CR4 , NULL , CR4_DE , 1 },
[ 5] = {DO_CR4 , NULL , CR4_PSE , 1 },
[ 6] = {DO_CR4 , NULL , CR4_PAE , 1 },
[ 7] = {DO_CR4 , NULL , CR4_MCE , 1 },
[ 8] = {DO_CR4 , NULL , CR4_PGE , 1 },
[ 9] = {DO_CR4 , NULL , CR4_PCE , 1 },
[10] = {DO_CR4 , NULL , CR4_OSFXSR , 1 },
[11] = {DO_CR4 , NULL , CR4_OSXMMEXCPT, 1 },
[12] = {DO_CR4 , NULL , CR4_UMIP , 1 },
[13] = {DO_CR4 , NULL , CR4_LA57 , 1 },
[14] = {DO_CR4 , NULL , CR4_VMXE , 1 },
[15] = {DO_CR4 , NULL , CR4_SMXE , 1 },
[16] = {DO_CR4 , NULL , CR4_FSGSBASE , 1 },
{DO_END , NULL , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REG_HDR_CR4).CODE(), RSC(SYS_REGS_CR4).CODE()},
[ 1] = {RSC(SYS_REG_HDR_CR4_PCID).CODE(),RSC(SYS_REG_CR4_PCID).CODE()},
[ 2] = {RSC(SYS_REG_HDR_CR4_SAV).CODE(),RSC(SYS_REG_CR4_SAV).CODE()},
[ 3] = {RSC(SYS_REG_HDR_CR4_KL).CODE(), RSC(SYS_REG_CR4_KL).CODE()},
[ 4] = {RSC(SYS_REG_HDR_CR4_SME).CODE(),RSC(SYS_REG_CR4_SME).CODE()},
[ 5] = {RSC(SYS_REG_HDR_CR4_SMA).CODE(),RSC(SYS_REG_CR4_SMA).CODE()},
[ 6] = {RSC(SYS_REG_HDR_CR4_PKE).CODE(),RSC(SYS_REG_CR4_PKE).CODE()},
[ 7] = {RSC(SYS_REG_HDR_CR4_CET).CODE(),RSC(SYS_REG_CR4_CET).CODE()},
[ 8] = {RSC(SYS_REG_HDR_CR4_PKS).CODE(),RSC(SYS_REG_CR4_PKS).CODE()},
[ 9] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[10] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[11] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REG_HDR_CR8).CODE(), RSC(SYS_REGS_CR8).CODE() },
[16] = {RSC(SYS_REG_HDR_CR8_TPL).CODE(), RSC(SYS_REG_CR8_TPL).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_CR4 , NULL , CR4_PCIDE , 1 },
[ 2] = {DO_CR4 , NULL , CR4_OSXSAVE , 1 },
[ 3] = {DO_CR4 , NULL , CR4_KL , 1 },
[ 4] = {DO_CR4 , NULL , CR4_SMEP , 1 },
[ 5] = {DO_CR4 , NULL , CR4_SMAP , 1 },
[ 6] = {DO_CR4 , NULL , CR4_PKE , 1 },
[ 7] = {DO_CR4 , NULL , CR4_CET , 1 },
[ 8] = {DO_CR4 , NULL , CR4_PKS , 1 },
[ 9] = {DO_SPC , NULL , UNDEF_CR , 0 },
[10] = {DO_SPC , NULL , UNDEF_CR , 0 },
[11] = {DO_SPC , NULL , UNDEF_CR , 0 },
[12] = {DO_SPC , NULL , UNDEF_CR , 0 },
[13] = {DO_SPC , NULL , UNDEF_CR , 0 },
[14] = {DO_SPC , NULL , UNDEF_CR , 0 },
[15] = {DO_SPC , NULL , UNDEF_CR , 0 },
[16] = {DO_CR8 , NULL , CR8_TPL , 4 },
{DO_END , NULL , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REG_HDR_EFCR).CODE(), RSC(SYS_REGS_EFCR).CODE()},
[ 1] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[ 2] = {RSC(SYS_REG_HDR_EFCR_LCK).CODE(),RSC(SYS_REG_EFCR_LCK).CODE()},
[ 3] = {RSC(SYS_REG_HDR_EFCR_VMX).CODE(),RSC(SYS_REG_EFCR_VMX).CODE()},
[ 4] = {RSC(SYS_REG_HDR_EFCR_SGX).CODE(),RSC(SYS_REG_EFCR_SGX).CODE()},
[ 5] = {RSC(SYS_REG_HDR_EFCR_LSE).CODE(),RSC(SYS_REG_EFCR_LSE).CODE()},
[ 6] = {RSC(SYS_REG_HDR_EFCR_GSE).CODE(),RSC(SYS_REG_EFCR_GSE).CODE()},
[ 7] ={RSC(SYS_REG_HDR_EFCR_LSGX).CODE(),RSC(SYS_REG_EFCR_LSGX).CODE()},
[ 8] ={RSC(SYS_REG_HDR_EFCR_GSGX).CODE(),RSC(SYS_REG_EFCR_GSGX).CODE()},
[ 9] = {RSC(SYS_REG_HDR_EFCR_LMC).CODE(),RSC(SYS_REG_EFCR_LMC).CODE()},
[10] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[11] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_SPC , NULL , UNDEF_CR , 0 },
[ 2] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_LOCK, 1},
[ 3] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_VMX_IN_SMX, 1},
[ 4] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_VMXOUT_SMX, 1},
[ 5] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_SENTER_LEN, 6},
[ 6] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_SENTER_GEN, 1},
[ 7] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_SGX_LCE, 1},
[ 8] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_SGX_GEN, 1},
[ 9] = {DO_EFCR,(unsigned int[]) {CRC_INTEL, 0}, EXFCR_LMCE, 1},
[10] = {DO_SPC , NULL , UNDEF_CR , 0 },
[11] = {DO_SPC , NULL , UNDEF_CR , 0 },
[12] = {DO_SPC , NULL , UNDEF_CR , 0 },
[13] = {DO_SPC , NULL , UNDEF_CR , 0 },
[14] = {DO_SPC , NULL , UNDEF_CR , 0 },
[15] = {DO_SPC , NULL , UNDEF_CR , 0 },
[16] = {DO_SPC , NULL , UNDEF_CR , 0 },
{DO_END , NULL , UNDEF_CR , 0 }
}
},
{
.header = (struct SR_HDR[]) {
[ 0] = {RSC(SYS_REG_HDR_EFER).CODE(), RSC(SYS_REGS_EFER).CODE()},
[ 1] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[ 2] = {RSC(SYS_REG_HDR_EFER_SCE).CODE(),RSC(SYS_REG_EFER_SCE).CODE()},
[ 3] = {RSC(SYS_REG_HDR_EFER_LME).CODE(),RSC(SYS_REG_EFER_LME).CODE()},
[ 4] = {RSC(SYS_REG_HDR_EFER_LMA).CODE(),RSC(SYS_REG_EFER_LMA).CODE()},
[ 5] = {RSC(SYS_REG_HDR_EFER_NXE).CODE(),RSC(SYS_REG_EFER_NXE).CODE()},
[ 6] = {RSC(SYS_REG_HDR_EFER_SVM).CODE(),RSC(SYS_REG_EFER_SVM).CODE()},
[ 7] = {RSC(SYS_REG_HDR_EFER_LMS).CODE(),RSC(SYS_REG_EFER_LMS).CODE()},
[ 8] = {RSC(SYS_REG_HDR_EFER_FFX).CODE(),RSC(SYS_REG_EFER_FFX).CODE()},
[ 9] = {RSC(SYS_REG_HDR_EFER_TCE).CODE(),RSC(SYS_REG_EFER_TCE).CODE()},
[10] = {RSC(SYS_REG_HDR_EFER_MCM).CODE(),RSC(SYS_REG_EFER_MCM).CODE()},
[11] = {RSC(SYS_REG_HDR_EFER_WBI).CODE(),RSC(SYS_REG_EFER_WBI).CODE()},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
[ 0] = {DO_CPU , NULL , UNDEF_CR , 0 },
[ 1] = {DO_SPC , NULL , UNDEF_CR , 0 },
[ 2] = {DO_EFER, NULL , EXFER_SCE , 1 },
[ 3] = {DO_EFER, NULL , EXFER_LME , 1 },
[ 4] = {DO_EFER, NULL , EXFER_LMA , 1 },
[ 5] = {DO_EFER, NULL , EXFER_NXE , 1 },
[ 6] = {DO_EFER, NULL , EXFER_SVME , 1 },
[ 7] = {DO_EFER, NULL , EXFER_LMSLE , 1 },
[ 8] = {DO_EFER, NULL , EXFER_FFXSE , 1 },
[ 9] = {DO_EFER, NULL , EXFER_TCE , 1 },
[10] = {DO_EFER, NULL , EXFER_MCOMMIT , 1 },
[11] = {DO_EFER, NULL , EXFER_INT_WBINVD , 1 },
[12] = {DO_SPC , NULL , UNDEF_CR , 0 },
[13] = {DO_SPC , NULL , UNDEF_CR , 0 },
[14] = {DO_SPC , NULL , UNDEF_CR , 0 },
[15] = {DO_SPC , NULL , UNDEF_CR , 0 },
[16] = {DO_SPC , NULL , UNDEF_CR , 0 },
{DO_END , NULL , UNDEF_CR , 0 }
}
}
};
CUINT cells_per_line = win->matrix.size.wth, *nl = &cells_per_line;
size_t idx;
for (idx = 0; idx < sizeof(SR) / sizeof(struct SR_ST); idx++)
{
struct SR_HDR *pHdr;
for (pHdr = SR[idx].header; pHdr->flag != NULL; pHdr++)
{
GridHover( PRT(REG, attrib[0], "%s", pHdr->flag),
(char *) pHdr->comm );
}
unsigned int cpu;
for (cpu = 0; cpu < Shm->Proc.CPU.Count; cpu++)
{
struct SR_BIT *pFlag;
for (pFlag = SR[idx].flag; pFlag->automat != DO_END; pFlag++)
{
switch (pFlag->automat) {
case DO_END:
case DO_SPC:
PRT(REG, attrib[0], RSC(SYS_REGS_SPACE).CODE());
break;
case DO_CPU:
PRT(REG,attrib[BITVAL(Shm->Cpu[cpu].OffLine,OS) ? 4:3],
"#%-2u ", cpu);
break;
default:
{
unsigned short capable = 0;
if (pFlag->CRC == NULL) {
capable = 1;
}
else
{
unsigned int *CRC;
for (CRC = pFlag->CRC;
(*CRC) != 0 && capable == 0; CRC++)
{
if((*CRC) == Shm->Proc.Features.Info.Vendor.CRC)
{
capable = 1;
}
}
}
if ((capable) && !BITVAL(Shm->Cpu[cpu].OffLine, OS))
{
switch (pFlag->automat) {
case DO_FLAG:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.RFLAGS,
pFlag->pos, pFlag->len));
break;
case DO_CR0:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.CR0,
pFlag->pos, pFlag->len));
break;
case DO_CR3:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.CR3,
pFlag->pos, pFlag->len));
break;
case DO_CR4:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.CR4,
pFlag->pos, pFlag->len));
break;
case DO_CR8:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.CR8,
pFlag->pos, pFlag->len));
break;
case DO_EFCR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.EFCR,
pFlag->pos, pFlag->len));
break;
case DO_EFER:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(Shm->Cpu[cpu].SystemRegister.EFER,
pFlag->pos, pFlag->len));
break;
default:
PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE());
break;
}
} else {
PRT(REG, attrib[1], RSC(SYS_REGS_NA).CODE());
}
}
break;
}
}
}
}
return reason;
}
char SymbUnlock[2][2] = {{'[', ']'}, {'<', '>'}};
TGrid *PrintRatioFreq( Window *win, struct FLIP_FLOP *CFlop,
unsigned int zerobase, char *pfx, unsigned int *pRatio,
int syc, unsigned long long _key,
CUINT width, CELL_FUNC OutFunc, ATTRIBUTE attrib[])
{
TGrid *pGrid = NULL;
if ((( (*pRatio) > 0) && !zerobase) || (zerobase))
{
double Freq_MHz = ABS_FREQ_MHz(double, (*pRatio), CFlop->Clock);
if ((Freq_MHz > 0.0) && (Freq_MHz < CLOCK_MHz(double, UNIT_GHz(10.0))))
{
pGrid = PUT(_key, attrib, width, 0,
"%.*s""%s""%.*s""%7.2f""%.*s""%c%4d %c",
(int) (20 - strlen(pfx)), hSpace, pfx, 3, hSpace,
Freq_MHz,
20, hSpace,
SymbUnlock[syc][0],
(*pRatio),
SymbUnlock[syc][1]);
} else {
pGrid = PUT(_key, attrib, width, 0,
"%.*s""%s""%.*s""%7s""%.*s""%c%4d %c",
(int) (20 - strlen(pfx)), hSpace, pfx, 3, hSpace,
RSC(AUTOMATIC).CODE(),
20, hSpace,
SymbUnlock[syc][0],
(*pRatio),
SymbUnlock[syc][1]);
}
}
return pGrid;
}
void RefreshBaseClock(TGrid *grid, DATA_TYPE data)
{
struct FLIP_FLOP *CFlop = &Shm->Cpu[Shm->Proc.Service.Core] \
.FlipFlop[!Shm->Cpu[Shm->Proc.Service.Core].Toggle];
char item[8+1];
UNUSED(data);
StrFormat(item, 8+1, "%7.3f", CLOCK_MHz(double, CFlop->Clock.Hz));
memcpy(&grid->cell.item[grid->cell.length - 9], item, 7);
}
void RefreshFactoryClock(TGrid *grid, DATA_TYPE data)
{
char item[8+1];
UNUSED(data);
StrFormat(item, 8+1, "%7.3f",
CLOCK_MHz(double, Shm->Proc.Features.Factory.Clock.Hz));
memcpy(&grid->cell.item[grid->cell.length - 9], item, 7);
}
void RefreshFactoryFreq(TGrid *grid, DATA_TYPE data)
{
char item[11+11+1];
UNUSED(data);
StrFormat(item, 11+11+1, "%5u" "%4d",
Shm->Proc.Features.Factory.Freq,
Shm->Proc.Features.Factory.Ratio);
memcpy(&grid->cell.item[22], &item[0], 5);
memcpy(&grid->cell.item[51], &item[5], 4);
}
void RefreshItemFreq(TGrid *grid, unsigned int ratio, double Freq_MHz)
{
char item[11+8+1];
if ((Freq_MHz > 0.0) && (Freq_MHz < CLOCK_MHz(double, UNIT_GHz(10.0)))) {
StrFormat(item,11+8+1, "%4u%7.2f", ratio, Freq_MHz);
} else {
StrFormat(item,11+7+1, "%4u%7s", ratio, RSC(AUTOMATIC).CODE());
}
memcpy(&grid->cell.item[23], &item[4], 7);
memcpy(&grid->cell.item[51], &item[0], 4);
}
void RefreshRatioFreq(TGrid *grid, DATA_TYPE data)
{
struct FLIP_FLOP *CFlop = &Shm->Cpu[
Shm->Proc.Service.Core
].FlipFlop[
!Shm->Cpu[Shm->Proc.Service.Core
].Toggle];
RefreshItemFreq(grid,
(*data.puint),
ABS_FREQ_MHz(double, (*data.puint), CFlop->Clock));
}
void RefreshTopFreq(TGrid *grid, DATA_TYPE data)
{
enum RATIO_BOOST boost = data.uint[0];
unsigned int top = Ruler.Top[boost];
unsigned int ratio = Shm->Cpu[top].Boost[boost];
struct FLIP_FLOP *CFlop = &Shm->Cpu[top] \
.FlipFlop[!Shm->Cpu[top].Toggle];
RefreshItemFreq(grid, ratio,
ABS_FREQ_MHz(double, ratio, CFlop->Clock));
}
void RefreshConfigTDP(TGrid *grid, DATA_TYPE data)
{
char item[11+11+1];
UNUSED(data);
StrFormat(item, 11+11+1, "%3d:%-3d",
Shm->Proc.Features.TDP_Cfg_Level,
Shm->Proc.Features.TDP_Levels);
memcpy(&grid->cell.item[grid->cell.length - 9], item, 7);
}
REASON_CODE SysInfoProc(Window *win, CUINT width, CELL_FUNC OutFunc)
{
REASON_INIT(reason);
ATTRIBUTE *attrib[4] = {
RSC(SYSINFO_PROC_COND0).ATTR(),
RSC(SYSINFO_PROC_COND1).ATTR(),
RSC(SYSINFO_PROC_COND2).ATTR(),
RSC(SYSINFO_PROC_COND3).ATTR()
};
struct FLIP_FLOP *CFlop;
unsigned int activeCores;
enum RATIO_BOOST boost = 0;
PUT( SCANKEY_NULL, attrib[0], width, 0,
"%s""%.*s[%s]", RSC(PROCESSOR).CODE(),
width - 2 - RSZ(PROCESSOR) - (int) strlen(Shm->Proc.Brand),
hSpace, Shm->Proc.Brand );
if (Shm->Proc.Features.Factory.PPIN > 0)
{
PUT( SCANKEY_NULL, attrib[0], width, 2,
"%s""%.*s[%16llx]", RSC(PPIN).CODE(),
width - 21 - RSZ(PPIN),
hSpace, Shm->Proc.Features.Factory.PPIN );
}
PUT( SCANKEY_NULL, attrib[0], width, 2,
"%s""%.*s[%s]", RSC(ARCHITECTURE).CODE(),
width - 5 - RSZ(ARCHITECTURE)
- (int) strlen(Shm->Proc.Architecture),
hSpace, Shm->Proc.Architecture );
PUT( SCANKEY_NULL, attrib[0], width, 2,
"%s""%.*s[%s]", RSC(VENDOR_ID).CODE(),
width - 5 - RSZ(VENDOR_ID)
- (int) strlen(Shm->Proc.Features.Info.Vendor.ID),
hSpace, Shm->Proc.Features.Info.Vendor.ID );
if (Shm->Proc.Features.Factory.SMU.Version > 0)
{
char version[17+1];
int len;
CONV(len, StrFormat, version, 17+1, "[%3u.%u.%u-%u]",
Shm->Proc.Features.Factory.SMU.Major,
Shm->Proc.Features.Factory.SMU.Minor,
Shm->Proc.Features.Factory.SMU.Revision,
Shm->Proc.Features.Factory.SMU.Interface);
PUT( SCANKEY_NULL, attrib[0], width, 2,
"%s""%.*s%s", RSC(FIRMWARE).CODE(),
width - 3 - RSZ(FIRMWARE) - len , hSpace, version );
}
PUT( SCANKEY_NULL, attrib[0], width, 2,
"%s""%.*s[0x%08x]", RSC(MICROCODE).CODE(),
width - 15 - RSZ(MICROCODE), hSpace,
Shm->Cpu[Shm->Proc.Service.Core].Query.Microcode );