From 8d3c6736e55960dcd5e5af0e174fb3135114fb40 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 2 Feb 2022 00:05:17 -0800 Subject: [PATCH 001/316] Drop LLVM_VERSION_SUFFIX --- llvm/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 957f9d96c985a..00d01f4ddbbd2 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -20,7 +20,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH) set(LLVM_VERSION_PATCH 0) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) - set(LLVM_VERSION_SUFFIX git) + set(LLVM_VERSION_SUFFIX) endif() if (NOT PACKAGE_VERSION) From e2cba651c40df5e8b550c8276de5e8755ddfbe9c Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 29 Jul 2021 23:38:24 +0000 Subject: [PATCH 002/316] Import workflows from release/13.x branch --- .github/workflows/clang-tests.yml | 49 ++++++ .github/workflows/libclang-abi-tests.yml | 158 +++++++++++++++++++ .github/workflows/libclc-tests.yml | 60 ++++++++ .github/workflows/lld-tests.yml | 49 ++++++ .github/workflows/lldb-tests.yml | 57 +++++++ .github/workflows/llvm-tests.yml | 185 +++++++++++++++++++++++ 6 files changed, 558 insertions(+) create mode 100644 .github/workflows/clang-tests.yml create mode 100644 .github/workflows/libclang-abi-tests.yml create mode 100644 .github/workflows/libclc-tests.yml create mode 100644 .github/workflows/lld-tests.yml create mode 100644 .github/workflows/lldb-tests.yml create mode 100644 .github/workflows/llvm-tests.yml diff --git a/.github/workflows/clang-tests.yml b/.github/workflows/clang-tests.yml new file mode 100644 index 0000000000000..71783e8ba8484 --- /dev/null +++ b/.github/workflows/clang-tests.yml @@ -0,0 +1,49 @@ +name: Clang Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'clang/**' + - 'llvm/**' + - '.github/workflows/clang-tests.yml' + pull_request: + paths: + - 'clang/**' + - 'llvm/**' + - '.github/workflows/clang-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + +jobs: + build_clang: + name: clang check-all + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + - windows-latest + - macOS-latest + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Test clang + uses: llvm/actions/build-test-llvm-project@main + with: + cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release + build_target: check-clang diff --git a/.github/workflows/libclang-abi-tests.yml b/.github/workflows/libclang-abi-tests.yml new file mode 100644 index 0000000000000..c533c2c2fa8e7 --- /dev/null +++ b/.github/workflows/libclang-abi-tests.yml @@ -0,0 +1,158 @@ +name: libclang ABI Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'clang/**' + - '.github/workflows/libclang-abi-tests.yml' + pull_request: + paths: + - 'clang/**' + - '.github/workflows/libclang-abi-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + + +jobs: + abi-dump-setup: + runs-on: ubuntu-latest + outputs: + BASELINE_REF: ${{ steps.vars.outputs.BASELINE_REF }} + ABI_HEADERS: ${{ steps.vars.outputs.ABI_HEADERS }} + ABI_LIBS: ${{ steps.vars.outputs.ABI_LIBS }} + BASELINE_VERSION_MAJOR: ${{ steps.vars.outputs.BASELINE_VERSION_MAJOR }} + BASELINE_VERSION_MINOR: ${{ steps.vars.outputs.BASELINE_VERSION_MINOR }} + LLVM_VERSION_MAJOR: ${{ steps.version.outputs.LLVM_VERSION_MAJOR }} + LLVM_VERSION_MINOR: ${{ steps.version.outputs.LLVM_VERSION_MINOR }} + LLVM_VERSION_PATCH: ${{ steps.version.outputs.LLVM_VERSION_PATCH }} + steps: + - name: Checkout source + uses: actions/checkout@v1 + with: + fetch-depth: 250 + + - name: Get LLVM version + id: version + uses: llvm/actions/get-llvm-version@main + + - name: Setup Variables + id: vars + run: | + minor_version=0 + remote_repo='https://github.com/llvm/llvm-project' + if [ ${{ steps.version.outputs.LLVM_VERSION_MINOR }} -ne 0 -o ${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then + major_version=$(( ${{ steps.version.outputs.LLVM_VERSION_MAJOR }} - 1)) + baseline_ref="llvmorg-$major_version.0.0" + + # If there is a minor release, we want to use that as the base line. + minor_ref=`git ls-remote --refs -t $remote_repo llvmorg-$major_version.[1-9].[0-9] | tail -n1 | grep -o 'llvmorg-.\+' || true` + if [ -n "$minor_ref" ]; then + baseline_ref=$minor_ref + else + # Check if we have a release candidate + rc_ref=`git ls-remote --refs -t $remote_repo llvmorg-$major_version.[1-9].[0-9]-rc* | tail -n1 | grep -o 'llvmorg-.\+' || true` + if [ -n "$rc_ref" ]; then + baseline_ref=$rc_ref + fi + fi + echo ::set-output name=BASELINE_VERSION_MAJOR::$major_version + echo ::set-output name=BASELINE_REF::$baseline_ref + echo ::set-output name=ABI_HEADERS::clang-c + echo ::set-output name=ABI_LIBS::libclang.so + else + echo ::set-output name=BASELINE_VERSION_MAJOR::${{ steps.version.outputs.LLVM_VERSION_MAJOR }} + echo ::set-output name=BASELINE_REF::llvmorg-${{ steps.version.outputs.LLVM_VERSION_MAJOR }}.0.0 + echo ::set-output name=ABI_HEADERS::. + echo ::set-output name=ABI_LIBS::libclang.so libclang-cpp.so + fi + + + abi-dump: + needs: abi-dump-setup + runs-on: ubuntu-latest + strategy: + matrix: + name: + - build-baseline + - build-latest + include: + - name: build-baseline + llvm_version_major: ${{ needs.abi-dump-setup.outputs.BASELINE_VERSION_MAJOR }} + ref: ${{ needs.abi-dump-setup.outputs.BASELINE_REF }} + repo: llvm/llvm-project + - name: build-latest + llvm_version_major: ${{ needs.abi-dump-setup.outputs.LLVM_VERSION_MAJOR }} + ref: ${{ github.sha }} + repo: ${{ github.repository }} + steps: + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - name: Install abi-compliance-checker + run: | + sudo apt-get install abi-dumper autoconf pkg-config + - name: Install universal-ctags + run: | + git clone https://github.com/universal-ctags/ctags.git + cd ctags + ./autogen.sh + ./configure + sudo make install + - name: Download source code + uses: llvm/actions/get-llvm-project-src@main + with: + ref: ${{ matrix.ref }} + repo: ${{ matrix.repo }} + - name: Configure + run: | + mkdir install + cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX=`pwd`/install llvm + - name: Build + run: ninja -C build/ ${{ needs.abi-dump-setup.outputs.ABI_LIBS }} install-clang-headers + - name: Dump ABI + run: | + parallel abi-dumper -lver ${{ matrix.ref }} -skip-cxx -public-headers ./install/include/${{ needs.abi-dump-setup.outputs.ABI_HEADERS }} -o {}-${{ matrix.ref }}.abi ./build/lib/{} ::: ${{ needs.abi-dump-setup.outputs.ABI_LIBS }} + for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do + # Remove symbol versioning from dumps, so we can compare across major versions. + sed -i 's/LLVM_${{ matrix.llvm_version_major }}/LLVM_NOVERSION/' $lib-${{ matrix.ref }}.abi + done + - name: Upload ABI file + uses: actions/upload-artifact@v2 + with: + name: ${{ matrix.name }} + path: "*${{ matrix.ref }}.abi" + + abi-compare: + runs-on: ubuntu-latest + needs: + - abi-dump-setup + - abi-dump + steps: + - name: Download baseline + uses: actions/download-artifact@v1 + with: + name: build-baseline + - name: Download latest + uses: actions/download-artifact@v1 + with: + name: build-latest + + - name: Install abi-compliance-checker + run: sudo apt-get install abi-compliance-checker + - name: Compare ABI + run: | + for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do + abi-compliance-checker -lib $lib -old build-baseline/$lib*.abi -new build-latest/$lib*.abi + done + - name: Upload ABI Comparison + if: always() + uses: actions/upload-artifact@v2 + with: + name: compat-report-${{ github.sha }} + path: compat_reports/ + diff --git a/.github/workflows/libclc-tests.yml b/.github/workflows/libclc-tests.yml new file mode 100644 index 0000000000000..d4dbbc6bc6a02 --- /dev/null +++ b/.github/workflows/libclc-tests.yml @@ -0,0 +1,60 @@ +name: libclc Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'clang/**' + - 'llvm/**' + - 'libclc/**' + - '.github/workflows/libclc-tests.yml' + pull_request: + paths: + - 'clang/**' + - 'llvm/**' + - 'libclc/**' + - '.github/workflows/libclc-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + + +jobs: + build_libclc: + name: libclc test + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + # Disable build on windows, because I can't figure out where llvm-config is. + #- windows-latest + - macOS-latest + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Build clang + uses: llvm/actions/build-test-llvm-project@main + with: + cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release + build_target: "" + - name: Build and test libclc + # spirv targets require llvm-spirv, so skip building them until we figure out + # how to install this tool. + run: | + cmake -G Ninja -S libclc -B libclc-build -DLLVM_CONFIG=`pwd`/build/bin/llvm-config -DLIBCLC_TARGETS_TO_BUILD="amdgcn--;amdgcn--amdhsa;r600--;nvptx--;nvptx64--;nvptx--nvidiacl;nvptx64--nvidiacl" + ninja -C libclc-build + ninja -C libclc-build test diff --git a/.github/workflows/lld-tests.yml b/.github/workflows/lld-tests.yml new file mode 100644 index 0000000000000..5cbcfcf515abb --- /dev/null +++ b/.github/workflows/lld-tests.yml @@ -0,0 +1,49 @@ +name: LLD Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'lld/**' + - 'llvm/**' + - '.github/workflows/lld-tests.yml' + pull_request: + paths: + - 'lld/**' + - 'llvm/**' + - '.github/workflows/lld-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + +jobs: + build_lld: + name: lld check-all + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + - windows-latest + - macOS-latest + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Test lld + uses: llvm/actions/build-test-llvm-project@main + with: + cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="lld" -DCMAKE_BUILD_TYPE=Release + build_target: check-lld diff --git a/.github/workflows/lldb-tests.yml b/.github/workflows/lldb-tests.yml new file mode 100644 index 0000000000000..761a5788ac99f --- /dev/null +++ b/.github/workflows/lldb-tests.yml @@ -0,0 +1,57 @@ +name: lldb Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'clang/**' + - 'llvm/**' + - 'lldb/**' + - '.github/workflows/lldb-tests.yml' + pull_request: + paths: + - 'clang/**' + - 'llvm/**' + - 'lldb/**' + - '.github/workflows/lldb-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + + +jobs: + build_lldb: + name: lldb build + runs-on: ${{ matrix.os }} + # Workaround for build faliure on Mac OS X: llvm.org/PR46190, https://github.com/actions/virtual-environments/issues/2274 + env: + CPLUS_INCLUDE_PATH: /usr/local/opt/llvm/include/c++/v1:/Library/Developer/CommandLineTools/SDKs/MacOSX10.15.sdk/usr/include + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + - windows-latest + - macOS-10.15 + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Build lldb + uses: llvm/actions/build-test-llvm-project@main + with: + # Mac OS requries that libcxx is enabled for lldb tests, so we need to disable them. + cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang;lldb" -DCMAKE_BUILD_TYPE=Release -DLLDB_INCLUDE_TESTS=OFF + # check-lldb is not consistent, so we only build lldb. + build_target: "" diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml new file mode 100644 index 0000000000000..2fc44e9599367 --- /dev/null +++ b/.github/workflows/llvm-tests.yml @@ -0,0 +1,185 @@ +name: LLVM Tests + +on: + push: + branches: + - 'release/**' + paths: + - 'llvm/**' + - '.github/workflows/llvm-tests.yml' + pull_request: + paths: + - 'llvm/**' + - '.github/workflows/llvm-tests.yml' + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + + +jobs: + build_llvm: + name: llvm check-all + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + - windows-latest + - macOS-latest + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Test llvm + uses: llvm/actions/build-test-llvm-project@main + with: + cmake_args: -G Ninja -DCMAKE_BUILD_TYPE=Release + + abi-dump-setup: + runs-on: ubuntu-latest + outputs: + BASELINE_REF: ${{ steps.vars.outputs.BASELINE_REF }} + ABI_HEADERS: ${{ steps.vars.outputs.ABI_HEADERS }} + BASELINE_VERSION_MAJOR: ${{ steps.vars.outputs.BASELINE_VERSION_MAJOR }} + LLVM_VERSION_MAJOR: ${{ steps.version.outputs.LLVM_VERSION_MAJOR }} + LLVM_VERSION_MINOR: ${{ steps.version.outputs.LLVM_VERSION_MINOR }} + LLVM_VERSION_PATCH: ${{ steps.version.outputs.LLVM_VERSION_PATCH }} + steps: + - name: Checkout source + uses: actions/checkout@v1 + with: + fetch-depth: 250 + + - name: Get LLVM version + id: version + uses: llvm/actions/get-llvm-version@main + + - name: Setup Variables + id: vars + run: | + if [ ${{ steps.version.outputs.LLVM_VERSION_MINOR }} -ne 0 -o ${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then + echo ::set-output name=BASELINE_VERSION_MAJOR::$(( ${{ steps.version.outputs.LLVM_VERSION_MAJOR }} - 1)) + echo ::set-output name=ABI_HEADERS::llvm-c + else + echo ::set-output name=BASELINE_VERSION_MAJOR::${{ steps.version.outputs.LLVM_VERSION_MAJOR }} + echo ::set-output name=ABI_HEADERS::. + fi + + abi-dump: + needs: abi-dump-setup + runs-on: ubuntu-latest + strategy: + matrix: + name: + - build-baseline + - build-latest + include: + - name: build-baseline + llvm_version_major: ${{ needs.abi-dump-setup.outputs.BASELINE_VERSION_MAJOR }} + ref: llvmorg-${{ needs.abi-dump-setup.outputs.BASELINE_VERSION_MAJOR }}.0.0 + repo: llvm/llvm-project + - name: build-latest + llvm_version_major: ${{ needs.abi-dump-setup.outputs.LLVM_VERSION_MAJOR }} + ref: ${{ github.sha }} + repo: ${{ github.repository }} + steps: + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - name: Install abi-compliance-checker + run: | + sudo apt-get install abi-dumper autoconf pkg-config + - name: Install universal-ctags + run: | + git clone https://github.com/universal-ctags/ctags.git + cd ctags + ./autogen.sh + ./configure + sudo make install + - name: Download source code + uses: llvm/actions/get-llvm-project-src@main + with: + ref: ${{ matrix.ref }} + repo: ${{ matrix.repo }} + - name: Configure + run: | + mkdir install + cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX=`pwd`/install llvm + - name: Build + # Need to run install-LLVM twice to ensure the symlink is installed (this is a bug). + run: | + ninja -C build install-LLVM + ninja -C build install-LLVM + ninja -C build install-llvm-headers + - name: Dump ABI + run: | + if [ "${{ needs.abi-dump-setup.outputs.ABI_HEADERS }}" = "llvm-c" ]; then + nm ./install/lib/libLLVM.so | awk "/T _LLVM/ || /T LLVM/ { print $3 }" | sort -u | sed -e "s/^_//g" | cut -d ' ' -f 3 > llvm.symbols + # Even though the -symbols-list option doesn't seem to filter out the symbols, I believe it speeds up processing, so I'm leaving it in. + export EXTRA_ARGS="-symbols-list llvm.symbols" + else + touch llvm.symbols + fi + abi-dumper $EXTRA_ARGS -lver ${{ matrix.ref }} -skip-cxx -public-headers ./install/include/${{ needs.abi-dump-setup.outputs.ABI_HEADERS }} -o ${{ matrix.ref }}.abi ./install/lib/libLLVM.so + # Remove symbol versioning from dumps, so we can compare across major versions. + sed -i 's/LLVM_${{ matrix.llvm_version_major }}/LLVM_NOVERSION/' ${{ matrix.ref }}.abi + - name: Upload ABI file + uses: actions/upload-artifact@v1 + with: + name: ${{ matrix.name }} + path: ${{ matrix.ref }}.abi + + - name: Upload symbol list file + if: matrix.name == 'build-baseline' + uses: actions/upload-artifact@v1 + with: + name: symbol-list + path: llvm.symbols + + abi-compare: + runs-on: ubuntu-latest + needs: + - abi-dump-setup + - abi-dump + steps: + - name: Download baseline + uses: actions/download-artifact@v1 + with: + name: build-baseline + - name: Download latest + uses: actions/download-artifact@v1 + with: + name: build-latest + - name: Download symbol list + uses: actions/download-artifact@v1 + with: + name: symbol-list + + - name: Install abi-compliance-checker + run: sudo apt-get install abi-compliance-checker + - name: Compare ABI + run: | + if [ -s symbol-list/llvm.symbols ]; then + # This option doesn't seem to work with the ABI dumper, so passing it here. + export EXTRA_ARGS="-symbols-list symbol-list/llvm.symbols" + fi + # FIXME: Reading of gzip'd abi files on the GitHub runners stop + # working some time in March of 2021, likely due to a change in the + # runner's environment. + abi-compliance-checker $EXTRA_ARGS -l libLLVM.so -old build-baseline/*.abi -new build-latest/*.abi || test "${{ needs.abi-dump-setup.outputs.ABI_HEADERS }}" = "llvm-c" + - name: Upload ABI Comparison + if: always() + uses: actions/upload-artifact@v1 + with: + name: compat-report-${{ github.sha }} + path: compat_reports/ From 8891aab065487b9d88b6babb2a252f353085a760 Mon Sep 17 00:00:00 2001 From: Tobias Hieta Date: Wed, 2 Feb 2022 10:06:37 +0100 Subject: [PATCH 003/316] [compiler-rt][Darwin] Add arm64 to simulator platforms I was looking around and noticed that builtins for iossim, tvossim and watchossim was missing arm64 builds, while apple's clang toolchain ship with these. After a bit of searching around it just seems like these are not listed correctly in CMake to be enabled. I enabled just arm64 since I saw that Apple clang didn't include arm64e. Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D118759 (cherry picked from commit a8e5ce76b475a22546090a73c22fa4f83529aa4e) --- compiler-rt/cmake/builtin-config-ix.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler-rt/cmake/builtin-config-ix.cmake b/compiler-rt/cmake/builtin-config-ix.cmake index b20730c2f25dd..c422ad45ed04e 100644 --- a/compiler-rt/cmake/builtin-config-ix.cmake +++ b/compiler-rt/cmake/builtin-config-ix.cmake @@ -115,7 +115,7 @@ if(APPLE) set(DARWIN_ios_BUILTIN_MIN_VER_FLAG ${DARWIN_ios_MIN_VER_FLAG}=${DARWIN_ios_BUILTIN_MIN_VER}) set(DARWIN_ios_BUILTIN_ALL_POSSIBLE_ARCHS ${ARM64} ${ARM32}) - set(DARWIN_iossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86} ${X86_64}) + set(DARWIN_iossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86} ${X86_64} arm64) endif() if(COMPILER_RT_ENABLE_WATCHOS) list(APPEND DARWIN_EMBEDDED_PLATFORMS watchos) @@ -124,7 +124,7 @@ if(APPLE) set(DARWIN_watchos_BUILTIN_MIN_VER_FLAG ${DARWIN_watchos_MIN_VER_FLAG}=${DARWIN_watchos_BUILTIN_MIN_VER}) set(DARWIN_watchos_BUILTIN_ALL_POSSIBLE_ARCHS armv7 armv7k arm64_32) - set(DARWIN_watchossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86}) + set(DARWIN_watchossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86} arm64) endif() if(COMPILER_RT_ENABLE_TVOS) list(APPEND DARWIN_EMBEDDED_PLATFORMS tvos) @@ -133,7 +133,7 @@ if(APPLE) set(DARWIN_tvos_BUILTIN_MIN_VER_FLAG ${DARWIN_tvos_MIN_VER_FLAG}=${DARWIN_tvos_BUILTIN_MIN_VER}) set(DARWIN_tvos_BUILTIN_ALL_POSSIBLE_ARCHS armv7 arm64) - set(DARWIN_tvossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86} ${X86_64}) + set(DARWIN_tvossim_BUILTIN_ALL_POSSIBLE_ARCHS ${X86} ${X86_64} arm64) endif() set(BUILTIN_SUPPORTED_OS osx) From e3c2861a2daa668414a59bf79339aeb95a91044d Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 1 Feb 2022 16:32:39 -0500 Subject: [PATCH 004/316] [libc++] Add CI without experimental features and don't exclude span from the tests There is no reason for the parts of std::span that don't depend on ranges to be disabled when ranges aren't provided. Also, to make sure the "no-experimental-stuff" configuration is tested, add a CI job for it. Differential Revision: https://reviews.llvm.org/D118740 (cherry picked from commit 99ae4582318a47ba4396b97f9764b2a111279eab) --- libcxx/cmake/caches/Generic-no-experimental.cmake | 2 ++ .../std/containers/views/span.cons/assign.pass.cpp | 1 - .../std/containers/views/span.cons/copy.pass.cpp | 1 - .../std/containers/views/span.cons/deduct.pass.cpp | 1 - .../views/span.cons/initializer_list.pass.cpp | 1 - .../views/span.cons/iterator_len.pass.cpp | 1 - .../views/span.cons/iterator_len.verify.cpp | 1 - .../views/span.cons/iterator_sentinel.pass.cpp | 1 - .../views/span.cons/iterator_sentinel.verify.cpp | 1 - .../std/containers/views/span.elem/back.pass.cpp | 1 - .../std/containers/views/span.elem/data.pass.cpp | 1 - .../std/containers/views/span.elem/front.pass.cpp | 1 - .../std/containers/views/span.elem/op_idx.pass.cpp | 1 - .../containers/views/span.iterators/begin.pass.cpp | 1 - .../containers/views/span.iterators/end.pass.cpp | 1 - .../containers/views/span.iterators/rbegin.pass.cpp | 1 - .../containers/views/span.iterators/rend.pass.cpp | 1 - .../views/span.objectrep/as_bytes.pass.cpp | 1 - .../views/span.objectrep/as_writable_bytes.fail.cpp | 1 - .../views/span.objectrep/as_writable_bytes.pass.cpp | 1 - .../views/span.obs/empty.nodiscard.verify.cpp | 1 - .../std/containers/views/span.obs/empty.pass.cpp | 1 - .../std/containers/views/span.obs/size.pass.cpp | 1 - .../containers/views/span.obs/size_bytes.pass.cpp | 1 - .../std/containers/views/span.sub/first.fail.cpp | 1 - .../std/containers/views/span.sub/first.pass.cpp | 1 - .../std/containers/views/span.sub/last.fail.cpp | 1 - .../std/containers/views/span.sub/last.pass.cpp | 1 - .../std/containers/views/span.sub/subspan.fail.cpp | 1 - .../std/containers/views/span.sub/subspan.pass.cpp | 1 - libcxx/utils/ci/buildkite-pipeline.yml | 13 +++++++++++++ libcxx/utils/ci/run-buildbot | 7 +++++++ 32 files changed, 22 insertions(+), 29 deletions(-) create mode 100644 libcxx/cmake/caches/Generic-no-experimental.cmake diff --git a/libcxx/cmake/caches/Generic-no-experimental.cmake b/libcxx/cmake/caches/Generic-no-experimental.cmake new file mode 100644 index 0000000000000..0f055f4a98e07 --- /dev/null +++ b/libcxx/cmake/caches/Generic-no-experimental.cmake @@ -0,0 +1,2 @@ +set(LIBCXX_ENABLE_EXPERIMENTAL_LIBRARY OFF CACHE BOOL "") +set(LIBCXX_ENABLE_INCOMPLETE_FEATURES OFF CACHE BOOL "") diff --git a/libcxx/test/std/containers/views/span.cons/assign.pass.cpp b/libcxx/test/std/containers/views/span.cons/assign.pass.cpp index 74588dfe565b0..4fa2184113ba8 100644 --- a/libcxx/test/std/containers/views/span.cons/assign.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/assign.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/copy.pass.cpp b/libcxx/test/std/containers/views/span.cons/copy.pass.cpp index 1ac7c181815ba..064680ecfe2d2 100644 --- a/libcxx/test/std/containers/views/span.cons/copy.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/copy.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp index 702ec487b0f18..e20c1811a7ffa 100644 --- a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/containers/views/span.cons/initializer_list.pass.cpp b/libcxx/test/std/containers/views/span.cons/initializer_list.pass.cpp index 9ca751e6c3c6d..916df32603aa7 100644 --- a/libcxx/test/std/containers/views/span.cons/initializer_list.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/initializer_list.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/iterator_len.pass.cpp b/libcxx/test/std/containers/views/span.cons/iterator_len.pass.cpp index 6670a213e7bb1..a9ed3f188b393 100644 --- a/libcxx/test/std/containers/views/span.cons/iterator_len.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/iterator_len.pass.cpp @@ -6,7 +6,6 @@ // //===---------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/iterator_len.verify.cpp b/libcxx/test/std/containers/views/span.cons/iterator_len.verify.cpp index 1ee4cc3d494d3..81a47a96f02f6 100644 --- a/libcxx/test/std/containers/views/span.cons/iterator_len.verify.cpp +++ b/libcxx/test/std/containers/views/span.cons/iterator_len.verify.cpp @@ -6,7 +6,6 @@ // //===---------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/iterator_sentinel.pass.cpp b/libcxx/test/std/containers/views/span.cons/iterator_sentinel.pass.cpp index 8fb9a75bf44db..49759b2f2ae05 100644 --- a/libcxx/test/std/containers/views/span.cons/iterator_sentinel.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/iterator_sentinel.pass.cpp @@ -6,7 +6,6 @@ // //===---------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.cons/iterator_sentinel.verify.cpp b/libcxx/test/std/containers/views/span.cons/iterator_sentinel.verify.cpp index 986e07612d018..d84c7c06edbc5 100644 --- a/libcxx/test/std/containers/views/span.cons/iterator_sentinel.verify.cpp +++ b/libcxx/test/std/containers/views/span.cons/iterator_sentinel.verify.cpp @@ -6,7 +6,6 @@ // //===---------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.elem/back.pass.cpp b/libcxx/test/std/containers/views/span.elem/back.pass.cpp index 9d4fbc9fdd8e4..497e8e4a19011 100644 --- a/libcxx/test/std/containers/views/span.elem/back.pass.cpp +++ b/libcxx/test/std/containers/views/span.elem/back.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.elem/data.pass.cpp b/libcxx/test/std/containers/views/span.elem/data.pass.cpp index 8c5422421823f..fd6e2b3c5bdfe 100644 --- a/libcxx/test/std/containers/views/span.elem/data.pass.cpp +++ b/libcxx/test/std/containers/views/span.elem/data.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.elem/front.pass.cpp b/libcxx/test/std/containers/views/span.elem/front.pass.cpp index d4e89f133c36a..135168eec3170 100644 --- a/libcxx/test/std/containers/views/span.elem/front.pass.cpp +++ b/libcxx/test/std/containers/views/span.elem/front.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.elem/op_idx.pass.cpp b/libcxx/test/std/containers/views/span.elem/op_idx.pass.cpp index 2c1218cb9ace0..8c324d04f6d99 100644 --- a/libcxx/test/std/containers/views/span.elem/op_idx.pass.cpp +++ b/libcxx/test/std/containers/views/span.elem/op_idx.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.iterators/begin.pass.cpp b/libcxx/test/std/containers/views/span.iterators/begin.pass.cpp index 0e6f236c5edd4..212b4284b8952 100644 --- a/libcxx/test/std/containers/views/span.iterators/begin.pass.cpp +++ b/libcxx/test/std/containers/views/span.iterators/begin.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.iterators/end.pass.cpp b/libcxx/test/std/containers/views/span.iterators/end.pass.cpp index bb71bdd717037..ef8370d87aefd 100644 --- a/libcxx/test/std/containers/views/span.iterators/end.pass.cpp +++ b/libcxx/test/std/containers/views/span.iterators/end.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.iterators/rbegin.pass.cpp b/libcxx/test/std/containers/views/span.iterators/rbegin.pass.cpp index bd1c3088e659c..b5ce5a9290f0e 100644 --- a/libcxx/test/std/containers/views/span.iterators/rbegin.pass.cpp +++ b/libcxx/test/std/containers/views/span.iterators/rbegin.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.iterators/rend.pass.cpp b/libcxx/test/std/containers/views/span.iterators/rend.pass.cpp index 6b57974e2a003..b71019ac20d67 100644 --- a/libcxx/test/std/containers/views/span.iterators/rend.pass.cpp +++ b/libcxx/test/std/containers/views/span.iterators/rend.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.objectrep/as_bytes.pass.cpp b/libcxx/test/std/containers/views/span.objectrep/as_bytes.pass.cpp index d2c44f3ddb00c..4d2b8db3ea815 100644 --- a/libcxx/test/std/containers/views/span.objectrep/as_bytes.pass.cpp +++ b/libcxx/test/std/containers/views/span.objectrep/as_bytes.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.fail.cpp b/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.fail.cpp index 9dcebf4018efe..a9852086859ac 100644 --- a/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.fail.cpp +++ b/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.fail.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.pass.cpp b/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.pass.cpp index 7f47ffd71fbe6..3b68e1542c049 100644 --- a/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.pass.cpp +++ b/libcxx/test/std/containers/views/span.objectrep/as_writable_bytes.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.obs/empty.nodiscard.verify.cpp b/libcxx/test/std/containers/views/span.obs/empty.nodiscard.verify.cpp index a6cb4792b92b7..8efc4b4a34404 100644 --- a/libcxx/test/std/containers/views/span.obs/empty.nodiscard.verify.cpp +++ b/libcxx/test/std/containers/views/span.obs/empty.nodiscard.verify.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/containers/views/span.obs/empty.pass.cpp b/libcxx/test/std/containers/views/span.obs/empty.pass.cpp index 5a86aaea607c2..24129d4e7d56d 100644 --- a/libcxx/test/std/containers/views/span.obs/empty.pass.cpp +++ b/libcxx/test/std/containers/views/span.obs/empty.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.obs/size.pass.cpp b/libcxx/test/std/containers/views/span.obs/size.pass.cpp index ffb28e6f76b4e..18ee056449434 100644 --- a/libcxx/test/std/containers/views/span.obs/size.pass.cpp +++ b/libcxx/test/std/containers/views/span.obs/size.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.obs/size_bytes.pass.cpp b/libcxx/test/std/containers/views/span.obs/size_bytes.pass.cpp index 4f5402188af9e..e798e02460e45 100644 --- a/libcxx/test/std/containers/views/span.obs/size_bytes.pass.cpp +++ b/libcxx/test/std/containers/views/span.obs/size_bytes.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/first.fail.cpp b/libcxx/test/std/containers/views/span.sub/first.fail.cpp index b7c8d0643b433..8db6934c2fd4c 100644 --- a/libcxx/test/std/containers/views/span.sub/first.fail.cpp +++ b/libcxx/test/std/containers/views/span.sub/first.fail.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/first.pass.cpp b/libcxx/test/std/containers/views/span.sub/first.pass.cpp index 43134723210ac..0bebc8af57108 100644 --- a/libcxx/test/std/containers/views/span.sub/first.pass.cpp +++ b/libcxx/test/std/containers/views/span.sub/first.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/last.fail.cpp b/libcxx/test/std/containers/views/span.sub/last.fail.cpp index 44c61f8cc5e46..24bcdf4c4886a 100644 --- a/libcxx/test/std/containers/views/span.sub/last.fail.cpp +++ b/libcxx/test/std/containers/views/span.sub/last.fail.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/last.pass.cpp b/libcxx/test/std/containers/views/span.sub/last.pass.cpp index dd599a44e3136..2859bdfda1bc2 100644 --- a/libcxx/test/std/containers/views/span.sub/last.pass.cpp +++ b/libcxx/test/std/containers/views/span.sub/last.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/subspan.fail.cpp b/libcxx/test/std/containers/views/span.sub/subspan.fail.cpp index 96595ef581812..5f1d0b6359e43 100644 --- a/libcxx/test/std/containers/views/span.sub/subspan.fail.cpp +++ b/libcxx/test/std/containers/views/span.sub/subspan.fail.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/test/std/containers/views/span.sub/subspan.pass.cpp b/libcxx/test/std/containers/views/span.sub/subspan.pass.cpp index c88022b1ee858..b4475000217b8 100644 --- a/libcxx/test/std/containers/views/span.sub/subspan.pass.cpp +++ b/libcxx/test/std/containers/views/span.sub/subspan.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // AppleClang 12.0.0 doesn't fully support ranges/concepts // XFAIL: apple-clang-12.0.0 diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml index f72d26d53452a..c5c56bb997dfd 100644 --- a/libcxx/utils/ci/buildkite-pipeline.yml +++ b/libcxx/utils/ci/buildkite-pipeline.yml @@ -465,6 +465,19 @@ steps: limit: 2 timeout_in_minutes: 120 + - label: "No experimental features" + command: "libcxx/utils/ci/run-buildbot generic-no-experimental" + artifact_paths: + - "**/test-results.xml" + agents: + queue: "libcxx-builders" + os: "linux" + retry: + automatic: + - exit_status: -1 # Agent was lost + limit: 2 + timeout_in_minutes: 120 + # Other non-testing CI jobs - label: "Benchmarks" command: "libcxx/utils/ci/run-buildbot benchmarks" diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot index f27979dcb5787..bb4c8fd48c61d 100755 --- a/libcxx/utils/ci/run-buildbot +++ b/libcxx/utils/ci/run-buildbot @@ -390,6 +390,13 @@ generic-no-wide-characters) -DLIBUNWIND_TEST_CONFIG="llvm-libunwind-shared.cfg.in" check-runtimes ;; +generic-no-experimental) + clean + generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-no-experimental.cmake" \ + -DLIBCXX_TEST_CONFIG="llvm-libc++-shared.cfg.in" \ + -DLIBUNWIND_TEST_CONFIG="llvm-libunwind-shared.cfg.in" + check-runtimes +;; apple-system) clean From c7463a90789c9a0024a3142e059e2db90dae2075 Mon Sep 17 00:00:00 2001 From: Arthur O'Dwyer Date: Tue, 1 Feb 2022 19:59:37 -0500 Subject: [PATCH 005/316] [libc++] [NFC] s/_LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS)/!defined(_LIBCPP_HAS_NO_CONCEPTS)/ Per Discord discussion, we're normalizing on a simple `!defined(_LIBCPP_HAS_NO_CONCEPTS)` so that we can do a big search-and-replace for `!defined(_LIBCPP_HAS_NO_CONCEPTS)` back into `_LIBCPP_STD_VER > 17` when we're ready to abandon support for concept-syntax-less compilers. Differential Revision: https://reviews.llvm.org/D118748 (cherry picked from commit 38db42d0043e501cbbb07ba6fa57597e6473fc3e) --- libcxx/include/__compare/compare_partial_order_fallback.h | 4 ++-- libcxx/include/__compare/compare_strong_order_fallback.h | 4 ++-- libcxx/include/__compare/compare_three_way.h | 4 ++-- libcxx/include/__compare/compare_weak_order_fallback.h | 4 ++-- libcxx/include/__compare/partial_order.h | 4 ++-- libcxx/include/__compare/strong_order.h | 4 ++-- libcxx/include/__compare/synth_three_way.h | 4 ++-- libcxx/include/__compare/three_way_comparable.h | 4 ++-- libcxx/include/__compare/weak_order.h | 4 ++-- libcxx/include/__concepts/arithmetic.h | 4 ++-- libcxx/include/__concepts/assignable.h | 4 ++-- libcxx/include/__concepts/boolean_testable.h | 4 ++-- libcxx/include/__concepts/class_or_enum.h | 4 ++-- libcxx/include/__concepts/common_reference_with.h | 4 ++-- libcxx/include/__concepts/common_with.h | 4 ++-- libcxx/include/__concepts/constructible.h | 4 ++-- libcxx/include/__concepts/convertible_to.h | 4 ++-- libcxx/include/__concepts/copyable.h | 4 ++-- libcxx/include/__concepts/derived_from.h | 4 ++-- libcxx/include/__concepts/destructible.h | 4 ++-- libcxx/include/__concepts/different_from.h | 4 ++-- libcxx/include/__concepts/equality_comparable.h | 4 ++-- libcxx/include/__concepts/invocable.h | 4 ++-- libcxx/include/__concepts/movable.h | 4 ++-- libcxx/include/__concepts/predicate.h | 4 ++-- libcxx/include/__concepts/regular.h | 4 ++-- libcxx/include/__concepts/relation.h | 4 ++-- libcxx/include/__concepts/same_as.h | 4 ++-- libcxx/include/__concepts/semiregular.h | 4 ++-- libcxx/include/__concepts/swappable.h | 4 ++-- libcxx/include/__concepts/totally_ordered.h | 4 ++-- libcxx/include/__iterator/distance.h | 4 ++-- libcxx/include/__iterator/insert_iterator.h | 2 +- libcxx/include/__iterator/reverse_iterator.h | 2 +- libcxx/include/__random/uniform_random_bit_generator.h | 4 ++-- libcxx/include/__ranges/enable_borrowed_range.h | 4 ++-- libcxx/include/__ranges/non_propagating_cache.h | 2 +- libcxx/include/__utility/cmp.h | 2 +- libcxx/include/__utility/pair.h | 6 +++--- libcxx/include/numbers | 4 ++-- libcxx/include/ranges | 4 ++-- libcxx/include/string_view | 8 ++++---- libcxx/include/tuple | 6 +++--- libcxx/include/type_traits | 4 ++-- 44 files changed, 88 insertions(+), 88 deletions(-) diff --git a/libcxx/include/__compare/compare_partial_order_fallback.h b/libcxx/include/__compare/compare_partial_order_fallback.h index 895523b38fb34..64937eaf37dd5 100644 --- a/libcxx/include/__compare/compare_partial_order_fallback.h +++ b/libcxx/include/__compare/compare_partial_order_fallback.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __compare_partial_order_fallback { @@ -66,7 +66,7 @@ inline namespace __cpo { inline constexpr auto compare_partial_order_fallback = __compare_partial_order_fallback::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/compare_strong_order_fallback.h b/libcxx/include/__compare/compare_strong_order_fallback.h index 5fee7b4780684..b7abef26e9d2e 100644 --- a/libcxx/include/__compare/compare_strong_order_fallback.h +++ b/libcxx/include/__compare/compare_strong_order_fallback.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __compare_strong_order_fallback { @@ -63,7 +63,7 @@ inline namespace __cpo { inline constexpr auto compare_strong_order_fallback = __compare_strong_order_fallback::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/compare_three_way.h b/libcxx/include/__compare/compare_three_way.h index d7f339eda992b..ddd37890a467c 100644 --- a/libcxx/include/__compare/compare_three_way.h +++ b/libcxx/include/__compare/compare_three_way.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) struct _LIBCPP_TEMPLATE_VIS compare_three_way { @@ -34,7 +34,7 @@ struct _LIBCPP_TEMPLATE_VIS compare_three_way using is_transparent = void; }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/compare_weak_order_fallback.h b/libcxx/include/__compare/compare_weak_order_fallback.h index 0abd4f2dfbee4..5a1807e697175 100644 --- a/libcxx/include/__compare/compare_weak_order_fallback.h +++ b/libcxx/include/__compare/compare_weak_order_fallback.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __compare_weak_order_fallback { @@ -63,7 +63,7 @@ inline namespace __cpo { inline constexpr auto compare_weak_order_fallback = __compare_weak_order_fallback::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/partial_order.h b/libcxx/include/__compare/partial_order.h index ac8b405a40903..cbadfcde73964 100644 --- a/libcxx/include/__compare/partial_order.h +++ b/libcxx/include/__compare/partial_order.h @@ -23,7 +23,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __partial_order { @@ -64,7 +64,7 @@ inline namespace __cpo { inline constexpr auto partial_order = __partial_order::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/strong_order.h b/libcxx/include/__compare/strong_order.h index 42f060387d595..a0dc077047f53 100644 --- a/libcxx/include/__compare/strong_order.h +++ b/libcxx/include/__compare/strong_order.h @@ -29,7 +29,7 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __strong_order { @@ -127,7 +127,7 @@ inline namespace __cpo { inline constexpr auto strong_order = __strong_order::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/synth_three_way.h b/libcxx/include/__compare/synth_three_way.h index 0f302c0fa11ff..b93d4932c57f6 100644 --- a/libcxx/include/__compare/synth_three_way.h +++ b/libcxx/include/__compare/synth_three_way.h @@ -21,7 +21,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [expos.only.func] @@ -44,7 +44,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr auto __synth_three_way = template using __synth_three_way_result = decltype(__synth_three_way(declval<_Tp&>(), declval<_Up&>())); -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/three_way_comparable.h b/libcxx/include/__compare/three_way_comparable.h index c4794949007ba..548bf17f0feb3 100644 --- a/libcxx/include/__compare/three_way_comparable.h +++ b/libcxx/include/__compare/three_way_comparable.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template concept __compares_as = @@ -51,7 +51,7 @@ concept three_way_comparable_with = { __u <=> __t } -> __compares_as<_Cat>; }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__compare/weak_order.h b/libcxx/include/__compare/weak_order.h index ce914b232108a..1286f39b020ca 100644 --- a/libcxx/include/__compare/weak_order.h +++ b/libcxx/include/__compare/weak_order.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [cmp.alg] namespace __weak_order { @@ -93,7 +93,7 @@ inline namespace __cpo { inline constexpr auto weak_order = __weak_order::__fn{}; } // namespace __cpo -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/arithmetic.h b/libcxx/include/__concepts/arithmetic.h index 9a1383904db62..c2f94239a6c39 100644 --- a/libcxx/include/__concepts/arithmetic.h +++ b/libcxx/include/__concepts/arithmetic.h @@ -18,7 +18,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concepts.arithmetic], arithmetic concepts @@ -41,7 +41,7 @@ concept __libcpp_unsigned_integer = __libcpp_is_unsigned_integer<_Tp>::value; template concept __libcpp_signed_integer = __libcpp_is_signed_integer<_Tp>::value; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/assignable.h b/libcxx/include/__concepts/assignable.h index 9cfc7c0e8318a..62f39f1c8cddd 100644 --- a/libcxx/include/__concepts/assignable.h +++ b/libcxx/include/__concepts/assignable.h @@ -21,7 +21,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.assignable] @@ -33,7 +33,7 @@ concept assignable_from = { __lhs = _VSTD::forward<_Rhs>(__rhs) } -> same_as<_Lhs>; }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/boolean_testable.h b/libcxx/include/__concepts/boolean_testable.h index 638fc3b20330c..c04c30429166a 100644 --- a/libcxx/include/__concepts/boolean_testable.h +++ b/libcxx/include/__concepts/boolean_testable.h @@ -19,7 +19,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concepts.booleantestable] @@ -31,7 +31,7 @@ concept __boolean_testable = __boolean_testable_impl<_Tp> && requires(_Tp&& __t) { !_VSTD::forward<_Tp>(__t) } -> __boolean_testable_impl; }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/class_or_enum.h b/libcxx/include/__concepts/class_or_enum.h index aa8606a219290..3d28a8ad984df 100644 --- a/libcxx/include/__concepts/class_or_enum.h +++ b/libcxx/include/__concepts/class_or_enum.h @@ -18,7 +18,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // Whether a type is a class type or enumeration type according to the Core wording. @@ -29,7 +29,7 @@ concept __class_or_enum = is_class_v<_Tp> || is_union_v<_Tp> || is_enum_v<_Tp>; template concept __workaround_52970 = is_class_v<__uncvref_t<_Tp>> || is_union_v<__uncvref_t<_Tp>>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/common_reference_with.h b/libcxx/include/__concepts/common_reference_with.h index 3269e3ae89fed..119d8fd8deed0 100644 --- a/libcxx/include/__concepts/common_reference_with.h +++ b/libcxx/include/__concepts/common_reference_with.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.commonref] @@ -30,7 +30,7 @@ concept common_reference_with = convertible_to<_Tp, common_reference_t<_Tp, _Up>> && convertible_to<_Up, common_reference_t<_Tp, _Up>>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/common_with.h b/libcxx/include/__concepts/common_with.h index b575aea5f77fc..ecaa23b63b228 100644 --- a/libcxx/include/__concepts/common_with.h +++ b/libcxx/include/__concepts/common_with.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.common] @@ -40,7 +40,7 @@ concept common_with = add_lvalue_reference_t, add_lvalue_reference_t>>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/constructible.h b/libcxx/include/__concepts/constructible.h index 9bba8118b8997..49986bb248d57 100644 --- a/libcxx/include/__concepts/constructible.h +++ b/libcxx/include/__concepts/constructible.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.constructible] template @@ -49,7 +49,7 @@ concept copy_constructible = constructible_from<_Tp, const _Tp&> && convertible_to && constructible_from<_Tp, const _Tp> && convertible_to; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/convertible_to.h b/libcxx/include/__concepts/convertible_to.h index 795b0bd7494ce..75f5da203c963 100644 --- a/libcxx/include/__concepts/convertible_to.h +++ b/libcxx/include/__concepts/convertible_to.h @@ -19,7 +19,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.convertible] @@ -30,7 +30,7 @@ concept convertible_to = static_cast<_To>(declval<_From>()); }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/copyable.h b/libcxx/include/__concepts/copyable.h index cfeeec86917e8..c264b31a21ca6 100644 --- a/libcxx/include/__concepts/copyable.h +++ b/libcxx/include/__concepts/copyable.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concepts.object] @@ -32,7 +32,7 @@ concept copyable = assignable_from<_Tp&, const _Tp&> && assignable_from<_Tp&, const _Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/derived_from.h b/libcxx/include/__concepts/derived_from.h index f7c83bf31fba0..acd4ba473cdd9 100644 --- a/libcxx/include/__concepts/derived_from.h +++ b/libcxx/include/__concepts/derived_from.h @@ -18,7 +18,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.derived] @@ -27,7 +27,7 @@ concept derived_from = is_base_of_v<_Bp, _Dp> && is_convertible_v; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/destructible.h b/libcxx/include/__concepts/destructible.h index 800ee2d56f048..d57824be9e19c 100644 --- a/libcxx/include/__concepts/destructible.h +++ b/libcxx/include/__concepts/destructible.h @@ -18,14 +18,14 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.destructible] template concept destructible = is_nothrow_destructible_v<_Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/different_from.h b/libcxx/include/__concepts/different_from.h index 5def31e652a51..c8560baf8af4c 100644 --- a/libcxx/include/__concepts/different_from.h +++ b/libcxx/include/__concepts/different_from.h @@ -19,12 +19,12 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template concept __different_from = !same_as, remove_cvref_t<_Up>>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/equality_comparable.h b/libcxx/include/__concepts/equality_comparable.h index 5df812c2600d3..064143b89443d 100644 --- a/libcxx/include/__concepts/equality_comparable.h +++ b/libcxx/include/__concepts/equality_comparable.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.equalitycomparable] @@ -46,7 +46,7 @@ concept equality_comparable_with = __make_const_lvalue_ref<_Up>>> && __weakly_equality_comparable_with<_Tp, _Up>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/invocable.h b/libcxx/include/__concepts/invocable.h index 0a8d9b7255ab5..e528258e35832 100644 --- a/libcxx/include/__concepts/invocable.h +++ b/libcxx/include/__concepts/invocable.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.invocable] @@ -34,7 +34,7 @@ concept invocable = requires(_Fn&& __fn, _Args&&... __args) { template concept regular_invocable = invocable<_Fn, _Args...>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/movable.h b/libcxx/include/__concepts/movable.h index dd0b8fb56d5b8..fd8c2e7fa20ec 100644 --- a/libcxx/include/__concepts/movable.h +++ b/libcxx/include/__concepts/movable.h @@ -21,7 +21,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concepts.object] @@ -32,7 +32,7 @@ concept movable = assignable_from<_Tp&, _Tp> && swappable<_Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/predicate.h b/libcxx/include/__concepts/predicate.h index 8e885406316db..491a7d6c73ea7 100644 --- a/libcxx/include/__concepts/predicate.h +++ b/libcxx/include/__concepts/predicate.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.predicate] @@ -28,7 +28,7 @@ template concept predicate = regular_invocable<_Fn, _Args...> && __boolean_testable>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/regular.h b/libcxx/include/__concepts/regular.h index d292e8d72dbe6..e8a87c97febf6 100644 --- a/libcxx/include/__concepts/regular.h +++ b/libcxx/include/__concepts/regular.h @@ -19,14 +19,14 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.object] template concept regular = semiregular<_Tp> && equality_comparable<_Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/relation.h b/libcxx/include/__concepts/relation.h index c6ff20d15195d..fa7e5d17df884 100644 --- a/libcxx/include/__concepts/relation.h +++ b/libcxx/include/__concepts/relation.h @@ -18,7 +18,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.relation] @@ -37,7 +37,7 @@ concept equivalence_relation = relation<_Rp, _Tp, _Up>; template concept strict_weak_order = relation<_Rp, _Tp, _Up>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/same_as.h b/libcxx/include/__concepts/same_as.h index 5a912b6f41c89..ee86c44ea35d2 100644 --- a/libcxx/include/__concepts/same_as.h +++ b/libcxx/include/__concepts/same_as.h @@ -18,7 +18,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.same] @@ -28,7 +28,7 @@ concept __same_as_impl = _IsSame<_Tp, _Up>::value; template concept same_as = __same_as_impl<_Tp, _Up> && __same_as_impl<_Up, _Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/semiregular.h b/libcxx/include/__concepts/semiregular.h index 4b96fe6dfba68..4797fc7eaa641 100644 --- a/libcxx/include/__concepts/semiregular.h +++ b/libcxx/include/__concepts/semiregular.h @@ -19,14 +19,14 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.object] template concept semiregular = copyable<_Tp> && default_initializable<_Tp>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/swappable.h b/libcxx/include/__concepts/swappable.h index d45249738535e..6b8cf82b70ef1 100644 --- a/libcxx/include/__concepts/swappable.h +++ b/libcxx/include/__concepts/swappable.h @@ -25,7 +25,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.swappable] @@ -109,7 +109,7 @@ concept swappable_with = ranges::swap(_VSTD::forward<_Up>(__u), _VSTD::forward<_Tp>(__t)); }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__concepts/totally_ordered.h b/libcxx/include/__concepts/totally_ordered.h index d8dd4a4944d07..58dcb42be5794 100644 --- a/libcxx/include/__concepts/totally_ordered.h +++ b/libcxx/include/__concepts/totally_ordered.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [concept.totallyordered] @@ -50,7 +50,7 @@ concept totally_ordered_with = __make_const_lvalue_ref<_Up>>> && __partially_ordered_with<_Tp, _Up>; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/distance.h b/libcxx/include/__iterator/distance.h index faab034923892..85309f8d47d6d 100644 --- a/libcxx/include/__iterator/distance.h +++ b/libcxx/include/__iterator/distance.h @@ -52,7 +52,7 @@ distance(_InputIter __first, _InputIter __last) return _VSTD::__distance(__first, __last, typename iterator_traits<_InputIter>::iterator_category()); } -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [range.iter.op.distance] @@ -100,7 +100,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/insert_iterator.h b/libcxx/include/__iterator/insert_iterator.h index 2f18f5f12162c..d3cd5ad6f9c50 100644 --- a/libcxx/include/__iterator/insert_iterator.h +++ b/libcxx/include/__iterator/insert_iterator.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template using __insert_iterator_iter_t = ranges::iterator_t<_Container>; #else diff --git a/libcxx/include/__iterator/reverse_iterator.h b/libcxx/include/__iterator/reverse_iterator.h index 449eb529aa983..af855a0a1e73b 100644 --- a/libcxx/include/__iterator/reverse_iterator.h +++ b/libcxx/include/__iterator/reverse_iterator.h @@ -184,7 +184,7 @@ operator<=(const reverse_iterator<_Iter1>& __x, const reverse_iterator<_Iter2>& return __x.base() >= __y.base(); } -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template _Iter2> _LIBCPP_HIDE_FROM_ABI constexpr compare_three_way_result_t<_Iter1, _Iter2> diff --git a/libcxx/include/__random/uniform_random_bit_generator.h b/libcxx/include/__random/uniform_random_bit_generator.h index 7b2f0df868d7b..8bcd20f423672 100644 --- a/libcxx/include/__random/uniform_random_bit_generator.h +++ b/libcxx/include/__random/uniform_random_bit_generator.h @@ -24,7 +24,7 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // [rand.req.urng] template @@ -36,7 +36,7 @@ concept uniform_random_bit_generator = requires bool_constant<(_Gen::min() < _Gen::max())>::value; }; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/enable_borrowed_range.h b/libcxx/include/__ranges/enable_borrowed_range.h index 5f5b3f505773c..f9985dfd0061b 100644 --- a/libcxx/include/__ranges/enable_borrowed_range.h +++ b/libcxx/include/__ranges/enable_borrowed_range.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) namespace ranges { @@ -34,7 +34,7 @@ inline constexpr bool enable_borrowed_range = false; } // namespace ranges -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/non_propagating_cache.h b/libcxx/include/__ranges/non_propagating_cache.h index d0f447ce7cc57..2d3a9408713e4 100644 --- a/libcxx/include/__ranges/non_propagating_cache.h +++ b/libcxx/include/__ranges/non_propagating_cache.h @@ -107,7 +107,7 @@ namespace ranges { struct __empty_cache { }; } // namespace ranges -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__utility/cmp.h b/libcxx/include/__utility/cmp.h index 4fc96b054f4d5..3889cc7492faa 100644 --- a/libcxx/include/__utility/cmp.h +++ b/libcxx/include/__utility/cmp.h @@ -24,7 +24,7 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template struct _IsSameAsAny : _Or<_IsSame<_Tp, _Up>...> {}; diff --git a/libcxx/include/__utility/pair.h b/libcxx/include/__utility/pair.h index f1114696884ac..82e82eabf8328 100644 --- a/libcxx/include/__utility/pair.h +++ b/libcxx/include/__utility/pair.h @@ -330,7 +330,7 @@ operator==(const pair<_T1,_T2>& __x, const pair<_T1,_T2>& __y) return __x.first == __y.first && __x.second == __y.second; } -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template _LIBCPP_HIDE_FROM_ABI constexpr @@ -345,7 +345,7 @@ operator<=>(const pair<_T1,_T2>& __x, const pair<_T1,_T2>& __y) return _VSTD::__synth_three_way(__x.second, __y.second); } -#else // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#else // !defined(_LIBCPP_HAS_NO_CONCEPTS) template inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX11 @@ -387,7 +387,7 @@ operator<=(const pair<_T1,_T2>& __x, const pair<_T1,_T2>& __y) return !(__y < __x); } -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) template inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 diff --git a/libcxx/include/numbers b/libcxx/include/numbers index 2ac36695b8880..35f5b04d9e417 100644 --- a/libcxx/include/numbers +++ b/libcxx/include/numbers @@ -63,7 +63,7 @@ namespace std::numbers { #include #include -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) #pragma GCC system_header @@ -128,6 +128,6 @@ inline constexpr double phi = phi_v; _LIBCPP_END_NAMESPACE_STD -#endif //_LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif //!defined(_LIBCPP_HAS_NO_CONCEPTS) #endif // _LIBCPP_NUMBERS diff --git a/libcxx/include/ranges b/libcxx/include/ranges index f7c543d7316cf..2d79d87eef895 100644 --- a/libcxx/include/ranges +++ b/libcxx/include/ranges @@ -239,11 +239,11 @@ namespace std::ranges { _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) namespace views = ranges::views; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/string_view b/libcxx/include/string_view index 992e88ea3c009..5d0a790dd13dd 100644 --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -286,7 +286,7 @@ public: #endif } -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template _End> requires (is_same_v, _CharT> && !is_convertible_v<_End, size_type>) constexpr _LIBCPP_HIDE_FROM_ABI basic_string_view(_It __begin, _End __end) @@ -707,17 +707,17 @@ private: size_type __size; }; -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template inline constexpr bool ranges::enable_view> = true; template inline constexpr bool ranges::enable_borrowed_range > = true; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) // [string.view.deduct] -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template _End> basic_string_view(_It, _End) -> basic_string_view>; #endif diff --git a/libcxx/include/tuple b/libcxx/include/tuple index 5cf120fec359e..6f3368ca301f5 100644 --- a/libcxx/include/tuple +++ b/libcxx/include/tuple @@ -1333,7 +1333,7 @@ operator==(const tuple<_Tp...>& __x, const tuple<_Up...>& __y) return __tuple_equal()(__x, __y); } -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // operator<=> @@ -1355,7 +1355,7 @@ operator<=>(const tuple<_Tp...>& __x, const tuple<_Up...>& __y) return _VSTD::__tuple_compare_three_way(__x, __y, index_sequence_for<_Tp...>{}); } -#else // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#else // !defined(_LIBCPP_HAS_NO_CONCEPTS) template inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX11 @@ -1425,7 +1425,7 @@ operator<=(const tuple<_Tp...>& __x, const tuple<_Up...>& __y) return !(__y < __x); } -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) // tuple_cat diff --git a/libcxx/include/type_traits b/libcxx/include/type_traits index b4010851f1334..3391999675a01 100644 --- a/libcxx/include/type_traits +++ b/libcxx/include/type_traits @@ -2442,7 +2442,7 @@ using __copy_cvref_t = typename __copy_cvref<_From, _To>::type; #endif // _LIBCPP_STD_VER > 11 // common_reference -#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) // Let COND_RES(X, Y) be: template using __cond_res = @@ -2596,7 +2596,7 @@ struct common_reference<_Tp, _Up, _Vp, _Rest...> // bullet 5 - Otherwise, there shall be no member `type`. template struct common_reference {}; -#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) // is_assignable From 91632c8ac97fa3daffe4ff8f1391735b5d6805e6 Mon Sep 17 00:00:00 2001 From: Arthur O'Dwyer Date: Tue, 1 Feb 2022 20:06:30 -0500 Subject: [PATCH 006/316] [libc++] [NFC] Normalize some `#ifndef _LIBCPP_HAS_NO_CONCEPTS`. (cherry picked from commit 93e7f35ac354a19a9db2f11fe17d1f955a5793b4) --- libcxx/include/__algorithm/in_in_out_result.h | 12 +++++++++--- libcxx/include/__algorithm/in_in_result.h | 10 ++++++++-- libcxx/include/__algorithm/in_out_result.h | 2 ++ libcxx/include/__iterator/indirectly_comparable.h | 4 ++-- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/libcxx/include/__algorithm/in_in_out_result.h b/libcxx/include/__algorithm/in_in_out_result.h index e365eb58eb624..a492d27352291 100644 --- a/libcxx/include/__algorithm/in_in_out_result.h +++ b/libcxx/include/__algorithm/in_in_out_result.h @@ -14,11 +14,16 @@ #include <__config> #include <__utility/move.h> +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +#pragma GCC system_header +#endif + _LIBCPP_BEGIN_NAMESPACE_STD -#ifndef _LIBCPP_HAS_NO_CONCEPTS +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) namespace ranges { + template struct in_in_out_result { [[no_unique_address]] _I1 in1; @@ -39,10 +44,11 @@ struct in_in_out_result { return {_VSTD::move(in1), _VSTD::move(in2), _VSTD::move(out)}; } }; + } // namespace ranges -#endif // _LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD -#endif // _LIBCPP___ALGORITHM_IN_IN_RESULT_H +#endif // _LIBCPP___ALGORITHM_IN_IN_OUT_RESULT_H diff --git a/libcxx/include/__algorithm/in_in_result.h b/libcxx/include/__algorithm/in_in_result.h index ed14ecedbbdfe..c8fe43d039dcb 100644 --- a/libcxx/include/__algorithm/in_in_result.h +++ b/libcxx/include/__algorithm/in_in_result.h @@ -14,11 +14,16 @@ #include <__config> #include <__utility/move.h> +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +#pragma GCC system_header +#endif + _LIBCPP_BEGIN_NAMESPACE_STD -#ifndef _LIBCPP_HAS_NO_CONCEPTS +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) namespace ranges { + template struct in_in_result { [[no_unique_address]] _I1 in1; @@ -36,9 +41,10 @@ struct in_in_result { _LIBCPP_HIDE_FROM_ABI constexpr operator in_in_result<_II1, _II2>() && { return {_VSTD::move(in1), _VSTD::move(in2)}; } }; + } // namespace ranges -#endif // _LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/in_out_result.h b/libcxx/include/__algorithm/in_out_result.h index 8a58d6ada10cf..d3c16e4acd459 100644 --- a/libcxx/include/__algorithm/in_out_result.h +++ b/libcxx/include/__algorithm/in_out_result.h @@ -21,6 +21,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if !defined(_LIBCPP_HAS_NO_CONCEPTS) + namespace ranges { template @@ -45,6 +46,7 @@ struct in_out_result { }; } // namespace ranges + #endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/indirectly_comparable.h b/libcxx/include/__iterator/indirectly_comparable.h index 3bafc56f926f9..ad5ff1a866d63 100644 --- a/libcxx/include/__iterator/indirectly_comparable.h +++ b/libcxx/include/__iterator/indirectly_comparable.h @@ -17,13 +17,13 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#ifndef _LIBCPP_HAS_NO_CONCEPTS +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) template concept indirectly_comparable = indirect_binary_predicate<_Rp, projected<_I1, _P1>, projected<_I2, _P2>>; -#endif // _LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD From c8bb1777fff5d1ae28a2deac0d6677e081d4200f Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Thu, 28 Oct 2021 11:53:48 -0400 Subject: [PATCH 007/316] [release] Use the Bootstrapping build for building LLVM releases Instead of using the (now deprecated) Projects build for libcxx, libcxxabi, libunwind and compiler-rt, this patch uses the Bootstrapping build. This implies that Clang will be built from scratch, and then the runtimes will be built using that just-built Clang instead of the system compiler. This is the correct way of assembling a toolchain, since we don't want to ship runtimes that were built with a non-Clang compiler (or a potentially older Clang). Differential Revision: https://reviews.llvm.org/D112748 (cherry picked from commit 26a1830e39baf0f8844cda0ba6be72eb8a66981d) --- llvm/utils/release/test-release.sh | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index cd1519370d5c8..d6fb5a972e633 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -236,16 +236,17 @@ fi # Projects list projects="llvm clang clang-tools-extra" +runtimes="" if [ $do_rt = "yes" ]; then - projects="$projects compiler-rt" + runtimes="$runtimes compiler-rt" fi if [ $do_libs = "yes" ]; then - projects="$projects libcxx" + runtimes="$runtimes libcxx" if [ $do_libcxxabi = "yes" ]; then - projects="$projects libcxxabi" + runtimes="$runtimes libcxxabi" fi if [ $do_libunwind = "yes" ]; then - projects="$projects libunwind" + runtimes="$runtimes libunwind" fi fi case $do_test_suite in @@ -377,6 +378,7 @@ function configure_llvmCore() { esac project_list=${projects// /;} + runtime_list=${runtimes// /;} echo "# Using C compiler: $c_compiler" echo "# Using C++ compiler: $cxx_compiler" @@ -389,6 +391,7 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ + -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log env CC="$c_compiler" CXX="$cxx_compiler" \ @@ -397,6 +400,7 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ + -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log From a55727f334b39600bfc71144b11b42aae6b94e0b Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 2 Feb 2022 11:20:55 +0100 Subject: [PATCH 008/316] [AVR] Avoid reusing the same variable name (NFC) Apparently GCC 5.4 (a supported compiler) has a bug where it will use the "MachineInstr &MI" defined by the range-based for loop to evaluate the for loop expression. Pick a different variable name to avoid this. (cherry picked from commit f8f55f7e0343634e8cf0892883ce7132b7a0dc50) --- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AVR/AVRFrameLowering.cpp b/llvm/lib/Target/AVR/AVRFrameLowering.cpp index b3bc9ede205eb..42a6e4f55dc86 100644 --- a/llvm/lib/Target/AVR/AVRFrameLowering.cpp +++ b/llvm/lib/Target/AVR/AVRFrameLowering.cpp @@ -298,11 +298,11 @@ bool AVRFrameLowering::restoreCalleeSavedRegisters( /// Replace pseudo store instructions that pass arguments through the stack with /// real instructions. static void fixStackStores(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, + MachineBasicBlock::iterator StartMI, const TargetInstrInfo &TII, Register FP) { // Iterate through the BB until we hit a call instruction or we reach the end. for (MachineInstr &MI : - llvm::make_early_inc_range(llvm::make_range(MI, MBB.end()))) { + llvm::make_early_inc_range(llvm::make_range(StartMI, MBB.end()))) { if (MI.isCall()) break; From d5e113c969bf4b6ac7f9f8872ee1ceaed22b1750 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Wed, 2 Feb 2022 20:15:40 +0100 Subject: [PATCH 009/316] [libc++] Remove the std::string base class Removing the base class of std::basic_string is not an ABI break, so we can remove any references to it from the header. Reviewed By: ldionne, Mordante, #libc Spies: libcxx-commits Differential Revision: https://reviews.llvm.org/D118733 (cherry picked from commit 5173f43cc892539271c34c5612fe783b51025da9) --- libcxx/include/__config | 2 +- libcxx/include/string | 15 --------------- libcxx/src/string.cpp | 21 ++++++++++++++++----- 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/libcxx/include/__config b/libcxx/include/__config index 3c3d4b57c76e4..d2d70c4ed7694 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -115,7 +115,7 @@ // about ABI compatibility. # define _LIBCPP_ABI_NO_RANDOM_DEVICE_COMPATIBILITY_LAYOUT // Remove basic_string common base -# define _LIBCPP_ABI_NO_BASIC_STRING_BASE_CLASS +# define _LIBCPP_ABI_DO_NOT_EXPORT_BASIC_STRING_COMMON #elif _LIBCPP_ABI_VERSION == 1 # if !defined(_LIBCPP_OBJECT_FORMAT_COFF) // Enable compiling copies of now inline methods into the dylib to support diff --git a/libcxx/include/string b/libcxx/include/string index 3616de8a214d8..01cff902e07db 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -618,18 +618,6 @@ operator+(const basic_string<_CharT, _Traits, _Allocator>& __x, _CharT __y); _LIBCPP_EXTERN_TEMPLATE(_LIBCPP_FUNC_VIS string operator+, allocator >(char const*, string const&)) -#ifndef _LIBCPP_ABI_NO_BASIC_STRING_BASE_CLASS -template -struct __basic_string_common; - -template <> -struct __basic_string_common { - // Both are defined in string.cpp - _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_length_error() const; - _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_out_of_range() const; -}; -#endif - template struct __string_is_trivial_iterator : public false_type {}; @@ -682,9 +670,6 @@ class _LIBCPP_PREFERRED_NAME(u32string) #endif basic_string -#ifndef _LIBCPP_ABI_NO_BASIC_STRING_BASE_CLASS - : private __basic_string_common // This base class is historical, but it needs to remain for ABI compatibility -#endif { public: typedef basic_string __self; diff --git a/libcxx/src/string.cpp b/libcxx/src/string.cpp index 3c63f408240d3..3cde2e9005ba2 100644 --- a/libcxx/src/string.cpp +++ b/libcxx/src/string.cpp @@ -21,15 +21,26 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#ifndef _LIBCPP_ABI_NO_BASIC_STRING_BASE_CLASS +#ifndef _LIBCPP_ABI_DO_NOT_EXPORT_BASIC_STRING_COMMON + +template +struct __basic_string_common; + +// The struct isn't declared anymore in the headers. It's only here for ABI compatibility. +template <> +struct __basic_string_common { + _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_length_error() const; + _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_out_of_range() const; +}; + void __basic_string_common::__throw_length_error() const { - _VSTD::__throw_length_error("basic_string"); + std::__throw_length_error("basic_string"); } - void __basic_string_common::__throw_out_of_range() const { - _VSTD::__throw_out_of_range("basic_string"); + std::__throw_out_of_range("basic_string"); } -#endif + +#endif // _LIBCPP_ABI_DO_NOT_EXPORT_BASIC_STRING_COMMON #define _LIBCPP_EXTERN_TEMPLATE_DEFINE(...) template __VA_ARGS__; #ifdef _LIBCPP_ABI_STRING_OPTIMIZED_EXTERNAL_INSTANTIATION From 2b6b76f480a3a15ac405944c19ba7327637a0052 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 3 Feb 2022 14:44:07 -0800 Subject: [PATCH 010/316] github: Add actions to automate part of the release workflow This adds support for automatically cherry-picking and testing fixes for the release branch using 'commands' in issue comments. The two supported commands are: /cherry-pick ... Which will backport and test commits from main. And also /branch owner/repo/branch Which will test commits from the given branch. Reviewed By: alexbatashev, kwk Differential Revision: https://reviews.llvm.org/D117386 (cherry picked from commit daf82a51a0c2ba9990cde172a4a1b8c1004d584d) --- .github/workflows/issue-release-workflow.yml | 80 ++++++ llvm/utils/git/github-automation.py | 244 ++++++++++++++++++- llvm/utils/git/requirements.txt | 36 +++ llvm/utils/git/requirements.txt.in | 7 + 4 files changed, 365 insertions(+), 2 deletions(-) create mode 100644 .github/workflows/issue-release-workflow.yml create mode 100644 llvm/utils/git/requirements.txt create mode 100644 llvm/utils/git/requirements.txt.in diff --git a/.github/workflows/issue-release-workflow.yml b/.github/workflows/issue-release-workflow.yml new file mode 100644 index 0000000000000..432f06d1586b0 --- /dev/null +++ b/.github/workflows/issue-release-workflow.yml @@ -0,0 +1,80 @@ +# This contains the workflow definitions that allow users to test backports +# to the release branch using comments on issues. +# +# /cherry-pick <...> +# +# This comment will attempt to cherry-pick the given commits to the latest +# release branch (release/Y.x) and if successful push the result to a branch +# on github. +# +# /branch // +# +# This comment will create a pull request from to the latest release +# branch. + +name: Issue Release Workflow + +on: + issue_comment: + types: + - created + - edited + +env: + COMMENT_BODY: ${{ github.event.comment.body }} + +jobs: + backport-commits: + name: Backport Commits + runs-on: ubuntu-20.04 + if: >- + (github.repository == 'llvm/llvm-project') && + !startswith(github.event.comment.body, '') && + contains(github.event.comment.body, '/cherry-pick') + steps: + - name: Fetch LLVM sources + uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + fetch-depth: 0 + + - name: Setup Environment + run: | + pip install -r ./llvm/utils/git/requirements.txt + ./llvm/utils/git/github-automation.py --token ${{ github.token }} setup-llvmbot-git + + - name: Backport Commits + run: | + printf "$COMMENT_BODY" | + ./llvm/utils/git/github-automation.py \ + --repo $GITHUB_REPOSITORY \ + --token ${{ secrets.RELEASE_WORKFLOW_PUSH_SECRET }} \ + release-workflow \ + --issue-number ${{ github.event.issue.number }} \ + auto + + create-pull-request: + name: Create Pull Request + runs-on: ubuntu-20.04 + if: >- + (github.repository == 'llvm/llvm-project') && + !startswith(github.event.comment.body, '') && + contains(github.event.comment.body, '/branch') + + steps: + - name: Fetch LLVM sources + uses: actions/checkout@v2 + + - name: Setup Environment + run: | + pip install -r ./llvm/utils/git/requirements.txt + + - name: Create Pull Request + run: | + printf "$COMMENT_BODY" | + ./llvm/utils/git/github-automation.py \ + --repo $GITHUB_REPOSITORY \ + --token ${{ secrets.RELEASE_WORKFLOW_PUSH_SECRET }} \ + release-workflow \ + --issue-number ${{ github.event.issue.number }} \ + auto diff --git a/llvm/utils/git/github-automation.py b/llvm/utils/git/github-automation.py index 9caa8588ddd76..95db66a5ade49 100755 --- a/llvm/utils/git/github-automation.py +++ b/llvm/utils/git/github-automation.py @@ -9,8 +9,12 @@ # ==-------------------------------------------------------------------------==# import argparse +from git import Repo # type: ignore import github import os +import re +import sys +from typing import * class IssueSubscriber: @@ -33,18 +37,254 @@ def run(self) -> bool: return True return False +def setup_llvmbot_git(git_dir = '.'): + """ + Configure the git repo in `git_dir` with the llvmbot account so + commits are attributed to llvmbot. + """ + repo = Repo(git_dir) + with repo.config_writer() as config: + config.set_value('user', 'name', 'llvmbot') + config.set_value('user', 'email', 'llvmbot@llvm.org') + +class ReleaseWorkflow: + + """ + This class implements the sub-commands for the release-workflow command. + The current sub-commands are: + * create-branch + * create-pull-request + + The execute_command method will automatically choose the correct sub-command + based on the text in stdin. + """ + + def __init__(self, token:str, repo:str, issue_number:int, + branch_repo_name:str, branch_repo_token:str, + llvm_project_dir:str) -> None: + self._token = token + self._repo_name = repo + self._issue_number = issue_number + self._branch_repo_name = branch_repo_name + if branch_repo_token: + self._branch_repo_token = branch_repo_token + else: + self._branch_repo_token = self.token + self._llvm_project_dir = llvm_project_dir + + @property + def token(self) -> str: + return self._token + + @property + def repo_name(self) -> str: + return self._repo_name + + @property + def issue_number(self) -> int: + return self._issue_number + + @property + def branch_repo_name(self) -> str: + return self._branch_repo_name + + @property + def branch_repo_token(self) -> str: + return self._branch_repo_token + + @property + def llvm_project_dir(self) -> str: + return self._llvm_project_dir + + @property + def __repo(self) -> github.Repository.Repository: + return github.Github(self.token).get_repo(self.repo_name) + + @property + def issue(self) -> github.Issue.Issue: + return self.__repo.get_issue(self.issue_number) + + @property + def push_url(self) -> str: + return 'https://{}@github.com/{}'.format(self.branch_repo_token, self.branch_repo_name) + + @property + def branch_name(self) -> str: + return 'issue{}'.format(self.issue_number) + + @property + def release_branch_for_issue(self) -> Optional[str]: + issue = self.issue + milestone = issue.milestone + if milestone is None: + return None + m = re.search('branch: (.+)',milestone.description) + if m: + return m.group(1) + return None + + def print_release_branch(self) -> None: + print(self.release_branch_for_issue) + + def issue_notify_branch(self) -> None: + self.issue.create_comment('/branch {}/{}'.format(self.branch_repo_name, self.branch_name)) + + def issue_notify_pull_request(self, pull:github.PullRequest.PullRequest) -> None: + self.issue.create_comment('/pull-request {}#{}'.format(self.branch_repo_name, pull.number)) + + @property + def action_url(self) -> str: + if os.getenv('CI'): + return 'https://github.com/{}/actions/runs/{}'.format(os.getenv('GITHUB_REPOSITORY'), os.getenv('GITHUB_RUN_ID')) + return "" + + def issue_notify_cherry_pick_failure(self, commit:str) -> github.IssueComment.IssueComment: + message = "\nFailed to cherry-pick: {}\n\n".format(commit) + action_url = self.action_url + if action_url: + message += action_url + "\n\n" + message += "Please manually backport the fix and push it to your github fork. Once this is done, please add a comment like this:\n\n`/branch //`" + issue = self.issue + comment = issue.create_comment(message) + issue.add_to_labels('release:cherry-pick-failed') + return comment + + def issue_notify_pull_request_failure(self, branch:str) -> github.IssueComment.IssueComment: + message = "Failed to create pull request for {} ".format(branch) + message += self.action_url + return self.issue.create_comment(message) + + + def create_branch(self, commits:List[str]) -> bool: + """ + This function attempts to backport `commits` into the branch associated + with `self.issue_number`. + + If this is successful, then the branch is pushed to `self.branch_repo_name`, if not, + a comment is added to the issue saying that the cherry-pick failed. + + :param list commits: List of commits to cherry-pick. + + """ + print('cherry-picking', commits) + branch_name = self.branch_name + local_repo = Repo(self.llvm_project_dir) + local_repo.git.checkout(self.release_branch_for_issue) + + for c in commits: + try: + local_repo.git.cherry_pick('-x', c) + except Exception as e: + self.issue_notify_cherry_pick_failure(c) + raise e + + push_url = self.push_url + print('Pushing to {} {}'.format(push_url, branch_name)) + local_repo.git.push(push_url, 'HEAD:{}'.format(branch_name)) + + self.issue_notify_branch() + return True + + + def create_pull_request(self, owner:str, branch:str) -> bool: + """ + reate a pull request in `self.branch_repo_name`. The base branch of the + pull request will be choosen based on the the milestone attached to + the issue represented by `self.issue_number` For example if the milestone + is Release 13.0.1, then the base branch will be release/13.x. `branch` + will be used as the compare branch. + https://docs.github.com/en/get-started/quickstart/github-glossary#base-branch + https://docs.github.com/en/get-started/quickstart/github-glossary#compare-branch + """ + repo = github.Github(self.token).get_repo(self.branch_repo_name) + issue_ref = '{}#{}'.format(self.repo_name, self.issue_number) + pull = None + release_branch_for_issue = self.release_branch_for_issue + if release_branch_for_issue is None: + return False + try: + pull = repo.create_pull(title='PR for {}'.format(issue_ref), + body='resolves {}'.format(issue_ref), + base=release_branch_for_issue, + head='{}:{}'.format(owner, branch), + maintainer_can_modify=False) + except Exception as e: + self.issue_notify_pull_request_failure(branch) + raise e + + if pull is None: + return False + + self.issue_notify_pull_request(pull) + + # TODO(tstellar): Do you really want to always return True? + return True + + + def execute_command(self) -> bool: + """ + This function reads lines from STDIN and executes the first command + that it finds. The 2 supported commands are: + /cherry-pick commit0 <...> + /branch // + """ + for line in sys.stdin: + line.rstrip() + m = re.search("/([a-z-]+)\s(.+)", line) + if not m: + continue + command = m.group(1) + args = m.group(2) + + if command == 'cherry-pick': + return self.create_branch(args.split()) + + if command == 'branch': + m = re.match('([^/]+)/([^/]+)/(.+)', args) + if m: + owner = m.group(1) + branch = m.group(3) + return self.create_pull_request(owner, branch) + + print("Do not understand input:") + print(sys.stdin.readlines()) + return False parser = argparse.ArgumentParser() -parser.add_argument('--token', type=str, required=True) -parser.add_argument('--repo', type=str, default=os.getenv('GITHUB_REPOSITORY', 'llvm/llvm-project')) +parser.add_argument('--token', type=str, required=True, help='GitHub authentiation token') +parser.add_argument('--repo', type=str, default=os.getenv('GITHUB_REPOSITORY', 'llvm/llvm-project'), + help='The GitHub repository that we are working with in the form of / (e.g. llvm/llvm-project)') subparsers = parser.add_subparsers(dest='command') issue_subscriber_parser = subparsers.add_parser('issue-subscriber') issue_subscriber_parser.add_argument('--label-name', type=str, required=True) issue_subscriber_parser.add_argument('--issue-number', type=int, required=True) +release_workflow_parser = subparsers.add_parser('release-workflow') +release_workflow_parser.add_argument('--llvm-project-dir', type=str, default='.', help='directory containing the llvm-project checout') +release_workflow_parser.add_argument('--issue-number', type=int, required=True, help='The issue number to update') +release_workflow_parser.add_argument('--branch-repo-token', type=str, + help='GitHub authentication token to use for the repository where new branches will be pushed. Defaults to TOKEN.') +release_workflow_parser.add_argument('--branch-repo', type=str, default='llvmbot/llvm-project', + help='The name of the repo where new branches will be pushed (e.g. llvm/llvm-project)') +release_workflow_parser.add_argument('sub_command', type=str, choices=['print-release-branch', 'auto'], + help='Print to stdout the name of the release branch ISSUE_NUMBER should be backported to') + +llvmbot_git_config_parser = subparsers.add_parser('setup-llvmbot-git', help='Set the default user and email for the git repo in LLVM_PROJECT_DIR to llvmbot') + args = parser.parse_args() if args.command == 'issue-subscriber': issue_subscriber = IssueSubscriber(args.token, args.repo, args.issue_number, args.label_name) issue_subscriber.run() +elif args.command == 'release-workflow': + release_workflow = ReleaseWorkflow(args.token, args.repo, args.issue_number, + args.branch_repo, args.branch_repo_token, + args.llvm_project_dir) + if args.sub_command == 'print-release-branch': + release_workflow.print_release_branch() + else: + if not release_workflow.execute_command(): + sys.exit(1) +elif args.command == 'setup-llvmbot-git': + setup_llvmbot_git() diff --git a/llvm/utils/git/requirements.txt b/llvm/utils/git/requirements.txt new file mode 100644 index 0000000000000..9ccbbd2ceb564 --- /dev/null +++ b/llvm/utils/git/requirements.txt @@ -0,0 +1,36 @@ +# +# This file is autogenerated by pip-compile with python 3.8 +# To update, run: +# +# pip-compile --output-file=requirements.txt requirements.txt.in +# +certifi==2021.10.8 + # via requests +cffi==1.15.0 + # via pynacl +charset-normalizer==2.0.10 + # via requests +deprecated==1.2.13 + # via pygithub +gitdb==4.0.9 + # via gitpython +gitpython==3.1.26 + # via -r requirements.txt.in +idna==3.3 + # via requests +pycparser==2.21 + # via cffi +pygithub==1.55 + # via -r requirements.txt.in +pyjwt==2.3.0 + # via pygithub +pynacl==1.5.0 + # via pygithub +requests==2.27.1 + # via pygithub +smmap==5.0.0 + # via gitdb +urllib3==1.26.8 + # via requests +wrapt==1.13.3 + # via deprecated diff --git a/llvm/utils/git/requirements.txt.in b/llvm/utils/git/requirements.txt.in new file mode 100644 index 0000000000000..7658a1a2bd06c --- /dev/null +++ b/llvm/utils/git/requirements.txt.in @@ -0,0 +1,7 @@ +# Convert this file into a requirements.txt file by running: +# +# pip install pip-tools +# pip-compile -o requirements.txt requirements.txt.in + +PyGithub==1.55 +GitPython==3.1.26 From 749fb39c8e8ac4aa8460aac4926cad42153cc9d1 Mon Sep 17 00:00:00 2001 From: Tiago Macarios Date: Thu, 3 Feb 2022 10:23:15 -0500 Subject: [PATCH 011/316] [libc++] Fix chrono::duration constructor constraint As per [time.duration.cons]/1, the constructor constraint should be on const Rep2&. As it is now the code will fail to compile in certain cases, for example (https://godbolt.org/z/c7fPrcTYM): struct S{ operator int() const&& noexcept = delete; operator int() const& noexcept; }; const S &fun(); auto k = std::chrono::microseconds{fun()}; Differential Revision: https://reviews.llvm.org/D118902 (cherry picked from commit eaadc451566f0d1aec873b7fe8b1a9dc3a7b29bd) --- libcxx/include/__chrono/duration.h | 2 +- .../time.duration.cons/rep.pass.cpp | 45 ++++++++++++++----- 2 files changed, 34 insertions(+), 13 deletions(-) diff --git a/libcxx/include/__chrono/duration.h b/libcxx/include/__chrono/duration.h index 24801772ec5d8..b7d88cb52ea83 100644 --- a/libcxx/include/__chrono/duration.h +++ b/libcxx/include/__chrono/duration.h @@ -251,7 +251,7 @@ class _LIBCPP_TEMPLATE_VIS duration explicit duration(const _Rep2& __r, typename enable_if < - is_convertible<_Rep2, rep>::value && + is_convertible::value && (treat_as_floating_point::value || !treat_as_floating_point<_Rep2>::value) >::type* = nullptr) diff --git a/libcxx/test/std/utilities/time/time.duration/time.duration.cons/rep.pass.cpp b/libcxx/test/std/utilities/time/time.duration/time.duration.cons/rep.pass.cpp index 92dbc5e9b62ad..252f5032966a5 100644 --- a/libcxx/test/std/utilities/time/time.duration/time.duration.cons/rep.pass.cpp +++ b/libcxx/test/std/utilities/time/time.duration/time.duration.cons/rep.pass.cpp @@ -20,24 +20,45 @@ #include "test_macros.h" #include "../../rep.h" +#if TEST_STD_VER >= 11 +struct NotValueConvertible { + operator int() const&& = delete; + constexpr operator int() const& { return 1; } +}; +#endif + template -void -test(R r) -{ +TEST_CONSTEXPR_CXX14 void check(R r) { D d(r); assert(d.count() == r); +} + +TEST_CONSTEXPR_CXX14 bool test() { + check >(5); + check > >(5); + check > >(Rep(3)); + check > >(5.5); + + // test for [time.duration.cons]/1 #if TEST_STD_VER >= 11 - constexpr D d2(R(2)); - static_assert(d2.count() == 2, ""); + check >(NotValueConvertible()); #endif + + return true; } -int main(int, char**) -{ - test >(5); - test > >(5); - test > >(Rep(3)); - test > >(5.5); +int main(int, char**) { + test(); +#if TEST_STD_VER > 11 + static_assert(test(), ""); +#endif - return 0; + // Basic test for constexpr-friendliness in C++11 +#if TEST_STD_VER >= 11 + { + constexpr std::chrono::duration d(5); + static_assert(d.count() == 5, ""); + } +#endif + return 0; } From 7ff79971b98a5143cba81bcaebb2d5a70b3728c0 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Thu, 3 Feb 2022 09:43:03 -0500 Subject: [PATCH 012/316] [libc++] Disable incomplete features for the LLVM 14 release For the LLVM 14 release, don't ship incomplete features (currently ranges and format) by default. If some vendors want to ship those features, they can override the CMake option manually. This is consistent with what we did for LLVM 13. Note that this patch is only aimed towards the release/14.x branch. Differential Revision: https://reviews.llvm.org/D118901 --- libcxx/CMakeLists.txt | 2 +- libcxx/benchmarks/CMakeLists.txt | 5 +++++ libcxx/docs/ReleaseNotes.rst | 5 +++-- libcxx/include/module.modulemap | 3 ++- ....libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist | 6 ------ ....libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist | 6 ------ ....libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist | 6 ------ libcxxabi/test/libcxxabi/test/config.py | 2 +- 8 files changed, 12 insertions(+), 23 deletions(-) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 77df59e4cd755..183b3df621b42 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -133,7 +133,7 @@ option(LIBCXX_ENABLE_INCOMPLETE_FEATURES "Whether to enable support for incomplete library features. Incomplete features are new library features under development. These features don't guarantee ABI stability nor the quality of completed library features. Vendors - shipping the library may want to disable this option." ON) + shipping the library may want to disable this option." OFF) set(LIBCXX_TEST_CONFIG "legacy.cfg.in" CACHE STRING "The path to the Lit testing configuration to use when running the tests. If a relative path is provided, it is assumed to be relative to '/libcxx/test/configs'.") diff --git a/libcxx/benchmarks/CMakeLists.txt b/libcxx/benchmarks/CMakeLists.txt index 8c8c9e4f186e0..95e28618b55e3 100644 --- a/libcxx/benchmarks/CMakeLists.txt +++ b/libcxx/benchmarks/CMakeLists.txt @@ -166,6 +166,11 @@ endfunction() # Register Benchmark tests #============================================================================== file(GLOB BENCHMARK_TESTS "*.bench.cpp") + +if (NOT LIBCXX_ENABLE_INCOMPLETE_FEATURES) + list(FILTER BENCHMARK_TESTS EXCLUDE REGEX "(format_to_n|format_to|format|formatted_size|formatter_float|std_format_spec_string_unicode).bench.cpp") +endif() + foreach(test_path ${BENCHMARK_TESTS}) get_filename_component(test_file "${test_path}" NAME) string(REPLACE ".bench.cpp" "" test_name "${test_file}") diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index 8d645426138a2..a33c6621d448d 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -43,8 +43,9 @@ New Features functions are known to be inefficient, both in memory usage and performance. The implementation isn't API- or ABI-stable and therefore considered experimental. (Some not-yet-implemented papers require an API-break.) - Vendors can still disable this header by turning the CMake option - `LIBCXX_ENABLE_INCOMPLETE_FEATURES` off. + As a result, it is disabled by default, however vendors can enable the + header by using ``-DLIBCXX_ENABLE_INCOMPLETE_FEATURES=ON`` when + configuring their build. - There's a new CMake option ``LIBCXX_ENABLE_UNICODE`` to disable Unicode support in the ```` header. This only affects the estimation of the diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index 84abf01bf5d75..749c17f8bc08f 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -2,7 +2,8 @@ // since __config may be included from C headers which may create an // include cycle. module std_config [system] [extern_c] { - header "__config" + textual header "__config" + textual header "__config_site" } module std [system] { diff --git a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist index 6f5f50e997664..cb315f91f659a 100644 --- a/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist +++ b/libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist @@ -1039,9 +1039,6 @@ {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED0Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED1Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED2Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD0Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD1Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD2Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorC1ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorC2ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorD0Ev', 'type': 'FUNC'} @@ -1991,7 +1988,6 @@ {'is_defined': True, 'name': '__ZTINSt3__112bad_weak_ptrE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTINSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} @@ -2186,7 +2182,6 @@ {'is_defined': True, 'name': '__ZTSNSt3__112bad_weak_ptrE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTSNSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} @@ -2366,7 +2361,6 @@ {'is_defined': True, 'name': '__ZTVNSt3__112bad_weak_ptrE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTVNSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} diff --git a/libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist b/libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist index 5ad475d43feb9..1c3af8ca31a06 100644 --- a/libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist +++ b/libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist @@ -1039,9 +1039,6 @@ {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED0Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED1Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112ctype_bynameIwED2Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD0Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD1Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '__ZNSt3__112format_errorD2Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorC1ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorC2ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '__ZNSt3__112future_errorD0Ev', 'type': 'FUNC'} @@ -2000,7 +1997,6 @@ {'is_defined': True, 'name': '__ZTINSt3__112codecvt_baseE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTINSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTINSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} @@ -2210,7 +2206,6 @@ {'is_defined': True, 'name': '__ZTSNSt3__112codecvt_baseE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTSNSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTSNSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} @@ -2396,7 +2391,6 @@ {'is_defined': True, 'name': '__ZTVNSt3__112bad_weak_ptrE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112ctype_bynameIcEE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112ctype_bynameIwEE', 'size': 0, 'type': 'OBJECT'} -{'is_defined': True, 'name': '__ZTVNSt3__112format_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112future_errorE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112strstreambufE', 'size': 0, 'type': 'OBJECT'} {'is_defined': True, 'name': '__ZTVNSt3__112system_errorE', 'size': 0, 'type': 'OBJECT'} diff --git a/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist b/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist index e658d3321ce8e..77dfde59a0794 100644 --- a/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist +++ b/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist @@ -730,9 +730,6 @@ {'is_defined': True, 'name': '_ZNSt3__112ctype_bynameIwED0Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '_ZNSt3__112ctype_bynameIwED1Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '_ZNSt3__112ctype_bynameIwED2Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '_ZNSt3__112format_errorD0Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '_ZNSt3__112format_errorD1Ev', 'type': 'FUNC'} -{'is_defined': True, 'name': '_ZNSt3__112format_errorD2Ev', 'type': 'FUNC'} {'is_defined': True, 'name': '_ZNSt3__112future_errorC1ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '_ZNSt3__112future_errorC2ENS_10error_codeE', 'type': 'FUNC'} {'is_defined': True, 'name': '_ZNSt3__112future_errorD0Ev', 'type': 'FUNC'} @@ -1667,7 +1664,6 @@ {'is_defined': True, 'name': '_ZTINSt3__112codecvt_baseE', 'size': 16, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTINSt3__112ctype_bynameIcEE', 'size': 24, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTINSt3__112ctype_bynameIwEE', 'size': 24, 'type': 'OBJECT'} -{'is_defined': True, 'name': '_ZTINSt3__112format_errorE', 'size': 24, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTINSt3__112future_errorE', 'size': 24, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTINSt3__112strstreambufE', 'size': 24, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTINSt3__112system_errorE', 'size': 24, 'type': 'OBJECT'} @@ -1797,7 +1793,6 @@ {'is_defined': True, 'name': '_ZTSNSt3__112codecvt_baseE', 'size': 23, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTSNSt3__112ctype_bynameIcEE', 'size': 26, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTSNSt3__112ctype_bynameIwEE', 'size': 26, 'type': 'OBJECT'} -{'is_defined': True, 'name': '_ZTSNSt3__112format_errorE', 'size': 23, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTSNSt3__112future_errorE', 'size': 23, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTSNSt3__112strstreambufE', 'size': 23, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTSNSt3__112system_errorE', 'size': 23, 'type': 'OBJECT'} @@ -1931,7 +1926,6 @@ {'is_defined': True, 'name': '_ZTVNSt3__112bad_weak_ptrE', 'size': 40, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTVNSt3__112ctype_bynameIcEE', 'size': 104, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTVNSt3__112ctype_bynameIwEE', 'size': 136, 'type': 'OBJECT'} -{'is_defined': True, 'name': '_ZTVNSt3__112format_errorE', 'size': 40, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTVNSt3__112future_errorE', 'size': 40, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTVNSt3__112strstreambufE', 'size': 128, 'type': 'OBJECT'} {'is_defined': True, 'name': '_ZTVNSt3__112system_errorE', 'size': 40, 'type': 'OBJECT'} diff --git a/libcxxabi/test/libcxxabi/test/config.py b/libcxxabi/test/libcxxabi/test/config.py index 5855240a4b24c..63c771689fe81 100644 --- a/libcxxabi/test/libcxxabi/test/config.py +++ b/libcxxabi/test/libcxxabi/test/config.py @@ -70,7 +70,7 @@ def configure_compile_flags_header_includes(self): cxx_target_headers = os.path.join(path, triple, cxx, version) if os.path.isdir(cxx_target_headers): self.cxx.compile_flags += ['-I' + cxx_target_headers] - self.cxx.compile_flags += ['-I' + cxx_headers] + self.cxx.compile_flags += ['-isystem' + cxx_headers] self.cxx.compile_flags += ['-I' + os.path.join(self.libcxx_src_root, 'src')] libcxxabi_headers = self.get_lit_conf( From 9f9ea707d0c6f2839a52a7045a35ea3356d851be Mon Sep 17 00:00:00 2001 From: Arthur O'Dwyer Date: Thu, 3 Feb 2022 21:41:30 -0500 Subject: [PATCH 013/316] [libc++] No longer support ranges::begin(x) when x is an array of incomplete type. var-const points out that `ranges::begin` is (non-normatively but explicitly) always supposed to return a `std::input_or_output_iterator`, and `Incomplete*` is not a `std::input_or_output_iterator` because it has no `operator++`. Therefore, we should never return `Incomplete*` from `ranges::begin(x)`, even when `x` is `Incomplete(&)[]`. Instead, just SFINAE away. Differential Revision: https://reviews.llvm.org/D118963 (cherry picked from commit cc1d02ba2d177e0d31561934337f5412167f6954) --- libcxx/include/__ranges/access.h | 15 +++- .../range.access/begin.incomplete_type.sh.cpp | 75 ------------------- .../std/ranges/range.access/begin.pass.cpp | 21 +++++- 3 files changed, 30 insertions(+), 81 deletions(-) delete mode 100644 libcxx/test/libcxx/ranges/range.access/begin.incomplete_type.sh.cpp diff --git a/libcxx/include/__ranges/access.h b/libcxx/include/__ranges/access.h index 67c6c57bd81e4..07a92d7834755 100644 --- a/libcxx/include/__ranges/access.h +++ b/libcxx/include/__ranges/access.h @@ -59,10 +59,17 @@ namespace __begin { struct __fn { template - requires is_array_v> - [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp& __t) const noexcept + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp (&__t)[]) const noexcept + requires (sizeof(_Tp) != 0) // Disallow incomplete element types. { - return __t; + return __t + 0; + } + + template + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp (&__t)[_Np]) const noexcept + requires (sizeof(_Tp) != 0) // Disallow incomplete element types. + { + return __t + 0; } template @@ -127,7 +134,7 @@ namespace __end { public: template [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Tp (&__t)[_Np]) const noexcept - requires (sizeof(*__t) != 0) // Disallow incomplete element types. + requires (sizeof(_Tp) != 0) // Disallow incomplete element types. { return __t + _Np; } diff --git a/libcxx/test/libcxx/ranges/range.access/begin.incomplete_type.sh.cpp b/libcxx/test/libcxx/ranges/range.access/begin.incomplete_type.sh.cpp deleted file mode 100644 index cc27789c04f3d..0000000000000 --- a/libcxx/test/libcxx/ranges/range.access/begin.incomplete_type.sh.cpp +++ /dev/null @@ -1,75 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// RUN: %{cxx} %{flags} %{compile_flags} -c %s -o %t.tu1.o -DTU1 -// RUN: %{cxx} %{flags} %{compile_flags} -c %s -o %t.tu2.o -DTU2 -// RUN: %{cxx} %t.tu1.o %t.tu2.o %{flags} %{link_flags} -o %t.exe -// RUN: %{exec} %t.exe - -// UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges - -// Test the libc++-specific behavior that we handle the IFNDR case for ranges::begin -// by returning the beginning of the array-of-incomplete-type. -// Use two translation units so that `Incomplete` really is never completed -// at any point within TU2, but the array `bounded` is still given a definition -// (in TU1) to avoid an "undefined reference" error from the linker. -// All of the actually interesting stuff takes place within TU2. - -#include -#include - -#include "test_macros.h" - -#if defined(TU1) - -struct Incomplete {}; -Incomplete bounded[10]; -Incomplete unbounded[10]; - -#else // defined(TU1) - -struct Incomplete; - -constexpr bool test() -{ - { - extern Incomplete bounded[10]; - assert(std::ranges::begin(bounded) == bounded); - assert(std::ranges::cbegin(bounded) == bounded); - assert(std::ranges::begin(std::as_const(bounded)) == bounded); - assert(std::ranges::cbegin(std::as_const(bounded)) == bounded); - ASSERT_SAME_TYPE(decltype(std::ranges::begin(bounded)), Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::cbegin(bounded)), const Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::begin(std::as_const(bounded))), const Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::cbegin(std::as_const(bounded))), const Incomplete*); - } - { - extern Incomplete unbounded[]; - assert(std::ranges::begin(unbounded) == unbounded); - assert(std::ranges::cbegin(unbounded) == unbounded); - assert(std::ranges::begin(std::as_const(unbounded)) == unbounded); - assert(std::ranges::cbegin(std::as_const(unbounded)) == unbounded); - ASSERT_SAME_TYPE(decltype(std::ranges::begin(unbounded)), Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::cbegin(unbounded)), const Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::begin(std::as_const(unbounded))), const Incomplete*); - ASSERT_SAME_TYPE(decltype(std::ranges::cbegin(std::as_const(unbounded))), const Incomplete*); - } - - return true; -} - -int main(int, char**) -{ - test(); - static_assert(test()); - return 0; -} - -#endif // defined(TU1) diff --git a/libcxx/test/std/ranges/range.access/begin.pass.cpp b/libcxx/test/std/ranges/range.access/begin.pass.cpp index 07b1a3b89a7f1..7014681ccabf9 100644 --- a/libcxx/test/std/ranges/range.access/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.access/begin.pass.cpp @@ -31,9 +31,26 @@ static_assert( std::is_invocable_v); struct Incomplete; static_assert(!std::is_invocable_v); -static_assert(!std::is_invocable_v); +static_assert(!std::is_invocable_v); static_assert(!std::is_invocable_v); -static_assert(!std::is_invocable_v); +static_assert(!std::is_invocable_v); + +static_assert(!std::is_invocable_v); +static_assert(!std::is_invocable_v); +static_assert(!std::is_invocable_v); +static_assert(!std::is_invocable_v); + +// This case is IFNDR; we handle it SFINAE-friendly. +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); + +// This case is IFNDR; we handle it SFINAE-friendly. +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); +LIBCPP_STATIC_ASSERT(!std::is_invocable_v); struct BeginMember { int x; From 62a6f40e14db35013b8ed36571f35fc62c759e9b Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 10:15:11 -0800 Subject: [PATCH 014/316] [msan] Guard FP_XSTATE_MAGIC1 usage with SANITIZER_GLIBC Fix build for Linux musl. Reviewed By: #sanitizers, dvyukov Differential Revision: https://reviews.llvm.org/D118970 (cherry picked from commit 9d1857f69f4ef00d9fd1b21660c20e00b993d06f) --- .../lib/sanitizer_common/sanitizer_platform_limits_posix.cpp | 2 +- compiler-rt/test/msan/Linux/signal_mcontext.cpp | 2 +- compiler-rt/test/msan/Linux/signal_mcontext2.cpp | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp index 82048f0eae2e3..32b8f47ed6338 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp @@ -217,7 +217,7 @@ namespace __sanitizer { unsigned struct_sockaddr_sz = sizeof(struct sockaddr); unsigned ucontext_t_sz(void *ctx) { -# if SANITIZER_LINUX && SANITIZER_X64 +# if SANITIZER_GLIBC && SANITIZER_X64 // See kernel arch/x86/kernel/fpu/signal.c for details. const auto *fpregs = static_cast(ctx)->uc_mcontext.fpregs; // The member names differ across header versions, but the actual layout diff --git a/compiler-rt/test/msan/Linux/signal_mcontext.cpp b/compiler-rt/test/msan/Linux/signal_mcontext.cpp index 932b4b8c09775..b49451fbb730b 100644 --- a/compiler-rt/test/msan/Linux/signal_mcontext.cpp +++ b/compiler-rt/test/msan/Linux/signal_mcontext.cpp @@ -10,7 +10,7 @@ void handler(int sig, siginfo_t *info, void *uctx) { __msan_check_mem_is_initialized(uctx, sizeof(ucontext_t)); -#if defined(__x86_64__) +#if defined(__GLIBC__) && defined(__x86_64__) auto *mctx = &static_cast(uctx)->uc_mcontext; if (auto *fpregs = mctx->fpregs) { // The member names differ across header versions, but the actual layout diff --git a/compiler-rt/test/msan/Linux/signal_mcontext2.cpp b/compiler-rt/test/msan/Linux/signal_mcontext2.cpp index 6bb6740c6fa7c..f65f909c87ef1 100644 --- a/compiler-rt/test/msan/Linux/signal_mcontext2.cpp +++ b/compiler-rt/test/msan/Linux/signal_mcontext2.cpp @@ -1,6 +1,7 @@ // RUN: %clangxx_msan -fsanitize-memory-track-origins=2 -O1 %s -o %t && not %run %t 2>&1 | FileCheck %s -// REQUIRES: x86_64-target-arch +// musl does not define FP_XSTATE_MAGIC1. +// REQUIRES: x86_64-target-arch && glibc-2.27 #include #include From 7d591098479927023ea3a393bbd47e40e1a22246 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 13:20:49 -0800 Subject: [PATCH 015/316] [ELF] Support REL-format R_AARCH64_NONE relocation -fprofile-use=/-fprofile-sample-use= compiles may produce REL-format .rel.llvm.call-graph-profile even if the prevailing format is RELA on AArch64. Add R_AARCH64_NONE to getImplicitAddend to fix this linker error: ``` ld.lld: error: internal linker error: cannot read addend for relocation R_AARCH64_NONE PLEASE submit a bug report to https://crbug.com and run tools/clang/scripts/process_crashreports.py (only works inside Google) which will upload a report and include the crash backtrace. ``` (cherry picked from commit f457863ae345d2635026501f5383e0e625869639) --- lld/ELF/Arch/AArch64.cpp | 2 + lld/test/ELF/relocation-none-aarch64.s | 26 --------- lld/test/ELF/relocation-none-aarch64.test | 69 +++++++++++++++++++++++ 3 files changed, 71 insertions(+), 26 deletions(-) delete mode 100644 lld/test/ELF/relocation-none-aarch64.s create mode 100644 lld/test/ELF/relocation-none-aarch64.test diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 5789bc935b638..9e857d5906845 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -197,6 +197,8 @@ int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const { switch (type) { case R_AARCH64_TLSDESC: return read64(buf + 8); + case R_AARCH64_NONE: + return 0; default: internalLinkerError(getErrorLocation(buf), "cannot read addend for relocation " + toString(type)); diff --git a/lld/test/ELF/relocation-none-aarch64.s b/lld/test/ELF/relocation-none-aarch64.s deleted file mode 100644 index 7783c127cf867..0000000000000 --- a/lld/test/ELF/relocation-none-aarch64.s +++ /dev/null @@ -1,26 +0,0 @@ -# REQUIRES: aarch64 - -# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-musl %s -o %t.o -# RUN: ld.lld --gc-sections %t.o -o %t -# RUN: llvm-readelf -S -r %t | FileCheck %s - -# Test that we discard R_AARCH64_NONE, but respect the references it creates -# among sections. - -# CHECK: .data -# CHECK: There are no relocations in this file. - -# RUN: ld.lld -r %t.o -o %t -# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s - -# RELOC: Section ({{.*}}) .rela.text { -# RELOC-NEXT: 0x0 R_AARCH64_NONE .data 0x0 -# RELOC-NEXT: } - -.globl _start -_start: - ret - .reloc 0, R_AARCH64_NONE, .data - -.data - .long 0 diff --git a/lld/test/ELF/relocation-none-aarch64.test b/lld/test/ELF/relocation-none-aarch64.test new file mode 100644 index 0000000000000..0147085021f7a --- /dev/null +++ b/lld/test/ELF/relocation-none-aarch64.test @@ -0,0 +1,69 @@ +# REQUIRES: aarch64 +# RUN: yaml2obj %s -o %t.o +# RUN: ld.lld --gc-sections %t.o -o %t +# RUN: llvm-readelf -S -r %t | FileCheck %s + +## Test that we discard R_AARCH64_NONE, but respect the references it creates +## among sections. + +# CHECK: .data +# CHECK: There are no relocations in this file. + +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + +## Both REL and RELA are supported. .rel.llvm.call-graph-profile uses REL even +## if the prevailing format is RELA. +# RELOC: Section ({{.*}}) .rela.text { +# RELOC-NEXT: 0x0 R_AARCH64_NONE .data 0x0 +# RELOC-NEXT: } +# RELOC: Section ({{.*}}) .rel.nonalloc1 { +# RELOC-NEXT: 0x0 R_AARCH64_NONE .data +# RELOC-NEXT: } +# RELOC: Section ({{.*}}) .rela.nonalloc2 { +# RELOC-NEXT: 0x0 R_AARCH64_NONE .data 0x0 +# RELOC-NEXT: } + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_AARCH64 +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + - Name: .data + Type: SHT_PROGBITS + Flags: [ SHF_WRITE, SHF_ALLOC ] + - Name: .nonalloc1 + Type: SHT_PROGBITS + - Name: .nonalloc2 + Type: SHT_PROGBITS + - Name: .rela.text + Type: SHT_RELA + Info: .text + Relocations: + - Symbol: .data + Type: R_AARCH64_NONE + - Name: .rel.nonalloc1 + Type: SHT_REL + Info: .nonalloc1 + Relocations: + - Symbol: .data + Type: R_AARCH64_NONE + - Name: .rela.nonalloc2 + Type: SHT_RELA + Info: .nonalloc2 + Relocations: + - Symbol: .data + Type: R_AARCH64_NONE +Symbols: + - Name: .data + Type: STT_SECTION + Section: .data + - Name: _start + Section: .text + Binding: STB_GLOBAL +... From 7ee59df38e38555bde58497ad6296f605a997831 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 13:59:18 -0800 Subject: [PATCH 016/316] [ELF][test] Test getImplicitAddend for R_ARM_NONE/R_RISCV_NONE/R_386_NONE/R_X86_64_NONE Similar to f457863ae345d2635026501f5383e0e625869639 (cherry picked from commit 3fd30958b79293f64545c7328c58982f959feb51) --- lld/test/ELF/relocation-none-arm.s | 26 ------------- lld/test/ELF/relocation-none-i386.s | 26 ------------- lld/test/ELF/relocation-none-x86-64.s | 26 ------------- ...none-aarch64.test => relocation-none.test} | 37 +++++++++++++------ 4 files changed, 26 insertions(+), 89 deletions(-) delete mode 100644 lld/test/ELF/relocation-none-arm.s delete mode 100644 lld/test/ELF/relocation-none-i386.s delete mode 100644 lld/test/ELF/relocation-none-x86-64.s rename lld/test/ELF/{relocation-none-aarch64.test => relocation-none.test} (61%) diff --git a/lld/test/ELF/relocation-none-arm.s b/lld/test/ELF/relocation-none-arm.s deleted file mode 100644 index a3ebc3189b34e..0000000000000 --- a/lld/test/ELF/relocation-none-arm.s +++ /dev/null @@ -1,26 +0,0 @@ -# REQUIRES: arm - -# RUN: llvm-mc -filetype=obj -triple=armv7-linux-musl %s -o %t.o -# RUN: ld.lld --gc-sections %t.o -o %t -# RUN: llvm-readelf -S -r %t | FileCheck %s - -# Test that we discard R_ARM_NONE, but respect the references it creates among -# sections. - -# CHECK: .data -# CHECK: There are no relocations in this file. - -# RUN: ld.lld -r %t.o -o %t -# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s - -# RELOC: Section ({{.*}}) .rel.text { -# RELOC-NEXT: 0x0 R_ARM_NONE .data -# RELOC-NEXT: } - -.globl _start -_start: - nop - .reloc 0, R_ARM_NONE, .data - -.data - .long 0 diff --git a/lld/test/ELF/relocation-none-i386.s b/lld/test/ELF/relocation-none-i386.s deleted file mode 100644 index 54913b37ed8b5..0000000000000 --- a/lld/test/ELF/relocation-none-i386.s +++ /dev/null @@ -1,26 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=i386-linux-musl %s -o %t.o -# RUN: ld.lld --gc-sections %t.o -o %t -# RUN: llvm-readelf -S -r %t | FileCheck %s - -# Test that we discard R_386_NONE, but respect the -# references it creates among sections. - -# CHECK: .data -# CHECK: There are no relocations in this file. - -# RUN: ld.lld -r %t.o -o %t -# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s - -# RELOC: Section ({{.*}}) .rel.text { -# RELOC-NEXT: 0x0 R_386_NONE .data -# RELOC-NEXT: } - -.globl _start -_start: - ret - .reloc 0, R_386_NONE, .data - -.data - .long 0 diff --git a/lld/test/ELF/relocation-none-x86-64.s b/lld/test/ELF/relocation-none-x86-64.s deleted file mode 100644 index be6b07c3f5022..0000000000000 --- a/lld/test/ELF/relocation-none-x86-64.s +++ /dev/null @@ -1,26 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-linux-musl %s -o %t.o -# RUN: ld.lld --gc-sections %t.o -o %t -# RUN: llvm-readelf -S -r %t | FileCheck %s - -# Test that we discard R_X86_64_NONE, but respect the -# references it creates among sections. - -# CHECK: .data -# CHECK: There are no relocations in this file. - -# RUN: ld.lld -r %t.o -o %t -# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s - -# RELOC: Section ({{.*}}) .rela.text { -# RELOC-NEXT: 0x0 R_X86_64_NONE .data 0x0 -# RELOC-NEXT: } - -.globl _start -_start: - ret - .reloc 0, R_X86_64_NONE, .data - -.data - .long 0 diff --git a/lld/test/ELF/relocation-none-aarch64.test b/lld/test/ELF/relocation-none.test similarity index 61% rename from lld/test/ELF/relocation-none-aarch64.test rename to lld/test/ELF/relocation-none.test index 0147085021f7a..a9ba6402ae8de 100644 --- a/lld/test/ELF/relocation-none-aarch64.test +++ b/lld/test/ELF/relocation-none.test @@ -1,9 +1,8 @@ -# REQUIRES: aarch64 -# RUN: yaml2obj %s -o %t.o +# RUN: yaml2obj -DMACHINE=AARCH64 %s -o %t.o # RUN: ld.lld --gc-sections %t.o -o %t # RUN: llvm-readelf -S -r %t | FileCheck %s -## Test that we discard R_AARCH64_NONE, but respect the references it creates +## Test that we discard R_*_NONE, but respect the references it creates ## among sections. # CHECK: .data @@ -12,24 +11,40 @@ # RUN: ld.lld -r %t.o -o %t # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s +# RUN: yaml2obj -DBITS=32 -DMACHINE=ARM %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + +# RUN: yaml2obj -DMACHINE=RISCV %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + +# RUN: yaml2obj -DBITS=32 -DMACHINE=386 %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + +# RUN: yaml2obj -DMACHINE=X86_64 %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + ## Both REL and RELA are supported. .rel.llvm.call-graph-profile uses REL even ## if the prevailing format is RELA. # RELOC: Section ({{.*}}) .rela.text { -# RELOC-NEXT: 0x0 R_AARCH64_NONE .data 0x0 +# RELOC-NEXT: 0x0 R_{{.*}}_NONE .data 0x0 # RELOC-NEXT: } # RELOC: Section ({{.*}}) .rel.nonalloc1 { -# RELOC-NEXT: 0x0 R_AARCH64_NONE .data +# RELOC-NEXT: 0x0 R_{{.*}}_NONE .data # RELOC-NEXT: } # RELOC: Section ({{.*}}) .rela.nonalloc2 { -# RELOC-NEXT: 0x0 R_AARCH64_NONE .data 0x0 +# RELOC-NEXT: 0x0 R_{{.*}}_NONE .data 0x0 # RELOC-NEXT: } --- !ELF FileHeader: - Class: ELFCLASS64 + Class: ELFCLASS[[BITS=64]] Data: ELFDATA2LSB Type: ET_REL - Machine: EM_AARCH64 + Machine: EM_[[MACHINE]] Sections: - Name: .text Type: SHT_PROGBITS @@ -46,19 +61,19 @@ Sections: Info: .text Relocations: - Symbol: .data - Type: R_AARCH64_NONE + Type: R_[[MACHINE]]_NONE - Name: .rel.nonalloc1 Type: SHT_REL Info: .nonalloc1 Relocations: - Symbol: .data - Type: R_AARCH64_NONE + Type: R_[[MACHINE]]_NONE - Name: .rela.nonalloc2 Type: SHT_RELA Info: .nonalloc2 Relocations: - Symbol: .data - Type: R_AARCH64_NONE + Type: R_[[MACHINE]]_NONE Symbols: - Name: .data Type: STT_SECTION From 31868bef9568751f64a1e3855bb0ef5cd9e93041 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 15:11:50 -0800 Subject: [PATCH 017/316] [yaml2obj] Support R_PPC_* relocation types (cherry picked from commit c161b30f5c23ef9fe246d6bdf875c5a08cf2df9f) --- llvm/lib/ObjectYAML/ELFYAML.cpp | 3 + .../llvm-readobj/ELF/reloc-types-ppc.test | 163 ++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 llvm/test/tools/llvm-readobj/ELF/reloc-types-ppc.test diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp index d597148b98ab4..3d4cd4088e9fc 100644 --- a/llvm/lib/ObjectYAML/ELFYAML.cpp +++ b/llvm/lib/ObjectYAML/ELFYAML.cpp @@ -839,6 +839,9 @@ void ScalarEnumerationTraits::enumeration( case ELF::EM_CSKY: #include "llvm/BinaryFormat/ELFRelocs/CSKY.def" break; + case ELF::EM_PPC: +#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def" + break; case ELF::EM_PPC64: #include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def" break; diff --git a/llvm/test/tools/llvm-readobj/ELF/reloc-types-ppc.test b/llvm/test/tools/llvm-readobj/ELF/reloc-types-ppc.test new file mode 100644 index 0000000000000..594d2da6c387a --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/reloc-types-ppc.test @@ -0,0 +1,163 @@ +## Test that llvm-readobj shows proper relocation type +## names and values for ppc target. + +# RUN: yaml2obj %s -o %t-ppc.o +# RUN: llvm-readobj -r --expand-relocs %t-ppc.o | FileCheck %s + +# CHECK: Type: R_PPC_NONE (0) +# CHECK: Type: R_PPC_ADDR32 (1) +# CHECK: Type: R_PPC_ADDR24 (2) +# CHECK: Type: R_PPC_ADDR16 (3) +# CHECK: Type: R_PPC_ADDR16_LO (4) +# CHECK: Type: R_PPC_ADDR16_HI (5) +# CHECK: Type: R_PPC_ADDR16_HA (6) +# CHECK: Type: R_PPC_ADDR14 (7) +# CHECK: Type: R_PPC_ADDR14_BRTAKEN (8) +# CHECK: Type: R_PPC_ADDR14_BRNTAKEN (9) +# CHECK: Type: R_PPC_REL24 (10) +# CHECK: Type: R_PPC_REL14 (11) +# CHECK: Type: R_PPC_REL14_BRTAKEN (12) +# CHECK: Type: R_PPC_REL14_BRNTAKEN (13) +# CHECK: Type: R_PPC_GOT16 (14) +# CHECK: Type: R_PPC_GOT16_LO (15) +# CHECK: Type: R_PPC_GOT16_HI (16) +# CHECK: Type: R_PPC_GOT16_HA (17) +# CHECK: Type: R_PPC_PLTREL24 (18) +# CHECK: Type: R_PPC_COPY (19) +# CHECK: Type: R_PPC_GLOB_DAT (20) +# CHECK: Type: R_PPC_JMP_SLOT (21) +# CHECK: Type: R_PPC_RELATIVE (22) +# CHECK: Type: R_PPC_LOCAL24PC (23) +# CHECK: Type: R_PPC_UADDR32 (24) +# CHECK: Type: R_PPC_UADDR16 (25) +# CHECK: Type: R_PPC_REL32 (26) +# CHECK: Type: R_PPC_PLT32 (27) +# CHECK: Type: R_PPC_PLTREL32 (28) +# CHECK: Type: R_PPC_PLT16_LO (29) +# CHECK: Type: R_PPC_PLT16_HI (30) +# CHECK: Type: R_PPC_PLT16_HA (31) +# CHECK: Type: R_PPC_SDAREL16 (32) +# CHECK: Type: R_PPC_SECTOFF (33) +# CHECK: Type: R_PPC_SECTOFF_LO (34) +# CHECK: Type: R_PPC_SECTOFF_HI (35) +# CHECK: Type: R_PPC_SECTOFF_HA (36) +# CHECK: Type: R_PPC_ADDR30 (37) +# CHECK: Type: R_PPC_TLS (67) +# CHECK: Type: R_PPC_DTPMOD32 (68) +# CHECK: Type: R_PPC_TPREL16 (69) +# CHECK: Type: R_PPC_TPREL16_LO (70) +# CHECK: Type: R_PPC_TPREL16_HI (71) +# CHECK: Type: R_PPC_TPREL16_HA (72) +# CHECK: Type: R_PPC_TPREL32 (73) +# CHECK: Type: R_PPC_DTPREL16 (74) +# CHECK: Type: R_PPC_DTPREL16_LO (75) +# CHECK: Type: R_PPC_DTPREL16_HI (76) +# CHECK: Type: R_PPC_DTPREL16_HA (77) +# CHECK: Type: R_PPC_DTPREL32 (78) +# CHECK: Type: R_PPC_GOT_TLSGD16 (79) +# CHECK: Type: R_PPC_GOT_TLSGD16_LO (80) +# CHECK: Type: R_PPC_GOT_TLSGD16_HI (81) +# CHECK: Type: R_PPC_GOT_TLSGD16_HA (82) +# CHECK: Type: R_PPC_GOT_TLSLD16 (83) +# CHECK: Type: R_PPC_GOT_TLSLD16_LO (84) +# CHECK: Type: R_PPC_GOT_TLSLD16_HI (85) +# CHECK: Type: R_PPC_GOT_TLSLD16_HA (86) +# CHECK: Type: R_PPC_GOT_TPREL16 (87) +# CHECK: Type: R_PPC_GOT_TPREL16_LO (88) +# CHECK: Type: R_PPC_GOT_TPREL16_HI (89) +# CHECK: Type: R_PPC_GOT_TPREL16_HA (90) +# CHECK: Type: R_PPC_GOT_DTPREL16 (91) +# CHECK: Type: R_PPC_GOT_DTPREL16_LO (92) +# CHECK: Type: R_PPC_GOT_DTPREL16_HI (93) +# CHECK: Type: R_PPC_GOT_DTPREL16_HA (94) +# CHECK: Type: R_PPC_TLSGD (95) +# CHECK: Type: R_PPC_TLSLD (96) +# CHECK: Type: R_PPC_IRELATIVE (248) +# CHECK: Type: R_PPC_REL16 (249) +# CHECK: Type: R_PPC_REL16_LO (250) +# CHECK: Type: R_PPC_REL16_HI (251) +# CHECK: Type: R_PPC_REL16_HA (252) + +--- !ELF +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2MSB + Type: ET_REL + Machine: EM_PPC +Sections: + - Name: .rela.text + Type: SHT_RELA + Relocations: + - Type: R_PPC_NONE + - Type: R_PPC_ADDR32 + - Type: R_PPC_ADDR24 + - Type: R_PPC_ADDR16 + - Type: R_PPC_ADDR16_LO + - Type: R_PPC_ADDR16_HI + - Type: R_PPC_ADDR16_HA + - Type: R_PPC_ADDR14 + - Type: R_PPC_ADDR14_BRTAKEN + - Type: R_PPC_ADDR14_BRNTAKEN + - Type: R_PPC_REL24 + - Type: R_PPC_REL14 + - Type: R_PPC_REL14_BRTAKEN + - Type: R_PPC_REL14_BRNTAKEN + - Type: R_PPC_GOT16 + - Type: R_PPC_GOT16_LO + - Type: R_PPC_GOT16_HI + - Type: R_PPC_GOT16_HA + - Type: R_PPC_PLTREL24 + - Type: R_PPC_COPY + - Type: R_PPC_GLOB_DAT + - Type: R_PPC_JMP_SLOT + - Type: R_PPC_RELATIVE + - Type: R_PPC_LOCAL24PC + - Type: R_PPC_UADDR32 + - Type: R_PPC_UADDR16 + - Type: R_PPC_REL32 + - Type: R_PPC_PLT32 + - Type: R_PPC_PLTREL32 + - Type: R_PPC_PLT16_LO + - Type: R_PPC_PLT16_HI + - Type: R_PPC_PLT16_HA + - Type: R_PPC_SDAREL16 + - Type: R_PPC_SECTOFF + - Type: R_PPC_SECTOFF_LO + - Type: R_PPC_SECTOFF_HI + - Type: R_PPC_SECTOFF_HA + - Type: R_PPC_ADDR30 + - Type: R_PPC_TLS + - Type: R_PPC_DTPMOD32 + - Type: R_PPC_TPREL16 + - Type: R_PPC_TPREL16_LO + - Type: R_PPC_TPREL16_HI + - Type: R_PPC_TPREL16_HA + - Type: R_PPC_TPREL32 + - Type: R_PPC_DTPREL16 + - Type: R_PPC_DTPREL16_LO + - Type: R_PPC_DTPREL16_HI + - Type: R_PPC_DTPREL16_HA + - Type: R_PPC_DTPREL32 + - Type: R_PPC_GOT_TLSGD16 + - Type: R_PPC_GOT_TLSGD16_LO + - Type: R_PPC_GOT_TLSGD16_HI + - Type: R_PPC_GOT_TLSGD16_HA + - Type: R_PPC_GOT_TLSLD16 + - Type: R_PPC_GOT_TLSLD16_LO + - Type: R_PPC_GOT_TLSLD16_HI + - Type: R_PPC_GOT_TLSLD16_HA + - Type: R_PPC_GOT_TPREL16 + - Type: R_PPC_GOT_TPREL16_LO + - Type: R_PPC_GOT_TPREL16_HI + - Type: R_PPC_GOT_TPREL16_HA + - Type: R_PPC_GOT_DTPREL16 + - Type: R_PPC_GOT_DTPREL16_LO + - Type: R_PPC_GOT_DTPREL16_HI + - Type: R_PPC_GOT_DTPREL16_HA + - Type: R_PPC_TLSGD + - Type: R_PPC_TLSLD + - Type: R_PPC_IRELATIVE + - Type: R_PPC_REL16 + - Type: R_PPC_REL16_LO + - Type: R_PPC_REL16_HI + - Type: R_PPC_REL16_HA From ff421befd25827223952913d58e90d56e7779eb6 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 15:13:37 -0800 Subject: [PATCH 018/316] [ELF] Support R_PPC_NONE/R_PPC64_NONE in getImplicitAddend Similar to f457863ae345d2635026501f5383e0e625869639 (cherry picked from commit 53fc5d9b9a0110f097c6e9f7aa3bff3621eaf268) --- lld/ELF/Arch/PPC.cpp | 12 ++++++++++++ lld/ELF/Arch/PPC64.cpp | 12 ++++++++++++ lld/test/ELF/relocation-none.test | 8 ++++++++ 3 files changed, 32 insertions(+) diff --git a/lld/ELF/Arch/PPC.cpp b/lld/ELF/Arch/PPC.cpp index 97e4d66331381..315ac7df608d0 100644 --- a/lld/ELF/Arch/PPC.cpp +++ b/lld/ELF/Arch/PPC.cpp @@ -30,6 +30,7 @@ class PPC final : public TargetInfo { RelExpr getRelExpr(RelType type, const Symbol &s, const uint8_t *loc) const override; RelType getDynRel(RelType type) const override; + int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; void writeGotHeader(uint8_t *buf) const override; void writePltHeader(uint8_t *buf) const override { llvm_unreachable("should call writePPC32GlinkSection() instead"); @@ -275,6 +276,17 @@ RelType PPC::getDynRel(RelType type) const { return R_PPC_NONE; } +int64_t PPC::getImplicitAddend(const uint8_t *buf, RelType type) const { + switch (type) { + case R_PPC_NONE: + return 0; + default: + internalLinkerError(getErrorLocation(buf), + "cannot read addend for relocation " + toString(type)); + return 0; + } +} + static std::pair fromDTPREL(RelType type, uint64_t val) { uint64_t dtpBiasedVal = val - 0x8000; switch (type) { diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp index d9e4fc97ea0be..c083484f42804 100644 --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -363,6 +363,7 @@ class PPC64 final : public TargetInfo { RelExpr getRelExpr(RelType type, const Symbol &s, const uint8_t *loc) const override; RelType getDynRel(RelType type) const override; + int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; void writePltHeader(uint8_t *buf) const override; void writePlt(uint8_t *buf, const Symbol &sym, uint64_t pltEntryAddr) const override; @@ -1059,6 +1060,17 @@ RelType PPC64::getDynRel(RelType type) const { return R_PPC64_NONE; } +int64_t PPC64::getImplicitAddend(const uint8_t *buf, RelType type) const { + switch (type) { + case R_PPC64_NONE: + return 0; + default: + internalLinkerError(getErrorLocation(buf), + "cannot read addend for relocation " + toString(type)); + return 0; + } +} + void PPC64::writeGotHeader(uint8_t *buf) const { write64(buf, getPPC64TocBase()); } diff --git a/lld/test/ELF/relocation-none.test b/lld/test/ELF/relocation-none.test index a9ba6402ae8de..4e808cc67c0d1 100644 --- a/lld/test/ELF/relocation-none.test +++ b/lld/test/ELF/relocation-none.test @@ -15,6 +15,14 @@ # RUN: ld.lld -r %t.o -o %t # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s +# RUN: yaml2obj -DBITS=32 -DMACHINE=PPC %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + +# RUN: yaml2obj -DMACHINE=PPC64 %s -o %t.o +# RUN: ld.lld -r %t.o -o %t +# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s + # RUN: yaml2obj -DMACHINE=RISCV %s -o %t.o # RUN: ld.lld -r %t.o -o %t # RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s From 461fc8b4caabddde77d329333dfb21b7089f9d44 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 17:29:19 -0800 Subject: [PATCH 019/316] [Debuginfod] Fix curl_easy_init in -DLLVM_ENABLE_ASSERTIONS=off build after D112753 (cherry picked from commit 3dd2d4c0a239ce78421d51491456cb1a075ad2f3) --- llvm/lib/Debuginfod/HTTPClient.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Debuginfod/HTTPClient.cpp b/llvm/lib/Debuginfod/HTTPClient.cpp index 65f457933b92d..cba342c9b3439 100644 --- a/llvm/lib/Debuginfod/HTTPClient.cpp +++ b/llvm/lib/Debuginfod/HTTPClient.cpp @@ -156,7 +156,8 @@ HTTPClient::HTTPClient() { "Must call HTTPClient::initialize() at the beginning of main()."); if (Curl) return; - assert((Curl = curl_easy_init()) && "Curl could not be initialized."); + Curl = curl_easy_init(); + assert(Curl && "Curl could not be initialized"); // Set the callback hooks. curl_easy_setopt(Curl, CURLOPT_WRITEFUNCTION, curlWriteFunction); curl_easy_setopt(Curl, CURLOPT_HEADERFUNCTION, curlHeaderFunction); From a3b31d895b79140aeefeaaddd67b0403c7a0ec70 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 4 Feb 2022 17:32:00 -0800 Subject: [PATCH 020/316] [Debuginfod][test] Fix debuginfod.test to use %python instead of python after D112759 (cherry picked from commit 42f9ca55dd487580cfd32d4b803315d789442442) --- llvm/test/tools/llvm-debuginfod-find/debuginfod.test | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/test/tools/llvm-debuginfod-find/debuginfod.test b/llvm/test/tools/llvm-debuginfod-find/debuginfod.test index e38913b78351b..d1c9c693c0e4a 100644 --- a/llvm/test/tools/llvm-debuginfod-find/debuginfod.test +++ b/llvm/test/tools/llvm-debuginfod-find/debuginfod.test @@ -2,13 +2,13 @@ # RUN: rm -rf %t # RUN: mkdir %t # # Query the python server for artifacts -# RUN: DEBUGINFOD_CACHE_PATH=%t python %s --server-path %S/Inputs \ +# RUN: DEBUGINFOD_CACHE_PATH=%t %python %s --server-path %S/Inputs \ # RUN: --tool-cmd 'llvm-debuginfod-find --dump --executable abcdef' | \ # RUN: FileCheck %s --check-prefix=EXECUTABLE -# RUN: DEBUGINFOD_CACHE_PATH=%t python %s --server-path %S/Inputs \ +# RUN: DEBUGINFOD_CACHE_PATH=%t %python %s --server-path %S/Inputs \ # RUN: --tool-cmd 'llvm-debuginfod-find --dump --source=/directory/file.c abcdef' | \ # RUN: FileCheck %s --check-prefix=SOURCE -# RUN: DEBUGINFOD_CACHE_PATH=%t python %s --server-path %S/Inputs \ +# RUN: DEBUGINFOD_CACHE_PATH=%t %python %s --server-path %S/Inputs \ # RUN: --tool-cmd 'llvm-debuginfod-find --dump --debuginfo abcdef' | \ # RUN: FileCheck %s --check-prefix=DEBUGINFO From 190be5457c905ca55100927d1f5846cd30cee87d Mon Sep 17 00:00:00 2001 From: "Alex Xu (Hello71)" Date: Fri, 4 Feb 2022 19:20:30 -0800 Subject: [PATCH 021/316] [Driver] Default to -fno-math-errno for musl musl does not set errno in math functions: https://wiki.musl-libc.org/mathematical-library.html, https://git.musl-libc.org/cgit/musl/tree/include/math.h?id=cfdfd5ea3ce14c6abf7fb22a531f3d99518b5a1b#n26. Reviewed By: srhines, MaskRay Differential Revision: https://reviews.llvm.org/D116753 (cherry picked from commit 38449c98f3d33dffdaf7e1feeb9dfdcf63b5126b) --- clang/lib/Driver/ToolChains/Linux.cpp | 2 +- clang/test/Driver/fast-math.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp index af74b108e04ee..f85c04df4f6c9 100644 --- a/clang/lib/Driver/ToolChains/Linux.cpp +++ b/clang/lib/Driver/ToolChains/Linux.cpp @@ -687,7 +687,7 @@ bool Linux::IsAArch64OutlineAtomicsDefault(const ArgList &Args) const { } bool Linux::IsMathErrnoDefault() const { - if (getTriple().isAndroid()) + if (getTriple().isAndroid() || getTriple().isMusl()) return false; return Generic_ELF::IsMathErrnoDefault(); } diff --git a/clang/test/Driver/fast-math.c b/clang/test/Driver/fast-math.c index a66e9d0eca177..36ea8ecb52985 100644 --- a/clang/test/Driver/fast-math.c +++ b/clang/test/Driver/fast-math.c @@ -119,6 +119,8 @@ // RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s // RUN: %clang -### -target x86_64-linux-android -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: %clang -### -target x86_64-linux-musl -c %s 2>&1 \ +// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s // RUN: %clang -### -target amdgcn-amd-amdhsa -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s // RUN: %clang -### -target amdgcn-amd-amdpal -c %s 2>&1 \ From c7bca45103e360ed9cb695d3db519f0639c898d3 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sat, 5 Feb 2022 23:34:14 -0800 Subject: [PATCH 022/316] [ELF] Fix crash when an input is incompatible with a lazy object file The diagnostic is concise. It is ok because the case is rare. (cherry picked from commit bad1b7fbb0fec532f097ac59805562020f895962) --- lld/ELF/InputFiles.cpp | 11 +++++------ lld/test/ELF/incompatible-ar-first.s | 3 +++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp index b5510b3b27362..775999a5f534c 100644 --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -152,18 +152,17 @@ static bool isCompatible(InputFile *file) { return false; } - InputFile *existing; + InputFile *existing = nullptr; if (!objectFiles.empty()) existing = objectFiles[0]; else if (!sharedFiles.empty()) existing = sharedFiles[0]; else if (!bitcodeFiles.empty()) existing = bitcodeFiles[0]; - else - llvm_unreachable("Must have -m, OUTPUT_FORMAT or existing input file to " - "determine target emulation"); - - error(toString(file) + " is incompatible with " + toString(existing)); + std::string with; + if (existing) + with = " with " + toString(existing); + error(toString(file) + " is incompatible" + with); return false; } diff --git a/lld/test/ELF/incompatible-ar-first.s b/lld/test/ELF/incompatible-ar-first.s index e49171939513c..a82a55a39ed80 100644 --- a/lld/test/ELF/incompatible-ar-first.s +++ b/lld/test/ELF/incompatible-ar-first.s @@ -10,3 +10,6 @@ // * -m was not used. // CHECK: .a({{.*}}a.o) is incompatible with {{.*}}b.o +// RUN: not ld.lld --start-lib %ta.o --end-lib %tb.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK2 + +// CHECK2: {{.*}}b.o is incompatible{{$}} From 20ea9e379984f240d7135843baae6999abf3bf2b Mon Sep 17 00:00:00 2001 From: Maurice Heumann Date: Mon, 7 Feb 2022 11:01:33 +0100 Subject: [PATCH 023/316] In change https://reviews.llvm.org/D115456 on-demand TLS initialization for Microsoft CXX ABI was added. This mentions the change in the release notes. Differential revision: https://reviews.llvm.org/D117500 --- clang/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5cc53e9ec27b2..a58e3fcd4f42c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -158,6 +158,8 @@ Windows Support along with tools such as Live++ or Recode. Microsoft Edit and Continue isn't currently supported. +- Support for on-demand initialization of TLS variables was added. + C Language Changes in Clang --------------------------- From 02d5b112138e7e9f30dec685afb380c1b9593a84 Mon Sep 17 00:00:00 2001 From: "Yaxun (Sam) Liu" Date: Fri, 4 Feb 2022 18:18:14 -0500 Subject: [PATCH 024/316] [HIPSPV] Fix literals are mapped to Generic address space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This issue is an oversight in D108621. Literals in HIP are emitted as global constant variables with default address space which maps to Generic address space for HIPSPV. In SPIR-V such variables translate to OpVariable instructions with Generic storage class which are not legal. Fix by mapping literals to CrossWorkGroup address space. The literals are not mapped to UniformConstant because the “flat” pointers in HIP may reference them and “flat” pointers are modeled as Generic pointers in SPIR-V. In SPIR-V/OpenCL UniformConstant pointers may not be casted to Generic. Patch by: Henry Linjamäki Reviewed by: Yaxun Liu Differential Revision: https://reviews.llvm.org/D118876 --- clang/lib/CodeGen/CodeGenModule.cpp | 8 ++++++++ clang/test/CodeGenHIP/hipspv-addr-spaces.cpp | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 2346176a15628..29806b65e984e 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -4381,6 +4381,14 @@ LangAS CodeGenModule::GetGlobalConstantAddressSpace() const { return LangAS::opencl_constant; if (LangOpts.SYCLIsDevice) return LangAS::sycl_global; + if (LangOpts.HIP && LangOpts.CUDAIsDevice && getTriple().isSPIRV()) + // For HIPSPV map literals to cuda_device (maps to CrossWorkGroup in SPIR-V) + // instead of default AS (maps to Generic in SPIR-V). Otherwise, we end up + // with OpVariable instructions with Generic storage class which is not + // allowed (SPIR-V V1.6 s3.42.8). Also, mapping literals to SPIR-V + // UniformConstant storage class is not viable as pointers to it may not be + // casted to Generic pointers which are used to model HIP's "flat" pointers. + return LangAS::cuda_device; if (auto AS = getTarget().getConstantAddressSpace()) return AS.getValue(); return LangAS::Default; diff --git a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp index 8f56f2104ecbd..bde360eec8cd9 100644 --- a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp +++ b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp @@ -22,6 +22,9 @@ __device__ struct foo_t { int* pi; } foo; +// Check literals are placed in address space 1 (CrossWorkGroup/__global). +// CHECK: @.str ={{.*}} unnamed_addr addrspace(1) constant + // CHECK: define{{.*}} spir_func noundef i32 addrspace(4)* @_Z3barPi(i32 addrspace(4)* __device__ int* bar(int *x) { return x; @@ -44,3 +47,8 @@ __device__ int* baz_s() { // CHECK: ret i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @s to i32 addrspace(4)* return &s; } + +// CHECK: define{{.*}} spir_func noundef i8 addrspace(4)* @_Z3quzv() +__device__ const char* quz() { + return "abc"; +} From 923b67e36917352c1ca1fb1e339dbe5acdc97ddf Mon Sep 17 00:00:00 2001 From: Mariusz Ceier Date: Mon, 7 Feb 2022 09:20:03 -0800 Subject: [PATCH 025/316] Fix lld standalone build lld/ELF/OutputSections.cpp includes llvm/Config/config.h for LLVM_ENABLE_ZLIB definition, but llvm/Config/config.h doesn't exist in standalone build. To fix this, this patch moves LLVM_ENABLE_ZLIB from config.h to llvm-config.h and updates OutputSections.cpp to include llvm-config.h instead of config.h Reviewed By: MaskRay, mgorny Differential Revision: https://reviews.llvm.org/D119058 (cherry picked from commit e8bff9ae54a55b4dbfeb6ba55f723abbd81bf494) --- lld/ELF/OutputSections.cpp | 2 +- llvm/include/llvm/Config/config.h.cmake | 3 --- llvm/include/llvm/Config/llvm-config.h.cmake | 3 +++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/lld/ELF/OutputSections.cpp b/lld/ELF/OutputSections.cpp index 241b3ea3b4188..53cdcee1bfe86 100644 --- a/lld/ELF/OutputSections.cpp +++ b/lld/ELF/OutputSections.cpp @@ -16,7 +16,7 @@ #include "lld/Common/Memory.h" #include "lld/Common/Strings.h" #include "llvm/BinaryFormat/Dwarf.h" -#include "llvm/Config/config.h" // LLVM_ENABLE_ZLIB +#include "llvm/Config/llvm-config.h" // LLVM_ENABLE_ZLIB #include "llvm/Support/MD5.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Parallel.h" diff --git a/llvm/include/llvm/Config/config.h.cmake b/llvm/include/llvm/Config/config.h.cmake index 064d2f27dc18b..2098c249e20db 100644 --- a/llvm/include/llvm/Config/config.h.cmake +++ b/llvm/include/llvm/Config/config.h.cmake @@ -300,9 +300,6 @@ /* Doesn't use `cmakedefine` because it is allowed to be empty. */ #define LLVM_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}" -/* Define if zlib compression is available */ -#cmakedefine01 LLVM_ENABLE_ZLIB - /* Define if overriding target triple is enabled */ #cmakedefine LLVM_TARGET_TRIPLE_ENV "${LLVM_TARGET_TRIPLE_ENV}" diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index ec18b40fe04d9..839a1c7c1984f 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -88,6 +88,9 @@ /* Define if we have curl and want to use it */ #cmakedefine LLVM_ENABLE_CURL ${LLVM_ENABLE_CURL} +/* Define if zlib compression is available */ +#cmakedefine01 LLVM_ENABLE_ZLIB + /* Define if LLVM was built with a dependency to the libtensorflow dynamic library */ #cmakedefine LLVM_HAVE_TF_API From 1e7adacd10a465af4e4856e23b7bfb9e0b5c4d76 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Mon, 7 Feb 2022 12:30:32 -0500 Subject: [PATCH 026/316] [libc++] Mention in the release notes --- libcxx/docs/ReleaseNotes.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index a33c6621d448d..dd8d2648ca019 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -47,6 +47,12 @@ New Features header by using ``-DLIBCXX_ENABLE_INCOMPLETE_FEATURES=ON`` when configuring their build. +- More parts of ```` have been implemented. Since we still expect to make + some API and ABI breaking changes, those are disabled by default. However, + vendors that wish to enable ```` in their distribution may do so + by defining ``-DLIBCXX_ENABLE_INCOMPLETE_FEATURES=ON`` when configuring + their build. + - There's a new CMake option ``LIBCXX_ENABLE_UNICODE`` to disable Unicode support in the ```` header. This only affects the estimation of the output width of the format functions. From c0fde7580aac12143d63291af452e261808dc4ec Mon Sep 17 00:00:00 2001 From: Sam James Date: Mon, 7 Feb 2022 09:37:08 -0800 Subject: [PATCH 027/316] [libunwind] Define _Unwind_Backtrace for powerpc, sparc Add SPARC to the list of platforms for which we provide a full unwind implementation which leads to _Unwind_Backtrace being defined within libunwind.so. Likewise for PPC (see D118320 for background). Reviewed By: #libunwind, MaskRay, Arfrever Differential Revision: https://reviews.llvm.org/D119068 (cherry picked from commit 022011078054c133777e1c3f8ea927bdef97f1fc) --- libunwind/src/config.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/libunwind/src/config.h b/libunwind/src/config.h index 560edda04eaa9..5ae1604f657dd 100644 --- a/libunwind/src/config.h +++ b/libunwind/src/config.h @@ -109,13 +109,10 @@ #define _LIBUNWIND_SUPPORT_FRAME_APIS #endif -#if defined(__i386__) || defined(__x86_64__) || \ - defined(__ppc__) || defined(__ppc64__) || defined(__powerpc64__) || \ - (!defined(__APPLE__) && defined(__arm__)) || \ - defined(__aarch64__) || \ - defined(__mips__) || \ - defined(__riscv) || \ - defined(__hexagon__) +#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \ + (!defined(__APPLE__) && defined(__arm__)) || defined(__aarch64__) || \ + defined(__mips__) || defined(__riscv) || defined(__hexagon__) || \ + defined(__sparc__) #if !defined(_LIBUNWIND_BUILD_SJLJ_APIS) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif From 2150816e666ac0e7f9545f016457e82af83bcad2 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Mon, 7 Feb 2022 04:04:39 -0500 Subject: [PATCH 028/316] [Driver][OpenBSD] -r: imply -nostdlib like GCC Similar to D116843 for Gnu.cpp Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D119071 (cherry picked from commit 1831cbd9d4174a93d4017e510ecf0f840af5f7d6) --- clang/lib/Driver/ToolChains/OpenBSD.cpp | 9 ++++++--- clang/test/Driver/openbsd.c | 5 +++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp b/clang/lib/Driver/ToolChains/OpenBSD.cpp index 96abac57764f7..bcd54bedfa897 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.cpp +++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp @@ -160,7 +160,8 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, assert(Output.isNothing() && "Invalid output."); } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { const char *crt0 = nullptr; const char *crtbegin = nullptr; if (!Args.hasArg(options::OPT_shared)) { @@ -191,7 +192,8 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, bool NeedsXRayDeps = addXRayRuntime(ToolChain, Args, CmdArgs); AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA); - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs, + options::OPT_r)) { // Use the static OpenMP runtime with -static-openmp bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && !Args.hasArg(options::OPT_static); @@ -234,7 +236,8 @@ void openbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-lcompiler_rt"); } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { const char *crtend = nullptr; if (!Args.hasArg(options::OPT_shared)) crtend = "crtend.o"; diff --git a/clang/test/Driver/openbsd.c b/clang/test/Driver/openbsd.c index c2ffe2a0397cd..d6d5ae994e67e 100644 --- a/clang/test/Driver/openbsd.c +++ b/clang/test/Driver/openbsd.c @@ -40,8 +40,9 @@ // RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s // RUN: %clang -no-canonical-prefixes -target mips64el-unknown-openbsd %s -### 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s -// CHECK-LD-R: clang{{.*}}" "-cc1" "-triple" "i686-pc-openbsd" -// CHECK-LD-R: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "-r" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" +// CHECK-LD-R: "-r" +// CHECK-LD-R-NOT: "-l +// CHECK-LD-R-NOT: crt{{[^.]+}}.o // CHECK-LD-S: clang{{.*}}" "-cc1" "-triple" "i686-pc-openbsd" // CHECK-LD-S: ld{{.*}}" "-e" "__start" "--eh-frame-hdr" "-Bdynamic" "-dynamic-linker" "{{.*}}ld.so" "-o" "a.out" "{{.*}}crt0.o" "{{.*}}crtbegin.o" "-L{{.*}}" "-s" "{{.*}}.o" "-lcompiler_rt" "-lc" "-lcompiler_rt" "{{.*}}crtend.o" // CHECK-LD-T: clang{{.*}}" "-cc1" "-triple" "i686-pc-openbsd" From ec05ccbc47156314217916b963d8bd9f664c37f8 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Sat, 5 Feb 2022 13:08:26 -0800 Subject: [PATCH 029/316] [libunwind] [sparc] Add SPARCv9 support Adds libunwind support for SPARCv9 (aka sparc64). This is a rebase of @kettenis' patch D32450, which I created (with his permission) because the original review has become inactive. The changes are of a cosmetic nature to make it fit better with the new code style, and to reuse the existing SPARCv8 code, whenever possible. Please let me know if I posted this on the wrong place. Also, the summary of the original review is reproduced below: > This adds unwinder support for 64-bit SPARC (aka SPARCv9). The implementation was done on OpenBSD/sparc64, so it takes StackGhost into account: > > https://www.usenix.org/legacy/publications/library/proceedings/sec01/full_papers/frantzen/frantzen_html/index.html > > Since StackGhost xor's return addresses with a random cookie before storing them on the stack, the unwinder has to do some extra work to recover those. This is done by introducing a new kRegisterInCFADecrypt "location" type that is used to implement the DW_CFA_GNU_window_save opcode. That implementation is SPARC-specific, but should work for 32-bit SPARC as well. DW_CFA_GNU_window_save is only ever generated on SPARC as far as I know. Co-authored-by: Mark Kettenis Reviewed By: #libunwind, thesamesam, MaskRay, Arfrever Differential Revision: https://reviews.llvm.org/D116857 (cherry picked from commit 2b9554b8850192bdd86c02eb671de1d866df8d87) --- libunwind/include/__libunwind_config.h | 8 ++ libunwind/src/DwarfInstructions.hpp | 19 +++ libunwind/src/DwarfParser.hpp | 27 +++- libunwind/src/Registers.hpp | 186 +++++++++++++++++++++++++ libunwind/src/UnwindCursor.hpp | 16 +++ libunwind/src/UnwindRegistersRestore.S | 47 +++++++ libunwind/src/UnwindRegistersSave.S | 58 ++++++++ libunwind/src/libunwind.cpp | 2 + 8 files changed, 362 insertions(+), 1 deletion(-) diff --git a/libunwind/include/__libunwind_config.h b/libunwind/include/__libunwind_config.h index 67527d9da4042..e87bcf40034f3 100644 --- a/libunwind/include/__libunwind_config.h +++ b/libunwind/include/__libunwind_config.h @@ -23,6 +23,7 @@ #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31 +#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64 31 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE 143 @@ -125,6 +126,12 @@ # error "Unsupported MIPS ABI and/or environment" # endif # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS +#elif defined(__sparc__) && defined(__arch64__) +#define _LIBUNWIND_TARGET_SPARC64 1 +#define _LIBUNWIND_HIGHEST_DWARF_REGISTER \ + _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64 +#define _LIBUNWIND_CONTEXT_SIZE 33 +#define _LIBUNWIND_CURSOR_SIZE 45 # elif defined(__sparc__) #define _LIBUNWIND_TARGET_SPARC 1 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC @@ -165,6 +172,7 @@ # define _LIBUNWIND_TARGET_MIPS_O32 1 # define _LIBUNWIND_TARGET_MIPS_NEWABI 1 # define _LIBUNWIND_TARGET_SPARC 1 +# define _LIBUNWIND_TARGET_SPARC64 1 # define _LIBUNWIND_TARGET_HEXAGON 1 # define _LIBUNWIND_TARGET_RISCV 1 # define _LIBUNWIND_TARGET_VE 1 diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp index 1c50941680b33..c1a241c55ce66 100644 --- a/libunwind/src/DwarfInstructions.hpp +++ b/libunwind/src/DwarfInstructions.hpp @@ -74,6 +74,13 @@ class DwarfInstructions { } }; +template +auto getSparcWCookie(const R &r, int) -> decltype(r.getWCookie()) { + return r.getWCookie(); +} +template uint64_t getSparcWCookie(const R &, long) { + return 0; +} template typename A::pint_t DwarfInstructions::getSavedRegister( @@ -83,6 +90,10 @@ typename A::pint_t DwarfInstructions::getSavedRegister( case CFI_Parser::kRegisterInCFA: return (pint_t)addressSpace.getRegister(cfa + (pint_t)savedReg.value); + case CFI_Parser::kRegisterInCFADecrypt: // sparc64 specific + return addressSpace.getP(cfa + (pint_t)savedReg.value) ^ + getSparcWCookie(registers, 0); + case CFI_Parser::kRegisterAtExpression: return (pint_t)addressSpace.getRegister(evaluateExpression( (pint_t)savedReg.value, addressSpace, registers, cfa)); @@ -124,6 +135,7 @@ double DwarfInstructions::getSavedFloatRegister( case CFI_Parser::kRegisterIsExpression: case CFI_Parser::kRegisterUnused: case CFI_Parser::kRegisterOffsetFromCFA: + case CFI_Parser::kRegisterInCFADecrypt: // FIX ME break; } @@ -148,6 +160,7 @@ v128 DwarfInstructions::getSavedVectorRegister( case CFI_Parser::kRegisterUndefined: case CFI_Parser::kRegisterOffsetFromCFA: case CFI_Parser::kRegisterInRegister: + case CFI_Parser::kRegisterInCFADecrypt: // FIX ME break; } @@ -266,6 +279,12 @@ int DwarfInstructions::stepWithDwarf(A &addressSpace, pint_t pc, } #endif +#if defined(_LIBUNWIND_TARGET_SPARC64) + // Skip call site instruction and delay slot. + if (R::getArch() == REGISTERS_SPARC64) + returnAddress += 8; +#endif + #if defined(_LIBUNWIND_TARGET_PPC64) #define PPC64_ELFV1_R2_LOAD_INST_ENCODING 0xe8410028u // ld r2,40(r1) #define PPC64_ELFV1_R2_OFFSET 40 diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp index 8630178777e34..b5a53166fc3f6 100644 --- a/libunwind/src/DwarfParser.hpp +++ b/libunwind/src/DwarfParser.hpp @@ -71,6 +71,7 @@ class CFI_Parser { kRegisterUnused, kRegisterUndefined, kRegisterInCFA, + kRegisterInCFADecrypt, // sparc64 specific kRegisterOffsetFromCFA, kRegisterInRegister, kRegisterAtExpression, @@ -733,7 +734,8 @@ bool CFI_Parser::parseFDEInstructions(A &addressSpace, "DW_CFA_GNU_negative_offset_extended(%" PRId64 ")\n", offset); break; -#if defined(_LIBUNWIND_TARGET_AARCH64) || defined(_LIBUNWIND_TARGET_SPARC) +#if defined(_LIBUNWIND_TARGET_AARCH64) || defined(_LIBUNWIND_TARGET_SPARC) || \ + defined(_LIBUNWIND_TARGET_SPARC64) // The same constant is used to represent different instructions on // AArch64 (negate_ra_state) and SPARC (window_save). static_assert(DW_CFA_AARCH64_negate_ra_state == DW_CFA_GNU_window_save, @@ -767,8 +769,31 @@ bool CFI_Parser::parseFDEInstructions(A &addressSpace, } break; #endif + +#if defined(_LIBUNWIND_TARGET_SPARC64) + // case DW_CFA_GNU_window_save: + case REGISTERS_SPARC64: + // Don't save %o0-%o7 on sparc64. + // https://reviews.llvm.org/D32450#736405 + + for (reg = UNW_SPARC_L0; reg <= UNW_SPARC_I7; reg++) { + if (reg == UNW_SPARC_I7) + results->setRegister( + reg, kRegisterInCFADecrypt, + static_cast((reg - UNW_SPARC_L0) * sizeof(pint_t)), + initialState); + else + results->setRegister( + reg, kRegisterInCFA, + static_cast((reg - UNW_SPARC_L0) * sizeof(pint_t)), + initialState); + } + _LIBUNWIND_TRACE_DWARF("DW_CFA_GNU_window_save\n"); + break; +#endif } break; + #else (void)arch; #endif diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp index 373d9e49018e0..cbc3876d672e1 100644 --- a/libunwind/src/Registers.hpp +++ b/libunwind/src/Registers.hpp @@ -35,6 +35,7 @@ enum { REGISTERS_MIPS_O32, REGISTERS_MIPS_NEWABI, REGISTERS_SPARC, + REGISTERS_SPARC64, REGISTERS_HEXAGON, REGISTERS_RISCV, REGISTERS_VE, @@ -3586,6 +3587,191 @@ inline const char *Registers_sparc::getRegisterName(int regNum) { } #endif // _LIBUNWIND_TARGET_SPARC +#if defined(_LIBUNWIND_TARGET_SPARC64) +/// Registers_sparc64 holds the register state of a thread in a 64-bit +/// sparc process. +class _LIBUNWIND_HIDDEN Registers_sparc64 { +public: + Registers_sparc64() = default; + Registers_sparc64(const void *registers); + + bool validRegister(int num) const; + uint64_t getRegister(int num) const; + void setRegister(int num, uint64_t value); + bool validFloatRegister(int num) const; + double getFloatRegister(int num) const; + void setFloatRegister(int num, double value); + bool validVectorRegister(int num) const; + v128 getVectorRegister(int num) const; + void setVectorRegister(int num, v128 value); + const char *getRegisterName(int num); + void jumpto(); + static int lastDwarfRegNum() { + return _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64; + } + static int getArch() { return REGISTERS_SPARC64; } + + uint64_t getSP() const { return _registers.__regs[UNW_SPARC_O6] + 2047; } + void setSP(uint64_t value) { _registers.__regs[UNW_SPARC_O6] = value - 2047; } + uint64_t getIP() const { return _registers.__regs[UNW_SPARC_O7]; } + void setIP(uint64_t value) { _registers.__regs[UNW_SPARC_O7] = value; } + uint64_t getWCookie() const { return _wcookie; } + +private: + struct sparc64_thread_state_t { + uint64_t __regs[32]; + }; + + sparc64_thread_state_t _registers{}; + uint64_t _wcookie = 0; +}; + +inline Registers_sparc64::Registers_sparc64(const void *registers) { + static_assert((check_fit::does_fit), + "sparc64 registers do not fit into unw_context_t"); + memcpy(&_registers, registers, sizeof(_registers)); + memcpy(&_wcookie, + static_cast(registers) + sizeof(_registers), + sizeof(_wcookie)); +} + +inline bool Registers_sparc64::validRegister(int regNum) const { + if (regNum == UNW_REG_IP) + return true; + if (regNum == UNW_REG_SP) + return true; + if (regNum < 0) + return false; + if (regNum <= UNW_SPARC_I7) + return true; + return false; +} + +inline uint64_t Registers_sparc64::getRegister(int regNum) const { + if (regNum >= UNW_SPARC_G0 && regNum <= UNW_SPARC_I7) + return _registers.__regs[regNum]; + + switch (regNum) { + case UNW_REG_IP: + return _registers.__regs[UNW_SPARC_O7]; + case UNW_REG_SP: + return _registers.__regs[UNW_SPARC_O6] + 2047; + } + _LIBUNWIND_ABORT("unsupported sparc64 register"); +} + +inline void Registers_sparc64::setRegister(int regNum, uint64_t value) { + if (regNum >= UNW_SPARC_G0 && regNum <= UNW_SPARC_I7) { + _registers.__regs[regNum] = value; + return; + } + + switch (regNum) { + case UNW_REG_IP: + _registers.__regs[UNW_SPARC_O7] = value; + return; + case UNW_REG_SP: + _registers.__regs[UNW_SPARC_O6] = value - 2047; + return; + } + _LIBUNWIND_ABORT("unsupported sparc64 register"); +} + +inline bool Registers_sparc64::validFloatRegister(int) const { return false; } + +inline double Registers_sparc64::getFloatRegister(int) const { + _LIBUNWIND_ABORT("no sparc64 float registers"); +} + +inline void Registers_sparc64::setFloatRegister(int, double) { + _LIBUNWIND_ABORT("no sparc64 float registers"); +} + +inline bool Registers_sparc64::validVectorRegister(int) const { return false; } + +inline v128 Registers_sparc64::getVectorRegister(int) const { + _LIBUNWIND_ABORT("no sparc64 vector registers"); +} + +inline void Registers_sparc64::setVectorRegister(int, v128) { + _LIBUNWIND_ABORT("no sparc64 vector registers"); +} + +inline const char *Registers_sparc64::getRegisterName(int regNum) { + switch (regNum) { + case UNW_REG_IP: + return "pc"; + case UNW_SPARC_G0: + return "g0"; + case UNW_SPARC_G1: + return "g1"; + case UNW_SPARC_G2: + return "g2"; + case UNW_SPARC_G3: + return "g3"; + case UNW_SPARC_G4: + return "g4"; + case UNW_SPARC_G5: + return "g5"; + case UNW_SPARC_G6: + return "g6"; + case UNW_SPARC_G7: + return "g7"; + case UNW_SPARC_O0: + return "o0"; + case UNW_SPARC_O1: + return "o1"; + case UNW_SPARC_O2: + return "o2"; + case UNW_SPARC_O3: + return "o3"; + case UNW_SPARC_O4: + return "o4"; + case UNW_SPARC_O5: + return "o5"; + case UNW_REG_SP: + case UNW_SPARC_O6: + return "o6"; + case UNW_SPARC_O7: + return "o7"; + case UNW_SPARC_L0: + return "l0"; + case UNW_SPARC_L1: + return "l1"; + case UNW_SPARC_L2: + return "l2"; + case UNW_SPARC_L3: + return "l3"; + case UNW_SPARC_L4: + return "l4"; + case UNW_SPARC_L5: + return "l5"; + case UNW_SPARC_L6: + return "l6"; + case UNW_SPARC_L7: + return "l7"; + case UNW_SPARC_I0: + return "i0"; + case UNW_SPARC_I1: + return "i1"; + case UNW_SPARC_I2: + return "i2"; + case UNW_SPARC_I3: + return "i3"; + case UNW_SPARC_I4: + return "i4"; + case UNW_SPARC_I5: + return "i5"; + case UNW_SPARC_I6: + return "i6"; + case UNW_SPARC_I7: + return "i7"; + default: + return "unknown register"; + } +} +#endif // _LIBUNWIND_TARGET_SPARC64 + #if defined(_LIBUNWIND_TARGET_HEXAGON) /// Registers_hexagon holds the register state of a thread in a Hexagon QDSP6 /// process. diff --git a/libunwind/src/UnwindCursor.hpp b/libunwind/src/UnwindCursor.hpp index c400fdf33d8a9..1ca842f33aa51 100644 --- a/libunwind/src/UnwindCursor.hpp +++ b/libunwind/src/UnwindCursor.hpp @@ -1032,6 +1032,10 @@ class UnwindCursor : public AbstractUnwindCursor{ int stepWithCompactEncoding(Registers_sparc &) { return UNW_EINVAL; } #endif +#if defined(_LIBUNWIND_TARGET_SPARC64) + int stepWithCompactEncoding(Registers_sparc64 &) { return UNW_EINVAL; } +#endif + #if defined (_LIBUNWIND_TARGET_RISCV) int stepWithCompactEncoding(Registers_riscv &) { return UNW_EINVAL; @@ -1104,6 +1108,12 @@ class UnwindCursor : public AbstractUnwindCursor{ bool compactSaysUseDwarf(Registers_sparc &, uint32_t *) const { return true; } #endif +#if defined(_LIBUNWIND_TARGET_SPARC64) + bool compactSaysUseDwarf(Registers_sparc64 &, uint32_t *) const { + return true; + } +#endif + #if defined (_LIBUNWIND_TARGET_RISCV) bool compactSaysUseDwarf(Registers_riscv &, uint32_t *) const { return true; @@ -1182,6 +1192,12 @@ class UnwindCursor : public AbstractUnwindCursor{ compact_unwind_encoding_t dwarfEncoding(Registers_sparc &) const { return 0; } #endif +#if defined(_LIBUNWIND_TARGET_SPARC64) + compact_unwind_encoding_t dwarfEncoding(Registers_sparc64 &) const { + return 0; + } +#endif + #if defined (_LIBUNWIND_TARGET_RISCV) compact_unwind_encoding_t dwarfEncoding(Registers_riscv &) const { return 0; diff --git a/libunwind/src/UnwindRegistersRestore.S b/libunwind/src/UnwindRegistersRestore.S index f3d9dd31683e4..1df97f5fc41c4 100644 --- a/libunwind/src/UnwindRegistersRestore.S +++ b/libunwind/src/UnwindRegistersRestore.S @@ -1062,6 +1062,53 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv) ld $4, (8 * 4)($4) .set pop +#elif defined(__sparc__) && defined(__arch64__) + +DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind17Registers_sparc646jumptoEv) +// +// void libunwind::Registers_sparc64::jumpto() +// +// On entry: +// thread_state pointer is in %o0 +// + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch + .register %g7, #scratch + flushw + ldx [%o0 + 0x08], %g1 + ldx [%o0 + 0x10], %g2 + ldx [%o0 + 0x18], %g3 + ldx [%o0 + 0x20], %g4 + ldx [%o0 + 0x28], %g5 + ldx [%o0 + 0x30], %g6 + ldx [%o0 + 0x38], %g7 + ldx [%o0 + 0x48], %o1 + ldx [%o0 + 0x50], %o2 + ldx [%o0 + 0x58], %o3 + ldx [%o0 + 0x60], %o4 + ldx [%o0 + 0x68], %o5 + ldx [%o0 + 0x70], %o6 + ldx [%o0 + 0x78], %o7 + ldx [%o0 + 0x80], %l0 + ldx [%o0 + 0x88], %l1 + ldx [%o0 + 0x90], %l2 + ldx [%o0 + 0x98], %l3 + ldx [%o0 + 0xa0], %l4 + ldx [%o0 + 0xa8], %l5 + ldx [%o0 + 0xb0], %l6 + ldx [%o0 + 0xb8], %l7 + ldx [%o0 + 0xc0], %i0 + ldx [%o0 + 0xc8], %i1 + ldx [%o0 + 0xd0], %i2 + ldx [%o0 + 0xd8], %i3 + ldx [%o0 + 0xe0], %i4 + ldx [%o0 + 0xe8], %i5 + ldx [%o0 + 0xf0], %i6 + ldx [%o0 + 0xf8], %i7 + jmp %o7 + ldx [%o0 + 0x40], %o0 + #elif defined(__sparc__) // diff --git a/libunwind/src/UnwindRegistersSave.S b/libunwind/src/UnwindRegistersSave.S index 7af5c9d154fb3..9566bb0335fee 100644 --- a/libunwind/src/UnwindRegistersSave.S +++ b/libunwind/src/UnwindRegistersSave.S @@ -999,6 +999,64 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) jumpr r31 +#elif defined(__sparc__) && defined(__arch64__) + +# +# extern int __unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in %o0 +# +DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) + .register %g2, #scratch + .register %g3, #scratch + .register %g6, #scratch + .register %g7, #scratch + stx %g1, [%o0 + 0x08] + stx %g2, [%o0 + 0x10] + stx %g3, [%o0 + 0x18] + stx %g4, [%o0 + 0x20] + stx %g5, [%o0 + 0x28] + stx %g6, [%o0 + 0x30] + stx %g7, [%o0 + 0x38] + stx %o0, [%o0 + 0x40] + stx %o1, [%o0 + 0x48] + stx %o2, [%o0 + 0x50] + stx %o3, [%o0 + 0x58] + stx %o4, [%o0 + 0x60] + stx %o5, [%o0 + 0x68] + stx %o6, [%o0 + 0x70] + stx %o7, [%o0 + 0x78] + stx %l0, [%o0 + 0x80] + stx %l1, [%o0 + 0x88] + stx %l2, [%o0 + 0x90] + stx %l3, [%o0 + 0x98] + stx %l4, [%o0 + 0xa0] + stx %l5, [%o0 + 0xa8] + stx %l6, [%o0 + 0xb0] + stx %l7, [%o0 + 0xb8] + stx %i0, [%o0 + 0xc0] + stx %i1, [%o0 + 0xc8] + stx %i2, [%o0 + 0xd0] + stx %i3, [%o0 + 0xd8] + stx %i4, [%o0 + 0xe0] + stx %i5, [%o0 + 0xe8] + stx %i6, [%o0 + 0xf0] + stx %i7, [%o0 + 0xf8] + + # save StackGhost cookie + mov %i7, %g4 + save %sp, -176, %sp + # register window flush necessary even without StackGhost + flushw + restore + ldx [%sp + 2047 + 0x78], %g5 + xor %g4, %g5, %g4 + stx %g4, [%o0 + 0x100] + retl + # return UNW_ESUCCESS + clr %o0 + #elif defined(__sparc__) # diff --git a/libunwind/src/libunwind.cpp b/libunwind/src/libunwind.cpp index ef48cbe860c7d..03f8b75b5bba4 100644 --- a/libunwind/src/libunwind.cpp +++ b/libunwind/src/libunwind.cpp @@ -67,6 +67,8 @@ _LIBUNWIND_HIDDEN int __unw_init_local(unw_cursor_t *cursor, # define REGISTER_KIND Registers_mips_newabi #elif defined(__mips__) # warning The MIPS architecture is not supported with this ABI and environment! +#elif defined(__sparc__) && defined(__arch64__) +#define REGISTER_KIND Registers_sparc64 #elif defined(__sparc__) # define REGISTER_KIND Registers_sparc #elif defined(__riscv) From 592367ab7ea8c70eb26f2a6a7ddeb05b50322545 Mon Sep 17 00:00:00 2001 From: mydeveloperday Date: Thu, 3 Feb 2022 18:36:56 +0000 Subject: [PATCH 030/316] [clang-format] regression from clang-format v13 https://github.com/llvm/llvm-project/issues/53567 The following source ``` namespace A { template struct Foo { void foo() { std::cout << "Bar"; } }; // namespace A ``` is incorrectly formatted as: ``` namespace A { template struct Foo{void foo(){std::cout << "Bar"; } } ; // namespace A ``` This looks to be caused by https://github.com/llvm/llvm-project/commit/5c2e7c9ca043d92bed75b08e653fb47c384edd13 Reviewed By: curdeius Differential Revision: https://reviews.llvm.org/D118911 (cherry picked from commit 23fc20e06c088acff81a06ad546a848bee083051) --- clang/lib/Format/UnwrappedLineParser.cpp | 3 ++- clang/unittests/Format/FormatTest.cpp | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 6426791284090..2e2293c6d58bd 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -3102,7 +3102,8 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { } if (FormatTok->is(tok::l_square)) { FormatToken *Previous = FormatTok->Previous; - if (!Previous || Previous->isNot(tok::r_paren)) { + if (!Previous || + !(Previous->is(tok::r_paren) || Previous->isTypeOrIdentifier())) { // Don't try parsing a lambda if we had a closing parenthesis before, // it was probably a pointer to an array: int (*)[]. if (!tryToParseLambda()) diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 005e2d6a7b559..136a25fa89468 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -23638,6 +23638,7 @@ TEST_F(FormatTest, ShortTemplatedArgumentLists) { verifyFormat("struct Y<[] { return 0; }> {};", Style); verifyFormat("struct Z : X {};", Style); + verifyFormat("template struct Foo {};", Style); } TEST_F(FormatTest, RemoveBraces) { From b391c02561bc14e7b2c761dcfff08ea621158acc Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Tue, 1 Feb 2022 19:19:20 +0000 Subject: [PATCH 031/316] Re-apply 3fab2d138e30, now with a triple added Was reverted in 1c1b670a73a9 as it broke all non-x86 bots. Original commit message: [DebugInfo][InstrRef] Add a max-stack-slots-to-track cut-out In certain circumstances with things like autogenerated code and asan, you can end up with thousands of Values live at the same time, causing a large working set and a lot of information spilled to the stack. Unfortunately InstrRefBasedLDV doesn't cope well with this and consumes a lot of memory when there are many many stack slots. See the reproducer in D116821. It seems very unlikely that a developer would be able to reason about hundreds of live named local variables at the same time, so a huge working set and many stack slots is an indicator that we're likely analysing autogenerated or instrumented code. In those cases: gracefully degrade by setting an upper bound on the amount of stack slots to track. This limits peak memory consumption, at the cost of dropping some variable locations, but in a rare scenario where it's unlikely someone is actually going to use them. In terms of the patch, this adds a cl::opt for max number of stack slots to track, and has the stack-slot-numbering code optionally return None. That then filters through a number of code paths, which can then chose to not track a spill / restore if it touches an untracked spill slot. The added test checks that we drop variable locations that are on the stack, if we set the limit to zero. Differential Revision: https://reviews.llvm.org/D118601 (cherry picked from commit 14aaaa12366f7d1328b5ec81c71c63de9d878e75) --- .../LiveDebugValues/InstrRefBasedImpl.cpp | 100 ++++++++++++------ .../LiveDebugValues/InstrRefBasedImpl.h | 10 +- .../MIR/InstrRef/spill-slot-limits.mir | 90 ++++++++++++++++ llvm/unittests/CodeGen/InstrRefLDVTest.cpp | 14 +-- 4 files changed, 169 insertions(+), 45 deletions(-) create mode 100644 llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 0eb6100230bd1..2e69a5e437e76 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -148,6 +148,20 @@ static cl::opt EmulateOldLDV("emulate-old-livedebugvalues", cl::Hidden, cl::desc("Act like old LiveDebugValues did"), cl::init(false)); +// Limit for the maximum number of stack slots we should track, past which we +// will ignore any spills. InstrRefBasedLDV gathers detailed information on all +// stack slots which leads to high memory consumption, and in some scenarios +// (such as asan with very many locals) the working set of the function can be +// very large, causing many spills. In these scenarios, it is very unlikely that +// the developer has hundreds of variables live at the same time that they're +// carefully thinking about -- instead, they probably autogenerated the code. +// When this happens, gracefully stop tracking excess spill slots, rather than +// consuming all the developer's memory. +static cl::opt + StackWorkingSetLimit("livedebugvalues-max-stack-slots", cl::Hidden, + cl::desc("livedebugvalues-stack-ws-limit"), + cl::init(250)); + /// Tracker for converting machine value locations and variable values into /// variable locations (the output of LiveDebugValues), recorded as DBG_VALUEs /// specifying block live-in locations and transfers within blocks. @@ -757,9 +771,15 @@ void MLocTracker::writeRegMask(const MachineOperand *MO, unsigned CurBB, Masks.push_back(std::make_pair(MO, InstID)); } -SpillLocationNo MLocTracker::getOrTrackSpillLoc(SpillLoc L) { +Optional MLocTracker::getOrTrackSpillLoc(SpillLoc L) { SpillLocationNo SpillID(SpillLocs.idFor(L)); + if (SpillID.id() == 0) { + // If there is no location, and we have reached the limit of how many stack + // slots to track, then don't track this one. + if (SpillLocs.size() >= StackWorkingSetLimit) + return None; + // Spill location is untracked: create record for this one, and all // subregister slots too. SpillID = SpillLocationNo(SpillLocs.insert(L)); @@ -898,7 +918,7 @@ bool InstrRefBasedLDV::isCalleeSaved(LocIdx L) const { // void InstrRefBasedLDV::printVarLocInMBB(..) #endif -SpillLocationNo +Optional InstrRefBasedLDV::extractSpillBaseRegAndOffset(const MachineInstr &MI) { assert(MI.hasOneMemOperand() && "Spill instruction does not have exactly one memory operand?"); @@ -913,8 +933,11 @@ InstrRefBasedLDV::extractSpillBaseRegAndOffset(const MachineInstr &MI) { return MTracker->getOrTrackSpillLoc({Reg, Offset}); } -Optional InstrRefBasedLDV::findLocationForMemOperand(const MachineInstr &MI) { - SpillLocationNo SpillLoc = extractSpillBaseRegAndOffset(MI); +Optional +InstrRefBasedLDV::findLocationForMemOperand(const MachineInstr &MI) { + Optional SpillLoc = extractSpillBaseRegAndOffset(MI); + if (!SpillLoc) + return None; // Where in the stack slot is this value defined -- i.e., what size of value // is this? An important question, because it could be loaded into a register @@ -930,7 +953,7 @@ Optional InstrRefBasedLDV::findLocationForMemOperand(const MachineInstr // occur, but the safe action is to indicate the variable is optimised out. return None; - unsigned SpillID = MTracker->getSpillIDWithIdx(SpillLoc, IdxIt->second); + unsigned SpillID = MTracker->getSpillIDWithIdx(*SpillLoc, IdxIt->second); return MTracker->getSpillMLoc(SpillID); } @@ -1251,7 +1274,12 @@ bool InstrRefBasedLDV::transferDebugPHI(MachineInstr &MI) { Register Base; StackOffset Offs = TFI->getFrameIndexReference(*MI.getMF(), FI, Base); SpillLoc SL = {Base, Offs}; - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(SL); + Optional SpillNo = MTracker->getOrTrackSpillLoc(SL); + + // We might be able to find a value, but have chosen not to, to avoid + // tracking too much stack information. + if (!SpillNo) + return true; // Problem: what value should we extract from the stack? LLVM does not // record what size the last store to the slot was, and it would become @@ -1263,7 +1291,7 @@ bool InstrRefBasedLDV::transferDebugPHI(MachineInstr &MI) { Optional Result = None; Optional SpillLoc = None; for (unsigned CS : CandidateSizes) { - unsigned SpillID = MTracker->getLocID(SpillNo, {CS, 0}); + unsigned SpillID = MTracker->getLocID(*SpillNo, {CS, 0}); SpillLoc = MTracker->getSpillMLoc(SpillID); ValueIDNum Val = MTracker->readMLoc(*SpillLoc); // If this value was defined in it's own position, then it was probably @@ -1280,7 +1308,7 @@ bool InstrRefBasedLDV::transferDebugPHI(MachineInstr &MI) { // "supposed" to be is more complex, and benefits a small number of // locations. if (!Result) { - unsigned SpillID = MTracker->getLocID(SpillNo, {64, 0}); + unsigned SpillID = MTracker->getLocID(*SpillNo, {64, 0}); SpillLoc = MTracker->getSpillMLoc(SpillID); Result = MTracker->readMLoc(*SpillLoc); } @@ -1357,11 +1385,12 @@ void InstrRefBasedLDV::transferRegisterDef(MachineInstr &MI) { // If this instruction writes to a spill slot, def that slot. if (hasFoldedStackStore(MI)) { - SpillLocationNo SpillNo = extractSpillBaseRegAndOffset(MI); - for (unsigned int I = 0; I < MTracker->NumSlotIdxes; ++I) { - unsigned SpillID = MTracker->getSpillIDWithIdx(SpillNo, I); - LocIdx L = MTracker->getSpillMLoc(SpillID); - MTracker->setMLoc(L, ValueIDNum(CurBB, CurInst, L)); + if (Optional SpillNo = extractSpillBaseRegAndOffset(MI)) { + for (unsigned int I = 0; I < MTracker->NumSlotIdxes; ++I) { + unsigned SpillID = MTracker->getSpillIDWithIdx(*SpillNo, I); + LocIdx L = MTracker->getSpillMLoc(SpillID); + MTracker->setMLoc(L, ValueIDNum(CurBB, CurInst, L)); + } } } @@ -1398,11 +1427,12 @@ void InstrRefBasedLDV::transferRegisterDef(MachineInstr &MI) { // Tell TTracker about any folded stack store. if (hasFoldedStackStore(MI)) { - SpillLocationNo SpillNo = extractSpillBaseRegAndOffset(MI); - for (unsigned int I = 0; I < MTracker->NumSlotIdxes; ++I) { - unsigned SpillID = MTracker->getSpillIDWithIdx(SpillNo, I); - LocIdx L = MTracker->getSpillMLoc(SpillID); - TTracker->clobberMloc(L, MI.getIterator(), true); + if (Optional SpillNo = extractSpillBaseRegAndOffset(MI)) { + for (unsigned int I = 0; I < MTracker->NumSlotIdxes; ++I) { + unsigned SpillID = MTracker->getSpillIDWithIdx(*SpillNo, I); + LocIdx L = MTracker->getSpillMLoc(SpillID); + TTracker->clobberMloc(L, MI.getIterator(), true); + } } } } @@ -1438,23 +1468,24 @@ void InstrRefBasedLDV::performCopy(Register SrcRegNum, Register DstRegNum) { } } -bool InstrRefBasedLDV::isSpillInstruction(const MachineInstr &MI, - MachineFunction *MF) { +Optional +InstrRefBasedLDV::isSpillInstruction(const MachineInstr &MI, + MachineFunction *MF) { // TODO: Handle multiple stores folded into one. if (!MI.hasOneMemOperand()) - return false; + return None; // Reject any memory operand that's aliased -- we can't guarantee its value. auto MMOI = MI.memoperands_begin(); const PseudoSourceValue *PVal = (*MMOI)->getPseudoValue(); if (PVal->isAliased(MFI)) - return false; + return None; if (!MI.getSpillSize(TII) && !MI.getFoldedSpillSize(TII)) - return false; // This is not a spill instruction, since no valid size was - // returned from either function. + return None; // This is not a spill instruction, since no valid size was + // returned from either function. - return true; + return extractSpillBaseRegAndOffset(MI); } bool InstrRefBasedLDV::isLocationSpill(const MachineInstr &MI, @@ -1511,13 +1542,11 @@ bool InstrRefBasedLDV::transferSpillOrRestoreInst(MachineInstr &MI) { // First, if there are any DBG_VALUEs pointing at a spill slot that is // written to, terminate that variable location. The value in memory // will have changed. DbgEntityHistoryCalculator doesn't try to detect this. - if (isSpillInstruction(MI, MF)) { - SpillLocationNo Loc = extractSpillBaseRegAndOffset(MI); - + if (Optional Loc = isSpillInstruction(MI, MF)) { // Un-set this location and clobber, so that earlier locations don't // continue past this store. for (unsigned SlotIdx = 0; SlotIdx < MTracker->NumSlotIdxes; ++SlotIdx) { - unsigned SpillID = MTracker->getSpillIDWithIdx(Loc, SlotIdx); + unsigned SpillID = MTracker->getSpillIDWithIdx(*Loc, SlotIdx); Optional MLoc = MTracker->getSpillMLoc(SpillID); if (!MLoc) continue; @@ -1535,7 +1564,9 @@ bool InstrRefBasedLDV::transferSpillOrRestoreInst(MachineInstr &MI) { // Try to recognise spill and restore instructions that may transfer a value. if (isLocationSpill(MI, MF, Reg)) { - SpillLocationNo Loc = extractSpillBaseRegAndOffset(MI); + // isLocationSpill returning true should guarantee we can extract a + // location. + SpillLocationNo Loc = *extractSpillBaseRegAndOffset(MI); auto DoTransfer = [&](Register SrcReg, unsigned SpillID) { auto ReadValue = MTracker->readReg(SrcReg); @@ -1562,10 +1593,9 @@ bool InstrRefBasedLDV::transferSpillOrRestoreInst(MachineInstr &MI) { unsigned SpillID = MTracker->getLocID(Loc, {Size, 0}); DoTransfer(Reg, SpillID); } else { - Optional OptLoc = isRestoreInstruction(MI, MF, Reg); - if (!OptLoc) + Optional Loc = isRestoreInstruction(MI, MF, Reg); + if (!Loc) return false; - SpillLocationNo Loc = *OptLoc; // Assumption: we're reading from the base of the stack slot, not some // offset into it. It seems very unlikely LLVM would ever generate @@ -1592,13 +1622,13 @@ bool InstrRefBasedLDV::transferSpillOrRestoreInst(MachineInstr &MI) { for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) { unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI); - unsigned SpillID = MTracker->getLocID(Loc, Subreg); + unsigned SpillID = MTracker->getLocID(*Loc, Subreg); DoTransfer(*SRI, SpillID); } // Directly look up this registers slot idx by size, and transfer. unsigned Size = TRI->getRegSizeInBits(Reg, *MRI); - unsigned SpillID = MTracker->getLocID(Loc, {Size, 0}); + unsigned SpillID = MTracker->getLocID(*Loc, {Size, 0}); DoTransfer(Reg, SpillID); } return true; diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index e7383209c0274..fe1d29260e4da 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -616,7 +616,9 @@ class MLocTracker { void writeRegMask(const MachineOperand *MO, unsigned CurBB, unsigned InstID); /// Find LocIdx for SpillLoc \p L, creating a new one if it's not tracked. - SpillLocationNo getOrTrackSpillLoc(SpillLoc L); + /// Returns None when in scenarios where a spill slot could be tracked, but + /// we would likely run into resource limitations. + Optional getOrTrackSpillLoc(SpillLoc L); // Get LocIdx of a spill ID. LocIdx getSpillMLoc(unsigned SpillID) { @@ -873,7 +875,8 @@ class InstrRefBasedLDV : public LDVImpl { StringRef StackProbeSymbolName; /// Tests whether this instruction is a spill to a stack slot. - bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF); + Optional isSpillInstruction(const MachineInstr &MI, + MachineFunction *MF); /// Decide if @MI is a spill instruction and return true if it is. We use 2 /// criteria to make this decision: @@ -891,7 +894,8 @@ class InstrRefBasedLDV : public LDVImpl { /// Given a spill instruction, extract the spill slot information, ensure it's /// tracked, and return the spill number. - SpillLocationNo extractSpillBaseRegAndOffset(const MachineInstr &MI); + Optional + extractSpillBaseRegAndOffset(const MachineInstr &MI); /// Observe a single instruction while stepping through a block. void process(MachineInstr &MI, ValueIDNum **MLiveOuts = nullptr, diff --git a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir new file mode 100644 index 0000000000000..7969fafabc788 --- /dev/null +++ b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir @@ -0,0 +1,90 @@ +# RUN: llc %s -o - -experimental-debug-variable-locations \ +# RUN: -mtriple=x86_64-unknown-unknown \ +# RUN: -run-pass=livedebugvalues -livedebugvalues-max-stack-slots=0 | \ +# RUN: FileCheck %s --implicit-check-not=DBG_VALUE +# RUN: llc %s -o - -experimental-debug-variable-locations \ +# RUN: -mtriple=x86_64-unknown-unknown \ +# RUN: -run-pass=livedebugvalues -livedebugvalues-max-stack-slots=100 | \ +# RUN: FileCheck %s --check-prefixes=NOLIMIT --implicit-check-not=DBG_VALUE +# +# Test that spills of live values to the stack are NOT tracked by +# LiveDebugValues if an internal accounting limit is exceeded -- in this test, +# set to zero. This is to avoid scenarios where we track thousands of stack +# slots, which can show up with autogenerated code and/or asan. +# +# This is a copy of livedebugvalues_stackslot_subregs.mir, here the stack slot +# limit is set to zero, meaning the spill shouldn't be tracked. +# +## Capture variable num, +# CHECK: ![[VARNUM:[0-9]+]] = !DILocalVariable +# +## There should be no variable location, just a single DBG_VALUE $noreg. +# CHECK: DBG_VALUE $noreg +# +## And then another. +# CHECK: DBG_VALUE $noreg +# +## Test that if there's no limit, we _do_ get some locations. +# NOLIMIT: DBG_INSTR_REF 1, 0 +# NOLIMIT-NEXT: DBG_VALUE $esi +# +# NOLIMIT: DBG_INSTR_REF 5, +# NOLIMIT-NEXT: DBG_VALUE $rsp +--- | + define i8 @test(i32 %bar) local_unnamed_addr !dbg !7 { + entry: + ret i8 0, !dbg !12 + } + + declare dso_local void @ext(i64) + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!3, !4, !5, !6} + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) + !1 = !DIFile(filename: "foo.cpp", directory: ".") + !2 = !DIBasicType(name: "int", size: 8, encoding: DW_ATE_signed) + !3 = !{i32 2, !"Dwarf Version", i32 4} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = !{i32 1, !"wchar_size", i32 2} + !6 = !{i32 7, !"PIC Level", i32 2} + !7 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: !1, file: !1, line: 6, type: !8, scopeLine: 6, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !10) + !8 = !DISubroutineType(types: !9) + !9 = !{!2, !2} + !10 = !{!11} + !11 = !DILocalVariable(name: "baz", scope: !7, file: !1, line: 7, type: !2) + !12 = !DILocation(line: 10, scope: !7) +... +--- +name: test +tracksRegLiveness: true +liveins: + - { reg: '$rdi', virtual-reg: '' } +stack: + - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + bb.0: + liveins: $rdi, $rax, $rbx + $eax = MOV32ri 0, debug-instr-number 1 + $edi = COPY $eax + MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0) + $rsi = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0) + + MOV64mr $rsp, 1, $noreg, 16, $noreg, $rbx :: (store 8 into %stack.0) + $rax = MOV64ri 0 + $rdi = MOV64ri 0 + + DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12 + ; This shouldn't find anything -- we have disabled tracking of spills. + + ; In addition to plain spills, spills that are folded into instructions + ; shouldn't be tracked either. + INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !12 :: (store (s32) into %stack.0) + + + DBG_INSTR_REF 5, 1000000, !11, !DIExpression(), debug-location !12 + ; Shouldn't be able to find the reference to instr 5's memory operand. + + RET64 $rsi, debug-location !12 +... diff --git a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp index cf7b23662365a..9b7683108d777 100644 --- a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp +++ b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp @@ -642,7 +642,7 @@ TEST_F(InstrRefLDVTest, MTransferCopies) { // it's not completely clear why, but here we only care about correctly // identifying the slot, not that all the surrounding data is correct. SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); unsigned SpillLocID = MTracker->getLocID(SpillNo, {64, 0}); LocIdx SpillLoc = MTracker->getSpillMLoc(SpillLocID); ValueIDNum V = MTracker->readMLoc(SpillLoc); @@ -766,7 +766,7 @@ TEST_F(InstrRefLDVTest, MTransferSubregSpills) { ValueIDNum DefNum(0, 1, RegLoc); // Read the corresponding subreg field from the stack. SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); @@ -803,7 +803,7 @@ TEST_F(InstrRefLDVTest, MTransferSubregSpills) { // $rbx should contain something else; today it's a def at the spill point // of the 4 byte value. SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); unsigned SpillID = MTracker->getLocID(SpillNo, {64, 0}); LocIdx Spill64Loc = MTracker->getSpillMLoc(SpillID); ValueIDNum DefAtSpill64(0, 3, Spill64Loc); @@ -817,7 +817,7 @@ TEST_F(InstrRefLDVTest, MTransferSubregSpills) { LocIdx RegLoc = MTracker->getRegMLoc(getRegByName(SubRegNames[I])); ValueIDNum DefNum(0, 1, RegLoc); // Read the corresponding subreg field from the stack. - SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillNo = *MTracker->getOrTrackSpillLoc(L); SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); @@ -846,7 +846,7 @@ TEST_F(InstrRefLDVTest, MTransferSubregSpills) { for (unsigned int I = 0; I < 5; ++I) { // Read subreg fields from the stack. - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); @@ -859,7 +859,7 @@ TEST_F(InstrRefLDVTest, MTransferSubregSpills) { // Read xmm0's position and ensure it has a value. Should be the live-in // value to the block, as IMPLICIT_DEF isn't a real def. - SpillNo = MTracker->getOrTrackSpillLoc(L); + SpillNo = *MTracker->getOrTrackSpillLoc(L); SpillID = MTracker->getLocID(SpillNo, {128, 0}); LocIdx Spill128Loc = MTracker->getSpillMLoc(SpillID); SpillValue = MTracker->readMLoc(Spill128Loc); @@ -1097,7 +1097,7 @@ TEST_F(InstrRefLDVTest, MLocDiamondSpills) { // Create a stack location and ensure it's tracked. SpillLoc SL = {getRegByName("RSP"), StackOffset::getFixed(-8)}; - SpillLocationNo SpillNo = MTracker->getOrTrackSpillLoc(SL); + SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(SL); ASSERT_EQ(MTracker->getNumLocs(), 10u); // Tracks all possible stack locs. // Locations are: RSP, stack slots from 2^3 bits wide up to 2^9 for zmm regs, // then slots for sub_8bit_hi and sub_16bit_hi ({8, 8} and {16, 16}). From e870e07019abf9c05660f30c49458b7699f9c5bd Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 12:12:32 +0000 Subject: [PATCH 032/316] [DebugInfo][InstrRef][NFC] Cache some PHI resolutions Install a cache of DBG_INSTR_REF -> ValueIDNum resolutions, for scenarios where the value has to be reconstructed from several DBG_PHIs. Whenever this happens, it's because branch folding + tail duplication has messed with the SSA form of the program, and we have to solve a mini SSA problem to find the variable value. This is always called twice, so it makes sense to cache the value. This gives a ~0.5% geomean compile-time-performance improvement on CTMark. Differential Revision: https://reviews.llvm.org/D118455 (cherry picked from commit d556eb7e27c25ae20befb0811bc8a3423241431d) --- .../LiveDebugValues/InstrRefBasedImpl.cpp | 16 ++++++++++++++++ .../CodeGen/LiveDebugValues/InstrRefBasedImpl.h | 12 ++++++++++++ 2 files changed, 28 insertions(+) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 2e69a5e437e76..25d764dee2ed8 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -3122,6 +3122,7 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, DebugPHINumToValue.clear(); OverlapFragments.clear(); SeenFragments.clear(); + SeenDbgPHIs.clear(); return Changed; } @@ -3387,6 +3388,21 @@ Optional InstrRefBasedLDV::resolveDbgPHIs(MachineFunction &MF, ValueIDNum **MLiveIns, MachineInstr &Here, uint64_t InstrNum) { + // This function will be called twice per DBG_INSTR_REF, and might end up + // computing lots of SSA information: memoize it. + auto SeenDbgPHIIt = SeenDbgPHIs.find(&Here); + if (SeenDbgPHIIt != SeenDbgPHIs.end()) + return SeenDbgPHIIt->second; + + Optional Result = + resolveDbgPHIsImpl(MF, MLiveOuts, MLiveIns, Here, InstrNum); + SeenDbgPHIs.insert({&Here, Result}); + return Result; +} + +Optional InstrRefBasedLDV::resolveDbgPHIsImpl( + MachineFunction &MF, ValueIDNum **MLiveOuts, ValueIDNum **MLiveIns, + MachineInstr &Here, uint64_t InstrNum) { // Pick out records of DBG_PHI instructions that have been observed. If there // are none, then we cannot compute a value number. auto RangePair = std::equal_range(DebugPHINumToValue.begin(), diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index fe1d29260e4da..1e1bb758d3d44 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -864,6 +864,12 @@ class InstrRefBasedLDV : public LDVImpl { OverlapMap OverlapFragments; VarToFragments SeenFragments; + /// Mapping of DBG_INSTR_REF instructions to their values, for those + /// DBG_INSTR_REFs that call resolveDbgPHIs. These variable references solve + /// a mini SSA problem caused by DBG_PHIs being cloned, this collection caches + /// the result. + DenseMap> SeenDbgPHIs; + /// True if we need to examine call instructions for stack clobbers. We /// normally assume that they don't clobber SP, but stack probes on Windows /// do. @@ -944,6 +950,12 @@ class InstrRefBasedLDV : public LDVImpl { ValueIDNum **MLiveIns, MachineInstr &Here, uint64_t InstrNum); + Optional resolveDbgPHIsImpl(MachineFunction &MF, + ValueIDNum **MLiveOuts, + ValueIDNum **MLiveIns, + MachineInstr &Here, + uint64_t InstrNum); + /// Step through the function, recording register definitions and movements /// in an MLocTracker. Convert the observations into a per-block transfer /// function in \p MLocTransfer, suitable for using with the machine value From 762c17b7b6f24a55b4071382f822114128bb3af1 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 12:23:52 +0000 Subject: [PATCH 033/316] [DebugInfo][InstrRef][NFC] Free resources at an earlier stage This patch releases some memory from InstrRefBasedLDV earlier that it would otherwise. The underlying problem is: * We store a big table of "live in values for each block", * We translate that into DBG_VALUE instructions in each block, And both exist in memory at the same time, which needlessly doubles that information. The most of what this patch does is: as we progressively translate live-in information into DBG_VALUEs, we free the variable-value / machine-value tracking information as we go, which significantly reduces peak memory. While I'm here, also add a clear method to wipe variable assignments that have been accumulated into VLocTracker objects, and turn a DenseMap into a SmallDenseMap to avoid an initial allocation. Differential Revision: https://reviews.llvm.org/D118453 (cherry picked from commit a80181a81ea44215e49e5da1457614ec0bd44111) --- .../LiveDebugValues/InstrRefBasedImpl.cpp | 30 ++++++++++++++----- .../LiveDebugValues/InstrRefBasedImpl.h | 7 ++++- 2 files changed, 29 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 25d764dee2ed8..7b06bc9b0c39c 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -1029,7 +1029,7 @@ bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI, // Only handle this instruction when we are building the variable value // transfer function. - if (!VTracker) + if (!VTracker && !TTracker) return false; unsigned InstNo = MI.getOperand(0).getImm(); @@ -1185,7 +1185,8 @@ bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI, // for DBG_INSTR_REFs as DBG_VALUEs (just, the former can refer to values that // aren't immediately available). DbgValueProperties Properties(Expr, false); - VTracker->defVar(MI, Properties, NewID); + if (VTracker) + VTracker->defVar(MI, Properties, NewID); // If we're on the final pass through the function, decompose this INSTR_REF // into a plain DBG_VALUE. @@ -2826,6 +2827,7 @@ void InstrRefBasedLDV::emitLocations( const TargetPassConfig &TPC) { TTracker = new TransferTracker(TII, MTracker, MF, *TRI, CalleeSavedRegs, TPC); unsigned NumLocs = MTracker->getNumLocs(); + VTracker = nullptr; // For each block, load in the machine value locations and variable value // live-ins, then step through each instruction in the block. New DBG_VALUEs @@ -2844,6 +2846,15 @@ void InstrRefBasedLDV::emitLocations( TTracker->checkInstForNewValues(CurInst, MI.getIterator()); ++CurInst; } + + // Our block information has now been converted into DBG_VALUEs, to be + // inserted below. Free the memory we allocated to track variable / register + // values. If we don't, we needlessy record the same info in memory twice. + delete[] MInLocs[bbnum]; + delete[] MOutLocs[bbnum]; + MInLocs[bbnum] = nullptr; + MOutLocs[bbnum] = nullptr; + SavedLiveIns[bbnum].clear(); } emitTransfers(AllVarsNumbering); @@ -3080,6 +3091,12 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, << " has " << MaxNumBlocks << " basic blocks and " << VarAssignCount << " variable assignments, exceeding limits.\n"); + + // Perform memory cleanup that emitLocations would do otherwise. + for (int Idx = 0; Idx < MaxNumBlocks; ++Idx) { + delete[] MOutLocs[Idx]; + delete[] MInLocs[Idx]; + } } else { // Compute the extended ranges, iterating over scopes. There might be // something to be said for ordering them by size/locality, but that's for @@ -3091,6 +3108,9 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, vlocs); } + // Now that we've analysed variable assignments, free any tracking data. + vlocs.clear(); + // Using the computed value locations and variable values for each block, // create the DBG_VALUE instructions representing the extended variable // locations. @@ -3100,11 +3120,7 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, Changed = TTracker->Transfers.size() != 0; } - // Common clean-up of memory. - for (int Idx = 0; Idx < MaxNumBlocks; ++Idx) { - delete[] MOutLocs[Idx]; - delete[] MInLocs[Idx]; - } + // Elements of these arrays will be deleted by emitLocations. delete[] MOutLocs; delete[] MInLocs; diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index 1e1bb758d3d44..9ae0d4dd087c3 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -680,7 +680,7 @@ class VLocTracker { /// movement of values between locations inside of a block is handled at a /// much later stage, in the TransferTracker class. MapVector Vars; - DenseMap Scopes; + SmallDenseMap Scopes; MachineBasicBlock *MBB = nullptr; const OverlapMap &OverlappingFragments; DbgValueProperties EmptyProperties; @@ -749,6 +749,11 @@ class VLocTracker { Scopes[Overlapped] = Loc; } } + + void clear() { + Vars.clear(); + Scopes.clear(); + } }; // XXX XXX docs From 89d7063d7ece761901f3d4c8313d29b21a846d85 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 13:48:36 +0000 Subject: [PATCH 034/316] [DebugInfo][InstrRef][NFC] Use depth-first scope search for variable locs This patch aims to reduce max-rss from instruction referencing, by avoiding keeping variable value information in memory for too long. Instead of computing all the variable values then emitting them to DBG_VALUE instructions, this patch tries to stream the information out through a depth first search: * Make use of the fact LexicalScopes gives a depth-number to each lexical scope, * Produce a map that identifies the last lexical scope to make use of a block, * Enumerate each scope in LexicalScopes' DFS order, solving the variable value problem, * After each scope is processed, look for any blocks that won't be used by any other scope, and emit all the variable information to DBG_VALUE instructions. Differential Revision: https://reviews.llvm.org/D118460 (cherry picked from commit 9fd9d56dc6bdeeddf8cf2af834c6c39d00cd7244) --- .../LiveDebugValues/InstrRefBasedImpl.cpp | 234 +++++++++++++----- .../LiveDebugValues/InstrRefBasedImpl.h | 34 ++- 2 files changed, 196 insertions(+), 72 deletions(-) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 7b06bc9b0c39c..268095e0943a0 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -2821,45 +2821,6 @@ void InstrRefBasedLDV::dump_mloc_transfer( } #endif -void InstrRefBasedLDV::emitLocations( - MachineFunction &MF, LiveInsT SavedLiveIns, ValueIDNum **MOutLocs, - ValueIDNum **MInLocs, DenseMap &AllVarsNumbering, - const TargetPassConfig &TPC) { - TTracker = new TransferTracker(TII, MTracker, MF, *TRI, CalleeSavedRegs, TPC); - unsigned NumLocs = MTracker->getNumLocs(); - VTracker = nullptr; - - // For each block, load in the machine value locations and variable value - // live-ins, then step through each instruction in the block. New DBG_VALUEs - // to be inserted will be created along the way. - for (MachineBasicBlock &MBB : MF) { - unsigned bbnum = MBB.getNumber(); - MTracker->reset(); - MTracker->loadFromArray(MInLocs[bbnum], bbnum); - TTracker->loadInlocs(MBB, MInLocs[bbnum], SavedLiveIns[MBB.getNumber()], - NumLocs); - - CurBB = bbnum; - CurInst = 1; - for (auto &MI : MBB) { - process(MI, MOutLocs, MInLocs); - TTracker->checkInstForNewValues(CurInst, MI.getIterator()); - ++CurInst; - } - - // Our block information has now been converted into DBG_VALUEs, to be - // inserted below. Free the memory we allocated to track variable / register - // values. If we don't, we needlessy record the same info in memory twice. - delete[] MInLocs[bbnum]; - delete[] MOutLocs[bbnum]; - MInLocs[bbnum] = nullptr; - MOutLocs[bbnum] = nullptr; - SavedLiveIns[bbnum].clear(); - } - - emitTransfers(AllVarsNumbering); -} - void InstrRefBasedLDV::initialSetup(MachineFunction &MF) { // Build some useful data structures. @@ -2902,8 +2863,175 @@ void InstrRefBasedLDV::initialSetup(MachineFunction &MF) { #endif } +// Produce an "ejection map" for blocks, i.e., what's the highest-numbered +// lexical scope it's used in. When exploring in DFS order and we pass that +// scope, the block can be processed and any tracking information freed. +void InstrRefBasedLDV::makeDepthFirstEjectionMap( + SmallVectorImpl &EjectionMap, + const ScopeToDILocT &ScopeToDILocation, + ScopeToAssignBlocksT &ScopeToAssignBlocks) { + SmallPtrSet BlocksToExplore; + SmallVector, 4> WorkStack; + auto *TopScope = LS.getCurrentFunctionScope(); + + // Unlike lexical scope explorers, we explore in reverse order, to find the + // "last" lexical scope used for each block early. + WorkStack.push_back({TopScope, TopScope->getChildren().size() - 1}); + + while (!WorkStack.empty()) { + auto &ScopePosition = WorkStack.back(); + LexicalScope *WS = ScopePosition.first; + ssize_t ChildNum = ScopePosition.second--; + + const SmallVectorImpl &Children = WS->getChildren(); + if (ChildNum >= 0) { + // If ChildNum is positive, there are remaining children to explore. + // Push the child and its children-count onto the stack. + auto &ChildScope = Children[ChildNum]; + WorkStack.push_back( + std::make_pair(ChildScope, ChildScope->getChildren().size() - 1)); + } else { + WorkStack.pop_back(); + + // We've explored all children and any later blocks: examine all blocks + // in our scope. If they haven't yet had an ejection number set, then + // this scope will be the last to use that block. + auto DILocationIt = ScopeToDILocation.find(WS); + if (DILocationIt != ScopeToDILocation.end()) { + getBlocksForScope(DILocationIt->second, BlocksToExplore, + ScopeToAssignBlocks.find(WS)->second); + for (auto *MBB : BlocksToExplore) { + unsigned BBNum = MBB->getNumber(); + if (EjectionMap[BBNum] == 0) + EjectionMap[BBNum] = WS->getDFSOut(); + } + + BlocksToExplore.clear(); + } + } + } +} + +bool InstrRefBasedLDV::depthFirstVLocAndEmit( + unsigned MaxNumBlocks, const ScopeToDILocT &ScopeToDILocation, + const ScopeToVarsT &ScopeToVars, ScopeToAssignBlocksT &ScopeToAssignBlocks, + LiveInsT &Output, ValueIDNum **MOutLocs, ValueIDNum **MInLocs, + SmallVectorImpl &AllTheVLocs, MachineFunction &MF, + DenseMap &AllVarsNumbering, + const TargetPassConfig &TPC) { + TTracker = new TransferTracker(TII, MTracker, MF, *TRI, CalleeSavedRegs, TPC); + unsigned NumLocs = MTracker->getNumLocs(); + VTracker = nullptr; + + // No scopes? No variable locations. + if (!LS.getCurrentFunctionScope()) + return false; + + // Build map from block number to the last scope that uses the block. + SmallVector EjectionMap; + EjectionMap.resize(MaxNumBlocks, 0); + makeDepthFirstEjectionMap(EjectionMap, ScopeToDILocation, + ScopeToAssignBlocks); + + // Helper lambda for ejecting a block -- if nothing is going to use the block, + // we can translate the variable location information into DBG_VALUEs and then + // free all of InstrRefBasedLDV's data structures. + auto EjectBlock = [&](MachineBasicBlock &MBB) -> void { + unsigned BBNum = MBB.getNumber(); + AllTheVLocs[BBNum].clear(); + + // Prime the transfer-tracker, and then step through all the block + // instructions, installing transfers. + MTracker->reset(); + MTracker->loadFromArray(MInLocs[BBNum], BBNum); + TTracker->loadInlocs(MBB, MInLocs[BBNum], Output[BBNum], NumLocs); + + CurBB = BBNum; + CurInst = 1; + for (auto &MI : MBB) { + process(MI, MOutLocs, MInLocs); + TTracker->checkInstForNewValues(CurInst, MI.getIterator()); + ++CurInst; + } + + // Free machine-location tables for this block. + delete[] MInLocs[BBNum]; + delete[] MOutLocs[BBNum]; + // Make ourselves brittle to use-after-free errors. + MInLocs[BBNum] = nullptr; + MOutLocs[BBNum] = nullptr; + // We don't need live-in variable values for this block either. + Output[BBNum].clear(); + AllTheVLocs[BBNum].clear(); + }; + + SmallPtrSet BlocksToExplore; + SmallVector, 4> WorkStack; + WorkStack.push_back({LS.getCurrentFunctionScope(), 0}); + unsigned HighestDFSIn = 0; + + // Proceed to explore in depth first order. + while (!WorkStack.empty()) { + auto &ScopePosition = WorkStack.back(); + LexicalScope *WS = ScopePosition.first; + ssize_t ChildNum = ScopePosition.second++; + + // We obesrve scopes with children twice here, once descending in, once + // ascending out of the scope nest. Use HighestDFSIn as a ratchet to ensure + // we don't process a scope twice. Additionally, ignore scopes that don't + // have a DILocation -- by proxy, this means we never tracked any variable + // assignments in that scope. + auto DILocIt = ScopeToDILocation.find(WS); + if (HighestDFSIn <= WS->getDFSIn() && DILocIt != ScopeToDILocation.end()) { + const DILocation *DILoc = DILocIt->second; + auto &VarsWeCareAbout = ScopeToVars.find(WS)->second; + auto &BlocksInScope = ScopeToAssignBlocks.find(WS)->second; + + buildVLocValueMap(DILoc, VarsWeCareAbout, BlocksInScope, Output, MOutLocs, + MInLocs, AllTheVLocs); + } + + HighestDFSIn = std::max(HighestDFSIn, WS->getDFSIn()); + + // Descend into any scope nests. + const SmallVectorImpl &Children = WS->getChildren(); + if (ChildNum < (ssize_t)Children.size()) { + // There are children to explore -- push onto stack and continue. + auto &ChildScope = Children[ChildNum]; + WorkStack.push_back(std::make_pair(ChildScope, 0)); + } else { + WorkStack.pop_back(); + + // We've explored a leaf, or have explored all the children of a scope. + // Try to eject any blocks where this is the last scope it's relevant to. + auto DILocationIt = ScopeToDILocation.find(WS); + if (DILocationIt == ScopeToDILocation.end()) + continue; + + getBlocksForScope(DILocationIt->second, BlocksToExplore, + ScopeToAssignBlocks.find(WS)->second); + for (auto *MBB : BlocksToExplore) + if (WS->getDFSOut() == EjectionMap[MBB->getNumber()]) + EjectBlock(const_cast(*MBB)); + + BlocksToExplore.clear(); + } + } + + // Some artificial blocks may not have been ejected, meaning they're not + // connected to an actual legitimate scope. This can technically happen + // with things like the entry block. In theory, we shouldn't need to do + // anything for such out-of-scope blocks, but for the sake of being similar + // to VarLocBasedLDV, eject these too. + for (auto *MBB : ArtificialBlocks) + if (MOutLocs[MBB->getNumber()]) + EjectBlock(*MBB); + + return emitTransfers(AllVarsNumbering); +} + bool InstrRefBasedLDV::emitTransfers( - DenseMap &AllVarsNumbering) { + DenseMap &AllVarsNumbering) { // Go through all the transfers recorded in the TransferTracker -- this is // both the live-ins to a block, and any movements of values that happen // in the middle. @@ -3098,26 +3226,12 @@ bool InstrRefBasedLDV::ExtendRanges(MachineFunction &MF, delete[] MInLocs[Idx]; } } else { - // Compute the extended ranges, iterating over scopes. There might be - // something to be said for ordering them by size/locality, but that's for - // the future. For each scope, solve the variable value problem, producing - // a map of variables to values in SavedLiveIns. - for (auto &P : ScopeToVars) { - buildVLocValueMap(ScopeToDILocation[P.first], P.second, - ScopeToAssignBlocks[P.first], SavedLiveIns, MOutLocs, MInLocs, - vlocs); - } - - // Now that we've analysed variable assignments, free any tracking data. - vlocs.clear(); - - // Using the computed value locations and variable values for each block, - // create the DBG_VALUE instructions representing the extended variable - // locations. - emitLocations(MF, SavedLiveIns, MOutLocs, MInLocs, AllVarsNumbering, *TPC); - - // Did we actually make any changes? If we created any DBG_VALUEs, then yes. - Changed = TTracker->Transfers.size() != 0; + // Optionally, solve the variable value problem and emit to blocks by using + // a lexical-scope-depth search. It should be functionally identical to + // the "else" block of this condition. + Changed = depthFirstVLocAndEmit( + MaxNumBlocks, ScopeToDILocation, ScopeToVars, ScopeToAssignBlocks, + SavedLiveIns, MOutLocs, MInLocs, vlocs, MF, AllVarsNumbering, *TPC); } // Elements of these arrays will be deleted by emitLocations. diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h index 9ae0d4dd087c3..d778561db471c 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h @@ -1071,18 +1071,6 @@ class InstrRefBasedLDV : public LDVImpl { const LiveIdxT &LiveOuts, ValueIDNum **MOutLocs, const SmallVectorImpl &BlockOrders); - /// Given the solutions to the two dataflow problems, machine value locations - /// in \p MInLocs and live-in variable values in \p SavedLiveIns, runs the - /// TransferTracker class over the function to produce live-in and transfer - /// DBG_VALUEs, then inserts them. Groups of DBG_VALUEs are inserted in the - /// order given by AllVarsNumbering -- this could be any stable order, but - /// right now "order of appearence in function, when explored in RPO", so - /// that we can compare explictly against VarLocBasedImpl. - void emitLocations(MachineFunction &MF, LiveInsT SavedLiveIns, - ValueIDNum **MOutLocs, ValueIDNum **MInLocs, - DenseMap &AllVarsNumbering, - const TargetPassConfig &TPC); - /// Take collections of DBG_VALUE instructions stored in TTracker, and /// install them into their output blocks. Preserves a stable order of /// DBG_VALUEs produced (which would otherwise cause nondeterminism) through @@ -1093,6 +1081,28 @@ class InstrRefBasedLDV : public LDVImpl { /// RPOT block ordering. void initialSetup(MachineFunction &MF); + /// Produce a map of the last lexical scope that uses a block, using the + /// scopes DFSOut number. Mapping is block-number to DFSOut. + /// \p EjectionMap Pre-allocated vector in which to install the built ma. + /// \p ScopeToDILocation Mapping of LexicalScopes to their DILocations. + /// \p AssignBlocks Map of blocks where assignments happen for a scope. + void makeDepthFirstEjectionMap(SmallVectorImpl &EjectionMap, + const ScopeToDILocT &ScopeToDILocation, + ScopeToAssignBlocksT &AssignBlocks); + + /// When determining per-block variable values and emitting to DBG_VALUEs, + /// this function explores by lexical scope depth. Doing so means that per + /// block information can be fully computed before exploration finishes, + /// allowing us to emit it and free data structures earlier than otherwise. + /// It's also good for locality. + bool depthFirstVLocAndEmit( + unsigned MaxNumBlocks, const ScopeToDILocT &ScopeToDILocation, + const ScopeToVarsT &ScopeToVars, ScopeToAssignBlocksT &ScopeToBlocks, + LiveInsT &Output, ValueIDNum **MOutLocs, ValueIDNum **MInLocs, + SmallVectorImpl &AllTheVLocs, MachineFunction &MF, + DenseMap &AllVarsNumbering, + const TargetPassConfig &TPC); + bool ExtendRanges(MachineFunction &MF, MachineDominatorTree *DomTree, TargetPassConfig *TPC, unsigned InputBBLimit, unsigned InputDbgValLimit) override; From 87f0dd330eaa089ca4034dffc105a7f2eef6b90c Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 15:54:24 +0000 Subject: [PATCH 035/316] Follow up to 9fd9d56dc6b, avoid a memory leak Gaps in the basic block number range (from blocks being deleted or folded) get block-value-tables allocated but never ejected, leading to a memory leak, currently tripping up the asan buildbots. Fix this up by manually freeing that memory. As suggested elsewhere, if these things were owned by a unique_ptr then cleanup would happen automagically. D118774 should eliminate the need for this dance. (cherry picked from commit 206cafb680cea0741f8c7b276351db516ff27f81) --- llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 268095e0943a0..cc800736a2dc1 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -3027,6 +3027,16 @@ bool InstrRefBasedLDV::depthFirstVLocAndEmit( if (MOutLocs[MBB->getNumber()]) EjectBlock(*MBB); + // Finally, there might have been gaps in the block numbering, from dead + // blocks being deleted or folded. In those scenarios, we might allocate a + // block-table that's never ejected, meaning we have to free it at the end. + for (unsigned int I = 0; I < MaxNumBlocks; ++I) { + if (MInLocs[I]) { + delete[] MInLocs[I]; + delete[] MOutLocs[I]; + } + } + return emitTransfers(AllVarsNumbering); } From 64adff8ec0c14d2184a4a7cfae4bc503ed41bcea Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 15:04:14 +0000 Subject: [PATCH 036/316] [DebugInfo][InstrRef] Fix a tombstone-in-DenseMap crash from D117877 This is a follow-up to D117877: variable assignments of DBG_VALUE $noreg, or DBG_INSTR_REFs where no value can be found, are represented by a DbgValue object with Kind "Undef", explicitly meaning "there is no value". In D117877 I added a special-case to some assignment accounting faster, without considering this scenario. It causes variables to be given the value ValueIDNum::EmptyValue, which then ends up being a DenseMap key. The DenseMap asserts, because EmptyValue is the tombstone key. Fix this by handling the assign-undef scenario in the special case, to match what happens in the general case: the variable has no value if it's only ever assigned $noreg / undef. Differential Revision: https://reviews.llvm.org/D118715 (cherry picked from commit 43de305704a50983bf134d8fb916f752a02eb076) --- .../LiveDebugValues/InstrRefBasedImpl.cpp | 5 ++ .../InstrRef/single-assign-propagation.mir | 65 ++++++++++++++++++- 2 files changed, 68 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index cc800736a2dc1..3b4d717c9ab4a 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -2796,6 +2796,11 @@ void InstrRefBasedLDV::placePHIsForSingleVarDefinition( auto ValueIt = VLocs.Vars.find(Var); const DbgValue &Value = ValueIt->second; + // If it's an explicit assignment of "undef", that means there is no location + // anyway, anywhere. + if (Value.Kind == DbgValue::Undef) + return; + // Assign the variable value to entry to each dominated block that's in scope. // Skip the definition block -- it's assigned the variable value in the middle // of the block somewhere. diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir index 19408b2ec4291..c247004368837 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir @@ -1,9 +1,11 @@ # RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \ # RUN: -experimental-debug-variable-locations=true \ -# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE +# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ +# RUN: --check-prefixes=CHECK,COMMON # RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \ # RUN: -experimental-debug-variable-locations=false \ -# RUN: | FileCheck %s --check-prefixes=VARLOC -implicit-check-not=DBG_VALUE +# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \ +# RUN: --check-prefixes=VARLOC,COMMON # # This test is designed to stimulate a simplification of variable-value # propagation in InstrRefBasedLDV. When we only have a single assignment of @@ -63,12 +65,23 @@ # VARLOC-LABEL: bb.3: # VARLOC: DBG_VALUE # +## Common tail for 'test2' -- this is checking that the assignment of undef or +## $noreg in single-assignment mode doesn't lead to trouble further down the +## line, specifically assertion failures. +# +# COMMON-LABEL: name: test2 +# COMMON: DBG_VALUE $noreg --- | define i32 @_Z8bb_to_bb() local_unnamed_addr !dbg !12 { entry: ret i32 0, !dbg !17 } + define i32 @test2() local_unnamed_addr !dbg !112 { + entry: + ret i32 0, !dbg !117 + } + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!7, !8, !9, !10} !llvm.ident = !{!11} @@ -94,6 +107,13 @@ !18 = distinct !DILexicalBlock(scope: !12, file: !1, line: 1, column: 1) !19 = distinct !DILexicalBlock(scope: !12, file: !1, line: 1, column: 1) !20 = !DILocation(line: 10, scope: !19) + !112 = distinct !DISubprogram(name: "test2", linkageName: "102", scope: !1, file: !1, line: 6, type: !13, scopeLine: 6, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !115) + !115 = !{!116} + !116 = !DILocalVariable(name: "myVar", scope: !118, file: !1, line: 7, type: !6) + !117 = !DILocation(line: 10, scope: !118) + !118 = distinct !DILexicalBlock(scope: !112, file: !1, line: 1, column: 1) + !119 = distinct !DILexicalBlock(scope: !112, file: !1, line: 1, column: 1) + !120 = !DILocation(line: 10, scope: !119) ... --- @@ -136,3 +156,44 @@ body: | bb.6: RET 0, debug-location !17 +... +--- +name: test2 +debugValueSubstitutions: + - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 } +body: | + bb.0.entry: + successors: %bb.1, %bb.5, %bb.6 + + $rax = MOV64ri 1, debug-instr-number 1, debug-location !117 + JCC_1 %bb.5, 1, implicit $eflags + JCC_1 %bb.6, 2, implicit $eflags + JMP_1 %bb.1 + + bb.1: + successors: %bb.2, %bb.3 + + DBG_VALUE $noreg, $noreg, !116, !DIExpression(), debug-location !117 + JCC_1 %bb.3, 1, implicit $eflags, debug-location !117 + + bb.2: + successors: %bb.4 + + JMP_1 %bb.4, debug-location !120 + + bb.3: + successors: %bb.4 + + JMP_1 %bb.4, debug-location !117 + + bb.4: + successors: %bb.5, %bb.6 + + JCC_1 %bb.5, 1, implicit $eflags, debug-location !117 + JMP_1 %bb.6, debug-location !117 + + bb.5: + RET 0, debug-location !117 + + bb.6: + RET 0, debug-location !117 From a03ffad5d34c6d1df14e25df17f18ea2fa437c0c Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 19:17:42 +0000 Subject: [PATCH 037/316] [DebugInfo] Re-enable instruction referencing for x86_64 After discussion in D116821 this was turned off in 74db5c8c95e, 14aaaa12366f7 applied to limit the maximum memory consumption in rare conditions, plus some performance patches. (cherry picked from commit 6e03a68b776dc06826dacbdab26d24a90bb2173b) --- llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp | 5 +++++ llvm/test/DebugInfo/X86/instr-ref-flag.ll | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp index 8f697611a82c0..40770b15aa35b 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp @@ -123,6 +123,11 @@ bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) { } bool llvm::debuginfoShouldUseDebugInstrRef(const Triple &T) { + // Enable by default on x86_64, disable if explicitly turned off on cmdline. + if (T.getArch() == llvm::Triple::x86_64 && + ValueTrackingVariableLocations != cl::boolOrDefault::BOU_FALSE) + return true; + // Enable if explicitly requested on command line. return ValueTrackingVariableLocations == cl::boolOrDefault::BOU_TRUE; } diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll index 56d34aedabd02..f9d5f99edf77f 100644 --- a/llvm/test/DebugInfo/X86/instr-ref-flag.ll +++ b/llvm/test/DebugInfo/X86/instr-ref-flag.ll @@ -13,10 +13,6 @@ ;; by llc by default, and that it can be turned explicitly on or off as ;; desired. -;; Xfail due to faults found in the discussion on -;; https://reviews.llvm.org/D116821 -; XFAIL: * - ; INSTRREFON: DBG_INSTR_REF ; INSTRREFOFF: DBG_VALUE From 52557b918b1dbb50f5ba52644db3be87b7934d9a Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Thu, 3 Feb 2022 17:26:41 +0100 Subject: [PATCH 038/316] [clang-tidy] Fix LLVM include order check policy Clang-format LLVM style has a custom include category for gtest/ and gmock/ headers between regular includes and angled includes. Do the same here. Fixes https://github.com/llvm/llvm-project/issues/53525. Differential Revision: https://reviews.llvm.org/D118913 (cherry picked from commit 0447ec2fb050eb37ed1f5991a1562dea6e228f9e) --- .../clang-tidy/llvm/IncludeOrderCheck.cpp | 10 ++- .../checkers/llvm-include-order.cpp | 2 + .../unittests/clang-tidy/LLVMModuleTest.cpp | 61 ++++++++++++++----- 3 files changed, 56 insertions(+), 17 deletions(-) diff --git a/clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp b/clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp index c962fb3bc25b2..ab75e3100d85d 100644 --- a/clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp +++ b/clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp @@ -66,11 +66,15 @@ static int getPriority(StringRef Filename, bool IsAngled, bool IsMainModule) { Filename.startswith("clang/") || Filename.startswith("clang-c/")) return 2; - // System headers are sorted to the end. - if (IsAngled || Filename.startswith("gtest/") || - Filename.startswith("gmock/")) + // Put these between system and llvm headers to be consistent with LLVM + // clang-format style. + if (Filename.startswith("gtest/") || Filename.startswith("gmock/")) return 3; + // System headers are sorted to the end. + if (IsAngled) + return 4; + // Other headers are inserted between the main module header and LLVM headers. return 1; } diff --git a/clang-tools-extra/test/clang-tidy/checkers/llvm-include-order.cpp b/clang-tools-extra/test/clang-tidy/checkers/llvm-include-order.cpp index 6dd3d6ace4581..d4da826ced386 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/llvm-include-order.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/llvm-include-order.cpp @@ -6,6 +6,7 @@ #include "gmock/foo.h" #include "i.h" #include +#include #include "llvm/a.h" #include "clang/b.h" #include "clang-c/c.h" // hi @@ -19,6 +20,7 @@ // CHECK-FIXES-NEXT: #include "llvm/a.h" // CHECK-FIXES-NEXT: #include "gmock/foo.h" // CHECK-FIXES-NEXT: #include "gtest/foo.h" +// CHECK-FIXES-NEXT: #include // CHECK-FIXES-NEXT: #include #include "b.h" diff --git a/clang-tools-extra/unittests/clang-tidy/LLVMModuleTest.cpp b/clang-tools-extra/unittests/clang-tidy/LLVMModuleTest.cpp index 2a3fae05f585f..46a1600e2bd6d 100644 --- a/clang-tools-extra/unittests/clang-tidy/LLVMModuleTest.cpp +++ b/clang-tools-extra/unittests/clang-tidy/LLVMModuleTest.cpp @@ -1,4 +1,7 @@ +#include "ClangTidyOptions.h" #include "ClangTidyTest.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/StringRef.h" #include "llvm/HeaderGuardCheck.h" #include "llvm/IncludeOrderCheck.h" #include "gtest/gtest.h" @@ -9,11 +12,15 @@ namespace clang { namespace tidy { namespace test { -static std::string runHeaderGuardCheck(StringRef Code, const Twine &Filename, - Optional ExpectedWarning) { +template +static std::string runCheck(StringRef Code, const Twine &Filename, + Optional ExpectedWarning, + std::map PathsToContent = + std::map()) { std::vector Errors; - std::string Result = test::runCheckOnCode( - Code, &Errors, Filename, std::string("-xc++-header")); + std::string Result = test::runCheckOnCode( + Code, &Errors, Filename, std::string("-xc++-header"), ClangTidyOptions{}, + std::move(PathsToContent)); if (Errors.size() != (size_t)ExpectedWarning.hasValue()) return "invalid error count"; if (ExpectedWarning && *ExpectedWarning != Errors.back().Message.Message) @@ -22,27 +29,36 @@ static std::string runHeaderGuardCheck(StringRef Code, const Twine &Filename, return Result; } +static std::string runHeaderGuardCheck(StringRef Code, const Twine &Filename, + Optional ExpectedWarning) { + return runCheck(Code, Filename, + std::move(ExpectedWarning)); +} + +static std::string +runIncludeOrderCheck(StringRef Code, const Twine &Filename, + Optional ExpectedWarning, + llvm::ArrayRef Includes) { + std::map PathsToContent; + for (auto Include : Includes) + PathsToContent.emplace(Include, ""); + return runCheck(Code, Filename, std::move(ExpectedWarning), + PathsToContent); +} + namespace { struct WithEndifComment : public LLVMHeaderGuardCheck { WithEndifComment(StringRef Name, ClangTidyContext *Context) : LLVMHeaderGuardCheck(Name, Context) {} bool shouldSuggestEndifComment(StringRef Filename) override { return true; } }; -} // namespace static std::string runHeaderGuardCheckWithEndif(StringRef Code, const Twine &Filename, Optional ExpectedWarning) { - std::vector Errors; - std::string Result = test::runCheckOnCode( - Code, &Errors, Filename, std::string("-xc++-header")); - if (Errors.size() != (size_t)ExpectedWarning.hasValue()) - return "invalid error count"; - if (ExpectedWarning && *ExpectedWarning != Errors.back().Message.Message) - return "expected: '" + ExpectedWarning->str() + "', saw: '" + - Errors.back().Message.Message + "'"; - return Result; + return runCheck(Code, Filename, std::move(ExpectedWarning)); } +} // namespace TEST(LLVMHeaderGuardCheckTest, FixHeaderGuards) { EXPECT_EQ("#ifndef LLVM_ADT_FOO_H\n" @@ -270,6 +286,23 @@ TEST(LLVMHeaderGuardCheckTest, FixHeaderGuards) { #endif } +TEST(IncludeOrderCheck, GTestHeaders) { + EXPECT_EQ( + R"cpp( + #include "foo.h" + #include "llvm/foo.h" + #include "gtest/foo.h" + #include )cpp", + runIncludeOrderCheck( + R"cpp( + #include "foo.h" + #include "llvm/foo.h" + #include + #include "gtest/foo.h")cpp", + "foo.cc", StringRef("#includes are not sorted properly"), + {"foo.h", "algorithm", "gtest/foo.h", "llvm/foo.h"})); +} + } // namespace test } // namespace tidy } // namespace clang From 3a8f3b38760277fe1c32ac2d016185d7f5a96974 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Fri, 4 Feb 2022 21:53:09 +0100 Subject: [PATCH 039/316] [TSan] Handle FreeBSD specific indirection of libpthread functions Similar to 60cc1d3218fc for NetBSD, add aliases and interceptors for the following pthread related functions: - pthread_cond_init(3) - pthread_cond_destroy(3) - pthread_cond_signal(3) - pthread_cond_broadcast(3) - pthread_cond_wait(3) - pthread_mutex_init(3) - pthread_mutex_destroy(3) - pthread_mutex_lock(3) - pthread_mutex_trylock(3) - pthread_mutex_unlock(3) - pthread_rwlock_init(3) - pthread_rwlock_destroy(3) - pthread_rwlock_rdlock(3) - pthread_rwlock_tryrdlock(3) - pthread_rwlock_wrlock(3) - pthread_rwlock_trywrlock(3) - pthread_rwlock_unlock(3) - pthread_once(3) - pthread_sigmask(3) In FreeBSD's libc, a number of internal aliases of the pthread functions are invoked, typically with an additional prefixed underscore, e.g. _pthread_cond_init() and so on. ThreadSanitizer needs to intercept these aliases too, otherwise some false positive reports about data races might be produced. Reviewed By: dvyukov Differential Revision: https://reviews.llvm.org/D119034 (cherry picked from commit 28fb22c90fe73877c529ddae74b9fe30a3a09234) --- compiler-rt/lib/tsan/rtl/tsan_interceptors.h | 8 +++ .../lib/tsan/rtl/tsan_interceptors_posix.cpp | 69 +++++++++++++++---- 2 files changed, 65 insertions(+), 12 deletions(-) diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors.h b/compiler-rt/lib/tsan/rtl/tsan_interceptors.h index 88a54b5544216..3091ad809c40f 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_interceptors.h +++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors.h @@ -78,6 +78,14 @@ inline bool MustIgnoreInterceptor(ThreadState *thr) { #define TSAN_INTERCEPTOR(ret, func, ...) INTERCEPTOR(ret, func, __VA_ARGS__) +#if SANITIZER_FREEBSD +# define TSAN_INTERCEPTOR_FREEBSD_ALIAS(ret, func, ...) \ + TSAN_INTERCEPTOR(ret, _pthread_##func, __VA_ARGS__) \ + ALIAS(WRAPPER_NAME(pthread_##func)); +#else +# define TSAN_INTERCEPTOR_FREEBSD_ALIAS(ret, func, ...) +#endif + #if SANITIZER_NETBSD # define TSAN_INTERCEPTOR_NETBSD_ALIAS(ret, func, ...) \ TSAN_INTERCEPTOR(ret, __libc_##func, __VA_ARGS__) \ diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp index 733ae5ee87ef6..999be79c6418b 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp @@ -289,20 +289,25 @@ void ScopedInterceptor::DisableIgnoresImpl() { } #define TSAN_INTERCEPT(func) INTERCEPT_FUNCTION(func) +#if SANITIZER_FREEBSD || SANITIZER_NETBSD +# define TSAN_INTERCEPT_VER(func, ver) INTERCEPT_FUNCTION(func) +#else +# define TSAN_INTERCEPT_VER(func, ver) INTERCEPT_FUNCTION_VER(func, ver) +#endif #if SANITIZER_FREEBSD -# define TSAN_INTERCEPT_VER(func, ver) INTERCEPT_FUNCTION(func) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(func) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS_THR(func) -#elif SANITIZER_NETBSD -# define TSAN_INTERCEPT_VER(func, ver) INTERCEPT_FUNCTION(func) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(func) \ - INTERCEPT_FUNCTION(__libc_##func) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS_THR(func) \ - INTERCEPT_FUNCTION(__libc_thr_##func) +# define TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(func) \ + INTERCEPT_FUNCTION(_pthread_##func) #else -# define TSAN_INTERCEPT_VER(func, ver) INTERCEPT_FUNCTION_VER(func, ver) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(func) -# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS_THR(func) +# define TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(func) +#endif +#if SANITIZER_NETBSD +# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(func) \ + INTERCEPT_FUNCTION(__libc_##func) +# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS_THR(func) \ + INTERCEPT_FUNCTION(__libc_thr_##func) +#else +# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(func) +# define TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS_THR(func) #endif #define READ_STRING_OF_LEN(thr, pc, s, len, n) \ @@ -2713,6 +2718,26 @@ TSAN_INTERCEPTOR(void, thr_exit, tid_t *state) { #define TSAN_MAYBE_INTERCEPT_THR_EXIT #endif +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, cond_init, void *c, void *a) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, cond_destroy, void *c) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, cond_signal, void *c) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, cond_broadcast, void *c) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, cond_wait, void *c, void *m) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, mutex_init, void *m, void *a) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, mutex_destroy, void *m) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, mutex_lock, void *m) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, mutex_trylock, void *m) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, mutex_unlock, void *m) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_init, void *l, void *a) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_destroy, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_rdlock, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_tryrdlock, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_wrlock, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_trywrlock, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, rwlock_unlock, void *l) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, once, void *o, void (*i)()) +TSAN_INTERCEPTOR_FREEBSD_ALIAS(int, sigmask, int f, void *n, void *o) + TSAN_INTERCEPTOR_NETBSD_ALIAS(int, cond_init, void *c, void *a) TSAN_INTERCEPTOR_NETBSD_ALIAS(int, cond_signal, void *c) TSAN_INTERCEPTOR_NETBSD_ALIAS(int, cond_broadcast, void *c) @@ -2941,6 +2966,26 @@ void InitializeInterceptors() { } #endif + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(cond_init); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(cond_destroy); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(cond_signal); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(cond_broadcast); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(cond_wait); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(mutex_init); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(mutex_destroy); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(mutex_lock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(mutex_trylock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(mutex_unlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_init); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_destroy); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_rdlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_tryrdlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_wrlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_trywrlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(rwlock_unlock); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(once); + TSAN_MAYBE_INTERCEPT_FREEBSD_ALIAS(sigmask); + TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(cond_init); TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(cond_signal); TSAN_MAYBE_INTERCEPT_NETBSD_ALIAS(cond_broadcast); From 319f4b2d52e31b000db75a0a2484b5f2ab90534a Mon Sep 17 00:00:00 2001 From: John Ericson Date: Wed, 2 Feb 2022 15:37:13 +0000 Subject: [PATCH 040/316] [lld][clang][cmake] Clean up a few things - If not using `llvm-config`, `LLVM_MAIN_SRC_DIR` now has a sane default - `LLVM_CONFIG_PATH` will continue to work for LLD for back compat. - More quoting of paths in an abundance of caution. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D118792 (cherry picked from commit e0eeae9a447004cc346d9bf36c0d02f45e276a7c) --- clang/CMakeLists.txt | 26 ++++++++++++++------------ lld/CMakeLists.txt | 18 ++++++++++++------ 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index 2bb395ffece53..1cc9bacf4e5eb 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -71,24 +71,26 @@ if(CLANG_BUILT_STANDALONE) endif() find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_DIR}") - list(APPEND CMAKE_MODULE_PATH ${LLVM_DIR}) + list(APPEND CMAKE_MODULE_PATH "${LLVM_DIR}") # We can't check LLVM_CONFIG here, because find_package(LLVM ...) also sets # LLVM_CONFIG. if (NOT LLVM_CONFIG_FOUND) # Pull values from LLVMConfig.cmake. We can drop this once the llvm-config # path is removed. - set(MAIN_INCLUDE_DIR ${LLVM_INCLUDE_DIR}) - set(LLVM_OBJ_DIR ${LLVM_BINARY_DIR}) - set(TOOLS_BINARY_DIR ${LLVM_TOOLS_BINARY_DIR}) - set(LIBRARY_DIR ${LLVM_LIBRARY_DIR}) - endif() - - set(LLVM_MAIN_INCLUDE_DIR ${MAIN_INCLUDE_DIR} CACHE PATH "Path to llvm/include") - set(LLVM_BINARY_DIR ${LLVM_OBJ_ROOT} CACHE PATH "Path to LLVM build tree") - set(LLVM_MAIN_SRC_DIR ${MAIN_SRC_DIR} CACHE PATH "Path to LLVM source tree") - set(LLVM_TOOLS_BINARY_DIR ${TOOLS_BINARY_DIR} CACHE PATH "Path to llvm/bin") - set(LLVM_LIBRARY_DIR ${LIBRARY_DIR} CACHE PATH "Path to llvm/lib") + set(MAIN_INCLUDE_DIR "${LLVM_INCLUDE_DIR}") + set(LLVM_OBJ_DIR "${LLVM_BINARY_DIR}") + # N.B. this is just a default value, the CACHE PATHs below can be overriden. + set(MAIN_SRC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../llvm") + set(TOOLS_BINARY_DIR "${LLVM_TOOLS_BINARY_DIR}") + set(LIBRARY_DIR "${LLVM_LIBRARY_DIR}") + endif() + + set(LLVM_MAIN_INCLUDE_DIR "${MAIN_INCLUDE_DIR}" CACHE PATH "Path to llvm/include") + set(LLVM_BINARY_DIR "${LLVM_OBJ_ROOT}" CACHE PATH "Path to LLVM build tree") + set(LLVM_MAIN_SRC_DIR "${MAIN_SRC_DIR}" CACHE PATH "Path to LLVM source tree") + set(LLVM_TOOLS_BINARY_DIR "${TOOLS_BINARY_DIR}" CACHE PATH "Path to llvm/bin") + set(LLVM_LIBRARY_DIR "${LIBRARY_DIR}" CACHE PATH "Path to llvm/lib") find_program(LLVM_TABLEGEN_EXE "llvm-tblgen" ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) diff --git a/lld/CMakeLists.txt b/lld/CMakeLists.txt index 1a53c5bf47a8d..9bcc135665d02 100644 --- a/lld/CMakeLists.txt +++ b/lld/CMakeLists.txt @@ -15,6 +15,10 @@ if(LLD_BUILT_STANDALONE) # Rely on llvm-config. set(LLVM_CONFIG_OUTPUT) + if(NOT LLVM_CONFIG) + # back compat + set(LLVM_CONFIG "${LLVM_CONFIG_PATH}") + endif() if(LLVM_CONFIG) set (LLVM_CONFIG_FOUND 1) message(STATUS "Found LLVM_CONFIG as ${LLVM_CONFIG}") @@ -55,20 +59,22 @@ if(LLD_BUILT_STANDALONE) endif() find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_DIR}") - list(APPEND CMAKE_MODULE_PATH ${LLVM_DIR}) + list(APPEND CMAKE_MODULE_PATH "${LLVM_DIR}") # We can't check LLVM_CONFIG here, because find_package(LLVM ...) also sets # LLVM_CONFIG. if (NOT LLVM_CONFIG_FOUND) # Pull values from LLVMConfig.cmake. We can drop this once the llvm-config # path is removed. - set(MAIN_INCLUDE_DIR ${LLVM_INCLUDE_DIR}) - set(LLVM_OBJ_DIR ${LLVM_BINARY_DIR}) + set(MAIN_INCLUDE_DIR "${LLVM_INCLUDE_DIR}") + set(LLVM_OBJ_DIR "${LLVM_BINARY_DIR}") + # N.B. this is just a default value, the CACHE PATHs below can be overriden. + set(MAIN_SRC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../llvm") endif() - set(LLVM_MAIN_INCLUDE_DIR ${MAIN_INCLUDE_DIR} CACHE PATH "Path to llvm/include") - set(LLVM_BINARY_DIR ${LLVM_OBJ_ROOT} CACHE PATH "Path to LLVM build tree") - set(LLVM_MAIN_SRC_DIR ${MAIN_SRC_DIR} CACHE PATH "Path to LLVM source tree") + set(LLVM_MAIN_INCLUDE_DIR "${MAIN_INCLUDE_DIR}" CACHE PATH "Path to llvm/include") + set(LLVM_BINARY_DIR "${LLVM_OBJ_ROOT}" CACHE PATH "Path to LLVM build tree") + set(LLVM_MAIN_SRC_DIR "${MAIN_SRC_DIR}" CACHE PATH "Path to LLVM source tree") find_program(LLVM_TABLEGEN_EXE "llvm-tblgen" ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) From e6b508f49ae951b67ed99218003f9c966e59e2ae Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Thu, 3 Feb 2022 09:36:03 +0000 Subject: [PATCH 041/316] [LV] Use VScaleForTuning to allow wider epilogue VFs. When the main loop is e.g. VF=vscale x 1 and the epilogue VF cannot be any smaller, the vectorizer should try to estimate how many lanes are executed at runtime and allow a suitable fixed-width VF to be chosen. It can use VScaleForTuning to figure out what a suitable fixed-width VF could be. For the case where the main loop VF is VF=vscale x 1, and VScaleForTuning=8, it could still choose an epilogue VF upto VF=4. This was a bit tricky to test, so this patch also introduces a wrapper function to get 'VScaleForTuning' by also considering vscale_range. If min and max are equal, then that will be the vscale we compile for. It makes little sense to tune for a different width if the code will not be portable for other widths. Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D118709 (cherry picked from commit eaee477edafed691dae206cea7c0a42893eb2821) --- .../Transforms/Vectorize/LoopVectorize.cpp | 35 +++- .../LoopVectorize/AArch64/sve-epilog-vect.ll | 193 +++++++++++++++++- 2 files changed, 218 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 3290439ecd070..21c16f07e2377 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1701,6 +1701,11 @@ class LoopVectorizationCostModel { private: unsigned NumPredStores = 0; + /// Convenience function that returns the value of vscale_range iff + /// vscale_range.min == vscale_range.max or otherwise returns the value + /// returned by the corresponding TLI method. + Optional getVScaleForTuning() const; + /// \return An upper bound for the vectorization factors for both /// fixed and scalable vectorization, where the minimum-known number of /// elements is a power-of-2 larger than zero. If scalable vectorization is @@ -5600,6 +5605,18 @@ ElementCount LoopVectorizationCostModel::getMaximizedVFForTarget( return MaxVF; } +Optional LoopVectorizationCostModel::getVScaleForTuning() const { + if (TheFunction->hasFnAttribute(Attribute::VScaleRange)) { + auto Attr = TheFunction->getFnAttribute(Attribute::VScaleRange); + auto Min = Attr.getVScaleRangeMin(); + auto Max = Attr.getVScaleRangeMax(); + if (Max && Min == Max) + return Max; + } + + return TTI.getVScaleForTuning(); +} + bool LoopVectorizationCostModel::isMoreProfitable( const VectorizationFactor &A, const VectorizationFactor &B) const { InstructionCost CostA = A.Cost; @@ -5624,7 +5641,7 @@ bool LoopVectorizationCostModel::isMoreProfitable( // Improve estimate for the vector width if it is scalable. unsigned EstimatedWidthA = A.Width.getKnownMinValue(); unsigned EstimatedWidthB = B.Width.getKnownMinValue(); - if (Optional VScale = TTI.getVScaleForTuning()) { + if (Optional VScale = getVScaleForTuning()) { if (A.Width.isScalable()) EstimatedWidthA *= VScale.getValue(); if (B.Width.isScalable()) @@ -5673,7 +5690,7 @@ VectorizationFactor LoopVectorizationCostModel::selectVectorizationFactor( #ifndef NDEBUG unsigned AssumedMinimumVscale = 1; - if (Optional VScale = TTI.getVScaleForTuning()) + if (Optional VScale = getVScaleForTuning()) AssumedMinimumVscale = VScale.getValue(); unsigned Width = Candidate.Width.isScalable() @@ -5885,8 +5902,20 @@ LoopVectorizationCostModel::selectEpilogueVectorizationFactor( return Result; } + // If MainLoopVF = vscale x 2, and vscale is expected to be 4, then we know + // the main loop handles 8 lanes per iteration. We could still benefit from + // vectorizing the epilogue loop with VF=4. + ElementCount EstimatedRuntimeVF = MainLoopVF; + if (MainLoopVF.isScalable()) { + EstimatedRuntimeVF = ElementCount::getFixed(MainLoopVF.getKnownMinValue()); + if (Optional VScale = getVScaleForTuning()) + EstimatedRuntimeVF *= VScale.getValue(); + } + for (auto &NextVF : ProfitableVFs) - if (ElementCount::isKnownLT(NextVF.Width, MainLoopVF) && + if (((!NextVF.Width.isScalable() && MainLoopVF.isScalable() && + ElementCount::isKnownLT(NextVF.Width, EstimatedRuntimeVF)) || + ElementCount::isKnownLT(NextVF.Width, MainLoopVF)) && (Result.Width.isScalar() || isMoreProfitable(NextVF, Result)) && LVP.hasPlanWithVF(NextVF.Width)) Result = NextVF; diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll index e68bb7ecb456a..ab3cdebb31e50 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll @@ -2,24 +2,22 @@ ; REQUIRES: asserts ; RUN: opt < %s -loop-vectorize -force-vector-interleave=2 -epilogue-vectorization-minimum-VF=0 --debug-only=loop-vectorize -force-target-instruction-cost=1 -S 2>%t | FileCheck %s --check-prefix=CHECK ; RUN: cat %t | FileCheck %s --check-prefix=DEBUG -; RUN: opt < %s -loop-vectorize -force-vector-interleave=2 -epilogue-vectorization-minimum-VF=8 --debug-only=loop-vectorize -S 2>%t | FileCheck %s --check-prefix=CHECK -; RUN: cat %t | FileCheck %s --check-prefix=DEBUG ; RUN: opt < %s -loop-vectorize -force-vector-interleave=2 -epilogue-vectorization-force-VF=8 --debug-only=loop-vectorize -S 2>%t | FileCheck %s --check-prefix=CHECK-VF8 ; RUN: cat %t | FileCheck %s --check-prefix=DEBUG-FORCED target triple = "aarch64-linux-gnu" -; DEBUG: LV: Checking a loop in "f1" +; DEBUG: LV: Checking a loop in "main_vf_vscale_x_16" ; DEBUG: Create Skeleton for epilogue vectorized loop (first pass) ; DEBUG: Main Loop VF:vscale x 16, Main Loop UF:2, Epilogue Loop VF:vscale x 8, Epilogue Loop UF:1 -; DEBUG-FORCED: LV: Checking a loop in "f1" +; DEBUG-FORCED: LV: Checking a loop in "main_vf_vscale_x_16" ; DEBUG-FORCED: LEV: Epilogue vectorization factor is forced. ; DEBUG-FORCED: Create Skeleton for epilogue vectorized loop (first pass) ; DEBUG-FORCED: Main Loop VF:vscale x 16, Main Loop UF:2, Epilogue Loop VF:8, Epilogue Loop UF:1 -define void @f1(i8* %A) #0 { -; CHECK-LABEL: @f1( +define void @main_vf_vscale_x_16(i8* %A) #0 { +; CHECK-LABEL: @main_vf_vscale_x_16( ; CHECK-NEXT: iter.check: ; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 8 @@ -105,7 +103,7 @@ define void @f1(i8* %A) #0 { ; CHECK: exit: ; CHECK-NEXT: ret void ; -; CHECK-VF8-LABEL: @f1( +; CHECK-VF8-LABEL: @main_vf_vscale_x_16( ; CHECK-VF8-NEXT: iter.check: ; CHECK-VF8-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] ; CHECK-VF8: vector.main.loop.iter.check: @@ -195,4 +193,185 @@ exit: ret void } + +; DEBUG: LV: Checking a loop in "main_vf_vscale_x_2" +; DEBUG: Create Skeleton for epilogue vectorized loop (first pass) +; DEBUG: Main Loop VF:vscale x 2, Main Loop UF:2, Epilogue Loop VF:8, Epilogue Loop UF:1 + +; DEBUG-FORCED: LV: Checking a loop in "main_vf_vscale_x_2" +; DEBUG-FORCED: LEV: Epilogue vectorization factor is forced. +; DEBUG-FORCED: Create Skeleton for epilogue vectorized loop (first pass) +; DEBUG-FORCED: Main Loop VF:vscale x 2, Main Loop UF:2, Epilogue Loop VF:8, Epilogue Loop UF:1 + +; When the vector.body uses VF=vscale x 1 (or VF=vscale x 2 because +; that's the minimum supported VF by SVE), we could still use a wide +; fixed-width VF=8 for the epilogue if the vectors are known to be +; sufficiently wide. This information can be deduced from vscale_range or +; VScaleForTuning (set by mcpu/mtune). +define void @main_vf_vscale_x_2(i64* %A) #0 vscale_range(8, 8) { +; CHECK-LABEL: @main_vf_vscale_x_2( +; CHECK-NEXT: iter.check: +; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; CHECK: vector.main.loop.iter.check: +; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4 +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 1 +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, i64* [[A:%.*]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[TMP9]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, i64* [[TMP10]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64* [[TMP12]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i64 1, i32 0), poison, zeroinitializer), * [[TMP13]], align 1 +; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vscale.i32() +; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], 2 +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i64, i64* [[TMP10]], i32 [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = bitcast i64* [[TMP16]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i64 1, i32 0), poison, zeroinitializer), * [[TMP17]], align 1 +; CHECK-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP19]] +; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; CHECK: vec.epilog.iter.check: +; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 1024, [[N_VEC]] +; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 8 +; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; CHECK: vec.epilog.ph: +; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; CHECK: vec.epilog.vector.body: +; CHECK-NEXT: [[INDEX2:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[INDEX2]], 0 +; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, i64* [[TMP22]], i32 0 +; CHECK-NEXT: [[TMP24:%.*]] = bitcast i64* [[TMP23]] to <8 x i64>* +; CHECK-NEXT: store <8 x i64> , <8 x i64>* [[TMP24]], align 1 +; CHECK-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX2]], 8 +; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 1024 +; CHECK-NEXT: br i1 [[TMP25]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK: vec.epilog.middle.block: +; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i64 1024, 1024 +; CHECK-NEXT: br i1 [[CMP_N1]], label [[EXIT_LOOPEXIT:%.*]], label [[VEC_EPILOG_SCALAR_PH]] +; CHECK: vec.epilog.scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1024, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[IV]] +; CHECK-NEXT: store i64 1, i64* [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], 1024 +; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK: exit.loopexit: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +; CHECK-VF8-LABEL: @main_vf_vscale_x_2( +; CHECK-VF8-NEXT: iter.check: +; CHECK-VF8-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; CHECK-VF8: vector.main.loop.iter.check: +; CHECK-VF8-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-VF8-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 +; CHECK-VF8-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] +; CHECK-VF8-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK-VF8: vector.ph: +; CHECK-VF8-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-VF8-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4 +; CHECK-VF8-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] +; CHECK-VF8-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] +; CHECK-VF8-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK-VF8: vector.body: +; CHECK-VF8-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-VF8-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 +; CHECK-VF8-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-VF8-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 2 +; CHECK-VF8-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 0 +; CHECK-VF8-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 1 +; CHECK-VF8-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], [[TMP8]] +; CHECK-VF8-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, i64* [[A:%.*]], i64 [[TMP4]] +; CHECK-VF8-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[TMP9]] +; CHECK-VF8-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, i64* [[TMP10]], i32 0 +; CHECK-VF8-NEXT: [[TMP13:%.*]] = bitcast i64* [[TMP12]] to * +; CHECK-VF8-NEXT: store shufflevector ( insertelement ( poison, i64 1, i32 0), poison, zeroinitializer), * [[TMP13]], align 1 +; CHECK-VF8-NEXT: [[TMP14:%.*]] = call i32 @llvm.vscale.i32() +; CHECK-VF8-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], 2 +; CHECK-VF8-NEXT: [[TMP16:%.*]] = getelementptr inbounds i64, i64* [[TMP10]], i32 [[TMP15]] +; CHECK-VF8-NEXT: [[TMP17:%.*]] = bitcast i64* [[TMP16]] to * +; CHECK-VF8-NEXT: store shufflevector ( insertelement ( poison, i64 1, i32 0), poison, zeroinitializer), * [[TMP17]], align 1 +; CHECK-VF8-NEXT: [[TMP18:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-VF8-NEXT: [[TMP19:%.*]] = mul i64 [[TMP18]], 4 +; CHECK-VF8-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP19]] +; CHECK-VF8-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-VF8-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-VF8: middle.block: +; CHECK-VF8-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] +; CHECK-VF8-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; CHECK-VF8: vec.epilog.iter.check: +; CHECK-VF8-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 1024, [[N_VEC]] +; CHECK-VF8-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 8 +; CHECK-VF8-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; CHECK-VF8: vec.epilog.ph: +; CHECK-VF8-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; CHECK-VF8-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; CHECK-VF8: vec.epilog.vector.body: +; CHECK-VF8-NEXT: [[INDEX2:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT3:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-VF8-NEXT: [[TMP21:%.*]] = add i64 [[INDEX2]], 0 +; CHECK-VF8-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[TMP21]] +; CHECK-VF8-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, i64* [[TMP22]], i32 0 +; CHECK-VF8-NEXT: [[TMP24:%.*]] = bitcast i64* [[TMP23]] to <8 x i64>* +; CHECK-VF8-NEXT: store <8 x i64> , <8 x i64>* [[TMP24]], align 1 +; CHECK-VF8-NEXT: [[INDEX_NEXT3]] = add nuw i64 [[INDEX2]], 8 +; CHECK-VF8-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT3]], 1024 +; CHECK-VF8-NEXT: br i1 [[TMP25]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK-VF8: vec.epilog.middle.block: +; CHECK-VF8-NEXT: [[CMP_N1:%.*]] = icmp eq i64 1024, 1024 +; CHECK-VF8-NEXT: br i1 [[CMP_N1]], label [[EXIT_LOOPEXIT:%.*]], label [[VEC_EPILOG_SCALAR_PH]] +; CHECK-VF8: vec.epilog.scalar.ph: +; CHECK-VF8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1024, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; CHECK-VF8-NEXT: br label [[FOR_BODY:%.*]] +; CHECK-VF8: for.body: +; CHECK-VF8-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-VF8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 [[IV]] +; CHECK-VF8-NEXT: store i64 1, i64* [[ARRAYIDX]], align 1 +; CHECK-VF8-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 +; CHECK-VF8-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], 1024 +; CHECK-VF8-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[EXIT_LOOPEXIT]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK-VF8: exit.loopexit: +; CHECK-VF8-NEXT: br label [[EXIT]] +; CHECK-VF8: exit: +; CHECK-VF8-NEXT: ret void +; +entry: + br label %for.body + +for.body: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] + %arrayidx = getelementptr inbounds i64, i64* %A, i64 %iv + store i64 1, i64* %arrayidx, align 1 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond = icmp ne i64 %iv.next, 1024 + br i1 %exitcond, label %for.body, label %exit + +exit: + ret void +} + attributes #0 = { "target-features"="+sve" } From ebe5b447270cc77ca8000d50d4032bc806658086 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 4 Feb 2022 10:35:17 -0500 Subject: [PATCH 042/316] [x86] add test coverage for AMD Ryzen fast sqrt codegen; NFC (cherry picked from commit 1eb4f88bfef1ab93b8286fdfd05a8b814507e329) --- llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll | 147 ++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll index df0a6adff100c..ab97dd6f4b33e 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll @@ -3,6 +3,8 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell | FileCheck %s --check-prefixes=FAST-SCALAR,BDW ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,SKL +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN1 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN3 define float @f32_no_daz(float %f) #0 { ; NHM-LABEL: f32_no_daz: @@ -24,6 +26,19 @@ define float @f32_no_daz(float %f) #0 { ; FAST-SCALAR: # %bb.0: ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: retq +; +; SLOW-SCALAR-LABEL: f32_no_daz: +; SLOW-SCALAR: # %bb.0: +; SLOW-SCALAR-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 +; SLOW-SCALAR-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN] +; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm0, %xmm2 +; SLOW-SCALAR-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem +; SLOW-SCALAR-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; SLOW-SCALAR-NEXT: vandps %xmm3, %xmm0, %xmm0 +; SLOW-SCALAR-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm2, %xmm1 +; SLOW-SCALAR-NEXT: vandnps %xmm1, %xmm0, %xmm0 +; SLOW-SCALAR-NEXT: retq %call = tail call fast float @llvm.sqrt.f32(float %f) #2 ret float %call } @@ -80,6 +95,38 @@ define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 { ; SKL: # %bb.0: ; SKL-NEXT: vsqrtps %xmm0, %xmm0 ; SKL-NEXT: retq +; +; ZN1-LABEL: v4f32_no_daz: +; ZN1: # %bb.0: +; ZN1-NEXT: vrsqrtps %xmm0, %xmm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN] +; ZN1-NEXT: vmulps %xmm1, %xmm0, %xmm2 +; ZN1-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN1-NEXT: vandps %xmm4, %xmm0, %xmm0 +; ZN1-NEXT: vmulps %xmm1, %xmm2, %xmm1 +; ZN1-NEXT: vmulps %xmm3, %xmm1, %xmm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] +; ZN1-NEXT: vcmpleps %xmm0, %xmm3, %xmm0 +; ZN1-NEXT: vandps %xmm1, %xmm0, %xmm0 +; ZN1-NEXT: retq +; +; ZN3-LABEL: v4f32_no_daz: +; ZN3: # %bb.0: +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN3-NEXT: vrsqrtps %xmm0, %xmm1 +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN] +; ZN3-NEXT: vmulps %xmm1, %xmm0, %xmm2 +; ZN3-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN3-NEXT: vandps %xmm4, %xmm0, %xmm0 +; ZN3-NEXT: vmulps %xmm1, %xmm2, %xmm1 +; ZN3-NEXT: vmulps %xmm3, %xmm1, %xmm1 +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] +; ZN3-NEXT: vcmpleps %xmm0, %xmm3, %xmm0 +; ZN3-NEXT: vandps %xmm1, %xmm0, %xmm0 +; ZN3-NEXT: retq %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 ret <4 x float> %call } @@ -151,6 +198,38 @@ define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 { ; SKL: # %bb.0: ; SKL-NEXT: vsqrtps %ymm0, %ymm0 ; SKL-NEXT: retq +; +; ZN1-LABEL: v8f32_no_daz: +; ZN1: # %bb.0: +; ZN1-NEXT: vrsqrtps %ymm0, %ymm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] +; ZN1-NEXT: vmulps %ymm1, %ymm0, %ymm2 +; ZN1-NEXT: vandps %ymm4, %ymm0, %ymm0 +; ZN1-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN1-NEXT: vmulps %ymm1, %ymm2, %ymm1 +; ZN1-NEXT: vmulps %ymm3, %ymm1, %ymm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] +; ZN1-NEXT: vcmpleps %ymm0, %ymm3, %ymm0 +; ZN1-NEXT: vandps %ymm1, %ymm0, %ymm0 +; ZN1-NEXT: retq +; +; ZN3-LABEL: v8f32_no_daz: +; ZN3: # %bb.0: +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN3-NEXT: vrsqrtps %ymm0, %ymm1 +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] +; ZN3-NEXT: vmulps %ymm1, %ymm0, %ymm2 +; ZN3-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN3-NEXT: vandps %ymm4, %ymm0, %ymm0 +; ZN3-NEXT: vmulps %ymm1, %ymm2, %ymm1 +; ZN3-NEXT: vmulps %ymm3, %ymm1, %ymm1 +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] +; ZN3-NEXT: vcmpleps %ymm0, %ymm3, %ymm0 +; ZN3-NEXT: vandps %ymm1, %ymm0, %ymm0 +; ZN3-NEXT: retq %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2 ret <8 x float> %call } @@ -177,6 +256,18 @@ define float @f32_daz(float %f) #1 { ; FAST-SCALAR: # %bb.0: ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: retq +; +; SLOW-SCALAR-LABEL: f32_daz: +; SLOW-SCALAR: # %bb.0: +; SLOW-SCALAR-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 +; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm0, %xmm2 +; SLOW-SCALAR-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem +; SLOW-SCALAR-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm2, %xmm1 +; SLOW-SCALAR-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; SLOW-SCALAR-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0 +; SLOW-SCALAR-NEXT: vandnps %xmm1, %xmm0, %xmm0 +; SLOW-SCALAR-NEXT: retq %call = tail call fast float @llvm.sqrt.f32(float %f) #2 ret float %call } @@ -228,6 +319,34 @@ define <4 x float> @v4f32_daz(<4 x float> %f) #1 { ; SKL: # %bb.0: ; SKL-NEXT: vsqrtps %xmm0, %xmm0 ; SKL-NEXT: retq +; +; ZN1-LABEL: v4f32_daz: +; ZN1: # %bb.0: +; ZN1-NEXT: vrsqrtps %xmm0, %xmm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN1-NEXT: vmulps %xmm1, %xmm0, %xmm2 +; ZN1-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 +; ZN1-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN1-NEXT: vmulps %xmm1, %xmm2, %xmm1 +; ZN1-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; ZN1-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0 +; ZN1-NEXT: vmulps %xmm3, %xmm1, %xmm1 +; ZN1-NEXT: vandps %xmm1, %xmm0, %xmm0 +; ZN1-NEXT: retq +; +; ZN3-LABEL: v4f32_daz: +; ZN3: # %bb.0: +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN3-NEXT: vrsqrtps %xmm0, %xmm1 +; ZN3-NEXT: vmulps %xmm1, %xmm0, %xmm2 +; ZN3-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 +; ZN3-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN3-NEXT: vmulps %xmm1, %xmm2, %xmm1 +; ZN3-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; ZN3-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0 +; ZN3-NEXT: vmulps %xmm3, %xmm1, %xmm1 +; ZN3-NEXT: vandps %xmm1, %xmm0, %xmm0 +; ZN3-NEXT: retq %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 ret <4 x float> %call } @@ -290,6 +409,34 @@ define <8 x float> @v8f32_daz(<8 x float> %f) #1 { ; SKL: # %bb.0: ; SKL-NEXT: vsqrtps %ymm0, %ymm0 ; SKL-NEXT: retq +; +; ZN1-LABEL: v8f32_daz: +; ZN1: # %bb.0: +; ZN1-NEXT: vrsqrtps %ymm0, %ymm1 +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN1-NEXT: vmulps %ymm1, %ymm0, %ymm2 +; ZN1-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 +; ZN1-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN1-NEXT: vmulps %ymm1, %ymm2, %ymm1 +; ZN1-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; ZN1-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0 +; ZN1-NEXT: vmulps %ymm3, %ymm1, %ymm1 +; ZN1-NEXT: vandps %ymm1, %ymm0, %ymm0 +; ZN1-NEXT: retq +; +; ZN3-LABEL: v8f32_daz: +; ZN3: # %bb.0: +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] +; ZN3-NEXT: vrsqrtps %ymm0, %ymm1 +; ZN3-NEXT: vmulps %ymm1, %ymm0, %ymm2 +; ZN3-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 +; ZN3-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] +; ZN3-NEXT: vmulps %ymm1, %ymm2, %ymm1 +; ZN3-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; ZN3-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0 +; ZN3-NEXT: vmulps %ymm3, %ymm1, %ymm1 +; ZN3-NEXT: vandps %ymm1, %ymm0, %ymm0 +; ZN3-NEXT: retq %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2 ret <8 x float> %call } From 0f27bf28d255e2b227865aa0f5f6d63273eacefd Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 4 Feb 2022 13:13:01 -0500 Subject: [PATCH 043/316] [x86] enable fast sqrtss/sqrtps tuning for AMD Zen cores As discussed in D118534, all of the recent AMD CPUs have relatively fast (<14 cycle latency) "sqrtss" and "sqrtps" instructions: https://uops.info/table.html?search=sqrtps&cb_lat=on&cb_tp=on&cb_SNB=on&cb_SKL=on&cb_ZENp=on&cb_ZEN2=on&cb_ZEN3=on&cb_measurements=on&cb_avx=on&cb_sse=on So we should set this tuning flag to alter codegen of plain "sqrt(X)" expansion (as opposed to reciprocal-sqrt - there is other test coverage for that pattern). The expansion is both slower and less accurate than the hardware instruction. Differential Revision: https://reviews.llvm.org/D119001 (cherry picked from commit fff3e1dbaa9ee2d91dc15b39defa88346f03a4c2) --- llvm/lib/Target/X86/X86.td | 2 + llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll | 183 ++------------------ 2 files changed, 21 insertions(+), 164 deletions(-) diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 380507308c3dd..bafba2ee09c37 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1169,6 +1169,8 @@ def ProcessorFeatures { TuningFastBEXTR, TuningFast15ByteNOP, TuningBranchFusion, + TuningFastScalarFSQRT, + TuningFastVectorFSQRT, TuningFastScalarShiftMasks, TuningFastMOVBE, TuningSlowSHLD, diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll index ab97dd6f4b33e..6d2fbe0364dbd 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem | FileCheck %s --check-prefixes=NHM ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell | FileCheck %s --check-prefixes=FAST-SCALAR,BDW -; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,SKL -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN1 -; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN3 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR define float @f32_no_daz(float %f) #0 { ; NHM-LABEL: f32_no_daz: @@ -26,19 +26,6 @@ define float @f32_no_daz(float %f) #0 { ; FAST-SCALAR: # %bb.0: ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: retq -; -; SLOW-SCALAR-LABEL: f32_no_daz: -; SLOW-SCALAR: # %bb.0: -; SLOW-SCALAR-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 -; SLOW-SCALAR-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN] -; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm0, %xmm2 -; SLOW-SCALAR-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem -; SLOW-SCALAR-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 -; SLOW-SCALAR-NEXT: vandps %xmm3, %xmm0, %xmm0 -; SLOW-SCALAR-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm2, %xmm1 -; SLOW-SCALAR-NEXT: vandnps %xmm1, %xmm0, %xmm0 -; SLOW-SCALAR-NEXT: retq %call = tail call fast float @llvm.sqrt.f32(float %f) #2 ret float %call } @@ -91,42 +78,10 @@ define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 { ; BDW-NEXT: vandps %xmm1, %xmm0, %xmm0 ; BDW-NEXT: retq ; -; SKL-LABEL: v4f32_no_daz: -; SKL: # %bb.0: -; SKL-NEXT: vsqrtps %xmm0, %xmm0 -; SKL-NEXT: retq -; -; ZN1-LABEL: v4f32_no_daz: -; ZN1: # %bb.0: -; ZN1-NEXT: vrsqrtps %xmm0, %xmm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN] -; ZN1-NEXT: vmulps %xmm1, %xmm0, %xmm2 -; ZN1-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN1-NEXT: vandps %xmm4, %xmm0, %xmm0 -; ZN1-NEXT: vmulps %xmm1, %xmm2, %xmm1 -; ZN1-NEXT: vmulps %xmm3, %xmm1, %xmm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] -; ZN1-NEXT: vcmpleps %xmm0, %xmm3, %xmm0 -; ZN1-NEXT: vandps %xmm1, %xmm0, %xmm0 -; ZN1-NEXT: retq -; -; ZN3-LABEL: v4f32_no_daz: -; ZN3: # %bb.0: -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN3-NEXT: vrsqrtps %xmm0, %xmm1 -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN] -; ZN3-NEXT: vmulps %xmm1, %xmm0, %xmm2 -; ZN3-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN3-NEXT: vandps %xmm4, %xmm0, %xmm0 -; ZN3-NEXT: vmulps %xmm1, %xmm2, %xmm1 -; ZN3-NEXT: vmulps %xmm3, %xmm1, %xmm1 -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] -; ZN3-NEXT: vcmpleps %xmm0, %xmm3, %xmm0 -; ZN3-NEXT: vandps %xmm1, %xmm0, %xmm0 -; ZN3-NEXT: retq +; FAST-VECTOR-LABEL: v4f32_no_daz: +; FAST-VECTOR: # %bb.0: +; FAST-VECTOR-NEXT: vsqrtps %xmm0, %xmm0 +; FAST-VECTOR-NEXT: retq %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 ret <4 x float> %call } @@ -194,42 +149,10 @@ define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 { ; BDW-NEXT: vandps %ymm1, %ymm0, %ymm0 ; BDW-NEXT: retq ; -; SKL-LABEL: v8f32_no_daz: -; SKL: # %bb.0: -; SKL-NEXT: vsqrtps %ymm0, %ymm0 -; SKL-NEXT: retq -; -; ZN1-LABEL: v8f32_no_daz: -; ZN1: # %bb.0: -; ZN1-NEXT: vrsqrtps %ymm0, %ymm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] -; ZN1-NEXT: vmulps %ymm1, %ymm0, %ymm2 -; ZN1-NEXT: vandps %ymm4, %ymm0, %ymm0 -; ZN1-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN1-NEXT: vmulps %ymm1, %ymm2, %ymm1 -; ZN1-NEXT: vmulps %ymm3, %ymm1, %ymm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] -; ZN1-NEXT: vcmpleps %ymm0, %ymm3, %ymm0 -; ZN1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; ZN1-NEXT: retq -; -; ZN3-LABEL: v8f32_no_daz: -; ZN3: # %bb.0: -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN3-NEXT: vrsqrtps %ymm0, %ymm1 -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm4 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] -; ZN3-NEXT: vmulps %ymm1, %ymm0, %ymm2 -; ZN3-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN3-NEXT: vandps %ymm4, %ymm0, %ymm0 -; ZN3-NEXT: vmulps %ymm1, %ymm2, %ymm1 -; ZN3-NEXT: vmulps %ymm3, %ymm1, %ymm1 -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] -; ZN3-NEXT: vcmpleps %ymm0, %ymm3, %ymm0 -; ZN3-NEXT: vandps %ymm1, %ymm0, %ymm0 -; ZN3-NEXT: retq +; FAST-VECTOR-LABEL: v8f32_no_daz: +; FAST-VECTOR: # %bb.0: +; FAST-VECTOR-NEXT: vsqrtps %ymm0, %ymm0 +; FAST-VECTOR-NEXT: retq %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2 ret <8 x float> %call } @@ -256,18 +179,6 @@ define float @f32_daz(float %f) #1 { ; FAST-SCALAR: # %bb.0: ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: retq -; -; SLOW-SCALAR-LABEL: f32_daz: -; SLOW-SCALAR: # %bb.0: -; SLOW-SCALAR-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 -; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm0, %xmm2 -; SLOW-SCALAR-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem -; SLOW-SCALAR-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 -; SLOW-SCALAR-NEXT: vmulss %xmm1, %xmm2, %xmm1 -; SLOW-SCALAR-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; SLOW-SCALAR-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0 -; SLOW-SCALAR-NEXT: vandnps %xmm1, %xmm0, %xmm0 -; SLOW-SCALAR-NEXT: retq %call = tail call fast float @llvm.sqrt.f32(float %f) #2 ret float %call } @@ -315,38 +226,10 @@ define <4 x float> @v4f32_daz(<4 x float> %f) #1 { ; BDW-NEXT: vandps %xmm1, %xmm0, %xmm0 ; BDW-NEXT: retq ; -; SKL-LABEL: v4f32_daz: -; SKL: # %bb.0: -; SKL-NEXT: vsqrtps %xmm0, %xmm0 -; SKL-NEXT: retq -; -; ZN1-LABEL: v4f32_daz: -; ZN1: # %bb.0: -; ZN1-NEXT: vrsqrtps %xmm0, %xmm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN1-NEXT: vmulps %xmm1, %xmm0, %xmm2 -; ZN1-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 -; ZN1-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN1-NEXT: vmulps %xmm1, %xmm2, %xmm1 -; ZN1-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; ZN1-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0 -; ZN1-NEXT: vmulps %xmm3, %xmm1, %xmm1 -; ZN1-NEXT: vandps %xmm1, %xmm0, %xmm0 -; ZN1-NEXT: retq -; -; ZN3-LABEL: v4f32_daz: -; ZN3: # %bb.0: -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN3-NEXT: vrsqrtps %xmm0, %xmm1 -; ZN3-NEXT: vmulps %xmm1, %xmm0, %xmm2 -; ZN3-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 -; ZN3-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN3-NEXT: vmulps %xmm1, %xmm2, %xmm1 -; ZN3-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; ZN3-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0 -; ZN3-NEXT: vmulps %xmm3, %xmm1, %xmm1 -; ZN3-NEXT: vandps %xmm1, %xmm0, %xmm0 -; ZN3-NEXT: retq +; FAST-VECTOR-LABEL: v4f32_daz: +; FAST-VECTOR: # %bb.0: +; FAST-VECTOR-NEXT: vsqrtps %xmm0, %xmm0 +; FAST-VECTOR-NEXT: retq %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 ret <4 x float> %call } @@ -405,38 +288,10 @@ define <8 x float> @v8f32_daz(<8 x float> %f) #1 { ; BDW-NEXT: vandps %ymm1, %ymm0, %ymm0 ; BDW-NEXT: retq ; -; SKL-LABEL: v8f32_daz: -; SKL: # %bb.0: -; SKL-NEXT: vsqrtps %ymm0, %ymm0 -; SKL-NEXT: retq -; -; ZN1-LABEL: v8f32_daz: -; ZN1: # %bb.0: -; ZN1-NEXT: vrsqrtps %ymm0, %ymm1 -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN1-NEXT: vmulps %ymm1, %ymm0, %ymm2 -; ZN1-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 -; ZN1-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN1-NEXT: vmulps %ymm1, %ymm2, %ymm1 -; ZN1-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; ZN1-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0 -; ZN1-NEXT: vmulps %ymm3, %ymm1, %ymm1 -; ZN1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; ZN1-NEXT: retq -; -; ZN3-LABEL: v8f32_daz: -; ZN3: # %bb.0: -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] -; ZN3-NEXT: vrsqrtps %ymm0, %ymm1 -; ZN3-NEXT: vmulps %ymm1, %ymm0, %ymm2 -; ZN3-NEXT: vfmadd231ps {{.*#+}} ymm3 = (ymm2 * ymm1) + ymm3 -; ZN3-NEXT: vbroadcastss {{.*#+}} ymm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] -; ZN3-NEXT: vmulps %ymm1, %ymm2, %ymm1 -; ZN3-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; ZN3-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0 -; ZN3-NEXT: vmulps %ymm3, %ymm1, %ymm1 -; ZN3-NEXT: vandps %ymm1, %ymm0, %ymm0 -; ZN3-NEXT: retq +; FAST-VECTOR-LABEL: v8f32_daz: +; FAST-VECTOR: # %bb.0: +; FAST-VECTOR-NEXT: vsqrtps %ymm0, %ymm0 +; FAST-VECTOR-NEXT: retq %call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2 ret <8 x float> %call } From 2bae96d8a3490b1e5df19f4df56842448cb5caa7 Mon Sep 17 00:00:00 2001 From: Matt Devereau Date: Mon, 31 Jan 2022 16:24:48 +0000 Subject: [PATCH 044/316] [AArch64][SVE] Remove false register dependency for unary FP convert operations Generate movprfx for floating point convert zeroing pseudo operations Differential Revision: https://reviews.llvm.org/D118617 (cherry picked from commit 6b73a4cc7db96af1dd02db68c07fe4a807104c53) --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 53 +-- llvm/lib/Target/AArch64/SVEInstrFormats.td | 25 +- llvm/test/CodeGen/AArch64/sve-fcvt.ll | 374 ++++++++++++++++++ llvm/test/CodeGen/AArch64/sve-fpext-load.ll | 9 +- llvm/test/CodeGen/AArch64/sve-split-fcvt.ll | 54 ++- 5 files changed, 470 insertions(+), 45 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 1d162610de9ca..2397a6d320a22 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1679,60 +1679,61 @@ let Predicates = [HasSVEorStreamingSVE] in { defm FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd< 0b1111110, "fcvtzs", ZPR64, ZPR64, null_frag, AArch64fcvtzs_mt, nxv2i64, nxv2i1, nxv2f64, ElementSizeD>; defm FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd< 0b1111111, "fcvtzu", ZPR64, ZPR64, null_frag, AArch64fcvtzu_mt, nxv2i64, nxv2i1, nxv2f64, ElementSizeD>; - def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 PPR:$Pg), (nxv2f16 ZPR:$Zs), (nxv2f32 ZPR:$Zd))), - (FCVT_ZPmZ_HtoS ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + //These patterns exist to improve the code quality of conversions on unpacked types. + def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f16 ZPR:$Zs), (nxv2f32 ZPR:$Zd))), + (FCVT_ZPmZ_HtoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // FP_ROUND has an additional 'precise' flag which indicates the type of rounding. // This is ignored by the pattern below where it is matched by (i64 timm0_1) - def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 PPR:$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))), - (FCVT_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))), + (FCVT_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - // Floating-point -> signed integer - def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), + // Signed integer -> Floating-point + def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (nxv2f16 ZPR:$Zd))), - (SCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 PPR:$Pg), + def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 (SVEAllActive):$Pg), (sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (nxv4f16 ZPR:$Zd))), - (SCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f16 ZPR:$Zd))), - (SCVTF_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (SCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f32 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f32 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f32 ZPR:$Zd))), - (SCVTF_ZPmZ_StoS ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (SCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f64 (AArch64scvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f64 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f64 ZPR:$Zd))), - (SCVTF_ZPmZ_StoD ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (SCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - // Floating-point -> unsigned integer - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 PPR:$Pg), + // Unsigned integer -> Floating-point + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), (and (nxv2i64 ZPR:$Zs), (nxv2i64 (AArch64dup (i64 0xFFFF)))), (nxv2f16 ZPR:$Zd))), - (UCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), (and (nxv2i64 ZPR:$Zs), (nxv2i64 (AArch64dup (i64 0xFFFFFFFF)))), (nxv2f16 ZPR:$Zd))), - (UCVTF_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (UCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 PPR:$Pg), + def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 (SVEAllActive):$Pg), (and (nxv4i32 ZPR:$Zs), (nxv4i32 (AArch64dup (i32 0xFFFF)))), (nxv4f16 ZPR:$Zd))), - (UCVTF_ZPmZ_HtoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), (and (nxv2i64 ZPR:$Zs), (nxv2i64 (AArch64dup (i64 0xFFFFFFFF)))), (nxv2f32 ZPR:$Zd))), - (UCVTF_ZPmZ_StoS ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (UCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 PPR:$Pg), + def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), (and (nxv2i64 ZPR:$Zs), (nxv2i64 (AArch64dup (i64 0xFFFFFFFF)))), (nxv2f64 ZPR:$Zd))), - (UCVTF_ZPmZ_StoD ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; + (UCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", AArch64frintn_mt>; defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp", AArch64frintp_mt>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 9d4bdbe5d0539..37b2ac4d87594 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -370,6 +370,14 @@ class SVE_1_Op_Passthru_Round_Pat; +multiclass SVE_1_Op_PassthruUndef_Round_Pat{ + def : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), (vtd undef))), + (inst (IMPLICIT_DEF), $Op1, $Op2)>; + def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, (i64 timm0_1), vtd:$Op3)), + (inst $Op3, $Op1, $Op2)>; +} + class SVE_1_Op_Imm_OptLsl_Reverse_Pat : Pat<(vt (op (vt (AArch64dup (it (cpx i32:$imm, i32:$shift)))), (vt zprty:$Op1))), @@ -2589,8 +2597,8 @@ multiclass sve_fp_2op_p_zd opc, string asm, SDPatternOperator int_op, SDPatternOperator ir_op, ValueType vt1, ValueType vt2, ValueType vt3, ElementSizeEnum Sz> { - def NAME : sve_fp_2op_p_zd; - + def NAME : sve_fp_2op_p_zd, + SVEPseudo2Instr; // convert vt1 to a packed type for the intrinsic patterns defvar packedvt1 = !cond(!eq(!cast(vt1), "nxv2f16"): nxv8f16, !eq(!cast(vt1), "nxv4f16"): nxv8f16, @@ -2604,8 +2612,11 @@ multiclass sve_fp_2op_p_zd opc, string asm, 1 : vt3); def : SVE_3_Op_Pat(NAME)>; - def : SVE_1_Op_Passthru_Pat(NAME)>; + + def _UNDEF : PredOneOpPassthruPseudo(i_zprtype)>; + + defm : SVE_1_Op_PassthruUndef_Pat(NAME # _UNDEF)>; } multiclass sve_fp_2op_p_zdr opc, string asm, @@ -2614,7 +2625,8 @@ multiclass sve_fp_2op_p_zdr opc, string asm, SDPatternOperator int_op, SDPatternOperator ir_op, ValueType vt1, ValueType vt2, ValueType vt3, ElementSizeEnum Sz> { - def NAME : sve_fp_2op_p_zd; + def NAME : sve_fp_2op_p_zd, + SVEPseudo2Instr; // convert vt1 to a packed type for the intrinsic patterns defvar packedvt1 = !cond(!eq(!cast(vt1), "nxv2f16"): nxv8f16, @@ -2623,8 +2635,11 @@ multiclass sve_fp_2op_p_zdr opc, string asm, 1 : vt1); def : SVE_3_Op_Pat(NAME)>; - def : SVE_1_Op_Passthru_Round_Pat(NAME)>; + + def _UNDEF : PredOneOpPassthruPseudo(i_zprtype)>; + + defm : SVE_1_Op_PassthruUndef_Round_Pat(NAME # _UNDEF)>; } multiclass sve_fp_2op_p_zd_HSD opc, string asm, SDPatternOperator op> { diff --git a/llvm/test/CodeGen/AArch64/sve-fcvt.ll b/llvm/test/CodeGen/AArch64/sve-fcvt.ll index f8fb037436cf2..0fe38bf9ae718 100644 --- a/llvm/test/CodeGen/AArch64/sve-fcvt.ll +++ b/llvm/test/CodeGen/AArch64/sve-fcvt.ll @@ -898,3 +898,377 @@ define @ucvtf_d_nxv2i64( %a) { %res = uitofp %a to ret %res } + +define @fcvt_htos_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_htos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.s, p0/m, z1.h +; CHECK-NEXT: ret + %res = fpext %b to + ret %res +} + +define @fcvt_htod_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_htod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.d, p0/m, z1.h +; CHECK-NEXT: ret + %res = fpext %b to + ret %res +} + +define @fcvt_stod_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_stod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.d, p0/m, z1.s +; CHECK-NEXT: ret + %res = fpext %b to + ret %res +} + +define @fcvt_stoh_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_stoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.h, p0/m, z1.s +; CHECK-NEXT: ret + %res = fptrunc %b to + ret %res +} + +define @fcvt_dtoh_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_dtoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.h, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptrunc %b to + ret %res +} + +define @fcvt_dtos_movprfx( %a, %b) { +; CHECK-LABEL: fcvt_dtos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvt z0.s, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptrunc %b to + ret %res +} + +define @scvtf_htoh_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_htoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_stos_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_stos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_stod_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_stod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.d, p0/m, z1.s +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_dtos_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_dtos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.s, p0/m, z1.d +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_stoh_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_stoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.h, p0/m, z1.s +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_dtoh_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_dtoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.h, p0/m, z1.d +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @scvtf_dtod_movprfx( %a, %b) { +; CHECK-LABEL: scvtf_dtod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: scvtf z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = sitofp %b to + ret %res +} + +define @ucvtf_stos_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_stos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_htoh_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_htoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_stod_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_stod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.d, p0/m, z1.s +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_stoh_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_stoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.h, p0/m, z1.s +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_dtos_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_dtos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.s, p0/m, z1.d +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_dtoh_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_dtoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.h, p0/m, z1.d +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @ucvtf_dtod_movprfx( %a, %b) { +; CHECK-LABEL: ucvtf_dtod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: ucvtf z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = uitofp %b to + ret %res +} + +define @fcvtzs_htoh_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_htoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_stos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_stos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_dtos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_dtos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_stod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_stod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_htos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_htos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_htod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_htod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzs_dtod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzs_dtod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptosi %b to + ret %res +} + +define @fcvtzu_htoh_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_htoh_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.h, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_stos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_stos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.s +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_dtos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_dtos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_stod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_stod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_htos_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_htos_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_htod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_htod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} + +define @fcvtzu_dtod_movprfx( %a, %b) { +; CHECK-LABEL: fcvtzu_dtod_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.d +; CHECK-NEXT: ret + %res = fptoui %b to + ret %res +} diff --git a/llvm/test/CodeGen/AArch64/sve-fpext-load.ll b/llvm/test/CodeGen/AArch64/sve-fpext-load.ll index 913230eebe8b2..f18252b6bfe76 100644 --- a/llvm/test/CodeGen/AArch64/sve-fpext-load.ll +++ b/llvm/test/CodeGen/AArch64/sve-fpext-load.ll @@ -23,7 +23,9 @@ define @ext4_f16_f64( *%ptr, i64 %index ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvt z0.d, p0/m, z1.h +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvt z1.d, p0/m, z2.h ; CHECK-NEXT: ret %load = load , * %ptr, align 4 @@ -43,10 +45,13 @@ define @ext8_f16_f64( *%ptr, i64 %index ; CHECK-NEXT: uunpklo z2.d, z1.s ; CHECK-NEXT: uunpkhi z1.d, z1.s ; CHECK-NEXT: uunpklo z3.d, z0.s +; CHECK-NEXT: fcvt z1.d, p0/m, z1.h ; CHECK-NEXT: uunpkhi z4.d, z0.s +; CHECK-NEXT: movprfx z0, z2 ; CHECK-NEXT: fcvt z0.d, p0/m, z2.h -; CHECK-NEXT: fcvt z1.d, p0/m, z1.h +; CHECK-NEXT: movprfx z2, z3 ; CHECK-NEXT: fcvt z2.d, p0/m, z3.h +; CHECK-NEXT: movprfx z3, z4 ; CHECK-NEXT: fcvt z3.d, p0/m, z4.h ; CHECK-NEXT: ret %load = load , * %ptr, align 4 @@ -76,7 +81,9 @@ define @ext4_f32_f64( *%ptr, i64 %inde ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvt z0.d, p0/m, z1.s +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvt z1.d, p0/m, z2.s ; CHECK-NEXT: ret %load = load , * %ptr, align 4 diff --git a/llvm/test/CodeGen/AArch64/sve-split-fcvt.ll b/llvm/test/CodeGen/AArch64/sve-split-fcvt.ll index 0fae0e7dbe7e8..99e9e61fca295 100644 --- a/llvm/test/CodeGen/AArch64/sve-split-fcvt.ll +++ b/llvm/test/CodeGen/AArch64/sve-split-fcvt.ll @@ -6,10 +6,12 @@ define @fcvts_nxv8f16( %a) { ; CHECK-LABEL: fcvts_nxv8f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: uunpklo z1.s, z0.h +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: uunpkhi z2.s, z0.h +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvt z0.s, p0/m, z1.h +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvt z1.s, p0/m, z2.h ; CHECK-NEXT: ret %res = fpext %a to @@ -19,10 +21,12 @@ define @fcvts_nxv8f16( %a) { define @fcvtd_nxv4f16( %a) { ; CHECK-LABEL: fcvtd_nxv4f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvt z0.d, p0/m, z1.h +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvt z1.d, p0/m, z2.h ; CHECK-NEXT: ret %res = fpext %a to @@ -33,15 +37,18 @@ define @fcvtd_nxv8f16( %a) { ; CHECK-LABEL: fcvtd_nxv8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: uunpklo z1.s, z0.h -; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uunpkhi z0.s, z0.h ; CHECK-NEXT: uunpklo z2.d, z1.s ; CHECK-NEXT: uunpkhi z1.d, z1.s ; CHECK-NEXT: uunpklo z3.d, z0.s +; CHECK-NEXT: fcvt z1.d, p0/m, z1.h ; CHECK-NEXT: uunpkhi z4.d, z0.s +; CHECK-NEXT: movprfx z0, z2 ; CHECK-NEXT: fcvt z0.d, p0/m, z2.h -; CHECK-NEXT: fcvt z1.d, p0/m, z1.h +; CHECK-NEXT: movprfx z2, z3 ; CHECK-NEXT: fcvt z2.d, p0/m, z3.h +; CHECK-NEXT: movprfx z3, z4 ; CHECK-NEXT: fcvt z3.d, p0/m, z4.h ; CHECK-NEXT: ret %res = fpext %a to @@ -51,10 +58,12 @@ define @fcvtd_nxv8f16( %a) { define @fcvtd_nxv4f32( %a) { ; CHECK-LABEL: fcvtd_nxv4f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvt z0.d, p0/m, z1.s +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvt z1.d, p0/m, z2.s ; CHECK-NEXT: ret %res = fpext %a to @@ -64,14 +73,18 @@ define @fcvtd_nxv4f32( %a) { define @fcvtd_nxv8f32( %a) { ; CHECK-LABEL: fcvtd_nxv8f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z2.d, z0.s ; CHECK-NEXT: uunpkhi z3.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z4.d, z1.s ; CHECK-NEXT: uunpkhi z5.d, z1.s +; CHECK-NEXT: movprfx z0, z2 ; CHECK-NEXT: fcvt z0.d, p0/m, z2.s +; CHECK-NEXT: movprfx z1, z3 ; CHECK-NEXT: fcvt z1.d, p0/m, z3.s +; CHECK-NEXT: movprfx z2, z4 ; CHECK-NEXT: fcvt z2.d, p0/m, z4.s +; CHECK-NEXT: movprfx z3, z5 ; CHECK-NEXT: fcvt z3.d, p0/m, z5.s ; CHECK-NEXT: ret %res = fpext %a to @@ -182,10 +195,12 @@ define @fcvtzs_h_nxv8f64( %a) { define @fcvtzs_d_nxv4f32( %a) { ; CHECK-LABEL: fcvtzs_d_nxv4f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s ; CHECK-NEXT: ret %res = fptosi %a to @@ -195,14 +210,18 @@ define @fcvtzs_d_nxv4f32( %a) { define @fcvtzs_s_nxv16f16( %a) { ; CHECK-LABEL: fcvtzs_s_nxv16f16: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: uunpklo z2.s, z0.h ; CHECK-NEXT: uunpkhi z3.s, z0.h +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: uunpklo z4.s, z1.h ; CHECK-NEXT: uunpkhi z5.s, z1.h +; CHECK-NEXT: movprfx z0, z2 ; CHECK-NEXT: fcvtzs z0.s, p0/m, z2.h +; CHECK-NEXT: movprfx z1, z3 ; CHECK-NEXT: fcvtzs z1.s, p0/m, z3.h +; CHECK-NEXT: movprfx z2, z4 ; CHECK-NEXT: fcvtzs z2.s, p0/m, z4.h +; CHECK-NEXT: movprfx z3, z5 ; CHECK-NEXT: fcvtzs z3.s, p0/m, z5.h ; CHECK-NEXT: ret %res = fptosi %a to @@ -228,10 +247,12 @@ define @fcvtzu_s_nxv4f64( %a) { define @fcvtzu_d_nxv4f32( %a) { ; CHECK-LABEL: fcvtzu_d_nxv4f32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.s ; CHECK-NEXT: ret %res = fptoui %a to @@ -274,15 +295,18 @@ define @scvtf_s_nxv16i8( %a) { ; CHECK-LABEL: scvtf_s_nxv16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sunpklo z1.h, z0.b -; CHECK-NEXT: sunpkhi z0.h, z0.b ; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: sunpkhi z0.h, z0.b ; CHECK-NEXT: sunpklo z2.s, z1.h ; CHECK-NEXT: sunpkhi z1.s, z1.h ; CHECK-NEXT: sunpklo z3.s, z0.h +; CHECK-NEXT: scvtf z1.s, p0/m, z1.s ; CHECK-NEXT: sunpkhi z4.s, z0.h +; CHECK-NEXT: movprfx z0, z2 ; CHECK-NEXT: scvtf z0.s, p0/m, z2.s -; CHECK-NEXT: scvtf z1.s, p0/m, z1.s +; CHECK-NEXT: movprfx z2, z3 ; CHECK-NEXT: scvtf z2.s, p0/m, z3.s +; CHECK-NEXT: movprfx z3, z4 ; CHECK-NEXT: scvtf z3.s, p0/m, z4.s ; CHECK-NEXT: ret %res = sitofp %a to @@ -292,10 +316,12 @@ define @scvtf_s_nxv16i8( %a) { define @scvtf_d_nxv4i32( %a) { ; CHECK-LABEL: scvtf_d_nxv4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: sunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: sunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: scvtf z0.d, p0/m, z1.d +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: scvtf z1.d, p0/m, z2.d ; CHECK-NEXT: ret %res = sitofp %a to @@ -352,10 +378,12 @@ define @ucvtf_h_nxv8i64( %a) { define @ucvtf_d_nxv4i32( %a) { ; CHECK-LABEL: ucvtf_d_nxv4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpklo z1.d, z0.s +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: uunpkhi z2.d, z0.s +; CHECK-NEXT: movprfx z0, z1 ; CHECK-NEXT: ucvtf z0.d, p0/m, z1.d +; CHECK-NEXT: movprfx z1, z2 ; CHECK-NEXT: ucvtf z1.d, p0/m, z2.d ; CHECK-NEXT: ret %res = uitofp %a to From 1e0f843abd4f0c3d2f1a9f7350d658f7d95332d0 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 7 Feb 2022 14:06:52 -0800 Subject: [PATCH 045/316] libclang-abi-tests: Fix failure when checking libclang.so We were assuming that the symbol versions for libclang.so would be different for each major release, but this is not longer true. The libclang.so symbol versions only change when the ABI changes. --- .github/workflows/libclang-abi-tests.yml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/.github/workflows/libclang-abi-tests.yml b/.github/workflows/libclang-abi-tests.yml index c533c2c2fa8e7..3825961472909 100644 --- a/.github/workflows/libclang-abi-tests.yml +++ b/.github/workflows/libclang-abi-tests.yml @@ -117,10 +117,12 @@ jobs: - name: Dump ABI run: | parallel abi-dumper -lver ${{ matrix.ref }} -skip-cxx -public-headers ./install/include/${{ needs.abi-dump-setup.outputs.ABI_HEADERS }} -o {}-${{ matrix.ref }}.abi ./build/lib/{} ::: ${{ needs.abi-dump-setup.outputs.ABI_LIBS }} - for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do - # Remove symbol versioning from dumps, so we can compare across major versions. - sed -i 's/LLVM_${{ matrix.llvm_version_major }}/LLVM_NOVERSION/' $lib-${{ matrix.ref }}.abi - done + # Remove symbol versioning from dumps, so we can compare across major + # versions. We don't need to do this for libclang.so since its ABI + # is stable across major releases and the symbol versions don't change. + if [ -e libclang-cpp.so-${{ matrix.ref }}.abi ]; then + sed -i 's/LLVM_[0-9]\+/LLVM_NOVERSION/' libclang-cpp.so-${{ matrix.ref }}.abi + fi - name: Upload ABI file uses: actions/upload-artifact@v2 with: From 524758d1a75e21a9133b597ea649237d75a46abb Mon Sep 17 00:00:00 2001 From: Mariusz Ceier Date: Mon, 7 Feb 2022 23:26:22 -0800 Subject: [PATCH 046/316] [lldb][CMake] Fix linking of gdb-remote when LLVM_ENABLE_ZLIB is ON When LLVM_ENABLE_ZLIB is ON gdb-remote should link against ZLIB::ZLIB. This fixes ``` /mnt/b/yoe/master/build/tmp/hosttools/ld: lib/liblldbPluginProcessGDBRemote.a(GDBRemoteCommunication.cpp.o): in function `lldb_private::process_gdb_remote::GDBRemoteCommunication::DecompressPacket() [clone .localalias]': GDBRemoteCommunication.cpp:(.text._ZN12lldb_private18process_gdb_remote22GDBRemoteCommunication16DecompressPacketEv+0x59a): undefined reference to `inflateInit2_' /mnt/b/yoe/master/build/tmp/hosttools/ld: GDBRemoteCommunication.cpp:(.text._ZN12lldb_private18process_gdb_remote22GDBRemoteCommunication16DecompressPacketEv+0x5af): undefined reference to `inflate' ``` Reviewed By: JDevlieghere, MaskRay Differential Revision: https://reviews.llvm.org/D119186 (cherry picked from commit 385f5c4d33799df25a85ceb54b6232499cb8a78d) --- lldb/source/Plugins/Process/gdb-remote/CMakeLists.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lldb/source/Plugins/Process/gdb-remote/CMakeLists.txt b/lldb/source/Plugins/Process/gdb-remote/CMakeLists.txt index 3a1a0e435ad25..e0c798187bd5b 100644 --- a/lldb/source/Plugins/Process/gdb-remote/CMakeLists.txt +++ b/lldb/source/Plugins/Process/gdb-remote/CMakeLists.txt @@ -15,6 +15,10 @@ if(HAVE_LIBCOMPRESSION) set(LIBCOMPRESSION compression) endif() +if(LLVM_ENABLE_ZLIB) + list(APPEND LLDB_SYSTEM_LIBS ZLIB::ZLIB) +endif() + add_lldb_library(lldbPluginProcessGDBRemote PLUGIN GDBRemoteClientBase.cpp GDBRemoteCommunication.cpp @@ -39,6 +43,7 @@ add_lldb_library(lldbPluginProcessGDBRemote PLUGIN lldbSymbol lldbTarget lldbUtility + ${LLDB_SYSTEM_LIBS} ${LLDB_PLUGINS} ${LIBCOMPRESSION} LINK_COMPONENTS From 56dcb10a9942c206d53a59abd66c2207a01b39fa Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Tue, 8 Feb 2022 17:49:05 +0000 Subject: [PATCH 047/316] Add Cortex-X1C to Clang LLVM 14 release notes Reviewed By: amilendra Differential Revision: https://reviews.llvm.org/D119008 --- clang/docs/ReleaseNotes.rst | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a58e3fcd4f42c..caa2349f9d860 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -101,6 +101,10 @@ Modified Compiler Flags - RISC-V SiFive S51 (``sifive-s51``). - RISC-V SiFive S54 (``sifive-s54``). - RISC-V SiFive S76 (``sifive-s76``). + - Arm Cortex-X1C (``cortex-x1c``) + - Arm Cortex-X2 (``cortex-x2``) + - Arm Cortex-A510 (``cortex-a510``) + - Arm Cortex-A710 (``cortex-a710``) - Support has been added for the following architectures (``-march`` identifiers in parentheses): @@ -283,11 +287,6 @@ DWARF Support in Clang Arm and AArch64 Support in Clang -------------------------------- -- Support has been added for the following processors (command-line identifiers in parentheses): - - Arm Cortex-A510 (``cortex-a510``) - - Arm Cortex-X2 (``cortex-x2``) - - Arm Cortex-A710 (``cortex-A710``) - - The -mtune flag is no longer ignored for AArch64. It is now possible to tune code generation for a particular CPU with -mtune without setting any architectural features. For example, compiling with From 54a83652eebad6508fb861847fbb84606f37b502 Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 2 Feb 2022 21:00:20 +0000 Subject: [PATCH 048/316] Follow up to 6e03a68b776dc, squelch another leak This patch is a sticking-paster until D118774 solves the situation with unique_ptrs. I'm certainly wishing I'd focused on that first X_X. (cherry picked from commit 4654fa89eacca375ff860203697982b873bbd7c8) --- llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 3b4d717c9ab4a..6af5f07d801ac 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -2929,8 +2929,15 @@ bool InstrRefBasedLDV::depthFirstVLocAndEmit( VTracker = nullptr; // No scopes? No variable locations. - if (!LS.getCurrentFunctionScope()) + if (!LS.getCurrentFunctionScope()) { + // FIXME: this is a sticking plaster to prevent a memory leak, these + // pointers will be automagically freed by being unique pointers, shortly. + for (unsigned int I = 0; I < MaxNumBlocks; ++I) { + delete[] MInLocs[I]; + delete[] MOutLocs[I]; + } return false; + } // Build map from block number to the last scope that uses the block. SmallVector EjectionMap; From bf60baea583e624ca02766e605018e3be9680a42 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Fri, 4 Feb 2022 07:45:57 -0500 Subject: [PATCH 049/316] Revert "[x86] try harder to scalarize a vector load with extracted integer op uses" This reverts commit b4b97ec813a02585000f30ac7d532dda74e8bfda. As discussed in post-commit feedback at: https://reviews.llvm.org/D118376 ...there's a stage 2 failure on a Mac running a clang-refactor tool test. (cherry picked from commit 7b03725097872fbd3369a7213c1d98b372aa2d78) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 32 - ...011-12-26-extractelement-duplicate-load.ll | 12 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 18 +- llvm/test/CodeGen/X86/bitcast-vector-bool.ll | 6 +- llvm/test/CodeGen/X86/extractelement-load.ll | 12 +- llvm/test/CodeGen/X86/oddsubvector.ll | 72 +-- llvm/test/CodeGen/X86/pr45378.ll | 17 +- llvm/test/CodeGen/X86/scalar_widen_div.ll | 31 +- llvm/test/CodeGen/X86/shrink_vmul.ll | 214 ++++--- llvm/test/CodeGen/X86/vec_cast.ll | 2 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 591 +++++++++++------- 11 files changed, 597 insertions(+), 410 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 90753b5b4d33c..9afb885f582aa 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43108,38 +43108,6 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG, } } - // If this extract is from a loaded vector value and will be used as an - // integer, that requires a potentially expensive XMM -> GPR transfer. - // Additionally, if we can convert to a scalar integer load, that will likely - // be folded into a subsequent integer op. - // Note: Unlike the related fold for this in DAGCombiner, this is not limited - // to a single-use of the loaded vector. For the reasons above, we - // expect this to be profitable even if it creates an extra load. - bool LikelyUsedAsVector = any_of(N->uses(), [](SDNode *Use) { - return Use->getOpcode() == ISD::STORE || - Use->getOpcode() == ISD::INSERT_VECTOR_ELT || - Use->getOpcode() == ISD::SCALAR_TO_VECTOR; - }); - auto *LoadVec = dyn_cast(InputVector); - if (LoadVec && CIdx && ISD::isNormalLoad(LoadVec) && VT.isInteger() && - SrcVT.getVectorElementType() == VT && DCI.isAfterLegalizeDAG() && - !LikelyUsedAsVector) { - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - SDValue NewPtr = - TLI.getVectorElementPointer(DAG, LoadVec->getBasePtr(), SrcVT, EltIdx); - unsigned PtrOff = VT.getSizeInBits() * CIdx->getZExtValue() / 8; - MachinePointerInfo MPI = LoadVec->getPointerInfo().getWithOffset(PtrOff); - Align Alignment = commonAlignment(LoadVec->getAlign(), PtrOff); - SDValue Load = - DAG.getLoad(VT, dl, LoadVec->getChain(), NewPtr, MPI, Alignment, - LoadVec->getMemOperand()->getFlags(), LoadVec->getAAInfo()); - SDValue Chain = Load.getValue(1); - SDValue From[] = {SDValue(N, 0), SDValue(LoadVec, 1)}; - SDValue To[] = {Load, Chain}; - DAG.ReplaceAllUsesOfValuesWith(From, To, 2); - return SDValue(N, 0); - } - return SDValue(); } diff --git a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll index 5fb01b8c1b992..ad52d58bde1c6 100644 --- a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll +++ b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll @@ -10,13 +10,13 @@ define <4 x i32> @test(<4 x i32>* %p) { ; CHECK-LABEL: test: ; CHECK: # %bb.0: -; CHECK-NEXT: cmpl $3, 8(%rdi) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: movaps (%rdi), %xmm0 +; CHECK-NEXT: extractps $2, %xmm0, %eax +; CHECK-NEXT: cmpl $3, %eax +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: retq %v = load <4 x i32>, <4 x i32>* %p %e = extractelement <4 x i32> %v, i32 2 diff --git a/llvm/test/CodeGen/X86/avx512-cvt.ll b/llvm/test/CodeGen/X86/avx512-cvt.ll index f632db7160e60..5d7940b2fa7ce 100644 --- a/llvm/test/CodeGen/X86/avx512-cvt.ll +++ b/llvm/test/CodeGen/X86/avx512-cvt.ll @@ -148,12 +148,18 @@ define <2 x float> @sltof2f32(<2 x i64> %a) { define <4 x float> @slto4f32_mem(<4 x i64>* %a) { ; NODQ-LABEL: slto4f32_mem: ; NODQ: # %bb.0: -; NODQ-NEXT: vcvtsi2ssq 8(%rdi), %xmm0, %xmm0 -; NODQ-NEXT: vcvtsi2ssq (%rdi), %xmm1, %xmm1 -; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; NODQ-NEXT: vcvtsi2ssq 16(%rdi), %xmm2, %xmm1 -; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; NODQ-NEXT: vcvtsi2ssq 24(%rdi), %xmm2, %xmm1 +; NODQ-NEXT: vmovdqu (%rdi), %xmm0 +; NODQ-NEXT: vmovdqu 16(%rdi), %xmm1 +; NODQ-NEXT: vpextrq $1, %xmm0, %rax +; NODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 +; NODQ-NEXT: vmovq %xmm0, %rax +; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 +; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; NODQ-NEXT: vmovq %xmm1, %rax +; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 +; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; NODQ-NEXT: vpextrq $1, %xmm1, %rax +; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; NODQ-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll index a47dbe570fd52..bf3ffecb414ff 100644 --- a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll +++ b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll @@ -542,8 +542,10 @@ define i32 @bitcast_v64i8_to_v2i32(<64 x i8> %a0) nounwind { ; AVX512: # %bb.0: ; AVX512-NEXT: vpmovb2m %zmm0, %k0 ; AVX512-NEXT: kmovq %k0, -{{[0-9]+}}(%rsp) -; AVX512-NEXT: movl -{{[0-9]+}}(%rsp), %eax -; AVX512-NEXT: addl -{{[0-9]+}}(%rsp), %eax +; AVX512-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm0 +; AVX512-NEXT: vmovd %xmm0, %ecx +; AVX512-NEXT: vpextrd $1, %xmm0, %eax +; AVX512-NEXT: addl %ecx, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = icmp slt <64 x i8> %a0, zeroinitializer diff --git a/llvm/test/CodeGen/X86/extractelement-load.ll b/llvm/test/CodeGen/X86/extractelement-load.ll index c0c32eb3cfce8..2a7ed3a8b4e71 100644 --- a/llvm/test/CodeGen/X86/extractelement-load.ll +++ b/llvm/test/CodeGen/X86/extractelement-load.ll @@ -301,35 +301,33 @@ define void @subextract_broadcast_load_constant(<2 x i16>* nocapture %0, i16* no ret void } -; A scalar load is favored over a XMM->GPR register transfer in this example. - define i32 @multi_use_load_scalarization(<4 x i32>* %p) { ; X32-SSE2-LABEL: multi_use_load_scalarization: ; X32-SSE2: # %bb.0: ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-SSE2-NEXT: movl (%ecx), %eax ; X32-SSE2-NEXT: movdqu (%ecx), %xmm0 ; X32-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 +; X32-SSE2-NEXT: movd %xmm0, %eax ; X32-SSE2-NEXT: psubd %xmm1, %xmm0 ; X32-SSE2-NEXT: movdqa %xmm0, (%ecx) ; X32-SSE2-NEXT: retl ; ; X64-SSSE3-LABEL: multi_use_load_scalarization: ; X64-SSSE3: # %bb.0: -; X64-SSSE3-NEXT: movl (%rdi), %eax ; X64-SSSE3-NEXT: movdqu (%rdi), %xmm0 ; X64-SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 +; X64-SSSE3-NEXT: movd %xmm0, %eax ; X64-SSSE3-NEXT: psubd %xmm1, %xmm0 ; X64-SSSE3-NEXT: movdqa %xmm0, (%rdi) ; X64-SSSE3-NEXT: retq ; ; X64-AVX-LABEL: multi_use_load_scalarization: ; X64-AVX: # %bb.0: -; X64-AVX-NEXT: movl (%rdi), %eax ; X64-AVX-NEXT: vmovdqu (%rdi), %xmm0 ; X64-AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; X64-AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; X64-AVX-NEXT: vmovdqa %xmm0, (%rdi) +; X64-AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm1 +; X64-AVX-NEXT: vmovdqa %xmm1, (%rdi) +; X64-AVX-NEXT: vmovd %xmm0, %eax ; X64-AVX-NEXT: retq %v = load <4 x i32>, <4 x i32>* %p, align 1 %v1 = add <4 x i32> %v, diff --git a/llvm/test/CodeGen/X86/oddsubvector.ll b/llvm/test/CodeGen/X86/oddsubvector.ll index fb4c23e7de1a4..a28a64f4fc60b 100644 --- a/llvm/test/CodeGen/X86/oddsubvector.ll +++ b/llvm/test/CodeGen/X86/oddsubvector.ll @@ -161,46 +161,46 @@ define <16 x i32> @PR42819(<8 x i32>* %a0) { define void @PR42833() { ; SSE2-LABEL: PR42833: ; SSE2: # %bb.0: -; SSE2-NEXT: movl b(%rip), %eax -; SSE2-NEXT: movdqa c+144(%rip), %xmm0 -; SSE2-NEXT: movdqa c+128(%rip), %xmm1 -; SSE2-NEXT: addl c+128(%rip), %eax +; SSE2-NEXT: movdqa c+144(%rip), %xmm1 +; SSE2-NEXT: movdqa c+128(%rip), %xmm0 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: addl b(%rip), %eax ; SSE2-NEXT: movd %eax, %xmm2 ; SSE2-NEXT: movd %eax, %xmm3 -; SSE2-NEXT: paddd %xmm1, %xmm3 +; SSE2-NEXT: paddd %xmm0, %xmm3 ; SSE2-NEXT: movdqa d+144(%rip), %xmm4 -; SSE2-NEXT: psubd %xmm0, %xmm4 -; SSE2-NEXT: paddd %xmm0, %xmm0 -; SSE2-NEXT: movdqa %xmm1, %xmm5 -; SSE2-NEXT: paddd %xmm1, %xmm5 +; SSE2-NEXT: psubd %xmm1, %xmm4 +; SSE2-NEXT: paddd %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm5 +; SSE2-NEXT: paddd %xmm0, %xmm5 ; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm3[0],xmm5[1,2,3] -; SSE2-NEXT: movdqa %xmm0, c+144(%rip) +; SSE2-NEXT: movdqa %xmm1, c+144(%rip) ; SSE2-NEXT: movaps %xmm5, c+128(%rip) -; SSE2-NEXT: movdqa c+160(%rip), %xmm0 +; SSE2-NEXT: movdqa c+160(%rip), %xmm1 ; SSE2-NEXT: movdqa c+176(%rip), %xmm3 ; SSE2-NEXT: movdqa d+160(%rip), %xmm5 ; SSE2-NEXT: movdqa d+176(%rip), %xmm6 ; SSE2-NEXT: movdqa d+128(%rip), %xmm7 -; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] -; SSE2-NEXT: psubd %xmm1, %xmm7 +; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] +; SSE2-NEXT: psubd %xmm0, %xmm7 ; SSE2-NEXT: psubd %xmm3, %xmm6 -; SSE2-NEXT: psubd %xmm0, %xmm5 +; SSE2-NEXT: psubd %xmm1, %xmm5 ; SSE2-NEXT: movdqa %xmm5, d+160(%rip) ; SSE2-NEXT: movdqa %xmm6, d+176(%rip) ; SSE2-NEXT: movdqa %xmm4, d+144(%rip) ; SSE2-NEXT: movdqa %xmm7, d+128(%rip) ; SSE2-NEXT: paddd %xmm3, %xmm3 -; SSE2-NEXT: paddd %xmm0, %xmm0 -; SSE2-NEXT: movdqa %xmm0, c+160(%rip) +; SSE2-NEXT: paddd %xmm1, %xmm1 +; SSE2-NEXT: movdqa %xmm1, c+160(%rip) ; SSE2-NEXT: movdqa %xmm3, c+176(%rip) ; SSE2-NEXT: retq ; ; SSE42-LABEL: PR42833: ; SSE42: # %bb.0: -; SSE42-NEXT: movl b(%rip), %eax ; SSE42-NEXT: movdqa c+144(%rip), %xmm0 ; SSE42-NEXT: movdqa c+128(%rip), %xmm1 -; SSE42-NEXT: addl c+128(%rip), %eax +; SSE42-NEXT: movd %xmm1, %eax +; SSE42-NEXT: addl b(%rip), %eax ; SSE42-NEXT: movd %eax, %xmm2 ; SSE42-NEXT: paddd %xmm1, %xmm2 ; SSE42-NEXT: movdqa d+144(%rip), %xmm3 @@ -232,20 +232,20 @@ define void @PR42833() { ; ; AVX1-LABEL: PR42833: ; AVX1: # %bb.0: -; AVX1-NEXT: movl b(%rip), %eax -; AVX1-NEXT: addl c+128(%rip), %eax -; AVX1-NEXT: vmovd %eax, %xmm0 -; AVX1-NEXT: vmovdqa c+128(%rip), %xmm1 -; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0 -; AVX1-NEXT: vpaddd %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa c+128(%rip), %xmm0 +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: addl b(%rip), %eax +; AVX1-NEXT: vmovd %eax, %xmm1 +; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm2 ; AVX1-NEXT: vmovdqa c+144(%rip), %xmm3 ; AVX1-NEXT: vpaddd %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 -; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7] +; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2,3,4,5,6,7] ; AVX1-NEXT: vmovdqa d+144(%rip), %xmm2 ; AVX1-NEXT: vpsubd c+144(%rip), %xmm2, %xmm2 -; AVX1-NEXT: vmovups %ymm0, c+128(%rip) -; AVX1-NEXT: vpinsrd $0, %eax, %xmm1, %xmm0 +; AVX1-NEXT: vmovups %ymm1, c+128(%rip) +; AVX1-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0 ; AVX1-NEXT: vmovdqa d+128(%rip), %xmm1 ; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vmovdqa d+176(%rip), %xmm1 @@ -314,20 +314,20 @@ define void @PR42833() { ; ; XOP-LABEL: PR42833: ; XOP: # %bb.0: -; XOP-NEXT: movl b(%rip), %eax -; XOP-NEXT: addl c+128(%rip), %eax -; XOP-NEXT: vmovd %eax, %xmm0 -; XOP-NEXT: vmovdqa c+128(%rip), %xmm1 -; XOP-NEXT: vpaddd %xmm0, %xmm1, %xmm0 -; XOP-NEXT: vpaddd %xmm1, %xmm1, %xmm2 +; XOP-NEXT: vmovdqa c+128(%rip), %xmm0 +; XOP-NEXT: vmovd %xmm0, %eax +; XOP-NEXT: addl b(%rip), %eax +; XOP-NEXT: vmovd %eax, %xmm1 +; XOP-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; XOP-NEXT: vpaddd %xmm0, %xmm0, %xmm2 ; XOP-NEXT: vmovdqa c+144(%rip), %xmm3 ; XOP-NEXT: vpaddd %xmm3, %xmm3, %xmm3 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 -; XOP-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7] +; XOP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2,3,4,5,6,7] ; XOP-NEXT: vmovdqa d+144(%rip), %xmm2 ; XOP-NEXT: vpsubd c+144(%rip), %xmm2, %xmm2 -; XOP-NEXT: vmovups %ymm0, c+128(%rip) -; XOP-NEXT: vpinsrd $0, %eax, %xmm1, %xmm0 +; XOP-NEXT: vmovups %ymm1, c+128(%rip) +; XOP-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0 ; XOP-NEXT: vmovdqa d+128(%rip), %xmm1 ; XOP-NEXT: vpsubd %xmm0, %xmm1, %xmm0 ; XOP-NEXT: vmovdqa d+176(%rip), %xmm1 diff --git a/llvm/test/CodeGen/X86/pr45378.ll b/llvm/test/CodeGen/X86/pr45378.ll index 0f2b212242793..d5da5c73a891d 100644 --- a/llvm/test/CodeGen/X86/pr45378.ll +++ b/llvm/test/CodeGen/X86/pr45378.ll @@ -76,23 +76,28 @@ define i1 @parseHeaders2_scalar_and(i64 * %ptr) nounwind { ; SSE2-LABEL: parseHeaders2_scalar_and: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqu (%rdi), %xmm0 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, %rax -; SSE2-NEXT: testq %rax, (%rdi) +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; SSE2-NEXT: movq %xmm0, %rcx +; SSE2-NEXT: testq %rcx, %rax ; SSE2-NEXT: sete %al ; SSE2-NEXT: retq ; ; SSE41-LABEL: parseHeaders2_scalar_and: ; SSE41: # %bb.0: -; SSE41-NEXT: movq (%rdi), %rax -; SSE41-NEXT: testq %rax, 8(%rdi) +; SSE41-NEXT: movdqu (%rdi), %xmm0 +; SSE41-NEXT: movq %xmm0, %rax +; SSE41-NEXT: pextrq $1, %xmm0, %rcx +; SSE41-NEXT: testq %rcx, %rax ; SSE41-NEXT: sete %al ; SSE41-NEXT: retq ; ; AVX-LABEL: parseHeaders2_scalar_and: ; AVX: # %bb.0: -; AVX-NEXT: movq (%rdi), %rax -; AVX-NEXT: testq %rax, 8(%rdi) +; AVX-NEXT: vmovdqu (%rdi), %xmm0 +; AVX-NEXT: vmovq %xmm0, %rax +; AVX-NEXT: vpextrq $1, %xmm0, %rcx +; AVX-NEXT: testq %rcx, %rax ; AVX-NEXT: sete %al ; AVX-NEXT: retq %vptr = bitcast i64 * %ptr to <2 x i64> * diff --git a/llvm/test/CodeGen/X86/scalar_widen_div.ll b/llvm/test/CodeGen/X86/scalar_widen_div.ll index 816892d62a0b3..d21b441580688 100644 --- a/llvm/test/CodeGen/X86/scalar_widen_div.ll +++ b/llvm/test/CodeGen/X86/scalar_widen_div.ll @@ -403,29 +403,32 @@ define void @test_int_div(<3 x i32>* %dest, <3 x i32>* %old, i32 %n) { ; CHECK-NEXT: testl %edx, %edx ; CHECK-NEXT: jle .LBB12_3 ; CHECK-NEXT: # %bb.1: # %bb.nph -; CHECK-NEXT: movl %edx, %r11d +; CHECK-NEXT: movl %edx, %r9d ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB12_2: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: movl 8(%rdi,%rcx), %r8d -; CHECK-NEXT: movl (%rdi,%rcx), %r9d -; CHECK-NEXT: movl 4(%rdi,%rcx), %eax +; CHECK-NEXT: movdqa (%rdi,%rcx), %xmm0 +; CHECK-NEXT: movdqa (%rsi,%rcx), %xmm1 +; CHECK-NEXT: pextrd $1, %xmm0, %eax +; CHECK-NEXT: pextrd $1, %xmm1, %r8d ; CHECK-NEXT: cltd -; CHECK-NEXT: idivl 4(%rsi,%rcx) -; CHECK-NEXT: movl %eax, %r10d -; CHECK-NEXT: movl %r9d, %eax +; CHECK-NEXT: idivl %r8d +; CHECK-NEXT: movl %eax, %r8d +; CHECK-NEXT: movd %xmm0, %eax +; CHECK-NEXT: movd %xmm1, %r10d ; CHECK-NEXT: cltd -; CHECK-NEXT: idivl (%rsi,%rcx) -; CHECK-NEXT: movd %eax, %xmm0 -; CHECK-NEXT: pinsrd $1, %r10d, %xmm0 -; CHECK-NEXT: movl %r8d, %eax +; CHECK-NEXT: idivl %r10d +; CHECK-NEXT: movd %eax, %xmm2 +; CHECK-NEXT: pinsrd $1, %r8d, %xmm2 +; CHECK-NEXT: pextrd $2, %xmm0, %eax +; CHECK-NEXT: pextrd $2, %xmm1, %r8d ; CHECK-NEXT: cltd -; CHECK-NEXT: idivl 8(%rsi,%rcx) +; CHECK-NEXT: idivl %r8d ; CHECK-NEXT: movl %eax, 8(%rdi,%rcx) -; CHECK-NEXT: movq %xmm0, (%rdi,%rcx) +; CHECK-NEXT: movq %xmm2, (%rdi,%rcx) ; CHECK-NEXT: addq $16, %rcx -; CHECK-NEXT: decl %r11d +; CHECK-NEXT: decl %r9d ; CHECK-NEXT: jne .LBB12_2 ; CHECK-NEXT: .LBB12_3: # %for.end ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/shrink_vmul.ll b/llvm/test/CodeGen/X86/shrink_vmul.ll index 5558b7eefffb8..82a633b6d8cad 100644 --- a/llvm/test/CodeGen/X86/shrink_vmul.ll +++ b/llvm/test/CodeGen/X86/shrink_vmul.ll @@ -2072,10 +2072,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-SSE-NEXT: divl %ecx ; X86-SSE-NEXT: movd %edx, %xmm4 ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] +; X86-SSE-NEXT: movd %xmm1, %ecx ; X86-SSE-NEXT: movl %esi, %eax ; X86-SSE-NEXT: xorl %edx, %edx -; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-SSE-NEXT: divl 16(%esi) +; X86-SSE-NEXT: divl %ecx ; X86-SSE-NEXT: movd %edx, %xmm3 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1] ; X86-SSE-NEXT: movd %xmm2, %eax @@ -2086,9 +2086,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-SSE-NEXT: movd %edx, %xmm1 ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] +; X86-SSE-NEXT: movd %xmm0, %ecx ; X86-SSE-NEXT: movl %edi, %eax ; X86-SSE-NEXT: xorl %edx, %edx -; X86-SSE-NEXT: divl (%esi) +; X86-SSE-NEXT: divl %ecx ; X86-SSE-NEXT: movd %edx, %xmm1 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1] ; X86-SSE-NEXT: movd %xmm2, %ecx @@ -2114,7 +2115,8 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; X86-SSE-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-SSE-NEXT: xorl %edx, %edx -; X86-SSE-NEXT: divl 32(%esi) +; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-SSE-NEXT: divl 32(%ecx) ; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; X86-SSE-NEXT: pmuludq %xmm0, %xmm1 @@ -2149,43 +2151,53 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero -; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero -; X86-AVX1-NEXT: vmovd %xmm2, %eax +; X86-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero +; X86-AVX1-NEXT: vmovd %xmm1, %eax ; X86-AVX1-NEXT: xorl %edx, %edx ; X86-AVX1-NEXT: divl 32(%ecx) ; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-AVX1-NEXT: vpextrd $3, %xmm1, %eax +; X86-AVX1-NEXT: vpextrd $3, %xmm2, %eax +; X86-AVX1-NEXT: vmovdqa (%ecx), %xmm1 +; X86-AVX1-NEXT: vmovdqa 16(%ecx), %xmm3 +; X86-AVX1-NEXT: vpextrd $3, %xmm3, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 28(%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-AVX1-NEXT: vpextrd $2, %xmm1, %eax +; X86-AVX1-NEXT: vpextrd $2, %xmm2, %eax +; X86-AVX1-NEXT: vpextrd $2, %xmm3, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 24(%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-AVX1-NEXT: vpextrd $1, %xmm1, %eax +; X86-AVX1-NEXT: vpextrd $1, %xmm2, %eax +; X86-AVX1-NEXT: vpextrd $1, %xmm3, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 20(%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: movl %edx, (%esp) # 4-byte Spill -; X86-AVX1-NEXT: vmovd %xmm1, %eax +; X86-AVX1-NEXT: vmovd %xmm2, %eax +; X86-AVX1-NEXT: vmovd %xmm3, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 16(%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: movl %edx, %ebp ; X86-AVX1-NEXT: vpextrd $3, %xmm0, %eax +; X86-AVX1-NEXT: vpextrd $3, %xmm1, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 12(%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: movl %edx, %ebx ; X86-AVX1-NEXT: vpextrd $2, %xmm0, %eax +; X86-AVX1-NEXT: vpextrd $2, %xmm1, %esi ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 8(%ecx) +; X86-AVX1-NEXT: divl %esi ; X86-AVX1-NEXT: movl %edx, %esi ; X86-AVX1-NEXT: vpextrd $1, %xmm0, %eax +; X86-AVX1-NEXT: vpextrd $1, %xmm1, %edi ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl 4(%ecx) +; X86-AVX1-NEXT: divl %edi ; X86-AVX1-NEXT: movl %edx, %edi ; X86-AVX1-NEXT: vmovd %xmm0, %eax +; X86-AVX1-NEXT: vmovd %xmm1, %ecx ; X86-AVX1-NEXT: xorl %edx, %edx -; X86-AVX1-NEXT: divl (%ecx) +; X86-AVX1-NEXT: divl %ecx ; X86-AVX1-NEXT: vmovd %edx, %xmm0 ; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpinsrd $2, %esi, %xmm0, %xmm0 @@ -2211,47 +2223,58 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; ; X86-AVX2-LABEL: PR34947: ; X86-AVX2: # %bb.0: +; X86-AVX2-NEXT: pushl %edi ; X86-AVX2-NEXT: pushl %esi ; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; X86-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero -; X86-AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 -; X86-AVX2-NEXT: vpextrd $1, %xmm2, %eax +; X86-AVX2-NEXT: vmovdqa (%esi), %xmm2 +; X86-AVX2-NEXT: vmovdqa 16(%esi), %xmm3 +; X86-AVX2-NEXT: vpextrd $1, %xmm3, %ecx +; X86-AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4 +; X86-AVX2-NEXT: vpextrd $1, %xmm4, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 20(%esi) +; X86-AVX2-NEXT: divl %ecx ; X86-AVX2-NEXT: movl %edx, %ecx -; X86-AVX2-NEXT: vmovd %xmm2, %eax +; X86-AVX2-NEXT: vmovd %xmm3, %edi +; X86-AVX2-NEXT: vmovd %xmm4, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 16(%esi) -; X86-AVX2-NEXT: vmovd %edx, %xmm3 -; X86-AVX2-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3 -; X86-AVX2-NEXT: vpextrd $2, %xmm2, %eax +; X86-AVX2-NEXT: divl %edi +; X86-AVX2-NEXT: vmovd %edx, %xmm5 +; X86-AVX2-NEXT: vpinsrd $1, %ecx, %xmm5, %xmm5 +; X86-AVX2-NEXT: vpextrd $2, %xmm3, %ecx +; X86-AVX2-NEXT: vpextrd $2, %xmm4, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 24(%esi) -; X86-AVX2-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 -; X86-AVX2-NEXT: vpextrd $3, %xmm2, %eax +; X86-AVX2-NEXT: divl %ecx +; X86-AVX2-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 +; X86-AVX2-NEXT: vpextrd $3, %xmm3, %ecx +; X86-AVX2-NEXT: vpextrd $3, %xmm4, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 28(%esi) -; X86-AVX2-NEXT: vpinsrd $3, %edx, %xmm3, %xmm2 +; X86-AVX2-NEXT: divl %ecx +; X86-AVX2-NEXT: vpinsrd $3, %edx, %xmm5, %xmm3 +; X86-AVX2-NEXT: vpextrd $1, %xmm2, %ecx ; X86-AVX2-NEXT: vpextrd $1, %xmm1, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 4(%esi) +; X86-AVX2-NEXT: divl %ecx ; X86-AVX2-NEXT: movl %edx, %ecx +; X86-AVX2-NEXT: vmovd %xmm2, %edi ; X86-AVX2-NEXT: vmovd %xmm1, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl (%esi) -; X86-AVX2-NEXT: vmovd %edx, %xmm3 -; X86-AVX2-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3 +; X86-AVX2-NEXT: divl %edi +; X86-AVX2-NEXT: vmovd %edx, %xmm4 +; X86-AVX2-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4 +; X86-AVX2-NEXT: vpextrd $2, %xmm2, %ecx ; X86-AVX2-NEXT: vpextrd $2, %xmm1, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 8(%esi) -; X86-AVX2-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 +; X86-AVX2-NEXT: divl %ecx +; X86-AVX2-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 +; X86-AVX2-NEXT: vpextrd $3, %xmm2, %ecx ; X86-AVX2-NEXT: vpextrd $3, %xmm1, %eax ; X86-AVX2-NEXT: xorl %edx, %edx -; X86-AVX2-NEXT: divl 12(%esi) -; X86-AVX2-NEXT: vpinsrd $3, %edx, %xmm3, %xmm1 -; X86-AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 +; X86-AVX2-NEXT: divl %ecx +; X86-AVX2-NEXT: vpinsrd $3, %edx, %xmm4, %xmm1 +; X86-AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1 ; X86-AVX2-NEXT: vmovd %xmm0, %eax ; X86-AVX2-NEXT: xorl %edx, %edx ; X86-AVX2-NEXT: divl 32(%esi) @@ -2261,6 +2284,7 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX2-NEXT: movl %eax, (%eax) ; X86-AVX2-NEXT: vmovdqa %ymm0, (%eax) ; X86-AVX2-NEXT: popl %esi +; X86-AVX2-NEXT: popl %edi ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -2293,9 +2317,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-SSE-NEXT: divl %edi ; X64-SSE-NEXT: movd %edx, %xmm4 ; X64-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] +; X64-SSE-NEXT: movd %xmm1, %edi ; X64-SSE-NEXT: movl %r9d, %eax ; X64-SSE-NEXT: xorl %edx, %edx -; X64-SSE-NEXT: divl 16(%rsi) +; X64-SSE-NEXT: divl %edi ; X64-SSE-NEXT: movd %edx, %xmm3 ; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1] ; X64-SSE-NEXT: movd %xmm2, %eax @@ -2306,9 +2331,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-SSE-NEXT: movd %edx, %xmm1 ; X64-SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] +; X64-SSE-NEXT: movd %xmm0, %edi ; X64-SSE-NEXT: movl %r10d, %eax ; X64-SSE-NEXT: xorl %edx, %edx -; X64-SSE-NEXT: divl (%rsi) +; X64-SSE-NEXT: divl %edi ; X64-SSE-NEXT: movd %edx, %xmm1 ; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1] ; X64-SSE-NEXT: movd %xmm2, %edi @@ -2359,50 +2385,60 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX1-NEXT: pushq %rbp ; X64-AVX1-NEXT: pushq %rbx ; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero -; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero -; X64-AVX1-NEXT: vmovd %xmm2, %eax +; X64-AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero +; X64-AVX1-NEXT: vmovd %xmm1, %eax ; X64-AVX1-NEXT: xorl %edx, %edx ; X64-AVX1-NEXT: divl 32(%rsi) ; X64-AVX1-NEXT: movl %edx, %r8d -; X64-AVX1-NEXT: vpextrd $3, %xmm1, %eax +; X64-AVX1-NEXT: vpextrd $3, %xmm2, %eax +; X64-AVX1-NEXT: vmovdqa (%rsi), %xmm1 +; X64-AVX1-NEXT: vmovdqa 16(%rsi), %xmm3 +; X64-AVX1-NEXT: vpextrd $3, %xmm3, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 28(%rsi) +; X64-AVX1-NEXT: divl %ecx ; X64-AVX1-NEXT: movl %edx, %r9d -; X64-AVX1-NEXT: vpextrd $2, %xmm1, %eax +; X64-AVX1-NEXT: vpextrd $2, %xmm2, %eax +; X64-AVX1-NEXT: vpextrd $2, %xmm3, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 24(%rsi) +; X64-AVX1-NEXT: divl %ecx ; X64-AVX1-NEXT: movl %edx, %r10d -; X64-AVX1-NEXT: vpextrd $1, %xmm1, %eax +; X64-AVX1-NEXT: vpextrd $1, %xmm2, %eax +; X64-AVX1-NEXT: vpextrd $1, %xmm3, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 20(%rsi) +; X64-AVX1-NEXT: divl %ecx ; X64-AVX1-NEXT: movl %edx, %r11d -; X64-AVX1-NEXT: vmovd %xmm1, %eax +; X64-AVX1-NEXT: vmovd %xmm2, %eax +; X64-AVX1-NEXT: vmovd %xmm3, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 16(%rsi) -; X64-AVX1-NEXT: movl %edx, %ecx +; X64-AVX1-NEXT: divl %ecx +; X64-AVX1-NEXT: movl %edx, %esi ; X64-AVX1-NEXT: vpextrd $3, %xmm0, %eax +; X64-AVX1-NEXT: vpextrd $3, %xmm1, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 12(%rsi) +; X64-AVX1-NEXT: divl %ecx ; X64-AVX1-NEXT: movl %edx, %edi ; X64-AVX1-NEXT: vpextrd $2, %xmm0, %eax +; X64-AVX1-NEXT: vpextrd $2, %xmm1, %ecx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 8(%rsi) -; X64-AVX1-NEXT: movl %edx, %ebx +; X64-AVX1-NEXT: divl %ecx +; X64-AVX1-NEXT: movl %edx, %ecx ; X64-AVX1-NEXT: vpextrd $1, %xmm0, %eax +; X64-AVX1-NEXT: vpextrd $1, %xmm1, %ebx ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl 4(%rsi) -; X64-AVX1-NEXT: movl %edx, %ebp +; X64-AVX1-NEXT: divl %ebx +; X64-AVX1-NEXT: movl %edx, %ebx ; X64-AVX1-NEXT: vmovd %xmm0, %eax +; X64-AVX1-NEXT: vmovd %xmm1, %ebp ; X64-AVX1-NEXT: xorl %edx, %edx -; X64-AVX1-NEXT: divl (%rsi) +; X64-AVX1-NEXT: divl %ebp ; X64-AVX1-NEXT: vmovd %edx, %xmm0 -; X64-AVX1-NEXT: vpinsrd $1, %ebp, %xmm0, %xmm0 -; X64-AVX1-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0 +; X64-AVX1-NEXT: vpinsrd $1, %ebx, %xmm0, %xmm0 +; X64-AVX1-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [8199,8199,8199,8199] ; X64-AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0 -; X64-AVX1-NEXT: vmovd %ecx, %xmm2 +; X64-AVX1-NEXT: vmovd %esi, %xmm2 ; X64-AVX1-NEXT: vpinsrd $1, %r11d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm2, %xmm2 @@ -2419,42 +2455,52 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX2: # %bb.0: ; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero -; X64-AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 -; X64-AVX2-NEXT: vpextrd $1, %xmm2, %eax +; X64-AVX2-NEXT: vmovdqa (%rsi), %xmm2 +; X64-AVX2-NEXT: vmovdqa 16(%rsi), %xmm3 +; X64-AVX2-NEXT: vpextrd $1, %xmm3, %ecx +; X64-AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4 +; X64-AVX2-NEXT: vpextrd $1, %xmm4, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 20(%rsi) +; X64-AVX2-NEXT: divl %ecx ; X64-AVX2-NEXT: movl %edx, %ecx -; X64-AVX2-NEXT: vmovd %xmm2, %eax +; X64-AVX2-NEXT: vmovd %xmm3, %edi +; X64-AVX2-NEXT: vmovd %xmm4, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 16(%rsi) -; X64-AVX2-NEXT: vmovd %edx, %xmm3 -; X64-AVX2-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3 -; X64-AVX2-NEXT: vpextrd $2, %xmm2, %eax +; X64-AVX2-NEXT: divl %edi +; X64-AVX2-NEXT: vmovd %edx, %xmm5 +; X64-AVX2-NEXT: vpinsrd $1, %ecx, %xmm5, %xmm5 +; X64-AVX2-NEXT: vpextrd $2, %xmm3, %ecx +; X64-AVX2-NEXT: vpextrd $2, %xmm4, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 24(%rsi) -; X64-AVX2-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 -; X64-AVX2-NEXT: vpextrd $3, %xmm2, %eax +; X64-AVX2-NEXT: divl %ecx +; X64-AVX2-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 +; X64-AVX2-NEXT: vpextrd $3, %xmm3, %ecx +; X64-AVX2-NEXT: vpextrd $3, %xmm4, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 28(%rsi) -; X64-AVX2-NEXT: vpinsrd $3, %edx, %xmm3, %xmm2 +; X64-AVX2-NEXT: divl %ecx +; X64-AVX2-NEXT: vpinsrd $3, %edx, %xmm5, %xmm3 +; X64-AVX2-NEXT: vpextrd $1, %xmm2, %ecx ; X64-AVX2-NEXT: vpextrd $1, %xmm1, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 4(%rsi) +; X64-AVX2-NEXT: divl %ecx ; X64-AVX2-NEXT: movl %edx, %ecx +; X64-AVX2-NEXT: vmovd %xmm2, %edi ; X64-AVX2-NEXT: vmovd %xmm1, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl (%rsi) -; X64-AVX2-NEXT: vmovd %edx, %xmm3 -; X64-AVX2-NEXT: vpinsrd $1, %ecx, %xmm3, %xmm3 +; X64-AVX2-NEXT: divl %edi +; X64-AVX2-NEXT: vmovd %edx, %xmm4 +; X64-AVX2-NEXT: vpinsrd $1, %ecx, %xmm4, %xmm4 +; X64-AVX2-NEXT: vpextrd $2, %xmm2, %ecx ; X64-AVX2-NEXT: vpextrd $2, %xmm1, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 8(%rsi) -; X64-AVX2-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 +; X64-AVX2-NEXT: divl %ecx +; X64-AVX2-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 +; X64-AVX2-NEXT: vpextrd $3, %xmm2, %ecx ; X64-AVX2-NEXT: vpextrd $3, %xmm1, %eax ; X64-AVX2-NEXT: xorl %edx, %edx -; X64-AVX2-NEXT: divl 12(%rsi) -; X64-AVX2-NEXT: vpinsrd $3, %edx, %xmm3, %xmm1 -; X64-AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 +; X64-AVX2-NEXT: divl %ecx +; X64-AVX2-NEXT: vpinsrd $3, %edx, %xmm4, %xmm1 +; X64-AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1 ; X64-AVX2-NEXT: vmovd %xmm0, %eax ; X64-AVX2-NEXT: xorl %edx, %edx ; X64-AVX2-NEXT: divl 32(%rsi) diff --git a/llvm/test/CodeGen/X86/vec_cast.ll b/llvm/test/CodeGen/X86/vec_cast.ll index e0089354cc953..0a6bc2f59b685 100644 --- a/llvm/test/CodeGen/X86/vec_cast.ll +++ b/llvm/test/CodeGen/X86/vec_cast.ll @@ -156,7 +156,7 @@ define <3 x i16> @h(<3 x i32> %a) nounwind { ; CHECK-WIN-LABEL: h: ; CHECK-WIN: # %bb.0: ; CHECK-WIN-NEXT: movdqa (%rcx), %xmm0 -; CHECK-WIN-NEXT: movl (%rcx), %eax +; CHECK-WIN-NEXT: movd %xmm0, %eax ; CHECK-WIN-NEXT: pextrw $2, %xmm0, %edx ; CHECK-WIN-NEXT: pextrw $4, %xmm0, %ecx ; CHECK-WIN-NEXT: # kill: def $ax killed $ax killed $eax diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll index e95afd00304f2..12d7b05bf3dac 100644 --- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll @@ -2895,7 +2895,8 @@ define <2 x double> @sitofp_load_2i64_to_2f64(<2 x i64> *%a) { ; SSE2-LABEL: sitofp_load_2i64_to_2f64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa (%rdi), %xmm1 -; SSE2-NEXT: cvtsi2sdq (%rdi), %xmm0 +; SSE2-NEXT: movq %xmm1, %rax +; SSE2-NEXT: cvtsi2sd %rax, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 @@ -2905,30 +2906,43 @@ define <2 x double> @sitofp_load_2i64_to_2f64(<2 x i64> *%a) { ; ; SSE41-LABEL: sitofp_load_2i64_to_2f64: ; SSE41: # %bb.0: -; SSE41-NEXT: cvtsi2sdq 8(%rdi), %xmm1 -; SSE41-NEXT: cvtsi2sdq (%rdi), %xmm0 +; SSE41-NEXT: movdqa (%rdi), %xmm0 +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: cvtsi2sd %rax, %xmm1 +; SSE41-NEXT: movq %xmm0, %rax +; SSE41-NEXT: xorps %xmm0, %xmm0 +; SSE41-NEXT: cvtsi2sd %rax, %xmm0 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: retq ; ; VEX-LABEL: sitofp_load_2i64_to_2f64: ; VEX: # %bb.0: -; VEX-NEXT: vcvtsi2sdq 8(%rdi), %xmm0, %xmm0 -; VEX-NEXT: vcvtsi2sdq (%rdi), %xmm1, %xmm1 -; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; VEX-NEXT: vmovdqa (%rdi), %xmm0 +; VEX-NEXT: vpextrq $1, %xmm0, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm1, %xmm1 +; VEX-NEXT: vmovq %xmm0, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm2, %xmm0 +; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; VEX-NEXT: retq ; ; AVX512F-LABEL: sitofp_load_2i64_to_2f64: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtsi2sdq 8(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtsi2sdq (%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm1, %xmm1 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm2, %xmm0 +; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: sitofp_load_2i64_to_2f64: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtsi2sdq 8(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtsi2sdq (%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm1, %xmm1 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm2, %xmm0 +; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_load_2i64_to_2f64: @@ -3078,14 +3092,16 @@ define <4 x double> @sitofp_load_4i64_to_4f64(<4 x i64> *%a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa (%rdi), %xmm1 ; SSE2-NEXT: movdqa 16(%rdi), %xmm2 -; SSE2-NEXT: cvtsi2sdq (%rdi), %xmm0 +; SSE2-NEXT: movq %xmm1, %rax +; SSE2-NEXT: cvtsi2sd %rax, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2sd %rax, %xmm1 ; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: cvtsi2sdq 16(%rdi), %xmm1 +; SSE2-NEXT: cvtsi2sd %rax, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: xorps %xmm2, %xmm2 @@ -3095,46 +3111,72 @@ define <4 x double> @sitofp_load_4i64_to_4f64(<4 x i64> *%a) { ; ; SSE41-LABEL: sitofp_load_4i64_to_4f64: ; SSE41: # %bb.0: -; SSE41-NEXT: cvtsi2sdq 8(%rdi), %xmm1 -; SSE41-NEXT: cvtsi2sdq (%rdi), %xmm0 -; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; SSE41-NEXT: cvtsi2sdq 24(%rdi), %xmm2 +; SSE41-NEXT: movdqa (%rdi), %xmm0 +; SSE41-NEXT: movdqa 16(%rdi), %xmm1 +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: cvtsi2sd %rax, %xmm2 +; SSE41-NEXT: movq %xmm0, %rax +; SSE41-NEXT: xorps %xmm0, %xmm0 +; SSE41-NEXT: cvtsi2sd %rax, %xmm0 +; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; SSE41-NEXT: pextrq $1, %xmm1, %rax +; SSE41-NEXT: xorps %xmm2, %xmm2 +; SSE41-NEXT: cvtsi2sd %rax, %xmm2 +; SSE41-NEXT: movq %xmm1, %rax ; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2sdq 16(%rdi), %xmm1 +; SSE41-NEXT: cvtsi2sd %rax, %xmm1 ; SSE41-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; SSE41-NEXT: retq ; ; VEX-LABEL: sitofp_load_4i64_to_4f64: ; VEX: # %bb.0: -; VEX-NEXT: vcvtsi2sdq 24(%rdi), %xmm0, %xmm0 -; VEX-NEXT: vcvtsi2sdq 16(%rdi), %xmm1, %xmm1 -; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; VEX-NEXT: vcvtsi2sdq 8(%rdi), %xmm2, %xmm1 -; VEX-NEXT: vcvtsi2sdq (%rdi), %xmm2, %xmm2 -; VEX-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm2[0],xmm1[0] -; VEX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; VEX-NEXT: vmovapd (%rdi), %xmm0 +; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 +; VEX-NEXT: vpextrq $1, %xmm1, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm2, %xmm2 +; VEX-NEXT: vmovq %xmm1, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm3, %xmm1 +; VEX-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; VEX-NEXT: vpextrq $1, %xmm0, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm3, %xmm2 +; VEX-NEXT: vmovq %xmm0, %rax +; VEX-NEXT: vcvtsi2sd %rax, %xmm3, %xmm0 +; VEX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; VEX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; VEX-NEXT: retq ; ; AVX512F-LABEL: sitofp_load_4i64_to_4f64: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtsi2sdq 24(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtsi2sdq 16(%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; AVX512F-NEXT: vcvtsi2sdq 8(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vcvtsi2sdq (%rdi), %xmm2, %xmm2 -; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm2[0],xmm1[0] -; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512F-NEXT: vmovapd (%rdi), %xmm0 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512F-NEXT: vpextrq $1, %xmm1, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm2, %xmm2 +; AVX512F-NEXT: vmovq %xmm1, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm3, %xmm1 +; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm3, %xmm2 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtsi2sd %rax, %xmm3, %xmm0 +; AVX512F-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: sitofp_load_4i64_to_4f64: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtsi2sdq 24(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtsi2sdq 16(%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; AVX512VL-NEXT: vcvtsi2sdq 8(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vcvtsi2sdq (%rdi), %xmm2, %xmm2 -; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm2[0],xmm1[0] -; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512VL-NEXT: vmovapd (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm2, %xmm2 +; AVX512VL-NEXT: vmovq %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm3, %xmm1 +; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm3, %xmm2 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2sd %rax, %xmm3, %xmm0 +; AVX512VL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_load_4i64_to_4f64: @@ -3839,14 +3881,16 @@ define <4 x float> @sitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa (%rdi), %xmm1 ; SSE2-NEXT: movdqa 16(%rdi), %xmm0 -; SSE2-NEXT: cvtsi2ssq 16(%rdi), %xmm2 +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: cvtsi2ss %rax, %xmm2 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm0, %xmm0 -; SSE2-NEXT: cvtsi2ssq (%rdi), %xmm0 +; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 @@ -3857,47 +3901,72 @@ define <4 x float> @sitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; ; SSE41-LABEL: sitofp_load_4i64_to_4f32: ; SSE41: # %bb.0: -; SSE41-NEXT: cvtsi2ssq 8(%rdi), %xmm1 -; SSE41-NEXT: cvtsi2ssq (%rdi), %xmm0 -; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] -; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2ssq 16(%rdi), %xmm1 -; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] +; SSE41-NEXT: movdqa (%rdi), %xmm0 +; SSE41-NEXT: movdqa 16(%rdi), %xmm1 +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: cvtsi2ss %rax, %xmm2 +; SSE41-NEXT: movq %xmm0, %rax +; SSE41-NEXT: xorps %xmm0, %xmm0 +; SSE41-NEXT: cvtsi2ss %rax, %xmm0 +; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; SSE41-NEXT: movq %xmm1, %rax +; SSE41-NEXT: xorps %xmm2, %xmm2 +; SSE41-NEXT: cvtsi2ss %rax, %xmm2 +; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; SSE41-NEXT: pextrq $1, %xmm1, %rax ; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2ssq 24(%rdi), %xmm1 +; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE41-NEXT: retq ; ; VEX-LABEL: sitofp_load_4i64_to_4f32: ; VEX: # %bb.0: -; VEX-NEXT: vcvtsi2ssq 8(%rdi), %xmm0, %xmm0 -; VEX-NEXT: vcvtsi2ssq (%rdi), %xmm1, %xmm1 -; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; VEX-NEXT: vcvtsi2ssq 16(%rdi), %xmm2, %xmm1 -; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; VEX-NEXT: vcvtsi2ssq 24(%rdi), %xmm2, %xmm1 +; VEX-NEXT: vmovdqa (%rdi), %xmm0 +; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 +; VEX-NEXT: vpextrq $1, %xmm0, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 +; VEX-NEXT: vmovq %xmm0, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 +; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; VEX-NEXT: vmovq %xmm1, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 +; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; VEX-NEXT: vpextrq $1, %xmm1, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; VEX-NEXT: retq ; ; AVX512F-LABEL: sitofp_load_4i64_to_4f32: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtsi2ssq 8(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtsi2ssq (%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512F-NEXT: vcvtsi2ssq 16(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512F-NEXT: vcvtsi2ssq 24(%rdi), %xmm2, %xmm1 +; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; AVX512F-NEXT: vmovq %xmm1, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; AVX512F-NEXT: vpextrq $1, %xmm1, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: sitofp_load_4i64_to_4f32: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtsi2ssq 8(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtsi2ssq (%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512VL-NEXT: vcvtsi2ssq 16(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512VL-NEXT: vcvtsi2ssq 24(%rdi), %xmm2, %xmm1 +; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; AVX512VL-NEXT: vmovq %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: retq ; @@ -3991,29 +4060,33 @@ define <8 x float> @sitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-NEXT: movdqa 16(%rdi), %xmm0 ; SSE2-NEXT: movdqa 32(%rdi), %xmm2 ; SSE2-NEXT: movdqa 48(%rdi), %xmm3 -; SSE2-NEXT: cvtsi2ssq 16(%rdi), %xmm4 +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: cvtsi2ss %rax, %xmm4 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1] +; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm0, %xmm0 -; SSE2-NEXT: cvtsi2ssq (%rdi), %xmm0 +; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm4[0] +; SSE2-NEXT: movq %xmm3, %rax ; SSE2-NEXT: xorps %xmm4, %xmm4 -; SSE2-NEXT: cvtsi2ssq 48(%rdi), %xmm4 +; SSE2-NEXT: cvtsi2ss %rax, %xmm4 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] +; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: cvtsi2ssq 32(%rdi), %xmm1 +; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: xorps %xmm2, %xmm2 @@ -4024,82 +4097,132 @@ define <8 x float> @sitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; ; SSE41-LABEL: sitofp_load_8i64_to_8f32: ; SSE41: # %bb.0: -; SSE41-NEXT: cvtsi2ssq 8(%rdi), %xmm1 -; SSE41-NEXT: cvtsi2ssq (%rdi), %xmm0 -; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] -; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2ssq 16(%rdi), %xmm1 -; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] +; SSE41-NEXT: movdqa (%rdi), %xmm0 +; SSE41-NEXT: movdqa 16(%rdi), %xmm1 +; SSE41-NEXT: movdqa 32(%rdi), %xmm2 +; SSE41-NEXT: movdqa 48(%rdi), %xmm3 +; SSE41-NEXT: pextrq $1, %xmm0, %rax +; SSE41-NEXT: cvtsi2ss %rax, %xmm4 +; SSE41-NEXT: movq %xmm0, %rax +; SSE41-NEXT: xorps %xmm0, %xmm0 +; SSE41-NEXT: cvtsi2ss %rax, %xmm0 +; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[2,3] +; SSE41-NEXT: movq %xmm1, %rax +; SSE41-NEXT: xorps %xmm4, %xmm4 +; SSE41-NEXT: cvtsi2ss %rax, %xmm4 +; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm4[0],xmm0[3] +; SSE41-NEXT: pextrq $1, %xmm1, %rax ; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2ssq 24(%rdi), %xmm1 +; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; SSE41-NEXT: cvtsi2ssq 40(%rdi), %xmm2 +; SSE41-NEXT: pextrq $1, %xmm2, %rax +; SSE41-NEXT: xorps %xmm4, %xmm4 +; SSE41-NEXT: cvtsi2ss %rax, %xmm4 +; SSE41-NEXT: movq %xmm2, %rax ; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: cvtsi2ssq 32(%rdi), %xmm1 -; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] +; SSE41-NEXT: cvtsi2ss %rax, %xmm1 +; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3] +; SSE41-NEXT: movq %xmm3, %rax ; SSE41-NEXT: xorps %xmm2, %xmm2 -; SSE41-NEXT: cvtsi2ssq 48(%rdi), %xmm2 +; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] +; SSE41-NEXT: pextrq $1, %xmm3, %rax ; SSE41-NEXT: xorps %xmm2, %xmm2 -; SSE41-NEXT: cvtsi2ssq 56(%rdi), %xmm2 +; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; SSE41-NEXT: retq ; ; VEX-LABEL: sitofp_load_8i64_to_8f32: ; VEX: # %bb.0: -; VEX-NEXT: vcvtsi2ssq 40(%rdi), %xmm0, %xmm0 -; VEX-NEXT: vcvtsi2ssq 32(%rdi), %xmm1, %xmm1 -; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; VEX-NEXT: vcvtsi2ssq 48(%rdi), %xmm2, %xmm1 -; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; VEX-NEXT: vcvtsi2ssq 56(%rdi), %xmm2, %xmm1 +; VEX-NEXT: vmovaps (%rdi), %xmm0 +; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 +; VEX-NEXT: vmovdqa 32(%rdi), %xmm2 +; VEX-NEXT: vmovdqa 48(%rdi), %xmm3 +; VEX-NEXT: vpextrq $1, %xmm2, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 +; VEX-NEXT: vmovq %xmm2, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 +; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] +; VEX-NEXT: vmovq %xmm3, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 +; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] +; VEX-NEXT: vpextrq $1, %xmm3, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] +; VEX-NEXT: vpextrq $1, %xmm0, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; VEX-NEXT: vmovq %xmm0, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 +; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] +; VEX-NEXT: vmovq %xmm1, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] +; VEX-NEXT: vpextrq $1, %xmm1, %rax +; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; VEX-NEXT: vcvtsi2ssq 8(%rdi), %xmm2, %xmm1 -; VEX-NEXT: vcvtsi2ssq (%rdi), %xmm2, %xmm2 -; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] -; VEX-NEXT: vcvtsi2ssq 16(%rdi), %xmm3, %xmm2 -; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] -; VEX-NEXT: vcvtsi2ssq 24(%rdi), %xmm3, %xmm2 -; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; VEX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; VEX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; VEX-NEXT: retq ; ; AVX512F-LABEL: sitofp_load_8i64_to_8f32: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtsi2ssq 40(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtsi2ssq 32(%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512F-NEXT: vcvtsi2ssq 48(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512F-NEXT: vcvtsi2ssq 56(%rdi), %xmm2, %xmm1 +; AVX512F-NEXT: vmovaps (%rdi), %xmm0 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 +; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 +; AVX512F-NEXT: vpextrq $1, %xmm2, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 +; AVX512F-NEXT: vmovq %xmm2, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] +; AVX512F-NEXT: vmovq %xmm3, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] +; AVX512F-NEXT: vpextrq $1, %xmm3, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] +; AVX512F-NEXT: vmovq %xmm1, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] +; AVX512F-NEXT: vpextrq $1, %xmm1, %rax +; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; AVX512F-NEXT: vcvtsi2ssq 8(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vcvtsi2ssq (%rdi), %xmm2, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] -; AVX512F-NEXT: vcvtsi2ssq 16(%rdi), %xmm3, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] -; AVX512F-NEXT: vcvtsi2ssq 24(%rdi), %xmm3, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: sitofp_load_8i64_to_8f32: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtsi2ssq 40(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtsi2ssq 32(%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512VL-NEXT: vcvtsi2ssq 48(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512VL-NEXT: vcvtsi2ssq 56(%rdi), %xmm2, %xmm1 +; AVX512VL-NEXT: vmovaps (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 +; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 +; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 +; AVX512VL-NEXT: vmovq %xmm2, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] +; AVX512VL-NEXT: vmovq %xmm3, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] +; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] +; AVX512VL-NEXT: vmovq %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] +; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax +; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; AVX512VL-NEXT: vcvtsi2ssq 8(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vcvtsi2ssq (%rdi), %xmm2, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] -; AVX512VL-NEXT: vcvtsi2ssq 16(%rdi), %xmm3, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] -; AVX512VL-NEXT: vcvtsi2ssq 24(%rdi), %xmm3, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_load_8i64_to_8f32: @@ -4229,7 +4352,7 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; SSE2-LABEL: uitofp_load_4i64_to_4f32: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa 16(%rdi), %xmm0 -; SSE2-NEXT: movq 16(%rdi), %rax +; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB83_1 ; SSE2-NEXT: # %bb.2: @@ -4243,23 +4366,23 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: addss %xmm1, %xmm1 ; SSE2-NEXT: .LBB83_3: -; SSE2-NEXT: movq (%rdi), %rax +; SSE2-NEXT: movdqa (%rdi), %xmm2 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; SSE2-NEXT: movq %xmm0, %rcx -; SSE2-NEXT: testq %rcx, %rcx +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB83_4 ; SSE2-NEXT: # %bb.5: -; SSE2-NEXT: cvtsi2ss %rcx, %xmm2 +; SSE2-NEXT: cvtsi2ss %rax, %xmm3 ; SSE2-NEXT: jmp .LBB83_6 ; SSE2-NEXT: .LBB83_4: -; SSE2-NEXT: movq %rcx, %rdx -; SSE2-NEXT: shrq %rdx -; SSE2-NEXT: andl $1, %ecx -; SSE2-NEXT: orq %rdx, %rcx -; SSE2-NEXT: cvtsi2ss %rcx, %xmm2 -; SSE2-NEXT: addss %xmm2, %xmm2 +; SSE2-NEXT: movq %rax, %rcx +; SSE2-NEXT: shrq %rcx +; SSE2-NEXT: andl $1, %eax +; SSE2-NEXT: orq %rcx, %rax +; SSE2-NEXT: cvtsi2ss %rax, %xmm3 +; SSE2-NEXT: addss %xmm3, %xmm3 ; SSE2-NEXT: .LBB83_6: -; SSE2-NEXT: movdqa (%rdi), %xmm3 +; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB83_7 ; SSE2-NEXT: # %bb.8: @@ -4275,8 +4398,8 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: addss %xmm0, %xmm0 ; SSE2-NEXT: .LBB83_9: -; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,2,3] +; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB83_10 @@ -4397,23 +4520,35 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; ; AVX512F-LABEL: uitofp_load_4i64_to_4f32: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtusi2ssq 8(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtusi2ssq (%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512F-NEXT: vcvtusi2ssq 16(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512F-NEXT: vcvtusi2ssq 24(%rdi), %xmm2, %xmm1 +; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; AVX512F-NEXT: vmovq %xmm1, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; AVX512F-NEXT: vpextrq $1, %xmm1, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_load_4i64_to_4f32: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtusi2ssq 8(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtusi2ssq (%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512VL-NEXT: vcvtusi2ssq 16(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512VL-NEXT: vcvtusi2ssq 24(%rdi), %xmm2, %xmm1 +; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] +; AVX512VL-NEXT: vmovq %xmm1, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] +; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: retq ; @@ -4566,7 +4701,7 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-LABEL: uitofp_load_8i64_to_8f32: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa 16(%rdi), %xmm0 -; SSE2-NEXT: movq 16(%rdi), %rax +; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_1 ; SSE2-NEXT: # %bb.2: @@ -4580,23 +4715,23 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-NEXT: cvtsi2ss %rax, %xmm2 ; SSE2-NEXT: addss %xmm2, %xmm2 ; SSE2-NEXT: .LBB87_3: -; SSE2-NEXT: movq (%rdi), %rax +; SSE2-NEXT: movdqa (%rdi), %xmm3 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; SSE2-NEXT: movq %xmm0, %rcx -; SSE2-NEXT: testq %rcx, %rcx +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_4 ; SSE2-NEXT: # %bb.5: -; SSE2-NEXT: cvtsi2ss %rcx, %xmm1 +; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB87_6 ; SSE2-NEXT: .LBB87_4: -; SSE2-NEXT: movq %rcx, %rdx -; SSE2-NEXT: shrq %rdx -; SSE2-NEXT: andl $1, %ecx -; SSE2-NEXT: orq %rdx, %rcx -; SSE2-NEXT: cvtsi2ss %rcx, %xmm1 +; SSE2-NEXT: movq %rax, %rcx +; SSE2-NEXT: shrq %rcx +; SSE2-NEXT: andl $1, %eax +; SSE2-NEXT: orq %rcx, %rax +; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: addss %xmm1, %xmm1 ; SSE2-NEXT: .LBB87_6: -; SSE2-NEXT: movdqa (%rdi), %xmm3 +; SSE2-NEXT: movq %xmm3, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_7 ; SSE2-NEXT: # %bb.8: @@ -4612,23 +4747,23 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: addss %xmm0, %xmm0 ; SSE2-NEXT: .LBB87_9: -; SSE2-NEXT: movq 48(%rdi), %rax +; SSE2-NEXT: movdqa 48(%rdi), %xmm6 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3] -; SSE2-NEXT: movq %xmm3, %rcx -; SSE2-NEXT: testq %rcx, %rcx +; SSE2-NEXT: movq %xmm3, %rax +; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_10 ; SSE2-NEXT: # %bb.11: -; SSE2-NEXT: cvtsi2ss %rcx, %xmm4 +; SSE2-NEXT: cvtsi2ss %rax, %xmm4 ; SSE2-NEXT: jmp .LBB87_12 ; SSE2-NEXT: .LBB87_10: -; SSE2-NEXT: movq %rcx, %rdx -; SSE2-NEXT: shrq %rdx -; SSE2-NEXT: andl $1, %ecx -; SSE2-NEXT: orq %rdx, %rcx -; SSE2-NEXT: cvtsi2ss %rcx, %xmm4 +; SSE2-NEXT: movq %rax, %rcx +; SSE2-NEXT: shrq %rcx +; SSE2-NEXT: andl $1, %eax +; SSE2-NEXT: orq %rcx, %rax +; SSE2-NEXT: cvtsi2ss %rax, %xmm4 ; SSE2-NEXT: addss %xmm4, %xmm4 ; SSE2-NEXT: .LBB87_12: -; SSE2-NEXT: movdqa 48(%rdi), %xmm5 +; SSE2-NEXT: movq %xmm6, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_13 ; SSE2-NEXT: # %bb.14: @@ -4644,27 +4779,27 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-NEXT: cvtsi2ss %rax, %xmm3 ; SSE2-NEXT: addss %xmm3, %xmm3 ; SSE2-NEXT: .LBB87_15: -; SSE2-NEXT: movq 32(%rdi), %rax -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3] -; SSE2-NEXT: movq %xmm5, %rcx -; SSE2-NEXT: testq %rcx, %rcx +; SSE2-NEXT: movdqa 32(%rdi), %xmm5 +; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,2,3] +; SSE2-NEXT: movq %xmm6, %rax +; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_16 ; SSE2-NEXT: # %bb.17: -; SSE2-NEXT: xorps %xmm5, %xmm5 -; SSE2-NEXT: cvtsi2ss %rcx, %xmm5 +; SSE2-NEXT: xorps %xmm6, %xmm6 +; SSE2-NEXT: cvtsi2ss %rax, %xmm6 ; SSE2-NEXT: jmp .LBB87_18 ; SSE2-NEXT: .LBB87_16: -; SSE2-NEXT: movq %rcx, %rdx -; SSE2-NEXT: shrq %rdx -; SSE2-NEXT: andl $1, %ecx -; SSE2-NEXT: orq %rdx, %rcx -; SSE2-NEXT: xorps %xmm5, %xmm5 -; SSE2-NEXT: cvtsi2ss %rcx, %xmm5 -; SSE2-NEXT: addss %xmm5, %xmm5 +; SSE2-NEXT: movq %rax, %rcx +; SSE2-NEXT: shrq %rcx +; SSE2-NEXT: andl $1, %eax +; SSE2-NEXT: orq %rcx, %rax +; SSE2-NEXT: xorps %xmm6, %xmm6 +; SSE2-NEXT: cvtsi2ss %rax, %xmm6 +; SSE2-NEXT: addss %xmm6, %xmm6 ; SSE2-NEXT: .LBB87_18: ; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1] -; SSE2-NEXT: movdqa 32(%rdi), %xmm4 +; SSE2-NEXT: movq %xmm5, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_19 ; SSE2-NEXT: # %bb.20: @@ -4681,8 +4816,8 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; SSE2-NEXT: addss %xmm1, %xmm1 ; SSE2-NEXT: .LBB87_21: ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] -; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,2,3] +; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm6[0],xmm3[1],xmm6[1] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3] ; SSE2-NEXT: movq %xmm2, %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_22 @@ -4886,40 +5021,64 @@ define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { ; ; AVX512F-LABEL: uitofp_load_8i64_to_8f32: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vcvtusi2ssq 40(%rdi), %xmm0, %xmm0 -; AVX512F-NEXT: vcvtusi2ssq 32(%rdi), %xmm1, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512F-NEXT: vcvtusi2ssq 48(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512F-NEXT: vcvtusi2ssq 56(%rdi), %xmm2, %xmm1 +; AVX512F-NEXT: vmovaps (%rdi), %xmm0 +; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 +; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 +; AVX512F-NEXT: vpextrq $1, %xmm2, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4 +; AVX512F-NEXT: vmovq %xmm2, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] +; AVX512F-NEXT: vmovq %xmm3, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] +; AVX512F-NEXT: vpextrq $1, %xmm3, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] +; AVX512F-NEXT: vpextrq $1, %xmm0, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] +; AVX512F-NEXT: vmovq %xmm1, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] +; AVX512F-NEXT: vpextrq $1, %xmm1, %rax +; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1 ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; AVX512F-NEXT: vcvtusi2ssq 8(%rdi), %xmm2, %xmm1 -; AVX512F-NEXT: vcvtusi2ssq (%rdi), %xmm2, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] -; AVX512F-NEXT: vcvtusi2ssq 16(%rdi), %xmm3, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] -; AVX512F-NEXT: vcvtusi2ssq 24(%rdi), %xmm3, %xmm2 -; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_load_8i64_to_8f32: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vcvtusi2ssq 40(%rdi), %xmm0, %xmm0 -; AVX512VL-NEXT: vcvtusi2ssq 32(%rdi), %xmm1, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] -; AVX512VL-NEXT: vcvtusi2ssq 48(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] -; AVX512VL-NEXT: vcvtusi2ssq 56(%rdi), %xmm2, %xmm1 +; AVX512VL-NEXT: vmovaps (%rdi), %xmm0 +; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 +; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 +; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 +; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4 +; AVX512VL-NEXT: vmovq %xmm2, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] +; AVX512VL-NEXT: vmovq %xmm3, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] +; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] +; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vmovq %xmm0, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] +; AVX512VL-NEXT: vmovq %xmm1, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 +; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] +; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax +; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1 ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] -; AVX512VL-NEXT: vcvtusi2ssq 8(%rdi), %xmm2, %xmm1 -; AVX512VL-NEXT: vcvtusi2ssq (%rdi), %xmm2, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] -; AVX512VL-NEXT: vcvtusi2ssq 16(%rdi), %xmm3, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] -; AVX512VL-NEXT: vcvtusi2ssq 24(%rdi), %xmm3, %xmm2 -; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; AVX512VL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: uitofp_load_8i64_to_8f32: From dbf2f560947fcf8e7460fea3bfde443fef0eddf7 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 3 Feb 2022 17:26:19 -0800 Subject: [PATCH 050/316] [lldb] Improve RichManglingContext ergonomics (NFC) Have the different ::Parse.* methods return the demangled string directly instead of having to go through ::GetBufferRef. Differential revision: https://reviews.llvm.org/D118953 (cherry picked from commit fa52788b7a6da1eab9fec0f2db5f74a8db555196) --- lldb/include/lldb/Core/RichManglingContext.h | 29 +++-------- lldb/source/Core/Mangled.cpp | 3 +- lldb/source/Core/RichManglingContext.cpp | 46 ++++++++--------- lldb/source/Symbol/Symtab.cpp | 7 +-- .../Core/RichManglingContextTest.cpp | 51 ++++++------------- 5 files changed, 47 insertions(+), 89 deletions(-) diff --git a/lldb/include/lldb/Core/RichManglingContext.h b/lldb/include/lldb/Core/RichManglingContext.h index a6b7af8d8d7ec..ecd11e93f044d 100644 --- a/lldb/include/lldb/Core/RichManglingContext.h +++ b/lldb/include/lldb/Core/RichManglingContext.h @@ -43,25 +43,15 @@ class RichManglingContext { bool IsCtorOrDtor() const; /// Get the base name of a function. This doesn't include trailing template - /// arguments, ie "a::b" gives "b". The result will overwrite the - /// internal buffer. It can be obtained via GetBufferRef(). - void ParseFunctionBaseName(); + /// arguments, ie "a::b" gives "b". + llvm::StringRef ParseFunctionBaseName(); /// Get the context name for a function. For "a::b::c", this function returns - /// "a::b". The result will overwrite the internal buffer. It can be obtained - /// via GetBufferRef(). - void ParseFunctionDeclContextName(); - - /// Get the entire demangled name. The result will overwrite the internal - /// buffer. It can be obtained via GetBufferRef(). - void ParseFullName(); - - /// Obtain a StringRef to the internal buffer that holds the result of the - /// most recent ParseXy() operation. The next ParseXy() call invalidates it. - llvm::StringRef GetBufferRef() const { - assert(m_provider != None && "Initialize a provider first"); - return m_buffer; - } + /// "a::b". + llvm::StringRef ParseFunctionDeclContextName(); + + /// Get the entire demangled name. + llvm::StringRef ParseFullName(); private: enum InfoProvider { None, ItaniumPartialDemangler, PluginCxxLanguage }; @@ -69,9 +59,6 @@ class RichManglingContext { /// Selects the rich mangling info provider. InfoProvider m_provider = None; - /// Reference to the buffer used for results of ParseXy() operations. - llvm::StringRef m_buffer; - /// Members for ItaniumPartialDemangler llvm::ItaniumPartialDemangler m_ipd; /// Note: m_ipd_buf is a raw pointer due to being resized by realloc via @@ -93,7 +80,7 @@ class RichManglingContext { void ResetProvider(InfoProvider new_provider); /// Uniform handling of string buffers for ItaniumPartialDemangler. - void processIPDStrResult(char *ipd_res, size_t res_len); + llvm::StringRef processIPDStrResult(char *ipd_res, size_t res_len); /// Cast the given parser to the given type. Ideally we would have a type /// trait to deduce \a ParserT from a given InfoProvider, but unfortunately we diff --git a/lldb/source/Core/Mangled.cpp b/lldb/source/Core/Mangled.cpp index 4e10324401dc0..7af1ad66f5b5a 100644 --- a/lldb/source/Core/Mangled.cpp +++ b/lldb/source/Core/Mangled.cpp @@ -217,8 +217,7 @@ bool Mangled::DemangleWithRichManglingInfo( if (context.FromItaniumName(m_mangled)) { // If we got an info, we have a name. Copy to string pool and connect the // counterparts to accelerate later access in GetDemangledName(). - context.ParseFullName(); - m_demangled.SetStringWithMangledCounterpart(context.GetBufferRef(), + m_demangled.SetStringWithMangledCounterpart(context.ParseFullName(), m_mangled); return true; } else { diff --git a/lldb/source/Core/RichManglingContext.cpp b/lldb/source/Core/RichManglingContext.cpp index 63170feb6231c..cecb5c6a2e548 100644 --- a/lldb/source/Core/RichManglingContext.cpp +++ b/lldb/source/Core/RichManglingContext.cpp @@ -83,15 +83,15 @@ bool RichManglingContext::IsCtorOrDtor() const { llvm_unreachable("Fully covered switch above!"); } -void RichManglingContext::processIPDStrResult(char *ipd_res, size_t res_size) { +llvm::StringRef RichManglingContext::processIPDStrResult(char *ipd_res, + size_t res_size) { // Error case: Clear the buffer. if (LLVM_UNLIKELY(ipd_res == nullptr)) { assert(res_size == m_ipd_buf_size && "Failed IPD queries keep the original size in the N parameter"); m_ipd_buf[0] = '\0'; - m_buffer = llvm::StringRef(m_ipd_buf, 0); - return; + return llvm::StringRef(m_ipd_buf, 0); } // IPD's res_size includes null terminator. @@ -109,60 +109,54 @@ void RichManglingContext::processIPDStrResult(char *ipd_res, size_t res_size) { } // 99% case: Just remember the string length. - m_buffer = llvm::StringRef(m_ipd_buf, res_size - 1); + return llvm::StringRef(m_ipd_buf, res_size - 1); } -void RichManglingContext::ParseFunctionBaseName() { +llvm::StringRef RichManglingContext::ParseFunctionBaseName() { assert(m_provider != None && "Initialize a provider first"); switch (m_provider) { case ItaniumPartialDemangler: { auto n = m_ipd_buf_size; auto buf = m_ipd.getFunctionBaseName(m_ipd_buf, &n); - processIPDStrResult(buf, n); - return; + return processIPDStrResult(buf, n); } case PluginCxxLanguage: - m_buffer = - get(m_cxx_method_parser)->GetBasename(); - return; + return get(m_cxx_method_parser) + ->GetBasename(); case None: - return; + return {}; } } -void RichManglingContext::ParseFunctionDeclContextName() { +llvm::StringRef RichManglingContext::ParseFunctionDeclContextName() { assert(m_provider != None && "Initialize a provider first"); switch (m_provider) { case ItaniumPartialDemangler: { auto n = m_ipd_buf_size; auto buf = m_ipd.getFunctionDeclContextName(m_ipd_buf, &n); - processIPDStrResult(buf, n); - return; + return processIPDStrResult(buf, n); } case PluginCxxLanguage: - m_buffer = - get(m_cxx_method_parser)->GetContext(); - return; + return get(m_cxx_method_parser) + ->GetContext(); case None: - return; + return {}; } } -void RichManglingContext::ParseFullName() { +llvm::StringRef RichManglingContext::ParseFullName() { assert(m_provider != None && "Initialize a provider first"); switch (m_provider) { case ItaniumPartialDemangler: { auto n = m_ipd_buf_size; auto buf = m_ipd.finishDemangle(m_ipd_buf, &n); - processIPDStrResult(buf, n); - return; + return processIPDStrResult(buf, n); } case PluginCxxLanguage: - m_buffer = get(m_cxx_method_parser) - ->GetFullName() - .GetStringRef(); - return; + return get(m_cxx_method_parser) + ->GetFullName() + .GetStringRef(); case None: - return; + return {}; } } diff --git a/lldb/source/Symbol/Symtab.cpp b/lldb/source/Symbol/Symtab.cpp index 97dc31bc97660..765e7bc9520fd 100644 --- a/lldb/source/Symbol/Symtab.cpp +++ b/lldb/source/Symbol/Symtab.cpp @@ -383,16 +383,13 @@ void Symtab::RegisterMangledNameEntry( std::vector> &backlog, RichManglingContext &rmc) { // Only register functions that have a base name. - rmc.ParseFunctionBaseName(); - llvm::StringRef base_name = rmc.GetBufferRef(); + llvm::StringRef base_name = rmc.ParseFunctionBaseName(); if (base_name.empty()) return; // The base name will be our entry's name. NameToIndexMap::Entry entry(ConstString(base_name), value); - - rmc.ParseFunctionDeclContextName(); - llvm::StringRef decl_context = rmc.GetBufferRef(); + llvm::StringRef decl_context = rmc.ParseFunctionDeclContextName(); // Register functions with no context. if (decl_context.empty()) { diff --git a/lldb/unittests/Core/RichManglingContextTest.cpp b/lldb/unittests/Core/RichManglingContextTest.cpp index 89e9ef03650f9..65a5503c61a30 100644 --- a/lldb/unittests/Core/RichManglingContextTest.cpp +++ b/lldb/unittests/Core/RichManglingContextTest.cpp @@ -18,18 +18,12 @@ using namespace lldb_private; TEST(RichManglingContextTest, Basic) { RichManglingContext RMC; ConstString mangled("_ZN3foo3barEv"); - EXPECT_TRUE(RMC.FromItaniumName(mangled)); + EXPECT_TRUE(RMC.FromItaniumName(mangled)); EXPECT_FALSE(RMC.IsCtorOrDtor()); - - RMC.ParseFunctionDeclContextName(); - EXPECT_EQ("foo", RMC.GetBufferRef()); - - RMC.ParseFunctionBaseName(); - EXPECT_EQ("bar", RMC.GetBufferRef()); - - RMC.ParseFullName(); - EXPECT_EQ("foo::bar()", RMC.GetBufferRef()); + EXPECT_EQ("foo", RMC.ParseFunctionDeclContextName()); + EXPECT_EQ("bar", RMC.ParseFunctionBaseName()); + EXPECT_EQ("foo::bar()", RMC.ParseFullName()); } TEST(RichManglingContextTest, FromCxxMethodName) { @@ -41,19 +35,12 @@ TEST(RichManglingContextTest, FromCxxMethodName) { ConstString demangled("foo::bar()"); EXPECT_TRUE(CxxMethodRMC.FromCxxMethodName(demangled)); - EXPECT_TRUE(ItaniumRMC.IsCtorOrDtor() == CxxMethodRMC.IsCtorOrDtor()); - - ItaniumRMC.ParseFunctionDeclContextName(); - CxxMethodRMC.ParseFunctionDeclContextName(); - EXPECT_TRUE(ItaniumRMC.GetBufferRef() == CxxMethodRMC.GetBufferRef()); - - ItaniumRMC.ParseFunctionBaseName(); - CxxMethodRMC.ParseFunctionBaseName(); - EXPECT_TRUE(ItaniumRMC.GetBufferRef() == CxxMethodRMC.GetBufferRef()); - - ItaniumRMC.ParseFullName(); - CxxMethodRMC.ParseFullName(); - EXPECT_TRUE(ItaniumRMC.GetBufferRef() == CxxMethodRMC.GetBufferRef()); + EXPECT_EQ(ItaniumRMC.IsCtorOrDtor(), CxxMethodRMC.IsCtorOrDtor()); + EXPECT_EQ(ItaniumRMC.ParseFunctionDeclContextName(), + CxxMethodRMC.ParseFunctionDeclContextName()); + EXPECT_EQ(ItaniumRMC.ParseFunctionBaseName(), + CxxMethodRMC.ParseFunctionBaseName()); + EXPECT_EQ(ItaniumRMC.ParseFullName(), CxxMethodRMC.ParseFullName()); // Construct with a random name. { @@ -68,8 +55,7 @@ TEST(RichManglingContextTest, FromCxxMethodName) { ConstString("void * operator new(unsigned __int64)"))); // We expect its context is empty. - CxxMethodRMC.ParseFunctionDeclContextName(); - EXPECT_TRUE(CxxMethodRMC.GetBufferRef().empty()); + EXPECT_TRUE(CxxMethodRMC.ParseFunctionDeclContextName().empty()); } } @@ -79,16 +65,13 @@ TEST(RichManglingContextTest, SwitchProvider) { llvm::StringRef demangled = "foo::bar()"; EXPECT_TRUE(RMC.FromItaniumName(ConstString(mangled))); - RMC.ParseFullName(); - EXPECT_EQ("foo::bar()", RMC.GetBufferRef()); + EXPECT_EQ("foo::bar()", RMC.ParseFullName()); EXPECT_TRUE(RMC.FromCxxMethodName(ConstString(demangled))); - RMC.ParseFullName(); - EXPECT_EQ("foo::bar()", RMC.GetBufferRef()); + EXPECT_EQ("foo::bar()", RMC.ParseFullName()); EXPECT_TRUE(RMC.FromItaniumName(ConstString(mangled))); - RMC.ParseFullName(); - EXPECT_EQ("foo::bar()", RMC.GetBufferRef()); + EXPECT_EQ("foo::bar()", RMC.ParseFullName()); } TEST(RichManglingContextTest, IPDRealloc) { @@ -116,13 +99,11 @@ TEST(RichManglingContextTest, IPDRealloc) { // Demangle the short one. EXPECT_TRUE(RMC.FromItaniumName(ConstString(ShortMangled))); - RMC.ParseFullName(); - const char *ShortDemangled = RMC.GetBufferRef().data(); + const char *ShortDemangled = RMC.ParseFullName().data(); // Demangle the long one. EXPECT_TRUE(RMC.FromItaniumName(ConstString(LongMangled))); - RMC.ParseFullName(); - const char *LongDemangled = RMC.GetBufferRef().data(); + const char *LongDemangled = RMC.ParseFullName().data(); // Make sure a new buffer was allocated or the default buffer was extended. bool AllocatedNewBuffer = (ShortDemangled != LongDemangled); From bee0279abedae908e344d740d5e95f4bc5e5557e Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 3 Feb 2022 10:48:16 -0800 Subject: [PATCH 051/316] [lldb] Don't construct the demangled strings while indexing the symbol table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The symbol table needs to demangle all symbol names when building its index. However, this doesn't require the full mangled name: we only need the base name and the function declaration context. Currently, we always construct the demangled string during indexing and cache it in the string pool as a way to speed up future lookups. Constructing the demangled string is by far the most expensive step of the demangling process, because the output string can be exponentially larger than the input and unless you're dumping the symbol table, many of those demangled names will not be needed again. This patch avoids constructing the full demangled string when we can partially demangle. This speeds up indexing and reduces memory usage. I gathered some numbers by attaching to Slack: Before ------ Memory usage: 280MB Benchmark 1: ./bin/lldb -n Slack -o quit Time (mean ± σ): 4.829 s ± 0.518 s [User: 4.012 s, System: 0.208 s] Range (min … max): 4.624 s … 6.294 s 10 runs After ----- Memory usage: 189MB Benchmark 1: ./bin/lldb -n Slack -o quit Time (mean ± σ): 4.182 s ± 0.025 s [User: 3.536 s, System: 0.192 s] Range (min … max): 4.152 s … 4.233 s 10 runs Differential revision: https://reviews.llvm.org/D118814 (cherry picked from commit aed965d55d460ebcc2b442b9d799b4c1ab929157) --- lldb/source/Core/Mangled.cpp | 16 ++++------------ lldb/source/Symbol/Symtab.cpp | 4 +++- .../dyld-trie-symbols/TestDyldTrieSymbols.py | 4 ---- 3 files changed, 7 insertions(+), 17 deletions(-) diff --git a/lldb/source/Core/Mangled.cpp b/lldb/source/Core/Mangled.cpp index 7af1ad66f5b5a..14d170b61366e 100644 --- a/lldb/source/Core/Mangled.cpp +++ b/lldb/source/Core/Mangled.cpp @@ -214,24 +214,16 @@ bool Mangled::DemangleWithRichManglingInfo( case eManglingSchemeItanium: // We want the rich mangling info here, so we don't care whether or not // there is a demangled string in the pool already. - if (context.FromItaniumName(m_mangled)) { - // If we got an info, we have a name. Copy to string pool and connect the - // counterparts to accelerate later access in GetDemangledName(). - m_demangled.SetStringWithMangledCounterpart(context.ParseFullName(), - m_mangled); - return true; - } else { - m_demangled.SetCString(""); - return false; - } + return context.FromItaniumName(m_mangled); case eManglingSchemeMSVC: { // We have no rich mangling for MSVC-mangled names yet, so first try to // demangle it if necessary. if (!m_demangled && !m_mangled.GetMangledCounterpart(m_demangled)) { if (char *d = GetMSVCDemangledStr(m_mangled.GetCString())) { - // If we got an info, we have a name. Copy to string pool and connect - // the counterparts to accelerate later access in GetDemangledName(). + // Without the rich mangling info we have to demangle the full name. + // Copy it to string pool and connect the counterparts to accelerate + // later access in GetDemangledName(). m_demangled.SetStringWithMangledCounterpart(llvm::StringRef(d), m_mangled); ::free(d); diff --git a/lldb/source/Symbol/Symtab.cpp b/lldb/source/Symbol/Symtab.cpp index 765e7bc9520fd..436f97e623819 100644 --- a/lldb/source/Symbol/Symtab.cpp +++ b/lldb/source/Symbol/Symtab.cpp @@ -328,8 +328,10 @@ void Symtab::InitNameIndexes() { const SymbolType type = symbol->GetType(); if (type == eSymbolTypeCode || type == eSymbolTypeResolver) { - if (mangled.DemangleWithRichManglingInfo(rmc, lldb_skip_name)) + if (mangled.DemangleWithRichManglingInfo(rmc, lldb_skip_name)) { RegisterMangledNameEntry(value, class_contexts, backlog, rmc); + continue; + } } } diff --git a/lldb/test/API/macosx/dyld-trie-symbols/TestDyldTrieSymbols.py b/lldb/test/API/macosx/dyld-trie-symbols/TestDyldTrieSymbols.py index 3455f21392dc4..6f2f1c5b7cee4 100644 --- a/lldb/test/API/macosx/dyld-trie-symbols/TestDyldTrieSymbols.py +++ b/lldb/test/API/macosx/dyld-trie-symbols/TestDyldTrieSymbols.py @@ -43,8 +43,6 @@ def test_dyld_trie_symbols(self): self.assertEqual(unstripped_Z3pat_symbols.GetSize(), 1) unstripped_pat_symbols = unstripped_target.FindSymbols("pat") self.assertEqual(unstripped_pat_symbols.GetSize(), 1) - unstripped_patint_symbols = unstripped_target.FindSymbols("pat(int)") - self.assertEqual(unstripped_patint_symbols.GetSize(), 1) unstripped_bar_symbols = unstripped_target.FindSymbols("bar") self.assertEqual(unstripped_bar_symbols.GetSize(), 1) @@ -77,8 +75,6 @@ def test_dyld_trie_symbols(self): self.assertEqual(stripped_Z3pat_symbols.GetSize(), 1) stripped_pat_symbols = stripped_target.FindSymbols("pat") self.assertEqual(stripped_pat_symbols.GetSize(), 1) - stripped_patint_symbols = stripped_target.FindSymbols("pat(int)") - self.assertEqual(stripped_patint_symbols.GetSize(), 1) # bar should have been strippped. We should not find it, or the # stripping went wrong. From 39b1d3d27ae3d0355e3b10789d63bf1e645b3d1d Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Fri, 4 Feb 2022 10:32:34 -0800 Subject: [PATCH 052/316] [lldb] Rename DemangleWithRichManglingInfo to GetRichManglingInfo (NFC) This addresses Pavel's comment from D118814. (cherry picked from commit edbb0f6df76b04100357c7c9438f3b5b978e0200) --- lldb/include/lldb/Core/Mangled.h | 11 +++++------ lldb/source/Core/Mangled.cpp | 4 ++-- lldb/source/Symbol/Symtab.cpp | 2 +- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/lldb/include/lldb/Core/Mangled.h b/lldb/include/lldb/Core/Mangled.h index 4e4f75e18e34d..aaefb69f017bc 100644 --- a/lldb/include/lldb/Core/Mangled.h +++ b/lldb/include/lldb/Core/Mangled.h @@ -226,10 +226,9 @@ class Mangled { /// Function signature for filtering mangled names. using SkipMangledNameFn = bool(llvm::StringRef, ManglingScheme); - /// Trigger explicit demangling to obtain rich mangling information. This is - /// optimized for batch processing while populating a name index. To get the - /// pure demangled name string for a single entity, use GetDemangledName() - /// instead. + /// Get rich mangling information. This is optimized for batch processing + /// while populating a name index. To get the pure demangled name string for + /// a single entity, use GetDemangledName() instead. /// /// For names that match the Itanium mangling scheme, this uses LLVM's /// ItaniumPartialDemangler. All other names fall back to LLDB's builtin @@ -248,8 +247,8 @@ class Mangled { /// /// \return /// True on success, false otherwise. - bool DemangleWithRichManglingInfo(RichManglingContext &context, - SkipMangledNameFn *skip_mangled_name); + bool GetRichManglingInfo(RichManglingContext &context, + SkipMangledNameFn *skip_mangled_name); /// Try to identify the mangling scheme used. /// \param[in] name diff --git a/lldb/source/Core/Mangled.cpp b/lldb/source/Core/Mangled.cpp index 14d170b61366e..b8e405544b332 100644 --- a/lldb/source/Core/Mangled.cpp +++ b/lldb/source/Core/Mangled.cpp @@ -195,8 +195,8 @@ static char *GetDLangDemangledStr(const char *M) { // Explicit demangling for scheduled requests during batch processing. This // makes use of ItaniumPartialDemangler's rich demangle info -bool Mangled::DemangleWithRichManglingInfo( - RichManglingContext &context, SkipMangledNameFn *skip_mangled_name) { +bool Mangled::GetRichManglingInfo(RichManglingContext &context, + SkipMangledNameFn *skip_mangled_name) { // Others are not meant to arrive here. ObjC names or C's main() for example // have their names stored in m_demangled, while m_mangled is empty. assert(m_mangled); diff --git a/lldb/source/Symbol/Symtab.cpp b/lldb/source/Symbol/Symtab.cpp index 436f97e623819..d148706003adf 100644 --- a/lldb/source/Symbol/Symtab.cpp +++ b/lldb/source/Symbol/Symtab.cpp @@ -328,7 +328,7 @@ void Symtab::InitNameIndexes() { const SymbolType type = symbol->GetType(); if (type == eSymbolTypeCode || type == eSymbolTypeResolver) { - if (mangled.DemangleWithRichManglingInfo(rmc, lldb_skip_name)) { + if (mangled.GetRichManglingInfo(rmc, lldb_skip_name)) { RegisterMangledNameEntry(value, class_contexts, backlog, rmc); continue; } From 47ea1e198cec19da30fd3e63b4452147696fb388 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Sat, 5 Feb 2022 09:48:14 -0800 Subject: [PATCH 053/316] [lldb] Use mangled symbol name to look for __asan::AsanDie() After aed965d we no longer demangle full symbol names while indexing the symbol table which means we have to use the mangled name instead of the demangled name to find the symbol for __asan::AsanDie(). This fixes the following two tests: lldb-api :: functionalities/asan/TestMemoryHistory.py lldb-api :: functionalities/asan/TestReportData.py (cherry picked from commit ef3fade14b32c20e0a35b8fca30e7d2f20e0c983) --- .../InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Plugins/InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp b/lldb/source/Plugins/InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp index 8d8b5c68e41b3..33b2b5dd51559 100644 --- a/lldb/source/Plugins/InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp +++ b/lldb/source/Plugins/InstrumentationRuntime/ASan/InstrumentationRuntimeASan.cpp @@ -281,7 +281,7 @@ void InstrumentationRuntimeASan::Activate() { if (!process_sp) return; - ConstString symbol_name("__asan::AsanDie()"); + ConstString symbol_name("_ZN6__asanL7AsanDieEv"); const Symbol *symbol = GetRuntimeModuleSP()->FindFirstSymbolWithNameAndType( symbol_name, eSymbolTypeCode); From 39e9a64cf5847935c2ba0099f4bf39945d8ee19b Mon Sep 17 00:00:00 2001 From: ksyx <18738953+ksyx@users.noreply.github.com> Date: Sun, 6 Feb 2022 02:18:04 +0000 Subject: [PATCH 054/316] [clang-format] Fix DefSeparator empty line issues - Add or remove empty lines surrounding union blocks. - Fixes https://github.com/llvm/llvm-project/issues/53229, in which keywords like class and struct in a line ending with left brace or whose next line is left brace only, will be falsely recognized as definition line, causing extra empty lines inserted surrounding blocks with no need to be formatted. Reviewed By: MyDeveloperDay, curdeius, HazardyKnusperkeks, owenpan Differential Revision: https://reviews.llvm.org/D119067 (cherry picked from commit a70549ae43dfa551f3eacdfa7a7f2c0df073be8e) --- clang/lib/Format/DefinitionBlockSeparator.cpp | 49 ++++++++++++------- .../Format/DefinitionBlockSeparatorTest.cpp | 22 +++++++++ 2 files changed, 54 insertions(+), 17 deletions(-) diff --git a/clang/lib/Format/DefinitionBlockSeparator.cpp b/clang/lib/Format/DefinitionBlockSeparator.cpp index 827564357f788..cfb019a471dce 100644 --- a/clang/lib/Format/DefinitionBlockSeparator.cpp +++ b/clang/lib/Format/DefinitionBlockSeparator.cpp @@ -35,19 +35,31 @@ void DefinitionBlockSeparator::separateBlocks( const bool IsNeverStyle = Style.SeparateDefinitionBlocks == FormatStyle::SDS_Never; const AdditionalKeywords &ExtraKeywords = Tokens.getKeywords(); - auto LikelyDefinition = [this, ExtraKeywords](const AnnotatedLine *Line, - bool ExcludeEnum = false) { + auto GetBracketLevelChange = [](const FormatToken *Tok) { + if (Tok->isOneOf(tok::l_brace, tok::l_paren, tok::l_square)) + return 1; + if (Tok->isOneOf(tok::r_brace, tok::r_paren, tok::r_square)) + return -1; + return 0; + }; + auto LikelyDefinition = [&](const AnnotatedLine *Line, + bool ExcludeEnum = false) { if ((Line->MightBeFunctionDecl && Line->mightBeFunctionDefinition()) || Line->startsWithNamespace()) return true; - FormatToken *CurrentToken = Line->First; - while (CurrentToken) { - if (CurrentToken->isOneOf(tok::kw_class, tok::kw_struct) || - (Style.isJavaScript() && CurrentToken->is(ExtraKeywords.kw_function))) - return true; - if (!ExcludeEnum && CurrentToken->is(tok::kw_enum)) - return true; - CurrentToken = CurrentToken->Next; + int BracketLevel = 0; + for (const FormatToken *CurrentToken = Line->First; CurrentToken; + CurrentToken = CurrentToken->Next) { + if (BracketLevel == 0) { + if ((CurrentToken->isOneOf(tok::kw_class, tok::kw_struct, + tok::kw_union) || + (Style.isJavaScript() && + CurrentToken->is(ExtraKeywords.kw_function)))) + return true; + if (!ExcludeEnum && CurrentToken->is(tok::kw_enum)) + return true; + } + BracketLevel += GetBracketLevelChange(CurrentToken); } return false; }; @@ -102,14 +114,17 @@ void DefinitionBlockSeparator::separateBlocks( IsPPConditional(OpeningLineIndex - 1); }; const auto HasEnumOnLine = [&]() { - FormatToken *CurrentToken = CurrentLine->First; bool FoundEnumKeyword = false; - while (CurrentToken) { - if (CurrentToken->is(tok::kw_enum)) - FoundEnumKeyword = true; - else if (FoundEnumKeyword && CurrentToken->is(tok::l_brace)) - return true; - CurrentToken = CurrentToken->Next; + int BracketLevel = 0; + for (const FormatToken *CurrentToken = CurrentLine->First; CurrentToken; + CurrentToken = CurrentToken->Next) { + if (BracketLevel == 0) { + if (CurrentToken->is(tok::kw_enum)) + FoundEnumKeyword = true; + else if (FoundEnumKeyword && CurrentToken->is(tok::l_brace)) + return true; + } + BracketLevel += GetBracketLevelChange(CurrentToken); } return FoundEnumKeyword && I + 1 < Lines.size() && Lines[I + 1]->First->is(tok::l_brace); diff --git a/clang/unittests/Format/DefinitionBlockSeparatorTest.cpp b/clang/unittests/Format/DefinitionBlockSeparatorTest.cpp index 4cbae0f55b036..582b62e445df9 100644 --- a/clang/unittests/Format/DefinitionBlockSeparatorTest.cpp +++ b/clang/unittests/Format/DefinitionBlockSeparatorTest.cpp @@ -109,6 +109,15 @@ TEST_F(DefinitionBlockSeparatorTest, Basic) { "};", Style); + verifyFormat("union foo {\n" + " int i, j;\n" + "};\n" + "\n" + "union bar {\n" + " int j, k;\n" + "};", + Style); + verifyFormat("class foo {\n" " int i, j;\n" "};\n" @@ -311,6 +320,9 @@ TEST_F(DefinitionBlockSeparatorTest, Always) { "int bar3(int j, int k, const enum Bar b) {\n" " // A comment\n" " int r = j % k;\n" + " if (struct S = getS()) {\n" + " // if condition\n" + " }\n" " return r;\n" "}\n"; std::string Postfix = "\n" @@ -364,6 +376,9 @@ TEST_F(DefinitionBlockSeparatorTest, Never) { "int bar3(int j, int k, const enum Bar b) {\n" " // A comment\n" " int r = j % k;\n" + " if (struct S = getS()) {\n" + " // if condition\n" + " }\n" " return r;\n" "}\n" "} // namespace"; @@ -425,6 +440,10 @@ TEST_F(DefinitionBlockSeparatorTest, OpeningBracketOwnsLine) { "{\n" " // A comment\n" " int r = j % k;\n" + " if (struct S = getS())\n" + " {\n" + " // if condition\n" + " }\n" " return r;\n" "}\n" "} // namespace NS", @@ -473,6 +492,9 @@ TEST_F(DefinitionBlockSeparatorTest, Leave) { "int bar3(int j, int k, const enum Bar b) {\n" " // A comment\n" " int r = j % k;\n" + " if (struct S = getS()) {\n" + " // if condition\n" + " }\n" " return r;\n" "}\n" "} // namespace"; From 26cc50aba7176996d50780a5f7957d7822065ae9 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 3 Feb 2022 16:41:47 -0500 Subject: [PATCH 055/316] [OpenMP] Add Cuda path to linker wrapper tool The linker wrapper tool uses the 'nvlink' and 'ptxas' binaries to link and assemble device files. Previously we searched for this using the binaries in the user's path. This didn't work in cases where the user passed in a specific Cuda path to Clang. This patch changes the linker wrapper to accept an argument for the Cuda path we can get from Clang. This should fix #53573. Reviewed By: tianshilei1992 Differential Revision: https://reviews.llvm.org/D118944 (cherry picked from commit 8cc4ca95b02bc5b5b668b3d537b45a6585575cba) --- clang/lib/Driver/ToolChains/Clang.cpp | 35 +++++++++++++------ .../ClangLinkerWrapper.cpp | 23 +++++++++--- 2 files changed, 43 insertions(+), 15 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 7aac977209eba..5b2984ea2496f 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -8148,11 +8148,25 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { + const Driver &D = getToolChain().getDriver(); + const llvm::Triple TheTriple = getToolChain().getTriple(); + auto OpenMPTCRange = C.getOffloadToolChains(); ArgStringList CmdArgs; - if (getToolChain().getDriver().isUsingLTO(/* IsOffload */ true)) { + // Pass the CUDA path to the linker wrapper tool. + for (auto &I : llvm::make_range(OpenMPTCRange.first, OpenMPTCRange.second)) { + const ToolChain *TC = I.second; + if (TC->getTriple().isNVPTX()) { + CudaInstallationDetector CudaInstallation(D, TheTriple, Args); + if (CudaInstallation.isValid()) + CmdArgs.push_back(Args.MakeArgString( + "--cuda-path=" + CudaInstallation.getInstallPath())); + break; + } + } + + if (D.isUsingLTO(/* IsOffload */ true)) { // Pass in target features for each toolchain. - auto OpenMPTCRange = C.getOffloadToolChains(); for (auto &I : llvm::make_range(OpenMPTCRange.first, OpenMPTCRange.second)) { const ToolChain *TC = I.second; @@ -8165,9 +8179,10 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, } // Pass in the bitcode library to be linked during LTO. - for (auto &I : llvm::make_range(OpenMPTCRange.first, OpenMPTCRange.second)) { + for (auto &I : + llvm::make_range(OpenMPTCRange.first, OpenMPTCRange.second)) { const ToolChain *TC = I.second; - const Driver &D = TC->getDriver(); + const Driver &TCDriver = TC->getDriver(); const ArgList &TCArgs = C.getArgsForToolChain(TC, "", Action::OFK_OpenMP); StringRef Arch = TCArgs.getLastArgValue(options::OPT_march_EQ); @@ -8182,7 +8197,7 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, BitcodeSuffix += Arch; ArgStringList BitcodeLibrary; - addOpenMPDeviceRTL(D, TCArgs, BitcodeLibrary, BitcodeSuffix, + addOpenMPDeviceRTL(TCDriver, TCArgs, BitcodeLibrary, BitcodeSuffix, TC->getTriple()); if (!BitcodeLibrary.empty()) @@ -8210,12 +8225,8 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, } } - // Construct the link job so we can wrap around it. - Linker->ConstructJob(C, JA, Output, Inputs, Args, LinkingOutput); - const auto &LinkCommand = C.getJobs().getJobs().back(); - CmdArgs.push_back("-host-triple"); - CmdArgs.push_back(Args.MakeArgString(getToolChain().getTripleString())); + CmdArgs.push_back(Args.MakeArgString(TheTriple.getTriple())); if (Args.hasArg(options::OPT_v)) CmdArgs.push_back("-v"); @@ -8246,6 +8257,10 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, if (Args.getLastArg(options::OPT_save_temps_EQ)) CmdArgs.push_back("-save-temps"); + // Construct the link job so we can wrap around it. + Linker->ConstructJob(C, JA, Output, Inputs, Args, LinkingOutput); + const auto &LinkCommand = C.getJobs().getJobs().back(); + // Add the linker arguments to be forwarded by the wrapper. CmdArgs.push_back("-linker-path"); CmdArgs.push_back(LinkCommand->getExecutable()); diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 4ec4d6b134049..de0af187731d3 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -99,8 +99,8 @@ static cl::opt static cl::list PtxasArgs("ptxas-args", cl::ZeroOrMore, - cl::desc("Argument to pass to the ptxas invocation"), - cl::cat(ClangLinkerWrapperCategory)); + cl::desc("Argument to pass to the ptxas invocation"), + cl::cat(ClangLinkerWrapperCategory)); static cl::opt Verbose("v", cl::ZeroOrMore, cl::desc("Verbose output from tools"), @@ -118,6 +118,10 @@ static cl::opt SaveTemps("save-temps", cl::ZeroOrMore, cl::desc("Save intermediary results."), cl::cat(ClangLinkerWrapperCategory)); +static cl::opt CudaPath("cuda-path", cl::ZeroOrMore, + cl::desc("Save intermediary results."), + cl::cat(ClangLinkerWrapperCategory)); + // Do not parse linker options. static cl::list HostLinkerArgs(cl::Positional, @@ -129,6 +133,9 @@ static const char *LinkerExecutable; /// Filename of the executable being created. static StringRef ExecutableName; +/// Binary path for the CUDA installation. +static std::string CudaBinaryPath; + /// Temporary files created by the linker wrapper. static SmallVector TempFiles; @@ -507,9 +514,9 @@ extractFromBuffer(std::unique_ptr Buffer, namespace nvptx { Expected assemble(StringRef InputFile, Triple TheTriple, StringRef Arch) { - // NVPTX uses the nvlink binary to link device object files. + // NVPTX uses the ptxas binary to create device object files. ErrorOr PtxasPath = - sys::findProgramByName("ptxas", sys::path::parent_path(LinkerExecutable)); + sys::findProgramByName("ptxas", {CudaBinaryPath}); if (!PtxasPath) PtxasPath = sys::findProgramByName("ptxas"); if (!PtxasPath) @@ -554,7 +561,10 @@ Expected assemble(StringRef InputFile, Triple TheTriple, Expected link(ArrayRef InputFiles, Triple TheTriple, StringRef Arch) { // NVPTX uses the nvlink binary to link device object files. - ErrorOr NvlinkPath = sys::findProgramByName("nvlink"); + ErrorOr NvlinkPath = + sys::findProgramByName("nvlink", {CudaBinaryPath}); + if (!NvlinkPath) + NvlinkPath = sys::findProgramByName("nvlink"); if (!NvlinkPath) return createStringError(NvlinkPath.getError(), "Unable to find 'nvlink' in path"); @@ -1097,6 +1107,9 @@ int main(int argc, const char **argv) { return EXIT_FAILURE; }; + if (!CudaPath.empty()) + CudaBinaryPath = CudaPath + "/bin"; + ExecutableName = *(llvm::find(HostLinkerArgs, "-o") + 1); SmallVector LinkerArgs; for (const std::string &Arg : HostLinkerArgs) From 3e2d79e2a27dce5f8ba1d33bbc1344b9d24f2b5a Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 7 Feb 2022 16:41:35 -0500 Subject: [PATCH 056/316] [Libomptarget] Replace Value RAII with default value This patch replaces the ValueRAII pointer with a default 'nullptr' value. Previously this was initialized as a reference to an existing variable. The use of this variable caused overhead as the compiler could not look through the uses and determine that it was unused if 'Active' was not set. Because of this accesses to the variable would be left in the runtime once compiled. Fixes #53641 Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D119187 (cherry picked from commit d28051c4ab44141d7c52902de500dfe1293d3de2) --- openmp/libomptarget/DeviceRTL/include/State.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openmp/libomptarget/DeviceRTL/include/State.h b/openmp/libomptarget/DeviceRTL/include/State.h index 3365b054b4720..2f9cbd4c9ca6e 100644 --- a/openmp/libomptarget/DeviceRTL/include/State.h +++ b/openmp/libomptarget/DeviceRTL/include/State.h @@ -124,20 +124,21 @@ template struct PtrValue { template struct ValueRAII { ValueRAII(VTy &V, Ty NewValue, Ty OldValue, bool Active, IdentTy *Ident) - : Ptr(Active ? V.lookup(/* IsReadonly */ false, Ident) : Val), + : Ptr(Active ? &V.lookup(/* IsReadonly */ false, Ident) : nullptr), Val(OldValue), Active(Active) { if (!Active) return; - ASSERT(Ptr == OldValue && "ValueRAII initialization with wrong old value!"); - Ptr = NewValue; + ASSERT(*Ptr == OldValue && + "ValueRAII initialization with wrong old value!"); + *Ptr = NewValue; } ~ValueRAII() { if (Active) - Ptr = Val; + *Ptr = Val; } private: - Ty &Ptr; + Ty *Ptr; Ty Val; bool Active; }; From 7cfe202a679a0c3cd5aa71ec2497885ef596ea7b Mon Sep 17 00:00:00 2001 From: Florian Weimer Date: Tue, 8 Feb 2022 12:46:41 -0800 Subject: [PATCH 057/316] [sanitizer] Use _thread_db_sizeof_pthread to obtain struct pthread size This symbol has been exported (as an internal GLIBC_PRIVATE symbol) from libc.so.6 starting with glibc 2.34. glibc uses it internally for its libthread_db implementation to enable thread debugging on GDB, so it is unlikely to go away for now. Fixes #52989. Reviewed By: #sanitizers, MaskRay, vitalybuka Differential Revision: https://reviews.llvm.org/D119007 (cherry picked from commit ef14b78d9a144ba81ba02083fe21eb286a88732b) --- .../sanitizer_linux_libcdep.cpp | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp index b025a5e4fb644..eeb157d1c4280 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp @@ -220,10 +220,8 @@ void InitTlsSize() { } // sizeof(struct pthread) from glibc. static atomic_uintptr_t thread_descriptor_size; -uptr ThreadDescriptorSize() { - uptr val = atomic_load_relaxed(&thread_descriptor_size); - if (val) - return val; +static uptr ThreadDescriptorSizeFallback() { + uptr val = 0; #if defined(__x86_64__) || defined(__i386__) || defined(__arm__) int major; int minor; @@ -285,8 +283,21 @@ uptr ThreadDescriptorSize() { #elif defined(__powerpc64__) val = 1776; // from glibc.ppc64le 2.20-8.fc21 #endif + return val; +} + +uptr ThreadDescriptorSize() { + uptr val = atomic_load_relaxed(&thread_descriptor_size); if (val) - atomic_store_relaxed(&thread_descriptor_size, val); + return val; + // _thread_db_sizeof_pthread is a GLIBC_PRIVATE symbol that is exported in + // glibc 2.34 and later. + if (unsigned *psizeof = static_cast( + dlsym(RTLD_DEFAULT, "_thread_db_sizeof_pthread"))) + val = *psizeof; + if (!val) + val = ThreadDescriptorSizeFallback(); + atomic_store_relaxed(&thread_descriptor_size, val); return val; } From 0ad6c094176e3978b3042b2f0860f273b87e7a85 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 8 Feb 2022 14:48:34 -0800 Subject: [PATCH 058/316] [sanitizer] Guard the whole ThreadDescriptorSize block with #if !SANITIZER_GO after D119007 The SANITIZER_GO code path reports an undefined symbol error for dlsym. ``` FAILED: projects/compiler-rt/lib/tsan/rtl/CMakeFiles/GotsanRuntimeCheck /tmp/RelA/projects/compiler-rt/lib/tsan/rtl/CMakeFiles/GotsanRuntimeCheck ``` (cherry picked from commit f0cdacd99bd41dbd778099dfe303ba92660826b3) --- .../lib/sanitizer_common/sanitizer_linux_libcdep.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp index eeb157d1c4280..4ccd2e8281080 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp @@ -216,7 +216,7 @@ void InitTlsSize() { } // On glibc x86_64, ThreadDescriptorSize() needs to be precise due to the usage // of g_tls_size. On other targets, ThreadDescriptorSize() is only used by lsan // to get the pointer to thread-specific data keys in the thread control block. -#if (SANITIZER_FREEBSD || SANITIZER_LINUX) && !SANITIZER_ANDROID +#if (SANITIZER_FREEBSD || SANITIZER_LINUX) && !SANITIZER_ANDROID && !SANITIZER_GO // sizeof(struct pthread) from glibc. static atomic_uintptr_t thread_descriptor_size; @@ -319,7 +319,6 @@ static uptr TlsPreTcbSize() { } #endif -#if !SANITIZER_GO namespace { struct TlsBlock { uptr begin, end, align; @@ -407,9 +406,8 @@ __attribute__((unused)) static void GetStaticTlsBoundary(uptr *addr, uptr *size, *addr = ranges[l].begin; *size = ranges[r - 1].end - ranges[l].begin; } -#endif // !SANITIZER_GO #endif // (x86_64 || i386 || mips || ...) && (SANITIZER_FREEBSD || - // SANITIZER_LINUX) && !SANITIZER_ANDROID + // SANITIZER_LINUX) && !SANITIZER_ANDROID && !SANITIZER_GO #if SANITIZER_NETBSD static struct tls_tcb * ThreadSelfTlsTcb() { From 61c8cf97479f37c63724f63fd4c727cd2b433ae9 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Mon, 7 Feb 2022 19:39:19 -0600 Subject: [PATCH 059/316] [Attributor][FIX] Do not use assumed information for UB detection The helper `Attributor::checkForAllReturnedValuesAndReturnInsts` simplifies the returned value optimistically. In `AAUndefinedBehavior` we cannot use such optimistic values when deducing UB. As a result, we assumed UB for the return value of a function because we initially (=optimistically) thought the function return is `undef`. While we later adjusted this properly, the `AAUndefinedBehavior` was under the impression the return value is "known" (=fix) and could never change. To correct this we use `Attributor::checkForAllInstructions` and then manually to perform simplification of the return value, only allowing known values to be used. This actually matches the other UB deductions. Fixes #53647 (cherry picked from commit dd101c808b85aad8edb48ab6d5f754cc6527fcff) --- .../Transforms/IPO/AttributorAttributes.cpp | 69 +++++++++---------- .../Attributor/undefined_behavior.ll | 37 +++++++++- 2 files changed, 69 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 2d88e329e0931..db2ba91bea589 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -2691,40 +2691,38 @@ struct AAUndefinedBehaviorImpl : public AAUndefinedBehavior { return true; }; - auto InspectReturnInstForUB = - [&](Value &V, const SmallSetVector RetInsts) { - // Check if a return instruction always cause UB or not - // Note: It is guaranteed that the returned position of the anchor - // scope has noundef attribute when this is called. - // We also ensure the return position is not "assumed dead" - // because the returned value was then potentially simplified to - // `undef` in AAReturnedValues without removing the `noundef` - // attribute yet. - - // When the returned position has noundef attriubte, UB occur in the - // following cases. - // (1) Returned value is known to be undef. - // (2) The value is known to be a null pointer and the returned - // position has nonnull attribute (because the returned value is - // poison). - bool FoundUB = false; - if (isa(V)) { - FoundUB = true; - } else { - if (isa(V)) { - auto &NonNullAA = A.getAAFor( - *this, IRPosition::returned(*getAnchorScope()), - DepClassTy::NONE); - if (NonNullAA.isKnownNonNull()) - FoundUB = true; - } - } + auto InspectReturnInstForUB = [&](Instruction &I) { + auto &RI = cast(I); + // Either we stopped and the appropriate action was taken, + // or we got back a simplified return value to continue. + Optional SimplifiedRetValue = + stopOnUndefOrAssumed(A, RI.getReturnValue(), &I); + if (!SimplifiedRetValue.hasValue() || !SimplifiedRetValue.getValue()) + return true; - if (FoundUB) - for (ReturnInst *RI : RetInsts) - KnownUBInsts.insert(RI); - return true; - }; + // Check if a return instruction always cause UB or not + // Note: It is guaranteed that the returned position of the anchor + // scope has noundef attribute when this is called. + // We also ensure the return position is not "assumed dead" + // because the returned value was then potentially simplified to + // `undef` in AAReturnedValues without removing the `noundef` + // attribute yet. + + // When the returned position has noundef attriubte, UB occurs in the + // following cases. + // (1) Returned value is known to be undef. + // (2) The value is known to be a null pointer and the returned + // position has nonnull attribute (because the returned value is + // poison). + if (isa(*SimplifiedRetValue)) { + auto &NonNullAA = A.getAAFor( + *this, IRPosition::returned(*getAnchorScope()), DepClassTy::NONE); + if (NonNullAA.isKnownNonNull()) + KnownUBInsts.insert(&I); + } + + return true; + }; bool UsedAssumedInformation = false; A.checkForAllInstructions(InspectMemAccessInstForUB, *this, @@ -2747,8 +2745,9 @@ struct AAUndefinedBehaviorImpl : public AAUndefinedBehavior { auto &RetPosNoUndefAA = A.getAAFor(*this, ReturnIRP, DepClassTy::NONE); if (RetPosNoUndefAA.isKnownNoUndef()) - A.checkForAllReturnedValuesAndReturnInsts(InspectReturnInstForUB, - *this); + A.checkForAllInstructions(InspectReturnInstForUB, *this, + {Instruction::Ret}, UsedAssumedInformation, + /* CheckBBLivenessOnly */ true); } } diff --git a/llvm/test/Transforms/Attributor/undefined_behavior.ll b/llvm/test/Transforms/Attributor/undefined_behavior.ll index bb5a7ef19bbef..40d6340c185b0 100644 --- a/llvm/test/Transforms/Attributor/undefined_behavior.ll +++ b/llvm/test/Transforms/Attributor/undefined_behavior.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -793,6 +793,39 @@ define i32* @violate_noundef_pointer() { %ret = call i32* @argument_noundef2(i32* undef) ret i32* %ret } + +define internal noundef i32 @assumed_undef_is_ok(i1 %c, i32 %arg) { +; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@assumed_undef_is_ok +; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR0]] { +; IS__CGSCC____-NEXT: br i1 [[C]], label [[REC:%.*]], label [[RET:%.*]] +; IS__CGSCC____: rec: +; IS__CGSCC____-NEXT: br label [[RET]] +; IS__CGSCC____: ret: +; IS__CGSCC____-NEXT: ret i32 undef +; + %stack = alloca i32 + store i32 %arg, i32* %stack + br i1 %c, label %rec, label %ret +rec: + %call = call i32 @assumed_undef_is_ok(i1 false, i32 0) + store i32 %call, i32* %stack + br label %ret +ret: + %l = load i32, i32* %stack + ret i32 %l +} + +define noundef i32 @assumed_undef_is_ok_caller(i1 %c) { +; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK-LABEL: define {{[^@]+}}@assumed_undef_is_ok_caller +; CHECK-SAME: (i1 [[C:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: ret i32 0 +; + %call = call i32 @assumed_undef_is_ok(i1 %c, i32 undef) + ret i32 %call +} + ;. ; IS__TUNIT____: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ; IS__TUNIT____: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn } From f01051dd4edfa27cae33ea46648d9fea8536657b Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 8 Feb 2022 08:45:40 -0800 Subject: [PATCH 060/316] [Hexagon] Alter meaning of versionless -mhvx The documentation for the official (downstream) Qualcomm Hexagon Clang states that -mhvx sets the HVX version to be the same as the CPU version. The current implementation upstream would use the most recent versioned -mhvx= flag first (if present), then the CPU version. Change the upstream behavior to match the documented behavior of the downstream compiler. (cherry picked from commit 2ecda9ec9cc89b87ce2e56452229c9444beabf21) --- clang/lib/Driver/ToolChains/Hexagon.cpp | 34 +++++++++-------- clang/test/Driver/hexagon-hvx.c | 50 ++++++++++++------------- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp b/clang/lib/Driver/ToolChains/Hexagon.cpp index ba3040636604f..e772122f5ff5e 100644 --- a/clang/lib/Driver/ToolChains/Hexagon.cpp +++ b/clang/lib/Driver/ToolChains/Hexagon.cpp @@ -72,23 +72,25 @@ static void handleHVXTargetFeatures(const Driver &D, const ArgList &Args, (Cpu.back() == 'T' || Cpu.back() == 't' ? Cpu.drop_back(1) : Cpu).str(); HasHVX = false; - // Handle -mhvx, -mhvx=, -mno-hvx. If both present, -mhvx= wins over -mhvx. - auto argOrNull = [&Args](auto FlagOn, auto FlagOff) -> Arg* { - if (Arg *A = Args.getLastArg(FlagOn, FlagOff)) { - if (A->getOption().matches(FlagOn)) - return A; - } - return nullptr; - }; - - Arg *HvxBareA = - argOrNull(options::OPT_mhexagon_hvx, options::OPT_mno_hexagon_hvx); - Arg *HvxVerA = - argOrNull(options::OPT_mhexagon_hvx_EQ, options::OPT_mno_hexagon_hvx); + // Handle -mhvx, -mhvx=, -mno-hvx. If versioned and versionless flags + // are both present, the last one wins. + Arg *HvxEnablingArg = + Args.getLastArg(options::OPT_mhexagon_hvx, options::OPT_mhexagon_hvx_EQ, + options::OPT_mno_hexagon_hvx); + if (HvxEnablingArg) { + if (HvxEnablingArg->getOption().matches(options::OPT_mno_hexagon_hvx)) + HvxEnablingArg = nullptr; + } - if (Arg *A = HvxVerA ? HvxVerA : HvxBareA) { - if (A->getOption().matches(options::OPT_mhexagon_hvx_EQ)) - HvxVer = StringRef(A->getValue()).lower(); // lower produces std:string + if (HvxEnablingArg) { + // If -mhvx[=] was given, it takes precedence. + if (Arg *A = Args.getLastArg(options::OPT_mhexagon_hvx, + options::OPT_mhexagon_hvx_EQ)) { + // If the version was given, set HvxVer. Otherwise HvxVer + // will remain equal to the CPU version. + if (A->getOption().matches(options::OPT_mhexagon_hvx_EQ)) + HvxVer = StringRef(A->getValue()).lower(); + } HasHVX = true; Features.push_back(makeFeature(Twine("hvx") + HvxVer, true)); } else if (Arg *A = Args.getLastArg(options::OPT_mno_hexagon_hvx)) { diff --git a/clang/test/Driver/hexagon-hvx.c b/clang/test/Driver/hexagon-hvx.c index 10bb8fe9327f0..385774824cb0a 100644 --- a/clang/test/Driver/hexagon-hvx.c +++ b/clang/test/Driver/hexagon-hvx.c @@ -54,6 +54,23 @@ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V68 %s // RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v69 \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V69 %s +// Infer HVX version from CPU version: +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V60 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V62 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv65 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V65 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv66 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V66 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv67 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V67 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv67t -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V67 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv68 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V68 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv69 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V69 %s // Direct version flag with different CPU version: // RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v60 -mv62 \ @@ -73,19 +90,19 @@ // Direct version flag with different CPU version and versionless -mhvx: // RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v60 -mv62 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V60 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v62 -mv65 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V62 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v65 -mv66 -mhvx \ +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v62 -mv65 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V65 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v66 -mv67 -mhvx \ +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v65 -mv66 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V66 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v67 -mv68 -mhvx \ +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v66 -mv67 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V67 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v68 -mv69 -mhvx \ +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v67 -mv68 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V68 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v69 -mv60 -mhvx \ +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v68 -mv69 -mhvx \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V69 %s +// RUN: %clang -c %s -### -target hexagon-unknown-elf -mhvx=v69 -mv60 -mhvx \ +// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V60 %s // Direct version flag with different CPU version, versionless -mhvx // and -mno-hvx. The -mno-hvx cancels -mhvx=, versionless -mhvx wins: @@ -121,25 +138,6 @@ // RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx -mno-hvx -mhvx=v69 \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V69 %s -// Infer HVX version from CPU version: - -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv60 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V60 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv62 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V62 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv65 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V65 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv66 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V66 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv67 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V67 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv67t -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V67 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv68 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V68 %s -// RUN: %clang -c %s -### -target hexagon-unknown-elf -mv69 -mhvx \ -// RUN: 2>&1 | FileCheck -check-prefix=CHECK-HVX-V69 %s - // Infer HVX length from flag: // CHECK-HVX-L64: "-target-feature" "+hvx-length64b" From 4f624dd81687dcad957421ca6803e81a2262c4f4 Mon Sep 17 00:00:00 2001 From: Piotr Kubaj Date: Sun, 6 Feb 2022 01:13:42 +0800 Subject: [PATCH 061/316] [PowerPC] Fix SSE translation on FreeBSD This patch drops throws specifier in posix_memalign declaration because that's different between glibc and other libc, and Clang has a hack. Differential Revision: https://reviews.llvm.org/D117972 (cherry picked from commit f2f4080c10f4319adf75c660425911cd4e0e1843) --- clang/lib/Headers/ppc_wrappers/mm_malloc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Headers/ppc_wrappers/mm_malloc.h b/clang/lib/Headers/ppc_wrappers/mm_malloc.h index 86cf1a0f76180..b6bf22f928879 100644 --- a/clang/lib/Headers/ppc_wrappers/mm_malloc.h +++ b/clang/lib/Headers/ppc_wrappers/mm_malloc.h @@ -19,7 +19,7 @@ #ifndef __cplusplus extern int posix_memalign (void **, size_t, size_t); #else -extern "C" int posix_memalign (void **, size_t, size_t) throw (); +extern "C" int posix_memalign (void **, size_t, size_t); #endif static __inline void * From a2f583280e48d8673de63c2a9f208f7b534fad02 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 2 Feb 2022 08:01:23 -0500 Subject: [PATCH 062/316] [x86] invert a vector select IR canonicalization with a binop identity constant This is an intentionally limited/different form of D90113. That patch bravely tries to generalize folds where we pull a binop into the arms of a select: N0 + (Cond ? 0 : FVal) --> Cond ? N0 : (N0 + FVal) ...but it is not universally profitable. This is the inverse of IR canonicalization as discussed in D113442. We know that this transform is not entirely profitable even within x86, so we only handle x86 vector fadd/fsub as a 1st step. The intent is to prevent AVX512 regressions as mentioned in D113442. The plan is to port this to DAGCombiner (so it will eventually look more like D90113) and add more types/cases in pieces with many more tests to verify that we are seeing improvements. Differential Revision: https://reviews.llvm.org/D118644 (cherry picked from commit 6592bcecd4ffc03f72d23f81bcb8d51f8ebeb07d) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 80 +++++++++++++++++++ .../X86/avx512fp16-arith-intrinsics.ll | 4 +- llvm/test/CodeGen/X86/vector-bo-select.ll | 44 +++++----- 3 files changed, 102 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9afb885f582aa..6f1fe81955952 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -48920,6 +48920,83 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG, return DAG.getBitcast(VT, CFmul); } +/// This inverts a canonicalization in IR that replaces a variable select arm +/// with an identity constant. Codegen improves if we re-use the variable +/// operand rather than load a constant. This can also be converted into a +/// masked vector operation if the target supports it. +static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, + bool ShouldCommuteOperands) { + // Match a select as operand 1. The identity constant that we are looking for + // is only valid as operand 1 of a non-commutative binop. + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + if (ShouldCommuteOperands) + std::swap(N0, N1); + + // TODO: Should this apply to scalar select too? + if (!N1.hasOneUse() || N1.getOpcode() != ISD::VSELECT) + return SDValue(); + + unsigned Opcode = N->getOpcode(); + EVT VT = N->getValueType(0); + SDValue Cond = N1.getOperand(0); + SDValue TVal = N1.getOperand(1); + SDValue FVal = N1.getOperand(2); + + // TODO: This (and possibly the entire function) belongs in a + // target-independent location with target hooks. + // TODO: The cases should match with IR's ConstantExpr::getBinOpIdentity(). + // TODO: With fast-math (NSZ), allow the opposite-sign form of zero? + auto isIdentityConstantForOpcode = [](unsigned Opcode, SDValue V) { + if (ConstantFPSDNode *C = isConstOrConstSplatFP(V)) { + switch (Opcode) { + case ISD::FADD: // X + -0.0 --> X + return C->isZero() && C->isNegative(); + case ISD::FSUB: // X - 0.0 --> X + return C->isZero() && !C->isNegative(); + } + } + return false; + }; + + // This transform increases uses of N0, so freeze it to be safe. + // binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal) + if (isIdentityConstantForOpcode(Opcode, TVal)) { + SDValue F0 = DAG.getFreeze(N0); + SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, FVal, N->getFlags()); + return DAG.getSelect(SDLoc(N), VT, Cond, F0, NewBO); + } + // binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0 + if (isIdentityConstantForOpcode(Opcode, FVal)) { + SDValue F0 = DAG.getFreeze(N0); + SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, TVal, N->getFlags()); + return DAG.getSelect(SDLoc(N), VT, Cond, NewBO, F0); + } + + return SDValue(); +} + +static SDValue combineBinopWithSelect(SDNode *N, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { + // TODO: This is too general. There are cases where pre-AVX512 codegen would + // benefit. The transform may also be profitable for scalar code. + if (!Subtarget.hasAVX512()) + return SDValue(); + + if (!Subtarget.hasVLX() && !N->getValueType(0).is512BitVector()) + return SDValue(); + + if (SDValue Sel = foldSelectWithIdentityConstant(N, DAG, false)) + return Sel; + + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (TLI.isCommutativeBinOp(N->getOpcode())) + if (SDValue Sel = foldSelectWithIdentityConstant(N, DAG, true)) + return Sel; + + return SDValue(); +} + /// Do target-specific dag combines on floating-point adds/subs. static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget) { @@ -48929,6 +49006,9 @@ static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG, if (SDValue COp = combineFaddCFmul(N, DAG, Subtarget)) return COp; + if (SDValue Sel = combineBinopWithSelect(N, DAG, Subtarget)) + return Sel; + return SDValue(); } diff --git a/llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll b/llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll index 8148585f8d793..d94da4a94e977 100644 --- a/llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll @@ -83,8 +83,8 @@ define <32 x half> @test_int_x86_avx512fp16_maskz_sub_ph_512(<32 x half> %src, < ; CHECK: # %bb.0: ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vsubph %zmm2, %zmm1, %zmm0 {%k1} {z} -; CHECK-NEXT: vsubph (%rsi), %zmm1, %zmm1 {%k1} {z} -; CHECK-NEXT: vsubph %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: vsubph (%rsi), %zmm1, %zmm1 +; CHECK-NEXT: vsubph %zmm1, %zmm0, %zmm0 {%k1} ; CHECK-NEXT: retq %mask = bitcast i32 %msk to <32 x i1> %val = load <32 x half>, <32 x half>* %ptr diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 9cc0761905ef8..93777915b1b88 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -27,9 +27,8 @@ define <4 x float> @fadd_v4f32(<4 x i1> %b, <4 x float> noundef %x, <4 x float> ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] -; AVX512VL-NEXT: vmovaps %xmm2, %xmm0 {%k1} -; AVX512VL-NEXT: vaddps %xmm0, %xmm1, %xmm0 +; AVX512VL-NEXT: vaddps %xmm2, %xmm1, %xmm1 {%k1} +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 ; AVX512VL-NEXT: retq %s = select <4 x i1> %b, <4 x float> %y, <4 x float> %r = fadd <4 x float> %x, %s @@ -62,9 +61,8 @@ define <8 x float> @fadd_v8f32_commute(<8 x i1> %b, <8 x float> noundef %x, <8 x ; AVX512VL-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512VL-NEXT: vpslld $31, %ymm0, %ymm0 ; AVX512VL-NEXT: vptestmd %ymm0, %ymm0, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] -; AVX512VL-NEXT: vmovaps %ymm2, %ymm0 {%k1} -; AVX512VL-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; AVX512VL-NEXT: vaddps %ymm2, %ymm1, %ymm1 {%k1} +; AVX512VL-NEXT: vmovaps %ymm1, %ymm0 ; AVX512VL-NEXT: retq %s = select <8 x i1> %b, <8 x float> %y, <8 x float> %r = fadd <8 x float> %s, %x @@ -92,8 +90,8 @@ define <16 x float> @fadd_v16f32_swap(<16 x i1> %b, <16 x float> noundef %x, <16 ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vbroadcastss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2 {%k1} ; AVX512-NEXT: vaddps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> , <16 x float> %y %r = fadd <16 x float> %x, %s @@ -121,8 +119,8 @@ define <16 x float> @fadd_v16f32_commute_swap(<16 x i1> %b, <16 x float> noundef ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vbroadcastss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2 {%k1} -; AVX512-NEXT: vaddps %zmm1, %zmm2, %zmm0 +; AVX512-NEXT: vaddps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> , <16 x float> %y %r = fadd <16 x float> %s, %x @@ -152,14 +150,16 @@ define <4 x float> @fsub_v4f32(<4 x i1> %b, <4 x float> noundef %x, <4 x float> ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512VL-NEXT: vmovaps %xmm2, %xmm0 {%k1} {z} -; AVX512VL-NEXT: vsubps %xmm0, %xmm1, %xmm0 +; AVX512VL-NEXT: vsubps %xmm2, %xmm1, %xmm1 {%k1} +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 ; AVX512VL-NEXT: retq %s = select <4 x i1> %b, <4 x float> %y, <4 x float> zeroinitializer %r = fsub <4 x float> %x, %s ret <4 x float> %r } +; negative test - fsub is not commutative; there is no identity constant for operand 0 + define <8 x float> @fsub_v8f32_commute(<8 x i1> %b, <8 x float> noundef %x, <8 x float> noundef %y) { ; AVX2-LABEL: fsub_v8f32_commute: ; AVX2: # %bb.0: @@ -214,15 +214,17 @@ define <16 x float> @fsub_v16f32_swap(<16 x i1> %b, <16 x float> noundef %x, <16 ; AVX512: # %bb.0: ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 -; AVX512-NEXT: vptestnmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vmovaps %zmm2, %zmm0 {%k1} {z} -; AVX512-NEXT: vsubps %zmm0, %zmm1, %zmm0 +; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 +; AVX512-NEXT: vsubps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> zeroinitializer, <16 x float> %y %r = fsub <16 x float> %x, %s ret <16 x float> %r } +; negative test - fsub is not commutative; there is no identity constant for operand 0 + define <16 x float> @fsub_v16f32_commute_swap(<16 x i1> %b, <16 x float> noundef %x, <16 x float> noundef %y) { ; AVX2-LABEL: fsub_v16f32_commute_swap: ; AVX2: # %bb.0: @@ -570,9 +572,7 @@ define <8 x float> @fadd_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> nou ; AVX512VL-LABEL: fadd_v8f32_cast_cond: ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: kmovw %edi, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] -; AVX512VL-NEXT: vmovaps %ymm1, %ymm2 {%k1} -; AVX512VL-NEXT: vaddps %ymm2, %ymm0, %ymm0 +; AVX512VL-NEXT: vaddps %ymm1, %ymm0, %ymm0 {%k1} ; AVX512VL-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x float> %y, <8 x float> @@ -636,9 +636,7 @@ define <8 x double> @fadd_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> n ; AVX512-LABEL: fadd_v8f64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vbroadcastsd {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] -; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1} -; AVX512-NEXT: vaddpd %zmm2, %zmm0, %zmm0 +; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0 {%k1} ; AVX512-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x double> %y, <8 x double> @@ -709,8 +707,7 @@ define <8 x float> @fsub_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> nou ; AVX512VL-LABEL: fsub_v8f32_cast_cond: ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: kmovw %edi, %k1 -; AVX512VL-NEXT: vmovaps %ymm1, %ymm1 {%k1} {z} -; AVX512VL-NEXT: vsubps %ymm1, %ymm0, %ymm0 +; AVX512VL-NEXT: vsubps %ymm1, %ymm0, %ymm0 {%k1} ; AVX512VL-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x float> %y, <8 x float> zeroinitializer @@ -775,8 +772,7 @@ define <8 x double> @fsub_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> n ; AVX512-LABEL: fsub_v8f64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vmovapd %zmm1, %zmm1 {%k1} {z} -; AVX512-NEXT: vsubpd %zmm1, %zmm0, %zmm0 +; AVX512-NEXT: vsubpd %zmm1, %zmm0, %zmm0 {%k1} ; AVX512-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x double> %y, <8 x double> zeroinitializer From 7607a39e9388b32ca90414ada56ce687b2272be4 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 8 Feb 2022 21:45:55 -0800 Subject: [PATCH 063/316] [ELF] --warn-backrefs: suppress warnings for backward references within the archive (cherry picked from commit 99580e29d821beeaf75345deb3e4cc2c6808bfc0) --- lld/ELF/Driver.cpp | 32 +++++++++++++++++++------------- lld/test/ELF/warn-backrefs.s | 2 ++ 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index 406571e4e9fd5..ca56f5ee0f10f 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -235,22 +235,28 @@ void LinkerDriver::addFile(StringRef path, bool withLOption) { // user is attempting LTO and using a default ar command that doesn't // understand the LLVM bitcode file. Treat the archive as a group of lazy // object files. - if (!file->isEmpty() && !file->hasSymbolTable()) { - for (const std::pair &p : - getArchiveMembers(mbref)) { - auto magic = identify_magic(p.first.getBuffer()); - if (magic == file_magic::bitcode || - magic == file_magic::elf_relocatable) - files.push_back(createLazyFile(p.first, path, p.second)); - else - error(path + ": archive member '" + p.first.getBufferIdentifier() + - "' is neither ET_REL nor LLVM bitcode"); - } + if (file->isEmpty() || file->hasSymbolTable()) { + // Handle the regular case. + files.push_back(make(std::move(file))); return; } - // Handle the regular case. - files.push_back(make(std::move(file))); + // All files within the archive get the same group ID to allow mutual + // references for --warn-backrefs. + bool saved = InputFile::isInGroup; + InputFile::isInGroup = true; + for (const std::pair &p : + getArchiveMembers(mbref)) { + auto magic = identify_magic(p.first.getBuffer()); + if (magic == file_magic::bitcode || magic == file_magic::elf_relocatable) + files.push_back(createLazyFile(p.first, path, p.second)); + else + error(path + ": archive member '" + p.first.getBufferIdentifier() + + "' is neither ET_REL nor LLVM bitcode"); + } + InputFile::isInGroup = saved; + if (!saved) + ++InputFile::nextGroupId; return; } case file_magic::elf_shared_object: diff --git a/lld/test/ELF/warn-backrefs.s b/lld/test/ELF/warn-backrefs.s index a6866869054a4..907f042c0e818 100644 --- a/lld/test/ELF/warn-backrefs.s +++ b/lld/test/ELF/warn-backrefs.s @@ -63,6 +63,8 @@ # RUN: echo '.globl bar; bar:' | llvm-mc -filetype=obj -triple=x86_64 - -o %t3.o # RUN: echo '.globl foo; foo: call bar' | llvm-mc -filetype=obj -triple=x86_64 - -o %t4.o # RUN: ld.lld --fatal-warnings --warn-backrefs %t1.o --start-lib %t3.o %t4.o --end-lib -o /dev/null +# RUN: rm -f %t34.a && llvm-ar rcS %t34.a %t3.o %t4.o +# RUN: ld.lld --fatal-warnings --warn-backrefs %t1.o %t34.a -o /dev/null ## We don't report backward references to weak symbols as they can be overridden later. # RUN: echo '.weak foo; foo:' | llvm-mc -filetype=obj -triple=x86_64 - -o %tweak.o From be308cf4cda010ca04e064f77bd5df307903314f Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Wed, 2 Feb 2022 19:20:02 +0100 Subject: [PATCH 064/316] [clang][Sparc] Fix __builtin_extract_return_addr etc. While investigating the failures of `symbolize_pc.cpp` and `symbolize_pc_inline.cpp` on SPARC (both Solaris and Linux), I noticed that `__builtin_extract_return_addr` is a no-op in `clang` on all targets, while `gcc` has non-default implementations for arm, mips, s390, and sparc. This patch provides the SPARC implementation. For background see `SparcISelLowering.cpp` (`SparcTargetLowering::LowerReturn_32`), the SPARC psABI p.3-12, `%i7` and p.3-16/17, and SCD 2.4.1, p.3P-10, `%i7` and p.3P-15. Tested (after enabling the `sanitizer_common` tests on SPARC) on `sparcv9-sun-solaris2.11`. Differential Revision: https://reviews.llvm.org/D91607 (cherry picked from commit efdd0a29b7eb6f3b6ca3fe9182a6c1085806c73a) --- clang/lib/CodeGen/TargetInfo.cpp | 34 +++++++++++++++++++++++++++++ clang/test/CodeGen/builtins-sparc.c | 25 ++++++++++++++++++--- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 8a0150218a7a9..9af3004ebcc5b 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -9474,6 +9474,28 @@ class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo { public: SparcV8TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(std::make_unique(CGT)) {} + + llvm::Value *decodeReturnAddress(CodeGen::CodeGenFunction &CGF, + llvm::Value *Address) const override { + int Offset; + if (isAggregateTypeForABI(CGF.CurFnInfo->getReturnType())) + Offset = 12; + else + Offset = 8; + return CGF.Builder.CreateGEP(CGF.Int8Ty, Address, + llvm::ConstantInt::get(CGF.Int32Ty, Offset)); + } + + llvm::Value *encodeReturnAddress(CodeGen::CodeGenFunction &CGF, + llvm::Value *Address) const override { + int Offset; + if (isAggregateTypeForABI(CGF.CurFnInfo->getReturnType())) + Offset = -12; + else + Offset = -8; + return CGF.Builder.CreateGEP(CGF.Int8Ty, Address, + llvm::ConstantInt::get(CGF.Int32Ty, Offset)); + } }; } // end anonymous namespace @@ -9748,6 +9770,18 @@ class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo { bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const override; + + llvm::Value *decodeReturnAddress(CodeGen::CodeGenFunction &CGF, + llvm::Value *Address) const override { + return CGF.Builder.CreateGEP(CGF.Int8Ty, Address, + llvm::ConstantInt::get(CGF.Int32Ty, 8)); + } + + llvm::Value *encodeReturnAddress(CodeGen::CodeGenFunction &CGF, + llvm::Value *Address) const override { + return CGF.Builder.CreateGEP(CGF.Int8Ty, Address, + llvm::ConstantInt::get(CGF.Int32Ty, -8)); + } }; } // end anonymous namespace diff --git a/clang/test/CodeGen/builtins-sparc.c b/clang/test/CodeGen/builtins-sparc.c index 92cc7677e21f7..343a1c521526c 100644 --- a/clang/test/CodeGen/builtins-sparc.c +++ b/clang/test/CodeGen/builtins-sparc.c @@ -1,10 +1,29 @@ // REQUIRES: sparc-registered-target // RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s -// RUN: %clang_cc1 -triple sparc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple sparc64-unknown-unknown -emit-llvm %s -o - | FileCheck -check-prefix CHECK-V9 %s void test_eh_return_data_regno(void) { volatile int res; - res = __builtin_eh_return_data_regno(0); // CHECK: store volatile i32 24 - res = __builtin_eh_return_data_regno(1); // CHECK: store volatile i32 25 + res = __builtin_eh_return_data_regno(0); // CHECK,CHECKV9: store volatile i32 24 + res = __builtin_eh_return_data_regno(1); // CHECK,CHECKV9: store volatile i32 25 +} + +void *test_extract_return_address(void) +{ + // CHECK,CHECKV9: getelementptr i8, i8* %0, i32 8 + return __builtin_extract_return_addr(__builtin_return_address(0)); +} + +struct s { + void *p; +}; + +struct s test_extract_struct_return_address(void) +{ + struct s s; + // CHECK: getelementptr i8, i8* %0, i32 12 + // CHECK-V9: getelementptr i8, i8* %0, i32 8 + s.p = __builtin_extract_return_addr(__builtin_return_address(0)); + return s; } From 7246d583d6017dbea8baa453e78f26e145448d6e Mon Sep 17 00:00:00 2001 From: Amilendra Kodithuwakku Date: Tue, 8 Feb 2022 19:11:49 +0000 Subject: [PATCH 065/316] [clang][ARM] Re-word PACBTI warning. The original warning added in D115501 when pacbti is used with an incompatible architecture was not exactly correct because it was not really ignored and can affect codegen. Therefore reword to say that the pacbti option is incompatible with the given architecture. Reviewed By: chill Differential Revision: https://reviews.llvm.org/D119166 (cherry picked from commit 424e850f1ebc3e7011cb4af44cb2d62c02a58fbe) --- clang/include/clang/Basic/DiagnosticCommonKinds.td | 4 ++-- clang/lib/Driver/ToolChains/Clang.cpp | 2 +- clang/test/Driver/arm-security-options.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index 5ea55b0fd31ba..421527827a4bd 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -145,8 +145,8 @@ def warn_conflicting_nullability_attr_overriding_param_types : Warning< def err_nullability_conflicting : Error< "nullability specifier %0 conflicts with existing specifier %1">; -def warn_target_unsupported_branch_protection_option: Warning < - "ignoring '-mbranch-protection=' option because the '%0' architecture does not support it">, +def warn_incompatible_branch_protection_option: Warning < + "'-mbranch-protection=' option is incompatible with the '%0' architecture">, InGroup; def warn_target_unsupported_branch_protection_attribute: Warning < diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 5b2984ea2496f..f2f18e901ab01 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1639,7 +1639,7 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, const Driver &D = TC.getDriver(); const llvm::Triple &Triple = TC.getEffectiveTriple(); if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass()))) - D.Diag(diag::warn_target_unsupported_branch_protection_option) + D.Diag(diag::warn_incompatible_branch_protection_option) << Triple.getArchName(); StringRef Scope, Key; diff --git a/clang/test/Driver/arm-security-options.c b/clang/test/Driver/arm-security-options.c index 79367d7bbb965..fc1b5da78d2cf 100644 --- a/clang/test/Driver/arm-security-options.c +++ b/clang/test/Driver/arm-security-options.c @@ -90,4 +90,4 @@ // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}' // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}' -// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the '{{.*}}' architecture does not support it +// INCOMPATIBLE-ARCH: '-mbranch-protection=' option is incompatible with the '{{.*}}' architecture From f5f0bd8e3d972d040827c88adf1a9880ebcb821e Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Mon, 7 Feb 2022 11:31:22 -0500 Subject: [PATCH 066/316] Revert "[Clang] Propagate guaranteed alignment for malloc and others" The above change assumed that malloc (and friends) would always allocate memory to getNewAlign(), even for allocations which have a smaller size. This is not actually required by spec (a 1-byte allocation may validly have 1-byte alignment). Some real-world malloc implementations do not provide this guarantee, and thus this optimization is breaking programs. Fixes #53540 This reverts commit c2297544c04764237cedc523083c7be2fb3833d4. Differential Revision: https://reviews.llvm.org/D118804 (cherry picked from commit 9545976ff160e19805a84a06a7e59d446f9994d9) --- clang/include/clang/Basic/TargetInfo.h | 4 +- clang/lib/Sema/SemaDecl.cpp | 17 ------- clang/test/CodeGen/alloc-fns-alignment.c | 56 +++++++++--------------- 3 files changed, 22 insertions(+), 55 deletions(-) diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index a49342a34f3e8..e7db877f4e2bc 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -644,8 +644,8 @@ class TargetInfo : public virtual TransferrableTargetInfo, } /// Return the largest alignment for which a suitably-sized allocation with - /// '::operator new(size_t)' or 'malloc' is guaranteed to produce a - /// correctly-aligned pointer. + /// '::operator new(size_t)' is guaranteed to produce a correctly-aligned + /// pointer. unsigned getNewAlign() const { return NewAlign ? NewAlign : std::max(LongDoubleAlign, LongLongAlign); } diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index cbd9df4d6a7b7..bcadf4139046c 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -15319,24 +15319,7 @@ void Sema::AddKnownFunctionAttributes(FunctionDecl *FD) { if (!FD->hasAttr()) FD->addAttr(AllocAlignAttr::CreateImplicit(Context, ParamIdx(1, FD), FD->getLocation())); - LLVM_FALLTHROUGH; - case Builtin::BIcalloc: - case Builtin::BImalloc: - case Builtin::BImemalign: - case Builtin::BIrealloc: - case Builtin::BIstrdup: - case Builtin::BIstrndup: { - if (!FD->hasAttr()) { - unsigned NewAlign = Context.getTargetInfo().getNewAlign() / - Context.getTargetInfo().getCharWidth(); - IntegerLiteral *Alignment = IntegerLiteral::Create( - Context, Context.MakeIntValue(NewAlign, Context.UnsignedIntTy), - Context.UnsignedIntTy, FD->getLocation()); - FD->addAttr(AssumeAlignedAttr::CreateImplicit( - Context, Alignment, /*Offset=*/nullptr, FD->getLocation())); - } break; - } default: break; } diff --git a/clang/test/CodeGen/alloc-fns-alignment.c b/clang/test/CodeGen/alloc-fns-alignment.c index 8ab0610accf03..31dc9bb2d759d 100644 --- a/clang/test/CodeGen/alloc-fns-alignment.c +++ b/clang/test/CodeGen/alloc-fns-alignment.c @@ -1,11 +1,9 @@ -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm < %s | FileCheck %s --check-prefix=ALIGN16 -// RUN: %clang_cc1 -triple x86_64-windows-msvc -emit-llvm < %s | FileCheck %s --check-prefix=ALIGN16 -// RUN: %clang_cc1 -triple i386-apple-darwin -emit-llvm < %s | FileCheck %s --check-prefix=ALIGN16 -// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm < %s | FileCheck %s --check-prefix=ALIGN8 -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-malloc -emit-llvm < %s | FileCheck %s --check-prefix=NOBUILTIN-MALLOC -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-calloc -emit-llvm < %s | FileCheck %s --check-prefix=NOBUILTIN-CALLOC -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-realloc -emit-llvm < %s | FileCheck %s --check-prefix=NOBUILTIN-REALLOC -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-aligned_alloc -emit-llvm < %s | FileCheck %s --check-prefix=NOBUILTIN-ALIGNED_ALLOC +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm < %s | FileCheck %s + +// Note: this test originally asserted that malloc/calloc/realloc got alignment +// attributes on their return pointer. However, that was reverted in +// https://reviews.llvm.org/D118804 and it now asserts that they do _NOT_ get +// align attributes. typedef __SIZE_TYPE__ size_t; @@ -39,43 +37,29 @@ void *aligned_alloc_large_constant_test(size_t n) { } // CHECK-LABEL: @malloc_test -// ALIGN16: align 16 i8* @malloc - -// CHECK-LABEL: @calloc_test -// ALIGN16: align 16 i8* @calloc - -// CHECK-LABEL: @realloc_test -// ALIGN16: align 16 i8* @realloc - -// CHECK-LABEL: @aligned_alloc_variable_test -// ALIGN16: %[[ALLOCATED:.*]] = call align 16 i8* @aligned_alloc({{i32|i64}} noundef %[[ALIGN:.*]], {{i32|i64}} noundef %[[NBYTES:.*]]) -// ALIGN16-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* %[[ALLOCATED]], {{i32|i64}} %[[ALIGN]]) ] +// CHECK: call i8* @malloc -// CHECK-LABEL: @aligned_alloc_constant_test -// ALIGN16: align 16 i8* @aligned_alloc - -// CHECK-LABEL: @aligned_alloc_large_constant_test -// ALIGN16: align 4096 i8* @aligned_alloc - -// CHECK-LABEL: @malloc_test -// ALIGN8: align 8 i8* @malloc +// CHECK: declare i8* @malloc // CHECK-LABEL: @calloc_test -// ALIGN8: align 8 i8* @calloc +// CHECK: call i8* @calloc + +// CHECK: declare i8* @calloc // CHECK-LABEL: @realloc_test -// ALIGN8: align 8 i8* @realloc +// CHECK: call i8* @realloc + +// CHECK: declare i8* @realloc // CHECK-LABEL: @aligned_alloc_variable_test -// ALIGN8: align 8 i8* @aligned_alloc +// CHECK: %[[ALLOCATED:.*]] = call i8* @aligned_alloc({{i32|i64}} noundef %[[ALIGN:.*]], {{i32|i64}} noundef %[[NBYTES:.*]]) +// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* %[[ALLOCATED]], {{i32|i64}} %[[ALIGN]]) ] + +// CHECK: declare i8* @aligned_alloc // CHECK-LABEL: @aligned_alloc_constant_test -// ALIGN8: align 8 i8* @aligned_alloc +// CHECK: call align 8 i8* @aligned_alloc // CHECK-LABEL: @aligned_alloc_large_constant_test -// ALIGN8: align 4096 i8* @aligned_alloc +// CHECK: call align 4096 i8* @aligned_alloc -// NOBUILTIN-MALLOC: declare i8* @malloc -// NOBUILTIN-CALLOC: declare i8* @calloc -// NOBUILTIN-REALLOC: declare i8* @realloc -// NOBUILTIN-ALIGNED_ALLOC: declare i8* @aligned_alloc From 8344ab9c4f19b10d62806b0b7fdc48891595c2fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 9 Feb 2022 13:42:02 +0200 Subject: [PATCH 067/316] [docs] Add release notes for things that I've been involved in --- clang/docs/ReleaseNotes.rst | 14 ++++++++++++++ lld/docs/ReleaseNotes.rst | 9 +++++++-- llvm/docs/ReleaseNotes.rst | 30 ++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index caa2349f9d860..c8596fcfdc989 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -81,6 +81,10 @@ New Compiler Flags - The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't be added after a setjmp or possible other return-twice construct (ARM backend only). +- The ``--start-no-unused-arguments`` and ``--end-no-unused-arguments`` flags + allow silencing warnings about unused arguments for only a subset of + the command line arguments, keeping potential warnings for other arguments + outside of such a region. Deprecated Compiler Flags ------------------------- @@ -164,6 +168,16 @@ Windows Support - Support for on-demand initialization of TLS variables was added. +- Improved code generation for ARM, by assuming less strict alignment + requirements for instructions (just like other OSes do). + +- Fixed using the ``-m32`` flag in x86_64 MinGW setups, by e.g. making ``-m32`` + pick i686 instead of i386, if there is no i386 sysroot, but only one for + i686. + +- Fixed passing the ``--no-demangle`` option through to the linker for MinGW + targets. + C Language Changes in Clang --------------------------- diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index 82683801fad94..f611da428a8fe 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -58,12 +58,17 @@ Breaking changes COFF Improvements ----------------- -* ... +* Correctly handle a signed immediate offset in ARM64 adr/adrp relocations. + (`D114347 `_) + +* Omit section and label symbols from the symbol table. + (`D113866 `_) MinGW Improvements ------------------ -* ... +* ``--heap`` is now handled. + (`D118405 `_) MachO Improvements ------------------ diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 3745128fd948d..447ef45e6ae88 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -80,12 +80,17 @@ Changes to the AArch64 Backend the use of the -mtune frontend flag. This allows certain scheduling features and optimisations to be enabled independently of the architecture. If the "tune-cpu" attribute is absent it tunes according to the "target-cpu". +* Fixed relocations against temporary symbols (e.g. in jump tables and + constant pools) in large COFF object files. Changes to the ARM Backend -------------------------- * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures. * Added support for the Armv8.1-M PACBTI-M extension. +* Changed the assembly comment string for MSVC targets to ``@`` (consistent + with the MinGW and ELF targets), freeing up ``;`` to be used as + statement separator. Changes to the MIPS Target -------------------------- @@ -124,6 +129,24 @@ Changes to the WebAssembly Target During this release ... +Changes to the Windows Target +----------------------------- + +* Changed how the ``.pdata`` sections refer to the code they're describing, + to avoid conflicting unwind info if weak symbols are overridden. + +* Fixed code generation for calling support routines for converting 128 bit + integers from/to floats on x86_64. + +* The preferred path separator form (backslashes or forward slashes) can be + configured in Windows builds of LLVM now, with the + ``LLVM_WINDOWS_PREFER_FORWARD_SLASH`` CMake option. This defaults to + true in MinGW builds of LLVM. + +* Set proper COFF symbol types for function aliases (e.g. for Itanium C++ + constructors), making sure that GNU ld exports all of them correctly as + functions, not data, when linking a DLL. + Changes to the OCaml bindings ----------------------------- @@ -134,6 +157,9 @@ Changes to the C API * ``LLVMSetInstDebugLocation`` has been deprecated in favor of the more general ``LLVMAddMetadataToInst``. +* Fixed building LLVM-C.dll for i386 targets with MSVC, which had been broken + since the LLVM 8.0.0 release. + Changes to the Go bindings -------------------------- @@ -159,6 +185,8 @@ Changes to the LLVM tools `-name-whitelist` is marked as deprecated and to be removed in future releases. +* llvm-readobj: Improved printing of symbols in Windows unwind data. + Changes to LLDB --------------------------------- @@ -177,6 +205,8 @@ Changes to LLDB * The ``memory read`` command has a new option ``--show-tags``. Use this option to show memory tags beside the contents of tagged memory ranges. +* Fixed continuing from breakpoints and singlestepping on Windows on ARM/ARM64. + Changes to Sanitizers --------------------- From 1bdeb1b877196345a0a0a0b0730b902fb16704d3 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Thu, 3 Feb 2022 23:09:37 +0100 Subject: [PATCH 068/316] [libc++] Remove vector base class Remove the vector base class as suggested by @ldionne Reviewed By: ldionne, Quuxplusone, #libc Spies: libcxx-commits, ldionne Differential Revision: https://reviews.llvm.org/D117108 (cherry picked from commit b82da8b555603b172f826fdd5ea902eff3aeb7ad) --- libcxx/include/__config | 2 + libcxx/include/vector | 93 ++++++++++++----------------------------- libcxx/src/vector.cpp | 17 +++++++- 3 files changed, 44 insertions(+), 68 deletions(-) diff --git a/libcxx/include/__config b/libcxx/include/__config index d2d70c4ed7694..458d0c1b897af 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -116,6 +116,8 @@ # define _LIBCPP_ABI_NO_RANDOM_DEVICE_COMPATIBILITY_LAYOUT // Remove basic_string common base # define _LIBCPP_ABI_DO_NOT_EXPORT_BASIC_STRING_COMMON +// Remove vector base class +# define _LIBCPP_ABI_DO_NOT_EXPORT_VECTOR_BASE_COMMON #elif _LIBCPP_ABI_VERSION == 1 # if !defined(_LIBCPP_OBJECT_FORMAT_COFF) // Enable compiling copies of now inline methods into the dylib to support diff --git a/libcxx/include/vector b/libcxx/include/vector index fd0fb0db27565..28a7ed9bdf364 100644 --- a/libcxx/include/vector +++ b/libcxx/include/vector @@ -302,55 +302,10 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -template -struct __vector_base_common; - -template <> -struct __vector_base_common { - // Both are defined in vector.cpp - _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_length_error() const; - _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_out_of_range() const; -}; - -template -class __vector_base - : protected __vector_base_common // This base class is historical, but it needs to remain for ABI compatibility -{ - typedef _Allocator allocator_type; - typedef typename allocator_traits::pointer pointer; - -protected: - pointer __begin_; - pointer __end_; - __compressed_pair __end_cap_; - - _LIBCPP_INLINE_VISIBILITY - __vector_base() - _NOEXCEPT_(is_nothrow_default_constructible::value) - : __begin_(nullptr), - __end_(nullptr), - __end_cap_(nullptr, __default_init_tag()) {} - - _LIBCPP_INLINE_VISIBILITY __vector_base(const allocator_type& __a) - : __begin_(nullptr), - __end_(nullptr), - __end_cap_(nullptr, __a) {} - -#ifndef _LIBCPP_CXX03_LANG - _LIBCPP_INLINE_VISIBILITY __vector_base(allocator_type&& __a) _NOEXCEPT - : __begin_(nullptr), - __end_(nullptr), - __end_cap_(nullptr, _VSTD::move(__a)) {} -#endif -}; - template */> class _LIBCPP_TEMPLATE_VIS vector - // This base class is historical, but it needs to remain for ABI compatibility. - : private __vector_base<_Tp, _Allocator> { private: - typedef __vector_base<_Tp, _Allocator> __base; typedef allocator<_Tp> __default_allocator_type; public: typedef vector __self; @@ -382,7 +337,7 @@ public: #else _NOEXCEPT #endif - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); } @@ -394,7 +349,7 @@ public: template ::value> > vector(size_type __n, const value_type& __x, const allocator_type& __a) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); if (__n > 0) @@ -691,6 +646,11 @@ public: #endif // _LIBCPP_DEBUG_LEVEL == 2 private: + pointer __begin_ = nullptr; + pointer __end_ = nullptr; + __compressed_pair __end_cap_ = + __compressed_pair(nullptr, __default_init_tag()); + _LIBCPP_INLINE_VISIBILITY void __invalidate_all_iterators(); _LIBCPP_INLINE_VISIBILITY void __invalidate_iterators_past(pointer __new_last); void __vallocate(size_type __n); @@ -859,20 +819,12 @@ private: _LIBCPP_NORETURN _LIBCPP_HIDE_FROM_ABI void __throw_length_error() const { -#ifndef _LIBCPP_NO_EXCEPTIONS - __vector_base_common::__throw_length_error(); -#else - _VSTD::abort(); -#endif + _VSTD::__throw_length_error("vector"); } _LIBCPP_NORETURN _LIBCPP_HIDE_FROM_ABI void __throw_out_of_range() const { -#ifndef _LIBCPP_NO_EXCEPTIONS - __vector_base_common::__throw_out_of_range(); -#else - _VSTD::abort(); -#endif + _VSTD::__throw_out_of_range("vector"); } _LIBCPP_INLINE_VISIBILITY @@ -1106,7 +1058,7 @@ vector<_Tp, _Allocator>::vector(size_type __n) #if _LIBCPP_STD_VER > 11 template vector<_Tp, _Allocator>::vector(size_type __n, const allocator_type& __a) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); if (__n > 0) @@ -1151,7 +1103,7 @@ vector<_Tp, _Allocator>::vector(_InputIterator __first, _InputIterator __last, c is_constructible< value_type, typename iterator_traits<_InputIterator>::reference>::value>::type*) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); for (; __first != __last; ++__first) @@ -1183,7 +1135,7 @@ vector<_Tp, _Allocator>::vector(_ForwardIterator __first, _ForwardIterator __las is_constructible< value_type, typename iterator_traits<_ForwardIterator>::reference>::value>::type*) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); size_type __n = static_cast(_VSTD::distance(__first, __last)); @@ -1196,7 +1148,7 @@ vector<_Tp, _Allocator>::vector(_ForwardIterator __first, _ForwardIterator __las template vector<_Tp, _Allocator>::vector(const vector& __x) - : __base(__alloc_traits::select_on_container_copy_construction(__x.__alloc())) + : __end_cap_(nullptr, __alloc_traits::select_on_container_copy_construction(__x.__alloc())) { _VSTD::__debug_db_insert_c(this); size_type __n = __x.size(); @@ -1209,7 +1161,7 @@ vector<_Tp, _Allocator>::vector(const vector& __x) template vector<_Tp, _Allocator>::vector(const vector& __x, const __identity_t& __a) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); size_type __n = __x.size(); @@ -1230,7 +1182,7 @@ vector<_Tp, _Allocator>::vector(vector&& __x) #else _NOEXCEPT_(is_nothrow_move_constructible::value) #endif - : __base(_VSTD::move(__x.__alloc())) + : __end_cap_(nullptr, _VSTD::move(__x.__alloc())) { _VSTD::__debug_db_insert_c(this); #if _LIBCPP_DEBUG_LEVEL == 2 @@ -1245,7 +1197,7 @@ vector<_Tp, _Allocator>::vector(vector&& __x) template inline _LIBCPP_INLINE_VISIBILITY vector<_Tp, _Allocator>::vector(vector&& __x, const __identity_t& __a) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); if (__a == __x.__alloc()) @@ -1280,7 +1232,7 @@ vector<_Tp, _Allocator>::vector(initializer_list __il) template inline _LIBCPP_INLINE_VISIBILITY vector<_Tp, _Allocator>::vector(initializer_list __il, const allocator_type& __a) - : __base(__a) + : __end_cap_(nullptr, __a) { _VSTD::__debug_db_insert_c(this); if (__il.size() > 0) @@ -2079,7 +2031,6 @@ struct __has_storage_type > template class _LIBCPP_TEMPLATE_VIS vector - : private __vector_base_common { public: typedef vector __self; @@ -2348,6 +2299,16 @@ public: bool __invariants() const; private: + _LIBCPP_NORETURN _LIBCPP_HIDE_FROM_ABI + void __throw_length_error() const { + _VSTD::__throw_length_error("vector"); + } + + _LIBCPP_NORETURN _LIBCPP_HIDE_FROM_ABI + void __throw_out_of_range() const { + _VSTD::__throw_out_of_range("vector"); + } + _LIBCPP_INLINE_VISIBILITY void __invalidate_all_iterators(); void __vallocate(size_type __n); void __vdeallocate() _NOEXCEPT; diff --git a/libcxx/src/vector.cpp b/libcxx/src/vector.cpp index cc3d291e350e1..201d4e3bf09a4 100644 --- a/libcxx/src/vector.cpp +++ b/libcxx/src/vector.cpp @@ -10,12 +10,25 @@ _LIBCPP_BEGIN_NAMESPACE_STD +#ifndef _LIBCPP_ABI_DO_NOT_EXPORT_VECTOR_BASE_COMMON + +template +struct __vector_base_common; + +template <> +struct __vector_base_common { + _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_length_error() const; + _LIBCPP_NORETURN _LIBCPP_EXPORTED_FROM_ABI void __throw_out_of_range() const; +}; + void __vector_base_common::__throw_length_error() const { - _VSTD::__throw_length_error("vector"); + _VSTD::__throw_length_error("vector"); } void __vector_base_common::__throw_out_of_range() const { - _VSTD::__throw_out_of_range("vector"); + _VSTD::__throw_out_of_range("vector"); } +#endif // _LIBCPP_ABI_DO_NOT_EXPORT_VECTOR_BASE_COMMON + _LIBCPP_END_NAMESPACE_STD From ac8818e38f6ea6d84e54ff1ea2c0436ecb43bc69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 9 Feb 2022 18:57:13 +0200 Subject: [PATCH 069/316] [docs] Mention another fixed bug in the release notes --- llvm/docs/ReleaseNotes.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 447ef45e6ae88..f513b620066a1 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -147,6 +147,10 @@ Changes to the Windows Target constructors), making sure that GNU ld exports all of them correctly as functions, not data, when linking a DLL. +* Handling of temporary files on more uncommon file systems (network + mounts, ramdisks) on Windows is fixed now (which previously either + errored out or left stray files behind). + Changes to the OCaml bindings ----------------------------- From 43f21792e4af17c88d9740fb63d7c26dbb1560b9 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 9 Feb 2022 10:13:19 -0500 Subject: [PATCH 070/316] [runtimes] Add a warning about the Standalone build being deprecated We are removing support for the Standalone build altogether on the main branch, so this is going to help give an additional heads up to users that don't read our release notes. Also, as a fly-by fix, fixup incorrect documentation for libcxxabi and mention libunwind in our release notes. Differential Revision: https://reviews.llvm.org/D119341 --- libcxx/CMakeLists.txt | 2 ++ libcxx/docs/ReleaseNotes.rst | 20 ++++++++-------- libcxxabi/CMakeLists.txt | 3 +++ libcxxabi/www/index.html | 46 ++++-------------------------------- libunwind/CMakeLists.txt | 3 +++ 5 files changed, 22 insertions(+), 52 deletions(-) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 183b3df621b42..6cd36ecfa7224 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -27,6 +27,8 @@ set(LIBCXX_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}) set(LIBCXX_BINARY_INCLUDE_DIR "${LIBCXX_BINARY_DIR}/include/c++build") if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBCXX_STANDALONE_BUILD) + message(WARNING "The Standalone build is deprecated in this release. Please use one of the ways " + "described at https://libcxx.llvm.org/BuildingLibcxx.html for building libc++.") project(libcxx CXX C) set(PACKAGE_NAME libcxx) diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index dd8d2648ca019..a9dd06e9490d2 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -189,14 +189,14 @@ Build System Changes Consider using a Bootstrapping build to build libc++ with a fresh Clang if you can't use the system compiler to build libc++ anymore. -- Historically, there have been numerous ways of building libc++ and libc++abi. This has - led to at least 5 different ways to build the runtimes, which was impossible to - maintain with a good level of support. Starting with this release, libc++ and libc++abi support - exactly two ways of being built, which should cater to all use-cases. Furthermore, - these builds are as lightweight as possible and will work consistently even when targeting - embedded platforms, which used not to be the case. :doc:`BuildingLibcxx` describes - those two ways of building. Please migrate over to the appropriate build instructions - as soon as possible. +- Historically, there have been numerous ways of building libc++, libc++abi, and libunwind. + This has led to at least 5 different ways to build the runtimes, which was impossible to + maintain with a good level of support. Starting with this release, libc++, libc++abi, and + libunwind support exactly two ways of being built, which should cater to all use-cases. + Furthermore, these builds are as lightweight as possible and will work consistently even + when targeting embedded platforms, which used not to be the case. :doc:`BuildingLibcxx` + describes those two ways of building. Please migrate over to the appropriate build + instructions as soon as possible. All other ways to build are deprecated and will not be supported in the next release. We understand that making these changes can be daunting. For that reason, here's a @@ -206,8 +206,8 @@ Build System Changes (which was the previously advertised way to build the runtimes), please simply root your CMake invocation at ``/runtimes`` and pass ``-DLLVM_ENABLE_RUNTIMES=<...>``. - - If you were doing two CMake invocations, one rooted at ``/libcxx`` and one rooted at - ``/libcxxabi`` (this used to be called a "Standalone build"), please move them to a + - If you were doing multiple CMake invocations, e.g. one rooted at ``/libcxx`` and one rooted + at ``/libcxxabi`` (this used to be called a "Standalone build"), please move them to a single invocation like so: .. code-block:: bash diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt index ecbc7091864e7..58c21059c6025 100644 --- a/libcxxabi/CMakeLists.txt +++ b/libcxxabi/CMakeLists.txt @@ -28,6 +28,9 @@ set(LIBCXXABI_LIBCXX_PATH "${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH "Specify path to libc++ source.") if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBCXXABI_STANDALONE_BUILD) + message(WARNING "The Standalone build is deprecated in this release. Please use one of the ways " + "described at https://libcxx.llvm.org/BuildingLibcxx.html for building libc++abi.") + project(libcxxabi CXX C) set(PACKAGE_NAME libcxxabi) diff --git a/libcxxabi/www/index.html b/libcxxabi/www/index.html index b6275e61da938..88035047dd391 100644 --- a/libcxxabi/www/index.html +++ b/libcxxabi/www/index.html @@ -73,52 +73,14 @@

Current Status

Get it and get involved!

-

To check out the code (including llvm and others), use:

- -
    -
  • git clone https://github.com/llvm/llvm-project.git
    • -
- -

To build:

-
    -
  • cd llvm-project
    • -
  • mkdir build && cd build
    • -
  • cmake -DLLVM_ENABLE_PROJECTS=libcxxabi ../llvm # on linux you may need to specify -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++
    • -
  • make
    • -
- -

To do a standalone build:

-
    -
  • - Check out the source tree. This includes the other subprojects, but you'll only use the libcxxabi part. -
    • -
  • cd llvm-project
    • -
  • mkdir build-libcxxabi && cd build-libcxxabi
    • -
  • cmake ../libcxxabi # on linux you may need -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++
    • -
  • make
    • -
-

By default CMake uses llvm-config to locate the required - LLVM sources. If CMake cannot find llvm-config then you must - configure CMake using either of the following options. +

For building libc++abi, please see the libc++ documentation on + building the runtimes.

-
    -
  • -DLLVM_CONFIG_PATH=path/to/llvm-config
    • -
  • -DLLVM_PATH=path/to/llvm-source-root
    • -
+

For getting involved with libc++abi, please see the libc++ documentation on + getting involved.

-

To run the tests:

-
    -
  • make check-cxxabi
    • -
-

Note: in a standalone build, the system's libc++ will be used for tests. If - the system's libc++ was statically linked against libc++abi (or linked against - a different ABI library), this may interfere with test results.

- -

Send discussions to the - (libcxx-dev mailing list).

-

Frequently asked questions

diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index 04550ae51a422..87d51b7894459 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -24,6 +24,9 @@ set(LIBUNWIND_LIBCXX_PATH "${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH "Specify path to libc++ source.") if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBUNWIND_STANDALONE_BUILD) + message(WARNING "The Standalone build is deprecated in this release. Please use one of the ways " + "described at https://libcxx.llvm.org/BuildingLibcxx.html for building libunwind.") + # We may have an incomplete toolchain - do language support tests without # linking. include(EnableLanguageNolink) From 7efa49801166f221d8fd7b20ac0d04368b8ea9d5 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 9 Feb 2022 10:10:45 -0800 Subject: [PATCH 071/316] [ELF] Warn about to-be-removed -d, -dc, -dp, and --[no-]define-common See https://github.com/llvm/llvm-project/issues/53660 --- lld/ELF/Driver.cpp | 3 +++ lld/test/ELF/relocatable-common.s | 12 +++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index ca56f5ee0f10f..54b487bdc2434 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -1240,6 +1240,9 @@ static void readConfigs(opt::InputArgList &args) { error(errPrefix + toString(pat.takeError())); } + if (args.hasArg(OPT_define_common, OPT_no_define_common)) + warn("-d, -dc, -dp, and --[no-]define-common will be removed. See https://github.com/llvm/llvm-project/issues/53660"); + cl::ResetAllOptionOccurrences(); // Parse LTO options. diff --git a/lld/test/ELF/relocatable-common.s b/lld/test/ELF/relocatable-common.s index 0c89cea9be406..1b87358217f12 100644 --- a/lld/test/ELF/relocatable-common.s +++ b/lld/test/ELF/relocatable-common.s @@ -2,17 +2,19 @@ # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o # RUN: ld.lld -r %t1.o -o %t # RUN: llvm-readobj --symbols -r %t | FileCheck %s -# RUN: ld.lld -r --no-define-common %t1.o -o %t +# RUN: ld.lld -r --no-define-common %t1.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN # RUN: llvm-readobj --symbols -r %t | FileCheck %s -# RUN: ld.lld -r --define-common %t1.o -o %t +# RUN: ld.lld -r --define-common %t1.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN # RUN: llvm-readobj --symbols -r %t | FileCheck -check-prefix=DEFCOMM %s -# RUN: ld.lld -r -d %t1.o -o %t +# RUN: ld.lld -r -d %t1.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN # RUN: llvm-readobj --symbols -r %t | FileCheck -check-prefix=DEFCOMM %s -# RUN: ld.lld -r -dc %t1.o -o %t +# RUN: ld.lld -r -dc %t1.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN # RUN: llvm-readobj --symbols -r %t | FileCheck -check-prefix=DEFCOMM %s -# RUN: ld.lld -r -dp %t1.o -o %t +# RUN: ld.lld -r -dp %t1.o -o %t 2>&1 | FileCheck %s --check-prefix=WARN # RUN: llvm-readobj --symbols -r %t | FileCheck -check-prefix=DEFCOMM %s +# WARN: warning: -d, -dc, -dp, and --[no-]define-common will be removed. See https://github.com/llvm/llvm-project/issues/53660 + # CHECK: Symbol { # CHECK: Name: common # CHECK-NEXT: Value: 0x4 From 816988d19a7a2bb72daf4a62a59e96384bf5f2e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 9 Feb 2022 19:36:58 +0200 Subject: [PATCH 072/316] [libunwind] Avoid a warning in 32 bit builds. NFC. The warning was introduced with the recently merged SPARCv9 support in 2b9554b8850192bdd86c02eb671de1d866df8d87. The cast matches the existing surrounding cases. Differential Revision: https://reviews.llvm.org/D119353 (cherry picked from commit dfa5ab7b2b510e68ca2b11b043898c192633c0f6) --- libunwind/src/DwarfInstructions.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp index c1a241c55ce66..ab83b0c87acdc 100644 --- a/libunwind/src/DwarfInstructions.hpp +++ b/libunwind/src/DwarfInstructions.hpp @@ -91,8 +91,8 @@ typename A::pint_t DwarfInstructions::getSavedRegister( return (pint_t)addressSpace.getRegister(cfa + (pint_t)savedReg.value); case CFI_Parser::kRegisterInCFADecrypt: // sparc64 specific - return addressSpace.getP(cfa + (pint_t)savedReg.value) ^ - getSparcWCookie(registers, 0); + return (pint_t)(addressSpace.getP(cfa + (pint_t)savedReg.value) ^ + getSparcWCookie(registers, 0)); case CFI_Parser::kRegisterAtExpression: return (pint_t)addressSpace.getRegister(evaluateExpression( From e77317a786b0c6d4489de0e6679128baf363498e Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Wed, 9 Feb 2022 10:22:50 +0100 Subject: [PATCH 073/316] test-release.sh: Remove test-suite from LLVM_ENABLE_PROJECTS I think this was just being ignored before, but now it crashes because we're checking if the projects that we're trying to enable are valid. There is no test-suite project (it's a separate repo with separate handling), so we should never try to enable it. Differential Revision: https://reviews.llvm.org/D119322 --- llvm/utils/release/test-release.sh | 5 ----- 1 file changed, 5 deletions(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index d6fb5a972e633..41c3f3af14221 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -249,11 +249,6 @@ if [ $do_libs = "yes" ]; then runtimes="$runtimes libunwind" fi fi -case $do_test_suite in - yes|export-only) - projects="$projects test-suite" - ;; -esac if [ $do_openmp = "yes" ]; then projects="$projects openmp" fi From 2ead82c6f972c8372f761b40fcfd7f533b632db5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 9 Feb 2022 15:15:25 +0200 Subject: [PATCH 074/316] [clang] [MinGW] Default to DWARF 4 Neither LLDB nor GDB seem to work with DWARF 5 debug information on Windows right now. This applies the same change as in 9c6272861032f511a23784ce0c5cc8f6ac2f625b (Default to DWARFv4 on Windows) to the MinGW driver too. Differential Revision: https://reviews.llvm.org/D119326 (cherry picked from commit 6cf64b2d2858dc93c3ec93438bdaca2807847e9b) --- clang/lib/Driver/ToolChains/MinGW.h | 2 ++ clang/test/CodeGen/dwarf-version.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/clang/lib/Driver/ToolChains/MinGW.h b/clang/lib/Driver/ToolChains/MinGW.h index c3de19b977246..c9553b4f46520 100644 --- a/clang/lib/Driver/ToolChains/MinGW.h +++ b/clang/lib/Driver/ToolChains/MinGW.h @@ -90,6 +90,8 @@ class LLVM_LIBRARY_VISIBILITY MinGW : public ToolChain { void printVerboseInfo(raw_ostream &OS) const override; + unsigned GetDefaultDwarfVersion() const override { return 4; } + protected: Tool *getTool(Action::ActionClass AC) const override; Tool *buildLinker() const override; diff --git a/clang/test/CodeGen/dwarf-version.c b/clang/test/CodeGen/dwarf-version.c index 47025e241d13c..0a6fa4768026d 100644 --- a/clang/test/CodeGen/dwarf-version.c +++ b/clang/test/CodeGen/dwarf-version.c @@ -32,6 +32,11 @@ // Explicitly request both. // RUN: %clang -target i686-pc-windows-msvc -gdwarf -gcodeview -S -emit-llvm -o - %s \ // RUN: | FileCheck %s --check-prefixes=VER4,CODEVIEW + +// Check what version of dwarf is used for MinGW targets. +// RUN: %clang -target i686-pc-windows-gnu -g -S -emit-llvm -o - %s | \ +// RUN: FileCheck %s --check-prefixes=VER4 + // RUN: %clang -target powerpc-ibm-aix-xcoff -g -S -emit-llvm -o - %s | \ // RUN: FileCheck %s --check-prefix=VER3 // RUN: %clang -target powerpc-ibm-aix-xcoff -gdwarf-2 -S -emit-llvm -o - %s | \ From 97fdb3a48aa849750378f01d4bcd0dc89c71b747 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 9 Feb 2022 12:08:44 -0500 Subject: [PATCH 075/316] Update all LLVM documentation mentioning runtimes in LLVM_ENABLE_PROJECTS We are moving away from building the runtimes with LLVM_ENABLE_PROJECTS, however the documentation was largely outdated. This commit updates all the documentation I could find to use LLVM_ENABLE_RUNTIMES instead of LLVM_ENABLE_PROJECTS for building runtimes. Note that in the near future, libcxx, libcxxabi and libunwind will stop supporting being built with LLVM_ENABLE_PROJECTS altogether. I don't know what the plans are for other runtimes like libc, openmp and compiler-rt, so I didn't make any changes to the documentation that would imply something for those projects. Once this lands, I will also cherry-pick this on the release/14.x branch to make sure that LLVM's documentation is up-to-date and reflects what we intend to support in the future. Differential Revision: https://reviews.llvm.org/D119351 (cherry picked from commit 4ae83bb2b1e27628f6bd14d746aef964ed776d52) --- README.md | 20 ++++++++++++++------ bolt/docs/OptimizingClang.md | 5 +++-- clang/docs/DataFlowSanitizer.rst | 6 +++--- clang/docs/Toolchain.rst | 2 +- compiler-rt/www/index.html | 2 +- flang/README.md | 9 +++++---- libcxx/docs/BuildingLibcxx.rst | 8 ++++---- libunwind/docs/BuildingLibunwind.rst | 2 +- llvm/docs/BuildingADistribution.rst | 4 ++-- llvm/docs/CMake.rst | 20 ++++++++++++-------- llvm/docs/GettingStarted.rst | 18 ++++++++++++++---- 11 files changed, 60 insertions(+), 36 deletions(-) diff --git a/README.md b/README.md index 303721f8a4dac..f79f4fc2ae0b5 100644 --- a/README.md +++ b/README.md @@ -63,17 +63,25 @@ This is an example work-flow and configuration to get and build the LLVM source: Some common options: - * ``-DLLVM_ENABLE_PROJECTS='...'`` --- semicolon-separated list of the LLVM - sub-projects you'd like to additionally build. Can include any of: clang, - clang-tools-extra, compiler-rt,cross-project-tests, flang, libc, libclc, - libcxx, libcxxabi, libunwind, lld, lldb, mlir, openmp, polly, or pstl. + * ``-DLLVM_ENABLE_PROJECTS='...'`` and ``-DLLVM_ENABLE_RUNTIMES='...'`` --- + semicolon-separated list of the LLVM sub-projects and runtimes you'd like to + additionally build. ``LLVM_ENABLE_PROJECTS`` can include any of: clang, + clang-tools-extra, cross-project-tests, flang, libc, libclc, lld, lldb, + mlir, openmp, polly, or pstl. ``LLVM_ENABLE_RUNTIMES`` can include any of + libcxx, libcxxabi, libunwind, compiler-rt, libc or openmp. Some runtime + projects can be specified either in ``LLVM_ENABLE_PROJECTS`` or in + ``LLVM_ENABLE_RUNTIMES``. For example, to build LLVM, Clang, libcxx, and libcxxabi, use - ``-DLLVM_ENABLE_PROJECTS="clang;libcxx;libcxxabi"``. + ``-DLLVM_ENABLE_PROJECTS="clang" -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi"``. * ``-DCMAKE_INSTALL_PREFIX=directory`` --- Specify for *directory* the full path name of where you want the LLVM tools and libraries to be installed - (default ``/usr/local``). + (default ``/usr/local``). Be careful if you install runtime libraries: if + your system uses those provided by LLVM (like libc++ or libc++abi), you + must not overwrite your system's copy of those libraries, since that + could render your system unusable. In general, using something like + ``/usr`` is not advised, but ``/usr/local`` is fine. * ``-DCMAKE_BUILD_TYPE=type`` --- Valid options for *type* are Debug, Release, RelWithDebInfo, and MinSizeRel. Default is Debug. diff --git a/bolt/docs/OptimizingClang.md b/bolt/docs/OptimizingClang.md index 5d727d9417819..e66201b31d6d4 100644 --- a/bolt/docs/OptimizingClang.md +++ b/bolt/docs/OptimizingClang.md @@ -41,7 +41,7 @@ Collecting accurate profile requires running `perf` on a hardware that implements taken branch sampling (`-b/-j` flag). For that reason, it may not be possible to collect the accurate profile in a virtualized environment, e.g. in the cloud. We do support regular sampling profiles, but the performance -improvements are expected to be more modest. +improvements are expected to be more modest. ```bash $ mkdir ${TOPLEV}/stage3 @@ -211,7 +211,8 @@ $ cd ${TOPLEV}/stage1 $ cmake -G Ninja ${TOPLEV}/llvm-project/llvm -DLLVM_TARGETS_TO_BUILD=X86 \ -DCMAKE_BUILD_TYPE=Release \ -DCMAKE_C_COMPILER=gcc -DCMAKE_CXX_COMPILER=g++ -DCMAKE_ASM_COMPILER=gcc \ - -DLLVM_ENABLE_PROJECTS="clang;lld;compiler-rt" \ + -DLLVM_ENABLE_PROJECTS="clang;lld" \ + -DLLVM_ENABLE_RUNTIMES="compiler-rt" \ -DCOMPILER_RT_BUILD_SANITIZERS=OFF -DCOMPILER_RT_BUILD_XRAY=OFF \ -DCOMPILER_RT_BUILD_LIBFUZZER=OFF \ -DCMAKE_INSTALL_PREFIX=${TOPLEV}/stage1/install diff --git a/clang/docs/DataFlowSanitizer.rst b/clang/docs/DataFlowSanitizer.rst index b4136a935dd28..6faca3f2ed913 100644 --- a/clang/docs/DataFlowSanitizer.rst +++ b/clang/docs/DataFlowSanitizer.rst @@ -32,15 +32,15 @@ libc++ and the libc++ ABI with data flow sanitizer instrumentation. .. code-block:: console + mkdir libcxx-build cd libcxx-build # An example using ninja - cmake -GNinja path/to/llvm-project/llvm \ + cmake -GNinja -S /runtimes \ -DCMAKE_C_COMPILER=clang \ -DCMAKE_CXX_COMPILER=clang++ \ -DLLVM_USE_SANITIZER="DataFlow" \ - -DLLVM_ENABLE_LIBCXX=ON \ - -DLLVM_ENABLE_PROJECTS="libcxx;libcxxabi" + -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi" ninja cxx cxxabi diff --git a/clang/docs/Toolchain.rst b/clang/docs/Toolchain.rst index 2ed835c0317e4..958199eb7a2e2 100644 --- a/clang/docs/Toolchain.rst +++ b/clang/docs/Toolchain.rst @@ -230,7 +230,7 @@ libunwind (LLVM) ^^^^^^^^^^^^^^^^ LLVM's unwinder library is part of the llvm-project git repository. To -build it, pass ``-DLLVM_ENABLE_PROJECTS=libunwind`` to the cmake invocation. +build it, pass ``-DLLVM_ENABLE_RUNTIMES=libunwind`` to the cmake invocation. If using libc++abi, you may need to configure it to use libunwind rather than libgcc_s by passing ``-DLIBCXXABI_USE_LLVM_UNWINDER=YES`` diff --git a/compiler-rt/www/index.html b/compiler-rt/www/index.html index 3954a3c4e516a..d190565244004 100644 --- a/compiler-rt/www/index.html +++ b/compiler-rt/www/index.html @@ -112,7 +112,7 @@

Get it and get involved!

Generally, you need to build LLVM/Clang in order to build compiler-rt. You can build it either together with llvm and clang, or separately. -

To build it together, simply add compiler-rt to the -DLLVM_ENABLE_PROJECTS= option to +

To build it together, simply add compiler-rt to the -DLLVM_ENABLE_RUNTIMES= option to cmake.

To build it separately, first diff --git a/flang/README.md b/flang/README.md index a8cd9c83846df..604049a5ebee9 100644 --- a/flang/README.md +++ b/flang/README.md @@ -33,8 +33,8 @@ read the [style guide](docs/C++style.md) and also review [how flang uses modern C++ features](docs/C++17.md). -If you are interested in writing new documentation, follow -[markdown style guide from LLVM](https://github.com/llvm/llvm-project/blob/main/llvm/docs/MarkdownQuickstartTemplate.md). +If you are interested in writing new documentation, follow +[LLVM's Markdown style guide](https://github.com/llvm/llvm-project/blob/main/llvm/docs/MarkdownQuickstartTemplate.md). ## Building flang There are two ways to build flang. The first method is to build it at the same @@ -55,7 +55,7 @@ Note that compiler-rt is only needed to access libraries that support 16 bit floating point numbers. It's not needed to run the automated tests. Here's a complete set of commands to clone all of the necessary source and do -the build. +the build. First clone the source: ```bash @@ -79,7 +79,8 @@ cmake \ -DLLVM_TARGETS_TO_BUILD=host \ -DCMAKE_INSTALL_PREFIX=$INSTALLDIR -DLLVM_LIT_ARGS=-v \ - -DLLVM_ENABLE_PROJECTS="clang;mlir;flang;compiler-rt" + -DLLVM_ENABLE_PROJECTS="clang;mlir;flang" \ + -DLLVM_ENABLE_RUNTIMES="compiler-rt" ninja ``` diff --git a/libcxx/docs/BuildingLibcxx.rst b/libcxx/docs/BuildingLibcxx.rst index b84bf8cdbf461..a0c7672ff7717 100644 --- a/libcxx/docs/BuildingLibcxx.rst +++ b/libcxx/docs/BuildingLibcxx.rst @@ -523,8 +523,8 @@ We can now run CMake: .. code-block:: bash - $ cmake -G Ninja -S llvm -B build \ - -DLLVM_ENABLE_PROJECTS="libcxx" \ + $ cmake -G Ninja -S runtimes -B build \ + -DLLVM_ENABLE_RUNTIMES="libcxx" \ -DLIBCXX_CXX_ABI=libstdc++ \ -DLIBCXX_CXX_ABI_INCLUDE_PATHS="/usr/include/c++/4.7/;/usr/include/c++/4.7/x86_64-linux-gnu/" $ ninja -C build install-cxx @@ -549,8 +549,8 @@ We can now run CMake like: .. code-block:: bash - $ cmake -G Ninja -S llvm -B build \ - -DLLVM_ENABLE_PROJECTS="libcxx" \ + $ cmake -G Ninja -S runtimes -B build \ + -DLLVM_ENABLE_RUNTIMES="libcxx" \ -DLIBCXX_CXX_ABI=libcxxrt \ -DLIBCXX_CXX_ABI_INCLUDE_PATHS=path/to/libcxxrt-sources/src $ ninja -C build install-cxx diff --git a/libunwind/docs/BuildingLibunwind.rst b/libunwind/docs/BuildingLibunwind.rst index d4e051e93a74f..99e52761515cc 100644 --- a/libunwind/docs/BuildingLibunwind.rst +++ b/libunwind/docs/BuildingLibunwind.rst @@ -32,7 +32,7 @@ The basic steps needed to build libc++ are: * ``cd where you want to build llvm`` * ``mkdir build`` * ``cd build`` - * ``cmake -G -DLLVM_ENABLE_PROJECTS=libunwind [options] `` + * ``cmake -G -DLLVM_ENABLE_RUNTIMES=libunwind [options] /runtimes`` For more information about configuring libunwind see :ref:`CMake Options`. diff --git a/llvm/docs/BuildingADistribution.rst b/llvm/docs/BuildingADistribution.rst index ee7abe1f5cd7f..e52e55cb996c0 100644 --- a/llvm/docs/BuildingADistribution.rst +++ b/llvm/docs/BuildingADistribution.rst @@ -199,8 +199,8 @@ Relevant CMake Options This section provides documentation of the CMake options that are intended to help construct distributions. This is not an exhaustive list, and many additional options are documented in the :doc:`CMake` page. Some key options -that are already documented include: *LLVM_TARGETS_TO_BUILD*, -*LLVM_ENABLE_PROJECTS*, *LLVM_BUILD_LLVM_DYLIB*, and *LLVM_LINK_LLVM_DYLIB*. +that are already documented include: *LLVM_TARGETS_TO_BUILD*, *LLVM_ENABLE_PROJECTS*, +*LLVM_ENABLE_RUNTIMES*, *LLVM_BUILD_LLVM_DYLIB*, and *LLVM_LINK_LLVM_DYLIB*. **LLVM_ENABLE_RUNTIMES**:STRING When building a distribution that includes LLVM runtime projects (i.e. libcxx, diff --git a/llvm/docs/CMake.rst b/llvm/docs/CMake.rst index a567c8e501044..ac635fc7df885 100644 --- a/llvm/docs/CMake.rst +++ b/llvm/docs/CMake.rst @@ -221,6 +221,10 @@ description is in `LLVM-related variables`_ below. Control which projects are enabled. For example you may want to work on clang or lldb by specifying ``-DLLVM_ENABLE_PROJECTS="clang;lldb"``. +**LLVM_ENABLE_RUNTIMES**:STRING + Control which runtimes are enabled. For example you may want to work on + libc++ or libc++abi by specifying ``-DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi"``. + **LLVM_LIBDIR_SUFFIX**:STRING Extra suffix to append to the directory where libraries are to be installed. On a 64-bit architecture, one could use ``-DLLVM_LIBDIR_SUFFIX=64`` @@ -505,17 +509,17 @@ enabled sub-projects. Nearly all of these variable names begin with **LLVM_ENABLE_PROJECTS**:STRING Semicolon-separated list of projects to build, or *all* for building all - (clang, lldb, compiler-rt, lld, polly, etc) projects. This flag assumes - that projects are checked out side-by-side and not nested, i.e. clang - needs to be in parallel of llvm instead of nested in `llvm/tools`. - This feature allows to have one build for only LLVM and another for clang+llvm - using the same source checkout. + (clang, lldb, lld, polly, etc) projects. This flag assumes that projects + are checked out side-by-side and not nested, i.e. clang needs to be in + parallel of llvm instead of nested in `llvm/tools`. This feature allows + to have one build for only LLVM and another for clang+llvm using the same + source checkout. The full list is: - ``clang;clang-tools-extra;compiler-rt;cross-project-tests;libc;libclc;lld;lldb;openmp;polly;pstl`` + ``clang;clang-tools-extra;cross-project-tests;libc;libclc;lld;lldb;openmp;polly;pstl`` **LLVM_ENABLE_RUNTIMES**:STRING - Build libc++, libc++abi or other projects using that a just-built compiler. - This is the correct way to build libc++ when putting together a toolchain. + Build libc++, libc++abi, libunwind or compiler-rt using the just-built compiler. + This is the correct way to build runtimes when putting together a toolchain. It will build the builtins separately from the other runtimes to preserve correct dependency ordering. If you want to build the runtimes using a system compiler, see the `libc++ documentation `_. diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst index d1eaa09cfc26b..7d699d87491bb 100644 --- a/llvm/docs/GettingStarted.rst +++ b/llvm/docs/GettingStarted.rst @@ -623,10 +623,15 @@ used by people developing LLVM. | | other LLVM subprojects to additionally build. (Only| | | effective when using a side-by-side project layout | | | e.g. via git). The default list is empty. Can | -| | include: clang, clang-tools-extra, compiler-rt, | -| | cross-project-tests, flang, libc, libclc, libcxx, | -| | libcxxabi, libunwind, lld, lldb, mlir, openmp, | -| | polly, or pstl. | +| | include: clang, clang-tools-extra, | +| | cross-project-tests, flang, libc, libclc, lld, | +| | lldb, mlir, openmp, polly, or pstl. | ++-------------------------+----------------------------------------------------+ +| LLVM_ENABLE_RUNTIMES | A semicolon-delimited list selecting which of the | +| | runtimes to build. (Only effective when using the | +| | full monorepo layout). The default list is empty. | +| | Can include: compiler-rt, libc, libcxx, libcxxabi, | +| | libunwind, or openmp. | +-------------------------+----------------------------------------------------+ | LLVM_ENABLE_SPHINX | Build sphinx-based documentation from the source | | | code. This is disabled by default because it is | @@ -1217,6 +1222,11 @@ following options with cmake: compiling more than one project, separate the items with a semicolon. Should you run into issues with the semicolon, try surrounding it with single quotes. +* -DLLVM_ENABLE_RUNTIMES + Set this equal to the runtimes you wish to compile (e.g. libcxx, libcxxabi, etc.) + If compiling more than one runtime, separate the items with a semicolon. Should + you run into issues with the semicolon, try surrounding it with single quotes. + * -DCLANG_ENABLE_STATIC_ANALYZER Set this option to OFF if you do not require the clang static analyzer. This should improve your build time slightly. From 5410d0ac67ad0d64b973eab0f5bc106d75639790 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Mon, 7 Feb 2022 16:24:16 +0200 Subject: [PATCH 076/316] [libcxx] Silence -Wformat-nonliteral warnings in the Windows support code This brings the mingw build back to zero build warnings as it was at some earlier time. Differential Revision: https://reviews.llvm.org/D119134 (cherry picked from commit 8cffea061afc556332a86fbf80ef5613db994974) --- libcxx/src/support/win32/locale_win32.cpp | 3 +++ libcxx/src/support/win32/support.cpp | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/libcxx/src/support/win32/locale_win32.cpp b/libcxx/src/support/win32/locale_win32.cpp index f10916875d42f..43e5c9a57227f 100644 --- a/libcxx/src/support/win32/locale_win32.cpp +++ b/libcxx/src/support/win32/locale_win32.cpp @@ -97,7 +97,10 @@ int snprintf_l(char *ret, size_t n, locale_t loc, const char *format, ...) ret, n, format, loc, ap); #else __libcpp_locale_guard __current(loc); +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wformat-nonliteral" int result = vsnprintf( ret, n, format, ap ); +#pragma clang diagnostic pop #endif va_end(ap); return result; diff --git a/libcxx/src/support/win32/support.cpp b/libcxx/src/support/win32/support.cpp index 115d975bbf9a6..6d4b371f3dc20 100644 --- a/libcxx/src/support/win32/support.cpp +++ b/libcxx/src/support/win32/support.cpp @@ -23,7 +23,10 @@ int __libcpp_vasprintf( char **sptr, const char *__restrict format, va_list ap ) // Query the count required. va_list ap_copy; va_copy(ap_copy, ap); +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wformat-nonliteral" int count = vsnprintf( NULL, 0, format, ap_copy ); +#pragma clang diagnostic pop va_end(ap_copy); if (count < 0) return count; @@ -33,7 +36,10 @@ int __libcpp_vasprintf( char **sptr, const char *__restrict format, va_list ap ) return -1; // If we haven't used exactly what was required, something is wrong. // Maybe bug in vsnprintf. Report the error and return. +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wformat-nonliteral" if (vsnprintf(p, buffer_size, format, ap) != count) { +#pragma clang diagnostic pop free(p); return -1; } From 71e4987ae6643255474917cc4d95c2d42b4b165c Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 2 Feb 2022 13:02:35 +0100 Subject: [PATCH 077/316] Revert "[SLP]Alternate vectorization for cmp instructions." This reverts commit 83620bd2ad867f706c699d0f2b8be10e43d9f3d7. It's causing miscompilations, see review comments at https://reviews.llvm.org/D115955 (cherry picked from commit 0c3d22a5926dd7d6fd28682683abd9d476f8e78b) --- .../Transforms/Vectorize/SLPVectorizer.cpp | 179 +---------- .../X86/vector-reductions-logical.ll | 57 ++-- .../X86/cmp_commute-inseltpoison.ll | 52 +++- .../SLPVectorizer/X86/cmp_commute.ll | 52 +++- .../SLPVectorizer/X86/reduction-logical.ll | 278 ++++++++---------- 5 files changed, 251 insertions(+), 367 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 15b349f53fd99..25bf69729c70f 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -471,36 +471,17 @@ static bool isValidForAlternation(unsigned Opcode) { return true; } -static InstructionsState getSameOpcode(ArrayRef VL, - unsigned BaseIndex = 0); - -/// Checks if the provided operands of 2 cmp instructions are compatible, i.e. -/// compatible instructions or constants, or just some other regular values. -static bool areCompatibleCmpOps(Value *BaseOp0, Value *BaseOp1, Value *Op0, - Value *Op1) { - return (isConstant(BaseOp0) && isConstant(Op0)) || - (isConstant(BaseOp1) && isConstant(Op1)) || - (!isa(BaseOp0) && !isa(Op0) && - !isa(BaseOp1) && !isa(Op1)) || - getSameOpcode({BaseOp0, Op0}).getOpcode() || - getSameOpcode({BaseOp1, Op1}).getOpcode(); -} - /// \returns analysis of the Instructions in \p VL described in /// InstructionsState, the Opcode that we suppose the whole list /// could be vectorized even if its structure is diverse. static InstructionsState getSameOpcode(ArrayRef VL, - unsigned BaseIndex) { + unsigned BaseIndex = 0) { // Make sure these are all Instructions. if (llvm::any_of(VL, [](Value *V) { return !isa(V); })) return InstructionsState(VL[BaseIndex], nullptr, nullptr); bool IsCastOp = isa(VL[BaseIndex]); bool IsBinOp = isa(VL[BaseIndex]); - bool IsCmpOp = isa(VL[BaseIndex]); - CmpInst::Predicate BasePred = - IsCmpOp ? cast(VL[BaseIndex])->getPredicate() - : CmpInst::BAD_ICMP_PREDICATE; unsigned Opcode = cast(VL[BaseIndex])->getOpcode(); unsigned AltOpcode = Opcode; unsigned AltIndex = BaseIndex; @@ -533,57 +514,6 @@ static InstructionsState getSameOpcode(ArrayRef VL, continue; } } - } else if (IsCmpOp && isa(VL[Cnt])) { - auto *BaseInst = cast(VL[BaseIndex]); - auto *Inst = cast(VL[Cnt]); - Type *Ty0 = BaseInst->getOperand(0)->getType(); - Type *Ty1 = Inst->getOperand(0)->getType(); - if (Ty0 == Ty1) { - Value *BaseOp0 = BaseInst->getOperand(0); - Value *BaseOp1 = BaseInst->getOperand(1); - Value *Op0 = Inst->getOperand(0); - Value *Op1 = Inst->getOperand(1); - CmpInst::Predicate CurrentPred = - cast(VL[Cnt])->getPredicate(); - CmpInst::Predicate SwappedCurrentPred = - CmpInst::getSwappedPredicate(CurrentPred); - // Check for compatible operands. If the corresponding operands are not - // compatible - need to perform alternate vectorization. - if (InstOpcode == Opcode) { - if (BasePred == CurrentPred && - areCompatibleCmpOps(BaseOp0, BaseOp1, Op0, Op1)) - continue; - if (BasePred == SwappedCurrentPred && - areCompatibleCmpOps(BaseOp0, BaseOp1, Op1, Op0)) - continue; - if (E == 2 && - (BasePred == CurrentPred || BasePred == SwappedCurrentPred)) - continue; - auto *AltInst = cast(VL[AltIndex]); - CmpInst::Predicate AltPred = AltInst->getPredicate(); - Value *AltOp0 = AltInst->getOperand(0); - Value *AltOp1 = AltInst->getOperand(1); - // Check if operands are compatible with alternate operands. - if (AltPred == CurrentPred && - areCompatibleCmpOps(AltOp0, AltOp1, Op0, Op1)) - continue; - if (AltPred == SwappedCurrentPred && - areCompatibleCmpOps(AltOp0, AltOp1, Op1, Op0)) - continue; - } - if (BaseIndex == AltIndex) { - assert(isValidForAlternation(Opcode) && - isValidForAlternation(InstOpcode) && - "Cast isn't safe for alternation, logic needs to be updated!"); - AltIndex = Cnt; - continue; - } - auto *AltInst = cast(VL[AltIndex]); - CmpInst::Predicate AltPred = AltInst->getPredicate(); - if (BasePred == CurrentPred || BasePred == SwappedCurrentPred || - AltPred == CurrentPred || AltPred == SwappedCurrentPred) - continue; - } } else if (InstOpcode == Opcode || InstOpcode == AltOpcode) continue; return InstructionsState(VL[BaseIndex], nullptr, nullptr); @@ -4424,41 +4354,9 @@ void BoUpSLP::buildTree_rec(ArrayRef VL, unsigned Depth, LLVM_DEBUG(dbgs() << "SLP: added a ShuffleVector op.\n"); // Reorder operands if reordering would enable vectorization. - auto *CI = dyn_cast(VL0); - if (isa(VL0) || CI) { + if (isa(VL0)) { ValueList Left, Right; - if (!CI || all_of(VL, [](Value *V) { - return cast(V)->isCommutative(); - })) { - reorderInputsAccordingToOpcode(VL, Left, Right, *DL, *SE, *this); - } else { - CmpInst::Predicate P0 = CI->getPredicate(); - CmpInst::Predicate AltP0 = cast(S.AltOp)->getPredicate(); - CmpInst::Predicate AltP0Swapped = CmpInst::getSwappedPredicate(AltP0); - Value *BaseOp0 = VL0->getOperand(0); - Value *BaseOp1 = VL0->getOperand(1); - // Collect operands - commute if it uses the swapped predicate or - // alternate operation. - for (Value *V : VL) { - auto *Cmp = cast(V); - Value *LHS = Cmp->getOperand(0); - Value *RHS = Cmp->getOperand(1); - CmpInst::Predicate CurrentPred = CI->getPredicate(); - CmpInst::Predicate CurrentPredSwapped = - CmpInst::getSwappedPredicate(CurrentPred); - if (P0 == AltP0 || P0 == AltP0Swapped) { - if ((P0 == CurrentPred && - !areCompatibleCmpOps(BaseOp0, BaseOp1, LHS, RHS)) || - (P0 == CurrentPredSwapped && - !areCompatibleCmpOps(BaseOp0, BaseOp1, RHS, LHS))) - std::swap(LHS, RHS); - } else if (!areCompatibleCmpOps(BaseOp0, BaseOp1, LHS, RHS)) { - std::swap(LHS, RHS); - } - Left.push_back(LHS); - Right.push_back(RHS); - } - } + reorderInputsAccordingToOpcode(VL, Left, Right, *DL, *SE, *this); TE->setOperand(0, Left); TE->setOperand(1, Right); buildTree_rec(Left, Depth + 1, {TE, 0}); @@ -5390,8 +5288,7 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, ((Instruction::isBinaryOp(E->getOpcode()) && Instruction::isBinaryOp(E->getAltOpcode())) || (Instruction::isCast(E->getOpcode()) && - Instruction::isCast(E->getAltOpcode())) || - (isa(VL0) && isa(E->getAltOp()))) && + Instruction::isCast(E->getAltOpcode()))) && "Invalid Shuffle Vector Operand"); InstructionCost ScalarCost = 0; if (NeedToShuffleReuses) { @@ -5439,14 +5336,6 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, VecCost = TTI->getArithmeticInstrCost(E->getOpcode(), VecTy, CostKind); VecCost += TTI->getArithmeticInstrCost(E->getAltOpcode(), VecTy, CostKind); - } else if (auto *CI0 = dyn_cast(VL0)) { - VecCost = TTI->getCmpSelInstrCost(E->getOpcode(), ScalarTy, - Builder.getInt1Ty(), - CI0->getPredicate(), CostKind, VL0); - VecCost += TTI->getCmpSelInstrCost( - E->getOpcode(), ScalarTy, Builder.getInt1Ty(), - cast(E->getAltOp())->getPredicate(), CostKind, - E->getAltOp()); } else { Type *Src0SclTy = E->getMainOp()->getOperand(0)->getType(); Type *Src1SclTy = E->getAltOp()->getOperand(0)->getType(); @@ -5463,29 +5352,6 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, E->Scalars, E->ReorderIndices, E->ReuseShuffleIndices, [E](Instruction *I) { assert(E->isOpcodeOrAlt(I) && "Unexpected main/alternate opcode"); - if (auto *CI0 = dyn_cast(E->getMainOp())) { - auto *AltCI0 = cast(E->getAltOp()); - auto *CI = cast(I); - CmpInst::Predicate P0 = CI0->getPredicate(); - CmpInst::Predicate AltP0 = AltCI0->getPredicate(); - CmpInst::Predicate AltP0Swapped = - CmpInst::getSwappedPredicate(AltP0); - CmpInst::Predicate CurrentPred = CI->getPredicate(); - CmpInst::Predicate CurrentPredSwapped = - CmpInst::getSwappedPredicate(CurrentPred); - if (P0 == AltP0 || P0 == AltP0Swapped) { - // Alternate cmps have same/swapped predicate as main cmps but - // different order of compatible operands. - return !( - (P0 == CurrentPred && - areCompatibleCmpOps(CI0->getOperand(0), CI0->getOperand(1), - I->getOperand(0), I->getOperand(1))) || - (P0 == CurrentPredSwapped && - areCompatibleCmpOps(CI0->getOperand(0), CI0->getOperand(1), - I->getOperand(1), I->getOperand(0)))); - } - return CurrentPred != P0 && CurrentPredSwapped != P0; - } return I->getOpcode() == E->getAltOpcode(); }, Mask); @@ -6968,12 +6834,11 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { ((Instruction::isBinaryOp(E->getOpcode()) && Instruction::isBinaryOp(E->getAltOpcode())) || (Instruction::isCast(E->getOpcode()) && - Instruction::isCast(E->getAltOpcode())) || - (isa(VL0) && isa(E->getAltOp()))) && + Instruction::isCast(E->getAltOpcode()))) && "Invalid Shuffle Vector Operand"); Value *LHS = nullptr, *RHS = nullptr; - if (Instruction::isBinaryOp(E->getOpcode()) || isa(VL0)) { + if (Instruction::isBinaryOp(E->getOpcode())) { setInsertPointAfterBundle(E); LHS = vectorizeTree(E->getOperand(0)); RHS = vectorizeTree(E->getOperand(1)); @@ -6993,15 +6858,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { static_cast(E->getOpcode()), LHS, RHS); V1 = Builder.CreateBinOp( static_cast(E->getAltOpcode()), LHS, RHS); - } else if (auto *CI0 = dyn_cast(VL0)) { - V0 = Builder.CreateCmp(CI0->getPredicate(), LHS, RHS); - auto *AltCI = cast(E->getAltOp()); - CmpInst::Predicate AltPred = AltCI->getPredicate(); - unsigned AltIdx = - std::distance(E->Scalars.begin(), find(E->Scalars, AltCI)); - if (AltCI->getOperand(0) != E->getOperand(0)[AltIdx]) - AltPred = CmpInst::getSwappedPredicate(AltPred); - V1 = Builder.CreateCmp(AltPred, LHS, RHS); } else { V0 = Builder.CreateCast( static_cast(E->getOpcode()), LHS, VecTy); @@ -7026,29 +6882,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { E->Scalars, E->ReorderIndices, E->ReuseShuffleIndices, [E](Instruction *I) { assert(E->isOpcodeOrAlt(I) && "Unexpected main/alternate opcode"); - if (auto *CI0 = dyn_cast(E->getMainOp())) { - auto *AltCI0 = cast(E->getAltOp()); - auto *CI = cast(I); - CmpInst::Predicate P0 = CI0->getPredicate(); - CmpInst::Predicate AltP0 = AltCI0->getPredicate(); - CmpInst::Predicate AltP0Swapped = - CmpInst::getSwappedPredicate(AltP0); - CmpInst::Predicate CurrentPred = CI->getPredicate(); - CmpInst::Predicate CurrentPredSwapped = - CmpInst::getSwappedPredicate(CurrentPred); - if (P0 == AltP0 || P0 == AltP0Swapped) { - // Alternate cmps have same/swapped predicate as main cmps but - // different order of compatible operands. - return !( - (P0 == CurrentPred && - areCompatibleCmpOps(CI0->getOperand(0), CI0->getOperand(1), - I->getOperand(0), I->getOperand(1))) || - (P0 == CurrentPredSwapped && - areCompatibleCmpOps(CI0->getOperand(0), CI0->getOperand(1), - I->getOperand(1), I->getOperand(0)))); - } - return CurrentPred != P0 && CurrentPredSwapped != P0; - } return I->getOpcode() == E->getAltOpcode(); }, Mask, &OpScalars, &AltScalars); diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll index 83cab29aa883a..486faf75fb7a7 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll @@ -90,17 +90,24 @@ return: define float @test_merge_anyof_v4sf(<4 x float> %t) { ; CHECK-LABEL: @test_merge_anyof_v4sf( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x float> [[T:%.*]], <4 x float> poison, <8 x i32> -; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <8 x float> [[SHUFFLE]], -; CHECK-NEXT: [[TMP1:%.*]] = fcmp ogt <8 x float> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = freeze <8 x i1> [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i1> [[TMP3]] to i8 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i8 [[TMP4]], 0 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[SHIFT]], [[T]] -; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP5]], i64 0 -; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[DOTNOT]], float [[ADD]], float 0.000000e+00 +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T:%.*]], i64 3 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T]], i64 2 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T]], i64 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T]], i64 0 +; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T]] +; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 +; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 +; CHECK-NEXT: [[CMP19:%.*]] = fcmp ogt float [[TMP3]], 1.000000e+00 +; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP19]] +; CHECK-NEXT: [[CMP24:%.*]] = fcmp ogt float [[TMP2]], 1.000000e+00 +; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP24]] +; CHECK-NEXT: [[CMP29:%.*]] = fcmp ogt float [[TMP1]], 1.000000e+00 +; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP29]] +; CHECK-NEXT: [[CMP34:%.*]] = fcmp ogt float [[TMP0]], 1.000000e+00 +; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP34]] +; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]] ; CHECK-NEXT: ret float [[RETVAL_0]] ; entry: @@ -413,18 +420,24 @@ return: define float @test_merge_anyof_v4si(<4 x i32> %t) { ; CHECK-LABEL: @test_merge_anyof_v4si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[T:%.*]], <4 x i32> poison, <8 x i32> -; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i1> [[TMP0]], <8 x i1> [[TMP1]], <8 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = freeze <8 x i1> [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i1> [[TMP3]] to i8 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i8 [[TMP4]], 0 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]] -; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP5]], i64 0 +; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i4 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0 +; CHECK-NEXT: [[OR_COND3:%.*]] = or i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1 +; CHECK-NEXT: [[OR_COND4:%.*]] = or i1 [[OR_COND3]], [[TMP5]] +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2 +; CHECK-NEXT: [[OR_COND5:%.*]] = or i1 [[OR_COND4]], [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3 +; CHECK-NEXT: [[OR_COND6:%.*]] = or i1 [[OR_COND5]], [[TMP7]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T_FR]] +; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP8]], i64 0 ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float -; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[DOTNOT]], float [[CONV]], float 0.000000e+00 +; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[CONV]] ; CHECK-NEXT: ret float [[RETVAL_0]] ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll index 0ba0fb8f2d8b2..8f8931d0a6c1d 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+sse2 | FileCheck %s -; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+avx | FileCheck %s +; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX ; ; Check that we can commute operands based on the predicate. @@ -235,14 +235,46 @@ define <4 x i32> @fcmp_ogt_olt_v4i32(<4 x float> %a, float* %b) { } define <4 x i32> @fcmp_ord_uno_v4i32(<4 x float> %a, float* %b) { -; CHECK-LABEL: @fcmp_ord_uno_v4i32( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>* -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = fcmp ord <4 x float> [[TMP2]], [[A:%.*]] -; CHECK-NEXT: [[TMP4:%.*]] = fcmp uno <4 x float> [[TMP2]], [[A]] -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32> -; CHECK-NEXT: ret <4 x i32> [[R]] +; SSE-LABEL: @fcmp_ord_uno_v4i32( +; SSE-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1 +; SSE-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3 +; SSE-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4 +; SSE-NEXT: [[TMP1:%.*]] = bitcast float* [[P1]] to <2 x float>* +; SSE-NEXT: [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4 +; SSE-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4 +; SSE-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <2 x i32> +; SSE-NEXT: [[TMP4:%.*]] = fcmp uno <2 x float> [[TMP2]], [[TMP3]] +; SSE-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[A]], <4 x float> undef, <2 x i32> +; SSE-NEXT: [[TMP6:%.*]] = insertelement <2 x float> poison, float [[B3]], i64 0 +; SSE-NEXT: [[TMP7:%.*]] = insertelement <2 x float> [[TMP6]], float [[B0]], i64 1 +; SSE-NEXT: [[TMP8:%.*]] = fcmp ord <2 x float> [[TMP5]], [[TMP7]] +; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <4 x i32> +; SSE-NEXT: [[D0:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> undef, <4 x i32> +; SSE-NEXT: [[TMP10:%.*]] = shufflevector <2 x i1> [[TMP4]], <2 x i1> poison, <4 x i32> +; SSE-NEXT: [[D21:%.*]] = shufflevector <4 x i1> [[D0]], <4 x i1> [[TMP10]], <4 x i32> +; SSE-NEXT: [[D3:%.*]] = shufflevector <4 x i1> [[D21]], <4 x i1> [[TMP9]], <4 x i32> +; SSE-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32> +; SSE-NEXT: ret <4 x i32> [[R]] +; +; AVX-LABEL: @fcmp_ord_uno_v4i32( +; AVX-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0 +; AVX-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i64 3 +; AVX-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1 +; AVX-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3 +; AVX-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4 +; AVX-NEXT: [[TMP1:%.*]] = bitcast float* [[P1]] to <2 x float>* +; AVX-NEXT: [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4 +; AVX-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4 +; AVX-NEXT: [[C0:%.*]] = fcmp ord float [[A0]], [[B0]] +; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[A]], <4 x float> undef, <2 x i32> +; AVX-NEXT: [[TMP4:%.*]] = fcmp uno <2 x float> [[TMP2]], [[TMP3]] +; AVX-NEXT: [[C3:%.*]] = fcmp ord float [[A3]], [[B3]] +; AVX-NEXT: [[D0:%.*]] = insertelement <4 x i1> poison, i1 [[C0]], i64 0 +; AVX-NEXT: [[TMP5:%.*]] = shufflevector <2 x i1> [[TMP4]], <2 x i1> poison, <4 x i32> +; AVX-NEXT: [[D21:%.*]] = shufflevector <4 x i1> [[D0]], <4 x i1> [[TMP5]], <4 x i32> +; AVX-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D21]], i1 [[C3]], i64 3 +; AVX-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32> +; AVX-NEXT: ret <4 x i32> [[R]] ; %a0 = extractelement <4 x float> %a, i32 0 %a1 = extractelement <4 x float> %a, i32 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll index 8cdd2c4dd2e36..3180078691e40 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+sse2 | FileCheck %s -; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+avx | FileCheck %s +; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX ; ; Check that we can commute operands based on the predicate. @@ -235,14 +235,46 @@ define <4 x i32> @fcmp_ogt_olt_v4i32(<4 x float> %a, float* %b) { } define <4 x i32> @fcmp_ord_uno_v4i32(<4 x float> %a, float* %b) { -; CHECK-LABEL: @fcmp_ord_uno_v4i32( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>* -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = fcmp ord <4 x float> [[TMP2]], [[A:%.*]] -; CHECK-NEXT: [[TMP4:%.*]] = fcmp uno <4 x float> [[TMP2]], [[A]] -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> [[TMP4]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32> -; CHECK-NEXT: ret <4 x i32> [[R]] +; SSE-LABEL: @fcmp_ord_uno_v4i32( +; SSE-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1 +; SSE-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3 +; SSE-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4 +; SSE-NEXT: [[TMP1:%.*]] = bitcast float* [[P1]] to <2 x float>* +; SSE-NEXT: [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4 +; SSE-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4 +; SSE-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <2 x i32> +; SSE-NEXT: [[TMP4:%.*]] = fcmp uno <2 x float> [[TMP2]], [[TMP3]] +; SSE-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[A]], <4 x float> undef, <2 x i32> +; SSE-NEXT: [[TMP6:%.*]] = insertelement <2 x float> poison, float [[B3]], i64 0 +; SSE-NEXT: [[TMP7:%.*]] = insertelement <2 x float> [[TMP6]], float [[B0]], i64 1 +; SSE-NEXT: [[TMP8:%.*]] = fcmp ord <2 x float> [[TMP5]], [[TMP7]] +; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> poison, <4 x i32> +; SSE-NEXT: [[D0:%.*]] = shufflevector <2 x i1> [[TMP8]], <2 x i1> undef, <4 x i32> +; SSE-NEXT: [[TMP10:%.*]] = shufflevector <2 x i1> [[TMP4]], <2 x i1> poison, <4 x i32> +; SSE-NEXT: [[D21:%.*]] = shufflevector <4 x i1> [[D0]], <4 x i1> [[TMP10]], <4 x i32> +; SSE-NEXT: [[D3:%.*]] = shufflevector <4 x i1> [[D21]], <4 x i1> [[TMP9]], <4 x i32> +; SSE-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32> +; SSE-NEXT: ret <4 x i32> [[R]] +; +; AVX-LABEL: @fcmp_ord_uno_v4i32( +; AVX-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0 +; AVX-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i64 3 +; AVX-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1 +; AVX-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3 +; AVX-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4 +; AVX-NEXT: [[TMP1:%.*]] = bitcast float* [[P1]] to <2 x float>* +; AVX-NEXT: [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4 +; AVX-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4 +; AVX-NEXT: [[C0:%.*]] = fcmp ord float [[A0]], [[B0]] +; AVX-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[A]], <4 x float> undef, <2 x i32> +; AVX-NEXT: [[TMP4:%.*]] = fcmp uno <2 x float> [[TMP2]], [[TMP3]] +; AVX-NEXT: [[C3:%.*]] = fcmp ord float [[A3]], [[B3]] +; AVX-NEXT: [[D0:%.*]] = insertelement <4 x i1> undef, i1 [[C0]], i64 0 +; AVX-NEXT: [[TMP5:%.*]] = shufflevector <2 x i1> [[TMP4]], <2 x i1> poison, <4 x i32> +; AVX-NEXT: [[D21:%.*]] = shufflevector <4 x i1> [[D0]], <4 x i1> [[TMP5]], <4 x i32> +; AVX-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D21]], i1 [[C3]], i64 3 +; AVX-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32> +; AVX-NEXT: ret <4 x i32> [[R]] ; %a0 = extractelement <4 x float> %a, i32 0 %a1 = extractelement <4 x float> %a, i32 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll index 9c7826442ab05..ee3481e242d04 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll @@ -93,13 +93,36 @@ define i1 @logical_or_fcmp(<4 x float> %x) { } define i1 @logical_and_icmp_diff_preds(<4 x i32> %x) { -; CHECK-LABEL: @logical_and_icmp_diff_preds( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <4 x i32> [[X:%.*]], zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <4 x i32> [[X]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> [[TMP2]], <4 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP4]]) -; CHECK-NEXT: ret i1 [[TMP5]] +; SSE-LABEL: @logical_and_icmp_diff_preds( +; SSE-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; SSE-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; SSE-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; SSE-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; SSE-NEXT: [[C0:%.*]] = icmp ult i32 [[X0]], 0 +; SSE-NEXT: [[C2:%.*]] = icmp sgt i32 [[X2]], 0 +; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X3]], i32 0 +; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[X1]], i32 1 +; SSE-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP2]], zeroinitializer +; SSE-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1 +; SSE-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[TMP4]], i1 false +; SSE-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; SSE-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0 +; SSE-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[TMP5]], i1 false +; SSE-NEXT: ret i1 [[S3]] +; +; AVX-LABEL: @logical_and_icmp_diff_preds( +; AVX-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; AVX-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; AVX-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; AVX-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; AVX-NEXT: [[C0:%.*]] = icmp ult i32 [[X0]], 0 +; AVX-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 0 +; AVX-NEXT: [[C2:%.*]] = icmp sgt i32 [[X2]], 0 +; AVX-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], 0 +; AVX-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false +; AVX-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; AVX-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false +; AVX-NEXT: ret i1 [[S3]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 @@ -191,13 +214,19 @@ define i1 @logical_and_icmp_subvec(<4 x i32> %x) { define i1 @logical_and_icmp_clamp(<4 x i32> %x) { ; CHECK-LABEL: @logical_and_icmp_clamp( -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = freeze <8 x i1> [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> [[TMP4]]) -; CHECK-NEXT: ret i1 [[TMP5]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[X:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[X]], +; CHECK-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP2]], i32 0 +; CHECK-NEXT: [[S4:%.*]] = select i1 [[TMP4]], i1 [[TMP5]], i1 false +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP2]], i32 1 +; CHECK-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[TMP6]], i1 false +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP2]], i32 2 +; CHECK-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[TMP7]], i1 false +; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP2]], i32 3 +; CHECK-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[TMP8]], i1 false +; CHECK-NEXT: ret i1 [[S7]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 @@ -222,53 +251,28 @@ define i1 @logical_and_icmp_clamp(<4 x i32> %x) { } define i1 @logical_and_icmp_clamp_extra_use_cmp(<4 x i32> %x) { -; SSE-LABEL: @logical_and_icmp_clamp_extra_use_cmp( -; SSE-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 -; SSE-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 -; SSE-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 -; SSE-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 -; SSE-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 -; SSE-NEXT: call void @use1(i1 [[C2]]) -; SSE-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0 -; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X1]], i32 1 -; SSE-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3]], i32 2 -; SSE-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[X0]], i32 3 -; SSE-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], -; SSE-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[TMP4]], -; SSE-NEXT: [[TMP7:%.*]] = shufflevector <4 x i1> [[TMP5]], <4 x i1> [[TMP6]], <4 x i32> -; SSE-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 -; SSE-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 -; SSE-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 -; SSE-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]] -; SSE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP8]]) -; SSE-NEXT: [[OP_EXTRA:%.*]] = select i1 [[TMP9]], i1 [[C2]], i1 false -; SSE-NEXT: [[S5:%.*]] = select i1 [[OP_EXTRA]], i1 [[D1]], i1 false -; SSE-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false -; SSE-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false -; SSE-NEXT: ret i1 [[S7]] -; -; AVX-LABEL: @logical_and_icmp_clamp_extra_use_cmp( -; AVX-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> -; AVX-NEXT: [[TMP1:%.*]] = icmp slt <8 x i32> [[SHUFFLE]], -; AVX-NEXT: [[TMP2:%.*]] = icmp sgt <8 x i32> [[SHUFFLE]], -; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; AVX-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i32 1 -; AVX-NEXT: call void @use1(i1 [[TMP4]]) -; AVX-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[TMP3]], i32 2 -; AVX-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP3]], i32 3 -; AVX-NEXT: [[S1:%.*]] = select i1 [[TMP6]], i1 [[TMP5]], i1 false -; AVX-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[TMP4]], i1 false -; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i1> [[TMP3]], i32 0 -; AVX-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[TMP7]], i1 false -; AVX-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP3]], i32 7 -; AVX-NEXT: [[S4:%.*]] = select i1 [[S3]], i1 [[TMP8]], i1 false -; AVX-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP3]], i32 6 -; AVX-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[TMP9]], i1 false -; AVX-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP3]], i32 5 -; AVX-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[TMP10]], i1 false -; AVX-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP3]], i32 4 -; AVX-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[TMP11]], i1 false -; AVX-NEXT: ret i1 [[S7]] +; CHECK-LABEL: @logical_and_icmp_clamp_extra_use_cmp( +; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 42 +; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 42 +; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 +; CHECK-NEXT: call void @use1(i1 [[C2]]) +; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], 42 +; CHECK-NEXT: [[D0:%.*]] = icmp sgt i32 [[X0]], 17 +; CHECK-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 +; CHECK-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 +; CHECK-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 +; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false +; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false +; CHECK-NEXT: [[S4:%.*]] = select i1 [[S3]], i1 [[D0]], i1 false +; CHECK-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[D1]], i1 false +; CHECK-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false +; CHECK-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false +; CHECK-NEXT: ret i1 [[S7]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 @@ -294,49 +298,28 @@ define i1 @logical_and_icmp_clamp_extra_use_cmp(<4 x i32> %x) { } define i1 @logical_and_icmp_clamp_extra_use_select(<4 x i32> %x) { -; SSE-LABEL: @logical_and_icmp_clamp_extra_use_select( -; SSE-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 3 -; SSE-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[X]], i32 2 -; SSE-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[X]], i32 1 -; SSE-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[X]], i32 0 -; SSE-NEXT: [[C0:%.*]] = icmp slt i32 [[TMP4]], 42 -; SSE-NEXT: [[C1:%.*]] = icmp slt i32 [[TMP3]], 42 -; SSE-NEXT: [[C2:%.*]] = icmp slt i32 [[TMP2]], 42 -; SSE-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[X]], -; SSE-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[X]], -; SSE-NEXT: [[TMP7:%.*]] = shufflevector <4 x i1> [[TMP5]], <4 x i1> [[TMP6]], <4 x i32> -; SSE-NEXT: [[D3:%.*]] = icmp sgt i32 [[TMP1]], 17 -; SSE-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false -; SSE-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false -; SSE-NEXT: call void @use1(i1 [[S2]]) -; SSE-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]] -; SSE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP8]]) -; SSE-NEXT: [[OP_EXTRA:%.*]] = select i1 [[TMP9]], i1 [[S2]], i1 false -; SSE-NEXT: [[S7:%.*]] = select i1 [[OP_EXTRA]], i1 [[D3]], i1 false -; SSE-NEXT: ret i1 [[S7]] -; -; AVX-LABEL: @logical_and_icmp_clamp_extra_use_select( -; AVX-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> -; AVX-NEXT: [[TMP1:%.*]] = icmp slt <8 x i32> [[SHUFFLE]], -; AVX-NEXT: [[TMP2:%.*]] = icmp sgt <8 x i32> [[SHUFFLE]], -; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; AVX-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[TMP3]], i32 2 -; AVX-NEXT: [[TMP5:%.*]] = extractelement <8 x i1> [[TMP3]], i32 3 -; AVX-NEXT: [[S1:%.*]] = select i1 [[TMP5]], i1 [[TMP4]], i1 false -; AVX-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP3]], i32 1 -; AVX-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[TMP6]], i1 false -; AVX-NEXT: call void @use1(i1 [[S2]]) -; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x i1> [[TMP3]], i32 0 -; AVX-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[TMP7]], i1 false -; AVX-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP3]], i32 7 -; AVX-NEXT: [[S4:%.*]] = select i1 [[S3]], i1 [[TMP8]], i1 false -; AVX-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP3]], i32 6 -; AVX-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[TMP9]], i1 false -; AVX-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP3]], i32 5 -; AVX-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[TMP10]], i1 false -; AVX-NEXT: [[TMP11:%.*]] = extractelement <8 x i1> [[TMP3]], i32 4 -; AVX-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[TMP11]], i1 false -; AVX-NEXT: ret i1 [[S7]] +; CHECK-LABEL: @logical_and_icmp_clamp_extra_use_select( +; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 42 +; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 42 +; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 +; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], 42 +; CHECK-NEXT: [[D0:%.*]] = icmp sgt i32 [[X0]], 17 +; CHECK-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 +; CHECK-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 +; CHECK-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 +; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false +; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; CHECK-NEXT: call void @use1(i1 [[S2]]) +; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false +; CHECK-NEXT: [[S4:%.*]] = select i1 [[S3]], i1 [[D0]], i1 false +; CHECK-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[D1]], i1 false +; CHECK-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false +; CHECK-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false +; CHECK-NEXT: ret i1 [[S7]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 @@ -412,47 +395,25 @@ define i1 @logical_and_icmp_clamp_v8i32(<8 x i32> %x, <8 x i32> %y) { } define i1 @logical_and_icmp_clamp_partial(<4 x i32> %x) { -; SSE-LABEL: @logical_and_icmp_clamp_partial( -; SSE-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 -; SSE-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 -; SSE-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 -; SSE-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 -; SSE-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0 -; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[X1]], i32 1 -; SSE-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X2]], i32 2 -; SSE-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[X0]], i32 3 -; SSE-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], -; SSE-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[TMP4]], -; SSE-NEXT: [[TMP7:%.*]] = shufflevector <4 x i1> [[TMP5]], <4 x i1> [[TMP6]], <4 x i32> -; SSE-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 -; SSE-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 -; SSE-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 -; SSE-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP7]] -; SSE-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP8]]) -; SSE-NEXT: [[S5:%.*]] = select i1 [[TMP9]], i1 [[D1]], i1 false -; SSE-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false -; SSE-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false -; SSE-NEXT: ret i1 [[S7]] -; -; AVX-LABEL: @logical_and_icmp_clamp_partial( -; AVX-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 -; AVX-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 -; AVX-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 -; AVX-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 -; AVX-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 42 -; AVX-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 42 -; AVX-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 -; AVX-NEXT: [[D0:%.*]] = icmp sgt i32 [[X0]], 17 -; AVX-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 -; AVX-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 -; AVX-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 -; AVX-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false -; AVX-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false -; AVX-NEXT: [[S4:%.*]] = select i1 [[S2]], i1 [[D0]], i1 false -; AVX-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[D1]], i1 false -; AVX-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false -; AVX-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false -; AVX-NEXT: ret i1 [[S7]] +; CHECK-LABEL: @logical_and_icmp_clamp_partial( +; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 42 +; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 42 +; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 +; CHECK-NEXT: [[D0:%.*]] = icmp sgt i32 [[X0]], 17 +; CHECK-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 +; CHECK-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 +; CHECK-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 +; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false +; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; CHECK-NEXT: [[S4:%.*]] = select i1 [[S2]], i1 [[D0]], i1 false +; CHECK-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[D1]], i1 false +; CHECK-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false +; CHECK-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false +; CHECK-NEXT: ret i1 [[S7]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 @@ -478,13 +439,26 @@ define i1 @logical_and_icmp_clamp_partial(<4 x i32> %x) { define i1 @logical_and_icmp_clamp_pred_diff(<4 x i32> %x) { ; CHECK-LABEL: @logical_and_icmp_clamp_pred_diff( -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <8 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <8 x i32> [[SHUFFLE]], -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = freeze <8 x i1> [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> [[TMP4]]) -; CHECK-NEXT: ret i1 [[TMP5]] +; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0 +; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1 +; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2 +; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3 +; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 42 +; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 42 +; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 42 +; CHECK-NEXT: [[C3:%.*]] = icmp ult i32 [[X3]], 42 +; CHECK-NEXT: [[D0:%.*]] = icmp sgt i32 [[X0]], 17 +; CHECK-NEXT: [[D1:%.*]] = icmp sgt i32 [[X1]], 17 +; CHECK-NEXT: [[D2:%.*]] = icmp sgt i32 [[X2]], 17 +; CHECK-NEXT: [[D3:%.*]] = icmp sgt i32 [[X3]], 17 +; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false +; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false +; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false +; CHECK-NEXT: [[S4:%.*]] = select i1 [[S3]], i1 [[D0]], i1 false +; CHECK-NEXT: [[S5:%.*]] = select i1 [[S4]], i1 [[D1]], i1 false +; CHECK-NEXT: [[S6:%.*]] = select i1 [[S5]], i1 [[D2]], i1 false +; CHECK-NEXT: [[S7:%.*]] = select i1 [[S6]], i1 [[D3]], i1 false +; CHECK-NEXT: ret i1 [[S7]] ; %x0 = extractelement <4 x i32> %x, i32 0 %x1 = extractelement <4 x i32> %x, i32 1 From 1772de7212e9d2ea0711028709a5833ea7769173 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Thu, 10 Feb 2022 19:40:28 +0100 Subject: [PATCH 078/316] [compiler-rt] Fix endianness in get_sock_peer_name test Fix passing the port and IP address with the wrong endianness in get_sock_peer_name() that causes the connect() to fail inside without an outgoing network interface (it's trying to connect to 1.0.0.127 instead of 127.0.0.1). Differential Revision: https://reviews.llvm.org/D119461 (cherry picked from commit c65fb0cdf26296ae83d23260337d1231d0249020) --- .../sanitizer_common/TestCases/Linux/get_sock_peer_name.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler-rt/test/sanitizer_common/TestCases/Linux/get_sock_peer_name.cpp b/compiler-rt/test/sanitizer_common/TestCases/Linux/get_sock_peer_name.cpp index d4e6189d61703..04ac7a1072459 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Linux/get_sock_peer_name.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/Linux/get_sock_peer_name.cpp @@ -17,10 +17,10 @@ int main() { const sockaddr_in sin = { .sin_family = AF_INET, - .sin_port = 1234, + .sin_port = htons(1234), .sin_addr = { - .s_addr = INADDR_LOOPBACK, + .s_addr = htonl(INADDR_LOOPBACK), }, }; assert(connect(fd, reinterpret_cast(&sin), sizeof(sin)) == From 917c47b3bf0dfc45a2a5ba12c1397d647ecf4017 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Wed, 2 Feb 2022 15:06:01 +0100 Subject: [PATCH 079/316] Reapply [sanitizers] Avoid macro clash in SignalContext::WriteFlag (NFC) D116208 may cause a macro clash on older versions of linux, where fs.h defines a READ macro. This is resolved by switching to a more typical casing style for non-macro symbols. Reapplying with changes to the symbol names in various platform specific code, which I missed previously. Differential Revision: https://reviews.llvm.org/D118783 (cherry picked from commit 36cae4299d3225bb32d20dc525f017034ea3c3c1) --- compiler-rt/lib/asan/asan_errors.h | 4 +- .../lib/sanitizer_common/sanitizer_common.h | 2 +- .../lib/sanitizer_common/sanitizer_linux.cpp | 46 +++++++++---------- .../lib/sanitizer_common/sanitizer_mac.cpp | 4 +- .../sanitizer_symbolizer_report.cpp | 4 +- .../lib/sanitizer_common/sanitizer_win.cpp | 10 ++-- 6 files changed, 35 insertions(+), 35 deletions(-) diff --git a/compiler-rt/lib/asan/asan_errors.h b/compiler-rt/lib/asan/asan_errors.h index a7fda2fd9f5d6..af6d1f295eb29 100644 --- a/compiler-rt/lib/asan/asan_errors.h +++ b/compiler-rt/lib/asan/asan_errors.h @@ -53,9 +53,9 @@ struct ErrorDeadlySignal : ErrorBase { scariness.Scare(10, "null-deref"); } else if (signal.addr == signal.pc) { scariness.Scare(60, "wild-jump"); - } else if (signal.write_flag == SignalContext::WRITE) { + } else if (signal.write_flag == SignalContext::Write) { scariness.Scare(30, "wild-addr-write"); - } else if (signal.write_flag == SignalContext::READ) { + } else if (signal.write_flag == SignalContext::Read) { scariness.Scare(20, "wild-addr-read"); } else { scariness.Scare(25, "wild-addr"); diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common.h b/compiler-rt/lib/sanitizer_common/sanitizer_common.h index 139d5a0666646..3302590c67719 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common.h @@ -956,7 +956,7 @@ struct SignalContext { uptr sp; uptr bp; bool is_memory_access; - enum WriteFlag { UNKNOWN, READ, WRITE } write_flag; + enum WriteFlag { Unknown, Read, Write } write_flag; // In some cases the kernel cannot provide the true faulting address; `addr` // will be zero then. This field allows to distinguish between these cases diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp index 29ff7c0417291..2e4d57d87f58e 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp @@ -1825,7 +1825,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #else uptr err = ucontext->uc_mcontext.gregs[REG_ERR]; #endif // SANITIZER_FREEBSD - return err & PF_WRITE ? WRITE : READ; + return err & PF_WRITE ? Write : Read; #elif defined(__mips__) uint32_t *exception_source; uint32_t faulty_instruction; @@ -1848,7 +1848,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { case 0x2a: // swl case 0x2e: // swr #endif - return SignalContext::WRITE; + return SignalContext::Write; case 0x20: // lb case 0x24: // lbu @@ -1863,27 +1863,27 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { case 0x22: // lwl case 0x26: // lwr #endif - return SignalContext::READ; + return SignalContext::Read; #if __mips_isa_rev == 6 case 0x3b: // pcrel op_code = (faulty_instruction >> 19) & 0x3; switch (op_code) { case 0x1: // lwpc case 0x2: // lwupc - return SignalContext::READ; + return SignalContext::Read; } #endif } - return SignalContext::UNKNOWN; + return SignalContext::Unknown; #elif defined(__arm__) static const uptr FSR_WRITE = 1U << 11; uptr fsr = ucontext->uc_mcontext.error_code; - return fsr & FSR_WRITE ? WRITE : READ; + return fsr & FSR_WRITE ? Write : Read; #elif defined(__aarch64__) static const u64 ESR_ELx_WNR = 1U << 6; u64 esr; - if (!Aarch64GetESR(ucontext, &esr)) return UNKNOWN; - return esr & ESR_ELx_WNR ? WRITE : READ; + if (!Aarch64GetESR(ucontext, &esr)) return Unknown; + return esr & ESR_ELx_WNR ? Write : Read; #elif defined(__sparc__) // Decode the instruction to determine the access type. // From OpenSolaris $SRC/uts/sun4/os/trap.c (get_accesstype). @@ -1899,7 +1899,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #endif #endif u32 instr = *(u32 *)pc; - return (instr >> 21) & 1 ? WRITE: READ; + return (instr >> 21) & 1 ? Write: Read; #elif defined(__riscv) #if SANITIZER_FREEBSD unsigned long pc = ucontext->uc_mcontext.mc_gpregs.gp_sepc; @@ -1919,7 +1919,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #if __riscv_xlen == 64 case 0b10'011: // c.ldsp (rd != x0) #endif - return rd ? SignalContext::READ : SignalContext::UNKNOWN; + return rd ? SignalContext::Read : SignalContext::Unknown; case 0b00'010: // c.lw #if __riscv_flen >= 32 && __riscv_xlen == 32 case 0b10'011: // c.flwsp @@ -1931,7 +1931,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { case 0b00'001: // c.fld case 0b10'001: // c.fldsp #endif - return SignalContext::READ; + return SignalContext::Read; case 0b00'110: // c.sw case 0b10'110: // c.swsp #if __riscv_flen >= 32 || __riscv_xlen == 64 @@ -1942,9 +1942,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { case 0b00'101: // c.fsd case 0b10'101: // c.fsdsp #endif - return SignalContext::WRITE; + return SignalContext::Write; default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } } #endif @@ -1962,9 +1962,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #endif case 0b100: // lbu case 0b101: // lhu - return SignalContext::READ; + return SignalContext::Read; default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } case 0b0100011: // stores switch (funct3) { @@ -1974,9 +1974,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #if __riscv_xlen == 64 case 0b011: // sd #endif - return SignalContext::WRITE; + return SignalContext::Write; default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } #if __riscv_flen >= 32 case 0b0000111: // floating-point loads @@ -1985,9 +1985,9 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #if __riscv_flen == 64 case 0b011: // fld #endif - return SignalContext::READ; + return SignalContext::Read; default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } case 0b0100111: // floating-point stores switch (funct3) { @@ -1995,17 +1995,17 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #if __riscv_flen == 64 case 0b011: // fsd #endif - return SignalContext::WRITE; + return SignalContext::Write; default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } #endif default: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } #else (void)ucontext; - return UNKNOWN; // FIXME: Implement. + return Unknown; // FIXME: Implement. #endif } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp index a2fc310ad1a29..3b20e1c5e2afb 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp @@ -871,9 +871,9 @@ void LogFullErrorReport(const char *buffer) { SignalContext::WriteFlag SignalContext::GetWriteFlag() const { #if defined(__x86_64__) || defined(__i386__) ucontext_t *ucontext = static_cast(context); - return ucontext->uc_mcontext->__es.__err & 2 /*T_PF_WRITE*/ ? WRITE : READ; + return ucontext->uc_mcontext->__es.__err & 2 /*T_PF_WRITE*/ ? Write : Read; #else - return UNKNOWN; + return Unknown; #endif } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp index 869c8935330d9..ac855c8be1c86 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp @@ -211,9 +211,9 @@ static void ReportDeadlySignalImpl(const SignalContext &sig, u32 tid, Report("Hint: pc points to the zero page.\n"); if (sig.is_memory_access) { const char *access_type = - sig.write_flag == SignalContext::WRITE + sig.write_flag == SignalContext::Write ? "WRITE" - : (sig.write_flag == SignalContext::READ ? "READ" : "UNKNOWN"); + : (sig.write_flag == SignalContext::Read ? "READ" : "UNKNOWN"); Report("The signal is caused by a %s memory access.\n", access_type); if (!sig.is_true_faulting_addr) Report("Hint: this fault was caused by a dereference of a high value " diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp index 87758a4904aba..7c84cdc22ce44 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp @@ -983,7 +983,7 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { // The write flag is only available for access violation exceptions. if (exception_record->ExceptionCode != EXCEPTION_ACCESS_VIOLATION) - return SignalContext::UNKNOWN; + return SignalContext::Unknown; // The contents of this array are documented at // https://docs.microsoft.com/en-us/windows/win32/api/winnt/ns-winnt-exception_record @@ -991,13 +991,13 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { // second element is the faulting address. switch (exception_record->ExceptionInformation[0]) { case 0: - return SignalContext::READ; + return SignalContext::Read; case 1: - return SignalContext::WRITE; + return SignalContext::Write; case 8: - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } - return SignalContext::UNKNOWN; + return SignalContext::Unknown; } void SignalContext::DumpAllRegisters(void *context) { From 0024f665446068af7dc24162f432c89f4e91b2a7 Mon Sep 17 00:00:00 2001 From: Muhammad Omair Javaid Date: Tue, 8 Feb 2022 20:25:41 +0500 Subject: [PATCH 080/316] [clang-cl] Bump default -fms-compatibility-version to 19.20 clang-cl MSVC required version is 19.20 now. Update the default -fms-compatibility-version to 19.20. Differential Revision: https://reviews.llvm.org/D114639 --- clang/lib/Driver/ToolChains/MSVC.cpp | 4 ++-- clang/test/Driver/cl-options.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp index 18cef288f018a..9f4751167ac12 100644 --- a/clang/lib/Driver/ToolChains/MSVC.cpp +++ b/clang/lib/Driver/ToolChains/MSVC.cpp @@ -1393,8 +1393,8 @@ VersionTuple MSVCToolChain::computeMSVCVersion(const Driver *D, if (MSVT.empty() && Args.hasFlag(options::OPT_fms_extensions, options::OPT_fno_ms_extensions, IsWindowsMSVC)) { - // -fms-compatibility-version=19.14 is default, aka 2017, 15.7 - MSVT = VersionTuple(19, 14); + // -fms-compatibility-version=19.20 is default, aka 2019, 16.x + MSVT = VersionTuple(19, 20); } return MSVT; } diff --git a/clang/test/Driver/cl-options.c b/clang/test/Driver/cl-options.c index 733e733de738e..8d240e6e6e5c6 100644 --- a/clang/test/Driver/cl-options.c +++ b/clang/test/Driver/cl-options.c @@ -757,7 +757,7 @@ // Validate that the default triple is used when run an empty tools dir is specified // RUN: %clang_cl -vctoolsdir "" -### -- %s 2>&1 | FileCheck %s --check-prefix VCTOOLSDIR -// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.14.0" +// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.20.0" // Validate that built-in include paths are based on the supplied path // RUN: %clang_cl --target=aarch64-pc-windows-msvc -vctoolsdir "/fake" -winsdkdir "/foo" -winsdkversion 10.0.12345.0 -### -- %s 2>&1 | FileCheck %s --check-prefix FAKEDIR From 4c33252b7d9ad1b52c7faa66fafeb816ab53f964 Mon Sep 17 00:00:00 2001 From: Muhammad Omair Javaid Date: Wed, 9 Feb 2022 14:26:15 +0500 Subject: [PATCH 081/316] Set LLVM_FORCE_USE_OLD_TOOLCHAIN to disable VS2019 checks VS2019 version 1920 in now the default and get tested in llvm/include/llvm/Support/Compiler.h. This patch propagates LLVM_FORCE_USE_OLD_TOOLCHAIN macro to disable testing for VS2019. Differential Revision: https://reviews.llvm.org/D114639 --- llvm/include/llvm/Config/llvm-config.h.cmake | 3 +++ llvm/include/llvm/Support/Compiler.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index 839a1c7c1984f..e8a8c20c7c7ad 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -109,4 +109,7 @@ /* Define if building LLVM with BUILD_SHARED_LIBS */ #cmakedefine LLVM_BUILD_SHARED_LIBS +/* Define if building LLVM with LLVM_FORCE_USE_OLD_TOOLCHAIN_LIBS */ +#cmakedefine LLVM_FORCE_USE_OLD_TOOLCHAIN $(LLVM_FORCE_USE_OLD_TOOLCHAIN) + #endif diff --git a/llvm/include/llvm/Support/Compiler.h b/llvm/include/llvm/Support/Compiler.h index f3317049524f3..80b2dfaec4273 100644 --- a/llvm/include/llvm/Support/Compiler.h +++ b/llvm/include/llvm/Support/Compiler.h @@ -90,9 +90,11 @@ #define LLVM_MSC_PREREQ(version) (_MSC_VER >= (version)) // We require at least VS 2019. +#if !defined(LLVM_FORCE_USE_OLD_TOOLCHAIN) #if !LLVM_MSC_PREREQ(1920) #error LLVM requires at least VS 2019. #endif +#endif #else #define LLVM_MSC_PREREQ(version) 0 From 6e7a837fdd553c51516b24e83076047343625c90 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Fri, 11 Feb 2022 09:17:33 -0500 Subject: [PATCH 082/316] [docs] Fix missing space in the GettingStarted documentation (cherry picked from commit 6a7f6e9404f5e4094f5bec3774d9345ce539db85) --- llvm/docs/GettingStarted.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst index 7d699d87491bb..3341d56171fa1 100644 --- a/llvm/docs/GettingStarted.rst +++ b/llvm/docs/GettingStarted.rst @@ -1222,7 +1222,7 @@ following options with cmake: compiling more than one project, separate the items with a semicolon. Should you run into issues with the semicolon, try surrounding it with single quotes. -* -DLLVM_ENABLE_RUNTIMES + * -DLLVM_ENABLE_RUNTIMES Set this equal to the runtimes you wish to compile (e.g. libcxx, libcxxabi, etc.) If compiling more than one runtime, separate the items with a semicolon. Should you run into issues with the semicolon, try surrounding it with single quotes. From d6f290ec136b7faef956ee2b9bfc0fe0ee0f85ab Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Thu, 10 Feb 2022 17:10:12 -0500 Subject: [PATCH 083/316] [libc++] Revert the addition of _LIBCPP_HIDE_FROM_ABI and inline in __threading_support This reverts commit 2722ac65. As explained in D115906, this was actually unnecessary and it broke the external threading configuration. Differential Revision: https://reviews.llvm.org/D119484 (cherry picked from commit c74b1924048251f65d5bd9ca3df78ce1e490a5ed) --- libcxx/include/__threading_support | 56 ------------------------------ 1 file changed, 56 deletions(-) diff --git a/libcxx/include/__threading_support b/libcxx/include/__threading_support index bf85d5f5d9f05..2db571d84c8f7 100644 --- a/libcxx/include/__threading_support +++ b/libcxx/include/__threading_support @@ -254,7 +254,6 @@ int __libcpp_tls_set(__libcpp_tls_key __key, void *__p); #if defined(_LIBCPP_HAS_THREAD_API_PTHREAD) -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_init(__libcpp_recursive_mutex_t *__m) { pthread_mutexattr_t attr; @@ -279,88 +278,74 @@ int __libcpp_recursive_mutex_init(__libcpp_recursive_mutex_t *__m) return 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_lock(__libcpp_recursive_mutex_t *__m) { return pthread_mutex_lock(__m); } -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_recursive_mutex_trylock(__libcpp_recursive_mutex_t *__m) { return pthread_mutex_trylock(__m) == 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_unlock(__libcpp_recursive_mutex_t *__m) { return pthread_mutex_unlock(__m); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_destroy(__libcpp_recursive_mutex_t *__m) { return pthread_mutex_destroy(__m); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_lock(__libcpp_mutex_t *__m) { return pthread_mutex_lock(__m); } -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_mutex_trylock(__libcpp_mutex_t *__m) { return pthread_mutex_trylock(__m) == 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_unlock(__libcpp_mutex_t *__m) { return pthread_mutex_unlock(__m); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_destroy(__libcpp_mutex_t *__m) { return pthread_mutex_destroy(__m); } // Condition Variable -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_signal(__libcpp_condvar_t *__cv) { return pthread_cond_signal(__cv); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_broadcast(__libcpp_condvar_t *__cv) { return pthread_cond_broadcast(__cv); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_wait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m) { return pthread_cond_wait(__cv, __m); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_timedwait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m, __libcpp_timespec_t *__ts) { return pthread_cond_timedwait(__cv, __m, __ts); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_destroy(__libcpp_condvar_t *__cv) { return pthread_cond_destroy(__cv); } // Execute once -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_execute_once(__libcpp_exec_once_flag *flag, void (*init_routine)()) { return pthread_once(flag, init_routine); @@ -368,40 +353,34 @@ int __libcpp_execute_once(__libcpp_exec_once_flag *flag, // Thread id // Returns non-zero if the thread ids are equal, otherwise 0 -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_id_equal(__libcpp_thread_id t1, __libcpp_thread_id t2) { return t1 == t2; } // Returns non-zero if t1 < t2, otherwise 0 -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_id_less(__libcpp_thread_id t1, __libcpp_thread_id t2) { return t1 < t2; } // Thread -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_isnull(const __libcpp_thread_t *__t) { return __libcpp_thread_get_id(__t) == 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_create(__libcpp_thread_t *__t, void *(*__func)(void *), void *__arg) { return pthread_create(__t, nullptr, __func, __arg); } -_LIBCPP_HIDE_FROM_ABI inline __libcpp_thread_id __libcpp_thread_get_current_id() { const __libcpp_thread_t thread = pthread_self(); return __libcpp_thread_get_id(&thread); } -_LIBCPP_HIDE_FROM_ABI inline __libcpp_thread_id __libcpp_thread_get_id(const __libcpp_thread_t *__t) { #if defined(__MVS__) @@ -411,25 +390,21 @@ __libcpp_thread_id __libcpp_thread_get_id(const __libcpp_thread_t *__t) #endif } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_join(__libcpp_thread_t *__t) { return pthread_join(*__t, nullptr); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_detach(__libcpp_thread_t *__t) { return pthread_detach(*__t); } -_LIBCPP_HIDE_FROM_ABI inline void __libcpp_thread_yield() { sched_yield(); } -_LIBCPP_HIDE_FROM_ABI inline void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) { __libcpp_timespec_t __ts = _VSTD::__convert_to_timespec<__libcpp_timespec_t>(__ns); @@ -437,19 +412,16 @@ void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) } // Thread local storage -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_tls_create(__libcpp_tls_key *__key, void (*__at_exit)(void *)) { return pthread_key_create(__key, __at_exit); } -_LIBCPP_HIDE_FROM_ABI inline void *__libcpp_tls_get(__libcpp_tls_key __key) { return pthread_getspecific(__key); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_tls_set(__libcpp_tls_key __key, void *__p) { return pthread_setspecific(__key, __p); @@ -457,56 +429,47 @@ int __libcpp_tls_set(__libcpp_tls_key __key, void *__p) #elif defined(_LIBCPP_HAS_THREAD_API_C11) -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_init(__libcpp_recursive_mutex_t *__m) { return mtx_init(__m, mtx_plain | mtx_recursive) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_lock(__libcpp_recursive_mutex_t *__m) { return mtx_lock(__m) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_recursive_mutex_trylock(__libcpp_recursive_mutex_t *__m) { return mtx_trylock(__m) == thrd_success; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_unlock(__libcpp_recursive_mutex_t *__m) { return mtx_unlock(__m) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_recursive_mutex_destroy(__libcpp_recursive_mutex_t *__m) { mtx_destroy(__m); return 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_lock(__libcpp_mutex_t *__m) { return mtx_lock(__m) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_mutex_trylock(__libcpp_mutex_t *__m) { return mtx_trylock(__m) == thrd_success; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_unlock(__libcpp_mutex_t *__m) { return mtx_unlock(__m) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_mutex_destroy(__libcpp_mutex_t *__m) { mtx_destroy(__m); @@ -514,25 +477,21 @@ int __libcpp_mutex_destroy(__libcpp_mutex_t *__m) } // Condition Variable -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_signal(__libcpp_condvar_t *__cv) { return cnd_signal(__cv) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_broadcast(__libcpp_condvar_t *__cv) { return cnd_broadcast(__cv) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_wait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m) { return cnd_wait(__cv, __m) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_timedwait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m, timespec *__ts) { @@ -540,7 +499,6 @@ int __libcpp_condvar_timedwait(__libcpp_condvar_t *__cv, __libcpp_mutex_t *__m, return __ec == thrd_timedout ? ETIMEDOUT : __ec; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_condvar_destroy(__libcpp_condvar_t *__cv) { cnd_destroy(__cv); @@ -548,7 +506,6 @@ int __libcpp_condvar_destroy(__libcpp_condvar_t *__cv) } // Execute once -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_execute_once(__libcpp_exec_once_flag *flag, void (*init_routine)(void)) { ::call_once(flag, init_routine); @@ -557,26 +514,22 @@ int __libcpp_execute_once(__libcpp_exec_once_flag *flag, // Thread id // Returns non-zero if the thread ids are equal, otherwise 0 -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_id_equal(__libcpp_thread_id t1, __libcpp_thread_id t2) { return thrd_equal(t1, t2) != 0; } // Returns non-zero if t1 < t2, otherwise 0 -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_id_less(__libcpp_thread_id t1, __libcpp_thread_id t2) { return t1 < t2; } // Thread -_LIBCPP_HIDE_FROM_ABI inline bool __libcpp_thread_isnull(const __libcpp_thread_t *__t) { return __libcpp_thread_get_id(__t) == 0; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_create(__libcpp_thread_t *__t, void *(*__func)(void *), void *__arg) { @@ -584,37 +537,31 @@ int __libcpp_thread_create(__libcpp_thread_t *__t, void *(*__func)(void *), return __ec == thrd_nomem ? ENOMEM : __ec; } -_LIBCPP_HIDE_FROM_ABI inline __libcpp_thread_id __libcpp_thread_get_current_id() { return thrd_current(); } -_LIBCPP_HIDE_FROM_ABI inline __libcpp_thread_id __libcpp_thread_get_id(const __libcpp_thread_t *__t) { return *__t; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_join(__libcpp_thread_t *__t) { return thrd_join(*__t, nullptr) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_thread_detach(__libcpp_thread_t *__t) { return thrd_detach(*__t) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline void __libcpp_thread_yield() { thrd_yield(); } -_LIBCPP_HIDE_FROM_ABI inline void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) { __libcpp_timespec_t __ts = _VSTD::__convert_to_timespec<__libcpp_timespec_t>(__ns); @@ -622,19 +569,16 @@ void __libcpp_thread_sleep_for(const chrono::nanoseconds& __ns) } // Thread local storage -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_tls_create(__libcpp_tls_key *__key, void (*__at_exit)(void *)) { return tss_create(__key, __at_exit) == thrd_success ? 0 : EINVAL; } -_LIBCPP_HIDE_FROM_ABI inline void *__libcpp_tls_get(__libcpp_tls_key __key) { return tss_get(__key); } -_LIBCPP_HIDE_FROM_ABI inline int __libcpp_tls_set(__libcpp_tls_key __key, void *__p) { return tss_set(__key, __p) == thrd_success ? 0 : EINVAL; From 2a2286e9859a518a46ead8e3ef5e283662766370 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 11 Feb 2022 15:23:18 -0800 Subject: [PATCH 084/316] [tsan] Make __fxstat code path glibc only This fixes Linux musl build after D118423. (cherry picked from commit da2a16f702efe3307d407d5c6db6c8c18ef6bd9b) --- compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp index 999be79c6418b..ea99c3843075a 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp @@ -1554,16 +1554,16 @@ TSAN_INTERCEPTOR(int, __fxstat, int version, int fd, void *buf) { #endif TSAN_INTERCEPTOR(int, fstat, int fd, void *buf) { -#if SANITIZER_FREEBSD || SANITIZER_MAC || SANITIZER_ANDROID || SANITIZER_NETBSD - SCOPED_TSAN_INTERCEPTOR(fstat, fd, buf); +#if SANITIZER_GLIBC + SCOPED_TSAN_INTERCEPTOR(__fxstat, 0, fd, buf); if (fd > 0) FdAccess(thr, pc, fd); - return REAL(fstat)(fd, buf); + return REAL(__fxstat)(0, fd, buf); #else - SCOPED_TSAN_INTERCEPTOR(__fxstat, 0, fd, buf); + SCOPED_TSAN_INTERCEPTOR(fstat, fd, buf); if (fd > 0) FdAccess(thr, pc, fd); - return REAL(__fxstat)(0, fd, buf); + return REAL(fstat)(fd, buf); #endif } From 2f23d4b0ac0aba4629fa484264b4e5b52bf774ca Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 9 Feb 2022 11:55:57 -0800 Subject: [PATCH 085/316] ReleaseNotes: add lld/ELF notes For the release/14.x branch. Differential Revision: https://reviews.llvm.org/D119318 --- lld/docs/ReleaseNotes.rst | 58 +++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index f611da428a8fe..ed4a374d579a3 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -30,30 +30,78 @@ ELF Improvements (`D107317 `_) * ``--why-extract`` has been added to query why archive members/lazy object files are extracted. (`D109572 `_) -* ``e_entry`` no longer falls back to the address of ``.text`` if the entry symbol does not exist. - Instead, a value of 0 will be written. - (`D110014 `_) * If ``-Map`` is specified, ``--cref`` will be printed to the specified file. (`D114663 `_) +* ``-z bti-report`` and ``-z cet-report`` are now supported. + (`D113901 `_) +* ``--lto-pgo-warn-mismatch`` has been added. + (`D104431 `_) +* Archives without an index (symbol table) are now supported and work with + ``--warn-backrefs``. One may build such an archive with ``llvm-ar rcS + [--thin]`` to save space. + (`D117284 `_) + The archive index may be `entirely ignored ` + in a future release. * No longer deduplicate local symbol names at the default optimization level of ``-O1``. This results in a larger ``.strtab`` (usually less than 1%) but a faster link - time. Use optimization level ``-O2`` to restore the deduplication. + time. Use optimization level ``-O2`` to restore the deduplication. The ``-O2`` + deduplication may be dropped in the future to help parallel ``.symtab`` write. +* In relocatable output, relocations to discarded symbols now use tombstone + values. + (`D116946 `_) +* Orphan section placement now picks a more suitable segment. Previously the + algorithm might pick a readonly segment for a writable orphan section and make + the segment writable. + (`D111717 `_) +* An empty output section moved by an ``INSERT`` comment now gets appropriate + flags. + (`D118529 `_) +* Negation in a memory region attribute is now correctly handled. + (`D113771 `_) +* ``--compress-debug-sections=zlib`` is now run in parallel. ``{clang,gcc} -gz`` link + actions are significantly faster. + (`D117853 `_) +* "relocation out of range" diagnostics and a few uncommon diagnostics + now report an object file location beside a source file location. + (`D112518 `_) +* The write of ``.rela.dyn`` and ``SHF_MERGE|SHF_STRINGS`` sections (e.g. + ``.debug_str``) is now run in parallel. Architecture specific changes: +* The AArch64 port now supports adrp+ldr and adrp+add optimizations. + ``--no-relax`` can suppress the optimization. + (`D112063 `_) + (`D117614 `_) * The x86-32 port now supports TLSDESC (``-mtls-dialect=gnu2``). (`D112582 `_) * The x86-64 port now handles non-RAX/non-adjacent ``R_X86_64_GOTPC32_TLSDESC`` and ``R_X86_64_TLSDESC_CALL`` (``-mtls-dialect=gnu2``). (`D114416 `_) +* The x86-32 and x86-64 ports now support mixed TLSDESC and TLS GD, i.e. mixing + objects compiled with and without ``-mtls-dialect=gnu2`` referencing the same + TLS variable is now supported. + (`D114416 `_) * For x86-64, ``--no-relax`` now suppresses ``R_X86_64_GOTPCRELX`` and ``R_X86_64_REX_GOTPCRELX`` GOT optimization (`D113615 `_) +* ``R_X86_64_PLTOFF64`` is now supported. + (`D112386 `_) +* ``R_AARCH64_NONE``, ``R_PPC_NONE``, and ``R_PPC64_NONE`` in input REL + relocation sections are now supported. Breaking changes ---------------- -* ... +* ``e_entry`` no longer falls back to the address of ``.text`` if the entry symbol does not exist. + Instead, a value of 0 will be written. + (`D110014 `_) +* ``--lto-pseudo-probe-for-profiling`` has been removed. In LTO, the compiler + enables this feature automatically. + (`D110209 `_) +* Use of ``--[no-]define-common``, ``-d``, ``-dc``, and ``-dp`` will now get a + warning. They will be removed or ignored in 15.0.0. + (`llvm-project#53660 `_) COFF Improvements ----------------- From 24bf96cda6cccaea4f0f95a2ce20df39a94c07ae Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 14 Feb 2022 11:52:55 -0800 Subject: [PATCH 086/316] ReleaseNotes: add some clang notes --- clang/docs/ReleaseNotes.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index c8596fcfdc989..899165b842b58 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -85,6 +85,8 @@ New Compiler Flags allow silencing warnings about unused arguments for only a subset of the command line arguments, keeping potential warnings for other arguments outside of such a region. +- ``-falign-loops=N`` (N is a power of 2) is now supported for non-LTO cases. + (`D106701 `_) Deprecated Compiler Flags ------------------------- @@ -116,9 +118,14 @@ Modified Compiler Flags - Armv9.1-A (``armv9.1-a``). - Armv9.2-A (``armv9.2-a``). +- ``-r`` now implies ``-nostdlib`` for many toolchains, matching GCC. + (`D116843 `_) + Removed Compiler Flags ------------------------- +- The legacy ``-gz=zlib-gnu`` and ``-Wa,--compress-debug-sections=zlib-gnu`` + have been removed. - ``-fno-experimental-new-pass-manager`` has been removed. ``-flegacy-pass-manager`` can be used as a makeshift, Using the legacy pass manager for the optimization pipeline was deprecated in From 4384a21fdcaa315a083db2b4b4bcd63b7e6555fc Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 14 Feb 2022 12:00:05 -0800 Subject: [PATCH 087/316] ReleaseNotes: mention removal of Intel MPX --- llvm/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index f513b620066a1..08ebd6c092f5f 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -113,6 +113,8 @@ Changes to the X86 Target During this release ... * Support for ``AVX512-FP16`` instructions has been added. +* Removed incomplete support for Intel MPX. + (`D111517 `_) Changes to the AMDGPU Target ----------------------------- From ee75c7698dc36178e60f030bbdfcbe060ced1984 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Mon, 7 Feb 2022 22:40:13 -0600 Subject: [PATCH 088/316] [Attributor][FIX] Honor alloca address space in AAPrivatizablePtr When we privatize a pointer (~argument promotion) we introduce new private allocas as replacement. These need to be placed in the alloca address space as later passes cannot properly deal with them otherwise. Fixes https://github.com/llvm/llvm-project/issues/53725 (cherry picked from commit e39b41931264d9f774dbe151bb64f4b579cf1ee0) --- .../Transforms/IPO/AttributorAttributes.cpp | 15 ++-- .../Attributor/ArgumentPromotion/alloca-as.ll | 78 +++++++++++++++++++ 2 files changed, 87 insertions(+), 6 deletions(-) create mode 100644 llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index db2ba91bea589..4e4f768ed2cbd 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -236,7 +236,8 @@ static Value *constructPointer(Type *ResTy, Type *PtrElemTy, Value *Ptr, } // Ensure the result has the requested type. - Ptr = IRB.CreateBitOrPointerCast(Ptr, ResTy, Ptr->getName() + ".cast"); + Ptr = IRB.CreatePointerBitCastOrAddrSpaceCast(Ptr, ResTy, + Ptr->getName() + ".cast"); LLVM_DEBUG(dbgs() << "Constructed pointer: " << *Ptr << "\n"); return Ptr; @@ -6748,8 +6749,8 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { Type *PrivPtrType = PrivType->getPointerTo(); if (Base->getType() != PrivPtrType) - Base = BitCastInst::CreateBitOrPointerCast(Base, PrivPtrType, "", - ACS.getInstruction()); + Base = BitCastInst::CreatePointerBitCastOrAddrSpaceCast( + Base, PrivPtrType, "", ACS.getInstruction()); // Traverse the type, build GEPs and loads. if (auto *PrivStructType = dyn_cast(PrivType)) { @@ -6816,14 +6817,16 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { Function &ReplacementFn, Function::arg_iterator ArgIt) { BasicBlock &EntryBB = ReplacementFn.getEntryBlock(); Instruction *IP = &*EntryBB.getFirstInsertionPt(); - Instruction *AI = new AllocaInst(PrivatizableType.getValue(), 0, + const DataLayout &DL = IP->getModule()->getDataLayout(); + unsigned AS = DL.getAllocaAddrSpace(); + Instruction *AI = new AllocaInst(PrivatizableType.getValue(), AS, Arg->getName() + ".priv", IP); createInitialization(PrivatizableType.getValue(), *AI, ReplacementFn, ArgIt->getArgNo(), *IP); if (AI->getType() != Arg->getType()) - AI = - BitCastInst::CreateBitOrPointerCast(AI, Arg->getType(), "", IP); + AI = BitCastInst::CreatePointerBitCastOrAddrSpaceCast( + AI, Arg->getType(), "", IP); Arg->replaceAllUsesWith(AI); for (CallInst *CI : TailCalls) diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll new file mode 100644 index 0000000000000..883e23f4eb865 --- /dev/null +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll @@ -0,0 +1,78 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM + +target datalayout = "A7" + +; Make sure we create allocas in AS 7 and cast them properly. + +define i32 @bar(i32 %arg) { +; IS________OPM-LABEL: define {{[^@]+}}@bar +; IS________OPM-SAME: (i32 [[ARG:%.*]]) { +; IS________OPM-NEXT: entry: +; IS________OPM-NEXT: [[STACK:%.*]] = alloca i32, align 4 +; IS________OPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4 +; IS________OPM-NEXT: [[CALL:%.*]] = call i32 @foo(i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[STACK]]) +; IS________OPM-NEXT: ret i32 [[CALL]] +; +; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@bar +; IS__TUNIT_NPM-SAME: (i32 [[ARG:%.*]]) { +; IS__TUNIT_NPM-NEXT: entry: +; IS__TUNIT_NPM-NEXT: [[STACK:%.*]] = alloca i32, align 4 +; IS__TUNIT_NPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4 +; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[STACK]], align 4 +; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[TMP0]]) +; IS__TUNIT_NPM-NEXT: ret i32 [[CALL]] +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@bar +; IS__CGSCC_NPM-SAME: (i32 returned [[ARG:%.*]]) { +; IS__CGSCC_NPM-NEXT: entry: +; IS__CGSCC_NPM-NEXT: [[STACK:%.*]] = alloca i32, align 4 +; IS__CGSCC_NPM-NEXT: store i32 [[ARG]], i32* [[STACK]], align 4 +; IS__CGSCC_NPM-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[ARG]]) +; IS__CGSCC_NPM-NEXT: ret i32 [[ARG]] +; +entry: + %stack = alloca i32 + store i32 %arg, i32* %stack + %call = call i32 @foo(i32* %stack) + ret i32 %call +} + +define internal i32 @foo(i32* %arg) { +; IS________OPM-LABEL: define {{[^@]+}}@foo +; IS________OPM-SAME: (i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) { +; IS________OPM-NEXT: entry: +; IS________OPM-NEXT: [[L:%.*]] = load i32, i32* [[ARG]], align 4 +; IS________OPM-NEXT: call void @use(i32 [[L]]) +; IS________OPM-NEXT: ret i32 [[L]] +; +; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@foo +; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]]) { +; IS__TUNIT_NPM-NEXT: entry: +; IS__TUNIT_NPM-NEXT: [[ARG_PRIV:%.*]] = alloca i32, align 4, addrspace(7) +; IS__TUNIT_NPM-NEXT: store i32 [[TMP0]], i32 addrspace(7)* [[ARG_PRIV]], align 4 +; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = addrspacecast i32 addrspace(7)* [[ARG_PRIV]] to i32* +; IS__TUNIT_NPM-NEXT: [[L:%.*]] = load i32, i32* [[TMP1]], align 4 +; IS__TUNIT_NPM-NEXT: call void @use(i32 [[L]]) +; IS__TUNIT_NPM-NEXT: ret i32 [[L]] +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@foo +; IS__CGSCC_NPM-SAME: (i32 returned [[TMP0:%.*]]) { +; IS__CGSCC_NPM-NEXT: entry: +; IS__CGSCC_NPM-NEXT: [[ARG_PRIV:%.*]] = alloca i32, align 4, addrspace(7) +; IS__CGSCC_NPM-NEXT: store i32 [[TMP0]], i32 addrspace(7)* [[ARG_PRIV]], align 4 +; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = addrspacecast i32 addrspace(7)* [[ARG_PRIV]] to i32* +; IS__CGSCC_NPM-NEXT: [[L:%.*]] = load i32, i32* [[TMP1]], align 4 +; IS__CGSCC_NPM-NEXT: call void @use(i32 [[TMP0]]) +; IS__CGSCC_NPM-NEXT: ret i32 [[TMP0]] +; +entry: + %l = load i32, i32* %arg + call void @use(i32 %l) + ret i32 %l +} + +declare void @use(i32) From 66c59c0e5bb7b0e89dc9e77a36be09c7f3cc8f5c Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Wed, 9 Feb 2022 16:31:38 -0800 Subject: [PATCH 089/316] [X86] Only force FP usage in the presence of pushf/popf on Win64 This ensures that the Windows unwinder will work at every instruction boundary, and allows other targets to read and write flags without setting up a frame pointer. Fixes GH-46875 Differential Revision: https://reviews.llvm.org/D119391 (cherry picked from commit f3481f43bbe2c8a24e74210d310cf3be291bf52d) --- llvm/lib/Target/X86/X86FrameLowering.cpp | 5 +- .../CodeGen/X86/x86-64-flags-intrinsics.ll | 61 ++++++++++++------- llvm/test/CodeGen/X86/x86-flags-intrinsics.ll | 16 ++--- 3 files changed, 51 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index 51f2ced321bb7..0971a0e33f98b 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -99,7 +99,7 @@ bool X86FrameLowering::hasFP(const MachineFunction &MF) const { MF.getInfo()->hasPreallocatedCall() || MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() || MFI.hasStackMap() || MFI.hasPatchPoint() || - MFI.hasCopyImplyingStackAdjustment()); + (isWin64Prologue(MF) && MFI.hasCopyImplyingStackAdjustment())); } static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) { @@ -1289,6 +1289,9 @@ bool X86FrameLowering::has128ByteRedZone(const MachineFunction& MF) const { return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone); } +/// Return true if we need to use the restricted Windows x64 prologue and +/// epilogue code patterns that can be described with WinCFI (.seh_* +/// directives). bool X86FrameLowering::isWin64Prologue(const MachineFunction &MF) const { return MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); } diff --git a/llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll b/llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll index 2cc64685552df..5460f36fca670 100644 --- a/llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll +++ b/llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll @@ -1,37 +1,54 @@ -; RUN: llc -verify-machineinstrs < %s | FileCheck %s -target triple = "x86_64-pc-win32" +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple x86_64-linux < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple x86_64-windows < %s | FileCheck %s --check-prefix=WIN64 declare i64 @llvm.x86.flags.read.u64() declare void @llvm.x86.flags.write.u64(i64) define i64 @read_flags() { +; CHECK-LABEL: read_flags: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushfq +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq +; +; WIN64-LABEL: read_flags: +; WIN64: # %bb.0: # %entry +; WIN64-NEXT: pushq %rbp +; WIN64-NEXT: .seh_pushreg %rbp +; WIN64-NEXT: movq %rsp, %rbp +; WIN64-NEXT: .seh_setframe %rbp, 0 +; WIN64-NEXT: .seh_endprologue +; WIN64-NEXT: pushfq +; WIN64-NEXT: popq %rax +; WIN64-NEXT: popq %rbp +; WIN64-NEXT: retq +; WIN64-NEXT: .seh_endproc entry: %flags = call i64 @llvm.x86.flags.read.u64() ret i64 %flags } -; CHECK-LABEL: read_flags: -; CHECK: pushq %rbp -; CHECK: .seh_pushreg %rbp -; CHECK: movq %rsp, %rbp -; CHECK: .seh_setframe %rbp, 0 -; CHECK: .seh_endprologue -; CHECK-NEXT: pushfq -; CHECK-NEXT: popq %rax -; CHECK-NEXT: popq %rbp - define void @write_flags(i64 %arg) { +; CHECK-LABEL: write_flags: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rdi +; CHECK-NEXT: popfq +; CHECK-NEXT: retq +; +; WIN64-LABEL: write_flags: +; WIN64: # %bb.0: # %entry +; WIN64-NEXT: pushq %rbp +; WIN64-NEXT: .seh_pushreg %rbp +; WIN64-NEXT: movq %rsp, %rbp +; WIN64-NEXT: .seh_setframe %rbp, 0 +; WIN64-NEXT: .seh_endprologue +; WIN64-NEXT: pushq %rcx +; WIN64-NEXT: popfq +; WIN64-NEXT: popq %rbp +; WIN64-NEXT: retq +; WIN64-NEXT: .seh_endproc entry: call void @llvm.x86.flags.write.u64(i64 %arg) ret void } - -; CHECK-LABEL: write_flags: -; CHECK: pushq %rbp -; CHECK: .seh_pushreg %rbp -; CHECK: movq %rsp, %rbp -; CHECK: .seh_setframe %rbp, 0 -; CHECK: .seh_endprologue -; CHECK-NEXT: pushq %rcx -; CHECK-NEXT: popfq -; CHECK-NEXT: popq %rbp diff --git a/llvm/test/CodeGen/X86/x86-flags-intrinsics.ll b/llvm/test/CodeGen/X86/x86-flags-intrinsics.ll index e2233aec22c7c..67cf0ef6e8b8f 100644 --- a/llvm/test/CodeGen/X86/x86-flags-intrinsics.ll +++ b/llvm/test/CodeGen/X86/x86-flags-intrinsics.ll @@ -1,6 +1,10 @@ ; RUN: llc -verify-machineinstrs < %s | FileCheck %s target triple = "i686-pc-win32" +; Check that pushf/popf intrinsics on win32 don't need a frame pointer. +; FIXME: These can't be autogenerated due to the fastcall function name label, +; it seems. + declare i32 @llvm.x86.flags.read.u32() declare void @llvm.x86.flags.write.u32(i32) @@ -11,11 +15,9 @@ entry: } ; CHECK-LABEL: _read_flags: -; CHECK: pushl %ebp -; CHECK-NEXT: movl %esp, %ebp -; CHECK-NEXT: pushfl +; CHECK: pushfl ; CHECK-NEXT: popl %eax -; CHECK-NEXT: popl %ebp +; CHECK-NEXT: retl define x86_fastcallcc void @write_flags(i32 inreg %arg) { entry: @@ -24,8 +26,6 @@ entry: } ; CHECK-LABEL: @write_flags@4: -; CHECK: pushl %ebp -; CHECK-NEXT: movl %esp, %ebp -; CHECK-NEXT: pushl %ecx +; CHECK: pushl %ecx ; CHECK-NEXT: popfl -; CHECK-NEXT: popl %ebp +; CHECK-NEXT: retl From 92f6212d3cdbb13557520c5b7172e251f8736c52 Mon Sep 17 00:00:00 2001 From: Amy Kwan Date: Fri, 11 Feb 2022 01:06:25 -0600 Subject: [PATCH 090/316] [test-release.sh] Add option to disable building clang-tools-extra during release testing. This patch adds an option (no-clang-tools) to disable building clang-tools-extra when performing release testing. Prior to this patch, clang-tools-extra was built by default, but on some platforms (such as AIX), clang-tools-extra is not supported, and so we do not normally build it. Furthermore, this change should not change the invocation for targets that build clang-tools-extra normally. Differential Revision: https://reviews.llvm.org/D119520 (cherry picked from commit db691903d268d6d56f8a028de85aa2fc0c7d48e9) --- llvm/utils/release/test-release.sh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index 41c3f3af14221..5cb7f186c530c 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -29,6 +29,7 @@ do_debug="no" do_asserts="no" do_compare="yes" do_rt="yes" +do_clang_tools="yes" do_libs="yes" do_libcxxabi="yes" do_libunwind="yes" @@ -62,6 +63,7 @@ function usage() { echo " -configure-flags FLAGS Extra flags to pass to the configure step." echo " -git-ref sha Use the specified git ref for testing instead of a release." echo " -no-rt Disable check-out & build Compiler-RT" + echo " -no-clang-tools Disable check-out & build clang-tools-extra" echo " -no-libs Disable check-out & build libcxx/libcxxabi/libunwind" echo " -no-libcxxabi Disable check-out & build libcxxabi" echo " -no-libunwind Disable check-out & build libunwind" @@ -144,6 +146,9 @@ while [ $# -gt 0 ]; do -no-libs ) do_libs="no" ;; + -no-clang-tools ) + do_clang_tools="no" + ;; -no-libcxxabi ) do_libcxxabi="no" ;; @@ -235,7 +240,10 @@ if [ -z "$NumJobs" ]; then fi # Projects list -projects="llvm clang clang-tools-extra" +projects="llvm clang" +if [ $do_clang_tools = "yes" ]; then + projects="$projects clang-tools-extra" +fi runtimes="" if [ $do_rt = "yes" ]; then runtimes="$runtimes compiler-rt" From ae88d8844673fbe7a2b7550a8cd168c7bebca99d Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Tue, 8 Feb 2022 08:32:14 -0500 Subject: [PATCH 091/316] [SDAG] move x86 select-with-identity-constant fold behind a target hook; NFC This is no-functional-change-intended because only the x86 target enables the TLI hook currently. We can add fmul/fdiv opcodes to the switch similar to the proposal D119111, but we don't need to make other changes like enabling target-specific combines. We can also add integer opcodes (add, or, shl, etc.) to the switch because this function is called from all of the generic binary opcodes. The goal is to incrementally enable the profitable diffs from D90113 while avoiding regressions. Differential Revision: https://reviews.llvm.org/D119150 (cherry picked from commit a68e098024708cba7b37d6c5a27a4003e8944142) --- llvm/include/llvm/CodeGen/TargetLowering.h | 8 ++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 70 +++++++++++++- llvm/lib/Target/X86/X86ISelLowering.cpp | 94 +++---------------- llvm/lib/Target/X86/X86ISelLowering.h | 3 + 4 files changed, 92 insertions(+), 83 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 3861648a5feba..de8b0e9cfd10b 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2851,6 +2851,14 @@ class TargetLoweringBase { return false; } + /// Return true if pulling a binary operation into a select with an identity + /// constant is profitable. This is the inverse of an IR transform. + /// Example: X + (Cond ? Y : 0) --> Cond ? (X + Y) : X + virtual bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, + EVT VT) const { + return false; + } + /// Return true if it is beneficial to convert a load of a constant to /// just the constant itself. /// On some targets it might be more efficient to use a combination of diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 041d7e5b4a4aa..6a36b7862ce95 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2101,10 +2101,77 @@ static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, VT.getTypeForEVT(*DAG.getContext()), AS); } +/// This inverts a canonicalization in IR that replaces a variable select arm +/// with an identity constant. Codegen improves if we re-use the variable +/// operand rather than load a constant. This can also be converted into a +/// masked vector operation if the target supports it. +static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, + bool ShouldCommuteOperands) { + // Match a select as operand 1. The identity constant that we are looking for + // is only valid as operand 1 of a non-commutative binop. + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + if (ShouldCommuteOperands) + std::swap(N0, N1); + + // TODO: Should this apply to scalar select too? + if (!N1.hasOneUse() || N1.getOpcode() != ISD::VSELECT) + return SDValue(); + + unsigned Opcode = N->getOpcode(); + EVT VT = N->getValueType(0); + SDValue Cond = N1.getOperand(0); + SDValue TVal = N1.getOperand(1); + SDValue FVal = N1.getOperand(2); + + // TODO: The cases should match with IR's ConstantExpr::getBinOpIdentity(). + // TODO: Target-specific opcodes could be added. Ex: "isCommutativeBinOp()". + // TODO: With fast-math (NSZ), allow the opposite-sign form of zero? + auto isIdentityConstantForOpcode = [](unsigned Opcode, SDValue V) { + if (ConstantFPSDNode *C = isConstOrConstSplatFP(V)) { + switch (Opcode) { + case ISD::FADD: // X + -0.0 --> X + return C->isZero() && C->isNegative(); + case ISD::FSUB: // X - 0.0 --> X + return C->isZero() && !C->isNegative(); + } + } + return false; + }; + + // This transform increases uses of N0, so freeze it to be safe. + // binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal) + if (isIdentityConstantForOpcode(Opcode, TVal)) { + SDValue F0 = DAG.getFreeze(N0); + SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, FVal, N->getFlags()); + return DAG.getSelect(SDLoc(N), VT, Cond, F0, NewBO); + } + // binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0 + if (isIdentityConstantForOpcode(Opcode, FVal)) { + SDValue F0 = DAG.getFreeze(N0); + SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, TVal, N->getFlags()); + return DAG.getSelect(SDLoc(N), VT, Cond, NewBO, F0); + } + + return SDValue(); +} + SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) { assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && "Unexpected binary operator"); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + auto BinOpcode = BO->getOpcode(); + EVT VT = BO->getValueType(0); + if (TLI.shouldFoldSelectWithIdentityConstant(BinOpcode, VT)) { + if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, false)) + return Sel; + + if (TLI.isCommutativeBinOp(BO->getOpcode())) + if (SDValue Sel = foldSelectWithIdentityConstant(BO, DAG, true)) + return Sel; + } + // Don't do this unless the old select is going away. We want to eliminate the // binary operator, not replace a binop with a select. // TODO: Handle ISD::SELECT_CC. @@ -2133,7 +2200,6 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) { // propagate non constant operands into select. I.e.: // and (select Cond, 0, -1), X --> select Cond, 0, X // or X, (select Cond, -1, 0) --> select Cond, -1, X - auto BinOpcode = BO->getOpcode(); bool CanFoldNonConst = (BinOpcode == ISD::AND || BinOpcode == ISD::OR) && (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) && @@ -2145,8 +2211,6 @@ SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) { !DAG.isConstantFPBuildVectorOrConstantFP(CBO)) return SDValue(); - EVT VT = BO->getValueType(0); - // We have a select-of-constants followed by a binary operator with a // constant. Eliminate the binop by pulling the constant math into the select. // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6f1fe81955952..a1c387574ebb7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -33418,6 +33418,20 @@ bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { return !(VT1 == MVT::i32 && VT2 == MVT::i16); } +bool X86TargetLowering::shouldFoldSelectWithIdentityConstant(unsigned Opcode, + EVT VT) const { + // TODO: This is too general. There are cases where pre-AVX512 codegen would + // benefit. The transform may also be profitable for scalar code. + if (!Subtarget.hasAVX512()) + return false; + if (!Subtarget.hasVLX() && !VT.is512BitVector()) + return false; + if (!VT.isVector()) + return false; + + return true; +} + /// Targets can use this to indicate that they only support *some* /// VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values @@ -48920,83 +48934,6 @@ static SDValue combineFaddCFmul(SDNode *N, SelectionDAG &DAG, return DAG.getBitcast(VT, CFmul); } -/// This inverts a canonicalization in IR that replaces a variable select arm -/// with an identity constant. Codegen improves if we re-use the variable -/// operand rather than load a constant. This can also be converted into a -/// masked vector operation if the target supports it. -static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, - bool ShouldCommuteOperands) { - // Match a select as operand 1. The identity constant that we are looking for - // is only valid as operand 1 of a non-commutative binop. - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - if (ShouldCommuteOperands) - std::swap(N0, N1); - - // TODO: Should this apply to scalar select too? - if (!N1.hasOneUse() || N1.getOpcode() != ISD::VSELECT) - return SDValue(); - - unsigned Opcode = N->getOpcode(); - EVT VT = N->getValueType(0); - SDValue Cond = N1.getOperand(0); - SDValue TVal = N1.getOperand(1); - SDValue FVal = N1.getOperand(2); - - // TODO: This (and possibly the entire function) belongs in a - // target-independent location with target hooks. - // TODO: The cases should match with IR's ConstantExpr::getBinOpIdentity(). - // TODO: With fast-math (NSZ), allow the opposite-sign form of zero? - auto isIdentityConstantForOpcode = [](unsigned Opcode, SDValue V) { - if (ConstantFPSDNode *C = isConstOrConstSplatFP(V)) { - switch (Opcode) { - case ISD::FADD: // X + -0.0 --> X - return C->isZero() && C->isNegative(); - case ISD::FSUB: // X - 0.0 --> X - return C->isZero() && !C->isNegative(); - } - } - return false; - }; - - // This transform increases uses of N0, so freeze it to be safe. - // binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal) - if (isIdentityConstantForOpcode(Opcode, TVal)) { - SDValue F0 = DAG.getFreeze(N0); - SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, FVal, N->getFlags()); - return DAG.getSelect(SDLoc(N), VT, Cond, F0, NewBO); - } - // binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0 - if (isIdentityConstantForOpcode(Opcode, FVal)) { - SDValue F0 = DAG.getFreeze(N0); - SDValue NewBO = DAG.getNode(Opcode, SDLoc(N), VT, F0, TVal, N->getFlags()); - return DAG.getSelect(SDLoc(N), VT, Cond, NewBO, F0); - } - - return SDValue(); -} - -static SDValue combineBinopWithSelect(SDNode *N, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { - // TODO: This is too general. There are cases where pre-AVX512 codegen would - // benefit. The transform may also be profitable for scalar code. - if (!Subtarget.hasAVX512()) - return SDValue(); - - if (!Subtarget.hasVLX() && !N->getValueType(0).is512BitVector()) - return SDValue(); - - if (SDValue Sel = foldSelectWithIdentityConstant(N, DAG, false)) - return Sel; - - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.isCommutativeBinOp(N->getOpcode())) - if (SDValue Sel = foldSelectWithIdentityConstant(N, DAG, true)) - return Sel; - - return SDValue(); -} - /// Do target-specific dag combines on floating-point adds/subs. static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG, const X86Subtarget &Subtarget) { @@ -49006,9 +48943,6 @@ static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG, if (SDValue COp = combineFaddCFmul(N, DAG, Subtarget)) return COp; - if (SDValue Sel = combineBinopWithSelect(N, DAG, Subtarget)) - return Sel; - return SDValue(); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 3f6d567d3f4de..50c7e2c319f63 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1288,6 +1288,9 @@ namespace llvm { /// from i32 to i8 but not from i32 to i16. bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; + bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, + EVT VT) const override; + /// Given an intrinsic, checks if on the target the intrinsic will need to map /// to a MemIntrinsicNode (touches memory). If this is the case, it returns /// true and stores the intrinsic information into the IntrinsicInfo that was From a42f1f88f1361bd010fbec932d70f698853488ec Mon Sep 17 00:00:00 2001 From: Jameson Nash Date: Mon, 7 Feb 2022 18:46:33 -0500 Subject: [PATCH 092/316] replace clang LLVM_ENABLE_PLUGINS -> CLANG_PLUGIN_SUPPORT in tests Ensure CLANG_PLUGIN_SUPPORT is compatible with llvm_add_library. Fixes an issue noted in D111100. Differential Revision: https://reviews.llvm.org/D119199 (cherry picked from commit 76cad51ba700233d6e3492eddcbb466b6adbc2eb) --- clang-tools-extra/test/CMakeLists.txt | 13 +++++++++++-- clang-tools-extra/test/lit.site.cfg.py.in | 2 +- clang/CMakeLists.txt | 4 ++++ clang/examples/AnnotateFunctions/CMakeLists.txt | 2 +- clang/examples/Attribute/CMakeLists.txt | 2 +- clang/examples/CallSuperAttribute/CMakeLists.txt | 2 +- clang/examples/PluginsOrder/CMakeLists.txt | 2 +- clang/examples/PrintFunctionNames/CMakeLists.txt | 2 +- clang/lib/Analysis/plugins/CMakeLists.txt | 2 +- clang/test/CMakeLists.txt | 4 ++-- clang/test/lit.site.cfg.py.in | 2 +- clang/tools/driver/CMakeLists.txt | 2 -- 12 files changed, 25 insertions(+), 14 deletions(-) diff --git a/clang-tools-extra/test/CMakeLists.txt b/clang-tools-extra/test/CMakeLists.txt index 9321457ae1a39..170e5f8bd197d 100644 --- a/clang-tools-extra/test/CMakeLists.txt +++ b/clang-tools-extra/test/CMakeLists.txt @@ -17,7 +17,7 @@ string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} CLANG_TOOLS_DIR ${LLVM_RUN llvm_canonicalize_cmake_booleans( CLANG_TIDY_ENABLE_STATIC_ANALYZER - LLVM_ENABLE_PLUGINS + CLANG_PLUGIN_SUPPORT LLVM_INSTALL_TOOLCHAIN_ONLY ) @@ -87,10 +87,19 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY) PLUGIN_TOOL clang-tidy DEPENDS clang-tidy-headers) + if(CLANG_BUILT_STANDALONE) + # LLVMHello library is needed below + if (EXISTS ${LLVM_MAIN_SRC_DIR}/lib/Transforms/Hello + AND NOT TARGET LLVMHello) + add_subdirectory(${LLVM_MAIN_SRC_DIR}/lib/Transforms/Hello + lib/Transforms/Hello) + endif() + endif() + if(TARGET CTTestTidyModule) list(APPEND CLANG_TOOLS_TEST_DEPS CTTestTidyModule LLVMHello) target_include_directories(CTTestTidyModule PUBLIC BEFORE "${CLANG_TOOLS_SOURCE_DIR}") - if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) + if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang-tools-extra/test/lit.site.cfg.py.in b/clang-tools-extra/test/lit.site.cfg.py.in index e7db0e2ef2cb8..d30e6664816b7 100644 --- a/clang-tools-extra/test/lit.site.cfg.py.in +++ b/clang-tools-extra/test/lit.site.cfg.py.in @@ -12,7 +12,7 @@ config.clang_libs_dir = "@SHLIBDIR@" config.python_executable = "@Python3_EXECUTABLE@" config.target_triple = "@TARGET_TRIPLE@" config.clang_tidy_staticanalyzer = @CLANG_TIDY_ENABLE_STATIC_ANALYZER@ -config.has_plugins = @LLVM_ENABLE_PLUGINS@ & ~@LLVM_INSTALL_TOOLCHAIN_ONLY@ +config.has_plugins = @CLANG_PLUGIN_SUPPORT@ & ~@LLVM_INSTALL_TOOLCHAIN_ONLY@ # Support substitution of the tools and libs dirs with user parameters. This is # used when we can't determine the tool dir at configuration time. diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index 1cc9bacf4e5eb..4225c028e1794 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -476,6 +476,10 @@ add_definitions( -D_GNU_SOURCE ) option(CLANG_BUILD_TOOLS "Build the Clang tools. If OFF, just generate build targets." ON) +CMAKE_DEPENDENT_OPTION(CLANG_PLUGIN_SUPPORT + "Build clang with plugin support" ON + "LLVM_ENABLE_PLUGINS OR LLVM_EXPORT_SYMBOLS_FOR_PLUGINS" OFF) + option(CLANG_ENABLE_ARCMT "Build ARCMT." ON) option(CLANG_ENABLE_STATIC_ANALYZER "Include static analyzer in clang binary." ON) diff --git a/clang/examples/AnnotateFunctions/CMakeLists.txt b/clang/examples/AnnotateFunctions/CMakeLists.txt index e9850b64f08d7..e6541f7cc62a6 100644 --- a/clang/examples/AnnotateFunctions/CMakeLists.txt +++ b/clang/examples/AnnotateFunctions/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(AnnotateFunctions MODULE AnnotateFunctions.cpp PLUGIN_TOOL clang) -if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) +if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/Attribute/CMakeLists.txt b/clang/examples/Attribute/CMakeLists.txt index 42f04f5039bc7..5392ac0df1703 100644 --- a/clang/examples/Attribute/CMakeLists.txt +++ b/clang/examples/Attribute/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(Attribute MODULE Attribute.cpp PLUGIN_TOOL clang) -if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) +if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) target_link_libraries(Attribute PRIVATE clangAST clangBasic diff --git a/clang/examples/CallSuperAttribute/CMakeLists.txt b/clang/examples/CallSuperAttribute/CMakeLists.txt index 922f0cfa797a8..f4284adf289e3 100644 --- a/clang/examples/CallSuperAttribute/CMakeLists.txt +++ b/clang/examples/CallSuperAttribute/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(CallSuperAttr MODULE CallSuperAttrInfo.cpp PLUGIN_TOOL clang) -if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) +if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/PluginsOrder/CMakeLists.txt b/clang/examples/PluginsOrder/CMakeLists.txt index 289e234ac28c4..612587a6d2fe3 100644 --- a/clang/examples/PluginsOrder/CMakeLists.txt +++ b/clang/examples/PluginsOrder/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(PluginsOrder MODULE PluginsOrder.cpp PLUGIN_TOOL clang) -if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) +if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/PrintFunctionNames/CMakeLists.txt b/clang/examples/PrintFunctionNames/CMakeLists.txt index 63b0c015732c3..67f1b16744eaf 100644 --- a/clang/examples/PrintFunctionNames/CMakeLists.txt +++ b/clang/examples/PrintFunctionNames/CMakeLists.txt @@ -11,7 +11,7 @@ endif() add_llvm_library(PrintFunctionNames MODULE PrintFunctionNames.cpp PLUGIN_TOOL clang) -if(LLVM_ENABLE_PLUGINS AND (WIN32 OR CYGWIN)) +if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/lib/Analysis/plugins/CMakeLists.txt b/clang/lib/Analysis/plugins/CMakeLists.txt index bd7314a871fc5..7b754ea3f2bc9 100644 --- a/clang/lib/Analysis/plugins/CMakeLists.txt +++ b/clang/lib/Analysis/plugins/CMakeLists.txt @@ -1,4 +1,4 @@ -if(CLANG_ENABLE_STATIC_ANALYZER AND LLVM_ENABLE_PLUGINS) +if(CLANG_ENABLE_STATIC_ANALYZER AND CLANG_PLUGIN_SUPPORT) add_subdirectory(SampleAnalyzer) add_subdirectory(CheckerDependencyHandling) add_subdirectory(CheckerOptionHandling) diff --git a/clang/test/CMakeLists.txt b/clang/test/CMakeLists.txt index 07de12b7c190b..cbe7c787a1a26 100644 --- a/clang/test/CMakeLists.txt +++ b/clang/test/CMakeLists.txt @@ -14,12 +14,12 @@ llvm_canonicalize_cmake_booleans( CLANG_DEFAULT_PIE_ON_LINUX CLANG_ENABLE_ARCMT CLANG_ENABLE_STATIC_ANALYZER + CLANG_PLUGIN_SUPPORT CLANG_SPAWN_CC1 ENABLE_BACKTRACES LLVM_ENABLE_NEW_PASS_MANAGER LLVM_ENABLE_ZLIB LLVM_ENABLE_PER_TARGET_RUNTIME_DIR - LLVM_ENABLE_PLUGINS LLVM_ENABLE_THREADS LLVM_WITH_Z3 ) @@ -145,7 +145,7 @@ if( NOT CLANG_BUILT_STANDALONE ) endif() if (CLANG_ENABLE_STATIC_ANALYZER) - if (LLVM_ENABLE_PLUGINS) + if (CLANG_PLUGIN_SUPPORT) list(APPEND CLANG_TEST_DEPS SampleAnalyzerPlugin CheckerDependencyHandlingAnalyzerPlugin diff --git a/clang/test/lit.site.cfg.py.in b/clang/test/lit.site.cfg.py.in index bc3022d2bee9a..1e2e331d54db9 100644 --- a/clang/test/lit.site.cfg.py.in +++ b/clang/test/lit.site.cfg.py.in @@ -34,7 +34,7 @@ config.enable_threads = @LLVM_ENABLE_THREADS@ config.host_arch = "@HOST_ARCH@" config.python_executable = "@Python3_EXECUTABLE@" config.use_z3_solver = lit_config.params.get('USE_Z3_SOLVER', "@USE_Z3_SOLVER@") -config.has_plugins = @LLVM_ENABLE_PLUGINS@ +config.has_plugins = @CLANG_PLUGIN_SUPPORT@ config.clang_vendor_uti = "@CLANG_VENDOR_UTI@" config.llvm_external_lit = path(r"@LLVM_EXTERNAL_LIT@") diff --git a/clang/tools/driver/CMakeLists.txt b/clang/tools/driver/CMakeLists.txt index 52d439ce6a3b6..6b3e159d1b648 100644 --- a/clang/tools/driver/CMakeLists.txt +++ b/clang/tools/driver/CMakeLists.txt @@ -17,8 +17,6 @@ set( LLVM_LINK_COMPONENTS Vectorize ) -option(CLANG_PLUGIN_SUPPORT "Build clang with plugin support" ON) - # Support plugins. if(CLANG_PLUGIN_SUPPORT) set(support_plugins SUPPORT_PLUGINS) From 67e0b64c0e6c769126b354b39bc5fa3f5d9d73d1 Mon Sep 17 00:00:00 2001 From: Marek Kurdej Date: Wed, 9 Feb 2022 21:58:22 +0100 Subject: [PATCH 093/316] [clang-format] Honour "// clang-format off" when using QualifierOrder. Fixes https://github.com/llvm/llvm-project/issues/53643. Reviewed By: MyDeveloperDay, HazardyKnusperkeks, owenpan Differential Revision: https://reviews.llvm.org/D119218 (cherry picked from commit e329b5866f1732f5c24cf2ae96479971f7101914) --- clang/lib/Format/QualifierAlignmentFixer.cpp | 4 ++++ clang/unittests/Format/QualifierFixerTest.cpp | 22 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/clang/lib/Format/QualifierAlignmentFixer.cpp b/clang/lib/Format/QualifierAlignmentFixer.cpp index b3a4684bead1a..0142a6c08ed30 100644 --- a/clang/lib/Format/QualifierAlignmentFixer.cpp +++ b/clang/lib/Format/QualifierAlignmentFixer.cpp @@ -396,6 +396,10 @@ LeftRightQualifierAlignmentFixer::analyze( for (AnnotatedLine *Line : AnnotatedLines) { FormatToken *First = Line->First; + assert(First); + if (First->Finalized) + continue; + const auto *Last = Line->Last; for (const auto *Tok = First; Tok && Tok != Last && Tok->Next; diff --git a/clang/unittests/Format/QualifierFixerTest.cpp b/clang/unittests/Format/QualifierFixerTest.cpp index 0517de2820d9d..14f09d875e6be 100755 --- a/clang/unittests/Format/QualifierFixerTest.cpp +++ b/clang/unittests/Format/QualifierFixerTest.cpp @@ -858,5 +858,27 @@ TEST_F(QualifierFixerTest, QualifierTemplates) { Style); } +TEST_F(QualifierFixerTest, DisableRegions) { + FormatStyle Style = getLLVMStyle(); + Style.QualifierAlignment = FormatStyle::QAS_Custom; + Style.QualifierOrder = {"inline", "static", "const", "type"}; + + ReplacementCount = 0; + verifyFormat("// clang-format off\n" + "int const inline static a = 0;\n" + "// clang-format on\n", + Style); + EXPECT_EQ(ReplacementCount, 0); + verifyFormat("// clang-format off\n" + "int const inline static a = 0;\n" + "// clang-format on\n" + "inline static const int a = 0;\n", + "// clang-format off\n" + "int const inline static a = 0;\n" + "// clang-format on\n" + "int const inline static a = 0;\n", + Style); +} + } // namespace format } // namespace clang From 8b3ba440a2f0e7539574395d9bed209646d341e4 Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Wed, 2 Feb 2022 10:23:02 +0000 Subject: [PATCH 094/316] [OpenCL] Test -fdeclare-opencl-builtins with CL3 and CLC++2021 But only test in combination with -finclude-default-header, as the headerless tests may be dropped soon. (cherry picked from commit e0e6f3a6a2e13ee11b014ca45a48997e78d3efc5) --- clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl b/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl index 8c5863987be68..d1a4f72837260 100644 --- a/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl +++ b/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl @@ -4,8 +4,10 @@ // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL1.2 -fdeclare-opencl-builtins -finclude-default-header // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL2.0 -fdeclare-opencl-builtins -DNO_HEADER // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL2.0 -fdeclare-opencl-builtins -finclude-default-header +// RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL3.0 -fdeclare-opencl-builtins -finclude-default-header // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC++ -fdeclare-opencl-builtins -DNO_HEADER // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC++ -fdeclare-opencl-builtins -finclude-default-header +// RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC++2021 -fdeclare-opencl-builtins -finclude-default-header // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL2.0 -fdeclare-opencl-builtins -finclude-default-header -cl-ext=-cl_khr_fp64 -DNO_FP64 // Test the -fdeclare-opencl-builtins option. This is not a completeness From 174dffbae24fbad842603c1d32d3c70c0b9783ae Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Thu, 3 Feb 2022 11:09:41 +0000 Subject: [PATCH 095/316] [OpenCL] Move most _explicit atomics into multiclass; NFC This will simplify future conditionalization for OpenCL 3.0 optionality of atomic features. The only set of atomic functions not using the multiclass is atomic_compare_exchange_strong/weak, as these don't fit the common pattern due to having 2 MemoryOrder arguments. (cherry picked from commit d97a4dfea6c2781494f6fe54ce265128f5c08dc2) --- clang/lib/Sema/OpenCLBuiltins.td | 216 +++++++------------------------ 1 file changed, 46 insertions(+), 170 deletions(-) diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index cd704ba2df13d..516653681331e 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -1040,6 +1040,18 @@ let Extension = FuncExtOpenCLCxx in { } } +// An atomic builtin with 2 additional _explicit variants. +multiclass BuiltinAtomicExplicit Types> { + // Without explicit MemoryOrder or MemoryScope. + def : Builtin; + + // With an explicit MemoryOrder argument. + def : Builtin; + + // With explicit MemoryOrder and MemoryScope arguments. + def : Builtin; +} + // OpenCL v2.0 s6.13.11 - Atomic Functions. let MinVersion = CL20 in { def : Builtin<"atomic_work_item_fence", [Void, MemFenceFlags, MemoryOrder, MemoryScope]>; @@ -1049,24 +1061,12 @@ let MinVersion = CL20 in { [AtomicFloat, Float], [AtomicDouble, Double]] in { def : Builtin<"atomic_init", [Void, PointerType, GenericAS>, TypePair[1]]>; - def : Builtin<"atomic_store", + defm : BuiltinAtomicExplicit<"atomic_store", [Void, PointerType, GenericAS>, TypePair[1]]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GenericAS>, TypePair[1], MemoryOrder]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GenericAS>, TypePair[1], MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_load", + defm : BuiltinAtomicExplicit<"atomic_load", [TypePair[1], PointerType, GenericAS>]>; - def : Builtin<"atomic_load_explicit", - [TypePair[1], PointerType, GenericAS>, MemoryOrder]>; - def : Builtin<"atomic_load_explicit", - [TypePair[1], PointerType, GenericAS>, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_exchange", + defm : BuiltinAtomicExplicit<"atomic_exchange", [TypePair[1], PointerType, GenericAS>, TypePair[1]]>; - def : Builtin<"atomic_exchange_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[1], MemoryOrder]>; - def : Builtin<"atomic_exchange_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[1], MemoryOrder, MemoryScope]>; foreach Variant = ["weak", "strong"] in { def : Builtin<"atomic_compare_exchange_" # Variant, [Bool, PointerType, GenericAS>, @@ -1084,249 +1084,125 @@ let MinVersion = CL20 in { [AtomicLong, Long, Long], [AtomicULong, ULong, ULong], [AtomicUIntPtr, UIntPtr, PtrDiff]] in { foreach ModOp = ["add", "sub"] in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [TypePair[1], PointerType, GenericAS>, TypePair[2]]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[2], MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[2], MemoryOrder, MemoryScope]>; } } foreach TypePair = [[AtomicInt, Int, Int], [AtomicUInt, UInt, UInt], [AtomicLong, Long, Long], [AtomicULong, ULong, ULong]] in { foreach ModOp = ["or", "xor", "and", "min", "max"] in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [TypePair[1], PointerType, GenericAS>, TypePair[2]]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[2], MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [TypePair[1], PointerType, GenericAS>, TypePair[2], MemoryOrder, MemoryScope]>; } } - def : Builtin<"atomic_flag_clear", + defm : BuiltinAtomicExplicit<"atomic_flag_clear", [Void, PointerType, GenericAS>]>; - def : Builtin<"atomic_flag_clear_explicit", - [Void, PointerType, GenericAS>, MemoryOrder]>; - def : Builtin<"atomic_flag_clear_explicit", - [Void, PointerType, GenericAS>, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_flag_test_and_set", + defm : BuiltinAtomicExplicit<"atomic_flag_test_and_set", [Bool, PointerType, GenericAS>]>; - def : Builtin<"atomic_flag_test_and_set_explicit", - [Bool, PointerType, GenericAS>, MemoryOrder]>; - def : Builtin<"atomic_flag_test_and_set_explicit", - [Bool, PointerType, GenericAS>, MemoryOrder, MemoryScope]>; } // The functionality added by cl_ext_float_atomics extension let MinVersion = CL20 in { let Extension = FuncExtFloatAtomicsFp16GlobalLoadStore in { - def : Builtin<"atomic_store", + defm : BuiltinAtomicExplicit<"atomic_store", [Void, PointerType, GlobalAS>, AtomicHalf]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GlobalAS>, AtomicHalf, MemoryOrder]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GlobalAS>, AtomicHalf, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_load", + defm : BuiltinAtomicExplicit<"atomic_load", [Half, PointerType, GlobalAS>]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, GlobalAS>, MemoryOrder]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, GlobalAS>, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_exchange", + defm : BuiltinAtomicExplicit<"atomic_exchange", [Half, PointerType, GlobalAS>, Half]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16LocalLoadStore in { - def : Builtin<"atomic_store", + defm : BuiltinAtomicExplicit<"atomic_store", [Void, PointerType, LocalAS>, AtomicHalf]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, LocalAS>, AtomicHalf, MemoryOrder]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, LocalAS>, AtomicHalf, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_load", + defm : BuiltinAtomicExplicit<"atomic_load", [Half, PointerType, LocalAS>]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, LocalAS>, MemoryOrder]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, LocalAS>, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_exchange", + defm : BuiltinAtomicExplicit<"atomic_exchange", [Half, PointerType, LocalAS>, Half]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16GenericLoadStore in { - def : Builtin<"atomic_store", + defm : BuiltinAtomicExplicit<"atomic_store", [Void, PointerType, GenericAS>, AtomicHalf]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GenericAS>, AtomicHalf, MemoryOrder]>; - def : Builtin<"atomic_store_explicit", - [Void, PointerType, GenericAS>, AtomicHalf, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_load", + defm : BuiltinAtomicExplicit<"atomic_load", [Half, PointerType, GenericAS>]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, GenericAS>, MemoryOrder]>; - def : Builtin<"atomic_load_explicit", - [Half, PointerType, GenericAS>, MemoryOrder, MemoryScope]>; - def : Builtin<"atomic_exchange", + defm : BuiltinAtomicExplicit<"atomic_exchange", [Half, PointerType, GenericAS>, Half]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_exchange_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder, MemoryScope]>; } foreach ModOp = ["add", "sub"] in { let Extension = FuncExtFloatAtomicsFp16GlobalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, GlobalAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32GlobalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, GlobalAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GlobalAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GlobalAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64GlobalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, GlobalAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GlobalAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GlobalAS>, Double, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16LocalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, LocalAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32LocalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, LocalAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, LocalAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, LocalAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64LocalAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, LocalAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, LocalAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, LocalAS>, Double, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16GenericAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, GenericAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32GenericAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, GenericAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GenericAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GenericAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64GenericAdd in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, GenericAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GenericAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GenericAS>, Double, MemoryOrder, MemoryScope]>; } } foreach ModOp = ["min", "max"] in { let Extension = FuncExtFloatAtomicsFp16GlobalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, GlobalAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GlobalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32GlobalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, GlobalAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GlobalAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GlobalAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64GlobalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, GlobalAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GlobalAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GlobalAS>, Double, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16LocalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, LocalAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, LocalAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32LocalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, LocalAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, LocalAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, LocalAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64LocalMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, LocalAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, LocalAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, LocalAS>, Double, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp16GenericMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Half, PointerType, GenericAS>, Half]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Half, PointerType, GenericAS>, Half, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp32GenericMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Float, PointerType, GenericAS>, Float]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GenericAS>, Float, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Float, PointerType, GenericAS>, Float, MemoryOrder, MemoryScope]>; } let Extension = FuncExtFloatAtomicsFp64GenericMinMax in { - def : Builtin<"atomic_fetch_" # ModOp, + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, [Double, PointerType, GenericAS>, Double]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GenericAS>, Double, MemoryOrder]>; - def : Builtin<"atomic_fetch_" # ModOp # "_explicit", - [Double, PointerType, GenericAS>, Double, MemoryOrder, MemoryScope]>; } } } From 865a18c94d50b6bd79c31e05a5c142846182c998 Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Fri, 4 Feb 2022 10:17:48 +0000 Subject: [PATCH 096/316] [OpenCL] Move OpenCL 2.0 atomics into multiclass; NFC This is in preparation for adding the OpenCL 3.0 builtins with named address space arguments. (cherry picked from commit 31fa3a4d44316fd36e11f92729ea9596ee3bf3f8) --- clang/lib/Sema/OpenCLBuiltins.td | 42 ++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index 516653681331e..08f8630a67e22 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -1040,6 +1040,8 @@ let Extension = FuncExtOpenCLCxx in { } } +// OpenCL v2.0 s6.13.11 - Atomic Functions. + // An atomic builtin with 2 additional _explicit variants. multiclass BuiltinAtomicExplicit Types> { // Without explicit MemoryOrder or MemoryScope. @@ -1052,31 +1054,29 @@ multiclass BuiltinAtomicExplicit Types> { def : Builtin; } -// OpenCL v2.0 s6.13.11 - Atomic Functions. -let MinVersion = CL20 in { - def : Builtin<"atomic_work_item_fence", [Void, MemFenceFlags, MemoryOrder, MemoryScope]>; - +// OpenCL 2.0 atomic functions that have a pointer argument in a given address space. +multiclass OpenCL2Atomics { foreach TypePair = [[AtomicInt, Int], [AtomicUInt, UInt], [AtomicLong, Long], [AtomicULong, ULong], [AtomicFloat, Float], [AtomicDouble, Double]] in { def : Builtin<"atomic_init", - [Void, PointerType, GenericAS>, TypePair[1]]>; + [Void, PointerType, addrspace>, TypePair[1]]>; defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, GenericAS>, TypePair[1]]>; + [Void, PointerType, addrspace>, TypePair[1]]>; defm : BuiltinAtomicExplicit<"atomic_load", - [TypePair[1], PointerType, GenericAS>]>; + [TypePair[1], PointerType, addrspace>]>; defm : BuiltinAtomicExplicit<"atomic_exchange", - [TypePair[1], PointerType, GenericAS>, TypePair[1]]>; + [TypePair[1], PointerType, addrspace>, TypePair[1]]>; foreach Variant = ["weak", "strong"] in { def : Builtin<"atomic_compare_exchange_" # Variant, - [Bool, PointerType, GenericAS>, - PointerType, TypePair[1]]>; + [Bool, PointerType, addrspace>, + PointerType, TypePair[1]]>; def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", - [Bool, PointerType, GenericAS>, - PointerType, TypePair[1], MemoryOrder, MemoryOrder]>; + [Bool, PointerType, addrspace>, + PointerType, TypePair[1], MemoryOrder, MemoryOrder]>; def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", - [Bool, PointerType, GenericAS>, - PointerType, TypePair[1], MemoryOrder, MemoryOrder, MemoryScope]>; + [Bool, PointerType, addrspace>, + PointerType, TypePair[1], MemoryOrder, MemoryOrder, MemoryScope]>; } } @@ -1085,22 +1085,28 @@ let MinVersion = CL20 in { [AtomicUIntPtr, UIntPtr, PtrDiff]] in { foreach ModOp = ["add", "sub"] in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [TypePair[1], PointerType, GenericAS>, TypePair[2]]>; + [TypePair[1], PointerType, addrspace>, TypePair[2]]>; } } foreach TypePair = [[AtomicInt, Int, Int], [AtomicUInt, UInt, UInt], [AtomicLong, Long, Long], [AtomicULong, ULong, ULong]] in { foreach ModOp = ["or", "xor", "and", "min", "max"] in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [TypePair[1], PointerType, GenericAS>, TypePair[2]]>; + [TypePair[1], PointerType, addrspace>, TypePair[2]]>; } } defm : BuiltinAtomicExplicit<"atomic_flag_clear", - [Void, PointerType, GenericAS>]>; + [Void, PointerType, addrspace>]>; defm : BuiltinAtomicExplicit<"atomic_flag_test_and_set", - [Bool, PointerType, GenericAS>]>; + [Bool, PointerType, addrspace>]>; +} + +let MinVersion = CL20 in { + def : Builtin<"atomic_work_item_fence", [Void, MemFenceFlags, MemoryOrder, MemoryScope]>; + + defm : OpenCL2Atomics; } // The functionality added by cl_ext_float_atomics extension From 84260978cbf52485d9347e20386fda6bb82df763 Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Wed, 9 Feb 2022 10:47:45 +0000 Subject: [PATCH 097/316] [OpenCL] Fix atomic_fetch_add/sub with half type An error in the tablegen description affects the declarations provided by `-fdeclare-opencl-builtins` for `atomic_fetch_add` and `atomic_fetch_sub`. The atomic argument should be an atomic_half, not an atomic_float. (cherry picked from commit fe690587bedb23dec2753549d4216059a7f894a1) --- clang/lib/Sema/OpenCLBuiltins.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index 08f8630a67e22..60a05f95fbec8 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -1138,7 +1138,7 @@ let MinVersion = CL20 in { foreach ModOp = ["add", "sub"] in { let Extension = FuncExtFloatAtomicsFp16GlobalAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GlobalAS>, Half]>; + [Half, PointerType, GlobalAS>, Half]>; } let Extension = FuncExtFloatAtomicsFp32GlobalAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, @@ -1150,7 +1150,7 @@ let MinVersion = CL20 in { } let Extension = FuncExtFloatAtomicsFp16LocalAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, LocalAS>, Half]>; + [Half, PointerType, LocalAS>, Half]>; } let Extension = FuncExtFloatAtomicsFp32LocalAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, @@ -1162,7 +1162,7 @@ let MinVersion = CL20 in { } let Extension = FuncExtFloatAtomicsFp16GenericAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GenericAS>, Half]>; + [Half, PointerType, GenericAS>, Half]>; } let Extension = FuncExtFloatAtomicsFp32GenericAdd in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, From f4c48b2015cb3045962695b6e9e9fa7545b2895b Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Thu, 10 Feb 2022 09:43:32 +0000 Subject: [PATCH 098/316] [OpenCL] Refactor cl_ext_float_atomics declarations; NFC Reduce the amount of repetition in the declarations by leveraging more TableGen constructs. This is in preparation for adding the OpenCL 3.0 atomics feature optionality. (cherry picked from commit 8d37043520f57e63e032c9d0ba4cba8701a3cd35) --- clang/lib/Sema/OpenCLBuiltins.td | 172 ++++++++++--------------------- 1 file changed, 55 insertions(+), 117 deletions(-) diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index 60a05f95fbec8..4d36df352d5ec 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -90,27 +90,27 @@ def FuncExtOpenCLCNamedAddressSpaceBuiltins : FunctionExtension<"__opencl_c_name def FuncExtOpenCLCPipes : FunctionExtension<"__opencl_c_pipes">; def FuncExtOpenCLCWGCollectiveFunctions : FunctionExtension<"__opencl_c_work_group_collective_functions">; def FuncExtOpenCLCReadWriteImages : FunctionExtension<"__opencl_c_read_write_images">; -def FuncExtFloatAtomicsFp16GlobalLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_load_store">; -def FuncExtFloatAtomicsFp16LocalLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_load_store">; -def FuncExtFloatAtomicsFp16GenericLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_load_store __opencl_c_ext_fp16_local_atomic_load_store">; -def FuncExtFloatAtomicsFp16GlobalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_add">; -def FuncExtFloatAtomicsFp32GlobalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_global_atomic_add">; -def FuncExtFloatAtomicsFp64GlobalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_global_atomic_add">; -def FuncExtFloatAtomicsFp16LocalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_add">; -def FuncExtFloatAtomicsFp32LocalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_add">; -def FuncExtFloatAtomicsFp64LocalAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_add">; -def FuncExtFloatAtomicsFp16GenericAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_add __opencl_c_ext_fp16_global_atomic_add">; -def FuncExtFloatAtomicsFp32GenericAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_add __opencl_c_ext_fp32_global_atomic_add">; -def FuncExtFloatAtomicsFp64GenericAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_add __opencl_c_ext_fp64_global_atomic_add">; -def FuncExtFloatAtomicsFp16GlobalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_min_max">; -def FuncExtFloatAtomicsFp32GlobalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_global_atomic_min_max">; -def FuncExtFloatAtomicsFp64GlobalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_global_atomic_min_max">; -def FuncExtFloatAtomicsFp16LocalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_min_max">; -def FuncExtFloatAtomicsFp32LocalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_min_max">; -def FuncExtFloatAtomicsFp64LocalMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_min_max">; -def FuncExtFloatAtomicsFp16GenericMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_min_max __opencl_c_ext_fp16_global_atomic_min_max">; -def FuncExtFloatAtomicsFp32GenericMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_min_max __opencl_c_ext_fp32_global_atomic_min_max">; -def FuncExtFloatAtomicsFp64GenericMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_min_max __opencl_c_ext_fp64_global_atomic_min_max">; +def FuncExtFloatAtomicsFp16GlobalASLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_load_store">; +def FuncExtFloatAtomicsFp16LocalASLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_load_store">; +def FuncExtFloatAtomicsFp16GenericASLoadStore : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_load_store __opencl_c_ext_fp16_local_atomic_load_store">; +def FuncExtFloatAtomicsFp16GlobalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_add">; +def FuncExtFloatAtomicsFp32GlobalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_global_atomic_add">; +def FuncExtFloatAtomicsFp64GlobalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_global_atomic_add">; +def FuncExtFloatAtomicsFp16LocalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_add">; +def FuncExtFloatAtomicsFp32LocalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_add">; +def FuncExtFloatAtomicsFp64LocalASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_add">; +def FuncExtFloatAtomicsFp16GenericASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_add __opencl_c_ext_fp16_global_atomic_add">; +def FuncExtFloatAtomicsFp32GenericASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_add __opencl_c_ext_fp32_global_atomic_add">; +def FuncExtFloatAtomicsFp64GenericASAdd : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_add __opencl_c_ext_fp64_global_atomic_add">; +def FuncExtFloatAtomicsFp16GlobalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_global_atomic_min_max">; +def FuncExtFloatAtomicsFp32GlobalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_global_atomic_min_max">; +def FuncExtFloatAtomicsFp64GlobalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_global_atomic_min_max">; +def FuncExtFloatAtomicsFp16LocalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_min_max">; +def FuncExtFloatAtomicsFp32LocalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_min_max">; +def FuncExtFloatAtomicsFp64LocalASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_min_max">; +def FuncExtFloatAtomicsFp16GenericASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp16_local_atomic_min_max __opencl_c_ext_fp16_global_atomic_min_max">; +def FuncExtFloatAtomicsFp32GenericASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp32_local_atomic_min_max __opencl_c_ext_fp32_global_atomic_min_max">; +def FuncExtFloatAtomicsFp64GenericASMinMax : FunctionExtension<"cl_ext_float_atomics __opencl_c_ext_fp64_local_atomic_min_max __opencl_c_ext_fp64_global_atomic_min_max">; // Not a real extension, but a workaround to add C++ for OpenCL specific builtins. def FuncExtOpenCLCxx : FunctionExtension<"__cplusplus">; @@ -1111,104 +1111,42 @@ let MinVersion = CL20 in { // The functionality added by cl_ext_float_atomics extension let MinVersion = CL20 in { - let Extension = FuncExtFloatAtomicsFp16GlobalLoadStore in { - defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, GlobalAS>, AtomicHalf]>; - defm : BuiltinAtomicExplicit<"atomic_load", - [Half, PointerType, GlobalAS>]>; - defm : BuiltinAtomicExplicit<"atomic_exchange", - [Half, PointerType, GlobalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp16LocalLoadStore in { - defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, LocalAS>, AtomicHalf]>; - defm : BuiltinAtomicExplicit<"atomic_load", - [Half, PointerType, LocalAS>]>; - defm : BuiltinAtomicExplicit<"atomic_exchange", - [Half, PointerType, LocalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp16GenericLoadStore in { - defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, GenericAS>, AtomicHalf]>; - defm : BuiltinAtomicExplicit<"atomic_load", - [Half, PointerType, GenericAS>]>; - defm : BuiltinAtomicExplicit<"atomic_exchange", - [Half, PointerType, GenericAS>, Half]>; - } - foreach ModOp = ["add", "sub"] in { - let Extension = FuncExtFloatAtomicsFp16GlobalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GlobalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32GlobalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, GlobalAS>, Float]>; - } - let Extension = FuncExtFloatAtomicsFp64GlobalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, GlobalAS>, Double]>; - } - let Extension = FuncExtFloatAtomicsFp16LocalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, LocalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32LocalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, LocalAS>, Float]>; - } - let Extension = FuncExtFloatAtomicsFp64LocalAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, LocalAS>, Double]>; - } - let Extension = FuncExtFloatAtomicsFp16GenericAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GenericAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32GenericAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, GenericAS>, Float]>; + foreach addrspace = [GlobalAS, LocalAS, GenericAS] in { + let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "LoadStore") in { + defm : BuiltinAtomicExplicit<"atomic_store", + [Void, PointerType, addrspace>, AtomicHalf]>; + defm : BuiltinAtomicExplicit<"atomic_load", + [Half, PointerType, addrspace>]>; + defm : BuiltinAtomicExplicit<"atomic_exchange", + [Half, PointerType, addrspace>, Half]>; } - let Extension = FuncExtFloatAtomicsFp64GenericAdd in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, GenericAS>, Double]>; - } - } - foreach ModOp = ["min", "max"] in { - let Extension = FuncExtFloatAtomicsFp16GlobalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GlobalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32GlobalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, GlobalAS>, Float]>; - } - let Extension = FuncExtFloatAtomicsFp64GlobalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, GlobalAS>, Double]>; - } - let Extension = FuncExtFloatAtomicsFp16LocalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, LocalAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32LocalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, LocalAS>, Float]>; - } - let Extension = FuncExtFloatAtomicsFp64LocalMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, LocalAS>, Double]>; - } - let Extension = FuncExtFloatAtomicsFp16GenericMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, GenericAS>, Half]>; - } - let Extension = FuncExtFloatAtomicsFp32GenericMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, GenericAS>, Float]>; + foreach ModOp = ["add", "sub"] in { + let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "Add") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Half, PointerType, addrspace>, Half]>; + } + let Extension = !cast("FuncExtFloatAtomicsFp32" # addrspace # "Add") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Float, PointerType, addrspace>, Float]>; + } + let Extension = !cast("FuncExtFloatAtomicsFp64" # addrspace # "Add") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Double, PointerType, addrspace>, Double]>; + } } - let Extension = FuncExtFloatAtomicsFp64GenericMinMax in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, GenericAS>, Double]>; + foreach ModOp = ["min", "max"] in { + let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "MinMax") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Half, PointerType, addrspace>, Half]>; + } + let Extension = !cast("FuncExtFloatAtomicsFp32" # addrspace # "MinMax") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Float, PointerType, addrspace>, Float]>; + } + let Extension = !cast("FuncExtFloatAtomicsFp64" # addrspace # "MinMax") in { + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Double, PointerType, addrspace>, Double]>; + } } } } From fa24d7e3e0ea67d53b7057e07d5bc7e75ffda9ba Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Fri, 11 Feb 2022 10:14:14 +0000 Subject: [PATCH 099/316] [OpenCL] Add OpenCL 3.0 atomics to -fdeclare-opencl-builtins Add the atomic overloads for the `global` and `local` address spaces, which are new in OpenCL 3.0. Ensure the preexisting `generic` overloads are guarded by the generic address space feature macro. Ensure a subset of the atomic builtins are guarded by the `__opencl_c_atomic_order_seq_cst` and `__opencl_c_atomic_scope_device` feature macros, and enable those macros for SPIR/SPIR-V targets in `opencl-c-base.h`. Also guard the `cl_ext_float_atomics` builtins with the atomic order and scope feature macros. Differential Revision: https://reviews.llvm.org/D119420 (cherry picked from commit 50f8abb9f40a6c4974ec71e760773a711732648f) --- clang/lib/Headers/opencl-c-base.h | 2 + clang/lib/Sema/OpenCLBuiltins.td | 142 +++++++++++------- .../SemaOpenCL/fdeclare-opencl-builtins.cl | 28 ++++ 3 files changed, 118 insertions(+), 54 deletions(-) diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h index ad276dc0f6aae..5191c41bcd057 100644 --- a/clang/lib/Headers/opencl-c-base.h +++ b/clang/lib/Headers/opencl-c-base.h @@ -67,6 +67,8 @@ #if (__OPENCL_CPP_VERSION__ == 202100 || __OPENCL_C_VERSION__ == 300) // For the SPIR and SPIR-V target all features are supported. #if defined(__SPIR__) || defined(__SPIRV__) +#define __opencl_c_atomic_order_seq_cst 1 +#define __opencl_c_atomic_scope_device 1 #define __opencl_c_atomic_scope_all_devices 1 #define __opencl_c_read_write_images 1 #endif // defined(__SPIR__) diff --git a/clang/lib/Sema/OpenCLBuiltins.td b/clang/lib/Sema/OpenCLBuiltins.td index 4d36df352d5ec..ab30553005729 100644 --- a/clang/lib/Sema/OpenCLBuiltins.td +++ b/clang/lib/Sema/OpenCLBuiltins.td @@ -57,6 +57,23 @@ class FunctionExtension : AbstractExtension<_Ext>; // disabled. class TypeExtension : AbstractExtension<_Ext>; +// Concatenate zero or more space-separated extensions in NewExts to Base and +// return the resulting FunctionExtension in ret. +class concatExtension { + FunctionExtension ret = FunctionExtension< + !cond( + // Return Base extension if NewExts is empty, + !empty(NewExts) : Base.ExtName, + + // otherwise, return NewExts if Base extension is empty, + !empty(Base.ExtName) : NewExts, + + // otherwise, concatenate NewExts to Base. + true : Base.ExtName # " " # NewExts + ) + >; +} + // TypeExtension definitions. def NoTypeExt : TypeExtension<"">; def Fp16TypeExt : TypeExtension<"cl_khr_fp16">; @@ -1043,40 +1060,57 @@ let Extension = FuncExtOpenCLCxx in { // OpenCL v2.0 s6.13.11 - Atomic Functions. // An atomic builtin with 2 additional _explicit variants. -multiclass BuiltinAtomicExplicit Types> { +multiclass BuiltinAtomicExplicit Types, FunctionExtension BaseExt> { // Without explicit MemoryOrder or MemoryScope. - def : Builtin; + let Extension = concatExtension.ret in { + def : Builtin; + } // With an explicit MemoryOrder argument. - def : Builtin; + let Extension = concatExtension.ret in { + def : Builtin; + } // With explicit MemoryOrder and MemoryScope arguments. - def : Builtin; + let Extension = BaseExt in { + def : Builtin; + } } // OpenCL 2.0 atomic functions that have a pointer argument in a given address space. -multiclass OpenCL2Atomics { +multiclass OpenCL2Atomics { foreach TypePair = [[AtomicInt, Int], [AtomicUInt, UInt], [AtomicLong, Long], [AtomicULong, ULong], [AtomicFloat, Float], [AtomicDouble, Double]] in { def : Builtin<"atomic_init", [Void, PointerType, addrspace>, TypePair[1]]>; defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, addrspace>, TypePair[1]]>; + [Void, PointerType, addrspace>, TypePair[1]], BaseExt>; defm : BuiltinAtomicExplicit<"atomic_load", - [TypePair[1], PointerType, addrspace>]>; + [TypePair[1], PointerType, addrspace>], BaseExt>; defm : BuiltinAtomicExplicit<"atomic_exchange", - [TypePair[1], PointerType, addrspace>, TypePair[1]]>; + [TypePair[1], PointerType, addrspace>, TypePair[1]], BaseExt>; foreach Variant = ["weak", "strong"] in { - def : Builtin<"atomic_compare_exchange_" # Variant, - [Bool, PointerType, addrspace>, - PointerType, TypePair[1]]>; - def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", - [Bool, PointerType, addrspace>, - PointerType, TypePair[1], MemoryOrder, MemoryOrder]>; - def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", - [Bool, PointerType, addrspace>, - PointerType, TypePair[1], MemoryOrder, MemoryOrder, MemoryScope]>; + foreach exp_ptr_addrspace = !cond( + !eq(BaseExt, FuncExtOpenCLCGenericAddressSpace): [GenericAS], + !eq(BaseExt, FuncExtOpenCLCNamedAddressSpaceBuiltins): [GlobalAS, LocalAS, PrivateAS]) + in { + let Extension = concatExtension.ret in { + def : Builtin<"atomic_compare_exchange_" # Variant, + [Bool, PointerType, addrspace>, + PointerType, TypePair[1]]>; + } + let Extension = concatExtension.ret in { + def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", + [Bool, PointerType, addrspace>, + PointerType, TypePair[1], MemoryOrder, MemoryOrder]>; + } + let Extension = BaseExt in { + def : Builtin<"atomic_compare_exchange_" # Variant # "_explicit", + [Bool, PointerType, addrspace>, + PointerType, TypePair[1], MemoryOrder, MemoryOrder, MemoryScope]>; + } + } } } @@ -1085,68 +1119,68 @@ multiclass OpenCL2Atomics { [AtomicUIntPtr, UIntPtr, PtrDiff]] in { foreach ModOp = ["add", "sub"] in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [TypePair[1], PointerType, addrspace>, TypePair[2]]>; + [TypePair[1], PointerType, addrspace>, TypePair[2]], BaseExt>; } } foreach TypePair = [[AtomicInt, Int, Int], [AtomicUInt, UInt, UInt], [AtomicLong, Long, Long], [AtomicULong, ULong, ULong]] in { foreach ModOp = ["or", "xor", "and", "min", "max"] in { defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [TypePair[1], PointerType, addrspace>, TypePair[2]]>; + [TypePair[1], PointerType, addrspace>, TypePair[2]], BaseExt>; } } defm : BuiltinAtomicExplicit<"atomic_flag_clear", - [Void, PointerType, addrspace>]>; + [Void, PointerType, addrspace>], BaseExt>; defm : BuiltinAtomicExplicit<"atomic_flag_test_and_set", - [Bool, PointerType, addrspace>]>; + [Bool, PointerType, addrspace>], BaseExt>; } let MinVersion = CL20 in { def : Builtin<"atomic_work_item_fence", [Void, MemFenceFlags, MemoryOrder, MemoryScope]>; - defm : OpenCL2Atomics; + defm : OpenCL2Atomics; + defm : OpenCL2Atomics; + defm : OpenCL2Atomics; } // The functionality added by cl_ext_float_atomics extension let MinVersion = CL20 in { foreach addrspace = [GlobalAS, LocalAS, GenericAS] in { - let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "LoadStore") in { - defm : BuiltinAtomicExplicit<"atomic_store", - [Void, PointerType, addrspace>, AtomicHalf]>; - defm : BuiltinAtomicExplicit<"atomic_load", - [Half, PointerType, addrspace>]>; - defm : BuiltinAtomicExplicit<"atomic_exchange", - [Half, PointerType, addrspace>, Half]>; - } + defvar extension_fp16 = !cast("FuncExtFloatAtomicsFp16" # addrspace # "LoadStore"); + + defm : BuiltinAtomicExplicit<"atomic_store", + [Void, PointerType, addrspace>, AtomicHalf], extension_fp16>; + defm : BuiltinAtomicExplicit<"atomic_load", + [Half, PointerType, addrspace>], extension_fp16>; + defm : BuiltinAtomicExplicit<"atomic_exchange", + [Half, PointerType, addrspace>, Half], extension_fp16>; + foreach ModOp = ["add", "sub"] in { - let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "Add") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, addrspace>, Half]>; - } - let Extension = !cast("FuncExtFloatAtomicsFp32" # addrspace # "Add") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, addrspace>, Float]>; - } - let Extension = !cast("FuncExtFloatAtomicsFp64" # addrspace # "Add") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, addrspace>, Double]>; - } + defvar extension_fp16 = !cast("FuncExtFloatAtomicsFp16" # addrspace # "Add"); + defvar extension_fp32 = !cast("FuncExtFloatAtomicsFp32" # addrspace # "Add"); + defvar extension_fp64 = !cast("FuncExtFloatAtomicsFp64" # addrspace # "Add"); + + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Half, PointerType, addrspace>, Half], extension_fp16>; + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Float, PointerType, addrspace>, Float], extension_fp32>; + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Double, PointerType, addrspace>, Double], extension_fp64>; } + foreach ModOp = ["min", "max"] in { - let Extension = !cast("FuncExtFloatAtomicsFp16" # addrspace # "MinMax") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Half, PointerType, addrspace>, Half]>; - } - let Extension = !cast("FuncExtFloatAtomicsFp32" # addrspace # "MinMax") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Float, PointerType, addrspace>, Float]>; - } - let Extension = !cast("FuncExtFloatAtomicsFp64" # addrspace # "MinMax") in { - defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, - [Double, PointerType, addrspace>, Double]>; - } + defvar extension_fp16 = !cast("FuncExtFloatAtomicsFp16" # addrspace # "MinMax"); + defvar extension_fp32 = !cast("FuncExtFloatAtomicsFp32" # addrspace # "MinMax"); + defvar extension_fp64 = !cast("FuncExtFloatAtomicsFp64" # addrspace # "MinMax"); + + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Half, PointerType, addrspace>, Half], extension_fp16>; + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Float, PointerType, addrspace>, Float], extension_fp32>; + defm : BuiltinAtomicExplicit<"atomic_fetch_" # ModOp, + [Double, PointerType, addrspace>, Double], extension_fp64>; } } } diff --git a/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl b/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl index d1a4f72837260..d526c32d65a92 100644 --- a/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl +++ b/clang/test/SemaOpenCL/fdeclare-opencl-builtins.cl @@ -9,6 +9,7 @@ // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC++ -fdeclare-opencl-builtins -finclude-default-header // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC++2021 -fdeclare-opencl-builtins -finclude-default-header // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL2.0 -fdeclare-opencl-builtins -finclude-default-header -cl-ext=-cl_khr_fp64 -DNO_FP64 +// RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CL3.0 -fdeclare-opencl-builtins -finclude-default-header -DNO_ATOMSCOPE // Test the -fdeclare-opencl-builtins option. This is not a completeness // test, so it should not test for all builtins defined by OpenCL. Instead @@ -80,6 +81,11 @@ typedef struct {int a;} ndrange_t; #define __opencl_c_read_write_images 1 #endif +#if (__OPENCL_CPP_VERSION__ == 100 || __OPENCL_C_VERSION__ == 200) +#define __opencl_c_atomic_order_seq_cst 1 +#define __opencl_c_atomic_scope_device 1 +#endif + #define __opencl_c_named_address_space_builtins 1 #endif @@ -98,6 +104,7 @@ kernel void test_pointers(volatile global void *global_p, global const int4 *a) #if !defined(NO_HEADER) && (defined(__OPENCL_CPP_VERSION__) || __OPENCL_C_VERSION__ >= 200) kernel void test_enum_args(volatile global atomic_int *global_p, global int *expected) { int desired; + atomic_work_item_fence(CLK_GLOBAL_MEM_FENCE, memory_order_acq_rel, memory_scope_device); atomic_compare_exchange_strong_explicit(global_p, expected, desired, memory_order_acq_rel, memory_order_relaxed, @@ -156,6 +163,27 @@ void test_atomic_fetch_with_address_space(volatile __generic atomic_float *a_flo } #endif // !defined(NO_HEADER) && __OPENCL_C_VERSION__ >= 200 +#if defined(NO_ATOMSCOPE) && __OPENCL_C_VERSION__ >= 300 +// Disable the feature by undefining the feature macro. +#undef __opencl_c_atomic_scope_device + +// Test that only the overload with explicit order and scope arguments is +// available when the __opencl_c_atomic_scope_device feature is disabled. +void test_atomics_without_scope_device(volatile __generic atomic_int *a_int) { + int d; + + atomic_exchange(a_int, d); + // expected-error@-1{{implicit declaration of function 'atomic_exchange' is invalid in OpenCL}} + + atomic_exchange_explicit(a_int, d, memory_order_seq_cst); + // expected-error@-1{{no matching function for call to 'atomic_exchange_explicit'}} + // expected-note@-2 + {{candidate function not viable}} + + atomic_exchange_explicit(a_int, d, memory_order_seq_cst, memory_scope_work_group); +} + +#endif + // Test old atomic overloaded with generic address space in C++ for OpenCL. #if __OPENCL_C_VERSION__ >= 200 void test_legacy_atomics_cpp(__generic volatile unsigned int *a) { From 95dd9c5f2a0642260c5351d860757c4b8abe4537 Mon Sep 17 00:00:00 2001 From: Anton Zabaznov Date: Mon, 7 Feb 2022 15:45:42 +0300 Subject: [PATCH 100/316] [OpenCL] Add support of language builtins for OpenCL C 3.0 OpenCL C 3.0 introduces optionality to some builtins, in particularly to those which are conditionally supported with pipe, device enqueue and generic address space features. The idea is to conditionally support such builtins depending on the language options being set for a certain feature. This allows users to define functions with names of those optional builtins in OpenCL (as such names are not reserved). Reviewed By: Anastasia Differential Revision: https://reviews.llvm.org/D118605 (cherry picked from commit bee4bd70f76952b2c6296feb46a087b497322376) --- clang/include/clang/Basic/Builtins.def | 56 +++++++++---------- clang/include/clang/Basic/Builtins.h | 25 +++++---- clang/lib/Basic/Builtins.cpp | 26 +++++---- .../CodeGenOpenCL/cl20-device-side-enqueue.cl | 3 + clang/test/CodeGenOpenCL/pipe_types.cl | 5 +- clang/test/CodeGenOpenCL/to_addr_builtin.cl | 2 + .../SemaOpenCL/cl20-device-side-enqueue.cl | 5 ++ .../test/SemaOpenCL/clang-builtin-version.cl | 9 ++- clang/test/SemaOpenCL/to_addr_builtin.cl | 34 +++++------ 9 files changed, 93 insertions(+), 72 deletions(-) diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def index d2cb14d2fd8cc..a17d2e59f5d8b 100644 --- a/clang/include/clang/Basic/Builtins.def +++ b/clang/include/clang/Basic/Builtins.def @@ -1625,50 +1625,50 @@ LANGBUILTIN(__builtin_coro_suspend, "cIb", "n", COR_LANG) // OpenCL v2.0 s6.13.16, s9.17.3.5 - Pipe functions. // We need the generic prototype, since the packet type could be anything. -LANGBUILTIN(read_pipe, "i.", "tn", OCLC20_LANG) -LANGBUILTIN(write_pipe, "i.", "tn", OCLC20_LANG) +LANGBUILTIN(read_pipe, "i.", "tn", OCL_PIPE) +LANGBUILTIN(write_pipe, "i.", "tn", OCL_PIPE) -LANGBUILTIN(reserve_read_pipe, "i.", "tn", OCLC20_LANG) -LANGBUILTIN(reserve_write_pipe, "i.", "tn", OCLC20_LANG) +LANGBUILTIN(reserve_read_pipe, "i.", "tn", OCL_PIPE) +LANGBUILTIN(reserve_write_pipe, "i.", "tn", OCL_PIPE) -LANGBUILTIN(commit_write_pipe, "v.", "tn", OCLC20_LANG) -LANGBUILTIN(commit_read_pipe, "v.", "tn", OCLC20_LANG) +LANGBUILTIN(commit_write_pipe, "v.", "tn", OCL_PIPE) +LANGBUILTIN(commit_read_pipe, "v.", "tn", OCL_PIPE) -LANGBUILTIN(sub_group_reserve_read_pipe, "i.", "tn", OCLC20_LANG) -LANGBUILTIN(sub_group_reserve_write_pipe, "i.", "tn", OCLC20_LANG) +LANGBUILTIN(sub_group_reserve_read_pipe, "i.", "tn", OCL_PIPE) +LANGBUILTIN(sub_group_reserve_write_pipe, "i.", "tn", OCL_PIPE) -LANGBUILTIN(sub_group_commit_read_pipe, "v.", "tn", OCLC20_LANG) -LANGBUILTIN(sub_group_commit_write_pipe, "v.", "tn", OCLC20_LANG) +LANGBUILTIN(sub_group_commit_read_pipe, "v.", "tn", OCL_PIPE) +LANGBUILTIN(sub_group_commit_write_pipe, "v.", "tn", OCL_PIPE) -LANGBUILTIN(work_group_reserve_read_pipe, "i.", "tn", OCLC20_LANG) -LANGBUILTIN(work_group_reserve_write_pipe, "i.", "tn", OCLC20_LANG) +LANGBUILTIN(work_group_reserve_read_pipe, "i.", "tn", OCL_PIPE) +LANGBUILTIN(work_group_reserve_write_pipe, "i.", "tn", OCL_PIPE) -LANGBUILTIN(work_group_commit_read_pipe, "v.", "tn", OCLC20_LANG) -LANGBUILTIN(work_group_commit_write_pipe, "v.", "tn", OCLC20_LANG) +LANGBUILTIN(work_group_commit_read_pipe, "v.", "tn", OCL_PIPE) +LANGBUILTIN(work_group_commit_write_pipe, "v.", "tn", OCL_PIPE) -LANGBUILTIN(get_pipe_num_packets, "Ui.", "tn", OCLC20_LANG) -LANGBUILTIN(get_pipe_max_packets, "Ui.", "tn", OCLC20_LANG) +LANGBUILTIN(get_pipe_num_packets, "Ui.", "tn", OCL_PIPE) +LANGBUILTIN(get_pipe_max_packets, "Ui.", "tn", OCL_PIPE) // OpenCL v2.0 s6.13.17 - Enqueue kernel functions. // Custom builtin check allows to perform special check of passed block arguments. -LANGBUILTIN(enqueue_kernel, "i.", "tn", OCLC20_LANG) -LANGBUILTIN(get_kernel_work_group_size, "Ui.", "tn", OCLC20_LANG) -LANGBUILTIN(get_kernel_preferred_work_group_size_multiple, "Ui.", "tn", OCLC20_LANG) -LANGBUILTIN(get_kernel_max_sub_group_size_for_ndrange, "Ui.", "tn", OCLC20_LANG) -LANGBUILTIN(get_kernel_sub_group_count_for_ndrange, "Ui.", "tn", OCLC20_LANG) +LANGBUILTIN(enqueue_kernel, "i.", "tn", OCL_DSE) +LANGBUILTIN(get_kernel_work_group_size, "Ui.", "tn", OCL_DSE) +LANGBUILTIN(get_kernel_preferred_work_group_size_multiple, "Ui.", "tn", OCL_DSE) +LANGBUILTIN(get_kernel_max_sub_group_size_for_ndrange, "Ui.", "tn", OCL_DSE) +LANGBUILTIN(get_kernel_sub_group_count_for_ndrange, "Ui.", "tn", OCL_DSE) // OpenCL v2.0 s6.13.9 - Address space qualifier functions. // FIXME: Pointer parameters of OpenCL builtins should have their address space // requirement defined. -LANGBUILTIN(to_global, "v*v*", "tn", OCLC20_LANG) -LANGBUILTIN(to_local, "v*v*", "tn", OCLC20_LANG) -LANGBUILTIN(to_private, "v*v*", "tn", OCLC20_LANG) +LANGBUILTIN(to_global, "v*v*", "tn", OCL_GAS) +LANGBUILTIN(to_local, "v*v*", "tn", OCL_GAS) +LANGBUILTIN(to_private, "v*v*", "tn", OCL_GAS) // OpenCL half load/store builtin -LANGBUILTIN(__builtin_store_half, "vdh*", "n", ALL_OCLC_LANGUAGES) -LANGBUILTIN(__builtin_store_halff, "vfh*", "n", ALL_OCLC_LANGUAGES) -LANGBUILTIN(__builtin_load_half, "dhC*", "nc", ALL_OCLC_LANGUAGES) -LANGBUILTIN(__builtin_load_halff, "fhC*", "nc", ALL_OCLC_LANGUAGES) +LANGBUILTIN(__builtin_store_half, "vdh*", "n", ALL_OCL_LANGUAGES) +LANGBUILTIN(__builtin_store_halff, "vfh*", "n", ALL_OCL_LANGUAGES) +LANGBUILTIN(__builtin_load_half, "dhC*", "nc", ALL_OCL_LANGUAGES) +LANGBUILTIN(__builtin_load_halff, "fhC*", "nc", ALL_OCL_LANGUAGES) // Builtins for os_log/os_trace BUILTIN(__builtin_os_log_format_buffer_size, "zcC*.", "p:0:nut") diff --git a/clang/include/clang/Basic/Builtins.h b/clang/include/clang/Basic/Builtins.h index cdaaee48c32d8..1dabafce54f39 100644 --- a/clang/include/clang/Basic/Builtins.h +++ b/clang/include/clang/Basic/Builtins.h @@ -28,20 +28,21 @@ class IdentifierTable; class LangOptions; enum LanguageID { - GNU_LANG = 0x1, // builtin requires GNU mode. - C_LANG = 0x2, // builtin for c only. - CXX_LANG = 0x4, // builtin for cplusplus only. - OBJC_LANG = 0x8, // builtin for objective-c and objective-c++ - MS_LANG = 0x10, // builtin requires MS mode. - OCLC20_LANG = 0x20, // builtin for OpenCL C 2.0 only. - OCLC1X_LANG = 0x40, // builtin for OpenCL C 1.x only. - OMP_LANG = 0x80, // builtin requires OpenMP. - CUDA_LANG = 0x100, // builtin requires CUDA. - COR_LANG = 0x200, // builtin requires use of 'fcoroutine-ts' option. + GNU_LANG = 0x1, // builtin requires GNU mode. + C_LANG = 0x2, // builtin for c only. + CXX_LANG = 0x4, // builtin for cplusplus only. + OBJC_LANG = 0x8, // builtin for objective-c and objective-c++ + MS_LANG = 0x10, // builtin requires MS mode. + OMP_LANG = 0x20, // builtin requires OpenMP. + CUDA_LANG = 0x40, // builtin requires CUDA. + COR_LANG = 0x80, // builtin requires use of 'fcoroutine-ts' option. + OCL_GAS = 0x100, // builtin requires OpenCL generic address space. + OCL_PIPE = 0x200, // builtin requires OpenCL pipe. + OCL_DSE = 0x400, // builtin requires OpenCL device side enqueue. + ALL_OCL_LANGUAGES = 0x800, // builtin for OCL languages. ALL_LANGUAGES = C_LANG | CXX_LANG | OBJC_LANG, // builtin for all languages. ALL_GNU_LANGUAGES = ALL_LANGUAGES | GNU_LANG, // builtin requires GNU mode. - ALL_MS_LANGUAGES = ALL_LANGUAGES | MS_LANG, // builtin requires MS mode. - ALL_OCLC_LANGUAGES = OCLC1X_LANG | OCLC20_LANG // builtin for OCLC languages. + ALL_MS_LANGUAGES = ALL_LANGUAGES | MS_LANG // builtin requires MS mode. }; namespace Builtin { diff --git a/clang/lib/Basic/Builtins.cpp b/clang/lib/Basic/Builtins.cpp index 2b0f4071662c0..6d278e9c4a229 100644 --- a/clang/lib/Basic/Builtins.cpp +++ b/clang/lib/Basic/Builtins.cpp @@ -69,22 +69,26 @@ bool Builtin::Context::builtinIsSupported(const Builtin::Info &BuiltinInfo, bool MSModeUnsupported = !LangOpts.MicrosoftExt && (BuiltinInfo.Langs & MS_LANG); bool ObjCUnsupported = !LangOpts.ObjC && BuiltinInfo.Langs == OBJC_LANG; - bool OclC1Unsupported = (LangOpts.OpenCLVersion / 100) != 1 && - (BuiltinInfo.Langs & ALL_OCLC_LANGUAGES ) == OCLC1X_LANG; - bool OclC2Unsupported = - (LangOpts.getOpenCLCompatibleVersion() != 200) && - (BuiltinInfo.Langs & ALL_OCLC_LANGUAGES) == OCLC20_LANG; - bool OclCUnsupported = !LangOpts.OpenCL && - (BuiltinInfo.Langs & ALL_OCLC_LANGUAGES); + bool OclCUnsupported = + !LangOpts.OpenCL && (BuiltinInfo.Langs & ALL_OCL_LANGUAGES); + bool OclGASUnsupported = + !LangOpts.OpenCLGenericAddressSpace && (BuiltinInfo.Langs & OCL_GAS); + bool OclPipeUnsupported = + !LangOpts.OpenCLPipes && (BuiltinInfo.Langs & OCL_PIPE); + // Device side enqueue is not supported until OpenCL 2.0. In 2.0 and higher + // support is indicated with language option for blocks. + bool OclDSEUnsupported = + (LangOpts.getOpenCLCompatibleVersion() < 200 || !LangOpts.Blocks) && + (BuiltinInfo.Langs & OCL_DSE); bool OpenMPUnsupported = !LangOpts.OpenMP && BuiltinInfo.Langs == OMP_LANG; bool CUDAUnsupported = !LangOpts.CUDA && BuiltinInfo.Langs == CUDA_LANG; bool CPlusPlusUnsupported = !LangOpts.CPlusPlus && BuiltinInfo.Langs == CXX_LANG; return !BuiltinsUnsupported && !CorBuiltinsUnsupported && - !MathBuiltinsUnsupported && !OclCUnsupported && !OclC1Unsupported && - !OclC2Unsupported && !OpenMPUnsupported && !GnuModeUnsupported && - !MSModeUnsupported && !ObjCUnsupported && !CPlusPlusUnsupported && - !CUDAUnsupported; + !MathBuiltinsUnsupported && !OclCUnsupported && !OclGASUnsupported && + !OclPipeUnsupported && !OclDSEUnsupported && !OpenMPUnsupported && + !GnuModeUnsupported && !MSModeUnsupported && !ObjCUnsupported && + !CPlusPlusUnsupported && !CUDAUnsupported; } /// initializeBuiltins - Mark the identifiers for all the builtins with their diff --git a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl index fdbc0aaa6e263..01750804884b3 100644 --- a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl +++ b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue.cl @@ -1,6 +1,9 @@ // RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B32 // RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B64 // RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL2.0 -ffake-address-space-map -O1 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=CHECK-LIFETIMES +// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL3.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B32 +// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL3.0 -ffake-address-space-map -O0 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=COMMON --check-prefix=B64 +// RUN: %clang_cc1 -disable-noundef-analysis %s -cl-std=CL3.0 -ffake-address-space-map -O1 -emit-llvm -o - -triple "spir64-unknown-unknown" | FileCheck %s --check-prefix=CHECK-LIFETIMES #pragma OPENCL EXTENSION cl_khr_subgroups : enable diff --git a/clang/test/CodeGenOpenCL/pipe_types.cl b/clang/test/CodeGenOpenCL/pipe_types.cl index 57da95fec0d70..9644aff1a6248 100644 --- a/clang/test/CodeGenOpenCL/pipe_types.cl +++ b/clang/test/CodeGenOpenCL/pipe_types.cl @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -O0 -cl-std=CL2.0 -DTEST_STRUCT -o - %s | FileCheck --check-prefixes=CHECK,CHECK-STRUCT %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -O0 -cl-std=CL2.0 -o - %s | FileCheck --check-prefixes=CHECK,CHECK-STRUCT %s // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -O0 -cl-std=CL3.0 -cl-ext=-all,+__opencl_c_pipes,+__opencl_c_generic_address_space,+__opencl_c_program_scope_global_variables -o - %s | FileCheck --check-prefixes=CHECK %s // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -O0 -cl-std=CL3.0 -cl-ext=-all,+__opencl_c_pipes,+__opencl_c_generic_address_space -o - %s | FileCheck --check-prefixes=CHECK %s // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -O0 -cl-std=clc++2021 -cl-ext=-all,+__opencl_c_pipes,+__opencl_c_generic_address_space,+__opencl_c_program_scope_global_variables -o - %s | FileCheck --check-prefixes=CHECK %s @@ -36,8 +36,6 @@ kernel void test6(MyPipe p) { // CHECK: define{{.*}} spir_kernel void @test6(%opencl.pipe_ro_t* %p) } -#ifdef TEST_STRUCT -// FIXME: not supported for OpenCL C 3.0 as language built-ins not supported yet struct Person { const char *Name; bool isFemale; @@ -52,4 +50,3 @@ void test_reserved_read_pipe(global struct Person *SDst, read_pipe (SPipe, SDst); // CHECK-STRUCT: call i32 @__read_pipe_2(%opencl.pipe_ro_t* %{{.*}}, i8* %{{.*}}, i32 16, i32 8) } -#endif // TEST_STRUCT diff --git a/clang/test/CodeGenOpenCL/to_addr_builtin.cl b/clang/test/CodeGenOpenCL/to_addr_builtin.cl index b5b197079b74b..03097f60f7931 100644 --- a/clang/test/CodeGenOpenCL/to_addr_builtin.cl +++ b/clang/test/CodeGenOpenCL/to_addr_builtin.cl @@ -1,4 +1,6 @@ // RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm -O0 -cl-std=clc++ -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm -O0 -cl-std=cl2.0 -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm -O0 -cl-std=cl3.0 -o - %s | FileCheck %s // CHECK: %[[A:.*]] = type { float, float, float } typedef struct { diff --git a/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl b/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl index 5cfdfb3cdc5ca..9c375b2603ac1 100644 --- a/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl +++ b/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl @@ -3,6 +3,11 @@ // RUN: %clang_cc1 %s -cl-std=CL2.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS="const volatile" // RUN: %clang_cc1 %s -cl-std=CL2.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS= // RUN: %clang_cc1 %s -cl-std=CL2.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS="const volatile" +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS= +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS= -cl-ext=-cl_khr_subgroups +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS="const volatile" +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS= +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS="const volatile" typedef struct {int a;} ndrange_t; // Diagnostic tests for different overloads of enqueue_kernel from Table 6.13.17.1 of OpenCL 2.0 Spec. diff --git a/clang/test/SemaOpenCL/clang-builtin-version.cl b/clang/test/SemaOpenCL/clang-builtin-version.cl index 3e270e64c69d1..7111db1784c60 100644 --- a/clang/test/SemaOpenCL/clang-builtin-version.cl +++ b/clang/test/SemaOpenCL/clang-builtin-version.cl @@ -1,6 +1,8 @@ // RUN: %clang_cc1 %s -fblocks -verify -pedantic -fsyntax-only -ferror-limit 100 +// RUN: %clang_cc1 %s -fblocks -verify -pedantic -fsyntax-only -ferror-limit 100 -cl-std=CL1.2 +// RUN: %clang_cc1 %s -fblocks -verify -pedantic -fsyntax-only -ferror-limit 100 -cl-std=CL3.0 -cl-ext=-__opencl_c_device_enqueue,-__opencl_c_generic_address_space,-__opencl_c_pipes -// Confirm CL2.0 Clang builtins are not available in earlier versions +// Confirm CL2.0 Clang builtins are not available in earlier versions and in OpenCL C 3.0 without required features. kernel void dse_builtins() { int tmp; @@ -13,6 +15,11 @@ kernel void dse_builtins() { size = get_kernel_preferred_work_group_size_multiple(^(void) { // expected-error{{implicit declaration of function 'get_kernel_preferred_work_group_size_multiple' is invalid in OpenCL}} return; }); +#if (__OPENCL_C_VERSION__ >= CL_VERSION_3_0) && !defined(__opencl_c_device_enqueue) +// expected-error@-10{{support disabled - compile with -fblocks or for OpenCL C 2.0 or OpenCL C 3.0 with __opencl_c_device_enqueue feature}} +// expected-error@-8{{support disabled - compile with -fblocks or for OpenCL C 2.0 or OpenCL C 3.0 with __opencl_c_device_enqueue feature}} +// expected-error@-6{{support disabled - compile with -fblocks or for OpenCL C 2.0 or OpenCL C 3.0 with __opencl_c_device_enqueue feature}} +#endif } void pipe_builtins() { diff --git a/clang/test/SemaOpenCL/to_addr_builtin.cl b/clang/test/SemaOpenCL/to_addr_builtin.cl index 8f4a20ac7662a..f5df7abc3b4f2 100644 --- a/clang/test/SemaOpenCL/to_addr_builtin.cl +++ b/clang/test/SemaOpenCL/to_addr_builtin.cl @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -verify -fsyntax-only %s // RUN: %clang_cc1 -Wconversion -verify -fsyntax-only -cl-std=CL2.0 %s +// RUN: %clang_cc1 -Wconversion -verify -fsyntax-only -cl-std=CL3.0 -cl-ext=-all %s +// RUN: %clang_cc1 -Wconversion -verify -fsyntax-only -cl-std=CL3.0 %s void test(void) { global int *glob; @@ -11,7 +13,7 @@ void test(void) { const_int_ty *con_typedef; glob = to_global(glob, loc); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-error@-2{{implicit declaration of function 'to_global' is invalid in OpenCL}} // expected-warning@-3{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else @@ -20,28 +22,28 @@ void test(void) { int x; glob = to_global(x); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-error@-4{{invalid argument x to function: 'to_global', expecting a generic pointer argument}} #endif glob = to_global(con); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-error@-4{{invalid argument con to function: 'to_global', expecting a generic pointer argument}} #endif glob = to_global(con_typedef); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-error@-4{{invalid argument con_typedef to function: 'to_global', expecting a generic pointer argument}} #endif loc = to_global(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__local int *__private' from 'int'}} #else // expected-error@-4{{assigning '__global int *' to '__local int *__private' changes address space of pointer}} @@ -49,7 +51,7 @@ void test(void) { #endif loc = to_private(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-error@-2{{implicit declaration of function 'to_private' is invalid in OpenCL}} // expected-warning@-3{{incompatible integer to pointer conversion assigning to '__local int *__private' from 'int'}} #else @@ -58,17 +60,17 @@ void test(void) { #endif loc = to_local(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-error@-2{{implicit declaration of function 'to_local' is invalid in OpenCL}} // expected-warning@-3{{incompatible integer to pointer conversion assigning to '__local int *__private' from 'int'}} // expected-note@-4{{did you mean 'to_global'}} - // expected-note@13{{'to_global' declared here}} + // expected-note@15{{'to_global' declared here}} #else // expected-warning@-7{{passing non-generic address space pointer to to_local may cause dynamic conversion affecting performance}} #endif priv = to_global(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__private int *__private' from 'int'}} #else // expected-error@-4{{assigning '__global int *' to '__private int *__private' changes address space of pointer}} @@ -76,7 +78,7 @@ void test(void) { #endif priv = to_private(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__private int *__private' from 'int'}} #else // expected-warning@-4{{passing non-generic address space pointer to to_private may cause dynamic conversion affecting performance}} @@ -84,7 +86,7 @@ void test(void) { priv = to_local(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__private int *__private' from 'int'}} #else // expected-error@-4{{assigning '__local int *' to '__private int *__private' changes address space of pointer}} @@ -92,14 +94,14 @@ void test(void) { #endif glob = to_global(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-warning@-4{{passing non-generic address space pointer to to_global may cause dynamic conversion affecting performance}} #endif glob = to_private(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-error@-4{{assigning '__private int *' to '__global int *__private' changes address space of pointer}} @@ -107,7 +109,7 @@ void test(void) { #endif glob = to_local(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global int *__private' from 'int'}} #else // expected-error@-4{{assigning '__local int *' to '__global int *__private' changes address space of pointer}} @@ -115,7 +117,7 @@ void test(void) { #endif global char *glob_c = to_global(loc); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion initializing '__global char *__private' with an expression of type 'int'}} #else // expected-warning@-4{{incompatible pointer types initializing '__global char *__private' with an expression of type '__global int *'}} @@ -123,7 +125,7 @@ void test(void) { #endif glob_wrong_ty = to_global(glob); -#if __OPENCL_C_VERSION__ < CL_VERSION_2_0 +#if (__OPENCL_C_VERSION__ < CL_VERSION_2_0) || (__OPENCL_C_VERSION__ >= CL_VERSION_3_0 && !defined(__opencl_c_generic_address_space)) // expected-warning@-2{{incompatible integer to pointer conversion assigning to '__global float *__private' from 'int'}} #else // expected-warning@-4{{incompatible pointer types assigning to '__global float *__private' from '__global int *'}} From 7bb1dfeeba8779ab9740cf05f01198ed7ce41277 Mon Sep 17 00:00:00 2001 From: Anton Zabaznov Date: Fri, 11 Feb 2022 15:54:55 +0300 Subject: [PATCH 101/316] [OpenCL] Adjust diagnostic for subgroup support. OpenCL C 3.0 __opencl_c_subgroups feature is slightly different then other equivalent features and extensions (fp64 and 3d image writes): OpenCL C 3.0 device can support the extension but not the feature. cl_khr_subgroups requires subgroup independent forward progress. This patch adjusts the check which is used when translating language builtins to check either the extension or feature is supported. Reviewed By: Anastasia Differential Revision: https://reviews.llvm.org/D118999 (cherry picked from commit bfb1a33bec7c88170b0809b8a7c9cb860e7cc19b) --- clang/lib/Sema/SemaChecking.cpp | 10 ++++++++-- clang/test/SemaOpenCL/cl20-device-side-enqueue.cl | 6 +++--- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index dfbf4cdc89cb9..69dcc3aaaaf37 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -1042,9 +1042,15 @@ static bool checkOpenCLBlockArgs(Sema &S, Expr *BlockArg) { } static bool checkOpenCLSubgroupExt(Sema &S, CallExpr *Call) { - if (!S.getOpenCLOptions().isSupported("cl_khr_subgroups", S.getLangOpts())) { + // OpenCL device can support extension but not the feature as extension + // requires subgroup independent forward progress, but subgroup independent + // forward progress is optional in OpenCL C 3.0 __opencl_c_subgroups feature. + if (!S.getOpenCLOptions().isSupported("cl_khr_subgroups", S.getLangOpts()) && + !S.getOpenCLOptions().isSupported("__opencl_c_subgroups", + S.getLangOpts())) { S.Diag(Call->getBeginLoc(), diag::err_opencl_requires_extension) - << 1 << Call->getDirectCallee() << "cl_khr_subgroups"; + << 1 << Call->getDirectCallee() + << "cl_khr_subgroups or __opencl_c_subgroups"; return true; } return false; diff --git a/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl b/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl index 9c375b2603ac1..344297ebbe0ca 100644 --- a/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl +++ b/clang/test/SemaOpenCL/cl20-device-side-enqueue.cl @@ -4,7 +4,7 @@ // RUN: %clang_cc1 %s -cl-std=CL2.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS= // RUN: %clang_cc1 %s -cl-std=CL2.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS="const volatile" // RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS= -// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS= -cl-ext=-cl_khr_subgroups +// RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS= -cl-ext=-cl_khr_subgroups,-__opencl_c_subgroups // RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir-unknown-unknown" -verify -pedantic -fsyntax-only -DB32 -DQUALS="const volatile" // RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS= // RUN: %clang_cc1 %s -cl-std=CL3.0 -triple "spir64-unknown-unknown" -verify -pedantic -fsyntax-only -Wconversion -DWCONV -DQUALS="const volatile" @@ -241,12 +241,12 @@ kernel void bar(global unsigned int *buf) kernel void foo1(global unsigned int *buf) { ndrange_t n; - buf[0] = get_kernel_max_sub_group_size_for_ndrange(n, ^(){}); // expected-error {{use of declaration 'get_kernel_max_sub_group_size_for_ndrange' requires cl_khr_subgroups support}} + buf[0] = get_kernel_max_sub_group_size_for_ndrange(n, ^(){}); // expected-error {{use of declaration 'get_kernel_max_sub_group_size_for_ndrange' requires cl_khr_subgroups or __opencl_c_subgroups support}} } kernel void bar1(global unsigned int *buf) { ndrange_t n; - buf[0] = get_kernel_sub_group_count_for_ndrange(n, ^(){}); // expected-error {{use of declaration 'get_kernel_sub_group_count_for_ndrange' requires cl_khr_subgroups support}} + buf[0] = get_kernel_sub_group_count_for_ndrange(n, ^(){}); // expected-error {{use of declaration 'get_kernel_sub_group_count_for_ndrange' requires cl_khr_subgroups or __opencl_c_subgroups support}} } #endif // ifdef cl_khr_subgroups From 200390c3c17196b9c0f34453eeb85175015b2283 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Tue, 8 Feb 2022 10:48:32 +0200 Subject: [PATCH 102/316] [clang] [MinGW] Recognize -lcrtdll as a library replacing -lmsvcrt Differential Revision: https://reviews.llvm.org/D119234 (cherry picked from commit 079b6d02d1f52301e2d3276fadba822bf87b75b2) --- clang/lib/Driver/ToolChains/MinGW.cpp | 4 +++- clang/test/Driver/mingw-msvcrt.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/MinGW.cpp b/clang/lib/Driver/ToolChains/MinGW.cpp index 0501f97374044..ceeaa79bc2021 100644 --- a/clang/lib/Driver/ToolChains/MinGW.cpp +++ b/clang/lib/Driver/ToolChains/MinGW.cpp @@ -86,7 +86,9 @@ void tools::MinGW::Linker::AddLibGCC(const ArgList &Args, CmdArgs.push_back("-lmoldname"); CmdArgs.push_back("-lmingwex"); for (auto Lib : Args.getAllArgValues(options::OPT_l)) - if (StringRef(Lib).startswith("msvcr") || StringRef(Lib).startswith("ucrt")) + if (StringRef(Lib).startswith("msvcr") || + StringRef(Lib).startswith("ucrt") || + StringRef(Lib).startswith("crtdll")) return; CmdArgs.push_back("-lmsvcrt"); } diff --git a/clang/test/Driver/mingw-msvcrt.c b/clang/test/Driver/mingw-msvcrt.c index bb4813ca33a5a..48a30d8469cb6 100644 --- a/clang/test/Driver/mingw-msvcrt.c +++ b/clang/test/Driver/mingw-msvcrt.c @@ -2,6 +2,7 @@ // RUN: %clang -v -target i686-pc-windows-gnu -lmsvcr120 -### %s 2>&1 | FileCheck -check-prefix=CHECK_MSVCR120 %s // RUN: %clang -v -target i686-pc-windows-gnu -lucrtbase -### %s 2>&1 | FileCheck -check-prefix=CHECK_UCRTBASE %s // RUN: %clang -v -target i686-pc-windows-gnu -lucrt -### %s 2>&1 | FileCheck -check-prefix=CHECK_UCRT %s +// RUN: %clang -v -target i686-pc-windows-gnu -lcrtdll -### %s 2>&1 | FileCheck -check-prefix=CHECK_CRTDLL %s // CHECK_DEFAULT: "-lmingwex" "-lmsvcrt" "-ladvapi32" // CHECK_DEFAULT-SAME: "-lmsvcrt" "-lkernel32" "{{.*}}crtend.o" @@ -11,3 +12,5 @@ // CHECK_UCRTBASE-SAME: "-lmingwex" "-ladvapi32" // CHECK_UCRT: "-lucrt" // CHECK_UCRT-SAME: "-lmingwex" "-ladvapi32" +// CHECK_CRTDLL: "-lcrtdll" +// CHECK_CRTDLL-SAME: "-lmingwex" "-ladvapi32" From b9f51faa087ae639ea231a86d3210b96accf0306 Mon Sep 17 00:00:00 2001 From: Amy Kwan Date: Thu, 3 Feb 2022 21:31:44 -0600 Subject: [PATCH 103/316] [test-release.sh] Set TEST_SUITE_HOST_CC to the release testing build compiler when compiling test-suite tools. The tools used by test-suite are originally configured to compile with cc by default, and this is dictated by TEST_SUITE_HOST_CC. However, it is possible that on some systems that the version of cc may either not be present or it may not be able to compile the tools as it may be too old, which could be an issue seen during release testing. This patch updates the compiler to be the default build compiler that is used for release testing. If no such compiler it specified, then cc will be set as the test-suite tools build compiler by default (as it already is set under TEST_SUITE_HOST_CC). Differential Revision: https://reviews.llvm.org/D118357 (cherry picked from commit 413b35cd74e42f6371641bc9dc6c707aedac82ff) --- llvm/utils/release/test-release.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index 5cb7f186c530c..009f9358145f3 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -455,7 +455,8 @@ function test_llvmCore() { if [ $do_test_suite = 'yes' ]; then cd $TestSuiteBuildDir env CC="$c_compiler" CXX="$cxx_compiler" \ - cmake $TestSuiteSrcDir -G "$generator" -DTEST_SUITE_LIT=$Lit + cmake $TestSuiteSrcDir -G "$generator" -DTEST_SUITE_LIT=$Lit \ + -DTEST_SUITE_HOST_CC=$build_compiler if ! ( ${MAKE} -j $NumJobs $KeepGoing check \ 2>&1 | tee $LogDir/llvm.check-Phase$Phase-$Flavor.log ) ; then @@ -551,6 +552,8 @@ for Flavor in $Flavors ; do c_compiler="$CC" cxx_compiler="$CXX" + build_compiler="$CC" + [[ -z "$build_compiler" ]] && build_compiler="cc" llvmCore_phase1_objdir=$BuildDir/Phase1/$Flavor/llvmCore-$Release-$RC.obj llvmCore_phase1_destdir=$BuildDir/Phase1/$Flavor/llvmCore-$Release-$RC.install From 9fa896f9e48f54efce4a44bd5e1310b442283da7 Mon Sep 17 00:00:00 2001 From: Balazs Benics Date: Wed, 2 Feb 2022 12:55:44 +0100 Subject: [PATCH 104/316] [scan-build] Fix deadlock at failures in libears/ear.c We experienced some deadlocks when we used multiple threads for logging using `scan-builds` intercept-build tool when we used multiple threads by e.g. logging `make -j16` ``` (gdb) bt #0 0x00007f2bb3aff110 in __lll_lock_wait () from /lib/x86_64-linux-gnu/libpthread.so.0 #1 0x00007f2bb3af70a3 in pthread_mutex_lock () from /lib/x86_64-linux-gnu/libpthread.so.0 #2 0x00007f2bb3d152e4 in ?? () #3 0x00007ffcc5f0cc80 in ?? () #4 0x00007f2bb3d2bf5b in ?? () from /lib64/ld-linux-x86-64.so.2 #5 0x00007f2bb3b5da27 in ?? () from /lib/x86_64-linux-gnu/libc.so.6 #6 0x00007f2bb3b5dbe0 in exit () from /lib/x86_64-linux-gnu/libc.so.6 #7 0x00007f2bb3d144ee in ?? () #8 0x746e692f706d742f in ?? () #9 0x692d747065637265 in ?? () #10 0x2f653631326b3034 in ?? () #11 0x646d632e35353532 in ?? () #12 0x0000000000000000 in ?? () ``` I think the gcc's exit call caused the injected `libear.so` to be unloaded by the `ld`, which in turn called the `void on_unload() __attribute__((destructor))`. That tried to acquire an already locked mutex which was left locked in the `bear_report_call()` call, that probably encountered some error and returned early when it forgot to unlock the mutex. All of these are speculation since from the backtrace I could not verify if frames 2 and 3 are in fact corresponding to the `libear.so` module. But I think it's a fairly safe bet. So, hereby I'm releasing the held mutex on *all paths*, even if some failure happens. PS: I would use lock_guards, but it's C. Reviewed-by: NoQ Differential Revision: https://reviews.llvm.org/D118439 (cherry picked from commit d919d027ba2a41df5d51ce82ae7f2fb64d2cba41) --- clang/tools/scan-build-py/lib/libear/ear.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/clang/tools/scan-build-py/lib/libear/ear.c b/clang/tools/scan-build-py/lib/libear/ear.c index b06ec7ab00040..94cb865bd0cab 100644 --- a/clang/tools/scan-build-py/lib/libear/ear.c +++ b/clang/tools/scan-build-py/lib/libear/ear.c @@ -411,6 +411,7 @@ static void bear_report_call(char const *fun, char const *const argv[]) { const char *cwd = getcwd(NULL, 0); if (0 == cwd) { perror("bear: getcwd"); + pthread_mutex_unlock(&mutex); exit(EXIT_FAILURE); } char const *const out_dir = initial_env[0]; @@ -419,11 +420,13 @@ static void bear_report_call(char const *fun, char const *const argv[]) { if (-1 == snprintf(filename, path_max_length, "%s/%d.cmd", out_dir, getpid())) { perror("bear: snprintf"); + pthread_mutex_unlock(&mutex); exit(EXIT_FAILURE); } FILE *fd = fopen(filename, "a+"); if (0 == fd) { perror("bear: fopen"); + pthread_mutex_unlock(&mutex); exit(EXIT_FAILURE); } fprintf(fd, "%d%c", getpid(), RS); @@ -437,6 +440,7 @@ static void bear_report_call(char const *fun, char const *const argv[]) { fprintf(fd, "%c", GS); if (fclose(fd)) { perror("bear: fclose"); + pthread_mutex_unlock(&mutex); exit(EXIT_FAILURE); } free((void *)cwd); From f0b442c8ac58bbd40489defd2f3d65ff0b02b09c Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 8 Feb 2022 13:06:44 -0500 Subject: [PATCH 105/316] [release] Use a supported way of building libc++ when building the documentation Instead of using the deprecated LLVM_ENABLE_PROJECTS build, use the default runtimes build. This is just as fast, but it's supported. Differential Revision: https://reviews.llvm.org/D119275 (cherry picked from commit f34f7dfe3a3d8a6ec2c582f5672c3ca37d9aed7c) --- llvm/utils/release/build-docs.sh | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/llvm/utils/release/build-docs.sh b/llvm/utils/release/build-docs.sh index 8b12a4526e133..6d416e4830e64 100755 --- a/llvm/utils/release/build-docs.sh +++ b/llvm/utils/release/build-docs.sh @@ -90,7 +90,7 @@ if [ -n "$release" ]; then fi cmake -G Ninja $srcdir -B $builddir \ - -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld;libcxx;polly;flang" \ + -DLLVM_ENABLE_PROJECTS="clang;clang-tools-extra;lld;polly;flang" \ -DCMAKE_BUILD_TYPE=Release \ -DLLVM_ENABLE_DOXYGEN=ON \ -DLLVM_ENABLE_SPHINX=ON \ @@ -102,7 +102,6 @@ ninja -C $builddir \ docs-clang-html \ docs-clang-tools-html \ docs-flang-html \ - docs-libcxx-html \ docs-lld-html \ docs-llvm-html \ docs-polly-html \ @@ -113,6 +112,13 @@ ninja -C $builddir \ doxygen-mlir \ doxygen-polly +cmake -G Ninja $srcdir/../runtimes -B $builddir/runtimes-doc \ + -DLLVM_ENABLE_RUNTIMES="libcxx" \ + -DLLVM_ENABLE_SPHINX=ON \ + -DSPHINX_WARNINGS_AS_ERRORS=OFF + +ninja -C $builddir/runtimes-doc \ + docs-libcxx-html \ package_doxygen llvm . package_doxygen clang tools/clang @@ -121,7 +127,13 @@ package_doxygen flang tools/flang html_dir=$builddir/html-export/ -for d in docs/ tools/clang/docs/ tools/lld/docs/ tools/clang/tools/extra/docs/ projects/libcxx/docs/ tools/polly/docs/ tools/flang/docs/; do +for d in docs/ tools/clang/docs/ tools/lld/docs/ tools/clang/tools/extra/docs/ tools/polly/docs/ tools/flang/docs/; do mkdir -p $html_dir/$d mv $builddir/$d/html/* $html_dir/$d/ done + +# Keep the documentation for the runtimes under /projects/ to avoid breaking existing links. +for d in libcxx/docs/; do + mkdir -p $html_dir/projects/$d + mv $builddir/runtimes-doc/$d/html/* $html_dir/projects/$d/ +done From 01e3eb2bd438089ced550ab74de497f2bfa67038 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sat, 12 Feb 2022 22:02:47 -0500 Subject: [PATCH 106/316] [OpenMP][Offloading] Fix infinite loop in applyToShadowMapEntries This patch fixes the issue that the for loop in `applyToShadowMapEntries` is infinite because `Itr` is not incremented in `CB`. Fixes #53727. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D119471 (cherry picked from commit c27f530d4c6306b2010306131f66e771d6a66594) --- openmp/libomptarget/src/omptarget.cpp | 2 + .../libomptarget/test/offloading/bug53727.cpp | 57 +++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 openmp/libomptarget/test/offloading/bug53727.cpp diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index c8504c8ea5ff9..304091e4f2f1d 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -889,6 +889,7 @@ static int targetDataContiguous(ident_t *loc, DeviceTy &Device, void *ArgsBase, DP("Restoring original host pointer value " DPxMOD " for host pointer " DPxMOD "\n", DPxPTR(Itr->second.HstPtrVal), DPxPTR(ShadowHstPtrAddr)); + ++Itr; return OFFLOAD_SUCCESS; }; applyToShadowMapEntries(Device, CB, HstPtrBegin, ArgSize, TPR); @@ -911,6 +912,7 @@ static int targetDataContiguous(ident_t *loc, DeviceTy &Device, void *ArgsBase, sizeof(void *), AsyncInfo); if (Ret != OFFLOAD_SUCCESS) REPORT("Copying data to device failed.\n"); + ++Itr; return Ret; }; applyToShadowMapEntries(Device, CB, HstPtrBegin, ArgSize, TPR); diff --git a/openmp/libomptarget/test/offloading/bug53727.cpp b/openmp/libomptarget/test/offloading/bug53727.cpp new file mode 100644 index 0000000000000..4744024dfec47 --- /dev/null +++ b/openmp/libomptarget/test/offloading/bug53727.cpp @@ -0,0 +1,57 @@ +// RUN: %libomptarget-compilexx-and-run-generic + +#include +#include + +constexpr const int N = 10; + +struct T { + int a; + int *p; +}; + +struct S { + int b; + T t; +}; + +int main(int argc, char *argv[]) { + S s; + s.t.p = new int[N]; + for (int i = 0; i < N; ++i) { + s.t.p[i] = i; + } + +#pragma omp target enter data map(to : s, s.t.p[:N]) + +#pragma omp target + { + for (int i = 0; i < N; ++i) { + s.t.p[i] += i; + } + } + +#pragma omp target update from(s.t.p[:N]) + + for (int i = 0; i < N; ++i) { + assert(s.t.p[i] == 2 * i); + s.t.p[i] += i; + } + +#pragma omp target update to(s.t.p[:N]) + +#pragma omp target + { + for (int i = 0; i < N; ++i) { + s.t.p[i] += i; + } + } + +#pragma omp target exit data map(from : s, s.t.p[:N]) + + for (int i = 0; i < N; ++i) { + assert(s.t.p[i] == 4 * i); + } + + return 0; +} From af19ae529271f9ae96927662d7d876489115fb26 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Wed, 1 Dec 2021 16:14:54 +0000 Subject: [PATCH 107/316] Reland "[lldb] Remove non address bits when looking up memory regions" (cherry picked from 2937b282188bafb6bdb65ee87c70e9109aa910b7) This reverts commit 0df522969a7a0128052bd79182c8d58e00556e2f. Additional checks are added to fix the detection of the last memory region in GetMemoryRegions or repeating the "memory region" command when the target has non-address bits. Normally you keep reading from address 0, looking up each region's end address until you get LLDB_INVALID_ADDR as the region end address. (0xffffffffffffffff) This is what the remote will return once you go beyond the last mapped region: [0x0000fffffffdf000-0x0001000000000000) rw- [stack] [0x0001000000000000-0xffffffffffffffff) --- Problem is that when we "fix" the lookup address, we remove some bits from it. On an AArch64 system we have 48 bit virtual addresses, so when we fix the end address of the [stack] region the result is 0. So we loop back to the start. [0x0000fffffffdf000-0x0001000000000000) rw- [stack] [0x0000000000000000-0x0000000000400000) --- To fix this I added an additional check for the last range. If the end address of the region is different once you apply FixDataAddress, we are at the last region. Since the end of the last region will be the last valid mappable address, plus 1. That 1 will be removed by the ABI plugin. The only side effect is that on systems with non-address bits, you won't get that last catch all unmapped region from the max virtual address up to 0xf...f. [0x0000fffff8000000-0x0000fffffffdf000) --- [0x0000fffffffdf000-0x0001000000000000) rw- [stack] Though in some way this is more correct because that region is not just unmapped, it's not mappable at all. No extra testing is needed because this is already covered by TestMemoryRegion.py, I simply forgot to run it on system that had both top byte ignore and pointer authentication. This change has been tested on a qemu VM with top byte ignore, memory tagging and pointer authentication enabled. Reviewed By: omjavaid Differential Revision: https://reviews.llvm.org/D115508 --- lldb/include/lldb/Target/Process.h | 38 +++++++--- lldb/source/Commands/CommandObjectMemory.cpp | 20 ++++-- .../Process/Windows/Common/ProcessWindows.cpp | 4 +- .../Process/Windows/Common/ProcessWindows.h | 6 +- .../Process/elf-core/ProcessElfCore.cpp | 4 +- .../Plugins/Process/elf-core/ProcessElfCore.h | 8 +-- .../Process/gdb-remote/ProcessGDBRemote.cpp | 4 +- .../Process/gdb-remote/ProcessGDBRemote.h | 6 +- .../Process/mach-core/ProcessMachCore.cpp | 4 +- .../Process/mach-core/ProcessMachCore.h | 8 +-- .../Process/minidump/ProcessMinidump.cpp | 4 +- .../Process/minidump/ProcessMinidump.h | 6 +- .../Process/scripted/ScriptedProcess.cpp | 4 +- .../Process/scripted/ScriptedProcess.h | 6 +- lldb/source/Target/Process.cpp | 23 +++++- .../aarch64/tagged_memory_region/Makefile | 3 + .../TestAArch64LinuxTaggedMemoryRegion.py | 70 +++++++++++++++++++ .../linux/aarch64/tagged_memory_region/main.c | 17 +++++ llvm/docs/ReleaseNotes.rst | 7 ++ 19 files changed, 193 insertions(+), 49 deletions(-) create mode 100644 lldb/test/API/linux/aarch64/tagged_memory_region/Makefile create mode 100644 lldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py create mode 100644 lldb/test/API/linux/aarch64/tagged_memory_region/main.c diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 12ed1e09227cf..7911dac40b705 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -1759,7 +1759,7 @@ class Process : public std::enable_shared_from_this, /// /// If load_addr is within the address space the process has mapped /// range_info will be filled in with the start and end of that range as - /// well as the permissions for that range and range_info.GetMapped will + /// well as the permissions for that range and range_info. GetMapped will /// return true. /// /// If load_addr is outside any mapped region then range_info will have its @@ -1768,23 +1768,21 @@ class Process : public std::enable_shared_from_this, /// there are no valid mapped ranges between load_addr and the end of the /// process address space. /// - /// GetMemoryRegionInfo will only return an error if it is unimplemented for - /// the current process. + /// GetMemoryRegionInfo calls DoGetMemoryRegionInfo. Override that function in + /// process subclasses. /// /// \param[in] load_addr - /// The load address to query the range_info for. + /// The load address to query the range_info for. May include non + /// address bits, these will be removed by the the ABI plugin if there is + /// one. /// /// \param[out] range_info /// An range_info value containing the details of the range. /// /// \return /// An error value. - virtual Status GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo &range_info) { - Status error; - error.SetErrorString("Process::GetMemoryRegionInfo() not supported"); - return error; - } + Status GetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo &range_info); /// Obtain all the mapped memory regions within this process. /// @@ -2604,6 +2602,26 @@ void PruneThreadPlans(); virtual size_t DoReadMemory(lldb::addr_t vm_addr, void *buf, size_t size, Status &error) = 0; + /// DoGetMemoryRegionInfo is called by GetMemoryRegionInfo after it has + /// removed non address bits from load_addr. Override this method in + /// subclasses of Process. + /// + /// See GetMemoryRegionInfo for details of the logic. + /// + /// \param[in] load_addr + /// The load address to query the range_info for. (non address bits + /// removed) + /// + /// \param[out] range_info + /// An range_info value containing the details of the range. + /// + /// \return + /// An error value. + virtual Status DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo &range_info) { + return Status("Process::DoGetMemoryRegionInfo() not supported"); + } + lldb::StateType GetPrivateState(); /// The "private" side of resuming a process. This doesn't alter the state diff --git a/lldb/source/Commands/CommandObjectMemory.cpp b/lldb/source/Commands/CommandObjectMemory.cpp index 1b44a1bd709a9..1033d13f9f260 100644 --- a/lldb/source/Commands/CommandObjectMemory.cpp +++ b/lldb/source/Commands/CommandObjectMemory.cpp @@ -1665,14 +1665,11 @@ class CommandObjectMemoryRegion : public CommandObjectParsed { m_prev_end_addr = LLDB_INVALID_ADDRESS; const size_t argc = command.GetArgumentCount(); - if (argc > 1 || (argc == 0 && load_addr == LLDB_INVALID_ADDRESS)) { - result.AppendErrorWithFormat("'%s' takes one argument:\nUsage: %s\n", - m_cmd_name.c_str(), m_cmd_syntax.c_str()); - return false; - } + const lldb::ABISP &abi = process_sp->GetABI(); if (argc == 1) { auto load_addr_str = command[0].ref(); + // Non-address bits in this will be handled later by GetMemoryRegion load_addr = OptionArgParser::ToAddress(&m_exe_ctx, load_addr_str, LLDB_INVALID_ADDRESS, &error); if (error.Fail() || load_addr == LLDB_INVALID_ADDRESS) { @@ -1680,6 +1677,19 @@ class CommandObjectMemoryRegion : public CommandObjectParsed { command[0].c_str(), error.AsCString()); return false; } + } else if (argc > 1 || + // When we're repeating the command, the previous end address is + // used for load_addr. If that was 0xF...F then we must have + // reached the end of memory. + (argc == 0 && load_addr == LLDB_INVALID_ADDRESS) || + // If the target has non-address bits (tags, limited virtual + // address size, etc.), the end of mappable memory will be lower + // than that. So if we find any non-address bit set, we must be + // at the end of the mappable range. + (abi && (abi->FixDataAddress(load_addr) != load_addr))) { + result.AppendErrorWithFormat("'%s' takes one argument:\nUsage: %s\n", + m_cmd_name.c_str(), m_cmd_syntax.c_str()); + return false; } lldb_private::MemoryRegionInfo range_info; diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp index 5398d16777ac4..ba2ed2056d20e 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp @@ -601,8 +601,8 @@ Status ProcessWindows::DoDeallocateMemory(lldb::addr_t ptr) { return ProcessDebugger::DeallocateMemory(ptr); } -Status ProcessWindows::GetMemoryRegionInfo(lldb::addr_t vm_addr, - MemoryRegionInfo &info) { +Status ProcessWindows::DoGetMemoryRegionInfo(lldb::addr_t vm_addr, + MemoryRegionInfo &info) { return ProcessDebugger::GetMemoryRegionInfo(vm_addr, info); } diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h index fc83649818edd..6f6f93f588e33 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h @@ -78,8 +78,6 @@ class ProcessWindows : public Process, public ProcessDebugger { lldb::addr_t DoAllocateMemory(size_t size, uint32_t permissions, Status &error) override; Status DoDeallocateMemory(lldb::addr_t ptr) override; - Status GetMemoryRegionInfo(lldb::addr_t vm_addr, - MemoryRegionInfo &info) override; lldb::addr_t GetImageInfoAddress() override; @@ -103,6 +101,10 @@ class ProcessWindows : public Process, public ProcessDebugger { Status EnableWatchpoint(Watchpoint *wp, bool notify = true) override; Status DisableWatchpoint(Watchpoint *wp, bool notify = true) override; +protected: + Status DoGetMemoryRegionInfo(lldb::addr_t vm_addr, + MemoryRegionInfo &info) override; + private: struct WatchpointInfo { uint32_t slot_id; diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp index 65dbc8ea95b31..043544f056655 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp @@ -285,8 +285,8 @@ size_t ProcessElfCore::ReadMemory(lldb::addr_t addr, void *buf, size_t size, return DoReadMemory(addr, buf, size, error); } -Status ProcessElfCore::GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo ®ion_info) { +Status ProcessElfCore::DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo ®ion_info) { region_info.Clear(); const VMRangeToPermissions::Entry *permission_entry = m_core_range_infos.FindEntryThatContainsOrFollows(load_addr); diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h index 67df3c5fac76a..fd36e50278168 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h @@ -86,10 +86,6 @@ class ProcessElfCore : public lldb_private::PostMortemProcess { size_t DoReadMemory(lldb::addr_t addr, void *buf, size_t size, lldb_private::Status &error) override; - lldb_private::Status - GetMemoryRegionInfo(lldb::addr_t load_addr, - lldb_private::MemoryRegionInfo ®ion_info) override; - lldb::addr_t GetImageInfoAddress() override; lldb_private::ArchSpec GetArchitecture(); @@ -105,6 +101,10 @@ class ProcessElfCore : public lldb_private::PostMortemProcess { bool DoUpdateThreadList(lldb_private::ThreadList &old_thread_list, lldb_private::ThreadList &new_thread_list) override; + lldb_private::Status + DoGetMemoryRegionInfo(lldb::addr_t load_addr, + lldb_private::MemoryRegionInfo ®ion_info) override; + private: struct NT_FILE_Entry { lldb::addr_t start; diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 82357cd117d78..fee2071a0780f 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -2962,8 +2962,8 @@ lldb::addr_t ProcessGDBRemote::DoAllocateMemory(size_t size, return allocated_addr; } -Status ProcessGDBRemote::GetMemoryRegionInfo(addr_t load_addr, - MemoryRegionInfo ®ion_info) { +Status ProcessGDBRemote::DoGetMemoryRegionInfo(addr_t load_addr, + MemoryRegionInfo ®ion_info) { Status error(m_gdb_comm.GetMemoryRegionInfo(load_addr, region_info)); return error; diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h index bdf130e3ec110..dd907042608da 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h @@ -143,9 +143,6 @@ class ProcessGDBRemote : public Process, lldb::addr_t DoAllocateMemory(size_t size, uint32_t permissions, Status &error) override; - Status GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo ®ion_info) override; - Status DoDeallocateMemory(lldb::addr_t ptr) override; // Process STDIO @@ -415,6 +412,9 @@ class ProcessGDBRemote : public Process, Status DoWriteMemoryTags(lldb::addr_t addr, size_t len, int32_t type, const std::vector &tags) override; + Status DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo ®ion_info) override; + private: // For ProcessGDBRemote only std::string m_partial_profile_data; diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp index 4b3e244dcb23f..cd68f291b16d6 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp @@ -659,8 +659,8 @@ size_t ProcessMachCore::DoReadMemory(addr_t addr, void *buf, size_t size, return bytes_read; } -Status ProcessMachCore::GetMemoryRegionInfo(addr_t load_addr, - MemoryRegionInfo ®ion_info) { +Status ProcessMachCore::DoGetMemoryRegionInfo(addr_t load_addr, + MemoryRegionInfo ®ion_info) { region_info.Clear(); const VMRangeToPermissions::Entry *permission_entry = m_core_range_infos.FindEntryThatContainsOrFollows(load_addr); diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h index e55bfcfcc723b..b5ca515a7d3fb 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h @@ -68,10 +68,6 @@ class ProcessMachCore : public lldb_private::PostMortemProcess { size_t DoReadMemory(lldb::addr_t addr, void *buf, size_t size, lldb_private::Status &error) override; - lldb_private::Status - GetMemoryRegionInfo(lldb::addr_t load_addr, - lldb_private::MemoryRegionInfo ®ion_info) override; - lldb::addr_t GetImageInfoAddress() override; protected: @@ -84,6 +80,10 @@ class ProcessMachCore : public lldb_private::PostMortemProcess { lldb_private::ObjectFile *GetCoreObjectFile(); + lldb_private::Status + DoGetMemoryRegionInfo(lldb::addr_t load_addr, + lldb_private::MemoryRegionInfo ®ion_info) override; + private: bool GetDynamicLoaderAddress(lldb::addr_t addr); diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp index 37ee5466c5b98..162697bed7e93 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp @@ -439,8 +439,8 @@ void ProcessMinidump::BuildMemoryRegions() { llvm::sort(*m_memory_regions); } -Status ProcessMinidump::GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo ®ion) { +Status ProcessMinidump::DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo ®ion) { BuildMemoryRegions(); region = MinidumpParser::GetMemoryRegionInfo(*m_memory_regions, load_addr); return Status(); diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h index 3501d38a0f27e..5360269199cdd 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h @@ -75,9 +75,6 @@ class ProcessMinidump : public PostMortemProcess { ArchSpec GetArchitecture(); - Status GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo &range_info) override; - Status GetMemoryRegions( lldb_private::MemoryRegionInfos ®ion_list) override; @@ -98,6 +95,9 @@ class ProcessMinidump : public PostMortemProcess { bool DoUpdateThreadList(ThreadList &old_thread_list, ThreadList &new_thread_list) override; + Status DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo &range_info) override; + void ReadModuleList(); lldb::ModuleSP GetOrCreateModule(lldb_private::UUID minidump_uuid, diff --git a/lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp b/lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp index 5eb7cb0e6a5c8..c231ea6b0d10f 100644 --- a/lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp +++ b/lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp @@ -245,8 +245,8 @@ ArchSpec ScriptedProcess::GetArchitecture() { return GetTarget().GetArchitecture(); } -Status ScriptedProcess::GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo ®ion) { +Status ScriptedProcess::DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo ®ion) { CheckInterpreterAndScriptObject(); Status error; diff --git a/lldb/source/Plugins/Process/scripted/ScriptedProcess.h b/lldb/source/Plugins/Process/scripted/ScriptedProcess.h index d56658a2e48af..c8355f35548a8 100644 --- a/lldb/source/Plugins/Process/scripted/ScriptedProcess.h +++ b/lldb/source/Plugins/Process/scripted/ScriptedProcess.h @@ -84,9 +84,6 @@ class ScriptedProcess : public Process { ArchSpec GetArchitecture(); - Status GetMemoryRegionInfo(lldb::addr_t load_addr, - MemoryRegionInfo &range_info) override; - Status GetMemoryRegions(lldb_private::MemoryRegionInfos ®ion_list) override; @@ -100,6 +97,9 @@ class ScriptedProcess : public Process { bool DoUpdateThreadList(ThreadList &old_thread_list, ThreadList &new_thread_list) override; + Status DoGetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo &range_info) override; + private: friend class ScriptedThread; diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index 94f378886e50e..6a306ab762da0 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -5853,12 +5853,18 @@ Process::AdvanceAddressToNextBranchInstruction(Address default_stop_addr, return retval; } -Status -Process::GetMemoryRegions(lldb_private::MemoryRegionInfos ®ion_list) { +Status Process::GetMemoryRegionInfo(lldb::addr_t load_addr, + MemoryRegionInfo &range_info) { + if (const lldb::ABISP &abi = GetABI()) + load_addr = abi->FixDataAddress(load_addr); + return DoGetMemoryRegionInfo(load_addr, range_info); +} +Status Process::GetMemoryRegions(lldb_private::MemoryRegionInfos ®ion_list) { Status error; lldb::addr_t range_end = 0; + const lldb::ABISP &abi = GetABI(); region_list.clear(); do { @@ -5870,11 +5876,22 @@ Process::GetMemoryRegions(lldb_private::MemoryRegionInfos ®ion_list) { break; } + // We only check the end address, not start and end, because we assume that + // the start will not have non-address bits until the first unmappable + // region. We will have exited the loop by that point because the previous + // region, the last mappable region, will have non-address bits in its end + // address. range_end = region_info.GetRange().GetRangeEnd(); if (region_info.GetMapped() == MemoryRegionInfo::eYes) { region_list.push_back(std::move(region_info)); } - } while (range_end != LLDB_INVALID_ADDRESS); + } while ( + // For a process with no non-address bits, all address bits + // set means the end of memory. + range_end != LLDB_INVALID_ADDRESS && + // If we have non-address bits and some are set then the end + // is at or beyond the end of mappable memory. + !(abi && (abi->FixDataAddress(range_end) != range_end))); return error; } diff --git a/lldb/test/API/linux/aarch64/tagged_memory_region/Makefile b/lldb/test/API/linux/aarch64/tagged_memory_region/Makefile new file mode 100644 index 0000000000000..10495940055b6 --- /dev/null +++ b/lldb/test/API/linux/aarch64/tagged_memory_region/Makefile @@ -0,0 +1,3 @@ +C_SOURCES := main.c + +include Makefile.rules diff --git a/lldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py b/lldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py new file mode 100644 index 0000000000000..0b5f341574e00 --- /dev/null +++ b/lldb/test/API/linux/aarch64/tagged_memory_region/TestAArch64LinuxTaggedMemoryRegion.py @@ -0,0 +1,70 @@ +""" +Test that "memory region" lookup uses the ABI plugin to remove +non address bits from addresses before lookup. +""" + + + +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class AArch64LinuxTaggedMemoryRegionTestCase(TestBase): + + mydir = TestBase.compute_mydir(__file__) + + NO_DEBUG_INFO_TESTCASE = True + + # AArch64 Linux always enables the top byte ignore feature + @skipUnlessArch("aarch64") + @skipUnlessPlatform(["linux"]) + def test_mte_regions(self): + self.build() + self.runCmd("file " + self.getBuildArtifact("a.out"), CURRENT_EXECUTABLE_SET) + + lldbutil.run_break_set_by_file_and_line(self, "main.c", + line_number('main.c', '// Set break point at this line.'), + num_expected_locations=1) + + self.runCmd("run", RUN_SUCCEEDED) + + if self.process().GetState() == lldb.eStateExited: + self.fail("Test program failed to run.") + + self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT, + substrs=['stopped', + 'stop reason = breakpoint']) + + # Despite the non address bits we should find a region + self.expect("memory region the_page", patterns=[ + "\[0x[0-9A-Fa-f]+-0x[0-9A-Fa-f]+\) r-x"]) + + # Check that the usual error message is displayed after repeating + # the command until the last region. + self.runCmd("memory region 0") + + # Count the number of repeats for use in the next check + repeats = 0 + interp = self.dbg.GetCommandInterpreter() + result = lldb.SBCommandReturnObject() + + while True: + interp.HandleCommand("memory region", result) + if result.Succeeded(): + repeats += 1 + else: + self.assertRegexpMatches(result.GetError(), "Usage: memory region ADDR") + break + + # This time repeat until we get the last region. At that + # point the previous address will have non-address bits in it. + self.runCmd("memory region 0") + for i in range(repeats): + self.runCmd("memory region") + + # This should not error, since the user supplied address overrides + # the previous end address. + self.expect("memory region the_page", patterns=[ + "\[0x[0-9A-Fa-f]+-0x[0-9A-Fa-f]+\) r-x"]) diff --git a/lldb/test/API/linux/aarch64/tagged_memory_region/main.c b/lldb/test/API/linux/aarch64/tagged_memory_region/main.c new file mode 100644 index 0000000000000..29f99d73e12d1 --- /dev/null +++ b/lldb/test/API/linux/aarch64/tagged_memory_region/main.c @@ -0,0 +1,17 @@ +#include +#include +#include +#include + +int main(int argc, char const *argv[]) { + void *the_page = mmap(0, sysconf(_SC_PAGESIZE), PROT_READ | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (the_page == MAP_FAILED) + return 1; + + // Put something in the top byte (AArch64 Linux always enables top byte + // ignore) + the_page = (void *)((size_t)the_page | ((size_t)0x34 << 56)); + + return 0; // Set break point at this line. +} diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 08ebd6c092f5f..32536eae9e548 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -205,9 +205,16 @@ Changes to LLDB * ``memory find`` * ``memory read`` + * ``memory region`` (see below) * ``memory tag read`` * ``memory tag write`` +* The ``memory region`` command and ``GetMemoryRegionInfo`` API method now + ignore non-address bits in the address parameter. This also means that on + systems with non-address bits the last (usually unmapped) memory region + will not extend to 0xF...F. Instead it will end at the end of the mappable + range that the virtual address size allows. + * The ``memory read`` command has a new option ``--show-tags``. Use this option to show memory tags beside the contents of tagged memory ranges. From 78f8449e01f7a397c6ba1cb7e9d0e1e863bbeaa5 Mon Sep 17 00:00:00 2001 From: Jonathan Peyton Date: Wed, 9 Feb 2022 08:04:47 -0600 Subject: [PATCH 108/316] [OpenMP][libomp] Replace accidental VLA with KMP_ALLOCA MSVC does not support variable length arrays. Replace with KMP_ALLOCA which is already used in the same file for stack-allocated variables. (cherry picked from commit 6be7c21b57e4a45b012209974ab9038b679134f5) --- openmp/runtime/src/kmp_affinity.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openmp/runtime/src/kmp_affinity.cpp b/openmp/runtime/src/kmp_affinity.cpp index 71e8b7fd10eb6..d1f1b6790e2d5 100644 --- a/openmp/runtime/src/kmp_affinity.cpp +++ b/openmp/runtime/src/kmp_affinity.cpp @@ -948,7 +948,7 @@ bool kmp_topology_t::filter_hw_subset() { bool using_core_effs = false; int hw_subset_depth = __kmp_hw_subset->get_depth(); kmp_hw_t specified[KMP_HW_LAST]; - int topology_levels[hw_subset_depth]; + int *topology_levels = (int *)KMP_ALLOCA(sizeof(int) * hw_subset_depth); KMP_ASSERT(hw_subset_depth > 0); KMP_FOREACH_HW_TYPE(i) { specified[i] = KMP_HW_UNKNOWN; } int core_level = get_level(KMP_HW_CORE); From 8f8a31ec88b5908870960061dcc24007e7682925 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 10 Feb 2022 13:55:29 -0800 Subject: [PATCH 109/316] [RISCV] Add test case for a vsetvli insertion bug found after D118667. We're missing a vsetvli before a vse after a redsum in this test. This appears to be because the vmv.s.x has a VL of 1, but did not trigger a vsetvli because it is a scalar move op and any non-zero VL would work. So it looked at it the predecessors and decided it was that they all had a non-zero vl. Then the redsum was visited, it also took the VL from the predecessors since the vmv.s.x and the 4 was found compatible. Finally we visit the vse and it looks at the BBLocalInfo and sees that is compatible because it contains a VL of 1 from the vmv.s.x, the first instruction in the block. BBLocalInfo was not updated when the vredsum was visited because BBLocalInfo was valid and no vsetvli was generated. I think fundamentally the vmv.s.x optimization has the same first phase and third phase not matching problem that D118667 was trying to fix for stores. Differential Revision: https://reviews.llvm.org/D119516 (cherry picked from commit ba9a7ae798053d7cf741143739351b5a4ac29d8b) --- .../RISCV/rvv/vsetvli-insert-crossbb.mir | 134 ++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir index b222360c4c4e7..70ac53052e05c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -99,6 +99,31 @@ ret void } + define void @redusum_loop(i32* nocapture noundef readonly %a, i32 noundef signext %n, i32* nocapture noundef writeonly %res) #0 { + entry: + br label %vector.body + + vector.body: ; preds = %vector.body, %entry + %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %a, %entry ] + %lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ 2048, %entry ] + %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %0, %vector.body ] + %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %lsr.iv12, align 4 + %0 = add <4 x i32> %wide.load, %vec.phi + %lsr.iv.next = add nsw i64 %lsr.iv, -4 + %scevgep = getelementptr i32, i32* %lsr.iv1, i64 4 + %1 = icmp eq i64 %lsr.iv.next, 0 + br i1 %1, label %middle.block, label %vector.body + + middle.block: ; preds = %vector.body + %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %0) + store i32 %2, i32* %res, align 4 + ret void + } + + ; Function Attrs: nofree nosync nounwind readnone willreturn + declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) + ; Function Attrs: nounwind readnone declare @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(, , i64) #1 @@ -599,3 +624,112 @@ body: | PseudoRET ... +--- +name: redusum_loop +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: vr } + - { id: 3, class: vr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: vr } + - { id: 11, class: vr } + - { id: 12, class: vr } + - { id: 13, class: gpr } + - { id: 14, class: vr } + - { id: 15, class: vr } + - { id: 16, class: vr } + - { id: 17, class: vr } + - { id: 18, class: gpr } + - { id: 19, class: gpr } + - { id: 20, class: vr } + - { id: 21, class: vr } + - { id: 22, class: vr } + - { id: 23, class: vr } + - { id: 24, class: vr } +liveins: + - { reg: '$x10', virtual-reg: '%6' } + - { reg: '$x12', virtual-reg: '%8' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: redusum_loop + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x10, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 80, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 0, 4, 5, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVMV_V_I_M1_]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY2]] + ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1 + ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[LUI]], -2048 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.vector.body: + ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1 + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[PHI]], 4, 5, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4 + ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.middle.block: + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5, implicit $vl, implicit $vtype + ; FIXME: There should be a VSETVLI here. + ; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_]], [[COPY]], 1, 5, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) + ; CHECK-NEXT: PseudoRET + bb.0.entry: + liveins: $x10, $x12 + + %8:gpr = COPY $x12 + %6:gpr = COPY $x10 + %11:vr = PseudoVMV_V_I_M1 0, 4, 5 + %12:vr = COPY %11 + %10:vr = COPY %12 + %13:gpr = LUI 1 + %9:gpr = ADDIW killed %13, -2048 + + bb.1.vector.body: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %0:gpr = PHI %6, %bb.0, %5, %bb.1 + %1:gpr = PHI %9, %bb.0, %4, %bb.1 + %2:vr = PHI %10, %bb.0, %16, %bb.1 + %14:vr = PseudoVLE32_V_M1 %0, 4, 5 :: (load (s128) from %ir.lsr.iv12, align 4) + %16:vr = PseudoVADD_VV_M1 killed %14, %2, 4, 5 + %4:gpr = nsw ADDI %1, -4 + %5:gpr = ADDI %0, 16 + %18:gpr = COPY $x0 + BNE %4, %18, %bb.1 + PseudoBR %bb.2 + + bb.2.middle.block: + %19:gpr = COPY $x0 + %21:vr = IMPLICIT_DEF + %20:vr = PseudoVMV_S_X_M1 %21, %19, 1, 5 + %24:vr = IMPLICIT_DEF + %23:vr = PseudoVREDSUM_VS_M1 %24, %16, killed %20, 4, 5 + PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res) + PseudoRET + +... From e22573ab7b2ddd24699f5e645562cf50f0858e33 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 10 Feb 2022 21:03:12 -0800 Subject: [PATCH 110/316] Revert "[RISCV] Fix a vsetvli insertion bug involving loads/stores." and "[RISCC] Add missing words to comment. NFC" This reverts commit f943c58cae2480755cecdac5be832274f238df93. and commit 7eb781072744b31a60e82b5a5903471032d4845f. This introduced a new bug that appears to be easier to hit. Differential Revision: https://reviews.llvm.org/D119517 (cherry picked from commit f35ac872b8224f771808a9ecd5c4da0fe307ac9c) --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 21 +------------------ .../RISCV/rvv/vsetvli-insert-crossbb.mir | 6 +++++- 2 files changed, 6 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 649eb57b325bf..d39e0805a79c2 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -999,12 +999,6 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require, void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { VSETVLIInfo CurInfo; - // BBLocalInfo tracks the VL/VTYPE state the same way BBInfo.Change was - // calculated in computeIncomingVLVTYPE. We need this to apply - // canSkipVSETVLIForLoadStore the same way computeIncomingVLVTYPE did. We - // can't include predecessor information in that decision to avoid disagreeing - // with the global analysis. - VSETVLIInfo BBLocalInfo; // Only be set if current VSETVLIInfo is from an explicit VSET(I)VLI. MachineInstr *PrevVSETVLIMI = nullptr; @@ -1020,7 +1014,6 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { MI.getOperand(3).setIsDead(false); MI.getOperand(4).setIsDead(false); CurInfo = getInfoForVSETVLI(MI); - BBLocalInfo = getInfoForVSETVLI(MI); PrevVSETVLIMI = &MI; continue; } @@ -1050,22 +1043,12 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { // use the predecessor information. assert(BlockInfo[MBB.getNumber()].Pred.isValid() && "Expected a valid predecessor state."); - // Don't use predecessor information if there was an earlier instruction - // in this block that allowed a vsetvli to be skipped for load/store. - if (!(BBLocalInfo.isValid() && - canSkipVSETVLIForLoadStore(MI, NewInfo, BBLocalInfo)) && - needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) && + if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) && needVSETVLIPHI(NewInfo, MBB)) { insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred); CurInfo = NewInfo; - BBLocalInfo = NewInfo; } - - // We must update BBLocalInfo for every vector instruction. - if (!BBLocalInfo.isValid()) - BBLocalInfo = NewInfo; } else { - assert(BBLocalInfo.isValid()); // If this instruction isn't compatible with the previous VL/VTYPE // we need to insert a VSETVLI. // If this is a unit-stride or strided load/store, we may be able to use @@ -1101,7 +1084,6 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { if (NeedInsertVSETVLI) insertVSETVLI(MBB, MI, NewInfo, CurInfo); CurInfo = NewInfo; - BBLocalInfo = NewInfo; } } PrevVSETVLIMI = nullptr; @@ -1112,7 +1094,6 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) || MI.modifiesRegister(RISCV::VTYPE)) { CurInfo = VSETVLIInfo::getUnknown(); - BBLocalInfo = VSETVLIInfo::getUnknown(); PrevVSETVLIMI = nullptr; } } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir index 70ac53052e05c..c96c6e5a3f4c4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -592,6 +592,10 @@ body: | ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6, implicit $vl, implicit $vtype ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] + ; FIXME: We insert a SEW=32,LMUL=1/2 VSETVLI here but no SEW=64,LMUL=1 + ; VSETVLI before the VADD above. This misconfigures the VADD in the case that + ; the loop takes its backedge. + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 87, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1 @@ -695,7 +699,7 @@ body: | ; CHECK-NEXT: [[PseudoVMV_S_X_M1_:%[0-9]+]]:vr = PseudoVMV_S_X_M1 [[DEF]], [[COPY5]], 1, 5, implicit $vl, implicit $vtype ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1 [[DEF1]], [[PseudoVADD_VV_M1_]], killed [[PseudoVMV_S_X_M1_]], 4, 5, implicit $vl, implicit $vtype - ; FIXME: There should be a VSETVLI here. + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 80, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: PseudoVSE32_V_M1 killed [[PseudoVREDSUM_VS_M1_]], [[COPY]], 1, 5, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) ; CHECK-NEXT: PseudoRET bb.0.entry: From 3b544440f63157411d2bcf0e195329f7560a6991 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 10 Feb 2022 21:33:08 -0800 Subject: [PATCH 111/316] [RISCV] Insert VSETVLI at the end of a basic block if we didn't produce BlockInfo.Exit. This is an alternative to D118667 that instead of fixing the store to match phase 1, it tries to detect the mismatch with the expected value at the end of the block. This inserts a vsetvli after the vse to satisfy the requirement of the other basic block. We still have serious design issues in the pass, that is going to require some rethinking. Differential Revision: https://reviews.llvm.org/D119518 (cherry picked from commit 541c9ba842256023611e5a6c5f01e01c40688044) --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 15 +++++++++++++++ .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir | 4 +--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index d39e0805a79c2..6c4d2682bcd8c 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -334,6 +334,10 @@ class VSETVLIInfo { return false; } + bool operator!=(const VSETVLIInfo &Other) const { + return !(*this == Other); + } + // Calculate the VSETVLIInfo visible to a block assuming this and Other are // both predecessors. VSETVLIInfo intersect(const VSETVLIInfo &Other) const { @@ -1096,6 +1100,17 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { CurInfo = VSETVLIInfo::getUnknown(); PrevVSETVLIMI = nullptr; } + + // If we reach the end of the block and our current info doesn't match the + // expected info, insert a vsetvli to correct. + if (MI.isTerminator()) { + const VSETVLIInfo &ExitInfo = BlockInfo[MBB.getNumber()].Exit; + if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() && + CurInfo != ExitInfo) { + insertVSETVLI(MBB, MI, ExitInfo, CurInfo); + CurInfo = ExitInfo; + } + } } } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir index c96c6e5a3f4c4..1cb41692a8cc8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -592,12 +592,10 @@ body: | ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6, implicit $vl, implicit $vtype ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] - ; FIXME: We insert a SEW=32,LMUL=1/2 VSETVLI here but no SEW=64,LMUL=1 - ; VSETVLI before the VADD above. This misconfigures the VADD in the case that - ; the loop takes its backedge. ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 87, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 88, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1 ; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: {{ $}} From 89fb25f481a5c829498c408bad54c8640ccc6233 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Fri, 28 Jan 2022 14:53:20 +0100 Subject: [PATCH 112/316] [lldb] [Commands] Implement "thread siginfo" Differential Revision: https://reviews.llvm.org/D118473 (cherry picked from commit 287ce6b51675aee43870bebfff68bb144d1ab90e) --- lldb/source/Commands/CommandObjectThread.cpp | 49 +++++++++++++++++++ lldb/test/Shell/Commands/Inputs/sigchld.c | 31 ++++++++++++ .../Commands/command-thread-siginfo.test | 19 +++++++ 3 files changed, 99 insertions(+) create mode 100644 lldb/test/Shell/Commands/Inputs/sigchld.c create mode 100644 lldb/test/Shell/Commands/command-thread-siginfo.test diff --git a/lldb/source/Commands/CommandObjectThread.cpp b/lldb/source/Commands/CommandObjectThread.cpp index 137aaa81c61a0..f6042937a4ff1 100644 --- a/lldb/source/Commands/CommandObjectThread.cpp +++ b/lldb/source/Commands/CommandObjectThread.cpp @@ -1320,6 +1320,53 @@ class CommandObjectThreadException : public CommandObjectIterateOverThreads { } }; +class CommandObjectThreadSiginfo : public CommandObjectIterateOverThreads { +public: + CommandObjectThreadSiginfo(CommandInterpreter &interpreter) + : CommandObjectIterateOverThreads( + interpreter, "thread siginfo", + "Display the current siginfo object for a thread. Defaults to " + "the current thread.", + "thread siginfo", + eCommandRequiresProcess | eCommandTryTargetAPILock | + eCommandProcessMustBeLaunched | eCommandProcessMustBePaused) {} + + ~CommandObjectThreadSiginfo() override = default; + + void + HandleArgumentCompletion(CompletionRequest &request, + OptionElementVector &opt_element_vector) override { + CommandCompletions::InvokeCommonCompletionCallbacks( + GetCommandInterpreter(), CommandCompletions::eThreadIndexCompletion, + request, nullptr); + } + + bool HandleOneThread(lldb::tid_t tid, CommandReturnObject &result) override { + ThreadSP thread_sp = + m_exe_ctx.GetProcessPtr()->GetThreadList().FindThreadByID(tid); + if (!thread_sp) { + result.AppendErrorWithFormat("thread no longer exists: 0x%" PRIx64 "\n", + tid); + return false; + } + + Stream &strm = result.GetOutputStream(); + if (!thread_sp->GetDescription(strm, eDescriptionLevelFull, false, false)) { + result.AppendErrorWithFormat("error displaying info for thread: \"%d\"\n", + thread_sp->GetIndexID()); + return false; + } + ValueObjectSP exception_object_sp = thread_sp->GetSiginfoValue(); + if (exception_object_sp) + exception_object_sp->Dump(strm); + else + strm.Printf("(no siginfo)\n"); + strm.PutChar('\n'); + + return true; + } +}; + // CommandObjectThreadReturn #define LLDB_OPTIONS_thread_return #include "CommandOptions.inc" @@ -2293,6 +2340,8 @@ CommandObjectMultiwordThread::CommandObjectMultiwordThread( CommandObjectSP(new CommandObjectThreadInfo(interpreter))); LoadSubCommand("exception", CommandObjectSP(new CommandObjectThreadException( interpreter))); + LoadSubCommand("siginfo", + CommandObjectSP(new CommandObjectThreadSiginfo(interpreter))); LoadSubCommand("step-in", CommandObjectSP(new CommandObjectThreadStepWithTypeAndScope( interpreter, "thread step-in", diff --git a/lldb/test/Shell/Commands/Inputs/sigchld.c b/lldb/test/Shell/Commands/Inputs/sigchld.c new file mode 100644 index 0000000000000..ba8c5ef45365b --- /dev/null +++ b/lldb/test/Shell/Commands/Inputs/sigchld.c @@ -0,0 +1,31 @@ +#include +#include +#include +#include +#include + +void handler(int signo) { + printf("SIGCHLD\n"); +} + +int main() { + void *ret = signal(SIGINT, handler); + assert (ret != SIG_ERR); + + pid_t child_pid = fork(); + assert (child_pid != -1); + + if (child_pid == 0) { + sleep(1); + _exit(14); + } + + printf("signo = %d\n", SIGCHLD); + printf("code = %d\n", CLD_EXITED); + printf("child_pid = %d\n", child_pid); + printf("uid = %d\n", getuid()); + pid_t waited = wait(NULL); + assert(waited == child_pid); + + return 0; +} diff --git a/lldb/test/Shell/Commands/command-thread-siginfo.test b/lldb/test/Shell/Commands/command-thread-siginfo.test new file mode 100644 index 0000000000000..92829f3dcb0c4 --- /dev/null +++ b/lldb/test/Shell/Commands/command-thread-siginfo.test @@ -0,0 +1,19 @@ +# REQUIRES: system-linux +# RUN: %clang_host -g %S/Inputs/sigchld.c -o %t +# RUN: %lldb %t -b -s %s | FileCheck %s + +process launch -s +process handle SIGCHLD -s true +process continue +# CHECK: signo = [[SIGNO:[0-9]+]] +# CHECK: code = [[CODE:[0-9]+]] +# CHECK: child_pid = [[PID:[0-9]+]] +# CHECK: uid = [[UID:[0-9]+]] +# CHECK: stop reason = signal SIGCHLD +thread siginfo +# CHECK-DAG: si_signo = [[SIGNO]] +# CHECK-DAG: si_errno = 0 +# CHECK-DAG: si_code = [[CODE]] +# CHECK-DAG: si_pid = [[PID]] +# CHECK-DAG: si_uid = [[UID]] +# CHECK-DAG: si_status = 14 From 2eed91114f3276bacfe14f98ff49f4bb6494dd3b Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sat, 12 Feb 2022 19:04:12 +0100 Subject: [PATCH 113/316] Revert "[RISCV] Enable shrink wrap by default" This reverts commit 5ebdb07e7eb366c20fa2d914e07a4d380975f266. Enabling shrink wrap by default can cause assertions or crashes, and these should first be investigated and fixed. For now, reverting the change so it can be cherry-picked into 14.0.0 is the safest choice. (cherry picked from commit 7af3d4ab3d5da07256e1a7a0438e7308e14b9fd5) --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 8 - llvm/lib/Target/RISCV/RISCVFrameLowering.h | 2 - llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 55 ++--- llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 204 ++++++++++++------ .../RISCV/double-stack-spill-restore.ll | 8 +- llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 204 ++++++++++++------ llvm/test/CodeGen/RISCV/frame-info.ll | 46 ++-- llvm/test/CodeGen/RISCV/half-br-fcmp.ll | 204 ++++++++++++------ llvm/test/CodeGen/RISCV/rv32zbb.ll | 22 +- llvm/test/CodeGen/RISCV/rv64zbb.ll | 65 +++--- llvm/test/CodeGen/RISCV/shrinkwrap.ll | 41 ++-- 11 files changed, 538 insertions(+), 321 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index ad003404d793e..f3cc7d3fb46fa 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -1116,14 +1116,6 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( return true; } -bool RISCVFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { - // Keep the conventional code flow when not optimizing. - if (MF.getFunction().hasOptNone()) - return false; - - return true; -} - bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { MachineBasicBlock *TmpMBB = const_cast(&MBB); const MachineFunction *MF = MBB.getParent(); diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 1e94e34acf2f1..bc3ace786272d 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -65,8 +65,6 @@ class RISCVFrameLowering : public TargetFrameLowering { bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override; - bool enableShrinkWrapping(const MachineFunction &MF) const override; - bool isSupportedStackID(TargetStackID::Value ID) const override; TargetStackID::Value getStackIDForScalableVectors() const override; diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll index 89592c6ecbb29..d5de71d7e42db 100644 --- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll @@ -167,10 +167,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind { define i32 @test_cttz_i32(i32 %a) nounwind { ; RV32I-LABEL: test_cttz_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: beqz a0, .LBB2_2 -; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a0, .LBB2_2 +; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 @@ -194,20 +194,21 @@ define i32 @test_cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: srli a0, a0, 24 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB2_3 ; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: .LBB2_3: # %cond.end +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_cttz_i32: ; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: beqz a1, .LBB2_2 ; RV64I-NEXT: # %bb.1: # %cond.false -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: addiw a1, a0, -1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: and a0, a0, a1 @@ -231,11 +232,12 @@ define i32 @test_cttz_i32(i32 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB2_3 ; RV64I-NEXT: .LBB2_2: ; RV64I-NEXT: li a0, 32 +; RV64I-NEXT: .LBB2_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_cttz_i32: @@ -254,10 +256,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind { define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV32I-LABEL: test_ctlz_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: beqz a0, .LBB3_2 -; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a0, .LBB3_2 +; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 2 @@ -289,20 +291,21 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: srli a0, a0, 24 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: .LBB3_3: # %cond.end +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_ctlz_i32: ; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: beqz a1, .LBB3_2 ; RV64I-NEXT: # %bb.1: # %cond.false -; RV64I-NEXT: addi sp, sp, -16 -; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 @@ -334,11 +337,12 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB3_3 ; RV64I-NEXT: .LBB3_2: ; RV64I-NEXT: li a0, 32 +; RV64I-NEXT: .LBB3_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_ctlz_i32: @@ -429,10 +433,10 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; ; RV64I-LABEL: test_cttz_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB4_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB4_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: and a0, a0, a1 @@ -456,11 +460,12 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: ld a1, %lo(.LCPI4_3)(a1) ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srli a0, a0, 56 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB4_3 ; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: li a0, 64 +; RV64I-NEXT: .LBB4_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_cttz_i64: diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll index 2467280a95f24..6b535a2bdc439 100644 --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -10,24 +10,28 @@ declare void @exit(i32) define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: li a0, 1 ; RV32IFD-NEXT: bnez a0, .LBB0_2 ; RV32IFD-NEXT: # %bb.1: # %if.then +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB0_2: # %if.else -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: li a0, 1 ; RV64IFD-NEXT: bnez a0, .LBB0_2 ; RV64IFD-NEXT: # %bb.1: # %if.then +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB0_2: # %if.else -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp false double %a, %b br i1 %1, label %if.then, label %if.else @@ -41,24 +45,28 @@ if.else: define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_oeq: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: feq.d a0, fa0, fa1 ; RV32IFD-NEXT: bnez a0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB1_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_oeq: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: feq.d a0, fa0, fa1 ; RV64IFD-NEXT: bnez a0, .LBB1_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB1_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else @@ -75,24 +83,28 @@ if.then: define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_oeq_alt: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: feq.d a0, fa0, fa1 ; RV32IFD-NEXT: bnez a0, .LBB2_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB2_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_oeq_alt: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: feq.d a0, fa0, fa1 ; RV64IFD-NEXT: bnez a0, .LBB2_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB2_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else @@ -106,24 +118,28 @@ if.else: define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ogt: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa1, fa0 ; RV32IFD-NEXT: bnez a0, .LBB3_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB3_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ogt: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa1, fa0 ; RV64IFD-NEXT: bnez a0, .LBB3_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB3_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ogt double %a, %b br i1 %1, label %if.then, label %if.else @@ -137,24 +153,28 @@ if.then: define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_oge: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fle.d a0, fa1, fa0 ; RV32IFD-NEXT: bnez a0, .LBB4_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB4_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_oge: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fle.d a0, fa1, fa0 ; RV64IFD-NEXT: bnez a0, .LBB4_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB4_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp oge double %a, %b br i1 %1, label %if.then, label %if.else @@ -168,24 +188,28 @@ if.then: define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_olt: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa0, fa1 ; RV32IFD-NEXT: bnez a0, .LBB5_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB5_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_olt: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa0, fa1 ; RV64IFD-NEXT: bnez a0, .LBB5_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB5_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp olt double %a, %b br i1 %1, label %if.then, label %if.else @@ -199,24 +223,28 @@ if.then: define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ole: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fle.d a0, fa0, fa1 ; RV32IFD-NEXT: bnez a0, .LBB6_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB6_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ole: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fle.d a0, fa0, fa1 ; RV64IFD-NEXT: bnez a0, .LBB6_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB6_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ole double %a, %b br i1 %1, label %if.then, label %if.else @@ -230,28 +258,32 @@ if.then: define void @br_fcmp_one(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_one: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa0, fa1 ; RV32IFD-NEXT: flt.d a1, fa1, fa0 ; RV32IFD-NEXT: or a0, a1, a0 ; RV32IFD-NEXT: bnez a0, .LBB7_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB7_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_one: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa0, fa1 ; RV64IFD-NEXT: flt.d a1, fa1, fa0 ; RV64IFD-NEXT: or a0, a1, a0 ; RV64IFD-NEXT: bnez a0, .LBB7_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB7_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp one double %a, %b br i1 %1, label %if.then, label %if.else @@ -265,28 +297,32 @@ if.then: define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ord: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: feq.d a0, fa1, fa1 ; RV32IFD-NEXT: feq.d a1, fa0, fa0 ; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: bnez a0, .LBB8_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB8_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ord: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: feq.d a0, fa1, fa1 ; RV64IFD-NEXT: feq.d a1, fa0, fa0 ; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB8_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ord double %a, %b br i1 %1, label %if.then, label %if.else @@ -300,28 +336,32 @@ if.then: define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ueq: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa0, fa1 ; RV32IFD-NEXT: flt.d a1, fa1, fa0 ; RV32IFD-NEXT: or a0, a1, a0 ; RV32IFD-NEXT: beqz a0, .LBB9_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB9_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ueq: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa0, fa1 ; RV64IFD-NEXT: flt.d a1, fa1, fa0 ; RV64IFD-NEXT: or a0, a1, a0 ; RV64IFD-NEXT: beqz a0, .LBB9_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB9_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ueq double %a, %b br i1 %1, label %if.then, label %if.else @@ -335,24 +375,28 @@ if.then: define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ugt: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fle.d a0, fa0, fa1 ; RV32IFD-NEXT: beqz a0, .LBB10_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB10_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ugt: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fle.d a0, fa0, fa1 ; RV64IFD-NEXT: beqz a0, .LBB10_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB10_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ugt double %a, %b br i1 %1, label %if.then, label %if.else @@ -366,24 +410,28 @@ if.then: define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_uge: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa0, fa1 ; RV32IFD-NEXT: beqz a0, .LBB11_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB11_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_uge: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa0, fa1 ; RV64IFD-NEXT: beqz a0, .LBB11_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB11_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp uge double %a, %b br i1 %1, label %if.then, label %if.else @@ -397,24 +445,28 @@ if.then: define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ult: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: fle.d a0, fa1, fa0 ; RV32IFD-NEXT: beqz a0, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB12_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ult: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fle.d a0, fa1, fa0 ; RV64IFD-NEXT: beqz a0, .LBB12_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB12_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ult double %a, %b br i1 %1, label %if.then, label %if.else @@ -428,24 +480,28 @@ if.then: define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_ule: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: flt.d a0, fa1, fa0 ; RV32IFD-NEXT: beqz a0, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB13_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_ule: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: flt.d a0, fa1, fa0 ; RV64IFD-NEXT: beqz a0, .LBB13_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB13_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp ule double %a, %b br i1 %1, label %if.then, label %if.else @@ -459,24 +515,28 @@ if.then: define void @br_fcmp_une(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_une: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: feq.d a0, fa0, fa1 ; RV32IFD-NEXT: beqz a0, .LBB14_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB14_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_une: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: feq.d a0, fa0, fa1 ; RV64IFD-NEXT: beqz a0, .LBB14_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB14_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp une double %a, %b br i1 %1, label %if.then, label %if.else @@ -491,28 +551,32 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; TODO: sltiu+bne -> beq ; RV32IFD-LABEL: br_fcmp_uno: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: feq.d a0, fa1, fa1 ; RV32IFD-NEXT: feq.d a1, fa0, fa0 ; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: beqz a0, .LBB15_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB15_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_uno: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: feq.d a0, fa1, fa1 ; RV64IFD-NEXT: feq.d a1, fa0, fa0 ; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: beqz a0, .LBB15_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB15_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp uno double %a, %b br i1 %1, label %if.then, label %if.else @@ -526,24 +590,28 @@ if.then: define void @br_fcmp_true(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_true: ; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: li a0, 1 ; RV32IFD-NEXT: bnez a0, .LBB16_2 ; RV32IFD-NEXT: # %bb.1: # %if.else +; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB16_2: # %if.then -; RV32IFD-NEXT: addi sp, sp, -16 -; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort@plt ; ; RV64IFD-LABEL: br_fcmp_true: ; RV64IFD: # %bb.0: +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: li a0, 1 ; RV64IFD-NEXT: bnez a0, .LBB16_2 ; RV64IFD-NEXT: # %bb.1: # %if.else +; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret ; RV64IFD-NEXT: .LBB16_2: # %if.then -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort@plt %1 = fcmp true double %a, %b br i1 %1, label %if.then, label %if.else diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll index 6c5bd89b6b0eb..f612b533008ec 100644 --- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll +++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll @@ -35,12 +35,12 @@ define double @func(double %d, i32 %n) nounwind { ; ; RV64IFD-LABEL: func: ; RV64IFD: # %bb.0: # %entry +; RV64IFD-NEXT: addi sp, sp, -16 +; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sext.w a2, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: beqz a2, .LBB0_2 ; RV64IFD-NEXT: # %bb.1: # %if.else -; RV64IFD-NEXT: addi sp, sp, -16 -; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: addiw a1, a1, -1 ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill @@ -48,13 +48,11 @@ define double @func(double %d, i32 %n) nounwind { ; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 +; RV64IFD-NEXT: .LBB0_2: # %return ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: ret -; RV64IFD-NEXT: .LBB0_2: # %return -; RV64IFD-NEXT: fmv.x.d a0, ft0 -; RV64IFD-NEXT: ret entry: %cmp = icmp eq i32 %n, 0 br i1 %cmp, label %return, label %if.else diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll index cac2df760cfbe..05c9ce89c5a8f 100644 --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -11,24 +11,28 @@ declare float @dummy(float) define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_false: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: li a0, 1 ; RV32IF-NEXT: bnez a0, .LBB0_2 ; RV32IF-NEXT: # %bb.1: # %if.then +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB0_2: # %if.else -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_false: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: li a0, 1 ; RV64IF-NEXT: bnez a0, .LBB0_2 ; RV64IF-NEXT: # %bb.1: # %if.then +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB0_2: # %if.else -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp false float %a, %b br i1 %1, label %if.then, label %if.else @@ -42,24 +46,28 @@ if.else: define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_oeq: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: feq.s a0, fa0, fa1 ; RV32IF-NEXT: bnez a0, .LBB1_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB1_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_oeq: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: feq.s a0, fa0, fa1 ; RV64IF-NEXT: bnez a0, .LBB1_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB1_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else @@ -76,24 +84,28 @@ if.then: define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_oeq_alt: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: feq.s a0, fa0, fa1 ; RV32IF-NEXT: bnez a0, .LBB2_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB2_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_oeq_alt: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: feq.s a0, fa0, fa1 ; RV64IF-NEXT: bnez a0, .LBB2_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB2_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else @@ -107,24 +119,28 @@ if.else: define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ogt: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa1, fa0 ; RV32IF-NEXT: bnez a0, .LBB3_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB3_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ogt: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa1, fa0 ; RV64IF-NEXT: bnez a0, .LBB3_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB3_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ogt float %a, %b br i1 %1, label %if.then, label %if.else @@ -138,24 +154,28 @@ if.then: define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_oge: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fle.s a0, fa1, fa0 ; RV32IF-NEXT: bnez a0, .LBB4_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB4_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_oge: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: fle.s a0, fa1, fa0 ; RV64IF-NEXT: bnez a0, .LBB4_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB4_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp oge float %a, %b br i1 %1, label %if.then, label %if.else @@ -169,24 +189,28 @@ if.then: define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_olt: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa0, fa1 ; RV32IF-NEXT: bnez a0, .LBB5_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB5_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_olt: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa0, fa1 ; RV64IF-NEXT: bnez a0, .LBB5_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB5_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp olt float %a, %b br i1 %1, label %if.then, label %if.else @@ -200,24 +224,28 @@ if.then: define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ole: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fle.s a0, fa0, fa1 ; RV32IF-NEXT: bnez a0, .LBB6_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB6_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ole: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: fle.s a0, fa0, fa1 ; RV64IF-NEXT: bnez a0, .LBB6_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB6_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ole float %a, %b br i1 %1, label %if.then, label %if.else @@ -231,28 +259,32 @@ if.then: define void @br_fcmp_one(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_one: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa0, fa1 ; RV32IF-NEXT: flt.s a1, fa1, fa0 ; RV32IF-NEXT: or a0, a1, a0 ; RV32IF-NEXT: bnez a0, .LBB7_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB7_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_one: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa0, fa1 ; RV64IF-NEXT: flt.s a1, fa1, fa0 ; RV64IF-NEXT: or a0, a1, a0 ; RV64IF-NEXT: bnez a0, .LBB7_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB7_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp one float %a, %b br i1 %1, label %if.then, label %if.else @@ -266,28 +298,32 @@ if.then: define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ord: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: feq.s a0, fa1, fa1 ; RV32IF-NEXT: feq.s a1, fa0, fa0 ; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB8_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ord: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: feq.s a0, fa1, fa1 ; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB8_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ord float %a, %b br i1 %1, label %if.then, label %if.else @@ -301,28 +337,32 @@ if.then: define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ueq: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa0, fa1 ; RV32IF-NEXT: flt.s a1, fa1, fa0 ; RV32IF-NEXT: or a0, a1, a0 ; RV32IF-NEXT: beqz a0, .LBB9_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB9_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ueq: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa0, fa1 ; RV64IF-NEXT: flt.s a1, fa1, fa0 ; RV64IF-NEXT: or a0, a1, a0 ; RV64IF-NEXT: beqz a0, .LBB9_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB9_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ueq float %a, %b br i1 %1, label %if.then, label %if.else @@ -336,24 +376,28 @@ if.then: define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ugt: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fle.s a0, fa0, fa1 ; RV32IF-NEXT: beqz a0, .LBB10_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB10_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ugt: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: fle.s a0, fa0, fa1 ; RV64IF-NEXT: beqz a0, .LBB10_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB10_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ugt float %a, %b br i1 %1, label %if.then, label %if.else @@ -367,24 +411,28 @@ if.then: define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_uge: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa0, fa1 ; RV32IF-NEXT: beqz a0, .LBB11_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB11_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_uge: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa0, fa1 ; RV64IF-NEXT: beqz a0, .LBB11_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB11_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp uge float %a, %b br i1 %1, label %if.then, label %if.else @@ -398,24 +446,28 @@ if.then: define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ult: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fle.s a0, fa1, fa0 ; RV32IF-NEXT: beqz a0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB12_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ult: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: fle.s a0, fa1, fa0 ; RV64IF-NEXT: beqz a0, .LBB12_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB12_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ult float %a, %b br i1 %1, label %if.then, label %if.else @@ -429,24 +481,28 @@ if.then: define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_ule: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: flt.s a0, fa1, fa0 ; RV32IF-NEXT: beqz a0, .LBB13_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB13_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_ule: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: flt.s a0, fa1, fa0 ; RV64IF-NEXT: beqz a0, .LBB13_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB13_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp ule float %a, %b br i1 %1, label %if.then, label %if.else @@ -460,24 +516,28 @@ if.then: define void @br_fcmp_une(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_une: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: feq.s a0, fa0, fa1 ; RV32IF-NEXT: beqz a0, .LBB14_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB14_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_une: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: feq.s a0, fa0, fa1 ; RV64IF-NEXT: beqz a0, .LBB14_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB14_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp une float %a, %b br i1 %1, label %if.then, label %if.else @@ -492,28 +552,32 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; TODO: sltiu+bne -> beq ; RV32IF-LABEL: br_fcmp_uno: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: feq.s a0, fa1, fa1 ; RV32IF-NEXT: feq.s a1, fa0, fa0 ; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: beqz a0, .LBB15_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB15_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_uno: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: feq.s a0, fa1, fa1 ; RV64IF-NEXT: feq.s a1, fa0, fa0 ; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: beqz a0, .LBB15_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB15_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp uno float %a, %b br i1 %1, label %if.then, label %if.else @@ -527,24 +591,28 @@ if.then: define void @br_fcmp_true(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_true: ; RV32IF: # %bb.0: +; RV32IF-NEXT: addi sp, sp, -16 +; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: li a0, 1 ; RV32IF-NEXT: bnez a0, .LBB16_2 ; RV32IF-NEXT: # %bb.1: # %if.else +; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB16_2: # %if.then -; RV32IF-NEXT: addi sp, sp, -16 -; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort@plt ; ; RV64IF-LABEL: br_fcmp_true: ; RV64IF: # %bb.0: +; RV64IF-NEXT: addi sp, sp, -16 +; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: li a0, 1 ; RV64IF-NEXT: bnez a0, .LBB16_2 ; RV64IF-NEXT: # %bb.1: # %if.else +; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; RV64IF-NEXT: .LBB16_2: # %if.then -; RV64IF-NEXT: addi sp, sp, -16 -; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort@plt %1 = fcmp true float %a, %b br i1 %1, label %if.then, label %if.else diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll index 0a28df1cf5fb2..c872fb3774b5e 100644 --- a/llvm/test/CodeGen/RISCV/frame-info.ll +++ b/llvm/test/CodeGen/RISCV/frame-info.ll @@ -146,15 +146,17 @@ entry: define void @branch_and_tail_call(i1 %a) { ; RV32-LABEL: branch_and_tail_call: ; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: andi a0, a0, 1 ; RV32-NEXT: beqz a0, .LBB2_2 ; RV32-NEXT: # %bb.1: # %blue_pill +; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: tail callee1@plt ; RV32-NEXT: .LBB2_2: # %red_pill -; RV32-NEXT: addi sp, sp, -16 -; RV32-NEXT: .cfi_def_cfa_offset 16 -; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: call callee2@plt ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: addi sp, sp, 16 @@ -162,15 +164,17 @@ define void @branch_and_tail_call(i1 %a) { ; ; RV64-LABEL: branch_and_tail_call: ; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -16 +; RV64-NEXT: .cfi_def_cfa_offset 16 +; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: andi a0, a0, 1 ; RV64-NEXT: beqz a0, .LBB2_2 ; RV64-NEXT: # %bb.1: # %blue_pill +; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: tail callee1@plt ; RV64-NEXT: .LBB2_2: # %red_pill -; RV64-NEXT: addi sp, sp, -16 -; RV64-NEXT: .cfi_def_cfa_offset 16 -; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: call callee2@plt ; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 @@ -178,11 +182,6 @@ define void @branch_and_tail_call(i1 %a) { ; ; RV32-WITHFP-LABEL: branch_and_tail_call: ; RV32-WITHFP: # %bb.0: -; RV32-WITHFP-NEXT: andi a0, a0, 1 -; RV32-WITHFP-NEXT: beqz a0, .LBB2_2 -; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV32-WITHFP-NEXT: tail callee1@plt -; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill @@ -191,6 +190,14 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-NEXT: .cfi_offset s0, -8 ; RV32-WITHFP-NEXT: addi s0, sp, 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0 +; RV32-WITHFP-NEXT: andi a0, a0, 1 +; RV32-WITHFP-NEXT: beqz a0, .LBB2_2 +; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill +; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32-WITHFP-NEXT: addi sp, sp, 16 +; RV32-WITHFP-NEXT: tail callee1@plt +; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV32-WITHFP-NEXT: call callee2@plt ; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -199,11 +206,6 @@ define void @branch_and_tail_call(i1 %a) { ; ; RV64-WITHFP-LABEL: branch_and_tail_call: ; RV64-WITHFP: # %bb.0: -; RV64-WITHFP-NEXT: andi a0, a0, 1 -; RV64-WITHFP-NEXT: beqz a0, .LBB2_2 -; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV64-WITHFP-NEXT: tail callee1@plt -; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill @@ -212,6 +214,14 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-NEXT: .cfi_offset s0, -16 ; RV64-WITHFP-NEXT: addi s0, sp, 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0 +; RV64-WITHFP-NEXT: andi a0, a0, 1 +; RV64-WITHFP-NEXT: beqz a0, .LBB2_2 +; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill +; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-WITHFP-NEXT: addi sp, sp, 16 +; RV64-WITHFP-NEXT: tail callee1@plt +; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill ; RV64-WITHFP-NEXT: call callee2@plt ; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll index ccff49cd98cf6..5f9108f46d309 100644 --- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -11,24 +11,28 @@ declare half @dummy(half) define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_false: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: li a0, 1 ; RV32IZFH-NEXT: bnez a0, .LBB0_2 ; RV32IZFH-NEXT: # %bb.1: # %if.then +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB0_2: # %if.else -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: li a0, 1 ; RV64IZFH-NEXT: bnez a0, .LBB0_2 ; RV64IZFH-NEXT: # %bb.1: # %if.then +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB0_2: # %if.else -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp false half %a, %b br i1 %1, label %if.then, label %if.else @@ -42,24 +46,28 @@ if.else: define void @br_fcmp_oeq(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_oeq: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: bnez a0, .LBB1_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB1_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_oeq: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: bnez a0, .LBB1_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB1_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp oeq half %a, %b br i1 %1, label %if.then, label %if.else @@ -76,24 +84,28 @@ if.then: define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_oeq_alt: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: bnez a0, .LBB2_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB2_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_oeq_alt: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: bnez a0, .LBB2_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB2_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp oeq half %a, %b br i1 %1, label %if.then, label %if.else @@ -107,24 +119,28 @@ if.else: define void @br_fcmp_ogt(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ogt: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: bnez a0, .LBB3_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB3_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ogt: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: bnez a0, .LBB3_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB3_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ogt half %a, %b br i1 %1, label %if.then, label %if.else @@ -138,24 +154,28 @@ if.then: define void @br_fcmp_oge(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_oge: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: bnez a0, .LBB4_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB4_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_oge: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: bnez a0, .LBB4_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB4_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp oge half %a, %b br i1 %1, label %if.then, label %if.else @@ -169,24 +189,28 @@ if.then: define void @br_fcmp_olt(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_olt: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: bnez a0, .LBB5_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB5_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_olt: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: bnez a0, .LBB5_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB5_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp olt half %a, %b br i1 %1, label %if.then, label %if.else @@ -200,24 +224,28 @@ if.then: define void @br_fcmp_ole(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ole: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: bnez a0, .LBB6_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB6_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ole: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: bnez a0, .LBB6_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB6_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ole half %a, %b br i1 %1, label %if.then, label %if.else @@ -231,28 +259,32 @@ if.then: define void @br_fcmp_one(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_one: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0 ; RV32IZFH-NEXT: or a0, a1, a0 ; RV32IZFH-NEXT: bnez a0, .LBB7_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB7_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_one: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0 ; RV64IZFH-NEXT: or a0, a1, a0 ; RV64IZFH-NEXT: bnez a0, .LBB7_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB7_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp one half %a, %b br i1 %1, label %if.then, label %if.else @@ -266,28 +298,32 @@ if.then: define void @br_fcmp_ord(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ord: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: bnez a0, .LBB8_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB8_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ord: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: bnez a0, .LBB8_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB8_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ord half %a, %b br i1 %1, label %if.then, label %if.else @@ -301,28 +337,32 @@ if.then: define void @br_fcmp_ueq(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ueq: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0 ; RV32IZFH-NEXT: or a0, a1, a0 ; RV32IZFH-NEXT: beqz a0, .LBB9_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB9_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ueq: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0 ; RV64IZFH-NEXT: or a0, a1, a0 ; RV64IZFH-NEXT: beqz a0, .LBB9_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB9_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ueq half %a, %b br i1 %1, label %if.then, label %if.else @@ -336,24 +376,28 @@ if.then: define void @br_fcmp_ugt(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ugt: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: beqz a0, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB10_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ugt: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: beqz a0, .LBB10_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB10_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ugt half %a, %b br i1 %1, label %if.then, label %if.else @@ -367,24 +411,28 @@ if.then: define void @br_fcmp_uge(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_uge: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: beqz a0, .LBB11_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB11_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_uge: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: beqz a0, .LBB11_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB11_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp uge half %a, %b br i1 %1, label %if.then, label %if.else @@ -398,24 +446,28 @@ if.then: define void @br_fcmp_ult(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ult: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: beqz a0, .LBB12_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB12_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ult: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: beqz a0, .LBB12_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB12_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ult half %a, %b br i1 %1, label %if.then, label %if.else @@ -429,24 +481,28 @@ if.then: define void @br_fcmp_ule(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_ule: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: beqz a0, .LBB13_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB13_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_ule: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: beqz a0, .LBB13_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB13_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp ule half %a, %b br i1 %1, label %if.then, label %if.else @@ -460,24 +516,28 @@ if.then: define void @br_fcmp_une(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_une: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: beqz a0, .LBB14_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB14_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_une: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: beqz a0, .LBB14_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB14_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp une half %a, %b br i1 %1, label %if.then, label %if.else @@ -492,28 +552,32 @@ define void @br_fcmp_uno(half %a, half %b) nounwind { ; TODO: sltiu+bne -> beq ; RV32IZFH-LABEL: br_fcmp_uno: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: beqz a0, .LBB15_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB15_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_uno: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: beqz a0, .LBB15_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB15_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp uno half %a, %b br i1 %1, label %if.then, label %if.else @@ -527,24 +591,28 @@ if.then: define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_true: ; RV32IZFH: # %bb.0: +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: li a0, 1 ; RV32IZFH-NEXT: bnez a0, .LBB16_2 ; RV32IZFH-NEXT: # %bb.1: # %if.else +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: .LBB16_2: # %if.then -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort@plt ; ; RV64IZFH-LABEL: br_fcmp_true: ; RV64IZFH: # %bb.0: +; RV64IZFH-NEXT: addi sp, sp, -16 +; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: li a0, 1 ; RV64IZFH-NEXT: bnez a0, .LBB16_2 ; RV64IZFH-NEXT: # %bb.1: # %if.else +; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: .LBB16_2: # %if.then -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort@plt %1 = fcmp true half %a, %b br i1 %1, label %if.then, label %if.else diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll index d5d6b3ab0b893..64c9e35146f63 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -9,10 +9,10 @@ declare i32 @llvm.ctlz.i32(i32, i1) define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I-LABEL: ctlz_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: beqz a0, .LBB0_2 -; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a0, .LBB0_2 +; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 2 @@ -44,11 +44,12 @@ define i32 @ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: srli a0, a0, 24 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB0_3 ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: .LBB0_3: # %cond.end +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: ctlz_i32: @@ -171,10 +172,10 @@ declare i32 @llvm.cttz.i32(i32, i1) define i32 @cttz_i32(i32 %a) nounwind { ; RV32I-LABEL: cttz_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: beqz a0, .LBB2_2 -; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: beqz a0, .LBB2_2 +; RV32I-NEXT: # %bb.1: # %cond.false ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 @@ -198,11 +199,12 @@ define i32 @cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a1, a1, 257 ; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: srli a0, a0, 24 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret +; RV32I-NEXT: j .LBB2_3 ; RV32I-NEXT: .LBB2_2: ; RV32I-NEXT: li a0, 32 +; RV32I-NEXT: .LBB2_3: # %cond.end +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: cttz_i32: diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll index db249e9f22c04..e1e1cbac591ac 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -9,10 +9,10 @@ declare i32 @llvm.ctlz.i32(i32, i1) define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-LABEL: ctlz_i32: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB0_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB0_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 @@ -44,11 +44,12 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB0_3 ; RV64I-NEXT: .LBB0_2: ; RV64I-NEXT: li a0, 32 +; RV64I-NEXT: .LBB0_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: ctlz_i32: @@ -62,10 +63,10 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-LABEL: log2_i32: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB1_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB1_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 @@ -97,14 +98,14 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: j .LBB1_3 ; RV64I-NEXT: .LBB1_2: ; RV64I-NEXT: li a0, 32 ; RV64I-NEXT: .LBB1_3: # %cond.end ; RV64I-NEXT: li a1, 31 ; RV64I-NEXT: sub a0, a1, a0 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: log2_i32: @@ -249,13 +250,13 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-LABEL: ctlz_lshr_i32: ; RV64I: # %bb.0: -; RV64I-NEXT: srliw a0, a0, 1 -; RV64I-NEXT: beqz a0, .LBB4_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: .cfi_def_cfa_offset 16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: srliw a0, a0, 1 +; RV64I-NEXT: beqz a0, .LBB4_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 2 @@ -288,11 +289,12 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB4_3 ; RV64I-NEXT: .LBB4_2: ; RV64I-NEXT: li a0, 32 +; RV64I-NEXT: .LBB4_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: ctlz_lshr_i32: @@ -310,10 +312,10 @@ declare i64 @llvm.ctlz.i64(i64, i1) define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-LABEL: ctlz_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB5_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB5_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 2 @@ -347,11 +349,12 @@ define i64 @ctlz_i64(i64 %a) nounwind { ; RV64I-NEXT: ld a1, %lo(.LCPI5_3)(a1) ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srli a0, a0, 56 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB5_3 ; RV64I-NEXT: .LBB5_2: ; RV64I-NEXT: li a0, 64 +; RV64I-NEXT: .LBB5_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: ctlz_i64: @@ -367,10 +370,10 @@ declare i32 @llvm.cttz.i32(i32, i1) define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-LABEL: cttz_i32: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB6_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB6_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addiw a1, a0, -1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: and a0, a0, a1 @@ -394,11 +397,12 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB6_3 ; RV64I-NEXT: .LBB6_2: ; RV64I-NEXT: li a0, 32 +; RV64I-NEXT: .LBB6_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: cttz_i32: @@ -567,10 +571,10 @@ declare i64 @llvm.cttz.i64(i64, i1) define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-LABEL: cttz_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: beqz a0, .LBB10_2 -; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: beqz a0, .LBB10_2 +; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi a1, a0, -1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: and a0, a0, a1 @@ -594,11 +598,12 @@ define i64 @cttz_i64(i64 %a) nounwind { ; RV64I-NEXT: ld a1, %lo(.LCPI10_3)(a1) ; RV64I-NEXT: call __muldi3@plt ; RV64I-NEXT: srli a0, a0, 56 -; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: addi sp, sp, 16 -; RV64I-NEXT: ret +; RV64I-NEXT: j .LBB10_3 ; RV64I-NEXT: .LBB10_2: ; RV64I-NEXT: li a0, 64 +; RV64I-NEXT: .LBB10_3: # %cond.end +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: cttz_i64: diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll index e64cc5273e56f..d41269c841e84 100644 --- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll +++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll @@ -26,35 +26,39 @@ define void @eliminate_restore(i32 %n) nounwind { ; ; RV32I-SW-LABEL: eliminate_restore: ; RV32I-SW: # %bb.0: +; RV32I-SW-NEXT: addi sp, sp, -16 +; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: li a1, 32 ; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-NEXT: # %bb.1: # %if.end +; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-SW-NEXT: addi sp, sp, 16 ; RV32I-SW-NEXT: ret ; RV32I-SW-NEXT: .LBB0_2: # %if.then -; RV32I-SW-NEXT: addi sp, sp, -16 -; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: call abort@plt ; ; RV32I-SW-SR-LABEL: eliminate_restore: ; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 ; RV32I-SW-SR-NEXT: li a1, 32 ; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 ; RV32I-SW-SR-NEXT: # %bb.1: # %if.end -; RV32I-SW-SR-NEXT: ret +; RV32I-SW-SR-NEXT: tail __riscv_restore_0 ; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then -; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 ; RV32I-SW-SR-NEXT: call abort@plt ; ; RV64I-SW-LABEL: eliminate_restore: ; RV64I-SW: # %bb.0: +; RV64I-SW-NEXT: addi sp, sp, -16 +; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: sext.w a0, a0 ; RV64I-SW-NEXT: li a1, 32 ; RV64I-SW-NEXT: bgeu a1, a0, .LBB0_2 ; RV64I-SW-NEXT: # %bb.1: # %if.end +; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-SW-NEXT: addi sp, sp, 16 ; RV64I-SW-NEXT: ret ; RV64I-SW-NEXT: .LBB0_2: # %if.then -; RV64I-SW-NEXT: addi sp, sp, -16 -; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: call abort@plt %cmp = icmp ule i32 %n, 32 br i1 %cmp, label %if.then, label %if.end @@ -93,52 +97,51 @@ define void @conditional_alloca(i32 %n) nounwind { ; ; RV32I-SW-LABEL: conditional_alloca: ; RV32I-SW: # %bb.0: -; RV32I-SW-NEXT: li a1, 32 -; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 -; RV32I-SW-NEXT: # %bb.1: # %if.then ; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-SW-NEXT: addi s0, sp, 16 +; RV32I-SW-NEXT: li a1, 32 +; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-NEXT: # %bb.1: # %if.then ; RV32I-SW-NEXT: addi a0, a0, 15 ; RV32I-SW-NEXT: andi a0, a0, -16 ; RV32I-SW-NEXT: sub a0, sp, a0 ; RV32I-SW-NEXT: mv sp, a0 ; RV32I-SW-NEXT: call notdead@plt +; RV32I-SW-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NEXT: addi sp, s0, -16 ; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-SW-NEXT: addi sp, sp, 16 -; RV32I-SW-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NEXT: ret ; ; RV32I-SW-SR-LABEL: conditional_alloca: ; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 +; RV32I-SW-SR-NEXT: addi s0, sp, 16 ; RV32I-SW-SR-NEXT: li a1, 32 ; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 ; RV32I-SW-SR-NEXT: # %bb.1: # %if.then -; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 -; RV32I-SW-SR-NEXT: addi s0, sp, 16 ; RV32I-SW-SR-NEXT: addi a0, a0, 15 ; RV32I-SW-SR-NEXT: andi a0, a0, -16 ; RV32I-SW-SR-NEXT: sub a0, sp, a0 ; RV32I-SW-SR-NEXT: mv sp, a0 ; RV32I-SW-SR-NEXT: call notdead@plt +; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end ; RV32I-SW-SR-NEXT: addi sp, s0, -16 ; RV32I-SW-SR-NEXT: tail __riscv_restore_1 -; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end -; RV32I-SW-SR-NEXT: ret ; ; RV64I-SW-LABEL: conditional_alloca: ; RV64I-SW: # %bb.0: -; RV64I-SW-NEXT: sext.w a1, a0 -; RV64I-SW-NEXT: li a2, 32 -; RV64I-SW-NEXT: bltu a2, a1, .LBB1_2 -; RV64I-SW-NEXT: # %bb.1: # %if.then ; RV64I-SW-NEXT: addi sp, sp, -16 ; RV64I-SW-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-SW-NEXT: addi s0, sp, 16 +; RV64I-SW-NEXT: sext.w a1, a0 +; RV64I-SW-NEXT: li a2, 32 +; RV64I-SW-NEXT: bltu a2, a1, .LBB1_2 +; RV64I-SW-NEXT: # %bb.1: # %if.then ; RV64I-SW-NEXT: slli a0, a0, 32 ; RV64I-SW-NEXT: srli a0, a0, 32 ; RV64I-SW-NEXT: addi a0, a0, 15 @@ -146,11 +149,11 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV64I-SW-NEXT: sub a0, sp, a0 ; RV64I-SW-NEXT: mv sp, a0 ; RV64I-SW-NEXT: call notdead@plt +; RV64I-SW-NEXT: .LBB1_2: # %if.end ; RV64I-SW-NEXT: addi sp, s0, -16 ; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-SW-NEXT: addi sp, sp, 16 -; RV64I-SW-NEXT: .LBB1_2: # %if.end ; RV64I-SW-NEXT: ret %cmp = icmp ule i32 %n, 32 br i1 %cmp, label %if.then, label %if.end From 6277e34840ebd7cab1e856ec56b90b995655c493 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 15 Feb 2022 11:50:21 -0500 Subject: [PATCH 114/316] [libc++] Disable back-deployment CI on the release branch As explained in the comment, we don't have macOS 10.15 builders anymore in the fleet. Enabling those tests on the release branch would require cherry-picking too many changes from `main`. --- libcxx/utils/ci/buildkite-pipeline.yml | 59 ++++++++++++++------------ 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/libcxx/utils/ci/buildkite-pipeline.yml b/libcxx/utils/ci/buildkite-pipeline.yml index c5c56bb997dfd..6b5137bf30e70 100644 --- a/libcxx/utils/ci/buildkite-pipeline.yml +++ b/libcxx/utils/ci/buildkite-pipeline.yml @@ -598,34 +598,37 @@ steps: limit: 2 timeout_in_minutes: 120 - # Test back-deployment to older Apple platforms - - label: "Apple back-deployment macosx10.9" - command: "libcxx/utils/ci/run-buildbot apple-system-backdeployment-10.9" - artifact_paths: - - "**/test-results.xml" - agents: - queue: "libcxx-builders" - os: "macos10.15" # TODO: For now, we're running the back-deployment tests for 10.9 on 10.15, because we don't have proper 10.9 machines - arch: "x86_64" - retry: - automatic: - - exit_status: -1 # Agent was lost - limit: 2 - timeout_in_minutes: 120 - - - label: "Apple back-deployment macosx10.15" - command: "libcxx/utils/ci/run-buildbot apple-system-backdeployment-10.15" - artifact_paths: - - "**/test-results.xml" - agents: - queue: "libcxx-builders" - os: "macos10.15" - arch: "x86_64" - retry: - automatic: - - exit_status: -1 # Agent was lost - limit: 2 - timeout_in_minutes: 120 + # Those are disabled on the release/14.x branch because we don't have macOS 10.15 builders anymore + # in the fleet. Enabling those tests on the release branch would require cherry-picking too many + # changes from `main`. + # # Test back-deployment to older Apple platforms + # - label: "Apple back-deployment macosx10.9" + # command: "libcxx/utils/ci/run-buildbot apple-system-backdeployment-10.9" + # artifact_paths: + # - "**/test-results.xml" + # agents: + # queue: "libcxx-builders" + # os: "macos10.15" # TODO: For now, we're running the back-deployment tests for 10.9 on 10.15, because we don't have proper 10.9 machines + # arch: "x86_64" + # retry: + # automatic: + # - exit_status: -1 # Agent was lost + # limit: 2 + # timeout_in_minutes: 120 + + # - label: "Apple back-deployment macosx10.15" + # command: "libcxx/utils/ci/run-buildbot apple-system-backdeployment-10.15" + # artifact_paths: + # - "**/test-results.xml" + # agents: + # queue: "libcxx-builders" + # os: "macos10.15" + # arch: "x86_64" + # retry: + # automatic: + # - exit_status: -1 # Agent was lost + # limit: 2 + # timeout_in_minutes: 120 - label: "AArch64" command: "libcxx/utils/ci/run-buildbot aarch64" From b2ca48a8412270e323ac8441772d0d69190a8417 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 14 Feb 2022 11:41:41 -0800 Subject: [PATCH 115/316] ReleaseNotes: add notes for binary utilities For the release/14.x branch. Reviewed By: alexander-shaposhnikov, jhenderson Differential Revision: https://reviews.llvm.org/D119611 --- llvm/docs/ReleaseNotes.rst | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 32536eae9e548..e67eb4b39ddfd 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -191,7 +191,39 @@ Changes to the LLVM tools `-name-whitelist` is marked as deprecated and to be removed in future releases. +* llvm-ar now supports ``--thin`` for creating a thin archive. The modifier + ``T`` has a different meaning in some ar implementations. + (`D116979 `_) +* llvm-ar now supports reading big archives for XCOFF. + (`D111889 `_) +* llvm-nm now demangles Rust symbols. + (`D111937 `_) +* llvm-objcopy's ELF port now avoids reordering section headers to preserve ``st_shndx`` fields of dynamic symbols. + (`D107653 `_) +* llvm-objcopy now supports ``--update-section`` for ELF and Mach-O. + (`D112116 `_) + (`D117281 `_) +* llvm-objcopy now supports ``--subsystem`` for PE/COFF. + (`D116556 `_) +* llvm-objcopy now supports mips64le relocations for ELF. + (`D115635 `_) +* llvm-objcopy ``--rename-section`` now renames relocation sections together with their targets. + (`D110352 `_) +* llvm-objdump ``--symbolize-operands`` now supports PowerPC. + (`D114492 `_) +* llvm-objdump ``-p`` now dumps PE header. + (`D113356 `_) +* llvm-objdump ``-R`` now supports ELF position-dependent executables. + (`D110595 `_) +* llvm-objdump ``-T`` now prints symbol versions. + (`D108097 `_) * llvm-readobj: Improved printing of symbols in Windows unwind data. +* llvm-readobj now supports ``--elf-output-style=JSON`` for JSON output and + ``--pretty-print`` for pretty printing of this output. + (`D114225 `_) +* llvm-readobj now supports several dump styles (``--needed-libs, --relocs, --syms``) for XCOFF. +* llvm-symbolizer now supports `--debuginfod `. + (`D113717 `_) Changes to LLDB --------------------------------- From 062111fe8073de55c0f00fe04847e986781d1cad Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 8 Feb 2022 19:22:00 -0500 Subject: [PATCH 116/316] InferAddressSpaces: Fix assert on inferred source for inttoptr/ptrtoint If we had some source value we could infer an address space from that went through a ptrtoint/inttoptr pair, this would fail since bitcast can't change the address space. Fixes issue 53665. (cherry picked from commit 52fbb786a638ecc7349641b45b62a5abafffdf75) --- .../Transforms/Scalar/InferAddressSpaces.cpp | 11 ++-- .../InferAddressSpaces/AMDGPU/issue53665.ll | 54 +++++++++++++++++++ 2 files changed, 61 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp index 8f5933b7bd71a..ddc747a2ca297 100644 --- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp +++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp @@ -655,10 +655,13 @@ Value *InferAddressSpacesImpl::cloneInstructionWithNewAddressSpace( case Instruction::IntToPtr: { assert(isNoopPtrIntCastPair(cast(I), *DL, TTI)); Value *Src = cast(I->getOperand(0))->getOperand(0); - assert(Src->getType()->getPointerAddressSpace() == NewAddrSpace); - if (Src->getType() != NewPtrType) - return new BitCastInst(Src, NewPtrType); - return Src; + if (Src->getType() == NewPtrType) + return Src; + + // If we had a no-op inttoptr/ptrtoint pair, we may still have inferred a + // source address space from a generic pointer source need to insert a cast + // back. + return CastInst::CreatePointerBitCastOrAddrSpaceCast(Src, NewPtrType); } default: llvm_unreachable("Unexpected opcode"); diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll new file mode 100644 index 0000000000000..fcc1f56affbb6 --- /dev/null +++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/issue53665.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces -o - %s | FileCheck %s +; https://github.com/llvm/llvm-project/issues/53665 + +define i32 @addrspacecast_ptrtoint_inttoptr(i8 addrspace(1)* %arg) { +; CHECK-LABEL: @addrspacecast_ptrtoint_inttoptr( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(1)* [[ARG:%.*]] to i32 addrspace(1)* +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32 addrspace(1)* [[TMP0]], align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; +bb: + %asc = addrspacecast i8 addrspace(1)* %arg to i8* + %p2i = ptrtoint i8* %asc to i64 + %i2p = inttoptr i64 %p2i to i32* + %load = load i32, i32* %i2p + ret i32 %load +} + +define i32 @assumed_ptrtoint_inttoptr(i8* %arg) { +bb: + %is.priv = call i1 @llvm.amdgcn.is.private(i8* %arg) + %not.is.priv = xor i1 %is.priv, -1 + %is.shared = call i1 @llvm.amdgcn.is.shared(i8* %arg) + %not.is.shared = xor i1 %is.shared, -1 + %and = and i1 %not.is.priv, %not.is.shared + tail call void @llvm.assume(i1 %and) + %p2i = ptrtoint i8* %arg to i64 + %i2p = inttoptr i64 %p2i to i32* + %load = load i32, i32* %i2p + ret i32 %load +} + +define i32 @addrspacecast_ptrtoint_inttptr_nontrivial(i8 addrspace(3)* %arg) { +; CHECK-LABEL: @addrspacecast_ptrtoint_inttptr_nontrivial( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8 addrspace(3)* [[ARG:%.*]] to i32 addrspace(3)* +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32 addrspace(3)* [[TMP0]], align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; +bb: + %asc = addrspacecast i8 addrspace(3)* %arg to i8* + %p2i = ptrtoint i8* %asc to i64 + %i2p = inttoptr i64 %p2i to i32* + %load = load i32, i32* %i2p + ret i32 %load +} + +declare void @llvm.assume(i1 noundef) #0 +declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #1 +declare i1 @llvm.amdgcn.is.private(i8* nocapture) #1 + +attributes #0 = { inaccessiblememonly nofree nosync nounwind willreturn } +attributes #1 = { nounwind readnone speculatable willreturn } From ea97fc6b564ec6a843337a550a2209b653cffceb Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 11 Feb 2022 12:22:51 -0600 Subject: [PATCH 117/316] [OpenMP][FIX] The `llvm.amdgcn.s.barrier` is actually not aligned If we assume `llvm.amdgcn.s.barrier` is aligned we may remove it and cause OpenMP GPU applications on the AMD GPU to be stuck or wrongly synchronized. Reported by Carlo Bertolli. (cherry picked from commit ede248e614bb2c232b7b1815829eb3d5c1aab1e4) --- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 1 - llvm/test/Transforms/OpenMP/barrier_removal.ll | 10 ++++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index 2d765fb6ce6d0..520b6ebf9e74f 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -1458,7 +1458,6 @@ struct OpenMPOpt { case Intrinsic::nvvm_barrier0_and: case Intrinsic::nvvm_barrier0_or: case Intrinsic::nvvm_barrier0_popc: - case Intrinsic::amdgcn_s_barrier: return true; default: break; diff --git a/llvm/test/Transforms/OpenMP/barrier_removal.ll b/llvm/test/Transforms/OpenMP/barrier_removal.ll index 8c7cca8053e93..7de421f728f10 100644 --- a/llvm/test/Transforms/OpenMP/barrier_removal.ll +++ b/llvm/test/Transforms/OpenMP/barrier_removal.ll @@ -66,8 +66,9 @@ define void @pos_empty_6() { call i32 @llvm.nvvm.barrier0.popc(i32 0) ret void } -define void @pos_empty_7() { -; CHECK-LABEL: define {{[^@]+}}@pos_empty_7() { +define void @neg_empty_7() { +; CHECK-LABEL: define {{[^@]+}}@neg_empty_7() { +; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() ; CHECK-NEXT: ret void ; call void @llvm.amdgcn.s.barrier() @@ -211,6 +212,7 @@ define void @neg_mem() { define void @pos_multiple() { ; CHECK-LABEL: define {{[^@]+}}@pos_multiple() { +; CHECK-NEXT: call void @llvm.amdgcn.s.barrier() ; CHECK-NEXT: ret void ; call void @llvm.nvvm.barrier0() @@ -233,7 +235,7 @@ define void @pos_multiple() { !3 = !{void ()* @pos_empty_4, !"kernel", i32 1} !4 = !{void ()* @pos_empty_5, !"kernel", i32 1} !5 = !{void ()* @pos_empty_6, !"kernel", i32 1} -!6 = !{void ()* @pos_empty_7, !"kernel", i32 1} +!6 = !{void ()* @neg_empty_7, !"kernel", i32 1} !7 = !{void ()* @pos_constant_loads, !"kernel", i32 1} !8 = !{void ()* @neg_loads, !"kernel", i32 1} !9 = !{void ()* @pos_priv_mem, !"kernel", i32 1} @@ -254,7 +256,7 @@ define void @pos_multiple() { ; CHECK: [[META5:![0-9]+]] = !{void ()* @pos_empty_4, !"kernel", i32 1} ; CHECK: [[META6:![0-9]+]] = !{void ()* @pos_empty_5, !"kernel", i32 1} ; CHECK: [[META7:![0-9]+]] = !{void ()* @pos_empty_6, !"kernel", i32 1} -; CHECK: [[META8:![0-9]+]] = !{void ()* @pos_empty_7, !"kernel", i32 1} +; CHECK: [[META8:![0-9]+]] = !{void ()* @neg_empty_7, !"kernel", i32 1} ; CHECK: [[META9:![0-9]+]] = !{void ()* @pos_constant_loads, !"kernel", i32 1} ; CHECK: [[META10:![0-9]+]] = !{void ()* @neg_loads, !"kernel", i32 1} ; CHECK: [[META11:![0-9]+]] = !{void ()* @pos_priv_mem, !"kernel", i32 1} From e493f08f8222b3a36186331a0d5486b4407ed830 Mon Sep 17 00:00:00 2001 From: Jez Ng Date: Tue, 15 Feb 2022 02:33:01 -0500 Subject: [PATCH 118/316] [lld-macho] Fill out release notes for 14.x Differential Revision: https://reviews.llvm.org/D119811 --- lld/docs/ReleaseNotes.rst | 83 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 4 deletions(-) diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index ed4a374d579a3..3601a968bd77b 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -118,10 +118,85 @@ MinGW Improvements * ``--heap`` is now handled. (`D118405 `_) -MachO Improvements ------------------- - -* Item 1. +Mach-O Improvements +------------------- + +* The ``ld64.lld.darwinnew`` symlink has been removed. Use ``ld64.lld`` to + invoke the Mach-O backend from now on. Moreover, the symlink + ``ld64.lld.darwinold`` -- and the old Mach-O LLD code that it pointed to -- + have been removed. (`D114842 `_) +* The "cannot export hidden symbol" error has been downgraded to a warning. + (`D107011 `_) +* Common bitcode symbols are now supported. + (`D107027 `_) +* Weak references in bitcode are now supported. + (`D115949 `_) +* Thunk insertion now works more reliably. + (`D108897 `_, + `D108924 `_, + `D109079 `_, + `D116705 `_) +* ``-ObjC`` now loads archive members before the symbol resolution phase. + (`D108781 `_) +* ``-oso_prefix`` is now supported. + (`D112291 `_) +* Properly encode binaries with zero exported symbols. Tools like + ``codesign_allocate`` no longer choke on those binaries. + (`D112589 `_) +* We no longer treat architecture mismatches as a fatal error. Use + ``-arch_errors_fatal`` if that behavior is still desired. + (`D113082 `_) +* Several performance improvements were done to speed LLD up on projects with + a lot of framework flags and library lookups. Large Swift-based projects + will benefit significantly. + (`D113073 `_, + `D113063 `_, + `D113153 `_, + `D113235 `_) +* Several memory-reduction optimizations were done to reduce LLD's RSS + footprint. + (`D113813 `_, + `D113818 `_) +* Symbol patterns from ``-[un]exported_symbols_list`` are now processed in + parallel. (`D113820 `_) +* ``.weak_def_can_be_hidden`` symbols can now be exported. + (`D113167 `_) +* ``-S`` -- to omit debug info -- is now handled. + (`D112594 `_) +* ``-v`` now writes to stderr instead of stdout. + (`D113020 `_) +* Private externs with GOT relocations are now marked as LOCAL in the indirect + symbol table. This allows ``strip -x`` to remove more symbols. + (`D111852 `_) +* We no longer generate bogus addresses when ``__TEXT,__gcc_except_tab`` is + renamed. (`D113582 `_) +* Unreferenced weak dylib symbols no longer trigger fetches from an archive. + (`D115092 `_) +* ``$ld$hide`` symbols are now supported. + (`D115775 `_) +* Symbols imported via `-weak_framework` are now properly marked as weak refs. + (`D114397 `_) +* ``--warn-dylib-install-name`` and ``--no-warn-dylib-install-name`` were added + to toggle LLD-specific warnings around the use of ``-install_name``. + (`D113534 `_) +* Passing both ``--icf=all`` and ``-no_deduplicate`` no longer results in a + warning. (`D110672 `_) +* ICF now deduplicates functions with (identical) unwind info too. + (`D109946 `_) +* We now support ordering sections based on call graph profile data. + (`D112164 `_) +* Map file output now proceeds in parallel with output of the binary. + (`D117069 `_) +* The map file now contains dead-stripped symbols too. + (`D114737 `_) +* Multiple TLV sections with different alignments are now handled properly. + (`D116263 `_) +* ``--start-lib`` and ``--end-lib`` are now supported. + (`D116913 `_) +* ``-noall_load`` is now supported. + (`D117629 `_) +* ``-add_empty_section`` is now supported. + (`D117749 `_) WebAssembly Improvements ------------------------ From 7fdca71be63aa2abad2bff099c6754938a2fe4fc Mon Sep 17 00:00:00 2001 From: Arthur O'Dwyer Date: Tue, 1 Feb 2022 16:52:02 -0500 Subject: [PATCH 119/316] [libc++] Guard much of std::ranges under _LIBCPP_HAS_NO_INCOMPLETE_RANGES. The logic here is that we are disabling *only* things in `std::ranges::`. Everything in `std::` is permitted, including `default_sentinel`, `contiguous_iterator`, `common_iterator`, `projected`, `swappable`, and so on. Then, we include anything from `std::ranges::` that is required in order to make those things work: `ranges::swap`, `ranges::swap_ranges`, `input_range`, `ranges::begin`, `ranges::iter_move`, and so on. But then that's all. Everything else (including notably all of the "views" and the `std::views` namespace itself) is still locked up behind `_LIBCPP_HAS_NO_INCOMPLETE_RANGES`. Originally reviewed as https://reviews.llvm.org/D118736. (cherry picked from commit 53406fb691db38b21decf233e091f648f8317b2d) Differential Revision: https://reviews.llvm.org/D119853 --- libcxx/include/__algorithm/in_in_out_result.h | 4 +- libcxx/include/__algorithm/in_out_result.h | 4 +- .../include/__filesystem/directory_iterator.h | 2 +- .../recursive_directory_iterator.h | 2 +- .../include/__functional/ranges_operations.h | 5 ++- libcxx/include/__iterator/advance.h | 4 +- libcxx/include/__iterator/distance.h | 4 +- libcxx/include/__iterator/insert_iterator.h | 2 +- libcxx/include/__iterator/iter_move.h | 2 +- libcxx/include/__iterator/iter_swap.h | 1 - libcxx/include/__iterator/next.h | 4 +- libcxx/include/__iterator/prev.h | 4 +- libcxx/include/__memory/concepts.h | 6 ++- libcxx/include/__memory/ranges_construct_at.h | 4 +- .../ranges_uninitialized_algorithms.h | 6 ++- libcxx/include/__ranges/all.h | 4 +- libcxx/include/__ranges/common_view.h | 4 +- libcxx/include/__ranges/concepts.h | 12 ++++-- libcxx/include/__ranges/copyable_box.h | 4 +- libcxx/include/__ranges/counted.h | 4 +- libcxx/include/__ranges/dangling.h | 2 +- libcxx/include/__ranges/data.h | 4 +- libcxx/include/__ranges/drop_view.h | 4 +- libcxx/include/__ranges/empty.h | 4 +- libcxx/include/__ranges/empty_view.h | 4 +- .../include/__ranges/enable_borrowed_range.h | 3 +- libcxx/include/__ranges/enable_view.h | 2 +- libcxx/include/__ranges/iota_view.h | 4 +- libcxx/include/__ranges/join_view.h | 4 +- .../include/__ranges/non_propagating_cache.h | 4 +- libcxx/include/__ranges/owning_view.h | 4 +- libcxx/include/__ranges/range_adaptor.h | 4 +- libcxx/include/__ranges/ref_view.h | 4 +- libcxx/include/__ranges/reverse_view.h | 4 +- libcxx/include/__ranges/single_view.h | 4 +- libcxx/include/__ranges/size.h | 4 +- libcxx/include/__ranges/subrange.h | 4 +- libcxx/include/__ranges/take_view.h | 4 +- libcxx/include/__ranges/transform_view.h | 4 +- libcxx/include/__ranges/view_interface.h | 4 +- libcxx/include/ranges | 12 ++---- libcxx/include/span | 19 +++++---- libcxx/include/string_view | 8 ++-- .../nothrow_forward_iterator.compile.pass.cpp | 1 + .../nothrow_input_iterator.compile.pass.cpp | 1 + .../nothrow_sentinel_for.compile.pass.cpp | 1 + .../has-no-incomplete-ranges.compile.pass.cpp | 40 +++++++++++++++++++ .../range.access/end.incomplete_type.pass.cpp | 1 - .../different_from.compile.pass.cpp | 3 +- .../has_arrow.compile.pass.cpp | 3 +- .../algorithms.results/in_in_result.pass.cpp | 1 - .../views/span.cons/deduct.pass.cpp | 5 +++ .../constraints.verify.cpp | 1 + .../iterator_count.pass.cpp | 1 + .../iterator_count_sentinel.pass.cpp | 1 + .../iterator_sentinel.pass.cpp | 1 + .../iterator_sentinel.pass.cpp | 1 + .../range.iter.ops.distance/lwg3664.pass.cpp | 1 + .../constraints.compile.pass.cpp | 1 + .../range.iter.ops.next/iterator.pass.cpp | 1 + .../iterator_count.pass.cpp | 1 + .../iterator_count_sentinel.pass.cpp | 1 + .../iterator_sentinel.pass.cpp | 1 + .../constraints.compile.pass.cpp | 1 + .../range.iter.ops.prev/iterator.pass.cpp | 1 + .../iterator_count.pass.cpp | 1 + .../iterator_count_sentinel.pass.cpp | 1 + .../iter_move.nodiscard.verify.cpp | 1 + .../counted.iterator/compare.pass.cpp | 1 + .../iterators.common/assign.pass.cpp | 24 ++++------- .../std/ranges/range.access/begin.pass.cpp | 1 - .../test/std/ranges/range.access/end.pass.cpp | 1 - .../borrowed_range.compile.pass.cpp | 1 - ...orrowed_range.subsumption.compile.pass.cpp | 1 - .../enable_borrowed_range.compile.pass.cpp | 1 - .../from_iterator_sentinel.pass.cpp | 2 - .../string.view.deduct/range.pass.cpp | 1 + .../range.cmp/equal_to.pass.cpp | 1 + .../range.cmp/greater.pass.cpp | 1 + .../range.cmp/greater_equal.pass.cpp | 1 + .../function.objects/range.cmp/less.pass.cpp | 1 + .../range.cmp/less_equal.pass.cpp | 1 + .../range.cmp/not_equal_to.pass.cpp | 1 + libcxx/test/support/test_iterators.h | 6 ++- libcxx/test/support/test_macros.h | 4 -- 85 files changed, 185 insertions(+), 132 deletions(-) create mode 100644 libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp diff --git a/libcxx/include/__algorithm/in_in_out_result.h b/libcxx/include/__algorithm/in_in_out_result.h index a492d27352291..8d29b7b69b47c 100644 --- a/libcxx/include/__algorithm/in_in_out_result.h +++ b/libcxx/include/__algorithm/in_in_out_result.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { @@ -47,7 +47,7 @@ struct in_in_out_result { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/in_out_result.h b/libcxx/include/__algorithm/in_out_result.h index d3c16e4acd459..dcf72d08dd8a8 100644 --- a/libcxx/include/__algorithm/in_out_result.h +++ b/libcxx/include/__algorithm/in_out_result.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { @@ -47,7 +47,7 @@ struct in_out_result { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__filesystem/directory_iterator.h b/libcxx/include/__filesystem/directory_iterator.h index 1cb1794efdae9..cfaf2064beadf 100644 --- a/libcxx/include/__filesystem/directory_iterator.h +++ b/libcxx/include/__filesystem/directory_iterator.h @@ -143,7 +143,7 @@ template <> _LIBCPP_AVAILABILITY_FILESYSTEM inline constexpr bool _VSTD::ranges::enable_view<_VSTD_FS::directory_iterator> = true; -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__filesystem/recursive_directory_iterator.h b/libcxx/include/__filesystem/recursive_directory_iterator.h index c26d0a3811593..b80d59750ed0e 100644 --- a/libcxx/include/__filesystem/recursive_directory_iterator.h +++ b/libcxx/include/__filesystem/recursive_directory_iterator.h @@ -174,7 +174,7 @@ template <> _LIBCPP_AVAILABILITY_FILESYSTEM inline constexpr bool _VSTD::ranges::enable_view<_VSTD_FS::recursive_directory_iterator> = true; -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) #endif // _LIBCPP_CXX03_LANG diff --git a/libcxx/include/__functional/ranges_operations.h b/libcxx/include/__functional/ranges_operations.h index 8b06240e46a7a..a0ea7ccaffeff 100644 --- a/libcxx/include/__functional/ranges_operations.h +++ b/libcxx/include/__functional/ranges_operations.h @@ -20,7 +20,8 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + namespace ranges { struct equal_to { @@ -90,7 +91,7 @@ struct greater_equal { }; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/advance.h b/libcxx/include/__iterator/advance.h index 5b0e97d76be9a..d74d6b8b929ee 100644 --- a/libcxx/include/__iterator/advance.h +++ b/libcxx/include/__iterator/advance.h @@ -64,7 +64,7 @@ void advance(_InputIter& __i, _Distance __orig_n) { _VSTD::__advance(__i, __n, typename iterator_traits<_InputIter>::iterator_category()); } -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.iter.op.advance] @@ -192,7 +192,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/distance.h b/libcxx/include/__iterator/distance.h index 85309f8d47d6d..50ed76a4e53a9 100644 --- a/libcxx/include/__iterator/distance.h +++ b/libcxx/include/__iterator/distance.h @@ -52,7 +52,7 @@ distance(_InputIter __first, _InputIter __last) return _VSTD::__distance(__first, __last, typename iterator_traits<_InputIter>::iterator_category()); } -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.iter.op.distance] @@ -100,7 +100,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/insert_iterator.h b/libcxx/include/__iterator/insert_iterator.h index d3cd5ad6f9c50..dc617c1c93d71 100644 --- a/libcxx/include/__iterator/insert_iterator.h +++ b/libcxx/include/__iterator/insert_iterator.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template using __insert_iterator_iter_t = ranges::iterator_t<_Container>; #else diff --git a/libcxx/include/__iterator/iter_move.h b/libcxx/include/__iterator/iter_move.h index dfcf8e6c8308b..45d9ade682276 100644 --- a/libcxx/include/__iterator/iter_move.h +++ b/libcxx/include/__iterator/iter_move.h @@ -86,7 +86,7 @@ template<__dereferenceable _Tp> requires requires(_Tp& __t) { { ranges::iter_move(__t) } -> __referenceable; } using iter_rvalue_reference_t = decltype(ranges::iter_move(declval<_Tp&>())); -#endif // !_LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/iter_swap.h b/libcxx/include/__iterator/iter_swap.h index 0179546667b75..0b290520b702d 100644 --- a/libcxx/include/__iterator/iter_swap.h +++ b/libcxx/include/__iterator/iter_swap.h @@ -14,7 +14,6 @@ #include <__iterator/iter_move.h> #include <__iterator/iterator_traits.h> #include <__iterator/readable_traits.h> -#include <__ranges/access.h> #include <__utility/forward.h> #include <__utility/move.h> #include diff --git a/libcxx/include/__iterator/next.h b/libcxx/include/__iterator/next.h index 8683e2210e957..5dda0674d57e5 100644 --- a/libcxx/include/__iterator/next.h +++ b/libcxx/include/__iterator/next.h @@ -35,7 +35,7 @@ inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX14 return __x; } -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.iter.op.next] @@ -79,7 +79,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__iterator/prev.h b/libcxx/include/__iterator/prev.h index 5a58dc0e4b438..2b8c15fe57261 100644 --- a/libcxx/include/__iterator/prev.h +++ b/libcxx/include/__iterator/prev.h @@ -34,7 +34,7 @@ inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX14 return __x; } -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.iter.op.prev] @@ -71,7 +71,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__memory/concepts.h b/libcxx/include/__memory/concepts.h index dced563f38b67..eabc245c915e4 100644 --- a/libcxx/include/__memory/concepts.h +++ b/libcxx/include/__memory/concepts.h @@ -25,7 +25,8 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + namespace ranges { // [special.mem.concepts] @@ -59,7 +60,8 @@ concept __nothrow_forward_range = __nothrow_forward_iterator>; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) + +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__memory/ranges_construct_at.h b/libcxx/include/__memory/ranges_construct_at.h index b1821c8cc29e2..d26f726836e19 100644 --- a/libcxx/include/__memory/ranges_construct_at.h +++ b/libcxx/include/__memory/ranges_construct_at.h @@ -29,7 +29,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { // construct_at @@ -117,7 +117,7 @@ inline namespace __cpo { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__memory/ranges_uninitialized_algorithms.h b/libcxx/include/__memory/ranges_uninitialized_algorithms.h index 70d901a5ad03e..4a6123ec69467 100644 --- a/libcxx/include/__memory/ranges_uninitialized_algorithms.h +++ b/libcxx/include/__memory/ranges_uninitialized_algorithms.h @@ -32,7 +32,8 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + namespace ranges { // uninitialized_default_construct @@ -309,7 +310,8 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) + +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/all.h b/libcxx/include/__ranges/all.h index b0a58e9bad82c..acdf30a503a8e 100644 --- a/libcxx/include/__ranges/all.h +++ b/libcxx/include/__ranges/all.h @@ -28,7 +28,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges::views { @@ -75,7 +75,7 @@ using all_t = decltype(views::all(declval<_Range>())); } // namespace ranges::views -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/common_view.h b/libcxx/include/__ranges/common_view.h index fb8078d65558e..3be49e8dbe716 100644 --- a/libcxx/include/__ranges/common_view.h +++ b/libcxx/include/__ranges/common_view.h @@ -30,7 +30,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { @@ -128,7 +128,7 @@ inline namespace __cpo { } // namespace views } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/concepts.h b/libcxx/include/__ranges/concepts.h index 0590863138ed4..5f1fa834d4099 100644 --- a/libcxx/include/__ranges/concepts.h +++ b/libcxx/include/__ranges/concepts.h @@ -35,13 +35,18 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if !defined(_LIBCPP_HAS_NO_CONCEPTS) namespace ranges { + // [range.range] + template concept range = requires(_Tp& __t) { ranges::begin(__t); // sometimes equality-preserving ranges::end(__t); }; + template + concept input_range = range<_Tp> && input_iterator>; + template concept borrowed_range = range<_Range> && (is_lvalue_reference_v<_Range> || enable_borrowed_range>); @@ -63,6 +68,8 @@ namespace ranges { template using range_rvalue_reference_t = iter_rvalue_reference_t>; +#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + // [range.sized] template concept sized_range = range<_Tp> && requires(_Tp& __t) { ranges::size(__t); }; @@ -93,9 +100,6 @@ namespace ranges { template concept output_range = range<_Rp> && output_iterator, _Tp>; - template - concept input_range = range<_Tp> && input_iterator>; - template concept forward_range = input_range<_Tp> && forward_iterator>; @@ -131,6 +135,8 @@ namespace ranges { (is_lvalue_reference_v<_Tp> || (movable> && !__is_std_initializer_list>)))); +#endif // !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + } // namespace ranges #endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) diff --git a/libcxx/include/__ranges/copyable_box.h b/libcxx/include/__ranges/copyable_box.h index 608db55dbc5fb..77e47b1216b4e 100644 --- a/libcxx/include/__ranges/copyable_box.h +++ b/libcxx/include/__ranges/copyable_box.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // __copyable_box allows turning a type that is copy-constructible (but maybe not copy-assignable) into // a type that is both copy-constructible and copy-assignable. It does that by introducing an empty state @@ -171,7 +171,7 @@ namespace ranges { }; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/counted.h b/libcxx/include/__ranges/counted.h index 92bcf06be3ad1..2eb44035cbb29 100644 --- a/libcxx/include/__ranges/counted.h +++ b/libcxx/include/__ranges/counted.h @@ -29,7 +29,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges::views { @@ -74,7 +74,7 @@ inline namespace __cpo { } // namespace ranges::views -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/dangling.h b/libcxx/include/__ranges/dangling.h index b6b733a6eaa98..ecc7c093c92bd 100644 --- a/libcxx/include/__ranges/dangling.h +++ b/libcxx/include/__ranges/dangling.h @@ -35,7 +35,7 @@ using borrowed_iterator_t = _If, iterator_t<_Rp>, dangling>; // borrowed_subrange_t defined in <__ranges/subrange.h> } // namespace ranges -#endif // !_LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/data.h b/libcxx/include/__ranges/data.h index f97ec80332976..f8d92cbc75204 100644 --- a/libcxx/include/__ranges/data.h +++ b/libcxx/include/__ranges/data.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.prim.data] @@ -99,7 +99,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/drop_view.h b/libcxx/include/__ranges/drop_view.h index 1e2bfa40b325d..8ff895863e2a9 100644 --- a/libcxx/include/__ranges/drop_view.h +++ b/libcxx/include/__ranges/drop_view.h @@ -31,7 +31,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -120,7 +120,7 @@ namespace ranges { inline constexpr bool enable_borrowed_range> = enable_borrowed_range<_Tp>; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/empty.h b/libcxx/include/__ranges/empty.h index b06a81c98e8fe..1be55c192f60e 100644 --- a/libcxx/include/__ranges/empty.h +++ b/libcxx/include/__ranges/empty.h @@ -22,7 +22,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // [range.prim.empty] @@ -75,7 +75,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/empty_view.h b/libcxx/include/__ranges/empty_view.h index e0116b933797c..b5509098da273 100644 --- a/libcxx/include/__ranges/empty_view.h +++ b/libcxx/include/__ranges/empty_view.h @@ -20,7 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -38,7 +38,7 @@ namespace ranges { inline constexpr bool enable_borrowed_range> = true; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/enable_borrowed_range.h b/libcxx/include/__ranges/enable_borrowed_range.h index f9985dfd0061b..5523285580ea9 100644 --- a/libcxx/include/__ranges/enable_borrowed_range.h +++ b/libcxx/include/__ranges/enable_borrowed_range.h @@ -24,8 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if !defined(_LIBCPP_HAS_NO_CONCEPTS) -namespace ranges -{ +namespace ranges { // [range.range], ranges diff --git a/libcxx/include/__ranges/enable_view.h b/libcxx/include/__ranges/enable_view.h index 87d53f3fcc8ca..837d44908bf5b 100644 --- a/libcxx/include/__ranges/enable_view.h +++ b/libcxx/include/__ranges/enable_view.h @@ -40,7 +40,7 @@ inline constexpr bool enable_view = derived_from<_Tp, view_base> || } // namespace ranges -#endif // !_LIBCPP_HAS_NO_CONCEPTS +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/iota_view.h b/libcxx/include/__ranges/iota_view.h index 17f6021f7dd4a..b74f57d7cd68c 100644 --- a/libcxx/include/__ranges/iota_view.h +++ b/libcxx/include/__ranges/iota_view.h @@ -39,7 +39,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -401,7 +401,7 @@ inline namespace __cpo { } // namespace views } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/join_view.h b/libcxx/include/__ranges/join_view.h index 7efbcfdf87884..26674b30f6105 100644 --- a/libcxx/include/__ranges/join_view.h +++ b/libcxx/include/__ranges/join_view.h @@ -30,7 +30,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -343,7 +343,7 @@ namespace ranges { #undef _CONSTEXPR_TERNARY -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/non_propagating_cache.h b/libcxx/include/__ranges/non_propagating_cache.h index 2d3a9408713e4..0e464e169088f 100644 --- a/libcxx/include/__ranges/non_propagating_cache.h +++ b/libcxx/include/__ranges/non_propagating_cache.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { // __non_propagating_cache is a helper type that allows storing an optional value in it, @@ -107,7 +107,7 @@ namespace ranges { struct __empty_cache { }; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/owning_view.h b/libcxx/include/__ranges/owning_view.h index 9c038cbd7580d..7206f813b1dd7 100644 --- a/libcxx/include/__ranges/owning_view.h +++ b/libcxx/include/__ranges/owning_view.h @@ -28,7 +28,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -74,7 +74,7 @@ namespace ranges { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/range_adaptor.h b/libcxx/include/__ranges/range_adaptor.h index d037585d26795..fbe3b888668a5 100644 --- a/libcxx/include/__ranges/range_adaptor.h +++ b/libcxx/include/__ranges/range_adaptor.h @@ -25,7 +25,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) // CRTP base that one can derive from in order to be considered a range adaptor closure // by the library. When deriving from this class, a pipe operator will be provided to @@ -66,7 +66,7 @@ struct __range_adaptor_closure { { return __range_adaptor_closure_t(_VSTD::__compose(_VSTD::forward<_OtherClosure>(__c2), _VSTD::forward<_Closure>(__c1))); } }; -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/ref_view.h b/libcxx/include/__ranges/ref_view.h index 4d12759e614f9..8777b71ac5e2b 100644 --- a/libcxx/include/__ranges/ref_view.h +++ b/libcxx/include/__ranges/ref_view.h @@ -31,7 +31,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -79,7 +79,7 @@ namespace ranges { inline constexpr bool enable_borrowed_range> = true; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/reverse_view.h b/libcxx/include/__ranges/reverse_view.h index 04ac7f29aa7cd..a2519e3cb1a67 100644 --- a/libcxx/include/__ranges/reverse_view.h +++ b/libcxx/include/__ranges/reverse_view.h @@ -33,7 +33,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -183,7 +183,7 @@ namespace ranges { } // namespace views } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/single_view.h b/libcxx/include/__ranges/single_view.h index c6f0746ea795d..bf5a5e2700ef6 100644 --- a/libcxx/include/__ranges/single_view.h +++ b/libcxx/include/__ranges/single_view.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -74,7 +74,7 @@ namespace ranges { single_view(_Tp) -> single_view<_Tp>; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/size.h b/libcxx/include/__ranges/size.h index e1aaf7eba898e..2b71c03fb3996 100644 --- a/libcxx/include/__ranges/size.h +++ b/libcxx/include/__ranges/size.h @@ -24,7 +24,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -128,7 +128,7 @@ inline namespace __cpo { } // namespace __cpo } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/subrange.h b/libcxx/include/__ranges/subrange.h index c6977cec36721..47752a9d05c87 100644 --- a/libcxx/include/__ranges/subrange.h +++ b/libcxx/include/__ranges/subrange.h @@ -36,7 +36,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -282,7 +282,7 @@ struct tuple_element<1, const ranges::subrange<_Ip, _Sp, _Kp>> { using type = _Sp; }; -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/take_view.h b/libcxx/include/__ranges/take_view.h index 4d45219020da9..16b9faf168b92 100644 --- a/libcxx/include/__ranges/take_view.h +++ b/libcxx/include/__ranges/take_view.h @@ -34,7 +34,7 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { template @@ -176,7 +176,7 @@ namespace ranges { inline constexpr bool enable_borrowed_range> = enable_borrowed_range<_Tp>; } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/transform_view.h b/libcxx/include/__ranges/transform_view.h index d39dd40972905..34a64f623a3ba 100644 --- a/libcxx/include/__ranges/transform_view.h +++ b/libcxx/include/__ranges/transform_view.h @@ -41,7 +41,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { @@ -433,7 +433,7 @@ inline namespace __cpo { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__ranges/view_interface.h b/libcxx/include/__ranges/view_interface.h index 0a37323df8174..63417652c1223 100644 --- a/libcxx/include/__ranges/view_interface.h +++ b/libcxx/include/__ranges/view_interface.h @@ -27,7 +27,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) namespace ranges { @@ -188,7 +188,7 @@ class view_interface { } // namespace ranges -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/ranges b/libcxx/include/ranges index 2d79d87eef895..82ad7f4d507f2 100644 --- a/libcxx/include/ranges +++ b/libcxx/include/ranges @@ -200,11 +200,6 @@ namespace std::ranges { */ -// Make sure all feature-test macros are available. -#include -// Enable the contents of the header only when libc++ was built with LIBCXX_ENABLE_INCOMPLETE_FEATURES. -#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) - #include <__config> #include <__ranges/access.h> #include <__ranges/all.h> @@ -232,19 +227,18 @@ namespace std::ranges { #include // Required by the standard. #include // Required by the standard. #include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) #pragma GCC system_header #endif -_LIBCPP_BEGIN_NAMESPACE_STD +#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +_LIBCPP_BEGIN_NAMESPACE_STD namespace views = ranges::views; -#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) - _LIBCPP_END_NAMESPACE_STD #endif // !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) diff --git a/libcxx/include/span b/libcxx/include/span index bd11330e69d9d..fd95ecca17f7b 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -170,7 +170,7 @@ struct __is_std_span : false_type {}; template struct __is_std_span> : true_type {}; -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template concept __span_compatible_range = ranges::contiguous_range<_Range> && @@ -234,7 +234,7 @@ public: _LIBCPP_ASSERT(__last - __first == _Extent, "invalid range in span's constructor (iterator, sentinel): last - first != extent"); } -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) _LIBCPP_INLINE_VISIBILITY constexpr span(type_identity_t (&__arr)[_Extent]) noexcept : __data{__arr} {} @@ -248,13 +248,13 @@ public: _LIBCPP_INLINE_VISIBILITY constexpr span(const array<_OtherElementType, _Extent>& __arr) noexcept : __data{__arr.data()} {} -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template <__span_compatible_range _Range> _LIBCPP_INLINE_VISIBILITY constexpr explicit span(_Range&& __r) : __data{ranges::data(__r)} { _LIBCPP_ASSERT(ranges::size(__r) == _Extent, "size mismatch in span's constructor (range)"); } -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template _LIBCPP_INLINE_VISIBILITY @@ -418,7 +418,7 @@ public: _LIBCPP_INLINE_VISIBILITY constexpr span(_It __first, _End __last) : __data(_VSTD::to_address(__first)), __size(__last - __first) {} -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) template _LIBCPP_INLINE_VISIBILITY @@ -434,11 +434,11 @@ public: _LIBCPP_INLINE_VISIBILITY constexpr span(const array<_OtherElementType, _Sz>& __arr) noexcept : __data{__arr.data()}, __size{_Sz} {} -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template <__span_compatible_range _Range> _LIBCPP_INLINE_VISIBILITY constexpr span(_Range&& __r) : __data(ranges::data(__r)), __size{ranges::size(__r)} {} -# endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template _LIBCPP_INLINE_VISIBILITY @@ -565,10 +565,9 @@ auto as_writable_bytes(span<_Tp, _Extent> __s) noexcept { return __s.__as_writable_bytes(); } #if !defined(_LIBCPP_HAS_NO_CONCEPTS) -// Deduction guides template span(_It, _EndOrSize) -> span>>; -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) template span(_Tp (&)[_Sz]) -> span<_Tp, _Sz>; @@ -579,7 +578,7 @@ template template span(const array<_Tp, _Sz>&) -> span; -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template span(_Range&&) -> span>>; #endif diff --git a/libcxx/include/string_view b/libcxx/include/string_view index 5d0a790dd13dd..97b24eb44108c 100644 --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -294,9 +294,9 @@ public: { _LIBCPP_ASSERT((__end - __begin) >= 0, "std::string_view::string_view(iterator, sentinel) received invalid range"); } -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) -#if _LIBCPP_STD_VER > 20 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if _LIBCPP_STD_VER > 20 && !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template requires ( !is_same_v, basic_string_view> && @@ -720,10 +720,10 @@ inline constexpr bool ranges::enable_borrowed_range _End> basic_string_view(_It, _End) -> basic_string_view>; -#endif +#endif // !defined(_LIBCPP_HAS_NO_CONCEPTS) -#if _LIBCPP_STD_VER > 20 && !defined(_LIBCPP_HAS_NO_CONCEPTS) +#if _LIBCPP_STD_VER > 20 && !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) template basic_string_view(_Range) -> basic_string_view>; #endif diff --git a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_forward_iterator.compile.pass.cpp b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_forward_iterator.compile.pass.cpp index 8567cf2dc9263..192955002fa65 100644 --- a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_forward_iterator.compile.pass.cpp +++ b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_forward_iterator.compile.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // concept __nothrow_forward_iterator; diff --git a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_input_iterator.compile.pass.cpp b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_input_iterator.compile.pass.cpp index 03e655284cc4a..6fdf6133c7e9d 100644 --- a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_input_iterator.compile.pass.cpp +++ b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_input_iterator.compile.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // concept __nothrow_input_iterator; diff --git a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_sentinel_for.compile.pass.cpp b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_sentinel_for.compile.pass.cpp index 7bd97b0115ec0..ce9d18b7812b1 100644 --- a/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_sentinel_for.compile.pass.cpp +++ b/libcxx/test/libcxx/algorithms/specialized.algorithms/special.mem.concepts/nothrow_sentinel_for.compile.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // concept __nothrow_sentinel_for; diff --git a/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp b/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp new file mode 100644 index 0000000000000..a131f87ae1e4d --- /dev/null +++ b/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp @@ -0,0 +1,40 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// REQUIRES: libcpp-has-no-incomplete-ranges + +// Test that _LIBCPP_HAS_NO_INCOMPLETE_RANGES disables the std::ranges namespace. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +_LIBCPP_BEGIN_NAMESPACE_STD +namespace ranges { + int output_range; + int data; + int size; + int prev; + int next; + int distance; + int take_view; + int drop_view; + int transform_view; + int filter_view; + int join_view; + int views; // this entire namespace should be absent +} +_LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/test/libcxx/ranges/range.access/end.incomplete_type.pass.cpp b/libcxx/test/libcxx/ranges/range.access/end.incomplete_type.pass.cpp index b4e9068faad69..c038fa78aa4e7 100644 --- a/libcxx/test/libcxx/ranges/range.access/end.incomplete_type.pass.cpp +++ b/libcxx/test/libcxx/ranges/range.access/end.incomplete_type.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // Test the libc++-specific behavior that we handle the IFNDR case for ranges::end // by being SFINAE-friendly. diff --git a/libcxx/test/libcxx/ranges/range.utility.helpers/different_from.compile.pass.cpp b/libcxx/test/libcxx/ranges/range.utility.helpers/different_from.compile.pass.cpp index 7a9c4028cbf03..9f33510a5683c 100644 --- a/libcxx/test/libcxx/ranges/range.utility.helpers/different_from.compile.pass.cpp +++ b/libcxx/test/libcxx/ranges/range.utility.helpers/different_from.compile.pass.cpp @@ -10,9 +10,8 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges -#include +#include #include "test_macros.h" diff --git a/libcxx/test/libcxx/ranges/range.utility.helpers/has_arrow.compile.pass.cpp b/libcxx/test/libcxx/ranges/range.utility.helpers/has_arrow.compile.pass.cpp index 94b20c8643e9d..f59b6c5c8ac7d 100644 --- a/libcxx/test/libcxx/ranges/range.utility.helpers/has_arrow.compile.pass.cpp +++ b/libcxx/test/libcxx/ranges/range.utility.helpers/has_arrow.compile.pass.cpp @@ -10,9 +10,8 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges -#include +#include #include "test_macros.h" diff --git a/libcxx/test/std/algorithms/algorithms.results/in_in_result.pass.cpp b/libcxx/test/std/algorithms/algorithms.results/in_in_result.pass.cpp index fbb6da6340ff8..b86e4d882695b 100644 --- a/libcxx/test/std/algorithms/algorithms.results/in_in_result.pass.cpp +++ b/libcxx/test/std/algorithms/algorithms.results/in_in_result.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // struct in_in_result; diff --git a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp index e20c1811a7ffa..81632fed711d3 100644 --- a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp @@ -86,6 +86,7 @@ void test_std_array() { } } +#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES void test_range_std_container() { { std::string str{"ABCDE"}; @@ -103,13 +104,17 @@ void test_range_std_container() { assert(s.data() == str.data()); } } +#endif // _LIBCPP_HAS_NO_INCOMPLETE_RANGES int main(int, char**) { test_iterator_sentinel(); test_c_array(); test_std_array(); + +#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES test_range_std_container(); +#endif // _LIBCPP_HAS_NO_INCOMPLETE_RANGES return 0; } diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/constraints.verify.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/constraints.verify.cpp index b509b1e1d2549..6110bcf7e2fe7 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/constraints.verify.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/constraints.verify.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count.pass.cpp index f8da9e7c1e0dd..f4c235769f62b 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::advance(it, n) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count_sentinel.pass.cpp index 75f12802af7f5..eb1ab87622d05 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::advance(it, n, sent) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_sentinel.pass.cpp index 3332aa1bc53fc..e7662919e8195 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::advance(it, sent) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/iterator_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/iterator_sentinel.pass.cpp index d15fcc7404cb2..f8e8faf38479d 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/iterator_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/iterator_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template S> // requires (!sized_sentinel_for) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/lwg3664.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/lwg3664.pass.cpp index 3e68de3b6933c..6be09d5c61fd7 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/lwg3664.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.distance/lwg3664.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template S> // requires (!sized_sentinel_for) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/constraints.compile.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/constraints.compile.pass.cpp index ebcdff5f54d14..e00f4d1e27e06 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/constraints.compile.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/constraints.compile.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next // Make sure we're SFINAE-friendly when the template argument constraints are not met. diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator.pass.cpp index 972b410cf2f2f..7e779b0e14605 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next(it) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count.pass.cpp index 0bc400dde1b44..6e89039db04a8 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next(it, n) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count_sentinel.pass.cpp index 5cfbbf3c5a156..96f3f7f581b93 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next(it, n, bound) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_sentinel.pass.cpp index 633a6bd7b6de5..c2871a8535842 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::next(it, bound) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/constraints.compile.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/constraints.compile.pass.cpp index b72aa132df17d..e656959d6b058 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/constraints.compile.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/constraints.compile.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::prev // Make sure we're SFINAE-friendly when the template argument constraints are not met. diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator.pass.cpp index 334b674adeb79..2f1452d937f71 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::prev(it) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count.pass.cpp index 2a4cee39fdbc9..547aae5cf3946 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::prev(it, n) diff --git a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count_sentinel.pass.cpp b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count_sentinel.pass.cpp index 253194605fcfb..e126d1ec35f18 100644 --- a/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count_sentinel.pass.cpp +++ b/libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count_sentinel.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // ranges::prev(it, n, bound) diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.nodiscard.verify.cpp b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.nodiscard.verify.cpp index d7cde443b16bc..3355b4db0b8de 100644 --- a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.nodiscard.verify.cpp +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/iterator.cust.move/iter_move.nodiscard.verify.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // Test the [[nodiscard]] extension in libc++. diff --git a/libcxx/test/std/iterators/predef.iterators/counted.iterator/compare.pass.cpp b/libcxx/test/std/iterators/predef.iterators/counted.iterator/compare.pass.cpp index d1749e4588f6d..074bf16b114f9 100644 --- a/libcxx/test/std/iterators/predef.iterators/counted.iterator/compare.pass.cpp +++ b/libcxx/test/std/iterators/predef.iterators/counted.iterator/compare.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template I2> // friend constexpr bool operator==( diff --git a/libcxx/test/std/iterators/predef.iterators/iterators.common/assign.pass.cpp b/libcxx/test/std/iterators/predef.iterators/iterators.common/assign.pass.cpp index dd6e1dce5f5f1..cd896c36d8dac 100644 --- a/libcxx/test/std/iterators/predef.iterators/iterators.common/assign.pass.cpp +++ b/libcxx/test/std/iterators/predef.iterators/iterators.common/assign.pass.cpp @@ -15,9 +15,7 @@ // common_iterator& operator=(const common_iterator& x); #include -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES #include -#endif #include #include "test_macros.h" @@ -56,7 +54,6 @@ void test() { assert(*commonIter2 == 2); assert(commonIter1 == commonIter2); } -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES { auto iter1 = random_access_iterator(buffer); auto commonIter1 = std::common_iterator>(iter1); @@ -75,15 +72,14 @@ void test() { assert(*commonIter2 == 2); assert(commonIter1 == commonIter2); - assert(std::ranges::next(commonIter1, 6) != commonSent1); - assert(std::ranges::next(commonIter1, 6) == commonSent2); + assert(std::next(commonIter1, 6) != commonSent1); + assert(std::next(commonIter1, 6) == commonSent2); commonSent1 = commonSent2; - assert(std::ranges::next(commonIter1, 6) == commonSent1); - assert(std::ranges::next(commonIter1, 6) == commonSent2); + assert(std::next(commonIter1, 6) == commonSent1); + assert(std::next(commonIter1, 6) == commonSent2); } -#endif { auto iter1 = assignable_iterator(buffer); auto iter2 = forward_iterator(buffer + 1); @@ -102,17 +98,13 @@ void test() { assert(*commonIter2 == 2); assert(commonIter1 == commonIter2); -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES - assert(std::ranges::next(commonIter1, 6) != commonSent1); - assert(std::ranges::next(commonIter1, 6) == commonSent2); -#endif + assert(std::next(commonIter1, 6) != commonSent1); + assert(std::next(commonIter1, 6) == commonSent2); commonSent1 = commonSent2; -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES - assert(std::ranges::next(commonIter1, 6) == commonSent1); - assert(std::ranges::next(commonIter1, 6) == commonSent2); -#endif + assert(std::next(commonIter1, 6) == commonSent1); + assert(std::next(commonIter1, 6) == commonSent2); commonIter1 = commonSent1; diff --git a/libcxx/test/std/ranges/range.access/begin.pass.cpp b/libcxx/test/std/ranges/range.access/begin.pass.cpp index 7014681ccabf9..37be374729904 100644 --- a/libcxx/test/std/ranges/range.access/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.access/begin.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // std::ranges::begin // std::ranges::cbegin diff --git a/libcxx/test/std/ranges/range.access/end.pass.cpp b/libcxx/test/std/ranges/range.access/end.pass.cpp index 5f4f05279cdda..1a58d87294943 100644 --- a/libcxx/test/std/ranges/range.access/end.pass.cpp +++ b/libcxx/test/std/ranges/range.access/end.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // std::ranges::end // std::ranges::cend diff --git a/libcxx/test/std/ranges/range.req/range.range/borrowed_range.compile.pass.cpp b/libcxx/test/std/ranges/range.req/range.range/borrowed_range.compile.pass.cpp index 150aa8230cb66..a08750c13c0d0 100644 --- a/libcxx/test/std/ranges/range.req/range.range/borrowed_range.compile.pass.cpp +++ b/libcxx/test/std/ranges/range.req/range.range/borrowed_range.compile.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // concept borrowed_range; diff --git a/libcxx/test/std/ranges/range.req/range.range/borrowed_range.subsumption.compile.pass.cpp b/libcxx/test/std/ranges/range.req/range.range/borrowed_range.subsumption.compile.pass.cpp index 5937509bb9f58..b2bd797295ac1 100644 --- a/libcxx/test/std/ranges/range.req/range.range/borrowed_range.subsumption.compile.pass.cpp +++ b/libcxx/test/std/ranges/range.req/range.range/borrowed_range.subsumption.compile.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // template // concept borrowed_range; diff --git a/libcxx/test/std/ranges/range.req/range.range/enable_borrowed_range.compile.pass.cpp b/libcxx/test/std/ranges/range.req/range.range/enable_borrowed_range.compile.pass.cpp index b2267431b1a49..46755e3129c05 100644 --- a/libcxx/test/std/ranges/range.req/range.range/enable_borrowed_range.compile.pass.cpp +++ b/libcxx/test/std/ranges/range.req/range.range/enable_borrowed_range.compile.pass.cpp @@ -8,7 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/strings/string.view/string.view.cons/from_iterator_sentinel.pass.cpp b/libcxx/test/std/strings/string.view/string.view.cons/from_iterator_sentinel.pass.cpp index f53018c5c8e0a..931eac89aede3 100644 --- a/libcxx/test/std/strings/string.view/string.view.cons/from_iterator_sentinel.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.cons/from_iterator_sentinel.pass.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts -// UNSUPPORTED: libcpp-has-no-incomplete-ranges // @@ -17,7 +16,6 @@ #include #include #include -#include #include "make_string.h" #include "test_iterators.h" diff --git a/libcxx/test/std/strings/string.view/string.view.deduct/range.pass.cpp b/libcxx/test/std/strings/string.view/string.view.deduct/range.pass.cpp index d8858db9b04b1..828f4e80ddd6c 100644 --- a/libcxx/test/std/strings/string.view/string.view.deduct/range.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.deduct/range.pass.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/equal_to.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/equal_to.pass.cpp index c27159407bb5f..43cfbd9760277 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/equal_to.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/equal_to.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/greater.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/greater.pass.cpp index 95f490d951023..31aa4274e5a70 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/greater.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/greater.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/greater_equal.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/greater_equal.pass.cpp index a3e8ff215bb75..547c8f37e717b 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/greater_equal.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/greater_equal.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/less.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/less.pass.cpp index 72f54b7b923fb..7415ed1202a0e 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/less.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/less.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/less_equal.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/less_equal.pass.cpp index 05cc56e89d403..aa066191e83bf 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/less_equal.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/less_equal.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/std/utilities/function.objects/range.cmp/not_equal_to.pass.cpp b/libcxx/test/std/utilities/function.objects/range.cmp/not_equal_to.pass.cpp index 142aaf1f74286..3e91524902a68 100644 --- a/libcxx/test/std/utilities/function.objects/range.cmp/not_equal_to.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/range.cmp/not_equal_to.pass.cpp @@ -8,6 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // UNSUPPORTED: libcpp-no-concepts +// UNSUPPORTED: libcpp-has-no-incomplete-ranges // diff --git a/libcxx/test/support/test_iterators.h b/libcxx/test/support/test_iterators.h index 60313a5889a52..679f978861ede 100644 --- a/libcxx/test/support/test_iterators.h +++ b/libcxx/test/support/test_iterators.h @@ -484,7 +484,8 @@ struct NonThrowingIterator { const T *current_; }; -#ifdef TEST_SUPPORTS_RANGES +#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) + template class cpp20_input_iterator { @@ -669,7 +670,8 @@ class stride_counting_iterator { difference_type stride_count_ = 0; difference_type stride_displacement_ = 0; }; -#endif // TEST_SUPPORTS_RANGES + +#endif // TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_CONCEPTS) #if TEST_STD_VER > 17 template diff --git a/libcxx/test/support/test_macros.h b/libcxx/test/support/test_macros.h index d1923848b7f52..cb49e28d5f6a8 100644 --- a/libcxx/test/support/test_macros.h +++ b/libcxx/test/support/test_macros.h @@ -243,10 +243,6 @@ #define LIBCPP_ONLY(...) static_assert(true, "") #endif -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) -#define TEST_SUPPORTS_RANGES -#endif - #define TEST_IGNORE_NODISCARD (void) namespace test_macros_detail { From 199e05e34bb8beb1cafce3a086932a32c493fa13 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 15 Feb 2022 15:10:27 -0500 Subject: [PATCH 120/316] [libc++] Add missing UNSUPPORTED for the has-no-incomplete-ranges test This wasn't caught because we don't test the combination of no-filesystem and no-experimental-features in the CI. (cherry picked from commit 7dad5f84f1b8a7aafd5a27ce2889bd72a1e54002) --- .../test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp b/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp index a131f87ae1e4d..0d151073ca481 100644 --- a/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp +++ b/libcxx/test/libcxx/ranges/has-no-incomplete-ranges.compile.pass.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: libcpp-has-no-filesystem-library // REQUIRES: libcpp-has-no-incomplete-ranges // Test that _LIBCPP_HAS_NO_INCOMPLETE_RANGES disables the std::ranges namespace. From dfc24b8522ba9943e20bc4162d42d6b49bf85214 Mon Sep 17 00:00:00 2001 From: Konstantin Varlamov Date: Fri, 11 Feb 2022 11:56:29 -0800 Subject: [PATCH 121/316] [libc++][NFC] Work around false positive ODR violations from ASan. This works around a known issue in ASan. ASan doesn't instrument weak symbols. Because instrumentation increases object size, the binary can end up with two versions of the same object, one instrumented and one not instrumented, with different sizes, which ASan will report as an ODR violation. In libc++, this affects typeinfo for `std::bad_function_call` which is emitted as a weak symbol in the test executable and as a strong symbol in the shared library. The main open issue for ASan appears to be https://github.com/google/sanitizers/issues/1017. Differential Revision: https://reviews.llvm.org/D119410 (cherry picked from commit 10953974ed6b61247fd4b070b3a6e390e02d0edb) --- libcxx/cmake/caches/Generic-asan.cmake | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libcxx/cmake/caches/Generic-asan.cmake b/libcxx/cmake/caches/Generic-asan.cmake index cf919765c3a29..a86b34748550b 100644 --- a/libcxx/cmake/caches/Generic-asan.cmake +++ b/libcxx/cmake/caches/Generic-asan.cmake @@ -1 +1,3 @@ set(LLVM_USE_SANITIZER "Address" CACHE STRING "") +# This is a temporary (hopefully) workaround for an ASan issue (see https://llvm.org/D119410). +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mllvm -asan-use-private-alias=1" CACHE INTERNAL "") From 2fc17e919f0cc6d6ca7ce189f0dc0c7bd82344c2 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 15 Feb 2022 15:47:45 -0500 Subject: [PATCH 122/316] [libc++] Temporarily silence failing debug mode test Also, fix the actual code so that the test would pass if we fixed the issue that the method is instantiated in the dylib, and hence the debug assertion will never fire except if the debug mode is enabled when the dylib is being compiled. (cherry picked from commit 5c53afe5aac0d295a9345cd439c6caf3ac5eb8ba) --- libcxx/include/string | 4 ++++ .../string.modifiers/insert_iter_char_db1.pass.cpp | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/libcxx/include/string b/libcxx/include/string index 01cff902e07db..fd6a7424c815f 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -2897,6 +2897,10 @@ template typename basic_string<_CharT, _Traits, _Allocator>::iterator basic_string<_CharT, _Traits, _Allocator>::insert(const_iterator __pos, value_type __c) { + _LIBCPP_DEBUG_ASSERT(__get_const_db()->__find_c_from_i(&__pos) == this, + "string::insert(iterator, character) called with an iterator not" + " referring to this string"); + size_type __ip = static_cast(__pos - begin()); size_type __sz = size(); size_type __cap = capacity(); diff --git a/libcxx/test/libcxx/strings/basic.string/string.modifiers/insert_iter_char_db1.pass.cpp b/libcxx/test/libcxx/strings/basic.string/string.modifiers/insert_iter_char_db1.pass.cpp index c6a81ebfa65ae..ac05b69cf5561 100644 --- a/libcxx/test/libcxx/strings/basic.string/string.modifiers/insert_iter_char_db1.pass.cpp +++ b/libcxx/test/libcxx/strings/basic.string/string.modifiers/insert_iter_char_db1.pass.cpp @@ -14,6 +14,12 @@ // ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DEBUG=1 +// TODO: Since string::insert(iter, char) is intantiated in the dylib, this test doesn't +// actually work if the dylib hasn't been built with debug assertions enabled. +// Until we overhaul the debug mode, mark this test as unsupported to avoid +// spurious CI failures. +// REQUIRES: never-run + #include #include "test_macros.h" @@ -24,7 +30,8 @@ int main(int, char**) typedef std::string S; S s; S s2; - TEST_LIBCPP_ASSERT_FAILURE(s.insert(s2.begin(), '1'), "Attempted to subtract incompatible iterators"); + TEST_LIBCPP_ASSERT_FAILURE(s.insert(s2.begin(), '1'), + "string::insert(iterator, character) called with an iterator not referring to this string"); return 0; } From edf64474d66286a7f5578a033d1c3ccb31f2a2a7 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 15 Feb 2022 12:57:27 -0800 Subject: [PATCH 123/316] [ELF][PPC64] Fix assertion failure for branches to hidden undefined weak for -no-pie Reported by Stefan Pintilie in D119773. For a branch to a hidden undefined weak symbol, there is an `assert(sym->getVA());` failure in PPC64LongBranchTargetSection::writeTo for a -no-pie link. The root cause is that we unnecessarily create the thunk for the -no-pie link. Fix this by changing the condition to just `s.isUndefined()`. See the inline comment. Rename ppc64-weak-undef-call.s to ppc64-undefined-weak.s to be consistent with other architectures. Reviewed By: sfertile, stefanp Differential Revision: https://reviews.llvm.org/D119787 (cherry picked from commit 53b59fdc52bf6c8bf15ce7c146d2cebe338f34a7) --- lld/ELF/Arch/PPC64.cpp | 7 ++-- lld/test/ELF/ppc64-undefined-weak.s | 40 +++++++++++++++++++++ lld/test/ELF/ppc64-undefined.s | 11 ++++++ lld/test/ELF/ppc64-weak-undef-call-shared.s | 21 ----------- lld/test/ELF/ppc64-weak-undef-call.s | 29 --------------- 5 files changed, 55 insertions(+), 53 deletions(-) create mode 100644 lld/test/ELF/ppc64-undefined-weak.s create mode 100644 lld/test/ELF/ppc64-undefined.s delete mode 100644 lld/test/ELF/ppc64-weak-undef-call-shared.s delete mode 100644 lld/test/ELF/ppc64-weak-undef-call.s diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp index c083484f42804..7d051c43af0d3 100644 --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -1380,9 +1380,10 @@ bool PPC64::needsThunk(RelExpr expr, RelType type, const InputFile *file, if (type == R_PPC64_REL24_NOTOC && (s.stOther >> 5) > 1) return true; - // If a symbol is a weak undefined and we are compiling an executable - // it doesn't need a range-extending thunk since it can't be called. - if (s.isUndefWeak() && !config->shared) + // An undefined weak symbol not in a PLT does not need a thunk. If it is + // hidden, its binding has been converted to local, so we just check + // isUndefined() here. A undefined non-weak symbol has been errored. + if (s.isUndefined()) return false; // If the offset exceeds the range of the branch type then it will need diff --git a/lld/test/ELF/ppc64-undefined-weak.s b/lld/test/ELF/ppc64-undefined-weak.s new file mode 100644 index 0000000000000..7b1be5e36dd32 --- /dev/null +++ b/lld/test/ELF/ppc64-undefined-weak.s @@ -0,0 +1,40 @@ +# REQUIRES: ppc + +# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o +# RUN: ld.lld %t.o -o %t +# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=PDE +# RUN: ld.lld -pie %t.o -o %t +# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=PIC +# RUN: ld.lld -shared %t.o -o %t.so +# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s --check-prefix=PIC + +# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s -o %t.o +# RUN: ld.lld %t.o -o %t +# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=PDE + +## Branches to an undefined weak symbol need a thunk iff a dynamic relocation is +## produced. undefweak2 is hidden and does not need a dynamic relocation, so we +## suppress the thunk. undefweak1 needs a thunk iff -pie or -shared. + +# PDE-LABEL: <_start>: +# PDE-NEXT: bl {{.*}} <_start> +# PDE-NEXT: nop +# PDE-NEXT: bl {{.*}} <_start+0x8> +# PDE-NEXT: nop + +# PIC-LABEL: <_start>: +# PIC-NEXT: bl {{.*}} <__plt_undefweak1> +# PIC-NEXT: ld 2, 24(1) +# PIC-NEXT: bl {{.*}} <_start+0x8> +# PIC-NEXT: nop + +.text +.global _start +_start: + bl undefweak1 + nop + bl undefweak2 + nop + +.weak undefweak1, undefweak2 +.hidden undefweak2 diff --git a/lld/test/ELF/ppc64-undefined.s b/lld/test/ELF/ppc64-undefined.s new file mode 100644 index 0000000000000..c9c2a7564f95f --- /dev/null +++ b/lld/test/ELF/ppc64-undefined.s @@ -0,0 +1,11 @@ +# REQUIRES: ppc + +# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o +# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR + +# ERR: error: undefined symbol: undef + +.global _start +_start: + bl undef + nop diff --git a/lld/test/ELF/ppc64-weak-undef-call-shared.s b/lld/test/ELF/ppc64-weak-undef-call-shared.s deleted file mode 100644 index 244f72f995737..0000000000000 --- a/lld/test/ELF/ppc64-weak-undef-call-shared.s +++ /dev/null @@ -1,21 +0,0 @@ -# REQUIRES: ppc - -# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o -# RUN: ld.lld -shared %t.o -o %t.so -# RUN: llvm-readobj --symbols -r --dyn-syms %t.so | FileCheck %s - -# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o -# RUN: ld.lld -shared %t.o -o %t.so -# RUN: llvm-readobj --symbols -r --dyn-syms %t.so | FileCheck %s - -.section ".toc","aw" -.quad weakfunc -// CHECK-NOT: R_PPC64_RELATIVE - -.text -.Lfoo: - bl weakfunc - nop -// CHECK-NOT: R_PPC64_REL24 - -.weak weakfunc diff --git a/lld/test/ELF/ppc64-weak-undef-call.s b/lld/test/ELF/ppc64-weak-undef-call.s deleted file mode 100644 index 1f6869311708c..0000000000000 --- a/lld/test/ELF/ppc64-weak-undef-call.s +++ /dev/null @@ -1,29 +0,0 @@ -# REQUIRES: ppc - -# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t -# RUN: ld.lld %t -o %t2 -# RUN: llvm-objdump -d --no-show-raw-insn %t2 | FileCheck %s - -# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t -# RUN: ld.lld %t -o %t2 -# RUN: llvm-objdump -d --no-show-raw-insn %t2 | FileCheck %s - -# CHECK: Disassembly of section .text: -# CHECK-EMPTY: - -.text -.global _start -_start: - bl weakfunc - nop - blr - -.weak weakfunc - -# It does not really matter how we fixup the bl, if at all, because it needs to -# be unreachable. But, we should link successfully. We should not, however, -# generate a .plt entry (this would be wasted space). For now, we do nothing -# (leaving the zero relative offset present in the input). -# CHECK: 10010158: bl 0x10010158 -# CHECK: 1001015c: nop -# CHECK: 10010160: blr From fc2dbf90d12a4e34b6d06264ce2ff6b8b94aac8e Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 15 Feb 2022 16:12:08 -0500 Subject: [PATCH 124/316] [libc++] Mark test as unsupported with apple-clang This is to avoid spurious test failures in case apple-clang-14 doesn't support _BitInt. (cherry picked from commit 87b218b42b14e392aa0363a413d440b77bf04bd4) --- libcxx/test/libcxx/atomics/bit-int.verify.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/test/libcxx/atomics/bit-int.verify.cpp b/libcxx/test/libcxx/atomics/bit-int.verify.cpp index cf3cf97566606..fb080965740a3 100644 --- a/libcxx/test/libcxx/atomics/bit-int.verify.cpp +++ b/libcxx/test/libcxx/atomics/bit-int.verify.cpp @@ -12,7 +12,7 @@ // disable them for now until their behavior can be designed better later. // See https://reviews.llvm.org/D84049 for details. -// UNSUPPORTED: apple-clang-12, apple-clang-13 +// UNSUPPORTED: apple-clang-12, apple-clang-13, apple-clang-14 // UNSUPPORTED: clang-12, clang-13 // UNSUPPORTED: c++03 From b54c95790b8a410b8eab1cbaae306cdc56a8e82a Mon Sep 17 00:00:00 2001 From: Anastasia Stulova Date: Wed, 16 Feb 2022 11:09:32 +0000 Subject: [PATCH 125/316] [Docs] Release 14 notes for SPIR-V in clang. Differential Revision: https://reviews.llvm.org/D119713 --- clang/docs/ReleaseNotes.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 899165b842b58..edabf0d974cd9 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -47,6 +47,8 @@ sections with improvements to Clang's support for those languages. Major New Features ------------------ +- Added SPIR-V triple and binary generation using external ``llvm-spirv`` tool. + For more details refer to :ref:`the SPIR-V support section `. - ... Improvements to Clang's diagnostics @@ -324,6 +326,17 @@ Arm and AArch64 Support in Clang - The ``attribute((target("branch-protection=...)))`` attributes will now also work for the ARM backend. +SPIR-V Support in Clang +----------------------- + +- Added triple/target ``spirv32`` and ``spirv64`` for 32-bit and 64-bit SPIR-V + respectively. +- Added generation of binaries via external ``llvm-spirv`` tool. This can now + be used for HIP or OpenCL. +- Added linking of separate object files in SPIR-V format using external + ``spirv-link`` tool. + + Floating Point Support in Clang ------------------------------- - The default setting of FP contraction (FMA) is now -ffp-contract=on (for From e8712accba1150b94168d8ace6c7dd7b9612e174 Mon Sep 17 00:00:00 2001 From: Anastasia Stulova Date: Wed, 16 Feb 2022 11:29:58 +0000 Subject: [PATCH 126/316] [Docs][OpenCL] Release 14 notes. Differential Revision: https://reviews.llvm.org/D119710 --- clang/docs/ReleaseNotes.rst | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index edabf0d974cd9..869d62aebfb18 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -18,7 +18,7 @@ Written by the `LLVM Team `_ Introduction ============ -This document contains the release notes for the Clang C/C++/Objective-C +This document contains the release notes for the Clang C/C++/Objective-C/OpenCL frontend, part of the LLVM Compiler Infrastructure, release |release|. Here we describe the status of Clang in some detail, including major improvements from the previous release and new feature work. For the @@ -49,6 +49,8 @@ Major New Features - Added SPIR-V triple and binary generation using external ``llvm-spirv`` tool. For more details refer to :ref:`the SPIR-V support section `. +- Completed support of OpenCL C 3.0 and C++ for OpenCL 2021 at experimental + state. - ... Improvements to Clang's diagnostics @@ -262,10 +264,37 @@ CUDA Language Changes in Clang Objective-C Language Changes in Clang ------------------------------------- -OpenCL C Language Changes in Clang ----------------------------------- +OpenCL Kernel Language Changes in Clang +--------------------------------------- -... +OpenCL 3.0 is completed, but remains experimental: + +- Added parsing support for optionality of device-side enqueue and blocks. +- Added missing support for optionality of various builtin functions: + + - ``read_write`` images, pipes, collective workgroup in the default header. + - ``read_write`` images, named address space atomics in internal ``opencl-c.h`` + (enabled via ``-finclude-default-header`` frontend flag). + +C++ for OpenCL: + +- Added experimental support of C++ for OpenCL 2021 as per `the provisional + language documentation + `_. + Support of all optional features is aligned with OpenCL 3.0. +- Added ``__remove_address_space`` utility (documentation available in + :doc:`LanguageExtensions`). +- Fixed address space for temporaries (to be ``__private``). +- Disallowed static kernel functions. +- Fixed implicit definition of ``__cpp_threadsafe_static_init`` macro. + +Misc changes: + +- Added generation of SPIR-V binaries via external ``llvm-spirv`` tool. + For more details refer to :ref:`the SPIR-V support section `. +- Added new extensions for ``atomic_half`` and ``cl_ext_float_atomics``. +- Fixed/improved support of ``vload``/``vstore``. +- Fixed incorrect ``as_type`` support for 3-element vector types. ABI Changes in Clang -------------------- From 5264342c242b0d0c1ad664104cb371dc9a659d59 Mon Sep 17 00:00:00 2001 From: Anastasia Stulova Date: Wed, 16 Feb 2022 12:05:55 +0000 Subject: [PATCH 127/316] [Docs][OpenCL] Update OpenCL 3.0 status in docs. Reflect the latest achievements in clang docs. Differential Revision: https://reviews.llvm.org/D119719 --- clang/docs/OpenCLSupport.rst | 78 ++++++++++++++++++------------------ clang/docs/UsersManual.rst | 5 +-- 2 files changed, 41 insertions(+), 42 deletions(-) diff --git a/clang/docs/OpenCLSupport.rst b/clang/docs/OpenCLSupport.rst index c1202601d48d3..723e186cb66dc 100644 --- a/clang/docs/OpenCLSupport.rst +++ b/clang/docs/OpenCLSupport.rst @@ -17,8 +17,8 @@ OpenCL Support ================== -Clang has complete support of OpenCL C versions from 1.0 to 2.0. -There is an ongoing work to support :ref:`OpenCL 3.0 `. +Clang has complete support of OpenCL C versions from 1.0 to 3.0. +Support for OpenCL 3.0 is in experimental phase (:ref:`OpenCL 3.0 `). Clang also supports :ref:`the C++ for OpenCL kernel language `. @@ -371,43 +371,43 @@ OpenCL C 3.0 Implementation Status The following table provides an overview of features in OpenCL C 3.0 and their implementation status. -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Category | Feature | Status | Reviews | -+==============================+=========================+=========================================+======================+==============================================================================================+ -| Command line interface | New value for ``-cl-std`` flag | :good:`done` | https://reviews.llvm.org/D88300 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Predefined macros | New version macro | :good:`done` | https://reviews.llvm.org/D88300 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Predefined macros | Feature macros | :good:`done` | https://reviews.llvm.org/D95776 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Generic address space | :good:`done` | https://reviews.llvm.org/D95778 and https://reviews.llvm.org/D103401 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Builtin function overloads with generic address space | :good:`done` | https://reviews.llvm.org/D105526 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Program scope variables in global memory | :good:`done` | https://reviews.llvm.org/D103191 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | 3D image writes including builtin functions | :part:`worked on` | https://reviews.llvm.org/D106260 (frontend) | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | read_write images including builtin functions | :part:`worked on` | https://reviews.llvm.org/D104915 (frontend) and https://reviews.llvm.org/D107539 (functions) | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | C11 atomics memory scopes, ordering and builtin function | :good:`done` | https://reviews.llvm.org/D106111 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Blocks and Device-side kernel enqueue including builtin functions | :none:`unclaimed` | | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Pipes including builtin functions | :good:`done` | https://reviews.llvm.org/D107154 (frontend) and https://reviews.llvm.org/D105858 (functions) | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Work group collective builtin functions | :good:`done` | https://reviews.llvm.org/D105858 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Image types and builtin functions | :good:`done` | https://reviews.llvm.org/D103911 (frontend) and https://reviews.llvm.org/D107539 (functions) | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| Feature optionality | Double precision floating point type | :good:`done` | https://reviews.llvm.org/D96524 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| New functionality | RGBA vector components | :good:`done` | https://reviews.llvm.org/D99969 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| New functionality | Subgroup functions | :part:`worked on` | https://reviews.llvm.org/D105858 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ -| New functionality | Atomic mem scopes: subgroup, all devices including functions | :part:`worked on` | https://reviews.llvm.org/D103241 | -+------------------------------+-------------------------+-----------------------------------------+----------------------+----------------------------------------------------------------------------------------------+ ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Category | Feature | Status | Reviews | ++==============================+=========================+=========================================+======================+================================================================================================================================+ +| Command line interface | New value for ``-cl-std`` flag | :good:`done` | https://reviews.llvm.org/D88300 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Predefined macros | New version macro | :good:`done` | https://reviews.llvm.org/D88300 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Predefined macros | Feature macros | :good:`done` | https://reviews.llvm.org/D95776 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Generic address space | :good:`done` | https://reviews.llvm.org/D95778 and https://reviews.llvm.org/D103401 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Builtin function overloads with generic address space | :good:`done` | https://reviews.llvm.org/D105526, https://reviews.llvm.org/D107769 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Program scope variables in global memory | :good:`done` | https://reviews.llvm.org/D103191 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | 3D image writes including builtin functions | :good:`done` | https://reviews.llvm.org/D106260 (frontend) | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | read_write images including builtin functions | :good:`done` | https://reviews.llvm.org/D104915 (frontend) and https://reviews.llvm.org/D107539, https://reviews.llvm.org/D117899 (functions) | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | C11 atomics memory scopes, ordering and builtin function | :good:`done` | https://reviews.llvm.org/D106111, https://reviews.llvm.org/D119420 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Blocks and Device-side kernel enqueue including builtin functions | :good:`done` | https://reviews.llvm.org/D115640, https://reviews.llvm.org/D118605 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Pipes including builtin functions | :good:`done` | https://reviews.llvm.org/D107154 (frontend) and https://reviews.llvm.org/D105858 (functions) | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Work group collective builtin functions | :good:`done` | https://reviews.llvm.org/D105858 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Image types and builtin functions | :good:`done` | https://reviews.llvm.org/D103911 (frontend) and https://reviews.llvm.org/D107539 (functions) | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| Feature optionality | Double precision floating point type | :good:`done` | https://reviews.llvm.org/D96524 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| New functionality | RGBA vector components | :good:`done` | https://reviews.llvm.org/D99969 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| New functionality | Subgroup functions | :good:`done` | https://reviews.llvm.org/D105858, https://reviews.llvm.org/D118999 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ +| New functionality | Atomic mem scopes: subgroup, all devices including functions | :good:`done` | https://reviews.llvm.org/D103241 | ++------------------------------+-------------------------+-----------------------------------------+----------------------+--------------------------------------------------------------------------------------------------------------------------------+ .. _opencl_experimenal: diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 1df96296cb8ac..981909aa16eaf 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -3060,9 +3060,8 @@ profile. Starting from clang 9 a C++ mode is available for OpenCL (see :ref:`C++ for OpenCL `). -There is ongoing support for OpenCL v3.0 that is documented along with other -experimental functionality and features in development on :doc:`OpenCLSupport` -page. +OpenCL v3.0 support is complete but it remains in experimental state, see more +details about the experimental features in :doc:`OpenCLSupport` page. OpenCL Specific Options ----------------------- From 9e1f13d14e1975f19fa9823347184a6007ef95c7 Mon Sep 17 00:00:00 2001 From: Jez Ng Date: Wed, 16 Feb 2022 08:29:11 -0500 Subject: [PATCH 128/316] [lld] Fix RST formatting in release notes --- lld/docs/ReleaseNotes.rst | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index 3601a968bd77b..d928b04d8dc04 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -40,7 +40,7 @@ ELF Improvements ``--warn-backrefs``. One may build such an archive with ``llvm-ar rcS [--thin]`` to save space. (`D117284 `_) - The archive index may be `entirely ignored ` + The archive index may be `entirely ignored `_ in a future release. * No longer deduplicate local symbol names at the default optimization level of ``-O1``. This results in a larger ``.strtab`` (usually less than 1%) but a faster link @@ -133,9 +133,9 @@ Mach-O Improvements (`D115949 `_) * Thunk insertion now works more reliably. (`D108897 `_, - `D108924 `_, - `D109079 `_, - `D116705 `_) + `D108924 `_, + `D109079 `_, + `D116705 `_) * ``-ObjC`` now loads archive members before the symbol resolution phase. (`D108781 `_) * ``-oso_prefix`` is now supported. @@ -150,13 +150,13 @@ Mach-O Improvements a lot of framework flags and library lookups. Large Swift-based projects will benefit significantly. (`D113073 `_, - `D113063 `_, - `D113153 `_, - `D113235 `_) + `D113063 `_, + `D113153 `_, + `D113235 `_) * Several memory-reduction optimizations were done to reduce LLD's RSS footprint. (`D113813 `_, - `D113818 `_) + `D113818 `_) * Symbol patterns from ``-[un]exported_symbols_list`` are now processed in parallel. (`D113820 `_) * ``.weak_def_can_be_hidden`` symbols can now be exported. @@ -188,11 +188,11 @@ Mach-O Improvements * Map file output now proceeds in parallel with output of the binary. (`D117069 `_) * The map file now contains dead-stripped symbols too. - (`D114737 `_) + (`D114737 `_) * Multiple TLV sections with different alignments are now handled properly. (`D116263 `_) * ``--start-lib`` and ``--end-lib`` are now supported. - (`D116913 `_) + (`D116913 `_) * ``-noall_load`` is now supported. (`D117629 `_) * ``-add_empty_section`` is now supported. From 89309e187631e6648bc5c45846470f6fd2b2395f Mon Sep 17 00:00:00 2001 From: Jez Ng Date: Wed, 16 Feb 2022 08:33:23 -0500 Subject: [PATCH 129/316] [lld] One more formatting fix for the release notes --- lld/docs/ReleaseNotes.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index d928b04d8dc04..672759fdf6b38 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -174,7 +174,7 @@ Mach-O Improvements (`D115092 `_) * ``$ld$hide`` symbols are now supported. (`D115775 `_) -* Symbols imported via `-weak_framework` are now properly marked as weak refs. +* Symbols imported via ``-weak_framework`` are now properly marked as weak refs. (`D114397 `_) * ``--warn-dylib-install-name`` and ``--no-warn-dylib-install-name`` were added to toggle LLD-specific warnings around the use of ``-install_name``. From 8b10e0a840473b74d5d2f1343e317653d297781a Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 15 Feb 2022 08:18:38 -0500 Subject: [PATCH 130/316] [runtimes] Deprecate FOO_SYSROOT & friends As suggested in https://reviews.llvm.org/D112155. Differential Revision: https://reviews.llvm.org/D119836 (cherry picked from commit 641a141da1f22de319e891bdfd61e614632b39f0) --- libcxx/CMakeLists.txt | 10 ++++++++++ libcxxabi/CMakeLists.txt | 10 ++++++++++ libunwind/CMakeLists.txt | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 6cd36ecfa7224..9c2e026f54010 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -282,6 +282,16 @@ set(LIBCXX_TARGET_TRIPLE "${LIBCXX_DEFAULT_TARGET_TRIPLE}" CACHE STRING "Use alt set(LIBCXX_SYSROOT "${CMAKE_SYSROOT}" CACHE STRING "Use alternate sysroot.") set(LIBCXX_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE STRING "Use alternate GCC toolchain.") +if(NOT CMAKE_SYSROOT AND LIBCXX_SYSROOT) + message(WARNING "LIBCXX_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") +endif() +if(NOT CMAKE_CXX_COMPILER_TARGET AND LIBCXX_TARGET_TRIPLE) + message(WARNING "LIBCXX_TARGET_TRIPLE is deprecated, please use CMAKE_CXX_COMPILER_TARGET instead") +endif() +if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBCXX_GCC_TOOLCHAIN) + message(WARNING "LIBCXX_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") +endif() + # Feature options ------------------------------------------------------------- option(LIBCXX_ENABLE_EXCEPTIONS "Use exceptions." ON) option(LIBCXX_ENABLE_RTTI "Use run time type information." ON) diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt index 58c21059c6025..77fcb5d22eb67 100644 --- a/libcxxabi/CMakeLists.txt +++ b/libcxxabi/CMakeLists.txt @@ -131,6 +131,16 @@ set(LIBCXXABI_TARGET_TRIPLE "${LIBCXXABI_DEFAULT_TARGET_TRIPLE}" CACHE STRING "T set(LIBCXXABI_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE PATH "GCC toolchain for cross compiling.") set(LIBCXXABI_SYSROOT "${CMAKE_SYSROOT}" CACHE PATH "Sysroot for cross compiling.") +if(NOT CMAKE_SYSROOT AND LIBCXXABI_SYSROOT) + message(WARNING "LIBCXXABI_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") +endif() +if(NOT CMAKE_CXX_COMPILER_TARGET AND LIBCXXABI_TARGET_TRIPLE) + message(WARNING "LIBCXXABI_TARGET_TRIPLE is deprecated, please use CMAKE_CXX_COMPILER_TARGET instead") +endif() +if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBCXXABI_GCC_TOOLCHAIN) + message(WARNING "LIBCXXABI_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") +endif() + set(LIBCXXABI_LIBCXX_LIBRARY_PATH "" CACHE PATH "The path to libc++ library.") set(LIBCXXABI_LIBRARY_VERSION "1.0" CACHE STRING "Version of libc++abi. This will be reflected in the name of the shared \ diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index 87d51b7894459..a50aa4669304a 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -109,6 +109,16 @@ set(LIBUNWIND_TEST_LINKER_FLAGS "" CACHE STRING set(LIBUNWIND_TEST_COMPILER_FLAGS "" CACHE STRING "Additional compiler flags for test programs.") +if(NOT CMAKE_SYSROOT AND LIBUNWIND_SYSROOT) + message(WARNING "LIBUNWIND_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") +endif() +if(NOT CMAKE_CXX_COMPILER_TARGET AND LIBUNWIND_TARGET_TRIPLE) + message(WARNING "LIBUNWIND_TARGET_TRIPLE is deprecated, please use CMAKE_CXX_COMPILER_TARGET instead") +endif() +if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBUNWIND_GCC_TOOLCHAIN) + message(WARNING "LIBUNWIND_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") +endif() + if (LIBUNWIND_ENABLE_SHARED) set(LIBUNWIND_DEFAULT_TEST_CONFIG "llvm-libunwind-shared.cfg.in") else() From c561bf0daa95797c36163ff730f570ed15e82632 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 16 Feb 2022 09:46:04 -0500 Subject: [PATCH 131/316] [runtimes] Add release note for deprecation of FOO_SYSROOT & friends --- libcxx/docs/ReleaseNotes.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index a9dd06e9490d2..b7e07d17755a0 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -235,3 +235,8 @@ Build System Changes ``-DCMAKE_POSITION_INDEPENDENT_CODE=ON`` explicitly when configuring the build, or ``-DRUNTIMES__CMAKE_POSITION_INDEPENDENT_CODE=ON`` if using the bootstrapping build. + +- The ``{LIBCXX,LIBCXXABI,LIBUNWIND}_TARGET_TRIPLE``, ``{LIBCXX,LIBCXXABI,LIBUNWIND}_SYSROOT`` and + ``{LIBCXX,LIBCXXABI,LIBUNWIND}_GCC_TOOLCHAIN`` CMake variables are deprecated. Instead, please use + the ``CMAKE_CXX_COMPILER_TARGET``, ``CMAKE_SYSROOT`` and ``CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN`` + variables provided by CMake. From 812894f74a8ad7bc448218cdeff4789fbad376e7 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 16 Feb 2022 11:59:32 -0500 Subject: [PATCH 132/316] [runtimes] Move warning messages for FOO_SYSROOT & friends above their default value Otherwise, the warnings always trigger. (cherry picked from commit 2e3bb910e3f7f5cc92e7c5c8acc7e6e7328afcce) --- libcxx/CMakeLists.txt | 18 +++++++++--------- libcxxabi/CMakeLists.txt | 18 +++++++++--------- libunwind/CMakeLists.txt | 20 ++++++++++---------- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 9c2e026f54010..35c2ce515dd19 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -273,15 +273,6 @@ if (LIBCXX_BUILD_32_BITS) message(FATAL_ERROR "LIBCXX_BUILD_32_BITS is not supported anymore when building the runtimes, please specify a full triple instead.") endif() -if(CMAKE_CXX_COMPILER_TARGET) - set(LIBCXX_DEFAULT_TARGET_TRIPLE "${CMAKE_CXX_COMPILER_TARGET}") -else() - set(LIBCXX_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") -endif() -set(LIBCXX_TARGET_TRIPLE "${LIBCXX_DEFAULT_TARGET_TRIPLE}" CACHE STRING "Use alternate target triple.") -set(LIBCXX_SYSROOT "${CMAKE_SYSROOT}" CACHE STRING "Use alternate sysroot.") -set(LIBCXX_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE STRING "Use alternate GCC toolchain.") - if(NOT CMAKE_SYSROOT AND LIBCXX_SYSROOT) message(WARNING "LIBCXX_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") endif() @@ -292,6 +283,15 @@ if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBCXX_GCC_TOOLCHAIN) message(WARNING "LIBCXX_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") endif() +if(CMAKE_CXX_COMPILER_TARGET) + set(LIBCXX_DEFAULT_TARGET_TRIPLE "${CMAKE_CXX_COMPILER_TARGET}") +else() + set(LIBCXX_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") +endif() +set(LIBCXX_TARGET_TRIPLE "${LIBCXX_DEFAULT_TARGET_TRIPLE}" CACHE STRING "Use alternate target triple.") +set(LIBCXX_SYSROOT "${CMAKE_SYSROOT}" CACHE STRING "Use alternate sysroot.") +set(LIBCXX_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE STRING "Use alternate GCC toolchain.") + # Feature options ------------------------------------------------------------- option(LIBCXX_ENABLE_EXCEPTIONS "Use exceptions." ON) option(LIBCXX_ENABLE_RTTI "Use run time type information." ON) diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt index 77fcb5d22eb67..8e8cdf8ad737b 100644 --- a/libcxxabi/CMakeLists.txt +++ b/libcxxabi/CMakeLists.txt @@ -122,15 +122,6 @@ set(LIBCXXABI_LIBDIR_SUFFIX "${LLVM_LIBDIR_SUFFIX}" CACHE STRING "Define suffix of library directory name (32/64)") option(LIBCXXABI_INSTALL_LIBRARY "Install the libc++abi library." ON) -if(CMAKE_CXX_COMPILER_TARGET) - set(LIBCXXABI_DEFAULT_TARGET_TRIPLE "${CMAKE_CXX_COMPILER_TARGET}") -else() - set(LIBCXXABI_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") -endif() -set(LIBCXXABI_TARGET_TRIPLE "${LIBCXXABI_DEFAULT_TARGET_TRIPLE}" CACHE STRING "Target triple for cross compiling.") -set(LIBCXXABI_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE PATH "GCC toolchain for cross compiling.") -set(LIBCXXABI_SYSROOT "${CMAKE_SYSROOT}" CACHE PATH "Sysroot for cross compiling.") - if(NOT CMAKE_SYSROOT AND LIBCXXABI_SYSROOT) message(WARNING "LIBCXXABI_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") endif() @@ -141,6 +132,15 @@ if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBCXXABI_GCC_TOOLCHAIN) message(WARNING "LIBCXXABI_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") endif() +if(CMAKE_CXX_COMPILER_TARGET) + set(LIBCXXABI_DEFAULT_TARGET_TRIPLE "${CMAKE_CXX_COMPILER_TARGET}") +else() + set(LIBCXXABI_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}") +endif() +set(LIBCXXABI_TARGET_TRIPLE "${LIBCXXABI_DEFAULT_TARGET_TRIPLE}" CACHE STRING "Target triple for cross compiling.") +set(LIBCXXABI_GCC_TOOLCHAIN "${CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN}" CACHE PATH "GCC toolchain for cross compiling.") +set(LIBCXXABI_SYSROOT "${CMAKE_SYSROOT}" CACHE PATH "Sysroot for cross compiling.") + set(LIBCXXABI_LIBCXX_LIBRARY_PATH "" CACHE PATH "The path to libc++ library.") set(LIBCXXABI_LIBRARY_VERSION "1.0" CACHE STRING "Version of libc++abi. This will be reflected in the name of the shared \ diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index a50aa4669304a..6523fb0d307df 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -87,6 +87,16 @@ option(LIBUNWIND_USE_FRAME_HEADER_CACHE "Cache frame headers for unwinding. Requ option(LIBUNWIND_REMEMBER_HEAP_ALLOC "Use heap instead of the stack for .cfi_remember_state." OFF) option(LIBUNWIND_INSTALL_HEADERS "Install the libunwind headers." OFF) +if(NOT CMAKE_SYSROOT AND LIBUNWIND_SYSROOT) + message(WARNING "LIBUNWIND_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") +endif() +if(NOT CMAKE_CXX_COMPILER_TARGET AND LIBUNWIND_TARGET_TRIPLE) + message(WARNING "LIBUNWIND_TARGET_TRIPLE is deprecated, please use CMAKE_CXX_COMPILER_TARGET instead") +endif() +if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBUNWIND_GCC_TOOLCHAIN) + message(WARNING "LIBUNWIND_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") +endif() + set(LIBUNWIND_LIBDIR_SUFFIX "${LLVM_LIBDIR_SUFFIX}" CACHE STRING "Define suffix of library directory name (32/64)") option(LIBUNWIND_INSTALL_LIBRARY "Install the libunwind library." ON) @@ -109,16 +119,6 @@ set(LIBUNWIND_TEST_LINKER_FLAGS "" CACHE STRING set(LIBUNWIND_TEST_COMPILER_FLAGS "" CACHE STRING "Additional compiler flags for test programs.") -if(NOT CMAKE_SYSROOT AND LIBUNWIND_SYSROOT) - message(WARNING "LIBUNWIND_SYSROOT is deprecated, please use CMAKE_SYSROOT instead") -endif() -if(NOT CMAKE_CXX_COMPILER_TARGET AND LIBUNWIND_TARGET_TRIPLE) - message(WARNING "LIBUNWIND_TARGET_TRIPLE is deprecated, please use CMAKE_CXX_COMPILER_TARGET instead") -endif() -if(NOT CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN AND LIBUNWIND_GCC_TOOLCHAIN) - message(WARNING "LIBUNWIND_GCC_TOOLCHAIN is deprecated, please use CMAKE_CXX_COMPILER_EXTERNAL_TOOLCHAIN instead") -endif() - if (LIBUNWIND_ENABLE_SHARED) set(LIBUNWIND_DEFAULT_TEST_CONFIG "llvm-libunwind-shared.cfg.in") else() From 6311bae1b42429729e0a03f84fc4dc4d5683686a Mon Sep 17 00:00:00 2001 From: "Luo, Yuanke" Date: Mon, 7 Feb 2022 15:58:45 +0800 Subject: [PATCH 133/316] [X86] Add test cases for fmul/fdiv with select. (cherry picked from commit 24562babdf16093052230e91332f1b1f13e2c4de) --- llvm/test/CodeGen/X86/vector-bo-select.ll | 282 ++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 93777915b1b88..63d5031e6166f 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -779,3 +779,285 @@ define <8 x double> @fsub_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> n %r = fsub <8 x double> %x, %s ret <8 x double> %r } + +define <8 x float> @fmul_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> noundef %x, <8 x float> noundef %y) { +; AVX2-LABEL: fmul_v8f32_cast_cond: +; AVX2: # %bb.0: +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $5, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: movl %edi, %ecx +; AVX2-NEXT: shrb $4, %cl +; AVX2-NEXT: movzbl %cl, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: negl %ecx +; AVX2-NEXT: vmovd %ecx, %xmm2 +; AVX2-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $6, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $7, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vmovd %eax, %xmm3 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $2, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 +; AVX2-NEXT: shrb $3, %dil +; AVX2-NEXT: movzbl %dil, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $3, %eax, %xmm3, %xmm3 +; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX2-NEXT: vblendvps %ymm2, %ymm1, %ymm3, %ymm1 +; AVX2-NEXT: vmulps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512F-LABEL: fmul_v8f32_cast_cond: +; AVX512F: # %bb.0: +; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512F-NEXT: kmovw %edi, %k1 +; AVX512F-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512F-NEXT: vmovaps %zmm1, %zmm2 {%k1} +; AVX512F-NEXT: vmulps %ymm2, %ymm0, %ymm0 +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: fmul_v8f32_cast_cond: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: kmovw %edi, %k1 +; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512VL-NEXT: vmovaps %ymm1, %ymm2 {%k1} +; AVX512VL-NEXT: vmulps %ymm2, %ymm0, %ymm0 +; AVX512VL-NEXT: retq + %b = bitcast i8 %pb to <8 x i1> + %s = select <8 x i1> %b, <8 x float> %y, <8 x float> + %r = fmul <8 x float> %x, %s + ret <8 x float> %r +} + +define <8 x double> @fmul_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> noundef %x, <8 x double> noundef %y) { +; AVX2-LABEL: fmul_v8f64_cast_cond: +; AVX2: # %bb.0: +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: movl %edi, %ecx +; AVX2-NEXT: andb $1, %cl +; AVX2-NEXT: movzbl %cl, %ecx +; AVX2-NEXT: vmovd %ecx, %xmm4 +; AVX2-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $2, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $3, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $4, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $8, %eax, %xmm4, %xmm5 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $5, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $10, %eax, %xmm5, %xmm5 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $6, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $12, %eax, %xmm5, %xmm5 +; AVX2-NEXT: shrb $7, %dil +; AVX2-NEXT: movzbl %dil, %eax +; AVX2-NEXT: vpinsrb $14, %eax, %xmm5, %xmm5 +; AVX2-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm5[4,4,5,5,6,6,7,7] +; AVX2-NEXT: vpslld $31, %xmm5, %xmm5 +; AVX2-NEXT: vpmovsxdq %xmm5, %ymm5 +; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm6 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX2-NEXT: vblendvpd %ymm5, %ymm3, %ymm6, %ymm3 +; AVX2-NEXT: vpmovzxwd {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero +; AVX2-NEXT: vpslld $31, %xmm4, %xmm4 +; AVX2-NEXT: vpmovsxdq %xmm4, %ymm4 +; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm6, %ymm2 +; AVX2-NEXT: vmulpd %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vmulpd %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX512-LABEL: fmul_v8f64_cast_cond: +; AVX512: # %bb.0: +; AVX512-NEXT: kmovw %edi, %k1 +; AVX512-NEXT: vbroadcastsd {{.*#+}} zmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1} +; AVX512-NEXT: vmulpd %zmm2, %zmm0, %zmm0 +; AVX512-NEXT: retq + %b = bitcast i8 %pb to <8 x i1> + %s = select <8 x i1> %b, <8 x double> %y, <8 x double> + %r = fmul <8 x double> %x, %s + ret <8 x double> %r +} + +define <8 x float> @fdiv_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> noundef %x, <8 x float> noundef %y) { +; AVX2-LABEL: fdiv_v8f32_cast_cond: +; AVX2: # %bb.0: +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $5, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: movl %edi, %ecx +; AVX2-NEXT: shrb $4, %cl +; AVX2-NEXT: movzbl %cl, %ecx +; AVX2-NEXT: andl $1, %ecx +; AVX2-NEXT: negl %ecx +; AVX2-NEXT: vmovd %ecx, %xmm2 +; AVX2-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $6, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $7, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $3, %eax, %xmm2, %xmm2 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vmovd %eax, %xmm3 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $2, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 +; AVX2-NEXT: shrb $3, %dil +; AVX2-NEXT: movzbl %dil, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: negl %eax +; AVX2-NEXT: vpinsrd $3, %eax, %xmm3, %xmm3 +; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX2-NEXT: vblendvps %ymm2, %ymm1, %ymm3, %ymm1 +; AVX2-NEXT: vdivps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512F-LABEL: fdiv_v8f32_cast_cond: +; AVX512F: # %bb.0: +; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512F-NEXT: kmovw %edi, %k1 +; AVX512F-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512F-NEXT: vmovaps %zmm1, %zmm2 {%k1} +; AVX512F-NEXT: vdivps %ymm2, %ymm0, %ymm0 +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: fdiv_v8f32_cast_cond: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: kmovw %edi, %k1 +; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512VL-NEXT: vmovaps %ymm1, %ymm2 {%k1} +; AVX512VL-NEXT: vdivps %ymm2, %ymm0, %ymm0 +; AVX512VL-NEXT: retq + %b = bitcast i8 %pb to <8 x i1> + %s = select <8 x i1> %b, <8 x float> %y, <8 x float> + %r = fdiv <8 x float> %x, %s + ret <8 x float> %r +} + +define <8 x double> @fdiv_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> noundef %x, <8 x double> noundef %y) { +; AVX2-LABEL: fdiv_v8f64_cast_cond: +; AVX2: # %bb.0: +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: movl %edi, %ecx +; AVX2-NEXT: andb $1, %cl +; AVX2-NEXT: movzbl %cl, %ecx +; AVX2-NEXT: vmovd %ecx, %xmm4 +; AVX2-NEXT: vpinsrb $2, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $2, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $4, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $3, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $6, %eax, %xmm4, %xmm4 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $4, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $8, %eax, %xmm4, %xmm5 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $5, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $10, %eax, %xmm5, %xmm5 +; AVX2-NEXT: movl %edi, %eax +; AVX2-NEXT: shrb $6, %al +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movzbl %al, %eax +; AVX2-NEXT: vpinsrb $12, %eax, %xmm5, %xmm5 +; AVX2-NEXT: shrb $7, %dil +; AVX2-NEXT: movzbl %dil, %eax +; AVX2-NEXT: vpinsrb $14, %eax, %xmm5, %xmm5 +; AVX2-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm5[4,4,5,5,6,6,7,7] +; AVX2-NEXT: vpslld $31, %xmm5, %xmm5 +; AVX2-NEXT: vpmovsxdq %xmm5, %ymm5 +; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm6 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX2-NEXT: vblendvpd %ymm5, %ymm3, %ymm6, %ymm3 +; AVX2-NEXT: vpmovzxwd {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero +; AVX2-NEXT: vpslld $31, %xmm4, %xmm4 +; AVX2-NEXT: vpmovsxdq %xmm4, %ymm4 +; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm6, %ymm2 +; AVX2-NEXT: vdivpd %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vdivpd %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX512-LABEL: fdiv_v8f64_cast_cond: +; AVX512: # %bb.0: +; AVX512-NEXT: kmovw %edi, %k1 +; AVX512-NEXT: vbroadcastsd {{.*#+}} zmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1} +; AVX512-NEXT: vdivpd %zmm2, %zmm0, %zmm0 +; AVX512-NEXT: retq + %b = bitcast i8 %pb to <8 x i1> + %s = select <8 x i1> %b, <8 x double> %y, <8 x double> + %r = fdiv <8 x double> %x, %s + ret <8 x double> %r +} From b0ae8076cf4cf4d9c14af24567a524b8c570349a Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Tue, 8 Feb 2022 10:41:34 -0500 Subject: [PATCH 134/316] [SDAG] enable binop identity constant folds for fmul/fdiv The test diffs are identical to D119111. This only affects x86 currently because no other target has an override for the TLI hook that controls this transform. (cherry picked from commit 905abc5b7db27fa26f49f668b47a57b462be24c9) --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++ llvm/test/CodeGen/X86/vector-bo-select.ll | 39 +++++++------------ 2 files changed, 17 insertions(+), 25 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6a36b7862ce95..ec297579090ef 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2134,6 +2134,9 @@ static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG, return C->isZero() && C->isNegative(); case ISD::FSUB: // X - 0.0 --> X return C->isZero() && !C->isNegative(); + case ISD::FMUL: // X * 1.0 --> X + case ISD::FDIV: // X / 1.0 --> X + return C->isExactlyValue(1.0); } } return false; diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 63d5031e6166f..74549f95a2625 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -279,9 +279,8 @@ define <4 x float> @fmul_v4f32(<4 x i1> %b, <4 x float> noundef %x, <4 x float> ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512VL-NEXT: vmovaps %xmm2, %xmm0 {%k1} -; AVX512VL-NEXT: vmulps %xmm0, %xmm1, %xmm0 +; AVX512VL-NEXT: vmulps %xmm2, %xmm1, %xmm1 {%k1} +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 ; AVX512VL-NEXT: retq %s = select <4 x i1> %b, <4 x float> %y, <4 x float> %r = fmul <4 x float> %x, %s @@ -314,9 +313,8 @@ define <8 x float> @fmul_v8f32_commute(<8 x i1> %b, <8 x float> noundef %x, <8 x ; AVX512VL-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512VL-NEXT: vpslld $31, %ymm0, %ymm0 ; AVX512VL-NEXT: vptestmd %ymm0, %ymm0, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512VL-NEXT: vmovaps %ymm2, %ymm0 {%k1} -; AVX512VL-NEXT: vmulps %ymm1, %ymm0, %ymm0 +; AVX512VL-NEXT: vmulps %ymm2, %ymm1, %ymm1 {%k1} +; AVX512VL-NEXT: vmovaps %ymm1, %ymm0 ; AVX512VL-NEXT: retq %s = select <8 x i1> %b, <8 x float> %y, <8 x float> %r = fmul <8 x float> %s, %x @@ -344,8 +342,8 @@ define <16 x float> @fmul_v16f32_swap(<16 x i1> %b, <16 x float> noundef %x, <16 ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vbroadcastss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2 {%k1} ; AVX512-NEXT: vmulps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> , <16 x float> %y %r = fmul <16 x float> %x, %s @@ -373,8 +371,8 @@ define <16 x float> @fmul_v16f32_commute_swap(<16 x i1> %b, <16 x float> noundef ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vbroadcastss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2 {%k1} -; AVX512-NEXT: vmulps %zmm1, %zmm2, %zmm0 +; AVX512-NEXT: vmulps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> , <16 x float> %y %r = fmul <16 x float> %s, %x @@ -405,9 +403,8 @@ define <4 x float> @fdiv_v4f32(<4 x i1> %b, <4 x float> noundef %x, <4 x float> ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512VL-NEXT: vmovaps %xmm2, %xmm0 {%k1} -; AVX512VL-NEXT: vdivps %xmm0, %xmm1, %xmm0 +; AVX512VL-NEXT: vdivps %xmm2, %xmm1, %xmm1 {%k1} +; AVX512VL-NEXT: vmovaps %xmm1, %xmm0 ; AVX512VL-NEXT: retq %s = select <4 x i1> %b, <4 x float> %y, <4 x float> %r = fdiv <4 x float> %x, %s @@ -470,8 +467,8 @@ define <16 x float> @fdiv_v16f32_swap(<16 x i1> %b, <16 x float> noundef %x, <16 ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1 -; AVX512-NEXT: vbroadcastss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2 {%k1} ; AVX512-NEXT: vdivps %zmm2, %zmm1, %zmm0 +; AVX512-NEXT: vmovaps %zmm1, %zmm0 {%k1} ; AVX512-NEXT: retq %s = select <16 x i1> %b, <16 x float> , <16 x float> %y %r = fdiv <16 x float> %x, %s @@ -845,9 +842,7 @@ define <8 x float> @fmul_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> nou ; AVX512VL-LABEL: fmul_v8f32_cast_cond: ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: kmovw %edi, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512VL-NEXT: vmovaps %ymm1, %ymm2 {%k1} -; AVX512VL-NEXT: vmulps %ymm2, %ymm0, %ymm0 +; AVX512VL-NEXT: vmulps %ymm1, %ymm0, %ymm0 {%k1} ; AVX512VL-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x float> %y, <8 x float> @@ -911,9 +906,7 @@ define <8 x double> @fmul_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> n ; AVX512-LABEL: fmul_v8f64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vbroadcastsd {{.*#+}} zmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1} -; AVX512-NEXT: vmulpd %zmm2, %zmm0, %zmm0 +; AVX512-NEXT: vmulpd %zmm1, %zmm0, %zmm0 {%k1} ; AVX512-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x double> %y, <8 x double> @@ -986,9 +979,7 @@ define <8 x float> @fdiv_v8f32_cast_cond(i8 noundef zeroext %pb, <8 x float> nou ; AVX512VL-LABEL: fdiv_v8f32_cast_cond: ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: kmovw %edi, %k1 -; AVX512VL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512VL-NEXT: vmovaps %ymm1, %ymm2 {%k1} -; AVX512VL-NEXT: vdivps %ymm2, %ymm0, %ymm0 +; AVX512VL-NEXT: vdivps %ymm1, %ymm0, %ymm0 {%k1} ; AVX512VL-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x float> %y, <8 x float> @@ -1052,9 +1043,7 @@ define <8 x double> @fdiv_v8f64_cast_cond(i8 noundef zeroext %pb, <8 x double> n ; AVX512-LABEL: fdiv_v8f64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vbroadcastsd {{.*#+}} zmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] -; AVX512-NEXT: vmovapd %zmm1, %zmm2 {%k1} -; AVX512-NEXT: vdivpd %zmm2, %zmm0, %zmm0 +; AVX512-NEXT: vdivpd %zmm1, %zmm0, %zmm0 {%k1} ; AVX512-NEXT: retq %b = bitcast i8 %pb to <8 x i1> %s = select <8 x i1> %b, <8 x double> %y, <8 x double> From ecdd25c8651145916f52bf84d094fe94db1a3686 Mon Sep 17 00:00:00 2001 From: Daniel Thornburgh Date: Tue, 25 Jan 2022 22:23:38 +0000 Subject: [PATCH 135/316] [Debuginfod] [Symbolizer] Break debuginfod out of libLLVM. Debuginfod can pull in libcurl as a dependency, which isn't appropriate for libLLVM. (See https://gitlab.freedesktop.org/mesa/mesa/-/issues/5732). This change breaks out debuginfod into a separate non-component library that can be used directly in llvm-symbolizer. The tool can inject debuginfod into the Symbolizer library via an abstract DebugInfoFetcher interface, breaking the dependency of Symbolizer on debuinfod. See https://github.com/llvm/llvm-project/issues/52731 Reviewed By: phosek Differential Revision: https://reviews.llvm.org/D118413 --- .../llvm/DebugInfo/Symbolize/DIFetcher.h | 51 ++++++ .../llvm/DebugInfo/Symbolize/Symbolize.h | 13 ++ llvm/include/llvm/Debuginfod/DIFetcher.h | 34 ++++ llvm/lib/DebugInfo/Symbolize/CMakeLists.txt | 2 +- llvm/lib/DebugInfo/Symbolize/DIFetcher.cpp | 58 +++++++ llvm/lib/DebugInfo/Symbolize/Symbolize.cpp | 161 ++++++++---------- llvm/lib/Debuginfod/CMakeLists.txt | 20 +-- llvm/lib/Debuginfod/DIFetcher.cpp | 28 +++ .../tools/llvm-debuginfod-find/CMakeLists.txt | 2 +- llvm/tools/llvm-symbolizer/CMakeLists.txt | 4 +- .../tools/llvm-symbolizer/llvm-symbolizer.cpp | 9 +- llvm/unittests/Debuginfod/CMakeLists.txt | 9 +- 12 files changed, 272 insertions(+), 119 deletions(-) create mode 100644 llvm/include/llvm/DebugInfo/Symbolize/DIFetcher.h create mode 100644 llvm/include/llvm/Debuginfod/DIFetcher.h create mode 100644 llvm/lib/DebugInfo/Symbolize/DIFetcher.cpp create mode 100644 llvm/lib/Debuginfod/DIFetcher.cpp diff --git a/llvm/include/llvm/DebugInfo/Symbolize/DIFetcher.h b/llvm/include/llvm/DebugInfo/Symbolize/DIFetcher.h new file mode 100644 index 0000000000000..c5340b5f04609 --- /dev/null +++ b/llvm/include/llvm/DebugInfo/Symbolize/DIFetcher.h @@ -0,0 +1,51 @@ +//===-- llvm/DebugInfo/Symbolize/DIFetcher.h --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file declares a DIFetcher abstraction for obtaining debug info from an +/// arbitrary outside source. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DEBUGINFO_SYMBOLIZE_DIFETCHER_H +#define LLVM_DEBUGINFO_SYMBOLIZE_DIFETCHER_H + +#include +#include + +#include "llvm/ADT/ArrayRef.h" + +namespace llvm { +namespace symbolize { + +/// The DIFetcher interface provides arbitrary mechanisms for obtaining debug +/// info from an outside source. +class DIFetcher { +public: + virtual ~DIFetcher() = default; + virtual Optional + fetchBuildID(ArrayRef BuildID) const = 0; +}; + +/// LocalDIFetcher searches local cache directories for debug info. +class LocalDIFetcher : public DIFetcher { +public: + LocalDIFetcher(ArrayRef DebugFileDirectory) + : DebugFileDirectory(DebugFileDirectory){}; + virtual ~LocalDIFetcher() = default; + + Optional fetchBuildID(ArrayRef BuildID) const override; + +private: + const ArrayRef DebugFileDirectory; +}; + +} // end namespace symbolize +} // end namespace llvm + +#endif // LLVM_DEBUGINFO_SYMBOLIZE_DIFETCHER_H diff --git a/llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h b/llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h index 4ec333422c4bf..30e55c5d410ae 100644 --- a/llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h +++ b/llvm/include/llvm/DebugInfo/Symbolize/Symbolize.h @@ -13,6 +13,7 @@ #ifndef LLVM_DEBUGINFO_SYMBOLIZE_SYMBOLIZE_H #define LLVM_DEBUGINFO_SYMBOLIZE_SYMBOLIZE_H +#include "llvm/DebugInfo/Symbolize/DIFetcher.h" #include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" #include "llvm/Object/Binary.h" #include "llvm/Object/ELFObjectFile.h" @@ -83,6 +84,10 @@ class LLVMSymbolizer { DemangleName(const std::string &Name, const SymbolizableModule *DbiModuleDescriptor); + void addDIFetcher(std::unique_ptr Fetcher) { + DIFetchers.push_back(std::move(Fetcher)); + } + private: // Bundles together object file with code/data and object file with // corresponding debug info. These objects can be the same. @@ -126,6 +131,12 @@ class LLVMSymbolizer { const ELFObjectFileBase *Obj, const std::string &ArchName); + bool findDebugBinary(const std::string &OrigPath, + const std::string &DebuglinkName, uint32_t CRCHash, + std::string &Result); + + bool findDebugBinary(const ArrayRef BuildID, std::string &Result); + /// Returns pair of pointers to object and debug object. Expected getOrCreateObjectPair(const std::string &Path, const std::string &ArchName); @@ -152,6 +163,8 @@ class LLVMSymbolizer { ObjectForUBPathAndArch; Options Opts; + + SmallVector> DIFetchers; }; } // end namespace symbolize diff --git a/llvm/include/llvm/Debuginfod/DIFetcher.h b/llvm/include/llvm/Debuginfod/DIFetcher.h new file mode 100644 index 0000000000000..d398fd900051d --- /dev/null +++ b/llvm/include/llvm/Debuginfod/DIFetcher.h @@ -0,0 +1,34 @@ +//===- llvm/DebugInfod/DIFetcher.h - Debug info fetcher----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file declares a DIFetcher implementation for obtaining debug info from +/// debuginfod. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DEBUGINFOD_DIFETCHER_H +#define LLVM_DEBUGINFOD_DIFETCHER_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/DebugInfo/Symbolize/DIFetcher.h" + +namespace llvm { + +class DebuginfodDIFetcher : public symbolize::DIFetcher { +public: + virtual ~DebuginfodDIFetcher() = default; + + /// Fetches the given Build ID using debuginfod and returns a local path to + /// the resulting debug binary. + Optional fetchBuildID(ArrayRef BuildID) const override; +}; + +} // namespace llvm + +#endif // LLVM_DEBUGINFOD_DIFETCHER_H diff --git a/llvm/lib/DebugInfo/Symbolize/CMakeLists.txt b/llvm/lib/DebugInfo/Symbolize/CMakeLists.txt index c20ba897e0b80..a647a161579ae 100644 --- a/llvm/lib/DebugInfo/Symbolize/CMakeLists.txt +++ b/llvm/lib/DebugInfo/Symbolize/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_component_library(LLVMSymbolize + DIFetcher.cpp DIPrinter.cpp SymbolizableObjectFile.cpp Symbolize.cpp @@ -9,7 +10,6 @@ add_llvm_component_library(LLVMSymbolize LINK_COMPONENTS DebugInfoDWARF DebugInfoPDB - Debuginfod Object Support Demangle diff --git a/llvm/lib/DebugInfo/Symbolize/DIFetcher.cpp b/llvm/lib/DebugInfo/Symbolize/DIFetcher.cpp new file mode 100644 index 0000000000000..0493fcd3cbc50 --- /dev/null +++ b/llvm/lib/DebugInfo/Symbolize/DIFetcher.cpp @@ -0,0 +1,58 @@ +//===-- lib/DebugInfo/Symbolize/DIFetcher.cpp -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file defines the implementation of the local debug info fetcher, which +/// searches cache directories. +/// +//===----------------------------------------------------------------------===// + +#include "llvm/DebugInfo/Symbolize/DIFetcher.h" + +#include "llvm/Debuginfod/Debuginfod.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/Path.h" + +namespace llvm { +namespace symbolize { + +Optional +LocalDIFetcher::fetchBuildID(ArrayRef BuildID) const { + auto GetDebugPath = [&](StringRef Directory) { + SmallString<128> Path{Directory}; + sys::path::append(Path, ".build-id", + llvm::toHex(BuildID[0], /*LowerCase=*/true), + llvm::toHex(BuildID.slice(1), /*LowerCase=*/true)); + Path += ".debug"; + return Path; + }; + if (DebugFileDirectory.empty()) { + SmallString<128> Path = GetDebugPath( +#if defined(__NetBSD__) + // Try /usr/libdata/debug/.build-id/../... + "/usr/libdata/debug" +#else + // Try /usr/lib/debug/.build-id/../... + "/usr/lib/debug" +#endif + ); + if (llvm::sys::fs::exists(Path)) + return std::string(Path); + } else { + for (const auto &Directory : DebugFileDirectory) { + // Try /.build-id/../... + SmallString<128> Path = GetDebugPath(Directory); + if (llvm::sys::fs::exists(Path)) + return std::string(Path); + } + } + return None; +} + +} // namespace symbolize +} // namespace llvm diff --git a/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp b/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp index 5ec79df17fed9..f085cc63a8e3b 100644 --- a/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp +++ b/llvm/lib/DebugInfo/Symbolize/Symbolize.cpp @@ -20,7 +20,7 @@ #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/DebugInfo/PDB/PDB.h" #include "llvm/DebugInfo/PDB/PDBContext.h" -#include "llvm/Debuginfod/Debuginfod.h" +#include "llvm/DebugInfo/Symbolize/DIFetcher.h" #include "llvm/Demangle/Demangle.h" #include "llvm/Object/COFF.h" #include "llvm/Object/MachO.h" @@ -230,51 +230,6 @@ bool checkFileCRC(StringRef Path, uint32_t CRCHash) { return CRCHash == llvm::crc32(arrayRefFromStringRef(MB.get()->getBuffer())); } -bool findDebugBinary(const std::string &OrigPath, - const std::string &DebuglinkName, uint32_t CRCHash, - const std::string &FallbackDebugPath, - std::string &Result) { - SmallString<16> OrigDir(OrigPath); - llvm::sys::path::remove_filename(OrigDir); - SmallString<16> DebugPath = OrigDir; - // Try relative/path/to/original_binary/debuglink_name - llvm::sys::path::append(DebugPath, DebuglinkName); - if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); - return true; - } - // Try relative/path/to/original_binary/.debug/debuglink_name - DebugPath = OrigDir; - llvm::sys::path::append(DebugPath, ".debug", DebuglinkName); - if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); - return true; - } - // Make the path absolute so that lookups will go to - // "/usr/lib/debug/full/path/to/debug", not - // "/usr/lib/debug/to/debug" - llvm::sys::fs::make_absolute(OrigDir); - if (!FallbackDebugPath.empty()) { - // Try /absolute/path/to/original_binary/debuglink_name - DebugPath = FallbackDebugPath; - } else { -#if defined(__NetBSD__) - // Try /usr/libdata/debug/absolute/path/to/original_binary/debuglink_name - DebugPath = "/usr/libdata/debug"; -#else - // Try /usr/lib/debug/absolute/path/to/original_binary/debuglink_name - DebugPath = "/usr/lib/debug"; -#endif - } - llvm::sys::path::append(DebugPath, llvm::sys::path::relative_path(OrigDir), - DebuglinkName); - if (checkFileCRC(DebugPath, CRCHash)) { - Result = std::string(DebugPath.str()); - return true; - } - return false; -} - bool getGNUDebuglinkContents(const ObjectFile *Obj, std::string &DebugName, uint32_t &CRCHash) { if (!Obj) @@ -351,50 +306,6 @@ Optional> getBuildID(const ELFObjectFileBase *Obj) { return BuildID; } -bool findDebugBinary(const std::vector &DebugFileDirectory, - const ArrayRef BuildID, std::string &Result) { - auto getDebugPath = [&](StringRef Directory) { - SmallString<128> Path{Directory}; - sys::path::append(Path, ".build-id", - llvm::toHex(BuildID[0], /*LowerCase=*/true), - llvm::toHex(BuildID.slice(1), /*LowerCase=*/true)); - Path += ".debug"; - return Path; - }; - if (DebugFileDirectory.empty()) { - SmallString<128> Path = getDebugPath( -#if defined(__NetBSD__) - // Try /usr/libdata/debug/.build-id/../... - "/usr/libdata/debug" -#else - // Try /usr/lib/debug/.build-id/../... - "/usr/lib/debug" -#endif - ); - if (llvm::sys::fs::exists(Path)) { - Result = std::string(Path.str()); - return true; - } - } else { - for (const auto &Directory : DebugFileDirectory) { - // Try /.build-id/../... - SmallString<128> Path = getDebugPath(Directory); - if (llvm::sys::fs::exists(Path)) { - Result = std::string(Path.str()); - return true; - } - } - } - // Try debuginfod client cache and known servers. - Expected PathOrErr = getCachedOrDownloadDebuginfo(BuildID); - if (!PathOrErr) { - consumeError(PathOrErr.takeError()); - return false; - } - Result = *PathOrErr; - return true; -} - } // end anonymous namespace ObjectFile *LLVMSymbolizer::lookUpDsymFile(const std::string &ExePath, @@ -437,8 +348,7 @@ ObjectFile *LLVMSymbolizer::lookUpDebuglinkObject(const std::string &Path, std::string DebugBinaryPath; if (!getGNUDebuglinkContents(Obj, DebuglinkName, CRCHash)) return nullptr; - if (!findDebugBinary(Path, DebuglinkName, CRCHash, Opts.FallbackDebugPath, - DebugBinaryPath)) + if (!findDebugBinary(Path, DebuglinkName, CRCHash, DebugBinaryPath)) return nullptr; auto DbgObjOrErr = getOrCreateObject(DebugBinaryPath, ArchName); if (!DbgObjOrErr) { @@ -458,7 +368,7 @@ ObjectFile *LLVMSymbolizer::lookUpBuildIDObject(const std::string &Path, if (BuildID->size() < 2) return nullptr; std::string DebugBinaryPath; - if (!findDebugBinary(Opts.DebugFileDirectory, *BuildID, DebugBinaryPath)) + if (!findDebugBinary(*BuildID, DebugBinaryPath)) return nullptr; auto DbgObjOrErr = getOrCreateObject(DebugBinaryPath, ArchName); if (!DbgObjOrErr) { @@ -468,6 +378,71 @@ ObjectFile *LLVMSymbolizer::lookUpBuildIDObject(const std::string &Path, return DbgObjOrErr.get(); } +bool LLVMSymbolizer::findDebugBinary(const std::string &OrigPath, + const std::string &DebuglinkName, + uint32_t CRCHash, std::string &Result) { + SmallString<16> OrigDir(OrigPath); + llvm::sys::path::remove_filename(OrigDir); + SmallString<16> DebugPath = OrigDir; + // Try relative/path/to/original_binary/debuglink_name + llvm::sys::path::append(DebugPath, DebuglinkName); + if (checkFileCRC(DebugPath, CRCHash)) { + Result = std::string(DebugPath.str()); + return true; + } + // Try relative/path/to/original_binary/.debug/debuglink_name + DebugPath = OrigDir; + llvm::sys::path::append(DebugPath, ".debug", DebuglinkName); + if (checkFileCRC(DebugPath, CRCHash)) { + Result = std::string(DebugPath.str()); + return true; + } + // Make the path absolute so that lookups will go to + // "/usr/lib/debug/full/path/to/debug", not + // "/usr/lib/debug/to/debug" + llvm::sys::fs::make_absolute(OrigDir); + if (!Opts.FallbackDebugPath.empty()) { + // Try /absolute/path/to/original_binary/debuglink_name + DebugPath = Opts.FallbackDebugPath; + } else { +#if defined(__NetBSD__) + // Try /usr/libdata/debug/absolute/path/to/original_binary/debuglink_name + DebugPath = "/usr/libdata/debug"; +#else + // Try /usr/lib/debug/absolute/path/to/original_binary/debuglink_name + DebugPath = "/usr/lib/debug"; +#endif + } + llvm::sys::path::append(DebugPath, llvm::sys::path::relative_path(OrigDir), + DebuglinkName); + if (checkFileCRC(DebugPath, CRCHash)) { + Result = std::string(DebugPath.str()); + return true; + } + return false; +} + +bool LLVMSymbolizer::findDebugBinary(const ArrayRef BuildID, + std::string &Result) { + Optional Path; + Path = LocalDIFetcher(Opts.DebugFileDirectory).fetchBuildID(BuildID); + if (Path) { + Result = std::move(*Path); + return true; + } + + // Try caller-provided debug info fetchers. + for (const std::unique_ptr &Fetcher : DIFetchers) { + Path = Fetcher->fetchBuildID(BuildID); + if (Path) { + Result = std::move(*Path); + return true; + } + } + + return false; +} + Expected LLVMSymbolizer::getOrCreateObjectPair(const std::string &Path, const std::string &ArchName) { diff --git a/llvm/lib/Debuginfod/CMakeLists.txt b/llvm/lib/Debuginfod/CMakeLists.txt index fa02e0456b114..67e2c2d07aeb7 100644 --- a/llvm/lib/Debuginfod/CMakeLists.txt +++ b/llvm/lib/Debuginfod/CMakeLists.txt @@ -3,8 +3,11 @@ if (LLVM_ENABLE_CURL) set(imported_libs CURL::libcurl) endif() -add_llvm_component_library(LLVMDebuginfod +# Note: This isn't a component, since that could potentially add a libcurl +# dependency to libLLVM. +add_llvm_library(LLVMDebuginfod Debuginfod.cpp + DIFetcher.cpp HTTPClient.cpp ADDITIONAL_HEADER_DIRS @@ -16,18 +19,3 @@ add_llvm_component_library(LLVMDebuginfod LINK_COMPONENTS Support ) - -# This block is only needed for llvm-config. When we deprecate llvm-config and -# move to using CMake export, this block can be removed. -if(LLVM_ENABLE_CURL) - # CMAKE_BUILD_TYPE is only meaningful to single-configuration generators. - if(CMAKE_BUILD_TYPE) - string(TOUPPER ${CMAKE_BUILD_TYPE} build_type) - get_property(curl_library TARGET CURL::libcurl PROPERTY LOCATION_${build_type}) - endif() - if(NOT curl_library) - get_property(curl_library TARGET CURL::libcurl PROPERTY LOCATION) - endif() - get_library_name(${curl_library} curl_library) - set(llvm_system_libs ${llvm_system_libs} "${curl_library}") -endif() diff --git a/llvm/lib/Debuginfod/DIFetcher.cpp b/llvm/lib/Debuginfod/DIFetcher.cpp new file mode 100644 index 0000000000000..f0c134654534f --- /dev/null +++ b/llvm/lib/Debuginfod/DIFetcher.cpp @@ -0,0 +1,28 @@ +//===- llvm/DebugInfod/DIFetcher.cpp - Debug info fetcher -----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file defines a DIFetcher implementation for obtaining debug info +/// from debuginfod. +/// +//===----------------------------------------------------------------------===// + +#include "llvm/Debuginfod/DIFetcher.h" + +#include "llvm/Debuginfod/Debuginfod.h" + +using namespace llvm; + +Optional +DebuginfodDIFetcher::fetchBuildID(ArrayRef BuildID) const { + Expected PathOrErr = getCachedOrDownloadDebuginfo(BuildID); + if (PathOrErr) + return *PathOrErr; + consumeError(PathOrErr.takeError()); + return None; +} diff --git a/llvm/tools/llvm-debuginfod-find/CMakeLists.txt b/llvm/tools/llvm-debuginfod-find/CMakeLists.txt index e6badb5357f40..b8233e70ab1a1 100644 --- a/llvm/tools/llvm-debuginfod-find/CMakeLists.txt +++ b/llvm/tools/llvm-debuginfod-find/CMakeLists.txt @@ -1,10 +1,10 @@ set(LLVM_LINK_COMPONENTS - Debuginfod Support ) add_llvm_tool(llvm-debuginfod-find llvm-debuginfod-find.cpp ) +target_link_libraries(llvm-debuginfod-find PRIVATE LLVMDebuginfod) if(LLVM_INSTALL_BINUTILS_SYMLINKS) add_llvm_tool_symlink(debuginfod-find llvm-debuginfod-find) endif() diff --git a/llvm/tools/llvm-symbolizer/CMakeLists.txt b/llvm/tools/llvm-symbolizer/CMakeLists.txt index 583caec560184..f1a6087c0047f 100644 --- a/llvm/tools/llvm-symbolizer/CMakeLists.txt +++ b/llvm/tools/llvm-symbolizer/CMakeLists.txt @@ -10,7 +10,6 @@ add_public_tablegen_target(SymbolizerOptsTableGen) set(LLVM_LINK_COMPONENTS DebugInfoDWARF DebugInfoPDB - Debuginfod Demangle Object Option @@ -20,10 +19,13 @@ set(LLVM_LINK_COMPONENTS add_llvm_tool(llvm-symbolizer llvm-symbolizer.cpp + DEPENDS SymbolizerOptsTableGen ) +target_link_libraries(llvm-symbolizer PRIVATE LLVMDebuginfod) + add_llvm_tool_symlink(llvm-addr2line llvm-symbolizer) if(LLVM_INSTALL_BINUTILS_SYMLINKS) diff --git a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp index 66a2e703129bf..0315413ea0c3c 100644 --- a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp +++ b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp @@ -19,6 +19,7 @@ #include "llvm/Config/config.h" #include "llvm/DebugInfo/Symbolize/DIPrinter.h" #include "llvm/DebugInfo/Symbolize/Symbolize.h" +#include "llvm/Debuginfod/DIFetcher.h" #include "llvm/Debuginfod/HTTPClient.h" #include "llvm/Option/Arg.h" #include "llvm/Option/ArgList.h" @@ -262,8 +263,6 @@ static FunctionNameKind decideHowToPrintFunctions(const opt::InputArgList &Args, int main(int argc, char **argv) { InitLLVM X(argc, argv); - // The HTTPClient must be initialized for use by the debuginfod client. - HTTPClient::initialize(); sys::InitializeCOMRAII COM(sys::COMThreadingMode::MultiThreaded); bool IsAddr2Line = sys::path::stem(argv[0]).contains("addr2line"); @@ -330,6 +329,12 @@ int main(int argc, char **argv) { } LLVMSymbolizer Symbolizer(Opts); + + // Look up symbols using the debuginfod client. + Symbolizer.addDIFetcher(std::make_unique()); + // The HTTPClient must be initialized for use by the debuginfod client. + HTTPClient::initialize(); + std::unique_ptr Printer; if (Style == OutputStyle::GNU) Printer = std::make_unique(outs(), errs(), Config); diff --git a/llvm/unittests/Debuginfod/CMakeLists.txt b/llvm/unittests/Debuginfod/CMakeLists.txt index 967ea79bbf5c7..d2109fe8af175 100644 --- a/llvm/unittests/Debuginfod/CMakeLists.txt +++ b/llvm/unittests/Debuginfod/CMakeLists.txt @@ -1,10 +1,9 @@ -set(LLVM_LINK_COMPONENTS - Debuginfod - ) - add_llvm_unittest(DebuginfodTests HTTPClientTests.cpp DebuginfodTests.cpp ) -target_link_libraries(DebuginfodTests PRIVATE LLVMTestingSupport) +target_link_libraries(DebuginfodTests PRIVATE + LLVMDebuginfod + LLVMTestingSupport + ) From 9bc22aa5078020bd76d5e4150d39e929c63cc355 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Thu, 10 Feb 2022 14:13:18 -0500 Subject: [PATCH 136/316] [OpenMP][CUDA] Refine the logic to determine grid size This patch refines the logic to determine grid size as previous method can escape the check of whether `CudaBlocksPerGrid` could be greater than the actual hardware limit. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D119311 (cherry picked from commit f6685f774697c85d6a352dcea013f46a99f9fe31) --- openmp/libomptarget/plugins/cuda/src/rtl.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openmp/libomptarget/plugins/cuda/src/rtl.cpp b/openmp/libomptarget/plugins/cuda/src/rtl.cpp index e17593878b7c7..0ca05f0ec3a0f 100644 --- a/openmp/libomptarget/plugins/cuda/src/rtl.cpp +++ b/openmp/libomptarget/plugins/cuda/src/rtl.cpp @@ -1170,15 +1170,17 @@ class DeviceRTLTy { DP("Using default number of teams %d\n", DeviceData[DeviceId].NumTeams); CudaBlocksPerGrid = DeviceData[DeviceId].NumTeams; } - } else if (TeamNum > DeviceData[DeviceId].BlocksPerGrid) { - DP("Capping number of teams to team limit %d\n", - DeviceData[DeviceId].BlocksPerGrid); - CudaBlocksPerGrid = DeviceData[DeviceId].BlocksPerGrid; } else { DP("Using requested number of teams %d\n", TeamNum); CudaBlocksPerGrid = TeamNum; } + if (CudaBlocksPerGrid > DeviceData[DeviceId].BlocksPerGrid) { + DP("Capping number of teams to team limit %d\n", + DeviceData[DeviceId].BlocksPerGrid); + CudaBlocksPerGrid = DeviceData[DeviceId].BlocksPerGrid; + } + INFO(OMP_INFOTYPE_PLUGIN_KERNEL, DeviceId, "Launching kernel %s with %d blocks and %d threads in %s mode\n", (getOffloadEntry(DeviceId, TgtEntryPtr)) From 880717cc801d0814329af181afe3e084fd45ef74 Mon Sep 17 00:00:00 2001 From: Jameson Nash Date: Fri, 11 Feb 2022 16:42:37 -0500 Subject: [PATCH 137/316] clang-analyzer plugins require LLVM_ENABLE_PLUGINS also The clang-analyzer plugins are not linked to a particular tool, so they can only be compiled if plugins are broadly supported. We could opt instead to decide whether to link them to specifically against clang or with undefined symbols, depending on the value of LLVM_ENABLE_PLUGINS, but we do not currently expect there to be a use case for that rather niche configuration. Differential Revision: https://reviews.llvm.org/D119591 (cherry picked from commit 9d59cfc67eadbe4b4088d70f8bbc61c96568d2f1) --- clang/CMakeLists.txt | 7 ++++++- clang/examples/AnnotateFunctions/CMakeLists.txt | 2 +- clang/examples/Attribute/CMakeLists.txt | 2 +- clang/examples/CMakeLists.txt | 12 +++++++----- clang/examples/CallSuperAttribute/CMakeLists.txt | 2 +- clang/examples/PluginsOrder/CMakeLists.txt | 2 +- clang/examples/PrintFunctionNames/CMakeLists.txt | 2 +- clang/lib/Analysis/plugins/CMakeLists.txt | 5 ++++- clang/test/CMakeLists.txt | 6 +++--- 9 files changed, 25 insertions(+), 15 deletions(-) diff --git a/clang/CMakeLists.txt b/clang/CMakeLists.txt index 4225c028e1794..937a8467df1d7 100644 --- a/clang/CMakeLists.txt +++ b/clang/CMakeLists.txt @@ -476,9 +476,14 @@ add_definitions( -D_GNU_SOURCE ) option(CLANG_BUILD_TOOLS "Build the Clang tools. If OFF, just generate build targets." ON) +if(LLVM_ENABLE_PLUGINS OR LLVM_EXPORT_SYMBOLS_FOR_PLUGINS) + set(HAVE_CLANG_PLUGIN_SUPPORT ON) +else() + set(HAVE_CLANG_PLUGIN_SUPPORT OFF) +endif() CMAKE_DEPENDENT_OPTION(CLANG_PLUGIN_SUPPORT "Build clang with plugin support" ON - "LLVM_ENABLE_PLUGINS OR LLVM_EXPORT_SYMBOLS_FOR_PLUGINS" OFF) + "HAVE_CLANG_PLUGIN_SUPPORT" OFF) option(CLANG_ENABLE_ARCMT "Build ARCMT." ON) option(CLANG_ENABLE_STATIC_ANALYZER diff --git a/clang/examples/AnnotateFunctions/CMakeLists.txt b/clang/examples/AnnotateFunctions/CMakeLists.txt index e6541f7cc62a6..827ff79fcc410 100644 --- a/clang/examples/AnnotateFunctions/CMakeLists.txt +++ b/clang/examples/AnnotateFunctions/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(AnnotateFunctions MODULE AnnotateFunctions.cpp PLUGIN_TOOL clang) -if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) +if(WIN32 OR CYGWIN) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/Attribute/CMakeLists.txt b/clang/examples/Attribute/CMakeLists.txt index 5392ac0df1703..770fa28364b77 100644 --- a/clang/examples/Attribute/CMakeLists.txt +++ b/clang/examples/Attribute/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(Attribute MODULE Attribute.cpp PLUGIN_TOOL clang) -if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) +if(WIN32 OR CYGWIN) target_link_libraries(Attribute PRIVATE clangAST clangBasic diff --git a/clang/examples/CMakeLists.txt b/clang/examples/CMakeLists.txt index 4a677933bb54f..8be327bcdbb9d 100644 --- a/clang/examples/CMakeLists.txt +++ b/clang/examples/CMakeLists.txt @@ -3,8 +3,10 @@ if(NOT CLANG_BUILD_EXAMPLES) set(EXCLUDE_FROM_ALL ON) endif() -add_subdirectory(PrintFunctionNames) -add_subdirectory(AnnotateFunctions) -add_subdirectory(Attribute) -add_subdirectory(CallSuperAttribute) -add_subdirectory(PluginsOrder) +if(CLANG_PLUGIN_SUPPORT) + add_subdirectory(PrintFunctionNames) + add_subdirectory(AnnotateFunctions) + add_subdirectory(Attribute) + add_subdirectory(CallSuperAttribute) + add_subdirectory(PluginsOrder) +endif() diff --git a/clang/examples/CallSuperAttribute/CMakeLists.txt b/clang/examples/CallSuperAttribute/CMakeLists.txt index f4284adf289e3..dc832327c775d 100644 --- a/clang/examples/CallSuperAttribute/CMakeLists.txt +++ b/clang/examples/CallSuperAttribute/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(CallSuperAttr MODULE CallSuperAttrInfo.cpp PLUGIN_TOOL clang) -if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) +if(WIN32 OR CYGWIN) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/PluginsOrder/CMakeLists.txt b/clang/examples/PluginsOrder/CMakeLists.txt index 612587a6d2fe3..c22b0081ad686 100644 --- a/clang/examples/PluginsOrder/CMakeLists.txt +++ b/clang/examples/PluginsOrder/CMakeLists.txt @@ -1,6 +1,6 @@ add_llvm_library(PluginsOrder MODULE PluginsOrder.cpp PLUGIN_TOOL clang) -if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) +if(WIN32 OR CYGWIN) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/examples/PrintFunctionNames/CMakeLists.txt b/clang/examples/PrintFunctionNames/CMakeLists.txt index 67f1b16744eaf..28da363729f3a 100644 --- a/clang/examples/PrintFunctionNames/CMakeLists.txt +++ b/clang/examples/PrintFunctionNames/CMakeLists.txt @@ -11,7 +11,7 @@ endif() add_llvm_library(PrintFunctionNames MODULE PrintFunctionNames.cpp PLUGIN_TOOL clang) -if(CLANG_PLUGIN_SUPPORT AND (WIN32 OR CYGWIN)) +if(WIN32 OR CYGWIN) set(LLVM_LINK_COMPONENTS Support ) diff --git a/clang/lib/Analysis/plugins/CMakeLists.txt b/clang/lib/Analysis/plugins/CMakeLists.txt index 7b754ea3f2bc9..157be7e4147bc 100644 --- a/clang/lib/Analysis/plugins/CMakeLists.txt +++ b/clang/lib/Analysis/plugins/CMakeLists.txt @@ -1,4 +1,7 @@ -if(CLANG_ENABLE_STATIC_ANALYZER AND CLANG_PLUGIN_SUPPORT) +# Since these do not specify a specific PLUGIN_TOOL (which could be clang or +# clang-tidy), we cannot compile this unless the platform supports plugins with +# undefined symbols, and cannot use it unless the user has opted for clang plugins). +if(CLANG_ENABLE_STATIC_ANALYZER AND CLANG_PLUGIN_SUPPORT AND LLVM_ENABLE_PLUGINS) add_subdirectory(SampleAnalyzer) add_subdirectory(CheckerDependencyHandling) add_subdirectory(CheckerOptionHandling) diff --git a/clang/test/CMakeLists.txt b/clang/test/CMakeLists.txt index cbe7c787a1a26..d7cc8d2790961 100644 --- a/clang/test/CMakeLists.txt +++ b/clang/test/CMakeLists.txt @@ -94,7 +94,7 @@ if (CLANG_ENABLE_ARCMT) ) endif () -if (CLANG_BUILD_EXAMPLES) +if(CLANG_BUILD_EXAMPLES AND CLANG_PLUGIN_SUPPORT) list(APPEND CLANG_TEST_DEPS Attribute AnnotateFunctions @@ -144,8 +144,8 @@ if( NOT CLANG_BUILT_STANDALONE ) endif() endif() -if (CLANG_ENABLE_STATIC_ANALYZER) - if (CLANG_PLUGIN_SUPPORT) +if(CLANG_ENABLE_STATIC_ANALYZER) + if(CLANG_PLUGIN_SUPPORT AND LLVM_ENABLE_PLUGINS) # Determine if we built them list(APPEND CLANG_TEST_DEPS SampleAnalyzerPlugin CheckerDependencyHandlingAnalyzerPlugin From 1e348e6042fcec068dfb56c65339a5a60033d3bd Mon Sep 17 00:00:00 2001 From: Sven van Haastregt Date: Wed, 16 Feb 2022 10:07:35 +0000 Subject: [PATCH 138/316] [OpenCL] Guard atomic_double with cl_khr_int64_* It is necessary to guard atomic_double type according to https://www.khronos.org/registry/OpenCL/specs/3.0-unified/html/OpenCL_C.html#_footnotedef_54. Platform that disable cl_khr_int64_base_atomics and cl_khr_int64_extended_atomics will have compiling errors even if atomic_double is not used. Patch by Haonan Yang. Differential Revision: https://reviews.llvm.org/D119398 (cherry picked from commit 477bc8e8b9311fdac4c360b1fe7d29d0d10aac6c) --- clang/lib/Headers/opencl-c.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/clang/lib/Headers/opencl-c.h b/clang/lib/Headers/opencl-c.h index 059a2ec2371bd..c7bb77716ac4b 100644 --- a/clang/lib/Headers/opencl-c.h +++ b/clang/lib/Headers/opencl-c.h @@ -13832,6 +13832,7 @@ float __ovld atomic_fetch_max_explicit(volatile atomic_float *object, #endif // defined(__opencl_c_ext_fp32_global_atomic_min_max) && \ defined(__opencl_c_ext_fp32_local_atomic_min_max) +#if defined(cl_khr_int64_base_atomics) && defined(cl_khr_int64_extended_atomics) #if defined(__opencl_c_ext_fp64_global_atomic_min_max) double __ovld atomic_fetch_min(volatile __global atomic_double *object, double operand); @@ -13882,6 +13883,8 @@ double __ovld atomic_fetch_max_explicit(volatile atomic_double *object, memory_scope scope); #endif // defined(__opencl_c_ext_fp64_global_atomic_min_max) && \ defined(__opencl_c_ext_fp64_local_atomic_min_max) +#endif // defined(cl_khr_int64_base_atomics) && \ + defined(cl_khr_int64_extended_atomics) #if defined(__opencl_c_ext_fp16_global_atomic_add) half __ovld atomic_fetch_add(volatile __global atomic_half *object, @@ -13985,6 +13988,7 @@ float __ovld atomic_fetch_sub_explicit(volatile atomic_float *object, #endif // defined(__opencl_c_ext_fp32_global_atomic_add) && \ defined(__opencl_c_ext_fp32_local_atomic_add) +#if defined(cl_khr_int64_base_atomics) && defined(cl_khr_int64_extended_atomics) #if defined(__opencl_c_ext_fp64_global_atomic_add) double __ovld atomic_fetch_add(volatile __global atomic_double *object, double operand); @@ -14035,6 +14039,8 @@ double __ovld atomic_fetch_sub_explicit(volatile atomic_double *object, memory_scope scope); #endif // defined(__opencl_c_ext_fp64_global_atomic_add) && \ defined(__opencl_c_ext_fp64_local_atomic_add) +#endif // defined(cl_khr_int64_base_atomics) && \ + defined(cl_khr_int64_extended_atomics) #endif // cl_ext_float_atomics From 192d9680c1b11877e84b7431626ac8321c52d9c1 Mon Sep 17 00:00:00 2001 From: Shao-Ce SUN Date: Thu, 17 Feb 2022 21:02:58 +0800 Subject: [PATCH 139/316] [RISCV] add the MC layer support of Zfinx extension This patch added the MC layer support of Zfinx extension. Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun Reviewed By: asb Differential Revision: https://reviews.llvm.org/D93298 (cherry picked from commit 7798ecca9c3db42241169d31fea4fb820ed01830) --- llvm/lib/Support/RISCVISAInfo.cpp | 23 +- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 35 ++- .../RISCV/Disassembler/RISCVDisassembler.cpp | 32 ++ llvm/lib/Target/RISCV/RISCV.td | 37 +++ llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 215 +++++++++----- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 281 +++++++++++++----- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 213 ++++++++----- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 30 ++ llvm/lib/Target/RISCV/RISCVSubtarget.h | 8 + llvm/test/MC/RISCV/attribute-arch.s | 12 + llvm/test/MC/RISCV/rv32i-invalid.s | 6 +- llvm/test/MC/RISCV/rv32zdinx-invalid.s | 27 ++ llvm/test/MC/RISCV/rv32zdinx-valid.s | 124 ++++++++ llvm/test/MC/RISCV/rv32zfinx-invalid.s | 25 ++ llvm/test/MC/RISCV/rv32zfinx-valid.s | 128 ++++++++ llvm/test/MC/RISCV/rv32zhinx-invalid.s | 24 ++ llvm/test/MC/RISCV/rv32zhinx-valid.s | 128 ++++++++ llvm/test/MC/RISCV/rv32zhinxmin-invalid.s | 15 + llvm/test/MC/RISCV/rv32zhinxmin-valid.s | 18 ++ llvm/test/MC/RISCV/rv64zdinx-invalid.s | 9 + llvm/test/MC/RISCV/rv64zdinx-valid.s | 43 +++ llvm/test/MC/RISCV/rv64zfinx-invalid.s | 9 + llvm/test/MC/RISCV/rv64zfinx-valid.s | 43 +++ llvm/test/MC/RISCV/rv64zhinx-invalid.s | 9 + llvm/test/MC/RISCV/rv64zhinx-valid.s | 43 +++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s | 9 + llvm/test/MC/RISCV/rv64zhinxmin-valid.s | 13 + llvm/test/MC/RISCV/rvzdinx-aliases-valid.s | 49 +++ llvm/test/MC/RISCV/rvzfinx-aliases-valid.s | 82 +++++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s | 82 +++++ 30 files changed, 1548 insertions(+), 224 deletions(-) create mode 100644 llvm/test/MC/RISCV/rv32zdinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv32zdinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv32zfinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv32zfinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv32zhinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv32zhinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv32zhinxmin-invalid.s create mode 100644 llvm/test/MC/RISCV/rv32zhinxmin-valid.s create mode 100644 llvm/test/MC/RISCV/rv64zdinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zdinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv64zfinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zfinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv64zhinx-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zhinx-valid.s create mode 100644 llvm/test/MC/RISCV/rv64zhinxmin-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64zhinxmin-valid.s create mode 100644 llvm/test/MC/RISCV/rvzdinx-aliases-valid.s create mode 100644 llvm/test/MC/RISCV/rvzfinx-aliases-valid.s create mode 100644 llvm/test/MC/RISCV/rvzhinx-aliases-valid.s diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 2b3395b669b86..18de7dcd08f31 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -51,6 +51,11 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zfhmin", RISCVExtensionVersion{1, 0}}, {"zfh", RISCVExtensionVersion{1, 0}}, + {"zfinx", RISCVExtensionVersion{1, 0}}, + {"zdinx", RISCVExtensionVersion{1, 0}}, + {"zhinxmin", RISCVExtensionVersion{1, 0}}, + {"zhinx", RISCVExtensionVersion{1, 0}}, + {"zba", RISCVExtensionVersion{1, 0}}, {"zbb", RISCVExtensionVersion{1, 0}}, {"zbc", RISCVExtensionVersion{1, 0}}, @@ -686,6 +691,8 @@ Error RISCVISAInfo::checkDependency() { bool HasE = Exts.count("e") != 0; bool HasD = Exts.count("d") != 0; bool HasF = Exts.count("f") != 0; + bool HasZfinx = Exts.count("zfinx") != 0; + bool HasZdinx = Exts.count("zdinx") != 0; bool HasZve32x = Exts.count("zve32x") != 0; bool HasZve32f = Exts.count("zve32f") != 0; bool HasZve64d = Exts.count("zve64d") != 0; @@ -706,17 +713,15 @@ Error RISCVISAInfo::checkDependency() { return createStringError(errc::invalid_argument, "d requires f extension to also be specified"); - // FIXME: Consider Zfinx in the future - if (HasZve32f && !HasF) + if (HasZve32f && !HasF && !HasZfinx) return createStringError( errc::invalid_argument, - "zve32f requires f extension to also be specified"); + "zve32f requires f or zfinx extension to also be specified"); - // FIXME: Consider Zdinx in the future - if (HasZve64d && !HasD) + if (HasZve64d && !HasD && !HasZdinx) return createStringError( errc::invalid_argument, - "zve64d requires d extension to also be specified"); + "zve64d requires d or zdinx extension to also be specified"); if (HasZvl && !HasVector) return createStringError( @@ -733,6 +738,9 @@ Error RISCVISAInfo::checkDependency() { static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"}; static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfh[] = {"f"}; +static const char *ImpliedExtsZdinx[] = {"zfinx"}; +static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; +static const char *ImpliedExtsZhinx[] = {"zfinx"}; static const char *ImpliedExtsZve64d[] = {"zve64f"}; static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; @@ -767,8 +775,11 @@ struct ImpliedExtsEntry { // Note: The table needs to be sorted by name. static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"v"}, {ImpliedExtsV}}, + {{"zdinx"}, {ImpliedExtsZdinx}}, {{"zfh"}, {ImpliedExtsZfh}}, {{"zfhmin"}, {ImpliedExtsZfhmin}}, + {{"zhinx"}, {ImpliedExtsZhinx}}, + {{"zhinxmin"}, {ImpliedExtsZhinxmin}}, {{"zk"}, {ImpliedExtsZk}}, {{"zkn"}, {ImpliedExtsZkn}}, {{"zks"}, {ImpliedExtsZks}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 01f36e6dcdd23..95319d1b0b74e 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -170,6 +170,7 @@ class RISCVAsmParser : public MCTargetAsmParser { OperandMatchResultTy parseVTypeI(OperandVector &Operands); OperandMatchResultTy parseMaskReg(OperandVector &Operands); OperandMatchResultTy parseInsnDirectiveOpcode(OperandVector &Operands); + OperandMatchResultTy parseGPRAsFPR(OperandVector &Operands); bool parseOperand(OperandVector &Operands, StringRef Mnemonic); @@ -273,6 +274,8 @@ struct RISCVOperand : public MCParsedAsmOperand { bool IsRV64; + bool IsGPRAsFPR; + struct RegOp { MCRegister RegNum; }; @@ -343,6 +346,14 @@ struct RISCVOperand : public MCParsedAsmOperand { RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); } + bool isGPRAsFPR() const { return isGPR() && IsGPRAsFPR; } + + bool isGPRF64AsFPR() const { return isGPR() && IsGPRAsFPR && IsRV64; } + + bool isGPRPF64AsFPR() const { + return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1); + } + static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, RISCVMCExpr::VariantKind &VK) { if (auto *RE = dyn_cast(Expr)) { @@ -831,12 +842,14 @@ struct RISCVOperand : public MCParsedAsmOperand { } static std::unique_ptr createReg(unsigned RegNo, SMLoc S, - SMLoc E, bool IsRV64) { + SMLoc E, bool IsRV64, + bool IsGPRAsFPR = false) { auto Op = std::make_unique(KindTy::Register); Op->Reg.RegNum = RegNo; Op->StartLoc = S; Op->EndLoc = E; Op->IsRV64 = IsRV64; + Op->IsGPRAsFPR = IsGPRAsFPR; return Op; } @@ -1780,6 +1793,26 @@ OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) { return MatchOperand_Success; } +OperandMatchResultTy RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) { + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::Identifier: + StringRef Name = getLexer().getTok().getIdentifier(); + MCRegister RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + + if (RegNo == RISCV::NoRegister) + return MatchOperand_NoMatch; + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg( + RegNo, S, E, isRV64(), !getSTI().hasFeature(RISCV::FeatureStdExtF))); + } + return MatchOperand_Success; +} + OperandMatchResultTy RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::LParen)) { diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index ff96b2b254cac..18947997dc583 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -161,6 +161,17 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32 || RegNo & 1) + return MCDisassembler::Fail; + + MCRegister Reg = RISCV::X0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { @@ -427,6 +438,27 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return MCDisassembler::Fail; } Insn = support::endian::read32le(Bytes.data()); + if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] && + !STI.getFeatureBits()[RISCV::Feature64Bit]) { + LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and" + "rv32)\n"); + Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address, + this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) { + LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n"); + Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); Size = 4; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index e32a8fb010de1..065e731ff6bcf 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -63,6 +63,43 @@ def HasStdExtZfhOrZfhmin "'Zfh' (Half-Precision Floating-Point) or " "'Zfhmin' (Half-Precision Floating-Point Minimal)">; +def FeatureStdExtZfinx + : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true", + "'Zfinx' (Float in Integer)">; +def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">, + AssemblerPredicate<(all_of FeatureStdExtZfinx), + "'Zfinx' (Float in Integer)">; + +def FeatureStdExtZdinx + : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true", + "'Zdinx' (Double in Integer)", + [FeatureStdExtZfinx]>; +def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">, + AssemblerPredicate<(all_of FeatureStdExtZdinx), + "'Zdinx' (Double in Integer)">; + +def FeatureStdExtZhinxmin + : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true", + "'Zhinxmin' (Half Float in Integer Minimal)", + [FeatureStdExtZfinx]>; +def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">, + AssemblerPredicate<(all_of FeatureStdExtZhinxmin), + "'Zhinxmin' (Half Float in Integer Minimal)">; + +def FeatureStdExtZhinx + : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true", + "'Zhinx' (Half Float in Integer)", + [FeatureStdExtZfinx]>; +def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">, + AssemblerPredicate<(all_of FeatureStdExtZhinx), + "'Zhinx' (Half Float in Integer)">; + +def HasStdExtZhinxOrZhinxmin + : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">, + AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin), + "'Zhinx' (Half Float in Integer) or " + "'Zhinxmin' (Half Float in Integer Minimal)">; + def FeatureStdExtC : SubtargetFeature<"c", "HasStdExtC", "true", "'C' (Compressed Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index 2837b92da81f4..4f5ec6aada615 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -25,6 +25,69 @@ def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +// Zdinx + +def GPRPF64AsFPR : AsmOperandClass { + let Name = "GPRPF64AsFPR"; + let ParserMethod = "parseGPRAsFPR"; + let RenderMethod = "addRegOperands"; +} + +def GPRF64AsFPR : AsmOperandClass { + let Name = "GPRF64AsFPR"; + let ParserMethod = "parseGPRAsFPR"; + let RenderMethod = "addRegOperands"; +} + +def FPR64INX : RegisterOperand { + let ParserMatchClass = GPRF64AsFPR; + let DecoderMethod = "DecodeGPRRegisterClass"; +} + +def FPR64IN32X : RegisterOperand { + let ParserMatchClass = GPRPF64AsFPR; +} + +def DExt : ExtInfo<0, [HasStdExtD]>; +def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>; +def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>; +def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, IsRV32]>; + +def D : ExtInfo_r; +def D_INX : ExtInfo_r; +def D_IN32X : ExtInfo_r; + +def DD : ExtInfo_rr; +def DD_INX : ExtInfo_rr; +def DD_IN32X : ExtInfo_rr; +def DF : ExtInfo_rr; +def DF_INX : ExtInfo_rr; +def DF_IN32X : ExtInfo_rr; +def DX : ExtInfo_rr; +def DX_INX : ExtInfo_rr; +def DX_IN32X : ExtInfo_rr; +def DX_64 : ExtInfo_rr; +def FD : ExtInfo_rr; +def FD_INX : ExtInfo_rr; +def FD_IN32X : ExtInfo_rr; +def XD : ExtInfo_rr; +def XD_INX : ExtInfo_rr; +def XD_IN32X : ExtInfo_rr; +def XD_64 : ExtInfo_rr; + +defvar DINX = [D, D_INX, D_IN32X]; +defvar DDINX = [DD, DD_INX, DD_IN32X]; +defvar DXINX = [DX, DX_INX, DX_IN32X]; +defvar DFINX = [DF, DF_INX, DF_IN32X]; +defvar FDINX = [FD, FD_INX, FD_IN32X]; +defvar XDINX = [XD, XD_INX, XD_IN32X]; +defvar DXIN64X = [DX_64, DX_INX]; +defvar XDIN64X = [XD_64, XD_INX]; + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -36,106 +99,104 @@ def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>; // reflecting the order these fields are specified in the instruction // encoding. def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; +} // Predicates = [HasStdExtD] let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in { -def FMADD_D : FPFMA_rrr_frm; -def FMSUB_D : FPFMA_rrr_frm; -def FNMSUB_D : FPFMA_rrr_frm; -def FNMADD_D : FPFMA_rrr_frm; +defm FMADD_D : FPFMA_rrr_frm_m; +defm FMSUB_D : FPFMA_rrr_frm_m; +defm FNMSUB_D : FPFMA_rrr_frm_m; +defm FNMADD_D : FPFMA_rrr_frm_m; +} + +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; + +let SchedRW = [WriteFALU64, ReadFALU64, ReadFALU64] in { +defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX>; +defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>; } +let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in +defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", DINX>; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; - -def FADD_D : FPALU_rr_frm<0b0000001, "fadd.d", FPR64>, - Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; -def FSUB_D : FPALU_rr_frm<0b0000101, "fsub.d", FPR64>, - Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>; -def FMUL_D : FPALU_rr_frm<0b0001001, "fmul.d", FPR64>, - Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>; -def FDIV_D : FPALU_rr_frm<0b0001101, "fdiv.d", FPR64>, - Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; - -def FSQRT_D : FPUnaryOp_r_frm<0b0101101, 0b00000, FPR64, FPR64, "fsqrt.d">, - Sched<[WriteFSqrt64, ReadFSqrt64]>; -def : FPUnaryOpDynFrmAlias; +let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in +defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", DINX>; + +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; + +defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, DDINX, "fsqrt.d">, + Sched<[WriteFSqrt64, ReadFSqrt64]>; +defm : FPUnaryOpDynFrmAlias_m; let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64], mayRaiseFPException = 0 in { -def FSGNJ_D : FPALU_rr<0b0010001, 0b000, "fsgnj.d", FPR64>; -def FSGNJN_D : FPALU_rr<0b0010001, 0b001, "fsgnjn.d", FPR64>; -def FSGNJX_D : FPALU_rr<0b0010001, 0b010, "fsgnjx.d", FPR64>; +defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", DINX>; +defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", DINX>; +defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", DINX>; } let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in { -def FMIN_D : FPALU_rr<0b0010101, 0b000, "fmin.d", FPR64>; -def FMAX_D : FPALU_rr<0b0010101, 0b001, "fmax.d", FPR64>; +defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", DINX>; +defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", DINX>; } -def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, 0b00001, FPR32, FPR64, "fcvt.s.d">, - Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, FDINX, "fcvt.s.d">, + Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b00000, 0b000, FPR64, FPR32, "fcvt.d.s">, - Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; +defm FCVT_D_S : FPUnaryOp_r_m<0b0100001, 0b00000, 0b000, DFINX, "fcvt.d.s">, + Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in { -def FEQ_D : FPCmp_rr<0b1010001, 0b010, "feq.d", FPR64>; -def FLT_D : FPCmp_rr<0b1010001, 0b001, "flt.d", FPR64>; -def FLE_D : FPCmp_rr<0b1010001, 0b000, "fle.d", FPR64>; +defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", DINX>; +defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", DINX>; +defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", DINX>; } -let mayRaiseFPException = 0 in -def FCLASS_D : FPUnaryOp_r<0b1110001, 0b00000, 0b001, GPR, FPR64, "fclass.d">, - Sched<[WriteFClass64, ReadFClass64]>; +defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, XDINX, "fclass.d">, + Sched<[WriteFClass64, ReadFClass64]>; -def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, 0b00000, GPR, FPR64, "fcvt.w.d">, +defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, XDINX, "fcvt.w.d">, Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; -def : FPUnaryOpDynFrmAlias; - -def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, 0b00001, GPR, FPR64, "fcvt.wu.d">, - Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b00000, 0b000, FPR64, GPR, "fcvt.d.w">, - Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; +defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, XDINX, "fcvt.wu.d">, + Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b00001, 0b000, FPR64, GPR, "fcvt.d.wu">, +defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, DXINX, "fcvt.d.w">, Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; -} // Predicates = [HasStdExtD] -let Predicates = [HasStdExtD, IsRV64] in { -def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, 0b00010, GPR, FPR64, "fcvt.l.d">, - Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, DXINX, "fcvt.d.wu">, + Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; -def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, 0b00011, GPR, FPR64, "fcvt.lu.d">, +defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDIN64X, "fcvt.l.d">, Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -let mayRaiseFPException = 0 in +defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDIN64X, "fcvt.lu.d">, + Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; +defm : FPUnaryOpDynFrmAlias_m; + +let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">, Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; -def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, 0b00010, FPR64, GPR, "fcvt.d.l">, - Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; -def : FPUnaryOpDynFrmAlias; - -def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, 0b00011, FPR64, GPR, "fcvt.d.lu">, +defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXIN64X, "fcvt.d.l">, Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -let mayRaiseFPException = 0 in +defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXIN64X, "fcvt.d.lu">, + Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; +defm : FPUnaryOpDynFrmAlias_m; + +let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">, Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; -} // Predicates = [HasStdExtD, IsRV64] //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) @@ -164,6 +225,26 @@ def PseudoQuietFLT_D : PseudoQuietFCMP; } } // Predicates = [HasStdExtD] +let Predicates = [HasStdExtZdinx, IsRV64] in { +def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; +def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; + +def : InstAlias<"fgt.d $rd, $rs, $rt", + (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; +def : InstAlias<"fge.d $rd, $rs, $rt", + (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; +} // Predicates = [HasStdExtZdinx, IsRV64] + +let Predicates = [HasStdExtZdinx, IsRV32] in { +def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; +def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; + +def : InstAlias<"fgt.d $rd, $rs, $rt", + (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; +def : InstAlias<"fge.d $rd, $rs, $rt", + (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; +} // Predicates = [HasStdExtZdinx, IsRV32] + //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index a8ac06ba8da3f..4b45b47af451c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -57,6 +57,73 @@ def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm), // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// +// Zfinx + +def GPRAsFPR : AsmOperandClass { + let Name = "GPRAsFPR"; + let ParserMethod = "parseGPRAsFPR"; + let RenderMethod = "addRegOperands"; +} + +def FPR32INX : RegisterOperand { + let ParserMatchClass = GPRAsFPR; + let DecoderMethod = "DecodeGPRRegisterClass"; +} + +// inx = 0 : f, d, zfh, zfhmin +// = 1 : zfinx, zdinx, zhinx, zhinxmin +// = 2 : zdinx_rv32 +class ExtInfo inx, list pres> { + string Suffix = !cond(!eq(inx, 0): "", + !eq(inx, 1): "_INX", + !eq(inx, 2): "_IN32X"); + list Predicates = pres; + string Space = !cond(!eq(inx, 0): "", + !eq(inx, 1): "RVZfinx", + !eq(inx, 2): "RV32Zdinx"); +} + +class ExtInfo_r { + string Suffix = ext.Suffix; + list Predicates = ext.Predicates; + string Space = ext.Space; + DAGOperand Reg = reg; +} + +class ExtInfo_rr { + string Suffix = ext.Suffix; + list Predicates = ext.Predicates; + string Space = ext.Space; + DAGOperand RdTy = rdty; + DAGOperand Rs1Ty = rs1ty; +} + +def FExt : ExtInfo<0, [HasStdExtF]>; +def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>; +def ZfinxExt : ExtInfo<1, [HasStdExtZfinx]>; +def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>; + +def F : ExtInfo_r; +def F_INX : ExtInfo_r; + +def FF : ExtInfo_rr; +def FF_INX : ExtInfo_rr; +def FX : ExtInfo_rr; +def FX_INX : ExtInfo_rr; +def FX_64 : ExtInfo_rr; +def FX_INX_64 : ExtInfo_rr; +def XF : ExtInfo_rr; +def XF_64 : ExtInfo_rr; +def XF_INX : ExtInfo_rr; +def XF_INX_64 : ExtInfo_rr; + +defvar FINX = [F, F_INX]; +defvar FFINX = [FF, FF_INX]; +defvar FXINX = [FX, FX_INX]; +defvar XFINX = [XF, XF_INX]; +defvar XFIN64X = [XF_64, XF_INX_64]; +defvar FXIN64X = [FX_64, FX_INX_64]; + // Floating-point rounding mode def FRMArg : AsmOperandClass { @@ -94,62 +161,123 @@ class FPStore_r funct3, string opcodestr, RegisterClass rty, let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, UseNamedOperandTable = 1, hasPostISelHook = 1 in class FPFMA_rrr_frm funct2, string opcodestr, - RegisterClass rty> + DAGOperand rty> : RVInstR4Frm; +multiclass FPFMA_rrr_frm_m funct2, + string opcodestr, list Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPFMA_rrr_frm; +} + class FPFMADynFrmAlias + DAGOperand rty> : InstAlias; +multiclass FPFMADynFrmAlias_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def : FPFMADynFrmAlias(Inst#Ext.Suffix), OpcodeStr, + Ext.Reg>; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in class FPALU_rr funct7, bits<3> funct3, string opcodestr, - RegisterClass rty> + DAGOperand rty> : RVInstR; +multiclass FPALU_rr_m funct7, bits<3> funct3, string opcodestr, + list Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPALU_rr; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, UseNamedOperandTable = 1, hasPostISelHook = 1 in -class FPALU_rr_frm funct7, string opcodestr, RegisterClass rty> +class FPALU_rr_frm funct7, string opcodestr, DAGOperand rty> : RVInstRFrm; +multiclass FPALU_rr_frm_m funct7, string opcodestr, + list Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPALU_rr_frm; +} + class FPALUDynFrmAlias + DAGOperand rty> : InstAlias; +multiclass FPALUDynFrmAlias_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def : FPALUDynFrmAlias(Inst#Ext.Suffix), OpcodeStr, + Ext.Reg>; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in class FPUnaryOp_r funct7, bits<5> rs2val, bits<3> funct3, - RegisterClass rdty, RegisterClass rs1ty, string opcodestr> + DAGOperand rdty, DAGOperand rs1ty, string opcodestr> : RVInstR { let rs2 = rs2val; } +multiclass FPUnaryOp_r_m funct7, bits<5> rs2val, bits<3> funct3, + list Exts, string opcodestr> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPUnaryOp_r; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1, UseNamedOperandTable = 1, hasPostISelHook = 1 in -class FPUnaryOp_r_frm funct7, bits<5> rs2val, RegisterClass rdty, - RegisterClass rs1ty, string opcodestr> +class FPUnaryOp_r_frm funct7, bits<5> rs2val, DAGOperand rdty, + DAGOperand rs1ty, string opcodestr> : RVInstRFrm { let rs2 = rs2val; } +multiclass FPUnaryOp_r_frm_m funct7, bits<5> rs2val, + list Exts, string opcodestr> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPUnaryOp_r_frm; +} class FPUnaryOpDynFrmAlias + DAGOperand rdty, DAGOperand rs1ty> : InstAlias; +multiclass FPUnaryOpDynFrmAlias_m Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates in + def : FPUnaryOpDynFrmAlias(Inst#Ext.Suffix), + OpcodeStr, Ext.RdTy, Ext.Rs1Ty>; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in class FPCmp_rr funct7, bits<3> funct3, string opcodestr, - RegisterClass rty> + DAGOperand rty> : RVInstR; +multiclass FPCmp_rr_m funct7, bits<3> funct3, string opcodestr, + list Exts> { + foreach Ext = Exts in + let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in + def Ext.Suffix : FPCmp_rr; +} //===----------------------------------------------------------------------===// // Instructions @@ -162,101 +290,100 @@ def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>; // reflecting the order these fields are specified in the instruction // encoding. def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>; +} // Predicates = [HasStdExtF] let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in { -def FMADD_S : FPFMA_rrr_frm; -def FMSUB_S : FPFMA_rrr_frm; -def FNMSUB_S : FPFMA_rrr_frm; -def FNMADD_S : FPFMA_rrr_frm; +defm FMADD_S : FPFMA_rrr_frm_m; +defm FMSUB_S : FPFMA_rrr_frm_m; +defm FNMSUB_S : FPFMA_rrr_frm_m; +defm FNMADD_S : FPFMA_rrr_frm_m; +} + +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; + +let SchedRW = [WriteFALU32, ReadFALU32, ReadFALU32] in { +defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX>; +defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>; } +let SchedRW = [WriteFMul32, ReadFMul32, ReadFMul32] in +defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", FINX>; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; - -def FADD_S : FPALU_rr_frm<0b0000000, "fadd.s", FPR32>, - Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; -def FSUB_S : FPALU_rr_frm<0b0000100, "fsub.s", FPR32>, - Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; -def FMUL_S : FPALU_rr_frm<0b0001000, "fmul.s", FPR32>, - Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; -def FDIV_S : FPALU_rr_frm<0b0001100, "fdiv.s", FPR32>, - Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; - -def FSQRT_S : FPUnaryOp_r_frm<0b0101100, 0b00000, FPR32, FPR32, "fsqrt.s">, - Sched<[WriteFSqrt32, ReadFSqrt32]>; -def : FPUnaryOpDynFrmAlias; +let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in +defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", FINX>; + +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; + +defm FSQRT_S : FPUnaryOp_r_frm_m<0b0101100, 0b00000, FFINX, "fsqrt.s">, + Sched<[WriteFSqrt32, ReadFSqrt32]>; +defm : FPUnaryOpDynFrmAlias_m; let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32], mayRaiseFPException = 0 in { -def FSGNJ_S : FPALU_rr<0b0010000, 0b000, "fsgnj.s", FPR32>; -def FSGNJN_S : FPALU_rr<0b0010000, 0b001, "fsgnjn.s", FPR32>; -def FSGNJX_S : FPALU_rr<0b0010000, 0b010, "fsgnjx.s", FPR32>; +defm FSGNJ_S : FPALU_rr_m<0b0010000, 0b000, "fsgnj.s", FINX>; +defm FSGNJN_S : FPALU_rr_m<0b0010000, 0b001, "fsgnjn.s", FINX>; +defm FSGNJX_S : FPALU_rr_m<0b0010000, 0b010, "fsgnjx.s", FINX>; } let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in { -def FMIN_S : FPALU_rr<0b0010100, 0b000, "fmin.s", FPR32>; -def FMAX_S : FPALU_rr<0b0010100, 0b001, "fmax.s", FPR32>; +defm FMIN_S : FPALU_rr_m<0b0010100, 0b000, "fmin.s", FINX>; +defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", FINX>; } -def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, 0b00000, GPR, FPR32, "fcvt.w.s">, - Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; -def : FPUnaryOpDynFrmAlias; - -def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, 0b00001, GPR, FPR32, "fcvt.wu.s">, +defm FCVT_W_S : FPUnaryOp_r_frm_m<0b1100000, 0b00000, XFINX, "fcvt.w.s">, Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; + +defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, XFINX, "fcvt.wu.s">, + Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; +defm : FPUnaryOpDynFrmAlias_m; let mayRaiseFPException = 0 in def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">, Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>; let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in { -def FEQ_S : FPCmp_rr<0b1010000, 0b010, "feq.s", FPR32>; -def FLT_S : FPCmp_rr<0b1010000, 0b001, "flt.s", FPR32>; -def FLE_S : FPCmp_rr<0b1010000, 0b000, "fle.s", FPR32>; +defm FEQ_S : FPCmp_rr_m<0b1010000, 0b010, "feq.s", FINX>; +defm FLT_S : FPCmp_rr_m<0b1010000, 0b001, "flt.s", FINX>; +defm FLE_S : FPCmp_rr_m<0b1010000, 0b000, "fle.s", FINX>; } let mayRaiseFPException = 0 in -def FCLASS_S : FPUnaryOp_r<0b1110000, 0b00000, 0b001, GPR, FPR32, "fclass.s">, - Sched<[WriteFClass32, ReadFClass32]>; - -def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, 0b00000, FPR32, GPR, "fcvt.s.w">, - Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; -def : FPUnaryOpDynFrmAlias; +defm FCLASS_S : FPUnaryOp_r_m<0b1110000, 0b00000, 0b001, XFINX, "fclass.s">, + Sched<[WriteFClass32, ReadFClass32]>; -def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, 0b00001, FPR32, GPR, "fcvt.s.wu">, +defm FCVT_S_W : FPUnaryOp_r_frm_m<0b1101000, 0b00000, FXINX, "fcvt.s.w">, Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; + +defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">, + Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; +defm : FPUnaryOpDynFrmAlias_m; let mayRaiseFPException = 0 in def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">, Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>; -} // Predicates = [HasStdExtF] -let Predicates = [HasStdExtF, IsRV64] in { -def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, 0b00010, GPR, FPR32, "fcvt.l.s">, - Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; -def : FPUnaryOpDynFrmAlias; - -def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, 0b00011, GPR, FPR32, "fcvt.lu.s">, +defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">, Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, 0b00010, FPR32, GPR, "fcvt.s.l">, - Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFIN64X, "fcvt.lu.s">, + Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, 0b00011, FPR32, GPR, "fcvt.s.lu">, +defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXIN64X, "fcvt.s.l">, Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; -def : FPUnaryOpDynFrmAlias; -} // Predicates = [HasStdExtF, IsRV64] +defm : FPUnaryOpDynFrmAlias_m; + +defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXIN64X, "fcvt.s.lu">, + Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; +defm : FPUnaryOpDynFrmAlias_m; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) @@ -315,6 +442,16 @@ def PseudoQuietFLT_S : PseudoQuietFCMP; } } // Predicates = [HasStdExtF] +let Predicates = [HasStdExtZfinx] in { +def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>; +def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S_INX FPR32INX:$rd, FPR32INX:$rs, FPR32INX:$rs)>; + +def : InstAlias<"fgt.s $rd, $rs, $rt", + (FLT_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; +def : InstAlias<"fge.s $rd, $rs, $rt", + (FLE_S_INX GPR:$rd, FPR32INX:$rt, FPR32INX:$rs), 0>; +} // Predicates = [HasStdExtZfinx] + //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td index a2753c1323548..631525484bd9d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -25,6 +25,62 @@ def riscv_fmv_h_x def riscv_fmv_x_anyexth : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>; +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +// Zhinxmin and Zhinx + +def FPR16INX : RegisterOperand { + let ParserMatchClass = GPRAsFPR; + let DecoderMethod = "DecodeGPRRegisterClass"; +} + +def ZfhExt : ExtInfo<0, [HasStdExtZfh]>; +def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>; +def ZfhminExt : ExtInfo<0, [HasStdExtZfhOrZfhmin]>; +def ZhinxExt : ExtInfo<1, [HasStdExtZhinx]>; +def ZhinxminExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>; +def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>; + +def ZfhminDExt : ExtInfo<0, [HasStdExtZfhOrZfhmin, HasStdExtD]>; +def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]>; + +def H : ExtInfo_r; +def H_INX : ExtInfo_r; + +def HH : ExtInfo_rr; +def HH_INX : ExtInfo_rr; +def XH : ExtInfo_rr; +def XH_INX : ExtInfo_rr; +def HX : ExtInfo_rr; +def HX_INX : ExtInfo_rr; +def XH_64 : ExtInfo_rr; +def HX_64 : ExtInfo_rr; +def XH_INX_64 : ExtInfo_rr; +def HX_INX_64 : ExtInfo_rr; +def HFmin : ExtInfo_rr; +def HF_INXmin : ExtInfo_rr; +def HF_INX : ExtInfo_rr; +def FHmin : ExtInfo_rr; +def FH_INXmin : ExtInfo_rr; +def FH_INX : ExtInfo_rr; +def DHmin : ExtInfo_rr; +def DH_INXmin : ExtInfo_rr; +def HDmin : ExtInfo_rr; +def HD_INXmin : ExtInfo_rr; + +defvar HINX = [H, H_INX]; +defvar HHINX = [HH, HH_INX]; +defvar XHINX = [XH, XH_INX]; +defvar HXINX = [HX, HX_INX]; +defvar XHIN64X = [XH_64, XH_INX_64]; +defvar HXIN64X = [HX_64, HX_INX_64]; +defvar HFINXmin = [HFmin, HF_INXmin]; +defvar FHINXmin = [FHmin, FH_INXmin]; +defvar DHINXmin = [DHmin, DH_INXmin]; +defvar HDINXmin = [HDmin, HD_INXmin]; + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -38,74 +94,73 @@ def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>; def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>; } // Predicates = [HasStdExtZfhOrZfhmin] -let Predicates = [HasStdExtZfh] in { let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in { -def FMADD_H : FPFMA_rrr_frm; -def FMSUB_H : FPFMA_rrr_frm; -def FNMSUB_H : FPFMA_rrr_frm; -def FNMADD_H : FPFMA_rrr_frm; +defm FMADD_H : FPFMA_rrr_frm_m; +defm FMSUB_H : FPFMA_rrr_frm_m; +defm FNMSUB_H : FPFMA_rrr_frm_m; +defm FNMADD_H : FPFMA_rrr_frm_m; } -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; -def : FPFMADynFrmAlias; - -def FADD_H : FPALU_rr_frm<0b0000010, "fadd.h", FPR16>, - Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>; -def FSUB_H : FPALU_rr_frm<0b0000110, "fsub.h", FPR16>, - Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>; -def FMUL_H : FPALU_rr_frm<0b0001010, "fmul.h", FPR16>, - Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>; -def FDIV_H : FPALU_rr_frm<0b0001110, "fdiv.h", FPR16>, - Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>; - -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; -def : FPALUDynFrmAlias; - -def FSQRT_H : FPUnaryOp_r_frm<0b0101110, 0b00000, FPR16, FPR16, "fsqrt.h">, - Sched<[WriteFSqrt16, ReadFSqrt16]>; -def : FPUnaryOpDynFrmAlias; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; +defm : FPFMADynFrmAlias_m; + +let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in { +defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX>; +defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>; +} +let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in +defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", HINX>; + +let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in +defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", HINX>; + +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; +defm : FPALUDynFrmAlias_m; + +defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, HHINX, "fsqrt.h">, + Sched<[WriteFSqrt16, ReadFSqrt16]>; +defm : FPUnaryOpDynFrmAlias_m; let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16], mayRaiseFPException = 0 in { -def FSGNJ_H : FPALU_rr<0b0010010, 0b000, "fsgnj.h", FPR16>; -def FSGNJN_H : FPALU_rr<0b0010010, 0b001, "fsgnjn.h", FPR16>; -def FSGNJX_H : FPALU_rr<0b0010010, 0b010, "fsgnjx.h", FPR16>; +defm FSGNJ_H : FPALU_rr_m<0b0010010, 0b000, "fsgnj.h", HINX>; +defm FSGNJN_H : FPALU_rr_m<0b0010010, 0b001, "fsgnjn.h", HINX>; +defm FSGNJX_H : FPALU_rr_m<0b0010010, 0b010, "fsgnjx.h", HINX>; } let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in { -def FMIN_H : FPALU_rr<0b0010110, 0b000, "fmin.h", FPR16>; -def FMAX_H : FPALU_rr<0b0010110, 0b001, "fmax.h", FPR16>; +defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", HINX>; +defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", HINX>; } -def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, 0b00000, GPR, FPR16, "fcvt.w.h">, - Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; -def : FPUnaryOpDynFrmAlias; - -def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, 0b00001, GPR, FPR16, "fcvt.wu.h">, +defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, XHINX, "fcvt.w.h">, Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, 0b00000, FPR16, GPR, "fcvt.h.w">, - Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, XHINX, "fcvt.wu.h">, + Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, 0b00001, FPR16, GPR, "fcvt.h.wu">, +defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, HXINX, "fcvt.h.w">, Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; -def : FPUnaryOpDynFrmAlias; -} // Predicates = [HasStdExtZfh] +defm : FPUnaryOpDynFrmAlias_m; -let Predicates = [HasStdExtZfhOrZfhmin] in { -def FCVT_H_S : FPUnaryOp_r_frm<0b0100010, 0b00000, FPR16, FPR32, "fcvt.h.s">, - Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, HXINX, "fcvt.h.wu">, + Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b00010, 0b000, FPR32, FPR16, "fcvt.s.h">, +defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, HFINXmin, "fcvt.h.s">, + Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; +defm : FPUnaryOpDynFrmAlias_m; + +defm FCVT_S_H : FPUnaryOp_r_m<0b0100000, 0b00010, 0b000, FHINXmin, "fcvt.s.h">, Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>; +let Predicates = [HasStdExtZfhOrZfhmin] in { let mayRaiseFPException = 0 in def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">, Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>; @@ -115,45 +170,38 @@ def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">, Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>; } // Predicates = [HasStdExtZfhOrZfhmin] -let Predicates = [HasStdExtZfh] in { - let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in { -def FEQ_H : FPCmp_rr<0b1010010, 0b010, "feq.h", FPR16>; -def FLT_H : FPCmp_rr<0b1010010, 0b001, "flt.h", FPR16>; -def FLE_H : FPCmp_rr<0b1010010, 0b000, "fle.h", FPR16>; +defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", HINX>; +defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", HINX>; +defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", HINX>; } let mayRaiseFPException = 0 in -def FCLASS_H : FPUnaryOp_r<0b1110010, 0b00000, 0b001, GPR, FPR16, "fclass.h">, - Sched<[WriteFClass16, ReadFClass16]>; -} // Predicates = [HasStdExtZfh] - -let Predicates = [HasStdExtZfh, IsRV64] in { -def FCVT_L_H : FPUnaryOp_r_frm<0b1100010, 0b00010, GPR, FPR16, "fcvt.l.h">, - Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; -def : FPUnaryOpDynFrmAlias; +defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, XHINX, "fclass.h">, + Sched<[WriteFClass16, ReadFClass16]>; -def FCVT_LU_H : FPUnaryOp_r_frm<0b1100010, 0b00011, GPR, FPR16, "fcvt.lu.h">, +defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHIN64X, "fcvt.l.h">, Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; -def : FPUnaryOpDynFrmAlias; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, 0b00010, FPR16, GPR, "fcvt.h.l">, - Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHIN64X, "fcvt.lu.h">, + Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, 0b00011, FPR16, GPR, "fcvt.h.lu">, +defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXIN64X, "fcvt.h.l">, Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; -def : FPUnaryOpDynFrmAlias; -} // Predicates = [HasStdExtZfh, IsRV64] +defm : FPUnaryOpDynFrmAlias_m; -let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in { -def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, 0b00001, FPR16, FPR64, "fcvt.h.d">, - Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>; -def : FPUnaryOpDynFrmAlias; +defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXIN64X, "fcvt.h.lu">, + Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; +defm : FPUnaryOpDynFrmAlias_m; -def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b00010, 0b000, FPR64, FPR16, "fcvt.d.h">, - Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>; -} // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] +defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, HDINXmin, "fcvt.h.d">, + Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>; +defm : FPUnaryOpDynFrmAlias_m; + +defm FCVT_D_H : FPUnaryOp_r_m<0b0100001, 0b00010, 0b000, DHINXmin, "fcvt.d.h">, + Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) @@ -186,6 +234,17 @@ def PseudoQuietFLT_H : PseudoQuietFCMP; } } // Predicates = [HasStdExtZfhOrZfhmin] +let Predicates = [HasStdExtZhinx] in { +def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; +def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; +def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; + +def : InstAlias<"fgt.h $rd, $rs, $rt", + (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; +def : InstAlias<"fge.h $rd, $rs, $rt", + (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; +} // Predicates = [HasStdExtZhinx] + //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 8c1c03b51c249..b06af3787b5d3 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -66,6 +66,7 @@ def sub_vrm1_5 : ComposedSubRegIndex; def sub_vrm1_6 : ComposedSubRegIndex; def sub_vrm1_7 : ComposedSubRegIndex; +def sub_32_hi : SubRegIndex<32, 32>; } // Namespace = "RISCV" // Integer registers @@ -534,6 +535,35 @@ def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { let Size = 64; } +let RegInfos = XLenRI in { +def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; +def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +} // RegInfos = XLenRI + +let RegAltNameIndices = [ABIRegAltName] in { + foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, + 24, 26, 28, 30] in { + defvar Reg = !cast("X"#Index); + def X#Index#_PD : RISCVRegWithSubRegs("X"#Index), + !cast("X"#!add(Index, 1))], + Reg.AltNames> { + let SubRegIndices = [sub_32, sub_32_hi]; + } + } +} + +let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add + X10_PD, X12_PD, X14_PD, X16_PD, + X6_PD, + X28_PD, X30_PD, + X8_PD, + X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, + X0_PD, X2_PD, X4_PD +)>; + // The register class is added for inline assembly for vector mask types. def VM : VReg&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s # Out of range immediates ## fencearg @@ -172,6 +172,10 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) +fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer) +fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer) +fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer) flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}} sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) diff --git a/llvm/test/MC/RISCV/rv32zdinx-invalid.s b/llvm/test/MC/RISCV/rv32zdinx-invalid.s new file mode 100644 index 0000000000000..54dd4bbfb308a --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zdinx-invalid.s @@ -0,0 +1,27 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+zdinx %s 2>&1 | FileCheck %s + +# Unsupport Odd Registers in RV32 +fadd.d a0, a1, a2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction + +# Not support float registers +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point) + +# Invalid instructions +fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction +fmv.x.w s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + +# Invalid register names +fadd.d a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction +fsgnjn.d a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction + +# Rounding mode when a register is expected +fmadd.d x10, x12, x14, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction + +# Invalid rounding modes +fmadd.d x10, x12, x14, x16, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fmsub.d x10, x12, x14, x16, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fnmsub.d x10, x12, x14, x16, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic + +# FP registers where integer regs are expected +fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zdinx-valid.s b/llvm/test/MC/RISCV/rv32zdinx-valid.s new file mode 100644 index 0000000000000..660116bc9a555 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zdinx-valid.s @@ -0,0 +1,124 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zdinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zdinx %s \ +# RUN: | llvm-objdump --mattr=+zdinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zdinx %s \ +# RUN: | llvm-objdump --mattr=+zdinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, dyn +# CHECK-ASM: encoding: [0x43,0x75,0xe6,0x82] +fmadd.d x10, x12, x14, x16, dyn +# CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, dyn +# CHECK-ASM: encoding: [0x47,0x75,0xe6,0x82] +fmsub.d x10, x12, x14, x16, dyn +# CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, dyn +# CHECK-ASM: encoding: [0x4b,0x75,0xe6,0x82] +fnmsub.d x10, x12, x14, x16, dyn +# CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, dyn +# CHECK-ASM: encoding: [0x4f,0x75,0xe6,0x82] +fnmadd.d x10, x12, x14, x16, dyn + +# CHECK-ASM-AND-OBJ: fadd.d s10, t3, t5, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x03] +fadd.d x26, x28, x30, dyn +# CHECK-ASM-AND-OBJ: fsub.d s10, t3, t5, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x0b] +fsub.d x26, x28, x30, dyn +# CHECK-ASM-AND-OBJ: fmul.d s10, t3, t5, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x13] +fmul.d x26, x28, x30, dyn +# CHECK-ASM-AND-OBJ: fdiv.d s10, t3, t5, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x1b] +fdiv.d x26, x28, x30, dyn +# CHECK-ASM-AND-OBJ: fsqrt.d s4, s6, dyn +# CHECK-ASM: encoding: [0x53,0x7a,0x0b,0x5a] +fsqrt.d x20, x22, dyn +# CHECK-ASM-AND-OBJ: fsgnj.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x23] +fsgnj.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fsgnjn.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x23] +fsgnjn.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fsgnjx.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x2d,0xee,0x23] +fsgnjx.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fmin.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x2b] +fmin.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fmax.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x2b] +fmax.d x26, x28, x30 + +# CHECK-ASM-AND-OBJ: fcvt.s.d s10, t3, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0x1e,0x40] +fcvt.s.d x26, x28, dyn +# CHECK-ASM-AND-OBJ: fcvt.d.s s10, t3 +# CHECK-ASM: encoding: [0x53,0x0d,0x0e,0x42] +fcvt.d.s x26, x28 +# CHECK-ASM-AND-OBJ: feq.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x2d,0xee,0xa3] +feq.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: flt.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x1d,0xee,0xa3] +flt.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fle.d s10, t3, t5 +# CHECK-ASM: encoding: [0x53,0x0d,0xee,0xa3] +fle.d x26, x28, x30 +# CHECK-ASM-AND-OBJ: fclass.d s10, t3 +# CHECK-ASM: encoding: [0x53,0x1d,0x0e,0xe2] +fclass.d x26, x28 + +# CHECK-ASM-AND-OBJ: fcvt.w.d s4, s6, dyn +# CHECK-ASM: encoding: [0x53,0x7a,0x0b,0xc2] +fcvt.w.d x20, x22, dyn +# CHECK-ASM-AND-OBJ: fcvt.d.w s10, t3 +# CHECK-ASM: encoding: [0x53,0x0d,0x0e,0xd2] +fcvt.d.w x26, x28 +# CHECK-ASM-AND-OBJ: fcvt.d.wu s10, t3 +# CHECK-ASM: encoding: [0x53,0x0d,0x1e,0xd2] +fcvt.d.wu x26, x28 + +# Rounding modes + +# CHECK-ASM-AND-OBJ: fmadd.d a0, a2, a4, a6, rne +# CHECK-ASM: encoding: [0x43,0x05,0xe6,0x82] +fmadd.d x10, x12, x14, x16, rne +# CHECK-ASM-AND-OBJ: fmsub.d a0, a2, a4, a6, rtz +# CHECK-ASM: encoding: [0x47,0x15,0xe6,0x82] +fmsub.d x10, x12, x14, x16, rtz +# CHECK-ASM-AND-OBJ: fnmsub.d a0, a2, a4, a6, rdn +# CHECK-ASM: encoding: [0x4b,0x25,0xe6,0x82] +fnmsub.d x10, x12, x14, x16, rdn +# CHECK-ASM-AND-OBJ: fnmadd.d a0, a2, a4, a6, rup +# CHECK-ASM: encoding: [0x4f,0x35,0xe6,0x82] +fnmadd.d x10, x12, x14, x16, rup + +# CHECK-ASM-AND-OBJ: fadd.d s10, t3, t5, rmm +# CHECK-ASM: encoding: [0x53,0x4d,0xee,0x03] +fadd.d x26, x28, x30, rmm +# CHECK-ASM-AND-OBJ: fsub.d s10, t3, t5, dyn +# CHECK-ASM: encoding: [0x53,0x7d,0xee,0x0b] +fsub.d x26, x28, x30, dyn +# CHECK-ASM-AND-OBJ: fmul.d s10, t3, t5, rne +# CHECK-ASM: encoding: [0x53,0x0d,0xee,0x13] +fmul.d x26, x28, x30, rne +# CHECK-ASM-AND-OBJ: fdiv.d s10, t3, t5, rtz +# CHECK-ASM: encoding: [0x53,0x1d,0xee,0x1b] +fdiv.d x26, x28, x30, rtz + +# CHECK-ASM-AND-OBJ: fsqrt.d s4, s6, rdn +# CHECK-ASM: encoding: [0x53,0x2a,0x0b,0x5a] +fsqrt.d x20, x22, rdn +# CHECK-ASM-AND-OBJ: fcvt.s.d s4, s6, rup +# CHECK-ASM: encoding: [0x53,0x3a,0x1b,0x40] +fcvt.s.d x20, x22, rup +# CHECK-ASM-AND-OBJ: fcvt.w.d s4, s6, rmm +# CHECK-ASM: encoding: [0x53,0x4a,0x0b,0xc2] +fcvt.w.d x20, x22, rmm +# CHECK-ASM-AND-OBJ: fcvt.wu.d s4, s6, dyn +# CHECK-ASM: encoding: [0x53,0x7a,0x1b,0xc2] +fcvt.wu.d x20, x22, dyn diff --git a/llvm/test/MC/RISCV/rv32zfinx-invalid.s b/llvm/test/MC/RISCV/rv32zfinx-invalid.s new file mode 100644 index 0000000000000..b3712875673b1 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zfinx-invalid.s @@ -0,0 +1,25 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+zfinx %s 2>&1 | FileCheck %s + +# Not support float registers +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) + +# Invalid instructions +fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction +fmv.x.w s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer) + +# Invalid register names +fadd.d a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction +fsgnjn.s a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction + +# Rounding mode when a register is expected +fmadd.s x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction + +# Invalid rounding modes +fmadd.s x10, x11, x12, x13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fmsub.s x14, x15, x16, x17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fnmsub.s x18, x19, x20, x21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic + +# Using 'Zdinx' instructions for an 'Zfinx'-only target +fadd.d t0, t1, t2 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zfinx-valid.s b/llvm/test/MC/RISCV/rv32zfinx-valid.s new file mode 100644 index 0000000000000..58f805c9fce71 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zfinx-valid.s @@ -0,0 +1,128 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfinx %s \ +# RUN: | llvm-objdump --mattr=+zfinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfinx %s \ +# RUN: | llvm-objdump --mattr=+zfinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, dyn +# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x68] +fmadd.s x10, x11, x12, x13, dyn +# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7, dyn +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89] +fmsub.s x14, x15, x16, x17, dyn +# CHECK-ASM-AND-OBJ: fnmsub.s s2, s3, s4, s5, dyn +# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xa9] +fnmsub.s x18, x19, x20, x21, dyn +# CHECK-ASM-AND-OBJ: fnmadd.s s6, s7, s8, s9, dyn +# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xc9] +fnmadd.s x22, x23, x24, x25, dyn + +# CHECK-ASM-AND-OBJ: fadd.s s10, s11, t3, dyn +# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x01] +fadd.s x26, x27, x28, dyn +# CHECK-ASM-AND-OBJ: fsub.s t4, t5, t6, dyn +# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x09] +fsub.s x29, x30, x31, dyn +# CHECK-ASM-AND-OBJ: fmul.s s0, s1, s2, dyn +# CHECK-ASM: encoding: [0x53,0xf4,0x24,0x11] +fmul.s s0, s1, s2, dyn +# CHECK-ASM-AND-OBJ: fdiv.s s3, s4, s5, dyn +# CHECK-ASM: encoding: [0xd3,0x79,0x5a,0x19] +fdiv.s s3, s4, s5, dyn +# CHECK-ASM-AND-OBJ: fsqrt.s t1, t2, dyn +# CHECK-ASM: encoding: [0x53,0xf3,0x03,0x58] +fsqrt.s t1, t2, dyn +# CHECK-ASM-AND-OBJ: fsgnj.s s1, a0, a1 +# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x20] +fsgnj.s s1, a0, a1 +# CHECK-ASM-AND-OBJ: fsgnjn.s a1, a3, a4 +# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x20] +fsgnjn.s a1, a3, a4 +# CHECK-ASM-AND-OBJ: fsgnjx.s a4, a3, a2 +# CHECK-ASM: encoding: [0x53,0xa7,0xc6,0x20] +fsgnjx.s a4, a3, a2 +# CHECK-ASM-AND-OBJ: fmin.s a5, a6, a7 +# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x29] +fmin.s a5, a6, a7 +# CHECK-ASM-AND-OBJ: fmax.s s2, s3, s4 +# CHECK-ASM: encoding: [0x53,0x99,0x49,0x29] +fmax.s s2, s3, s4 +# CHECK-ASM-AND-OBJ: fcvt.w.s a0, s5, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x0a,0xc0] +fcvt.w.s a0, s5, dyn +# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x1b,0xc0] +fcvt.wu.s a1, s6, dyn +# CHECK-ASM-AND-OBJ: feq.s a1, s8, s9 +# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa1] +feq.s a1, s8, s9 +# CHECK-ASM-AND-OBJ: flt.s a2, s10, s11 +# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa1] +flt.s a2, s10, s11 +# CHECK-ASM-AND-OBJ: fle.s a3, t3, t4 +# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa1] +fle.s a3, t3, t4 +# CHECK-ASM-AND-OBJ: fclass.s a3, t5 +# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe0] +fclass.s a3, t5 +# CHECK-ASM-AND-OBJ: fcvt.s.w t6, a4, dyn +# CHECK-ASM: encoding: [0xd3,0x7f,0x07,0xd0] +fcvt.s.w t6, a4, dyn +# CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, dyn +# CHECK-ASM: encoding: [0x53,0xf4,0x17,0xd0] +fcvt.s.wu s0, a5, dyn + +# Rounding modes + +# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, rne +# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] +fmadd.s x10, x11, x12, x13, rne +# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7, rtz +# CHECK-ASM: encoding: [0x47,0x97,0x07,0x89] +fmsub.s x14, x15, x16, x17, rtz +# CHECK-ASM-AND-OBJ: fnmsub.s s2, s3, s4, s5, rdn +# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xa9] +fnmsub.s x18, x19, x20, x21, rdn +# CHECK-ASM-AND-OBJ: fnmadd.s s6, s7, s8, s9, rup +# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xc9] +fnmadd.s x22, x23, x24, x25, rup +# CHECK-ASM-AND-OBJ: fmadd.s a0, a1, a2, a3, rmm +# CHECK-ASM: encoding: [0x43,0xc5,0xc5,0x68] +fmadd.s x10, x11, x12, x13, rmm +# CHECK-ASM-AND-OBJ: fmsub.s a4, a5, a6, a7 +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89] +fmsub.s x14, x15, x16, x17, dyn + +# CHECK-ASM-AND-OBJ: fadd.s s10, s11, t3, rne +# CHECK-ASM: encoding: [0x53,0x8d,0xcd,0x01] +fadd.s x26, x27, x28, rne +# CHECK-ASM-AND-OBJ: fsub.s t4, t5, t6, rtz +# CHECK-ASM: encoding: [0xd3,0x1e,0xff,0x09] +fsub.s x29, x30, x31, rtz +# CHECK-ASM-AND-OBJ: fmul.s s0, s1, s2, rdn +# CHECK-ASM: encoding: [0x53,0xa4,0x24,0x11] +fmul.s s0, s1, s2, rdn +# CHECK-ASM-AND-OBJ: fdiv.s s3, s4, s5, rup +# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x19] +fdiv.s s3, s4, s5, rup + +# CHECK-ASM-AND-OBJ: fsqrt.s t1, t2, rmm +# CHECK-ASM: encoding: [0x53,0xc3,0x03,0x58] +fsqrt.s t1, t2, rmm +# CHECK-ASM-AND-OBJ: fcvt.w.s a0, s5, rup +# CHECK-ASM: encoding: [0x53,0xb5,0x0a,0xc0] +fcvt.w.s a0, s5, rup +# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, s6, rdn +# CHECK-ASM: encoding: [0xd3,0x25,0x1b,0xc0] +fcvt.wu.s a1, s6, rdn +# CHECK-ASM-AND-OBJ: fcvt.s.w t6, a4, rtz +# CHECK-ASM: encoding: [0xd3,0x1f,0x07,0xd0] +fcvt.s.w t6, a4, rtz +# CHECK-ASM-AND-OBJ: fcvt.s.wu s0, a5, rne +# CHECK-ASM: encoding: [0x53,0x84,0x17,0xd0] +fcvt.s.wu s0, a5, rne diff --git a/llvm/test/MC/RISCV/rv32zhinx-invalid.s b/llvm/test/MC/RISCV/rv32zhinx-invalid.s new file mode 100644 index 0000000000000..2ab1dee8d08a5 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zhinx-invalid.s @@ -0,0 +1,24 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+zhinx %s 2>&1 | FileCheck %s + +# Not support float registers +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) + +# Invalid instructions +fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction +fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + +# Invalid register names +fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction +fsgnjn.h a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction + +# Rounding mode when a register is expected +fmadd.h x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction + +# Invalid rounding modes +fmadd.h x10, x11, x12, x13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fmsub.h x14, x15, x16, x17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic +fnmsub.h x18, x19, x20, x21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic + +# FP registers where integer regs are expected +fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zhinx-valid.s b/llvm/test/MC/RISCV/rv32zhinx-valid.s new file mode 100644 index 0000000000000..97ec9dd1a34f8 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zhinx-valid.s @@ -0,0 +1,128 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zhinx %s \ +# RUN: | llvm-objdump --mattr=+zhinx -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zhinx %s \ +# RUN: | llvm-objdump --mattr=+zhinx -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, dyn +# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x6c] +fmadd.h x10, x11, x12, x13, dyn +# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7, dyn +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x8d] +fmsub.h x14, x15, x16, x17, dyn +# CHECK-ASM-AND-OBJ: fnmsub.h s2, s3, s4, s5, dyn +# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xad] +fnmsub.h x18, x19, x20, x21, dyn +# CHECK-ASM-AND-OBJ: fnmadd.h s6, s7, s8, s9, dyn +# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xcd] +fnmadd.h x22, x23, x24, x25, dyn + +# CHECK-ASM-AND-OBJ: fadd.h s10, s11, t3, dyn +# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x05] +fadd.h x26, x27, x28, dyn +# CHECK-ASM-AND-OBJ: fsub.h t4, t5, t6, dyn +# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x0d] +fsub.h x29, x30, x31, dyn +# CHECK-ASM-AND-OBJ: fmul.h s0, s1, s2, dyn +# CHECK-ASM: encoding: [0x53,0xf4,0x24,0x15] +fmul.h s0, s1, s2, dyn +# CHECK-ASM-AND-OBJ: fdiv.h s3, s4, s5, dyn +# CHECK-ASM: encoding: [0xd3,0x79,0x5a,0x1d] +fdiv.h s3, s4, s5, dyn +# CHECK-ASM-AND-OBJ: fsqrt.h s6, s7, dyn +# CHECK-ASM: encoding: [0x53,0xfb,0x0b,0x5c] +fsqrt.h s6, s7, dyn +# CHECK-ASM-AND-OBJ: fsgnj.h s1, a0, a1 +# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x24] +fsgnj.h x9, x10, x11 +# CHECK-ASM-AND-OBJ: fsgnjn.h a1, a3, a4 +# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x24] +fsgnjn.h x11, x13, x14 +# CHECK-ASM-AND-OBJ: fsgnjx.h a4, a3, a2 +# CHECK-ASM: encoding: [0x53,0xa7,0xc6,0x24] +fsgnjx.h x14, x13, x12 +# CHECK-ASM-AND-OBJ: fmin.h a5, a6, a7 +# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x2d] +fmin.h x15, x16, x17 +# CHECK-ASM-AND-OBJ: fmax.h s2, s3, s4 +# CHECK-ASM: encoding: [0x53,0x99,0x49,0x2d] +fmax.h x18, x19, x20 +# CHECK-ASM-AND-OBJ: fcvt.w.h a0, s5, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x0a,0xc4] +fcvt.w.h x10, x21, dyn +# CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x1b,0xc4] +fcvt.wu.h x11, x22, dyn +# CHECK-ASM-AND-OBJ: feq.h a1, s8, s9 +# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa5] +feq.h x11, x24, x25 +# CHECK-ASM-AND-OBJ: flt.h a2, s10, s11 +# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa5] +flt.h x12, x26, x27 +# CHECK-ASM-AND-OBJ: fle.h a3, t3, t4 +# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa5] +fle.h x13, x28, x29 +# CHECK-ASM-AND-OBJ: fclass.h a3, t5 +# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe4] +fclass.h x13, x30 +# CHECK-ASM-AND-OBJ: fcvt.h.w t6, a4, dyn +# CHECK-ASM: encoding: [0xd3,0x7f,0x07,0xd4] +fcvt.h.w x31, x14, dyn +# CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, dyn +# CHECK-ASM: encoding: [0x53,0xf4,0x17,0xd4] +fcvt.h.wu s0, x15, dyn + +# Rounding modes + +# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, rne +# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x6c] +fmadd.h x10, x11, x12, x13, rne +# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7, rtz +# CHECK-ASM: encoding: [0x47,0x97,0x07,0x8d] +fmsub.h x14, x15, x16, x17, rtz +# CHECK-ASM-AND-OBJ: fnmsub.h s2, s3, s4, s5, rdn +# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xad] +fnmsub.h x18, x19, x20, x21, rdn +# CHECK-ASM-AND-OBJ: fnmadd.h s6, s7, s8, s9, rup +# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xcd] +fnmadd.h x22, x23, x24, x25, rup +# CHECK-ASM-AND-OBJ: fmadd.h a0, a1, a2, a3, rmm +# CHECK-ASM: encoding: [0x43,0xc5,0xc5,0x6c] +fmadd.h x10, x11, x12, x13, rmm +# CHECK-ASM-AND-OBJ: fmsub.h a4, a5, a6, a7 +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x8d] +fmsub.h x14, x15, x16, x17, dyn + +# CHECK-ASM-AND-OBJ: fadd.h s10, s11, t3, rne +# CHECK-ASM: encoding: [0x53,0x8d,0xcd,0x05] +fadd.h x26, x27, x28, rne +# CHECK-ASM-AND-OBJ: fsub.h t4, t5, t6, rtz +# CHECK-ASM: encoding: [0xd3,0x1e,0xff,0x0d] +fsub.h x29, x30, x31, rtz +# CHECK-ASM-AND-OBJ: fmul.h s0, s1, s2, rdn +# CHECK-ASM: encoding: [0x53,0xa4,0x24,0x15] +fmul.h s0, s1, s2, rdn +# CHECK-ASM-AND-OBJ: fdiv.h s3, s4, s5, rup +# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x1d] +fdiv.h s3, s4, s5, rup + +# CHECK-ASM-AND-OBJ: fsqrt.h s6, s7, rmm +# CHECK-ASM: encoding: [0x53,0xcb,0x0b,0x5c] +fsqrt.h s6, s7, rmm +# CHECK-ASM-AND-OBJ: fcvt.w.h a0, s5, rup +# CHECK-ASM: encoding: [0x53,0xb5,0x0a,0xc4] +fcvt.w.h x10, x21, rup +# CHECK-ASM-AND-OBJ: fcvt.wu.h a1, s6, rdn +# CHECK-ASM: encoding: [0xd3,0x25,0x1b,0xc4] +fcvt.wu.h x11, x22, rdn +# CHECK-ASM-AND-OBJ: fcvt.h.w t6, a4, rtz +# CHECK-ASM: encoding: [0xd3,0x1f,0x07,0xd4] +fcvt.h.w x31, x14, rtz +# CHECK-ASM-AND-OBJ: fcvt.h.wu s0, a5, rne +# CHECK-ASM: encoding: [0x53,0x84,0x17,0xd4] +fcvt.h.wu s0, a5, rne diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s new file mode 100644 index 0000000000000..ebfd8a58562e3 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+zhinxmin %s 2>&1 | FileCheck %s + +# Not support float registers +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) + +# Invalid instructions +fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction +fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + +# Invalid register names +fcvt.h.s a100, a1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction + +# Valid in Zhinx +fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer) diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-valid.s b/llvm/test/MC/RISCV/rv32zhinxmin-valid.s new file mode 100644 index 0000000000000..536c0bdfe2b91 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zhinxmin-valid.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinxmin -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinxmin -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zhinxmin %s \ +# RUN: | llvm-objdump --mattr=+zhinxmin -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zhinxmin %s \ +# RUN: | llvm-objdump --mattr=+zhinxmin -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fcvt.s.h a0, a1 +# CHECK-ASM: encoding: [0x53,0x85,0x25,0x40] +fcvt.s.h a0, a1 + +# CHECK-ASM-AND-OBJ: fcvt.h.s a0, a1, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x05,0x44] +fcvt.h.s a0, a1 diff --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s new file mode 100644 index 0000000000000..8ba06963a553e --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s + +# Invalid Instructions +fmv.x.d t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +fmv.d.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zdinx-valid.s b/llvm/test/MC/RISCV/rv64zdinx-valid.s new file mode 100644 index 0000000000000..1e6e430686d01 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zdinx-valid.s @@ -0,0 +1,43 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zdinx %s \ +# RUN: | llvm-objdump --mattr=+zdinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -mattr=+zdinx %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-ASM-AND-OBJ: fcvt.l.d a0, t0, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc2] +# CHECK-RV32: :[[#@LINE+1]]:14: error: invalid operand for instruction +fcvt.l.d a0, t0, dyn +# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, t1, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc2] +# CHECK-RV32: :[[#@LINE+1]]:15: error: invalid operand for instruction +fcvt.lu.d a1, t1, dyn +# CHECK-ASM-AND-OBJ: fcvt.d.l t3, a3, dyn +# CHECK-ASM: encoding: [0x53,0xfe,0x26,0xd2] +# CHECK-RV32: :[[#@LINE+1]]:10: error: invalid operand for instruction +fcvt.d.l t3, a3, dyn +# CHECK-ASM-AND-OBJ: fcvt.d.lu t4, a4, dyn +# CHECK-ASM: encoding: [0xd3,0x7e,0x37,0xd2] +# CHECK-RV32: :[[#@LINE+1]]:11: error: invalid operand for instruction +fcvt.d.lu t4, a4, dyn + +# Rounding modes +# CHECK-ASM-AND-OBJ: fcvt.d.l t3, a3, rne +# CHECK-ASM: encoding: [0x53,0x8e,0x26,0xd2] +# CHECK-RV32: :[[#@LINE+1]]:10: error: invalid operand for instruction +fcvt.d.l t3, a3, rne +# CHECK-ASM-AND-OBJ: fcvt.d.lu t4, a4, rtz +# CHECK-ASM: encoding: [0xd3,0x1e,0x37,0xd2] +# CHECK-RV32: :[[#@LINE+1]]:11: error: invalid operand for instruction +fcvt.d.lu t4, a4, rtz +# CHECK-ASM-AND-OBJ: fcvt.l.d a0, t0, rdn +# CHECK-ASM: encoding: [0x53,0xa5,0x22,0xc2] +# CHECK-RV32: :[[#@LINE+1]]:14: error: invalid operand for instruction +fcvt.l.d a0, t0, rdn +# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, t1, rup +# CHECK-ASM: encoding: [0xd3,0x35,0x33,0xc2] +# CHECK-RV32: :[[#@LINE+1]]:15: error: invalid operand for instruction +fcvt.lu.d a1, t1, rup diff --git a/llvm/test/MC/RISCV/rv64zfinx-invalid.s b/llvm/test/MC/RISCV/rv64zfinx-invalid.s new file mode 100644 index 0000000000000..5815a85cdf0ea --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zfinx-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s + +# Invalid instructions +fmv.x.w t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +fmv.w.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zfinx-valid.s b/llvm/test/MC/RISCV/rv64zfinx-valid.s new file mode 100644 index 0000000000000..1a3e787e0d316 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zfinx-valid.s @@ -0,0 +1,43 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfinx %s \ +# RUN: | llvm-objdump --mattr=+zfinx -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -mattr=+zfinx %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-ASM-AND-OBJ: fcvt.l.s a0, t0, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.l.s a0, t0, dyn +# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, t1, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.lu.s a1, t1, dyn +# CHECK-ASM-AND-OBJ: fcvt.s.l t2, a2, dyn +# CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.s.l t2, a2, dyn +# CHECK-ASM-AND-OBJ: fcvt.s.lu t3, a3, dyn +# CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.s.lu t3, a3, dyn + +# Rounding modes +# CHECK-ASM-AND-OBJ: fcvt.l.s a4, t4, rne +# CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.l.s a4, t4, rne +# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, t5, rtz +# CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.lu.s a5, t5, rtz +# CHECK-ASM-AND-OBJ: fcvt.s.l t6, a6, rdn +# CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.s.l t6, a6, rdn +# CHECK-ASM-AND-OBJ: fcvt.s.lu s7, a7, rup +# CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd0] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.s.lu s7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s new file mode 100644 index 0000000000000..90fb08b5af7c2 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s + +# Invalid instructions +fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zhinx-valid.s b/llvm/test/MC/RISCV/rv64zhinx-valid.s new file mode 100644 index 0000000000000..57e47194632fd --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zhinx-valid.s @@ -0,0 +1,43 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zhinx %s \ +# RUN: | llvm-objdump --mattr=+zhinx -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -mattr=+zhinx %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-ASM-AND-OBJ: fcvt.l.h a0, t0, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.l.h a0, t0, dyn +# CHECK-ASM-AND-OBJ: fcvt.lu.h a1, t1, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.lu.h a1, t1, dyn +# CHECK-ASM-AND-OBJ: fcvt.h.l t2, a2, dyn +# CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.h.l t2, a2, dyn +# CHECK-ASM-AND-OBJ: fcvt.h.lu t3, a3, dyn +# CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.h.lu t3, a3, dyn + +# Rounding modes +# CHECK-ASM-AND-OBJ: fcvt.l.h a4, t4, rne +# CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.l.h a4, t4, rne +# CHECK-ASM-AND-OBJ: fcvt.lu.h a5, t5, rtz +# CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.lu.h a5, t5, rtz +# CHECK-ASM-AND-OBJ: fcvt.h.l t6, a6, rdn +# CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.h.l t6, a6, rdn +# CHECK-ASM-AND-OBJ: fcvt.h.lu s7, a7, rup +# CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd4] +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +fcvt.h.lu s7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s new file mode 100644 index 0000000000000..9a7e8b0c675d7 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s + +# Invalid instructions +fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +fcvt.h.d a0, fa2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-valid.s b/llvm/test/MC/RISCV/rv64zhinxmin-valid.s new file mode 100644 index 0000000000000..54f32e7a07b50 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zhinxmin-valid.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx,+zdinx -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zhinx,+zdinx %s \ +# RUN: | llvm-objdump --mattr=+zhinx,+zdinx -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fcvt.d.h a0, a2 +# CHECK-ASM: encoding: [0x53,0x05,0x26,0x42] +fcvt.d.h a0, a2 + +# CHECK-ASM-AND-OBJ: fcvt.h.d a0, a2, dyn +# CHECK-ASM: encoding: [0x53,0x75,0x16,0x44] +fcvt.h.d a0, a2, dyn diff --git a/llvm/test/MC/RISCV/rvzdinx-aliases-valid.s b/llvm/test/MC/RISCV/rvzdinx-aliases-valid.s new file mode 100644 index 0000000000000..3262c88e92816 --- /dev/null +++ b/llvm/test/MC/RISCV/rvzdinx-aliases-valid.s @@ -0,0 +1,49 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zdinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zdinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zdinx %s \ +# RUN: | llvm-objdump -d --mattr=+zdinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zdinx %s \ +# RUN: | llvm-objdump -d --mattr=+zdinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zdinx %s \ +# RUN: | llvm-objdump -d --mattr=+zdinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zdinx %s \ +# RUN: | llvm-objdump -d --mattr=+zdinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s + +##===----------------------------------------------------------------------===## +## Aliases which omit the rounding mode. +##===----------------------------------------------------------------------===## + +# CHECK-INST: fmadd.d a0, a2, a4, a6, dyn +# CHECK-ALIAS: fmadd.d a0, a2, a4, a6 +fmadd.d x10, x12, x14, x16 +# CHECK-INST: fmsub.d a0, a2, a4, a6, dyn +# CHECK-ALIAS: fmsub.d a0, a2, a4, a6 +fmsub.d x10, x12, x14, x16 +# CHECK-INST: fnmsub.d a0, a2, a4, a6, dyn +# CHECK-ALIAS: fnmsub.d a0, a2, a4, a6 +fnmsub.d x10, x12, x14, x16 +# CHECK-INST: fnmadd.d a0, a2, a4, a6, dyn +# CHECK-ALIAS: fnmadd.d a0, a2, a4, a6 +fnmadd.d x10, x12, x14, x16 +# CHECK-INST: fadd.d a0, a2, a4, dyn +# CHECK-ALIAS: fadd.d a0, a2, a4 +fadd.d x10, x12, x14 +# CHECK-INST: fsub.d a0, a2, a4, dyn +# CHECK-ALIAS: fsub.d a0, a2, a4 +fsub.d x10, x12, x14 +# CHECK-INST: fmul.d a0, a2, a4, dyn +# CHECK-ALIAS: fmul.d a0, a2, a4 +fmul.d x10, x12, x14 +# CHECK-INST: fdiv.d a0, a2, a4, dyn +# CHECK-ALIAS: fdiv.d a0, a2, a4 +fdiv.d x10, x12, x14 diff --git a/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s b/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s new file mode 100644 index 0000000000000..71e9977404d7a --- /dev/null +++ b/llvm/test/MC/RISCV/rvzfinx-aliases-valid.s @@ -0,0 +1,82 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \ +# RUN: | llvm-objdump -d --mattr=+zfinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zfinx %s \ +# RUN: | llvm-objdump -d --mattr=+zfinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \ +# RUN: | llvm-objdump -d --mattr=+zfinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zfinx %s \ +# RUN: | llvm-objdump -d --mattr=+zfinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s + +##===----------------------------------------------------------------------===## +## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) +##===----------------------------------------------------------------------===## + +# CHECK-INST: fsgnjx.s s1, s2, s2 +# CHECK-ALIAS: fabs.s s1, s2 +fabs.s s1, s2 +# CHECK-INST: fsgnjn.s s2, s3, s3 +# CHECK-ALIAS: fneg.s s2, s3 +fneg.s s2, s3 + +# CHECK-INST: flt.s tp, s6, s5 +# CHECK-ALIAS: flt.s tp, s6, s5 +fgt.s x4, s5, s6 +# CHECK-INST: fle.s t2, s1, s0 +# CHECK-ALIAS: fle.s t2, s1, s0 +fge.s x7, x8, x9 + +##===----------------------------------------------------------------------===## +## Aliases which omit the rounding mode. +##===----------------------------------------------------------------------===## + +# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn +# CHECK-ALIAS: fmadd.s a0, a1, a2, a3 +fmadd.s x10, x11, x12, x13 +# CHECK-INST: fmsub.s a4, a5, a6, a7, dyn +# CHECK-ALIAS: fmsub.s a4, a5, a6, a7 +fmsub.s x14, x15, x16, x17 +# CHECK-INST: fnmsub.s s2, s3, s4, s5, dyn +# CHECK-ALIAS: fnmsub.s s2, s3, s4, s5 +fnmsub.s x18, x19, x20, x21 +# CHECK-INST: fnmadd.s s6, s7, s8, s9, dyn +# CHECK-ALIAS: fnmadd.s s6, s7, s8, s9 +fnmadd.s x22, x23, x24, x25 +# CHECK-INST: fadd.s s10, s11, t3, dyn +# CHECK-ALIAS: fadd.s s10, s11, t3 +fadd.s x26, x27, x28 +# CHECK-INST: fsub.s t4, t5, t6, dyn +# CHECK-ALIAS: fsub.s t4, t5, t6 +fsub.s x29, x30, x31 +# CHECK-INST: fmul.s s0, s1, s2, dyn +# CHECK-ALIAS: fmul.s s0, s1, s2 +fmul.s s0, s1, s2 +# CHECK-INST: fdiv.s s3, s4, s5, dyn +# CHECK-ALIAS: fdiv.s s3, s4, s5 +fdiv.s s3, s4, s5 +# CHECK-INST: sqrt.s s6, s7, dyn +# CHECK-ALIAS: sqrt.s s6, s7 +fsqrt.s s6, s7 +# CHECK-INST: fcvt.w.s a0, s5, dyn +# CHECK-ALIAS: fcvt.w.s a0, s5 +fcvt.w.s a0, s5 +# CHECK-INST: fcvt.wu.s a1, s6, dyn +# CHECK-ALIAS: fcvt.wu.s a1, s6 +fcvt.wu.s a1, s6 +# CHECK-INST: fcvt.s.w t6, a4, dyn +# CHECK-ALIAS: fcvt.s.w t6, a4 +fcvt.s.w t6, a4 +# CHECK-INST: fcvt.s.wu s0, a5, dyn +# CHECK-ALIAS: fcvt.s.wu s0, a5 +fcvt.s.wu s0, a5 diff --git a/llvm/test/MC/RISCV/rvzhinx-aliases-valid.s b/llvm/test/MC/RISCV/rvzhinx-aliases-valid.s new file mode 100644 index 0000000000000..9a328e4441244 --- /dev/null +++ b/llvm/test/MC/RISCV/rvzhinx-aliases-valid.s @@ -0,0 +1,82 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \ +# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \ +# RUN: | llvm-objdump -d --mattr=+zhinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \ +# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \ +# RUN: | llvm-objdump -d --mattr=+zhinx - \ +# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s + +##===----------------------------------------------------------------------===## +## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) +##===----------------------------------------------------------------------===## + +# CHECK-INST: fsgnjx.h s1, s2, s2 +# CHECK-ALIAS: fabs.h s1, s2 +fabs.h s1, s2 +# CHECK-INST: fsgnjn.h s2, s3, s3 +# CHECK-ALIAS: fneg.h s2, s3 +fneg.h s2, s3 + +# CHECK-INST: flt.h tp, s6, s5 +# CHECK-ALIAS: flt.h tp, s6, s5 +fgt.h x4, s5, s6 +# CHECK-INST: fle.h t2, s1, s0 +# CHECK-ALIAS: fle.h t2, s1, s0 +fge.h x7, x8, x9 + +##===----------------------------------------------------------------------===## +## Aliases which omit the rounding mode. +##===----------------------------------------------------------------------===## + +# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn +# CHECK-ALIAS: fmadd.h a0, a1, a2, a3 +fmadd.h x10, x11, x12, x13 +# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn +# CHECK-ALIAS: fmsub.h a4, a5, a6, a7 +fmsub.h x14, x15, x16, x17 +# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn +# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5 +fnmsub.h x18, x19, x20, x21 +# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn +# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9 +fnmadd.h x22, x23, x24, x25 +# CHECK-INST: fadd.h s10, s11, t3, dyn +# CHECK-ALIAS: fadd.h s10, s11, t3 +fadd.h x26, x27, x28 +# CHECK-INST: fsub.h t4, t5, t6, dyn +# CHECK-ALIAS: fsub.h t4, t5, t6 +fsub.h x29, x30, x31 +# CHECK-INST: fmul.h s0, s1, s2, dyn +# CHECK-ALIAS: fmul.h s0, s1, s2 +fmul.h s0, s1, s2 +# CHECK-INST: fdiv.h s3, s4, s5, dyn +# CHECK-ALIAS: fdiv.h s3, s4, s5 +fdiv.h s3, s4, s5 +# CHECK-INST: fsqrt.h s6, s7, dyn +# CHECK-ALIAS: fsqrt.h s6, s7 +fsqrt.h s6, s7 +# CHECK-INST: fcvt.w.h a0, s5, dyn +# CHECK-ALIAS: fcvt.w.h a0, s5 +fcvt.w.h a0, s5 +# CHECK-INST: fcvt.wu.h a1, s6, dyn +# CHECK-ALIAS: fcvt.wu.h a1, s6 +fcvt.wu.h a1, s6 +# CHECK-INST: fcvt.h.w t6, a4, dyn +# CHECK-ALIAS: fcvt.h.w t6, a4 +fcvt.h.w t6, a4 +# CHECK-INST: fcvt.h.wu s0, a5, dyn +# CHECK-ALIAS: fcvt.h.wu s0, a5 +fcvt.h.wu s0, a5 From 4dc3cb8e325525214fccef33e32891e5dccc9540 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Tue, 15 Feb 2022 13:31:17 -0800 Subject: [PATCH 140/316] ReleaseNotes: add BOLT subsection For the release/14.x branch. Reviewed By: tstellar Differential Revision: https://reviews.llvm.org/D119889 --- llvm/docs/ReleaseNotes.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index e67eb4b39ddfd..1ac4cca463794 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -255,6 +255,13 @@ Changes to LLDB Changes to Sanitizers --------------------- +Changes to BOLT +--------------------- + +* BOLT project is added to the LLVM monorepo. BOLT is a post-link optimizer + developed to speed up large applications. Build and usage instructions are + given in `README `_. + External Open Source Projects Using LLVM 14 =========================================== From 42a797ef011bd920bb7b781a752b925362b9754c Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 18 Feb 2022 14:59:14 -0800 Subject: [PATCH 141/316] [ELF] Fix .strtab corruption when a symbol name is empty This is a simplified c12d49c4e286fa108d4d69f1c6d2b8d691993ffd in main which just fixes the bug but does not affect the -O2 deduplication. --- lld/ELF/SyntheticSections.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 986c1308cbaf6..ccf0c5fd65da2 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -1231,6 +1231,7 @@ StringTableSection::StringTableSection(StringRef name, bool dynamic) dynamic(dynamic) { // ELF string tables start with a NUL byte. strings.push_back(""); + stringMap.try_emplace(CachedHashStringRef(""), 0); size = 1; } From 908c1bae6e7fa2339e8b9b7856d849f20e98f653 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 11 Feb 2022 22:27:08 -0800 Subject: [PATCH 142/316] [RISCV] Fix incorrect extend type in vwmulsu combine. While matching widening multiply, if we matched an extend from i8->i32, i16->i64 or i8->i64, we need to reintroduce a narrower extend. If we're matching a vwmulsu we need to use a sext for op0 and a zext for op1. This bug exists in LLVM 14 and will need to be backported. Differential Revision: https://reviews.llvm.org/D119618 (cherry picked from commit 478c237e21b2c3a83e46f26fcbeb3876682f9b14) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 ++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 97d24c8e9c0bb..2fe491ad5ea42 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7443,6 +7443,8 @@ static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG, unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; if (Op0.getValueType() != NarrowVT) Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); + // vwmulsu requires second operand to be zero extended. + ExtOpc = IsVWMULSU ? RISCVISD::VZEXT_VL : ExtOpc; if (Op1.getValueType() != NarrowVT) Op1 = DAG.getNode(ExtOpc, DL, NarrowVT, Op1, Mask, VL); diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll index 6c204b24ae2bd..ffe4c56130901 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll @@ -375,7 +375,7 @@ define <2 x i32> @vwmulsu_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v11, v9 ; CHECK-NEXT: vwmulsu.vv v8, v11, v10 ; CHECK-NEXT: ret @@ -394,7 +394,7 @@ define <4 x i32> @vwmulsu_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vwmulsu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x From 1e340705f142ee7379272f94df888d6ddaaa32db Mon Sep 17 00:00:00 2001 From: Amy Kwan Date: Fri, 11 Feb 2022 12:45:07 -0600 Subject: [PATCH 143/316] [PowerPC] Add default handling for single element vectors, and split/promote vNi1 vectors. This patch updates the handling of vectors in getPreferredVectorAction(): For single-element and scalable vectors, fall back to default vector legalization handling. For vNi1 vectors, add handling to either split or promote them in order to prevent the production of wide v256i1/v512i1 types. The following assertion is fixed by this patch, as we ended up producing the wide vector types (that are used for MMA) in the backend prior to this fix. ``` Assertion failed: VT.getSizeInBits() == Operand.getValueSizeInBits() && "Cannot BITCAST between types of different sizes!" ``` Differential Revision: https://reviews.llvm.org/D119521 (cherry picked from commit ac5a5a9cfe7c83ee5fbbc48118b4239e7e6cf6c9) --- llvm/lib/Target/PowerPC/PPCISelLowering.h | 15 +- .../PowerPC/p10-handle-split-promote-vec.ll | 212 ++++++++++++++++++ 2 files changed, 225 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index eb52e4aa62734..b195b1f2556a9 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -765,8 +765,19 @@ namespace llvm { /// then the VPERM for the shuffle. All in all a very slow sequence. TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override { - if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 && - VT.getScalarSizeInBits() % 8 == 0) + // Default handling for scalable and single-element vectors. + if (VT.isScalableVector() || VT.getVectorNumElements() == 1) + return TargetLoweringBase::getPreferredVectorAction(VT); + + // Split and promote vNi1 vectors so we don't produce v256i1/v512i1 + // types as those are only for MMA instructions. + if (VT.getScalarSizeInBits() == 1 && VT.getSizeInBits() > 16) + return TypeSplitVector; + if (VT.getScalarSizeInBits() == 1) + return TypePromoteInteger; + + // Widen vectors that have reasonably sized elements. + if (VT.getScalarSizeInBits() % 8 == 0) return TypeWidenVector; return TargetLoweringBase::getPreferredVectorAction(VT); } diff --git a/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll b/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll new file mode 100644 index 0000000000000..ad0bd404d313e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll @@ -0,0 +1,212 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix -vec-extabi \ +; RUN: -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-AIX + +define i32 @SplitPromoteVectorTest(i32 %Opc) align 2 { +; CHECK-LABEL: SplitPromoteVectorTest: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: plxv v3, .LCPI0_0@PCREL(0), 1 +; CHECK-NEXT: mtvsrws v2, r3 +; CHECK-NEXT: li r5, 4 +; CHECK-NEXT: li r8, 0 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r6, r5, v3 +; CHECK-NEXT: vextubrx r4, r8, v3 +; CHECK-NEXT: rlwimi r4, r6, 1, 30, 30 +; CHECK-NEXT: li r6, 8 +; CHECK-NEXT: vextubrx r7, r6, v3 +; CHECK-NEXT: rlwimi r4, r7, 2, 29, 29 +; CHECK-NEXT: li r7, 12 +; CHECK-NEXT: vextubrx r9, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_1@PCREL(0), 1 +; CHECK-NEXT: rlwimi r4, r9, 3, 28, 28 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r9, r8, v3 +; CHECK-NEXT: rlwimi r4, r9, 4, 27, 27 +; CHECK-NEXT: vextubrx r9, r5, v3 +; CHECK-NEXT: rlwimi r4, r9, 5, 26, 26 +; CHECK-NEXT: vextubrx r9, r6, v3 +; CHECK-NEXT: rlwimi r4, r9, 6, 25, 25 +; CHECK-NEXT: vextubrx r9, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_2@PCREL(0), 1 +; CHECK-NEXT: rlwimi r4, r9, 7, 24, 24 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r9, r8, v3 +; CHECK-NEXT: rlwimi r4, r9, 8, 23, 23 +; CHECK-NEXT: vextubrx r9, r5, v3 +; CHECK-NEXT: rlwimi r4, r9, 9, 22, 22 +; CHECK-NEXT: vextubrx r9, r6, v3 +; CHECK-NEXT: rlwimi r4, r9, 10, 21, 21 +; CHECK-NEXT: vextubrx r9, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_3@PCREL(0), 1 +; CHECK-NEXT: rlwimi r4, r9, 11, 20, 20 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r9, r8, v3 +; CHECK-NEXT: rlwimi r4, r9, 12, 19, 19 +; CHECK-NEXT: vextubrx r9, r5, v3 +; CHECK-NEXT: rlwimi r4, r9, 13, 18, 18 +; CHECK-NEXT: vextubrx r9, r6, v3 +; CHECK-NEXT: rlwimi r4, r9, 14, 17, 17 +; CHECK-NEXT: vextubrx r9, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_4@PCREL(0), 1 +; CHECK-NEXT: rlwimi r4, r9, 15, 0, 16 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r10, r5, v3 +; CHECK-NEXT: vextubrx r9, r8, v3 +; CHECK-NEXT: rlwimi r9, r10, 1, 30, 30 +; CHECK-NEXT: vextubrx r10, r6, v3 +; CHECK-NEXT: rlwimi r9, r10, 2, 29, 29 +; CHECK-NEXT: vextubrx r10, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_5@PCREL(0), 1 +; CHECK-NEXT: rlwimi r9, r10, 3, 28, 28 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r10, r8, v3 +; CHECK-NEXT: rlwimi r9, r10, 4, 27, 27 +; CHECK-NEXT: vextubrx r10, r5, v3 +; CHECK-NEXT: rlwimi r9, r10, 5, 26, 26 +; CHECK-NEXT: vextubrx r10, r6, v3 +; CHECK-NEXT: rlwimi r9, r10, 6, 25, 25 +; CHECK-NEXT: vextubrx r10, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_6@PCREL(0), 1 +; CHECK-NEXT: rlwimi r9, r10, 7, 24, 24 +; CHECK-NEXT: vcmpequw v3, v2, v3 +; CHECK-NEXT: vextubrx r10, r8, v3 +; CHECK-NEXT: rlwimi r9, r10, 8, 23, 23 +; CHECK-NEXT: vextubrx r10, r5, v3 +; CHECK-NEXT: rlwimi r9, r10, 9, 22, 22 +; CHECK-NEXT: vextubrx r10, r6, v3 +; CHECK-NEXT: rlwimi r9, r10, 10, 21, 21 +; CHECK-NEXT: vextubrx r10, r7, v3 +; CHECK-NEXT: plxv v3, .LCPI0_7@PCREL(0), 1 +; CHECK-NEXT: rlwimi r9, r10, 11, 20, 20 +; CHECK-NEXT: vcmpequw v2, v2, v3 +; CHECK-NEXT: vextubrx r8, r8, v2 +; CHECK-NEXT: vextubrx r5, r5, v2 +; CHECK-NEXT: rlwimi r9, r8, 12, 19, 19 +; CHECK-NEXT: rlwimi r9, r5, 13, 18, 18 +; CHECK-NEXT: vextubrx r5, r6, v2 +; CHECK-NEXT: rlwimi r9, r5, 14, 17, 17 +; CHECK-NEXT: vextubrx r5, r7, v2 +; CHECK-NEXT: rlwimi r9, r5, 15, 0, 16 +; CHECK-NEXT: or r4, r9, r4 +; CHECK-NEXT: andi. r4, r4, 65535 +; CHECK-NEXT: iseleq r3, 0, r3 +; CHECK-NEXT: blr +; +; CHECK-AIX-LABEL: SplitPromoteVectorTest: +; CHECK-AIX: # %bb.0: # %entry +; CHECK-AIX-NEXT: ld 4, L..C0(2) # %const.0 +; CHECK-AIX-NEXT: mtvsrws 34, 3 +; CHECK-AIX-NEXT: li 8, 15 +; CHECK-AIX-NEXT: li 5, 11 +; CHECK-AIX-NEXT: lxv 35, 0(4) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 4, 8, 3 +; CHECK-AIX-NEXT: vextublx 6, 5, 3 +; CHECK-AIX-NEXT: clrlwi 4, 4, 31 +; CHECK-AIX-NEXT: rlwimi 4, 6, 1, 30, 30 +; CHECK-AIX-NEXT: li 6, 7 +; CHECK-AIX-NEXT: vextublx 7, 6, 3 +; CHECK-AIX-NEXT: rlwimi 4, 7, 2, 29, 29 +; CHECK-AIX-NEXT: li 7, 3 +; CHECK-AIX-NEXT: vextublx 9, 7, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 3, 28, 28 +; CHECK-AIX-NEXT: ld 9, L..C1(2) # %const.1 +; CHECK-AIX-NEXT: lxv 35, 0(9) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 9, 8, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 4, 27, 27 +; CHECK-AIX-NEXT: vextublx 9, 5, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 5, 26, 26 +; CHECK-AIX-NEXT: vextublx 9, 6, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 6, 25, 25 +; CHECK-AIX-NEXT: vextublx 9, 7, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 7, 24, 24 +; CHECK-AIX-NEXT: ld 9, L..C2(2) # %const.2 +; CHECK-AIX-NEXT: lxv 35, 0(9) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 9, 8, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 8, 23, 23 +; CHECK-AIX-NEXT: vextublx 9, 5, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 9, 22, 22 +; CHECK-AIX-NEXT: vextublx 9, 6, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 10, 21, 21 +; CHECK-AIX-NEXT: vextublx 9, 7, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 11, 20, 20 +; CHECK-AIX-NEXT: ld 9, L..C3(2) # %const.3 +; CHECK-AIX-NEXT: lxv 35, 0(9) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 9, 8, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 12, 19, 19 +; CHECK-AIX-NEXT: vextublx 9, 5, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 13, 18, 18 +; CHECK-AIX-NEXT: vextublx 9, 6, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 14, 17, 17 +; CHECK-AIX-NEXT: vextublx 9, 7, 3 +; CHECK-AIX-NEXT: rlwimi 4, 9, 15, 16, 16 +; CHECK-AIX-NEXT: ld 9, L..C4(2) # %const.4 +; CHECK-AIX-NEXT: lxv 35, 0(9) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 9, 8, 3 +; CHECK-AIX-NEXT: vextublx 10, 5, 3 +; CHECK-AIX-NEXT: clrlwi 9, 9, 31 +; CHECK-AIX-NEXT: rlwimi 9, 10, 1, 30, 30 +; CHECK-AIX-NEXT: vextublx 10, 6, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 2, 29, 29 +; CHECK-AIX-NEXT: vextublx 10, 7, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 3, 28, 28 +; CHECK-AIX-NEXT: ld 10, L..C5(2) # %const.5 +; CHECK-AIX-NEXT: lxv 35, 0(10) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 10, 8, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 4, 27, 27 +; CHECK-AIX-NEXT: vextublx 10, 5, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 5, 26, 26 +; CHECK-AIX-NEXT: vextublx 10, 6, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 6, 25, 25 +; CHECK-AIX-NEXT: vextublx 10, 7, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 7, 24, 24 +; CHECK-AIX-NEXT: ld 10, L..C6(2) # %const.6 +; CHECK-AIX-NEXT: lxv 35, 0(10) +; CHECK-AIX-NEXT: vcmpequw 3, 2, 3 +; CHECK-AIX-NEXT: vextublx 10, 8, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 8, 23, 23 +; CHECK-AIX-NEXT: vextublx 10, 5, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 9, 22, 22 +; CHECK-AIX-NEXT: vextublx 10, 6, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 10, 21, 21 +; CHECK-AIX-NEXT: vextublx 10, 7, 3 +; CHECK-AIX-NEXT: rlwimi 9, 10, 11, 20, 20 +; CHECK-AIX-NEXT: ld 10, L..C7(2) # %const.7 +; CHECK-AIX-NEXT: lxv 35, 0(10) +; CHECK-AIX-NEXT: vcmpequw 2, 2, 3 +; CHECK-AIX-NEXT: vextublx 8, 8, 2 +; CHECK-AIX-NEXT: vextublx 5, 5, 2 +; CHECK-AIX-NEXT: rlwimi 9, 8, 12, 19, 19 +; CHECK-AIX-NEXT: rlwimi 9, 5, 13, 18, 18 +; CHECK-AIX-NEXT: vextublx 5, 6, 2 +; CHECK-AIX-NEXT: rlwimi 9, 5, 14, 17, 17 +; CHECK-AIX-NEXT: vextublx 5, 7, 2 +; CHECK-AIX-NEXT: rlwimi 9, 5, 15, 16, 16 +; CHECK-AIX-NEXT: or 4, 9, 4 +; CHECK-AIX-NEXT: andi. 4, 4, 65535 +; CHECK-AIX-NEXT: iseleq 3, 0, 3 +; CHECK-AIX-NEXT: blr +entry: + %0 = insertelement <32 x i32> poison, i32 %Opc, i64 0 + %shuffle = shufflevector <32 x i32> %0, <32 x i32> poison, <32 x i32> zeroinitializer + %1 = icmp eq <32 x i32> %shuffle, + %2 = bitcast <32 x i1> %1 to i32 + %3 = icmp ne i32 %2, 0 + %op.rdx = or i1 %3, false + %op.rdx255 = or i1 %op.rdx, false + %4 = or i1 %op.rdx255, false + %5 = or i1 %4, false + %6 = or i1 %5, false + %7 = or i1 %6, false + %cond = select i1 %7, i32 %Opc, i32 0 + ret i32 %cond +} From e1b3afbbdef10a8ee085dddfb24afddef2cf70b2 Mon Sep 17 00:00:00 2001 From: Anton Afanasyev Date: Sat, 12 Feb 2022 11:46:49 +0300 Subject: [PATCH 144/316] [SLP] Simplify indices processing for insertelements Get rid of non-constant and undef indices of insertelements at `buildTree()` stage. Fix bugs. Differential Revision: https://reviews.llvm.org/D119623 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 78 ++++++++----------- .../SLPVectorizer/X86/insert-crash-index.ll | 67 ++++++++++++++++ 2 files changed, 101 insertions(+), 44 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 25bf69729c70f..8a58b52df45d0 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -666,19 +666,18 @@ static void inversePermutation(ArrayRef Indices, /// \returns inserting index of InsertElement or InsertValue instruction, /// using Offset as base offset for index. -static Optional getInsertIndex(Value *InsertInst, unsigned Offset) { +static Optional getInsertIndex(Value *InsertInst, + unsigned Offset = 0) { int Index = Offset; if (auto *IE = dyn_cast(InsertInst)) { if (auto *CI = dyn_cast(IE->getOperand(2))) { auto *VT = cast(IE->getType()); if (CI->getValue().uge(VT->getNumElements())) - return UndefMaskElem; + return None; Index *= VT->getNumElements(); Index += CI->getZExtValue(); return Index; } - if (isa(IE->getOperand(2))) - return UndefMaskElem; return None; } @@ -3848,13 +3847,15 @@ void BoUpSLP::buildTree_rec(ArrayRef VL, unsigned Depth, // Check that we have a buildvector and not a shuffle of 2 or more // different vectors. ValueSet SourceVectors; - int MinIdx = std::numeric_limits::max(); for (Value *V : VL) { SourceVectors.insert(cast(V)->getOperand(0)); - Optional Idx = *getInsertIndex(V, 0); - if (!Idx || *Idx == UndefMaskElem) - continue; - MinIdx = std::min(MinIdx, *Idx); + if (getInsertIndex(V) == None) { + LLVM_DEBUG(dbgs() << "SLP: Gather of insertelement vectors with " + "non-constant or undef index.\n"); + newTreeEntry(VL, None /*not vectorized*/, S, UserTreeIdx); + BS.cancelScheduling(VL, VL0); + return; + } } if (count_if(VL, [&SourceVectors](Value *V) { @@ -3876,10 +3877,8 @@ void BoUpSLP::buildTree_rec(ArrayRef VL, unsigned Depth, decltype(OrdCompare)> Indices(OrdCompare); for (int I = 0, E = VL.size(); I < E; ++I) { - Optional Idx = *getInsertIndex(VL[I], 0); - if (!Idx || *Idx == UndefMaskElem) - continue; - Indices.emplace(*Idx, I); + unsigned Idx = *getInsertIndex(VL[I]); + Indices.emplace(Idx, I); } OrdersType CurrentOrder(VL.size(), VL.size()); bool IsIdentity = true; @@ -5006,12 +5005,10 @@ InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, SmallVector PrevMask(NumElts, UndefMaskElem); Mask.swap(PrevMask); for (unsigned I = 0; I < NumScalars; ++I) { - Optional InsertIdx = getInsertIndex(VL[PrevMask[I]], 0); - if (!InsertIdx || *InsertIdx == UndefMaskElem) - continue; - DemandedElts.setBit(*InsertIdx); - IsIdentity &= *InsertIdx - Offset == I; - Mask[*InsertIdx - Offset] = I; + unsigned InsertIdx = *getInsertIndex(VL[PrevMask[I]]); + DemandedElts.setBit(InsertIdx); + IsIdentity &= InsertIdx - Offset == I; + Mask[InsertIdx - Offset] = I; } assert(Offset < NumElts && "Failed to find vector index offset"); @@ -5685,9 +5682,7 @@ InstructionCost BoUpSLP::getTreeCost(ArrayRef VectorizedVals) { // to detect it as a final shuffled/identity match. if (auto *VU = dyn_cast_or_null(EU.User)) { if (auto *FTy = dyn_cast(VU->getType())) { - Optional InsertIdx = getInsertIndex(VU, 0); - if (!InsertIdx || *InsertIdx == UndefMaskElem) - continue; + unsigned InsertIdx = *getInsertIndex(VU); auto *It = find_if(FirstUsers, [VU](Value *V) { return areTwoInsertFromSameBuildVector(VU, cast(V)); @@ -5717,9 +5712,8 @@ InstructionCost BoUpSLP::getTreeCost(ArrayRef VectorizedVals) { } else { VecId = std::distance(FirstUsers.begin(), It); } - int Idx = *InsertIdx; - ShuffleMask[VecId][Idx] = EU.Lane; - DemandedElts[VecId].setBit(Idx); + ShuffleMask[VecId][InsertIdx] = EU.Lane; + DemandedElts[VecId].setBit(InsertIdx); continue; } } @@ -6477,11 +6471,9 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { Mask.swap(PrevMask); for (unsigned I = 0; I < NumScalars; ++I) { Value *Scalar = E->Scalars[PrevMask[I]]; - Optional InsertIdx = getInsertIndex(Scalar, 0); - if (!InsertIdx || *InsertIdx == UndefMaskElem) - continue; - IsIdentity &= *InsertIdx - Offset == I; - Mask[*InsertIdx - Offset] = I; + unsigned InsertIdx = *getInsertIndex(Scalar); + IsIdentity &= InsertIdx - Offset == I; + Mask[InsertIdx - Offset] = I; } if (!IsIdentity || NumElts != NumScalars) { V = Builder.CreateShuffleVector(V, Mask); @@ -9323,21 +9315,22 @@ static Optional getAggregateSize(Instruction *InsertInst) { } while (true); } -static bool findBuildAggregate_rec(Instruction *LastInsertInst, +static void findBuildAggregate_rec(Instruction *LastInsertInst, TargetTransformInfo *TTI, SmallVectorImpl &BuildVectorOpds, SmallVectorImpl &InsertElts, unsigned OperandOffset) { do { Value *InsertedOperand = LastInsertInst->getOperand(1); - Optional OperandIndex = getInsertIndex(LastInsertInst, OperandOffset); + Optional OperandIndex = + getInsertIndex(LastInsertInst, OperandOffset); if (!OperandIndex) - return false; + return; if (isa(InsertedOperand) || isa(InsertedOperand)) { - if (!findBuildAggregate_rec(cast(InsertedOperand), TTI, - BuildVectorOpds, InsertElts, *OperandIndex)) - return false; + findBuildAggregate_rec(cast(InsertedOperand), TTI, + BuildVectorOpds, InsertElts, *OperandIndex); + } else { BuildVectorOpds[*OperandIndex] = InsertedOperand; InsertElts[*OperandIndex] = LastInsertInst; @@ -9347,7 +9340,6 @@ static bool findBuildAggregate_rec(Instruction *LastInsertInst, (isa(LastInsertInst) || isa(LastInsertInst)) && LastInsertInst->hasOneUse()); - return true; } /// Recognize construction of vectors like @@ -9382,13 +9374,11 @@ static bool findBuildAggregate(Instruction *LastInsertInst, BuildVectorOpds.resize(*AggregateSize); InsertElts.resize(*AggregateSize); - if (findBuildAggregate_rec(LastInsertInst, TTI, BuildVectorOpds, InsertElts, - 0)) { - llvm::erase_value(BuildVectorOpds, nullptr); - llvm::erase_value(InsertElts, nullptr); - if (BuildVectorOpds.size() >= 2) - return true; - } + findBuildAggregate_rec(LastInsertInst, TTI, BuildVectorOpds, InsertElts, 0); + llvm::erase_value(BuildVectorOpds, nullptr); + llvm::erase_value(InsertElts, nullptr); + if (BuildVectorOpds.size() >= 2) + return true; return false; } diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll new file mode 100644 index 0000000000000..882681027df76 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-crash-index.ll @@ -0,0 +1,67 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -slp-vectorizer < %s | FileCheck %s + +; These all crashing before patch + +define <2 x i8> @negative_index(<2 x i8> %aux_vec, i8* %in) { +; CHECK-LABEL: @negative_index( +; CHECK-NEXT: [[IN0:%.*]] = load i8, i8* [[IN:%.*]], align 4 +; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[IN]], i64 1 +; CHECK-NEXT: [[IN1:%.*]] = load i8, i8* [[G1]], align 4 +; CHECK-NEXT: [[V0:%.*]] = insertelement <2 x i8> [[AUX_VEC:%.*]], i8 [[IN0]], i8 -1 +; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x i8> [[V0]], i8 [[IN1]], i64 1 +; CHECK-NEXT: [[OUT:%.*]] = add <2 x i8> [[V1]], [[V1]] +; CHECK-NEXT: ret <2 x i8> [[OUT]] +; + %in0 = load i8, i8* %in, align 4 + %g1 = getelementptr inbounds i8, i8* %in, i64 1 + %in1 = load i8, i8* %g1, align 4 + + %v0 = insertelement <2 x i8> %aux_vec, i8 %in0, i8 -1 + %v1 = insertelement <2 x i8> %v0, i8 %in1, i64 1 + + %out = add <2 x i8> %v1, %v1 + ret <2 x i8> %out +} + +define <2 x i8> @exceed_index(<2 x i8> %aux_vec, i8* %in) { +; CHECK-LABEL: @exceed_index( +; CHECK-NEXT: [[IN0:%.*]] = load i8, i8* [[IN:%.*]], align 4 +; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[IN]], i64 1 +; CHECK-NEXT: [[IN1:%.*]] = load i8, i8* [[G1]], align 4 +; CHECK-NEXT: [[V0:%.*]] = insertelement <2 x i8> [[AUX_VEC:%.*]], i8 [[IN0]], i8 2 +; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x i8> [[V0]], i8 [[IN1]], i64 1 +; CHECK-NEXT: [[OUT:%.*]] = add <2 x i8> [[V1]], [[V1]] +; CHECK-NEXT: ret <2 x i8> [[OUT]] +; + %in0 = load i8, i8* %in, align 4 + %g1 = getelementptr inbounds i8, i8* %in, i64 1 + %in1 = load i8, i8* %g1, align 4 + + %v0 = insertelement <2 x i8> %aux_vec, i8 %in0, i8 2 + %v1 = insertelement <2 x i8> %v0, i8 %in1, i64 1 + + %out = add <2 x i8> %v1, %v1 + ret <2 x i8> %out +} + +define <2 x i8> @poison_index(<2 x i8> %aux_vec, i8* %in) { +; CHECK-LABEL: @poison_index( +; CHECK-NEXT: [[IN0:%.*]] = load i8, i8* [[IN:%.*]], align 4 +; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[IN]], i64 1 +; CHECK-NEXT: [[IN1:%.*]] = load i8, i8* [[G1]], align 4 +; CHECK-NEXT: [[V0:%.*]] = insertelement <2 x i8> [[AUX_VEC:%.*]], i8 [[IN0]], i8 poison +; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x i8> [[V0]], i8 [[IN1]], i64 1 +; CHECK-NEXT: [[OUT:%.*]] = add <2 x i8> [[V1]], [[V1]] +; CHECK-NEXT: ret <2 x i8> [[OUT]] +; + %in0 = load i8, i8* %in, align 4 + %g1 = getelementptr inbounds i8, i8* %in, i64 1 + %in1 = load i8, i8* %g1, align 4 + + %v0 = insertelement <2 x i8> %aux_vec, i8 %in0, i8 poison + %v1 = insertelement <2 x i8> %v0, i8 %in1, i64 1 + + %out = add <2 x i8> %v1, %v1 + ret <2 x i8> %out +} From 7d8e83dab37af0516bd9bbaafe818c29fbab7062 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 14 Feb 2022 13:47:00 -0800 Subject: [PATCH 145/316] [funcattrs] check reachability to improve noreturn There was a fixme in the code pertaining to attributing functions as noreturn. By using reachability, if none of the blocks that are reachable from the entry return, then the function is noreturn. Previously, the code only checked if any blocks returned. If they're unreachable, then they don't matter. This improves codegen for the Linux kernel. Fixes: https://github.com/ClangBuiltLinux/linux/issues/1563 Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D119571 (cherry picked from commit 9dcb0061657e9b7f321fa6c295960c8f829ed6f1) --- llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 24 ++++++++++++++++--- .../test/Transforms/FunctionAttrs/noreturn.ll | 5 ++-- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp index 213a998d5bba2..e2f1944cee63f 100644 --- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp +++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp @@ -1614,6 +1614,26 @@ static bool basicBlockCanReturn(BasicBlock &BB) { return none_of(BB, instructionDoesNotReturn); } +// FIXME: this doesn't handle recursion. +static bool canReturn(Function &F) { + SmallVector Worklist; + SmallPtrSet Visited; + + Visited.insert(&F.front()); + Worklist.push_back(&F.front()); + + do { + BasicBlock *BB = Worklist.pop_back_val(); + if (basicBlockCanReturn(*BB)) + return true; + for (BasicBlock *Succ : successors(BB)) + if (Visited.insert(Succ).second) + Worklist.push_back(Succ); + } while (!Worklist.empty()); + + return false; +} + // Set the noreturn function attribute if possible. static void addNoReturnAttrs(const SCCNodeSet &SCCNodes, SmallSet &Changed) { @@ -1622,9 +1642,7 @@ static void addNoReturnAttrs(const SCCNodeSet &SCCNodes, F->doesNotReturn()) continue; - // The function can return if any basic blocks can return. - // FIXME: this doesn't handle recursion or unreachable blocks. - if (none_of(*F, basicBlockCanReturn)) { + if (!canReturn(*F)) { F->setDoesNotReturn(); Changed.insert(F); } diff --git a/llvm/test/Transforms/FunctionAttrs/noreturn.ll b/llvm/test/Transforms/FunctionAttrs/noreturn.ll index eba56c9630adb..6bc1e32ed5165 100644 --- a/llvm/test/Transforms/FunctionAttrs/noreturn.ll +++ b/llvm/test/Transforms/FunctionAttrs/noreturn.ll @@ -40,9 +40,8 @@ end: ret i32 %c } -; CHECK-NOT: Function Attrs: {{.*}}noreturn +; CHECK: Function Attrs: {{.*}}noreturn ; CHECK: @caller5() -; We currently don't handle unreachable blocks. define i32 @caller5() { entry: %c = call i32 @noreturn() @@ -87,4 +86,4 @@ define void @coro() "coroutine.presplit"="1" { } declare token @llvm.coro.id.retcon.once(i32 %size, i32 %align, i8* %buffer, i8* %prototype, i8* %alloc, i8* %free) -declare i1 @llvm.coro.end(i8*, i1) \ No newline at end of file +declare i1 @llvm.coro.end(i8*, i1) From c06cc1c3a7f8e20f6243433d3d15986d8758be30 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Thu, 3 Feb 2022 12:39:45 -0800 Subject: [PATCH 146/316] [libc++] Fix std::__debug_less in c++17. b07b5bd72716625e0976a84d23652d94d8d0165a adds a use of `__comp_ref_type.h` to `std::min`. When libc++ is built with `-D_LIBCPP_DEBUG=0`, this enables `std::__debug_less`, which is only marked constexpr after c++17. `std::min` itself is marked as being `constexpr` as of c++14, so by extension, `std::__debug_less` should also be marked `constexpr` for the same versions so that `std::min` can use it. This change lowers the guard from `> 17` to `> 11`. Reproducer in godbolt: https://godbolt.org/z/ans3TGsj8 ``` constexpr int x() { return std::min({1, 2, 3, 4}); } static_assert(x() == 1); ``` Reviewed By: #libc, philnik, Quuxplusone, ldionne Differential Revision: https://reviews.llvm.org/D118940 (cherry picked from commit 99e5c5256ff2eeebd977f2c82567f52b1e534a1f) --- libcxx/include/__algorithm/comp_ref_type.h | 10 +++++----- libcxx/test/libcxx/algorithms/debug_less.pass.cpp | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/libcxx/include/__algorithm/comp_ref_type.h b/libcxx/include/__algorithm/comp_ref_type.h index 6cc6405686f5d..0802d2496f5c0 100644 --- a/libcxx/include/__algorithm/comp_ref_type.h +++ b/libcxx/include/__algorithm/comp_ref_type.h @@ -28,11 +28,11 @@ template struct __debug_less { _Compare &__comp_; - _LIBCPP_CONSTEXPR_AFTER_CXX17 + _LIBCPP_CONSTEXPR_AFTER_CXX11 __debug_less(_Compare& __c) : __comp_(__c) {} template - _LIBCPP_CONSTEXPR_AFTER_CXX17 + _LIBCPP_CONSTEXPR_AFTER_CXX11 bool operator()(const _Tp& __x, const _Up& __y) { bool __r = __comp_(__x, __y); @@ -42,7 +42,7 @@ struct __debug_less } template - _LIBCPP_CONSTEXPR_AFTER_CXX17 + _LIBCPP_CONSTEXPR_AFTER_CXX11 bool operator()(_Tp& __x, _Up& __y) { bool __r = __comp_(__x, __y); @@ -52,7 +52,7 @@ struct __debug_less } template - _LIBCPP_CONSTEXPR_AFTER_CXX17 + _LIBCPP_CONSTEXPR_AFTER_CXX11 inline _LIBCPP_INLINE_VISIBILITY decltype((void)declval<_Compare&>()( declval<_LHS &>(), declval<_RHS &>())) @@ -62,7 +62,7 @@ struct __debug_less } template - _LIBCPP_CONSTEXPR_AFTER_CXX17 + _LIBCPP_CONSTEXPR_AFTER_CXX11 inline _LIBCPP_INLINE_VISIBILITY void __do_compare_assert(long, _LHS &, _RHS &) {} }; diff --git a/libcxx/test/libcxx/algorithms/debug_less.pass.cpp b/libcxx/test/libcxx/algorithms/debug_less.pass.cpp index 6dd56955001d0..46735cd31c5cf 100644 --- a/libcxx/test/libcxx/algorithms/debug_less.pass.cpp +++ b/libcxx/test/libcxx/algorithms/debug_less.pass.cpp @@ -270,7 +270,7 @@ void test_value_categories() { assert(dl(static_cast(1), static_cast(2))); } -#if TEST_STD_VER > 17 +#if TEST_STD_VER > 11 constexpr bool test_constexpr() { std::less<> cmp{}; __debug_less > dcmp(cmp); @@ -287,7 +287,7 @@ int main(int, char**) { test_non_const_arg_cmp(); test_value_iterator(); test_value_categories(); -#if TEST_STD_VER > 17 +#if TEST_STD_VER > 11 static_assert(test_constexpr(), ""); #endif return 0; From f3cfaf8bc8eb772417294c2d3c847cd750337224 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 1 Feb 2022 14:32:33 -0600 Subject: [PATCH 147/316] [MemoryBuiltins][FIX] Adjust index type size properly wrt. AS casts Use existing functionality to strip constant offsets that works well with AS casts and avoids the code duplication. Since we strip AS casts during the computation of the offset we also need to adjust the APInt properly to avoid mismatches in the bit width. This code ensures the caller of `compute` sees APInts that match the index type size of the value passed to `compute`, not the value result of the strip pointer cast. Fixes #53559. Differential Revision: https://reviews.llvm.org/D118727 (cherry picked from commit 29c8ebad10b4c349a185438fed52e08426d603e1) --- llvm/include/llvm/Analysis/MemoryBuiltins.h | 2 +- llvm/lib/Analysis/MemoryBuiltins.cpp | 51 ++++++++++++------- .../builtin-dynamic-object-size.ll | 39 +++++++++++++- 3 files changed, 72 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/Analysis/MemoryBuiltins.h b/llvm/include/llvm/Analysis/MemoryBuiltins.h index d5b60ee540e06..ce4413682bdc8 100644 --- a/llvm/include/llvm/Analysis/MemoryBuiltins.h +++ b/llvm/include/llvm/Analysis/MemoryBuiltins.h @@ -210,7 +210,6 @@ class ObjectSizeOffsetVisitor SizeOffsetType visitConstantPointerNull(ConstantPointerNull&); SizeOffsetType visitExtractElementInst(ExtractElementInst &I); SizeOffsetType visitExtractValueInst(ExtractValueInst &I); - SizeOffsetType visitGEPOperator(GEPOperator &GEP); SizeOffsetType visitGlobalAlias(GlobalAlias &GA); SizeOffsetType visitGlobalVariable(GlobalVariable &GV); SizeOffsetType visitIntToPtrInst(IntToPtrInst&); @@ -221,6 +220,7 @@ class ObjectSizeOffsetVisitor SizeOffsetType visitInstruction(Instruction &I); private: + SizeOffsetType computeImpl(Value *V); bool CheckedZextOrTrunc(APInt &I); }; diff --git a/llvm/lib/Analysis/MemoryBuiltins.cpp b/llvm/lib/Analysis/MemoryBuiltins.cpp index 208f93aa1ac63..9e26f292b789a 100644 --- a/llvm/lib/Analysis/MemoryBuiltins.cpp +++ b/llvm/lib/Analysis/MemoryBuiltins.cpp @@ -573,18 +573,48 @@ ObjectSizeOffsetVisitor::ObjectSizeOffsetVisitor(const DataLayout &DL, } SizeOffsetType ObjectSizeOffsetVisitor::compute(Value *V) { + unsigned InitialIntTyBits = DL.getIndexTypeSizeInBits(V->getType()); + + // Stripping pointer casts can strip address space casts which can change the + // index type size. The invariant is that we use the value type to determine + // the index type size and if we stripped address space casts we have to + // readjust the APInt as we pass it upwards in order for the APInt to match + // the type the caller passed in. + APInt Offset(InitialIntTyBits, 0); + V = V->stripAndAccumulateConstantOffsets( + DL, Offset, /* AllowNonInbounds */ true, /* AllowInvariantGroup */ true); + + // Later we use the index type size and zero but it will match the type of the + // value that is passed to computeImpl. IntTyBits = DL.getIndexTypeSizeInBits(V->getType()); Zero = APInt::getZero(IntTyBits); - V = V->stripPointerCasts(); + bool IndexTypeSizeChanged = InitialIntTyBits != IntTyBits; + if (!IndexTypeSizeChanged && Offset.isZero()) + return computeImpl(V); + + // We stripped an address space cast that changed the index type size or we + // accumulated some constant offset (or both). Readjust the bit width to match + // the argument index type size and apply the offset, as required. + SizeOffsetType SOT = computeImpl(V); + if (IndexTypeSizeChanged) { + if (knownSize(SOT) && !::CheckedZextOrTrunc(SOT.first, InitialIntTyBits)) + SOT.first = APInt(); + if (knownOffset(SOT) && !::CheckedZextOrTrunc(SOT.second, InitialIntTyBits)) + SOT.second = APInt(); + } + // If the computed offset is "unknown" we cannot add the stripped offset. + return {SOT.first, + SOT.second.getBitWidth() > 1 ? SOT.second + Offset : SOT.second}; +} + +SizeOffsetType ObjectSizeOffsetVisitor::computeImpl(Value *V) { if (Instruction *I = dyn_cast(V)) { // If we have already seen this instruction, bail out. Cycles can happen in // unreachable code after constant propagation. if (!SeenInsts.insert(I).second) return unknown(); - if (GEPOperator *GEP = dyn_cast(V)) - return visitGEPOperator(*GEP); return visit(*I); } if (Argument *A = dyn_cast(V)) @@ -597,12 +627,6 @@ SizeOffsetType ObjectSizeOffsetVisitor::compute(Value *V) { return visitGlobalVariable(*GV); if (UndefValue *UV = dyn_cast(V)) return visitUndefValue(*UV); - if (ConstantExpr *CE = dyn_cast(V)) { - if (CE->getOpcode() == Instruction::IntToPtr) - return unknown(); // clueless - if (CE->getOpcode() == Instruction::GetElementPtr) - return visitGEPOperator(cast(*CE)); - } LLVM_DEBUG(dbgs() << "ObjectSizeOffsetVisitor::compute() unhandled value: " << *V << '\n'); @@ -682,15 +706,6 @@ ObjectSizeOffsetVisitor::visitExtractValueInst(ExtractValueInst&) { return unknown(); } -SizeOffsetType ObjectSizeOffsetVisitor::visitGEPOperator(GEPOperator &GEP) { - SizeOffsetType PtrData = compute(GEP.getPointerOperand()); - APInt Offset(DL.getIndexTypeSizeInBits(GEP.getPointerOperand()->getType()), 0); - if (!bothKnown(PtrData) || !GEP.accumulateConstantOffset(DL, Offset)) - return unknown(); - - return std::make_pair(PtrData.first, PtrData.second + Offset); -} - SizeOffsetType ObjectSizeOffsetVisitor::visitGlobalAlias(GlobalAlias &GA) { if (GA.isInterposable()) return unknown(); diff --git a/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll b/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll index 91c9d3c2827ff..5c10deb6717a5 100644 --- a/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll +++ b/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll @@ -1,6 +1,6 @@ ; RUN: opt -instcombine -S < %s | FileCheck %s -target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128-p7:32:32" target triple = "x86_64-apple-macosx10.14.0" ; Function Attrs: nounwind ssp uwtable @@ -152,6 +152,43 @@ if.end: ; preds = %if.else, %if.then ; CHECK-NEXT: br i1 false, label %if.else, label %if.then ; CHECK: call void @fortified_chk(i8* %obj, i64 [[SZ]]) +@p7 = internal addrspace(7) global i8 0 + +; Gracefully handle AS cast when the address spaces have different pointer widths. +define i64 @as_cast(i1 %c) { +; CHECK: [[TMP0:%.*]] = select i1 %c, i64 64, i64 1 +; CHECK: [[NOT:%.*]] = xor i1 %c, true +; CHECK: [[NEG:%.*]] = sext i1 [[NOT]] to i64 +; CHECK: [[TMP1:%.*]] = add nsw i64 [[TMP0]], [[NEG]] +; CHECK: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], -1 +; CHECK: call void @llvm.assume(i1 [[TMP2]]) +; CHECK: ret i64 [[TMP1]] +; +entry: + %p0 = tail call i8* @malloc(i64 64) + %gep = getelementptr i8, i8 addrspace(7)* @p7, i32 1 + %as = addrspacecast i8 addrspace(7)* %gep to i8* + %select = select i1 %c, i8* %p0, i8* %as + %calc_size = tail call i64 @llvm.objectsize.i64.p0i8(i8* %select, i1 false, i1 true, i1 true) + ret i64 %calc_size +} + +define i64 @constexpr_as_cast(i1 %c) { +; CHECK: [[TMP0:%.*]] = select i1 %c, i64 64, i64 1 +; CHECK: [[NOT:%.*]] = xor i1 %c, true +; CHECK: [[NEG:%.*]] = sext i1 [[NOT]] to i64 +; CHECK: [[TMP1:%.*]] = add nsw i64 [[TMP0]], [[NEG]] +; CHECK: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], -1 +; CHECK: call void @llvm.assume(i1 [[TMP2]]) +; CHECK: ret i64 [[TMP1]] +; +entry: + %p0 = tail call i8* @malloc(i64 64) + %select = select i1 %c, i8* %p0, i8* addrspacecast (i8 addrspace(7)* getelementptr (i8, i8 addrspace(7)* @p7, i32 1) to i8*) + %calc_size = tail call i64 @llvm.objectsize.i64.p0i8(i8* %select, i1 false, i1 true, i1 true) + ret i64 %calc_size +} + declare void @bury(i32) local_unnamed_addr #2 ; Function Attrs: nounwind allocsize(0) From 13fdc7afa8565810fb28793bd60b9a5cf8d0d978 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Mon, 7 Feb 2022 23:37:02 -0600 Subject: [PATCH 148/316] [Attributor][FIX] Reachability needs to account for readonly callees The oversight caused us to ignore call sites that are effectively dead when we computed reachability (or more precise the call edges of a function). The problem is that loads in the readonly callee might depend on stores prior to the callee. If we do not track the call edge we mistakenly assumed the store before the call cannot reach the load. The problem is nicely visible in: `llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll` Caused by D118673. Fixes https://github.com/llvm/llvm-project/issues/53726 --- .../Transforms/IPO/AttributorAttributes.cpp | 3 +- .../2008-02-01-ReturnAttrs.ll | 4 +- .../ArgumentPromotion/X86/attributes.ll | 4 +- .../X86/min-legal-vector-width.ll | 4 +- .../Attributor/ArgumentPromotion/alignment.ll | 6 +- .../Attributor/ArgumentPromotion/basictest.ll | 6 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 32 +- .../Attributor/IPConstantProp/PR26044.ll | 19 +- .../IPConstantProp/arg-count-mismatch.ll | 5 +- .../IPConstantProp/return-argument.ll | 64 +- .../IPConstantProp/return-constants.ll | 41 +- ...fter-each-resolving-undefs-for-function.ll | 4 +- llvm/test/Transforms/Attributor/align.ll | 1036 +++++++++-------- .../Transforms/Attributor/internal-noalias.ll | 4 +- llvm/test/Transforms/Attributor/liveness.ll | 164 +-- .../Transforms/Attributor/liveness_chains.ll | 4 +- .../Transforms/Attributor/memory_locations.ll | 154 +-- llvm/test/Transforms/Attributor/noalias.ll | 85 +- .../test/Transforms/Attributor/nocapture-2.ll | 146 +-- llvm/test/Transforms/Attributor/nodelete.ll | 2 - llvm/test/Transforms/Attributor/nofree.ll | 134 ++- llvm/test/Transforms/Attributor/nonnull.ll | 1004 ++++++++++------ llvm/test/Transforms/Attributor/norecurse.ll | 83 +- llvm/test/Transforms/Attributor/noreturn.ll | 17 +- llvm/test/Transforms/Attributor/nosync.ll | 62 +- llvm/test/Transforms/Attributor/nounwind.ll | 31 +- llvm/test/Transforms/Attributor/potential.ll | 87 +- llvm/test/Transforms/Attributor/range.ll | 41 +- .../read_write_returned_arguments_scc.ll | 10 +- llvm/test/Transforms/Attributor/returned.ll | 369 +++--- .../Attributor/value-simplify-gpu.ll | 4 +- .../Attributor/value-simplify-instances.ll | 33 +- llvm/test/Transforms/Attributor/willreturn.ll | 8 +- .../Transforms/OpenMP/remove_globalization.ll | 62 +- 34 files changed, 2159 insertions(+), 1573 deletions(-) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 4e4f768ed2cbd..de36d5d89a185 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -9586,7 +9586,8 @@ struct AACallEdgesFunction : public AACallEdgesImpl { // Visit all callable instructions. bool UsedAssumedInformation = false; if (!A.checkForAllCallLikeInstructions(ProcessCallInst, *this, - UsedAssumedInformation)) { + UsedAssumedInformation, + /* CheckBBLivenessOnly */ true)) { // If we haven't looked at all call like instructions, assume that there // are unknown callees. setHasUnknownCallee(true, Change); diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll index e2a78f1af66c6..0b946d41f008c 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll index c3060fd404159..b077dd3887800 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Test that we only promote arguments when the caller/callee have compatible diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll index c2f764b9284c5..a7bcf1e42252d 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Test that we only promote arguments when the caller/callee have compatible diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll index f8ec4d2ea3239..e0d0de56e05ce 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -76,7 +76,7 @@ define i32 @callercaller() { ; CHECK-LABEL: define {{[^@]+}}@callercaller ; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4 -; CHECK-NEXT: ret i32 undef +; CHECK-NEXT: ret i32 3 ; %B = alloca i32 store i32 2, i32* %B diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll index 7f3c75ab0e600..927efa6bfb17e 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" @@ -35,7 +35,7 @@ define i32 @callercaller() { ; CHECK-LABEL: define {{[^@]+}}@callercaller ; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4 -; CHECK-NEXT: ret i32 undef +; CHECK-NEXT: ret i32 3 ; %B = alloca i32 store i32 2, i32* %B diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll index 1bebfeeaee034..d368e22811894 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll @@ -147,15 +147,15 @@ define i32 @unions() nounwind { ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@unions ; IS__TUNIT_NPM-SAME: () #[[ATTR0]] { ; IS__TUNIT_NPM-NEXT: entry: -; IS__TUNIT_NPM-NEXT: [[MYSTR_CAST:%.*]] = bitcast %struct.MYstr* @mystr to i8* -; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i8, i8* [[MYSTR_CAST]], align 8 -; IS__TUNIT_NPM-NEXT: [[MYSTR_0_1:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* @mystr, i64 0, i32 1 -; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[MYSTR_0_1]], align 8 -; IS__TUNIT_NPM-NEXT: call void @vfu1(i8 [[TMP0]], i32 [[TMP1]]) #[[ATTR0]] ; IS__TUNIT_NPM-NEXT: [[MYSTR_CAST1:%.*]] = bitcast %struct.MYstr* @mystr to i8* -; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = load i8, i8* [[MYSTR_CAST1]], align 8 -; IS__TUNIT_NPM-NEXT: [[MYSTR_0_12:%.*]] = getelementptr [[STRUCT_MYSTR]], %struct.MYstr* @mystr, i64 0, i32 1 -; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = load i32, i32* [[MYSTR_0_12]], align 8 +; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i8, i8* [[MYSTR_CAST1]], align 8 +; IS__TUNIT_NPM-NEXT: [[MYSTR_0_12:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* @mystr, i64 0, i32 1 +; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[MYSTR_0_12]], align 8 +; IS__TUNIT_NPM-NEXT: call void @vfu1(i8 [[TMP0]], i32 [[TMP1]]) #[[ATTR0]] +; IS__TUNIT_NPM-NEXT: [[MYSTR_CAST:%.*]] = bitcast %struct.MYstr* @mystr to i8* +; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = load i8, i8* [[MYSTR_CAST]], align 8 +; IS__TUNIT_NPM-NEXT: [[MYSTR_0_1:%.*]] = getelementptr [[STRUCT_MYSTR]], %struct.MYstr* @mystr, i64 0, i32 1 +; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = load i32, i32* [[MYSTR_0_1]], align 8 ; IS__TUNIT_NPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(i8 [[TMP2]], i32 [[TMP3]]) #[[ATTR2:[0-9]+]] ; IS__TUNIT_NPM-NEXT: ret i32 [[RESULT]] ; @@ -164,7 +164,7 @@ define i32 @unions() nounwind { ; IS__CGSCC_OPM-SAME: () #[[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: call void @vfu1(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR:%.*]]) align 8 dereferenceable(8) @mystr) #[[ATTR0]] -; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR]]) align 8 dereferenceable(8) @mystr) #[[ATTR2:[0-9]+]] +; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR]]) align 8 dereferenceable(8) @mystr) #[[ATTR0]] ; IS__CGSCC_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__CGSCC_NPM: Function Attrs: nounwind @@ -176,7 +176,7 @@ define i32 @unions() nounwind { ; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = load i8, i8* getelementptr inbounds ([[STRUCT_MYSTR]], %struct.MYstr* @mystr, i32 0, i32 0), align 8 ; IS__CGSCC_NPM-NEXT: [[MYSTR_0_12:%.*]] = getelementptr [[STRUCT_MYSTR]], %struct.MYstr* @mystr, i64 0, i32 1 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = load i32, i32* [[MYSTR_0_12]], align 8 -; IS__CGSCC_NPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(i8 [[TMP1]], i32 [[TMP2]]) #[[ATTR2:[0-9]+]] +; IS__CGSCC_NPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(i8 [[TMP1]], i32 [[TMP2]]) #[[ATTR0]] ; IS__CGSCC_NPM-NEXT: ret i32 [[RESULT]] ; entry: @@ -277,7 +277,7 @@ define i32 @unions_v2() nounwind { ; IS__CGSCC_OPM-SAME: () #[[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: call void @vfu1(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR:%.*]]) align 8 dereferenceable(8) @mystr) #[[ATTR0]] -; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR]]) align 8 dereferenceable(8) @mystr) #[[ATTR2]] +; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_MYSTR]]) align 8 dereferenceable(8) @mystr) #[[ATTR0]] ; IS__CGSCC_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__CGSCC_NPM: Function Attrs: nounwind @@ -293,11 +293,13 @@ entry: ret i32 %result } ;. -; NOT_CGSCC_NPM: attributes #[[ATTR0:[0-9]+]] = { nounwind } -; NOT_CGSCC_NPM: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } -; NOT_CGSCC_NPM: attributes #[[ATTR2:[0-9]+]] = { nounwind readonly } +; IS__TUNIT____: attributes #[[ATTR0:[0-9]+]] = { nounwind } +; IS__TUNIT____: attributes #[[ATTR1:[0-9]+]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } +; IS__TUNIT____: attributes #[[ATTR2:[0-9]+]] = { nounwind readonly } +;. +; IS__CGSCC_OPM: attributes #[[ATTR0]] = { nounwind } +; IS__CGSCC_OPM: attributes #[[ATTR1]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } ;. ; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nounwind } ; IS__CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nounwind readonly } ;. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll b/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll index 35bf2c469e6aa..dae4fd00e81bc 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -49,7 +49,7 @@ define void @fn2(i32* %P, i1 %C) { ; IS__CGSCC_OPM: if.end: ; IS__CGSCC_OPM-NEXT: [[E_2:%.*]] = phi i32* [ [[P]], [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ] ; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[E_2]], align 4 -; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]]) #[[ATTR3:[0-9]+]] +; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]]) ; IS__CGSCC_OPM-NEXT: store i32 [[CALL]], i32* [[P]], align 4 ; IS__CGSCC_OPM-NEXT: br label [[FOR_COND1]] ; IS__CGSCC_OPM: exit: @@ -148,7 +148,7 @@ define void @fn_no_null_opt(i32* %P, i1 %C) null_pointer_is_valid { ; IS__CGSCC_OPM: if.end: ; IS__CGSCC_OPM-NEXT: [[E_2:%.*]] = phi i32* [ undef, [[ENTRY:%.*]] ], [ null, [[FOR_COND1:%.*]] ] ; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = load i32, i32* null, align 4294967296 -; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i32 @fn0(i32 [[TMP0]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i32 @fn0(i32 [[TMP0]]) ; IS__CGSCC_OPM-NEXT: store i32 [[CALL]], i32* [[P]], align 4 ; IS__CGSCC_OPM-NEXT: br label [[FOR_COND1]] ; IS__CGSCC_OPM: exit: @@ -212,12 +212,7 @@ entry: ; IS__TUNIT_NPM: attributes #[[ATTR0]] = { argmemonly nofree norecurse nosync nounwind } ; IS__TUNIT_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind null_pointer_is_valid } ;. -; IS__CGSCC_OPM: attributes #[[ATTR0]] = { argmemonly nofree norecurse nosync nounwind } -; IS__CGSCC_OPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR2]] = { nofree norecurse nosync nounwind null_pointer_is_valid } -; IS__CGSCC_OPM: attributes #[[ATTR3]] = { nounwind readnone } -;. -; IS__CGSCC_NPM: attributes #[[ATTR0]] = { argmemonly nofree norecurse nosync nounwind } -; IS__CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nofree norecurse nosync nounwind null_pointer_is_valid } +; IS__CGSCC____: attributes #[[ATTR0:[0-9]+]] = { argmemonly nofree norecurse nosync nounwind } +; IS__CGSCC____: attributes #[[ATTR1:[0-9]+]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR2:[0-9]+]] = { nofree norecurse nosync nounwind null_pointer_is_valid } ;. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll b/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll index 1b1198770875c..191ee3ae4ac61 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll @@ -103,9 +103,9 @@ define dso_local i16 @vararg_tests(i16 %a) { ; NOT_CGSCC_NPM-NEXT: [[ADD:%.*]] = add i16 7, [[CALL2]] ; NOT_CGSCC_NPM-NEXT: ret i16 [[ADD]] ; -; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone +; IS__CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@vararg_tests -; IS__CGSCC_NPM-SAME: (i16 [[A:%.*]]) #[[ATTR0]] { +; IS__CGSCC_NPM-SAME: (i16 [[A:%.*]]) #[[ATTR2:[0-9]+]] { ; IS__CGSCC_NPM-NEXT: [[CALL2:%.*]] = call i16 bitcast (i16 (i16, i16, ...)* @vararg_no_prop to i16 (i16)*)(i16 noundef 7) ; IS__CGSCC_NPM-NEXT: [[ADD:%.*]] = add i16 7, [[CALL2]] ; IS__CGSCC_NPM-NEXT: ret i16 [[ADD]] @@ -140,4 +140,5 @@ define internal i16 @vararg_no_prop(i16 %p1, i16 %p2, ...) { ;. ; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone } ; IS__CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nofree nosync nounwind readnone } ;. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll index fa8e4e6639799..c86179399cd90 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -66,24 +66,24 @@ define internal { i32, i32 } @foo(i32 %A, i32 %B) { } define void @caller(i1 %C) personality i32 (...)* @__gxx_personality_v0 { -; IS________OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS________OPM-LABEL: define {{[^@]+}}@caller -; IS________OPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] personality i32 (...)* @__gxx_personality_v0 { -; IS________OPM-NEXT: [[Q:%.*]] = alloca i32, align 4 -; IS________OPM-NEXT: [[W:%.*]] = call align 4 i32* @incdec(i1 [[C]], i32* noalias nofree noundef nonnull align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q]]) #[[ATTR2:[0-9]+]] -; IS________OPM-NEXT: [[S1:%.*]] = call { i32, i32 } @foo(i32 noundef 1, i32 noundef 2) #[[ATTR3:[0-9]+]] -; IS________OPM-NEXT: [[X1:%.*]] = extractvalue { i32, i32 } [[S1]], 0 -; IS________OPM-NEXT: [[S2:%.*]] = call { i32, i32 } @foo(i32 noundef 3, i32 noundef 4) #[[ATTR3]] -; IS________OPM-NEXT: br label [[OK:%.*]] -; IS________OPM: OK: -; IS________OPM-NEXT: [[X2:%.*]] = extractvalue { i32, i32 } [[S2]], 0 -; IS________OPM-NEXT: [[Z:%.*]] = add i32 [[X1]], [[X2]] -; IS________OPM-NEXT: store i32 [[Z]], i32* [[W]], align 4 -; IS________OPM-NEXT: br label [[RET:%.*]] -; IS________OPM: LPAD: -; IS________OPM-NEXT: unreachable -; IS________OPM: RET: -; IS________OPM-NEXT: ret void +; IS__TUNIT_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@caller +; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] personality i32 (...)* @__gxx_personality_v0 { +; IS__TUNIT_OPM-NEXT: [[Q:%.*]] = alloca i32, align 4 +; IS__TUNIT_OPM-NEXT: [[W:%.*]] = call align 4 i32* @incdec(i1 [[C]], i32* noalias nofree noundef nonnull align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q]]) #[[ATTR2:[0-9]+]] +; IS__TUNIT_OPM-NEXT: [[S1:%.*]] = call { i32, i32 } @foo(i32 noundef 1, i32 noundef 2) #[[ATTR3:[0-9]+]] +; IS__TUNIT_OPM-NEXT: [[X1:%.*]] = extractvalue { i32, i32 } [[S1]], 0 +; IS__TUNIT_OPM-NEXT: [[S2:%.*]] = call { i32, i32 } @foo(i32 noundef 3, i32 noundef 4) #[[ATTR3]] +; IS__TUNIT_OPM-NEXT: br label [[OK:%.*]] +; IS__TUNIT_OPM: OK: +; IS__TUNIT_OPM-NEXT: [[X2:%.*]] = extractvalue { i32, i32 } [[S2]], 0 +; IS__TUNIT_OPM-NEXT: [[Z:%.*]] = add i32 [[X1]], [[X2]] +; IS__TUNIT_OPM-NEXT: store i32 [[Z]], i32* [[W]], align 4 +; IS__TUNIT_OPM-NEXT: br label [[RET:%.*]] +; IS__TUNIT_OPM: LPAD: +; IS__TUNIT_OPM-NEXT: unreachable +; IS__TUNIT_OPM: RET: +; IS__TUNIT_OPM-NEXT: ret void ; ; IS__TUNIT_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@caller @@ -104,6 +104,25 @@ define void @caller(i1 %C) personality i32 (...)* @__gxx_personality_v0 { ; IS__TUNIT_NPM: RET: ; IS__TUNIT_NPM-NEXT: ret void ; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@caller +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] personality i32 (...)* @__gxx_personality_v0 { +; IS__CGSCC_OPM-NEXT: [[Q:%.*]] = alloca i32, align 4 +; IS__CGSCC_OPM-NEXT: [[W:%.*]] = call align 4 i32* @incdec(i1 [[C]], i32* noalias nofree noundef nonnull align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q]]) #[[ATTR2:[0-9]+]] +; IS__CGSCC_OPM-NEXT: [[S1:%.*]] = call { i32, i32 } @foo(i32 noundef 1, i32 noundef 2) #[[ATTR3:[0-9]+]] +; IS__CGSCC_OPM-NEXT: [[X1:%.*]] = extractvalue { i32, i32 } [[S1]], 0 +; IS__CGSCC_OPM-NEXT: [[S2:%.*]] = call { i32, i32 } @foo(i32 noundef 3, i32 noundef 4) #[[ATTR4:[0-9]+]] +; IS__CGSCC_OPM-NEXT: br label [[OK:%.*]] +; IS__CGSCC_OPM: OK: +; IS__CGSCC_OPM-NEXT: [[X2:%.*]] = extractvalue { i32, i32 } [[S2]], 0 +; IS__CGSCC_OPM-NEXT: [[Z:%.*]] = add i32 [[X1]], [[X2]] +; IS__CGSCC_OPM-NEXT: store i32 [[Z]], i32* [[W]], align 4 +; IS__CGSCC_OPM-NEXT: br label [[RET:%.*]] +; IS__CGSCC_OPM: LPAD: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: RET: +; IS__CGSCC_OPM-NEXT: ret void +; ; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@caller ; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] personality i32 (...)* @__gxx_personality_v0 { @@ -111,7 +130,7 @@ define void @caller(i1 %C) personality i32 (...)* @__gxx_personality_v0 { ; IS__CGSCC_NPM-NEXT: [[W:%.*]] = call i32* @incdec(i1 [[C]], i32* noalias nofree noundef nonnull align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q]]) #[[ATTR2:[0-9]+]] ; IS__CGSCC_NPM-NEXT: [[S1:%.*]] = call { i32, i32 } @foo(i32 noundef 1, i32 noundef 2) #[[ATTR3:[0-9]+]] ; IS__CGSCC_NPM-NEXT: [[X1:%.*]] = extractvalue { i32, i32 } [[S1]], 0 -; IS__CGSCC_NPM-NEXT: [[S2:%.*]] = call { i32, i32 } @foo(i32 noundef 3, i32 noundef 4) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: [[S2:%.*]] = call { i32, i32 } @foo(i32 noundef 3, i32 noundef 4) #[[ATTR4:[0-9]+]] ; IS__CGSCC_NPM-NEXT: br label [[OK:%.*]] ; IS__CGSCC_NPM: OK: ; IS__CGSCC_NPM-NEXT: [[X2:%.*]] = extractvalue { i32, i32 } [[S2]], 0 @@ -159,5 +178,6 @@ declare i32 @__gxx_personality_v0(...) ; IS__CGSCC____: attributes #[[ATTR0]] = { argmemonly nofree norecurse nosync nounwind willreturn } ; IS__CGSCC____: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } ; IS__CGSCC____: attributes #[[ATTR2:[0-9]+]] = { nounwind willreturn } -; IS__CGSCC____: attributes #[[ATTR3:[0-9]+]] = { nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR3:[0-9]+]] = { readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR4:[0-9]+]] = { nounwind readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll index e5b9c70b140bd..9129d25f6bbaf 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll @@ -80,33 +80,19 @@ define %0 @caller(i1 %Q) { ; Similar to @caller but the result of both calls are actually used. define i32 @caller2(i1 %Q) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@caller2 -; IS__TUNIT____-SAME: (i1 [[Q:%.*]]) #[[ATTR0]] { -; IS__TUNIT____-NEXT: [[X:%.*]] = call [[TMP0:%.*]] @foo(i1 [[Q]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: [[A:%.*]] = extractvalue [[TMP0]] [[X]], 0 -; IS__TUNIT____-NEXT: [[B:%.*]] = extractvalue [[TMP0]] [[X]], 1 -; IS__TUNIT____-NEXT: [[Y:%.*]] = call [[TMP0]] @bar(i1 [[Q]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: [[C:%.*]] = extractvalue [[TMP0]] [[Y]], 0 -; IS__TUNIT____-NEXT: [[D:%.*]] = extractvalue [[TMP0]] [[Y]], 1 -; IS__TUNIT____-NEXT: [[M:%.*]] = add i32 [[A]], [[C]] -; IS__TUNIT____-NEXT: [[N:%.*]] = add i32 [[B]], [[D]] -; IS__TUNIT____-NEXT: [[R:%.*]] = add i32 [[N]], [[M]] -; IS__TUNIT____-NEXT: ret i32 [[R]] -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@caller2 -; IS__CGSCC____-SAME: (i1 [[Q:%.*]]) #[[ATTR0]] { -; IS__CGSCC____-NEXT: [[X:%.*]] = call [[TMP0:%.*]] @foo(i1 [[Q]]) #[[ATTR2:[0-9]+]] -; IS__CGSCC____-NEXT: [[A:%.*]] = extractvalue [[TMP0]] [[X]], 0 -; IS__CGSCC____-NEXT: [[B:%.*]] = extractvalue [[TMP0]] [[X]], 1 -; IS__CGSCC____-NEXT: [[Y:%.*]] = call [[TMP0]] @bar(i1 [[Q]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: [[C:%.*]] = extractvalue [[TMP0]] [[Y]], 0 -; IS__CGSCC____-NEXT: [[D:%.*]] = extractvalue [[TMP0]] [[Y]], 1 -; IS__CGSCC____-NEXT: [[M:%.*]] = add i32 [[A]], [[C]] -; IS__CGSCC____-NEXT: [[N:%.*]] = add i32 [[B]], [[D]] -; IS__CGSCC____-NEXT: [[R:%.*]] = add i32 [[N]], [[M]] -; IS__CGSCC____-NEXT: ret i32 [[R]] +; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK-LABEL: define {{[^@]+}}@caller2 +; CHECK-SAME: (i1 [[Q:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[X:%.*]] = call [[TMP0:%.*]] @foo(i1 [[Q]]) #[[ATTR1]] +; CHECK-NEXT: [[A:%.*]] = extractvalue [[TMP0]] [[X]], 0 +; CHECK-NEXT: [[B:%.*]] = extractvalue [[TMP0]] [[X]], 1 +; CHECK-NEXT: [[Y:%.*]] = call [[TMP0]] @bar(i1 [[Q]]) #[[ATTR1]] +; CHECK-NEXT: [[C:%.*]] = extractvalue [[TMP0]] [[Y]], 0 +; CHECK-NEXT: [[D:%.*]] = extractvalue [[TMP0]] [[Y]], 1 +; CHECK-NEXT: [[M:%.*]] = add i32 [[A]], [[C]] +; CHECK-NEXT: [[N:%.*]] = add i32 [[B]], [[D]] +; CHECK-NEXT: [[R:%.*]] = add i32 [[N]], [[M]] +; CHECK-NEXT: ret i32 [[R]] ; %X = call %0 @foo(i1 %Q) %A = extractvalue %0 %X, 0 @@ -126,5 +112,4 @@ define i32 @caller2(i1 %Q) { ;. ; IS__CGSCC____: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ; IS__CGSCC____: attributes #[[ATTR1]] = { readnone willreturn } -; IS__CGSCC____: attributes #[[ATTR2]] = { nounwind readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll index 5b5240df354c9..ee703cd066d6e 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll index 4f9a491605511..9084185ed41b5 100644 --- a/llvm/test/Transforms/Attributor/align.ll +++ b/llvm/test/Transforms/Attributor/align.ll @@ -86,20 +86,30 @@ define i32* @test5_2() { ; TEST 6 ; SCC define i32* @test6_1() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@test6_1 -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32* undef +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test6_1 +; NOT_CGSCC_NPM-SAME: () #[[ATTR1:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: ret i32* undef +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test6_1 +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32* undef ; %ret = tail call i32* @test6_2() ret i32* %ret } define i32* @test6_2() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@test6_2 -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32* undef +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test6_2 +; NOT_CGSCC_NPM-SAME: () #[[ATTR1]] { +; NOT_CGSCC_NPM-NEXT: ret i32* undef +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test6_2 +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32* undef ; %ret = tail call i32* @test6_1() ret i32* %ret @@ -158,16 +168,27 @@ define internal i8* @f1(i8* readnone %0) local_unnamed_addr #0 { ; Function Attrs: nounwind readnone ssp uwtable define internal i8* @f2(i8* readnone %0) local_unnamed_addr #0 { -; IS__CGSCC____: Function Attrs: noinline nounwind uwtable -; IS__CGSCC____-LABEL: define {{[^@]+}}@f2 -; IS__CGSCC____-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 2: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 3: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 4: -; IS__CGSCC____-NEXT: unreachable +; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2 +; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 2: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 3: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 4: +; IS__CGSCC_OPM-NEXT: unreachable +; +; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f2 +; IS__CGSCC_NPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 3: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 4: +; IS__CGSCC_NPM-NEXT: unreachable ; %2 = icmp eq i8* %0, null br i1 %2, label %5, label %3 @@ -188,14 +209,23 @@ define internal i8* @f2(i8* readnone %0) local_unnamed_addr #0 { ; Function Attrs: nounwind readnone ssp uwtable define internal i8* @f3(i8* readnone %0) local_unnamed_addr #0 { -; IS__CGSCC____: Function Attrs: noinline nounwind uwtable -; IS__CGSCC____-LABEL: define {{[^@]+}}@f3 -; IS__CGSCC____-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC____-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC____: 2: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 3: -; IS__CGSCC____-NEXT: ret i8* @a1 +; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3 +; IS__CGSCC_OPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { +; IS__CGSCC_OPM-NEXT: br label [[TMP3:%.*]] +; IS__CGSCC_OPM: 2: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 3: +; IS__CGSCC_OPM-NEXT: ret i8* @a1 +; +; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f3 +; IS__CGSCC_NPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 3: +; IS__CGSCC_NPM-NEXT: ret i8* @a1 ; %2 = icmp eq i8* %0, null br i1 %2, label %3, label %5 @@ -259,16 +289,27 @@ define internal i8* @f1b(i8* readnone %0) local_unnamed_addr #0 { ; Function Attrs: nounwind readnone ssp uwtable define internal i8* @f2b(i8* readnone %0) local_unnamed_addr #0 { ; -; IS__CGSCC____: Function Attrs: noinline nounwind uwtable -; IS__CGSCC____-LABEL: define {{[^@]+}}@f2b -; IS__CGSCC____-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 2: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 3: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 4: -; IS__CGSCC____-NEXT: unreachable +; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2b +; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 2: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 3: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 4: +; IS__CGSCC_OPM-NEXT: unreachable +; +; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f2b +; IS__CGSCC_NPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 3: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 4: +; IS__CGSCC_NPM-NEXT: unreachable ; %2 = icmp eq i8* %0, null br i1 %2, label %5, label %3 @@ -290,14 +331,23 @@ define internal i8* @f2b(i8* readnone %0) local_unnamed_addr #0 { ; Function Attrs: nounwind readnone ssp uwtable define internal i8* @f3b(i8* readnone %0) local_unnamed_addr #0 { ; -; IS__CGSCC____: Function Attrs: noinline nounwind uwtable -; IS__CGSCC____-LABEL: define {{[^@]+}}@f3b -; IS__CGSCC____-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC____-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC____: 2: -; IS__CGSCC____-NEXT: unreachable -; IS__CGSCC____: 3: -; IS__CGSCC____-NEXT: ret i8* @a1 +; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3b +; IS__CGSCC_OPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { +; IS__CGSCC_OPM-NEXT: br label [[TMP3:%.*]] +; IS__CGSCC_OPM: 2: +; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM: 3: +; IS__CGSCC_OPM-NEXT: ret i8* @a1 +; +; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f3b +; IS__CGSCC_NPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 3: +; IS__CGSCC_NPM-NEXT: ret i8* @a1 ; %2 = icmp eq i8* %0, null br i1 %2, label %3, label %5 @@ -323,23 +373,23 @@ define align 4 i32* @test7b(i32* align 32 %p) #0 { ; TEST 8 define void @test8_helper() { -; IS__TUNIT____-LABEL: define {{[^@]+}}@test8_helper() { -; IS__TUNIT____-NEXT: [[PTR0:%.*]] = tail call i32* @unknown() -; IS__TUNIT____-NEXT: [[PTR1:%.*]] = tail call align 4 i32* @unknown() -; IS__TUNIT____-NEXT: [[PTR2:%.*]] = tail call align 8 i32* @unknown() -; IS__TUNIT____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone [[PTR0]]) #[[ATTR1:[0-9]+]] -; IS__TUNIT____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____-LABEL: define {{[^@]+}}@test8_helper() { -; IS__CGSCC____-NEXT: [[PTR0:%.*]] = tail call i32* @unknown() -; IS__CGSCC____-NEXT: [[PTR1:%.*]] = tail call align 4 i32* @unknown() -; IS__CGSCC____-NEXT: [[PTR2:%.*]] = tail call align 8 i32* @unknown() -; IS__CGSCC____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone [[PTR0]]) #[[ATTR2:[0-9]+]] -; IS__CGSCC____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test8_helper() { +; NOT_CGSCC_OPM-NEXT: [[PTR0:%.*]] = tail call i32* @unknown() +; NOT_CGSCC_OPM-NEXT: [[PTR1:%.*]] = tail call align 4 i32* @unknown() +; NOT_CGSCC_OPM-NEXT: [[PTR2:%.*]] = tail call align 8 i32* @unknown() +; NOT_CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone [[PTR0]]) #[[ATTR2:[0-9]+]] +; NOT_CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test8_helper() { +; IS__CGSCC_OPM-NEXT: [[PTR0:%.*]] = tail call i32* @unknown() +; IS__CGSCC_OPM-NEXT: [[PTR1:%.*]] = tail call align 4 i32* @unknown() +; IS__CGSCC_OPM-NEXT: [[PTR2:%.*]] = tail call align 8 i32* @unknown() +; IS__CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone [[PTR0]]) #[[ATTR3:[0-9]+]] +; IS__CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: tail call void @test8(i32* noalias nocapture readnone align 8 [[PTR2]], i32* noalias nocapture readnone align 4 [[PTR1]], i32* noalias nocapture readnone align 4 [[PTR1]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: ret void ; %ptr0 = tail call i32* @unknown() %ptr1 = tail call align 4 i32* @unknown() @@ -353,21 +403,21 @@ define void @test8_helper() { declare void @user_i32_ptr(i32* nocapture readnone) nounwind define internal void @test8(i32* %a, i32* %b, i32* %c) { -; IS__TUNIT____: Function Attrs: nounwind -; IS__TUNIT____-LABEL: define {{[^@]+}}@test8 -; IS__TUNIT____-SAME: (i32* noalias nocapture readnone align 4 [[A:%.*]], i32* noalias nocapture readnone align 4 [[B:%.*]], i32* noalias nocapture readnone [[C:%.*]]) #[[ATTR1]] { -; IS__TUNIT____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[A]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[B]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone [[C]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nounwind -; IS__CGSCC____-LABEL: define {{[^@]+}}@test8 -; IS__CGSCC____-SAME: (i32* noalias nocapture readnone align 4 [[A:%.*]], i32* noalias nocapture readnone align 4 [[B:%.*]], i32* noalias nocapture readnone [[C:%.*]]) #[[ATTR2]] { -; IS__CGSCC____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[A]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[B]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone [[C]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test8 +; NOT_CGSCC_OPM-SAME: (i32* noalias nocapture readnone align 4 [[A:%.*]], i32* noalias nocapture readnone align 4 [[B:%.*]], i32* noalias nocapture readnone [[C:%.*]]) #[[ATTR2]] { +; NOT_CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[A]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[B]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone [[C]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test8 +; IS__CGSCC_OPM-SAME: (i32* noalias nocapture readnone align 4 [[A:%.*]], i32* noalias nocapture readnone align 4 [[B:%.*]], i32* noalias nocapture readnone [[C:%.*]]) #[[ATTR3]] { +; IS__CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[A]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone align 4 [[B]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture readnone [[C]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: ret void ; call void @user_i32_ptr(i32* %a) call void @user_i32_ptr(i32* %b) @@ -395,43 +445,43 @@ define void @test9_traversal(i1 %cnd, i32* align 4 %B, i32* align 8 %C) { ; FIXME: This will work with an upcoming patch (D66618 or similar) ; store i32 -1, i32* %g1, align 32 define i32* @test10a(i32* align 32 %p) { -; IS__TUNIT____: Function Attrs: nofree nosync nounwind -; IS__TUNIT____-LABEL: define {{[^@]+}}@test10a -; IS__TUNIT____-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR2:[0-9]+]] { -; IS__TUNIT____-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 -; IS__TUNIT____-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 -; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[R:%.*]] = call align 32 i32* @test10a(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR2]] -; IS__TUNIT____-NEXT: store i32 1, i32* [[R]], align 32 -; IS__TUNIT____-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__TUNIT____-NEXT: br label [[E:%.*]] -; IS__TUNIT____: f: -; IS__TUNIT____-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__TUNIT____-NEXT: store i32 -1, i32* [[G1]], align 32 -; IS__TUNIT____-NEXT: br label [[E]] -; IS__TUNIT____: e: -; IS__TUNIT____-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] -; IS__TUNIT____-NEXT: ret i32* [[PHI]] -; -; IS__CGSCC____: Function Attrs: nofree nosync nounwind -; IS__CGSCC____-LABEL: define {{[^@]+}}@test10a -; IS__CGSCC____-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR3:[0-9]+]] { -; IS__CGSCC____-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 -; IS__CGSCC____-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 -; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[R:%.*]] = call align 32 i32* @test10a(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR3]] -; IS__CGSCC____-NEXT: store i32 1, i32* [[R]], align 32 -; IS__CGSCC____-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__CGSCC____-NEXT: br label [[E:%.*]] -; IS__CGSCC____: f: -; IS__CGSCC____-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__CGSCC____-NEXT: store i32 -1, i32* [[G1]], align 32 -; IS__CGSCC____-NEXT: br label [[E]] -; IS__CGSCC____: e: -; IS__CGSCC____-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] -; IS__CGSCC____-NEXT: ret i32* [[PHI]] +; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test10a +; NOT_CGSCC_OPM-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR3:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 +; NOT_CGSCC_OPM-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; NOT_CGSCC_OPM: t: +; NOT_CGSCC_OPM-NEXT: [[R:%.*]] = call align 32 i32* @test10a(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR3]] +; NOT_CGSCC_OPM-NEXT: store i32 1, i32* [[R]], align 32 +; NOT_CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; NOT_CGSCC_OPM-NEXT: br label [[E:%.*]] +; NOT_CGSCC_OPM: f: +; NOT_CGSCC_OPM-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; NOT_CGSCC_OPM-NEXT: store i32 -1, i32* [[G1]], align 32 +; NOT_CGSCC_OPM-NEXT: br label [[E]] +; NOT_CGSCC_OPM: e: +; NOT_CGSCC_OPM-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] +; NOT_CGSCC_OPM-NEXT: ret i32* [[PHI]] +; +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test10a +; IS__CGSCC_OPM-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; IS__CGSCC_OPM: t: +; IS__CGSCC_OPM-NEXT: [[R:%.*]] = call align 32 i32* @test10a(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR4]] +; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[R]], align 32 +; IS__CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; IS__CGSCC_OPM-NEXT: br label [[E:%.*]] +; IS__CGSCC_OPM: f: +; IS__CGSCC_OPM-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; IS__CGSCC_OPM-NEXT: store i32 -1, i32* [[G1]], align 32 +; IS__CGSCC_OPM-NEXT: br label [[E]] +; IS__CGSCC_OPM: e: +; IS__CGSCC_OPM-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] +; IS__CGSCC_OPM-NEXT: ret i32* [[PHI]] ; %l = load i32, i32* %p %c = icmp eq i32 %l, 0 @@ -457,43 +507,43 @@ e: ; FIXME: This will work with an upcoming patch (D66618 or similar) ; store i32 -1, i32* %g1, align 32 define i32* @test10b(i32* align 32 %p) { -; IS__TUNIT____: Function Attrs: nofree nosync nounwind -; IS__TUNIT____-LABEL: define {{[^@]+}}@test10b -; IS__TUNIT____-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR2]] { -; IS__TUNIT____-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 -; IS__TUNIT____-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 -; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[R:%.*]] = call align 32 i32* @test10b(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR2]] -; IS__TUNIT____-NEXT: store i32 1, i32* [[R]], align 32 -; IS__TUNIT____-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__TUNIT____-NEXT: br label [[E:%.*]] -; IS__TUNIT____: f: -; IS__TUNIT____-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8 -; IS__TUNIT____-NEXT: store i32 -1, i32* [[G1]], align 32 -; IS__TUNIT____-NEXT: br label [[E]] -; IS__TUNIT____: e: -; IS__TUNIT____-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] -; IS__TUNIT____-NEXT: ret i32* [[PHI]] -; -; IS__CGSCC____: Function Attrs: nofree nosync nounwind -; IS__CGSCC____-LABEL: define {{[^@]+}}@test10b -; IS__CGSCC____-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR3]] { -; IS__CGSCC____-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 -; IS__CGSCC____-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 -; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[R:%.*]] = call align 32 i32* @test10b(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR3]] -; IS__CGSCC____-NEXT: store i32 1, i32* [[R]], align 32 -; IS__CGSCC____-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 -; IS__CGSCC____-NEXT: br label [[E:%.*]] -; IS__CGSCC____: f: -; IS__CGSCC____-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8 -; IS__CGSCC____-NEXT: store i32 -1, i32* [[G1]], align 32 -; IS__CGSCC____-NEXT: br label [[E]] -; IS__CGSCC____: e: -; IS__CGSCC____-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] -; IS__CGSCC____-NEXT: ret i32* [[PHI]] +; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test10b +; NOT_CGSCC_OPM-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR3]] { +; NOT_CGSCC_OPM-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 +; NOT_CGSCC_OPM-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; NOT_CGSCC_OPM: t: +; NOT_CGSCC_OPM-NEXT: [[R:%.*]] = call align 32 i32* @test10b(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR3]] +; NOT_CGSCC_OPM-NEXT: store i32 1, i32* [[R]], align 32 +; NOT_CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; NOT_CGSCC_OPM-NEXT: br label [[E:%.*]] +; NOT_CGSCC_OPM: f: +; NOT_CGSCC_OPM-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8 +; NOT_CGSCC_OPM-NEXT: store i32 -1, i32* [[G1]], align 32 +; NOT_CGSCC_OPM-NEXT: br label [[E]] +; NOT_CGSCC_OPM: e: +; NOT_CGSCC_OPM-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] +; NOT_CGSCC_OPM-NEXT: ret i32* [[PHI]] +; +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test10b +; IS__CGSCC_OPM-SAME: (i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR4]] { +; IS__CGSCC_OPM-NEXT: [[L:%.*]] = load i32, i32* [[P]], align 32 +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; IS__CGSCC_OPM: t: +; IS__CGSCC_OPM-NEXT: [[R:%.*]] = call align 32 i32* @test10b(i32* nofree noundef nonnull align 32 dereferenceable(4) "no-capture-maybe-returned" [[P]]) #[[ATTR4]] +; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[R]], align 32 +; IS__CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr i32, i32* [[P]], i32 8 +; IS__CGSCC_OPM-NEXT: br label [[E:%.*]] +; IS__CGSCC_OPM: f: +; IS__CGSCC_OPM-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[P]], i32 -8 +; IS__CGSCC_OPM-NEXT: store i32 -1, i32* [[G1]], align 32 +; IS__CGSCC_OPM-NEXT: br label [[E]] +; IS__CGSCC_OPM: e: +; IS__CGSCC_OPM-NEXT: [[PHI:%.*]] = phi i32* [ [[G0]], [[T]] ], [ [[G1]], [[F]] ] +; IS__CGSCC_OPM-NEXT: ret i32* [[PHI]] ; %l = load i32, i32* %p %c = icmp eq i32 %l, 0 @@ -514,19 +564,19 @@ e: define i64 @test11(i32* %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@test11 -; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[P:%.*]]) #[[ATTR3:[0-9]+]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[RET:%.*]] = load i64, i64* [[P_CAST]], align 8 -; IS__TUNIT____-NEXT: ret i64 [[RET]] -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@test11 -; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[P:%.*]]) #[[ATTR4:[0-9]+]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[RET:%.*]] = load i64, i64* [[P_CAST]], align 8 -; IS__CGSCC____-NEXT: ret i64 [[RET]] +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test11 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[P:%.*]]) #[[ATTR4:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[P_CAST]], align 8 +; NOT_CGSCC_OPM-NEXT: ret i64 [[RET]] +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test11 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[P:%.*]]) #[[ATTR5:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[P_CAST]], align 8 +; IS__CGSCC_OPM-NEXT: ret i64 [[RET]] ; %p-cast = bitcast i32* %p to i64* %ret = load i64, i64* %p-cast, align 8 @@ -538,23 +588,23 @@ define i64 @test11(i32* %p) { ; FXIME: %p should have nonnull define i64 @test12-1(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-1 -; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 16 [[P:%.*]]) #[[ATTR3]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__TUNIT____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__TUNIT____-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX1]], align 16 -; IS__TUNIT____-NEXT: ret i64 [[RET]] -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-1 -; IS__CGSCC____-SAME: (i32* nocapture nofree readonly align 16 [[P:%.*]]) #[[ATTR4]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__CGSCC____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__CGSCC____-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX1]], align 16 -; IS__CGSCC____-NEXT: ret i64 [[RET]] +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-1 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree readonly align 16 [[P:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; NOT_CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX1]], align 16 +; NOT_CGSCC_OPM-NEXT: ret i64 [[RET]] +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-1 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree readonly align 16 [[P:%.*]]) #[[ATTR5]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX1]], align 16 +; IS__CGSCC_OPM-NEXT: ret i64 [[RET]] ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 1 @@ -564,21 +614,21 @@ define i64 @test12-1(i32* align 4 %p) { } define i64 @test12-2(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-2 -; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR3]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__TUNIT____-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX0]], align 16 -; IS__TUNIT____-NEXT: ret i64 [[RET]] -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-2 -; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR4]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__CGSCC____-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX0]], align 16 -; IS__CGSCC____-NEXT: ret i64 [[RET]] +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-2 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree nonnull readonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; NOT_CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX0]], align 16 +; NOT_CGSCC_OPM-NEXT: ret i64 [[RET]] +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-2 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree nonnull readonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR5]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = load i64, i64* [[ARRAYIDX0]], align 16 +; IS__CGSCC_OPM-NEXT: ret i64 [[RET]] ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 0 @@ -588,23 +638,23 @@ define i64 @test12-2(i32* align 4 %p) { ; FXIME: %p should have nonnull define void @test12-3(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-3 -; IS__TUNIT____-SAME: (i32* nocapture nofree writeonly align 16 [[P:%.*]]) #[[ATTR4:[0-9]+]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__TUNIT____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__TUNIT____-NEXT: store i64 0, i64* [[ARRAYIDX1]], align 16 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-3 -; IS__CGSCC____-SAME: (i32* nocapture nofree writeonly align 16 [[P:%.*]]) #[[ATTR5:[0-9]+]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__CGSCC____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__CGSCC____-NEXT: store i64 0, i64* [[ARRAYIDX1]], align 16 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-3 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree writeonly align 16 [[P:%.*]]) #[[ATTR5:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; NOT_CGSCC_OPM-NEXT: store i64 0, i64* [[ARRAYIDX1]], align 16 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-3 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree writeonly align 16 [[P:%.*]]) #[[ATTR6:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; IS__CGSCC_OPM-NEXT: store i64 0, i64* [[ARRAYIDX1]], align 16 +; IS__CGSCC_OPM-NEXT: ret void ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 1 @@ -614,21 +664,21 @@ define void @test12-3(i32* align 4 %p) { } define void @test12-4(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-4 -; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR4]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__TUNIT____-NEXT: store i64 0, i64* [[ARRAYIDX0]], align 16 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-4 -; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__CGSCC____-NEXT: store i64 0, i64* [[ARRAYIDX0]], align 16 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-4 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree nonnull writeonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR5]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; NOT_CGSCC_OPM-NEXT: store i64 0, i64* [[ARRAYIDX0]], align 16 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-4 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree nonnull writeonly align 16 dereferenceable(8) [[P:%.*]]) #[[ATTR6]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; IS__CGSCC_OPM-NEXT: store i64 0, i64* [[ARRAYIDX0]], align 16 +; IS__CGSCC_OPM-NEXT: ret void ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 0 @@ -639,23 +689,23 @@ define void @test12-4(i32* align 4 %p) { declare void @use(i64*) willreturn nounwind define void @test12-5(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: nounwind willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-5 -; IS__TUNIT____-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR5:[0-9]+]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__TUNIT____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__TUNIT____-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX1]]) #[[ATTR5]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nounwind willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-5 -; IS__CGSCC____-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR6:[0-9]+]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 -; IS__CGSCC____-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 -; IS__CGSCC____-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX1]]) #[[ATTR6]] -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-5 +; NOT_CGSCC_OPM-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR6:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; NOT_CGSCC_OPM-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX1]]) #[[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-5 +; IS__CGSCC_OPM-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR7:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 1 +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX1:%.*]] = getelementptr i64, i64* [[ARRAYIDX0]], i64 3 +; IS__CGSCC_OPM-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX1]]) #[[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 1 @@ -665,21 +715,21 @@ define void @test12-5(i32* align 4 %p) { } define void @test12-6(i32* align 4 %p) { -; IS__TUNIT____: Function Attrs: nounwind willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@test12-6 -; IS__TUNIT____-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR5]] { -; IS__TUNIT____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__TUNIT____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__TUNIT____-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX0]]) #[[ATTR5]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nounwind willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@test12-6 -; IS__CGSCC____-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR6]] { -; IS__CGSCC____-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* -; IS__CGSCC____-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 -; IS__CGSCC____-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX0]]) #[[ATTR6]] -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test12-6 +; NOT_CGSCC_OPM-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR6]] { +; NOT_CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; NOT_CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; NOT_CGSCC_OPM-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX0]]) #[[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test12-6 +; IS__CGSCC_OPM-SAME: (i32* align 16 [[P:%.*]]) #[[ATTR7]] { +; IS__CGSCC_OPM-NEXT: [[P_CAST:%.*]] = bitcast i32* [[P]] to i64* +; IS__CGSCC_OPM-NEXT: [[ARRAYIDX0:%.*]] = getelementptr i64, i64* [[P_CAST]], i64 0 +; IS__CGSCC_OPM-NEXT: tail call void @use(i64* align 16 [[ARRAYIDX0]]) #[[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void ; %p-cast = bitcast i32* %p to i64* %arrayidx0 = getelementptr i64, i64* %p-cast, i64 0 @@ -688,31 +738,31 @@ define void @test12-6(i32* align 4 %p) { } define void @test13(i1 %c, i32* align 32 %dst) #0 { -; IS__TUNIT____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test13 -; IS__TUNIT____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR6:[0-9]+]] { -; IS__TUNIT____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__TUNIT____: truebb: -; IS__TUNIT____-NEXT: br label [[END:%.*]] -; IS__TUNIT____: falsebb: -; IS__TUNIT____-NEXT: br label [[END]] -; IS__TUNIT____: end: -; IS__TUNIT____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ null, [[FALSEBB]] ] -; IS__TUNIT____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test13 -; IS__CGSCC____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR7:[0-9]+]] { -; IS__CGSCC____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__CGSCC____: truebb: -; IS__CGSCC____-NEXT: br label [[END:%.*]] -; IS__CGSCC____: falsebb: -; IS__CGSCC____-NEXT: br label [[END]] -; IS__CGSCC____: end: -; IS__CGSCC____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ null, [[FALSEBB]] ] -; IS__CGSCC____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test13 +; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR7:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; NOT_CGSCC_OPM: truebb: +; NOT_CGSCC_OPM-NEXT: br label [[END:%.*]] +; NOT_CGSCC_OPM: falsebb: +; NOT_CGSCC_OPM-NEXT: br label [[END]] +; NOT_CGSCC_OPM: end: +; NOT_CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ null, [[FALSEBB]] ] +; NOT_CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test13 +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; IS__CGSCC_OPM: truebb: +; IS__CGSCC_OPM-NEXT: br label [[END:%.*]] +; IS__CGSCC_OPM: falsebb: +; IS__CGSCC_OPM-NEXT: br label [[END]] +; IS__CGSCC_OPM: end: +; IS__CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ null, [[FALSEBB]] ] +; IS__CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; IS__CGSCC_OPM-NEXT: ret void ; br i1 %c, label %truebb, label %falsebb truebb: @@ -726,31 +776,31 @@ end: } define void @test13-1(i1 %c, i32* align 32 %dst) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test13-1 -; IS__TUNIT____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR7:[0-9]+]] { -; IS__TUNIT____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__TUNIT____: truebb: -; IS__TUNIT____-NEXT: br label [[END:%.*]] -; IS__TUNIT____: falsebb: -; IS__TUNIT____-NEXT: br label [[END]] -; IS__TUNIT____: end: -; IS__TUNIT____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 48 to i32*), [[FALSEBB]] ] -; IS__TUNIT____-NEXT: store i32 0, i32* [[PTR]], align 16 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test13-1 -; IS__CGSCC____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8:[0-9]+]] { -; IS__CGSCC____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__CGSCC____: truebb: -; IS__CGSCC____-NEXT: br label [[END:%.*]] -; IS__CGSCC____: falsebb: -; IS__CGSCC____-NEXT: br label [[END]] -; IS__CGSCC____: end: -; IS__CGSCC____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 48 to i32*), [[FALSEBB]] ] -; IS__CGSCC____-NEXT: store i32 0, i32* [[PTR]], align 16 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test13-1 +; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; NOT_CGSCC_OPM: truebb: +; NOT_CGSCC_OPM-NEXT: br label [[END:%.*]] +; NOT_CGSCC_OPM: falsebb: +; NOT_CGSCC_OPM-NEXT: br label [[END]] +; NOT_CGSCC_OPM: end: +; NOT_CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 48 to i32*), [[FALSEBB]] ] +; NOT_CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 16 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test13-1 +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR9:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; IS__CGSCC_OPM: truebb: +; IS__CGSCC_OPM-NEXT: br label [[END:%.*]] +; IS__CGSCC_OPM: falsebb: +; IS__CGSCC_OPM-NEXT: br label [[END]] +; IS__CGSCC_OPM: end: +; IS__CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 48 to i32*), [[FALSEBB]] ] +; IS__CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 16 +; IS__CGSCC_OPM-NEXT: ret void ; br i1 %c, label %truebb, label %falsebb truebb: @@ -764,31 +814,31 @@ end: } define void @test13-2(i1 %c, i32* align 32 %dst) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test13-2 -; IS__TUNIT____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR7]] { -; IS__TUNIT____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__TUNIT____: truebb: -; IS__TUNIT____-NEXT: br label [[END:%.*]] -; IS__TUNIT____: falsebb: -; IS__TUNIT____-NEXT: br label [[END]] -; IS__TUNIT____: end: -; IS__TUNIT____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 160 to i32*), [[FALSEBB]] ] -; IS__TUNIT____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test13-2 -; IS__CGSCC____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8]] { -; IS__CGSCC____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__CGSCC____: truebb: -; IS__CGSCC____-NEXT: br label [[END:%.*]] -; IS__CGSCC____: falsebb: -; IS__CGSCC____-NEXT: br label [[END]] -; IS__CGSCC____: end: -; IS__CGSCC____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 160 to i32*), [[FALSEBB]] ] -; IS__CGSCC____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test13-2 +; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8]] { +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; NOT_CGSCC_OPM: truebb: +; NOT_CGSCC_OPM-NEXT: br label [[END:%.*]] +; NOT_CGSCC_OPM: falsebb: +; NOT_CGSCC_OPM-NEXT: br label [[END]] +; NOT_CGSCC_OPM: end: +; NOT_CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 160 to i32*), [[FALSEBB]] ] +; NOT_CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test13-2 +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR9]] { +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; IS__CGSCC_OPM: truebb: +; IS__CGSCC_OPM-NEXT: br label [[END:%.*]] +; IS__CGSCC_OPM: falsebb: +; IS__CGSCC_OPM-NEXT: br label [[END]] +; IS__CGSCC_OPM: end: +; IS__CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 160 to i32*), [[FALSEBB]] ] +; IS__CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; IS__CGSCC_OPM-NEXT: ret void ; br i1 %c, label %truebb, label %falsebb truebb: @@ -802,31 +852,31 @@ end: } define void @test13-3(i1 %c, i32* align 32 %dst) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@test13-3 -; IS__TUNIT____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR7]] { -; IS__TUNIT____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__TUNIT____: truebb: -; IS__TUNIT____-NEXT: br label [[END:%.*]] -; IS__TUNIT____: falsebb: -; IS__TUNIT____-NEXT: br label [[END]] -; IS__TUNIT____: end: -; IS__TUNIT____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 128 to i32*), [[FALSEBB]] ] -; IS__TUNIT____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@test13-3 -; IS__CGSCC____-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8]] { -; IS__CGSCC____-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] -; IS__CGSCC____: truebb: -; IS__CGSCC____-NEXT: br label [[END:%.*]] -; IS__CGSCC____: falsebb: -; IS__CGSCC____-NEXT: br label [[END]] -; IS__CGSCC____: end: -; IS__CGSCC____-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 128 to i32*), [[FALSEBB]] ] -; IS__CGSCC____-NEXT: store i32 0, i32* [[PTR]], align 32 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test13-3 +; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR8]] { +; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; NOT_CGSCC_OPM: truebb: +; NOT_CGSCC_OPM-NEXT: br label [[END:%.*]] +; NOT_CGSCC_OPM: falsebb: +; NOT_CGSCC_OPM-NEXT: br label [[END]] +; NOT_CGSCC_OPM: end: +; NOT_CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 128 to i32*), [[FALSEBB]] ] +; NOT_CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test13-3 +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i32* nocapture nofree writeonly align 32 [[DST:%.*]]) #[[ATTR9]] { +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[TRUEBB:%.*]], label [[FALSEBB:%.*]] +; IS__CGSCC_OPM: truebb: +; IS__CGSCC_OPM-NEXT: br label [[END:%.*]] +; IS__CGSCC_OPM: falsebb: +; IS__CGSCC_OPM-NEXT: br label [[END]] +; IS__CGSCC_OPM: end: +; IS__CGSCC_OPM-NEXT: [[PTR:%.*]] = phi i32* [ [[DST]], [[TRUEBB]] ], [ inttoptr (i64 128 to i32*), [[FALSEBB]] ] +; IS__CGSCC_OPM-NEXT: store i32 0, i32* [[PTR]], align 32 +; IS__CGSCC_OPM-NEXT: ret void ; br i1 %c, label %truebb, label %falsebb truebb: @@ -841,33 +891,33 @@ end: ; Don't crash on ptr2int/int2ptr uses. define i64 @ptr2int(i32* %p) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@ptr2int -; IS__TUNIT____-SAME: (i32* nofree readnone [[P:%.*]]) #[[ATTR8:[0-9]+]] { -; IS__TUNIT____-NEXT: [[P2I:%.*]] = ptrtoint i32* [[P]] to i64 -; IS__TUNIT____-NEXT: ret i64 [[P2I]] -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@ptr2int -; IS__CGSCC____-SAME: (i32* nofree readnone [[P:%.*]]) #[[ATTR9:[0-9]+]] { -; IS__CGSCC____-NEXT: [[P2I:%.*]] = ptrtoint i32* [[P]] to i64 -; IS__CGSCC____-NEXT: ret i64 [[P2I]] +; NOT_CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@ptr2int +; NOT_CGSCC_OPM-SAME: (i32* nofree readnone [[P:%.*]]) #[[ATTR9:[0-9]+]] { +; NOT_CGSCC_OPM-NEXT: [[P2I:%.*]] = ptrtoint i32* [[P]] to i64 +; NOT_CGSCC_OPM-NEXT: ret i64 [[P2I]] +; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@ptr2int +; IS__CGSCC_OPM-SAME: (i32* nofree readnone [[P:%.*]]) #[[ATTR10:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[P2I:%.*]] = ptrtoint i32* [[P]] to i64 +; IS__CGSCC_OPM-NEXT: ret i64 [[P2I]] ; %p2i = ptrtoint i32* %p to i64 ret i64 %p2i } define i64* @int2ptr(i64 %i) { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@int2ptr -; IS__TUNIT____-SAME: (i64 [[I:%.*]]) #[[ATTR8]] { -; IS__TUNIT____-NEXT: [[I2P:%.*]] = inttoptr i64 [[I]] to i64* -; IS__TUNIT____-NEXT: ret i64* [[I2P]] -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@int2ptr -; IS__CGSCC____-SAME: (i64 [[I:%.*]]) #[[ATTR9]] { -; IS__CGSCC____-NEXT: [[I2P:%.*]] = inttoptr i64 [[I]] to i64* -; IS__CGSCC____-NEXT: ret i64* [[I2P]] +; NOT_CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@int2ptr +; NOT_CGSCC_OPM-SAME: (i64 [[I:%.*]]) #[[ATTR9]] { +; NOT_CGSCC_OPM-NEXT: [[I2P:%.*]] = inttoptr i64 [[I]] to i64* +; NOT_CGSCC_OPM-NEXT: ret i64* [[I2P]] +; +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@int2ptr +; IS__CGSCC_OPM-SAME: (i64 [[I:%.*]]) #[[ATTR10]] { +; IS__CGSCC_OPM-NEXT: [[I2P:%.*]] = inttoptr i64 [[I]] to i64* +; IS__CGSCC_OPM-NEXT: ret i64* [[I2P]] ; %i2p = inttoptr i64 %i to i64* ret i64* %i2p @@ -875,17 +925,17 @@ define i64* @int2ptr(i64 %i) { ; Use the store alignment only for the pointer operand. define void @aligned_store(i8* %Value, i8** %Ptr) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@aligned_store -; IS__TUNIT____-SAME: (i8* nofree writeonly [[VALUE:%.*]], i8** nocapture nofree noundef nonnull writeonly align 32 dereferenceable(8) [[PTR:%.*]]) #[[ATTR4]] { -; IS__TUNIT____-NEXT: store i8* [[VALUE]], i8** [[PTR]], align 32 -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@aligned_store -; IS__CGSCC____-SAME: (i8* nofree writeonly [[VALUE:%.*]], i8** nocapture nofree noundef nonnull writeonly align 32 dereferenceable(8) [[PTR:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: store i8* [[VALUE]], i8** [[PTR]], align 32 -; IS__CGSCC____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@aligned_store +; NOT_CGSCC_OPM-SAME: (i8* nofree writeonly [[VALUE:%.*]], i8** nocapture nofree noundef nonnull writeonly align 32 dereferenceable(8) [[PTR:%.*]]) #[[ATTR5]] { +; NOT_CGSCC_OPM-NEXT: store i8* [[VALUE]], i8** [[PTR]], align 32 +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@aligned_store +; IS__CGSCC_OPM-SAME: (i8* nofree writeonly [[VALUE:%.*]], i8** nocapture nofree noundef nonnull writeonly align 32 dereferenceable(8) [[PTR:%.*]]) #[[ATTR6]] { +; IS__CGSCC_OPM-NEXT: store i8* [[VALUE]], i8** [[PTR]], align 32 +; IS__CGSCC_OPM-NEXT: ret void ; store i8* %Value, i8** %Ptr, align 32 ret void @@ -905,19 +955,19 @@ define void @align_call_op_not_store(i8* align 2048 %arg) { } define void @align_store_after_bc(i32* align 2048 %arg) { ; -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@align_store_after_bc -; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 2048 dereferenceable(1) [[ARG:%.*]]) #[[ATTR4]] { -; IS__TUNIT____-NEXT: [[BC:%.*]] = bitcast i32* [[ARG]] to i8* -; IS__TUNIT____-NEXT: store i8 0, i8* [[BC]], align 2048 -; IS__TUNIT____-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@align_store_after_bc +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree nonnull writeonly align 2048 dereferenceable(1) [[ARG:%.*]]) #[[ATTR5]] { +; NOT_CGSCC_OPM-NEXT: [[BC:%.*]] = bitcast i32* [[ARG]] to i8* +; NOT_CGSCC_OPM-NEXT: store i8 0, i8* [[BC]], align 2048 +; NOT_CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@align_store_after_bc -; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 2048 dereferenceable(1) [[ARG:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: [[BC:%.*]] = bitcast i32* [[ARG]] to i8* -; IS__CGSCC____-NEXT: store i8 0, i8* [[BC]], align 2048 -; IS__CGSCC____-NEXT: ret void +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@align_store_after_bc +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree nonnull writeonly align 2048 dereferenceable(1) [[ARG:%.*]]) #[[ATTR6]] { +; IS__CGSCC_OPM-NEXT: [[BC:%.*]] = bitcast i32* [[ARG]] to i8* +; IS__CGSCC_OPM-NEXT: store i8 0, i8* [[BC]], align 2048 +; IS__CGSCC_OPM-NEXT: ret void ; %bc = bitcast i32* %arg to i8* store i8 0, i8* %bc @@ -928,17 +978,17 @@ define void @align_store_after_bc(i32* align 2048 %arg) { ; we cannot also put on the caller. @cnd = external global i1 define i32 @musttail_callee_1(i32* %p) { -; IS__TUNIT____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__TUNIT____-LABEL: define {{[^@]+}}@musttail_callee_1 -; IS__TUNIT____-SAME: (i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P:%.*]]) #[[ATTR3]] { -; IS__TUNIT____-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 32 -; IS__TUNIT____-NEXT: ret i32 [[V]] -; -; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@musttail_callee_1 -; IS__CGSCC____-SAME: (i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P:%.*]]) #[[ATTR4]] { -; IS__CGSCC____-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 32 -; IS__CGSCC____-NEXT: ret i32 [[V]] +; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@musttail_callee_1 +; NOT_CGSCC_OPM-SAME: (i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_OPM-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 32 +; NOT_CGSCC_OPM-NEXT: ret i32 [[V]] +; +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@musttail_callee_1 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P:%.*]]) #[[ATTR5]] { +; IS__CGSCC_OPM-NEXT: [[V:%.*]] = load i32, i32* [[P]], align 32 +; IS__CGSCC_OPM-NEXT: ret i32 [[V]] ; %v = load i32, i32* %p, align 32 ret i32 %v @@ -946,25 +996,36 @@ define i32 @musttail_callee_1(i32* %p) { define i32 @musttail_caller_1(i32* %p) { ; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readonly willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@musttail_caller_1 -; IS__TUNIT____-SAME: (i32* nocapture nofree readonly [[P:%.*]]) #[[ATTR9:[0-9]+]] { +; IS__TUNIT____-SAME: (i32* nocapture nofree readonly [[P:%.*]]) #[[ATTR10:[0-9]+]] { ; IS__TUNIT____-NEXT: [[C:%.*]] = load i1, i1* @cnd, align 1 ; IS__TUNIT____-NEXT: br i1 [[C]], label [[MT:%.*]], label [[EXIT:%.*]] ; IS__TUNIT____: mt: -; IS__TUNIT____-NEXT: [[V:%.*]] = musttail call i32 @musttail_callee_1(i32* nocapture nofree readonly [[P]]) #[[ATTR10:[0-9]+]] +; IS__TUNIT____-NEXT: [[V:%.*]] = musttail call i32 @musttail_callee_1(i32* nocapture nofree readonly [[P]]) #[[ATTR11:[0-9]+]] ; IS__TUNIT____-NEXT: ret i32 [[V]] ; IS__TUNIT____: exit: ; IS__TUNIT____-NEXT: ret i32 0 ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC____-LABEL: define {{[^@]+}}@musttail_caller_1 -; IS__CGSCC____-SAME: (i32* nocapture nofree readonly [[P:%.*]]) #[[ATTR10:[0-9]+]] { -; IS__CGSCC____-NEXT: [[C:%.*]] = load i1, i1* @cnd, align 1 -; IS__CGSCC____-NEXT: br i1 [[C]], label [[MT:%.*]], label [[EXIT:%.*]] -; IS__CGSCC____: mt: -; IS__CGSCC____-NEXT: [[V:%.*]] = musttail call i32 @musttail_callee_1(i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P]]) #[[ATTR11:[0-9]+]] -; IS__CGSCC____-NEXT: ret i32 [[V]] -; IS__CGSCC____: exit: -; IS__CGSCC____-NEXT: ret i32 0 +; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@musttail_caller_1 +; IS__CGSCC_OPM-SAME: (i32* nocapture nofree readonly [[P:%.*]]) #[[ATTR11:[0-9]+]] { +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = load i1, i1* @cnd, align 1 +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[MT:%.*]], label [[EXIT:%.*]] +; IS__CGSCC_OPM: mt: +; IS__CGSCC_OPM-NEXT: [[V:%.*]] = musttail call i32 @musttail_callee_1(i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P]]) #[[ATTR12:[0-9]+]] +; IS__CGSCC_OPM-NEXT: ret i32 [[V]] +; IS__CGSCC_OPM: exit: +; IS__CGSCC_OPM-NEXT: ret i32 0 +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readonly willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@musttail_caller_1 +; IS__CGSCC_NPM-SAME: (i32* nocapture nofree readonly [[P:%.*]]) #[[ATTR10:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: [[C:%.*]] = load i1, i1* @cnd, align 1 +; IS__CGSCC_NPM-NEXT: br i1 [[C]], label [[MT:%.*]], label [[EXIT:%.*]] +; IS__CGSCC_NPM: mt: +; IS__CGSCC_NPM-NEXT: [[V:%.*]] = musttail call i32 @musttail_callee_1(i32* nocapture nofree noundef nonnull readonly dereferenceable(4) [[P]]) #[[ATTR11:[0-9]+]] +; IS__CGSCC_NPM-NEXT: ret i32 [[V]] +; IS__CGSCC_NPM: exit: +; IS__CGSCC_NPM-NEXT: ret i32 0 ; %c = load i1, i1* @cnd br i1 %c, label %mt, label %exit @@ -976,37 +1037,37 @@ exit: } define i32* @checkAndAdvance(i32* align(16) %p) { -; IS__TUNIT____: Function Attrs: nounwind -; IS__TUNIT____-LABEL: define {{[^@]+}}@checkAndAdvance -; IS__TUNIT____-SAME: (i32* noundef nonnull readonly align 16 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR1]] { -; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 16 -; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0 -; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] -; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4 -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call nonnull align 16 i32* @checkAndAdvance(i32* nonnull readonly align 16 "no-capture-maybe-returned" [[ADD_PTR]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: br label [[RETURN]] -; IS__TUNIT____: return: -; IS__TUNIT____-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[CALL]], [[IF_THEN]] ], [ [[P]], [[ENTRY:%.*]] ] -; IS__TUNIT____-NEXT: call void @user_i32_ptr(i32* noalias nocapture nonnull readnone align 16 [[RETVAL_0]]) #[[ATTR1]] -; IS__TUNIT____-NEXT: ret i32* [[RETVAL_0]] -; -; IS__CGSCC____: Function Attrs: nounwind -; IS__CGSCC____-LABEL: define {{[^@]+}}@checkAndAdvance -; IS__CGSCC____-SAME: (i32* noundef nonnull readonly align 16 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR2]] { -; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 16 -; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0 -; IS__CGSCC____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] -; IS__CGSCC____: if.then: -; IS__CGSCC____-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4 -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call nonnull align 16 i32* @checkAndAdvance(i32* nonnull readonly align 16 "no-capture-maybe-returned" [[ADD_PTR]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: br label [[RETURN]] -; IS__CGSCC____: return: -; IS__CGSCC____-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[CALL]], [[IF_THEN]] ], [ [[P]], [[ENTRY:%.*]] ] -; IS__CGSCC____-NEXT: call void @user_i32_ptr(i32* noalias nocapture nonnull readnone align 16 [[RETVAL_0]]) #[[ATTR2]] -; IS__CGSCC____-NEXT: ret i32* [[RETVAL_0]] +; NOT_CGSCC_OPM: Function Attrs: nounwind +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@checkAndAdvance +; NOT_CGSCC_OPM-SAME: (i32* noundef nonnull readonly align 16 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR2]] { +; NOT_CGSCC_OPM-NEXT: entry: +; NOT_CGSCC_OPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 16 +; NOT_CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] +; NOT_CGSCC_OPM: if.then: +; NOT_CGSCC_OPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4 +; NOT_CGSCC_OPM-NEXT: [[CALL:%.*]] = call nonnull align 16 i32* @checkAndAdvance(i32* nonnull readonly align 16 "no-capture-maybe-returned" [[ADD_PTR]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: br label [[RETURN]] +; NOT_CGSCC_OPM: return: +; NOT_CGSCC_OPM-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[CALL]], [[IF_THEN]] ], [ [[P]], [[ENTRY:%.*]] ] +; NOT_CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture nonnull readnone align 16 [[RETVAL_0]]) #[[ATTR2]] +; NOT_CGSCC_OPM-NEXT: ret i32* [[RETVAL_0]] +; +; IS__CGSCC_OPM: Function Attrs: nounwind +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@checkAndAdvance +; IS__CGSCC_OPM-SAME: (i32* noundef nonnull readonly align 16 dereferenceable(4) "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR3]] { +; IS__CGSCC_OPM-NEXT: entry: +; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 16 +; IS__CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] +; IS__CGSCC_OPM: if.then: +; IS__CGSCC_OPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4 +; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call nonnull align 16 i32* @checkAndAdvance(i32* nonnull readonly align 16 "no-capture-maybe-returned" [[ADD_PTR]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: br label [[RETURN]] +; IS__CGSCC_OPM: return: +; IS__CGSCC_OPM-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[CALL]], [[IF_THEN]] ], [ [[P]], [[ENTRY:%.*]] ] +; IS__CGSCC_OPM-NEXT: call void @user_i32_ptr(i32* noalias nocapture nonnull readnone align 16 [[RETVAL_0]]) #[[ATTR3]] +; IS__CGSCC_OPM-NEXT: ret i32* [[RETVAL_0]] ; entry: %0 = load i32, i32* %p, align 4 @@ -1043,27 +1104,42 @@ attributes #1 = { uwtable noinline } attributes #2 = { null_pointer_is_valid } ;. ; IS__TUNIT____: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; IS__TUNIT____: attributes #[[ATTR1]] = { nounwind } -; IS__TUNIT____: attributes #[[ATTR2]] = { nofree nosync nounwind } -; IS__TUNIT____: attributes #[[ATTR3]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } -; IS__TUNIT____: attributes #[[ATTR4]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } -; IS__TUNIT____: attributes #[[ATTR5]] = { nounwind willreturn } -; IS__TUNIT____: attributes #[[ATTR6]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__TUNIT____: attributes #[[ATTR7]] = { nofree norecurse nosync nounwind willreturn writeonly } -; IS__TUNIT____: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__TUNIT____: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readonly willreturn } -; IS__TUNIT____: attributes #[[ATTR10]] = { nofree nosync nounwind readonly willreturn } +; IS__TUNIT____: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__TUNIT____: attributes #[[ATTR2]] = { nounwind } +; IS__TUNIT____: attributes #[[ATTR3]] = { nofree nosync nounwind } +; IS__TUNIT____: attributes #[[ATTR4]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } +; IS__TUNIT____: attributes #[[ATTR5]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR6]] = { nounwind willreturn } +; IS__TUNIT____: attributes #[[ATTR7]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__TUNIT____: attributes #[[ATTR10]] = { nofree norecurse nosync nounwind readonly willreturn } +; IS__TUNIT____: attributes #[[ATTR11]] = { nofree nosync nounwind readonly willreturn } +;. +; IS__CGSCC_OPM: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR2]] = { noinline nounwind uwtable } +; IS__CGSCC_OPM: attributes #[[ATTR3]] = { nounwind } +; IS__CGSCC_OPM: attributes #[[ATTR4]] = { nofree nosync nounwind } +; IS__CGSCC_OPM: attributes #[[ATTR5]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR6]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } +; IS__CGSCC_OPM: attributes #[[ATTR7]] = { nounwind willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR8]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__CGSCC_OPM: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind willreturn writeonly } +; IS__CGSCC_OPM: attributes #[[ATTR10]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR11]] = { nofree norecurse nosync nounwind readonly willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR12]] = { readonly willreturn } ;. -; IS__CGSCC____: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; IS__CGSCC____: attributes #[[ATTR1]] = { noinline nounwind uwtable } -; IS__CGSCC____: attributes #[[ATTR2]] = { nounwind } -; IS__CGSCC____: attributes #[[ATTR3]] = { nofree nosync nounwind } -; IS__CGSCC____: attributes #[[ATTR4]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } -; IS__CGSCC____: attributes #[[ATTR5]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR6]] = { nounwind willreturn } -; IS__CGSCC____: attributes #[[ATTR7]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__CGSCC____: attributes #[[ATTR10]] = { nofree norecurse nosync nounwind readonly willreturn } -; IS__CGSCC____: attributes #[[ATTR11]] = { readonly willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR1]] = { noinline nounwind uwtable } +; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR3]] = { nofree nosync nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR4]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR5]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } +; IS__CGSCC_NPM: attributes #[[ATTR6]] = { nounwind willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR7]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__CGSCC_NPM: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind willreturn writeonly } +; IS__CGSCC_NPM: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR10]] = { nofree norecurse nosync nounwind readonly willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR11]] = { readonly willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/internal-noalias.ll b/llvm/test/Transforms/Attributor/internal-noalias.ll index 1d72284e5283c..10a1915db1c6c 100644 --- a/llvm/test/Transforms/Attributor/internal-noalias.ll +++ b/llvm/test/Transforms/Attributor/internal-noalias.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/liveness.ll b/llvm/test/Transforms/Attributor/liveness.ll index 75788cb83e208..6b35c3d38c851 100644 --- a/llvm/test/Transforms/Attributor/liveness.ll +++ b/llvm/test/Transforms/Attributor/liveness.ll @@ -591,15 +591,15 @@ cond.end: ; preds = %cond.if, %con } define void @rec() #0 { -; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@rec ; NOT_CGSCC_NPM-SAME: () #[[ATTR9:[0-9]+]] { ; NOT_CGSCC_NPM-NEXT: entry: ; NOT_CGSCC_NPM-NEXT: ret void ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@rec -; IS__CGSCC____-SAME: () #[[ATTR6]] { +; IS__CGSCC____-SAME: () #[[ATTR11:[0-9]+]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: ret void ; @@ -1032,7 +1032,7 @@ define internal void @non_dead_a0() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a0 -; IS__CGSCC____-SAME: () #[[ATTR11:[0-9]+]] { +; IS__CGSCC____-SAME: () #[[ATTR12:[0-9]+]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1048,7 +1048,7 @@ define internal void @non_dead_a1() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a1 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1064,7 +1064,7 @@ define internal void @non_dead_a2() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a2 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1080,7 +1080,7 @@ define internal void @non_dead_a3() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a3 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1096,7 +1096,7 @@ define internal void @non_dead_a4() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a4 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1112,7 +1112,7 @@ define internal void @non_dead_a5() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a5 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1128,7 +1128,7 @@ define internal void @non_dead_a6() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a6 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1144,7 +1144,7 @@ define internal void @non_dead_a7() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a7 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1160,7 +1160,7 @@ define internal void @non_dead_a8() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a8 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1176,7 +1176,7 @@ define internal void @non_dead_a9() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a9 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1192,7 +1192,7 @@ define internal void @non_dead_a10() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a10 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1208,7 +1208,7 @@ define internal void @non_dead_a11() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a11 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1224,7 +1224,7 @@ define internal void @non_dead_a12() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a12 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1240,7 +1240,7 @@ define internal void @non_dead_a13() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a13 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1256,7 +1256,7 @@ define internal void @non_dead_a14() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a14 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1272,7 +1272,7 @@ define internal void @non_dead_a15() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_a15 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1288,7 +1288,7 @@ define internal void @non_dead_b0() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b0 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1304,7 +1304,7 @@ define internal void @non_dead_b1() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b1 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1320,7 +1320,7 @@ define internal void @non_dead_b2() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b2 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1336,7 +1336,7 @@ define internal void @non_dead_b3() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b3 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1352,7 +1352,7 @@ define internal void @non_dead_b4() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b4 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1368,7 +1368,7 @@ define internal void @non_dead_b5() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b5 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1384,7 +1384,7 @@ define internal void @non_dead_b6() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b6 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1400,7 +1400,7 @@ define internal void @non_dead_b7() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b7 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1416,7 +1416,7 @@ define internal void @non_dead_b8() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b8 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1432,7 +1432,7 @@ define internal void @non_dead_b9() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b9 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1448,7 +1448,7 @@ define internal void @non_dead_b10() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b10 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1464,7 +1464,7 @@ define internal void @non_dead_b11() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b11 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1480,7 +1480,7 @@ define internal void @non_dead_b12() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b12 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1496,7 +1496,7 @@ define internal void @non_dead_b13() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b13 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1512,7 +1512,7 @@ define internal void @non_dead_b14() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b14 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1528,7 +1528,7 @@ define internal void @non_dead_b15() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_b15 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1544,7 +1544,7 @@ define internal void @non_dead_c0() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c0 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1560,7 +1560,7 @@ define internal void @non_dead_c1() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c1 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1576,7 +1576,7 @@ define internal void @non_dead_c2() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c2 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1592,7 +1592,7 @@ define internal void @non_dead_c3() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c3 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1608,7 +1608,7 @@ define internal void @non_dead_c4() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c4 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1624,7 +1624,7 @@ define internal void @non_dead_c5() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c5 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1640,7 +1640,7 @@ define internal void @non_dead_c6() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c6 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1656,7 +1656,7 @@ define internal void @non_dead_c7() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c7 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1672,7 +1672,7 @@ define internal void @non_dead_c8() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c8 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1688,7 +1688,7 @@ define internal void @non_dead_c9() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c9 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1704,7 +1704,7 @@ define internal void @non_dead_c10() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c10 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1720,7 +1720,7 @@ define internal void @non_dead_c11() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c11 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1736,7 +1736,7 @@ define internal void @non_dead_c12() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c12 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1752,7 +1752,7 @@ define internal void @non_dead_c13() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c13 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1768,7 +1768,7 @@ define internal void @non_dead_c14() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c14 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1784,7 +1784,7 @@ define internal void @non_dead_c15() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_c15 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1800,7 +1800,7 @@ define internal void @non_dead_d0() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d0 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1816,7 +1816,7 @@ define internal void @non_dead_d1() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d1 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1832,7 +1832,7 @@ define internal void @non_dead_d2() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d2 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1848,7 +1848,7 @@ define internal void @non_dead_d3() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d3 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1864,7 +1864,7 @@ define internal void @non_dead_d4() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d4 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1880,7 +1880,7 @@ define internal void @non_dead_d5() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d5 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1896,7 +1896,7 @@ define internal void @non_dead_d6() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d6 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1912,7 +1912,7 @@ define internal void @non_dead_d7() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d7 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1928,7 +1928,7 @@ define internal void @non_dead_d8() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d8 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1944,7 +1944,7 @@ define internal void @non_dead_d9() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d9 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1960,7 +1960,7 @@ define internal void @non_dead_d10() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d10 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1976,7 +1976,7 @@ define internal void @non_dead_d11() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d11 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -1992,7 +1992,7 @@ define internal void @non_dead_d12() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d12 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2008,7 +2008,7 @@ define internal void @non_dead_d13() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d13 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2024,7 +2024,7 @@ define internal void @non_dead_d14() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d14 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2040,7 +2040,7 @@ define internal void @non_dead_d15() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@non_dead_d15 -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2112,7 +2112,7 @@ define internal void @useless_arg_sink(i32* %a) { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@useless_arg_sink -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2129,7 +2129,7 @@ define internal void @useless_arg_almost_sink(i32* %a) { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@useless_arg_almost_sink -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: call void @useless_arg_sink() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret void ; @@ -2187,7 +2187,7 @@ define internal i32 @switch_default(i64 %i) nounwind { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@switch_default -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: switch i64 0, label [[SW_DEFAULT:%.*]] [ ; IS__CGSCC____-NEXT: i64 3, label [[RETURN:%.*]] @@ -2222,7 +2222,7 @@ define i32 @switch_default_caller() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@switch_default_caller -; IS__CGSCC____-SAME: () #[[ATTR11]] { +; IS__CGSCC____-SAME: () #[[ATTR12]] { ; IS__CGSCC____-NEXT: [[CALL2:%.*]] = tail call i32 @switch_default() #[[ATTR15]] ; IS__CGSCC____-NEXT: ret i32 123 ; @@ -2260,7 +2260,7 @@ return: define i32 @switch_default_dead_caller() { ; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@switch_default_dead_caller -; NOT_CGSCC_NPM-SAME: () #[[ATTR9]] { +; NOT_CGSCC_NPM-SAME: () #[[ATTR11:[0-9]+]] { ; NOT_CGSCC_NPM-NEXT: ret i32 123 ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn @@ -2408,7 +2408,7 @@ define internal void @dead_with_blockaddress_users(i32* nocapture %pc) nounwind ; ; IS__CGSCC____: Function Attrs: nounwind readonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@dead_with_blockaddress_users -; IS__CGSCC____-SAME: (i32* nocapture [[PC:%.*]]) #[[ATTR12:[0-9]+]] { +; IS__CGSCC____-SAME: (i32* nocapture [[PC:%.*]]) #[[ATTR13:[0-9]+]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: br label [[INDIRECTGOTO:%.*]] ; IS__CGSCC____: lab0: @@ -2544,7 +2544,7 @@ declare noalias i8* @malloc(i64) define i32 @h(i32 %i) { ; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@h -; NOT_CGSCC_NPM-SAME: (i32 [[I:%.*]]) #[[ATTR9]] { +; NOT_CGSCC_NPM-SAME: (i32 [[I:%.*]]) #[[ATTR11]] { ; NOT_CGSCC_NPM-NEXT: ret i32 0 ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn @@ -2563,7 +2563,7 @@ define i32 @h(i32 %i) { define void @bad_gep() { ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@bad_gep -; NOT_CGSCC_NPM-SAME: () #[[ATTR11:[0-9]+]] { +; NOT_CGSCC_NPM-SAME: () #[[ATTR9]] { ; NOT_CGSCC_NPM-NEXT: entry: ; NOT_CGSCC_NPM-NEXT: [[N:%.*]] = alloca i8, align 1 ; NOT_CGSCC_NPM-NEXT: [[M:%.*]] = alloca i8, align 1 @@ -2581,7 +2581,7 @@ define void @bad_gep() { ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@bad_gep -; IS__CGSCC____-SAME: () #[[ATTR13:[0-9]+]] { +; IS__CGSCC____-SAME: () #[[ATTR11]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: [[N:%.*]] = alloca i8, align 1 ; IS__CGSCC____-NEXT: [[M:%.*]] = alloca i8, align 1 @@ -2625,7 +2625,7 @@ exit: define i8 @edge_vs_block_liveness() { ; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@edge_vs_block_liveness -; NOT_CGSCC_NPM-SAME: () #[[ATTR9]] { +; NOT_CGSCC_NPM-SAME: () #[[ATTR11]] { ; NOT_CGSCC_NPM-NEXT: entry: ; NOT_CGSCC_NPM-NEXT: br i1 true, label [[B1:%.*]], label [[B2:%.*]] ; NOT_CGSCC_NPM: b1: @@ -2669,9 +2669,9 @@ declare void @llvm.lifetime.end.p0i8(i64 %0, i8* %1) ; NOT_CGSCC_NPM: attributes #[[ATTR6]] = { argmemonly nofree norecurse nounwind uwtable willreturn } ; NOT_CGSCC_NPM: attributes #[[ATTR7:[0-9]+]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } ; NOT_CGSCC_NPM: attributes #[[ATTR8]] = { nofree norecurse noreturn nosync nounwind readnone } -; NOT_CGSCC_NPM: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR9]] = { nofree nosync nounwind readnone willreturn } ; NOT_CGSCC_NPM: attributes #[[ATTR10]] = { nofree nosync nounwind willreturn } -; NOT_CGSCC_NPM: attributes #[[ATTR11]] = { nofree nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR11]] = { nofree norecurse nosync nounwind readnone willreturn } ; NOT_CGSCC_NPM: attributes #[[ATTR12:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } ; NOT_CGSCC_NPM: attributes #[[ATTR13]] = { nounwind willreturn } ; NOT_CGSCC_NPM: attributes #[[ATTR14]] = { willreturn } @@ -2687,9 +2687,9 @@ declare void @llvm.lifetime.end.p0i8(i64 %0, i8* %1) ; IS__CGSCC____: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind readnone uwtable willreturn } ; IS__CGSCC____: attributes #[[ATTR9]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } ; IS__CGSCC____: attributes #[[ATTR10]] = { nofree norecurse noreturn nosync nounwind readnone } -; IS__CGSCC____: attributes #[[ATTR11]] = { nofree nosync nounwind willreturn } -; IS__CGSCC____: attributes #[[ATTR12]] = { nounwind readonly } -; IS__CGSCC____: attributes #[[ATTR13]] = { nofree nosync nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR11]] = { nofree nosync nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR12]] = { nofree nosync nounwind willreturn } +; IS__CGSCC____: attributes #[[ATTR13]] = { nounwind readonly } ; IS__CGSCC____: attributes #[[ATTR14:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } ; IS__CGSCC____: attributes #[[ATTR15]] = { nounwind willreturn } ; IS__CGSCC____: attributes #[[ATTR16]] = { willreturn } diff --git a/llvm/test/Transforms/Attributor/liveness_chains.ll b/llvm/test/Transforms/Attributor/liveness_chains.ll index 36511049969dd..c8219ea0c5b39 100644 --- a/llvm/test/Transforms/Attributor/liveness_chains.ll +++ b/llvm/test/Transforms/Attributor/liveness_chains.ll @@ -9,7 +9,7 @@ declare i32 @source() nounwind readonly define i32 @chain_dead(i32 %arg) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@chain_dead ; CHECK-SAME: (i32 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: ret i32 0 @@ -60,5 +60,5 @@ define i32 @chain_alive(i32 %arg) { } ;. ; CHECK: attributes #[[ATTR0]] = { nounwind readonly } -; CHECK: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; CHECK: attributes #[[ATTR1]] = { nofree nosync nounwind readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/memory_locations.ll b/llvm/test/Transforms/Attributor/memory_locations.ll index 68e7728a7d302..59c1597938faf 100644 --- a/llvm/test/Transforms/Attributor/memory_locations.ll +++ b/llvm/test/Transforms/Attributor/memory_locations.ll @@ -442,7 +442,7 @@ define void @callerD2() { } define void @callerE(i8* %arg) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@callerE ; CHECK-SAME: (i8* nocapture nofree readnone [[ARG:%.*]]) #[[ATTR5:[0-9]+]] { ; CHECK-NEXT: ret void @@ -484,33 +484,21 @@ define internal void @write_global_via_arg_internal(i32* %GPtr) { } define void @writeonly_global() { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@writeonly_global -; IS__TUNIT____-SAME: () #[[ATTR6]] { -; IS__TUNIT____-NEXT: call void @write_global() #[[ATTR10:[0-9]+]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@writeonly_global -; IS__CGSCC____-SAME: () #[[ATTR6]] { -; IS__CGSCC____-NEXT: call void @write_global() #[[ATTR9:[0-9]+]] -; IS__CGSCC____-NEXT: ret void +; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; CHECK-LABEL: define {{[^@]+}}@writeonly_global +; CHECK-SAME: () #[[ATTR6]] { +; CHECK-NEXT: call void @write_global() #[[ATTR10:[0-9]+]] +; CHECK-NEXT: ret void ; call void @write_global() ret void } define void @writeonly_global_via_arg() { -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@writeonly_global_via_arg -; IS__TUNIT____-SAME: () #[[ATTR6]] { -; IS__TUNIT____-NEXT: call void @write_global_via_arg(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) @G) #[[ATTR10]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@writeonly_global_via_arg -; IS__CGSCC____-SAME: () #[[ATTR6]] { -; IS__CGSCC____-NEXT: call void @write_global_via_arg(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) @G) #[[ATTR9]] -; IS__CGSCC____-NEXT: ret void +; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; CHECK-LABEL: define {{[^@]+}}@writeonly_global_via_arg +; CHECK-SAME: () #[[ATTR6]] { +; CHECK-NEXT: call void @write_global_via_arg(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) @G) #[[ATTR10]] +; CHECK-NEXT: ret void ; call void @write_global_via_arg(i32* @G) ret void @@ -518,46 +506,28 @@ define void @writeonly_global_via_arg() { define void @writeonly_global_via_arg_internal() { ; -; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@writeonly_global_via_arg_internal -; IS__TUNIT____-SAME: () #[[ATTR6]] { -; IS__TUNIT____-NEXT: call void @write_global_via_arg_internal() #[[ATTR10]] -; IS__TUNIT____-NEXT: ret void -; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@writeonly_global_via_arg_internal -; IS__CGSCC____-SAME: () #[[ATTR6]] { -; IS__CGSCC____-NEXT: call void @write_global_via_arg_internal() #[[ATTR9]] -; IS__CGSCC____-NEXT: ret void +; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; CHECK-LABEL: define {{[^@]+}}@writeonly_global_via_arg_internal +; CHECK-SAME: () #[[ATTR6]] { +; CHECK-NEXT: call void @write_global_via_arg_internal() #[[ATTR10]] +; CHECK-NEXT: ret void ; call void @write_global_via_arg_internal(i32* @G) ret void } define i8 @recursive_not_readnone(i8* %ptr, i1 %c) { -; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind writeonly -; IS__TUNIT____-LABEL: define {{[^@]+}}@recursive_not_readnone -; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR8:[0-9]+]] { -; IS__TUNIT____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 -; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11:[0-9]+]] -; IS__TUNIT____-NEXT: ret i8 1 -; IS__TUNIT____: f: -; IS__TUNIT____-NEXT: store i8 1, i8* [[PTR]], align 1 -; IS__TUNIT____-NEXT: ret i8 0 -; -; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@recursive_not_readnone -; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR8:[0-9]+]] { -; IS__CGSCC____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 -; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR10:[0-9]+]] -; IS__CGSCC____-NEXT: ret i8 1 -; IS__CGSCC____: f: -; IS__CGSCC____-NEXT: store i8 1, i8* [[PTR]], align 1 -; IS__CGSCC____-NEXT: ret i8 0 +; CHECK: Function Attrs: argmemonly nofree nosync nounwind writeonly +; CHECK-LABEL: define {{[^@]+}}@recursive_not_readnone +; CHECK-SAME: (i8* nocapture nofree writeonly [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR8:[0-9]+]] { +; CHECK-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 +; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; CHECK: t: +; CHECK-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11:[0-9]+]] +; CHECK-NEXT: ret i8 1 +; CHECK: f: +; CHECK-NEXT: store i8 1, i8* [[PTR]], align 1 +; CHECK-NEXT: ret i8 0 ; %alloc = alloca i8 br i1 %c, label %t, label %f @@ -577,18 +547,18 @@ define internal i8 @recursive_not_readnone_internal(i8* %ptr, i1 %c) { ; IS__TUNIT____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]], !range [[RNG0:![0-9]+]] +; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]] ; IS__TUNIT____-NEXT: ret i8 1 ; IS__TUNIT____: f: ; IS__TUNIT____-NEXT: ret i8 0 ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@recursive_not_readnone_internal ; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR5]] { ; IS__CGSCC____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR11:[0-9]+]], !range [[RNG0:![0-9]+]] +; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR12:[0-9]+]], !range [[RNG0:![0-9]+]] ; IS__CGSCC____-NEXT: ret i8 1 ; IS__CGSCC____: f: ; IS__CGSCC____-NEXT: ret i8 0 @@ -609,13 +579,13 @@ define i8 @readnone_caller(i1 %c) { ; IS__TUNIT____-LABEL: define {{[^@]+}}@readnone_caller ; IS__TUNIT____-SAME: (i1 [[C:%.*]]) #[[ATTR9:[0-9]+]] { ; IS__TUNIT____-NEXT: [[A:%.*]] = alloca i8, align 1 -; IS__TUNIT____-NEXT: [[R:%.*]] = call i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[A]], i1 [[C]]) #[[ATTR11]], !range [[RNG0]] +; IS__TUNIT____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[A]], i1 [[C]]) #[[ATTR11]], !range [[RNG0:![0-9]+]] ; IS__TUNIT____-NEXT: ret i8 [[R]] ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@readnone_caller -; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 [[C]]) #[[ATTR12:[0-9]+]], !range [[RNG0]] +; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR9:[0-9]+]] { +; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 [[C]]) #[[ATTR13:[0-9]+]], !range [[RNG0]] ; IS__CGSCC____-NEXT: ret i8 [[R]] ; %a = alloca i8 @@ -630,18 +600,18 @@ define internal i8 @recursive_readnone_internal2(i8* %ptr, i1 %c) { ; IS__TUNIT____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_readnone_internal2(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]], !range [[RNG0]] +; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_readnone_internal2(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]] ; IS__TUNIT____-NEXT: ret i8 1 ; IS__TUNIT____: f: ; IS__TUNIT____-NEXT: ret i8 0 ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@recursive_readnone_internal2 ; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull readnone [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR5]] { ; IS__CGSCC____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_readnone_internal2(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR11]], !range [[RNG0]] +; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_readnone_internal2(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR12]], !range [[RNG0]] ; IS__CGSCC____-NEXT: ret i8 1 ; IS__CGSCC____: f: ; IS__CGSCC____-NEXT: ret i8 0 @@ -661,13 +631,13 @@ define i8 @readnone_caller2(i1 %c) { ; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@readnone_caller2 ; IS__TUNIT____-SAME: (i1 [[C:%.*]]) #[[ATTR9]] { -; IS__TUNIT____-NEXT: [[R:%.*]] = call i8 @recursive_readnone_internal2(i8* undef, i1 [[C]]) #[[ATTR11]], !range [[RNG0]] +; IS__TUNIT____-NEXT: [[R:%.*]] = call noundef i8 @recursive_readnone_internal2(i8* undef, i1 [[C]]) #[[ATTR11]], !range [[RNG0]] ; IS__TUNIT____-NEXT: ret i8 [[R]] ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@readnone_caller2 -; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_readnone_internal2(i8* undef, i1 [[C]]) #[[ATTR12]], !range [[RNG0]] +; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR9]] { +; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_readnone_internal2(i8* undef, i1 [[C]]) #[[ATTR13]], !range [[RNG0]] ; IS__CGSCC____-NEXT: ret i8 [[R]] ; %r = call i8 @recursive_readnone_internal2(i8* undef, i1 %c) @@ -681,18 +651,18 @@ define internal i8 @recursive_not_readnone_internal3(i8* %ptr, i1 %c) { ; IS__TUNIT____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__TUNIT____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__TUNIT____: t: -; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]], !range [[RNG0]] +; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 noundef false) #[[ATTR11]] ; IS__TUNIT____-NEXT: ret i8 1 ; IS__TUNIT____: f: ; IS__TUNIT____-NEXT: ret i8 0 ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@recursive_not_readnone_internal3 ; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]], i1 [[C:%.*]]) #[[ATTR5]] { ; IS__CGSCC____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 ; IS__CGSCC____-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__CGSCC____: t: -; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR11]], !range [[RNG0]] +; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 noundef false) #[[ATTR12]], !range [[RNG0]] ; IS__CGSCC____-NEXT: ret i8 1 ; IS__CGSCC____: f: ; IS__CGSCC____-NEXT: ret i8 0 @@ -713,13 +683,13 @@ define i8 @readnone_caller3(i1 %c) { ; IS__TUNIT____-LABEL: define {{[^@]+}}@readnone_caller3 ; IS__TUNIT____-SAME: (i1 [[C:%.*]]) #[[ATTR9]] { ; IS__TUNIT____-NEXT: [[ALLOC:%.*]] = alloca i8, align 1 -; IS__TUNIT____-NEXT: [[R:%.*]] = call i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 [[C]]) #[[ATTR11]], !range [[RNG0]] +; IS__TUNIT____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[ALLOC]], i1 [[C]]) #[[ATTR11]], !range [[RNG0]] ; IS__TUNIT____-NEXT: ret i8 [[R]] ; -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@readnone_caller3 -; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR5]] { -; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 [[C]]) #[[ATTR12]], !range [[RNG0]] +; IS__CGSCC____-SAME: (i1 [[C:%.*]]) #[[ATTR9]] { +; IS__CGSCC____-NEXT: [[R:%.*]] = call noundef i8 @recursive_not_readnone_internal3(i8* noalias nocapture nofree nonnull readnone dereferenceable(1) undef, i1 [[C]]) #[[ATTR13]], !range [[RNG0]] ; IS__CGSCC____-NEXT: ret i8 [[R]] ; %alloc = alloca i8 @@ -728,20 +698,21 @@ define i8 @readnone_caller3(i1 %c) { } define internal void @argmemonly_before_ipconstprop(i32* %p) argmemonly { -; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; IS__CGSCC____-LABEL: define {{[^@]+}}@argmemonly_before_ipconstprop -; IS__CGSCC____-SAME: () #[[ATTR6]] { -; IS__CGSCC____-NEXT: store i32 0, i32* @G, align 4 -; IS__CGSCC____-NEXT: ret void +; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; CHECK-LABEL: define {{[^@]+}}@argmemonly_before_ipconstprop +; CHECK-SAME: () #[[ATTR6]] { +; CHECK-NEXT: store i32 0, i32* @G, align 4 +; CHECK-NEXT: ret void ; store i32 0, i32* %p ret void } define void @argmemonky_caller() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly ; CHECK-LABEL: define {{[^@]+}}@argmemonky_caller -; CHECK-SAME: () #[[ATTR5]] { +; CHECK-SAME: () #[[ATTR6]] { +; CHECK-NEXT: call void @argmemonly_before_ipconstprop() #[[ATTR10]] ; CHECK-NEXT: ret void ; call void @argmemonly_before_ipconstprop(i32* @G) @@ -753,7 +724,7 @@ define void @argmemonky_caller() { ; IS__TUNIT____: attributes #[[ATTR2]] = { readnone } ; IS__TUNIT____: attributes #[[ATTR3]] = { argmemonly } ; IS__TUNIT____: attributes #[[ATTR4:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } -; IS__TUNIT____: attributes #[[ATTR5]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__TUNIT____: attributes #[[ATTR5]] = { nofree nosync nounwind readnone willreturn } ; IS__TUNIT____: attributes #[[ATTR6]] = { nofree norecurse nosync nounwind willreturn writeonly } ; IS__TUNIT____: attributes #[[ATTR7]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } ; IS__TUNIT____: attributes #[[ATTR8]] = { argmemonly nofree nosync nounwind writeonly } @@ -766,14 +737,15 @@ define void @argmemonky_caller() { ; IS__CGSCC____: attributes #[[ATTR2]] = { readnone } ; IS__CGSCC____: attributes #[[ATTR3]] = { argmemonly } ; IS__CGSCC____: attributes #[[ATTR4:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } -; IS__CGSCC____: attributes #[[ATTR5]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR5]] = { nofree nosync nounwind readnone willreturn } ; IS__CGSCC____: attributes #[[ATTR6]] = { nofree norecurse nosync nounwind willreturn writeonly } ; IS__CGSCC____: attributes #[[ATTR7]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } ; IS__CGSCC____: attributes #[[ATTR8]] = { argmemonly nofree nosync nounwind writeonly } -; IS__CGSCC____: attributes #[[ATTR9]] = { nounwind willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR10]] = { nofree nosync nounwind writeonly } -; IS__CGSCC____: attributes #[[ATTR11]] = { nofree nosync nounwind readnone } -; IS__CGSCC____: attributes #[[ATTR12]] = { norecurse nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR9]] = { nofree norecurse nosync nounwind readnone } +; IS__CGSCC____: attributes #[[ATTR10]] = { nounwind willreturn writeonly } +; IS__CGSCC____: attributes #[[ATTR11]] = { nofree nosync nounwind writeonly } +; IS__CGSCC____: attributes #[[ATTR12]] = { nofree nosync nounwind readnone } +; IS__CGSCC____: attributes #[[ATTR13]] = { nounwind readnone willreturn } ;. ; CHECK: [[META0:![0-9]+]] = !{i8 0, i8 2} ;. diff --git a/llvm/test/Transforms/Attributor/noalias.ll b/llvm/test/Transforms/Attributor/noalias.ll index 1925a5e13388b..773e42d7e86c0 100644 --- a/llvm/test/Transforms/Attributor/noalias.ll +++ b/llvm/test/Transforms/Attributor/noalias.ll @@ -525,10 +525,10 @@ define i32 @i2p(i32* %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readonly willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@i2p ; IS__CGSCC____-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR4:[0-9]+]] { -; IS__CGSCC____-NEXT: [[C:%.*]] = call i32 @p2i(i32* noalias nofree readnone [[ARG]]) #[[ATTR9:[0-9]+]] +; IS__CGSCC____-NEXT: [[C:%.*]] = call i32 @p2i(i32* noalias nofree readnone [[ARG]]) #[[ATTR10:[0-9]+]] ; IS__CGSCC____-NEXT: [[I2P:%.*]] = inttoptr i32 [[C]] to i8* ; IS__CGSCC____-NEXT: [[BC:%.*]] = bitcast i8* [[I2P]] to i32* -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32 @ret(i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[BC]]) #[[ATTR10:[0-9]+]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32 @ret(i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[BC]]) #[[ATTR11:[0-9]+]] ; IS__CGSCC____-NEXT: ret i32 [[CALL]] ; %c = call i32 @p2i(i32* %arg) @@ -558,17 +558,29 @@ define internal i32 @ret(i32* %arg) { ; Function Attrs: nounwind optsize define internal fastcc double @strtox(i8* %s, i8** %p, i32 %prec) unnamed_addr { -; CHECK-LABEL: define {{[^@]+}}@strtox -; CHECK-SAME: (i8* [[S:%.*]]) unnamed_addr { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[F:%.*]] = alloca [[STRUCT__IO_FILE:%.*]], align 8 -; CHECK-NEXT: [[TMP0:%.*]] = bitcast %struct._IO_FILE* [[F]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) #[[ATTR11:[0-9]+]] -; CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull align 8 dereferenceable(240) [[F]], i8* [[S]]) -; CHECK-NEXT: call void @__shlim(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i64 noundef 0) -; CHECK-NEXT: [[CALL1:%.*]] = call double @__floatscan(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i32 noundef 1, i32 noundef 1) -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) -; CHECK-NEXT: ret double [[CALL1]] +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@strtox +; NOT_CGSCC_NPM-SAME: (i8* [[S:%.*]]) unnamed_addr { +; NOT_CGSCC_NPM-NEXT: entry: +; NOT_CGSCC_NPM-NEXT: [[F:%.*]] = alloca [[STRUCT__IO_FILE:%.*]], align 8 +; NOT_CGSCC_NPM-NEXT: [[TMP0:%.*]] = bitcast %struct._IO_FILE* [[F]] to i8* +; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) #[[ATTR11:[0-9]+]] +; NOT_CGSCC_NPM-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull align 8 dereferenceable(240) [[F]], i8* [[S]]) +; NOT_CGSCC_NPM-NEXT: call void @__shlim(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i64 noundef 0) +; NOT_CGSCC_NPM-NEXT: [[CALL1:%.*]] = call double @__floatscan(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i32 noundef 1, i32 noundef 1) +; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) +; NOT_CGSCC_NPM-NEXT: ret double [[CALL1]] +; +; IS__CGSCC____-LABEL: define {{[^@]+}}@strtox +; IS__CGSCC____-SAME: (i8* [[S:%.*]]) unnamed_addr { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[F:%.*]] = alloca [[STRUCT__IO_FILE:%.*]], align 8 +; IS__CGSCC____-NEXT: [[TMP0:%.*]] = bitcast %struct._IO_FILE* [[F]] to i8* +; IS__CGSCC____-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) #[[ATTR12:[0-9]+]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull align 8 dereferenceable(240) [[F]], i8* [[S]]) +; IS__CGSCC____-NEXT: call void @__shlim(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i64 noundef 0) +; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call double @__floatscan(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i32 noundef 1, i32 noundef 1) +; IS__CGSCC____-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) +; IS__CGSCC____-NEXT: ret double [[CALL1]] ; entry: %f = alloca %struct._IO_FILE, align 8 @@ -656,10 +668,10 @@ define void @test15_caller(i32* noalias %p, i32 %c) { ; IS__CGSCC____-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C]], 0 ; IS__CGSCC____-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; IS__CGSCC____: if.then: -; IS__CGSCC____-NEXT: tail call void @only_store(i32* noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12:[0-9]+]] +; IS__CGSCC____-NEXT: tail call void @only_store(i32* noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13:[0-9]+]] ; IS__CGSCC____-NEXT: br label [[IF_END]] ; IS__CGSCC____: if.end: -; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree writeonly [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree writeonly [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: ret void ; %tobool = icmp eq i32 %c, 0 @@ -719,14 +731,14 @@ define internal void @test16_sub(i32* noalias %p, i32 %c1, i32 %c2) { ; IS__CGSCC____-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C1]], 0 ; IS__CGSCC____-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; IS__CGSCC____: if.then: -; IS__CGSCC____-NEXT: tail call void @only_store(i32* noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] -; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @only_store(i32* noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] +; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: br label [[IF_END]] ; IS__CGSCC____: if.end: ; IS__CGSCC____-NEXT: [[TOBOOL1:%.*]] = icmp eq i32 [[C2]], 0 ; IS__CGSCC____-NEXT: br i1 [[TOBOOL1]], label [[IF_THEN2:%.*]], label [[IF_END3:%.*]] ; IS__CGSCC____: if.then2: -; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: br label [[IF_END3]] ; IS__CGSCC____: if.end3: ; IS__CGSCC____-NEXT: ret void @@ -752,11 +764,17 @@ if.end3: } define void @test16_caller(i32* %p, i32 %c) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly -; CHECK-LABEL: define {{[^@]+}}@test16_caller -; CHECK-SAME: (i32* nofree writeonly [[P:%.*]], i32 [[C:%.*]]) #[[ATTR7]] { -; CHECK-NEXT: tail call void @test16_sub(i32* noalias nofree writeonly [[P]], i32 [[C]], i32 [[C]]) #[[ATTR12:[0-9]+]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test16_caller +; NOT_CGSCC_NPM-SAME: (i32* nofree writeonly [[P:%.*]], i32 [[C:%.*]]) #[[ATTR7]] { +; NOT_CGSCC_NPM-NEXT: tail call void @test16_sub(i32* noalias nofree writeonly [[P]], i32 [[C]], i32 [[C]]) #[[ATTR12]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn writeonly +; IS__CGSCC____-LABEL: define {{[^@]+}}@test16_caller +; IS__CGSCC____-SAME: (i32* nofree writeonly [[P:%.*]], i32 [[C:%.*]]) #[[ATTR7]] { +; IS__CGSCC____-NEXT: tail call void @test16_sub(i32* noalias nofree writeonly [[P]], i32 [[C]], i32 [[C]]) #[[ATTR13]] +; IS__CGSCC____-NEXT: ret void ; tail call void @test16_sub(i32* %p, i32 %c, i32 %c) ret void @@ -804,10 +822,10 @@ define void @test17_caller(i32* noalias %p, i32 %c) { ; IS__CGSCC____-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C]], 0 ; IS__CGSCC____-NEXT: br i1 [[TOBOOL]], label [[L1:%.*]], label [[L2:%.*]] ; IS__CGSCC____: l1: -; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree writeonly [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree writeonly [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: br label [[L3:%.*]] ; IS__CGSCC____: l2: -; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: br label [[L3]] ; IS__CGSCC____: l3: ; IS__CGSCC____-NEXT: ret void @@ -840,9 +858,9 @@ l3: ; } define void @noreturn() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@noreturn -; CHECK-SAME: () #[[ATTR0]] { +; CHECK-SAME: () #[[ATTR9:[0-9]+]] { ; CHECK-NEXT: ret void ; call void @noreturn() @@ -870,10 +888,10 @@ define void @test18_caller(i32* noalias %p, i32 %c) { ; IS__CGSCC____-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C]], 0 ; IS__CGSCC____-NEXT: br i1 [[TOBOOL]], label [[L1:%.*]], label [[L2:%.*]] ; IS__CGSCC____: l1: -; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @make_alias(i32* nofree nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: br label [[L2]] ; IS__CGSCC____: l2: -; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR12]] +; IS__CGSCC____-NEXT: tail call void @only_store(i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[P]]) #[[ATTR13]] ; IS__CGSCC____-NEXT: ret void ; entry: @@ -913,8 +931,9 @@ l2: ; IS__CGSCC____: attributes #[[ATTR6:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } ; IS__CGSCC____: attributes #[[ATTR7]] = { nofree norecurse nosync nounwind willreturn writeonly } ; IS__CGSCC____: attributes #[[ATTR8]] = { argmemonly nofree norecurse nosync nounwind willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR9]] = { nounwind readnone willreturn } -; IS__CGSCC____: attributes #[[ATTR10]] = { nounwind readonly willreturn } -; IS__CGSCC____: attributes #[[ATTR11]] = { willreturn } -; IS__CGSCC____: attributes #[[ATTR12]] = { nounwind willreturn writeonly } +; IS__CGSCC____: attributes #[[ATTR9]] = { nofree nosync nounwind readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR10]] = { readnone willreturn } +; IS__CGSCC____: attributes #[[ATTR11]] = { readonly willreturn } +; IS__CGSCC____: attributes #[[ATTR12]] = { willreturn } +; IS__CGSCC____: attributes #[[ATTR13]] = { nounwind willreturn writeonly } ;. diff --git a/llvm/test/Transforms/Attributor/nocapture-2.ll b/llvm/test/Transforms/Attributor/nocapture-2.ll index 619c4f4b35bfc..244f051c30400 100644 --- a/llvm/test/Transforms/Attributor/nocapture-2.ll +++ b/llvm/test/Transforms/Attributor/nocapture-2.ll @@ -101,9 +101,9 @@ return: ; preds = %if.end3, %if.then2, ; } ; define double* @srec0(double* %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; CHECK: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@srec0 -; CHECK-SAME: (double* nocapture nofree readnone [[A:%.*]]) #[[ATTR0]] { +; CHECK-SAME: (double* nocapture nofree readnone [[A:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: ret double* null ; @@ -126,9 +126,9 @@ entry: ; Other arguments are possible here due to the no-return behavior. ; define i32* @srec16(i32* %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; CHECK: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@srec16 -; CHECK-SAME: (i32* nocapture nofree readnone [[A:%.*]]) #[[ATTR0]] { +; CHECK-SAME: (i32* nocapture nofree readnone [[A:%.*]]) #[[ATTR1]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: ret i32* undef ; @@ -168,17 +168,17 @@ entry: define float* @scc_A(i32* dereferenceable_or_null(4) %a) { ; CHECK: Function Attrs: nofree nosync nounwind readnone ; CHECK-LABEL: define {{[^@]+}}@scc_A -; CHECK-SAME: (i32* nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-SAME: (i32* nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32* [[A]], null ; CHECK-NEXT: br i1 [[TOBOOL]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] ; CHECK: cond.true: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A]] to i16* -; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[CALL]] to double* -; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP1]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP1]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[CALL1]] to i32* -; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[CALL2]] to i32* ; CHECK-NEXT: br label [[COND_END:%.*]] ; CHECK: cond.false: @@ -215,17 +215,17 @@ cond.end: ; preds = %cond.false, %cond.t define i64* @scc_B(double* dereferenceable_or_null(8) %a) { ; CHECK: Function Attrs: nofree nosync nounwind readnone ; CHECK-LABEL: define {{[^@]+}}@scc_B -; CHECK-SAME: (double* nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR1]] { +; CHECK-SAME: (double* nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne double* [[A]], null ; CHECK-NEXT: br i1 [[TOBOOL]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] ; CHECK: cond.true: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast double* [[A]] to i32* -; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[CALL]] to double* -; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP1]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP1]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[CALL1]] to i16* -; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR2]] ; CHECK-NEXT: br label [[COND_END:%.*]] ; CHECK: cond.false: ; CHECK-NEXT: [[TMP3:%.*]] = bitcast double* [[A]] to i8* @@ -261,25 +261,25 @@ cond.end: ; preds = %cond.false, %cond.t define i8* @scc_C(i16* dereferenceable_or_null(2) %a) { ; CHECK: Function Attrs: nofree nosync nounwind readnone ; CHECK-LABEL: define {{[^@]+}}@scc_C -; CHECK-SAME: (i16* nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR1]] { +; CHECK-SAME: (i16* nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BC:%.*]] = bitcast i16* [[A]] to i32* -; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[BC]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[BC]]) #[[ATTR2]] ; CHECK-NEXT: [[BC2:%.*]] = bitcast float* [[CALL]] to i8* ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[BC2]], null ; CHECK-NEXT: br i1 [[TOBOOL]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] ; CHECK: cond.true: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[A]] to double* -; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL1:%.*]] = call dereferenceable_or_null(4) i64* @scc_B(double* noalias nofree readnone dereferenceable_or_null(8) "no-capture-maybe-returned" [[TMP0]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[CALL1]] to i8* ; CHECK-NEXT: br label [[COND_END:%.*]] ; CHECK: cond.false: -; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL2:%.*]] = call dereferenceable_or_null(4) i8* @scc_C(i16* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[A]]) #[[ATTR2]] ; CHECK-NEXT: br label [[COND_END]] ; CHECK: cond.end: ; CHECK-NEXT: [[COND:%.*]] = phi i8* [ [[TMP1]], [[COND_TRUE]] ], [ [[CALL2]], [[COND_FALSE]] ] ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[COND]] to i32* -; CHECK-NEXT: [[CALL3:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR1]] +; CHECK-NEXT: [[CALL3:%.*]] = call dereferenceable_or_null(4) float* @scc_A(i32* noalias nofree readnone dereferenceable_or_null(4) "no-capture-maybe-returned" [[TMP2]]) #[[ATTR2]] ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[CALL3]] to i8* ; CHECK-NEXT: ret i8* [[TMP3]] ; @@ -321,7 +321,7 @@ declare void @external_no_capture(i32* nocapture) define void @test_external_no_capture(i32* %p) #0 { ; CHECK: Function Attrs: noinline nounwind uwtable ; CHECK-LABEL: define {{[^@]+}}@test_external_no_capture -; CHECK-SAME: (i32* nocapture [[P:%.*]]) #[[ATTR2:[0-9]+]] { +; CHECK-SAME: (i32* nocapture [[P:%.*]]) #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @external_no_capture(i32* nocapture [[P]]) ; CHECK-NEXT: ret void @@ -340,7 +340,7 @@ entry: define void @test_var_arg_call(i8* %p, i32 %a) #0 { ; CHECK: Function Attrs: noinline nounwind uwtable ; CHECK-LABEL: define {{[^@]+}}@test_var_arg_call -; CHECK-SAME: (i8* nocapture [[P:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { +; CHECK-SAME: (i8* nocapture [[P:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* nocapture [[P]], i32 [[A]]) ; CHECK-NEXT: ret void @@ -364,7 +364,7 @@ declare i32 @printf(i8* nocapture, ...) define i64* @not_captured_but_returned_0(i64* %a) #0 { ; CHECK: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_but_returned_0 -; CHECK-SAME: (i64* nofree noundef nonnull returned writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3:[0-9]+]] { +; CHECK-SAME: (i64* nofree noundef nonnull returned writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: store i64 0, i64* [[A]], align 8 ; CHECK-NEXT: ret i64* [[A]] @@ -385,7 +385,7 @@ entry: define i64* @not_captured_but_returned_1(i64* %a) #0 { ; CHECK: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_but_returned_1 -; CHECK-SAME: (i64* nofree nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3]] { +; CHECK-SAME: (i64* nofree nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i64, i64* [[A]], i64 1 ; CHECK-NEXT: store i64 1, i64* [[ADD_PTR]], align 8 @@ -407,18 +407,18 @@ entry: define void @test_not_captured_but_returned_calls(i64* %a) #0 { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@test_not_captured_but_returned_calls -; IS__TUNIT____-SAME: (i64* nocapture nofree writeonly align 8 [[A:%.*]]) #[[ATTR3]] { +; IS__TUNIT____-SAME: (i64* nocapture nofree writeonly align 8 [[A:%.*]]) #[[ATTR4]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8:[0-9]+]] -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9:[0-9]+]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@test_not_captured_but_returned_calls -; IS__CGSCC____-SAME: (i64* nocapture nofree noundef nonnull writeonly align 8 dereferenceable(16) [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC____-SAME: (i64* nocapture nofree noundef nonnull writeonly align 8 dereferenceable(16) [[A:%.*]]) #[[ATTR4]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR8:[0-9]+]] -; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR9:[0-9]+]] +; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__CGSCC____-NEXT: ret void ; entry: @@ -437,16 +437,16 @@ entry: define i64* @negative_test_not_captured_but_returned_call_0a(i64* %a) #0 { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_0a -; IS__TUNIT____-SAME: (i64* nofree returned writeonly align 8 "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3]] { +; IS__TUNIT____-SAME: (i64* nofree returned writeonly align 8 "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__TUNIT____-NEXT: ret i64* [[A]] ; ; IS__CGSCC____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_0a -; IS__CGSCC____-SAME: (i64* nofree noundef nonnull returned writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC____-SAME: (i64* nofree noundef nonnull returned writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__CGSCC____-NEXT: ret i64* [[A]] ; entry: @@ -464,18 +464,18 @@ entry: define void @negative_test_not_captured_but_returned_call_0b(i64* %a) #0 { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_0b -; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 [[A:%.*]]) #[[ATTR3]] { +; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 [[A:%.*]]) #[[ATTR4]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__TUNIT____-NEXT: [[TMP0:%.*]] = ptrtoint i64* [[A]] to i64 ; IS__TUNIT____-NEXT: store i64 [[TMP0]], i64* [[A]], align 8 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_0b -; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i64* @not_captured_but_returned_0(i64* nofree noundef nonnull writeonly align 8 dereferenceable(8) "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__CGSCC____-NEXT: [[TMP0:%.*]] = ptrtoint i64* [[A]] to i64 ; IS__CGSCC____-NEXT: store i64 [[TMP0]], i64* [[A]], align 8 ; IS__CGSCC____-NEXT: ret void @@ -497,16 +497,16 @@ entry: define i64* @negative_test_not_captured_but_returned_call_1a(i64* %a) #0 { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_1a -; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3]] { +; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call noundef nonnull align 8 dereferenceable(8) i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call noundef nonnull align 8 dereferenceable(8) i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__TUNIT____-NEXT: ret i64* [[CALL]] ; ; IS__CGSCC____: Function Attrs: argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_1a -; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR4]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call noundef nonnull align 8 dereferenceable(8) i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call noundef nonnull align 8 dereferenceable(8) i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__CGSCC____-NEXT: ret i64* [[CALL]] ; entry: @@ -524,18 +524,18 @@ entry: define void @negative_test_not_captured_but_returned_call_1b(i64* %a) #0 { ; IS__TUNIT____: Function Attrs: nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_1b -; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 [[A:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__TUNIT____-SAME: (i64* nofree writeonly align 8 [[A:%.*]]) #[[ATTR5:[0-9]+]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call align 8 i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call align 8 i64* @not_captured_but_returned_1(i64* nofree writeonly align 8 "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__TUNIT____-NEXT: [[TMP0:%.*]] = ptrtoint i64* [[CALL]] to i64 ; IS__TUNIT____-NEXT: store i64 [[TMP0]], i64* [[CALL]], align 8 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree noinline norecurse nosync nounwind uwtable willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@negative_test_not_captured_but_returned_call_1b -; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) [[A:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__CGSCC____-SAME: (i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) [[A:%.*]]) #[[ATTR5:[0-9]+]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call align 8 i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR8]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call align 8 i64* @not_captured_but_returned_1(i64* nofree noundef nonnull writeonly align 8 dereferenceable(16) "no-capture-maybe-returned" [[A]]) #[[ATTR9]] ; IS__CGSCC____-NEXT: [[TMP0:%.*]] = ptrtoint i64* [[CALL]] to i64 ; IS__CGSCC____-NEXT: store i64 [[TMP0]], i64* [[CALL]], align 8 ; IS__CGSCC____-NEXT: ret void @@ -561,7 +561,7 @@ entry: define i32* @ret_arg_or_unknown(i32* %b) #0 { ; CHECK: Function Attrs: noinline nounwind uwtable ; CHECK-LABEL: define {{[^@]+}}@ret_arg_or_unknown -; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR2]] { +; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null ; CHECK-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] @@ -586,7 +586,7 @@ ret_unknown: define i32* @ret_arg_or_unknown_through_phi(i32* %b) #0 { ; CHECK: Function Attrs: noinline nounwind uwtable ; CHECK-LABEL: define {{[^@]+}}@ret_arg_or_unknown_through_phi -; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR2]] { +; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null ; CHECK-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] @@ -623,9 +623,9 @@ declare i32* @readonly_unknown(i32*, i32*) readonly define void @not_captured_by_readonly_call(i32* %b) #0 { ; CHECK: Function Attrs: noinline nounwind readonly uwtable ; CHECK-LABEL: define {{[^@]+}}@not_captured_by_readonly_call -; CHECK-SAME: (i32* nocapture readonly [[B:%.*]]) #[[ATTR6:[0-9]+]] { +; CHECK-SAME: (i32* nocapture readonly [[B:%.*]]) #[[ATTR7:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown(i32* readonly [[B]], i32* readonly [[B]]) #[[ATTR5:[0-9]+]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown(i32* readonly [[B]], i32* readonly [[B]]) #[[ATTR6:[0-9]+]] ; CHECK-NEXT: ret void ; entry: @@ -641,9 +641,9 @@ entry: define i32* @not_captured_by_readonly_call_not_returned_either1(i32* %b, i32* returned %r) { ; CHECK: Function Attrs: nounwind readonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_by_readonly_call_not_returned_either1 -; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR7:[0-9]+]] { +; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR8:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR7]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR8]] ; CHECK-NEXT: ret i32* [[R]] ; entry: @@ -655,9 +655,9 @@ declare i32* @readonly_unknown_r1a(i32*, i32* returned) readonly define i32* @not_captured_by_readonly_call_not_returned_either2(i32* %b, i32* %r) { ; CHECK: Function Attrs: nounwind readonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_by_readonly_call_not_returned_either2 -; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR7]] { +; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR8]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1a(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR7]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1a(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR8]] ; CHECK-NEXT: ret i32* [[R]] ; entry: @@ -669,9 +669,9 @@ declare i32* @readonly_unknown_r1b(i32*, i32* returned) readonly nounwind define i32* @not_captured_by_readonly_call_not_returned_either3(i32* %b, i32* %r) { ; CHECK: Function Attrs: nounwind readonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_by_readonly_call_not_returned_either3 -; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR7]] { +; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR8]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1b(i32* nocapture readonly [[B]], i32* readonly [[R]]) #[[ATTR7]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1b(i32* nocapture readonly [[B]], i32* readonly [[R]]) #[[ATTR8]] ; CHECK-NEXT: ret i32* [[R]] ; entry: @@ -682,9 +682,9 @@ entry: define i32* @not_captured_by_readonly_call_not_returned_either4(i32* %b, i32* %r) nounwind { ; CHECK: Function Attrs: nounwind readonly ; CHECK-LABEL: define {{[^@]+}}@not_captured_by_readonly_call_not_returned_either4 -; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR7]] { +; CHECK-SAME: (i32* nocapture readonly [[B:%.*]], i32* readonly returned [[R:%.*]]) #[[ATTR8]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1a(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR5]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_unknown_r1a(i32* readonly [[B]], i32* readonly [[R]]) #[[ATTR6]] ; CHECK-NEXT: ret i32* [[R]] ; entry: @@ -713,7 +713,7 @@ define void @nocapture_is_not_subsumed_2(i32* nocapture %b) { ; CHECK-LABEL: define {{[^@]+}}@nocapture_is_not_subsumed_2 ; CHECK-SAME: (i32* nocapture [[B:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_i32p(i32* readonly [[B]]) #[[ATTR5]] +; CHECK-NEXT: [[CALL:%.*]] = call i32* @readonly_i32p(i32* readonly [[B]]) #[[ATTR6]] ; CHECK-NEXT: store i32 0, i32* [[CALL]], align 4 ; CHECK-NEXT: ret void ; @@ -726,22 +726,24 @@ entry: attributes #0 = { noinline nounwind uwtable } ;. ; IS__TUNIT____: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; IS__TUNIT____: attributes #[[ATTR1]] = { nofree nosync nounwind readnone } -; IS__TUNIT____: attributes #[[ATTR2]] = { noinline nounwind uwtable } -; IS__TUNIT____: attributes #[[ATTR3]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__TUNIT____: attributes #[[ATTR4]] = { nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__TUNIT____: attributes #[[ATTR5]] = { readonly } -; IS__TUNIT____: attributes #[[ATTR6]] = { noinline nounwind readonly uwtable } -; IS__TUNIT____: attributes #[[ATTR7]] = { nounwind readonly } -; IS__TUNIT____: attributes #[[ATTR8]] = { nofree nosync nounwind willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__TUNIT____: attributes #[[ATTR2]] = { nofree nosync nounwind readnone } +; IS__TUNIT____: attributes #[[ATTR3]] = { noinline nounwind uwtable } +; IS__TUNIT____: attributes #[[ATTR4]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR5]] = { nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__TUNIT____: attributes #[[ATTR6]] = { readonly } +; IS__TUNIT____: attributes #[[ATTR7]] = { noinline nounwind readonly uwtable } +; IS__TUNIT____: attributes #[[ATTR8]] = { nounwind readonly } +; IS__TUNIT____: attributes #[[ATTR9]] = { nofree nosync nounwind willreturn writeonly } ;. ; IS__CGSCC____: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; IS__CGSCC____: attributes #[[ATTR1]] = { nofree nosync nounwind readnone } -; IS__CGSCC____: attributes #[[ATTR2]] = { noinline nounwind uwtable } -; IS__CGSCC____: attributes #[[ATTR3]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR4]] = { nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } -; IS__CGSCC____: attributes #[[ATTR5]] = { readonly } -; IS__CGSCC____: attributes #[[ATTR6]] = { noinline nounwind readonly uwtable } -; IS__CGSCC____: attributes #[[ATTR7]] = { nounwind readonly } -; IS__CGSCC____: attributes #[[ATTR8]] = { nounwind willreturn writeonly } +; IS__CGSCC____: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__CGSCC____: attributes #[[ATTR2]] = { nofree nosync nounwind readnone } +; IS__CGSCC____: attributes #[[ATTR3]] = { noinline nounwind uwtable } +; IS__CGSCC____: attributes #[[ATTR4]] = { argmemonly nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__CGSCC____: attributes #[[ATTR5]] = { nofree noinline norecurse nosync nounwind uwtable willreturn writeonly } +; IS__CGSCC____: attributes #[[ATTR6]] = { readonly } +; IS__CGSCC____: attributes #[[ATTR7]] = { noinline nounwind readonly uwtable } +; IS__CGSCC____: attributes #[[ATTR8]] = { nounwind readonly } +; IS__CGSCC____: attributes #[[ATTR9]] = { nounwind willreturn writeonly } ;. diff --git a/llvm/test/Transforms/Attributor/nodelete.ll b/llvm/test/Transforms/Attributor/nodelete.ll index 4b957ed2ee23d..1342fd39fd67a 100644 --- a/llvm/test/Transforms/Attributor/nodelete.ll +++ b/llvm/test/Transforms/Attributor/nodelete.ll @@ -32,8 +32,6 @@ define internal i64 @f2(%"a"* %this) align 2 { ; IS__CGSCC____-LABEL: define {{[^@]+}}@f2 ; IS__CGSCC____-SAME: () #[[ATTR0]] align 2 { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[THIS_ADDR:%.*]] = alloca %a*, align 8 -; IS__CGSCC____-NEXT: [[THIS1:%.*]] = load %a*, %a** [[THIS_ADDR]], align 8 ; IS__CGSCC____-NEXT: ret i64 undef ; entry: diff --git a/llvm/test/Transforms/Attributor/nofree.ll b/llvm/test/Transforms/Attributor/nofree.ll index 952721b631fa5..f1c6089caa78f 100644 --- a/llvm/test/Transforms/Attributor/nofree.ll +++ b/llvm/test/Transforms/Attributor/nofree.ll @@ -106,20 +106,30 @@ end: define void @mutual_recursion1() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@mutual_recursion1 -; CHECK-SAME: () #[[ATTR3]] { -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@mutual_recursion1 +; NOT_CGSCC_NPM-SAME: () #[[ATTR4:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@mutual_recursion1 +; IS__CGSCC_NPM-SAME: () #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: ret void ; call void @mutual_recursion2() ret void } define void @mutual_recursion2() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@mutual_recursion2 -; CHECK-SAME: () #[[ATTR3]] { -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@mutual_recursion2 +; NOT_CGSCC_NPM-SAME: () #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@mutual_recursion2 +; IS__CGSCC_NPM-SAME: () #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: ret void ; call void @mutual_recursion1() ret void @@ -179,10 +189,15 @@ define noalias i8* @call_realloc(i8* nocapture %0, i64 %1) local_unnamed_addr #0 declare void @nofree_function() nofree readnone #0 define void @call_nofree_function() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@call_nofree_function -; CHECK-SAME: () #[[ATTR3]] { -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@call_nofree_function +; NOT_CGSCC_NPM-SAME: () #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_nofree_function +; IS__CGSCC_NPM-SAME: () #[[ATTR5:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: ret void ; tail call void @nofree_function() ret void @@ -232,21 +247,32 @@ define void @call_both() #0 { declare float @llvm.floor.f32(float) define void @call_floor(float %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@call_floor -; CHECK-SAME: (float [[A:%.*]]) #[[ATTR3]] { -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor +; NOT_CGSCC_NPM-SAME: (float [[A:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor +; IS__CGSCC_NPM-SAME: (float [[A:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: ret void ; tail call float @llvm.floor.f32(float %a) ret void } define float @call_floor2(float %a) #0 { -; CHECK: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@call_floor2 -; CHECK-SAME: (float [[A:%.*]]) #[[ATTR6:[0-9]+]] { -; CHECK-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) #[[ATTR11:[0-9]+]] -; CHECK-NEXT: ret float [[C]] +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor2 +; NOT_CGSCC_NPM-SAME: (float [[A:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) #[[ATTR11:[0-9]+]] +; NOT_CGSCC_NPM-NEXT: ret float [[C]] +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor2 +; IS__CGSCC_NPM-SAME: (float [[A:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) #[[ATTR11:[0-9]+]] +; IS__CGSCC_NPM-NEXT: ret float [[C]] ; %c = tail call float @llvm.floor.f32(float %a) ret float %c @@ -256,20 +282,30 @@ define float @call_floor2(float %a) #0 { ; Check propagation. define void @f1() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@f1 -; CHECK-SAME: () #[[ATTR3]] { -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f1 +; NOT_CGSCC_NPM-SAME: () #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f1 +; IS__CGSCC_NPM-SAME: () #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: ret void ; tail call void @nofree_function() ret void } define void @f2() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@f2 -; CHECK-SAME: () #[[ATTR3]] { -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@f2 +; IS__TUNIT____-SAME: () #[[ATTR4]] { +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@f2 +; IS__CGSCC____-SAME: () #[[ATTR3]] { +; IS__CGSCC____-NEXT: ret void ; tail call void @f1() ret void @@ -414,17 +450,31 @@ attributes #0 = { nounwind uwtable noinline } attributes #1 = { nounwind } attributes #2 = { nobuiltin nounwind } ;. -; CHECK: attributes #[[ATTR0]] = { nounwind } -; CHECK: attributes #[[ATTR1]] = { noinline nounwind uwtable } -; CHECK: attributes #[[ATTR2]] = { nobuiltin nounwind } -; CHECK: attributes #[[ATTR3]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; CHECK: attributes #[[ATTR4:[0-9]+]] = { nofree noinline nounwind readnone uwtable } -; CHECK: attributes #[[ATTR5:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } -; CHECK: attributes #[[ATTR6]] = { nofree noinline nosync nounwind readnone uwtable willreturn } -; CHECK: attributes #[[ATTR7]] = { nofree nounwind } -; CHECK: attributes #[[ATTR8:[0-9]+]] = { nobuiltin nofree nounwind } -; CHECK: attributes #[[ATTR9:[0-9]+]] = { inaccessiblememonly nofree nosync nounwind willreturn } -; CHECK: attributes #[[ATTR10:[0-9]+]] = { nounwind willreturn } -; CHECK: attributes #[[ATTR11]] = { readnone willreturn } -; CHECK: attributes #[[ATTR12]] = { willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR0]] = { nounwind } +; NOT_CGSCC_NPM: attributes #[[ATTR1]] = { noinline nounwind uwtable } +; NOT_CGSCC_NPM: attributes #[[ATTR2]] = { nobuiltin nounwind } +; NOT_CGSCC_NPM: attributes #[[ATTR3]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR4]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR5:[0-9]+]] = { nofree noinline nounwind readnone uwtable } +; NOT_CGSCC_NPM: attributes #[[ATTR6:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR7]] = { nofree nounwind } +; NOT_CGSCC_NPM: attributes #[[ATTR8:[0-9]+]] = { nobuiltin nofree nounwind } +; NOT_CGSCC_NPM: attributes #[[ATTR9:[0-9]+]] = { inaccessiblememonly nofree nosync nounwind willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR10:[0-9]+]] = { nounwind willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR11]] = { readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR12]] = { willreturn } +;. +; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR1]] = { noinline nounwind uwtable } +; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nobuiltin nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR3]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR4:[0-9]+]] = { nofree noinline nounwind readnone uwtable } +; IS__CGSCC_NPM: attributes #[[ATTR5]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR6:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR7]] = { nofree nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR8:[0-9]+]] = { nobuiltin nofree nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR9:[0-9]+]] = { inaccessiblememonly nofree nosync nounwind willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR10:[0-9]+]] = { nounwind willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR11]] = { readnone willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR12]] = { willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/nonnull.ll b/llvm/test/Transforms/Attributor/nonnull.ll index f4dcff85e78ab..7d4f6ecc08b4f 100644 --- a/llvm/test/Transforms/Attributor/nonnull.ll +++ b/llvm/test/Transforms/Attributor/nonnull.ll @@ -31,16 +31,27 @@ define i8* @test2(i8* nonnull %p) { } define i8* @test2A(i1 %c, i8* %ret) { -; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@test2A -; CHECK-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] -; CHECK: A: -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11:[0-9]+]] [ "nonnull"(i8* [[RET]]) ] -; CHECK-NEXT: ret i8* [[RET]] -; CHECK: B: -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "nonnull"(i8* [[RET]]) ] -; CHECK-NEXT: ret i8* [[RET]] +; NOT_CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test2A +; NOT_CGSCC_NPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] +; NOT_CGSCC_NPM: A: +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12:[0-9]+]] [ "nonnull"(i8* [[RET]]) ] +; NOT_CGSCC_NPM-NEXT: ret i8* [[RET]] +; NOT_CGSCC_NPM: B: +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12]] [ "nonnull"(i8* [[RET]]) ] +; NOT_CGSCC_NPM-NEXT: ret i8* [[RET]] +; +; IS__CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test2A +; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] +; IS__CGSCC_NPM: A: +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11:[0-9]+]] [ "nonnull"(i8* [[RET]]) ] +; IS__CGSCC_NPM-NEXT: ret i8* [[RET]] +; IS__CGSCC_NPM: B: +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "nonnull"(i8* [[RET]]) ] +; IS__CGSCC_NPM-NEXT: ret i8* [[RET]] ; br i1 %c, label %A, label %B A: @@ -52,16 +63,27 @@ B: } define i8* @test2B(i1 %c, i8* %ret) { -; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@test2B -; CHECK-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] -; CHECK: A: -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] -; CHECK-NEXT: ret i8* [[RET]] -; CHECK: B: -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] -; CHECK-NEXT: ret i8* [[RET]] +; NOT_CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test2B +; NOT_CGSCC_NPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0]] { +; NOT_CGSCC_NPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] +; NOT_CGSCC_NPM: A: +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; NOT_CGSCC_NPM-NEXT: ret i8* [[RET]] +; NOT_CGSCC_NPM: B: +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; NOT_CGSCC_NPM-NEXT: ret i8* [[RET]] +; +; IS__CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test2B +; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] +; IS__CGSCC_NPM: A: +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; IS__CGSCC_NPM-NEXT: ret i8* [[RET]] +; IS__CGSCC_NPM: B: +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; IS__CGSCC_NPM-NEXT: ret i8* [[RET]] ; br i1 %c, label %A, label %B A: @@ -117,20 +139,30 @@ define i8* @test3(i1 %c) { ; nonnull if neither can ever return null. (In this case, they ; just never return period.) define i8* @test4_helper() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@test4_helper -; CHECK-SAME: () #[[ATTR1]] { -; CHECK-NEXT: ret i8* undef +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test4_helper +; NOT_CGSCC_NPM-SAME: () #[[ATTR2:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: ret i8* undef +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test4_helper +; IS__CGSCC_NPM-SAME: () #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: ret i8* undef ; %ret = call i8* @test4() ret i8* %ret } define i8* @test4() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@test4 -; CHECK-SAME: () #[[ATTR1]] { -; CHECK-NEXT: ret i8* undef +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test4 +; NOT_CGSCC_NPM-SAME: () #[[ATTR2]] { +; NOT_CGSCC_NPM-NEXT: ret i8* undef +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test4 +; IS__CGSCC_NPM-SAME: () #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: ret i8* undef ; %ret = call i8* @test4_helper() ret i8* %ret @@ -139,14 +171,23 @@ define i8* @test4() { ; Given a mutual recursive set of functions which *can* return null ; make sure we haven't marked them as nonnull. define i8* @test5_helper(i1 %c) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@test5_helper -; CHECK-SAME: (i1 [[C:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: br i1 [[C]], label [[REC:%.*]], label [[END:%.*]] -; CHECK: rec: -; CHECK-NEXT: br label [[END]] -; CHECK: end: -; CHECK-NEXT: ret i8* null +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test5_helper +; NOT_CGSCC_NPM-SAME: (i1 [[C:%.*]]) #[[ATTR2]] { +; NOT_CGSCC_NPM-NEXT: br i1 [[C]], label [[REC:%.*]], label [[END:%.*]] +; NOT_CGSCC_NPM: rec: +; NOT_CGSCC_NPM-NEXT: br label [[END]] +; NOT_CGSCC_NPM: end: +; NOT_CGSCC_NPM-NEXT: ret i8* null +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test5_helper +; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: br i1 [[C]], label [[REC:%.*]], label [[END:%.*]] +; IS__CGSCC_NPM: rec: +; IS__CGSCC_NPM-NEXT: br label [[END]] +; IS__CGSCC_NPM: end: +; IS__CGSCC_NPM-NEXT: ret i8* null ; br i1 %c, label %rec, label %end rec: @@ -157,10 +198,15 @@ end: } define i8* @test5(i1 %c) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@test5 -; CHECK-SAME: (i1 [[C:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: ret i8* null +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test5 +; NOT_CGSCC_NPM-SAME: (i1 [[C:%.*]]) #[[ATTR2]] { +; NOT_CGSCC_NPM-NEXT: ret i8* null +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test5 +; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]]) #[[ATTR1]] { +; IS__CGSCC_NPM-NEXT: ret i8* null ; %ret = call i8* @test5_helper(i1 %c) ret i8* %ret @@ -169,16 +215,27 @@ define i8* @test5(i1 %c) { ; Local analysis, but going through a self recursive phi define i8* @test6a() { ; -; CHECK: Function Attrs: noreturn -; CHECK-LABEL: define {{[^@]+}}@test6a -; CHECK-SAME: () #[[ATTR2:[0-9]+]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[RET:%.*]] = call i8* @ret_nonnull() -; CHECK-NEXT: br label [[LOOP:%.*]] -; CHECK: loop: -; CHECK-NEXT: unreachable -; CHECK: exit: -; CHECK-NEXT: unreachable +; NOT_CGSCC_NPM: Function Attrs: noreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test6a +; NOT_CGSCC_NPM-SAME: () #[[ATTR3:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: entry: +; NOT_CGSCC_NPM-NEXT: [[RET:%.*]] = call i8* @ret_nonnull() +; NOT_CGSCC_NPM-NEXT: br label [[LOOP:%.*]] +; NOT_CGSCC_NPM: loop: +; NOT_CGSCC_NPM-NEXT: unreachable +; NOT_CGSCC_NPM: exit: +; NOT_CGSCC_NPM-NEXT: unreachable +; +; IS__CGSCC_NPM: Function Attrs: noreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test6a +; IS__CGSCC_NPM-SAME: () #[[ATTR2:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: entry: +; IS__CGSCC_NPM-NEXT: [[RET:%.*]] = call i8* @ret_nonnull() +; IS__CGSCC_NPM-NEXT: br label [[LOOP:%.*]] +; IS__CGSCC_NPM: loop: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: exit: +; IS__CGSCC_NPM-NEXT: unreachable ; entry: %ret = call i8* @ret_nonnull() @@ -247,12 +304,19 @@ define i8* @test9(i8* %a, i64 %n) { ; ATTRIBUTOR_OPM: define i8* @test10 ; ATTRIBUTOR_NPM: define nonnull i8* @test10 define i8* @test10(i8* %a, i64 %n) { -; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@test10 -; CHECK-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] -; CHECK-NEXT: [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]] -; CHECK-NEXT: ret i8* [[B]] +; NOT_CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test10 +; NOT_CGSCC_NPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12]] +; NOT_CGSCC_NPM-NEXT: [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]] +; NOT_CGSCC_NPM-NEXT: ret i8* [[B]] +; +; IS__CGSCC_NPM: Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test10 +; IS__CGSCC_NPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] +; IS__CGSCC_NPM-NEXT: [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]] +; IS__CGSCC_NPM-NEXT: ret i8* [[B]] ; %cmp = icmp ne i64 %n, 0 call void @llvm.assume(i1 %cmp) @@ -306,12 +370,19 @@ define void @test12(i8* nonnull %a) { ; Simple Argument Tests declare i8* @unknown() define void @test13_helper() { -; CHECK-LABEL: define {{[^@]+}}@test13_helper() { -; CHECK-NEXT: [[NONNULLPTR:%.*]] = tail call nonnull i8* @ret_nonnull() -; CHECK-NEXT: [[MAYBENULLPTR:%.*]] = tail call i8* @unknown() -; CHECK-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]]) #[[ATTR3:[0-9]+]] -; CHECK-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test13_helper() { +; NOT_CGSCC_NPM-NEXT: [[NONNULLPTR:%.*]] = tail call nonnull i8* @ret_nonnull() +; NOT_CGSCC_NPM-NEXT: [[MAYBENULLPTR:%.*]] = tail call i8* @unknown() +; NOT_CGSCC_NPM-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]]) #[[ATTR4:[0-9]+]] +; NOT_CGSCC_NPM-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test13_helper() { +; IS__CGSCC_NPM-NEXT: [[NONNULLPTR:%.*]] = tail call nonnull i8* @ret_nonnull() +; IS__CGSCC_NPM-NEXT: [[MAYBENULLPTR:%.*]] = tail call i8* @unknown() +; IS__CGSCC_NPM-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]]) #[[ATTR3:[0-9]+]] +; IS__CGSCC_NPM-NEXT: tail call void @test13(i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]], i8* noalias nocapture nofree readnone [[MAYBENULLPTR]], i8* noalias nocapture nofree nonnull readnone [[NONNULLPTR]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; %nonnullptr = tail call i8* @ret_nonnull() %maybenullptr = tail call i8* @unknown() @@ -321,13 +392,21 @@ define void @test13_helper() { } define internal void @test13(i8* %a, i8* %b, i8* %c) { ; -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@test13 -; CHECK-SAME: (i8* noalias nocapture nofree nonnull readnone [[A:%.*]], i8* noalias nocapture nofree readnone [[B:%.*]], i8* noalias nocapture nofree readnone [[C:%.*]]) #[[ATTR3]] { -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[A]]) #[[ATTR3]] -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[B]]) #[[ATTR3]] -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[C]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test13 +; NOT_CGSCC_NPM-SAME: (i8* noalias nocapture nofree nonnull readnone [[A:%.*]], i8* noalias nocapture nofree readnone [[B:%.*]], i8* noalias nocapture nofree readnone [[C:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[B]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[C]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test13 +; IS__CGSCC_NPM-SAME: (i8* noalias nocapture nofree nonnull readnone [[A:%.*]], i8* noalias nocapture nofree readnone [[B:%.*]], i8* noalias nocapture nofree readnone [[C:%.*]]) #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[B]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[C]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; call void @use_i8_ptr(i8* %a) call void @use_i8_ptr(i8* %b) @@ -351,27 +430,49 @@ declare nonnull i8* @nonnull() define internal i32* @f1(i32* %arg) { ; FIXME: missing nonnull It should be nonnull @f1(i32* nonnull readonly %arg) -; CHECK: Function Attrs: argmemonly nofree nosync nounwind readonly -; CHECK-LABEL: define {{[^@]+}}@f1 -; CHECK-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR4:[0-9]+]] { -; CHECK-NEXT: bb: -; CHECK-NEXT: [[TMP:%.*]] = icmp eq i32* [[ARG]], null -; CHECK-NEXT: br i1 [[TMP]], label [[BB9:%.*]], label [[BB1:%.*]] -; CHECK: bb1: -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]] -; CHECK: bb4: -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1 -; CHECK-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) #[[ATTR12:[0-9]+]] -; CHECK-NEXT: [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1 -; CHECK-NEXT: br label [[BB9]] -; CHECK: bb6: -; CHECK-NEXT: [[TMP7:%.*]] = tail call i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) #[[ATTR12]] -; CHECK-NEXT: ret i32* [[TMP7]] -; CHECK: bb9: -; CHECK-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ] -; CHECK-NEXT: ret i32* [[TMP10]] +; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f1 +; NOT_CGSCC_NPM-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR5:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: bb: +; NOT_CGSCC_NPM-NEXT: [[TMP:%.*]] = icmp eq i32* [[ARG]], null +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP]], label [[BB9:%.*]], label [[BB1:%.*]] +; NOT_CGSCC_NPM: bb1: +; NOT_CGSCC_NPM-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG]], align 4 +; NOT_CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]] +; NOT_CGSCC_NPM: bb4: +; NOT_CGSCC_NPM-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1 +; NOT_CGSCC_NPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) #[[ATTR13:[0-9]+]] +; NOT_CGSCC_NPM-NEXT: [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1 +; NOT_CGSCC_NPM-NEXT: br label [[BB9]] +; NOT_CGSCC_NPM: bb6: +; NOT_CGSCC_NPM-NEXT: [[TMP7:%.*]] = tail call i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) #[[ATTR13]] +; NOT_CGSCC_NPM-NEXT: ret i32* [[TMP7]] +; NOT_CGSCC_NPM: bb9: +; NOT_CGSCC_NPM-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ] +; NOT_CGSCC_NPM-NEXT: ret i32* [[TMP10]] +; +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f1 +; IS__CGSCC_NPM-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: bb: +; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = icmp eq i32* [[ARG]], null +; IS__CGSCC_NPM-NEXT: br i1 [[TMP]], label [[BB9:%.*]], label [[BB1:%.*]] +; IS__CGSCC_NPM: bb1: +; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG]], align 4 +; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]] +; IS__CGSCC_NPM: bb4: +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1 +; IS__CGSCC_NPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) #[[ATTR12:[0-9]+]] +; IS__CGSCC_NPM-NEXT: [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1 +; IS__CGSCC_NPM-NEXT: br label [[BB9]] +; IS__CGSCC_NPM: bb6: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = tail call i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) #[[ATTR12]] +; IS__CGSCC_NPM-NEXT: ret i32* [[TMP7]] +; IS__CGSCC_NPM: bb9: +; IS__CGSCC_NPM-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ] +; IS__CGSCC_NPM-NEXT: ret i32* [[TMP10]] ; bb: @@ -399,12 +500,19 @@ bb9: ; preds = %bb4, %bb } define internal i32* @f2(i32* %arg) { -; CHECK: Function Attrs: argmemonly nofree nosync nounwind readonly -; CHECK-LABEL: define {{[^@]+}}@f2 -; CHECK-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: bb: -; CHECK-NEXT: [[TMP:%.*]] = tail call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR12]] -; CHECK-NEXT: ret i32* [[TMP]] +; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f2 +; NOT_CGSCC_NPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR5]] { +; NOT_CGSCC_NPM-NEXT: bb: +; NOT_CGSCC_NPM-NEXT: [[TMP:%.*]] = tail call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR13]] +; NOT_CGSCC_NPM-NEXT: ret i32* [[TMP]] +; +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f2 +; IS__CGSCC_NPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR4]] { +; IS__CGSCC_NPM-NEXT: bb: +; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = tail call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR12]] +; IS__CGSCC_NPM-NEXT: ret i32* [[TMP]] ; bb: %tmp = tail call i32* @f1(i32* %arg) @@ -413,12 +521,19 @@ bb: define dso_local noalias i32* @f3(i32* %arg) { ; FIXME: missing nonnull. It should be nonnull @f3(i32* nonnull readonly %arg) -; CHECK: Function Attrs: argmemonly nofree nosync nounwind readonly -; CHECK-LABEL: define {{[^@]+}}@f3 -; CHECK-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: bb: -; CHECK-NEXT: [[TMP:%.*]] = call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR12]] -; CHECK-NEXT: ret i32* [[TMP]] +; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f3 +; NOT_CGSCC_NPM-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR5]] { +; NOT_CGSCC_NPM-NEXT: bb: +; NOT_CGSCC_NPM-NEXT: [[TMP:%.*]] = call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR13]] +; NOT_CGSCC_NPM-NEXT: ret i32* [[TMP]] +; +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind readonly +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f3 +; IS__CGSCC_NPM-SAME: (i32* nofree readonly [[ARG:%.*]]) #[[ATTR4]] { +; IS__CGSCC_NPM-NEXT: bb: +; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = call i32* @f1(i32* nofree readonly [[ARG]]) #[[ATTR12]] +; IS__CGSCC_NPM-NEXT: ret i32* [[TMP]] ; bb: ; FIXME: missing nonnull. It should be @f1(i32* nonnull readonly %arg) @@ -449,17 +564,29 @@ declare void @fun3(i8*, i8*, i8*) #1 ; fun2(nonnull %a, %b) ; We can say that %a is nonnull but %b is not. define void @f16(i8* %a, i8 * %b, i8 %c) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f16 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR5:[0-9]+]] { -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) #[[ATTR5]] -; CHECK-NEXT: ret void -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) #[[ATTR5]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f16 +; NOT_CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR6:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_NPM: if.then: +; NOT_CGSCC_NPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: ret void +; NOT_CGSCC_NPM: if.else: +; NOT_CGSCC_NPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f16 +; IS__CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR5:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_NPM: if.then: +; IS__CGSCC_NPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret void +; IS__CGSCC_NPM: if.else: +; IS__CGSCC_NPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret void ; %cmp = icmp eq i8 %c, 0 br i1 %cmp, label %if.then, label %if.else @@ -479,20 +606,35 @@ if.else: ; We can say that %a is nonnull define void @f17(i8* %a, i8 %c) { ; -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f17 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) #[[ATTR5]] { -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun0() #[[ATTR5]] -; CHECK-NEXT: br label [[CONT:%.*]] -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun0() #[[ATTR5]] -; CHECK-NEXT: br label [[CONT]] -; CHECK: cont: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR5]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f17 +; NOT_CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) #[[ATTR6]] { +; NOT_CGSCC_NPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_NPM: if.then: +; NOT_CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT:%.*]] +; NOT_CGSCC_NPM: if.else: +; NOT_CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT]] +; NOT_CGSCC_NPM: cont: +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f17 +; IS__CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_NPM: if.then: +; IS__CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT:%.*]] +; IS__CGSCC_NPM: if.else: +; IS__CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT]] +; IS__CGSCC_NPM: cont: +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret void ; %cmp = icmp eq i8 %c, 0 br i1 %cmp, label %if.then, label %if.else @@ -518,29 +660,53 @@ cont: ; fun1(nonnull %a) define void @f18(i8* %a, i8* %b, i8 %c) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f18 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR5]] { -; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun0() #[[ATTR5]] -; CHECK-NEXT: br label [[CONT:%.*]] -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun0() #[[ATTR5]] -; CHECK-NEXT: br label [[CONT]] -; CHECK: cont: -; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 -; CHECK-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] -; CHECK: cont.then: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR5]] -; CHECK-NEXT: br label [[CONT2:%.*]] -; CHECK: cont.else: -; CHECK-NEXT: tail call void @fun0() #[[ATTR5]] -; CHECK-NEXT: br label [[CONT2]] -; CHECK: cont2: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR5]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f18 +; NOT_CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR6]] { +; NOT_CGSCC_NPM-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_NPM: if.then: +; NOT_CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT:%.*]] +; NOT_CGSCC_NPM: if.else: +; NOT_CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT]] +; NOT_CGSCC_NPM: cont: +; NOT_CGSCC_NPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 +; NOT_CGSCC_NPM-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] +; NOT_CGSCC_NPM: cont.then: +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT2:%.*]] +; NOT_CGSCC_NPM: cont.else: +; NOT_CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: br label [[CONT2]] +; NOT_CGSCC_NPM: cont2: +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR6]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f18 +; IS__CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_NPM: if.then: +; IS__CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT:%.*]] +; IS__CGSCC_NPM: if.else: +; IS__CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT]] +; IS__CGSCC_NPM: cont: +; IS__CGSCC_NPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 +; IS__CGSCC_NPM-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] +; IS__CGSCC_NPM: cont.then: +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT2:%.*]] +; IS__CGSCC_NPM: cont.else: +; IS__CGSCC_NPM-NEXT: tail call void @fun0() #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[CONT2]] +; IS__CGSCC_NPM: cont2: +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret void ; %cmp1 = icmp eq i8 %c, 0 br i1 %cmp1, label %if.then, label %if.else @@ -567,20 +733,35 @@ cont2: ; TEST 19: Loop define void @f19(i8* %a, i8* %b, i8 %c) { -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@f19 -; CHECK-SAME: (i8* [[A:%.*]], i8* nonnull [[B:%.*]], i8 [[C:%.*]]) #[[ATTR3]] { -; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] -; CHECK: loop.header: -; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_BODY:%.*]], label [[LOOP_EXIT:%.*]] -; CHECK: loop.body: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR3]] -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR3]] -; CHECK-NEXT: br label [[LOOP_HEADER]] -; CHECK: loop.exit: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f19 +; NOT_CGSCC_NPM-SAME: (i8* [[A:%.*]], i8* nonnull [[B:%.*]], i8 [[C:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: br label [[LOOP_HEADER:%.*]] +; NOT_CGSCC_NPM: loop.header: +; NOT_CGSCC_NPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[CMP2]], label [[LOOP_BODY:%.*]], label [[LOOP_EXIT:%.*]] +; NOT_CGSCC_NPM: loop.body: +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: br label [[LOOP_HEADER]] +; NOT_CGSCC_NPM: loop.exit: +; NOT_CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f19 +; IS__CGSCC_NPM-SAME: (i8* [[A:%.*]], i8* nonnull [[B:%.*]], i8 [[C:%.*]]) #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: br label [[LOOP_HEADER:%.*]] +; IS__CGSCC_NPM: loop.header: +; IS__CGSCC_NPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[CMP2]], label [[LOOP_BODY:%.*]], label [[LOOP_EXIT:%.*]] +; IS__CGSCC_NPM: loop.body: +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: br label [[LOOP_HEADER]] +; IS__CGSCC_NPM: loop.exit: +; IS__CGSCC_NPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; br label %loop.header loop.header: @@ -713,11 +894,17 @@ define i8 @parent6(i8* %a, i8* %b) { ; The nonnull callsite is guaranteed to execute, so the argument must be nonnull throughout the parent. define i8 @parent7(i8* %a) { -; CHECK-LABEL: define {{[^@]+}}@parent7 -; CHECK-SAME: (i8* nonnull [[A:%.*]]) { -; CHECK-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) #[[ATTR13:[0-9]+]] -; CHECK-NEXT: call void @use1nonnull(i8* nonnull [[A]]) -; CHECK-NEXT: ret i8 [[RET]] +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@parent7 +; NOT_CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]]) { +; NOT_CGSCC_NPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) #[[ATTR14:[0-9]+]] +; NOT_CGSCC_NPM-NEXT: call void @use1nonnull(i8* nonnull [[A]]) +; NOT_CGSCC_NPM-NEXT: ret i8 [[RET]] +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@parent7 +; IS__CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]]) { +; IS__CGSCC_NPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) #[[ATTR13:[0-9]+]] +; IS__CGSCC_NPM-NEXT: call void @use1nonnull(i8* nonnull [[A]]) +; IS__CGSCC_NPM-NEXT: ret i8 [[RET]] ; @@ -731,18 +918,31 @@ define i8 @parent7(i8* %a) { declare i32 @esfp(...) define i1 @parent8(i8* %a, i8* %bogus1, i8* %b) personality i8* bitcast (i32 (...)* @esfp to i8*){ -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@parent8 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* nocapture nofree readnone [[BOGUS1:%.*]], i8* nonnull [[B:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @esfp to i8*) { -; CHECK-NEXT: entry: -; CHECK-NEXT: invoke void @use2nonnull(i8* nonnull [[A]], i8* nonnull [[B]]) -; CHECK-NEXT: to label [[CONT:%.*]] unwind label [[EXC:%.*]] -; CHECK: cont: -; CHECK-NEXT: ret i1 false -; CHECK: exc: -; CHECK-NEXT: [[LP:%.*]] = landingpad { i8*, i32 } -; CHECK-NEXT: filter [0 x i8*] zeroinitializer -; CHECK-NEXT: unreachable +; NOT_CGSCC_NPM: Function Attrs: nounwind +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@parent8 +; NOT_CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* nocapture nofree readnone [[BOGUS1:%.*]], i8* nonnull [[B:%.*]]) #[[ATTR4]] personality i8* bitcast (i32 (...)* @esfp to i8*) { +; NOT_CGSCC_NPM-NEXT: entry: +; NOT_CGSCC_NPM-NEXT: invoke void @use2nonnull(i8* nonnull [[A]], i8* nonnull [[B]]) +; NOT_CGSCC_NPM-NEXT: to label [[CONT:%.*]] unwind label [[EXC:%.*]] +; NOT_CGSCC_NPM: cont: +; NOT_CGSCC_NPM-NEXT: ret i1 false +; NOT_CGSCC_NPM: exc: +; NOT_CGSCC_NPM-NEXT: [[LP:%.*]] = landingpad { i8*, i32 } +; NOT_CGSCC_NPM-NEXT: filter [0 x i8*] zeroinitializer +; NOT_CGSCC_NPM-NEXT: unreachable +; +; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@parent8 +; IS__CGSCC_NPM-SAME: (i8* nonnull [[A:%.*]], i8* nocapture nofree readnone [[BOGUS1:%.*]], i8* nonnull [[B:%.*]]) #[[ATTR3]] personality i8* bitcast (i32 (...)* @esfp to i8*) { +; IS__CGSCC_NPM-NEXT: entry: +; IS__CGSCC_NPM-NEXT: invoke void @use2nonnull(i8* nonnull [[A]], i8* nonnull [[B]]) +; IS__CGSCC_NPM-NEXT: to label [[CONT:%.*]] unwind label [[EXC:%.*]] +; IS__CGSCC_NPM: cont: +; IS__CGSCC_NPM-NEXT: ret i1 false +; IS__CGSCC_NPM: exc: +; IS__CGSCC_NPM-NEXT: [[LP:%.*]] = landingpad { i8*, i32 } +; IS__CGSCC_NPM-NEXT: filter [0 x i8*] zeroinitializer +; IS__CGSCC_NPM-NEXT: unreachable ; entry: @@ -772,11 +972,17 @@ define i32* @gep1(i32* %p) { define i32* @gep1_no_null_opt(i32* %p) #0 { ; Should't be able to derive nonnull based on gep. -; CHECK: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@gep1_no_null_opt -; CHECK-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR7:[0-9]+]] { -; CHECK-NEXT: [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1 -; CHECK-NEXT: ret i32* [[Q]] +; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@gep1_no_null_opt +; NOT_CGSCC_NPM-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR8:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1 +; NOT_CGSCC_NPM-NEXT: ret i32* [[Q]] +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@gep1_no_null_opt +; IS__CGSCC_NPM-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR7:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1 +; IS__CGSCC_NPM-NEXT: ret i32* [[Q]] ; %q = getelementptr inbounds i32, i32* %p, i32 1 ret i32* %q @@ -825,11 +1031,17 @@ define i32* @g1() { declare void @use_i32_ptr(i32* readnone nocapture) nounwind define internal void @called_by_weak(i32* %a) { -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@called_by_weak -; CHECK-SAME: (i32* noalias nocapture nonnull readnone [[A:%.*]]) #[[ATTR3]] { -; CHECK-NEXT: call void @use_i32_ptr(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@called_by_weak +; NOT_CGSCC_NPM-SAME: (i32* noalias nocapture nonnull readnone [[A:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@called_by_weak +; IS__CGSCC_NPM-SAME: (i32* noalias nocapture nonnull readnone [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; call void @use_i32_ptr(i32* %a) ret void @@ -838,10 +1050,15 @@ define internal void @called_by_weak(i32* %a) { ; Check we do not annotate the function interface of this weak function. define weak_odr void @weak_caller(i32* nonnull %a) { ; -; CHECK-LABEL: define {{[^@]+}}@weak_caller -; CHECK-SAME: (i32* nonnull [[A:%.*]]) { -; CHECK-NEXT: call void @called_by_weak(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@weak_caller +; NOT_CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]]) { +; NOT_CGSCC_NPM-NEXT: call void @called_by_weak(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@weak_caller +; IS__CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]]) { +; IS__CGSCC_NPM-NEXT: call void @called_by_weak(i32* noalias nocapture nonnull readnone [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; call void @called_by_weak(i32* %a) ret void @@ -849,22 +1066,34 @@ define weak_odr void @weak_caller(i32* nonnull %a) { ; Expect nonnull define internal void @control(i32* dereferenceable(4) %a) { -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@control -; CHECK-SAME: (i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A:%.*]]) #[[ATTR3]] { -; CHECK-NEXT: call void @use_i32_ptr(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: nounwind +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@control +; NOT_CGSCC_NPM-SAME: (i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A:%.*]]) #[[ATTR4]] { +; NOT_CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@control +; IS__CGSCC_NPM-SAME: (i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A:%.*]]) #[[ATTR3]] { +; IS__CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; call void @use_i32_ptr(i32* %a) ret void } ; Avoid nonnull as we do not touch naked functions define internal void @naked(i32* dereferenceable(4) %a) naked { -; CHECK: Function Attrs: naked -; CHECK-LABEL: define {{[^@]+}}@naked -; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR8:[0-9]+]] { -; CHECK-NEXT: call void @use_i32_ptr(i32* [[A]]) -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: naked +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@naked +; NOT_CGSCC_NPM-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* [[A]]) +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: naked +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@naked +; IS__CGSCC_NPM-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR8:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* [[A]]) +; IS__CGSCC_NPM-NEXT: ret void ; call void @use_i32_ptr(i32* %a) ret void @@ -872,22 +1101,35 @@ define internal void @naked(i32* dereferenceable(4) %a) naked { ; Avoid nonnull as we do not touch optnone define internal void @optnone(i32* dereferenceable(4) %a) optnone noinline { ; -; CHECK: Function Attrs: noinline optnone -; CHECK-LABEL: define {{[^@]+}}@optnone -; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { -; CHECK-NEXT: call void @use_i32_ptr(i32* [[A]]) -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM: Function Attrs: noinline optnone +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@optnone +; NOT_CGSCC_NPM-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR10:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* [[A]]) +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM: Function Attrs: noinline optnone +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@optnone +; IS__CGSCC_NPM-SAME: (i32* dereferenceable(4) [[A:%.*]]) #[[ATTR9:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: call void @use_i32_ptr(i32* [[A]]) +; IS__CGSCC_NPM-NEXT: ret void ; call void @use_i32_ptr(i32* %a) ret void } define void @make_live(i32* nonnull dereferenceable(8) %a) { -; CHECK-LABEL: define {{[^@]+}}@make_live -; CHECK-SAME: (i32* noundef nonnull align 16 dereferenceable(8) [[A:%.*]]) { -; CHECK-NEXT: call void @naked(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) -; CHECK-NEXT: call void @control(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR3]] -; CHECK-NEXT: call void @optnone(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@make_live +; NOT_CGSCC_NPM-SAME: (i32* noundef nonnull align 16 dereferenceable(8) [[A:%.*]]) { +; NOT_CGSCC_NPM-NEXT: call void @naked(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) +; NOT_CGSCC_NPM-NEXT: call void @control(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: call void @optnone(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@make_live +; IS__CGSCC_NPM-SAME: (i32* noundef nonnull align 16 dereferenceable(8) [[A:%.*]]) { +; IS__CGSCC_NPM-NEXT: call void @naked(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) +; IS__CGSCC_NPM-NEXT: call void @control(i32* noalias nocapture noundef nonnull readnone align 16 dereferenceable(8) [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: call void @optnone(i32* noundef nonnull align 16 dereferenceable(8) [[A]]) +; IS__CGSCC_NPM-NEXT: ret void ; call void @naked(i32* nonnull dereferenceable(8) align 16 %a) call void @control(i32* nonnull dereferenceable(8) align 16 %a) @@ -908,35 +1150,51 @@ define i32 @nonnull_exec_ctx_1(i32* %a, i32 %b) { ; ; IS________OPM: Function Attrs: nounwind ; IS________OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1 -; IS________OPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR3]] { +; IS________OPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR4]] { ; IS________OPM-NEXT: en: ; IS________OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS________OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] ; IS________OPM: ex: -; IS________OPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] +; IS________OPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR4]] ; IS________OPM-NEXT: ret i32 [[TMP5]] ; IS________OPM: hd: ; IS________OPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] -; IS________OPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR3]] +; IS________OPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR4]] ; IS________OPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 ; IS________OPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] ; IS________OPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; -; IS________NPM: Function Attrs: nounwind willreturn -; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1 -; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { -; IS________NPM-NEXT: en: -; IS________NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 -; IS________NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] -; IS________NPM: ex: -; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR5]] -; IS________NPM-NEXT: ret i32 [[TMP5]] -; IS________NPM: hd: -; IS________NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] -; IS________NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR5]] -; IS________NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 -; IS________NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] -; IS________NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; IS__TUNIT_NPM: Function Attrs: nounwind willreturn +; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1 +; IS__TUNIT_NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR6]] { +; IS__TUNIT_NPM-NEXT: en: +; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__TUNIT_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__TUNIT_NPM: ex: +; IS__TUNIT_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR6]] +; IS__TUNIT_NPM-NEXT: ret i32 [[TMP5]] +; IS__TUNIT_NPM: hd: +; IS__TUNIT_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] +; IS__TUNIT_NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR6]] +; IS__TUNIT_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__TUNIT_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__TUNIT_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1 +; IS__CGSCC_NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: en: +; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__CGSCC_NPM: ex: +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; IS__CGSCC_NPM: hd: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] +; IS__CGSCC_NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; en: %tmp3 = icmp eq i32 %b, 0 @@ -958,39 +1216,57 @@ define i32 @nonnull_exec_ctx_1b(i32* %a, i32 %b) { ; ; IS________OPM: Function Attrs: nounwind ; IS________OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b -; IS________OPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR3]] { +; IS________OPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR4]] { ; IS________OPM-NEXT: en: ; IS________OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS________OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] ; IS________OPM: ex: -; IS________OPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] +; IS________OPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR4]] ; IS________OPM-NEXT: ret i32 [[TMP5]] ; IS________OPM: hd: ; IS________OPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] -; IS________OPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR3]] +; IS________OPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR4]] ; IS________OPM-NEXT: br label [[HD2]] ; IS________OPM: hd2: ; IS________OPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 ; IS________OPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] ; IS________OPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; -; IS________NPM: Function Attrs: nounwind willreturn -; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b -; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { -; IS________NPM-NEXT: en: -; IS________NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 -; IS________NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] -; IS________NPM: ex: -; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR5]] -; IS________NPM-NEXT: ret i32 [[TMP5]] -; IS________NPM: hd: -; IS________NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] -; IS________NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR5]] -; IS________NPM-NEXT: br label [[HD2]] -; IS________NPM: hd2: -; IS________NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 -; IS________NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] -; IS________NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; IS__TUNIT_NPM: Function Attrs: nounwind willreturn +; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b +; IS__TUNIT_NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR6]] { +; IS__TUNIT_NPM-NEXT: en: +; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__TUNIT_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__TUNIT_NPM: ex: +; IS__TUNIT_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR6]] +; IS__TUNIT_NPM-NEXT: ret i32 [[TMP5]] +; IS__TUNIT_NPM: hd: +; IS__TUNIT_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] +; IS__TUNIT_NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR6]] +; IS__TUNIT_NPM-NEXT: br label [[HD2]] +; IS__TUNIT_NPM: hd2: +; IS__TUNIT_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__TUNIT_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__TUNIT_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b +; IS__CGSCC_NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: en: +; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__CGSCC_NPM: ex: +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; IS__CGSCC_NPM: hd: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] +; IS__CGSCC_NPM-NEXT: tail call void @h(i32* [[A]]) #[[ATTR5]] +; IS__CGSCC_NPM-NEXT: br label [[HD2]] +; IS__CGSCC_NPM: hd2: +; IS__CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; en: %tmp3 = icmp eq i32 %b, 0 @@ -1013,21 +1289,37 @@ hd2: define i32 @nonnull_exec_ctx_2(i32* %a, i32 %b) willreturn nounwind { ; -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2 -; CHECK-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { -; CHECK-NEXT: en: -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 -; CHECK-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] -; CHECK: ex: -; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] -; CHECK-NEXT: ret i32 [[TMP5]] -; CHECK: hd: -; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] -; CHECK-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR3]] -; CHECK-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 -; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] -; CHECK-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; NOT_CGSCC_NPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2 +; NOT_CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR6]] { +; NOT_CGSCC_NPM-NEXT: en: +; NOT_CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; NOT_CGSCC_NPM: ex: +; NOT_CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; NOT_CGSCC_NPM: hd: +; NOT_CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] +; NOT_CGSCC_NPM-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; NOT_CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2 +; IS__CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: en: +; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__CGSCC_NPM: ex: +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; IS__CGSCC_NPM: hd: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] +; IS__CGSCC_NPM-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; en: %tmp3 = icmp eq i32 %b, 0 @@ -1047,23 +1339,41 @@ hd: define i32 @nonnull_exec_ctx_2b(i32* %a, i32 %b) willreturn nounwind { ; -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b -; CHECK-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { -; CHECK-NEXT: en: -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 -; CHECK-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] -; CHECK: ex: -; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] -; CHECK-NEXT: ret i32 [[TMP5]] -; CHECK: hd: -; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] -; CHECK-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR3]] -; CHECK-NEXT: br label [[HD2]] -; CHECK: hd2: -; CHECK-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 -; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] -; CHECK-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; NOT_CGSCC_NPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b +; NOT_CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR6]] { +; NOT_CGSCC_NPM-NEXT: en: +; NOT_CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; NOT_CGSCC_NPM: ex: +; NOT_CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; NOT_CGSCC_NPM: hd: +; NOT_CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] +; NOT_CGSCC_NPM-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: br label [[HD2]] +; NOT_CGSCC_NPM: hd2: +; NOT_CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; NOT_CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; NOT_CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] +; +; IS__CGSCC_NPM: Function Attrs: nounwind willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b +; IS__CGSCC_NPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) #[[ATTR5]] { +; IS__CGSCC_NPM-NEXT: en: +; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 +; IS__CGSCC_NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] +; IS__CGSCC_NPM: ex: +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret i32 [[TMP5]] +; IS__CGSCC_NPM: hd: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] +; IS__CGSCC_NPM-NEXT: tail call void @h(i32* nonnull [[A]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: br label [[HD2]] +; IS__CGSCC_NPM: hd2: +; IS__CGSCC_NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 +; IS__CGSCC_NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] +; IS__CGSCC_NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] ; en: %tmp3 = icmp eq i32 %b, 0 @@ -1200,14 +1510,23 @@ declare i8* @strrchr(i8* %0, i32 %1) nofree nounwind readonly willreturn ; We should not mark the return of @strrchr as `nonnull`, it may well be NULL! define i8* @mybasename(i8* nofree readonly %str) { -; CHECK: Function Attrs: nofree nounwind readonly willreturn -; CHECK-LABEL: define {{[^@]+}}@mybasename -; CHECK-SAME: (i8* nofree readonly [[STR:%.*]]) #[[ATTR10:[0-9]+]] { -; CHECK-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) #[[ATTR13]] -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null -; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1 -; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]] -; CHECK-NEXT: ret i8* [[COND]] +; NOT_CGSCC_NPM: Function Attrs: nofree nounwind readonly willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@mybasename +; NOT_CGSCC_NPM-SAME: (i8* nofree readonly [[STR:%.*]]) #[[ATTR11:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) #[[ATTR14]] +; NOT_CGSCC_NPM-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null +; NOT_CGSCC_NPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1 +; NOT_CGSCC_NPM-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]] +; NOT_CGSCC_NPM-NEXT: ret i8* [[COND]] +; +; IS__CGSCC_NPM: Function Attrs: nofree nounwind readonly willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@mybasename +; IS__CGSCC_NPM-SAME: (i8* nofree readonly [[STR:%.*]]) #[[ATTR10:[0-9]+]] { +; IS__CGSCC_NPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) #[[ATTR13]] +; IS__CGSCC_NPM-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null +; IS__CGSCC_NPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1 +; IS__CGSCC_NPM-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]] +; IS__CGSCC_NPM-NEXT: ret i8* [[COND]] ; %call = call i8* @strrchr(i8* %str, i32 47) %tobool = icmp ne i8* %call, null @@ -1224,12 +1543,19 @@ define void @nonnull_assume_pos(i8* %arg) { ; ATTRIBUTOR-NEXT: [[TMP1:%.*]] = call i8* @unknown() ; ATTRIBUTOR-NEXT: ret void ; -; CHECK-LABEL: define {{[^@]+}}@nonnull_assume_pos -; CHECK-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) { -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "nonnull"(i8* [[ARG]]) ] -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8* @unknown() -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_assume_pos +; NOT_CGSCC_NPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) { +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR12]] [ "nonnull"(i8* [[ARG]]) ] +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_assume_pos +; IS__CGSCC_NPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) { +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR11]] [ "nonnull"(i8* [[ARG]]) ] +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() +; IS__CGSCC_NPM-NEXT: ret void ; call void @llvm.assume(i1 true) ["nonnull"(i8* %arg)] call void @use_i8_ptr(i8* %arg) @@ -1250,17 +1576,29 @@ define void @nonnull_assume_neg(i8* %arg) { ; ATTRIBUTOR-NEXT: ret void ; ; -; CHECK-LABEL: define {{[^@]+}}@nonnull_assume_neg -; CHECK-SAME: (i8* nocapture nofree readnone [[ARG:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = call i8* @unknown() -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[ARG]]) #[[ATTR3]] -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] -; CHECK-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] -; CHECK-NEXT: [[TMP2:%.*]] = call i8* @unknown() -; CHECK-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] -; CHECK-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] -; CHECK-NEXT: ret void +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_assume_neg +; NOT_CGSCC_NPM-SAME: (i8* nocapture nofree readnone [[ARG:%.*]]) { +; NOT_CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[ARG]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: [[TMP2:%.*]] = call i8* @unknown() +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] +; NOT_CGSCC_NPM-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR4]] +; NOT_CGSCC_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@nonnull_assume_neg +; IS__CGSCC_NPM-SAME: (i8* nocapture nofree readnone [[ARG:%.*]]) { +; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree readnone [[ARG]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = call i8* @unknown() +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG]]) ] +; IS__CGSCC_NPM-NEXT: call void @use_i8_ptr_ret(i8* noalias nocapture nofree nonnull readnone [[ARG]]) #[[ATTR3]] +; IS__CGSCC_NPM-NEXT: ret void ; call i8* @unknown() call void @use_i8_ptr(i8* %arg) @@ -1312,18 +1650,34 @@ declare void @nonnull_callee(i8* nonnull %p) attributes #0 = { null_pointer_is_valid } attributes #1 = { nounwind willreturn} ;. -; CHECK: attributes #[[ATTR0]] = { inaccessiblememonly nofree nosync nounwind willreturn } -; CHECK: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } -; CHECK: attributes #[[ATTR2]] = { noreturn } -; CHECK: attributes #[[ATTR3]] = { nounwind } -; CHECK: attributes #[[ATTR4]] = { argmemonly nofree nosync nounwind readonly } -; CHECK: attributes #[[ATTR5]] = { nounwind willreturn } -; CHECK: attributes #[[ATTR6:[0-9]+]] = { nounwind readonly willreturn } -; CHECK: attributes #[[ATTR7]] = { nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn } -; CHECK: attributes #[[ATTR8]] = { naked } -; CHECK: attributes #[[ATTR9]] = { noinline optnone } -; CHECK: attributes #[[ATTR10]] = { nofree nounwind readonly willreturn } -; CHECK: attributes #[[ATTR11]] = { willreturn } -; CHECK: attributes #[[ATTR12]] = { nofree nosync nounwind readonly } -; CHECK: attributes #[[ATTR13]] = { readonly willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR0]] = { inaccessiblememonly nofree nosync nounwind willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR2]] = { nofree nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR3]] = { noreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR4]] = { nounwind } +; NOT_CGSCC_NPM: attributes #[[ATTR5]] = { argmemonly nofree nosync nounwind readonly } +; NOT_CGSCC_NPM: attributes #[[ATTR6]] = { nounwind willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR7:[0-9]+]] = { nounwind readonly willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR8]] = { nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR9]] = { naked } +; NOT_CGSCC_NPM: attributes #[[ATTR10]] = { noinline optnone } +; NOT_CGSCC_NPM: attributes #[[ATTR11]] = { nofree nounwind readonly willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR12]] = { willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR13]] = { nofree nosync nounwind readonly } +; NOT_CGSCC_NPM: attributes #[[ATTR14]] = { readonly willreturn } +;. +; IS__CGSCC_NPM: attributes #[[ATTR0]] = { inaccessiblememonly nofree nosync nounwind willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR2]] = { noreturn } +; IS__CGSCC_NPM: attributes #[[ATTR3]] = { nounwind } +; IS__CGSCC_NPM: attributes #[[ATTR4]] = { argmemonly nofree nosync nounwind readonly } +; IS__CGSCC_NPM: attributes #[[ATTR5]] = { nounwind willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR6:[0-9]+]] = { nounwind readonly willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR7]] = { nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR8]] = { naked } +; IS__CGSCC_NPM: attributes #[[ATTR9]] = { noinline optnone } +; IS__CGSCC_NPM: attributes #[[ATTR10]] = { nofree nounwind readonly willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR11]] = { willreturn } +; IS__CGSCC_NPM: attributes #[[ATTR12]] = { nofree nosync nounwind readonly } +; IS__CGSCC_NPM: attributes #[[ATTR13]] = { readonly willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/norecurse.ll b/llvm/test/Transforms/Attributor/norecurse.ll index 23ca0c987f868..61bba0a6044ed 100644 --- a/llvm/test/Transforms/Attributor/norecurse.ll +++ b/llvm/test/Transforms/Attributor/norecurse.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -14,9 +14,9 @@ define i32 @leaf() { } define i32 @self_rec() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@self_rec -; CHECK-SAME: () #[[ATTR0]] { +; CHECK-SAME: () #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: ret i32 4 ; %a = call i32 @self_rec() @@ -24,19 +24,29 @@ define i32 @self_rec() { } define i32 @indirect_rec() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@indirect_rec -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32 undef +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@indirect_rec +; NOT_CGSCC_NPM-SAME: () #[[ATTR1]] { +; NOT_CGSCC_NPM-NEXT: ret i32 undef +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@indirect_rec +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32 undef ; %a = call i32 @indirect_rec2() ret i32 %a } define i32 @indirect_rec2() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@indirect_rec2 -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32 undef +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@indirect_rec2 +; NOT_CGSCC_NPM-SAME: () #[[ATTR1]] { +; NOT_CGSCC_NPM-NEXT: ret i32 undef +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@indirect_rec2 +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32 undef ; %a = call i32 @indirect_rec() ret i32 %a @@ -45,7 +55,7 @@ define i32 @indirect_rec2() { define i32 @extern() { ; CHECK: Function Attrs: nosync readnone ; CHECK-LABEL: define {{[^@]+}}@extern -; CHECK-SAME: () #[[ATTR1:[0-9]+]] { +; CHECK-SAME: () #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: [[A:%.*]] = call i32 @k() ; CHECK-NEXT: ret i32 [[A]] ; @@ -60,8 +70,8 @@ declare i32 @k() readnone define void @intrinsic(i8* %dest, i8* %src, i32 %len) { ; CHECK: Function Attrs: argmemonly nofree nosync nounwind willreturn ; CHECK-LABEL: define {{[^@]+}}@intrinsic -; CHECK-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) #[[ATTR3:[0-9]+]] { -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) #[[ATTR7:[0-9]+]] +; CHECK-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) #[[ATTR4:[0-9]+]] { +; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) #[[ATTR8:[0-9]+]] ; CHECK-NEXT: ret void ; call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false) @@ -75,7 +85,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1) define internal i32 @called_by_norecurse() { ; CHECK: Function Attrs: norecurse nosync readnone ; CHECK-LABEL: define {{[^@]+}}@called_by_norecurse -; CHECK-SAME: () #[[ATTR5:[0-9]+]] { +; CHECK-SAME: () #[[ATTR6:[0-9]+]] { ; CHECK-NEXT: [[A:%.*]] = call i32 @k() ; CHECK-NEXT: ret i32 undef ; @@ -85,13 +95,13 @@ define internal i32 @called_by_norecurse() { define void @m() norecurse { ; IS__TUNIT____: Function Attrs: norecurse nosync readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@m -; IS__TUNIT____-SAME: () #[[ATTR5]] { -; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse() #[[ATTR1]] +; IS__TUNIT____-SAME: () #[[ATTR6]] { +; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse() #[[ATTR2]] ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@m -; IS__CGSCC____-SAME: () #[[ATTR5]] { +; IS__CGSCC____-SAME: () #[[ATTR6]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse() ; IS__CGSCC____-NEXT: ret void ; @@ -102,7 +112,7 @@ define void @m() norecurse { define internal i32 @called_by_norecurse_indirectly() { ; CHECK: Function Attrs: norecurse nosync readnone ; CHECK-LABEL: define {{[^@]+}}@called_by_norecurse_indirectly -; CHECK-SAME: () #[[ATTR5]] { +; CHECK-SAME: () #[[ATTR6]] { ; CHECK-NEXT: [[A:%.*]] = call i32 @k() ; CHECK-NEXT: ret i32 [[A]] ; @@ -112,13 +122,13 @@ define internal i32 @called_by_norecurse_indirectly() { define internal i32 @o() { ; IS__TUNIT____: Function Attrs: norecurse nosync readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@o -; IS__TUNIT____-SAME: () #[[ATTR5]] { -; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse_indirectly() #[[ATTR1]] +; IS__TUNIT____-SAME: () #[[ATTR6]] { +; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse_indirectly() #[[ATTR2]] ; IS__TUNIT____-NEXT: ret i32 [[A]] ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@o -; IS__CGSCC____-SAME: () #[[ATTR5]] { +; IS__CGSCC____-SAME: () #[[ATTR6]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse_indirectly() ; IS__CGSCC____-NEXT: ret i32 [[A]] ; @@ -128,13 +138,13 @@ define internal i32 @o() { define i32 @p() norecurse { ; IS__TUNIT____: Function Attrs: norecurse nosync readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@p -; IS__TUNIT____-SAME: () #[[ATTR5]] { -; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @o() #[[ATTR1]] +; IS__TUNIT____-SAME: () #[[ATTR6]] { +; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @o() #[[ATTR2]] ; IS__TUNIT____-NEXT: ret i32 [[A]] ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@p -; IS__CGSCC____-SAME: () #[[ATTR5]] { +; IS__CGSCC____-SAME: () #[[ATTR6]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @o() ; IS__CGSCC____-NEXT: ret i32 [[A]] ; @@ -143,9 +153,9 @@ define i32 @p() norecurse { } define void @f(i32 %x) { -; NOT_CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@f -; NOT_CGSCC_NPM-SAME: (i32 [[X:%.*]]) #[[ATTR0]] { +; NOT_CGSCC_NPM-SAME: (i32 [[X:%.*]]) #[[ATTR1]] { ; NOT_CGSCC_NPM-NEXT: entry: ; NOT_CGSCC_NPM-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 ; NOT_CGSCC_NPM-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 @@ -216,7 +226,7 @@ define i32 @eval_func1(i32 (i32)* , i32) local_unnamed_addr { define i32 @eval_func2(i32 (i32)* , i32) local_unnamed_addr null_pointer_is_valid{ ; CHECK: Function Attrs: null_pointer_is_valid ; CHECK-LABEL: define {{[^@]+}}@eval_func2 -; CHECK-SAME: (i32 (i32)* nocapture nofree noundef [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr #[[ATTR6:[0-9]+]] { +; CHECK-SAME: (i32 (i32)* nocapture nofree noundef [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr #[[ATTR7:[0-9]+]] { ; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 [[TMP0]](i32 [[TMP1]]) ; CHECK-NEXT: ret i32 [[TMP3]] ; @@ -242,11 +252,12 @@ Dead: ;. ; CHECK: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } -; CHECK: attributes #[[ATTR1]] = { nosync readnone } -; CHECK: attributes #[[ATTR2:[0-9]+]] = { readnone } -; CHECK: attributes #[[ATTR3]] = { argmemonly nofree nosync nounwind willreturn } -; CHECK: attributes #[[ATTR4:[0-9]+]] = { argmemonly nofree nounwind willreturn } -; CHECK: attributes #[[ATTR5]] = { norecurse nosync readnone } -; CHECK: attributes #[[ATTR6]] = { null_pointer_is_valid } -; CHECK: attributes #[[ATTR7]] = { willreturn } +; CHECK: attributes #[[ATTR1]] = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #[[ATTR2]] = { nosync readnone } +; CHECK: attributes #[[ATTR3:[0-9]+]] = { readnone } +; CHECK: attributes #[[ATTR4]] = { argmemonly nofree nosync nounwind willreturn } +; CHECK: attributes #[[ATTR5:[0-9]+]] = { argmemonly nofree nounwind willreturn } +; CHECK: attributes #[[ATTR6]] = { norecurse nosync readnone } +; CHECK: attributes #[[ATTR7]] = { null_pointer_is_valid } +; CHECK: attributes #[[ATTR8]] = { willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/noreturn.ll b/llvm/test/Transforms/Attributor/noreturn.ll index 5b35208683dd7..dfe40db52288f 100644 --- a/llvm/test/Transforms/Attributor/noreturn.ll +++ b/llvm/test/Transforms/Attributor/noreturn.ll @@ -17,7 +17,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; } ; define void @srec0() #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; CHECK: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@srec0 ; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: @@ -36,7 +36,7 @@ entry: ; } ; define i32 @srec16(i32 %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse noreturn nosync nounwind readnone uwtable willreturn +; CHECK: Function Attrs: nofree noinline noreturn nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@srec16 ; CHECK-SAME: (i32 [[A:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: entry: @@ -130,7 +130,7 @@ return: ; No predecessors! define i32 @multiple_noreturn_calls(i32 %a) #0 { ; CHECK: Function Attrs: nofree noinline norecurse noreturn nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@multiple_noreturn_calls -; CHECK-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { +; CHECK-SAME: (i32 [[A:%.*]]) #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 0 ; CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -165,7 +165,7 @@ cond.end: ; preds = %cond.false, %cond.t define i32 @endless_loop_but_willreturn() willreturn { ; CHECK: Function Attrs: nofree norecurse noreturn nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@endless_loop_but_willreturn -; CHECK-SAME: () #[[ATTR3:[0-9]+]] { +; CHECK-SAME: () #[[ATTR4:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[WHILE_BODY:%.*]] ; CHECK: while.body: @@ -182,7 +182,7 @@ while.body: ; preds = %entry, %while.body define i32 @UB_and_willreturn() willreturn { ; CHECK: Function Attrs: nofree norecurse noreturn nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@UB_and_willreturn -; CHECK-SAME: () #[[ATTR3]] { +; CHECK-SAME: () #[[ATTR4]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: unreachable ; @@ -192,8 +192,9 @@ entry: attributes #0 = { noinline nounwind uwtable } ;. -; CHECK: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; CHECK: attributes #[[ATTR1]] = { nofree noinline norecurse noreturn nosync nounwind readnone uwtable willreturn } +; CHECK: attributes #[[ATTR0]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; CHECK: attributes #[[ATTR1]] = { nofree noinline noreturn nosync nounwind readnone uwtable willreturn } ; CHECK: attributes #[[ATTR2]] = { nofree noinline norecurse noreturn nosync nounwind readnone uwtable } -; CHECK: attributes #[[ATTR3]] = { nofree norecurse noreturn nosync nounwind readnone willreturn } +; CHECK: attributes #[[ATTR3]] = { nofree noinline norecurse noreturn nosync nounwind readnone uwtable willreturn } +; CHECK: attributes #[[ATTR4]] = { nofree norecurse noreturn nosync nounwind readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/nosync.ll b/llvm/test/Transforms/Attributor/nosync.ll index c7e794776f0b6..0226e00bfb2a0 100644 --- a/llvm/test/Transforms/Attributor/nosync.ll +++ b/llvm/test/Transforms/Attributor/nosync.ll @@ -204,21 +204,21 @@ define i32 @scc1(i32* %0) noinline nounwind uwtable { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline nounwind uwtable ; IS__TUNIT____-LABEL: define {{[^@]+}}@scc1 ; IS__TUNIT____-SAME: (i32* nofree [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { -; IS__TUNIT____-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR19:[0-9]+]] -; IS__TUNIT____-NEXT: [[VAL:%.*]] = tail call i32 @volatile_load(i32* nofree align 4 [[TMP0]]) #[[ATTR19]] +; IS__TUNIT____-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR18:[0-9]+]] +; IS__TUNIT____-NEXT: [[VAL:%.*]] = tail call i32 @volatile_load(i32* nofree align 4 [[TMP0]]) #[[ATTR18]] ; IS__TUNIT____-NEXT: ret i32 [[VAL]] ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree noinline nounwind uwtable ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@scc1 ; IS__CGSCC_OPM-SAME: (i32* nofree [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { -; IS__CGSCC_OPM-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR19:[0-9]+]] -; IS__CGSCC_OPM-NEXT: [[VAL:%.*]] = tail call i32 @volatile_load(i32* nofree noundef align 4 [[TMP0]]) #[[ATTR20:[0-9]+]] +; IS__CGSCC_OPM-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR18:[0-9]+]] +; IS__CGSCC_OPM-NEXT: [[VAL:%.*]] = tail call i32 @volatile_load(i32* nofree noundef align 4 [[TMP0]]) #[[ATTR19:[0-9]+]] ; IS__CGSCC_OPM-NEXT: ret i32 [[VAL]] ; ; IS__CGSCC_NPM: Function Attrs: argmemonly nofree noinline nounwind uwtable ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@scc1 ; IS__CGSCC_NPM-SAME: (i32* nofree [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { -; IS__CGSCC_NPM-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR19:[0-9]+]] +; IS__CGSCC_NPM-NEXT: tail call void @scc2(i32* nofree [[TMP0]]) #[[ATTR18:[0-9]+]] ; IS__CGSCC_NPM-NEXT: [[VAL:%.*]] = tail call i32 @volatile_load(i32* nofree noundef align 4 [[TMP0]]) #[[ATTR14:[0-9]+]] ; IS__CGSCC_NPM-NEXT: ret i32 [[VAL]] ; @@ -231,7 +231,7 @@ define void @scc2(i32* %0) noinline nounwind uwtable { ; CHECK: Function Attrs: argmemonly nofree noinline nounwind uwtable ; CHECK-LABEL: define {{[^@]+}}@scc2 ; CHECK-SAME: (i32* nofree [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] { -; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @scc1(i32* nofree [[TMP0]]) #[[ATTR19:[0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @scc1(i32* nofree [[TMP0]]) #[[ATTR18:[0-9]+]] ; CHECK-NEXT: ret void ; tail call i32 @scc1(i32* %0); @@ -361,13 +361,13 @@ define i32 @memcpy_volatile(i8* %ptr1, i8* %ptr2) { ; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@memcpy_volatile ; NOT_CGSCC_OPM-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) #[[ATTR10:[0-9]+]] { -; NOT_CGSCC_OPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) #[[ATTR20:[0-9]+]] +; NOT_CGSCC_OPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) #[[ATTR19:[0-9]+]] ; NOT_CGSCC_OPM-NEXT: ret i32 4 ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@memcpy_volatile ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) #[[ATTR10:[0-9]+]] { -; IS__CGSCC_OPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) #[[ATTR21:[0-9]+]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) #[[ATTR20:[0-9]+]] ; IS__CGSCC_OPM-NEXT: ret i32 4 ; call void @llvm.memcpy(i8* %ptr1, i8* %ptr2, i32 8, i1 1) @@ -382,13 +382,13 @@ define i32 @memset_non_volatile(i8* %ptr1, i8 %val) { ; NOT_CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@memset_non_volatile ; NOT_CGSCC_OPM-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) #[[ATTR11:[0-9]+]] { -; NOT_CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) #[[ATTR21:[0-9]+]] +; NOT_CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) #[[ATTR20:[0-9]+]] ; NOT_CGSCC_OPM-NEXT: ret i32 4 ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@memset_non_volatile ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) #[[ATTR11:[0-9]+]] { -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) #[[ATTR22:[0-9]+]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) #[[ATTR21:[0-9]+]] ; IS__CGSCC_OPM-NEXT: ret i32 4 ; call void @llvm.memset(i8* %ptr1, i8 %val, i32 8, i1 0) @@ -444,7 +444,7 @@ declare float @llvm.cos(float %val) readnone ; TEST 19 - positive, readnone & non-convergent intrinsic. define i32 @cos_test(float %x) { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-LABEL: define {{[^@]+}}@cos_test ; CHECK-SAME: (float [[X:%.*]]) #[[ATTR15:[0-9]+]] { ; CHECK-NEXT: ret i32 4 @@ -456,14 +456,14 @@ define i32 @cos_test(float %x) { define float @cos_test2(float %x) { ; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@cos_test2 -; NOT_CGSCC_OPM-SAME: (float [[X:%.*]]) #[[ATTR16:[0-9]+]] { -; NOT_CGSCC_OPM-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) #[[ATTR22:[0-9]+]] +; NOT_CGSCC_OPM-SAME: (float [[X:%.*]]) #[[ATTR15]] { +; NOT_CGSCC_OPM-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) #[[ATTR21:[0-9]+]] ; NOT_CGSCC_OPM-NEXT: ret float [[C]] ; ; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@cos_test2 -; IS__CGSCC_OPM-SAME: (float [[X:%.*]]) #[[ATTR16:[0-9]+]] { -; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) #[[ATTR23:[0-9]+]] +; IS__CGSCC_OPM-SAME: (float [[X:%.*]]) #[[ATTR15]] { +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) #[[ATTR22:[0-9]+]] ; IS__CGSCC_OPM-NEXT: ret float [[C]] ; %c = call float @llvm.cos(float %x) @@ -485,14 +485,13 @@ define float @cos_test2(float %x) { ; NOT_CGSCC_OPM: attributes #[[ATTR12:[0-9]+]] = { convergent readnone } ; NOT_CGSCC_OPM: attributes #[[ATTR13]] = { readnone } ; NOT_CGSCC_OPM: attributes #[[ATTR14]] = { nounwind } -; NOT_CGSCC_OPM: attributes #[[ATTR15]] = { nofree norecurse nosync nounwind readnone willreturn } -; NOT_CGSCC_OPM: attributes #[[ATTR16]] = { nofree nosync nounwind readnone willreturn } -; NOT_CGSCC_OPM: attributes #[[ATTR17:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } -; NOT_CGSCC_OPM: attributes #[[ATTR18:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } -; NOT_CGSCC_OPM: attributes #[[ATTR19]] = { nofree nounwind } -; NOT_CGSCC_OPM: attributes #[[ATTR20]] = { willreturn } -; NOT_CGSCC_OPM: attributes #[[ATTR21]] = { willreturn writeonly } -; NOT_CGSCC_OPM: attributes #[[ATTR22]] = { readnone willreturn } +; NOT_CGSCC_OPM: attributes #[[ATTR15]] = { nofree nosync nounwind readnone willreturn } +; NOT_CGSCC_OPM: attributes #[[ATTR16:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } +; NOT_CGSCC_OPM: attributes #[[ATTR17:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } +; NOT_CGSCC_OPM: attributes #[[ATTR18]] = { nofree nounwind } +; NOT_CGSCC_OPM: attributes #[[ATTR19]] = { willreturn } +; NOT_CGSCC_OPM: attributes #[[ATTR20]] = { willreturn writeonly } +; NOT_CGSCC_OPM: attributes #[[ATTR21]] = { readnone willreturn } ;. ; IS__CGSCC_OPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind optsize readnone ssp uwtable willreturn } ; IS__CGSCC_OPM: attributes #[[ATTR1]] = { argmemonly nofree norecurse nosync nounwind uwtable willreturn } @@ -509,13 +508,12 @@ define float @cos_test2(float %x) { ; IS__CGSCC_OPM: attributes #[[ATTR12:[0-9]+]] = { convergent readnone } ; IS__CGSCC_OPM: attributes #[[ATTR13]] = { readnone } ; IS__CGSCC_OPM: attributes #[[ATTR14]] = { nounwind } -; IS__CGSCC_OPM: attributes #[[ATTR15]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR16]] = { nofree nosync nounwind readnone willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR17:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } -; IS__CGSCC_OPM: attributes #[[ATTR18:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR19]] = { nofree nounwind } -; IS__CGSCC_OPM: attributes #[[ATTR20]] = { nounwind willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR21]] = { willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR22]] = { willreturn writeonly } -; IS__CGSCC_OPM: attributes #[[ATTR23]] = { readnone willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR15]] = { nofree nosync nounwind readnone willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR16:[0-9]+]] = { argmemonly nofree nounwind willreturn writeonly } +; IS__CGSCC_OPM: attributes #[[ATTR17:[0-9]+]] = { nofree nosync nounwind readnone speculatable willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR18]] = { nofree nounwind } +; IS__CGSCC_OPM: attributes #[[ATTR19]] = { nounwind willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR20]] = { willreturn } +; IS__CGSCC_OPM: attributes #[[ATTR21]] = { willreturn writeonly } +; IS__CGSCC_OPM: attributes #[[ATTR22]] = { readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/nounwind.ll b/llvm/test/Transforms/Attributor/nounwind.ll index f3007d64d7e5c..51fd4df488402 100644 --- a/llvm/test/Transforms/Attributor/nounwind.ll +++ b/llvm/test/Transforms/Attributor/nounwind.ll @@ -16,10 +16,15 @@ define i32 @foo1() { ; TEST 2 define i32 @scc1_foo() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@scc1_foo -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32 1 +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@scc1_foo +; NOT_CGSCC_NPM-SAME: () #[[ATTR1:[0-9]+]] { +; NOT_CGSCC_NPM-NEXT: ret i32 1 +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@scc1_foo +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32 1 ; %1 = call i32 @scc1_bar() ret i32 1 @@ -28,10 +33,15 @@ define i32 @scc1_foo() { ; TEST 3 define i32 @scc1_bar() { -; CHECK: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@scc1_bar -; CHECK-SAME: () #[[ATTR0]] { -; CHECK-NEXT: ret i32 1 +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn +; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@scc1_bar +; NOT_CGSCC_NPM-SAME: () #[[ATTR1]] { +; NOT_CGSCC_NPM-NEXT: ret i32 1 +; +; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@scc1_bar +; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: ret i32 1 ; %1 = call i32 @scc1_foo() ret i32 1 @@ -133,5 +143,8 @@ declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() ;. -; CHECK: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } +; NOT_CGSCC_NPM: attributes #[[ATTR1]] = { nofree nosync nounwind readnone willreturn } +;. +; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/potential.ll b/llvm/test/Transforms/Attributor/potential.ll index 74317150f658f..7621329c97591 100644 --- a/llvm/test/Transforms/Attributor/potential.ll +++ b/llvm/test/Transforms/Attributor/potential.ll @@ -55,7 +55,6 @@ define internal i32 @call_with_two_values(i32 %c) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@call_with_two_values ; IS__CGSCC____-SAME: () #[[ATTR0]] { -; IS__CGSCC____-NEXT: [[RET:%.*]] = add i32 0, 0 ; IS__CGSCC____-NEXT: ret i32 undef ; %csret1 = call i32 @iszero2(i32 %c) @@ -104,7 +103,9 @@ define internal i32 @iszero3(i32 %c) { define internal i32 @less_than_two(i32 %c) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@less_than_two -; IS__CGSCC____-SAME: () #[[ATTR0]] { +; IS__CGSCC____-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { +; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp slt i32 undef, 2 +; IS__CGSCC____-NEXT: [[RET:%.*]] = zext i1 true to i32 ; IS__CGSCC____-NEXT: ret i32 undef ; %cmp = icmp slt i32 %c, 2 @@ -183,37 +184,21 @@ define i1 @potential_test6(i32 %c) { } define i1 @potential_test7(i32 %c) { -; IS__TUNIT_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@potential_test7 -; IS__TUNIT_OPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { -; IS__TUNIT_OPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR2]], !range [[RNG0]] -; IS__TUNIT_OPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR2]], !range [[RNG1:![0-9]+]] -; IS__TUNIT_OPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] -; IS__TUNIT_OPM-NEXT: ret i1 [[RET]] -; -; IS__TUNIT_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@potential_test7 -; IS__TUNIT_NPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { -; IS__TUNIT_NPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR1]], !range [[RNG0]] -; IS__TUNIT_NPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR1]], !range [[RNG1:![0-9]+]] -; IS__TUNIT_NPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] -; IS__TUNIT_NPM-NEXT: ret i1 [[RET]] -; -; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@potential_test7 -; IS__CGSCC_OPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { -; IS__CGSCC_OPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR2]], !range [[RNG0]] -; IS__CGSCC_OPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR3:[0-9]+]], !range [[RNG1:![0-9]+]] -; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] -; IS__CGSCC_OPM-NEXT: ret i1 [[RET]] -; -; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@potential_test7 -; IS__CGSCC_NPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { -; IS__CGSCC_NPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR1]], !range [[RNG0]] -; IS__CGSCC_NPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR2:[0-9]+]], !range [[RNG1:![0-9]+]] -; IS__CGSCC_NPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] -; IS__CGSCC_NPM-NEXT: ret i1 [[RET]] +; IS________OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS________OPM-LABEL: define {{[^@]+}}@potential_test7 +; IS________OPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { +; IS________OPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR2]], !range [[RNG0]] +; IS________OPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR2]], !range [[RNG1:![0-9]+]] +; IS________OPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] +; IS________OPM-NEXT: ret i1 [[RET]] +; +; IS________NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS________NPM-LABEL: define {{[^@]+}}@potential_test7 +; IS________NPM-SAME: (i32 [[C:%.*]]) #[[ATTR0]] { +; IS________NPM-NEXT: [[CSRET1:%.*]] = call i32 @return1or3(i32 [[C]]) #[[ATTR1]], !range [[RNG0]] +; IS________NPM-NEXT: [[CSRET2:%.*]] = call i32 @return3or4(i32 [[C]]) #[[ATTR1]], !range [[RNG1:![0-9]+]] +; IS________NPM-NEXT: [[RET:%.*]] = icmp eq i32 [[CSRET1]], [[CSRET2]] +; IS________NPM-NEXT: ret i1 [[RET]] ; %csret1 = call i32 @return1or3(i32 %c) %csret2 = call i32 @return3or4(i32 %c) @@ -582,29 +567,17 @@ define i32 @potential_test13_caller2() { } define i32 @potential_test13_caller3() { -; IS__TUNIT_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@potential_test13_caller3 -; IS__TUNIT_OPM-SAME: () #[[ATTR0]] { -; IS__TUNIT_OPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR2]], !range [[RNG2]] -; IS__TUNIT_OPM-NEXT: ret i32 [[RET]] -; -; IS__TUNIT_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@potential_test13_caller3 -; IS__TUNIT_NPM-SAME: () #[[ATTR0]] { -; IS__TUNIT_NPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR1]], !range [[RNG2]] -; IS__TUNIT_NPM-NEXT: ret i32 [[RET]] -; -; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@potential_test13_caller3 -; IS__CGSCC_OPM-SAME: () #[[ATTR0]] { -; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR3]], !range [[RNG2]] -; IS__CGSCC_OPM-NEXT: ret i32 [[RET]] -; -; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn -; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@potential_test13_caller3 -; IS__CGSCC_NPM-SAME: () #[[ATTR0]] { -; IS__CGSCC_NPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR2]], !range [[RNG2]] -; IS__CGSCC_NPM-NEXT: ret i32 [[RET]] +; IS________OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS________OPM-LABEL: define {{[^@]+}}@potential_test13_caller3 +; IS________OPM-SAME: () #[[ATTR0]] { +; IS________OPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR2]], !range [[RNG2]] +; IS________OPM-NEXT: ret i32 [[RET]] +; +; IS________NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn +; IS________NPM-LABEL: define {{[^@]+}}@potential_test13_caller3 +; IS________NPM-SAME: () #[[ATTR0]] { +; IS________NPM-NEXT: [[RET:%.*]] = call i32 @potential_test13_callee(i32 undef) #[[ATTR1]], !range [[RNG2]] +; IS________NPM-NEXT: ret i32 [[RET]] ; %ret = call i32 @potential_test13_callee(i32 undef) ret i32 %ret @@ -664,11 +637,9 @@ define i1 @potential_test16(i1 %c0, i1 %c1) { ; IS__CGSCC_OPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ; IS__CGSCC_OPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone } ; IS__CGSCC_OPM: attributes #[[ATTR2]] = { readnone willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR3]] = { nounwind readnone willreturn } ;. ; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ; IS__CGSCC_NPM: attributes #[[ATTR1]] = { readnone willreturn } -; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nounwind readnone willreturn } ;. ; CHECK: [[META0:![0-9]+]] = !{i32 1, i32 4} ; CHECK: [[META1:![0-9]+]] = !{i32 3, i32 5} diff --git a/llvm/test/Transforms/Attributor/range.ll b/llvm/test/Transforms/Attributor/range.ll index c4286251ca4b1..614571f060f80 100644 --- a/llvm/test/Transforms/Attributor/range.ll +++ b/llvm/test/Transforms/Attributor/range.ll @@ -1123,7 +1123,8 @@ define internal i32 @less_than_65536(i32 %arg) { define internal i1 @is_less_than_65536(i32 %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@is_less_than_65536 -; IS__CGSCC____-SAME: () #[[ATTR1]] { +; IS__CGSCC____-SAME: (i32 [[ARG:%.*]]) #[[ATTR1]] { +; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp ult i32 undef, 65536 ; IS__CGSCC____-NEXT: ret i1 undef ; %cmp = icmp ult i32 %arg, 65536 @@ -1315,7 +1316,8 @@ define internal i1 @is_less_than_100_2(i32 %c) { ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@is_less_than_100_2 -; IS__CGSCC____-SAME: () #[[ATTR1]] { +; IS__CGSCC____-SAME: (i32 [[C:%.*]]) #[[ATTR1]] { +; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp slt i32 undef, 100 ; IS__CGSCC____-NEXT: ret i1 undef ; %cmp = icmp slt i32 %c, 100 @@ -1354,17 +1356,17 @@ define internal i1 @non_zero(i8 %v) { ; Avoid range metadata for %l below define i1 @context(i8* %p) { -; IS__TUNIT_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@context -; IS__TUNIT_OPM-SAME: (i8* nocapture nofree noundef nonnull readonly dereferenceable(1) [[P:%.*]]) #[[ATTR0]] { -; IS__TUNIT_OPM-NEXT: [[L:%.*]] = load i8, i8* [[P]], align 1 -; IS__TUNIT_OPM-NEXT: [[C:%.*]] = icmp slt i8 0, [[L]] -; IS__TUNIT_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__TUNIT_OPM: t: -; IS__TUNIT_OPM-NEXT: [[R:%.*]] = call i1 @non_zero(i8 [[L]]) #[[ATTR5]] -; IS__TUNIT_OPM-NEXT: ret i1 [[R]] -; IS__TUNIT_OPM: f: -; IS__TUNIT_OPM-NEXT: ret i1 false +; IS________OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn +; IS________OPM-LABEL: define {{[^@]+}}@context +; IS________OPM-SAME: (i8* nocapture nofree noundef nonnull readonly dereferenceable(1) [[P:%.*]]) #[[ATTR0]] { +; IS________OPM-NEXT: [[L:%.*]] = load i8, i8* [[P]], align 1 +; IS________OPM-NEXT: [[C:%.*]] = icmp slt i8 0, [[L]] +; IS________OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; IS________OPM: t: +; IS________OPM-NEXT: [[R:%.*]] = call i1 @non_zero(i8 [[L]]) #[[ATTR5]] +; IS________OPM-NEXT: ret i1 [[R]] +; IS________OPM: f: +; IS________OPM-NEXT: ret i1 false ; ; IS________NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn ; IS________NPM-LABEL: define {{[^@]+}}@context @@ -1376,18 +1378,6 @@ define i1 @context(i8* %p) { ; IS________NPM-NEXT: ret i1 true ; IS________NPM: f: ; IS________NPM-NEXT: ret i1 false -; -; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn -; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@context -; IS__CGSCC_OPM-SAME: (i8* nocapture nofree noundef nonnull readonly dereferenceable(1) [[P:%.*]]) #[[ATTR0]] { -; IS__CGSCC_OPM-NEXT: [[L:%.*]] = load i8, i8* [[P]], align 1 -; IS__CGSCC_OPM-NEXT: [[C:%.*]] = icmp slt i8 0, [[L]] -; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS__CGSCC_OPM: t: -; IS__CGSCC_OPM-NEXT: [[R:%.*]] = call i1 @non_zero(i8 [[L]]) #[[ATTR6:[0-9]+]] -; IS__CGSCC_OPM-NEXT: ret i1 [[R]] -; IS__CGSCC_OPM: f: -; IS__CGSCC_OPM-NEXT: ret i1 false ; %l = load i8, i8* %p %c = icmp slt i8 0, %l @@ -1518,7 +1508,6 @@ declare void @barney(i32 signext, i32 signext) ; IS__CGSCC_OPM: attributes #[[ATTR3]] = { readonly willreturn } ; IS__CGSCC_OPM: attributes #[[ATTR4]] = { nounwind readnone } ; IS__CGSCC_OPM: attributes #[[ATTR5]] = { readnone willreturn } -; IS__CGSCC_OPM: attributes #[[ATTR6]] = { nounwind readnone willreturn } ;. ; IS__CGSCC_NPM: attributes #[[ATTR0]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } ; IS__CGSCC_NPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } diff --git a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll index d39af8c562851..2c8e29b007e51 100644 --- a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll +++ b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll @@ -296,7 +296,7 @@ define internal i32* @internal_ret1_rw(i32* %r0, i32* %w0) { ; IS__CGSCC____-NEXT: store i32 [[TMP1]], i32* [[W0]], align 4 ; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call i32* @internal_ret0_nw(i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0]], i32* nofree nonnull align 4 dereferenceable(4) [[W0]]) #[[ATTR3]] ; IS__CGSCC____-NEXT: [[CALL2:%.*]] = call i32* @internal_ret0_nw(i32* nofree nonnull align 4 dereferenceable(4) [[W0]], i32* nofree nonnull align 4 dereferenceable(4) [[W0]]) #[[ATTR3]] -; IS__CGSCC____-NEXT: [[CALL3:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[R0]], i32* nofree nonnull writeonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[W0]]) #[[ATTR4]] +; IS__CGSCC____-NEXT: [[CALL3:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[R0]], i32* nofree nonnull writeonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[W0]]) #[[ATTR5:[0-9]+]] ; IS__CGSCC____-NEXT: [[CALL4:%.*]] = call i32* @external_ret2_nrw(i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0]], i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0]], i32* nofree nonnull align 4 dereferenceable(4) [[W0]]) #[[ATTR3]] ; IS__CGSCC____-NEXT: br label [[RETURN]] ; IS__CGSCC____: return: @@ -339,8 +339,8 @@ define i32* @external_source_ret2_nrw(i32* %n0, i32* %r0, i32* %w0) { ; IS__CGSCC____-LABEL: define {{[^@]+}}@external_source_ret2_nrw ; IS__CGSCC____-SAME: (i32* nofree [[N0:%.*]], i32* nofree [[R0:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR2:[0-9]+]] { ; IS__CGSCC____-NEXT: entry: -; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree [[N0]], i32* nocapture nofree readonly [[R0]], i32* nofree writeonly "no-capture-maybe-returned" [[W0]]) #[[ATTR4]] -; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call i32* @external_ret2_nrw(i32* nofree [[N0]], i32* nofree [[R0]], i32* nofree [[W0]]) #[[ATTR5:[0-9]+]] +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree [[N0]], i32* nocapture nofree readonly [[R0]], i32* nofree writeonly "no-capture-maybe-returned" [[W0]]) #[[ATTR5]] +; IS__CGSCC____-NEXT: [[CALL1:%.*]] = call i32* @external_ret2_nrw(i32* nofree [[N0]], i32* nofree [[R0]], i32* nofree [[W0]]) #[[ATTR4]] ; IS__CGSCC____-NEXT: ret i32* [[CALL1]] ; entry: @@ -362,6 +362,6 @@ entry: ; IS__CGSCC____: attributes #[[ATTR1]] = { argmemonly nofree norecurse nosync nounwind willreturn } ; IS__CGSCC____: attributes #[[ATTR2]] = { argmemonly nofree norecurse nosync nounwind } ; IS__CGSCC____: attributes #[[ATTR3]] = { nofree nosync nounwind } -; IS__CGSCC____: attributes #[[ATTR4]] = { nounwind willreturn } -; IS__CGSCC____: attributes #[[ATTR5]] = { nounwind } +; IS__CGSCC____: attributes #[[ATTR4]] = { nounwind } +; IS__CGSCC____: attributes #[[ATTR5]] = { nounwind willreturn } ;. diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll index b760a83a4a006..f1d281dfcbc7f 100644 --- a/llvm/test/Transforms/Attributor/returned.ll +++ b/llvm/test/Transforms/Attributor/returned.ll @@ -58,7 +58,7 @@ define i32 @scc_r1(i32 %a, i32 %r, i32 %b) #0 { ; IS__TUNIT____-LABEL: define {{[^@]+}}@scc_r1 ; IS__TUNIT____-SAME: (i32 [[A:%.*]], i32 returned [[R:%.*]], i32 [[B:%.*]]) #[[ATTR1:[0-9]+]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[A]], i32 [[R]]) #[[ATTR9:[0-9]+]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[A]], i32 [[R]]) #[[ATTR10:[0-9]+]] ; IS__TUNIT____-NEXT: ret i32 [[R]] ; ; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn @@ -82,18 +82,18 @@ define i32 @scc_r2(i32 %a, i32 %b, i32 %r) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[A]], i32 [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[A]], i32 [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN:%.*]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_END12:%.*]] ; IS__TUNIT____: if.then3: -; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[R]], i32 [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[R]], i32 undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[R]], i32 [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call i32 @scc_r1(i32 [[B]], i32 [[R]], i32 undef) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[R]], i32 [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[R]], i32 undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[R]], i32 [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call i32 @scc_r1(i32 [[B]], i32 [[R]], i32 undef) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN]] ; IS__TUNIT____: if.end12: ; IS__TUNIT____-NEXT: [[CMP13:%.*]] = icmp eq i32 [[A]], [[B]] @@ -101,7 +101,7 @@ define i32 @scc_r2(i32 %a, i32 %b, i32 %r) #0 { ; IS__TUNIT____: cond.true: ; IS__TUNIT____-NEXT: br label [[COND_END:%.*]] ; IS__TUNIT____: cond.false: -; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[COND_END]] ; IS__TUNIT____: cond.end: ; IS__TUNIT____-NEXT: [[COND:%.*]] = phi i32 [ [[R]], [[COND_TRUE]] ], [ [[R]], [[COND_FALSE]] ] @@ -197,18 +197,18 @@ define i32 @scc_rX(i32 %a, i32 %b, i32 %r) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[A]], i32 [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[A]], i32 [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN:%.*]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_END12:%.*]] ; IS__TUNIT____: if.then3: -; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[R]], i32 [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[R]], i32 undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[R]], i32 [[B]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call i32 @scc_r1(i32 [[B]], i32 [[B]], i32 undef) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call i32 @scc_r2(i32 [[R]], i32 [[R]], i32 [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[R]], i32 undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call i32 @scc_r1(i32 [[A]], i32 [[B]], i32 undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call i32 @scc_r2(i32 [[B]], i32 [[R]], i32 [[B]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call i32 @scc_r1(i32 [[B]], i32 [[B]], i32 undef) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN]] ; IS__TUNIT____: if.end12: ; IS__TUNIT____-NEXT: [[CMP13:%.*]] = icmp eq i32 [[A]], [[B]] @@ -216,7 +216,7 @@ define i32 @scc_rX(i32 %a, i32 %b, i32 %r) #0 { ; IS__TUNIT____: cond.true: ; IS__TUNIT____-NEXT: br label [[COND_END:%.*]] ; IS__TUNIT____: cond.false: -; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call i32 @scc_r2(i32 [[A]], i32 [[B]], i32 [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[COND_END]] ; IS__TUNIT____: cond.end: ; IS__TUNIT____-NEXT: [[COND:%.*]] = phi i32 [ [[R]], [[COND_TRUE]] ], [ [[R]], [[COND_FALSE]] ] @@ -333,7 +333,7 @@ define double* @ptr_scc_r1(double* %a, double* %r, double* %b) #0 { ; IS__TUNIT____-LABEL: define {{[^@]+}}@ptr_scc_r1 ; IS__TUNIT____-SAME: (double* nocapture nofree readnone [[A:%.*]], double* nofree readnone returned "no-capture-maybe-returned" [[R:%.*]], double* nocapture nofree readnone [[B:%.*]]) #[[ATTR1]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[R]], double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[R]], double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: ret double* [[R]] ; ; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable @@ -357,18 +357,18 @@ define double* @ptr_scc_r2(double* %a, double* %b, double* %r) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp ugt double* [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[B]], double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[B]], double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN:%.*]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: [[CMP2:%.*]] = icmp ult double* [[A]], [[B]] ; IS__TUNIT____-NEXT: br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_END12:%.*]] ; IS__TUNIT____: if.then3: -; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[B]], double* noalias nocapture nofree readnone undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[R]], double* noalias nocapture nofree readnone [[R]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]], double* noalias nocapture nofree readnone undef) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[A]], double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[B]], double* noalias nocapture nofree readnone [[R]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] -; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]], double* noalias nocapture nofree readnone undef) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL5:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[B]], double* noalias nocapture nofree readnone undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL6:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[R]], double* noalias nocapture nofree readnone [[R]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL7:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[A]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]], double* noalias nocapture nofree readnone undef) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[A]], double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL9:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[B]], double* noalias nocapture nofree readnone [[R]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] +; IS__TUNIT____-NEXT: [[CALL11:%.*]] = call double* @ptr_scc_r1(double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]], double* noalias nocapture nofree readnone undef) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[RETURN]] ; IS__TUNIT____: if.end12: ; IS__TUNIT____-NEXT: [[CMP13:%.*]] = icmp eq double* [[A]], [[B]] @@ -376,7 +376,7 @@ define double* @ptr_scc_r2(double* %a, double* %b, double* %r) #0 { ; IS__TUNIT____: cond.true: ; IS__TUNIT____-NEXT: br label [[COND_END:%.*]] ; IS__TUNIT____: cond.false: -; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[A]], double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL14:%.*]] = call double* @ptr_scc_r2(double* noalias nocapture nofree readnone [[A]], double* noalias nocapture nofree readnone [[B]], double* noalias nofree readnone "no-capture-maybe-returned" [[R]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[COND_END]] ; IS__TUNIT____: cond.end: ; IS__TUNIT____-NEXT: [[COND:%.*]] = phi double* [ [[R]], [[COND_TRUE]] ], [ [[R]], [[COND_FALSE]] ] @@ -472,12 +472,19 @@ return: ; preds = %cond.end, %if.then3 ; } ; define i32* @rt0(i32* %a) #0 { -; CHECK: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable -; CHECK-LABEL: define {{[^@]+}}@rt0 -; CHECK-SAME: (i32* nofree noundef nonnull readonly returned align 4 dereferenceable(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3:[0-9]+]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @rt0(i32* nofree noundef nonnull readonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[A]]) #[[ATTR10:[0-9]+]] -; CHECK-NEXT: ret i32* [[A]] +; IS__TUNIT____: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@rt0 +; IS__TUNIT____-SAME: (i32* nofree noundef nonnull readonly returned align 4 dereferenceable(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3:[0-9]+]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt0(i32* nofree noundef nonnull readonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[A]]) #[[ATTR11:[0-9]+]] +; IS__TUNIT____-NEXT: ret i32* [[A]] +; +; IS__CGSCC____: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@rt0 +; IS__CGSCC____-SAME: (i32* nofree noundef nonnull readonly returned align 4 dereferenceable(4) "no-capture-maybe-returned" [[A:%.*]]) #[[ATTR3:[0-9]+]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @rt0(i32* nofree noundef nonnull readonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[A]]) #[[ATTR10:[0-9]+]] +; IS__CGSCC____-NEXT: ret i32* [[A]] ; entry: %v = load i32, i32* %a, align 4 @@ -494,11 +501,17 @@ entry: ; } ; define i32* @rt1(i32* %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@rt1 -; CHECK-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: ret i32* undef +; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@rt1 +; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: ret i32* undef +; +; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@rt1 +; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: ret i32* undef ; entry: %v = load i32, i32* %a, align 4 @@ -515,7 +528,7 @@ define i32* @rt2_helper(i32* %a) #0 { ; IS__TUNIT____-LABEL: define {{[^@]+}}@rt2_helper ; IS__TUNIT____-SAME: (i32* nofree readnone returned [[A:%.*]]) #[[ATTR1]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt2(i32* noalias nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[A]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt2(i32* noalias nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[A]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: ret i32* [[A]] ; ; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable @@ -538,7 +551,7 @@ define i32* @rt2(i32* %a, i32 *%b) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32* [[A]], null ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt2_helper(i32* noalias nofree readnone [[A]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt2_helper(i32* noalias nofree readnone [[A]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[IF_END]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: [[SEL:%.*]] = phi i32* [ [[B]], [[ENTRY:%.*]] ], [ [[A]], [[IF_THEN]] ] @@ -577,7 +590,7 @@ define i32* @rt3_helper(i32* %a, i32* %b) #0 { ; IS__TUNIT____-LABEL: define {{[^@]+}}@rt3_helper ; IS__TUNIT____-SAME: (i32* nocapture nofree readnone [[A:%.*]], i32* nofree readnone returned "no-capture-maybe-returned" [[B:%.*]]) #[[ATTR1]] { ; IS__TUNIT____-NEXT: entry: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt3(i32* noalias nocapture nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[B]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt3(i32* noalias nocapture nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[B]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: ret i32* [[B]] ; ; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable @@ -600,7 +613,7 @@ define i32* @rt3(i32* %a, i32 *%b) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32* [[A]], null ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt3_helper(i32* noalias nocapture nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[B]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @rt3_helper(i32* noalias nocapture nofree readnone [[A]], i32* noalias nofree readnone "no-capture-maybe-returned" [[B]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[IF_END]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: [[SEL:%.*]] = phi i32* [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[IF_THEN]] ] @@ -644,11 +657,17 @@ if.end: declare void @unknown_fn(i32* (i32*)*) #0 define i32* @calls_unknown_fn(i32* %r) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@calls_unknown_fn -; CHECK-SAME: (i32* nofree readnone returned "no-capture-maybe-returned" [[R:%.*]]) #[[ATTR4:[0-9]+]] { -; CHECK-NEXT: tail call void @unknown_fn(i32* (i32*)* noundef nonnull @calls_unknown_fn) #[[ATTR11:[0-9]+]] -; CHECK-NEXT: ret i32* [[R]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@calls_unknown_fn +; IS__TUNIT____-SAME: (i32* nofree readnone returned "no-capture-maybe-returned" [[R:%.*]]) #[[ATTR5:[0-9]+]] { +; IS__TUNIT____-NEXT: tail call void @unknown_fn(i32* (i32*)* noundef nonnull @calls_unknown_fn) #[[ATTR12:[0-9]+]] +; IS__TUNIT____-NEXT: ret i32* [[R]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@calls_unknown_fn +; IS__CGSCC____-SAME: (i32* nofree readnone returned "no-capture-maybe-returned" [[R:%.*]]) #[[ATTR4:[0-9]+]] { +; IS__CGSCC____-NEXT: tail call void @unknown_fn(i32* (i32*)* noundef nonnull @calls_unknown_fn) #[[ATTR11:[0-9]+]] +; IS__CGSCC____-NEXT: ret i32* [[R]] ; tail call void @unknown_fn(i32* (i32*)* nonnull @calls_unknown_fn) ret i32* %r @@ -669,23 +688,36 @@ define i32* @calls_unknown_fn(i32* %r) #0 { ; Verify the maybe-redefined function is not annotated: ; define linkonce_odr i32* @maybe_redefined_fn(i32* %r) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@maybe_redefined_fn -; CHECK-SAME: (i32* [[R:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: ret i32* [[R]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@maybe_redefined_fn +; IS__TUNIT____-SAME: (i32* [[R:%.*]]) #[[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: ret i32* [[R]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@maybe_redefined_fn +; IS__CGSCC____-SAME: (i32* [[R:%.*]]) #[[ATTR4]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: ret i32* [[R]] ; entry: ret i32* %r } define i32* @calls_maybe_redefined_fn(i32* %r) #0 { -; CHECK: Function Attrs: noinline norecurse nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn -; CHECK-SAME: (i32* returned [[R:%.*]]) #[[ATTR5:[0-9]+]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn(i32* [[R]]) #[[ATTR11]] -; CHECK-NEXT: ret i32* [[R]] +; IS__TUNIT____: Function Attrs: noinline norecurse nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn +; IS__TUNIT____-SAME: (i32* returned [[R:%.*]]) #[[ATTR6:[0-9]+]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn(i32* [[R]]) #[[ATTR12]] +; IS__TUNIT____-NEXT: ret i32* [[R]] +; +; IS__CGSCC____: Function Attrs: noinline norecurse nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn +; IS__CGSCC____-SAME: (i32* returned [[R:%.*]]) #[[ATTR5:[0-9]+]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn(i32* [[R]]) #[[ATTR11]] +; IS__CGSCC____-NEXT: ret i32* [[R]] ; entry: %call = call i32* @maybe_redefined_fn(i32* %r) @@ -705,23 +737,36 @@ entry: ; Verify the maybe-redefined function is not annotated: ; define linkonce_odr i32* @maybe_redefined_fn2(i32* %r) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@maybe_redefined_fn2 -; CHECK-SAME: (i32* [[R:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: ret i32* [[R]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@maybe_redefined_fn2 +; IS__TUNIT____-SAME: (i32* [[R:%.*]]) #[[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: ret i32* [[R]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@maybe_redefined_fn2 +; IS__CGSCC____-SAME: (i32* [[R:%.*]]) #[[ATTR4]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: ret i32* [[R]] ; entry: ret i32* %r } define i32* @calls_maybe_redefined_fn2(i32* %r) #0 { -; CHECK: Function Attrs: noinline norecurse nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn2 -; CHECK-SAME: (i32* [[R:%.*]]) #[[ATTR5]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn2(i32* [[R]]) #[[ATTR11]] -; CHECK-NEXT: ret i32* [[CALL]] +; IS__TUNIT____: Function Attrs: noinline norecurse nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn2 +; IS__TUNIT____-SAME: (i32* [[R:%.*]]) #[[ATTR6]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn2(i32* [[R]]) #[[ATTR12]] +; IS__TUNIT____-NEXT: ret i32* [[CALL]] +; +; IS__CGSCC____: Function Attrs: noinline norecurse nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@calls_maybe_redefined_fn2 +; IS__CGSCC____-SAME: (i32* [[R:%.*]]) #[[ATTR5]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @maybe_redefined_fn2(i32* [[R]]) #[[ATTR11]] +; IS__CGSCC____-NEXT: ret i32* [[CALL]] ; entry: %call = call i32* @maybe_redefined_fn2(i32* %r) @@ -783,7 +828,7 @@ define double @recursion_select_and_phi(i32 %a, double %b) #0 { ; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], 0 ; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: [[CALL:%.*]] = call double @recursion_select_and_phi(i32 [[DEC]], double [[B]]) #[[ATTR9]] +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call double @recursion_select_and_phi(i32 [[DEC]], double [[B]]) #[[ATTR10]] ; IS__TUNIT____-NEXT: br label [[IF_END]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: ret double [[B]] @@ -1041,17 +1086,29 @@ ret_undef1: declare i32* @unknown(i32*) define i32* @ret_arg_or_unknown(i32* %b) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@ret_arg_or_unknown -; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null -; CHECK-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] -; CHECK: ret_arg: -; CHECK-NEXT: ret i32* [[B]] -; CHECK: ret_unknown: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) -; CHECK-NEXT: ret i32* [[CALL]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@ret_arg_or_unknown +; IS__TUNIT____-SAME: (i32* [[B:%.*]]) #[[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null +; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] +; IS__TUNIT____: ret_arg: +; IS__TUNIT____-NEXT: ret i32* [[B]] +; IS__TUNIT____: ret_unknown: +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) +; IS__TUNIT____-NEXT: ret i32* [[CALL]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@ret_arg_or_unknown +; IS__CGSCC____-SAME: (i32* [[B:%.*]]) #[[ATTR4]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null +; IS__CGSCC____-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] +; IS__CGSCC____: ret_arg: +; IS__CGSCC____-NEXT: ret i32* [[B]] +; IS__CGSCC____: ret_unknown: +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) +; IS__CGSCC____-NEXT: ret i32* [[CALL]] ; entry: %cmp = icmp eq i32* %b, null @@ -1066,20 +1123,35 @@ ret_unknown: } define i32* @ret_arg_or_unknown_through_phi(i32* %b) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@ret_arg_or_unknown_through_phi -; CHECK-SAME: (i32* [[B:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null -; CHECK-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] -; CHECK: ret_arg: -; CHECK-NEXT: br label [[R:%.*]] -; CHECK: ret_unknown: -; CHECK-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) -; CHECK-NEXT: br label [[R]] -; CHECK: r: -; CHECK-NEXT: [[PHI:%.*]] = phi i32* [ [[B]], [[RET_ARG]] ], [ [[CALL]], [[RET_UNKNOWN]] ] -; CHECK-NEXT: ret i32* [[PHI]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@ret_arg_or_unknown_through_phi +; IS__TUNIT____-SAME: (i32* [[B:%.*]]) #[[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null +; IS__TUNIT____-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] +; IS__TUNIT____: ret_arg: +; IS__TUNIT____-NEXT: br label [[R:%.*]] +; IS__TUNIT____: ret_unknown: +; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) +; IS__TUNIT____-NEXT: br label [[R]] +; IS__TUNIT____: r: +; IS__TUNIT____-NEXT: [[PHI:%.*]] = phi i32* [ [[B]], [[RET_ARG]] ], [ [[CALL]], [[RET_UNKNOWN]] ] +; IS__TUNIT____-NEXT: ret i32* [[PHI]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@ret_arg_or_unknown_through_phi +; IS__CGSCC____-SAME: (i32* [[B:%.*]]) #[[ATTR4]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp eq i32* [[B]], null +; IS__CGSCC____-NEXT: br i1 [[CMP]], label [[RET_ARG:%.*]], label [[RET_UNKNOWN:%.*]] +; IS__CGSCC____: ret_arg: +; IS__CGSCC____-NEXT: br label [[R:%.*]] +; IS__CGSCC____: ret_unknown: +; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32* @unknown(i32* [[B]]) +; IS__CGSCC____-NEXT: br label [[R]] +; IS__CGSCC____: r: +; IS__CGSCC____-NEXT: [[PHI:%.*]] = phi i32* [ [[B]], [[RET_ARG]] ], [ [[CALL]], [[RET_UNKNOWN]] ] +; IS__CGSCC____-NEXT: ret i32* [[PHI]] ; entry: %cmp = icmp eq i32* %b, null @@ -1198,20 +1270,35 @@ r: declare void @noreturn() noreturn; define i32 @deadblockphi3(i32 %A, i1 %c) #0 { -; CHECK: Function Attrs: noinline nounwind uwtable -; CHECK-LABEL: define {{[^@]+}}@deadblockphi3 -; CHECK-SAME: (i32 returned [[A:%.*]], i1 [[C:%.*]]) #[[ATTR4]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 [[C]], label [[R:%.*]], label [[UNREACHABLECALL:%.*]] -; CHECK: unreachablecall: -; CHECK-NEXT: call void @noreturn() #[[ATTR6:[0-9]+]] -; CHECK-NEXT: unreachable -; CHECK: unreachableblock2: -; CHECK-NEXT: unreachable -; CHECK: unreachableblock3: -; CHECK-NEXT: unreachable -; CHECK: r: -; CHECK-NEXT: ret i32 [[A]] +; IS__TUNIT____: Function Attrs: noinline nounwind uwtable +; IS__TUNIT____-LABEL: define {{[^@]+}}@deadblockphi3 +; IS__TUNIT____-SAME: (i32 returned [[A:%.*]], i1 [[C:%.*]]) #[[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: br i1 [[C]], label [[R:%.*]], label [[UNREACHABLECALL:%.*]] +; IS__TUNIT____: unreachablecall: +; IS__TUNIT____-NEXT: call void @noreturn() #[[ATTR7:[0-9]+]] +; IS__TUNIT____-NEXT: unreachable +; IS__TUNIT____: unreachableblock2: +; IS__TUNIT____-NEXT: unreachable +; IS__TUNIT____: unreachableblock3: +; IS__TUNIT____-NEXT: unreachable +; IS__TUNIT____: r: +; IS__TUNIT____-NEXT: ret i32 [[A]] +; +; IS__CGSCC____: Function Attrs: noinline nounwind uwtable +; IS__CGSCC____-LABEL: define {{[^@]+}}@deadblockphi3 +; IS__CGSCC____-SAME: (i32 returned [[A:%.*]], i1 [[C:%.*]]) #[[ATTR4]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: br i1 [[C]], label [[R:%.*]], label [[UNREACHABLECALL:%.*]] +; IS__CGSCC____: unreachablecall: +; IS__CGSCC____-NEXT: call void @noreturn() #[[ATTR6:[0-9]+]] +; IS__CGSCC____-NEXT: unreachable +; IS__CGSCC____: unreachableblock2: +; IS__CGSCC____-NEXT: unreachable +; IS__CGSCC____: unreachableblock3: +; IS__CGSCC____-NEXT: unreachable +; IS__CGSCC____: r: +; IS__CGSCC____-NEXT: ret i32 [[A]] ; entry: br i1 %c, label %r, label %unreachablecall @@ -1269,21 +1356,37 @@ define weak_odr align 16 i32* @non_exact_4(i32* align 32 %a) { ; We can use the return information of the weak function non_exact_4. ; FIXME: %c2 and %c3 should be replaced but not %c0 or %c1! define i32 @exact(i32* align 8 %a, i32* align 8 %b) { -; CHECK: Function Attrs: norecurse -; CHECK-LABEL: define {{[^@]+}}@exact -; CHECK-SAME: (i32* align 8 [[A:%.*]], i32* align 8 [[B:%.*]]) #[[ATTR7:[0-9]+]] { -; CHECK-NEXT: [[C0:%.*]] = call i32 @non_exact_0() -; CHECK-NEXT: [[C1:%.*]] = call i32 @non_exact_1(i32 noundef 1) -; CHECK-NEXT: [[C2:%.*]] = call i32 @non_exact_2(i32 noundef 2) -; CHECK-NEXT: [[C3:%.*]] = call align 32 i32* @non_exact_3(i32* align 32 [[A]]) -; CHECK-NEXT: [[C4:%.*]] = call align 16 i32* @non_exact_4(i32* align 32 [[B]]) -; CHECK-NEXT: [[C3L:%.*]] = load i32, i32* [[A]], align 32 -; CHECK-NEXT: [[C4L:%.*]] = load i32, i32* [[C4]], align 16 -; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[C0]], [[C1]] -; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], 2 -; CHECK-NEXT: [[ADD3:%.*]] = add i32 [[ADD2]], [[C3L]] -; CHECK-NEXT: [[ADD4:%.*]] = add i32 [[ADD3]], [[C4L]] -; CHECK-NEXT: ret i32 [[ADD4]] +; IS__TUNIT____: Function Attrs: norecurse +; IS__TUNIT____-LABEL: define {{[^@]+}}@exact +; IS__TUNIT____-SAME: (i32* align 8 [[A:%.*]], i32* align 8 [[B:%.*]]) #[[ATTR8:[0-9]+]] { +; IS__TUNIT____-NEXT: [[C0:%.*]] = call i32 @non_exact_0() +; IS__TUNIT____-NEXT: [[C1:%.*]] = call i32 @non_exact_1(i32 noundef 1) +; IS__TUNIT____-NEXT: [[C2:%.*]] = call i32 @non_exact_2(i32 noundef 2) +; IS__TUNIT____-NEXT: [[C3:%.*]] = call align 32 i32* @non_exact_3(i32* align 32 [[A]]) +; IS__TUNIT____-NEXT: [[C4:%.*]] = call align 16 i32* @non_exact_4(i32* align 32 [[B]]) +; IS__TUNIT____-NEXT: [[C3L:%.*]] = load i32, i32* [[A]], align 32 +; IS__TUNIT____-NEXT: [[C4L:%.*]] = load i32, i32* [[C4]], align 16 +; IS__TUNIT____-NEXT: [[ADD1:%.*]] = add i32 [[C0]], [[C1]] +; IS__TUNIT____-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], 2 +; IS__TUNIT____-NEXT: [[ADD3:%.*]] = add i32 [[ADD2]], [[C3L]] +; IS__TUNIT____-NEXT: [[ADD4:%.*]] = add i32 [[ADD3]], [[C4L]] +; IS__TUNIT____-NEXT: ret i32 [[ADD4]] +; +; IS__CGSCC____: Function Attrs: norecurse +; IS__CGSCC____-LABEL: define {{[^@]+}}@exact +; IS__CGSCC____-SAME: (i32* align 8 [[A:%.*]], i32* align 8 [[B:%.*]]) #[[ATTR7:[0-9]+]] { +; IS__CGSCC____-NEXT: [[C0:%.*]] = call i32 @non_exact_0() +; IS__CGSCC____-NEXT: [[C1:%.*]] = call i32 @non_exact_1(i32 noundef 1) +; IS__CGSCC____-NEXT: [[C2:%.*]] = call i32 @non_exact_2(i32 noundef 2) +; IS__CGSCC____-NEXT: [[C3:%.*]] = call align 32 i32* @non_exact_3(i32* align 32 [[A]]) +; IS__CGSCC____-NEXT: [[C4:%.*]] = call align 16 i32* @non_exact_4(i32* align 32 [[B]]) +; IS__CGSCC____-NEXT: [[C3L:%.*]] = load i32, i32* [[A]], align 32 +; IS__CGSCC____-NEXT: [[C4L:%.*]] = load i32, i32* [[C4]], align 16 +; IS__CGSCC____-NEXT: [[ADD1:%.*]] = add i32 [[C0]], [[C1]] +; IS__CGSCC____-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], 2 +; IS__CGSCC____-NEXT: [[ADD3:%.*]] = add i32 [[ADD2]], [[C3L]] +; IS__CGSCC____-NEXT: [[ADD4:%.*]] = add i32 [[ADD3]], [[C4L]] +; IS__CGSCC____-NEXT: ret i32 [[ADD4]] ; %c0 = call i32 @non_exact_0() %c1 = call i32 @non_exact_1(i32 1) @@ -1377,15 +1480,16 @@ attributes #0 = { noinline nounwind uwtable } ; IS__TUNIT____: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable } ; IS__TUNIT____: attributes #[[ATTR2]] = { nofree noinline norecurse nosync nounwind readnone uwtable } ; IS__TUNIT____: attributes #[[ATTR3]] = { argmemonly nofree noinline nosync nounwind readonly uwtable } -; IS__TUNIT____: attributes #[[ATTR4]] = { noinline nounwind uwtable } -; IS__TUNIT____: attributes #[[ATTR5]] = { noinline norecurse nounwind uwtable } -; IS__TUNIT____: attributes #[[ATTR6]] = { noreturn } -; IS__TUNIT____: attributes #[[ATTR7]] = { norecurse } -; IS__TUNIT____: attributes #[[ATTR8:[0-9]+]] = { nofree norecurse nosync nounwind readnone willreturn } -; IS__TUNIT____: attributes #[[ATTR9]] = { nofree nosync nounwind readnone } -; IS__TUNIT____: attributes #[[ATTR10]] = { nofree nosync nounwind readonly } -; IS__TUNIT____: attributes #[[ATTR11]] = { nounwind } -; IS__TUNIT____: attributes #[[ATTR12:[0-9]+]] = { nounwind readnone } +; IS__TUNIT____: attributes #[[ATTR4]] = { nofree noinline nosync nounwind readnone uwtable willreturn } +; IS__TUNIT____: attributes #[[ATTR5]] = { noinline nounwind uwtable } +; IS__TUNIT____: attributes #[[ATTR6]] = { noinline norecurse nounwind uwtable } +; IS__TUNIT____: attributes #[[ATTR7]] = { noreturn } +; IS__TUNIT____: attributes #[[ATTR8]] = { norecurse } +; IS__TUNIT____: attributes #[[ATTR9:[0-9]+]] = { nofree norecurse nosync nounwind readnone willreturn } +; IS__TUNIT____: attributes #[[ATTR10]] = { nofree nosync nounwind readnone } +; IS__TUNIT____: attributes #[[ATTR11]] = { nofree nosync nounwind readonly } +; IS__TUNIT____: attributes #[[ATTR12]] = { nounwind } +; IS__TUNIT____: attributes #[[ATTR13:[0-9]+]] = { nounwind readnone } ;. ; IS__CGSCC____: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } ; IS__CGSCC____: attributes #[[ATTR1]] = { nofree noinline nosync nounwind readnone uwtable willreturn } @@ -1399,5 +1503,4 @@ attributes #0 = { noinline nounwind uwtable } ; IS__CGSCC____: attributes #[[ATTR9]] = { nofree nosync nounwind readnone } ; IS__CGSCC____: attributes #[[ATTR10]] = { nofree nosync nounwind readonly } ; IS__CGSCC____: attributes #[[ATTR11]] = { nounwind } -; IS__CGSCC____: attributes #[[ATTR12:[0-9]+]] = { nounwind readnone } ;. diff --git a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll index 66c41ba598ca9..0ed49765575ad 100644 --- a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll +++ b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/value-simplify-instances.ll b/llvm/test/Transforms/Attributor/value-simplify-instances.ll index a7c072c985315..16d1bb7d1ecb0 100644 --- a/llvm/test/Transforms/Attributor/value-simplify-instances.ll +++ b/llvm/test/Transforms/Attributor/value-simplify-instances.ll @@ -26,16 +26,16 @@ define internal i1 @recursive_inst_comparator(i1* %a, i1* %b) { } define internal i1 @recursive_inst_generator(i1 %c, i1* %p) { -; IS________OPM-LABEL: define {{[^@]+}}@recursive_inst_generator -; IS________OPM-SAME: (i1 [[C:%.*]], i1* nofree [[P:%.*]]) { -; IS________OPM-NEXT: [[A:%.*]] = call i1* @geti1Ptr() -; IS________OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; IS________OPM: t: -; IS________OPM-NEXT: [[R1:%.*]] = call i1 @recursive_inst_comparator(i1* noalias nofree readnone [[A]], i1* noalias nofree readnone [[P]]) #[[ATTR6:[0-9]+]] -; IS________OPM-NEXT: ret i1 [[R1]] -; IS________OPM: f: -; IS________OPM-NEXT: [[R2:%.*]] = call i1 @recursive_inst_generator(i1 noundef true, i1* nofree [[A]]) -; IS________OPM-NEXT: ret i1 [[R2]] +; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@recursive_inst_generator +; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]], i1* nofree [[P:%.*]]) { +; IS__TUNIT_OPM-NEXT: [[A:%.*]] = call i1* @geti1Ptr() +; IS__TUNIT_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; IS__TUNIT_OPM: t: +; IS__TUNIT_OPM-NEXT: [[R1:%.*]] = call i1 @recursive_inst_comparator(i1* noalias nofree readnone [[A]], i1* noalias nofree readnone [[P]]) #[[ATTR6:[0-9]+]] +; IS__TUNIT_OPM-NEXT: ret i1 [[R1]] +; IS__TUNIT_OPM: f: +; IS__TUNIT_OPM-NEXT: [[R2:%.*]] = call i1 @recursive_inst_generator(i1 noundef true, i1* nofree [[A]]) +; IS__TUNIT_OPM-NEXT: ret i1 [[R2]] ; ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@recursive_inst_generator ; IS__TUNIT_NPM-SAME: (i1 [[C:%.*]], i1* nofree [[P:%.*]]) { @@ -48,12 +48,23 @@ define internal i1 @recursive_inst_generator(i1 %c, i1* %p) { ; IS__TUNIT_NPM-NEXT: [[R2:%.*]] = call i1 @recursive_inst_generator(i1 noundef true, i1* nofree [[A]]) ; IS__TUNIT_NPM-NEXT: ret i1 [[R2]] ; +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@recursive_inst_generator +; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i1* nofree [[P:%.*]]) { +; IS__CGSCC_OPM-NEXT: [[A:%.*]] = call i1* @geti1Ptr() +; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; IS__CGSCC_OPM: t: +; IS__CGSCC_OPM-NEXT: [[R1:%.*]] = call i1 @recursive_inst_comparator(i1* noalias nofree readnone [[A]], i1* noalias nofree readnone [[P]]) +; IS__CGSCC_OPM-NEXT: ret i1 [[R1]] +; IS__CGSCC_OPM: f: +; IS__CGSCC_OPM-NEXT: [[R2:%.*]] = call i1 @recursive_inst_generator(i1 noundef true, i1* nofree [[A]]) +; IS__CGSCC_OPM-NEXT: ret i1 [[R2]] +; ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@recursive_inst_generator ; IS__CGSCC_NPM-SAME: (i1 [[C:%.*]]) { ; IS__CGSCC_NPM-NEXT: [[A:%.*]] = call i1* @geti1Ptr() ; IS__CGSCC_NPM-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] ; IS__CGSCC_NPM: t: -; IS__CGSCC_NPM-NEXT: [[R1:%.*]] = call i1 @recursive_inst_comparator(i1* noalias nofree readnone [[A]], i1* noalias nofree readnone [[A]]) #[[ATTR6:[0-9]+]] +; IS__CGSCC_NPM-NEXT: [[R1:%.*]] = call i1 @recursive_inst_comparator(i1* noalias nofree readnone [[A]], i1* noalias nofree readnone [[A]]) ; IS__CGSCC_NPM-NEXT: ret i1 [[R1]] ; IS__CGSCC_NPM: f: ; IS__CGSCC_NPM-NEXT: [[R2:%.*]] = call i1 @recursive_inst_generator(i1 noundef true) diff --git a/llvm/test/Transforms/Attributor/willreturn.ll b/llvm/test/Transforms/Attributor/willreturn.ll index 3746ac2e5a103..9b56703de9617 100644 --- a/llvm/test/Transforms/Attributor/willreturn.ll +++ b/llvm/test/Transforms/Attributor/willreturn.ll @@ -317,9 +317,9 @@ define void @conditional_exit(i32 %0, i32* nocapture readonly %1) local_unnamed_ declare float @llvm.floor.f32(float) define void @call_floor(float %a) #0 { -; CHECK: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn +; CHECK: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; CHECK-LABEL: define {{[^@]+}}@call_floor -; CHECK-SAME: (float [[A:%.*]]) #[[ATTR0]] { +; CHECK-SAME: (float [[A:%.*]]) #[[ATTR9:[0-9]+]] { ; CHECK-NEXT: ret void ; tail call float @llvm.floor.f32(float %a) @@ -329,13 +329,13 @@ define void @call_floor(float %a) #0 { define float @call_floor2(float %a) #0 { ; IS________OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@call_floor2 -; IS________OPM-SAME: (float [[A:%.*]]) #[[ATTR9:[0-9]+]] { +; IS________OPM-SAME: (float [[A:%.*]]) #[[ATTR9]] { ; IS________OPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) #[[ATTR27:[0-9]+]] ; IS________OPM-NEXT: ret float [[C]] ; ; IS________NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@call_floor2 -; IS________NPM-SAME: (float [[A:%.*]]) #[[ATTR9:[0-9]+]] { +; IS________NPM-SAME: (float [[A:%.*]]) #[[ATTR9]] { ; IS________NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) #[[ATTR29:[0-9]+]] ; IS________NPM-NEXT: ret float [[C]] ; diff --git a/llvm/test/Transforms/OpenMP/remove_globalization.ll b/llvm/test/Transforms/OpenMP/remove_globalization.ll index bc9ede6292ab3..c42e6430254b9 100644 --- a/llvm/test/Transforms/OpenMP/remove_globalization.ll +++ b/llvm/test/Transforms/OpenMP/remove_globalization.ll @@ -30,18 +30,18 @@ define void @kernel() { ; CHECK-LABEL: define {{[^@]+}}@kernel() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* nonnull null, i8 1, i1 false, i1 true) -; CHECK-NEXT: call void @foo() #[[ATTR3:[0-9]+]] -; CHECK-NEXT: call void @bar() #[[ATTR3]] -; CHECK-NEXT: call void @unknown_no_openmp() #[[ATTR2:[0-9]+]] +; CHECK-NEXT: call void @foo() #[[ATTR4:[0-9]+]] +; CHECK-NEXT: call void @bar() #[[ATTR4]] +; CHECK-NEXT: call void @unknown_no_openmp() #[[ATTR3:[0-9]+]] ; CHECK-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* nonnull null, i8 1, i1 true) ; CHECK-NEXT: ret void ; ; CHECK-DISABLED-LABEL: define {{[^@]+}}@kernel() { ; CHECK-DISABLED-NEXT: entry: ; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* nonnull null, i8 1, i1 false, i1 true) -; CHECK-DISABLED-NEXT: call void @foo() #[[ATTR3:[0-9]+]] -; CHECK-DISABLED-NEXT: call void @bar() #[[ATTR3]] -; CHECK-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR2:[0-9]+]] +; CHECK-DISABLED-NEXT: call void @foo() #[[ATTR4:[0-9]+]] +; CHECK-DISABLED-NEXT: call void @bar() #[[ATTR4]] +; CHECK-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR3:[0-9]+]] ; CHECK-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* nonnull null, i8 1, i1 true) ; CHECK-DISABLED-NEXT: ret void ; @@ -78,17 +78,17 @@ define internal void @bar() { ; CHECK-LABEL: define {{[^@]+}}@bar ; CHECK-SAME: () #[[ATTR0]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 noundef 4) #[[ATTR3]], !dbg [[DBG8:![0-9]+]] -; CHECK-NEXT: call void @share(i8* nofree writeonly [[TMP0]]) #[[ATTR4:[0-9]+]] -; CHECK-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 noundef 4) #[[ATTR3]] +; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 noundef 4) #[[ATTR4]], !dbg [[DBG8:![0-9]+]] +; CHECK-NEXT: call void @share(i8* nofree writeonly [[TMP0]]) #[[ATTR5:[0-9]+]] +; CHECK-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 noundef 4) #[[ATTR4]] ; CHECK-NEXT: ret void ; ; CHECK-DISABLED-LABEL: define {{[^@]+}}@bar ; CHECK-DISABLED-SAME: () #[[ATTR0]] { ; CHECK-DISABLED-NEXT: entry: -; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 noundef 4) #[[ATTR3]], !dbg [[DBG8:![0-9]+]] -; CHECK-DISABLED-NEXT: call void @share(i8* nofree writeonly [[TMP0]]) #[[ATTR4:[0-9]+]] -; CHECK-DISABLED-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 noundef 4) #[[ATTR3]] +; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 noundef 4) #[[ATTR4]], !dbg [[DBG8:![0-9]+]] +; CHECK-DISABLED-NEXT: call void @share(i8* nofree writeonly [[TMP0]]) #[[ATTR5:[0-9]+]] +; CHECK-DISABLED-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 noundef 4) #[[ATTR4]] ; CHECK-DISABLED-NEXT: ret void ; entry: @@ -99,19 +99,29 @@ entry: } define internal void @use(i8* %x) { +; CHECK-LABEL: define {{[^@]+}}@use +; CHECK-SAME: (i8* noalias nocapture nofree readnone [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +; CHECK-DISABLED-LABEL: define {{[^@]+}}@use +; CHECK-DISABLED-SAME: (i8* noalias nocapture nofree readnone [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-DISABLED-NEXT: entry: +; CHECK-DISABLED-NEXT: ret void +; entry: ret void } define internal void @share(i8* %x) { ; CHECK-LABEL: define {{[^@]+}}@share -; CHECK-SAME: (i8* nofree writeonly [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-SAME: (i8* nofree writeonly [[X:%.*]]) #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: store i8* [[X]], i8** @S, align 8 ; CHECK-NEXT: ret void ; ; CHECK-DISABLED-LABEL: define {{[^@]+}}@share -; CHECK-DISABLED-SAME: (i8* nofree writeonly [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-DISABLED-SAME: (i8* nofree writeonly [[X:%.*]]) #[[ATTR2:[0-9]+]] { ; CHECK-DISABLED-NEXT: entry: ; CHECK-DISABLED-NEXT: store i8* [[X]], i8** @S, align 8 ; CHECK-DISABLED-NEXT: ret void @@ -125,12 +135,14 @@ define void @unused() { ; CHECK-LABEL: define {{[^@]+}}@unused() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca i8, i64 4, align 1 +; CHECK-NEXT: call void @use(i8* noalias readnone undef) ; CHECK-NEXT: ret void ; ; CHECK-DISABLED-LABEL: define {{[^@]+}}@unused() { ; CHECK-DISABLED-NEXT: entry: -; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 4) #[[ATTR3]], !dbg [[DBG11:![0-9]+]] -; CHECK-DISABLED-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 4) #[[ATTR3]] +; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i8* @__kmpc_alloc_shared(i64 4), !dbg [[DBG11:![0-9]+]] +; CHECK-DISABLED-NEXT: call void @use(i8* noalias readnone [[TMP0]]) +; CHECK-DISABLED-NEXT: call void @__kmpc_free_shared(i8* [[TMP0]], i64 4) ; CHECK-DISABLED-NEXT: ret void ; entry: @@ -169,16 +181,18 @@ declare void @unknown_no_openmp() "llvm.assume"="omp_no_openmp" !14 = !DILocation(line: 6, column: 2, scope: !9) ;. ; CHECK: attributes #[[ATTR0]] = { nosync nounwind } -; CHECK: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind willreturn writeonly } -; CHECK: attributes #[[ATTR2]] = { "llvm.assume"="omp_no_openmp" } -; CHECK: attributes #[[ATTR3]] = { nounwind } -; CHECK: attributes #[[ATTR4]] = { nosync nounwind writeonly } +; CHECK: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; CHECK: attributes #[[ATTR2]] = { nofree norecurse nosync nounwind willreturn writeonly } +; CHECK: attributes #[[ATTR3]] = { "llvm.assume"="omp_no_openmp" } +; CHECK: attributes #[[ATTR4]] = { nounwind } +; CHECK: attributes #[[ATTR5]] = { nosync nounwind writeonly } ;. ; CHECK-DISABLED: attributes #[[ATTR0]] = { nosync nounwind } -; CHECK-DISABLED: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind willreturn writeonly } -; CHECK-DISABLED: attributes #[[ATTR2]] = { "llvm.assume"="omp_no_openmp" } -; CHECK-DISABLED: attributes #[[ATTR3]] = { nounwind } -; CHECK-DISABLED: attributes #[[ATTR4]] = { nosync nounwind writeonly } +; CHECK-DISABLED: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } +; CHECK-DISABLED: attributes #[[ATTR2]] = { nofree norecurse nosync nounwind willreturn writeonly } +; CHECK-DISABLED: attributes #[[ATTR3]] = { "llvm.assume"="omp_no_openmp" } +; CHECK-DISABLED: attributes #[[ATTR4]] = { nounwind } +; CHECK-DISABLED: attributes #[[ATTR5]] = { nosync nounwind writeonly } ;. ; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 13.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) ; CHECK: [[META1:![0-9]+]] = !DIFile(filename: "remove_globalization.c", directory: "/tmp/remove_globalization.c") From fef110bf8b2b3017b92c61de27ed5cd034b6b0e2 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 17 Feb 2022 12:15:14 -0500 Subject: [PATCH 149/316] [clangd] Fix building SerializationTests unit test on OpenBSD This fixes building the unit tests on OpenBSD. OpenBSD does not support RLIMIT_AS. Reviewed By: kadircet Differential Revision: https://reviews.llvm.org/D119989 (cherry picked from commit f374c8ddf2dd4920190cac0ea81e18a74040ddda) --- clang-tools-extra/clangd/unittests/SerializationTests.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang-tools-extra/clangd/unittests/SerializationTests.cpp b/clang-tools-extra/clangd/unittests/SerializationTests.cpp index 290e20a082d66..6070b229f31c7 100644 --- a/clang-tools-extra/clangd/unittests/SerializationTests.cpp +++ b/clang-tools-extra/clangd/unittests/SerializationTests.cpp @@ -308,9 +308,9 @@ TEST(SerializationTest, CmdlTest) { } } -// rlimit is part of POSIX. +// rlimit is part of POSIX. RLIMIT_AS does not exist in OpenBSD. // Sanitizers use a lot of address space, so we can't apply strict limits. -#if LLVM_ON_UNIX && !LLVM_ADDRESS_SANITIZER_BUILD && \ +#if LLVM_ON_UNIX && defined(RLIMIT_AS) && !LLVM_ADDRESS_SANITIZER_BUILD && \ !LLVM_MEMORY_SANITIZER_BUILD class ScopedMemoryLimit { struct rlimit OriginalLimit; From 56ac6dbc736904c3e812c575853e1e683aa0ed6a Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 17 Feb 2022 12:09:21 -0500 Subject: [PATCH 150/316] [RuntimeDyld] Fix building on OpenBSD With https://reviews.llvm.org/D105466 the tree does not build on OpenBSD/amd64. Moritz suggested only building this code on Linux. Reviewed By: MoritzS Differential Revision: https://reviews.llvm.org/D119991 (cherry picked from commit 7db1d4d8da4d4dfc5d0240825e8c4d536a12b19c) --- llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp index 21339a3f8f3d8..893d8a55c8950 100644 --- a/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp +++ b/llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp @@ -286,7 +286,7 @@ class TrivialMemoryManager : public RTDyldMemoryManager { uintptr_t SlabSize = 0; uintptr_t CurrentSlabOffset = 0; SectionIDMap *SecIDMap = nullptr; -#if defined(__x86_64__) && defined(__ELF__) +#if defined(__x86_64__) && defined(__ELF__) && defined(__linux__) unsigned UsedTLSStorage = 0; #endif }; @@ -350,7 +350,7 @@ uint8_t *TrivialMemoryManager::allocateDataSection(uintptr_t Size, // In case the execution needs TLS storage, we define a very small TLS memory // area here that will be used in allocateTLSSection(). -#if defined(__x86_64__) && defined(__ELF__) +#if defined(__x86_64__) && defined(__ELF__) && defined(__linux__) extern "C" { alignas(16) __attribute__((visibility("hidden"), tls_model("initial-exec"), used)) thread_local char LLVMRTDyldTLSSpace[16]; @@ -361,7 +361,7 @@ TrivialMemoryManager::TLSSection TrivialMemoryManager::allocateTLSSection(uintptr_t Size, unsigned Alignment, unsigned SectionID, StringRef SectionName) { -#if defined(__x86_64__) && defined(__ELF__) +#if defined(__x86_64__) && defined(__ELF__) && defined(__linux__) if (Size + UsedTLSStorage > sizeof(LLVMRTDyldTLSSpace)) { return {}; } From 9bf8897c84f797c98ec4c2e1475f5f1539f8277b Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Thu, 17 Feb 2022 13:20:51 -0500 Subject: [PATCH 151/316] [OpenMP] Add RTL function to externalization RAII This patch adds the '_kmpc_get_hardware_num_threads_in_block' OpenMP RTL function to the externalization RAII struct. This was getting optimized out and then being replaced with an undefined value once added back in, causing bugs for complex reductions. Fixes #53909. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D120076 (cherry picked from commit 74cacf212bb31f8ba837b7eb2434258dd79eaccb) --- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 2 ++ .../OpenMP/get_hardware_num_threads_in_block_fold.ll | 11 ++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index 520b6ebf9e74f..5113c0c67acc6 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -2119,6 +2119,8 @@ struct OpenMPOpt { OMPRTL___kmpc_barrier_simple_generic); ExternalizationRAII ThreadId(OMPInfoCache, OMPRTL___kmpc_get_hardware_thread_id_in_block); + ExternalizationRAII NumThreads( + OMPInfoCache, OMPRTL___kmpc_get_hardware_num_threads_in_block); ExternalizationRAII WarpSize(OMPInfoCache, OMPRTL___kmpc_get_warp_size); registerAAs(IsModulePass); diff --git a/llvm/test/Transforms/OpenMP/get_hardware_num_threads_in_block_fold.ll b/llvm/test/Transforms/OpenMP/get_hardware_num_threads_in_block_fold.ll index b72031a9b68c0..57eaebc7e141c 100644 --- a/llvm/test/Transforms/OpenMP/get_hardware_num_threads_in_block_fold.ll +++ b/llvm/test/Transforms/OpenMP/get_hardware_num_threads_in_block_fold.ll @@ -178,7 +178,16 @@ entry: ret void } -declare i32 @__kmpc_get_hardware_num_threads_in_block() +define internal i32 @__kmpc_get_hardware_num_threads_in_block() { +; CHECK-LABEL: define {{[^@]+}}@__kmpc_get_hardware_num_threads_in_block +; CHECK-SAME: () #[[ATTR1]] { +; CHECK-NEXT: [[RET:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block_dummy() +; CHECK-NEXT: ret i32 [[RET]] +; + %ret = call i32 @__kmpc_get_hardware_num_threads_in_block_dummy() + ret i32 %ret +} +declare i32 @__kmpc_get_hardware_num_threads_in_block_dummy() declare i32 @__kmpc_target_init(%struct.ident_t*, i8, i1 zeroext, i1 zeroext) #1 declare void @__kmpc_target_deinit(%struct.ident_t* nocapture readnone, i8, i1 zeroext) #1 declare void @__kmpc_parallel_51(%struct.ident_t*, i32, i32, i32, i32, i8*, i8*, i8**, i64) From b3d3501aa128e7c2cb715319918c0ca66384d3cc Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Mon, 14 Feb 2022 17:19:33 -0600 Subject: [PATCH 152/316] [OpenMP][FIX] Eliminate race on the IsSPMD global The `IsSPMD` global can only be read by threads other than the main thread *after* initialization is complete. To allow usage of `mapping::getBlockSize` before initialization is done, we can pass the `IsSPMD` state explicitly. This is similar to other APIs that take `IsSPMD` explicitly to avoid such a race, e.g., `mapping::isInitialThreadInLevel0(IsSPMD)` Fixes https://github.com/llvm/llvm-project/issues/53857 (cherry picked from commit 57b4c5267b7293b1990d8418477b24732ba0468b) --- openmp/libomptarget/DeviceRTL/include/Mapping.h | 5 +++++ openmp/libomptarget/DeviceRTL/src/Kernel.cpp | 2 +- openmp/libomptarget/DeviceRTL/src/Mapping.cpp | 7 +++++-- openmp/libomptarget/DeviceRTL/src/State.cpp | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/openmp/libomptarget/DeviceRTL/include/Mapping.h b/openmp/libomptarget/DeviceRTL/include/Mapping.h index 4f65d28da513f..36cfae7c5efa4 100644 --- a/openmp/libomptarget/DeviceRTL/include/Mapping.h +++ b/openmp/libomptarget/DeviceRTL/include/Mapping.h @@ -79,7 +79,12 @@ uint32_t getNumberOfWarpsInBlock(); uint32_t getBlockId(); /// Return the block size, thus number of threads in the block. +/// +/// Note: The version taking \p IsSPMD mode explicitly can be used during the +/// initialization of the target region, that is before `mapping::isSPMDMode()` +/// can be called by any thread other than the main one. uint32_t getBlockSize(); +uint32_t getBlockSize(bool IsSPMD); /// Return the number of blocks in the kernel. uint32_t getNumberOfBlocks(); diff --git a/openmp/libomptarget/DeviceRTL/src/Kernel.cpp b/openmp/libomptarget/DeviceRTL/src/Kernel.cpp index 65b554b729731..8b7a8a2495c45 100644 --- a/openmp/libomptarget/DeviceRTL/src/Kernel.cpp +++ b/openmp/libomptarget/DeviceRTL/src/Kernel.cpp @@ -100,7 +100,7 @@ int32_t __kmpc_target_init(IdentTy *Ident, int8_t Mode, // doing any work. mapping::getBlockSize() does not include any of the main // thread's warp, so none of its threads can ever be active worker threads. if (UseGenericStateMachine && - mapping::getThreadIdInBlock() < mapping::getBlockSize()) + mapping::getThreadIdInBlock() < mapping::getBlockSize(IsSPMD)) genericStateMachine(Ident); return mapping::getThreadIdInBlock(); diff --git a/openmp/libomptarget/DeviceRTL/src/Mapping.cpp b/openmp/libomptarget/DeviceRTL/src/Mapping.cpp index 75a500f39d20a..7f9f837ae98e4 100644 --- a/openmp/libomptarget/DeviceRTL/src/Mapping.cpp +++ b/openmp/libomptarget/DeviceRTL/src/Mapping.cpp @@ -212,11 +212,14 @@ uint32_t mapping::getThreadIdInBlock() { uint32_t mapping::getWarpSize() { return impl::getWarpSize(); } -uint32_t mapping::getBlockSize() { +uint32_t mapping::getBlockSize(bool IsSPMD) { uint32_t BlockSize = mapping::getNumberOfProcessorElements() - - (!mapping::isSPMDMode() * impl::getWarpSize()); + (!IsSPMD * impl::getWarpSize()); return BlockSize; } +uint32_t mapping::getBlockSize() { + return mapping::getBlockSize(mapping::isSPMDMode()); +} uint32_t mapping::getKernelSize() { return impl::getKernelSize(); } diff --git a/openmp/libomptarget/DeviceRTL/src/State.cpp b/openmp/libomptarget/DeviceRTL/src/State.cpp index 800176eb5eda5..a04f5cccb1738 100644 --- a/openmp/libomptarget/DeviceRTL/src/State.cpp +++ b/openmp/libomptarget/DeviceRTL/src/State.cpp @@ -236,7 +236,7 @@ struct TeamStateTy { TeamStateTy SHARED(TeamState); void TeamStateTy::init(bool IsSPMD) { - ICVState.NThreadsVar = mapping::getBlockSize(); + ICVState.NThreadsVar = mapping::getBlockSize(IsSPMD); ICVState.LevelVar = 0; ICVState.ActiveLevelVar = 0; ICVState.MaxActiveLevelsVar = 1; From 5593af72d0c53aa0f1ec1653f5bcfaaf1baeec5f Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Mon, 14 Feb 2022 18:32:00 -0600 Subject: [PATCH 153/316] [Attributor][FIX] Heap2Stack needs to use the alloca AS When we move an allocation from the heap to the stack we need to allocate it in the alloca AS and then cast the result. This also prevents us from inserting the alloca after the allocation call but rather right before. Fixes https://github.com/llvm/llvm-project/issues/53858 (cherry picked from commit 8ad39fbaf23893b3384cafa0f179d35dcf3c672b) --- .../Transforms/IPO/AttributorAttributes.cpp | 15 ++++--- .../Attributor/heap_to_stack_gpu.ll | 44 +++++++++++++++++++ llvm/test/Transforms/OpenMP/spmdization.ll | 10 +++-- 3 files changed, 58 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index de36d5d89a185..6dadfebae038d 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -32,6 +32,7 @@ #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Assumptions.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" @@ -6026,13 +6027,13 @@ struct AAHeapToStackFunction final : public AAHeapToStack { else A.emitRemark(AI.CB, "HeapToStack", Remark); + const DataLayout &DL = A.getInfoCache().getDL(); Value *Size; Optional SizeAPI = getSize(A, *this, AI); if (SizeAPI.hasValue()) { Size = ConstantInt::get(AI.CB->getContext(), *SizeAPI); } else { LLVMContext &Ctx = AI.CB->getContext(); - auto &DL = A.getInfoCache().getDL(); ObjectSizeOpts Opts; ObjectSizeOffsetEvaluator Eval(DL, TLI, Ctx, Opts); SizeOffsetEvalType SizeOffsetPair = Eval.compute(AI.CB); @@ -6052,14 +6053,14 @@ struct AAHeapToStackFunction final : public AAHeapToStack { max(Alignment, MaybeAlign(AlignmentAPI.getValue().getZExtValue())); } - unsigned AS = cast(AI.CB->getType())->getAddressSpace(); - Instruction *Alloca = - new AllocaInst(Type::getInt8Ty(F->getContext()), AS, Size, Alignment, - "", AI.CB->getNextNode()); + // TODO: Hoist the alloca towards the function entry. + unsigned AS = DL.getAllocaAddrSpace(); + Instruction *Alloca = new AllocaInst(Type::getInt8Ty(F->getContext()), AS, + Size, Alignment, "", AI.CB); if (Alloca->getType() != AI.CB->getType()) - Alloca = new BitCastInst(Alloca, AI.CB->getType(), "malloc_bc", - Alloca->getNextNode()); + Alloca = BitCastInst::CreatePointerBitCastOrAddrSpaceCast( + Alloca, AI.CB->getType(), "malloc_cast", AI.CB); auto *I8Ty = Type::getInt8Ty(F->getContext()); auto *InitVal = getInitialValueOfAllocation(AI.CB, TLI, I8Ty); diff --git a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll index 0f207e4027599..5ee0a6892ac69 100644 --- a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll +++ b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll @@ -4,7 +4,12 @@ ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; FIXME: amdgpu doesn't claim malloc is a thing, so the test is somewhat +; useless except the __kmpc_alloc_shared part which now also covers the important +; part this test was initially designed for, make sure the "is freed" check is +; not sufficient on a GPU. target triple = "amdgcn-amd-amdhsa" +target datalayout = "A5" declare noalias i8* @malloc(i64) @@ -20,6 +25,7 @@ declare void @no_sync_func(i8* nocapture %p) nofree nosync willreturn declare void @nofree_func(i8* nocapture %p) nofree nosync willreturn +declare void @usei8(i8* %p) declare void @foo(i32* %p) declare void @foo_nounw(i32* %p) nounwind nofree @@ -663,6 +669,43 @@ define void @test16d(i8 %v, i8** %P) { store i8* %1, i8** %P ret void } + +declare i8* @__kmpc_alloc_shared(i64) +declare void @__kmpc_free_shared(i8* nocapture, i64) + +define void @test17() { +; IS________OPM-LABEL: define {{[^@]+}}@test17() { +; IS________OPM-NEXT: [[TMP1:%.*]] = tail call noalias i8* @__kmpc_alloc_shared(i64 noundef 4) +; IS________OPM-NEXT: tail call void @usei8(i8* noalias nocapture nofree [[TMP1]]) #[[ATTR6:[0-9]+]] +; IS________OPM-NEXT: tail call void @__kmpc_free_shared(i8* noalias nocapture [[TMP1]], i64 noundef 4) +; IS________OPM-NEXT: ret void +; +; IS________NPM-LABEL: define {{[^@]+}}@test17() { +; IS________NPM-NEXT: [[TMP1:%.*]] = alloca i8, i64 4, align 1, addrspace(5) +; IS________NPM-NEXT: [[MALLOC_CAST:%.*]] = addrspacecast i8 addrspace(5)* [[TMP1]] to i8* +; IS________NPM-NEXT: tail call void @usei8(i8* noalias nocapture nofree [[MALLOC_CAST]]) #[[ATTR6:[0-9]+]] +; IS________NPM-NEXT: ret void +; + %1 = tail call noalias i8* @__kmpc_alloc_shared(i64 4) + tail call void @usei8(i8* nocapture nofree %1) willreturn nounwind nosync + tail call void @__kmpc_free_shared(i8* %1, i64 4) + ret void +} + +define void @test17b() { +; CHECK-LABEL: define {{[^@]+}}@test17b() { +; CHECK-NEXT: [[TMP1:%.*]] = tail call noalias i8* @__kmpc_alloc_shared(i64 noundef 4) +; CHECK-NEXT: tail call void @usei8(i8* nofree [[TMP1]]) #[[ATTR6:[0-9]+]] +; CHECK-NEXT: tail call void @__kmpc_free_shared(i8* nocapture [[TMP1]], i64 noundef 4) +; CHECK-NEXT: ret void +; + %1 = tail call noalias i8* @__kmpc_alloc_shared(i64 4) + tail call void @usei8(i8* nofree %1) willreturn nounwind nosync + tail call void @__kmpc_free_shared(i8* %1, i64 4) + ret void +} + + ;. ; CHECK: attributes #[[ATTR0:[0-9]+]] = { nounwind willreturn } ; CHECK: attributes #[[ATTR1:[0-9]+]] = { nofree nosync willreturn } @@ -670,4 +713,5 @@ define void @test16d(i8 %v, i8** %P) { ; CHECK: attributes #[[ATTR3]] = { noreturn } ; CHECK: attributes #[[ATTR4:[0-9]+]] = { argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #[[ATTR5]] = { nounwind } +; CHECK: attributes #[[ATTR6]] = { nosync nounwind willreturn } ;. diff --git a/llvm/test/Transforms/OpenMP/spmdization.ll b/llvm/test/Transforms/OpenMP/spmdization.ll index 07ed024cb35bc..752ccff9354ad 100644 --- a/llvm/test/Transforms/OpenMP/spmdization.ll +++ b/llvm/test/Transforms/OpenMP/spmdization.ll @@ -678,8 +678,9 @@ define internal void @__omp_outlined__2(i32* noalias %.global_tid., i32* noalias ; AMDGPU-SAME: (i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { ; AMDGPU-NEXT: entry: ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 -; AMDGPU-NEXT: [[TMP0:%.*]] = alloca i8, i64 4, align 4 -; AMDGPU-NEXT: [[X_ON_STACK:%.*]] = bitcast i8* [[TMP0]] to i32* +; AMDGPU-NEXT: [[TMP0:%.*]] = alloca i8, i64 4, align 4, addrspace(5) +; AMDGPU-NEXT: [[MALLOC_CAST:%.*]] = addrspacecast i8 addrspace(5)* [[TMP0]] to i8* +; AMDGPU-NEXT: [[X_ON_STACK:%.*]] = bitcast i8* [[MALLOC_CAST]] to i32* ; AMDGPU-NEXT: call void @use(i32* nocapture [[X_ON_STACK]]) #[[ATTR5]] ; AMDGPU-NEXT: br label [[FOR_COND:%.*]] ; AMDGPU: for.cond: @@ -722,8 +723,9 @@ define internal void @__omp_outlined__2(i32* noalias %.global_tid., i32* noalias ; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { ; AMDGPU-DISABLED-NEXT: entry: ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 -; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = alloca i8, i64 4, align 4 -; AMDGPU-DISABLED-NEXT: [[X_ON_STACK:%.*]] = bitcast i8* [[TMP0]] to i32* +; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = alloca i8, i64 4, align 4, addrspace(5) +; AMDGPU-DISABLED-NEXT: [[MALLOC_CAST:%.*]] = addrspacecast i8 addrspace(5)* [[TMP0]] to i8* +; AMDGPU-DISABLED-NEXT: [[X_ON_STACK:%.*]] = bitcast i8* [[MALLOC_CAST]] to i32* ; AMDGPU-DISABLED-NEXT: call void @use(i32* nocapture [[X_ON_STACK]]) #[[ATTR5]] ; AMDGPU-DISABLED-NEXT: br label [[FOR_COND:%.*]] ; AMDGPU-DISABLED: for.cond: From 08ad9ae10f327e3a511f1df7423f508103df1525 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 15 Feb 2022 12:00:47 +0100 Subject: [PATCH 154/316] [InstSimplify] Strip offsets once in computePointerICmp() Instead of doing an inbounds strip first and another non-inbounds strip afterward for equality comparisons, directly do a single inbounds or non-inbounds strip based on whether we have an equality predicate or not. This is NFC-ish in that the alloca equality codepath is the only part that sees additional non-inbounds offsets now, and for that codepath it doesn't matter whether or not the GEP is inbounds, as it does a stronger check itself. InstCombine would infer inbounds for such GEPs. (cherry picked from commit f35af77573d9e80bf6e61b3fdd20fe55191e962f) --- llvm/lib/Analysis/InstructionSimplify.cpp | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 4775340b34386..60895d3ced1ac 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -2588,8 +2588,14 @@ computePointerICmp(CmpInst::Predicate Pred, Value *LHS, Value *RHS, // numerous hazards. AliasAnalysis and its utilities rely on special rules // governing loads and stores which don't apply to icmps. Also, AliasAnalysis // doesn't need to guarantee pointer inequality when it says NoAlias. - Constant *LHSOffset = stripAndComputeConstantOffsets(DL, LHS); - Constant *RHSOffset = stripAndComputeConstantOffsets(DL, RHS); + + // Even if an non-inbounds GEP occurs along the path we can still optimize + // equality comparisons concerning the result. + bool AllowNonInbounds = ICmpInst::isEquality(Pred); + Constant *LHSOffset = + stripAndComputeConstantOffsets(DL, LHS, AllowNonInbounds); + Constant *RHSOffset = + stripAndComputeConstantOffsets(DL, RHS, AllowNonInbounds); // If LHS and RHS are related via constant offsets to the same base // value, we can replace it with an icmp which just compares the offsets. @@ -2659,17 +2665,6 @@ computePointerICmp(CmpInst::Predicate Pred, Value *LHS, Value *RHS, !CmpInst::isTrueWhenEqual(Pred)); } - // Even if an non-inbounds GEP occurs along the path we can still optimize - // equality comparisons concerning the result. We avoid walking the whole - // chain again by starting where the last calls to - // stripAndComputeConstantOffsets left off and accumulate the offsets. - Constant *LHSNoBound = stripAndComputeConstantOffsets(DL, LHS, true); - Constant *RHSNoBound = stripAndComputeConstantOffsets(DL, RHS, true); - if (LHS == RHS) - return ConstantExpr::getICmp(Pred, - ConstantExpr::getAdd(LHSOffset, LHSNoBound), - ConstantExpr::getAdd(RHSOffset, RHSNoBound)); - // If one side of the equality comparison must come from a noalias call // (meaning a system memory allocation function), and the other side must // come from a pointer that cannot overlap with dynamically-allocated From 9672d11441fd619d419554fee2ce006053d1d937 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Fri, 11 Feb 2022 10:24:58 +0100 Subject: [PATCH 155/316] [MLIR][Presburger] Disambiguate call to floor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While testing LLVM 14.0.0 rc1 on Solaris, compilation of `FAIL`ed with /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/mlir/lib/Analysis/Presburger/Utils.cpp: In lambda function: /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/mlir/lib/Analysis/Presburger/Utils.cpp:48:58: error: call of overloaded ‘floor(int64_t)’ is ambiguous 48 | [gcd](int64_t &n) { return floor(n / gcd); }); | ^ ... /usr/gcc/10/lib/gcc/sparcv9-sun-solaris2.11/10.3.0/include-fixed/iso/math_iso.h:201:21: note: candidate: ‘long double std::floor(long double)’ 201 | inline long double floor(long double __X) { return __floorl(__X); } | ^~~~~ /usr/gcc/10/lib/gcc/sparcv9-sun-solaris2.11/10.3.0/include-fixed/iso/math_iso.h:165:15: note: candidate: ‘float std::floor(float)’ 165 | inline float floor(float __X) { return __floorf(__X); } | ^~~~~ /usr/gcc/10/lib/gcc/sparcv9-sun-solaris2.11/10.3.0/include-fixed/iso/math_iso.h:78:15: note: candidate: ‘double std::floor(double)’ 78 | extern double floor __P((double)); | ^~~~~ The same issue had already occured in the past, cf. D108750 , and the solution is the same: cast the `floor` arg to `double`. Tested on `amd64-pc-solaris2.11` and `sparcv9-sun-solaris2.11`. Differential Revision: https://reviews.llvm.org/D119324 (cherry picked from commit 91596755359e29c677bfa84d86edcaa1e70df955) --- mlir/lib/Analysis/Presburger/Utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Analysis/Presburger/Utils.cpp b/mlir/lib/Analysis/Presburger/Utils.cpp index bb72881852577..a8de71df252d9 100644 --- a/mlir/lib/Analysis/Presburger/Utils.cpp +++ b/mlir/lib/Analysis/Presburger/Utils.cpp @@ -45,7 +45,7 @@ static void normalizeDivisionByGCD(SmallVectorImpl ÷nd, // Normalize the dividend and the denominator. std::transform(dividend.begin(), dividend.end(), dividend.begin(), - [gcd](int64_t &n) { return floor(n / gcd); }); + [gcd](int64_t &n) { return floor((double)(n / gcd)); }); divisor /= gcd; } From 3367c24735c3408517c6088061eee39030a69e70 Mon Sep 17 00:00:00 2001 From: Nicolas Miller Date: Sat, 19 Feb 2022 20:29:08 +0200 Subject: [PATCH 156/316] [COFF] Move section name encoding into BinaryFormat Large COFF section names are moved into the string table and the section header field is the offset into the string table encoded in ASCII for offset smaller than 7 digits and in base64 for larger offsets. The operation of taking the string table offsets is done in a few places in the codebase, so it is helpful to move this operation into `BinaryFormat` so that it can be shared everywhere it's done. So this patch takes the implementation of this operation from `llvm/lib/MC/WinCOFFObjectWriter.cpp` and moves it into `BinaryFormat`. Reviewed By: jhenderson, rnk Differential Revision: https://reviews.llvm.org/D118793 (cherry picked from commit 85f4023e731c0c42e45bf32bfcbf5f73c2013384) --- llvm/include/llvm/BinaryFormat/COFF.h | 4 ++ llvm/lib/BinaryFormat/CMakeLists.txt | 1 + llvm/lib/BinaryFormat/COFF.cpp | 57 +++++++++++++++++++++++++++ llvm/lib/MC/WinCOFFObjectWriter.cpp | 41 +------------------ 4 files changed, 64 insertions(+), 39 deletions(-) create mode 100644 llvm/lib/BinaryFormat/COFF.cpp diff --git a/llvm/include/llvm/BinaryFormat/COFF.h b/llvm/include/llvm/BinaryFormat/COFF.h index e7dde986784f7..016fe02894065 100644 --- a/llvm/include/llvm/BinaryFormat/COFF.h +++ b/llvm/include/llvm/BinaryFormat/COFF.h @@ -731,6 +731,10 @@ inline bool isReservedSectionNumber(int32_t SectionNumber) { return SectionNumber <= 0; } +/// Encode section name based on string table offset. +/// The size of Out must be at least COFF::NameSize. +bool encodeSectionName(char *Out, uint64_t Offset); + } // End namespace COFF. } // End namespace llvm. diff --git a/llvm/lib/BinaryFormat/CMakeLists.txt b/llvm/lib/BinaryFormat/CMakeLists.txt index 37f6865a487e8..50c1713804368 100644 --- a/llvm/lib/BinaryFormat/CMakeLists.txt +++ b/llvm/lib/BinaryFormat/CMakeLists.txt @@ -1,5 +1,6 @@ add_llvm_component_library(LLVMBinaryFormat AMDGPUMetadataVerifier.cpp + COFF.cpp Dwarf.cpp ELF.cpp MachO.cpp diff --git a/llvm/lib/BinaryFormat/COFF.cpp b/llvm/lib/BinaryFormat/COFF.cpp new file mode 100644 index 0000000000000..8fbee0218b79b --- /dev/null +++ b/llvm/lib/BinaryFormat/COFF.cpp @@ -0,0 +1,57 @@ +//===- llvm/BinaryFormat/COFF.cpp - The COFF format -----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/BinaryFormat/COFF.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Twine.h" + +// Maximum offsets for different string table entry encodings. +enum : unsigned { Max7DecimalOffset = 9999999U }; +enum : uint64_t { MaxBase64Offset = 0xFFFFFFFFFULL }; // 64^6, including 0 + +// Encode a string table entry offset in base 64, padded to 6 chars, and +// prefixed with a double slash: '//AAAAAA', '//AAAAAB', ... +// Buffer must be at least 8 bytes large. No terminating null appended. +static void encodeBase64StringEntry(char *Buffer, uint64_t Value) { + assert(Value > Max7DecimalOffset && Value <= MaxBase64Offset && + "Illegal section name encoding for value"); + + static const char Alphabet[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdefghijklmnopqrstuvwxyz" + "0123456789+/"; + + Buffer[0] = '/'; + Buffer[1] = '/'; + + char *Ptr = Buffer + 7; + for (unsigned i = 0; i < 6; ++i) { + unsigned Rem = Value % 64; + Value /= 64; + *(Ptr--) = Alphabet[Rem]; + } +} + +bool llvm::COFF::encodeSectionName(char *Out, uint64_t Offset) { + if (Offset <= Max7DecimalOffset) { + // Offsets of 7 digits or less are encoded in ASCII. + SmallVector Buffer; + Twine('/').concat(Twine(Offset)).toVector(Buffer); + assert(Buffer.size() <= COFF::NameSize && Buffer.size() >= 2); + std::memcpy(Out, Buffer.data(), Buffer.size()); + return true; + } + + if (Offset <= MaxBase64Offset) { + // Starting with 10,000,000, offsets are encoded as base64. + encodeBase64StringEntry(Out, Offset); + return true; + } + + // The offset is too large to be encoded. + return false; +} diff --git a/llvm/lib/MC/WinCOFFObjectWriter.cpp b/llvm/lib/MC/WinCOFFObjectWriter.cpp index 73c687331d300..aba2ad3155356 100644 --- a/llvm/lib/MC/WinCOFFObjectWriter.cpp +++ b/llvm/lib/MC/WinCOFFObjectWriter.cpp @@ -452,32 +452,6 @@ void WinCOFFObjectWriter::DefineSymbol(const MCSymbol &MCSym, Sym->MC = &MCSym; } -// Maximum offsets for different string table entry encodings. -enum : unsigned { Max7DecimalOffset = 9999999U }; -enum : uint64_t { MaxBase64Offset = 0xFFFFFFFFFULL }; // 64^6, including 0 - -// Encode a string table entry offset in base 64, padded to 6 chars, and -// prefixed with a double slash: '//AAAAAA', '//AAAAAB', ... -// Buffer must be at least 8 bytes large. No terminating null appended. -static void encodeBase64StringEntry(char *Buffer, uint64_t Value) { - assert(Value > Max7DecimalOffset && Value <= MaxBase64Offset && - "Illegal section name encoding for value"); - - static const char Alphabet[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklmnopqrstuvwxyz" - "0123456789+/"; - - Buffer[0] = '/'; - Buffer[1] = '/'; - - char *Ptr = Buffer + 7; - for (unsigned i = 0; i < 6; ++i) { - unsigned Rem = Value % 64; - Value /= 64; - *(Ptr--) = Alphabet[Rem]; - } -} - void WinCOFFObjectWriter::SetSectionName(COFFSection &S) { if (S.Name.size() <= COFF::NameSize) { std::memcpy(S.Header.Name, S.Name.c_str(), S.Name.size()); @@ -485,19 +459,8 @@ void WinCOFFObjectWriter::SetSectionName(COFFSection &S) { } uint64_t StringTableEntry = Strings.getOffset(S.Name); - if (StringTableEntry <= Max7DecimalOffset) { - SmallVector Buffer; - Twine('/').concat(Twine(StringTableEntry)).toVector(Buffer); - assert(Buffer.size() <= COFF::NameSize && Buffer.size() >= 2); - std::memcpy(S.Header.Name, Buffer.data(), Buffer.size()); - return; - } - if (StringTableEntry <= MaxBase64Offset) { - // Starting with 10,000,000, offsets are encoded as base64. - encodeBase64StringEntry(S.Header.Name, StringTableEntry); - return; - } - report_fatal_error("COFF string table is greater than 64 GB."); + if (!COFF::encodeSectionName(S.Header.Name, StringTableEntry)) + report_fatal_error("COFF string table is greater than 64 GB."); } void WinCOFFObjectWriter::SetSymbolName(COFFSymbol &S) { From cefe6876d6e55ee8d544ab98216251ddd35ee7a9 Mon Sep 17 00:00:00 2001 From: Nicolas Miller Date: Sat, 19 Feb 2022 20:28:38 +0200 Subject: [PATCH 157/316] [llvm-objcopy][COFF] Fix section name encoding The section name encoding for `llvm-objcopy` had two main issues, the first is that the size used for the `snprintf` in the original code is incorrect because `snprintf` adds a null byte, so this code was only able to encode offsets of 6 digits - `/`, `\0` and 6 digits of the offset - rather than the 7 digits it should support. And the second part is that it didn't support the base64 encoding for offsets larger than 7 digits. This issue specifically showed up when using the `clang-offload-bundler` with a binary containing a lot of symbols/sections, since it uses `llvm-objcopy` to add the sections containing the offload code. Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D118692 (cherry picked from commit ddf528b7a092fd24647d7c6186ece7392c92de92) --- .../llvm-objcopy/COFF/section-name-encoding.s | 95 +++++++++++++++++++ llvm/tools/llvm-objcopy/CMakeLists.txt | 1 + llvm/tools/llvm-objcopy/COFF/Writer.cpp | 21 ++-- llvm/tools/llvm-objcopy/COFF/Writer.h | 2 +- 4 files changed, 112 insertions(+), 7 deletions(-) create mode 100644 llvm/test/tools/llvm-objcopy/COFF/section-name-encoding.s diff --git a/llvm/test/tools/llvm-objcopy/COFF/section-name-encoding.s b/llvm/test/tools/llvm-objcopy/COFF/section-name-encoding.s new file mode 100644 index 0000000000000..bd8b7c1bcf960 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/COFF/section-name-encoding.s @@ -0,0 +1,95 @@ +## Check that COFF section names of sections added by llvm-objcopy are properly +## encoded. +## +## Encodings for different name lengths and string table index: +## [0, 8]: raw name +## (8, 999999]: base 10 string table index (/9999999) +## (999999, 0xFFFFFFFF]: base 64 string table index (##AAAAAA) +## +## Note: the names in the string table will be sorted in reverse +## lexicographical order. Use a suffix letter (z, y, x, ...) to +## get the preferred ordering of names in the test. +## +# REQUIRES: x86-registered-target +## +# RUN: echo DEADBEEF > %t.sec +# RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s -o %t.obj +# RUN: llvm-objcopy --add-section=s1234567=%t.sec \ +# RUN: --add-section=s1234567z=%t.sec \ +# RUN: --add-section=sevendigitx=%t.sec \ +# RUN: --add-section=doubleslashv=%t.sec \ +# RUN: %t.obj %t +# RUN: llvm-readobj --sections %t | FileCheck %s + +## Raw encoding + +# CHECK: Section { +# CHECK: Number: 14 +# CHECK: Name: s1234567 (73 31 32 33 34 35 36 37) +# CHECK: } + +## Base 10 encoding with a small offset, section name at the beginning of the +## string table. + +## /4 +## +# CHECK: Section { +# CHECK: Number: 15 +# CHECK: Name: s1234567z (2F 34 00 00 00 00 00 00) +# CHECK: } + +## Base 10 encoding with a 7 digit offset, section name after the y padding in +## the string table. + +## /1000029 == 4 + 10 + (5 * (2 + (20 * 10 * 1000) + 1)) +## v | | v ~~~~~~~~~~~~~~ v +## table size v v "p0" y pad NULL separator +## "s1234567z\0" # of pad sections +## +# CHECK: Section { +# CHECK: Number: 16 +# CHECK: Name: sevendigitx (2F 31 30 30 30 30 32 39) +# CHECK: } + +## Base 64 encoding, section name after the w padding in the string table. + +## //AAmJa4 == 1000029 + 12 + (5 * (2 + (9 * 20 * 10 * 1000) + 1)) == 38*64^3 + 9*64^2 + 26*64 + 56 +## v | | v ~~~~~~~~~~~~~~~~~~ v +## sevendigitx offset v v "p0" w pad NULL separator +## "sevendigitx\0" # of pad sections +## +## "2F 2F 41 41 6D 4A 61 34" is "//AAmJa4", which decodes to "0 0 38 9 26 56". +## +# CHECK: Section { +# CHECK: Number: 17 +# CHECK: Name: doubleslashv (2F 2F 41 41 6D 4A 61 34) +# CHECK: } + +## Generate padding sections to increase the string table size to at least +## 1,000,000 bytes. +.macro pad_sections2 pad + ## 10x \pad + .section p0\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1 + .section p1\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1 + .section p2\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1 + .section p3\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1 + .section p4\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1 +.endm + +.macro pad_sections pad + ## 20x \pad + pad_sections2 \pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad +.endm + +## 1000x 'y' +pad_sections yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy + +## Generate padding sections to increase the string table size to at least +## 10,000,000 bytes. +.macro pad_sections_ex pad + ## 9x \pad + pad_sections \pad\pad\pad\pad\pad\pad\pad\pad\pad +.endm + +## 1000x 'w' +pad_sections_ex wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww diff --git a/llvm/tools/llvm-objcopy/CMakeLists.txt b/llvm/tools/llvm-objcopy/CMakeLists.txt index d14d2135f5db7..94d897d759441 100644 --- a/llvm/tools/llvm-objcopy/CMakeLists.txt +++ b/llvm/tools/llvm-objcopy/CMakeLists.txt @@ -3,6 +3,7 @@ set(LLVM_LINK_COMPONENTS Option Support MC + BinaryFormat ) set(LLVM_TARGET_DEFINITIONS ObjcopyOpts.td) diff --git a/llvm/tools/llvm-objcopy/COFF/Writer.cpp b/llvm/tools/llvm-objcopy/COFF/Writer.cpp index cbd0e42612387..fcbfef96d8609 100644 --- a/llvm/tools/llvm-objcopy/COFF/Writer.cpp +++ b/llvm/tools/llvm-objcopy/COFF/Writer.cpp @@ -116,7 +116,7 @@ void COFFWriter::layoutSections() { } } -size_t COFFWriter::finalizeStringTable() { +Expected COFFWriter::finalizeStringTable() { for (const auto &S : Obj.getSections()) if (S.Name.size() > COFF::NameSize) StrTabBuilder.add(S.Name); @@ -129,11 +129,16 @@ size_t COFFWriter::finalizeStringTable() { for (auto &S : Obj.getMutableSections()) { memset(S.Header.Name, 0, sizeof(S.Header.Name)); - if (S.Name.size() > COFF::NameSize) { - snprintf(S.Header.Name, sizeof(S.Header.Name), "/%d", - (int)StrTabBuilder.getOffset(S.Name)); - } else { + if (S.Name.size() <= COFF::NameSize) { + // Short names can go in the field directly. memcpy(S.Header.Name, S.Name.data(), S.Name.size()); + } else { + // Offset of the section name in the string table. + size_t Offset = StrTabBuilder.getOffset(S.Name); + if (!COFF::encodeSectionName(S.Header.Name, Offset)) + return createStringError(object_error::invalid_section_index, + "COFF string table is greater than 64GB, " + "unable to encode section name offset"); } } for (auto &S : Obj.getMutableSymbols()) { @@ -219,7 +224,11 @@ Error COFFWriter::finalize(bool IsBigObj) { Obj.PeHeader.CheckSum = 0; } - size_t StrTabSize = finalizeStringTable(); + Expected StrTabSizeOrErr = finalizeStringTable(); + if (!StrTabSizeOrErr) + return StrTabSizeOrErr.takeError(); + + size_t StrTabSize = *StrTabSizeOrErr; size_t PointerToSymbolTable = FileSize; // StrTabSize <= 4 is the size of an empty string table, only consisting diff --git a/llvm/tools/llvm-objcopy/COFF/Writer.h b/llvm/tools/llvm-objcopy/COFF/Writer.h index eed43b3e58146..5758aadb54399 100644 --- a/llvm/tools/llvm-objcopy/COFF/Writer.h +++ b/llvm/tools/llvm-objcopy/COFF/Writer.h @@ -35,7 +35,7 @@ class COFFWriter { Error finalizeRelocTargets(); Error finalizeSymbolContents(); void layoutSections(); - size_t finalizeStringTable(); + Expected finalizeStringTable(); Error finalize(bool IsBigObj); From 88f8980a4d95b16a0dcd57bb6da298d4d60d8fd1 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin Date: Thu, 17 Feb 2022 16:00:36 +0000 Subject: [PATCH 158/316] [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo Currently, loading from or storing to a stack location with a structured load or store crashes in isAArch64FrameOffsetLegal as the opcodes are not handled by getMemOpInfo. This patch adds the opcodes for structured load/store instructions with an immediate index to getMemOpInfo & getLoadStoreImmIdx, setting appropriate values for the scale, width & min/max offsets. Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D119338 (cherry picked from commit fc1b21228e39d63f1a2ab98026d548de66cb3760) --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 65 +++++ .../CodeGen/AArch64/sve-fixed-ld2-alloca.ll | 27 ++ llvm/test/CodeGen/AArch64/sve-ldN.mir | 261 ++++++++++++++++++ llvm/test/CodeGen/AArch64/sve-stN.mir | 261 ++++++++++++++++++ 4 files changed, 614 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-ldN.mir create mode 100644 llvm/test/CodeGen/AArch64/sve-stN.mir diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index a9191924129c6..ea9c1b620065d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2270,6 +2270,19 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) { case AArch64::LD1SW_D_IMM: case AArch64::LD1D_IMM: + case AArch64::LD2B_IMM: + case AArch64::LD2H_IMM: + case AArch64::LD2W_IMM: + case AArch64::LD2D_IMM: + case AArch64::LD3B_IMM: + case AArch64::LD3H_IMM: + case AArch64::LD3W_IMM: + case AArch64::LD3D_IMM: + case AArch64::LD4B_IMM: + case AArch64::LD4H_IMM: + case AArch64::LD4W_IMM: + case AArch64::LD4D_IMM: + case AArch64::ST1B_IMM: case AArch64::ST1B_H_IMM: case AArch64::ST1B_S_IMM: @@ -2281,6 +2294,19 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) { case AArch64::ST1W_D_IMM: case AArch64::ST1D_IMM: + case AArch64::ST2B_IMM: + case AArch64::ST2H_IMM: + case AArch64::ST2W_IMM: + case AArch64::ST2D_IMM: + case AArch64::ST3B_IMM: + case AArch64::ST3H_IMM: + case AArch64::ST3W_IMM: + case AArch64::ST3D_IMM: + case AArch64::ST4B_IMM: + case AArch64::ST4H_IMM: + case AArch64::ST4W_IMM: + case AArch64::ST4D_IMM: + case AArch64::LD1RB_IMM: case AArch64::LD1RB_H_IMM: case AArch64::LD1RB_S_IMM: @@ -2897,6 +2923,45 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale, MinOffset = -8; MaxOffset = 7; break; + case AArch64::LD2B_IMM: + case AArch64::LD2H_IMM: + case AArch64::LD2W_IMM: + case AArch64::LD2D_IMM: + case AArch64::ST2B_IMM: + case AArch64::ST2H_IMM: + case AArch64::ST2W_IMM: + case AArch64::ST2D_IMM: + Scale = TypeSize::Scalable(32); + Width = SVEMaxBytesPerVector * 2; + MinOffset = -8; + MaxOffset = 7; + break; + case AArch64::LD3B_IMM: + case AArch64::LD3H_IMM: + case AArch64::LD3W_IMM: + case AArch64::LD3D_IMM: + case AArch64::ST3B_IMM: + case AArch64::ST3H_IMM: + case AArch64::ST3W_IMM: + case AArch64::ST3D_IMM: + Scale = TypeSize::Scalable(48); + Width = SVEMaxBytesPerVector * 3; + MinOffset = -8; + MaxOffset = 7; + break; + case AArch64::LD4B_IMM: + case AArch64::LD4H_IMM: + case AArch64::LD4W_IMM: + case AArch64::LD4D_IMM: + case AArch64::ST4B_IMM: + case AArch64::ST4H_IMM: + case AArch64::ST4W_IMM: + case AArch64::ST4D_IMM: + Scale = TypeSize::Scalable(64); + Width = SVEMaxBytesPerVector * 4; + MinOffset = -8; + MaxOffset = 7; + break; case AArch64::LD1B_H_IMM: case AArch64::LD1SB_H_IMM: case AArch64::LD1H_S_IMM: diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll new file mode 100644 index 0000000000000..f59891c31e934 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define void @st1d_fixed(<8 x double>* %ptr) #0 { +; CHECK-LABEL: st1d_fixed: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: add x8, sp, #8 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8] +; CHECK-NEXT: mov x8, #4 +; CHECK-NEXT: mov z0.d, #0 // =0x0 +; CHECK-NEXT: st1d { z0.d }, p0, [x0] +; CHECK-NEXT: st1d { z0.d }, p0, [x0, x8, lsl #3] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %alloc = alloca [16 x double], i32 0 + %bc = bitcast [16 x double]* %alloc to <8 x double>* + %load = load <8 x double>, <8 x double>* %bc + %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> + store <8 x double> zeroinitializer, <8 x double>* %ptr + ret void +} + +attributes #0 = { "target-features"="+sve" vscale_range(2,2) nounwind } diff --git a/llvm/test/CodeGen/AArch64/sve-ldN.mir b/llvm/test/CodeGen/AArch64/sve-ldN.mir new file mode 100644 index 0000000000000..c59c53da806ba --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-ldN.mir @@ -0,0 +1,261 @@ +# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET + +--- | + define void @testcase_valid_offset() nounwind { entry: unreachable } + define void @testcase_offset_out_of_range() nounwind { entry: unreachable } +... +--- +name: testcase_valid_offset +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 512, alignment: 16, stack-id: scalable-vector } +body: | + bb.0: + liveins: $p0 + + ; CHECK-LABEL: name: testcase_valid_offset + ; CHECK: liveins: $p0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.1) + ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -32 + ; CHECK-NEXT: renamable $z0_z1 = LD2B_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1 = LD2B_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1 = LD2H_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1 = LD2H_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1 = LD2W_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1 = LD2W_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1 = LD2D_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1 = LD2D_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3B_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3B_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3H_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3H_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3W_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3W_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3D_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3D_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, $sp, -8 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, $sp, 7 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 31 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 1 + ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.1) + ; CHECK-NEXT: RET_ReallyLR implicit $z0, implicit $z1, implicit $z2, implicit $z3 + + ; CHECK-OFFSET-LABEL: testcase_valid_offset: + ; CHECK-OFFSET: str x29, [sp, #-16]! + ; CHECK-OFFSET-NEXT: addvl sp, sp, #-32 + ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl sp, sp, #31 + ; CHECK-OFFSET-NEXT: addvl sp, sp, #1 + ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16 + ; CHECK-OFFSET-NEXT: ret + + renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1 = LD2W_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1 = LD2W_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1 = LD2D_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1 = LD2D_IMM renamable $p0, %stack.0, 7 + + renamable $z0_z1_z2 = LD3B_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2 = LD3B_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2 = LD3H_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2 = LD3H_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2 = LD3W_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2 = LD3W_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2 = LD3D_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2 = LD3D_IMM renamable $p0, %stack.0, 7 + + renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, %stack.0, 7 + renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, %stack.0, -8 + renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, %stack.0, 7 + RET_ReallyLR implicit $z0, implicit $z1, implicit $z2, implicit $z3 +... +--- +name: testcase_offset_out_of_range +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 512, alignment: 16, stack-id: scalable-vector } +body: | + bb.0: + liveins: $p0 + + ; CHECK-LABEL: name: testcase_offset_out_of_range + ; CHECK: liveins: $p0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.1) + ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -32 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: renamable $z0_z1 = LD2B_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: renamable $z0_z1 = LD2B_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: renamable $z0_z1 = LD2H_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: renamable $z0_z1 = LD2H_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: renamable $z0_z1 = LD2W_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: renamable $z0_z1 = LD2W_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: renamable $z0_z1 = LD2D_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: renamable $z0_z1 = LD2D_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3B_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3B_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3H_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3H_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3W_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3W_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3D_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: renamable $z0_z1_z2 = LD3D_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 31 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 1 + ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.1) + ; CHECK-NEXT: RET_ReallyLR implicit $z0, implicit $z1, implicit $z2, implicit $z3 + + ; CHECK-OFFSET-LABEL: testcase_offset_out_of_range: + ; CHECK-OFFSET: str x29, [sp, #-16]! + ; CHECK-OFFSET-NEXT: addvl sp, sp, #-32 + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: ld2b { z0.b, z1.b }, p0/z, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: ld2h { z0.h, z1.h }, p0/z, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: ld2w { z0.s, z1.s }, p0/z, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: ld2d { z0.d, z1.d }, p0/z, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: ld3b { z0.b, z1.b, z2.b }, p0/z, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: ld3w { z0.s, z1.s, z2.s }, p0/z, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: ld3d { z0.d, z1.d, z2.d }, p0/z, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl sp, sp, #31 + ; CHECK-OFFSET-NEXT: addvl sp, sp, #1 + ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16 + ; CHECK-OFFSET-NEXT: ret + + renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1 = LD2B_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1 = LD2H_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1 = LD2W_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1 = LD2W_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1 = LD2D_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1 = LD2D_IMM renamable $p0, %stack.0, 8 + + renamable $z0_z1_z2 = LD3B_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2 = LD3B_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2 = LD3H_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2 = LD3H_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2 = LD3W_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2 = LD3W_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2 = LD3D_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2 = LD3D_IMM renamable $p0, %stack.0, 8 + + renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2_z3 = LD4B_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2_z3 = LD4H_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2_z3 = LD4W_IMM renamable $p0, %stack.0, 8 + renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, %stack.0, -9 + renamable $z0_z1_z2_z3 = LD4D_IMM renamable $p0, %stack.0, 8 + RET_ReallyLR implicit $z0, implicit $z1, implicit $z2, implicit $z3 +... diff --git a/llvm/test/CodeGen/AArch64/sve-stN.mir b/llvm/test/CodeGen/AArch64/sve-stN.mir new file mode 100644 index 0000000000000..ac5c036a10bd0 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-stN.mir @@ -0,0 +1,261 @@ +# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET + +--- | + define void @testcase_valid_offset() nounwind { entry: unreachable } + define void @testcase_offset_out_of_range() nounwind { entry: unreachable } +... +--- +name: testcase_valid_offset +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 512, alignment: 16, stack-id: scalable-vector } +body: | + bb.0: + liveins: $p0, $z0 + + ; CHECK-LABEL: name: testcase_valid_offset + ; CHECK: liveins: $p0, $z0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.1) + ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -32 + ; CHECK-NEXT: ST2B_IMM renamable $z0_z1, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST2B_IMM renamable $z0_z1, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST2H_IMM renamable $z0_z1, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST2H_IMM renamable $z0_z1, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST2W_IMM renamable $z0_z1, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST2W_IMM renamable $z0_z1, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST2D_IMM renamable $z0_z1, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST2D_IMM renamable $z0_z1, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST3B_IMM renamable $z0_z1_z2, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST3B_IMM renamable $z0_z1_z2, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST3H_IMM renamable $z0_z1_z2, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST3H_IMM renamable $z0_z1_z2, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST3W_IMM renamable $z0_z1_z2, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST3W_IMM renamable $z0_z1_z2, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST3D_IMM renamable $z0_z1_z2, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST3D_IMM renamable $z0_z1_z2, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, 7 + ; CHECK-NEXT: ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, -8 + ; CHECK-NEXT: ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, $sp, 7 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 31 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 1 + ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.1) + ; CHECK-NEXT: RET_ReallyLR + + ; CHECK-OFFSET-LABEL: testcase_valid_offset: + ; CHECK-OFFSET: str x29, [sp, #-16]! + ; CHECK-OFFSET-NEXT: addvl sp, sp, #-32 + ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [sp, #-16, mul vl] + ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [sp, #14, mul vl] + ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [sp, #-24, mul vl] + ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [sp, #21, mul vl] + ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [sp, #-32, mul vl] + ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [sp, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl sp, sp, #31 + ; CHECK-OFFSET-NEXT: addvl sp, sp, #1 + ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16 + ; CHECK-OFFSET-NEXT: ret + + ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, -8 + ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, 7 + ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, -8 + ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, 7 + ST2W_IMM renamable $z0_z1, renamable $p0, %stack.0, -8 + ST2W_IMM renamable $z0_z1, renamable $p0, %stack.0, 7 + ST2D_IMM renamable $z0_z1, renamable $p0, %stack.0, -8 + ST2D_IMM renamable $z0_z1, renamable $p0, %stack.0, 7 + + ST3B_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -8 + ST3B_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 7 + ST3H_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -8 + ST3H_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 7 + ST3W_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -8 + ST3W_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 7 + ST3D_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -8 + ST3D_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 7 + + ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -8 + ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 7 + ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -8 + ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 7 + ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -8 + ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 7 + ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -8 + ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 7 + RET_ReallyLR +... +--- +name: testcase_offset_out_of_range +tracksRegLiveness: true +stack: + - { id: 0, name: '', type: default, offset: 0, size: 512, alignment: 16, stack-id: scalable-vector } +body: | + bb.0: + liveins: $p0, $z0 + + ; CHECK-LABEL: name: testcase_offset_out_of_range + ; CHECK: liveins: $p0, $z0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.1) + ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -32 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: ST2B_IMM renamable $z0_z1, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: ST2B_IMM renamable $z0_z1, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: ST2H_IMM renamable $z0_z1, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: ST2H_IMM renamable $z0_z1, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: ST2W_IMM renamable $z0_z1, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: ST2W_IMM renamable $z0_z1, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -2 + ; CHECK-NEXT: ST2D_IMM renamable $z0_z1, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 2 + ; CHECK-NEXT: ST2D_IMM renamable $z0_z1, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: ST3B_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: ST3B_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: ST3H_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: ST3H_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: ST3W_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: ST3W_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -3 + ; CHECK-NEXT: ST3D_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 3 + ; CHECK-NEXT: ST3D_IMM renamable $z0_z1_z2, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -4 + ; CHECK-NEXT: ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, -8 + ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 4 + ; CHECK-NEXT: ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, killed $x8, 7 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 31 + ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 1 + ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.1) + ; CHECK-NEXT: RET_ReallyLR + + ; CHECK-OFFSET-LABEL: testcase_offset_out_of_range + ; CHECK-OFFSET: str x29, [sp, #-16]! + ; CHECK-OFFSET-NEXT: addvl sp, sp, #-32 + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: st2b { z0.b, z1.b }, p0, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: st2h { z0.h, z1.h }, p0, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: st2w { z0.s, z1.s }, p0, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-2 + ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [x8, #-16, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #2 + ; CHECK-OFFSET-NEXT: st2d { z0.d, z1.d }, p0, [x8, #14, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-3 + ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x8, #-24, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #3 + ; CHECK-OFFSET-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x8, #21, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #-4 + ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x8, #-32, mul vl] + ; CHECK-OFFSET-NEXT: addvl x8, sp, #4 + ; CHECK-OFFSET-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x8, #28, mul vl] + ; CHECK-OFFSET-NEXT: addvl sp, sp, #31 + ; CHECK-OFFSET-NEXT: addvl sp, sp, #1 + ; CHECK-OFFSET-NEXT: ldr x29, [sp], #16 + ; CHECK-OFFSET-NEXT: ret + + ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, -9 + ST2B_IMM renamable $z0_z1, renamable $p0, %stack.0, 8 + ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, -9 + ST2H_IMM renamable $z0_z1, renamable $p0, %stack.0, 8 + ST2W_IMM renamable $z0_z1, renamable $p0, %stack.0, -9 + ST2W_IMM renamable $z0_z1, renamable $p0, %stack.0, 8 + ST2D_IMM renamable $z0_z1, renamable $p0, %stack.0, -9 + ST2D_IMM renamable $z0_z1, renamable $p0, %stack.0, 8 + + ST3B_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -9 + ST3B_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 8 + ST3H_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -9 + ST3H_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 8 + ST3W_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -9 + ST3W_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 8 + ST3D_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, -9 + ST3D_IMM renamable $z0_z1_z2, renamable $p0, %stack.0, 8 + + ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -9 + ST4B_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 8 + ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -9 + ST4H_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 8 + ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -9 + ST4W_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 8 + ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, -9 + ST4D_IMM renamable $z0_z1_z2_z3, renamable $p0, %stack.0, 8 + RET_ReallyLR +... From 1362f8bdfce732d99ad28556dcff4a0bcb391528 Mon Sep 17 00:00:00 2001 From: Bradley Smith Date: Thu, 10 Feb 2022 12:38:02 +0000 Subject: [PATCH 159/316] [AArch64][SVE] Fix selection failure caused by fp/int convert using non-Neon types Fixes: #53679 Differential Revision: https://reviews.llvm.org/D119428 (cherry picked from commit c53ad72aa93646a3ab1b9b2307319a7389a51039) --- .../Target/AArch64/AArch64ISelLowering.cpp | 6 +++-- .../AArch64/sve-fixed-length-fp-convert.ll | 25 +++++++++++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index c539c8617d99d..792e45bdb0ddc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -13676,8 +13676,10 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || - Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isSimple() || Op.getOpcode() != ISD::FMUL) + return SDValue(); + + if (!Op.getValueType().is64BitVector() && !Op.getValueType().is128BitVector()) return SDValue(); SDValue ConstVec = Op->getOperand(1); diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll new file mode 100644 index 0000000000000..72d0a5657f3cf --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; Ensure we don't crash when trying to combine fp<->int conversions +define void @fp_convert_combine_crash(<8 x float> *%a, <8 x i32> *%b) #0 { +; CHECK-LABEL: fp_convert_combine_crash: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fmov z1.s, #8.00000000 +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: fmul z0.s, z0.s, z1.s +; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-NEXT: st1w { z0.s }, p0, [x1] +; CHECK-NEXT: ret + %f = load <8 x float>, <8 x float>* %a + %mul.i = fmul <8 x float> %f, + %vcvt.i = fptosi <8 x float> %mul.i to <8 x i32> + store <8 x i32> %vcvt.i, <8 x i32>* %b + ret void +} + +attributes #0 = { vscale_range(2,2) "target-features"="+sve" } From 8c33ea3ab0ef304e6f43be31e9c72660a6261bf7 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Tue, 4 Jan 2022 13:11:47 +0000 Subject: [PATCH 160/316] [SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle Previously the code in AArch64TargetLowering::ReconstructShuffle assumed the input vectors were always fixed-width, however this is not always the case since you can extract elements from scalable vectors and insert into fixed-width ones. We were hitting crashes here for two different cases: 1. When lowering a fixed-length vector extract from a scalable vector with i1 element types. This happens due to the fact the i1 elements get promoted to larger integer types for fixed-width vectors and leads to sequences of INSERT_VECTOR_ELT and EXTRACT_VECTOR_ELT nodes. In this case AArch64TargetLowering::ReconstructShuffle will still fail to make a transformation, but at least it no longer crashes. 2. When lowering a sequence of extractelement/insertelement operations on mixed fixed-width/scalable vectors. For now, I've just changed AArch64TargetLowering::ReconstructShuffle to bail out if it finds a scalable vector. Tests for both instances described above have been added here: (1) CodeGen/AArch64/sve-extract-fixed-vector.ll (2) CodeGen/AArch64/sve-fixed-length-reshuffle.ll Differential Revision: https://reviews.llvm.org/D116602 (cherry picked from commit a57a7f3de551bd0ae4e27b1f0c85437cd3e2e834) --- .../Target/AArch64/AArch64ISelLowering.cpp | 15 +-- .../AArch64/sve-extract-fixed-vector.ll | 105 ++++++++++++++++++ .../AArch64/sve-fixed-length-reshuffle.ll | 32 ++++++ 3 files changed, 145 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 792e45bdb0ddc..aa2dca3eda4b8 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -8990,12 +8990,13 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, if (V.isUndef()) continue; else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || - !isa(V.getOperand(1))) { + !isa(V.getOperand(1)) || + V.getOperand(0).getValueType().isScalableVector()) { LLVM_DEBUG( dbgs() << "Reshuffle failed: " "a shuffle can only come from building a vector from " - "various elements of other vectors, provided their " - "indices are constant\n"); + "various elements of other fixed-width vectors, provided " + "their indices are constant\n"); return SDValue(); } @@ -9039,8 +9040,8 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, for (auto &Src : Sources) { EVT SrcVT = Src.ShuffleVec.getValueType(); - uint64_t SrcVTSize = SrcVT.getFixedSizeInBits(); - if (SrcVTSize == VTSize) + TypeSize SrcVTSize = SrcVT.getSizeInBits(); + if (SrcVTSize == TypeSize::Fixed(VTSize)) continue; // This stage of the search produces a source with the same element type as @@ -9049,7 +9050,7 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits(); EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); - if (SrcVTSize < VTSize) { + if (SrcVTSize.getFixedValue() < VTSize) { assert(2 * SrcVTSize == VTSize); // We can pad out the smaller vector for free, so if it's part of a // shuffle... @@ -9059,7 +9060,7 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, continue; } - if (SrcVTSize != 2 * VTSize) { + if (SrcVTSize.getFixedValue() != 2 * VTSize) { LLVM_DEBUG( dbgs() << "Reshuffle failed: result vector too small to extract\n"); return SDValue(); diff --git a/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll b/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll index 3be4b94dedd22..a3d161ec41026 100644 --- a/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll @@ -361,6 +361,106 @@ define <16 x i8> @extract_v16i8_nxv2i8_idx16( %vec) nounwind #1 ret <16 x i8> %retval } + +; Predicates + +define <2 x i1> @extract_v2i1_nxv2i1( %inmask) { +; CHECK-LABEL: extract_v2i1_nxv2i1: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z0.d, p0/z, #1 // =0x1 +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: mov x8, v0.d[1] +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: mov v0.s[1], w8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %mask = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1( %inmask, i64 0) + ret <2 x i1> %mask +} + +define <4 x i1> @extract_v4i1_nxv4i1( %inmask) { +; CHECK-LABEL: extract_v4i1_nxv4i1: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1 +; CHECK-NEXT: mov w8, v1.s[1] +; CHECK-NEXT: mov w9, v1.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: mov v0.h[1], w8 +; CHECK-NEXT: mov w8, v1.s[3] +; CHECK-NEXT: mov v0.h[2], w9 +; CHECK-NEXT: mov v0.h[3], w8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %mask = call <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1( %inmask, i64 0) + ret <4 x i1> %mask +} + +define <8 x i1> @extract_v8i1_nxv8i1( %inmask) { +; CHECK-LABEL: extract_v8i1_nxv8i1: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1 +; CHECK-NEXT: umov w8, v1.h[1] +; CHECK-NEXT: umov w9, v1.h[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: mov v0.b[1], w8 +; CHECK-NEXT: umov w8, v1.h[3] +; CHECK-NEXT: mov v0.b[2], w9 +; CHECK-NEXT: umov w9, v1.h[4] +; CHECK-NEXT: mov v0.b[3], w8 +; CHECK-NEXT: umov w8, v1.h[5] +; CHECK-NEXT: mov v0.b[4], w9 +; CHECK-NEXT: umov w9, v1.h[6] +; CHECK-NEXT: mov v0.b[5], w8 +; CHECK-NEXT: umov w8, v1.h[7] +; CHECK-NEXT: mov v0.b[6], w9 +; CHECK-NEXT: mov v0.b[7], w8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %mask = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1( %inmask, i64 0) + ret <8 x i1> %mask +} + +define <16 x i1> @extract_v16i1_nxv16i1( %inmask) { +; CHECK-LABEL: extract_v16i1_nxv16i1: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1 +; CHECK-NEXT: umov w8, v1.b[1] +; CHECK-NEXT: umov w9, v1.b[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: mov v0.b[1], w8 +; CHECK-NEXT: umov w8, v1.b[3] +; CHECK-NEXT: mov v0.b[2], w9 +; CHECK-NEXT: umov w9, v1.b[4] +; CHECK-NEXT: mov v0.b[3], w8 +; CHECK-NEXT: umov w8, v1.b[5] +; CHECK-NEXT: mov v0.b[4], w9 +; CHECK-NEXT: umov w9, v1.b[6] +; CHECK-NEXT: mov v0.b[5], w8 +; CHECK-NEXT: umov w8, v1.b[7] +; CHECK-NEXT: mov v0.b[6], w9 +; CHECK-NEXT: umov w9, v1.b[8] +; CHECK-NEXT: mov v0.b[7], w8 +; CHECK-NEXT: umov w8, v1.b[9] +; CHECK-NEXT: mov v0.b[8], w9 +; CHECK-NEXT: umov w9, v1.b[10] +; CHECK-NEXT: mov v0.b[9], w8 +; CHECK-NEXT: umov w8, v1.b[11] +; CHECK-NEXT: mov v0.b[10], w9 +; CHECK-NEXT: umov w9, v1.b[12] +; CHECK-NEXT: mov v0.b[11], w8 +; CHECK-NEXT: umov w8, v1.b[13] +; CHECK-NEXT: mov v0.b[12], w9 +; CHECK-NEXT: umov w9, v1.b[14] +; CHECK-NEXT: mov v0.b[13], w8 +; CHECK-NEXT: umov w8, v1.b[15] +; CHECK-NEXT: mov v0.b[14], w9 +; CHECK-NEXT: mov v0.b[15], w8 +; CHECK-NEXT: ret + %mask = call <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1( %inmask, i64 0) + ret <16 x i1> %mask +} + + ; Fixed length clamping define <2 x i64> @extract_fixed_v2i64_nxv2i64( %vec) nounwind #0 { @@ -441,4 +541,9 @@ declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv8i8( @llvm.experimental.vector.extract.v16i8.nxv4i8(, i64) declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv2i8(, i64) +declare <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(, i64) +declare <4 x i1> @llvm.experimental.vector.extract.v4i1.nxv4i1(, i64) +declare <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv8i1(, i64) +declare <16 x i1> @llvm.experimental.vector.extract.v16i1.nxv16i1(, i64) + declare <4 x i64> @llvm.experimental.vector.extract.v4i64.nxv2i64(, i64) diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll new file mode 100644 index 0000000000000..c826f7337b18a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; == Matching first N elements == + +define <4 x i1> @reshuffle_v4i1_nxv4i1( %a) #0 { +; CHECK-LABEL: reshuffle_v4i1_nxv4i1: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1 +; CHECK-NEXT: mov w8, v1.s[1] +; CHECK-NEXT: mov w9, v1.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: mov v0.h[1], w8 +; CHECK-NEXT: mov w8, v1.s[3] +; CHECK-NEXT: mov v0.h[2], w9 +; CHECK-NEXT: mov v0.h[3], w8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %el0 = extractelement %a, i32 0 + %el1 = extractelement %a, i32 1 + %el2 = extractelement %a, i32 2 + %el3 = extractelement %a, i32 3 + %v0 = insertelement <4 x i1> undef, i1 %el0, i32 0 + %v1 = insertelement <4 x i1> %v0, i1 %el1, i32 1 + %v2 = insertelement <4 x i1> %v1, i1 %el2, i32 2 + %v3 = insertelement <4 x i1> %v2, i1 %el3, i32 3 + ret <4 x i1> %v3 +} + +attributes #0 = { "target-features"="+sve" } From 8b5b29c4c2c541ae23bcb51c57ce4bb57de477d1 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Tue, 1 Feb 2022 13:09:54 +0000 Subject: [PATCH 161/316] Fix incorrect TypeSize->uint64_t cast in InductionDescriptor::isInductionPHI The code was relying upon the implicit conversion of TypeSize to uint64_t and assuming the type in question was always fixed. However, I discovered an issue when running the canon-freeze pass with some IR loops that contains scalable vector types. I've changed the code to bail out if the size is unknown at compile time, since we cannot compute whether the step is a multiple of the type size or not. I added a test here: Transforms/CanonicalizeFreezeInLoops/phis.ll Differential Revision: https://reviews.llvm.org/D118696 (cherry picked from commit 1badfbb4fc1a16f6dbe3b4edccdef44d9142857e) --- llvm/lib/Analysis/IVDescriptors.cpp | 8 +++- llvm/unittests/Analysis/IVDescriptorsTest.cpp | 41 +++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp index 44b1d94ebdc80..74b0d6751023a 100644 --- a/llvm/lib/Analysis/IVDescriptors.cpp +++ b/llvm/lib/Analysis/IVDescriptors.cpp @@ -1428,10 +1428,14 @@ bool InductionDescriptor::isInductionPHI( ConstantInt *CV = ConstStep->getValue(); const DataLayout &DL = Phi->getModule()->getDataLayout(); - int64_t Size = static_cast(DL.getTypeAllocSize(ElementType)); - if (!Size) + TypeSize TySize = DL.getTypeAllocSize(ElementType); + // TODO: We could potentially support this for scalable vectors if we can + // prove at compile time that the constant step is always a multiple of + // the scalable type. + if (TySize.isZero() || TySize.isScalable()) return false; + int64_t Size = static_cast(TySize.getFixedSize()); int64_t CVSize = CV->getSExtValue(); if (CVSize % Size) return false; diff --git a/llvm/unittests/Analysis/IVDescriptorsTest.cpp b/llvm/unittests/Analysis/IVDescriptorsTest.cpp index 1f63db3ff31cd..e7948db10ae66 100644 --- a/llvm/unittests/Analysis/IVDescriptorsTest.cpp +++ b/llvm/unittests/Analysis/IVDescriptorsTest.cpp @@ -97,6 +97,47 @@ for.end: }); } +TEST(IVDescriptorsTest, LoopWithScalableTypes) { + // Parse the module. + LLVMContext Context; + + std::unique_ptr M = + parseIR(Context, + R"(define void @foo(* %ptr) { +entry: + br label %for.body + +for.body: + %lsr.iv1 = phi * [ %0, %for.body ], [ %ptr, %entry ] + %j.0117 = phi i64 [ %inc, %for.body ], [ 0, %entry ] + %lsr.iv12 = bitcast * %lsr.iv1 to i8* + %inc = add nuw nsw i64 %j.0117, 1 + %uglygep = getelementptr i8, i8* %lsr.iv12, i64 4 + %0 = bitcast i8* %uglygep to * + %cmp = icmp ne i64 %inc, 1024 + br i1 %cmp, label %for.body, label %end + +end: + ret void +})"); + + runWithLoopInfoAndSE( + *M, "foo", [&](Function &F, LoopInfo &LI, ScalarEvolution &SE) { + Function::iterator FI = F.begin(); + // First basic block is entry - skip it. + BasicBlock *Header = &*(++FI); + assert(Header->getName() == "for.body"); + Loop *L = LI.getLoopFor(Header); + EXPECT_NE(L, nullptr); + PHINode *Inst_iv = dyn_cast(&Header->front()); + assert(Inst_iv->getName() == "lsr.iv1"); + InductionDescriptor IndDesc; + bool IsInductionPHI = + InductionDescriptor::isInductionPHI(Inst_iv, L, &SE, IndDesc); + EXPECT_FALSE(IsInductionPHI); + }); +} + // Depending on how SCEV deals with ptrtoint cast, the step of a phi could be // a pointer, and InductionDescriptor used to fail with an assertion. // So just check that it doesn't assert. From 03d9a4094763b33be4e1ae908f5ff9a1787cf8d3 Mon Sep 17 00:00:00 2001 From: Bradley Smith Date: Tue, 8 Feb 2022 16:01:13 +0000 Subject: [PATCH 162/316] [AArch64][SVE] Fix selection failure during lowering of shuffle_vector The lowering code for shuffle_vector has a code path that looks through extract_subvector, this code path did not properly account for the potential presense of larger than Neon vector types and could produce unselectable DAG nodes. Differential Revision: https://reviews.llvm.org/D119252 (cherry picked from commit 98936aee7d41f9ae60dd06558fbbb1e6a4a89e17) --- .../Target/AArch64/AArch64ISelLowering.cpp | 4 ++++ .../AArch64/sve-fixed-length-shuffles.ll | 22 +++++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index aa2dca3eda4b8..ac5e51e47ddf1 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9733,6 +9733,10 @@ static SDValue constructDup(SDValue V, int Lane, SDLoc dl, EVT VT, if (ExtIdxInBits % CastedEltBitWidth != 0) return false; + // Can't handle cases where vector size is not 128-bit + if (!Extract.getOperand(0).getValueType().is128BitVector()) + return false; + // Update the lane value by offsetting with the scaled extract index. LaneC += ExtIdxInBits / CastedEltBitWidth; diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll index 4e53128e13469..98f4077ef85da 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll @@ -1,4 +1,4 @@ -; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s +; RUN: llc < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" @@ -14,4 +14,22 @@ define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32 ret void } -attributes #0 = { nounwind "target-features"="+sve" } +; Ensure we don't crash when trying to lower a shuffle via and extract +define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) #0 { +; CHECK-LABEL: crash_when_lowering_extract_shuffle: +; CHECK: ld1w { z3.s }, p0/z, [x0] +; CHECK: st1w { z3.s }, p0, [x0] + %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer + br i1 %cond, label %exit, label %vector.body + +vector.body: + %1 = load <32 x i32>, <32 x i32>* %dst, align 16 + %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1 + store <32 x i32> %predphi, <32 x i32>* %dst, align 16 + br label %exit + +exit: + ret void +} + +attributes #0 = { vscale_range(2,2) "target-features"="+sve" } From 46266b3518b6190d4eaa8e4920371c87fd784f46 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Fri, 11 Feb 2022 10:27:50 +0100 Subject: [PATCH 163/316] [mlir][sparse] Rename index_t to index_type again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While testing LLVM 14.0.0 rc1 on Solaris, I ran into a compile failure: from /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp:22: /usr/include/sys/types.h:103:16: error: conflicting declaration ‘typedef short int index_t’ 103 | typedef short index_t; | ^~~~~~~ In file included from /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp:17: /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/mlir/include/mlir/ExecutionEngine/SparseTensorUtils.h:26:7: note: previous declaration as ‘using index_t = uint64_t’ 26 | using index_t = uint64_t; | ^~~~~~~ The same issue had already occured in the past and fixed in D72619 . More detailed explanation can also be found there. Tested on `amd64-pc-solaris2.11` and `sparcv9-solaris2.11`. Differential Revision: https://reviews.llvm.org/D119323 (cherry picked from commit d2215e79ac27301c2a7cad36b5bfe20bd12837fb) --- .../mlir/ExecutionEngine/SparseTensorUtils.h | 2 +- .../lib/ExecutionEngine/SparseTensorUtils.cpp | 53 ++++++++++--------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/mlir/include/mlir/ExecutionEngine/SparseTensorUtils.h b/mlir/include/mlir/ExecutionEngine/SparseTensorUtils.h index a1f1dd6ae32d1..52eda9bace6d7 100644 --- a/mlir/include/mlir/ExecutionEngine/SparseTensorUtils.h +++ b/mlir/include/mlir/ExecutionEngine/SparseTensorUtils.h @@ -23,7 +23,7 @@ extern "C" { /// type is 64-bit, but targets with different "index" bit widths should link /// with an alternatively built runtime support library. // TODO: support such targets? -using index_t = uint64_t; +using index_type = uint64_t; /// Encoding of overhead types (both pointer overhead and indices /// overhead), for "overloading" @newSparseTensor. diff --git a/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp b/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp index 605e17764773f..665dd8663a6c2 100644 --- a/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp +++ b/mlir/lib/ExecutionEngine/SparseTensorUtils.cpp @@ -796,7 +796,7 @@ extern "C" { #define IMPL_GETOVERHEAD(NAME, TYPE, LIB) \ void _mlir_ciface_##NAME(StridedMemRefType *ref, void *tensor, \ - index_t d) { \ + index_type d) { \ assert(ref &&tensor); \ std::vector *v; \ static_cast(tensor)->LIB(&v, d); \ @@ -808,15 +808,15 @@ extern "C" { #define IMPL_ADDELT(NAME, TYPE) \ void *_mlir_ciface_##NAME(void *tensor, TYPE value, \ - StridedMemRefType *iref, \ - StridedMemRefType *pref) { \ + StridedMemRefType *iref, \ + StridedMemRefType *pref) { \ assert(tensor &&iref &&pref); \ assert(iref->strides[0] == 1 && pref->strides[0] == 1); \ assert(iref->sizes[0] == pref->sizes[0]); \ - const index_t *indx = iref->data + iref->offset; \ - const index_t *perm = pref->data + pref->offset; \ + const index_type *indx = iref->data + iref->offset; \ + const index_type *perm = pref->data + pref->offset; \ uint64_t isize = iref->sizes[0]; \ - std::vector indices(isize); \ + std::vector indices(isize); \ for (uint64_t r = 0; r < isize; r++) \ indices[perm[r]] = indx[r]; \ static_cast *>(tensor)->add(indices, value); \ @@ -824,11 +824,12 @@ extern "C" { } #define IMPL_GETNEXT(NAME, V) \ - bool _mlir_ciface_##NAME(void *tensor, StridedMemRefType *iref, \ + bool _mlir_ciface_##NAME(void *tensor, \ + StridedMemRefType *iref, \ StridedMemRefType *vref) { \ assert(tensor &&iref &&vref); \ assert(iref->strides[0] == 1); \ - index_t *indx = iref->data + iref->offset; \ + index_type *indx = iref->data + iref->offset; \ V *value = vref->data + vref->offset; \ const uint64_t isize = iref->sizes[0]; \ auto iter = static_cast *>(tensor); \ @@ -844,30 +845,30 @@ extern "C" { } #define IMPL_LEXINSERT(NAME, V) \ - void _mlir_ciface_##NAME(void *tensor, StridedMemRefType *cref, \ - V val) { \ + void _mlir_ciface_##NAME(void *tensor, \ + StridedMemRefType *cref, V val) { \ assert(tensor &&cref); \ assert(cref->strides[0] == 1); \ - index_t *cursor = cref->data + cref->offset; \ + index_type *cursor = cref->data + cref->offset; \ assert(cursor); \ static_cast(tensor)->lexInsert(cursor, val); \ } #define IMPL_EXPINSERT(NAME, V) \ void _mlir_ciface_##NAME( \ - void *tensor, StridedMemRefType *cref, \ + void *tensor, StridedMemRefType *cref, \ StridedMemRefType *vref, StridedMemRefType *fref, \ - StridedMemRefType *aref, index_t count) { \ + StridedMemRefType *aref, index_type count) { \ assert(tensor &&cref &&vref &&fref &&aref); \ assert(cref->strides[0] == 1); \ assert(vref->strides[0] == 1); \ assert(fref->strides[0] == 1); \ assert(aref->strides[0] == 1); \ assert(vref->sizes[0] == fref->sizes[0]); \ - index_t *cursor = cref->data + cref->offset; \ + index_type *cursor = cref->data + cref->offset; \ V *values = vref->data + vref->offset; \ bool *filled = fref->data + fref->offset; \ - index_t *added = aref->data + aref->offset; \ + index_type *added = aref->data + aref->offset; \ static_cast(tensor)->expInsert( \ cursor, values, filled, added, count); \ } @@ -883,11 +884,11 @@ extern "C" { delete coo; \ } -// Assume index_t is in fact uint64_t, so that _mlir_ciface_newSparseTensor +// Assume index_type is in fact uint64_t, so that _mlir_ciface_newSparseTensor // can safely rewrite kIndex to kU64. We make this assertion to guarantee // that this file cannot get out of sync with its header. -static_assert(std::is_same::value, - "Expected index_t == uint64_t"); +static_assert(std::is_same::value, + "Expected index_type == uint64_t"); /// Constructs a new sparse tensor. This is the "swiss army knife" /// method for materializing sparse tensors into the computation. @@ -901,8 +902,8 @@ static_assert(std::is_same::value, /// kToIterator = returns iterator from storage in ptr (call getNext() to use) void * _mlir_ciface_newSparseTensor(StridedMemRefType *aref, // NOLINT - StridedMemRefType *sref, - StridedMemRefType *pref, + StridedMemRefType *sref, + StridedMemRefType *pref, OverheadType ptrTp, OverheadType indTp, PrimaryType valTp, Action action, void *ptr) { assert(aref && sref && pref); @@ -910,8 +911,8 @@ _mlir_ciface_newSparseTensor(StridedMemRefType *aref, // NOLINT pref->strides[0] == 1); assert(aref->sizes[0] == sref->sizes[0] && sref->sizes[0] == pref->sizes[0]); const DimLevelType *sparsity = aref->data + aref->offset; - const index_t *sizes = sref->data + sref->offset; - const index_t *perm = pref->data + pref->offset; + const index_type *sizes = sref->data + sref->offset; + const index_type *perm = pref->data + pref->offset; uint64_t rank = aref->sizes[0]; // Rewrite kIndex to kU64, to avoid introducing a bunch of new cases. @@ -1010,14 +1011,14 @@ _mlir_ciface_newSparseTensor(StridedMemRefType *aref, // NOLINT } /// Methods that provide direct access to pointers. -IMPL_GETOVERHEAD(sparsePointers, index_t, getPointers) +IMPL_GETOVERHEAD(sparsePointers, index_type, getPointers) IMPL_GETOVERHEAD(sparsePointers64, uint64_t, getPointers) IMPL_GETOVERHEAD(sparsePointers32, uint32_t, getPointers) IMPL_GETOVERHEAD(sparsePointers16, uint16_t, getPointers) IMPL_GETOVERHEAD(sparsePointers8, uint8_t, getPointers) /// Methods that provide direct access to indices. -IMPL_GETOVERHEAD(sparseIndices, index_t, getIndices) +IMPL_GETOVERHEAD(sparseIndices, index_type, getIndices) IMPL_GETOVERHEAD(sparseIndices64, uint64_t, getIndices) IMPL_GETOVERHEAD(sparseIndices32, uint32_t, getIndices) IMPL_GETOVERHEAD(sparseIndices16, uint16_t, getIndices) @@ -1092,7 +1093,7 @@ IMPL_OUT(outSparseTensorI8, int8_t) /// Helper method to read a sparse tensor filename from the environment, /// defined with the naming convention ${TENSOR0}, ${TENSOR1}, etc. -char *getTensorFilename(index_t id) { +char *getTensorFilename(index_type id) { char var[80]; sprintf(var, "TENSOR%" PRIu64, id); char *env = getenv(var); @@ -1100,7 +1101,7 @@ char *getTensorFilename(index_t id) { } /// Returns size of sparse tensor in given dimension. -index_t sparseDimSize(void *tensor, index_t d) { +index_type sparseDimSize(void *tensor, index_type d) { return static_cast(tensor)->getDimSize(d); } From 2fe5bf57172cebf5a3f0b3f82552cf5c2122eca2 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Thu, 10 Feb 2022 12:40:32 +0100 Subject: [PATCH 164/316] [Driver] Use libatomic for 32-bit SPARC atomics support Even after D86621 , `clang -m32` on Solaris/sparcv9 doesn't inline atomics with 8-byte operands, unlike `gcc`. This leads to many link failures in the testsuite (undefined references to `__atomic_load_8` and `__sync_val_compare_and_swap_8`. Until a proper codegen fix can be implemented, this patch works around the first of those by linking with `-latomic`. Tested on `sparcv9-sun-solaris2.11`. Differential Revision: https://reviews.llvm.org/D118021 (cherry picked from commit a6afa9e6b0d9a08ecc878e62343a2af80ff30435) --- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- clang/lib/Driver/ToolChains/CommonArgs.h | 2 ++ clang/lib/Driver/ToolChains/Solaris.cpp | 7 +++++++ clang/test/Driver/solaris-ld.c | 4 ++++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 6364cd133e0bf..dfcef2304040e 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -756,7 +756,7 @@ static bool addSanitizerDynamicList(const ToolChain &TC, const ArgList &Args, return false; } -static const char *getAsNeededOption(const ToolChain &TC, bool as_needed) { +const char *tools::getAsNeededOption(const ToolChain &TC, bool as_needed) { assert(!TC.getTriple().isOSAIX() && "AIX linker does not support any form of --as-needed option yet."); diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h b/clang/lib/Driver/ToolChains/CommonArgs.h index 646fa76949b78..23012dc247e41 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.h +++ b/clang/lib/Driver/ToolChains/CommonArgs.h @@ -117,6 +117,8 @@ bool addOpenMPRuntime(llvm::opt::ArgStringList &CmdArgs, const ToolChain &TC, bool ForceStaticHostRuntime = false, bool IsOffloadingHost = false, bool GompNeedsRT = false); +const char *getAsNeededOption(const ToolChain &TC, bool as_needed); + llvm::opt::Arg *getLastProfileUseArg(const llvm::opt::ArgList &Args); llvm::opt::Arg *getLastProfileSampleUseArg(const llvm::opt::ArgList &Args); diff --git a/clang/lib/Driver/ToolChains/Solaris.cpp b/clang/lib/Driver/ToolChains/Solaris.cpp index 4d1af094f4814..24f18b92dd661 100644 --- a/clang/lib/Driver/ToolChains/Solaris.cpp +++ b/clang/lib/Driver/ToolChains/Solaris.cpp @@ -132,6 +132,13 @@ void solaris::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-lssp_nonshared"); CmdArgs.push_back("-lssp"); } + // LLVM support for atomics on 32-bit SPARC V8+ is incomplete, so + // forcibly link with libatomic as a workaround. + if (getToolChain().getTriple().getArch() == llvm::Triple::sparc) { + CmdArgs.push_back(getAsNeededOption(getToolChain(), true)); + CmdArgs.push_back("-latomic"); + CmdArgs.push_back(getAsNeededOption(getToolChain(), false)); + } CmdArgs.push_back("-lgcc_s"); CmdArgs.push_back("-lc"); if (!Args.hasArg(options::OPT_shared)) { diff --git a/clang/test/Driver/solaris-ld.c b/clang/test/Driver/solaris-ld.c index 59d03c4d82253..d40e5dac2da9e 100644 --- a/clang/test/Driver/solaris-ld.c +++ b/clang/test/Driver/solaris-ld.c @@ -17,6 +17,7 @@ // CHECK-LD-SPARC32-SAME: "-L[[SYSROOT]]/usr/gcc/4.8/lib/gcc/sparc-sun-solaris2.11/4.8.2" // CHECK-LD-SPARC32-SAME: "-L[[SYSROOT]]/usr/gcc/4.8/lib/gcc/sparc-sun-solaris2.11/4.8.2/../../.." // CHECK-LD-SPARC32-SAME: "-L[[SYSROOT]]/usr/lib" +// CHECK-LD-SPARC32-SAME: "-zignore" "-latomic" "-zrecord" // CHECK-LD-SPARC32-SAME: "-lgcc_s" // CHECK-LD-SPARC32-SAME: "-lc" // CHECK-LD-SPARC32-SAME: "-lgcc" @@ -40,6 +41,7 @@ // CHECK-LD-SPARC64-SAME: "-L[[SYSROOT]]/usr/gcc/4.8/lib/gcc/sparc-sun-solaris2.11/4.8.2/sparcv9" // CHECK-LD-SPARC64-SAME: "-L[[SYSROOT]]/usr/gcc/4.8/lib/gcc/sparc-sun-solaris2.11/4.8.2/../../../sparcv9" // CHECK-LD-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib/sparcv9" +// CHECK-LD-SPARC64-NOT: "-latomic" // CHECK-LD-SPARC64-SAME: "-lgcc_s" // CHECK-LD-SPARC64-SAME: "-lc" // CHECK-LD-SPARC64-SAME: "-lgcc" @@ -63,6 +65,7 @@ // CHECK-LD-X32-SAME: "-L[[SYSROOT]]/usr/gcc/4.9/lib/gcc/i386-pc-solaris2.11/4.9.4" // CHECK-LD-X32-SAME: "-L[[SYSROOT]]/usr/gcc/4.9/lib/gcc/i386-pc-solaris2.11/4.9.4/../../.." // CHECK-LD-X32-SAME: "-L[[SYSROOT]]/usr/lib" +// CHECK-LD-X32-NOT: "-latomic" // CHECK-LD-X32-SAME: "-lgcc_s" // CHECK-LD-X32-SAME: "-lc" // CHECK-LD-X32-SAME: "-lgcc" @@ -86,6 +89,7 @@ // CHECK-LD-X64-SAME: "-L[[SYSROOT]]/usr/gcc/4.9/lib/gcc/i386-pc-solaris2.11/4.9.4/amd64" // CHECK-LD-X64-SAME: "-L[[SYSROOT]]/usr/gcc/4.9/lib/gcc/i386-pc-solaris2.11/4.9.4/../../../amd64" // CHECK-LD-X64-SAME: "-L[[SYSROOT]]/usr/lib/amd64" +// CHECK-LD-X64-NOT: "-latomic" // CHECK-LD-X64-SAME: "-lgcc_s" // CHECK-LD-X64-SAME: "-lc" // CHECK-LD-X64-SAME: "-lgcc" From 500889f56bce937a1263d5daf4a3bb76084ea188 Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Tue, 22 Feb 2022 16:46:28 +0300 Subject: [PATCH 165/316] [MIPS] Add `-no-pie` option to the clang driver's tests depend on it (cherry picked from commit cedc23bc8612feea61c0a7d92ccaae1ce51520ce) --- clang/test/Driver/mips-cs.cpp | 48 +++---- clang/test/Driver/mips-fsf.cpp | 208 ++++++++++++++--------------- clang/test/Driver/mips-img-v2.cpp | 24 ++-- clang/test/Driver/mips-img.cpp | 12 +- clang/test/Driver/mips-mti-linux.c | 6 +- 5 files changed, 150 insertions(+), 148 deletions(-) diff --git a/clang/test/Driver/mips-cs.cpp b/clang/test/Driver/mips-cs.cpp index 6ef4c5d4350cd..39f87d8fd8354 100644 --- a/clang/test/Driver/mips-cs.cpp +++ b/clang/test/Driver/mips-cs.cpp @@ -4,7 +4,7 @@ // // = Big-endian, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu \ +// RUN: --target=mips-linux-gnu -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32 %s // CHECK-BE-HF-32: "-internal-isystem" @@ -32,7 +32,7 @@ // // = Big-endian, hard float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -muclibc \ +// RUN: --target=mips-linux-gnu -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-HF-32 %s // CHECK-BE-UC-HF-32: "-internal-isystem" @@ -61,7 +61,7 @@ // // = Big-endian, hard float, mips16 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -mips16 \ +// RUN: --target=mips-linux-gnu -mips16 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-16 %s // CHECK-BE-HF-16: "-internal-isystem" @@ -90,7 +90,7 @@ // // = Big-endian, hard float, mmicromips // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -mmicromips \ +// RUN: --target=mips-linux-gnu -mmicromips -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-MICRO %s // CHECK-BE-HF-MICRO: "-internal-isystem" @@ -119,7 +119,7 @@ // // = Big-endian, hard float, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -mnan=2008 \ +// RUN: --target=mips-linux-gnu -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-NAN %s // CHECK-BE-HF-NAN: "-internal-isystem" @@ -148,7 +148,7 @@ // // = Big-endian, hard float, uclibc, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -muclibc -mnan=2008 \ +// RUN: --target=mips-linux-gnu -muclibc -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-HF-NAN %s // CHECK-BE-UC-HF-NAN: "-internal-isystem" @@ -177,7 +177,7 @@ // // = Big-endian, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -msoft-float \ +// RUN: --target=mips-linux-gnu -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-32 %s // CHECK-BE-SF-32: "-internal-isystem" @@ -206,7 +206,7 @@ // // = Big-endian, soft float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -muclibc -msoft-float \ +// RUN: --target=mips-linux-gnu -muclibc -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-SF-32 %s // CHECK-BE-UC-SF-32: "-internal-isystem" @@ -235,7 +235,7 @@ // // = Big-endian, soft float, mips16 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -msoft-float -mips16 \ +// RUN: --target=mips-linux-gnu -msoft-float -mips16 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-16 %s // CHECK-BE-SF-16: "-internal-isystem" @@ -264,7 +264,7 @@ // // = Big-endian, soft float, micromips // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-linux-gnu -msoft-float -mmicromips \ +// RUN: --target=mips-linux-gnu -msoft-float -mmicromips -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-MICRO %s // CHECK-BE-SF-MICRO: "-internal-isystem" @@ -293,7 +293,7 @@ // // = Big-endian, hard float, 64-bit // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-linux-gnu \ +// RUN: --target=mips64-linux-gnu -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64 %s // CHECK-BE-HF-64: "-internal-isystem" @@ -322,7 +322,7 @@ // // = Big-endian, soft float, 64-bit // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-linux-gnu -msoft-float \ +// RUN: --target=mips64-linux-gnu -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-64 %s // CHECK-BE-SF-64: "-internal-isystem" @@ -351,7 +351,7 @@ // // = Little-endian, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mhard-float \ +// RUN: --target=mipsel-linux-gnu -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-32 %s // CHECK-EL-HF-32: "-internal-isystem" @@ -380,7 +380,7 @@ // // = Little-endian, hard float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mhard-float -muclibc \ +// RUN: --target=mipsel-linux-gnu -mhard-float -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-HF-32 %s // CHECK-EL-UC-HF-32: "-internal-isystem" @@ -409,7 +409,7 @@ // // = Little-endian, hard float, mips16 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mips16 \ +// RUN: --target=mipsel-linux-gnu -mips16 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-16 %s // CHECK-EL-HF-16: "-internal-isystem" @@ -438,7 +438,7 @@ // // = Little-endian, hard float, micromips // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mmicromips \ +// RUN: --target=mipsel-linux-gnu -mmicromips -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-MICRO %s // CHECK-EL-HF-MICRO: "-internal-isystem" @@ -467,7 +467,7 @@ // // = Little-endian, hard float, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mnan=2008 \ +// RUN: --target=mipsel-linux-gnu -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-NAN %s // CHECK-EL-HF-NAN: "-internal-isystem" @@ -496,7 +496,7 @@ // // = Little-endian, hard float, uclibc, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -muclibc -mnan=2008 \ +// RUN: --target=mipsel-linux-gnu -muclibc -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-HF-NAN %s // CHECK-EL-UC-HF-NAN: "-internal-isystem" @@ -525,7 +525,7 @@ // // = Little-endian, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mfloat-abi=soft \ +// RUN: --target=mipsel-linux-gnu -mfloat-abi=soft -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-32 %s // CHECK-EL-SF-32: "-internal-isystem" @@ -554,7 +554,7 @@ // // = Little-endian, soft float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mfloat-abi=soft -muclibc \ +// RUN: --target=mipsel-linux-gnu -mfloat-abi=soft -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-SF-32 %s // CHECK-EL-UC-SF-32: "-internal-isystem" @@ -583,7 +583,7 @@ // // = Little-endian, soft float, mips16 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mips16 -msoft-float \ +// RUN: --target=mipsel-linux-gnu -mips16 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-16 %s // CHECK-EL-SF-16: "-internal-isystem" @@ -612,7 +612,7 @@ // // = Little-endian, soft float, micromips // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-linux-gnu -mmicromips -msoft-float \ +// RUN: --target=mipsel-linux-gnu -mmicromips -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-MICRO %s // CHECK-EL-SF-MICRO: "-internal-isystem" @@ -641,7 +641,7 @@ // // = Little-endian, hard float, 64-bit // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-linux-gnu \ +// RUN: --target=mips64el-linux-gnu -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-64 %s // CHECK-EL-HF-64: "-internal-isystem" @@ -670,7 +670,7 @@ // // = Little-endian, soft float, 64-bit // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-linux-gnu -msoft-float \ +// RUN: --target=mips64el-linux-gnu -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_cs_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-64 %s // CHECK-EL-SF-64: "-internal-isystem" diff --git a/clang/test/Driver/mips-fsf.cpp b/clang/test/Driver/mips-fsf.cpp index b94da69789169..f67ad4e18ff29 100644 --- a/clang/test/Driver/mips-fsf.cpp +++ b/clang/test/Driver/mips-fsf.cpp @@ -4,7 +4,7 @@ // // = Big-endian, mips32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32 %s // CHECK-BE-HF-32: "-internal-isystem" @@ -31,7 +31,7 @@ // // = Big-endian, mips32, hard float, fp64 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mfp64 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-32 %s // CHECK-BE-HF64-32: "-internal-isystem" @@ -58,7 +58,7 @@ // // = Big-endian, mips32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -msoft-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-32 %s // CHECK-BE-SF-32: "-internal-isystem" @@ -85,7 +85,7 @@ // // = Big-endian, mips16 / mips32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-16 %s // CHECK-BE-HF-16: "-internal-isystem" @@ -112,7 +112,7 @@ // // = Big-endian, mips16 / mips32, hard float, fp64 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mfp64 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-16 %s // CHECK-BE-HF64-16: "-internal-isystem" @@ -139,7 +139,7 @@ // // = Big-endian, mips16 / mips32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -msoft-float \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-16 %s // CHECK-BE-SF-16: "-internal-isystem" @@ -166,7 +166,7 @@ // // = Big-endian, mips32 / mips16, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-16 %s // CHECK-BE-NAN-16: "-internal-isystem" @@ -193,7 +193,7 @@ // // = Big-endian, mips32 / mips16, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mips16 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-16 %s // CHECK-BE-NAN64-16: "-internal-isystem" @@ -220,7 +220,7 @@ // // = Big-endian, mips32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-32 %s // CHECK-BE-NAN-32: "-internal-isystem" @@ -247,7 +247,7 @@ // // = Big-endian, mips32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32 -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-32 %s // CHECK-BE-NAN64-32: "-internal-isystem" @@ -274,7 +274,7 @@ // // = Big-endian, mips32r2, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32R2 %s // CHECK-BE-HF-32R2: "-internal-isystem" @@ -301,7 +301,7 @@ // // = Big-endian, mips32r2, hard float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mhard-float -muclibc \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mhard-float -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-HF-32R2 %s // CHECK-BE-UC-HF-32R2: "-internal-isystem" @@ -328,7 +328,7 @@ // // = Big-endian, mips32r2, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mfp64 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-32R2 %s // CHECK-BE-HF64-32R2: "-internal-isystem" @@ -355,7 +355,7 @@ // // = Big-endian, mips32r2, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -msoft-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-32R2 %s // CHECK-BE-SF-32R2: "-internal-isystem" @@ -382,7 +382,7 @@ // // = Big-endian, mips32r2, soft float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -msoft-float -muclibc \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -msoft-float -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-SF-32R2 %s // CHECK-BE-UC-SF-32R2: "-internal-isystem" @@ -409,7 +409,7 @@ // // = Big-endian, mips32r2 / mips16, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-16R2 %s // CHECK-BE-HF-16R2: "-internal-isystem" @@ -436,7 +436,7 @@ // // = Big-endian, mips32r2 / mips16, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-16R2 %s // CHECK-BE-HF64-16R2: "-internal-isystem" @@ -463,7 +463,7 @@ // // = Big-endian, mips32r2 / mips16, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -msoft-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-16R2 %s // CHECK-BE-SF-16R2: "-internal-isystem" @@ -490,7 +490,7 @@ // // = Big-endian, mips32r2 / mips16, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-16R2 %s // CHECK-BE-NAN-16R2: "-internal-isystem" @@ -517,7 +517,7 @@ // // = Big-endian, mips32r2 / mips16, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-16R2 %s // CHECK-BE-NAN64-16R2: "-internal-isystem" @@ -544,7 +544,7 @@ // // = Big-endian, mips32r2, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-32R2 %s // CHECK-BE-NAN-32R2: "-internal-isystem" @@ -571,7 +571,7 @@ // // = Big-endian, mips32r2, nan2008, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mnan=2008 -muclibc \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mnan=2008 -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-UC-NAN-32R2 %s // CHECK-BE-UC-NAN-32R2: "-internal-isystem" @@ -598,7 +598,7 @@ // // = Big-endian, mips32r2, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r2 -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mips32r2 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-32R2 %s // CHECK-BE-NAN64-32R2: "-internal-isystem" @@ -625,7 +625,7 @@ // // = Big-endian, default (mips32r2), fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-32R2-DEF %s // CHECK-BE-NAN64-32R2-DEF: "-internal-isystem" @@ -652,7 +652,7 @@ // // = Big-endian, micromips, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mmicromips -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mmicromips -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-MM %s // CHECK-BE-HF-MM: "-internal-isystem" @@ -679,7 +679,7 @@ // // = Big-endian, micromips, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mmicromips -mfp64 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mmicromips -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-MM %s // CHECK-BE-HF64-MM: "-internal-isystem" @@ -706,7 +706,7 @@ // // = Big-endian, micromips, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mmicromips -msoft-float \ +// RUN: --target=mips-mti-linux-gnu -mmicromips -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-MM %s // CHECK-BE-SF-MM: "-internal-isystem" @@ -733,7 +733,7 @@ // // = Big-endian, micromips, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mmicromips -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mmicromips -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-MM %s // CHECK-BE-NAN-MM: "-internal-isystem" @@ -760,7 +760,7 @@ // // = Big-endian, micromips, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mmicromips -mfp64 -mnan=2008 \ +// RUN: --target=mips-mti-linux-gnu -mmicromips -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-MM %s // CHECK-BE-NAN64-MM: "-internal-isystem" @@ -787,7 +787,7 @@ // // = Big-endian, mips64, ABI n32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64-N32 %s // CHECK-BE-HF-64-N32: "-internal-isystem" @@ -814,7 +814,7 @@ // // = Big-endian, mips64, ABI n32, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-64-N32 %s // CHECK-BE-HF64-64-N32: "-internal-isystem" @@ -841,7 +841,7 @@ // // = Big-endian, mips64, ABI n32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -msoft-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-64-N32 %s // CHECK-BE-SF-64-N32: "-internal-isystem" @@ -868,7 +868,7 @@ // // = Big-endian, mips64, ABI n32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-64-N32 %s // CHECK-BE-NAN-64-N32: "-internal-isystem" @@ -895,7 +895,7 @@ // // = Big-endian, mips64, ABI n32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-64-N32 %s // CHECK-BE-NAN64-64-N32: "-internal-isystem" @@ -922,7 +922,7 @@ // // = Big-endian, mips64, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64-64 %s // CHECK-BE-HF-64-64: "-internal-isystem" @@ -949,7 +949,7 @@ // // = Big-endian, mips64, ABI 64, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-64-64 %s // CHECK-BE-HF64-64-64: "-internal-isystem" @@ -976,7 +976,7 @@ // // = Big-endian, mips64, ABI 64, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -msoft-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-64-64 %s // CHECK-BE-SF-64-64: "-internal-isystem" @@ -1003,7 +1003,7 @@ // // = Big-endian, mips64, ABI 64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-64-64 %s // CHECK-BE-NAN-64-64: "-internal-isystem" @@ -1030,7 +1030,7 @@ // // = Big-endian, mips64, ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-64-64 %s // CHECK-BE-NAN64-64-64: "-internal-isystem" @@ -1057,7 +1057,7 @@ // // = Big-endian, mips64r2, ABI n32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64R2-N32 %s // CHECK-BE-HF-64R2-N32: "-internal-isystem" @@ -1084,7 +1084,7 @@ // // = Big-endian, mips64r2, ABI n32, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-64R2-N32 %s // CHECK-BE-HF64-64R2-N32: "-internal-isystem" @@ -1111,7 +1111,7 @@ // // = Big-endian, mips64r2, ABI n32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -msoft-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-64R2-N32 %s // CHECK-BE-SF-64R2-N32: "-internal-isystem" @@ -1138,7 +1138,7 @@ // // = Big-endian, mips64r2, ABI n32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-64R2-N32 %s // CHECK-BE-NAN-64R2-N32: "-internal-isystem" @@ -1165,7 +1165,7 @@ // // = Big-endian, mips64r2, ABI n32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-64R2-N32 %s // CHECK-BE-NAN64-64R2-N32: "-internal-isystem" @@ -1192,7 +1192,7 @@ // // = Big-endian, mips64r2, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64R2-64 %s // CHECK-BE-HF-64R2-64: "-internal-isystem" @@ -1219,7 +1219,7 @@ // // = Big-endian, mips64r2, ABI 64, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF64-64R2-64 %s // CHECK-BE-HF64-64R2-64: "-internal-isystem" @@ -1246,7 +1246,7 @@ // // = Big-endian, mips64r2, ABI 64, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -msoft-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-SF-64R2-64 %s // CHECK-BE-SF-64R2-64: "-internal-isystem" @@ -1273,7 +1273,7 @@ // // = Big-endian, mips64r2, ABI 64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN-64R2-64 %s // CHECK-BE-NAN-64R2-64: "-internal-isystem" @@ -1300,7 +1300,7 @@ // // = Big-endian, mips64r2, ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-64R2-64 %s // CHECK-BE-NAN64-64R2-64: "-internal-isystem" @@ -1327,7 +1327,7 @@ // // = Big-endian, default (mips64r2), ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64-mti-linux-gnu -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-NAN64-64R2-64-DEF %s // CHECK-BE-NAN64-64R2-64-DEF: "-internal-isystem" @@ -1354,7 +1354,7 @@ // // = Little-endian, mips32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-32 %s // CHECK-EL-HF-32: "-internal-isystem" @@ -1381,7 +1381,7 @@ // // = Little-endian, mips32, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mfp64 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-32 %s // CHECK-EL-HF64-32: "-internal-isystem" @@ -1408,7 +1408,7 @@ // // = Little-endian, mips32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -msoft-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-32 %s // CHECK-EL-SF-32: "-internal-isystem" @@ -1435,7 +1435,7 @@ // // = Little-endian, mips32 / mips16, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-16 %s // CHECK-EL-HF-16: "-internal-isystem" @@ -1462,7 +1462,7 @@ // // = Little-endian, mips32 / mips16, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mfp64 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-16 %s // CHECK-EL-HF64-16: "-internal-isystem" @@ -1489,7 +1489,7 @@ // // = Little-endian, mips32 / mips16, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -msoft-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-16 %s // CHECK-EL-SF-16: "-internal-isystem" @@ -1516,7 +1516,7 @@ // // = Little-endian, mips32 / mips16, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-16 %s // CHECK-EL-NAN-16: "-internal-isystem" @@ -1543,7 +1543,7 @@ // // = Little-endian, mips32 / mips16, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mips16 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-16 %s // CHECK-EL-NAN64-16: "-internal-isystem" @@ -1570,7 +1570,7 @@ // // = Little-endian, mips32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-32 %s // CHECK-EL-NAN-32: "-internal-isystem" @@ -1597,7 +1597,7 @@ // // = Little-endian, mips32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32 -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-32 %s // CHECK-EL-NAN64-32: "-internal-isystem" @@ -1624,7 +1624,7 @@ // // = Little-endian, mips32r2, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-32R2 %s // CHECK-EL-HF-32R2: "-internal-isystem" @@ -1651,7 +1651,7 @@ // // = Little-endian, mips32r2, hard float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mhard-float -muclibc \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mhard-float -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-HF-32R2 %s // CHECK-EL-UC-HF-32R2: "-internal-isystem" @@ -1678,7 +1678,7 @@ // // = Little-endian, mips32r2, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mfp64 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-32R2 %s // CHECK-EL-HF64-32R2: "-internal-isystem" @@ -1705,7 +1705,7 @@ // // = Little-endian, mips32r2, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -msoft-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-32R2 %s // CHECK-EL-SF-32R2: "-internal-isystem" @@ -1732,7 +1732,7 @@ // // = Little-endian, mips32r2, soft float, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -msoft-float -muclibc \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -msoft-float -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-SF-32R2 %s // CHECK-EL-UC-SF-32R2: "-internal-isystem" @@ -1759,7 +1759,7 @@ // // = Little-endian, mips32r2 / mips16, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-16R2 %s // CHECK-EL-HF-16R2: "-internal-isystem" @@ -1786,7 +1786,7 @@ // // = Little-endian, mips32r2 / mips16, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-16R2 %s // CHECK-EL-HF64-16R2: "-internal-isystem" @@ -1813,7 +1813,7 @@ // // = Little-endian, mips32r2 / mips16, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -msoft-float \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-16R2 %s // CHECK-EL-SF-16R2: "-internal-isystem" @@ -1840,7 +1840,7 @@ // // = Little-endian, mips32r2 / mips16, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-16R2 %s // CHECK-EL-NAN-16R2: "-internal-isystem" @@ -1867,7 +1867,7 @@ // // = Little-endian, mips32r2 / mips16, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mips16 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-16R2 %s // CHECK-EL-NAN64-16R2: "-internal-isystem" @@ -1894,7 +1894,7 @@ // // = Little-endian, mips32r2, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-32R2 %s // CHECK-EL-NAN-32R2: "-internal-isystem" @@ -1921,7 +1921,7 @@ // // = Little-endian, mips32r2, nan2008, uclibc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mnan=2008 -muclibc \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mnan=2008 -muclibc -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-UC-NAN-32R2 %s // CHECK-EL-UC-NAN-32R2: "-internal-isystem" @@ -1948,7 +1948,7 @@ // // = Little-endian, mips32r2, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mips32r2 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-32R2 %s // CHECK-EL-NAN64-32R2: "-internal-isystem" @@ -1975,7 +1975,7 @@ // // = Little-endian, default (mips32r2), fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-32R2-DEF %s // CHECK-EL-NAN64-32R2-DEF: "-internal-isystem" @@ -2002,7 +2002,7 @@ // // = Little-endian, micromips, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-MM %s // CHECK-EL-HF-MM: "-internal-isystem" @@ -2029,7 +2029,7 @@ // // = Little-endian, micromips, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mfp64 -mhard-float \ +// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-MM %s // CHECK-EL-HF64-MM: "-internal-isystem" @@ -2056,7 +2056,7 @@ // // = Little-endian, micromips, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mmicromips -msoft-float \ +// RUN: --target=mipsel-mti-linux-gnu -mmicromips -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-MM %s // CHECK-EL-SF-MM: "-internal-isystem" @@ -2083,7 +2083,7 @@ // // = Little-endian, micromips, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-MM %s // CHECK-EL-NAN-MM: "-internal-isystem" @@ -2110,7 +2110,7 @@ // // = Little-endian, micromips, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mfp64 -mnan=2008 \ +// RUN: --target=mipsel-mti-linux-gnu -mmicromips -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-MM %s // CHECK-EL-NAN64-MM: "-internal-isystem" @@ -2137,7 +2137,7 @@ // // = Little-endian, mips64, ABI n32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-64-N32 %s // CHECK-EL-HF-64-N32: "-internal-isystem" @@ -2164,7 +2164,7 @@ // // = Little-endian, mips64, ABI n32, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-64-N32 %s // CHECK-EL-HF64-64-N32: "-internal-isystem" @@ -2191,7 +2191,7 @@ // // = Little-endian, mips64, ABI n32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -msoft-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-64-N32 %s // CHECK-EL-SF-64-N32: "-internal-isystem" @@ -2218,7 +2218,7 @@ // // = Little-endian, mips64, ABI n32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-64-N32 %s // CHECK-EL-NAN-64-N32: "-internal-isystem" @@ -2245,7 +2245,7 @@ // // = Little-endian, mips64, ABI n32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=n32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-64-N32 %s // CHECK-EL-NAN64-64-N32: "-internal-isystem" @@ -2272,7 +2272,7 @@ // // = Little-endian, mips64, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-64-64 %s // CHECK-EL-HF-64-64: "-internal-isystem" @@ -2299,7 +2299,7 @@ // // = Little-endian, mips64, ABI 64, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-64-64 %s // CHECK-EL-HF64-64-64: "-internal-isystem" @@ -2326,7 +2326,7 @@ // // = Little-endian, mips64, ABI 64, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -msoft-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-64-64 %s // CHECK-EL-SF-64-64: "-internal-isystem" @@ -2353,7 +2353,7 @@ // // = Little-endian, mips64, ABI 64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-64-64 %s // CHECK-EL-NAN-64-64: "-internal-isystem" @@ -2380,7 +2380,7 @@ // // = Little-endian, mips64, ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64 -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-64-64 %s // CHECK-EL-NAN64-64-64: "-internal-isystem" @@ -2407,7 +2407,7 @@ // // = Little-endian, mips64r2, ABI n32, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-64R2-N32 %s // CHECK-EL-HF-64R2-N32: "-internal-isystem" @@ -2434,7 +2434,7 @@ // // = Little-endian, mips64r2, ABI n32, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-64R2-N32 %s // CHECK-EL-HF64-64R2-N32: "-internal-isystem" @@ -2461,7 +2461,7 @@ // // = Little-endian, mips64r2, ABI n32, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -msoft-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-64R2-N32 %s // CHECK-EL-SF-64R2-N32: "-internal-isystem" @@ -2488,7 +2488,7 @@ // // = Little-endian, mips64r2, ABI n32, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-64R2-N32 %s // CHECK-EL-NAN-64R2-N32: "-internal-isystem" @@ -2515,7 +2515,7 @@ // // = Little-endian, mips64r2, ABI n32, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=n32 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-64R2-N32 %s // CHECK-EL-NAN64-64R2-N32: "-internal-isystem" @@ -2542,7 +2542,7 @@ // // = Little-endian, mips64r2, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF-64R2-64 %s // CHECK-EL-HF-64R2-64: "-internal-isystem" @@ -2569,7 +2569,7 @@ // // = Little-endian, mips64r2, ABI 64, fp64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mhard-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-HF64-64R2-64 %s // CHECK-EL-HF64-64R2-64: "-internal-isystem" @@ -2596,7 +2596,7 @@ // // = Little-endian, mips64r2, ABI 64, soft float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -msoft-float \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -msoft-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-SF-64R2-64 %s // CHECK-EL-SF-64R2-64: "-internal-isystem" @@ -2623,7 +2623,7 @@ // // = Little-endian, mips64r2, ABI 64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN-64R2-64 %s // CHECK-EL-NAN-64R2-64: "-internal-isystem" @@ -2650,7 +2650,7 @@ // // = Little-endian, mips64r2, ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mips64r2 -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-64R2-64 %s // CHECK-EL-NAN64-64R2-64: "-internal-isystem" @@ -2677,7 +2677,7 @@ // // = Little-endian, default (mips64r2), ABI 64, fp64, nan2008 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64el-mti-linux-gnu -mabi=64 -mfp64 -mnan=2008 \ +// RUN: --target=mips64el-mti-linux-gnu -mabi=64 -mfp64 -mnan=2008 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-EL-NAN64-64R2-64-DEF %s // CHECK-EL-NAN64-64R2-64-DEF: "-internal-isystem" @@ -2706,7 +2706,7 @@ // // = Big-endian, mips32r3, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r3 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r3 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32R3 %s // CHECK-BE-HF-32R3: "-internal-isystem" @@ -2733,7 +2733,7 @@ // // = Big-endian, mips32r5, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux-gnu -mips32r5 -mhard-float \ +// RUN: --target=mips-mti-linux-gnu -mips32r5 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32R5 %s // CHECK-BE-HF-32R5: "-internal-isystem" @@ -2760,7 +2760,7 @@ // // = Big-endian, mips64r3, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r3 -mabi=64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r3 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64R3-64 %s // CHECK-BE-HF-64R3-64: "-internal-isystem" @@ -2787,7 +2787,7 @@ // // = Big-endian, mips64r5, ABI 64, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-mti-linux-gnu -mips64r5 -mabi=64 -mhard-float \ +// RUN: --target=mips64-mti-linux-gnu -mips64r5 -mabi=64 -mhard-float -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_fsf_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-64R5-64 %s // CHECK-BE-HF-64R5-64: "-internal-isystem" diff --git a/clang/test/Driver/mips-img-v2.cpp b/clang/test/Driver/mips-img-v2.cpp index 69250b716e5b1..e031466ea2ac4 100644 --- a/clang/test/Driver/mips-img-v2.cpp +++ b/clang/test/Driver/mips-img-v2.cpp @@ -7,7 +7,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips32r6 -mhard-float -mabi=32 \ +// RUN: -EB -mips32r6 -mhard-float -mabi=32 -no-pie \ // RUN: | FileCheck --check-prefix=EB-HARD-O32 %s // EB-HARD-O32: "-internal-isystem" // EB-HARD-O32: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -35,7 +35,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips64r6 -mhard-float -mabi=n32 \ +// RUN: -EB -mips64r6 -mhard-float -mabi=n32 -no-pie \ // RUN: | FileCheck --check-prefix=EB-HARD-N32 %s // EB-HARD-N32: "-internal-isystem" // EB-HARD-N32: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -63,7 +63,7 @@ // RUN: --target=mips64-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips64r6 -mhard-float -mabi=64 \ +// RUN: -EB -mips64r6 -mhard-float -mabi=64 -no-pie \ // RUN: | FileCheck --check-prefix=EB-HARD-N64 %s // EB-HARD-N64: "-internal-isystem" // EB-HARD-N64: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -91,7 +91,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips32r6 -mhard-float -mabi=32 \ +// RUN: -EL -mips32r6 -mhard-float -mabi=32 -no-pie \ // RUN: | FileCheck --check-prefix=EL-HARD-O32 %s // EL-HARD-O32: "-internal-isystem" // EL-HARD-O32: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -119,7 +119,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips64r6 -mhard-float -mabi=n32 \ +// RUN: -EL -mips64r6 -mhard-float -mabi=n32 -no-pie \ // RUN: | FileCheck --check-prefix=EL-HARD-N32 %s // EL-HARD-N32: "-internal-isystem" // EL-HARD-N32: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -147,7 +147,7 @@ // RUN: --target=mips64-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips64r6 -mhard-float -mabi=64 \ +// RUN: -EL -mips64r6 -mhard-float -mabi=64 -no-pie \ // RUN: | FileCheck --check-prefix=EL-HARD-N64 %s // EL-HARD-N64: "-internal-isystem" // EL-HARD-N64: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -175,7 +175,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips32r6 -msoft-float \ +// RUN: -EB -mips32r6 -msoft-float -no-pie \ // RUN: | FileCheck --check-prefix=EB-SOFT %s // EB-SOFT: "-internal-isystem" // EB-SOFT: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -203,7 +203,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips32r6 -msoft-float \ +// RUN: -EL -mips32r6 -msoft-float -no-pie \ // RUN: | FileCheck --check-prefix=EL-SOFT %s // EL-SOFT: "-internal-isystem" // EL-SOFT: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -231,7 +231,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips32r6 -mhard-float -mmicromips \ +// RUN: -EB -mips32r6 -mhard-float -mmicromips -no-pie \ // RUN: | FileCheck --check-prefix=EB-HARD-MICRO %s // EB-HARD-MICRO: "-internal-isystem" // EB-HARD-MICRO: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -259,7 +259,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EB -mips32r6 -msoft-float -mmicromips \ +// RUN: -EB -mips32r6 -msoft-float -mmicromips -no-pie \ // RUN: | FileCheck --check-prefix=EB-SOFT-MICRO %s // EB-SOFT-MICRO: "-internal-isystem" // EB-SOFT-MICRO: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -287,7 +287,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips32r6 -mhard-float -mmicromips \ +// RUN: -EL -mips32r6 -mhard-float -mmicromips -no-pie \ // RUN: | FileCheck --check-prefix=EL-HARD-MICRO %s // EL-HARD-MICRO: "-internal-isystem" // EL-HARD-MICRO: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" @@ -315,7 +315,7 @@ // RUN: --target=mips-img-linux-gnu \ // RUN: --gcc-toolchain=%S/Inputs/mips_img_v2_tree \ // RUN: -stdlib=libstdc++ \ -// RUN: -EL -mips32r6 -msoft-float -mmicromips \ +// RUN: -EL -mips32r6 -msoft-float -mmicromips -no-pie \ // RUN: | FileCheck --check-prefix=EL-SOFT-MICRO %s // EL-SOFT-MICRO: "-internal-isystem" // EL-SOFT-MICRO: "[[TC:[^"]+/lib/gcc/mips-img-linux-gnu/4.9.2]]/../../../../mips-img-linux-gnu/include/c++/4.9.2" diff --git a/clang/test/Driver/mips-img.cpp b/clang/test/Driver/mips-img.cpp index c97bb9478e7cb..272fa724102c4 100644 --- a/clang/test/Driver/mips-img.cpp +++ b/clang/test/Driver/mips-img.cpp @@ -4,7 +4,7 @@ // // = Big-endian, mips32r6 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-img-linux-gnu -mips32r6 \ +// RUN: --target=mips-img-linux-gnu -mips32r6 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-32R6 %s // CHECK-BE-32R6: "-internal-isystem" @@ -31,7 +31,7 @@ // // = Little-endian, mips32r6 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-img-linux-gnu -mips32r6 -EL \ +// RUN: --target=mips-img-linux-gnu -mips32r6 -EL -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-LE-32R6 %s // CHECK-LE-32R6: "-internal-isystem" @@ -58,7 +58,7 @@ // // = Big-endian, mips64r6, N32 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-img-linux-gnu -mips64r6 -mabi=n32 \ +// RUN: --target=mips64-img-linux-gnu -mips64r6 -mabi=n32 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-64R6-N32 %s // CHECK-BE-64R6-N32: "-internal-isystem" @@ -85,7 +85,7 @@ // // = Little-endian, mips64r6, N32 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-img-linux-gnu -mips64r6 -EL -mabi=n32 \ +// RUN: --target=mips64-img-linux-gnu -mips64r6 -EL -mabi=n32 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-LE-64R6-N32 %s // CHECK-LE-64R6-N32: "-internal-isystem" @@ -112,7 +112,7 @@ // // = Big-endian, mips64r6, N64 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-img-linux-gnu -mips64r6 -mabi=64 \ +// RUN: --target=mips64-img-linux-gnu -mips64r6 -mabi=64 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-BE-64R6-N64 %s // CHECK-BE-64R6-N64: "-internal-isystem" @@ -139,7 +139,7 @@ // // = Little-endian, mips64r6, N64 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips64-img-linux-gnu -mips64r6 -EL -mabi=64 \ +// RUN: --target=mips64-img-linux-gnu -mips64r6 -EL -mabi=64 -no-pie \ // RUN: -stdlib=libstdc++ --gcc-toolchain=%S/Inputs/mips_img_tree \ // RUN: | FileCheck --check-prefix=CHECK-LE-64R6-N64 %s // CHECK-LE-64R6-N64: "-internal-isystem" diff --git a/clang/test/Driver/mips-mti-linux.c b/clang/test/Driver/mips-mti-linux.c index 21b270c0a4b76..0c5efa536829f 100644 --- a/clang/test/Driver/mips-mti-linux.c +++ b/clang/test/Driver/mips-mti-linux.c @@ -8,7 +8,8 @@ // = Big-endian, mips32r2, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux -mips32r2 -mhard-float -rtlib=platform -fuse-ld=ld \ +// RUN: --target=mips-mti-linux -mips32r2 -mhard-float -no-pie \ +// RUN: -rtlib=platform -fuse-ld=ld \ // RUN: --sysroot=%S/Inputs/mips_mti_linux/sysroot \ // RUN: | FileCheck --check-prefix=CHECK-BE-HF-32R2 %s // @@ -26,7 +27,8 @@ // = Little-endian, mips32r2, hard float // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ -// RUN: --target=mips-mti-linux -mips32r2 -EL -mhard-float -rtlib=platform -fuse-ld=ld \ +// RUN: --target=mips-mti-linux -mips32r2 -EL -mhard-float -no-pie \ +// RUN: -rtlib=platform -fuse-ld=ld \ // RUN: --sysroot=%S/Inputs/mips_mti_linux/sysroot \ // RUN: | FileCheck --check-prefix=CHECK-LE-HF-32R2 %s // From 443f68c280aca3dacb01fd4036901808c10dc525 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 24 Feb 2022 15:25:35 -0800 Subject: [PATCH 166/316] [clang][test] Make mips-vector-return.c work with CLANG_DEFAULT_PIE_ON_LINUX=on (cherry picked from commit da047445f77bfd74b04c36169e104f35dbfff84e) --- clang/test/CodeGen/mips-vector-return.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/test/CodeGen/mips-vector-return.c b/clang/test/CodeGen/mips-vector-return.c index dfb0ca304dbe7..fe39f91f293ce 100644 --- a/clang/test/CodeGen/mips-vector-return.c +++ b/clang/test/CodeGen/mips-vector-return.c @@ -1,5 +1,5 @@ -// RUN: %clang -target mipsel-unknown-linux -O3 -S -o - -emit-llvm %s | FileCheck %s -check-prefix=O32 -// RUN: %clang -target mips64el-unknown-linux -O3 -S -mabi=n64 -o - -emit-llvm %s | FileCheck %s -check-prefix=N64 +// RUN: %clang_cc1 -triple mipsel-unknown-linux -O3 -S -o - -emit-llvm %s | FileCheck %s -check-prefix=O32 +// RUN: %clang_cc1 -triple mips64el-unknown-linux -O3 -S -target-abi n64 -o - -emit-llvm %s | FileCheck %s -check-prefix=N64 // vectors larger than 16-bytes are returned via the hidden pointer argument. // N64/N32 returns vectors whose size is equal to or smaller than 16-bytes in @@ -8,14 +8,14 @@ typedef float v4sf __attribute__ ((__vector_size__ (16))); typedef double v4df __attribute__ ((__vector_size__ (32))); typedef int v4i32 __attribute__ ((__vector_size__ (16))); -// O32-LABEL: define dso_local void @test_v4sf(<4 x float>* noalias nocapture writeonly sret -// N64: define inreg { i64, i64 } @test_v4sf +// O32-LABEL: define{{.*}} void @test_v4sf(<4 x float>* noalias nocapture writeonly sret +// N64: define{{.*}} inreg { i64, i64 } @test_v4sf v4sf test_v4sf(float a) { return (v4sf){0.0f, a, 0.0f, 0.0f}; } -// O32-LABEL: define dso_local void @test_v4df(<4 x double>* noalias nocapture writeonly sret -// N64-LABEL: define void @test_v4df(<4 x double>* noalias nocapture writeonly sret +// O32-LABEL: define{{.*}} void @test_v4df(<4 x double>* noalias nocapture writeonly sret +// N64-LABEL: define{{.*}} void @test_v4df(<4 x double>* noalias nocapture writeonly sret v4df test_v4df(double a) { return (v4df){0.0, a, 0.0, 0.0}; } @@ -23,8 +23,8 @@ v4df test_v4df(double a) { // O32 returns integer vectors whose size is equal to or smaller than 16-bytes // in integer registers. // -// O32: define dso_local inreg { i32, i32, i32, i32 } @test_v4i32 -// N64: define inreg { i64, i64 } @test_v4i32 +// O32: define{{.*}} inreg { i32, i32, i32, i32 } @test_v4i32 +// N64: define{{.*}} inreg { i64, i64 } @test_v4i32 v4i32 test_v4i32(int a) { return (v4i32){0, a, 0, 0}; } From 2a492dfd6b4edf21bfd05aa5e18c81ec89b04250 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 24 Feb 2022 23:53:38 +0000 Subject: [PATCH 167/316] [Driver][test] Make hexagon-toolchain-elf.c work with CLANG_DEFAULT_PIE_ON_LINUX=on (cherry picked from commit deee339796ccffc267d4e1846f4b8203f3f1a485) --- clang/test/Driver/hexagon-toolchain-elf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/hexagon-toolchain-elf.c b/clang/test/Driver/hexagon-toolchain-elf.c index d7c8015547e47..3ae2b56de22fd 100644 --- a/clang/test/Driver/hexagon-toolchain-elf.c +++ b/clang/test/Driver/hexagon-toolchain-elf.c @@ -484,19 +484,19 @@ // CHECK041: {{hexagon-link|ld}} // CHECK041: "-G0" -// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as \ +// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as -fno-pie -no-pie \ // RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \ // RUN: -mcpu=hexagonv60 \ // RUN: -G=8 \ // RUN: %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK042 %s -// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as \ +// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as -fno-pie -no-pie \ // RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \ // RUN: -mcpu=hexagonv60 \ // RUN: -G 8 \ // RUN: %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK042 %s -// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as \ +// RUN: %clang -### -target hexagon-unknown-elf -fno-integrated-as -fno-pie -no-pie \ // RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \ // RUN: -mcpu=hexagonv60 \ // RUN: -msmall-data-threshold=8 \ From 3e10605abcb297be25ef09eb606ac19c2fc52ea5 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 25 Feb 2022 00:04:07 +0000 Subject: [PATCH 168/316] [Driver][test] Remove soon irrelevant pie tests CLANG_DEFAULT_PIE_ON_LINUX=on will soon become the default. The purpose of these tests has gone. (cherry picked from commit 0ac6be6ab6b564327caeac417fe6d29044c7fe61) --- clang/test/Driver/fsanitize.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/clang/test/Driver/fsanitize.c b/clang/test/Driver/fsanitize.c index 7bcda5c33dc9e..17fce1981eead 100644 --- a/clang/test/Driver/fsanitize.c +++ b/clang/test/Driver/fsanitize.c @@ -1,4 +1,3 @@ -// UNSUPPORTED: default-pie-on-linux // RUN: %clang -target x86_64-linux-gnu -fsanitize=undefined -fsanitize-trap=undefined %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEFINED-TRAP // RUN: %clang -target x86_64-linux-gnu -fsanitize=undefined -fsanitize-trap=undefined -fno-sanitize-trap=signed-integer-overflow %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEFINED-TRAP2 // RUN: %clang -target x86_64-linux-gnu -fsanitize=undefined -fsanitize-undefined-trap-on-error %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEFINED-TRAP @@ -345,27 +344,6 @@ // RUN: %clang -target x86_64-linux-gnu -fsanitize=vptr -fno-sanitize=vptr -fsanitize=undefined,address %s -### 2>&1 // OK -// RUN: %clang -target x86_64-linux-gnu -fsanitize=thread %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-NO-PIE -// RUN: %clang -target x86_64-linux-gnu -fsanitize=memory %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-NO-PIE -// RUN: %clang -target x86_64-unknown-freebsd -fsanitize=memory %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PIE -// RUN: %clang -target aarch64-linux-gnu -fsanitize=memory %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PIE -// RUN: %clang -target arm-linux-androideabi -fsanitize=address %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PIE -// RUN: %clang -target arm-linux-androideabi24 -fsanitize=address %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PIE -// RUN: %clang -target aarch64-linux-android -fsanitize=address %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-PIE -// RUN: %clang -target x86_64-linux-gnu -fsanitize=address %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-NO-PIE -// RUN: %clang -target i386-linux-gnu -fsanitize=address %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-NO-PIE - -// CHECK-NO-PIE-NOT: "-pie" -// CHECK-NO-PIE: "-mrelocation-model" "static" -// CHECK-NO-PIE-NOT: "-pie" - -// CHECK-PIC-NO-PIE-NOT: "-pie" -// CHECK-PIC-NO-PIE: "-mrelocation-model" "pic" -// CHECK-PIC-NO-PIE-NOT: "-pie" - -// CHECK-PIE: "-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" -// CHECK-PIE: "-pie" - // RUN: %clang -target arm-linux-androideabi %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-ANDROID-NO-ASAN // CHECK-ANDROID-NO-ASAN: "-mrelocation-model" "pic" From bdbca8f3d0b272199c595dd55cb3d5d0a233771d Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 24 Feb 2022 16:09:18 -0800 Subject: [PATCH 169/316] [asan][test] asan_prelink_test.cpp: use -fno-pie -no-pie prelink (will be removed by glibc 2.37) does not support PIE. (cherry picked from commit 611122892e6d5813444bdd0e1fbe0a96f6e09779) --- compiler-rt/test/asan/TestCases/Linux/asan_prelink_test.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler-rt/test/asan/TestCases/Linux/asan_prelink_test.cpp b/compiler-rt/test/asan/TestCases/Linux/asan_prelink_test.cpp index 9c70b61291b36..2dfe689ddcbbc 100644 --- a/compiler-rt/test/asan/TestCases/Linux/asan_prelink_test.cpp +++ b/compiler-rt/test/asan/TestCases/Linux/asan_prelink_test.cpp @@ -7,7 +7,7 @@ // RUN: %clangxx_asan -DBUILD_SO=1 -fPIC -shared %s -o %t.so -Wl,-Ttext-segment=0x3600000000 ||\ // RUN: %clangxx_asan -DBUILD_SO=1 -fPIC -shared %s -o %t.so -Wl,--image-base=0x3600000000 ||\ // RUN: %clangxx_asan -DBUILD_SO=1 -fPIC -shared %s -o %t.so -Wl,-Ttext=0x3600000000 -// RUN: %clangxx_asan %t.o %t.so -Wl,-R. -o %t +// RUN: %clangxx_asan -fno-pie -no-pie %t.o %t.so -Wl,-R. -o %t // RUN: %env_asan_opts=verbosity=1 %run %t 2>&1 | FileCheck %s // GNU driver doesn't handle .so files properly. From 1f7e8b1c6893d0c5337441ff3726c64cdf54b618 Mon Sep 17 00:00:00 2001 From: Muhammad Omair Javaid Date: Fri, 25 Feb 2022 17:51:11 +0500 Subject: [PATCH 170/316] [Docs] Added note about LLDB Win/Arm64 binary release LLDB windows on ARM64 14.0.0 release will include LLDB binary. This patch adds a release note about it. --- llvm/docs/ReleaseNotes.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 1ac4cca463794..c6e6e445f709d 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -252,6 +252,9 @@ Changes to LLDB * Fixed continuing from breakpoints and singlestepping on Windows on ARM/ARM64. +* LLDB has been included in Windows on ARM64 binary release with Python support + disabled. + Changes to Sanitizers --------------------- From e89602b7b2ec12f20f2618cefb864c2b22d0048a Mon Sep 17 00:00:00 2001 From: Whisperity Date: Fri, 25 Feb 2022 14:21:18 +0100 Subject: [PATCH 171/316] [clang-tidy] Fix `readability-suspicious-call-argument` crash for arguments without name-like identifier As originally reported by @steakhal in http://github.com/llvm/llvm-project/issues/54074, the name extraction logic of `readability-suspicious-call-argument` crashes if the argument passed to a function was a function call to a non-trivially named entity (e.g. an operator). Fixed this crash case by ignoring such constructs and considering them as having no name. Reviewed By: aaron.ballman, steakhal Differential Revision: http://reviews.llvm.org/D120555 (Cherry-picked from commit 416e689ecda66616da855c82f7ec652657730c6a) --- .../SuspiciousCallArgumentCheck.cpp | 25 +++++++++------- clang-tools-extra/docs/ReleaseNotes.rst | 4 +++ .../readability-suspicious-call-argument.cpp | 29 +++++++++++++++++++ 3 files changed, 48 insertions(+), 10 deletions(-) diff --git a/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp b/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp index 4d7c3451acc7a..ac6bda3ff09ff 100644 --- a/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp @@ -711,23 +711,28 @@ void SuspiciousCallArgumentCheck::setArgNamesAndTypes( for (std::size_t I = InitialArgIndex, J = MatchedCallExpr->getNumArgs(); I < J; ++I) { + assert(ArgTypes.size() == I - InitialArgIndex && + ArgNames.size() == ArgTypes.size() && + "Every iteration must put an element into the vectors!"); + if (const auto *ArgExpr = dyn_cast( MatchedCallExpr->getArg(I)->IgnoreUnlessSpelledInSource())) { if (const auto *Var = dyn_cast(ArgExpr->getDecl())) { ArgTypes.push_back(Var->getType()); ArgNames.push_back(Var->getName()); - } else if (const auto *FCall = - dyn_cast(ArgExpr->getDecl())) { - ArgTypes.push_back(FCall->getType()); - ArgNames.push_back(FCall->getName()); - } else { - ArgTypes.push_back(QualType()); - ArgNames.push_back(StringRef()); + continue; + } + if (const auto *FCall = dyn_cast(ArgExpr->getDecl())) { + if (FCall->getNameInfo().getName().isIdentifier()) { + ArgTypes.push_back(FCall->getType()); + ArgNames.push_back(FCall->getName()); + continue; + } } - } else { - ArgTypes.push_back(QualType()); - ArgNames.push_back(StringRef()); } + + ArgTypes.push_back(QualType()); + ArgNames.push_back(StringRef()); } } diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 59aff131f6c22..a794983708cfc 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -352,6 +352,10 @@ Changes in existing checks return statements associated with ``case``, ``default`` and labeled statements. +- Fixed a crash in :doc:`readability-suspicious-call-argument + ` related to passing + arguments that refer to program elements without a trivial identifier. + Removed checks ^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability-suspicious-call-argument.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-suspicious-call-argument.cpp index 2597ee3b9e030..edd3591517af3 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability-suspicious-call-argument.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability-suspicious-call-argument.cpp @@ -485,3 +485,32 @@ int main() { return 0; } + +namespace Issue_54074 { + +class T {}; +using OperatorTy = int(const T &, const T &); +int operator-(const T &, const T &); + +template +struct Wrap { + Wrap(U); +}; + +template +void wrapTaker(V, Wrap); + +template +void wrapTaker(V aaaaa, V bbbbb, Wrap); + +void test() { + wrapTaker(0, operator-); + // NO-WARN. No crash! + + int aaaaa = 4, bbbbb = 8; + wrapTaker(bbbbb, aaaaa, operator-); + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: 1st argument 'bbbbb' (passed to 'aaaaa') looks like it might be swapped with the 2nd, 'aaaaa' (passed to 'bbbbb') + // CHECK-MESSAGES: :[[@LINE-9]]:6: note: in the call to 'wrapTaker', declared here +} + +} // namespace Issue_54074 From cdd8cca0c33c5392d9247c8aea036bfbb471c971 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 25 Feb 2022 19:25:18 +0000 Subject: [PATCH 172/316] [ELF] Support some absolute/PC-relative relocation types for REL format ctfconvert seems to use REL-format `.rel.SUNW_dof` for 32-bit architectures. ``` Binary file usr/ports/lang/perl5.32/work/perl-5.32.1/dtrace_mini.o matches [alfredo.junior@dell-a ~/tmp/llvm-bug]$ readelf -r dtrace_mini.o Relocation section (.rel.SUNW_dof): r_offset r_info r_type st_value st_name 00000184 0000281a R_PPC_REL32 00000000 $dtrace1772974259.Perl_dtrace_probe_load ``` Support R_PPC_REL32 to fix `ld.lld: error: drti.c:(.SUNW_dof+0x4E4): internal linker error: cannot read addend for relocation R_PPC_REL32`. While here, add some common relocation types for AArch64, PPC, and PPC64. We perform minimum tests. Reviewed By: adalava, arichardson Differential Revision: https://reviews.llvm.org/D120535 (cherry picked from commit 767e64fc11d7734843ec5bb0bd3f7330541bb1a6) --- lld/ELF/Arch/AArch64.cpp | 5 +++ lld/ELF/Arch/PPC.cpp | 3 ++ lld/ELF/Arch/PPC64.cpp | 5 +++ lld/test/ELF/relocation-rel-format.test | 42 +++++++++++++++++++++++++ 4 files changed, 55 insertions(+) create mode 100644 lld/test/ELF/relocation-rel-format.test diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 9e857d5906845..add819ff5a802 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -199,6 +199,11 @@ int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const { return read64(buf + 8); case R_AARCH64_NONE: return 0; + case R_AARCH64_PREL32: + return SignExtend64<32>(read32(buf)); + case R_AARCH64_ABS64: + case R_AARCH64_PREL64: + return read64(buf); default: internalLinkerError(getErrorLocation(buf), "cannot read addend for relocation " + toString(type)); diff --git a/lld/ELF/Arch/PPC.cpp b/lld/ELF/Arch/PPC.cpp index 315ac7df608d0..47c31e3a3b943 100644 --- a/lld/ELF/Arch/PPC.cpp +++ b/lld/ELF/Arch/PPC.cpp @@ -280,6 +280,9 @@ int64_t PPC::getImplicitAddend(const uint8_t *buf, RelType type) const { switch (type) { case R_PPC_NONE: return 0; + case R_PPC_ADDR32: + case R_PPC_REL32: + return SignExtend64<32>(read32(buf)); default: internalLinkerError(getErrorLocation(buf), "cannot read addend for relocation " + toString(type)); diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp index 7d051c43af0d3..871e19262ae77 100644 --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -1064,6 +1064,11 @@ int64_t PPC64::getImplicitAddend(const uint8_t *buf, RelType type) const { switch (type) { case R_PPC64_NONE: return 0; + case R_PPC64_REL32: + return SignExtend64<32>(read32(buf)); + case R_PPC64_ADDR64: + case R_PPC64_REL64: + return read64(buf); default: internalLinkerError(getErrorLocation(buf), "cannot read addend for relocation " + toString(type)); diff --git a/lld/test/ELF/relocation-rel-format.test b/lld/test/ELF/relocation-rel-format.test new file mode 100644 index 0000000000000..df38f8f7daf15 --- /dev/null +++ b/lld/test/ELF/relocation-rel-format.test @@ -0,0 +1,42 @@ +## Test some relocation types for REL format. +# RUN: yaml2obj -DMACHINE=AARCH64 -DR0=R_AARCH64_ABS64 -DR1=R_AARCH64_PREL32 -DR2=R_AARCH64_PREL64 %s -o %t.o +# RUN: ld.lld %t.o -o /dev/null +# RUN: yaml2obj -DMACHINE=PPC -DBITS=32 -DR0=R_PPC_ADDR32 -DR1=R_PPC_REL32 %s -o %t.o +# RUN: ld.lld %t.o -o /dev/null +# RUN: yaml2obj -DMACHINE=PPC64 -DR0=R_PPC64_ADDR64 -DR1=R_PPC64_REL32 -DR2=R_PPC64_REL64 %s -o %t.o +# RUN: ld.lld %t.o -o /dev/null + +--- !ELF +FileHeader: + Class: ELFCLASS[[BITS=64]] + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_[[MACHINE]] +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Size: 24 + - Name: .data + Type: SHT_PROGBITS + Flags: [ SHF_WRITE, SHF_ALLOC ] + - Name: .rel.text + Type: SHT_REL + Info: .text + Relocations: + - Symbol: .data + Type: [[R0]] + - Offset: 8 + Symbol: .data + Type: [[R1=0]] + - Offset: 16 + Symbol: .data + Type: [[R2=0]] +Symbols: + - Name: .data + Type: STT_SECTION + Section: .data + - Name: _start + Section: .text + Binding: STB_GLOBAL +... From df3182a7df1913f8503fda9bb4553297f0b8571b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Fri, 25 Feb 2022 20:00:08 +0100 Subject: [PATCH 173/316] [clang] [test] Skip hip-fpie-option.hip if default-pie Skip the hip-fpie-option.hip Driver test if default-pie-on-linux is used. This test currently relies on default-no-pie, and it has been changed to require default-pie in main. Differential Revision: https://reviews.llvm.org/D120577 --- clang/test/Driver/hip-fpie-option.hip | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/Driver/hip-fpie-option.hip b/clang/test/Driver/hip-fpie-option.hip index 2e296a099dea5..69a2954f6a90c 100644 --- a/clang/test/Driver/hip-fpie-option.hip +++ b/clang/test/Driver/hip-fpie-option.hip @@ -1,4 +1,5 @@ // REQUIRES: clang-driver, amdgpu-registered-target +// UNSUPPORTED: default-pie-on-linux // -fPIC and -fPIE only affects host relocation model. // device compilation always uses PIC. From 8400036358c8c8a6f2c68476cce9eb6a7888812c Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 25 Feb 2022 19:55:56 +0000 Subject: [PATCH 174/316] [libunwind][test] remember_state_leak.pass.sh.s: link with -no-pie The no-pic large code model style `movabsq $callback, %rsi` does not work with -pie. (cherry picked from commit 84647ff38ca76136e3c4be80cf6785a78188d33a) --- libunwind/test/remember_state_leak.pass.sh.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libunwind/test/remember_state_leak.pass.sh.s b/libunwind/test/remember_state_leak.pass.sh.s index f18d1768e7c4b..590653e2b10de 100644 --- a/libunwind/test/remember_state_leak.pass.sh.s +++ b/libunwind/test/remember_state_leak.pass.sh.s @@ -1,5 +1,5 @@ # REQUIRES: target={{x86_64-.+-linux-gnu}} -# RUN: %{build} +# RUN: %{build} -no-pie # RUN: %{run} # The following assembly is a translation of this code: From f8ca5fabdb54fdf64b3dffb38ebf7d0220f415a2 Mon Sep 17 00:00:00 2001 From: Joao Moreira Date: Sat, 26 Feb 2022 03:55:39 +0000 Subject: [PATCH 175/316] [ELF][X86] Don't create IBT .plt if there is no PLT entry https://github.com/ClangBuiltLinux/linux/issues/1606 When GNU_PROPERTY_X86_FEATURE_1_IBT is enabled, ld.lld will create .plt output section even if there is no PLT entry. Fix this by implementing IBTPltSection::isNeeded instead of using the default code path (which always returns true). Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D120600 (cherry picked from commit 9d7001eba9c4cb311e03cd8cdc231f9e579f2d0f) --- lld/ELF/SyntheticSections.cpp | 2 ++ lld/ELF/SyntheticSections.h | 1 + lld/test/ELF/format-binary.test | 6 +++--- lld/test/ELF/x86-64-feature-cet.s | 11 +++++++++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index ccf0c5fd65da2..7778ae5f78e66 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -2699,6 +2699,8 @@ size_t IBTPltSection::getSize() const { return 16 + in.plt->getNumEntries() * target->pltEntrySize; } +bool IBTPltSection::isNeeded() const { return in.plt->getNumEntries() > 0; } + // The string hash function for .gdb_index. static uint32_t computeGdbHash(StringRef s) { uint32_t h = 0; diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index 1b63a5d29d106..e609b3d7982a5 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -762,6 +762,7 @@ class IBTPltSection : public SyntheticSection { public: IBTPltSection(); void writeTo(uint8_t *Buf) override; + bool isNeeded() const override; size_t getSize() const override; }; diff --git a/lld/test/ELF/format-binary.test b/lld/test/ELF/format-binary.test index bb06d7e5ab9f2..3c580ebb99ed4 100644 --- a/lld/test/ELF/format-binary.test +++ b/lld/test/ELF/format-binary.test @@ -31,10 +31,10 @@ # EXE: Machine: Advanced Micro Devices X86-64 # EXE: [Nr] Name Type Address Off Size ES Flg Lk Inf Al -# EXE: [ 3] .data PROGBITS {{.*}} 00000c 00 WA 0 0 8 +# EXE: [ 2] .data PROGBITS {{.*}} 00000c 00 WA 0 0 8 # EXE: Size Type Bind Vis Ndx Name -# EXE: 0 OBJECT GLOBAL DEFAULT 3 _binary_d_t_txt_start -# EXE-NEXT: 0 OBJECT GLOBAL DEFAULT 3 _binary_d_t_txt_end +# EXE: 0 OBJECT GLOBAL DEFAULT 2 _binary_d_t_txt_start +# EXE-NEXT: 0 OBJECT GLOBAL DEFAULT 2 _binary_d_t_txt_end # EXE-NEXT: 0 OBJECT GLOBAL DEFAULT ABS _binary_d_t_txt_size # RUN: not ld.lld -b foo 2>&1 | FileCheck --check-prefix=ERR %s diff --git a/lld/test/ELF/x86-64-feature-cet.s b/lld/test/ELF/x86-64-feature-cet.s index 5322bbdf3f383..cf90d9708e119 100644 --- a/lld/test/ELF/x86-64-feature-cet.s +++ b/lld/test/ELF/x86-64-feature-cet.s @@ -91,6 +91,17 @@ # DISASM-NEXT: jmpq *0x2126(%rip) # DISASM-NEXT: nopw (%rax,%rax) +## If there is no PLT entry, don't create .plt section. +# RUN: ld.lld -e 0 %t1.o -o %t.noplt +# RUN: llvm-readelf -S %t.noplt | FileCheck %s --check-prefix=NOPLT +# RUN: ld.lld -r %t1.o -o %t.noplt +# RUN: llvm-readelf -S %t.noplt | FileCheck %s --check-prefix=NOPLT + +# NOPLT: [Nr] Name +# NOPLT-NOT: .plt +# NOPLT: .note.gnu.property +# NOPLT-NOT: .plt + .section ".note.gnu.property", "a" .long 4 .long 0x10 From d61805a8b6863663754b1d35ad5d3b25c30365cf Mon Sep 17 00:00:00 2001 From: Konstantin Varlamov Date: Mon, 28 Feb 2022 12:55:27 -0500 Subject: [PATCH 176/316] [libc++] Fix double file closing in `std::filesystem::remove_all()`. According to Linux documentation (see e.g. https://linux.die.net/man/3/closedir): > A successful call to `closedir()` also closes the underlying file > descriptor associated with `dirp`. Thus, calling `close()` after a successful call to `closedir()` is at best redundant. Worse, should a different thread open a file in-between the calls to `closedir()` and `close()` and get the same file descriptor, the call to `close()` might actually close a different file than was intended. rdar://89251874 Differential Revision: https://reviews.llvm.org/D120453 (cherry picked from commit 3906ebf750b80e36c2d6c52130cf40771e1b55fb) --- libcxx/src/filesystem/operations.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libcxx/src/filesystem/operations.cpp b/libcxx/src/filesystem/operations.cpp index 7aeeffaae8f38..39fb5739739be 100644 --- a/libcxx/src/filesystem/operations.cpp +++ b/libcxx/src/filesystem/operations.cpp @@ -1414,12 +1414,14 @@ uintmax_t remove_all_impl(int parent_directory, const path& p, error_code& ec) { if (fd != -1) { // If that worked, iterate over the contents of the directory and // remove everything in it, recursively. - scope_exit close_fd([=] { ::close(fd); }); DIR* stream = ::fdopendir(fd); if (stream == nullptr) { + ::close(fd); ec = detail::capture_errno(); return 0; } + // Note: `::closedir` will also close the associated file descriptor, so + // there should be no call to `close(fd)`. scope_exit close_stream([=] { ::closedir(stream); }); uintmax_t count = 0; From 8a323ada234ba2859942772b446bf2692dadb573 Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Thu, 17 Feb 2022 17:18:43 +0100 Subject: [PATCH 177/316] [clang][SemaTemplate] Fix a stack use after scope Differential Revision: https://reviews.llvm.org/D120065 (cherry picked from commit c79c13cae61564d3a03831013ea24ff483ee3e82) --- clang/include/clang/AST/DeclTemplate.h | 6 +++--- clang/lib/AST/DeclTemplate.cpp | 9 ++++++++- clang/test/SemaTemplate/friend-template.cpp | 9 +++++++++ 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index d216b359816e8..319e605a8a1c5 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -2461,10 +2461,10 @@ class FriendTemplateDecl : public Decl { SourceLocation FriendLoc; FriendTemplateDecl(DeclContext *DC, SourceLocation Loc, - MutableArrayRef Params, + TemplateParameterList **Params, unsigned NumParams, FriendUnion Friend, SourceLocation FriendLoc) - : Decl(Decl::FriendTemplate, DC, Loc), NumParams(Params.size()), - Params(Params.data()), Friend(Friend), FriendLoc(FriendLoc) {} + : Decl(Decl::FriendTemplate, DC, Loc), NumParams(NumParams), + Params(Params), Friend(Friend), FriendLoc(FriendLoc) {} FriendTemplateDecl(EmptyShell Empty) : Decl(Decl::FriendTemplate, Empty) {} diff --git a/clang/lib/AST/DeclTemplate.cpp b/clang/lib/AST/DeclTemplate.cpp index 223f06b9db1c9..d9ff3517a589c 100644 --- a/clang/lib/AST/DeclTemplate.cpp +++ b/clang/lib/AST/DeclTemplate.cpp @@ -28,6 +28,7 @@ #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/None.h" #include "llvm/ADT/PointerUnion.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Casting.h" #include "llvm/Support/ErrorHandling.h" @@ -1098,7 +1099,13 @@ FriendTemplateDecl::Create(ASTContext &Context, DeclContext *DC, SourceLocation L, MutableArrayRef Params, FriendUnion Friend, SourceLocation FLoc) { - return new (Context, DC) FriendTemplateDecl(DC, L, Params, Friend, FLoc); + TemplateParameterList **TPL = nullptr; + if (!Params.empty()) { + TPL = new (Context) TemplateParameterList *[Params.size()]; + llvm::copy(Params, TPL); + } + return new (Context, DC) + FriendTemplateDecl(DC, L, TPL, Params.size(), Friend, FLoc); } FriendTemplateDecl *FriendTemplateDecl::CreateDeserialized(ASTContext &C, diff --git a/clang/test/SemaTemplate/friend-template.cpp b/clang/test/SemaTemplate/friend-template.cpp index e9b2b9b8e64e5..2dcee6c76da7d 100644 --- a/clang/test/SemaTemplate/friend-template.cpp +++ b/clang/test/SemaTemplate/friend-template.cpp @@ -329,3 +329,12 @@ namespace rdar12350696 { foo(b); // expected-note {{in instantiation}} } } + +namespace StackUseAfterScope { +template class Bar {}; +class Foo { + // Make sure this doesn't crash. + template <> friend class Bar; // expected-error {{template specialization declaration cannot be a friend}} + bool aux; +}; +} From aadd03a2accd7af22a9377f5f76b140013f8841d Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Thu, 17 Feb 2022 22:01:29 +0100 Subject: [PATCH 178/316] [clang][ASTReader] Fix memory leak while reading FriendTemplateDecls Allocate on ASTContext, rather than just on heap, so that template parameter lists are freed up. Differential Revision: https://reviews.llvm.org/D120081 (cherry picked from commit 977b1f574fa18219fde5f709b906c79202ef1916) --- clang/lib/Serialization/ASTReaderDecl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index 1ab26e58a4040..5d63a26132b73 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -2103,7 +2103,7 @@ void ASTDeclReader::VisitFriendTemplateDecl(FriendTemplateDecl *D) { VisitDecl(D); unsigned NumParams = Record.readInt(); D->NumParams = NumParams; - D->Params = new TemplateParameterList*[NumParams]; + D->Params = new (Reader.getContext()) TemplateParameterList *[NumParams]; for (unsigned i = 0; i != NumParams; ++i) D->Params[i] = Record.readTemplateParameterList(); if (Record.readInt()) // HasFriendDecl From a2398c560144fbf30058c97c93492023d5c50cad Mon Sep 17 00:00:00 2001 From: Todd Mortimer Date: Sun, 27 Feb 2022 19:43:49 -0500 Subject: [PATCH 179/316] [Driver][OpenBSD] Enable unwind tables on all architectures (cherry picked from commit bcbb03754ef19a8682635ab83fe5283db27b94f5) --- clang/lib/Driver/ToolChains/OpenBSD.h | 4 ++++ clang/test/Driver/openbsd.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/clang/lib/Driver/ToolChains/OpenBSD.h b/clang/lib/Driver/ToolChains/OpenBSD.h index 95c10cc62316e..9d668711b91b3 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.h +++ b/clang/lib/Driver/ToolChains/OpenBSD.h @@ -82,6 +82,10 @@ class LLVM_LIBRARY_VISIBILITY OpenBSD : public Generic_ELF { std::string getCompilerRT(const llvm::opt::ArgList &Args, StringRef Component, FileType Type = ToolChain::FT_Static) const override; + bool IsUnwindTablesDefault(const llvm::opt::ArgList &Args) const override { + return true; + } + LangOptions::StackProtectorMode GetDefaultStackProtectorLevel(bool KernelOrKext) const override { return LangOptions::SSPStrong; diff --git a/clang/test/Driver/openbsd.c b/clang/test/Driver/openbsd.c index d6d5ae994e67e..e46de575aec09 100644 --- a/clang/test/Driver/openbsd.c +++ b/clang/test/Driver/openbsd.c @@ -121,3 +121,10 @@ // RUN: %clang -target powerpc-unknown-openbsd -### -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-POWERPC-SECUREPLT %s // CHECK-POWERPC-SECUREPLT: "-target-feature" "+secure-plt" + +// Check that unwind tables are enabled +// RUN: %clang -target arm-unknown-openbsd -### -S %s 2>&1 | \ +// RUN: FileCheck -check-prefix=UNWIND-TABLES %s +// RUN: %clang -target mips64-unknown-openbsd -### -S %s 2>&1 | \ +// RUN: FileCheck -check-prefix=UNWIND-TABLES %s +// UNWIND-TABLES: "-funwind-tables=2" From 4fe93c000b204d4d8a9a458e5eb2d4fabd85ba5e Mon Sep 17 00:00:00 2001 From: Brendon Cahoon Date: Sun, 20 Feb 2022 18:18:26 -0600 Subject: [PATCH 180/316] [SLP] Fix assert from non-constant index in insertelement A call to getInsertIndex() in getTreeCost() is returning None, which causes an assert because a non-constant index value for insertelement was not expected. This case occurs when the insertelement index value is defined with a PHI. Differential Revision: https://reviews.llvm.org/D120223 (cherry picked from commit 3cc15e2cb657f3a814c8bd482bb7108782561abd) --- .../Transforms/Vectorize/SLPVectorizer.cpp | 62 ++++++++++--------- .../slp-variable-insertelement.ll | 31 ++++++++++ 2 files changed, 63 insertions(+), 30 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/slp-variable-insertelement.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 8a58b52df45d0..9eafd94efea28 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -5682,39 +5682,41 @@ InstructionCost BoUpSLP::getTreeCost(ArrayRef VectorizedVals) { // to detect it as a final shuffled/identity match. if (auto *VU = dyn_cast_or_null(EU.User)) { if (auto *FTy = dyn_cast(VU->getType())) { - unsigned InsertIdx = *getInsertIndex(VU); - auto *It = find_if(FirstUsers, [VU](Value *V) { - return areTwoInsertFromSameBuildVector(VU, - cast(V)); - }); - int VecId = -1; - if (It == FirstUsers.end()) { - VF.push_back(FTy->getNumElements()); - ShuffleMask.emplace_back(VF.back(), UndefMaskElem); - // Find the insertvector, vectorized in tree, if any. - Value *Base = VU; - while (isa(Base)) { - // Build the mask for the vectorized insertelement instructions. - if (const TreeEntry *E = getTreeEntry(Base)) { - VU = cast(Base); - do { - int Idx = E->findLaneForValue(Base); - ShuffleMask.back()[Idx] = Idx; - Base = cast(Base)->getOperand(0); - } while (E == getTreeEntry(Base)); - break; + Optional InsertIdx = getInsertIndex(VU); + if (InsertIdx) { + auto *It = find_if(FirstUsers, [VU](Value *V) { + return areTwoInsertFromSameBuildVector(VU, + cast(V)); + }); + int VecId = -1; + if (It == FirstUsers.end()) { + VF.push_back(FTy->getNumElements()); + ShuffleMask.emplace_back(VF.back(), UndefMaskElem); + // Find the insertvector, vectorized in tree, if any. + Value *Base = VU; + while (isa(Base)) { + // Build the mask for the vectorized insertelement instructions. + if (const TreeEntry *E = getTreeEntry(Base)) { + VU = cast(Base); + do { + int Idx = E->findLaneForValue(Base); + ShuffleMask.back()[Idx] = Idx; + Base = cast(Base)->getOperand(0); + } while (E == getTreeEntry(Base)); + break; + } + Base = cast(Base)->getOperand(0); } - Base = cast(Base)->getOperand(0); + FirstUsers.push_back(VU); + DemandedElts.push_back(APInt::getZero(VF.back())); + VecId = FirstUsers.size() - 1; + } else { + VecId = std::distance(FirstUsers.begin(), It); } - FirstUsers.push_back(VU); - DemandedElts.push_back(APInt::getZero(VF.back())); - VecId = FirstUsers.size() - 1; - } else { - VecId = std::distance(FirstUsers.begin(), It); + ShuffleMask[VecId][*InsertIdx] = EU.Lane; + DemandedElts[VecId].setBit(*InsertIdx); + continue; } - ShuffleMask[VecId][InsertIdx] = EU.Lane; - DemandedElts[VecId].setBit(InsertIdx); - continue; } } diff --git a/llvm/test/Transforms/SLPVectorizer/slp-variable-insertelement.ll b/llvm/test/Transforms/SLPVectorizer/slp-variable-insertelement.ll new file mode 100644 index 0000000000000..d97bfe59e55c6 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/slp-variable-insertelement.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -slp-vectorizer -slp-max-vf=2 -slp-min-reg-size=32 -S < %s | FileCheck %s + +; It is possible to compute the tree cost for an insertelement that does not +; have a constant index when the index is a PHI. Check if getInsertIndex +; returns None. + +define void @test() local_unnamed_addr { +; CHECK-LABEL: @test( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: unreachable +; CHECK: for.body: +; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ poison, [[FOR_BODY]] ] +; CHECK-NEXT: [[J:%.*]] = phi i32 [ poison, [[ENTRY]] ], [ 0, [[FOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 poison, i32 [[I]] +; CHECK-NEXT: br i1 poison, label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] +; +entry: + br label %for.body + +for.cond.cleanup: + unreachable + +for.body: + %i = phi i32 [ 0, %entry ], [ poison, %for.body ] + %j = phi i32 [ poison, %entry ], [ 0, %for.body ] + %0 = insertelement <4 x i32> poison, i32 poison, i32 %i + br i1 poison, label %for.cond.cleanup, label %for.body +} From 64534d2f406c0cb87502b617940cb0d39b7ff489 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Mon, 21 Feb 2022 10:38:08 +0000 Subject: [PATCH 181/316] [InstCombine] Bail out of load-store forwarding for scalable vector types This patch fixes an invalid TypeSize->uint64_t implicit conversion in FoldReinterpretLoadFromConst. If the size of the constant is scalable we bail out of the optimisation for now. Tests added here: Transforms/InstCombine/load-store-forward.ll Differential Revision: https://reviews.llvm.org/D120240 (cherry picked from commit 47eff645d8e873ba531014751c1c06a716a367e9) --- llvm/lib/Analysis/ConstantFolding.cpp | 9 +- .../InstCombine/load-store-forward.ll | 169 ++++++++++++++++++ 2 files changed, 175 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index 7cf69f613c669..c0a9304b6257f 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -589,14 +589,17 @@ Constant *FoldReinterpretLoadFromConst(Constant *C, Type *LoadTy, if (BytesLoaded > 32 || BytesLoaded == 0) return nullptr; - int64_t InitializerSize = DL.getTypeAllocSize(C->getType()).getFixedSize(); - // If we're not accessing anything in this constant, the result is undefined. if (Offset <= -1 * static_cast(BytesLoaded)) return UndefValue::get(IntType); + // TODO: We should be able to support scalable types. + TypeSize InitializerSize = DL.getTypeAllocSize(C->getType()); + if (InitializerSize.isScalable()) + return nullptr; + // If we're not accessing anything in this constant, the result is undefined. - if (Offset >= InitializerSize) + if (Offset >= InitializerSize.getFixedValue()) return UndefValue::get(IntType); unsigned char RawBytes[32] = {0}; diff --git a/llvm/test/Transforms/InstCombine/load-store-forward.ll b/llvm/test/Transforms/InstCombine/load-store-forward.ll index c1a01454772f2..c7afe3c4c79fc 100644 --- a/llvm/test/Transforms/InstCombine/load-store-forward.ll +++ b/llvm/test/Transforms/InstCombine/load-store-forward.ll @@ -120,3 +120,172 @@ define i32 @vec_store_load_overlap(i32* %p) { %load = load i32, i32* %p5, align 2 ret i32 %load } + +define i32 @load_i32_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_i32_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 +; CHECK-NEXT: ret i32 [[TMP1]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %1 = load i32, i32* %a, align 4 + ret i32 %1 +} + +define i64 @load_i64_store_nxv8i8(i8* %a) { +; CHECK-LABEL: @load_i64_store_nxv8i8( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i8 1, i32 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[A2:%.*]] = bitcast i8* [[A]] to i64* +; CHECK-NEXT: [[LOAD:%.*]] = load i64, i64* [[A2]], align 8 +; CHECK-NEXT: ret i64 [[LOAD]] +; +entry: + %0 = bitcast i8* %a to * + store shufflevector ( insertelement ( poison, i8 1, i32 0), poison, zeroinitializer), * %0, align 16 + %a2 = bitcast i8* %a to i64* + %load = load i64, i64* %a2, align 8 + ret i64 %load +} + +define i64 @load_i64_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_i64_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[A2:%.*]] = bitcast i32* [[A]] to i64* +; CHECK-NEXT: [[LOAD:%.*]] = load i64, i64* [[A2]], align 8 +; CHECK-NEXT: ret i64 [[LOAD]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %a2 = bitcast i32* %a to i64* + %load = load i64, i64* %a2, align 8 + ret i64 %load +} + +define i8 @load_i8_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_i8_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[A2:%.*]] = bitcast i32* [[A]] to i8* +; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[A2]], align 1 +; CHECK-NEXT: ret i8 [[LOAD]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %a2 = bitcast i32* %a to i8* + %load = load i8, i8* %a2, align 1 + ret i8 %load +} + +define float @load_f32_store_nxv4f32(float* %a) { +; CHECK-LABEL: @load_f32_store_nxv4f32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, float 1.000000e+00, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[A]], align 4 +; CHECK-NEXT: ret float [[TMP1]] +; +entry: + %0 = bitcast float* %a to * + store shufflevector ( insertelement ( poison, float 1.0, i64 0), poison, zeroinitializer), * %0, align 16 + %1 = load float, float* %a, align 4 + ret float %1 +} + +define i32 @load_i32_store_nxv4f32(float* %a) { +; CHECK-LABEL: @load_i32_store_nxv4f32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, float 1.000000e+00, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[A2:%.*]] = bitcast float* [[A]] to i32* +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[A2]], align 4 +; CHECK-NEXT: ret i32 [[LOAD]] +; +entry: + %0 = bitcast float* %a to * + store shufflevector ( insertelement ( poison, float 1.0, i64 0), poison, zeroinitializer), * %0, align 16 + %a2 = bitcast float* %a to i32* + %load = load i32, i32* %a2, align 4 + ret i32 %load +} + +define <4 x i32> @load_v4i32_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_v4i32_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[A]] to <4 x i32>* +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 16 +; CHECK-NEXT: ret <4 x i32> [[TMP2]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %1 = bitcast i32* %a to <4 x i32>* + %2 = load <4 x i32>, <4 x i32>* %1, align 16 + ret <4 x i32> %2 +} + +define <4 x i16> @load_v4i16_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_v4i16_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[A]] to <4 x i16>* +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 16 +; CHECK-NEXT: ret <4 x i16> [[TMP2]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %1 = bitcast i32* %a to <4 x i16>* + %2 = load <4 x i16>, <4 x i16>* %1, align 16 + ret <4 x i16> %2 +} + +; Loaded data type exceeds the known minimum size of the store. +define i64 @load_i64_store_nxv4i8(i8* %a) { +; CHECK-LABEL: @load_i64_store_nxv4i8( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i8 1, i32 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[A2:%.*]] = bitcast i8* [[A]] to i64* +; CHECK-NEXT: [[LOAD:%.*]] = load i64, i64* [[A2]], align 8 +; CHECK-NEXT: ret i64 [[LOAD]] +; +entry: + %0 = bitcast i8* %a to * + store shufflevector ( insertelement ( poison, i8 1, i32 0), poison, zeroinitializer), * %0, align 16 + %a2 = bitcast i8* %a to i64* + %load = load i64, i64* %a2, align 8 + ret i64 %load +} + +; Loaded data size is unknown - we cannot guarantee it won't +; exceed the store size. +define @load_nxv4i8_store_nxv4i32(i32* %a) { +; CHECK-LABEL: @load_nxv4i8_store_nxv4i32( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A:%.*]] to * +; CHECK-NEXT: store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * [[TMP0]], align 16 +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[A]] to * +; CHECK-NEXT: [[TMP2:%.*]] = load , * [[TMP1]], align 16 +; CHECK-NEXT: ret [[TMP2]] +; +entry: + %0 = bitcast i32* %a to * + store shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer), * %0, align 16 + %1 = bitcast i32* %a to * + %2 = load , * %1, align 16 + ret %2 +} From 5f5b687460c3b1660e7a8a034ddfc5807fe41a8c Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Tue, 22 Feb 2022 09:36:52 +0000 Subject: [PATCH 182/316] Fix warning introduced by 47eff645d8e873ba531014751c1c06a716a367e9 (cherry picked from commit dc0657277f2ff53f4e3ab01d856bcc576867ba9e) --- llvm/lib/Analysis/ConstantFolding.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index c0a9304b6257f..f6b955162fa52 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -599,7 +599,7 @@ Constant *FoldReinterpretLoadFromConst(Constant *C, Type *LoadTy, return nullptr; // If we're not accessing anything in this constant, the result is undefined. - if (Offset >= InitializerSize.getFixedValue()) + if (Offset >= (int64_t)InitializerSize.getFixedValue()) return UndefValue::get(IntType); unsigned char RawBytes[32] = {0}; From 61e78c64a38ae4a4d1e0ab1fa87d81de830a0162 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Sat, 12 Feb 2022 10:29:33 +0100 Subject: [PATCH 183/316] [libunwind] Only include cet.h if __CET__ defined We should not assume that the cet.h header exists just because we're on x86 linux. Only include it if __CET__ is defined. This makes the code more similar to what compiler-rt does in https://github.com/llvm/llvm-project/blob/ee423d93ead39e94c2970b3cc7ef6e6faa75d10b/compiler-rt/lib/builtins/assembly.h#L17 (though that one also has a __has_include() check -- I've not found that to be necessary). Differential Revision: https://reviews.llvm.org/D119697 (cherry picked from commit 2d2ef384b2f6e723edb793d08f52e7f4dc94ba3a) --- libunwind/src/assembly.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libunwind/src/assembly.h b/libunwind/src/assembly.h index 978f6bd619bd3..89293a555bfc4 100644 --- a/libunwind/src/assembly.h +++ b/libunwind/src/assembly.h @@ -15,7 +15,7 @@ #ifndef UNWIND_ASSEMBLY_H #define UNWIND_ASSEMBLY_H -#if (defined(__i386__) || defined(__x86_64__)) && defined(__linux__) +#if defined(__linux__) && defined(__CET__) #include #define _LIBUNWIND_CET_ENDBR _CET_ENDBR #else From ee0ae47691d30802ae1eeb056d53886800d3c2fa Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Wed, 23 Feb 2022 11:05:46 +0000 Subject: [PATCH 184/316] [RISCV] Avoid infinite loop between DAGCombiner::visitMUL and RISCVISelLowering::transformAddImmMulImm See https://github.com/llvm/llvm-project/issues/53831 for a full discussion. The basic issue is that DAGCombiner::visitMUL and RISCVISelLowering;:transformAddImmMullImm get stuck in a loop, as the current checks in transformAddImmMulImm aren't sufficient to avoid all cases where DAGCombiner::isMulAddWithConstProfitable might trigger a transformation. This patch makes transformAddImmMulImm bail out if C0 (the constant used for multiplication) has more than one use. Differential Revision: https://reviews.llvm.org/D120332 (cherry picked from commit c5bcfb983e47167a8a1826c1a64d7aa1849add06) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 +++++ llvm/test/CodeGen/RISCV/addimm-mulimm.ll | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2fe491ad5ea42..7f5555b9b7a85 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7203,6 +7203,11 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG, auto *N1C = dyn_cast(N->getOperand(1)); if (!N0C || !N1C) return SDValue(); + // If N0C has multiple uses it's possible one of the cases in + // DAGCombiner::isMulAddWithConstProfitable will be true, which would result + // in an infinite loop. + if (!N0C->hasOneUse()) + return SDValue(); int64_t C0 = N0C->getSExtValue(); int64_t C1 = N1C->getSExtValue(); int64_t CA, CB; diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll index 4706f3904701d..adf0b98742e1b 100644 --- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -872,3 +872,16 @@ define i64 @mulneg3000_sub8990_c(i64 %x) { %tmp1 = add i64 %tmp0, -8990 ret i64 %tmp1 } + +; This test case previously caused an infinite loop between transformations +; performed in RISCVISelLowering;:transformAddImmMulImm and +; DAGCombiner::visitMUL. +define i1 @pr53831(i32 %x) { + %tmp0 = add i32 %x, 1 + %tmp1 = mul i32 %tmp0, 24 + %tmp2 = add i32 %tmp1, 1 + %tmp3 = mul i32 %x, 24 + %tmp4 = add i32 %tmp3, 2048 + %tmp5 = icmp eq i32 %tmp4, %tmp2 + ret i1 %tmp5 +} From 03cf88fc94da55b989f1c14cb0460777834749c0 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 15 Feb 2022 13:04:52 +0100 Subject: [PATCH 185/316] [DSE] Extract a common PDT check (NFC) --- .../Scalar/DeadStoreElimination.cpp | 77 +++++++++---------- 1 file changed, 36 insertions(+), 41 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index ae636e7b61f72..8739ddce91606 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -1508,54 +1508,49 @@ struct DSEState { CommonPred = PDT.findNearestCommonDominator(CommonPred, BB); } - // If CommonPred is in the set of killing blocks, just check if it - // post-dominates MaybeDeadAccess. - if (KillingBlocks.count(CommonPred)) { - if (PDT.dominates(CommonPred, MaybeDeadAccess->getBlock())) - return {MaybeDeadAccess}; - return None; - } - // If the common post-dominator does not post-dominate MaybeDeadAccess, // there is a path from MaybeDeadAccess to an exit not going through a // killing block. - if (PDT.dominates(CommonPred, MaybeDeadAccess->getBlock())) { - SetVector WorkList; - - // If CommonPred is null, there are multiple exits from the function. - // They all have to be added to the worklist. - if (CommonPred) - WorkList.insert(CommonPred); - else - for (BasicBlock *R : PDT.roots()) - WorkList.insert(R); - - NumCFGTries++; - // Check if all paths starting from an exit node go through one of the - // killing blocks before reaching MaybeDeadAccess. - for (unsigned I = 0; I < WorkList.size(); I++) { - NumCFGChecks++; - BasicBlock *Current = WorkList[I]; - if (KillingBlocks.count(Current)) - continue; - if (Current == MaybeDeadAccess->getBlock()) - return None; + if (!PDT.dominates(CommonPred, MaybeDeadAccess->getBlock())) + return None; - // MaybeDeadAccess is reachable from the entry, so we don't have to - // explore unreachable blocks further. - if (!DT.isReachableFromEntry(Current)) - continue; + // If CommonPred itself is in the set of killing blocks, we're done. + if (KillingBlocks.count(CommonPred)) + return {MaybeDeadAccess}; - for (BasicBlock *Pred : predecessors(Current)) - WorkList.insert(Pred); + SetVector WorkList; - if (WorkList.size() >= MemorySSAPathCheckLimit) - return None; - } - NumCFGSuccess++; - return {MaybeDeadAccess}; + // If CommonPred is null, there are multiple exits from the function. + // They all have to be added to the worklist. + if (CommonPred) + WorkList.insert(CommonPred); + else + for (BasicBlock *R : PDT.roots()) + WorkList.insert(R); + + NumCFGTries++; + // Check if all paths starting from an exit node go through one of the + // killing blocks before reaching MaybeDeadAccess. + for (unsigned I = 0; I < WorkList.size(); I++) { + NumCFGChecks++; + BasicBlock *Current = WorkList[I]; + if (KillingBlocks.count(Current)) + continue; + if (Current == MaybeDeadAccess->getBlock()) + return None; + + // MaybeDeadAccess is reachable from the entry, so we don't have to + // explore unreachable blocks further. + if (!DT.isReachableFromEntry(Current)) + continue; + + for (BasicBlock *Pred : predecessors(Current)) + WorkList.insert(Pred); + + if (WorkList.size() >= MemorySSAPathCheckLimit) + return None; } - return None; + NumCFGSuccess++; } // No aliasing MemoryUses of MaybeDeadAccess found, MaybeDeadAccess is From 453361d5ac0131ca713904bdd87166d429e17612 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 16 Feb 2022 14:06:40 +0000 Subject: [PATCH 186/316] [DSE] Fall back to CFG scan for unreachable terminators. Blocks with UnreachableInst terminators are considered as root nodes in the PDT. This pessimize DSE, if there are no aliasing reads from the potentially dead store and the block with the unreachable terminator. If any of the root nodes of the PDF has UnreachableInst as terminator, fall back to the CFG scan, even the common dominator of all killing blocks does not post-dominate the block with potentially dead store. It looks like the compile-time impact for the extra scans is negligible. https://llvm-compile-time-tracker.com/compare.php?from=779bbbf27fe631154bdfaac7a443f198d4654688&to=ac59945f1bec1c6a7d7f5590c8c69fd9c5369c53&stat=instructions Fixes #53800. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D119760 --- .../Scalar/DeadStoreElimination.cpp | 25 +++- .../multiblock-unreachable.ll | 136 ++++++++++++++++++ 2 files changed, 156 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index 8739ddce91606..c5c8e880eb3d5 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -770,6 +770,10 @@ struct DSEState { /// Keep track of instructions (partly) overlapping with killing MemoryDefs per /// basic block. MapVector IOLs; + // Check if there are root nodes that are terminated by UnreachableInst. + // Those roots pessimize post-dominance queries. If there are such roots, + // fall back to CFG scan starting from all non-unreachable roots. + bool AnyUnreachableExit; // Class contains self-reference, make sure it's not copied/moved. DSEState(const DSEState &) = delete; @@ -805,6 +809,10 @@ struct DSEState { // Collect whether there is any irreducible control flow in the function. ContainsIrreducibleLoops = mayContainIrreducibleControl(F, &LI); + + AnyUnreachableExit = any_of(PDT.roots(), [](const BasicBlock *E) { + return isa(E->getTerminator()); + }); } /// Return 'OW_Complete' if a store to the 'KillingLoc' location (by \p @@ -1511,22 +1519,29 @@ struct DSEState { // If the common post-dominator does not post-dominate MaybeDeadAccess, // there is a path from MaybeDeadAccess to an exit not going through a // killing block. - if (!PDT.dominates(CommonPred, MaybeDeadAccess->getBlock())) - return None; + if (!PDT.dominates(CommonPred, MaybeDeadAccess->getBlock())) { + if (!AnyUnreachableExit) + return None; + + // Fall back to CFG scan starting at all non-unreachable roots if not + // all paths to the exit go through CommonPred. + CommonPred = nullptr; + } // If CommonPred itself is in the set of killing blocks, we're done. if (KillingBlocks.count(CommonPred)) return {MaybeDeadAccess}; SetVector WorkList; - // If CommonPred is null, there are multiple exits from the function. // They all have to be added to the worklist. if (CommonPred) WorkList.insert(CommonPred); else - for (BasicBlock *R : PDT.roots()) - WorkList.insert(R); + for (BasicBlock *R : PDT.roots()) { + if (!isa(R->getTerminator())) + WorkList.insert(R); + } NumCFGTries++; // Check if all paths starting from an exit node go through one of the diff --git a/llvm/test/Transforms/DeadStoreElimination/multiblock-unreachable.ll b/llvm/test/Transforms/DeadStoreElimination/multiblock-unreachable.ll index 6548ec34ae0ac..a1af7271dcce0 100644 --- a/llvm/test/Transforms/DeadStoreElimination/multiblock-unreachable.ll +++ b/llvm/test/Transforms/DeadStoreElimination/multiblock-unreachable.ll @@ -57,3 +57,139 @@ bb50: ; preds = %bb43 bb53: ; preds = %bb53, %bb50, %bb22, %bb br label %bb53 } + +declare void @exit() + +define void @unreachable_exit_with_no_call(i64* noalias %ptr, i1 %c.1) { +; CHECK-LABEL: @unreachable_exit_with_no_call( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[C_1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: unreachable +; CHECK: if.end: +; CHECK-NEXT: store i64 0, i64* [[PTR:%.*]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 1, i64* %ptr, align 8 + br i1 %c.1, label %if.then, label %if.end + +if.then: + unreachable + +if.end: + store i64 0, i64* %ptr, align 8 + ret void +} + +; Test for PR53800. +define void @unreachable_exit_with_nounwind_call_pr53800(i64* noalias %ptr, i1 %c.1) { +; CHECK-LABEL: @unreachable_exit_with_nounwind_call_pr53800( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 [[C_1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: tail call void @exit() #[[ATTR0:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: if.end: +; CHECK-NEXT: store i64 0, i64* [[PTR:%.*]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 1, i64* %ptr, align 8 + br i1 %c.1, label %if.then, label %if.end + +if.then: + tail call void @exit() nounwind + unreachable + +if.end: + store i64 0, i64* %ptr, align 8 + ret void +} + +; The call @exit may read %ptr as it is not marked as noalias +define void @unreachable_exit_and_call_may_read(i64* %ptr, i1 %c.1) { +; CHECK-LABEL: @unreachable_exit_and_call_may_read( +; CHECK-NEXT: entry: +; CHECK-NEXT: store i64 1, i64* [[PTR:%.*]], align 8 +; CHECK-NEXT: br i1 [[C_1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: tail call void @exit() #[[ATTR0]] +; CHECK-NEXT: unreachable +; CHECK: if.end: +; CHECK-NEXT: store i64 0, i64* [[PTR]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 1, i64* %ptr, align 8 + br i1 %c.1, label %if.then, label %if.end + +if.then: + tail call void @exit() nounwind + unreachable + +if.end: + store i64 0, i64* %ptr, align 8 + ret void +} + +define void @unreachable_exit_with_may_unwind_call(i64* noalias %ptr, i1 %c.1) { +; CHECK-LABEL: @unreachable_exit_with_may_unwind_call( +; CHECK-NEXT: entry: +; CHECK-NEXT: store i64 1, i64* [[PTR:%.*]], align 8 +; CHECK-NEXT: br i1 [[C_1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: tail call void @exit() +; CHECK-NEXT: unreachable +; CHECK: if.end: +; CHECK-NEXT: store i64 0, i64* [[PTR]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 1, i64* %ptr, align 8 + br i1 %c.1, label %if.then, label %if.end + +if.then: + tail call void @exit() + unreachable + +if.end: + store i64 0, i64* %ptr, align 8 + ret void +} + +; Cannot remove the store in entry, because it is not dead on the path to e.1 +define void @unreachable_exit_but_another_exit(i64* noalias %ptr, i1 %c.1, i32 %s, i1 %c.2) { +; CHECK-LABEL: @unreachable_exit_but_another_exit( +; CHECK-NEXT: entry: +; CHECK-NEXT: store i64 1, i64* [[PTR:%.*]], align 8 +; CHECK-NEXT: br i1 [[C_1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +; CHECK: if.then: +; CHECK-NEXT: br i1 [[C_2:%.*]], label [[E_0:%.*]], label [[E_1:%.*]] +; CHECK: e.0: +; CHECK-NEXT: tail call void @exit() #[[ATTR0]] +; CHECK-NEXT: unreachable +; CHECK: e.1: +; CHECK-NEXT: ret void +; CHECK: if.end: +; CHECK-NEXT: store i64 0, i64* [[PTR]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 1, i64* %ptr, align 8 + br i1 %c.1, label %if.then, label %if.end + +if.then: + br i1 %c.2, label %e.0, label %e.1 + +e.0: + tail call void @exit() nounwind + unreachable + +e.1: + ret void + +if.end: + store i64 0, i64* %ptr, align 8 + ret void +} From 14c432b6a17a9ff447f2adecff4850fb62907aee Mon Sep 17 00:00:00 2001 From: Kelvin Li Date: Fri, 4 Feb 2022 22:15:14 -0500 Subject: [PATCH 187/316] [OpenMP] Add search path for llvm-strip Add the build directory to the search path for llvm-strip instead of solely relying on the PATH environment variable setting. Reviewed By: jhuber6 Differential Revision: https://reviews.llvm.org/D118965 (cherry picked from commit 8ea4aed50a9f84d9617219ccc936c005c5f31c24) --- clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index de0af187731d3..2f5ddb77b7b3f 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -310,7 +310,13 @@ extractFromBinary(const ObjectFile &Obj, // We will use llvm-strip to remove the now unneeded section containing the // offloading code. - ErrorOr StripPath = sys::findProgramByName("llvm-strip"); + void *P = (void *)(intptr_t)&Help; + StringRef COWDir = ""; + auto COWPath = sys::fs::getMainExecutable("llvm-strip", P); + if (!COWPath.empty()) + COWDir = sys::path::parent_path(COWPath); + ErrorOr StripPath = + sys::findProgramByName("llvm-strip", {COWDir}); if (!StripPath) return createStringError(StripPath.getError(), "Unable to find 'llvm-strip' in path"); From b29813fbbbaf222d80e422320fe67f4e3c0992be Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 7 Feb 2022 14:59:03 -0500 Subject: [PATCH 188/316] [OpenMP] Use executable path when searching for lld Summary: This patch changes the ClangLinkerWrapper to use the executable path when searching for the lld binary. Previously we relied on the program name. Also not finding 'llvm-strip' is not considered an error anymore because it is an optional optimization. (cherry picked from commit 7ee8bd60f225b36623114f52103b0ecb91e2fb64) --- .../ClangLinkerWrapper.cpp | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 2f5ddb77b7b3f..65c9a87edf3f1 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -174,6 +174,12 @@ static StringRef getDeviceFileExtension(StringRef DeviceTriple, return "o"; } +std::string getMainExecutable(const char *Name) { + void *Ptr = (void *)(intptr_t)&getMainExecutable; + auto COWPath = sys::fs::getMainExecutable(Name, Ptr); + return sys::path::parent_path(COWPath).str(); +} + /// Extract the device file from the string '-=.bc'. DeviceFile getBitcodeLibrary(StringRef LibraryStr) { auto DeviceAndPath = StringRef(LibraryStr).split('='); @@ -310,16 +316,12 @@ extractFromBinary(const ObjectFile &Obj, // We will use llvm-strip to remove the now unneeded section containing the // offloading code. - void *P = (void *)(intptr_t)&Help; - StringRef COWDir = ""; - auto COWPath = sys::fs::getMainExecutable("llvm-strip", P); - if (!COWPath.empty()) - COWDir = sys::path::parent_path(COWPath); ErrorOr StripPath = - sys::findProgramByName("llvm-strip", {COWDir}); + sys::findProgramByName("llvm-strip", {getMainExecutable("llvm-strip")}); if (!StripPath) - return createStringError(StripPath.getError(), - "Unable to find 'llvm-strip' in path"); + StripPath = sys::findProgramByName("llvm-strip"); + if (!StripPath) + return None; SmallString<128> TempFile; if (Error Err = createOutputFile(Prefix + "-host", Extension, TempFile)) @@ -608,9 +610,9 @@ Expected link(ArrayRef InputFiles, Triple TheTriple, namespace amdgcn { Expected link(ArrayRef InputFiles, Triple TheTriple, StringRef Arch) { - // AMDGPU uses the lld binary to link device object files. + // AMDGPU uses lld to link device object files. ErrorOr LLDPath = - sys::findProgramByName("lld", sys::path::parent_path(LinkerExecutable)); + sys::findProgramByName("lld", {getMainExecutable("lld")}); if (!LLDPath) LLDPath = sys::findProgramByName("lld"); if (!LLDPath) From 4de8e56982784b4eafa7df70662129cb553a5f10 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Sun, 27 Feb 2022 20:48:52 +0000 Subject: [PATCH 189/316] [RISCV] Fix parseBareSymbol to not double-parse top-level operators By failing to lex the token we end up both parsing it as a binary operator ourselves and parsing it as a unary operator when calling parseExpression on the RHS. For plus this is harmless but for minus this parses "foo - 4" as "foo - -4", effectively treating a top-level minus as a plus. Fixes https://github.com/llvm/llvm-project/issues/54105 Reviewed By: asb, MaskRay Differential Revision: https://reviews.llvm.org/D120635 (cherry picked from commit 6aa8521fdb7a551e32927cce71ecb0c424b51955) --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 ++ llvm/test/MC/RISCV/rvi-pseudos.s | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 95319d1b0b74e..9a6ffb20615b2 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1607,9 +1607,11 @@ OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) { return MatchOperand_Success; case AsmToken::Plus: Opcode = MCBinaryExpr::Add; + getLexer().Lex(); break; case AsmToken::Minus: Opcode = MCBinaryExpr::Sub; + getLexer().Lex(); break; } diff --git a/llvm/test/MC/RISCV/rvi-pseudos.s b/llvm/test/MC/RISCV/rvi-pseudos.s index 859f5fe640f6e..7a20cfc292fbc 100644 --- a/llvm/test/MC/RISCV/rvi-pseudos.s +++ b/llvm/test/MC/RISCV/rvi-pseudos.s @@ -187,3 +187,9 @@ sw a3, zero, a4 # CHECK: auipc a5, %pcrel_hi((255+a_symbol)-4) # CHECK: addi a5, a5, %pcrel_lo(.Lpcrel_hi30) lla a5, (0xFF + a_symbol) - 4 + +## Check that we don't double-parse a top-level minus. +# CHECK: .Lpcrel_hi31: +# CHECK: auipc a5, %pcrel_hi(a_symbol-4) +# CHECK: addi a5, a5, %pcrel_lo(.Lpcrel_hi31) +lla a5, a_symbol - 4 From 779871c3515add46508aa2901c838650eb01f2d3 Mon Sep 17 00:00:00 2001 From: Chia-hung Duan Date: Mon, 28 Feb 2022 18:21:28 +0000 Subject: [PATCH 190/316] [mlir-tblgen] Fix non-deterministic generating static verifier in DRR. Use SetVector instead of DenseSet to ensure we always generate the same name for the same function. This issue is found in https://github.com/llvm/llvm-project/issues/53768. Reviewed By: quinnp, rdzhabarov Differential Revision: https://reviews.llvm.org/D120514 (cherry picked from commit d56ef5ed20c5c1380c2d97e970c8fc4d4166bdb8) --- mlir/include/mlir/TableGen/CodeGenHelpers.h | 4 ++-- mlir/tools/mlir-tblgen/CodeGenHelpers.cpp | 4 ++-- mlir/tools/mlir-tblgen/RewriterGen.cpp | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/mlir/include/mlir/TableGen/CodeGenHelpers.h b/mlir/include/mlir/TableGen/CodeGenHelpers.h index db753f55cdf0f..d4d3294ea2a6f 100644 --- a/mlir/include/mlir/TableGen/CodeGenHelpers.h +++ b/mlir/include/mlir/TableGen/CodeGenHelpers.h @@ -114,7 +114,7 @@ class StaticVerifierFunctionEmitter { /// /// Constraints that do not meet the restriction that they can only reference /// `$_self`, `$_op`, and `$_builder` are not uniqued. - void emitPatternConstraints(const DenseSet &constraints); + void emitPatternConstraints(const ArrayRef constraints); /// Get the name of the static function used for the given type constraint. /// These functions are used for operand and result constraints and have the @@ -178,7 +178,7 @@ class StaticVerifierFunctionEmitter { /// Collect and unique all the constraints used by operations. void collectOpConstraints(ArrayRef opDefs); /// Collect and unique all pattern constraints. - void collectPatternConstraints(const DenseSet &constraints); + void collectPatternConstraints(ArrayRef constraints); /// The output stream. raw_ostream &os; diff --git a/mlir/tools/mlir-tblgen/CodeGenHelpers.cpp b/mlir/tools/mlir-tblgen/CodeGenHelpers.cpp index 973d50dab7ef3..7fb6d953b47f9 100644 --- a/mlir/tools/mlir-tblgen/CodeGenHelpers.cpp +++ b/mlir/tools/mlir-tblgen/CodeGenHelpers.cpp @@ -62,7 +62,7 @@ void StaticVerifierFunctionEmitter::emitOpConstraints( } void StaticVerifierFunctionEmitter::emitPatternConstraints( - const llvm::DenseSet &constraints) { + const llvm::ArrayRef constraints) { collectPatternConstraints(constraints); emitPatternConstraints(); } @@ -332,7 +332,7 @@ void StaticVerifierFunctionEmitter::collectOpConstraints( } void StaticVerifierFunctionEmitter::collectPatternConstraints( - const llvm::DenseSet &constraints) { + const llvm::ArrayRef constraints) { for (auto &leaf : constraints) { assert(leaf.isOperandMatcher() || leaf.isAttrMatcher()); collectConstraint( diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp index 4fcc880464c98..d37856112b196 100644 --- a/mlir/tools/mlir-tblgen/RewriterGen.cpp +++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp @@ -322,7 +322,7 @@ class StaticMatcherHelper { int staticMatcherCounter = 0; // The DagLeaf which contains type or attr constraint. - DenseSet constraints; + SetVector constraints; // Static type/attribute verification function emitter. StaticVerifierFunctionEmitter staticVerifierEmitter; @@ -1708,7 +1708,7 @@ void StaticMatcherHelper::populateStaticMatchers(raw_ostream &os) { } void StaticMatcherHelper::populateStaticConstraintFunctions(raw_ostream &os) { - staticVerifierEmitter.emitPatternConstraints(constraints); + staticVerifierEmitter.emitPatternConstraints(constraints.getArrayRef()); } void StaticMatcherHelper::addPattern(Record *record) { From 21f87ad9f590df3f016fa6c738b374b9971fb36e Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Mon, 14 Feb 2022 23:29:13 -0500 Subject: [PATCH 191/316] [Driver][NetBSD] -r: imply -nostdlib like GCC Similar to D116843 for Gnu.cpp Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D119655 (cherry picked from commit d241ce0f97e47afa4f01a643ebbb4eafd729b403) --- clang/lib/Driver/ToolChains/NetBSD.cpp | 9 ++++++--- clang/test/Driver/netbsd.c | 8 ++++++++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/clang/lib/Driver/ToolChains/NetBSD.cpp b/clang/lib/Driver/ToolChains/NetBSD.cpp index 37b1fc5215ff5..d1eda14a51f01 100644 --- a/clang/lib/Driver/ToolChains/NetBSD.cpp +++ b/clang/lib/Driver/ToolChains/NetBSD.cpp @@ -236,7 +236,8 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, assert(Output.isNothing() && "Invalid output."); } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { if (!Args.hasArg(options::OPT_shared)) { CmdArgs.push_back( Args.MakeArgString(ToolChain.GetFilePath("crt0.o"))); @@ -294,7 +295,8 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, } } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs, + options::OPT_r)) { // Use the static OpenMP runtime with -static-openmp bool StaticOpenMP = Args.hasArg(options::OPT_static_openmp) && !Args.hasArg(options::OPT_static); @@ -330,7 +332,8 @@ void netbsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, } } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) CmdArgs.push_back( Args.MakeArgString(ToolChain.GetFilePath("crtendS.o"))); diff --git a/clang/test/Driver/netbsd.c b/clang/test/Driver/netbsd.c index 812889309a0f7..b549b3cde9b5a 100644 --- a/clang/test/Driver/netbsd.c +++ b/clang/test/Driver/netbsd.c @@ -467,3 +467,11 @@ // RUN: %clang -target powerpc-unknown-netbsd -### -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=POWERPC-SECUREPLT %s // POWERPC-SECUREPLT: "-target-feature" "+secure-plt" + +// -r suppresses default -l and crt*.o like -nostdlib. +// RUN: %clang -no-canonical-prefixes -target x86_64-unknown-netbsd -r \ +// RUN: --sysroot=%S/Inputs/basic_netbsd_tree %s -### 2>&1 \ +// RUN: | FileCheck -check-prefix=RELOCATABLE %s +// RELOCATABLE: "-r" +// RELOCATABLE-NOT: "-l +// RELOCATABLE-NOT: crt{{[^.]+}}.o From e08bab88c9007a76a61330db3266eaa49ebe5683 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Mon, 14 Feb 2022 23:24:26 -0500 Subject: [PATCH 192/316] [Driver][DragonFly] -r: imply -nostdlib like GCC Similar to D116843 for Gnu.cpp Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D119656 (cherry picked from commit cbd9d136ef8164970957317737cf51182acd236c) --- clang/lib/Driver/ToolChains/DragonFly.cpp | 9 ++++++--- clang/test/Driver/dragonfly.c | 7 ++++++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/clang/lib/Driver/ToolChains/DragonFly.cpp b/clang/lib/Driver/ToolChains/DragonFly.cpp index 9568b47e89e67..8cfec6a6c4e05 100644 --- a/clang/lib/Driver/ToolChains/DragonFly.cpp +++ b/clang/lib/Driver/ToolChains/DragonFly.cpp @@ -91,7 +91,8 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, assert(Output.isNothing() && "Invalid output."); } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { if (!Args.hasArg(options::OPT_shared)) { if (Args.hasArg(options::OPT_pg)) CmdArgs.push_back( @@ -119,7 +120,8 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA); - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs, + options::OPT_r)) { CmdArgs.push_back("-L/usr/lib/gcc80"); if (!Args.hasArg(options::OPT_static)) { @@ -158,7 +160,8 @@ void dragonfly::Linker::ConstructJob(Compilation &C, const JobAction &JA, } } - if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) { + if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles, + options::OPT_r)) { if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_pie)) CmdArgs.push_back( Args.MakeArgString(getToolChain().GetFilePath("crtendS.o"))); diff --git a/clang/test/Driver/dragonfly.c b/clang/test/Driver/dragonfly.c index 20921bb38af0e..6c6d1909fe1b0 100644 --- a/clang/test/Driver/dragonfly.c +++ b/clang/test/Driver/dragonfly.c @@ -4,4 +4,9 @@ // CHECK: clang{{.*}}" "-cc1" "-triple" "x86_64-pc-dragonfly" // CHECK: ld{{.*}}" "--eh-frame-hdr" "-dynamic-linker" "/usr/libexec/ld-elf.so.{{.*}}" "--hash-style=gnu" "--enable-new-dtags" "-o" "a.out" "{{.*}}crt1.o" "{{.*}}crti.o" "{{.*}}crtbegin.o" "{{.*}}.o" "-L{{.*}}gcc{{.*}}" "-rpath" "{{.*}}gcc{{.*}}" "-lc" "-lgcc" "{{.*}}crtend.o" "{{.*}}crtn.o" - +// -r suppresses default -l and crt*.o like -nostdlib. +// RUN: %clang -### %s --target=x86_64-pc-dragonfly -r \ +// RUN: 2>&1 | FileCheck %s --check-prefix=RELOCATABLE +// RELOCATABLE: "-r" +// RELOCATABLE-NOT: "-l +// RELOCATABLE-NOT: {{.*}}crt{{[^.]+}}.o From d09f84adff1eb6003eedad1069e22e7d78a54e08 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Fri, 11 Feb 2022 18:07:20 +0100 Subject: [PATCH 193/316] [compiler-rt] Force ABI to libcxxabi when building cxustom libc++ Follow-up to 458ead66dc37, which replaced the bespoke CMakeLists.txt file for building a custom instrumented libc++ with an invocation of the runtimes build. In the the bespoke CMakeLists.txt, the LIBCXX_CXX_ABI setting was forced to libcxxabi, but this was not done for the CMake invocation for the runtimes build. This would cause CMake configuration issues on platforms where the default LIBCXX_CXX_ABI setting is not libcxxabi, such as FreeBSD. Add `-DLIBCXX_CXX_ABI=libcxxabi` to that invocation, to make sure the custom instrumented libc++ always uses the expected ABI. Reviewed By: phosek Differential Revision: https://reviews.llvm.org/D119554 (cherry picked from commit a9f1a9c00af3badc991028b313fcc701599c8ac2) --- compiler-rt/cmake/Modules/AddCompilerRT.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake index b69833cbcc09b..4a496fc18f657 100644 --- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake +++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake @@ -638,6 +638,7 @@ macro(add_custom_libcxx name prefix) -DLIBCXXABI_ENABLE_SHARED=OFF -DLIBCXXABI_HERMETIC_STATIC_LIBRARY=ON -DLIBCXXABI_INCLUDE_TESTS=OFF + -DLIBCXX_CXX_ABI=libcxxabi -DLIBCXX_ENABLE_EXPERIMENTAL_LIBRARY=OFF -DLIBCXX_ENABLE_SHARED=OFF -DLIBCXX_HERMETIC_STATIC_LIBRARY=ON From b3e9abd9683b11e81b7711fd654157b6b81b0509 Mon Sep 17 00:00:00 2001 From: George Koehler Date: Mon, 21 Feb 2022 15:15:53 -0500 Subject: [PATCH 194/316] [libunwind] Further fix for 32-bit PowerPC processors without AltiVec https://reviews.llvm.org/D91906 did most of the work necessary to fix libunwind on 32-bit PowerPC processors without AltiVec, but there was one more piece necessary. Reviewed By: luporl Differential Revision: https://reviews.llvm.org/D120197 (cherry picked from commit 3fa2e66c10aadac1d209afadba34d90c9bd95221) --- libunwind/src/UnwindRegistersSave.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libunwind/src/UnwindRegistersSave.S b/libunwind/src/UnwindRegistersSave.S index 9566bb0335fee..b39489235ce63 100644 --- a/libunwind/src/UnwindRegistersSave.S +++ b/libunwind/src/UnwindRegistersSave.S @@ -603,9 +603,11 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) stw 30,128(3) stw 31,132(3) +#if defined(__ALTIVEC__) // save VRSave register mfspr 0, 256 stw 0, 156(3) +#endif // save CR registers mfcr 0 stw 0, 136(3) From 3d913ec923083be7f8baeb3128849949e97b1f43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Sun, 6 Feb 2022 15:58:32 +0100 Subject: [PATCH 195/316] [llvm] [cmake] Fix finding modern ounit2 Apparently modern versions of ounit2 can only be found as "ounit2" rather than "oUnit" version 2. Update the CMake check to support both variants. This makes the OCaml tests run again with ounit2-2.2.4. Differential Revision: https://reviews.llvm.org/D119079 (cherry picked from commit 919dba9248f63d50e679ad5741d99ed8a8047227) --- llvm/cmake/config-ix.cmake | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/llvm/cmake/config-ix.cmake b/llvm/cmake/config-ix.cmake index a138d372d3b29..c70b8b3787a0a 100644 --- a/llvm/cmake/config-ix.cmake +++ b/llvm/cmake/config-ix.cmake @@ -650,7 +650,12 @@ else() find_ocamlfind_package(ctypes VERSION 0.4 OPTIONAL) if( HAVE_OCAML_CTYPES ) message(STATUS "OCaml bindings enabled.") - find_ocamlfind_package(oUnit VERSION 2 OPTIONAL) + find_ocamlfind_package(ounit2 OPTIONAL) + if ( HAVE_OCAML_OUNIT2 ) + set(HAVE_OCAML_OUNIT TRUE) + else() + find_ocamlfind_package(oUnit VERSION 2 OPTIONAL) + endif() set(LLVM_BINDINGS "${LLVM_BINDINGS} ocaml") set(LLVM_OCAML_INSTALL_PATH "${OCAML_STDLIB_PATH}" CACHE STRING From 4327d39b15b22b9ee23582e5455df5b2a093fe8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 1 Mar 2022 13:43:25 -0500 Subject: [PATCH 196/316] [libcxx] Add an explicit option to build against system-libcxxabi Add an explicit LIBCXX_CXX_ABI=system-libcxxabi option for linking to system-installed libc++abi. This fixes the ability to link against one when building libcxx via the runtimes build, as otherwise the build system insists on linking into in-tree targets. Differential Revision: https://reviews.llvm.org/D119539 (cherry picked from commit ba4f1e44e480d661d99973007a39dc642f5d79a4) --- libcxx/cmake/Modules/HandleLibCXXABI.cmake | 4 ++++ libcxx/docs/BuildingLibcxx.rst | 2 +- libcxx/utils/libcxx/test/config.py | 2 ++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/libcxx/cmake/Modules/HandleLibCXXABI.cmake b/libcxx/cmake/Modules/HandleLibCXXABI.cmake index d69405ddeeacf..9b5df6e015b35 100644 --- a/libcxx/cmake/Modules/HandleLibCXXABI.cmake +++ b/libcxx/cmake/Modules/HandleLibCXXABI.cmake @@ -118,6 +118,10 @@ elseif ("${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "libcxxabi") setup_abi_lib( "-DLIBCXX_BUILDING_LIBCXXABI" "${shared}" "${static}" "cxxabi.h;__cxxabi_config.h" "") +elseif ("${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "system-libcxxabi") + setup_abi_lib( + "-DLIBCXX_BUILDING_LIBCXXABI" + "c++abi" "c++abi" "cxxabi.h;__cxxabi_config.h" "") elseif ("${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "libcxxrt") if(NOT LIBCXX_CXX_ABI_INCLUDE_PATHS) set(LIBCXX_CXX_ABI_INCLUDE_PATHS "/usr/include/c++/v1") diff --git a/libcxx/docs/BuildingLibcxx.rst b/libcxx/docs/BuildingLibcxx.rst index a0c7672ff7717..544d06cc8c424 100644 --- a/libcxx/docs/BuildingLibcxx.rst +++ b/libcxx/docs/BuildingLibcxx.rst @@ -318,7 +318,7 @@ ABI Library Specific Options .. option:: LIBCXX_CXX_ABI:STRING - **Values**: ``none``, ``libcxxabi``, ``libcxxrt``, ``libstdc++``, ``libsupc++``. + **Values**: ``none``, ``libcxxabi``, ``system-libcxxabi``, ``libcxxrt``, ``libstdc++``, ``libsupc++``. Select the ABI library to build libc++ against. diff --git a/libcxx/utils/libcxx/test/config.py b/libcxx/utils/libcxx/test/config.py index fdc1ff4f714ab..152a9755206e1 100644 --- a/libcxx/utils/libcxx/test/config.py +++ b/libcxx/utils/libcxx/test/config.py @@ -410,6 +410,8 @@ def configure_link_flags_abi_library(self): self.cxx.link_flags += [abs_path] else: self.cxx.link_flags += ['-lc++abi'] + elif cxx_abi == 'system-libcxxabi': + self.cxx.link_flags += ['-lc++abi'] elif cxx_abi == 'libcxxrt': self.cxx.link_flags += ['-lcxxrt'] elif cxx_abi == 'vcruntime': From f58ab32850211621d5986da2d687be0d550e7140 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Wed, 16 Feb 2022 11:05:09 -0600 Subject: [PATCH 197/316] [Attributor][FIX] Pipe UsedAssumedInformation through more interfaces `UsedAssumedInformation` is a return argument utilized to determine what information is known. Most APIs used it already but `genericValueTraversal` did not. This adds it to `genericValueTraversal` and replaces `AllCallSitesKnown` of `checkForAllCallSites` with the commonly used `UsedAssumedInformation`. This was supposed to be a NFC commit, then the test change appeared. Turns out, we had one user of `AllCallSitesKnown` (AANoReturn) and the way we set `AllCallSitesKnown` was wrong as we ignored the fact some call sites were optimistically assumed dead. Included a dedicated test for this as well now. Fixes https://github.com/llvm/llvm-project/issues/53884 --- llvm/include/llvm/Transforms/IPO/Attributor.h | 14 +-- llvm/lib/Transforms/IPO/Attributor.cpp | 32 +++---- .../Transforms/IPO/AttributorAttributes.cpp | 91 ++++++++++++------- llvm/test/Transforms/Attributor/norecurse.ll | 50 +++++++++- .../OpenMP/custom_state_machines.ll | 40 ++++---- 5 files changed, 143 insertions(+), 84 deletions(-) diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h index 7eee16f71d64a..8677a0ba62f2a 100644 --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -192,6 +192,7 @@ bool getAssumedUnderlyingObjects(Attributor &A, const Value &Ptr, SmallVectorImpl &Objects, const AbstractAttribute &QueryingAA, const Instruction *CtxI, + bool &UsedAssumedInformation, bool Intraprocedural = false); /// Collect all potential values of the one stored by \p SI into @@ -1824,23 +1825,24 @@ struct Attributor { /// This method will evaluate \p Pred on call sites and return /// true if \p Pred holds in every call sites. However, this is only possible /// all call sites are known, hence the function has internal linkage. - /// If true is returned, \p AllCallSitesKnown is set if all possible call - /// sites of the function have been visited. + /// If true is returned, \p UsedAssumedInformation is set if assumed + /// information was used to skip or simplify potential call sites. bool checkForAllCallSites(function_ref Pred, const AbstractAttribute &QueryingAA, - bool RequireAllCallSites, bool &AllCallSitesKnown); + bool RequireAllCallSites, + bool &UsedAssumedInformation); /// Check \p Pred on all call sites of \p Fn. /// /// This method will evaluate \p Pred on call sites and return /// true if \p Pred holds in every call sites. However, this is only possible /// all call sites are known, hence the function has internal linkage. - /// If true is returned, \p AllCallSitesKnown is set if all possible call - /// sites of the function have been visited. + /// If true is returned, \p UsedAssumedInformation is set if assumed + /// information was used to skip or simplify potential call sites. bool checkForAllCallSites(function_ref Pred, const Function &Fn, bool RequireAllCallSites, const AbstractAttribute *QueryingAA, - bool &AllCallSitesKnown); + bool &UsedAssumedInformation); /// Check \p Pred on all values potentially returned by \p F. /// diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index d66140a726f69..7bca2084c448d 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -320,7 +320,8 @@ bool AA::getPotentialCopiesOfStoredValue( Value &Ptr = *SI.getPointerOperand(); SmallVector Objects; - if (!AA::getAssumedUnderlyingObjects(A, Ptr, Objects, QueryingAA, &SI)) { + if (!AA::getAssumedUnderlyingObjects(A, Ptr, Objects, QueryingAA, &SI, + UsedAssumedInformation)) { LLVM_DEBUG( dbgs() << "Underlying objects stored into could not be determined\n";); return false; @@ -514,10 +515,10 @@ isPotentiallyReachable(Attributor &A, const Instruction &FromI, return true; }; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; Result = !A.checkForAllCallSites(CheckCallSite, *FromFn, /* RequireAllCallSites */ true, - &QueryingAA, AllCallSitesKnown); + &QueryingAA, UsedAssumedInformation); if (Result) { LLVM_DEBUG(dbgs() << "[AA] stepping back to call sites from " << *CurFromI << " in @" << FromFn->getName() @@ -1277,7 +1278,7 @@ bool Attributor::checkForAllUses( bool Attributor::checkForAllCallSites(function_ref Pred, const AbstractAttribute &QueryingAA, bool RequireAllCallSites, - bool &AllCallSitesKnown) { + bool &UsedAssumedInformation) { // We can try to determine information from // the call sites. However, this is only possible all call sites are known, // hence the function has internal linkage. @@ -1286,31 +1287,26 @@ bool Attributor::checkForAllCallSites(function_ref Pred, if (!AssociatedFunction) { LLVM_DEBUG(dbgs() << "[Attributor] No function associated with " << IRP << "\n"); - AllCallSitesKnown = false; return false; } return checkForAllCallSites(Pred, *AssociatedFunction, RequireAllCallSites, - &QueryingAA, AllCallSitesKnown); + &QueryingAA, UsedAssumedInformation); } bool Attributor::checkForAllCallSites(function_ref Pred, const Function &Fn, bool RequireAllCallSites, const AbstractAttribute *QueryingAA, - bool &AllCallSitesKnown) { + bool &UsedAssumedInformation) { if (RequireAllCallSites && !Fn.hasLocalLinkage()) { LLVM_DEBUG( dbgs() << "[Attributor] Function " << Fn.getName() << " has no internal linkage, hence not all call sites are known\n"); - AllCallSitesKnown = false; return false; } - // If we do not require all call sites we might not see all. - AllCallSitesKnown = RequireAllCallSites; - SmallVector Uses(make_pointer_range(Fn.uses())); for (unsigned u = 0; u < Uses.size(); ++u) { const Use &U = *Uses[u]; @@ -1322,7 +1318,6 @@ bool Attributor::checkForAllCallSites(function_ref Pred, dbgs() << "[Attributor] Check use: " << *U << " in " << *U.getUser() << "\n"; }); - bool UsedAssumedInformation = false; if (isAssumedDead(U, QueryingAA, nullptr, UsedAssumedInformation, /* CheckBBLivenessOnly */ true)) { LLVM_DEBUG(dbgs() << "[Attributor] Dead use, skip!\n"); @@ -1795,7 +1790,7 @@ void Attributor::identifyDeadInternalFunctions() { if (!F) continue; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (checkForAllCallSites( [&](AbstractCallSite ACS) { Function *Callee = ACS.getInstruction()->getFunction(); @@ -1803,7 +1798,7 @@ void Attributor::identifyDeadInternalFunctions() { (Functions.count(Callee) && Callee->hasLocalLinkage() && !LiveInternalFns.count(Callee)); }, - *F, true, nullptr, AllCallSitesKnown)) { + *F, true, nullptr, UsedAssumedInformation)) { continue; } @@ -2290,9 +2285,9 @@ bool Attributor::isValidFunctionSignatureRewrite( } // Avoid callbacks for now. - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (!checkForAllCallSites(CallSiteCanBeChanged, *Fn, true, nullptr, - AllCallSitesKnown)) { + UsedAssumedInformation)) { LLVM_DEBUG(dbgs() << "[Attributor] Cannot rewrite all call sites\n"); return false; } @@ -2305,7 +2300,6 @@ bool Attributor::isValidFunctionSignatureRewrite( // Forbid must-tail calls for now. // TODO: - bool UsedAssumedInformation = false; auto &OpcodeInstMap = InfoCache.getOpcodeInstMapForFunction(*Fn); if (!checkForAllInstructionsImpl(nullptr, OpcodeInstMap, InstPred, nullptr, nullptr, {Instruction::Call}, @@ -2514,9 +2508,9 @@ ChangeStatus Attributor::rewriteFunctionSignatures( }; // Use the CallSiteReplacementCreator to create replacement call sites. - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; bool Success = checkForAllCallSites(CallSiteReplacementCreator, *OldFn, - true, nullptr, AllCallSitesKnown); + true, nullptr, UsedAssumedInformation); (void)Success; assert(Success && "Assumed call site replacement to succeed!"); diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 6dadfebae038d..5593a297d2d89 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -261,7 +261,8 @@ static bool genericValueTraversal( StateTy &State, function_ref VisitValueCB, - const Instruction *CtxI, bool UseValueSimplify = true, int MaxValues = 16, + const Instruction *CtxI, bool &UsedAssumedInformation, + bool UseValueSimplify = true, int MaxValues = 16, function_ref StripCB = nullptr, bool Intraprocedural = false) { @@ -321,7 +322,6 @@ static bool genericValueTraversal( // Look through select instructions, visit assumed potential values. if (auto *SI = dyn_cast(V)) { - bool UsedAssumedInformation = false; Optional C = A.getAssumedConstant( *SI->getCondition(), QueryingAA, UsedAssumedInformation); bool NoValueYet = !C.hasValue(); @@ -348,6 +348,7 @@ static bool genericValueTraversal( BasicBlock *IncomingBB = PHI->getIncomingBlock(u); if (LivenessAA->isEdgeDead(IncomingBB, PHI->getParent())) { AnyDead = true; + UsedAssumedInformation |= !LivenessAA->isAtFixpoint(); continue; } Worklist.push_back( @@ -359,7 +360,7 @@ static bool genericValueTraversal( if (auto *Arg = dyn_cast(V)) { if (!Intraprocedural && !Arg->hasPassPointeeByValueCopyAttr()) { SmallVector CallSiteValues; - bool AllCallSitesKnown = true; + bool UsedAssumedInformation = false; if (A.checkForAllCallSites( [&](AbstractCallSite ACS) { // Callbacks might not have a corresponding call site operand, @@ -370,7 +371,7 @@ static bool genericValueTraversal( CallSiteValues.push_back({CSOp, ACS.getInstruction()}); return true; }, - *Arg->getParent(), true, &QueryingAA, AllCallSitesKnown)) { + *Arg->getParent(), true, &QueryingAA, UsedAssumedInformation)) { Worklist.append(CallSiteValues); continue; } @@ -378,7 +379,6 @@ static bool genericValueTraversal( } if (UseValueSimplify && !isa(V)) { - bool UsedAssumedInformation = false; Optional SimpleV = A.getAssumedSimplified(*V, QueryingAA, UsedAssumedInformation); if (!SimpleV.hasValue()) @@ -413,6 +413,7 @@ bool AA::getAssumedUnderlyingObjects(Attributor &A, const Value &Ptr, SmallVectorImpl &Objects, const AbstractAttribute &QueryingAA, const Instruction *CtxI, + bool &UsedAssumedInformation, bool Intraprocedural) { auto StripCB = [&](Value *V) { return getUnderlyingObject(V); }; SmallPtrSet SeenObjects; @@ -425,7 +426,7 @@ bool AA::getAssumedUnderlyingObjects(Attributor &A, const Value &Ptr, }; if (!genericValueTraversal( A, IRPosition::value(Ptr), QueryingAA, Objects, VisitValueCB, CtxI, - true, 32, StripCB, Intraprocedural)) + UsedAssumedInformation, true, 32, StripCB, Intraprocedural)) return false; return true; } @@ -571,9 +572,9 @@ static void clampCallSiteArgumentStates(Attributor &A, const AAType &QueryingAA, return T->isValidState(); }; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (!A.checkForAllCallSites(CallSiteCheck, QueryingAA, true, - AllCallSitesKnown)) + UsedAssumedInformation)) S.indicatePessimisticFixpoint(); else if (T.hasValue()) S ^= *T; @@ -1895,17 +1896,18 @@ ChangeStatus AAReturnedValuesImpl::updateImpl(Attributor &A) { return true; }; + bool UsedAssumedInformation = false; auto ReturnInstCB = [&](Instruction &I) { ReturnInst &Ret = cast(I); return genericValueTraversal( A, IRPosition::value(*Ret.getReturnValue()), *this, Ret, ReturnValueCB, - &I, /* UseValueSimplify */ true, /* MaxValues */ 16, + &I, UsedAssumedInformation, /* UseValueSimplify */ true, + /* MaxValues */ 16, /* StripCB */ nullptr, /* Intraprocedural */ true); }; // Discover returned values from all live returned instructions in the // associated function. - bool UsedAssumedInformation = false; if (!A.checkForAllInstructions(ReturnInstCB, *this, {Instruction::Ret}, UsedAssumedInformation)) return indicatePessimisticFixpoint(); @@ -2421,8 +2423,10 @@ struct AANonNullFloating : public AANonNullImpl { }; StateType T; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, T, - VisitValueCB, getCtxI())) + VisitValueCB, getCtxI(), + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return clampStateAndIndicateChange(getState(), T); @@ -2500,14 +2504,15 @@ struct AANoRecurseFunction final : AANoRecurseImpl { DepClassTy::NONE); return NoRecurseAA.isKnownNoRecurse(); }; - bool AllCallSitesKnown; - if (A.checkForAllCallSites(CallSitePred, *this, true, AllCallSitesKnown)) { + bool UsedAssumedInformation = false; + if (A.checkForAllCallSites(CallSitePred, *this, true, + UsedAssumedInformation)) { // If we know all call sites and all are known no-recurse, we are done. // If all known call sites, which might not be all that exist, are known // to be no-recurse, we are not done but we can continue to assume // no-recurse. If one of the call sites we have not visited will become // live, another update is triggered. - if (AllCallSitesKnown) + if (!UsedAssumedInformation) indicateOptimisticFixpoint(); return ChangeStatus::UNCHANGED; } @@ -3147,10 +3152,10 @@ struct AANoAliasArgument final // If the argument is never passed through callbacks, no-alias cannot break // synchronization. - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (A.checkForAllCallSites( [](AbstractCallSite ACS) { return !ACS.isCallbackCall(); }, *this, - true, AllCallSitesKnown)) + true, UsedAssumedInformation)) return Base::updateImpl(A); // TODO: add no-alias but make sure it doesn't break synchronization by @@ -3728,9 +3733,8 @@ struct AAIsDeadReturned : public AAIsDeadValueImpl { return areAllUsesAssumedDead(A, *ACS.getInstruction()); }; - bool AllCallSitesKnown; if (!A.checkForAllCallSites(PredForCallSite, *this, true, - AllCallSitesKnown)) + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return ChangeStatus::UNCHANGED; @@ -4313,8 +4317,10 @@ struct AADereferenceableFloating : AADereferenceableImpl { }; DerefState T; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, T, - VisitValueCB, getCtxI())) + VisitValueCB, getCtxI(), + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return clampStateAndIndicateChange(getState(), T); @@ -4579,8 +4585,10 @@ struct AAAlignFloating : AAAlignImpl { }; StateType T; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, T, - VisitValueCB, getCtxI())) + VisitValueCB, getCtxI(), + UsedAssumedInformation)) return indicatePessimisticFixpoint(); // TODO: If we know we visited all incoming values, thus no are assumed @@ -5360,7 +5368,9 @@ struct AAValueSimplifyImpl : AAValueSimplify { Value &Ptr = *L.getPointerOperand(); SmallVector Objects; - if (!AA::getAssumedUnderlyingObjects(A, Ptr, Objects, AA, &L)) + bool UsedAssumedInformation = false; + if (!AA::getAssumedUnderlyingObjects(A, Ptr, Objects, AA, &L, + UsedAssumedInformation)) return false; const auto *TLI = @@ -5372,7 +5382,6 @@ struct AAValueSimplifyImpl : AAValueSimplify { if (isa(Obj)) { // A null pointer access can be undefined but any offset from null may // be OK. We do not try to optimize the latter. - bool UsedAssumedInformation = false; if (!NullPointerIsDefined(L.getFunction(), Ptr.getType()->getPointerAddressSpace()) && A.getAssumedSimplified(Ptr, AA, UsedAssumedInformation) == Obj) @@ -5478,14 +5487,14 @@ struct AAValueSimplifyArgument final : AAValueSimplifyImpl { // Generate a answer specific to a call site context. bool Success; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (hasCallBaseContext() && getCallBaseContext()->getCalledFunction() == Arg->getParent()) Success = PredForCallSite( AbstractCallSite(&getCallBaseContext()->getCalledOperandUse())); else Success = A.checkForAllCallSites(PredForCallSite, *this, true, - AllCallSitesKnown); + UsedAssumedInformation); if (!Success) if (!askSimplifiedValueForOtherAAs(A)) @@ -5755,8 +5764,10 @@ struct AAValueSimplifyFloating : AAValueSimplifyImpl { }; bool Dummy = false; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, Dummy, VisitValueCB, getCtxI(), + UsedAssumedInformation, /* UseValueSimplify */ false)) if (!askSimplifiedValueForOtherAAs(A)) return indicatePessimisticFixpoint(); @@ -6168,7 +6179,8 @@ ChangeStatus AAHeapToStackFunction::updateImpl(Attributor &A) { // branches etc. SmallVector Objects; if (!AA::getAssumedUnderlyingObjects(A, *DI.CB->getArgOperand(0), Objects, - *this, DI.CB)) { + *this, DI.CB, + UsedAssumedInformation)) { LLVM_DEBUG( dbgs() << "[H2S] Unexpected failure in getAssumedUnderlyingObjects!\n"); @@ -6446,10 +6458,10 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { Optional identifyPrivatizableType(Attributor &A) override { // If this is a byval argument and we know all the call sites (so we can // rewrite them), there is no need to check them explicitly. - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (getIRPosition().hasAttr(Attribute::ByVal) && A.checkForAllCallSites([](AbstractCallSite ACS) { return true; }, *this, - true, AllCallSitesKnown)) + true, UsedAssumedInformation)) return getAssociatedValue().getType()->getPointerElementType(); Optional Ty; @@ -6499,7 +6511,8 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { return !Ty.hasValue() || Ty.getValue(); }; - if (!A.checkForAllCallSites(CallSiteCheck, *this, true, AllCallSitesKnown)) + if (!A.checkForAllCallSites(CallSiteCheck, *this, true, + UsedAssumedInformation)) return nullptr; return Ty; } @@ -6546,9 +6559,9 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { return TTI->areTypesABICompatible( CB->getCaller(), CB->getCalledFunction(), ReplacementTypes); }; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; if (!A.checkForAllCallSites(CallSiteCheck, *this, true, - AllCallSitesKnown)) { + UsedAssumedInformation)) { LLVM_DEBUG( dbgs() << "[AAPrivatizablePtr] ABI incompatibility detected for " << Fn.getName() << "\n"); @@ -6675,7 +6688,7 @@ struct AAPrivatizablePtrArgument final : public AAPrivatizablePtrImpl { }; if (!A.checkForAllCallSites(IsCompatiblePrivArgOfOtherCallSite, *this, true, - AllCallSitesKnown)) + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return ChangeStatus::UNCHANGED; @@ -7775,7 +7788,9 @@ void AAMemoryLocationImpl::categorizePtrValue( << getMemoryLocationsAsStr(State.getAssumed()) << "]\n"); SmallVector Objects; + bool UsedAssumedInformation = false; if (!AA::getAssumedUnderlyingObjects(A, Ptr, Objects, *this, &I, + UsedAssumedInformation, /* Intraprocedural */ true)) { LLVM_DEBUG( dbgs() << "[AAMemoryLocation] Pointer locations not categorized\n"); @@ -8591,8 +8606,10 @@ struct AAValueConstantRangeFloating : AAValueConstantRangeImpl { IntegerRangeState T(getBitWidth()); + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, T, VisitValueCB, getCtxI(), + UsedAssumedInformation, /* UseValueSimplify */ false)) return indicatePessimisticFixpoint(); @@ -9403,8 +9420,10 @@ struct AANoUndefFloating : public AANoUndefImpl { }; StateType T; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, getIRPosition(), *this, T, - VisitValueCB, getCtxI())) + VisitValueCB, getCtxI(), + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return clampStateAndIndicateChange(getState(), T); @@ -9521,9 +9540,10 @@ struct AACallEdgesCallSite : public AACallEdgesImpl { // Process any value that we might call. auto ProcessCalledOperand = [&](Value *V) { bool DummyValue = false; + bool UsedAssumedInformation = false; if (!genericValueTraversal(A, IRPosition::value(*V), *this, DummyValue, VisitValue, nullptr, - false)) { + UsedAssumedInformation, false)) { // If we haven't gone through all values, assume that there are unknown // callees. setHasUnknownCallee(true, Change); @@ -9942,12 +9962,13 @@ struct AAAssumptionInfoFunction final : AAAssumptionInfoImpl { return !getAssumed().empty() || !getKnown().empty(); }; - bool AllCallSitesKnown; + bool UsedAssumedInformation = false; // Get the intersection of all assumptions held by this node's predecessors. // If we don't know all the call sites then this is either an entry into the // call graph or an empty node. This node is known to only contain its own // assumptions and can be propagated to its successors. - if (!A.checkForAllCallSites(CallSitePred, *this, true, AllCallSitesKnown)) + if (!A.checkForAllCallSites(CallSitePred, *this, true, + UsedAssumedInformation)) return indicatePessimisticFixpoint(); return Changed ? ChangeStatus::CHANGED : ChangeStatus::UNCHANGED; diff --git a/llvm/test/Transforms/Attributor/norecurse.ll b/llvm/test/Transforms/Attributor/norecurse.ll index 61bba0a6044ed..dd096a32c147b 100644 --- a/llvm/test/Transforms/Attributor/norecurse.ll +++ b/llvm/test/Transforms/Attributor/norecurse.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -71,7 +71,7 @@ define void @intrinsic(i8* %dest, i8* %src, i32 %len) { ; CHECK: Function Attrs: argmemonly nofree nosync nounwind willreturn ; CHECK-LABEL: define {{[^@]+}}@intrinsic ; CHECK-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) #[[ATTR4:[0-9]+]] { -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) #[[ATTR8:[0-9]+]] +; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) #[[ATTR9:[0-9]+]] ; CHECK-NEXT: ret void ; call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false) @@ -250,6 +250,47 @@ Dead: ret i32 1 } +define i1 @test_rec_neg(i1 %c) norecurse { +; CHECK: Function Attrs: norecurse +; CHECK-LABEL: define {{[^@]+}}@test_rec_neg +; CHECK-SAME: (i1 [[C:%.*]]) #[[ATTR8:[0-9]+]] { +; CHECK-NEXT: [[RC1:%.*]] = call noundef i1 @rec(i1 noundef true) +; CHECK-NEXT: br i1 [[RC1]], label [[T:%.*]], label [[F:%.*]] +; CHECK: t: +; CHECK-NEXT: [[RC2:%.*]] = call noundef i1 @rec(i1 [[C]]) +; CHECK-NEXT: ret i1 [[RC2]] +; CHECK: f: +; CHECK-NEXT: ret i1 [[RC1]] +; + %rc1 = call i1 @rec(i1 true) + br i1 %rc1, label %t, label %f +t: + %rc2 = call i1 @rec(i1 %c) + ret i1 %rc2 +f: + ret i1 %rc1 +} + +define internal i1 @rec(i1 %c1) { +; CHECK-LABEL: define {{[^@]+}}@rec +; CHECK-SAME: (i1 [[C1:%.*]]) { +; CHECK-NEXT: br i1 [[C1]], label [[T:%.*]], label [[F:%.*]] +; CHECK: t: +; CHECK-NEXT: ret i1 true +; CHECK: f: +; CHECK-NEXT: [[R:%.*]] = call i1 @rec(i1 noundef true) +; CHECK-NEXT: call void @unknown() +; CHECK-NEXT: ret i1 false +; + br i1 %c1, label %t, label %f +t: + ret i1 true +f: + %r = call i1 @rec(i1 true) + call void @unknown() + ret i1 false +} + ;. ; CHECK: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } ; CHECK: attributes #[[ATTR1]] = { nofree nosync nounwind readnone willreturn } @@ -259,5 +300,6 @@ Dead: ; CHECK: attributes #[[ATTR5:[0-9]+]] = { argmemonly nofree nounwind willreturn } ; CHECK: attributes #[[ATTR6]] = { norecurse nosync readnone } ; CHECK: attributes #[[ATTR7]] = { null_pointer_is_valid } -; CHECK: attributes #[[ATTR8]] = { willreturn } +; CHECK: attributes #[[ATTR8]] = { norecurse } +; CHECK: attributes #[[ATTR9]] = { willreturn } ;. diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines.ll b/llvm/test/Transforms/OpenMP/custom_state_machines.ll index e17679b2a8966..c0f51d3bbcf64 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines.ll @@ -1620,9 +1620,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: ret void ; ; -; AMDGPU: Function Attrs: convergent noinline norecurse nounwind +; AMDGPU: Function Attrs: convergent noinline nounwind ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized -; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { ; AMDGPU-NEXT: entry: ; AMDGPU-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -1632,7 +1632,7 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: br label [[RETURN:%.*]] ; AMDGPU: if.end: ; AMDGPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[A]], 1 -; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR11:[0-9]+]] +; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR8]] ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR8]] ; AMDGPU-NEXT: br label [[RETURN]] ; AMDGPU: return: @@ -1772,9 +1772,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: ret void ; ; -; AMDGPU: Function Attrs: convergent noinline norecurse nounwind +; AMDGPU: Function Attrs: convergent noinline nounwind ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized -; AMDGPU-SAME: () #[[ATTR0]] { +; AMDGPU-SAME: () #[[ATTR1]] { ; AMDGPU-NEXT: entry: ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef @[[GLOB2]]) #[[ATTR3]] @@ -2590,9 +2590,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: ret void ; ; -; NVPTX: Function Attrs: convergent noinline norecurse nounwind +; NVPTX: Function Attrs: convergent noinline nounwind ; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized -; NVPTX-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +; NVPTX-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { ; NVPTX-NEXT: entry: ; NVPTX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -2602,7 +2602,7 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: br label [[RETURN:%.*]] ; NVPTX: if.end: ; NVPTX-NEXT: [[SUB:%.*]] = sub nsw i32 [[A]], 1 -; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR11:[0-9]+]] +; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR8]] ; NVPTX-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR8]] ; NVPTX-NEXT: br label [[RETURN]] ; NVPTX: return: @@ -2741,9 +2741,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: ret void ; ; -; NVPTX: Function Attrs: convergent noinline norecurse nounwind +; NVPTX: Function Attrs: convergent noinline nounwind ; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized -; NVPTX-SAME: () #[[ATTR0]] { +; NVPTX-SAME: () #[[ATTR1]] { ; NVPTX-NEXT: entry: ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef @[[GLOB2]]) #[[ATTR3]] @@ -3315,9 +3315,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-DISABLED-NEXT: ret void ; ; -; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind +; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized -; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { ; AMDGPU-DISABLED-NEXT: entry: ; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -3327,7 +3327,7 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]] ; AMDGPU-DISABLED: if.end: ; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[A]], 1 -; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR11:[0-9]+]] +; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR8]] ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR8]] ; AMDGPU-DISABLED-NEXT: br label [[RETURN]] ; AMDGPU-DISABLED: return: @@ -3436,9 +3436,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-DISABLED-NEXT: ret void ; ; -; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind +; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized -; AMDGPU-DISABLED-SAME: () #[[ATTR0]] { +; AMDGPU-DISABLED-SAME: () #[[ATTR1]] { ; AMDGPU-DISABLED-NEXT: entry: ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef @[[GLOB2]]) #[[ATTR3]] @@ -4010,9 +4010,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-DISABLED-NEXT: ret void ; ; -; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind +; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized -; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { +; NVPTX-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { ; NVPTX-DISABLED-NEXT: entry: ; NVPTX-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 @@ -4022,7 +4022,7 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-DISABLED-NEXT: br label [[RETURN:%.*]] ; NVPTX-DISABLED: if.end: ; NVPTX-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[A]], 1 -; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR11:[0-9]+]] +; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR8]] ; NVPTX-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR8]] ; NVPTX-DISABLED-NEXT: br label [[RETURN]] ; NVPTX-DISABLED: return: @@ -4131,9 +4131,9 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-DISABLED-NEXT: ret void ; ; -; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind +; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind ; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized -; NVPTX-DISABLED-SAME: () #[[ATTR0]] { +; NVPTX-DISABLED-SAME: () #[[ATTR1]] { ; NVPTX-DISABLED-NEXT: entry: ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef @[[GLOB2]]) #[[ATTR3]] From 0372676278dd27b7971720b1b2839bc8e8e8cbe6 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Tue, 22 Feb 2022 13:48:21 +0000 Subject: [PATCH 198/316] [AArch64][SME] Remove term 'streaming-sve' from assembler diagnostics. 'streaming-sve' is not a feature that users should be able to set, hence why it shouldn't show up in user-diagnostics. The only flag that end-users should be able to set is '+sme'. Reviewed By: paulwalker-arm Differential Revision: https://reviews.llvm.org/D120256 (cherry picked from commit ffa4dfc8de526ba28d12d62a14f984a7e1e9224b) --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 +- llvm/test/MC/AArch64/SME/revd.s | 2 +- llvm/test/MC/AArch64/SME/sclamp.s | 8 +- .../test/MC/AArch64/SME/streaming-mode-neon.s | 24 +- llvm/test/MC/AArch64/SME/uclamp.s | 8 +- llvm/test/MC/AArch64/SVE/abs.s | 24 +- llvm/test/MC/AArch64/SVE/add.s | 104 ++-- llvm/test/MC/AArch64/SVE/addpl.s | 8 +- llvm/test/MC/AArch64/SVE/addvl.s | 8 +- llvm/test/MC/AArch64/SVE/and.s | 52 +- llvm/test/MC/AArch64/SVE/ands.s | 6 +- llvm/test/MC/AArch64/SVE/andv.s | 8 +- llvm/test/MC/AArch64/SVE/asr.s | 68 +-- llvm/test/MC/AArch64/SVE/asrd.s | 24 +- llvm/test/MC/AArch64/SVE/asrr.s | 16 +- llvm/test/MC/AArch64/SVE/bfcvt.s | 10 +- llvm/test/MC/AArch64/SVE/bfcvtnt.s | 10 +- llvm/test/MC/AArch64/SVE/bfdot.s | 18 +- llvm/test/MC/AArch64/SVE/bfmlal.s | 60 +- llvm/test/MC/AArch64/SVE/bfmmla.s | 2 +- llvm/test/MC/AArch64/SVE/bic.s | 50 +- llvm/test/MC/AArch64/SVE/bics.s | 4 +- llvm/test/MC/AArch64/SVE/brka.s | 4 +- llvm/test/MC/AArch64/SVE/brkas.s | 2 +- llvm/test/MC/AArch64/SVE/brkb.s | 4 +- llvm/test/MC/AArch64/SVE/brkbs.s | 2 +- llvm/test/MC/AArch64/SVE/brkn.s | 4 +- llvm/test/MC/AArch64/SVE/brkns.s | 4 +- llvm/test/MC/AArch64/SVE/brkpa.s | 4 +- llvm/test/MC/AArch64/SVE/brkpas.s | 4 +- llvm/test/MC/AArch64/SVE/brkpb.s | 4 +- llvm/test/MC/AArch64/SVE/brkpbs.s | 4 +- llvm/test/MC/AArch64/SVE/clasta.s | 28 +- llvm/test/MC/AArch64/SVE/clastb.s | 28 +- llvm/test/MC/AArch64/SVE/cls.s | 16 +- llvm/test/MC/AArch64/SVE/clz.s | 16 +- llvm/test/MC/AArch64/SVE/cmpeq.s | 30 +- llvm/test/MC/AArch64/SVE/cmpge.s | 30 +- llvm/test/MC/AArch64/SVE/cmpgt.s | 30 +- llvm/test/MC/AArch64/SVE/cmphi.s | 30 +- llvm/test/MC/AArch64/SVE/cmphs.s | 30 +- llvm/test/MC/AArch64/SVE/cmple.s | 30 +- llvm/test/MC/AArch64/SVE/cmplo.s | 30 +- llvm/test/MC/AArch64/SVE/cmpls.s | 30 +- llvm/test/MC/AArch64/SVE/cmplt.s | 30 +- llvm/test/MC/AArch64/SVE/cmpne.s | 30 +- llvm/test/MC/AArch64/SVE/cnot.s | 16 +- llvm/test/MC/AArch64/SVE/cnt.s | 16 +- llvm/test/MC/AArch64/SVE/cntb.s | 12 +- llvm/test/MC/AArch64/SVE/cntd.s | 12 +- llvm/test/MC/AArch64/SVE/cnth.s | 12 +- llvm/test/MC/AArch64/SVE/cntp.s | 8 +- llvm/test/MC/AArch64/SVE/cntw.s | 12 +- llvm/test/MC/AArch64/SVE/cpy.s | 118 ++-- llvm/test/MC/AArch64/SVE/ctermeq.s | 8 +- llvm/test/MC/AArch64/SVE/ctermne.s | 8 +- llvm/test/MC/AArch64/SVE/decb.s | 40 +- llvm/test/MC/AArch64/SVE/decd.s | 40 +- llvm/test/MC/AArch64/SVE/dech.s | 40 +- llvm/test/MC/AArch64/SVE/decp.s | 32 +- llvm/test/MC/AArch64/SVE/decw.s | 40 +- .../SVE/directive-arch_extension-negative.s | 2 +- llvm/test/MC/AArch64/SVE/dup.s | 84 +-- llvm/test/MC/AArch64/SVE/dupm.s | 20 +- llvm/test/MC/AArch64/SVE/eon.s | 20 +- llvm/test/MC/AArch64/SVE/eor.s | 52 +- llvm/test/MC/AArch64/SVE/eors.s | 6 +- llvm/test/MC/AArch64/SVE/eorv.s | 8 +- llvm/test/MC/AArch64/SVE/ext.s | 8 +- llvm/test/MC/AArch64/SVE/fabd.s | 14 +- llvm/test/MC/AArch64/SVE/fabs.s | 14 +- llvm/test/MC/AArch64/SVE/facge.s | 6 +- llvm/test/MC/AArch64/SVE/facgt.s | 6 +- llvm/test/MC/AArch64/SVE/facle.s | 6 +- llvm/test/MC/AArch64/SVE/faclt.s | 6 +- llvm/test/MC/AArch64/SVE/fadd.s | 44 +- llvm/test/MC/AArch64/SVE/faddv.s | 6 +- llvm/test/MC/AArch64/SVE/fcadd.s | 20 +- llvm/test/MC/AArch64/SVE/fcmeq.s | 12 +- llvm/test/MC/AArch64/SVE/fcmge.s | 12 +- llvm/test/MC/AArch64/SVE/fcmgt.s | 12 +- llvm/test/MC/AArch64/SVE/fcmla.s | 44 +- llvm/test/MC/AArch64/SVE/fcmle.s | 12 +- llvm/test/MC/AArch64/SVE/fcmlt.s | 12 +- llvm/test/MC/AArch64/SVE/fcmne.s | 12 +- llvm/test/MC/AArch64/SVE/fcmuo.s | 6 +- llvm/test/MC/AArch64/SVE/fcpy.s | 524 ++++++++--------- llvm/test/MC/AArch64/SVE/fcvt.s | 20 +- llvm/test/MC/AArch64/SVE/fcvtzs.s | 22 +- llvm/test/MC/AArch64/SVE/fcvtzu.s | 22 +- llvm/test/MC/AArch64/SVE/fdiv.s | 14 +- llvm/test/MC/AArch64/SVE/fdivr.s | 14 +- llvm/test/MC/AArch64/SVE/fdup.s | 516 ++++++++--------- llvm/test/MC/AArch64/SVE/fmad.s | 14 +- llvm/test/MC/AArch64/SVE/fmax.s | 36 +- llvm/test/MC/AArch64/SVE/fmaxnm.s | 38 +- llvm/test/MC/AArch64/SVE/fmaxnmv.s | 6 +- llvm/test/MC/AArch64/SVE/fmaxv.s | 6 +- llvm/test/MC/AArch64/SVE/fmin.s | 38 +- llvm/test/MC/AArch64/SVE/fminnm.s | 38 +- llvm/test/MC/AArch64/SVE/fminnmv.s | 6 +- llvm/test/MC/AArch64/SVE/fminv.s | 6 +- llvm/test/MC/AArch64/SVE/fmla.s | 24 +- llvm/test/MC/AArch64/SVE/fmls.s | 24 +- llvm/test/MC/AArch64/SVE/fmov.s | 538 +++++++++--------- llvm/test/MC/AArch64/SVE/fmsb.s | 14 +- llvm/test/MC/AArch64/SVE/fmul.s | 54 +- llvm/test/MC/AArch64/SVE/fmulx.s | 14 +- llvm/test/MC/AArch64/SVE/fneg.s | 14 +- llvm/test/MC/AArch64/SVE/fnmad.s | 14 +- llvm/test/MC/AArch64/SVE/fnmla.s | 14 +- llvm/test/MC/AArch64/SVE/fnmls.s | 14 +- llvm/test/MC/AArch64/SVE/fnmsb.s | 14 +- llvm/test/MC/AArch64/SVE/frecpe.s | 6 +- llvm/test/MC/AArch64/SVE/frecps.s | 6 +- llvm/test/MC/AArch64/SVE/frecpx.s | 14 +- llvm/test/MC/AArch64/SVE/frinta.s | 14 +- llvm/test/MC/AArch64/SVE/frinti.s | 14 +- llvm/test/MC/AArch64/SVE/frintm.s | 14 +- llvm/test/MC/AArch64/SVE/frintn.s | 14 +- llvm/test/MC/AArch64/SVE/frintp.s | 14 +- llvm/test/MC/AArch64/SVE/frintx.s | 14 +- llvm/test/MC/AArch64/SVE/frintz.s | 14 +- llvm/test/MC/AArch64/SVE/frsqrte.s | 6 +- llvm/test/MC/AArch64/SVE/frsqrts.s | 6 +- llvm/test/MC/AArch64/SVE/fscale.s | 14 +- llvm/test/MC/AArch64/SVE/fsqrt.s | 14 +- llvm/test/MC/AArch64/SVE/fsub.s | 44 +- llvm/test/MC/AArch64/SVE/fsubr.s | 38 +- llvm/test/MC/AArch64/SVE/ftmad.s | 2 +- llvm/test/MC/AArch64/SVE/incb.s | 66 +-- llvm/test/MC/AArch64/SVE/incd.s | 60 +- llvm/test/MC/AArch64/SVE/inch.s | 60 +- llvm/test/MC/AArch64/SVE/incp.s | 32 +- llvm/test/MC/AArch64/SVE/incw.s | 60 +- llvm/test/MC/AArch64/SVE/index.s | 64 +-- llvm/test/MC/AArch64/SVE/insr.s | 32 +- llvm/test/MC/AArch64/SVE/lasta.s | 16 +- llvm/test/MC/AArch64/SVE/lastb.s | 16 +- llvm/test/MC/AArch64/SVE/ld1b.s | 44 +- llvm/test/MC/AArch64/SVE/ld1d.s | 12 +- llvm/test/MC/AArch64/SVE/ld1h.s | 32 +- llvm/test/MC/AArch64/SVE/ld1rb.s | 16 +- llvm/test/MC/AArch64/SVE/ld1rd.s | 4 +- llvm/test/MC/AArch64/SVE/ld1rh.s | 12 +- llvm/test/MC/AArch64/SVE/ld1rqb.s | 10 +- llvm/test/MC/AArch64/SVE/ld1rqd.s | 10 +- llvm/test/MC/AArch64/SVE/ld1rqh.s | 10 +- llvm/test/MC/AArch64/SVE/ld1rqw.s | 10 +- llvm/test/MC/AArch64/SVE/ld1rsb.s | 12 +- llvm/test/MC/AArch64/SVE/ld1rsh.s | 8 +- llvm/test/MC/AArch64/SVE/ld1rsw.s | 4 +- llvm/test/MC/AArch64/SVE/ld1rw.s | 8 +- llvm/test/MC/AArch64/SVE/ld1sb.s | 34 +- llvm/test/MC/AArch64/SVE/ld1sh.s | 22 +- llvm/test/MC/AArch64/SVE/ld1sw.s | 12 +- llvm/test/MC/AArch64/SVE/ld1w.s | 22 +- llvm/test/MC/AArch64/SVE/ld2b.s | 10 +- llvm/test/MC/AArch64/SVE/ld2d.s | 10 +- llvm/test/MC/AArch64/SVE/ld2h.s | 10 +- llvm/test/MC/AArch64/SVE/ld2w.s | 10 +- llvm/test/MC/AArch64/SVE/ld3b.s | 10 +- llvm/test/MC/AArch64/SVE/ld3d.s | 10 +- llvm/test/MC/AArch64/SVE/ld3h.s | 10 +- llvm/test/MC/AArch64/SVE/ld3w.s | 10 +- llvm/test/MC/AArch64/SVE/ld4b.s | 10 +- llvm/test/MC/AArch64/SVE/ld4d.s | 10 +- llvm/test/MC/AArch64/SVE/ld4h.s | 10 +- llvm/test/MC/AArch64/SVE/ld4w.s | 10 +- llvm/test/MC/AArch64/SVE/ldnt1b.s | 10 +- llvm/test/MC/AArch64/SVE/ldnt1d.s | 10 +- llvm/test/MC/AArch64/SVE/ldnt1h.s | 10 +- llvm/test/MC/AArch64/SVE/ldnt1w.s | 10 +- llvm/test/MC/AArch64/SVE/ldr.s | 12 +- llvm/test/MC/AArch64/SVE/lsl.s | 68 +-- llvm/test/MC/AArch64/SVE/lslr.s | 16 +- llvm/test/MC/AArch64/SVE/lsr.s | 68 +-- llvm/test/MC/AArch64/SVE/lsrr.s | 16 +- llvm/test/MC/AArch64/SVE/mad.s | 16 +- .../MC/AArch64/SVE/matrix-multiply-fp64.s | 12 +- .../MC/AArch64/SVE/matrix-multiply-int8.s | 12 +- llvm/test/MC/AArch64/SVE/mla.s | 16 +- llvm/test/MC/AArch64/SVE/mls.s | 16 +- llvm/test/MC/AArch64/SVE/mov.s | 258 ++++----- llvm/test/MC/AArch64/SVE/movprfx.s | 14 +- llvm/test/MC/AArch64/SVE/movs.s | 8 +- llvm/test/MC/AArch64/SVE/msb.s | 16 +- llvm/test/MC/AArch64/SVE/mul.s | 36 +- llvm/test/MC/AArch64/SVE/nand.s | 4 +- llvm/test/MC/AArch64/SVE/nands.s | 4 +- llvm/test/MC/AArch64/SVE/neg.s | 24 +- llvm/test/MC/AArch64/SVE/nor.s | 4 +- llvm/test/MC/AArch64/SVE/nors.s | 4 +- llvm/test/MC/AArch64/SVE/not.s | 20 +- llvm/test/MC/AArch64/SVE/nots.s | 4 +- llvm/test/MC/AArch64/SVE/orn.s | 24 +- llvm/test/MC/AArch64/SVE/orns.s | 4 +- llvm/test/MC/AArch64/SVE/orr.s | 58 +- llvm/test/MC/AArch64/SVE/orrs.s | 6 +- llvm/test/MC/AArch64/SVE/orv.s | 8 +- llvm/test/MC/AArch64/SVE/pfalse.s | 2 +- llvm/test/MC/AArch64/SVE/pfirst.s | 4 +- llvm/test/MC/AArch64/SVE/pnext.s | 10 +- llvm/test/MC/AArch64/SVE/prfb.s | 60 +- llvm/test/MC/AArch64/SVE/prfd.s | 60 +- llvm/test/MC/AArch64/SVE/prfh.s | 60 +- llvm/test/MC/AArch64/SVE/prfw.s | 60 +- llvm/test/MC/AArch64/SVE/ptest.s | 4 +- llvm/test/MC/AArch64/SVE/ptrue.s | 80 +-- llvm/test/MC/AArch64/SVE/ptrues.s | 80 +-- llvm/test/MC/AArch64/SVE/punpkhi.s | 4 +- llvm/test/MC/AArch64/SVE/punpklo.s | 4 +- llvm/test/MC/AArch64/SVE/rbit.s | 16 +- llvm/test/MC/AArch64/SVE/rdvl.s | 8 +- llvm/test/MC/AArch64/SVE/rev.s | 8 +- llvm/test/MC/AArch64/SVE/revb.s | 14 +- llvm/test/MC/AArch64/SVE/revh.s | 12 +- llvm/test/MC/AArch64/SVE/revw.s | 10 +- llvm/test/MC/AArch64/SVE/sabd.s | 16 +- llvm/test/MC/AArch64/SVE/saddv.s | 6 +- llvm/test/MC/AArch64/SVE/scvtf.s | 22 +- llvm/test/MC/AArch64/SVE/sdiv.s | 12 +- llvm/test/MC/AArch64/SVE/sdivr.s | 12 +- llvm/test/MC/AArch64/SVE/sdot.s | 16 +- llvm/test/MC/AArch64/SVE/sel.s | 20 +- llvm/test/MC/AArch64/SVE/smax.s | 36 +- llvm/test/MC/AArch64/SVE/smaxv.s | 8 +- llvm/test/MC/AArch64/SVE/smin.s | 36 +- llvm/test/MC/AArch64/SVE/sminv.s | 8 +- llvm/test/MC/AArch64/SVE/smulh.s | 16 +- llvm/test/MC/AArch64/SVE/splice.s | 12 +- llvm/test/MC/AArch64/SVE/sqadd.s | 40 +- llvm/test/MC/AArch64/SVE/sqdecb.s | 78 +-- llvm/test/MC/AArch64/SVE/sqdecd.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqdech.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqdecp.s | 32 +- llvm/test/MC/AArch64/SVE/sqdecw.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqincb.s | 78 +-- llvm/test/MC/AArch64/SVE/sqincd.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqinch.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqincp.s | 32 +- llvm/test/MC/AArch64/SVE/sqincw.s | 102 ++-- llvm/test/MC/AArch64/SVE/sqsub.s | 40 +- llvm/test/MC/AArch64/SVE/st1b.s | 40 +- llvm/test/MC/AArch64/SVE/st1d.s | 10 +- llvm/test/MC/AArch64/SVE/st1h.s | 30 +- llvm/test/MC/AArch64/SVE/st1w.s | 20 +- llvm/test/MC/AArch64/SVE/st2b.s | 10 +- llvm/test/MC/AArch64/SVE/st2d.s | 10 +- llvm/test/MC/AArch64/SVE/st2h.s | 10 +- llvm/test/MC/AArch64/SVE/st2w.s | 10 +- llvm/test/MC/AArch64/SVE/st3b.s | 10 +- llvm/test/MC/AArch64/SVE/st3d.s | 10 +- llvm/test/MC/AArch64/SVE/st3h.s | 10 +- llvm/test/MC/AArch64/SVE/st3w.s | 10 +- llvm/test/MC/AArch64/SVE/st4b.s | 10 +- llvm/test/MC/AArch64/SVE/st4d.s | 10 +- llvm/test/MC/AArch64/SVE/st4h.s | 10 +- llvm/test/MC/AArch64/SVE/st4w.s | 10 +- llvm/test/MC/AArch64/SVE/stnt1b.s | 10 +- llvm/test/MC/AArch64/SVE/stnt1d.s | 10 +- llvm/test/MC/AArch64/SVE/stnt1h.s | 10 +- llvm/test/MC/AArch64/SVE/stnt1w.s | 10 +- llvm/test/MC/AArch64/SVE/str.s | 12 +- llvm/test/MC/AArch64/SVE/sub.s | 104 ++-- llvm/test/MC/AArch64/SVE/subr.s | 48 +- llvm/test/MC/AArch64/SVE/sunpkhi.s | 6 +- llvm/test/MC/AArch64/SVE/sunpklo.s | 6 +- llvm/test/MC/AArch64/SVE/sxtb.s | 20 +- llvm/test/MC/AArch64/SVE/sxth.s | 16 +- llvm/test/MC/AArch64/SVE/sxtw.s | 12 +- llvm/test/MC/AArch64/SVE/tbl.s | 16 +- llvm/test/MC/AArch64/SVE/trn1.s | 16 +- llvm/test/MC/AArch64/SVE/trn2.s | 16 +- llvm/test/MC/AArch64/SVE/uabd.s | 16 +- llvm/test/MC/AArch64/SVE/uaddv.s | 8 +- llvm/test/MC/AArch64/SVE/ucvtf.s | 22 +- llvm/test/MC/AArch64/SVE/udiv.s | 12 +- llvm/test/MC/AArch64/SVE/udivr.s | 12 +- llvm/test/MC/AArch64/SVE/udot.s | 16 +- llvm/test/MC/AArch64/SVE/umax.s | 36 +- llvm/test/MC/AArch64/SVE/umaxv.s | 8 +- llvm/test/MC/AArch64/SVE/umin.s | 36 +- llvm/test/MC/AArch64/SVE/uminv.s | 8 +- llvm/test/MC/AArch64/SVE/umulh.s | 16 +- llvm/test/MC/AArch64/SVE/uqadd.s | 40 +- llvm/test/MC/AArch64/SVE/uqdecb.s | 78 +-- llvm/test/MC/AArch64/SVE/uqdecd.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqdech.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqdecp.s | 32 +- llvm/test/MC/AArch64/SVE/uqdecw.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqincb.s | 78 +-- llvm/test/MC/AArch64/SVE/uqincd.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqinch.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqincp.s | 32 +- llvm/test/MC/AArch64/SVE/uqincw.s | 102 ++-- llvm/test/MC/AArch64/SVE/uqsub.s | 40 +- llvm/test/MC/AArch64/SVE/uunpkhi.s | 6 +- llvm/test/MC/AArch64/SVE/uunpklo.s | 6 +- llvm/test/MC/AArch64/SVE/uxtb.s | 20 +- llvm/test/MC/AArch64/SVE/uxth.s | 16 +- llvm/test/MC/AArch64/SVE/uxtw.s | 12 +- llvm/test/MC/AArch64/SVE/uzp1.s | 16 +- llvm/test/MC/AArch64/SVE/uzp2.s | 16 +- llvm/test/MC/AArch64/SVE/whilele.s | 20 +- llvm/test/MC/AArch64/SVE/whilelo.s | 20 +- llvm/test/MC/AArch64/SVE/whilels.s | 20 +- llvm/test/MC/AArch64/SVE/whilelt.s | 20 +- llvm/test/MC/AArch64/SVE/zip1.s | 32 +- llvm/test/MC/AArch64/SVE/zip2.s | 32 +- llvm/test/MC/AArch64/SVE2/adclb.s | 8 +- llvm/test/MC/AArch64/SVE2/adclt.s | 8 +- llvm/test/MC/AArch64/SVE2/addhnb.s | 6 +- llvm/test/MC/AArch64/SVE2/addhnt.s | 6 +- llvm/test/MC/AArch64/SVE2/addp.s | 16 +- llvm/test/MC/AArch64/SVE2/bcax.s | 12 +- llvm/test/MC/AArch64/SVE2/bsl.s | 6 +- llvm/test/MC/AArch64/SVE2/bsl1n.s | 6 +- llvm/test/MC/AArch64/SVE2/bsl2n.s | 6 +- llvm/test/MC/AArch64/SVE2/cadd.s | 20 +- llvm/test/MC/AArch64/SVE2/cdot.s | 28 +- llvm/test/MC/AArch64/SVE2/cmla.s | 48 +- .../MC/AArch64/SVE2/directive-arch-negative.s | 2 +- .../SVE2/directive-arch_extension-negative.s | 2 +- .../MC/AArch64/SVE2/directive-cpu-negative.s | 2 +- llvm/test/MC/AArch64/SVE2/eor3.s | 12 +- llvm/test/MC/AArch64/SVE2/eorbt.s | 12 +- llvm/test/MC/AArch64/SVE2/eortb.s | 12 +- llvm/test/MC/AArch64/SVE2/ext.s | 4 +- llvm/test/MC/AArch64/SVE2/faddp.s | 14 +- llvm/test/MC/AArch64/SVE2/fcvtlt.s | 4 +- llvm/test/MC/AArch64/SVE2/fcvtnt.s | 4 +- llvm/test/MC/AArch64/SVE2/fcvtx.s | 12 +- llvm/test/MC/AArch64/SVE2/fcvtxnt.s | 4 +- llvm/test/MC/AArch64/SVE2/flogb.s | 14 +- llvm/test/MC/AArch64/SVE2/fmaxnmp.s | 14 +- llvm/test/MC/AArch64/SVE2/fmaxp.s | 14 +- llvm/test/MC/AArch64/SVE2/fminnmp.s | 14 +- llvm/test/MC/AArch64/SVE2/fminp.s | 14 +- llvm/test/MC/AArch64/SVE2/fmlalb.s | 14 +- llvm/test/MC/AArch64/SVE2/fmlalt.s | 14 +- llvm/test/MC/AArch64/SVE2/fmlslb.s | 14 +- llvm/test/MC/AArch64/SVE2/fmlslt.s | 14 +- llvm/test/MC/AArch64/SVE2/mla.s | 10 +- llvm/test/MC/AArch64/SVE2/mls.s | 10 +- llvm/test/MC/AArch64/SVE2/mul.s | 14 +- llvm/test/MC/AArch64/SVE2/nbsl.s | 6 +- llvm/test/MC/AArch64/SVE2/pmul.s | 4 +- llvm/test/MC/AArch64/SVE2/pmullb.s | 4 +- llvm/test/MC/AArch64/SVE2/pmullt.s | 4 +- llvm/test/MC/AArch64/SVE2/raddhnb.s | 6 +- llvm/test/MC/AArch64/SVE2/raddhnt.s | 6 +- llvm/test/MC/AArch64/SVE2/rshrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/rshrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/rsubhnb.s | 6 +- llvm/test/MC/AArch64/SVE2/rsubhnt.s | 6 +- llvm/test/MC/AArch64/SVE2/saba.s | 12 +- llvm/test/MC/AArch64/SVE2/sabalb.s | 10 +- llvm/test/MC/AArch64/SVE2/sabalt.s | 10 +- llvm/test/MC/AArch64/SVE2/sabdlb.s | 6 +- llvm/test/MC/AArch64/SVE2/sabdlt.s | 6 +- llvm/test/MC/AArch64/SVE2/sadalp.s | 14 +- llvm/test/MC/AArch64/SVE2/saddlb.s | 6 +- llvm/test/MC/AArch64/SVE2/saddlbt.s | 6 +- llvm/test/MC/AArch64/SVE2/saddlt.s | 6 +- llvm/test/MC/AArch64/SVE2/saddwb.s | 6 +- llvm/test/MC/AArch64/SVE2/saddwt.s | 6 +- llvm/test/MC/AArch64/SVE2/sbclb.s | 8 +- llvm/test/MC/AArch64/SVE2/sbclt.s | 8 +- llvm/test/MC/AArch64/SVE2/shadd.s | 16 +- llvm/test/MC/AArch64/SVE2/shrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/shrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/shsub.s | 16 +- llvm/test/MC/AArch64/SVE2/shsubr.s | 16 +- llvm/test/MC/AArch64/SVE2/sli.s | 16 +- llvm/test/MC/AArch64/SVE2/smaxp.s | 16 +- llvm/test/MC/AArch64/SVE2/sminp.s | 16 +- llvm/test/MC/AArch64/SVE2/smlalb.s | 18 +- llvm/test/MC/AArch64/SVE2/smlalt.s | 18 +- llvm/test/MC/AArch64/SVE2/smlslb.s | 18 +- llvm/test/MC/AArch64/SVE2/smlslt.s | 18 +- llvm/test/MC/AArch64/SVE2/smulh.s | 8 +- llvm/test/MC/AArch64/SVE2/smullb.s | 10 +- llvm/test/MC/AArch64/SVE2/smullt.s | 10 +- llvm/test/MC/AArch64/SVE2/splice.s | 8 +- llvm/test/MC/AArch64/SVE2/sqabs.s | 16 +- llvm/test/MC/AArch64/SVE2/sqadd.s | 16 +- llvm/test/MC/AArch64/SVE2/sqcadd.s | 20 +- llvm/test/MC/AArch64/SVE2/sqdmlalb.s | 18 +- llvm/test/MC/AArch64/SVE2/sqdmlalbt.s | 10 +- llvm/test/MC/AArch64/SVE2/sqdmlalt.s | 18 +- llvm/test/MC/AArch64/SVE2/sqdmlslb.s | 18 +- llvm/test/MC/AArch64/SVE2/sqdmlslbt.s | 10 +- llvm/test/MC/AArch64/SVE2/sqdmlslt.s | 18 +- llvm/test/MC/AArch64/SVE2/sqdmulh.s | 14 +- llvm/test/MC/AArch64/SVE2/sqdmullb.s | 10 +- llvm/test/MC/AArch64/SVE2/sqdmullt.s | 10 +- llvm/test/MC/AArch64/SVE2/sqneg.s | 16 +- llvm/test/MC/AArch64/SVE2/sqrdcmlah.s | 48 +- llvm/test/MC/AArch64/SVE2/sqrdmlah.s | 22 +- llvm/test/MC/AArch64/SVE2/sqrdmlsh.s | 22 +- llvm/test/MC/AArch64/SVE2/sqrdmulh.s | 14 +- llvm/test/MC/AArch64/SVE2/sqrshl.s | 16 +- llvm/test/MC/AArch64/SVE2/sqrshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/sqrshrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/sqrshrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/sqrshrunb.s | 12 +- llvm/test/MC/AArch64/SVE2/sqrshrunt.s | 12 +- llvm/test/MC/AArch64/SVE2/sqshl.s | 40 +- llvm/test/MC/AArch64/SVE2/sqshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/sqshlu.s | 24 +- llvm/test/MC/AArch64/SVE2/sqshrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/sqshrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/sqshrunb.s | 12 +- llvm/test/MC/AArch64/SVE2/sqshrunt.s | 12 +- llvm/test/MC/AArch64/SVE2/sqsub.s | 16 +- llvm/test/MC/AArch64/SVE2/sqsubr.s | 16 +- llvm/test/MC/AArch64/SVE2/sqxtnb.s | 6 +- llvm/test/MC/AArch64/SVE2/sqxtnt.s | 6 +- llvm/test/MC/AArch64/SVE2/sqxtunb.s | 6 +- llvm/test/MC/AArch64/SVE2/sqxtunt.s | 6 +- llvm/test/MC/AArch64/SVE2/srhadd.s | 16 +- llvm/test/MC/AArch64/SVE2/sri.s | 16 +- llvm/test/MC/AArch64/SVE2/srshl.s | 16 +- llvm/test/MC/AArch64/SVE2/srshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/srshr.s | 24 +- llvm/test/MC/AArch64/SVE2/srsra.s | 20 +- llvm/test/MC/AArch64/SVE2/sshllb.s | 12 +- llvm/test/MC/AArch64/SVE2/sshllt.s | 12 +- llvm/test/MC/AArch64/SVE2/ssra.s | 20 +- llvm/test/MC/AArch64/SVE2/ssublb.s | 6 +- llvm/test/MC/AArch64/SVE2/ssublbt.s | 6 +- llvm/test/MC/AArch64/SVE2/ssublt.s | 6 +- llvm/test/MC/AArch64/SVE2/ssubltb.s | 6 +- llvm/test/MC/AArch64/SVE2/ssubwb.s | 6 +- llvm/test/MC/AArch64/SVE2/ssubwt.s | 6 +- llvm/test/MC/AArch64/SVE2/subhnb.s | 6 +- llvm/test/MC/AArch64/SVE2/subhnt.s | 6 +- llvm/test/MC/AArch64/SVE2/suqadd.s | 16 +- llvm/test/MC/AArch64/SVE2/tbl.s | 8 +- llvm/test/MC/AArch64/SVE2/tbx.s | 8 +- llvm/test/MC/AArch64/SVE2/uaba.s | 12 +- llvm/test/MC/AArch64/SVE2/uabalb.s | 10 +- llvm/test/MC/AArch64/SVE2/uabalt.s | 10 +- llvm/test/MC/AArch64/SVE2/uabdlb.s | 6 +- llvm/test/MC/AArch64/SVE2/uabdlt.s | 6 +- llvm/test/MC/AArch64/SVE2/uadalp.s | 14 +- llvm/test/MC/AArch64/SVE2/uaddlb.s | 6 +- llvm/test/MC/AArch64/SVE2/uaddlt.s | 6 +- llvm/test/MC/AArch64/SVE2/uaddwb.s | 6 +- llvm/test/MC/AArch64/SVE2/uaddwt.s | 6 +- llvm/test/MC/AArch64/SVE2/uhadd.s | 16 +- llvm/test/MC/AArch64/SVE2/uhsub.s | 16 +- llvm/test/MC/AArch64/SVE2/uhsubr.s | 16 +- llvm/test/MC/AArch64/SVE2/umaxp.s | 16 +- llvm/test/MC/AArch64/SVE2/uminp.s | 16 +- llvm/test/MC/AArch64/SVE2/umlalb.s | 18 +- llvm/test/MC/AArch64/SVE2/umlalt.s | 18 +- llvm/test/MC/AArch64/SVE2/umlslb.s | 18 +- llvm/test/MC/AArch64/SVE2/umlslt.s | 18 +- llvm/test/MC/AArch64/SVE2/umulh.s | 8 +- llvm/test/MC/AArch64/SVE2/umullb.s | 10 +- llvm/test/MC/AArch64/SVE2/umullt.s | 10 +- llvm/test/MC/AArch64/SVE2/uqadd.s | 16 +- llvm/test/MC/AArch64/SVE2/uqrshl.s | 16 +- llvm/test/MC/AArch64/SVE2/uqrshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/uqrshrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/uqrshrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/uqshl.s | 40 +- llvm/test/MC/AArch64/SVE2/uqshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/uqshrnb.s | 12 +- llvm/test/MC/AArch64/SVE2/uqshrnt.s | 12 +- llvm/test/MC/AArch64/SVE2/uqsub.s | 16 +- llvm/test/MC/AArch64/SVE2/uqsubr.s | 16 +- llvm/test/MC/AArch64/SVE2/uqxtnb.s | 6 +- llvm/test/MC/AArch64/SVE2/uqxtnt.s | 6 +- llvm/test/MC/AArch64/SVE2/urecpe.s | 10 +- llvm/test/MC/AArch64/SVE2/urhadd.s | 16 +- llvm/test/MC/AArch64/SVE2/urshl.s | 16 +- llvm/test/MC/AArch64/SVE2/urshlr.s | 16 +- llvm/test/MC/AArch64/SVE2/urshr.s | 24 +- llvm/test/MC/AArch64/SVE2/ursqrte.s | 10 +- llvm/test/MC/AArch64/SVE2/ursra.s | 20 +- llvm/test/MC/AArch64/SVE2/ushllb.s | 12 +- llvm/test/MC/AArch64/SVE2/ushllt.s | 12 +- llvm/test/MC/AArch64/SVE2/usqadd.s | 16 +- llvm/test/MC/AArch64/SVE2/usra.s | 20 +- llvm/test/MC/AArch64/SVE2/usublb.s | 6 +- llvm/test/MC/AArch64/SVE2/usublt.s | 6 +- llvm/test/MC/AArch64/SVE2/usubwb.s | 6 +- llvm/test/MC/AArch64/SVE2/usubwt.s | 6 +- llvm/test/MC/AArch64/SVE2/whilege.s | 20 +- llvm/test/MC/AArch64/SVE2/whilegt.s | 20 +- llvm/test/MC/AArch64/SVE2/whilehi.s | 20 +- llvm/test/MC/AArch64/SVE2/whilehs.s | 20 +- llvm/test/MC/AArch64/SVE2/whilerw.s | 8 +- llvm/test/MC/AArch64/SVE2/whilewr.s | 8 +- llvm/test/MC/AArch64/SVE2/xar.s | 20 +- 498 files changed, 5791 insertions(+), 5791 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 83bf89ff97c50..1316161f05f10 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -143,23 +143,23 @@ def HasSMEF64 : Predicate<"Subtarget->hasSMEF64()">, def HasSMEI64 : Predicate<"Subtarget->hasSMEI64()">, AssemblerPredicate<(all_of FeatureSMEI64), "sme-i64">; def HasStreamingSVE : Predicate<"Subtarget->hasStreamingSVE()">, - AssemblerPredicate<(all_of FeatureStreamingSVE), "streaming-sve">; + AssemblerPredicate<(all_of FeatureStreamingSVE), "sme">; // A subset of SVE(2) instructions are legal in Streaming SVE execution mode, // they should be enabled if either has been specified. def HasSVEorStreamingSVE : Predicate<"Subtarget->hasSVE() || Subtarget->hasStreamingSVE()">, AssemblerPredicate<(any_of FeatureSVE, FeatureStreamingSVE), - "streaming-sve or sve">; + "sve or sme">; def HasSVE2orStreamingSVE : Predicate<"Subtarget->hasSVE2() || Subtarget->hasStreamingSVE()">, AssemblerPredicate<(any_of FeatureSVE2, FeatureStreamingSVE), - "streaming-sve or sve2">; + "sve2 or sme">; // A subset of NEON instructions are legal in Streaming SVE execution mode, // they should be enabled if either has been specified. def HasNEONorStreamingSVE : Predicate<"Subtarget->hasNEON() || Subtarget->hasStreamingSVE()">, AssemblerPredicate<(any_of FeatureNEON, FeatureStreamingSVE), - "streaming-sve or neon">; + "neon or sme">; def HasRCPC : Predicate<"Subtarget->hasRCPC()">, AssemblerPredicate<(all_of FeatureRCPC), "rcpc">; def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, diff --git a/llvm/test/MC/AArch64/SME/revd.s b/llvm/test/MC/AArch64/SME/revd.s index d34b851d04993..ed45fb08120bc 100644 --- a/llvm/test/MC/AArch64/SME/revd.s +++ b/llvm/test/MC/AArch64/SME/revd.s @@ -42,7 +42,7 @@ revd z31.q, p7/m, z31.q movprfx z21, z25 // CHECK-INST: movprfx z21, z25 // CHECK-ENCODING: [0x35,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 35 bf 20 04 revd z21.q, p5/m, z10.q diff --git a/llvm/test/MC/AArch64/SME/sclamp.s b/llvm/test/MC/AArch64/SME/sclamp.s index 3e232711bca8d..0f1e6a2a4bd9b 100644 --- a/llvm/test/MC/AArch64/SME/sclamp.s +++ b/llvm/test/MC/AArch64/SME/sclamp.s @@ -126,7 +126,7 @@ sclamp z31.d, z31.d, z31.d movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 sclamp z23.b, z13.b, z8.b @@ -138,7 +138,7 @@ sclamp z23.b, z13.b, z8.b movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 sclamp z23.h, z13.h, z8.h @@ -150,7 +150,7 @@ sclamp z23.h, z13.h, z8.h movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 sclamp z23.s, z13.s, z8.s @@ -162,7 +162,7 @@ sclamp z23.s, z13.s, z8.s movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 sclamp z23.d, z13.d, z8.d diff --git a/llvm/test/MC/AArch64/SME/streaming-mode-neon.s b/llvm/test/MC/AArch64/SME/streaming-mode-neon.s index 157fcf966e569..88f5cedbb06d4 100644 --- a/llvm/test/MC/AArch64/SME/streaming-mode-neon.s +++ b/llvm/test/MC/AArch64/SME/streaming-mode-neon.s @@ -15,62 +15,62 @@ fmulx s0, s1, s2 // CHECK-INST: fmulx s0, s1, s2 // CHECK-ENCODING: [0x20,0xdc,0x22,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme fmulx d0, d1, d2 // CHECK-INST: fmulx d0, d1, d2 // CHECK-ENCODING: [0x20,0xdc,0x62,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecps s0, s1, s2 // CHECK-INST: frecps s0, s1, s2 // CHECK-ENCODING: [0x20,0xfc,0x22,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecps d0, d1, d2 // CHECK-INST: frecps d0, d1, d2 // CHECK-ENCODING: [0x20,0xfc,0x62,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frsqrts s0, s1, s2 // CHECK-INST: frsqrts s0, s1, s2 // CHECK-ENCODING: [0x20,0xfc,0xa2,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frsqrts d0, d1, d2 // CHECK-INST: frsqrts d0, d1, d2 // CHECK-ENCODING: [0x20,0xfc,0xe2,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecpe s0, s1 // CHECK-INST: frecpe s0, s1 // CHECK-ENCODING: [0x20,0xd8,0xa1,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecpe d0, d1 // CHECK-INST: frecpe d0, d1 // CHECK-ENCODING: [0x20,0xd8,0xe1,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecpx s0, s1 // CHECK-INST: frecpx s0, s1 // CHECK-ENCODING: [0x20,0xf8,0xa1,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frecpx d0, d1 // CHECK-INST: frecpx d0, d1 // CHECK-ENCODING: [0x20,0xf8,0xe1,0x5e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frsqrte s0, s1 // CHECK-INST: frsqrte s0, s1 // CHECK-ENCODING: [0x20,0xd8,0xa1,0x7e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme frsqrte d0, d1 // CHECK-INST: frsqrte d0, d1 // CHECK-ENCODING: [0x20,0xd8,0xe1,0x7e] -// CHECK-ERROR: instruction requires: streaming-sve or neon +// CHECK-ERROR: instruction requires: neon or sme // Vector to GPR integer move instructions diff --git a/llvm/test/MC/AArch64/SME/uclamp.s b/llvm/test/MC/AArch64/SME/uclamp.s index 2db0f8af0158f..94aa31c0f4c54 100644 --- a/llvm/test/MC/AArch64/SME/uclamp.s +++ b/llvm/test/MC/AArch64/SME/uclamp.s @@ -126,7 +126,7 @@ uclamp z31.d, z31.d, z31.d movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 uclamp z23.b, z13.b, z8.b @@ -138,7 +138,7 @@ uclamp z23.b, z13.b, z8.b movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 uclamp z23.h, z13.h, z8.h @@ -150,7 +150,7 @@ uclamp z23.h, z13.h, z8.h movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 uclamp z23.s, z13.s, z8.s @@ -162,7 +162,7 @@ uclamp z23.s, z13.s, z8.s movprfx z23, z27 // CHECK-INST: movprfx z23, z27 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 77 bf 20 04 uclamp z23.d, z13.d, z8.d diff --git a/llvm/test/MC/AArch64/SVE/abs.s b/llvm/test/MC/AArch64/SVE/abs.s index 1a7182da55340..58143bc128f0d 100644 --- a/llvm/test/MC/AArch64/SVE/abs.s +++ b/llvm/test/MC/AArch64/SVE/abs.s @@ -12,49 +12,49 @@ abs z0.b, p0/m, z0.b // CHECK-INST: abs z0.b, p0/m, z0.b // CHECK-ENCODING: [0x00,0xa0,0x16,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 16 04 abs z0.h, p0/m, z0.h // CHECK-INST: abs z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x56,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 56 04 abs z0.s, p0/m, z0.s // CHECK-INST: abs z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x96,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 96 04 abs z0.d, p0/m, z0.d // CHECK-INST: abs z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d6 04 abs z31.b, p7/m, z31.b // CHECK-INST: abs z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x16,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 16 04 abs z31.h, p7/m, z31.h // CHECK-INST: abs z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x56,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 56 04 abs z31.s, p7/m, z31.s // CHECK-INST: abs z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x96,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 96 04 abs z31.d, p7/m, z31.d // CHECK-INST: abs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d6 04 @@ -64,23 +64,23 @@ abs z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 abs z4.d, p7/m, z31.d // CHECK-INST: abs z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d6 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 abs z4.d, p7/m, z31.d // CHECK-INST: abs z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d6 04 diff --git a/llvm/test/MC/AArch64/SVE/add.s b/llvm/test/MC/AArch64/SVE/add.s index 7b641735e3d61..1a57e499c1a78 100644 --- a/llvm/test/MC/AArch64/SVE/add.s +++ b/llvm/test/MC/AArch64/SVE/add.s @@ -12,277 +12,277 @@ add z31.s, z31.s, z31.s // CHECK-INST: add z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x03,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 03 bf 04 add z23.d, z13.d, z8.d // CHECK-INST: add z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x01,0xe8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 01 e8 04 add z23.b, p3/m, z23.b, z13.b // CHECK-INST: add z23.b, p3/m, z23.b, z13.b // CHECK-ENCODING: [0xb7,0x0d,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 00 04 add z0.s, z0.s, z0.s // CHECK-INST: add z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 a0 04 add z31.d, z31.d, z31.d // CHECK-INST: add z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x03,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 03 ff 04 add z21.b, z10.b, z21.b // CHECK-INST: add z21.b, z10.b, z21.b // CHECK-ENCODING: [0x55,0x01,0x35,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 01 35 04 add z31.b, z31.b, z31.b // CHECK-INST: add z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x03,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 03 3f 04 add z0.h, p0/m, z0.h, z0.h // CHECK-INST: add z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 40 04 add z0.h, z0.h, z0.h // CHECK-INST: add z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 60 04 add z0.b, p0/m, z0.b, z0.b // CHECK-INST: add z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 00 04 add z0.s, p0/m, z0.s, z0.s // CHECK-INST: add z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 04 add z23.b, z13.b, z8.b // CHECK-INST: add z23.b, z13.b, z8.b // CHECK-ENCODING: [0xb7,0x01,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 01 28 04 add z0.d, z0.d, z0.d // CHECK-INST: add z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 e0 04 add z0.d, p0/m, z0.d, z0.d // CHECK-INST: add z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c0 04 add z31.h, z31.h, z31.h // CHECK-INST: add z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x03,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 03 7f 04 add z0.b, z0.b, z0.b // CHECK-INST: add z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 20 04 add z21.d, z10.d, z21.d // CHECK-INST: add z21.d, z10.d, z21.d // CHECK-ENCODING: [0x55,0x01,0xf5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 01 f5 04 add z23.h, p3/m, z23.h, z13.h // CHECK-INST: add z23.h, p3/m, z23.h, z13.h // CHECK-ENCODING: [0xb7,0x0d,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 40 04 add z23.s, p3/m, z23.s, z13.s // CHECK-INST: add z23.s, p3/m, z23.s, z13.s // CHECK-ENCODING: [0xb7,0x0d,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 80 04 add z31.s, p7/m, z31.s, z31.s // CHECK-INST: add z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 80 04 add z21.h, z10.h, z21.h // CHECK-INST: add z21.h, z10.h, z21.h // CHECK-ENCODING: [0x55,0x01,0x75,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 01 75 04 add z23.d, p3/m, z23.d, z13.d // CHECK-INST: add z23.d, p3/m, z23.d, z13.d // CHECK-ENCODING: [0xb7,0x0d,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d c0 04 add z21.d, p5/m, z21.d, z10.d // CHECK-INST: add z21.d, p5/m, z21.d, z10.d // CHECK-ENCODING: [0x55,0x15,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 c0 04 add z21.b, p5/m, z21.b, z10.b // CHECK-INST: add z21.b, p5/m, z21.b, z10.b // CHECK-ENCODING: [0x55,0x15,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 00 04 add z21.s, z10.s, z21.s // CHECK-INST: add z21.s, z10.s, z21.s // CHECK-ENCODING: [0x55,0x01,0xb5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 01 b5 04 add z21.h, p5/m, z21.h, z10.h // CHECK-INST: add z21.h, p5/m, z21.h, z10.h // CHECK-ENCODING: [0x55,0x15,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 40 04 add z31.h, p7/m, z31.h, z31.h // CHECK-INST: add z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 40 04 add z23.h, z13.h, z8.h // CHECK-INST: add z23.h, z13.h, z8.h // CHECK-ENCODING: [0xb7,0x01,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 01 68 04 add z31.d, p7/m, z31.d, z31.d // CHECK-INST: add z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f c0 04 add z21.s, p5/m, z21.s, z10.s // CHECK-INST: add z21.s, p5/m, z21.s, z10.s // CHECK-ENCODING: [0x55,0x15,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 80 04 add z31.b, p7/m, z31.b, z31.b // CHECK-INST: add z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 00 04 add z23.s, z13.s, z8.s // CHECK-INST: add z23.s, z13.s, z8.s // CHECK-ENCODING: [0xb7,0x01,0xa8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 01 a8 04 add z0.b, z0.b, #0 // CHECK-INST: add z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 20 25 add z31.b, z31.b, #255 // CHECK-INST: add z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 20 25 add z0.h, z0.h, #0 // CHECK-INST: add z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x60,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 60 25 add z0.h, z0.h, #0, lsl #8 // CHECK-INST: add z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x60,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 25 add z31.h, z31.h, #255, lsl #8 // CHECK-INST: add z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x60,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 60 25 add z31.h, z31.h, #65280 // CHECK-INST: add z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x60,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 60 25 add z0.s, z0.s, #0 // CHECK-INST: add z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a0 25 add z0.s, z0.s, #0, lsl #8 // CHECK-INST: add z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 25 add z31.s, z31.s, #255, lsl #8 // CHECK-INST: add z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a0 25 add z31.s, z31.s, #65280 // CHECK-INST: add z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a0 25 add z0.d, z0.d, #0 // CHECK-INST: add z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e0 25 add z0.d, z0.d, #0, lsl #8 // CHECK-INST: add z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 25 add z31.d, z31.d, #255, lsl #8 // CHECK-INST: add z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e0 25 add z31.d, z31.d, #65280 // CHECK-INST: add z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e0 25 @@ -293,35 +293,35 @@ add z31.d, z31.d, #65280 movprfx z4.b, p7/z, z6.b // CHECK-INST: movprfx z4.b, p7/z, z6.b // CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 10 04 add z4.b, p7/m, z4.b, z31.b // CHECK-INST: add z4.b, p7/m, z4.b, z31.b // CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f 00 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 add z4.b, p7/m, z4.b, z31.b // CHECK-INST: add z4.b, p7/m, z4.b, z31.b // CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f 00 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 add z31.d, z31.d, #65280 // CHECK-INST: add z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e0 25 diff --git a/llvm/test/MC/AArch64/SVE/addpl.s b/llvm/test/MC/AArch64/SVE/addpl.s index 3cbf92551f1bd..7a11345065990 100644 --- a/llvm/test/MC/AArch64/SVE/addpl.s +++ b/llvm/test/MC/AArch64/SVE/addpl.s @@ -12,23 +12,23 @@ addpl x21, x21, #0 // CHECK-INST: addpl x21, x21, #0 // CHECK-ENCODING: [0x15,0x50,0x75,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 75 04 addpl x23, x8, #-1 // CHECK-INST: addpl x23, x8, #-1 // CHECK-ENCODING: [0xf7,0x57,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f7 57 68 04 addpl sp, sp, #31 // CHECK-INST: addpl sp, sp, #31 // CHECK-ENCODING: [0xff,0x53,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 53 7f 04 addpl x0, x0, #-32 // CHECK-INST: addpl x0, x0, #-32 // CHECK-ENCODING: [0x00,0x54,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 54 60 04 diff --git a/llvm/test/MC/AArch64/SVE/addvl.s b/llvm/test/MC/AArch64/SVE/addvl.s index d8c7cbe75db08..8ac14fae10a22 100644 --- a/llvm/test/MC/AArch64/SVE/addvl.s +++ b/llvm/test/MC/AArch64/SVE/addvl.s @@ -12,23 +12,23 @@ addvl x21, x21, #0 // CHECK-INST: addvl x21, x21, #0 // CHECK-ENCODING: [0x15,0x50,0x35,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 35 04 addvl x23, x8, #-1 // CHECK-INST: addvl x23, x8, #-1 // CHECK-ENCODING: [0xf7,0x57,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f7 57 28 04 addvl sp, sp, #31 // CHECK-INST: addvl sp, sp, #31 // CHECK-ENCODING: [0xff,0x53,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 53 3f 04 addvl x0, x0, #-32 // CHECK-INST: addvl x0, x0, #-32 // CHECK-ENCODING: [0x00,0x54,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 54 20 04 diff --git a/llvm/test/MC/AArch64/SVE/and.s b/llvm/test/MC/AArch64/SVE/and.s index 725dc9410dc79..ccdc8ebfb0d7a 100644 --- a/llvm/test/MC/AArch64/SVE/and.s +++ b/llvm/test/MC/AArch64/SVE/and.s @@ -12,103 +12,103 @@ and z5.b, z5.b, #0xf9 // CHECK-INST: and z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 80 05 and z23.h, z23.h, #0xfff9 // CHECK-INST: and z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 80 05 and z0.s, z0.s, #0xfffffff9 // CHECK-INST: and z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 80 05 and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 83 05 and z5.b, z5.b, #0x6 // CHECK-INST: and z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 80 05 and z23.h, z23.h, #0x6 // CHECK-INST: and z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 80 05 and z0.s, z0.s, #0x6 // CHECK-INST: and z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 80 05 and z0.d, z0.d, #0x6 // CHECK-INST: and z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 83 05 and z0.d, z0.d, z0.d // CHECK-INST: and z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 20 04 and z23.d, z13.d, z8.d // CHECK-INST: and z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 28 04 and z31.b, p7/m, z31.b, z31.b // CHECK-INST: and z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x1a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 1a 04 and z31.h, p7/m, z31.h, z31.h // CHECK-INST: and z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x5a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 5a 04 and z31.s, p7/m, z31.s, z31.s // CHECK-INST: and z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x9a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 9a 04 and z31.d, p7/m, z31.d, z31.d // CHECK-INST: and z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f da 04 and p0.b, p0/z, p0.b, p1.b // CHECK-INST: and p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x40,0x01,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 01 25 and p0.b, p0/z, p0.b, p0.b // CHECK-INST: mov p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x40,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 25 and p15.b, p15/z, p15.b, p15.b // CHECK-INST: mov p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 0f 25 @@ -118,19 +118,19 @@ and p15.b, p15/z, p15.b, p15.b and z0.s, z0.s, z0.s // CHECK-INST: and z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 20 04 and z0.h, z0.h, z0.h // CHECK-INST: and z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 20 04 and z0.b, z0.b, z0.b // CHECK-INST: and z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 20 04 @@ -140,35 +140,35 @@ and z0.b, z0.b, z0.b movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 and z4.d, p7/m, z4.d, z31.d // CHECK-INST: and z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f da 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 and z4.d, p7/m, z4.d, z31.d // CHECK-INST: and z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f da 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 and z0.d, z0.d, #0x6 // CHECK-INST: and z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 83 05 diff --git a/llvm/test/MC/AArch64/SVE/ands.s b/llvm/test/MC/AArch64/SVE/ands.s index de15bacc66293..c5b12f8079814 100644 --- a/llvm/test/MC/AArch64/SVE/ands.s +++ b/llvm/test/MC/AArch64/SVE/ands.s @@ -12,18 +12,18 @@ ands p0.b, p0/z, p0.b, p1.b // CHECK-INST: ands p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x40,0x41,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 41 25 ands p0.b, p0/z, p0.b, p0.b // CHECK-INST: movs p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x40,0x40,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 40 25 ands p15.b, p15/z, p15.b, p15.b // CHECK-INST: movs p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/andv.s b/llvm/test/MC/AArch64/SVE/andv.s index bd892c8668381..ed4f57e500850 100644 --- a/llvm/test/MC/AArch64/SVE/andv.s +++ b/llvm/test/MC/AArch64/SVE/andv.s @@ -12,23 +12,23 @@ andv b0, p7, z31.b // CHECK-INST: andv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x1a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 1a 04 andv h0, p7, z31.h // CHECK-INST: andv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x5a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 5a 04 andv s0, p7, z31.s // CHECK-INST: andv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x9a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 9a 04 andv d0, p7, z31.d // CHECK-INST: andv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f da 04 diff --git a/llvm/test/MC/AArch64/SVE/asr.s b/llvm/test/MC/AArch64/SVE/asr.s index 62df01406fe91..3b9f4f354c504 100644 --- a/llvm/test/MC/AArch64/SVE/asr.s +++ b/llvm/test/MC/AArch64/SVE/asr.s @@ -12,157 +12,157 @@ asr z0.b, z0.b, #1 // CHECK-INST: asr z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0x90,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 90 2f 04 asr z31.b, z31.b, #8 // CHECK-INST: asr z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0x93,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 93 28 04 asr z0.h, z0.h, #1 // CHECK-INST: asr z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0x90,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 90 3f 04 asr z31.h, z31.h, #16 // CHECK-INST: asr z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0x93,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 93 30 04 asr z0.s, z0.s, #1 // CHECK-INST: asr z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0x90,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 90 7f 04 asr z31.s, z31.s, #32 // CHECK-INST: asr z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0x93,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 93 60 04 asr z0.d, z0.d, #1 // CHECK-INST: asr z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0x90,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 90 ff 04 asr z31.d, z31.d, #64 // CHECK-INST: asr z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0x93,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 93 a0 04 asr z0.b, p0/m, z0.b, #1 // CHECK-INST: asr z0.b, p0/m, z0.b, #1 // CHECK-ENCODING: [0xe0,0x81,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 81 00 04 asr z31.b, p0/m, z31.b, #8 // CHECK-INST: asr z31.b, p0/m, z31.b, #8 // CHECK-ENCODING: [0x1f,0x81,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 81 00 04 asr z0.h, p0/m, z0.h, #1 // CHECK-INST: asr z0.h, p0/m, z0.h, #1 // CHECK-ENCODING: [0xe0,0x83,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 00 04 asr z31.h, p0/m, z31.h, #16 // CHECK-INST: asr z31.h, p0/m, z31.h, #16 // CHECK-ENCODING: [0x1f,0x82,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 82 00 04 asr z0.s, p0/m, z0.s, #1 // CHECK-INST: asr z0.s, p0/m, z0.s, #1 // CHECK-ENCODING: [0xe0,0x83,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 40 04 asr z31.s, p0/m, z31.s, #32 // CHECK-INST: asr z31.s, p0/m, z31.s, #32 // CHECK-ENCODING: [0x1f,0x80,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 40 04 asr z0.d, p0/m, z0.d, #1 // CHECK-INST: asr z0.d, p0/m, z0.d, #1 // CHECK-ENCODING: [0xe0,0x83,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 c0 04 asr z31.d, p0/m, z31.d, #64 // CHECK-INST: asr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 80 04 asr z0.b, p0/m, z0.b, z0.b // CHECK-INST: asr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x10,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 10 04 asr z0.h, p0/m, z0.h, z0.h // CHECK-INST: asr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x50,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 50 04 asr z0.s, p0/m, z0.s, z0.s // CHECK-INST: asr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 90 04 asr z0.d, p0/m, z0.d, z0.d // CHECK-INST: asr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d0 04 asr z0.b, p0/m, z0.b, z1.d // CHECK-INST: asr z0.b, p0/m, z0.b, z1.d // CHECK-ENCODING: [0x20,0x80,0x18,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 18 04 asr z0.h, p0/m, z0.h, z1.d // CHECK-INST: asr z0.h, p0/m, z0.h, z1.d // CHECK-ENCODING: [0x20,0x80,0x58,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 58 04 asr z0.s, p0/m, z0.s, z1.d // CHECK-INST: asr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 98 04 asr z0.b, z1.b, z2.d // CHECK-INST: asr z0.b, z1.b, z2.d // CHECK-ENCODING: [0x20,0x80,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 22 04 asr z0.h, z1.h, z2.d // CHECK-INST: asr z0.h, z1.h, z2.d // CHECK-ENCODING: [0x20,0x80,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 62 04 asr z0.s, z1.s, z2.d // CHECK-INST: asr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x80,0xa2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 a2 04 @@ -172,47 +172,47 @@ asr z0.s, z1.s, z2.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 asr z31.d, p0/m, z31.d, #64 // CHECK-INST: asr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 80 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 asr z31.d, p0/m, z31.d, #64 // CHECK-INST: asr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 80 04 movprfx z0.s, p0/z, z7.s // CHECK-INST: movprfx z0.s, p0/z, z7.s // CHECK-ENCODING: [0xe0,0x20,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 90 04 asr z0.s, p0/m, z0.s, z1.d // CHECK-INST: asr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 98 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 asr z0.s, p0/m, z0.s, z1.d // CHECK-INST: asr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 98 04 diff --git a/llvm/test/MC/AArch64/SVE/asrd.s b/llvm/test/MC/AArch64/SVE/asrd.s index c025a87acdbfd..e5f10f21eb3db 100644 --- a/llvm/test/MC/AArch64/SVE/asrd.s +++ b/llvm/test/MC/AArch64/SVE/asrd.s @@ -12,49 +12,49 @@ asrd z0.b, p0/m, z0.b, #1 // CHECK-INST: asrd z0.b, p0/m, z0.b, #1 // CHECK-ENCODING: [0xe0,0x81,0x04,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 81 04 04 asrd z31.b, p0/m, z31.b, #8 // CHECK-INST: asrd z31.b, p0/m, z31.b, #8 // CHECK-ENCODING: [0x1f,0x81,0x04,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 81 04 04 asrd z0.h, p0/m, z0.h, #1 // CHECK-INST: asrd z0.h, p0/m, z0.h, #1 // CHECK-ENCODING: [0xe0,0x83,0x04,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 04 04 asrd z31.h, p0/m, z31.h, #16 // CHECK-INST: asrd z31.h, p0/m, z31.h, #16 // CHECK-ENCODING: [0x1f,0x82,0x04,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 82 04 04 asrd z0.s, p0/m, z0.s, #1 // CHECK-INST: asrd z0.s, p0/m, z0.s, #1 // CHECK-ENCODING: [0xe0,0x83,0x44,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 44 04 asrd z31.s, p0/m, z31.s, #32 // CHECK-INST: asrd z31.s, p0/m, z31.s, #32 // CHECK-ENCODING: [0x1f,0x80,0x44,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 44 04 asrd z0.d, p0/m, z0.d, #1 // CHECK-INST: asrd z0.d, p0/m, z0.d, #1 // CHECK-ENCODING: [0xe0,0x83,0xc4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 c4 04 asrd z31.d, p0/m, z31.d, #64 // CHECK-INST: asrd z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 84 04 @@ -64,23 +64,23 @@ asrd z31.d, p0/m, z31.d, #64 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 asrd z31.d, p0/m, z31.d, #64 // CHECK-INST: asrd z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 84 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 asrd z31.d, p0/m, z31.d, #64 // CHECK-INST: asrd z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 84 04 diff --git a/llvm/test/MC/AArch64/SVE/asrr.s b/llvm/test/MC/AArch64/SVE/asrr.s index c95f04a9fea13..5a7b6333bfa52 100644 --- a/llvm/test/MC/AArch64/SVE/asrr.s +++ b/llvm/test/MC/AArch64/SVE/asrr.s @@ -12,25 +12,25 @@ asrr z0.b, p0/m, z0.b, z0.b // CHECK-INST: asrr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x14,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 14 04 asrr z0.h, p0/m, z0.h, z0.h // CHECK-INST: asrr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x54,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 54 04 asrr z0.s, p0/m, z0.s, z0.s // CHECK-INST: asrr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x94,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 94 04 asrr z0.d, p0/m, z0.d, z0.d // CHECK-INST: asrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d4 04 @@ -40,23 +40,23 @@ asrr z0.d, p0/m, z0.d, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 asrr z5.d, p0/m, z5.d, z0.d // CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d4 04 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 asrr z5.d, p0/m, z5.d, z0.d // CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d4 04 diff --git a/llvm/test/MC/AArch64/SVE/bfcvt.s b/llvm/test/MC/AArch64/SVE/bfcvt.s index 96619e1e6cb42..d370d2b7cccda 100644 --- a/llvm/test/MC/AArch64/SVE/bfcvt.s +++ b/llvm/test/MC/AArch64/SVE/bfcvt.s @@ -8,24 +8,24 @@ bfcvt z0.H, p0/m, z1.S // CHECK-INST: bfcvt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x65] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0.S, p0/m, z2.S // CHECK-INST: movprfx z0.s, p0/m, z2.s // CHECK-ENCODING: [0x40,0x20,0x91,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfcvt z0.H, p0/m, z1.S // CHECK-INST: bfcvt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x65] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z2 // CHECK-INST: movprfx z0, z2 // CHECK-ENCODING: [0x40,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfcvt z0.H, p0/m, z1.S // CHECK-INST: bfcvt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x65] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme diff --git a/llvm/test/MC/AArch64/SVE/bfcvtnt.s b/llvm/test/MC/AArch64/SVE/bfcvtnt.s index 2973ffe88c7d3..8751b6f4ed2d8 100644 --- a/llvm/test/MC/AArch64/SVE/bfcvtnt.s +++ b/llvm/test/MC/AArch64/SVE/bfcvtnt.s @@ -8,24 +8,24 @@ bfcvtnt z0.H, p0/m, z1.S // CHECK-INST: bfcvtnt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0.S, p0/m, z2.S // CHECK-INST: movprfx z0.s, p0/m, z2.s // CHECK-ENCODING: [0x40,0x20,0x91,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfcvtnt z0.H, p0/m, z1.S // CHECK-INST: bfcvtnt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z2 // CHECK-INST: movprfx z0, z2 // CHECK-ENCODING: [0x40,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfcvtnt z0.H, p0/m, z1.S // CHECK-INST: bfcvtnt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x8a,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme diff --git a/llvm/test/MC/AArch64/SVE/bfdot.s b/llvm/test/MC/AArch64/SVE/bfdot.s index 08794f21daa9a..c2b48e6a9a48c 100644 --- a/llvm/test/MC/AArch64/SVE/bfdot.s +++ b/llvm/test/MC/AArch64/SVE/bfdot.s @@ -8,17 +8,17 @@ bfdot z0.S, z1.H, z2.H // CHECK-INST: bfdot z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x80,0x62,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfdot z0.S, z1.H, z2.H[0] // CHECK-INST: bfdot z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x40,0x62,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfdot z0.S, z1.H, z2.H[3] // CHECK-INST: bfdot z0.s, z1.h, z2.h[3] // CHECK-ENCODING: [0x20,0x40,0x7a,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme // --------------------------------------------------------------------------// // Test compatibility with MOVPRFX instruction. @@ -26,29 +26,29 @@ bfdot z0.S, z1.H, z2.H[3] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfdot z0.S, z1.H, z2.H // CHECK-INST: bfdot z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x80,0x62,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfdot z0.S, z1.H, z2.H[0] // CHECK-INST: bfdot z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x40,0x62,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfdot z0.S, z1.H, z2.H[3] // CHECK-INST: bfdot z0.s, z1.h, z2.h[3] // CHECK-ENCODING: [0x20,0x40,0x7a,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme diff --git a/llvm/test/MC/AArch64/SVE/bfmlal.s b/llvm/test/MC/AArch64/SVE/bfmlal.s index 6bb7b5876d8e3..4395fe8928247 100644 --- a/llvm/test/MC/AArch64/SVE/bfmlal.s +++ b/llvm/test/MC/AArch64/SVE/bfmlal.s @@ -8,52 +8,52 @@ bfmlalb z0.S, z1.H, z2.H // CHECK-INST: bfmlalb z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x80,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalt z0.S, z1.H, z2.H // CHECK-INST: bfmlalt z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x84,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalb z0.S, z1.H, z2.H[0] // CHECK-INST: bfmlalb z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x40,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalt z0.S, z1.H, z2.H[0] // CHECK-INST: bfmlalt z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x44,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalb z0.S, z1.H, z2.H[7] // CHECK-INST: bfmlalb z0.s, z1.h, z2.h[7] // CHECK-ENCODING: [0x20,0x48,0xfa,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalt z0.S, z1.H, z2.H[7] // CHECK-INST: bfmlalt z0.s, z1.h, z2.h[7] // CHECK-ENCODING: [0x20,0x4c,0xfa,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalt z0.S, z1.H, z7.H[7] // CHECK-INST: bfmlalt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x4c,0xff,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalb z10.S, z21.H, z14.H // CHECK-INST: bfmlalb z10.s, z21.h, z14.h // CHECK-ENCODING: [0xaa,0x82,0xee,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalt z14.S, z10.H, z21.H // CHECK-INST: bfmlalt z14.s, z10.h, z21.h // CHECK-ENCODING: [0x4e,0x85,0xf5,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme bfmlalb z21.s, z14.h, z3.h[2] // CHECK-INST: bfmlalb z21.s, z14.h, z3.h[2] // CHECK-ENCODING: [0xd5,0x41,0xeb,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme // --------------------------------------------------------------------------// // Test compatibility with MOVPRFX instruction. @@ -61,99 +61,99 @@ bfmlalb z21.s, z14.h, z3.h[2] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalb z0.S, z1.H, z2.H // CHECK-INST: bfmlalb z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x80,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalt z0.S, z1.H, z2.H // CHECK-INST: bfmlalt z0.s, z1.h, z2.h // CHECK-ENCODING: [0x20,0x84,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalb z0.S, z1.H, z2.H[0] // CHECK-INST: bfmlalb z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x40,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalt z0.S, z1.H, z2.H[0] // CHECK-INST: bfmlalt z0.s, z1.h, z2.h[0] // CHECK-ENCODING: [0x20,0x44,0xe2,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalb z0.S, z1.H, z2.H[7] // CHECK-INST: bfmlalb z0.s, z1.h, z2.h[7] // CHECK-ENCODING: [0x20,0x48,0xfa,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalt z0.S, z1.H, z2.H[7] // CHECK-INST: bfmlalt z0.s, z1.h, z2.h[7] // CHECK-ENCODING: [0x20,0x4c,0xfa,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalt z0.S, z1.H, z7.H[7] // CHECK-INST: bfmlalt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x4c,0xff,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z10, z7 // CHECK-INST: movprfx z10, z7 // CHECK-ENCODING: [0xea,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalb z10.S, z21.H, z14.H // CHECK-INST: bfmlalb z10.s, z21.h, z14.h // CHECK-ENCODING: [0xaa,0x82,0xee,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z14, z7 // CHECK-INST: movprfx z14, z7 // CHECK-ENCODING: [0xee,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalt z14.S, z10.H, z21.H // CHECK-INST: bfmlalt z14.s, z10.h, z21.h // CHECK-ENCODING: [0x4e,0x85,0xf5,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme movprfx z21, z7 // CHECK-INST: movprfx z21, z7 // CHECK-ENCODING: [0xf5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmlalb z21.s, z14.h, z3.h[2] // CHECK-INST: bfmlalb z21.s, z14.h, z3.h[2] // CHECK-ENCODING: [0xd5,0x41,0xeb,0x64] -// CHECK-ERROR: instruction requires: bf16 streaming-sve or sve +// CHECK-ERROR: instruction requires: bf16 sve or sme diff --git a/llvm/test/MC/AArch64/SVE/bfmmla.s b/llvm/test/MC/AArch64/SVE/bfmmla.s index 6d4d809341efa..660f3034837a9 100644 --- a/llvm/test/MC/AArch64/SVE/bfmmla.s +++ b/llvm/test/MC/AArch64/SVE/bfmmla.s @@ -14,7 +14,7 @@ bfmmla z0.S, z1.H, z2.H movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme bfmmla z0.S, z1.H, z2.H // CHECK-INST: bfmmla z0.s, z1.h, z2.h diff --git a/llvm/test/MC/AArch64/SVE/bic.s b/llvm/test/MC/AArch64/SVE/bic.s index 992da415df0ea..af7db10944cea 100644 --- a/llvm/test/MC/AArch64/SVE/bic.s +++ b/llvm/test/MC/AArch64/SVE/bic.s @@ -12,97 +12,97 @@ bic z5.b, z5.b, #0xf9 // CHECK-INST: and z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 80 05 bic z23.h, z23.h, #0xfff9 // CHECK-INST: and z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 80 05 bic z0.s, z0.s, #0xfffffff9 // CHECK-INST: and z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 80 05 bic z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: and z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 83 05 bic z5.b, z5.b, #0x6 // CHECK-INST: and z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 80 05 bic z23.h, z23.h, #0x6 // CHECK-INST: and z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 80 05 bic z0.s, z0.s, #0x6 // CHECK-INST: and z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 80 05 bic z0.d, z0.d, #0x6 // CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 83 05 bic z0.d, z0.d, z0.d // CHECK-INST: bic z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 e0 04 bic z23.d, z13.d, z8.d // CHECK-INST: bic z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0xe8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 e8 04 bic z31.b, p7/m, z31.b, z31.b // CHECK-INST: bic z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x1b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 1b 04 bic z31.h, p7/m, z31.h, z31.h // CHECK-INST: bic z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x5b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 5b 04 bic z31.s, p7/m, z31.s, z31.s // CHECK-INST: bic z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x9b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 9b 04 bic z31.d, p7/m, z31.d, z31.d // CHECK-INST: bic z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f db 04 bic p15.b, p15/z, p15.b, p15.b // CHECK-INST: bic p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7d 0f 25 bic p0.b, p0/z, p0.b, p0.b // CHECK-INST: bic p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 00 25 @@ -112,19 +112,19 @@ bic p0.b, p0/z, p0.b, p0.b bic z0.s, z0.s, z0.s // CHECK-INST: bic z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 e0 04 bic z0.h, z0.h, z0.h // CHECK-INST: bic z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 e0 04 bic z0.b, z0.b, z0.b // CHECK-INST: bic z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 e0 04 @@ -134,35 +134,35 @@ bic z0.b, z0.b, z0.b movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 bic z4.d, p7/m, z4.d, z31.d // CHECK-INST: bic z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f db 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 bic z4.d, p7/m, z4.d, z31.d // CHECK-INST: bic z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f db 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 bic z0.d, z0.d, #0x6 // CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 83 05 diff --git a/llvm/test/MC/AArch64/SVE/bics.s b/llvm/test/MC/AArch64/SVE/bics.s index eb83d3b0c9ba0..6605480cc473c 100644 --- a/llvm/test/MC/AArch64/SVE/bics.s +++ b/llvm/test/MC/AArch64/SVE/bics.s @@ -12,11 +12,11 @@ bics p0.b, p0/z, p0.b, p0.b // CHECK-INST: bics p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0x40,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 40 25 bics p15.b, p15/z, p15.b, p15.b // CHECK-INST: bics p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7d 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/brka.s b/llvm/test/MC/AArch64/SVE/brka.s index debe686e3c366..753299a860c44 100644 --- a/llvm/test/MC/AArch64/SVE/brka.s +++ b/llvm/test/MC/AArch64/SVE/brka.s @@ -12,11 +12,11 @@ brka p0.b, p15/m, p15.b // CHECK-INST: brka p0.b, p15/m, p15.b // CHECK-ENCODING: [0xf0,0x7d,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f0 7d 10 25 brka p0.b, p15/z, p15.b // CHECK-INST: brka p0.b, p15/z, p15.b // CHECK-ENCODING: [0xe0,0x7d,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 7d 10 25 diff --git a/llvm/test/MC/AArch64/SVE/brkas.s b/llvm/test/MC/AArch64/SVE/brkas.s index 3d37a4e113a92..7de38c524c458 100644 --- a/llvm/test/MC/AArch64/SVE/brkas.s +++ b/llvm/test/MC/AArch64/SVE/brkas.s @@ -12,5 +12,5 @@ brkas p0.b, p15/z, p15.b // CHECK-INST: brkas p0.b, p15/z, p15.b // CHECK-ENCODING: [0xe0,0x7d,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 7d 50 25 diff --git a/llvm/test/MC/AArch64/SVE/brkb.s b/llvm/test/MC/AArch64/SVE/brkb.s index ae59b6a8f3b11..c28727dc609c0 100644 --- a/llvm/test/MC/AArch64/SVE/brkb.s +++ b/llvm/test/MC/AArch64/SVE/brkb.s @@ -12,11 +12,11 @@ brkb p0.b, p15/m, p15.b // CHECK-INST: brkb p0.b, p15/m, p15.b // CHECK-ENCODING: [0xf0,0x7d,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f0 7d 90 25 brkb p0.b, p15/z, p15.b // CHECK-INST: brkb p0.b, p15/z, p15.b // CHECK-ENCODING: [0xe0,0x7d,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 7d 90 25 diff --git a/llvm/test/MC/AArch64/SVE/brkbs.s b/llvm/test/MC/AArch64/SVE/brkbs.s index 2865ab5127b73..d72c596076517 100644 --- a/llvm/test/MC/AArch64/SVE/brkbs.s +++ b/llvm/test/MC/AArch64/SVE/brkbs.s @@ -12,5 +12,5 @@ brkbs p0.b, p15/z, p15.b // CHECK-INST: brkbs p0.b, p15/z, p15.b // CHECK-ENCODING: [0xe0,0x7d,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 7d d0 25 diff --git a/llvm/test/MC/AArch64/SVE/brkn.s b/llvm/test/MC/AArch64/SVE/brkn.s index 43f189d6c93e0..8f8095fc61619 100644 --- a/llvm/test/MC/AArch64/SVE/brkn.s +++ b/llvm/test/MC/AArch64/SVE/brkn.s @@ -12,11 +12,11 @@ brkn p0.b, p15/z, p1.b, p0.b // CHECK-INST: brkn p0.b, p15/z, p1.b, p0.b // CHECK-ENCODING: [0x20,0x7c,0x18,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 18 25 brkn p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkn p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x18,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 18 25 diff --git a/llvm/test/MC/AArch64/SVE/brkns.s b/llvm/test/MC/AArch64/SVE/brkns.s index 9aaad2e820ef0..c380e1c2ba39d 100644 --- a/llvm/test/MC/AArch64/SVE/brkns.s +++ b/llvm/test/MC/AArch64/SVE/brkns.s @@ -12,11 +12,11 @@ brkns p0.b, p15/z, p1.b, p0.b // CHECK-INST: brkns p0.b, p15/z, p1.b, p0.b // CHECK-ENCODING: [0x20,0x7c,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 58 25 brkns p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkns p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 58 25 diff --git a/llvm/test/MC/AArch64/SVE/brkpa.s b/llvm/test/MC/AArch64/SVE/brkpa.s index b05fc96a41d44..e384b805e0f4c 100644 --- a/llvm/test/MC/AArch64/SVE/brkpa.s +++ b/llvm/test/MC/AArch64/SVE/brkpa.s @@ -12,11 +12,11 @@ brkpa p0.b, p15/z, p1.b, p2.b // CHECK-INST: brkpa p0.b, p15/z, p1.b, p2.b // CHECK-ENCODING: [0x20,0xfc,0x02,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc 02 25 brkpa p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkpa p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0xfd,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef fd 0f 25 diff --git a/llvm/test/MC/AArch64/SVE/brkpas.s b/llvm/test/MC/AArch64/SVE/brkpas.s index 6f816e19d5345..5cd7863fe36d0 100644 --- a/llvm/test/MC/AArch64/SVE/brkpas.s +++ b/llvm/test/MC/AArch64/SVE/brkpas.s @@ -12,11 +12,11 @@ brkpas p0.b, p15/z, p1.b, p2.b // CHECK-INST: brkpas p0.b, p15/z, p1.b, p2.b // CHECK-ENCODING: [0x20,0xfc,0x42,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc 42 25 brkpas p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkpas p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0xfd,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef fd 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/brkpb.s b/llvm/test/MC/AArch64/SVE/brkpb.s index 9db00f8862bfe..5b0d3ec5acce5 100644 --- a/llvm/test/MC/AArch64/SVE/brkpb.s +++ b/llvm/test/MC/AArch64/SVE/brkpb.s @@ -12,11 +12,11 @@ brkpb p0.b, p15/z, p1.b, p2.b // CHECK-INST: brkpb p0.b, p15/z, p1.b, p2.b // CHECK-ENCODING: [0x30,0xfc,0x02,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 fc 02 25 brkpb p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkpb p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0xfd,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff fd 0f 25 diff --git a/llvm/test/MC/AArch64/SVE/brkpbs.s b/llvm/test/MC/AArch64/SVE/brkpbs.s index fd6318a964dba..f7c9d408709fc 100644 --- a/llvm/test/MC/AArch64/SVE/brkpbs.s +++ b/llvm/test/MC/AArch64/SVE/brkpbs.s @@ -12,11 +12,11 @@ brkpbs p0.b, p15/z, p1.b, p2.b // CHECK-INST: brkpbs p0.b, p15/z, p1.b, p2.b // CHECK-ENCODING: [0x30,0xfc,0x42,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 fc 42 25 brkpbs p15.b, p15/z, p15.b, p15.b // CHECK-INST: brkpbs p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0xfd,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff fd 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/clasta.s b/llvm/test/MC/AArch64/SVE/clasta.s index 7620f7b2187fa..bed54441dc0c3 100644 --- a/llvm/test/MC/AArch64/SVE/clasta.s +++ b/llvm/test/MC/AArch64/SVE/clasta.s @@ -12,73 +12,73 @@ clasta w0, p7, w0, z31.b // CHECK-INST: clasta w0, p7, w0, z31.b // CHECK-ENCODING: [0xe0,0xbf,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 30 05 clasta w0, p7, w0, z31.h // CHECK-INST: clasta w0, p7, w0, z31.h // CHECK-ENCODING: [0xe0,0xbf,0x70,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 70 05 clasta w0, p7, w0, z31.s // CHECK-INST: clasta w0, p7, w0, z31.s // CHECK-ENCODING: [0xe0,0xbf,0xb0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf b0 05 clasta x0, p7, x0, z31.d // CHECK-INST: clasta x0, p7, x0, z31.d // CHECK-ENCODING: [0xe0,0xbf,0xf0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf f0 05 clasta b0, p7, b0, z31.b // CHECK-INST: clasta b0, p7, b0, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x2a,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 2a 05 clasta h0, p7, h0, z31.h // CHECK-INST: clasta h0, p7, h0, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x6a,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 6a 05 clasta s0, p7, s0, z31.s // CHECK-INST: clasta s0, p7, s0, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xaa,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f aa 05 clasta d0, p7, d0, z31.d // CHECK-INST: clasta d0, p7, d0, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xea,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f ea 05 clasta z0.b, p7, z0.b, z31.b // CHECK-INST: clasta z0.b, p7, z0.b, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 28 05 clasta z0.h, p7, z0.h, z31.h // CHECK-INST: clasta z0.h, p7, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 68 05 clasta z0.s, p7, z0.s, z31.s // CHECK-INST: clasta z0.s, p7, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a8 05 clasta z0.d, p7, z0.d, z31.d // CHECK-INST: clasta z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e8 05 @@ -88,11 +88,11 @@ clasta z0.d, p7, z0.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 clasta z0.d, p7, z0.d, z31.d // CHECK-INST: clasta z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e8 05 diff --git a/llvm/test/MC/AArch64/SVE/clastb.s b/llvm/test/MC/AArch64/SVE/clastb.s index 5426ef04d0afc..c564d1d100a4d 100644 --- a/llvm/test/MC/AArch64/SVE/clastb.s +++ b/llvm/test/MC/AArch64/SVE/clastb.s @@ -12,73 +12,73 @@ clastb w0, p7, w0, z31.b // CHECK-INST: clastb w0, p7, w0, z31.b // CHECK-ENCODING: [0xe0,0xbf,0x31,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 31 05 clastb w0, p7, w0, z31.h // CHECK-INST: clastb w0, p7, w0, z31.h // CHECK-ENCODING: [0xe0,0xbf,0x71,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 71 05 clastb w0, p7, w0, z31.s // CHECK-INST: clastb w0, p7, w0, z31.s // CHECK-ENCODING: [0xe0,0xbf,0xb1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf b1 05 clastb x0, p7, x0, z31.d // CHECK-INST: clastb x0, p7, x0, z31.d // CHECK-ENCODING: [0xe0,0xbf,0xf1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf f1 05 clastb b0, p7, b0, z31.b // CHECK-INST: clastb b0, p7, b0, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x2b,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 2b 05 clastb h0, p7, h0, z31.h // CHECK-INST: clastb h0, p7, h0, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x6b,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 6b 05 clastb s0, p7, s0, z31.s // CHECK-INST: clastb s0, p7, s0, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xab,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f ab 05 clastb d0, p7, d0, z31.d // CHECK-INST: clastb d0, p7, d0, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xeb,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f eb 05 clastb z0.b, p7, z0.b, z31.b // CHECK-INST: clastb z0.b, p7, z0.b, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x29,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 29 05 clastb z0.h, p7, z0.h, z31.h // CHECK-INST: clastb z0.h, p7, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x69,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 69 05 clastb z0.s, p7, z0.s, z31.s // CHECK-INST: clastb z0.s, p7, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa9,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a9 05 clastb z0.d, p7, z0.d, z31.d // CHECK-INST: clastb z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e9 05 @@ -88,11 +88,11 @@ clastb z0.d, p7, z0.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 clastb z0.d, p7, z0.d, z31.d // CHECK-INST: clastb z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e9 05 diff --git a/llvm/test/MC/AArch64/SVE/cls.s b/llvm/test/MC/AArch64/SVE/cls.s index 02e035eab89c4..127fb2a867848 100644 --- a/llvm/test/MC/AArch64/SVE/cls.s +++ b/llvm/test/MC/AArch64/SVE/cls.s @@ -12,25 +12,25 @@ cls z31.b, p7/m, z31.b // CHECK-INST: cls z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x18,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 18 04 cls z31.h, p7/m, z31.h // CHECK-INST: cls z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x58,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 58 04 cls z31.s, p7/m, z31.s // CHECK-INST: cls z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 98 04 cls z31.d, p7/m, z31.d // CHECK-INST: cls z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d8 04 @@ -40,23 +40,23 @@ cls z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 cls z4.d, p7/m, z31.d // CHECK-INST: cls z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d8 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cls z4.d, p7/m, z31.d // CHECK-INST: cls z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d8 04 diff --git a/llvm/test/MC/AArch64/SVE/clz.s b/llvm/test/MC/AArch64/SVE/clz.s index 73563b7a26e71..07d1f9f4b3304 100644 --- a/llvm/test/MC/AArch64/SVE/clz.s +++ b/llvm/test/MC/AArch64/SVE/clz.s @@ -12,25 +12,25 @@ clz z31.b, p7/m, z31.b // CHECK-INST: clz z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 19 04 clz z31.h, p7/m, z31.h // CHECK-INST: clz z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x59,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 59 04 clz z31.s, p7/m, z31.s // CHECK-INST: clz z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 99 04 clz z31.d, p7/m, z31.d // CHECK-INST: clz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d9 04 @@ -40,23 +40,23 @@ clz z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 clz z4.d, p7/m, z31.d // CHECK-INST: clz z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d9 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 clz z4.d, p7/m, z31.d // CHECK-INST: clz z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d9 04 diff --git a/llvm/test/MC/AArch64/SVE/cmpeq.s b/llvm/test/MC/AArch64/SVE/cmpeq.s index 3c2ac7ef7bd10..d5c79f8248a56 100644 --- a/llvm/test/MC/AArch64/SVE/cmpeq.s +++ b/llvm/test/MC/AArch64/SVE/cmpeq.s @@ -13,89 +13,89 @@ cmpeq p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x00,0xa0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 00 24 cmpeq p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x00,0xa0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 24 cmpeq p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x00,0xa0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 80 24 cmpeq p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmpeq p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x00,0xa0,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 24 cmpeq p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x00,0x20,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 00 24 cmpeq p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x00,0x20,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 40 24 cmpeq p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x00,0x20,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 80 24 cmpeq p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x00,0x80,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 10 25 cmpeq p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x00,0x80,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 50 25 cmpeq p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x00,0x80,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 90 25 cmpeq p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmpeq p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x00,0x80,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d0 25 cmpeq p0.b, p0/z, z0.b, #15 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x00,0x80,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 0f 25 cmpeq p0.h, p0/z, z0.h, #15 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x00,0x80,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 4f 25 cmpeq p0.s, p0/z, z0.s, #15 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x00,0x80,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 8f 25 cmpeq p0.d, p0/z, z0.d, #15 // CHECK-INST: cmpeq p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x00,0x80,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cmpge.s b/llvm/test/MC/AArch64/SVE/cmpge.s index 1953087c28da9..14fcfc40f2ac0 100644 --- a/llvm/test/MC/AArch64/SVE/cmpge.s +++ b/llvm/test/MC/AArch64/SVE/cmpge.s @@ -12,89 +12,89 @@ cmpge p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmpge p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 00 24 cmpge p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmpge p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 40 24 cmpge p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmpge p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 80 24 cmpge p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmpge p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 c0 24 cmpge p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmpge p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x00,0x40,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 24 cmpge p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmpge p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x00,0x40,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 40 24 cmpge p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmpge p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x00,0x40,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 80 24 cmpge p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmpge p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x00,0x00,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 10 25 cmpge p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmpge p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x00,0x00,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 50 25 cmpge p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmpge p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x00,0x00,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 90 25 cmpge p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmpge p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x00,0x00,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 d0 25 cmpge p0.b, p0/z, z0.b, #15 // CHECK-INST: cmpge p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x00,0x00,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 0f 25 cmpge p0.h, p0/z, z0.h, #15 // CHECK-INST: cmpge p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x00,0x00,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 4f 25 cmpge p0.s, p0/z, z0.s, #15 // CHECK-INST: cmpge p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x00,0x00,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 8f 25 cmpge p0.d, p0/z, z0.d, #15 // CHECK-INST: cmpge p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x00,0x00,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cmpgt.s b/llvm/test/MC/AArch64/SVE/cmpgt.s index 7b60eeacc23ff..34366e2110e3c 100644 --- a/llvm/test/MC/AArch64/SVE/cmpgt.s +++ b/llvm/test/MC/AArch64/SVE/cmpgt.s @@ -13,89 +13,89 @@ cmpgt p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x10,0x80,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 00 24 cmpgt p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x10,0x80,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 40 24 cmpgt p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x10,0x80,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 80 24 cmpgt p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmpgt p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x10,0x80,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 c0 24 cmpgt p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x10,0x40,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 00 24 cmpgt p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x10,0x40,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 40 24 cmpgt p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x10,0x40,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 80 24 cmpgt p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x10,0x00,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 10 25 cmpgt p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x10,0x00,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 50 25 cmpgt p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x10,0x00,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 90 25 cmpgt p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmpgt p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x10,0x00,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 d0 25 cmpgt p0.b, p0/z, z0.b, #15 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x10,0x00,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 0f 25 cmpgt p0.h, p0/z, z0.h, #15 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x10,0x00,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 4f 25 cmpgt p0.s, p0/z, z0.s, #15 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x10,0x00,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 8f 25 cmpgt p0.d, p0/z, z0.d, #15 // CHECK-INST: cmpgt p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x10,0x00,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cmphi.s b/llvm/test/MC/AArch64/SVE/cmphi.s index e4c9237a8e333..e2682d3b89ab3 100644 --- a/llvm/test/MC/AArch64/SVE/cmphi.s +++ b/llvm/test/MC/AArch64/SVE/cmphi.s @@ -13,89 +13,89 @@ cmphi p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x10,0x00,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 00 24 cmphi p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x10,0x00,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 40 24 cmphi p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x10,0x00,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 80 24 cmphi p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmphi p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x10,0x00,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 c0 24 cmphi p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x10,0xc0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 00 24 cmphi p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x10,0xc0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 40 24 cmphi p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x10,0xc0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 80 24 cmphi p0.b, p0/z, z0.b, #0 // CHECK-INST: cmphi p0.b, p0/z, z0.b, #0 // CHECK-ENCODING: [0x10,0x00,0x20,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 20 24 cmphi p0.h, p0/z, z0.h, #0 // CHECK-INST: cmphi p0.h, p0/z, z0.h, #0 // CHECK-ENCODING: [0x10,0x00,0x60,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 60 24 cmphi p0.s, p0/z, z0.s, #0 // CHECK-INST: cmphi p0.s, p0/z, z0.s, #0 // CHECK-ENCODING: [0x10,0x00,0xa0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 a0 24 cmphi p0.d, p0/z, z0.d, #0 // CHECK-INST: cmphi p0.d, p0/z, z0.d, #0 // CHECK-ENCODING: [0x10,0x00,0xe0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 00 e0 24 cmphi p0.b, p0/z, z0.b, #127 // CHECK-INST: cmphi p0.b, p0/z, z0.b, #127 // CHECK-ENCODING: [0x10,0xc0,0x3f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 3f 24 cmphi p0.h, p0/z, z0.h, #127 // CHECK-INST: cmphi p0.h, p0/z, z0.h, #127 // CHECK-ENCODING: [0x10,0xc0,0x7f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 7f 24 cmphi p0.s, p0/z, z0.s, #127 // CHECK-INST: cmphi p0.s, p0/z, z0.s, #127 // CHECK-ENCODING: [0x10,0xc0,0xbf,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 bf 24 cmphi p0.d, p0/z, z0.d, #127 // CHECK-INST: cmphi p0.d, p0/z, z0.d, #127 // CHECK-ENCODING: [0x10,0xc0,0xff,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 ff 24 diff --git a/llvm/test/MC/AArch64/SVE/cmphs.s b/llvm/test/MC/AArch64/SVE/cmphs.s index b80a864b0a12e..bbe3ec323c820 100644 --- a/llvm/test/MC/AArch64/SVE/cmphs.s +++ b/llvm/test/MC/AArch64/SVE/cmphs.s @@ -13,89 +13,89 @@ cmphs p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 00 24 cmphs p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 40 24 cmphs p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 24 cmphs p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmphs p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c0 24 cmphs p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x00,0xc0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 00 24 cmphs p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x00,0xc0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 40 24 cmphs p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x00,0xc0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 80 24 cmphs p0.b, p0/z, z0.b, #0 // CHECK-INST: cmphs p0.b, p0/z, z0.b, #0 // CHECK-ENCODING: [0x00,0x00,0x20,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 20 24 cmphs p0.h, p0/z, z0.h, #0 // CHECK-INST: cmphs p0.h, p0/z, z0.h, #0 // CHECK-ENCODING: [0x00,0x00,0x60,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 60 24 cmphs p0.s, p0/z, z0.s, #0 // CHECK-INST: cmphs p0.s, p0/z, z0.s, #0 // CHECK-ENCODING: [0x00,0x00,0xa0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 a0 24 cmphs p0.d, p0/z, z0.d, #0 // CHECK-INST: cmphs p0.d, p0/z, z0.d, #0 // CHECK-ENCODING: [0x00,0x00,0xe0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 e0 24 cmphs p0.b, p0/z, z0.b, #127 // CHECK-INST: cmphs p0.b, p0/z, z0.b, #127 // CHECK-ENCODING: [0x00,0xc0,0x3f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 3f 24 cmphs p0.h, p0/z, z0.h, #127 // CHECK-INST: cmphs p0.h, p0/z, z0.h, #127 // CHECK-ENCODING: [0x00,0xc0,0x7f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 7f 24 cmphs p0.s, p0/z, z0.s, #127 // CHECK-INST: cmphs p0.s, p0/z, z0.s, #127 // CHECK-ENCODING: [0x00,0xc0,0xbf,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 bf 24 cmphs p0.d, p0/z, z0.d, #127 // CHECK-INST: cmphs p0.d, p0/z, z0.d, #127 // CHECK-ENCODING: [0x00,0xc0,0xff,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 ff 24 diff --git a/llvm/test/MC/AArch64/SVE/cmple.s b/llvm/test/MC/AArch64/SVE/cmple.s index ecb8a9ac4fd55..8de87478f04b2 100644 --- a/llvm/test/MC/AArch64/SVE/cmple.s +++ b/llvm/test/MC/AArch64/SVE/cmple.s @@ -12,89 +12,89 @@ cmple p0.b, p0/z, z0.b, z1.b // CHECK-INST: cmpge p0.b, p0/z, z1.b, z0.b // CHECK-ENCODING: [0x20,0x80,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 00 24 cmple p0.h, p0/z, z0.h, z1.h // CHECK-INST: cmpge p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x20,0x80,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 40 24 cmple p0.s, p0/z, z0.s, z1.s // CHECK-INST: cmpge p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x20,0x80,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 80 24 cmple p0.d, p0/z, z0.d, z1.d // CHECK-INST: cmpge p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x20,0x80,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 c0 24 cmple p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmple p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x10,0x60,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 00 24 cmple p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmple p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x10,0x60,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 40 24 cmple p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmple p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x10,0x60,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 80 24 cmple p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmple p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x10,0x20,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 10 25 cmple p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmple p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x10,0x20,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 50 25 cmple p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmple p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x10,0x20,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 90 25 cmple p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmple p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x10,0x20,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 d0 25 cmple p0.b, p0/z, z0.b, #15 // CHECK-INST: cmple p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x10,0x20,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 0f 25 cmple p0.h, p0/z, z0.h, #15 // CHECK-INST: cmple p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x10,0x20,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 4f 25 cmple p0.s, p0/z, z0.s, #15 // CHECK-INST: cmple p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x10,0x20,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 8f 25 cmple p0.d, p0/z, z0.d, #15 // CHECK-INST: cmple p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x10,0x20,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cmplo.s b/llvm/test/MC/AArch64/SVE/cmplo.s index 139c86fd40999..30a6120c02144 100644 --- a/llvm/test/MC/AArch64/SVE/cmplo.s +++ b/llvm/test/MC/AArch64/SVE/cmplo.s @@ -12,89 +12,89 @@ cmplo p0.b, p0/z, z0.b, z1.b // CHECK-INST: cmphi p0.b, p0/z, z1.b, z0.b // CHECK-ENCODING: [0x30,0x00,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 00 00 24 cmplo p0.h, p0/z, z0.h, z1.h // CHECK-INST: cmphi p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x30,0x00,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 00 40 24 cmplo p0.s, p0/z, z0.s, z1.s // CHECK-INST: cmphi p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x30,0x00,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 00 80 24 cmplo p0.d, p0/z, z0.d, z1.d // CHECK-INST: cmphi p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x30,0x00,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 00 c0 24 cmplo p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmplo p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x00,0xe0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 24 cmplo p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmplo p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x00,0xe0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 24 cmplo p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmplo p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x00,0xe0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 80 24 cmplo p0.b, p0/z, z0.b, #0 // CHECK-INST: cmplo p0.b, p0/z, z0.b, #0 // CHECK-ENCODING: [0x00,0x20,0x20,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 20 24 cmplo p0.h, p0/z, z0.h, #0 // CHECK-INST: cmplo p0.h, p0/z, z0.h, #0 // CHECK-ENCODING: [0x00,0x20,0x60,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 60 24 cmplo p0.s, p0/z, z0.s, #0 // CHECK-INST: cmplo p0.s, p0/z, z0.s, #0 // CHECK-ENCODING: [0x00,0x20,0xa0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 a0 24 cmplo p0.d, p0/z, z0.d, #0 // CHECK-INST: cmplo p0.d, p0/z, z0.d, #0 // CHECK-ENCODING: [0x00,0x20,0xe0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 e0 24 cmplo p0.b, p0/z, z0.b, #127 // CHECK-INST: cmplo p0.b, p0/z, z0.b, #127 // CHECK-ENCODING: [0x00,0xe0,0x3f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 3f 24 cmplo p0.h, p0/z, z0.h, #127 // CHECK-INST: cmplo p0.h, p0/z, z0.h, #127 // CHECK-ENCODING: [0x00,0xe0,0x7f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 7f 24 cmplo p0.s, p0/z, z0.s, #127 // CHECK-INST: cmplo p0.s, p0/z, z0.s, #127 // CHECK-ENCODING: [0x00,0xe0,0xbf,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 bf 24 cmplo p0.d, p0/z, z0.d, #127 // CHECK-INST: cmplo p0.d, p0/z, z0.d, #127 // CHECK-ENCODING: [0x00,0xe0,0xff,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 ff 24 diff --git a/llvm/test/MC/AArch64/SVE/cmpls.s b/llvm/test/MC/AArch64/SVE/cmpls.s index c7aea83f9b373..195a4099d2d26 100644 --- a/llvm/test/MC/AArch64/SVE/cmpls.s +++ b/llvm/test/MC/AArch64/SVE/cmpls.s @@ -12,89 +12,89 @@ cmpls p0.b, p0/z, z0.b, z1.b // CHECK-INST: cmphs p0.b, p0/z, z1.b, z0.b // CHECK-ENCODING: [0x20,0x00,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 00 24 cmpls p0.h, p0/z, z0.h, z1.h // CHECK-INST: cmphs p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x20,0x00,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 40 24 cmpls p0.s, p0/z, z0.s, z1.s // CHECK-INST: cmphs p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x20,0x00,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 80 24 cmpls p0.d, p0/z, z0.d, z1.d // CHECK-INST: cmphs p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x20,0x00,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 c0 24 cmpls p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmpls p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x10,0xe0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 00 24 cmpls p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmpls p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x10,0xe0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 40 24 cmpls p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmpls p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x10,0xe0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 80 24 cmpls p0.b, p0/z, z0.b, #0 // CHECK-INST: cmpls p0.b, p0/z, z0.b, #0 // CHECK-ENCODING: [0x10,0x20,0x20,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 20 24 cmpls p0.h, p0/z, z0.h, #0 // CHECK-INST: cmpls p0.h, p0/z, z0.h, #0 // CHECK-ENCODING: [0x10,0x20,0x60,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 60 24 cmpls p0.s, p0/z, z0.s, #0 // CHECK-INST: cmpls p0.s, p0/z, z0.s, #0 // CHECK-ENCODING: [0x10,0x20,0xa0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 a0 24 cmpls p0.d, p0/z, z0.d, #0 // CHECK-INST: cmpls p0.d, p0/z, z0.d, #0 // CHECK-ENCODING: [0x10,0x20,0xe0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 e0 24 cmpls p0.b, p0/z, z0.b, #127 // CHECK-INST: cmpls p0.b, p0/z, z0.b, #127 // CHECK-ENCODING: [0x10,0xe0,0x3f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 3f 24 cmpls p0.h, p0/z, z0.h, #127 // CHECK-INST: cmpls p0.h, p0/z, z0.h, #127 // CHECK-ENCODING: [0x10,0xe0,0x7f,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 7f 24 cmpls p0.s, p0/z, z0.s, #127 // CHECK-INST: cmpls p0.s, p0/z, z0.s, #127 // CHECK-ENCODING: [0x10,0xe0,0xbf,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 bf 24 cmpls p0.d, p0/z, z0.d, #127 // CHECK-INST: cmpls p0.d, p0/z, z0.d, #127 // CHECK-ENCODING: [0x10,0xe0,0xff,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 ff 24 diff --git a/llvm/test/MC/AArch64/SVE/cmplt.s b/llvm/test/MC/AArch64/SVE/cmplt.s index 77353120b199e..93af97cf23f62 100644 --- a/llvm/test/MC/AArch64/SVE/cmplt.s +++ b/llvm/test/MC/AArch64/SVE/cmplt.s @@ -12,89 +12,89 @@ cmplt p0.b, p0/z, z0.b, z1.b // CHECK-INST: cmpgt p0.b, p0/z, z1.b, z0.b // CHECK-ENCODING: [0x30,0x80,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 80 00 24 cmplt p0.h, p0/z, z0.h, z1.h // CHECK-INST: cmpgt p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x30,0x80,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 80 40 24 cmplt p0.s, p0/z, z0.s, z1.s // CHECK-INST: cmpgt p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x30,0x80,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 80 80 24 cmplt p0.d, p0/z, z0.d, z1.d // CHECK-INST: cmpgt p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x30,0x80,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 80 c0 24 cmplt p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmplt p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x00,0x60,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 00 24 cmplt p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmplt p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x00,0x60,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 40 24 cmplt p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmplt p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x00,0x60,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 80 24 cmplt p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmplt p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x00,0x20,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 10 25 cmplt p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmplt p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x00,0x20,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 50 25 cmplt p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmplt p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x00,0x20,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 90 25 cmplt p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmplt p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x00,0x20,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 d0 25 cmplt p0.b, p0/z, z0.b, #15 // CHECK-INST: cmplt p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x00,0x20,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 0f 25 cmplt p0.h, p0/z, z0.h, #15 // CHECK-INST: cmplt p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x00,0x20,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 4f 25 cmplt p0.s, p0/z, z0.s, #15 // CHECK-INST: cmplt p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x00,0x20,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 8f 25 cmplt p0.d, p0/z, z0.d, #15 // CHECK-INST: cmplt p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x00,0x20,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cmpne.s b/llvm/test/MC/AArch64/SVE/cmpne.s index 59a844a27dc29..ff7982e41df71 100644 --- a/llvm/test/MC/AArch64/SVE/cmpne.s +++ b/llvm/test/MC/AArch64/SVE/cmpne.s @@ -13,89 +13,89 @@ cmpne p0.b, p0/z, z0.b, z0.b // CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.b // CHECK-ENCODING: [0x10,0xa0,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 a0 00 24 cmpne p0.h, p0/z, z0.h, z0.h // CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.h // CHECK-ENCODING: [0x10,0xa0,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 a0 40 24 cmpne p0.s, p0/z, z0.s, z0.s // CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.s // CHECK-ENCODING: [0x10,0xa0,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 a0 80 24 cmpne p0.d, p0/z, z0.d, z0.d // CHECK-INST: cmpne p0.d, p0/z, z0.d, z0.d // CHECK-ENCODING: [0x10,0xa0,0xc0,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 a0 c0 24 cmpne p0.b, p0/z, z0.b, z0.d // CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.d // CHECK-ENCODING: [0x10,0x20,0x00,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 00 24 cmpne p0.h, p0/z, z0.h, z0.d // CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.d // CHECK-ENCODING: [0x10,0x20,0x40,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 40 24 cmpne p0.s, p0/z, z0.s, z0.d // CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.d // CHECK-ENCODING: [0x10,0x20,0x80,0x24] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 80 24 cmpne p0.b, p0/z, z0.b, #-16 // CHECK-INST: cmpne p0.b, p0/z, z0.b, #-16 // CHECK-ENCODING: [0x10,0x80,0x10,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 10 25 cmpne p0.h, p0/z, z0.h, #-16 // CHECK-INST: cmpne p0.h, p0/z, z0.h, #-16 // CHECK-ENCODING: [0x10,0x80,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 50 25 cmpne p0.s, p0/z, z0.s, #-16 // CHECK-INST: cmpne p0.s, p0/z, z0.s, #-16 // CHECK-ENCODING: [0x10,0x80,0x90,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 90 25 cmpne p0.d, p0/z, z0.d, #-16 // CHECK-INST: cmpne p0.d, p0/z, z0.d, #-16 // CHECK-ENCODING: [0x10,0x80,0xd0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 d0 25 cmpne p0.b, p0/z, z0.b, #15 // CHECK-INST: cmpne p0.b, p0/z, z0.b, #15 // CHECK-ENCODING: [0x10,0x80,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 0f 25 cmpne p0.h, p0/z, z0.h, #15 // CHECK-INST: cmpne p0.h, p0/z, z0.h, #15 // CHECK-ENCODING: [0x10,0x80,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 4f 25 cmpne p0.s, p0/z, z0.s, #15 // CHECK-INST: cmpne p0.s, p0/z, z0.s, #15 // CHECK-ENCODING: [0x10,0x80,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 8f 25 cmpne p0.d, p0/z, z0.d, #15 // CHECK-INST: cmpne p0.d, p0/z, z0.d, #15 // CHECK-ENCODING: [0x10,0x80,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 80 cf 25 diff --git a/llvm/test/MC/AArch64/SVE/cnot.s b/llvm/test/MC/AArch64/SVE/cnot.s index fbc1f12b30964..29d1c4021be1b 100644 --- a/llvm/test/MC/AArch64/SVE/cnot.s +++ b/llvm/test/MC/AArch64/SVE/cnot.s @@ -12,25 +12,25 @@ cnot z31.b, p7/m, z31.b // CHECK-INST: cnot z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x1b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 1b 04 cnot z31.h, p7/m, z31.h // CHECK-INST: cnot z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x5b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 5b 04 cnot z31.s, p7/m, z31.s // CHECK-INST: cnot z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x9b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 9b 04 cnot z31.d, p7/m, z31.d // CHECK-INST: cnot z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf db 04 @@ -40,23 +40,23 @@ cnot z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 cnot z4.d, p7/m, z31.d // CHECK-INST: cnot z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf db 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cnot z4.d, p7/m, z31.d // CHECK-INST: cnot z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf db 04 diff --git a/llvm/test/MC/AArch64/SVE/cnt.s b/llvm/test/MC/AArch64/SVE/cnt.s index f3b8b4b9b9bd3..c63436a1547e2 100644 --- a/llvm/test/MC/AArch64/SVE/cnt.s +++ b/llvm/test/MC/AArch64/SVE/cnt.s @@ -12,25 +12,25 @@ cnt z31.b, p7/m, z31.b // CHECK-INST: cnt z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x1a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 1a 04 cnt z31.h, p7/m, z31.h // CHECK-INST: cnt z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x5a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 5a 04 cnt z31.s, p7/m, z31.s // CHECK-INST: cnt z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x9a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 9a 04 cnt z31.d, p7/m, z31.d // CHECK-INST: cnt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf da 04 @@ -40,23 +40,23 @@ cnt z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 cnt z4.d, p7/m, z31.d // CHECK-INST: cnt z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf da 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cnt z4.d, p7/m, z31.d // CHECK-INST: cnt z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf da 04 diff --git a/llvm/test/MC/AArch64/SVE/cntb.s b/llvm/test/MC/AArch64/SVE/cntb.s index ea3b47618c048..f1575f09099f6 100644 --- a/llvm/test/MC/AArch64/SVE/cntb.s +++ b/llvm/test/MC/AArch64/SVE/cntb.s @@ -12,35 +12,35 @@ cntb x0 // CHECK-INST: cntb x0 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 20 04 cntb x0, all // CHECK-INST: cntb x0 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 20 04 cntb x0, all, mul #1 // CHECK-INST: cntb x0 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 20 04 cntb x0, all, mul #16 // CHECK-INST: cntb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 2f 04 cntb x0, pow2 // CHECK-INST: cntb x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 20 04 cntb x0, #28 // CHECK-INST: cntb x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 20 04 diff --git a/llvm/test/MC/AArch64/SVE/cntd.s b/llvm/test/MC/AArch64/SVE/cntd.s index 2e6004a98b33e..f06544ba9ffa6 100644 --- a/llvm/test/MC/AArch64/SVE/cntd.s +++ b/llvm/test/MC/AArch64/SVE/cntd.s @@ -12,35 +12,35 @@ cntd x0 // CHECK-INST: cntd x0 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 e0 04 cntd x0, all // CHECK-INST: cntd x0 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 e0 04 cntd x0, all, mul #1 // CHECK-INST: cntd x0 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 e0 04 cntd x0, all, mul #16 // CHECK-INST: cntd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 ef 04 cntd x0, pow2 // CHECK-INST: cntd x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 04 cntd x0, #28 // CHECK-INST: cntd x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 e0 04 diff --git a/llvm/test/MC/AArch64/SVE/cnth.s b/llvm/test/MC/AArch64/SVE/cnth.s index a6e058b340773..e2ed0e237720f 100644 --- a/llvm/test/MC/AArch64/SVE/cnth.s +++ b/llvm/test/MC/AArch64/SVE/cnth.s @@ -12,35 +12,35 @@ cnth x0 // CHECK-INST: cnth x0 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 60 04 cnth x0, all // CHECK-INST: cnth x0 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 60 04 cnth x0, all, mul #1 // CHECK-INST: cnth x0 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 60 04 cnth x0, all, mul #16 // CHECK-INST: cnth x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 6f 04 cnth x0, pow2 // CHECK-INST: cnth x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 04 cnth x0, #28 // CHECK-INST: cnth x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 60 04 diff --git a/llvm/test/MC/AArch64/SVE/cntp.s b/llvm/test/MC/AArch64/SVE/cntp.s index ac472838fc3f1..07abd09c3128c 100644 --- a/llvm/test/MC/AArch64/SVE/cntp.s +++ b/llvm/test/MC/AArch64/SVE/cntp.s @@ -12,23 +12,23 @@ cntp x0, p15, p0.b // CHECK-INST: cntp x0, p15, p0.b // CHECK-ENCODING: [0x00,0xbc,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 bc 20 25 cntp x0, p15, p0.h // CHECK-INST: cntp x0, p15, p0.h // CHECK-ENCODING: [0x00,0xbc,0x60,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 bc 60 25 cntp x0, p15, p0.s // CHECK-INST: cntp x0, p15, p0.s // CHECK-ENCODING: [0x00,0xbc,0xa0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 bc a0 25 cntp x0, p15, p0.d // CHECK-INST: cntp x0, p15, p0.d // CHECK-ENCODING: [0x00,0xbc,0xe0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 bc e0 25 diff --git a/llvm/test/MC/AArch64/SVE/cntw.s b/llvm/test/MC/AArch64/SVE/cntw.s index 851b2e1643da9..6a3d84e84b89e 100644 --- a/llvm/test/MC/AArch64/SVE/cntw.s +++ b/llvm/test/MC/AArch64/SVE/cntw.s @@ -12,35 +12,35 @@ cntw x0 // CHECK-INST: cntw x0 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 a0 04 cntw x0, all // CHECK-INST: cntw x0 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 a0 04 cntw x0, all, mul #1 // CHECK-INST: cntw x0 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 a0 04 cntw x0, all, mul #16 // CHECK-INST: cntw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 af 04 cntw x0, pow2 // CHECK-INST: cntw x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 04 cntw x0, #28 // CHECK-INST: cntw x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 a0 04 diff --git a/llvm/test/MC/AArch64/SVE/cpy.s b/llvm/test/MC/AArch64/SVE/cpy.s index 441e9466df964..a60ece8e188a3 100644 --- a/llvm/test/MC/AArch64/SVE/cpy.s +++ b/llvm/test/MC/AArch64/SVE/cpy.s @@ -12,223 +12,223 @@ cpy z0.b, p0/m, w0 // CHECK-INST: mov z0.b, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 28 05 cpy z0.h, p0/m, w0 // CHECK-INST: mov z0.h, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 68 05 cpy z0.s, p0/m, w0 // CHECK-INST: mov z0.s, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a8 05 cpy z0.d, p0/m, x0 // CHECK-INST: mov z0.d, p0/m, x0 // CHECK-ENCODING: [0x00,0xa0,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e8 05 cpy z31.b, p7/m, wsp // CHECK-INST: mov z31.b, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 28 05 cpy z31.h, p7/m, wsp // CHECK-INST: mov z31.h, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 68 05 cpy z31.s, p7/m, wsp // CHECK-INST: mov z31.s, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf a8 05 cpy z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 cpy z0.b, p0/m, b0 // CHECK-INST: mov z0.b, p0/m, b0 // CHECK-ENCODING: [0x00,0x80,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 20 05 cpy z31.b, p7/m, b31 // CHECK-INST: mov z31.b, p7/m, b31 // CHECK-ENCODING: [0xff,0x9f,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 20 05 cpy z0.h, p0/m, h0 // CHECK-INST: mov z0.h, p0/m, h0 // CHECK-ENCODING: [0x00,0x80,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 60 05 cpy z31.h, p7/m, h31 // CHECK-INST: mov z31.h, p7/m, h31 // CHECK-ENCODING: [0xff,0x9f,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 60 05 cpy z0.s, p0/m, s0 // CHECK-INST: mov z0.s, p0/m, s0 // CHECK-ENCODING: [0x00,0x80,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a0 05 cpy z31.s, p7/m, s31 // CHECK-INST: mov z31.s, p7/m, s31 // CHECK-ENCODING: [0xff,0x9f,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f a0 05 cpy z0.d, p0/m, d0 // CHECK-INST: mov z0.d, p0/m, d0 // CHECK-ENCODING: [0x00,0x80,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e0 05 cpy z31.d, p7/m, d31 // CHECK-INST: mov z31.d, p7/m, d31 // CHECK-ENCODING: [0xff,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f e0 05 cpy z5.b, p0/z, #-128 // CHECK-INST: mov z5.b, p0/z, #-128 // CHECK-ENCODING: [0x05,0x10,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 10 10 05 cpy z5.b, p0/z, #127 // CHECK-INST: mov z5.b, p0/z, #127 // CHECK-ENCODING: [0xe5,0x0f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 0f 10 05 cpy z5.b, p0/z, #255 // CHECK-INST: mov z5.b, p0/z, #-1 // CHECK-ENCODING: [0xe5,0x1f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 1f 10 05 cpy z21.h, p0/z, #-128 // CHECK-INST: mov z21.h, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 50 05 cpy z21.h, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.h, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 50 05 cpy z21.h, p0/z, #-32768 // CHECK-INST: mov z21.h, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 50 05 cpy z21.h, p0/z, #127 // CHECK-INST: mov z21.h, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f 50 05 cpy z21.h, p0/z, #127, lsl #8 // CHECK-INST: mov z21.h, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 50 05 cpy z21.h, p0/z, #32512 // CHECK-INST: mov z21.h, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 50 05 cpy z21.s, p0/z, #-128 // CHECK-INST: mov z21.s, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 90 05 cpy z21.s, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.s, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 90 05 cpy z21.s, p0/z, #-32768 // CHECK-INST: mov z21.s, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 90 05 cpy z21.s, p0/z, #127 // CHECK-INST: mov z21.s, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f 90 05 cpy z21.s, p0/z, #127, lsl #8 // CHECK-INST: mov z21.s, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 90 05 cpy z21.s, p0/z, #32512 // CHECK-INST: mov z21.s, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 90 05 cpy z21.d, p0/z, #-128 // CHECK-INST: mov z21.d, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 d0 05 cpy z21.d, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.d, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 d0 05 cpy z21.d, p0/z, #-32768 // CHECK-INST: mov z21.d, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 d0 05 cpy z21.d, p0/z, #127 // CHECK-INST: mov z21.d, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f d0 05 cpy z21.d, p0/z, #127, lsl #8 // CHECK-INST: mov z21.d, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f d0 05 cpy z21.d, p0/z, #32512 // CHECK-INST: mov z21.d, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f d0 05 // --------------------------------------------------------------------------// @@ -238,19 +238,19 @@ cpy z21.d, p0/z, #32512 cpy z0.b, p0/z, #-129 // CHECK-INST: mov z0.b, p0/z, #127 // CHECK-ENCODING: [0xe0,0x0f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 0f 10 05 cpy z0.h, p0/z, #-33024 // CHECK-INST: mov z0.h, p0/z, #32512 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 2f 50 05 cpy z0.h, p0/z, #-129, lsl #8 // CHECK-INST: mov z0.h, p0/z, #32512 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 2f 50 05 @@ -261,43 +261,43 @@ cpy z0.h, p0/z, #-129, lsl #8 cpy z5.b, p15/m, #-128 // CHECK-INST: mov z5.b, p15/m, #-128 // CHECK-ENCODING: [0x05,0x50,0x1f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 50 1f 05 cpy z21.h, p15/m, #-128 // CHECK-INST: mov z21.h, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0x5f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 5f 05 cpy z21.h, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.h, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0x5f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 5f 05 cpy z21.s, p15/m, #-128 // CHECK-INST: mov z21.s, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0x9f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 9f 05 cpy z21.s, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.s, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0x9f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 9f 05 cpy z21.d, p15/m, #-128 // CHECK-INST: mov z21.d, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 df 05 cpy z21.d, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 df 05 @@ -307,71 +307,71 @@ cpy z21.d, p15/m, #-128, lsl #8 movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 cpy z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 cpy z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 movprfx z21.d, p7/z, z28.d // CHECK-INST: movprfx z21.d, p7/z, z28.d // CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 3f d0 04 cpy z21.d, p7/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p7/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xd7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 d7 05 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 cpy z21.d, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 df 05 movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 cpy z4.d, p7/m, d31 // CHECK-INST: mov z4.d, p7/m, d31 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f e0 05 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cpy z4.d, p7/m, d31 // CHECK-INST: mov z4.d, p7/m, d31 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f e0 05 diff --git a/llvm/test/MC/AArch64/SVE/ctermeq.s b/llvm/test/MC/AArch64/SVE/ctermeq.s index f6a8650aa8836..a9da41cd58b77 100644 --- a/llvm/test/MC/AArch64/SVE/ctermeq.s +++ b/llvm/test/MC/AArch64/SVE/ctermeq.s @@ -12,23 +12,23 @@ ctermeq w30, wzr // CHECK-INST: ctermeq w30, wzr // CHECK-ENCODING: [0xc0,0x23,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 23 bf 25 ctermeq wzr, w30 // CHECK-INST: ctermeq wzr, w30 // CHECK-ENCODING: [0xe0,0x23,0xbe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 23 be 25 ctermeq x30, xzr // CHECK-INST: ctermeq x30, xzr // CHECK-ENCODING: [0xc0,0x23,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 23 ff 25 ctermeq xzr, x30 // CHECK-INST: ctermeq xzr, x30 // CHECK-ENCODING: [0xe0,0x23,0xfe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 23 fe 25 diff --git a/llvm/test/MC/AArch64/SVE/ctermne.s b/llvm/test/MC/AArch64/SVE/ctermne.s index 2f302b50cfa4d..35092ead6a8ec 100644 --- a/llvm/test/MC/AArch64/SVE/ctermne.s +++ b/llvm/test/MC/AArch64/SVE/ctermne.s @@ -12,23 +12,23 @@ ctermne w30, wzr // CHECK-INST: ctermne w30, wzr // CHECK-ENCODING: [0xd0,0x23,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: d0 23 bf 25 ctermne wzr, w30 // CHECK-INST: ctermne wzr, w30 // CHECK-ENCODING: [0xf0,0x23,0xbe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f0 23 be 25 ctermne x30, xzr // CHECK-INST: ctermne x30, xzr // CHECK-ENCODING: [0xd0,0x23,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: d0 23 ff 25 ctermne xzr, x30 // CHECK-INST: ctermne xzr, x30 // CHECK-ENCODING: [0xf0,0x23,0xfe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f0 23 fe 25 diff --git a/llvm/test/MC/AArch64/SVE/decb.s b/llvm/test/MC/AArch64/SVE/decb.s index 71f9f6a39db18..02d12bb4f8b8e 100644 --- a/llvm/test/MC/AArch64/SVE/decb.s +++ b/llvm/test/MC/AArch64/SVE/decb.s @@ -12,119 +12,119 @@ decb x0 // CHECK-INST: decb x0 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 30 04 decb x0, all // CHECK-INST: decb x0 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 30 04 decb x0, all, mul #1 // CHECK-INST: decb x0 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 30 04 decb x0, all, mul #16 // CHECK-INST: decb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe7,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 3f 04 decb x0, pow2 // CHECK-INST: decb x0, pow2 // CHECK-ENCODING: [0x00,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e4 30 04 decb x0, vl1 // CHECK-INST: decb x0, vl1 // CHECK-ENCODING: [0x20,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e4 30 04 decb x0, vl2 // CHECK-INST: decb x0, vl2 // CHECK-ENCODING: [0x40,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e4 30 04 decb x0, vl3 // CHECK-INST: decb x0, vl3 // CHECK-ENCODING: [0x60,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e4 30 04 decb x0, vl4 // CHECK-INST: decb x0, vl4 // CHECK-ENCODING: [0x80,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e4 30 04 decb x0, vl5 // CHECK-INST: decb x0, vl5 // CHECK-ENCODING: [0xa0,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e4 30 04 decb x0, vl6 // CHECK-INST: decb x0, vl6 // CHECK-ENCODING: [0xc0,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e4 30 04 decb x0, vl7 // CHECK-INST: decb x0, vl7 // CHECK-ENCODING: [0xe0,0xe4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e4 30 04 decb x0, vl8 // CHECK-INST: decb x0, vl8 // CHECK-ENCODING: [0x00,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e5 30 04 decb x0, vl16 // CHECK-INST: decb x0, vl16 // CHECK-ENCODING: [0x20,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e5 30 04 decb x0, vl32 // CHECK-INST: decb x0, vl32 // CHECK-ENCODING: [0x40,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e5 30 04 decb x0, vl64 // CHECK-INST: decb x0, vl64 // CHECK-ENCODING: [0x60,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e5 30 04 decb x0, vl128 // CHECK-INST: decb x0, vl128 // CHECK-ENCODING: [0x80,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e5 30 04 decb x0, vl256 // CHECK-INST: decb x0, vl256 // CHECK-ENCODING: [0xa0,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e5 30 04 decb x0, #14 // CHECK-INST: decb x0, #14 // CHECK-ENCODING: [0xc0,0xe5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e5 30 04 decb x0, #28 // CHECK-INST: decb x0, #28 // CHECK-ENCODING: [0x80,0xe7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e7 30 04 diff --git a/llvm/test/MC/AArch64/SVE/decd.s b/llvm/test/MC/AArch64/SVE/decd.s index 38b53f92d56c5..6a1a2cd2c89e6 100644 --- a/llvm/test/MC/AArch64/SVE/decd.s +++ b/llvm/test/MC/AArch64/SVE/decd.s @@ -12,119 +12,119 @@ decd x0 // CHECK-INST: decd x0 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 f0 04 decd x0, all // CHECK-INST: decd x0 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 f0 04 decd x0, all, mul #1 // CHECK-INST: decd x0 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 f0 04 decd x0, all, mul #16 // CHECK-INST: decd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe7,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 ff 04 decd x0, pow2 // CHECK-INST: decd x0, pow2 // CHECK-ENCODING: [0x00,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e4 f0 04 decd x0, vl1 // CHECK-INST: decd x0, vl1 // CHECK-ENCODING: [0x20,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e4 f0 04 decd x0, vl2 // CHECK-INST: decd x0, vl2 // CHECK-ENCODING: [0x40,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e4 f0 04 decd x0, vl3 // CHECK-INST: decd x0, vl3 // CHECK-ENCODING: [0x60,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e4 f0 04 decd x0, vl4 // CHECK-INST: decd x0, vl4 // CHECK-ENCODING: [0x80,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e4 f0 04 decd x0, vl5 // CHECK-INST: decd x0, vl5 // CHECK-ENCODING: [0xa0,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e4 f0 04 decd x0, vl6 // CHECK-INST: decd x0, vl6 // CHECK-ENCODING: [0xc0,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e4 f0 04 decd x0, vl7 // CHECK-INST: decd x0, vl7 // CHECK-ENCODING: [0xe0,0xe4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e4 f0 04 decd x0, vl8 // CHECK-INST: decd x0, vl8 // CHECK-ENCODING: [0x00,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e5 f0 04 decd x0, vl16 // CHECK-INST: decd x0, vl16 // CHECK-ENCODING: [0x20,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e5 f0 04 decd x0, vl32 // CHECK-INST: decd x0, vl32 // CHECK-ENCODING: [0x40,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e5 f0 04 decd x0, vl64 // CHECK-INST: decd x0, vl64 // CHECK-ENCODING: [0x60,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e5 f0 04 decd x0, vl128 // CHECK-INST: decd x0, vl128 // CHECK-ENCODING: [0x80,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e5 f0 04 decd x0, vl256 // CHECK-INST: decd x0, vl256 // CHECK-ENCODING: [0xa0,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e5 f0 04 decd x0, #14 // CHECK-INST: decd x0, #14 // CHECK-ENCODING: [0xc0,0xe5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e5 f0 04 decd x0, #28 // CHECK-INST: decd x0, #28 // CHECK-ENCODING: [0x80,0xe7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e7 f0 04 diff --git a/llvm/test/MC/AArch64/SVE/dech.s b/llvm/test/MC/AArch64/SVE/dech.s index 89608699e4d71..f89ad118f525b 100644 --- a/llvm/test/MC/AArch64/SVE/dech.s +++ b/llvm/test/MC/AArch64/SVE/dech.s @@ -12,119 +12,119 @@ dech x0 // CHECK-INST: dech x0 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 70 04 dech x0, all // CHECK-INST: dech x0 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 70 04 dech x0, all, mul #1 // CHECK-INST: dech x0 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 70 04 dech x0, all, mul #16 // CHECK-INST: dech x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe7,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 7f 04 dech x0, pow2 // CHECK-INST: dech x0, pow2 // CHECK-ENCODING: [0x00,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e4 70 04 dech x0, vl1 // CHECK-INST: dech x0, vl1 // CHECK-ENCODING: [0x20,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e4 70 04 dech x0, vl2 // CHECK-INST: dech x0, vl2 // CHECK-ENCODING: [0x40,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e4 70 04 dech x0, vl3 // CHECK-INST: dech x0, vl3 // CHECK-ENCODING: [0x60,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e4 70 04 dech x0, vl4 // CHECK-INST: dech x0, vl4 // CHECK-ENCODING: [0x80,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e4 70 04 dech x0, vl5 // CHECK-INST: dech x0, vl5 // CHECK-ENCODING: [0xa0,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e4 70 04 dech x0, vl6 // CHECK-INST: dech x0, vl6 // CHECK-ENCODING: [0xc0,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e4 70 04 dech x0, vl7 // CHECK-INST: dech x0, vl7 // CHECK-ENCODING: [0xe0,0xe4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e4 70 04 dech x0, vl8 // CHECK-INST: dech x0, vl8 // CHECK-ENCODING: [0x00,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e5 70 04 dech x0, vl16 // CHECK-INST: dech x0, vl16 // CHECK-ENCODING: [0x20,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e5 70 04 dech x0, vl32 // CHECK-INST: dech x0, vl32 // CHECK-ENCODING: [0x40,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e5 70 04 dech x0, vl64 // CHECK-INST: dech x0, vl64 // CHECK-ENCODING: [0x60,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e5 70 04 dech x0, vl128 // CHECK-INST: dech x0, vl128 // CHECK-ENCODING: [0x80,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e5 70 04 dech x0, vl256 // CHECK-INST: dech x0, vl256 // CHECK-ENCODING: [0xa0,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e5 70 04 dech x0, #14 // CHECK-INST: dech x0, #14 // CHECK-ENCODING: [0xc0,0xe5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e5 70 04 dech x0, #28 // CHECK-INST: dech x0, #28 // CHECK-ENCODING: [0x80,0xe7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e7 70 04 diff --git a/llvm/test/MC/AArch64/SVE/decp.s b/llvm/test/MC/AArch64/SVE/decp.s index e9466cfc789b0..bae5fabbd351f 100644 --- a/llvm/test/MC/AArch64/SVE/decp.s +++ b/llvm/test/MC/AArch64/SVE/decp.s @@ -12,85 +12,85 @@ decp x0, p0.b // CHECK-INST: decp x0, p0.b // CHECK-ENCODING: [0x00,0x88,0x2d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 2d 25 decp x0, p0.h // CHECK-INST: decp x0, p0.h // CHECK-ENCODING: [0x00,0x88,0x6d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 6d 25 decp x0, p0.s // CHECK-INST: decp x0, p0.s // CHECK-ENCODING: [0x00,0x88,0xad,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 ad 25 decp x0, p0.d // CHECK-INST: decp x0, p0.d // CHECK-ENCODING: [0x00,0x88,0xed,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 ed 25 decp xzr, p15.b // CHECK-INST: decp xzr, p15.b // CHECK-ENCODING: [0xff,0x89,0x2d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 2d 25 decp xzr, p15.h // CHECK-INST: decp xzr, p15.h // CHECK-ENCODING: [0xff,0x89,0x6d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 6d 25 decp xzr, p15.s // CHECK-INST: decp xzr, p15.s // CHECK-ENCODING: [0xff,0x89,0xad,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ad 25 decp xzr, p15.d // CHECK-INST: decp xzr, p15.d // CHECK-ENCODING: [0xff,0x89,0xed,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ed 25 decp z31.h, p15 // CHECK-INST: decp z31.h, p15.h // CHECK-ENCODING: [0xff,0x81,0x6d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 6d 25 decp z31.h, p15.h // CHECK-INST: decp z31.h, p15.h // CHECK-ENCODING: [0xff,0x81,0x6d,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 6d 25 decp z31.s, p15 // CHECK-INST: decp z31.s, p15.s // CHECK-ENCODING: [0xff,0x81,0xad,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ad 25 decp z31.s, p15.s // CHECK-INST: decp z31.s, p15.s // CHECK-ENCODING: [0xff,0x81,0xad,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ad 25 decp z31.d, p15 // CHECK-INST: decp z31.d, p15.d // CHECK-ENCODING: [0xff,0x81,0xed,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ed 25 decp z31.d, p15.d // CHECK-INST: decp z31.d, p15.d // CHECK-ENCODING: [0xff,0x81,0xed,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ed 25 @@ -100,11 +100,11 @@ decp z31.d, p15.d movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 decp z31.d, p15.d // CHECK-INST: decp z31.d, p15 // CHECK-ENCODING: [0xff,0x81,0xed,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ed 25 diff --git a/llvm/test/MC/AArch64/SVE/decw.s b/llvm/test/MC/AArch64/SVE/decw.s index 2ad72fc6dd102..d064c39193b59 100644 --- a/llvm/test/MC/AArch64/SVE/decw.s +++ b/llvm/test/MC/AArch64/SVE/decw.s @@ -12,119 +12,119 @@ decw x0 // CHECK-INST: decw x0 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 b0 04 decw x0, all // CHECK-INST: decw x0 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 b0 04 decw x0, all, mul #1 // CHECK-INST: decw x0 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 b0 04 decw x0, all, mul #16 // CHECK-INST: decw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe7,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e7 bf 04 decw x0, pow2 // CHECK-INST: decw x0, pow2 // CHECK-ENCODING: [0x00,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e4 b0 04 decw x0, vl1 // CHECK-INST: decw x0, vl1 // CHECK-ENCODING: [0x20,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e4 b0 04 decw x0, vl2 // CHECK-INST: decw x0, vl2 // CHECK-ENCODING: [0x40,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e4 b0 04 decw x0, vl3 // CHECK-INST: decw x0, vl3 // CHECK-ENCODING: [0x60,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e4 b0 04 decw x0, vl4 // CHECK-INST: decw x0, vl4 // CHECK-ENCODING: [0x80,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e4 b0 04 decw x0, vl5 // CHECK-INST: decw x0, vl5 // CHECK-ENCODING: [0xa0,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e4 b0 04 decw x0, vl6 // CHECK-INST: decw x0, vl6 // CHECK-ENCODING: [0xc0,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e4 b0 04 decw x0, vl7 // CHECK-INST: decw x0, vl7 // CHECK-ENCODING: [0xe0,0xe4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e4 b0 04 decw x0, vl8 // CHECK-INST: decw x0, vl8 // CHECK-ENCODING: [0x00,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e5 b0 04 decw x0, vl16 // CHECK-INST: decw x0, vl16 // CHECK-ENCODING: [0x20,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e5 b0 04 decw x0, vl32 // CHECK-INST: decw x0, vl32 // CHECK-ENCODING: [0x40,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e5 b0 04 decw x0, vl64 // CHECK-INST: decw x0, vl64 // CHECK-ENCODING: [0x60,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e5 b0 04 decw x0, vl128 // CHECK-INST: decw x0, vl128 // CHECK-ENCODING: [0x80,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e5 b0 04 decw x0, vl256 // CHECK-INST: decw x0, vl256 // CHECK-ENCODING: [0xa0,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e5 b0 04 decw x0, #14 // CHECK-INST: decw x0, #14 // CHECK-ENCODING: [0xc0,0xe5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e5 b0 04 decw x0, #28 // CHECK-INST: decw x0, #28 // CHECK-ENCODING: [0x80,0xe7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e7 b0 04 diff --git a/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s index 1aa8f91c1374d..661f13974d0bc 100644 --- a/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s +++ b/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s @@ -3,5 +3,5 @@ .arch_extension nosve ptrue p0.b, pow2 -// CHECK: error: instruction requires: streaming-sve or sve +// CHECK: error: instruction requires: sve or sme // CHECK-NEXT: ptrue p0.b, pow2 diff --git a/llvm/test/MC/AArch64/SVE/dup.s b/llvm/test/MC/AArch64/SVE/dup.s index 48bdda3e27e03..dd7077e9d7907 100644 --- a/llvm/test/MC/AArch64/SVE/dup.s +++ b/llvm/test/MC/AArch64/SVE/dup.s @@ -12,235 +12,235 @@ dup z0.b, w0 // CHECK-INST: mov z0.b, w0 // CHECK-ENCODING: [0x00,0x38,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 20 05 dup z0.h, w0 // CHECK-INST: mov z0.h, w0 // CHECK-ENCODING: [0x00,0x38,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 60 05 dup z0.s, w0 // CHECK-INST: mov z0.s, w0 // CHECK-ENCODING: [0x00,0x38,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 a0 05 dup z0.d, x0 // CHECK-INST: mov z0.d, x0 // CHECK-ENCODING: [0x00,0x38,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 e0 05 dup z31.h, wsp // CHECK-INST: mov z31.h, wsp // CHECK-ENCODING: [0xff,0x3b,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 60 05 dup z31.s, wsp // CHECK-INST: mov z31.s, wsp // CHECK-ENCODING: [0xff,0x3b,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b a0 05 dup z31.d, sp // CHECK-INST: mov z31.d, sp // CHECK-ENCODING: [0xff,0x3b,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b e0 05 dup z31.b, wsp // CHECK-INST: mov z31.b, wsp // CHECK-ENCODING: [0xff,0x3b,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 20 05 dup z5.b, #-128 // CHECK-INST: mov z5.b, #-128 // CHECK-ENCODING: [0x05,0xd0,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 d0 38 25 dup z5.b, #127 // CHECK-INST: mov z5.b, #127 // CHECK-ENCODING: [0xe5,0xcf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 cf 38 25 dup z5.b, #255 // CHECK-INST: mov z5.b, #-1 // CHECK-ENCODING: [0xe5,0xdf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 df 38 25 dup z21.h, #-128 // CHECK-INST: mov z21.h, #-128 // CHECK-ENCODING: [0x15,0xd0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 78 25 dup z21.h, #-128, lsl #8 // CHECK-INST: mov z21.h, #-32768 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 78 25 dup z21.h, #-32768 // CHECK-INST: mov z21.h, #-32768 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 78 25 dup z21.h, #127 // CHECK-INST: mov z21.h, #127 // CHECK-ENCODING: [0xf5,0xcf,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf 78 25 dup z21.h, #127, lsl #8 // CHECK-INST: mov z21.h, #32512 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef 78 25 dup z21.h, #32512 // CHECK-INST: mov z21.h, #32512 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef 78 25 dup z21.s, #-128 // CHECK-INST: mov z21.s, #-128 // CHECK-ENCODING: [0x15,0xd0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 b8 25 dup z21.s, #-128, lsl #8 // CHECK-INST: mov z21.s, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 b8 25 dup z21.s, #-32768 // CHECK-INST: mov z21.s, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 b8 25 dup z21.s, #127 // CHECK-INST: mov z21.s, #127 // CHECK-ENCODING: [0xf5,0xcf,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf b8 25 dup z21.s, #127, lsl #8 // CHECK-INST: mov z21.s, #32512 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef b8 25 dup z21.s, #32512 // CHECK-INST: mov z21.s, #32512 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef b8 25 dup z21.d, #-128 // CHECK-INST: mov z21.d, #-128 // CHECK-ENCODING: [0x15,0xd0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 f8 25 dup z21.d, #-128, lsl #8 // CHECK-INST: mov z21.d, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 f8 25 dup z21.d, #-32768 // CHECK-INST: mov z21.d, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 f8 25 dup z21.d, #127 // CHECK-INST: mov z21.d, #127 // CHECK-ENCODING: [0xf5,0xcf,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf f8 25 dup z21.d, #127, lsl #8 // CHECK-INST: mov z21.d, #32512 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef f8 25 dup z21.d, #32512 // CHECK-INST: mov z21.d, #32512 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef f8 25 dup z0.b, z0.b[0] // CHECK-INST: mov z0.b, b0 // CHECK-ENCODING: [0x00,0x20,0x21,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 21 05 dup z0.h, z0.h[0] // CHECK-INST: mov z0.h, h0 // CHECK-ENCODING: [0x00,0x20,0x22,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 22 05 dup z0.s, z0.s[0] // CHECK-INST: mov z0.s, s0 // CHECK-ENCODING: [0x00,0x20,0x24,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 24 05 dup z0.d, z0.d[0] // CHECK-INST: mov z0.d, d0 // CHECK-ENCODING: [0x00,0x20,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 28 05 dup z0.q, z0.q[0] // CHECK-INST: mov z0.q, q0 // CHECK-ENCODING: [0x00,0x20,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 30 05 dup z31.b, z31.b[63] // CHECK-INST: mov z31.b, z31.b[63] // CHECK-ENCODING: [0xff,0x23,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 ff 05 dup z31.h, z31.h[31] // CHECK-INST: mov z31.h, z31.h[31] // CHECK-ENCODING: [0xff,0x23,0xfe,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 fe 05 dup z31.s, z31.s[15] // CHECK-INST: mov z31.s, z31.s[15] // CHECK-ENCODING: [0xff,0x23,0xfc,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 fc 05 dup z31.d, z31.d[7] // CHECK-INST: mov z31.d, z31.d[7] // CHECK-ENCODING: [0xff,0x23,0xf8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 f8 05 dup z5.q, z17.q[3] // CHECK-INST: mov z5.q, z17.q[3] // CHECK-ENCODING: [0x25,0x22,0xf0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 22 f0 05 // --------------------------------------------------------------------------// @@ -250,17 +250,17 @@ dup z5.q, z17.q[3] dup z0.b, #-129 // CHECK-INST: mov z0.b, #127 // CHECK-ENCODING: [0xe0,0xcf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 38 25 dup z0.h, #-33024 // CHECK-INST: mov z0.h, #32512 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ef 78 25 dup z0.h, #-129, lsl #8 // CHECK-INST: mov z0.h, #32512 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ef 78 25 diff --git a/llvm/test/MC/AArch64/SVE/dupm.s b/llvm/test/MC/AArch64/SVE/dupm.s index 9f0b863075cad..ad4678ff656f0 100644 --- a/llvm/test/MC/AArch64/SVE/dupm.s +++ b/llvm/test/MC/AArch64/SVE/dupm.s @@ -12,59 +12,59 @@ dupm z5.b, #0xf9 // CHECK-INST: dupm z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e c0 05 dupm z5.h, #0xf9f9 // CHECK-INST: dupm z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e c0 05 dupm z5.s, #0xf9f9f9f9 // CHECK-INST: dupm z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e c0 05 dupm z5.d, #0xf9f9f9f9f9f9f9f9 // CHECK-INST: dupm z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e c0 05 dupm z23.h, #0xfff9 // CHECK-INST: dupm z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d c0 05 dupm z23.s, #0xfff9fff9 // CHECK-INST: dupm z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d c0 05 dupm z23.d, #0xfff9fff9fff9fff9 // CHECK-INST: dupm z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d c0 05 dupm z0.s, #0xfffffff9 // CHECK-INST: dupm z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb c0 05 dupm z0.d, #0xfffffff9fffffff9 // CHECK-INST: dupm z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb c0 05 dupm z0.d, #0xfffffffffffffff9 // CHECK-INST: dupm z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0xc3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef c3 05 diff --git a/llvm/test/MC/AArch64/SVE/eon.s b/llvm/test/MC/AArch64/SVE/eon.s index d2583b1a13388..cf66bb6deacd9 100644 --- a/llvm/test/MC/AArch64/SVE/eon.s +++ b/llvm/test/MC/AArch64/SVE/eon.s @@ -12,49 +12,49 @@ eon z5.b, z5.b, #0xf9 // CHECK-INST: eor z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 40 05 eon z23.h, z23.h, #0xfff9 // CHECK-INST: eor z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 40 05 eon z0.s, z0.s, #0xfffffff9 // CHECK-INST: eor z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 40 05 eon z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: eor z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 43 05 eon z5.b, z5.b, #0x6 // CHECK-INST: eor z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 40 05 eon z23.h, z23.h, #0x6 // CHECK-INST: eor z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 40 05 eon z0.s, z0.s, #0x6 // CHECK-INST: eor z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 40 05 eon z0.d, z0.d, #0x6 // CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 43 05 @@ -64,11 +64,11 @@ eon z0.d, z0.d, #0x6 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 eon z0.d, z0.d, #0x6 // CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 43 05 diff --git a/llvm/test/MC/AArch64/SVE/eor.s b/llvm/test/MC/AArch64/SVE/eor.s index 861799660d4ee..5b38312b84fdc 100644 --- a/llvm/test/MC/AArch64/SVE/eor.s +++ b/llvm/test/MC/AArch64/SVE/eor.s @@ -12,103 +12,103 @@ eor z5.b, z5.b, #0xf9 // CHECK-INST: eor z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 40 05 eor z23.h, z23.h, #0xfff9 // CHECK-INST: eor z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 40 05 eor z0.s, z0.s, #0xfffffff9 // CHECK-INST: eor z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 40 05 eor z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 43 05 eor z5.b, z5.b, #0x6 // CHECK-INST: eor z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 40 05 eor z23.h, z23.h, #0x6 // CHECK-INST: eor z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 40 05 eor z0.s, z0.s, #0x6 // CHECK-INST: eor z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x40,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 40 05 eor z0.d, z0.d, #0x6 // CHECK-INST: eor z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 43 05 eor z23.d, z13.d, z8.d // CHECK-INST: eor z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0xa8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 a8 04 eor z0.d, z0.d, z0.d // CHECK-INST: eor z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 a0 04 eor z31.s, p7/m, z31.s, z31.s // CHECK-INST: eor z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 99 04 eor z31.h, p7/m, z31.h, z31.h // CHECK-INST: eor z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x59,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 59 04 eor z31.d, p7/m, z31.d, z31.d // CHECK-INST: eor z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xd9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f d9 04 eor z31.b, p7/m, z31.b, z31.b // CHECK-INST: eor z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 19 04 eor p0.b, p0/z, p0.b, p1.b // CHECK-INST: eor p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x42,0x01,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 01 25 eor p0.b, p0/z, p0.b, p0.b // CHECK-INST: not p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x42,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 00 25 eor p15.b, p15/z, p15.b, p15.b // CHECK-INST: not p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f 0f 25 @@ -118,19 +118,19 @@ eor p15.b, p15/z, p15.b, p15.b eor z0.s, z0.s, z0.s // CHECK-INST: eor z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 a0 04 eor z0.h, z0.h, z0.h // CHECK-INST: eor z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 a0 04 eor z0.b, z0.b, z0.b // CHECK-INST: eor z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 a0 04 @@ -140,35 +140,35 @@ eor z0.b, z0.b, z0.b movprfx z4.b, p7/z, z6.b // CHECK-INST: movprfx z4.b, p7/z, z6.b // CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 10 04 eor z4.b, p7/m, z4.b, z31.b // CHECK-INST: eor z4.b, p7/m, z4.b, z31.b // CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f 19 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 eor z4.b, p7/m, z4.b, z31.b // CHECK-INST: eor z4.b, p7/m, z4.b, z31.b // CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f 19 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 eor z0.d, z0.d, #0x6 // CHECK-INST: eor z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 43 05 diff --git a/llvm/test/MC/AArch64/SVE/eors.s b/llvm/test/MC/AArch64/SVE/eors.s index b48369c67450a..4ec189c867bc8 100644 --- a/llvm/test/MC/AArch64/SVE/eors.s +++ b/llvm/test/MC/AArch64/SVE/eors.s @@ -12,17 +12,17 @@ eors p0.b, p0/z, p0.b, p1.b // CHECK-INST: eors p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x42,0x41,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 41 25 eors p0.b, p0/z, p0.b, p0.b // CHECK-INST: nots p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x42,0x40,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 40 25 eors p15.b, p15/z, p15.b, p15.b // CHECK-INST: nots p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/eorv.s b/llvm/test/MC/AArch64/SVE/eorv.s index eddd66b25b41e..3a85be1bdf67b 100644 --- a/llvm/test/MC/AArch64/SVE/eorv.s +++ b/llvm/test/MC/AArch64/SVE/eorv.s @@ -12,23 +12,23 @@ eorv b0, p7, z31.b // CHECK-INST: eorv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 19 04 eorv h0, p7, z31.h // CHECK-INST: eorv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x59,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 59 04 eorv s0, p7, z31.s // CHECK-INST: eorv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 99 04 eorv d0, p7, z31.d // CHECK-INST: eorv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xd9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f d9 04 diff --git a/llvm/test/MC/AArch64/SVE/ext.s b/llvm/test/MC/AArch64/SVE/ext.s index 301c2db24f84e..733e5ee8ca7bd 100644 --- a/llvm/test/MC/AArch64/SVE/ext.s +++ b/llvm/test/MC/AArch64/SVE/ext.s @@ -12,13 +12,13 @@ ext z31.b, z31.b, z0.b, #0 // CHECK-INST: ext z31.b, z31.b, z0.b, #0 // CHECK-ENCODING: [0x1f,0x00,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 00 20 05 ext z31.b, z31.b, z0.b, #255 // CHECK-INST: ext z31.b, z31.b, z0.b, #255 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c 3f 05 @@ -28,11 +28,11 @@ ext z31.b, z31.b, z0.b, #255 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 ext z31.b, z31.b, z0.b, #255 // CHECK-INST: ext z31.b, z31.b, z0.b, #255 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c 3f 05 diff --git a/llvm/test/MC/AArch64/SVE/fabd.s b/llvm/test/MC/AArch64/SVE/fabd.s index 5656354e19c22..d215cc4542e5c 100644 --- a/llvm/test/MC/AArch64/SVE/fabd.s +++ b/llvm/test/MC/AArch64/SVE/fabd.s @@ -12,19 +12,19 @@ fabd z0.h, p7/m, z0.h, z31.h // CHECK-INST: fabd z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x48,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 48 65 fabd z0.s, p7/m, z0.s, z31.s // CHECK-INST: fabd z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x88,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 88 65 fabd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c8 65 @@ -34,23 +34,23 @@ fabd z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fabd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c8 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fabd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c8 65 diff --git a/llvm/test/MC/AArch64/SVE/fabs.s b/llvm/test/MC/AArch64/SVE/fabs.s index 7c3e9595049aa..c83db482d5377 100644 --- a/llvm/test/MC/AArch64/SVE/fabs.s +++ b/llvm/test/MC/AArch64/SVE/fabs.s @@ -12,19 +12,19 @@ fabs z31.h, p7/m, z31.h // CHECK-INST: fabs z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x5c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 5c 04 fabs z31.s, p7/m, z31.s // CHECK-INST: fabs z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x9c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 9c 04 fabs z31.d, p7/m, z31.d // CHECK-INST: fabs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf dc 04 @@ -34,23 +34,23 @@ fabs z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 fabs z4.d, p7/m, z31.d // CHECK-INST: fabs z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf dc 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 fabs z4.d, p7/m, z31.d // CHECK-INST: fabs z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf dc 04 diff --git a/llvm/test/MC/AArch64/SVE/facge.s b/llvm/test/MC/AArch64/SVE/facge.s index 79cc24b353b10..e08deb567b3e5 100644 --- a/llvm/test/MC/AArch64/SVE/facge.s +++ b/llvm/test/MC/AArch64/SVE/facge.s @@ -12,17 +12,17 @@ facge p0.h, p0/z, z0.h, z1.h // CHECK-INST: facge p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x10,0xc0,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 41 65 facge p0.s, p0/z, z0.s, z1.s // CHECK-INST: facge p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x10,0xc0,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 81 65 facge p0.d, p0/z, z0.d, z1.d // CHECK-INST: facge p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x10,0xc0,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 c0 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/facgt.s b/llvm/test/MC/AArch64/SVE/facgt.s index 4021d3c968f26..4c2a01bbf6140 100644 --- a/llvm/test/MC/AArch64/SVE/facgt.s +++ b/llvm/test/MC/AArch64/SVE/facgt.s @@ -12,17 +12,17 @@ facgt p0.h, p0/z, z0.h, z1.h // CHECK-INST: facgt p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x10,0xe0,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 41 65 facgt p0.s, p0/z, z0.s, z1.s // CHECK-INST: facgt p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x10,0xe0,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 81 65 facgt p0.d, p0/z, z0.d, z1.d // CHECK-INST: facgt p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x10,0xe0,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 e0 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/facle.s b/llvm/test/MC/AArch64/SVE/facle.s index 0a4a2eb34b6bb..a1b1340caf9a3 100644 --- a/llvm/test/MC/AArch64/SVE/facle.s +++ b/llvm/test/MC/AArch64/SVE/facle.s @@ -12,17 +12,17 @@ facle p0.h, p0/z, z0.h, z1.h // CHECK-INST: facge p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x30,0xc0,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 c0 40 65 facle p0.s, p0/z, z0.s, z1.s // CHECK-INST: facge p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x30,0xc0,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 c0 80 65 facle p0.d, p0/z, z0.d, z1.d // CHECK-INST: facge p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x30,0xc0,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 c0 c0 65 diff --git a/llvm/test/MC/AArch64/SVE/faclt.s b/llvm/test/MC/AArch64/SVE/faclt.s index de620adfa9bef..7ba7e2cea9237 100644 --- a/llvm/test/MC/AArch64/SVE/faclt.s +++ b/llvm/test/MC/AArch64/SVE/faclt.s @@ -12,17 +12,17 @@ faclt p0.h, p0/z, z0.h, z1.h // CHECK-INST: facgt p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x30,0xe0,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 e0 40 65 faclt p0.s, p0/z, z0.s, z1.s // CHECK-INST: facgt p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x30,0xe0,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 e0 80 65 faclt p0.d, p0/z, z0.d, z1.d // CHECK-INST: facgt p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x30,0xe0,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 e0 c0 65 diff --git a/llvm/test/MC/AArch64/SVE/fadd.s b/llvm/test/MC/AArch64/SVE/fadd.s index fecf763f0c24f..e44e4e9bf25fb 100644 --- a/llvm/test/MC/AArch64/SVE/fadd.s +++ b/llvm/test/MC/AArch64/SVE/fadd.s @@ -12,85 +12,85 @@ fadd z0.h, p0/m, z0.h, #0.500000000000000 // CHECK-INST: fadd z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x58,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 58 65 fadd z0.h, p0/m, z0.h, #0.5 // CHECK-INST: fadd z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x58,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 58 65 fadd z0.s, p0/m, z0.s, #0.5 // CHECK-INST: fadd z0.s, p0/m, z0.s, #0.5 // CHECK-ENCODING: [0x00,0x80,0x98,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 98 65 fadd z0.d, p0/m, z0.d, #0.5 // CHECK-INST: fadd z0.d, p0/m, z0.d, #0.5 // CHECK-ENCODING: [0x00,0x80,0xd8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d8 65 fadd z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fadd z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x58,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 58 65 fadd z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fadd z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x58,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 58 65 fadd z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fadd z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x98,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 98 65 fadd z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d8 65 fadd z0.h, p7/m, z0.h, z31.h // CHECK-INST: fadd z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 40 65 fadd z0.s, p7/m, z0.s, z31.s // CHECK-INST: fadd z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 80 65 fadd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c0 65 fadd z0.h, z1.h, z31.h // CHECK-INST: fadd z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x00,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 5f 65 fadd z0.s, z1.s, z31.s // CHECK-INST: fadd z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x00,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 9f 65 fadd z0.d, z1.d, z31.d // CHECK-INST: fadd z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x00,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 df 65 @@ -100,47 +100,47 @@ fadd z0.d, z1.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fadd z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d8 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fadd z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d8 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fadd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c0 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fadd z0.d, p7/m, z0.d, z31.d // CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c0 65 diff --git a/llvm/test/MC/AArch64/SVE/faddv.s b/llvm/test/MC/AArch64/SVE/faddv.s index 98c47ba5a87a4..9a6056d91889e 100644 --- a/llvm/test/MC/AArch64/SVE/faddv.s +++ b/llvm/test/MC/AArch64/SVE/faddv.s @@ -12,17 +12,17 @@ faddv h0, p7, z31.h // CHECK-INST: faddv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 40 65 faddv s0, p7, z31.s // CHECK-INST: faddv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 80 65 faddv d0, p7, z31.d // CHECK-INST: faddv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c0 65 diff --git a/llvm/test/MC/AArch64/SVE/fcadd.s b/llvm/test/MC/AArch64/SVE/fcadd.s index e904453ef8c48..d10888de89956 100644 --- a/llvm/test/MC/AArch64/SVE/fcadd.s +++ b/llvm/test/MC/AArch64/SVE/fcadd.s @@ -12,37 +12,37 @@ fcadd z0.h, p0/m, z0.h, z0.h, #90 // CHECK-INST: fcadd z0.h, p0/m, z0.h, z0.h, #90 // CHECK-ENCODING: [0x00,0x80,0x40,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 40 64 fcadd z0.s, p0/m, z0.s, z0.s, #90 // CHECK-INST: fcadd z0.s, p0/m, z0.s, z0.s, #90 // CHECK-ENCODING: [0x00,0x80,0x80,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 80 64 fcadd z0.d, p0/m, z0.d, z0.d, #90 // CHECK-INST: fcadd z0.d, p0/m, z0.d, z0.d, #90 // CHECK-ENCODING: [0x00,0x80,0xc0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 c0 64 fcadd z31.h, p7/m, z31.h, z31.h, #270 // CHECK-INST: fcadd z31.h, p7/m, z31.h, z31.h, #270 // CHECK-ENCODING: [0xff,0x9f,0x41,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 41 64 fcadd z31.s, p7/m, z31.s, z31.s, #270 // CHECK-INST: fcadd z31.s, p7/m, z31.s, z31.s, #270 // CHECK-ENCODING: [0xff,0x9f,0x81,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 81 64 fcadd z31.d, p7/m, z31.d, z31.d, #270 // CHECK-INST: fcadd z31.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0x9f,0xc1,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f c1 64 @@ -52,23 +52,23 @@ fcadd z31.d, p7/m, z31.d, z31.d, #270 movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 fcadd z4.d, p7/m, z4.d, z31.d, #270 // CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f c1 64 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 fcadd z4.d, p7/m, z4.d, z31.d, #270 // CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f c1 64 diff --git a/llvm/test/MC/AArch64/SVE/fcmeq.s b/llvm/test/MC/AArch64/SVE/fcmeq.s index 8f75330f12dbf..a523546141eb9 100644 --- a/llvm/test/MC/AArch64/SVE/fcmeq.s +++ b/llvm/test/MC/AArch64/SVE/fcmeq.s @@ -12,35 +12,35 @@ fcmeq p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmeq p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x20,0x52,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 52 65 fcmeq p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmeq p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x20,0x92,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 92 65 fcmeq p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmeq p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x20,0xd2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 d2 65 fcmeq p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmeq p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x00,0x60,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 41 65 fcmeq p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmeq p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x00,0x60,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 81 65 fcmeq p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmeq p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x00,0x60,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmge.s b/llvm/test/MC/AArch64/SVE/fcmge.s index 60d6325966d72..9500c79affbc0 100644 --- a/llvm/test/MC/AArch64/SVE/fcmge.s +++ b/llvm/test/MC/AArch64/SVE/fcmge.s @@ -12,35 +12,35 @@ fcmge p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmge p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x20,0x50,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 50 65 fcmge p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmge p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x20,0x90,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 90 65 fcmge p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmge p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x20,0xd0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 d0 65 fcmge p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmge p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x00,0x40,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 41 65 fcmge p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmge p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x00,0x40,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 81 65 fcmge p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmge p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x00,0x40,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmgt.s b/llvm/test/MC/AArch64/SVE/fcmgt.s index d69adf168dcea..e352a5e17f076 100644 --- a/llvm/test/MC/AArch64/SVE/fcmgt.s +++ b/llvm/test/MC/AArch64/SVE/fcmgt.s @@ -12,35 +12,35 @@ fcmgt p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmgt p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x10,0x20,0x50,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 50 65 fcmgt p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmgt p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x10,0x20,0x90,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 90 65 fcmgt p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmgt p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x10,0x20,0xd0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 d0 65 fcmgt p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmgt p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x10,0x40,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 41 65 fcmgt p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmgt p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x10,0x40,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 81 65 fcmgt p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmgt p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x10,0x40,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmla.s b/llvm/test/MC/AArch64/SVE/fcmla.s index 24cf8e840fdab..e3952e1943bef 100644 --- a/llvm/test/MC/AArch64/SVE/fcmla.s +++ b/llvm/test/MC/AArch64/SVE/fcmla.s @@ -12,97 +12,97 @@ fcmla z0.h, p0/m, z0.h, z0.h, #0 // CHECK-INST: fcmla z0.h, p0/m, z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0x00,0x40,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 40 64 fcmla z0.s, p0/m, z0.s, z0.s, #0 // CHECK-INST: fcmla z0.s, p0/m, z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0x00,0x80,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 64 fcmla z0.d, p0/m, z0.d, z0.d, #0 // CHECK-INST: fcmla z0.d, p0/m, z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0x00,0xc0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c0 64 fcmla z0.h, p0/m, z1.h, z2.h, #90 // CHECK-INST: fcmla z0.h, p0/m, z1.h, z2.h, #90 // CHECK-ENCODING: [0x20,0x20,0x42,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 20 42 64 fcmla z0.s, p0/m, z1.s, z2.s, #90 // CHECK-INST: fcmla z0.s, p0/m, z1.s, z2.s, #90 // CHECK-ENCODING: [0x20,0x20,0x82,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 20 82 64 fcmla z0.d, p0/m, z1.d, z2.d, #90 // CHECK-INST: fcmla z0.d, p0/m, z1.d, z2.d, #90 // CHECK-ENCODING: [0x20,0x20,0xc2,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 20 c2 64 fcmla z29.h, p7/m, z30.h, z31.h, #180 // CHECK-INST: fcmla z29.h, p7/m, z30.h, z31.h, #180 // CHECK-ENCODING: [0xdd,0x5f,0x5f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: dd 5f 5f 64 fcmla z29.s, p7/m, z30.s, z31.s, #180 // CHECK-INST: fcmla z29.s, p7/m, z30.s, z31.s, #180 // CHECK-ENCODING: [0xdd,0x5f,0x9f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: dd 5f 9f 64 fcmla z29.d, p7/m, z30.d, z31.d, #180 // CHECK-INST: fcmla z29.d, p7/m, z30.d, z31.d, #180 // CHECK-ENCODING: [0xdd,0x5f,0xdf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: dd 5f df 64 fcmla z31.h, p7/m, z31.h, z31.h, #270 // CHECK-INST: fcmla z31.h, p7/m, z31.h, z31.h, #270 // CHECK-ENCODING: [0xff,0x7f,0x5f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f 5f 64 fcmla z31.s, p7/m, z31.s, z31.s, #270 // CHECK-INST: fcmla z31.s, p7/m, z31.s, z31.s, #270 // CHECK-ENCODING: [0xff,0x7f,0x9f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f 9f 64 fcmla z31.d, p7/m, z31.d, z31.d, #270 // CHECK-INST: fcmla z31.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0x7f,0xdf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f df 64 fcmla z0.h, z0.h, z0.h[0], #0 // CHECK-INST: fcmla z0.h, z0.h, z0.h[0], #0 // CHECK-ENCODING: [0x00,0x10,0xa0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 10 a0 64 fcmla z23.s, z13.s, z8.s[0], #270 // CHECK-INST: fcmla z23.s, z13.s, z8.s[0], #270 // CHECK-ENCODING: [0xb7,0x1d,0xe8,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 1d e8 64 fcmla z31.h, z31.h, z7.h[3], #270 // CHECK-INST: fcmla z31.h, z31.h, z7.h[3], #270 // CHECK-ENCODING: [0xff,0x1f,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f bf 64 fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 f5 64 @@ -112,35 +112,35 @@ fcmla z21.s, z10.s, z5.s[1], #90 movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 fcmla z4.d, p7/m, z31.d, z31.d, #270 // CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 7f df 64 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 fcmla z4.d, p7/m, z31.d, z31.d, #270 // CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 7f df 64 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 f5 64 diff --git a/llvm/test/MC/AArch64/SVE/fcmle.s b/llvm/test/MC/AArch64/SVE/fcmle.s index 119b873f79812..95ed55a87f885 100644 --- a/llvm/test/MC/AArch64/SVE/fcmle.s +++ b/llvm/test/MC/AArch64/SVE/fcmle.s @@ -12,35 +12,35 @@ fcmle p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmle p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x10,0x20,0x51,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 51 65 fcmle p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmle p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x10,0x20,0x91,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 91 65 fcmle p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmle p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x10,0x20,0xd1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 20 d1 65 fcmle p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmge p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x20,0x40,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 40 40 65 fcmle p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmge p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x20,0x40,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 40 80 65 fcmle p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmge p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x20,0x40,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 40 c0 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmlt.s b/llvm/test/MC/AArch64/SVE/fcmlt.s index 62399d0e8b9cb..a145b386aef04 100644 --- a/llvm/test/MC/AArch64/SVE/fcmlt.s +++ b/llvm/test/MC/AArch64/SVE/fcmlt.s @@ -12,35 +12,35 @@ fcmlt p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmlt p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x20,0x51,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 51 65 fcmlt p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmlt p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x20,0x91,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 91 65 fcmlt p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmlt p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x20,0xd1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 d1 65 fcmlt p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmgt p0.h, p0/z, z1.h, z0.h // CHECK-ENCODING: [0x30,0x40,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 40 40 65 fcmlt p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmgt p0.s, p0/z, z1.s, z0.s // CHECK-ENCODING: [0x30,0x40,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 40 80 65 fcmlt p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmgt p0.d, p0/z, z1.d, z0.d // CHECK-ENCODING: [0x30,0x40,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 30 40 c0 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmne.s b/llvm/test/MC/AArch64/SVE/fcmne.s index d1b8f8e29ce00..355044df20fb3 100644 --- a/llvm/test/MC/AArch64/SVE/fcmne.s +++ b/llvm/test/MC/AArch64/SVE/fcmne.s @@ -12,35 +12,35 @@ fcmne p0.h, p0/z, z0.h, #0.0 // CHECK-INST: fcmne p0.h, p0/z, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x20,0x53,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 53 65 fcmne p0.s, p0/z, z0.s, #0.0 // CHECK-INST: fcmne p0.s, p0/z, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x20,0x93,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 93 65 fcmne p0.d, p0/z, z0.d, #0.0 // CHECK-INST: fcmne p0.d, p0/z, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x20,0xd3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 d3 65 fcmne p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmne p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x10,0x60,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 41 65 fcmne p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmne p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x10,0x60,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 81 65 fcmne p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmne p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x10,0x60,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 60 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fcmuo.s b/llvm/test/MC/AArch64/SVE/fcmuo.s index dece61eef2086..d75ab77c18ca8 100644 --- a/llvm/test/MC/AArch64/SVE/fcmuo.s +++ b/llvm/test/MC/AArch64/SVE/fcmuo.s @@ -12,18 +12,18 @@ fcmuo p0.h, p0/z, z0.h, z1.h // CHECK-INST: fcmuo p0.h, p0/z, z0.h, z1.h // CHECK-ENCODING: [0x00,0xc0,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 41 65 fcmuo p0.s, p0/z, z0.s, z1.s // CHECK-INST: fcmuo p0.s, p0/z, z0.s, z1.s // CHECK-ENCODING: [0x00,0xc0,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 81 65 fcmuo p0.d, p0/z, z0.d, z1.d // CHECK-INST: fcmuo p0.d, p0/z, z0.d, z1.d // CHECK-ENCODING: [0x00,0xc0,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fcpy.s b/llvm/test/MC/AArch64/SVE/fcpy.s index 6cdd3b5f8b2cf..f2c4776ccf528 100644 --- a/llvm/test/MC/AArch64/SVE/fcpy.s +++ b/llvm/test/MC/AArch64/SVE/fcpy.s @@ -12,1549 +12,1549 @@ fcpy z0.h, p0/m, #-0.12500000 // CHECK-INST: fmov z0.h, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 50 05 fcpy z0.s, p0/m, #-0.12500000 // CHECK-INST: fmov z0.s, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 90 05 fcpy z0.d, p0/m, #-0.12500000 // CHECK-INST: fmov z0.d, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 d0 05 fcpy z0.d, p0/m, #-0.13281250 // CHECK-INST: fmov z0.d, p0/m, #-0.13281250 // CHECK-ENCODING: [0x20,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d8 d0 05 fcpy z0.d, p0/m, #-0.14062500 // CHECK-INST: fmov z0.d, p0/m, #-0.14062500 // CHECK-ENCODING: [0x40,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d8 d0 05 fcpy z0.d, p0/m, #-0.14843750 // CHECK-INST: fmov z0.d, p0/m, #-0.14843750 // CHECK-ENCODING: [0x60,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d8 d0 05 fcpy z0.d, p0/m, #-0.15625000 // CHECK-INST: fmov z0.d, p0/m, #-0.15625000 // CHECK-ENCODING: [0x80,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d8 d0 05 fcpy z0.d, p0/m, #-0.16406250 // CHECK-INST: fmov z0.d, p0/m, #-0.16406250 // CHECK-ENCODING: [0xa0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d8 d0 05 fcpy z0.d, p0/m, #-0.17187500 // CHECK-INST: fmov z0.d, p0/m, #-0.17187500 // CHECK-ENCODING: [0xc0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d8 d0 05 fcpy z0.d, p0/m, #-0.17968750 // CHECK-INST: fmov z0.d, p0/m, #-0.17968750 // CHECK-ENCODING: [0xe0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d8 d0 05 fcpy z0.d, p0/m, #-0.18750000 // CHECK-INST: fmov z0.d, p0/m, #-0.18750000 // CHECK-ENCODING: [0x00,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d9 d0 05 fcpy z0.d, p0/m, #-0.19531250 // CHECK-INST: fmov z0.d, p0/m, #-0.19531250 // CHECK-ENCODING: [0x20,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d9 d0 05 fcpy z0.d, p0/m, #-0.20312500 // CHECK-INST: fmov z0.d, p0/m, #-0.20312500 // CHECK-ENCODING: [0x40,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d9 d0 05 fcpy z0.d, p0/m, #-0.21093750 // CHECK-INST: fmov z0.d, p0/m, #-0.21093750 // CHECK-ENCODING: [0x60,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d9 d0 05 fcpy z0.d, p0/m, #-0.21875000 // CHECK-INST: fmov z0.d, p0/m, #-0.21875000 // CHECK-ENCODING: [0x80,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d9 d0 05 fcpy z0.d, p0/m, #-0.22656250 // CHECK-INST: fmov z0.d, p0/m, #-0.22656250 // CHECK-ENCODING: [0xa0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d9 d0 05 fcpy z0.d, p0/m, #-0.23437500 // CHECK-INST: fmov z0.d, p0/m, #-0.23437500 // CHECK-ENCODING: [0xc0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d9 d0 05 fcpy z0.d, p0/m, #-0.24218750 // CHECK-INST: fmov z0.d, p0/m, #-0.24218750 // CHECK-ENCODING: [0xe0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d9 d0 05 fcpy z0.d, p0/m, #-0.25000000 // CHECK-INST: fmov z0.d, p0/m, #-0.25000000 // CHECK-ENCODING: [0x00,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 da d0 05 fcpy z0.d, p0/m, #-0.26562500 // CHECK-INST: fmov z0.d, p0/m, #-0.26562500 // CHECK-ENCODING: [0x20,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 da d0 05 fcpy z0.d, p0/m, #-0.28125000 // CHECK-INST: fmov z0.d, p0/m, #-0.28125000 // CHECK-ENCODING: [0x40,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 da d0 05 fcpy z0.d, p0/m, #-0.29687500 // CHECK-INST: fmov z0.d, p0/m, #-0.29687500 // CHECK-ENCODING: [0x60,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 da d0 05 fcpy z0.d, p0/m, #-0.31250000 // CHECK-INST: fmov z0.d, p0/m, #-0.31250000 // CHECK-ENCODING: [0x80,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 da d0 05 fcpy z0.d, p0/m, #-0.32812500 // CHECK-INST: fmov z0.d, p0/m, #-0.32812500 // CHECK-ENCODING: [0xa0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 da d0 05 fcpy z0.d, p0/m, #-0.34375000 // CHECK-INST: fmov z0.d, p0/m, #-0.34375000 // CHECK-ENCODING: [0xc0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 da d0 05 fcpy z0.d, p0/m, #-0.35937500 // CHECK-INST: fmov z0.d, p0/m, #-0.35937500 // CHECK-ENCODING: [0xe0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 da d0 05 fcpy z0.d, p0/m, #-0.37500000 // CHECK-INST: fmov z0.d, p0/m, #-0.37500000 // CHECK-ENCODING: [0x00,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 db d0 05 fcpy z0.d, p0/m, #-0.39062500 // CHECK-INST: fmov z0.d, p0/m, #-0.39062500 // CHECK-ENCODING: [0x20,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 db d0 05 fcpy z0.d, p0/m, #-0.40625000 // CHECK-INST: fmov z0.d, p0/m, #-0.40625000 // CHECK-ENCODING: [0x40,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 db d0 05 fcpy z0.d, p0/m, #-0.42187500 // CHECK-INST: fmov z0.d, p0/m, #-0.42187500 // CHECK-ENCODING: [0x60,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 db d0 05 fcpy z0.d, p0/m, #-0.43750000 // CHECK-INST: fmov z0.d, p0/m, #-0.43750000 // CHECK-ENCODING: [0x80,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 db d0 05 fcpy z0.d, p0/m, #-0.45312500 // CHECK-INST: fmov z0.d, p0/m, #-0.45312500 // CHECK-ENCODING: [0xa0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 db d0 05 fcpy z0.d, p0/m, #-0.46875000 // CHECK-INST: fmov z0.d, p0/m, #-0.46875000 // CHECK-ENCODING: [0xc0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 db d0 05 fcpy z0.d, p0/m, #-0.48437500 // CHECK-INST: fmov z0.d, p0/m, #-0.48437500 // CHECK-ENCODING: [0xe0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 db d0 05 fcpy z0.d, p0/m, #-0.50000000 // CHECK-INST: fmov z0.d, p0/m, #-0.50000000 // CHECK-ENCODING: [0x00,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dc d0 05 fcpy z0.d, p0/m, #-0.53125000 // CHECK-INST: fmov z0.d, p0/m, #-0.53125000 // CHECK-ENCODING: [0x20,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc d0 05 fcpy z0.d, p0/m, #-0.56250000 // CHECK-INST: fmov z0.d, p0/m, #-0.56250000 // CHECK-ENCODING: [0x40,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dc d0 05 fcpy z0.d, p0/m, #-0.59375000 // CHECK-INST: fmov z0.d, p0/m, #-0.59375000 // CHECK-ENCODING: [0x60,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dc d0 05 fcpy z0.d, p0/m, #-0.62500000 // CHECK-INST: fmov z0.d, p0/m, #-0.62500000 // CHECK-ENCODING: [0x80,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dc d0 05 fcpy z0.d, p0/m, #-0.65625000 // CHECK-INST: fmov z0.d, p0/m, #-0.65625000 // CHECK-ENCODING: [0xa0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dc d0 05 fcpy z0.d, p0/m, #-0.68750000 // CHECK-INST: fmov z0.d, p0/m, #-0.68750000 // CHECK-ENCODING: [0xc0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dc d0 05 fcpy z0.d, p0/m, #-0.71875000 // CHECK-INST: fmov z0.d, p0/m, #-0.71875000 // CHECK-ENCODING: [0xe0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dc d0 05 fcpy z0.d, p0/m, #-0.75000000 // CHECK-INST: fmov z0.d, p0/m, #-0.75000000 // CHECK-ENCODING: [0x00,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dd d0 05 fcpy z0.d, p0/m, #-0.78125000 // CHECK-INST: fmov z0.d, p0/m, #-0.78125000 // CHECK-ENCODING: [0x20,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dd d0 05 fcpy z0.d, p0/m, #-0.81250000 // CHECK-INST: fmov z0.d, p0/m, #-0.81250000 // CHECK-ENCODING: [0x40,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dd d0 05 fcpy z0.d, p0/m, #-0.84375000 // CHECK-INST: fmov z0.d, p0/m, #-0.84375000 // CHECK-ENCODING: [0x60,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dd d0 05 fcpy z0.d, p0/m, #-0.87500000 // CHECK-INST: fmov z0.d, p0/m, #-0.87500000 // CHECK-ENCODING: [0x80,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dd d0 05 fcpy z0.d, p0/m, #-0.90625000 // CHECK-INST: fmov z0.d, p0/m, #-0.90625000 // CHECK-ENCODING: [0xa0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dd d0 05 fcpy z0.d, p0/m, #-0.93750000 // CHECK-INST: fmov z0.d, p0/m, #-0.93750000 // CHECK-ENCODING: [0xc0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dd d0 05 fcpy z0.d, p0/m, #-0.96875000 // CHECK-INST: fmov z0.d, p0/m, #-0.96875000 // CHECK-ENCODING: [0xe0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dd d0 05 fcpy z0.d, p0/m, #-1.00000000 // CHECK-INST: fmov z0.d, p0/m, #-1.00000000 // CHECK-ENCODING: [0x00,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 de d0 05 fcpy z0.d, p0/m, #-1.06250000 // CHECK-INST: fmov z0.d, p0/m, #-1.06250000 // CHECK-ENCODING: [0x20,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 de d0 05 fcpy z0.d, p0/m, #-1.12500000 // CHECK-INST: fmov z0.d, p0/m, #-1.12500000 // CHECK-ENCODING: [0x40,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 de d0 05 fcpy z0.d, p0/m, #-1.18750000 // CHECK-INST: fmov z0.d, p0/m, #-1.18750000 // CHECK-ENCODING: [0x60,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 de d0 05 fcpy z0.d, p0/m, #-1.25000000 // CHECK-INST: fmov z0.d, p0/m, #-1.25000000 // CHECK-ENCODING: [0x80,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 de d0 05 fcpy z0.d, p0/m, #-1.31250000 // CHECK-INST: fmov z0.d, p0/m, #-1.31250000 // CHECK-ENCODING: [0xa0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 de d0 05 fcpy z0.d, p0/m, #-1.37500000 // CHECK-INST: fmov z0.d, p0/m, #-1.37500000 // CHECK-ENCODING: [0xc0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 de d0 05 fcpy z0.d, p0/m, #-1.43750000 // CHECK-INST: fmov z0.d, p0/m, #-1.43750000 // CHECK-ENCODING: [0xe0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 de d0 05 fcpy z0.d, p0/m, #-1.50000000 // CHECK-INST: fmov z0.d, p0/m, #-1.50000000 // CHECK-ENCODING: [0x00,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 df d0 05 fcpy z0.d, p0/m, #-1.56250000 // CHECK-INST: fmov z0.d, p0/m, #-1.56250000 // CHECK-ENCODING: [0x20,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 df d0 05 fcpy z0.d, p0/m, #-1.62500000 // CHECK-INST: fmov z0.d, p0/m, #-1.62500000 // CHECK-ENCODING: [0x40,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 df d0 05 fcpy z0.d, p0/m, #-1.68750000 // CHECK-INST: fmov z0.d, p0/m, #-1.68750000 // CHECK-ENCODING: [0x60,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 df d0 05 fcpy z0.d, p0/m, #-1.75000000 // CHECK-INST: fmov z0.d, p0/m, #-1.75000000 // CHECK-ENCODING: [0x80,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 df d0 05 fcpy z0.d, p0/m, #-1.81250000 // CHECK-INST: fmov z0.d, p0/m, #-1.81250000 // CHECK-ENCODING: [0xa0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 df d0 05 fcpy z0.d, p0/m, #-1.87500000 // CHECK-INST: fmov z0.d, p0/m, #-1.87500000 // CHECK-ENCODING: [0xc0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 df d0 05 fcpy z0.d, p0/m, #-1.93750000 // CHECK-INST: fmov z0.d, p0/m, #-1.93750000 // CHECK-ENCODING: [0xe0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df d0 05 fcpy z0.d, p0/m, #-2.00000000 // CHECK-INST: fmov z0.d, p0/m, #-2.00000000 // CHECK-ENCODING: [0x00,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 d0 05 fcpy z0.d, p0/m, #-2.12500000 // CHECK-INST: fmov z0.d, p0/m, #-2.12500000 // CHECK-ENCODING: [0x20,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d0 d0 05 fcpy z0.d, p0/m, #-2.25000000 // CHECK-INST: fmov z0.d, p0/m, #-2.25000000 // CHECK-ENCODING: [0x40,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d0 d0 05 fcpy z0.d, p0/m, #-2.37500000 // CHECK-INST: fmov z0.d, p0/m, #-2.37500000 // CHECK-ENCODING: [0x60,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d0 d0 05 fcpy z0.d, p0/m, #-2.50000000 // CHECK-INST: fmov z0.d, p0/m, #-2.50000000 // CHECK-ENCODING: [0x80,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d0 d0 05 fcpy z0.d, p0/m, #-2.62500000 // CHECK-INST: fmov z0.d, p0/m, #-2.62500000 // CHECK-ENCODING: [0xa0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d0 d0 05 fcpy z0.d, p0/m, #-2.75000000 // CHECK-INST: fmov z0.d, p0/m, #-2.75000000 // CHECK-ENCODING: [0xc0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d0 d0 05 fcpy z0.d, p0/m, #-2.87500000 // CHECK-INST: fmov z0.d, p0/m, #-2.87500000 // CHECK-ENCODING: [0xe0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d0 d0 05 fcpy z0.d, p0/m, #-3.00000000 // CHECK-INST: fmov z0.d, p0/m, #-3.00000000 // CHECK-ENCODING: [0x00,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d1 d0 05 fcpy z0.d, p0/m, #-3.12500000 // CHECK-INST: fmov z0.d, p0/m, #-3.12500000 // CHECK-ENCODING: [0x20,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d1 d0 05 fcpy z0.d, p0/m, #-3.25000000 // CHECK-INST: fmov z0.d, p0/m, #-3.25000000 // CHECK-ENCODING: [0x40,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d1 d0 05 fcpy z0.d, p0/m, #-3.37500000 // CHECK-INST: fmov z0.d, p0/m, #-3.37500000 // CHECK-ENCODING: [0x60,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d1 d0 05 fcpy z0.d, p0/m, #-3.50000000 // CHECK-INST: fmov z0.d, p0/m, #-3.50000000 // CHECK-ENCODING: [0x80,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d1 d0 05 fcpy z0.d, p0/m, #-3.62500000 // CHECK-INST: fmov z0.d, p0/m, #-3.62500000 // CHECK-ENCODING: [0xa0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d1 d0 05 fcpy z0.d, p0/m, #-3.75000000 // CHECK-INST: fmov z0.d, p0/m, #-3.75000000 // CHECK-ENCODING: [0xc0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d1 d0 05 fcpy z0.d, p0/m, #-3.87500000 // CHECK-INST: fmov z0.d, p0/m, #-3.87500000 // CHECK-ENCODING: [0xe0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d1 d0 05 fcpy z0.d, p0/m, #-4.00000000 // CHECK-INST: fmov z0.d, p0/m, #-4.00000000 // CHECK-ENCODING: [0x00,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d2 d0 05 fcpy z0.d, p0/m, #-4.25000000 // CHECK-INST: fmov z0.d, p0/m, #-4.25000000 // CHECK-ENCODING: [0x20,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d2 d0 05 fcpy z0.d, p0/m, #-4.50000000 // CHECK-INST: fmov z0.d, p0/m, #-4.50000000 // CHECK-ENCODING: [0x40,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d2 d0 05 fcpy z0.d, p0/m, #-4.75000000 // CHECK-INST: fmov z0.d, p0/m, #-4.75000000 // CHECK-ENCODING: [0x60,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d2 d0 05 fcpy z0.d, p0/m, #-5.00000000 // CHECK-INST: fmov z0.d, p0/m, #-5.00000000 // CHECK-ENCODING: [0x80,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d2 d0 05 fcpy z0.d, p0/m, #-5.25000000 // CHECK-INST: fmov z0.d, p0/m, #-5.25000000 // CHECK-ENCODING: [0xa0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d2 d0 05 fcpy z0.d, p0/m, #-5.50000000 // CHECK-INST: fmov z0.d, p0/m, #-5.50000000 // CHECK-ENCODING: [0xc0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d2 d0 05 fcpy z0.d, p0/m, #-5.75000000 // CHECK-INST: fmov z0.d, p0/m, #-5.75000000 // CHECK-ENCODING: [0xe0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d2 d0 05 fcpy z0.d, p0/m, #-6.00000000 // CHECK-INST: fmov z0.d, p0/m, #-6.00000000 // CHECK-ENCODING: [0x00,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d3 d0 05 fcpy z0.d, p0/m, #-6.25000000 // CHECK-INST: fmov z0.d, p0/m, #-6.25000000 // CHECK-ENCODING: [0x20,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d3 d0 05 fcpy z0.d, p0/m, #-6.50000000 // CHECK-INST: fmov z0.d, p0/m, #-6.50000000 // CHECK-ENCODING: [0x40,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d3 d0 05 fcpy z0.d, p0/m, #-6.75000000 // CHECK-INST: fmov z0.d, p0/m, #-6.75000000 // CHECK-ENCODING: [0x60,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d3 d0 05 fcpy z0.d, p0/m, #-7.00000000 // CHECK-INST: fmov z0.d, p0/m, #-7.00000000 // CHECK-ENCODING: [0x80,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d3 d0 05 fcpy z0.d, p0/m, #-7.25000000 // CHECK-INST: fmov z0.d, p0/m, #-7.25000000 // CHECK-ENCODING: [0xa0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d3 d0 05 fcpy z0.d, p0/m, #-7.50000000 // CHECK-INST: fmov z0.d, p0/m, #-7.50000000 // CHECK-ENCODING: [0xc0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d3 d0 05 fcpy z0.d, p0/m, #-7.75000000 // CHECK-INST: fmov z0.d, p0/m, #-7.75000000 // CHECK-ENCODING: [0xe0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d3 d0 05 fcpy z0.d, p0/m, #-8.00000000 // CHECK-INST: fmov z0.d, p0/m, #-8.00000000 // CHECK-ENCODING: [0x00,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d4 d0 05 fcpy z0.d, p0/m, #-8.50000000 // CHECK-INST: fmov z0.d, p0/m, #-8.50000000 // CHECK-ENCODING: [0x20,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d4 d0 05 fcpy z0.d, p0/m, #-9.00000000 // CHECK-INST: fmov z0.d, p0/m, #-9.00000000 // CHECK-ENCODING: [0x40,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d4 d0 05 fcpy z0.d, p0/m, #-9.50000000 // CHECK-INST: fmov z0.d, p0/m, #-9.50000000 // CHECK-ENCODING: [0x60,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d4 d0 05 fcpy z0.d, p0/m, #-10.00000000 // CHECK-INST: fmov z0.d, p0/m, #-10.00000000 // CHECK-ENCODING: [0x80,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d4 d0 05 fcpy z0.d, p0/m, #-10.50000000 // CHECK-INST: fmov z0.d, p0/m, #-10.50000000 // CHECK-ENCODING: [0xa0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d4 d0 05 fcpy z0.d, p0/m, #-11.00000000 // CHECK-INST: fmov z0.d, p0/m, #-11.00000000 // CHECK-ENCODING: [0xc0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d4 d0 05 fcpy z0.d, p0/m, #-11.50000000 // CHECK-INST: fmov z0.d, p0/m, #-11.50000000 // CHECK-ENCODING: [0xe0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d4 d0 05 fcpy z0.d, p0/m, #-12.00000000 // CHECK-INST: fmov z0.d, p0/m, #-12.00000000 // CHECK-ENCODING: [0x00,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d5 d0 05 fcpy z0.d, p0/m, #-12.50000000 // CHECK-INST: fmov z0.d, p0/m, #-12.50000000 // CHECK-ENCODING: [0x20,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d5 d0 05 fcpy z0.d, p0/m, #-13.00000000 // CHECK-INST: fmov z0.d, p0/m, #-13.00000000 // CHECK-ENCODING: [0x40,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d5 d0 05 fcpy z0.d, p0/m, #-13.50000000 // CHECK-INST: fmov z0.d, p0/m, #-13.50000000 // CHECK-ENCODING: [0x60,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d5 d0 05 fcpy z0.d, p0/m, #-14.00000000 // CHECK-INST: fmov z0.d, p0/m, #-14.00000000 // CHECK-ENCODING: [0x80,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d5 d0 05 fcpy z0.d, p0/m, #-14.50000000 // CHECK-INST: fmov z0.d, p0/m, #-14.50000000 // CHECK-ENCODING: [0xa0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d5 d0 05 fcpy z0.d, p0/m, #-15.00000000 // CHECK-INST: fmov z0.d, p0/m, #-15.00000000 // CHECK-ENCODING: [0xc0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d5 d0 05 fcpy z0.d, p0/m, #-15.50000000 // CHECK-INST: fmov z0.d, p0/m, #-15.50000000 // CHECK-ENCODING: [0xe0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d5 d0 05 fcpy z0.d, p0/m, #-16.00000000 // CHECK-INST: fmov z0.d, p0/m, #-16.00000000 // CHECK-ENCODING: [0x00,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d6 d0 05 fcpy z0.d, p0/m, #-17.00000000 // CHECK-INST: fmov z0.d, p0/m, #-17.00000000 // CHECK-ENCODING: [0x20,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d6 d0 05 fcpy z0.d, p0/m, #-18.00000000 // CHECK-INST: fmov z0.d, p0/m, #-18.00000000 // CHECK-ENCODING: [0x40,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d6 d0 05 fcpy z0.d, p0/m, #-19.00000000 // CHECK-INST: fmov z0.d, p0/m, #-19.00000000 // CHECK-ENCODING: [0x60,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d6 d0 05 fcpy z0.d, p0/m, #-20.00000000 // CHECK-INST: fmov z0.d, p0/m, #-20.00000000 // CHECK-ENCODING: [0x80,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d6 d0 05 fcpy z0.d, p0/m, #-21.00000000 // CHECK-INST: fmov z0.d, p0/m, #-21.00000000 // CHECK-ENCODING: [0xa0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d6 d0 05 fcpy z0.d, p0/m, #-22.00000000 // CHECK-INST: fmov z0.d, p0/m, #-22.00000000 // CHECK-ENCODING: [0xc0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d6 d0 05 fcpy z0.d, p0/m, #-23.00000000 // CHECK-INST: fmov z0.d, p0/m, #-23.00000000 // CHECK-ENCODING: [0xe0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d6 d0 05 fcpy z0.d, p0/m, #-24.00000000 // CHECK-INST: fmov z0.d, p0/m, #-24.00000000 // CHECK-ENCODING: [0x00,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d7 d0 05 fcpy z0.d, p0/m, #-25.00000000 // CHECK-INST: fmov z0.d, p0/m, #-25.00000000 // CHECK-ENCODING: [0x20,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d7 d0 05 fcpy z0.d, p0/m, #-26.00000000 // CHECK-INST: fmov z0.d, p0/m, #-26.00000000 // CHECK-ENCODING: [0x40,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d7 d0 05 fcpy z0.d, p0/m, #-27.00000000 // CHECK-INST: fmov z0.d, p0/m, #-27.00000000 // CHECK-ENCODING: [0x60,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d7 d0 05 fcpy z0.d, p0/m, #-28.00000000 // CHECK-INST: fmov z0.d, p0/m, #-28.00000000 // CHECK-ENCODING: [0x80,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d7 d0 05 fcpy z0.d, p0/m, #-29.00000000 // CHECK-INST: fmov z0.d, p0/m, #-29.00000000 // CHECK-ENCODING: [0xa0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d7 d0 05 fcpy z0.d, p0/m, #-30.00000000 // CHECK-INST: fmov z0.d, p0/m, #-30.00000000 // CHECK-ENCODING: [0xc0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d7 d0 05 fcpy z0.d, p0/m, #-31.00000000 // CHECK-INST: fmov z0.d, p0/m, #-31.00000000 // CHECK-ENCODING: [0xe0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d7 d0 05 fcpy z0.d, p0/m, #0.12500000 // CHECK-INST: fmov z0.d, p0/m, #0.12500000 // CHECK-ENCODING: [0x00,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 d0 05 fcpy z0.d, p0/m, #0.13281250 // CHECK-INST: fmov z0.d, p0/m, #0.13281250 // CHECK-ENCODING: [0x20,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c8 d0 05 fcpy z0.d, p0/m, #0.14062500 // CHECK-INST: fmov z0.d, p0/m, #0.14062500 // CHECK-ENCODING: [0x40,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c8 d0 05 fcpy z0.d, p0/m, #0.14843750 // CHECK-INST: fmov z0.d, p0/m, #0.14843750 // CHECK-ENCODING: [0x60,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c8 d0 05 fcpy z0.d, p0/m, #0.15625000 // CHECK-INST: fmov z0.d, p0/m, #0.15625000 // CHECK-ENCODING: [0x80,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c8 d0 05 fcpy z0.d, p0/m, #0.16406250 // CHECK-INST: fmov z0.d, p0/m, #0.16406250 // CHECK-ENCODING: [0xa0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c8 d0 05 fcpy z0.d, p0/m, #0.17187500 // CHECK-INST: fmov z0.d, p0/m, #0.17187500 // CHECK-ENCODING: [0xc0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c8 d0 05 fcpy z0.d, p0/m, #0.17968750 // CHECK-INST: fmov z0.d, p0/m, #0.17968750 // CHECK-ENCODING: [0xe0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c8 d0 05 fcpy z0.d, p0/m, #0.18750000 // CHECK-INST: fmov z0.d, p0/m, #0.18750000 // CHECK-ENCODING: [0x00,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c9 d0 05 fcpy z0.d, p0/m, #0.19531250 // CHECK-INST: fmov z0.d, p0/m, #0.19531250 // CHECK-ENCODING: [0x20,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c9 d0 05 fcpy z0.d, p0/m, #0.20312500 // CHECK-INST: fmov z0.d, p0/m, #0.20312500 // CHECK-ENCODING: [0x40,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c9 d0 05 fcpy z0.d, p0/m, #0.21093750 // CHECK-INST: fmov z0.d, p0/m, #0.21093750 // CHECK-ENCODING: [0x60,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c9 d0 05 fcpy z0.d, p0/m, #0.21875000 // CHECK-INST: fmov z0.d, p0/m, #0.21875000 // CHECK-ENCODING: [0x80,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c9 d0 05 fcpy z0.d, p0/m, #0.22656250 // CHECK-INST: fmov z0.d, p0/m, #0.22656250 // CHECK-ENCODING: [0xa0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c9 d0 05 fcpy z0.d, p0/m, #0.23437500 // CHECK-INST: fmov z0.d, p0/m, #0.23437500 // CHECK-ENCODING: [0xc0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c9 d0 05 fcpy z0.d, p0/m, #0.24218750 // CHECK-INST: fmov z0.d, p0/m, #0.24218750 // CHECK-ENCODING: [0xe0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c9 d0 05 fcpy z0.d, p0/m, #0.25000000 // CHECK-INST: fmov z0.d, p0/m, #0.25000000 // CHECK-ENCODING: [0x00,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ca d0 05 fcpy z0.d, p0/m, #0.26562500 // CHECK-INST: fmov z0.d, p0/m, #0.26562500 // CHECK-ENCODING: [0x20,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ca d0 05 fcpy z0.d, p0/m, #0.28125000 // CHECK-INST: fmov z0.d, p0/m, #0.28125000 // CHECK-ENCODING: [0x40,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ca d0 05 fcpy z0.d, p0/m, #0.29687500 // CHECK-INST: fmov z0.d, p0/m, #0.29687500 // CHECK-ENCODING: [0x60,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ca d0 05 fcpy z0.d, p0/m, #0.31250000 // CHECK-INST: fmov z0.d, p0/m, #0.31250000 // CHECK-ENCODING: [0x80,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ca d0 05 fcpy z0.d, p0/m, #0.32812500 // CHECK-INST: fmov z0.d, p0/m, #0.32812500 // CHECK-ENCODING: [0xa0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ca d0 05 fcpy z0.d, p0/m, #0.34375000 // CHECK-INST: fmov z0.d, p0/m, #0.34375000 // CHECK-ENCODING: [0xc0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ca d0 05 fcpy z0.d, p0/m, #0.35937500 // CHECK-INST: fmov z0.d, p0/m, #0.35937500 // CHECK-ENCODING: [0xe0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ca d0 05 fcpy z0.d, p0/m, #0.37500000 // CHECK-INST: fmov z0.d, p0/m, #0.37500000 // CHECK-ENCODING: [0x00,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cb d0 05 fcpy z0.d, p0/m, #0.39062500 // CHECK-INST: fmov z0.d, p0/m, #0.39062500 // CHECK-ENCODING: [0x20,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cb d0 05 fcpy z0.d, p0/m, #0.40625000 // CHECK-INST: fmov z0.d, p0/m, #0.40625000 // CHECK-ENCODING: [0x40,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cb d0 05 fcpy z0.d, p0/m, #0.42187500 // CHECK-INST: fmov z0.d, p0/m, #0.42187500 // CHECK-ENCODING: [0x60,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cb d0 05 fcpy z0.d, p0/m, #0.43750000 // CHECK-INST: fmov z0.d, p0/m, #0.43750000 // CHECK-ENCODING: [0x80,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cb d0 05 fcpy z0.d, p0/m, #0.45312500 // CHECK-INST: fmov z0.d, p0/m, #0.45312500 // CHECK-ENCODING: [0xa0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cb d0 05 fcpy z0.d, p0/m, #0.46875000 // CHECK-INST: fmov z0.d, p0/m, #0.46875000 // CHECK-ENCODING: [0xc0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cb d0 05 fcpy z0.d, p0/m, #0.48437500 // CHECK-INST: fmov z0.d, p0/m, #0.48437500 // CHECK-ENCODING: [0xe0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb d0 05 fcpy z0.d, p0/m, #0.50000000 // CHECK-INST: fmov z0.d, p0/m, #0.50000000 // CHECK-ENCODING: [0x00,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc d0 05 fcpy z0.d, p0/m, #0.53125000 // CHECK-INST: fmov z0.d, p0/m, #0.53125000 // CHECK-ENCODING: [0x20,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cc d0 05 fcpy z0.d, p0/m, #0.56250000 // CHECK-INST: fmov z0.d, p0/m, #0.56250000 // CHECK-ENCODING: [0x40,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cc d0 05 fcpy z0.d, p0/m, #0.59375000 // CHECK-INST: fmov z0.d, p0/m, #0.59375000 // CHECK-ENCODING: [0x60,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cc d0 05 fcpy z0.d, p0/m, #0.62500000 // CHECK-INST: fmov z0.d, p0/m, #0.62500000 // CHECK-ENCODING: [0x80,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cc d0 05 fcpy z0.d, p0/m, #0.65625000 // CHECK-INST: fmov z0.d, p0/m, #0.65625000 // CHECK-ENCODING: [0xa0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cc d0 05 fcpy z0.d, p0/m, #0.68750000 // CHECK-INST: fmov z0.d, p0/m, #0.68750000 // CHECK-ENCODING: [0xc0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cc d0 05 fcpy z0.d, p0/m, #0.71875000 // CHECK-INST: fmov z0.d, p0/m, #0.71875000 // CHECK-ENCODING: [0xe0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cc d0 05 fcpy z0.d, p0/m, #0.75000000 // CHECK-INST: fmov z0.d, p0/m, #0.75000000 // CHECK-ENCODING: [0x00,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cd d0 05 fcpy z0.d, p0/m, #0.78125000 // CHECK-INST: fmov z0.d, p0/m, #0.78125000 // CHECK-ENCODING: [0x20,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cd d0 05 fcpy z0.d, p0/m, #0.81250000 // CHECK-INST: fmov z0.d, p0/m, #0.81250000 // CHECK-ENCODING: [0x40,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cd d0 05 fcpy z0.d, p0/m, #0.84375000 // CHECK-INST: fmov z0.d, p0/m, #0.84375000 // CHECK-ENCODING: [0x60,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cd d0 05 fcpy z0.d, p0/m, #0.87500000 // CHECK-INST: fmov z0.d, p0/m, #0.87500000 // CHECK-ENCODING: [0x80,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cd d0 05 fcpy z0.d, p0/m, #0.90625000 // CHECK-INST: fmov z0.d, p0/m, #0.90625000 // CHECK-ENCODING: [0xa0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cd d0 05 fcpy z0.d, p0/m, #0.93750000 // CHECK-INST: fmov z0.d, p0/m, #0.93750000 // CHECK-ENCODING: [0xc0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cd d0 05 fcpy z0.d, p0/m, #0.96875000 // CHECK-INST: fmov z0.d, p0/m, #0.96875000 // CHECK-ENCODING: [0xe0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cd d0 05 fcpy z0.d, p0/m, #1.00000000 // CHECK-INST: fmov z0.d, p0/m, #1.00000000 // CHECK-ENCODING: [0x00,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ce d0 05 fcpy z0.d, p0/m, #1.06250000 // CHECK-INST: fmov z0.d, p0/m, #1.06250000 // CHECK-ENCODING: [0x20,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ce d0 05 fcpy z0.d, p0/m, #1.12500000 // CHECK-INST: fmov z0.d, p0/m, #1.12500000 // CHECK-ENCODING: [0x40,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ce d0 05 fcpy z0.d, p0/m, #1.18750000 // CHECK-INST: fmov z0.d, p0/m, #1.18750000 // CHECK-ENCODING: [0x60,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ce d0 05 fcpy z0.d, p0/m, #1.25000000 // CHECK-INST: fmov z0.d, p0/m, #1.25000000 // CHECK-ENCODING: [0x80,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ce d0 05 fcpy z0.d, p0/m, #1.31250000 // CHECK-INST: fmov z0.d, p0/m, #1.31250000 // CHECK-ENCODING: [0xa0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ce d0 05 fcpy z0.d, p0/m, #1.37500000 // CHECK-INST: fmov z0.d, p0/m, #1.37500000 // CHECK-ENCODING: [0xc0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ce d0 05 fcpy z0.d, p0/m, #1.43750000 // CHECK-INST: fmov z0.d, p0/m, #1.43750000 // CHECK-ENCODING: [0xe0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ce d0 05 fcpy z0.d, p0/m, #1.50000000 // CHECK-INST: fmov z0.d, p0/m, #1.50000000 // CHECK-ENCODING: [0x00,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cf d0 05 fcpy z0.d, p0/m, #1.56250000 // CHECK-INST: fmov z0.d, p0/m, #1.56250000 // CHECK-ENCODING: [0x20,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cf d0 05 fcpy z0.d, p0/m, #1.62500000 // CHECK-INST: fmov z0.d, p0/m, #1.62500000 // CHECK-ENCODING: [0x40,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cf d0 05 fcpy z0.d, p0/m, #1.68750000 // CHECK-INST: fmov z0.d, p0/m, #1.68750000 // CHECK-ENCODING: [0x60,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cf d0 05 fcpy z0.d, p0/m, #1.75000000 // CHECK-INST: fmov z0.d, p0/m, #1.75000000 // CHECK-ENCODING: [0x80,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cf d0 05 fcpy z0.d, p0/m, #1.81250000 // CHECK-INST: fmov z0.d, p0/m, #1.81250000 // CHECK-ENCODING: [0xa0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cf d0 05 fcpy z0.d, p0/m, #1.87500000 // CHECK-INST: fmov z0.d, p0/m, #1.87500000 // CHECK-ENCODING: [0xc0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cf d0 05 fcpy z0.d, p0/m, #1.93750000 // CHECK-INST: fmov z0.d, p0/m, #1.93750000 // CHECK-ENCODING: [0xe0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf d0 05 fcpy z0.d, p0/m, #2.00000000 // CHECK-INST: fmov z0.d, p0/m, #2.00000000 // CHECK-ENCODING: [0x00,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 d0 05 fcpy z0.d, p0/m, #2.12500000 // CHECK-INST: fmov z0.d, p0/m, #2.12500000 // CHECK-ENCODING: [0x20,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c0 d0 05 fcpy z0.d, p0/m, #2.25000000 // CHECK-INST: fmov z0.d, p0/m, #2.25000000 // CHECK-ENCODING: [0x40,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c0 d0 05 fcpy z0.d, p0/m, #2.37500000 // CHECK-INST: fmov z0.d, p0/m, #2.37500000 // CHECK-ENCODING: [0x60,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c0 d0 05 fcpy z0.d, p0/m, #2.50000000 // CHECK-INST: fmov z0.d, p0/m, #2.50000000 // CHECK-ENCODING: [0x80,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c0 d0 05 fcpy z0.d, p0/m, #2.62500000 // CHECK-INST: fmov z0.d, p0/m, #2.62500000 // CHECK-ENCODING: [0xa0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c0 d0 05 fcpy z0.d, p0/m, #2.75000000 // CHECK-INST: fmov z0.d, p0/m, #2.75000000 // CHECK-ENCODING: [0xc0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c0 d0 05 fcpy z0.d, p0/m, #2.87500000 // CHECK-INST: fmov z0.d, p0/m, #2.87500000 // CHECK-ENCODING: [0xe0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c0 d0 05 fcpy z0.d, p0/m, #3.00000000 // CHECK-INST: fmov z0.d, p0/m, #3.00000000 // CHECK-ENCODING: [0x00,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c1 d0 05 fcpy z0.d, p0/m, #3.12500000 // CHECK-INST: fmov z0.d, p0/m, #3.12500000 // CHECK-ENCODING: [0x20,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c1 d0 05 fcpy z0.d, p0/m, #3.25000000 // CHECK-INST: fmov z0.d, p0/m, #3.25000000 // CHECK-ENCODING: [0x40,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c1 d0 05 fcpy z0.d, p0/m, #3.37500000 // CHECK-INST: fmov z0.d, p0/m, #3.37500000 // CHECK-ENCODING: [0x60,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c1 d0 05 fcpy z0.d, p0/m, #3.50000000 // CHECK-INST: fmov z0.d, p0/m, #3.50000000 // CHECK-ENCODING: [0x80,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c1 d0 05 fcpy z0.d, p0/m, #3.62500000 // CHECK-INST: fmov z0.d, p0/m, #3.62500000 // CHECK-ENCODING: [0xa0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c1 d0 05 fcpy z0.d, p0/m, #3.75000000 // CHECK-INST: fmov z0.d, p0/m, #3.75000000 // CHECK-ENCODING: [0xc0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c1 d0 05 fcpy z0.d, p0/m, #3.87500000 // CHECK-INST: fmov z0.d, p0/m, #3.87500000 // CHECK-ENCODING: [0xe0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c1 d0 05 fcpy z0.d, p0/m, #4.00000000 // CHECK-INST: fmov z0.d, p0/m, #4.00000000 // CHECK-ENCODING: [0x00,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c2 d0 05 fcpy z0.d, p0/m, #4.25000000 // CHECK-INST: fmov z0.d, p0/m, #4.25000000 // CHECK-ENCODING: [0x20,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c2 d0 05 fcpy z0.d, p0/m, #4.50000000 // CHECK-INST: fmov z0.d, p0/m, #4.50000000 // CHECK-ENCODING: [0x40,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c2 d0 05 fcpy z0.d, p0/m, #4.75000000 // CHECK-INST: fmov z0.d, p0/m, #4.75000000 // CHECK-ENCODING: [0x60,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c2 d0 05 fcpy z0.d, p0/m, #5.00000000 // CHECK-INST: fmov z0.d, p0/m, #5.00000000 // CHECK-ENCODING: [0x80,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c2 d0 05 fcpy z0.d, p0/m, #5.25000000 // CHECK-INST: fmov z0.d, p0/m, #5.25000000 // CHECK-ENCODING: [0xa0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c2 d0 05 fcpy z0.d, p0/m, #5.50000000 // CHECK-INST: fmov z0.d, p0/m, #5.50000000 // CHECK-ENCODING: [0xc0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c2 d0 05 fcpy z0.d, p0/m, #5.75000000 // CHECK-INST: fmov z0.d, p0/m, #5.75000000 // CHECK-ENCODING: [0xe0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c2 d0 05 fcpy z0.d, p0/m, #6.00000000 // CHECK-INST: fmov z0.d, p0/m, #6.00000000 // CHECK-ENCODING: [0x00,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c3 d0 05 fcpy z0.d, p0/m, #6.25000000 // CHECK-INST: fmov z0.d, p0/m, #6.25000000 // CHECK-ENCODING: [0x20,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c3 d0 05 fcpy z0.d, p0/m, #6.50000000 // CHECK-INST: fmov z0.d, p0/m, #6.50000000 // CHECK-ENCODING: [0x40,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c3 d0 05 fcpy z0.d, p0/m, #6.75000000 // CHECK-INST: fmov z0.d, p0/m, #6.75000000 // CHECK-ENCODING: [0x60,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c3 d0 05 fcpy z0.d, p0/m, #7.00000000 // CHECK-INST: fmov z0.d, p0/m, #7.00000000 // CHECK-ENCODING: [0x80,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c3 d0 05 fcpy z0.d, p0/m, #7.25000000 // CHECK-INST: fmov z0.d, p0/m, #7.25000000 // CHECK-ENCODING: [0xa0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c3 d0 05 fcpy z0.d, p0/m, #7.50000000 // CHECK-INST: fmov z0.d, p0/m, #7.50000000 // CHECK-ENCODING: [0xc0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c3 d0 05 fcpy z0.d, p0/m, #7.75000000 // CHECK-INST: fmov z0.d, p0/m, #7.75000000 // CHECK-ENCODING: [0xe0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 d0 05 fcpy z0.d, p0/m, #8.00000000 // CHECK-INST: fmov z0.d, p0/m, #8.00000000 // CHECK-ENCODING: [0x00,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 d0 05 fcpy z0.d, p0/m, #8.50000000 // CHECK-INST: fmov z0.d, p0/m, #8.50000000 // CHECK-ENCODING: [0x20,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c4 d0 05 fcpy z0.d, p0/m, #9.00000000 // CHECK-INST: fmov z0.d, p0/m, #9.00000000 // CHECK-ENCODING: [0x40,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c4 d0 05 fcpy z0.d, p0/m, #9.50000000 // CHECK-INST: fmov z0.d, p0/m, #9.50000000 // CHECK-ENCODING: [0x60,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c4 d0 05 fcpy z0.d, p0/m, #10.00000000 // CHECK-INST: fmov z0.d, p0/m, #10.00000000 // CHECK-ENCODING: [0x80,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c4 d0 05 fcpy z0.d, p0/m, #10.50000000 // CHECK-INST: fmov z0.d, p0/m, #10.50000000 // CHECK-ENCODING: [0xa0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c4 d0 05 fcpy z0.d, p0/m, #11.00000000 // CHECK-INST: fmov z0.d, p0/m, #11.00000000 // CHECK-ENCODING: [0xc0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c4 d0 05 fcpy z0.d, p0/m, #11.50000000 // CHECK-INST: fmov z0.d, p0/m, #11.50000000 // CHECK-ENCODING: [0xe0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c4 d0 05 fcpy z0.d, p0/m, #12.00000000 // CHECK-INST: fmov z0.d, p0/m, #12.00000000 // CHECK-ENCODING: [0x00,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c5 d0 05 fcpy z0.d, p0/m, #12.50000000 // CHECK-INST: fmov z0.d, p0/m, #12.50000000 // CHECK-ENCODING: [0x20,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c5 d0 05 fcpy z0.d, p0/m, #13.00000000 // CHECK-INST: fmov z0.d, p0/m, #13.00000000 // CHECK-ENCODING: [0x40,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c5 d0 05 fcpy z0.d, p0/m, #13.50000000 // CHECK-INST: fmov z0.d, p0/m, #13.50000000 // CHECK-ENCODING: [0x60,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c5 d0 05 fcpy z0.d, p0/m, #14.00000000 // CHECK-INST: fmov z0.d, p0/m, #14.00000000 // CHECK-ENCODING: [0x80,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c5 d0 05 fcpy z0.d, p0/m, #14.50000000 // CHECK-INST: fmov z0.d, p0/m, #14.50000000 // CHECK-ENCODING: [0xa0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c5 d0 05 fcpy z0.d, p0/m, #15.00000000 // CHECK-INST: fmov z0.d, p0/m, #15.00000000 // CHECK-ENCODING: [0xc0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c5 d0 05 fcpy z0.d, p0/m, #15.50000000 // CHECK-INST: fmov z0.d, p0/m, #15.50000000 // CHECK-ENCODING: [0xe0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 d0 05 fcpy z0.d, p0/m, #16.00000000 // CHECK-INST: fmov z0.d, p0/m, #16.00000000 // CHECK-ENCODING: [0x00,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c6 d0 05 fcpy z0.d, p0/m, #17.00000000 // CHECK-INST: fmov z0.d, p0/m, #17.00000000 // CHECK-ENCODING: [0x20,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c6 d0 05 fcpy z0.d, p0/m, #18.00000000 // CHECK-INST: fmov z0.d, p0/m, #18.00000000 // CHECK-ENCODING: [0x40,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c6 d0 05 fcpy z0.d, p0/m, #19.00000000 // CHECK-INST: fmov z0.d, p0/m, #19.00000000 // CHECK-ENCODING: [0x60,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c6 d0 05 fcpy z0.d, p0/m, #20.00000000 // CHECK-INST: fmov z0.d, p0/m, #20.00000000 // CHECK-ENCODING: [0x80,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c6 d0 05 fcpy z0.d, p0/m, #21.00000000 // CHECK-INST: fmov z0.d, p0/m, #21.00000000 // CHECK-ENCODING: [0xa0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c6 d0 05 fcpy z0.d, p0/m, #22.00000000 // CHECK-INST: fmov z0.d, p0/m, #22.00000000 // CHECK-ENCODING: [0xc0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c6 d0 05 fcpy z0.d, p0/m, #23.00000000 // CHECK-INST: fmov z0.d, p0/m, #23.00000000 // CHECK-ENCODING: [0xe0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c6 d0 05 fcpy z0.d, p0/m, #24.00000000 // CHECK-INST: fmov z0.d, p0/m, #24.00000000 // CHECK-ENCODING: [0x00,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c7 d0 05 fcpy z0.d, p0/m, #25.00000000 // CHECK-INST: fmov z0.d, p0/m, #25.00000000 // CHECK-ENCODING: [0x20,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c7 d0 05 fcpy z0.d, p0/m, #26.00000000 // CHECK-INST: fmov z0.d, p0/m, #26.00000000 // CHECK-ENCODING: [0x40,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c7 d0 05 fcpy z0.d, p0/m, #27.00000000 // CHECK-INST: fmov z0.d, p0/m, #27.00000000 // CHECK-ENCODING: [0x60,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c7 d0 05 fcpy z0.d, p0/m, #28.00000000 // CHECK-INST: fmov z0.d, p0/m, #28.00000000 // CHECK-ENCODING: [0x80,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c7 d0 05 fcpy z0.d, p0/m, #29.00000000 // CHECK-INST: fmov z0.d, p0/m, #29.00000000 // CHECK-ENCODING: [0xa0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c7 d0 05 fcpy z0.d, p0/m, #30.00000000 // CHECK-INST: fmov z0.d, p0/m, #30.00000000 // CHECK-ENCODING: [0xc0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c7 d0 05 fcpy z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 @@ -1564,23 +1564,23 @@ fcpy z0.d, p0/m, #31.00000000 movprfx z0.d, p0/z, z7.d // CHECK-INST: movprfx z0.d, p0/z, z7.d // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 d0 04 fcpy z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fcpy z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 diff --git a/llvm/test/MC/AArch64/SVE/fcvt.s b/llvm/test/MC/AArch64/SVE/fcvt.s index cc9f7722bee39..d68d4f9494506 100644 --- a/llvm/test/MC/AArch64/SVE/fcvt.s +++ b/llvm/test/MC/AArch64/SVE/fcvt.s @@ -12,37 +12,37 @@ fcvt z0.h, p0/m, z0.s // CHECK-INST: fcvt z0.h, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x88,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 88 65 fcvt z0.h, p0/m, z0.d // CHECK-INST: fcvt z0.h, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xc8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c8 65 fcvt z0.s, p0/m, z0.h // CHECK-INST: fcvt z0.s, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x89,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 89 65 fcvt z0.s, p0/m, z0.d // CHECK-INST: fcvt z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xca,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 ca 65 fcvt z0.d, p0/m, z0.h // CHECK-INST: fcvt z0.d, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0xc9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c9 65 fcvt z0.d, p0/m, z0.s // CHECK-INST: fcvt z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xcb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 cb 65 @@ -52,23 +52,23 @@ fcvt z0.d, p0/m, z0.s movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 fcvt z5.d, p0/m, z0.s // CHECK-INST: fcvt z5.d, p0/m, z0.s // CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 cb 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 fcvt z5.d, p0/m, z0.s // CHECK-INST: fcvt z5.d, p0/m, z0.s // CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 cb 65 diff --git a/llvm/test/MC/AArch64/SVE/fcvtzs.s b/llvm/test/MC/AArch64/SVE/fcvtzs.s index a25f9ec13d03e..84ad36694ce80 100644 --- a/llvm/test/MC/AArch64/SVE/fcvtzs.s +++ b/llvm/test/MC/AArch64/SVE/fcvtzs.s @@ -12,43 +12,43 @@ fcvtzs z0.h, p0/m, z0.h // CHECK-INST: fcvtzs z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5a 65 fcvtzs z0.s, p0/m, z0.h // CHECK-INST: fcvtzs z0.s, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5c 65 fcvtzs z0.s, p0/m, z0.s // CHECK-INST: fcvtzs z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x9c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 9c 65 fcvtzs z0.s, p0/m, z0.d // CHECK-INST: fcvtzs z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd8,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d8 65 fcvtzs z0.d, p0/m, z0.h // CHECK-INST: fcvtzs z0.d, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5e 65 fcvtzs z0.d, p0/m, z0.s // CHECK-INST: fcvtzs z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xdc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 dc 65 fcvtzs z0.d, p0/m, z0.d // CHECK-INST: fcvtzs z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 de 65 @@ -58,23 +58,23 @@ fcvtzs z0.d, p0/m, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 fcvtzs z5.d, p0/m, z0.d // CHECK-INST: fcvtzs z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 de 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 fcvtzs z5.d, p0/m, z0.d // CHECK-INST: fcvtzs z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 de 65 diff --git a/llvm/test/MC/AArch64/SVE/fcvtzu.s b/llvm/test/MC/AArch64/SVE/fcvtzu.s index 9ea5dde0021ad..bcab336eb3f8e 100644 --- a/llvm/test/MC/AArch64/SVE/fcvtzu.s +++ b/llvm/test/MC/AArch64/SVE/fcvtzu.s @@ -12,43 +12,43 @@ fcvtzu z0.h, p0/m, z0.h // CHECK-INST: fcvtzu z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5b 65 fcvtzu z0.s, p0/m, z0.h // CHECK-INST: fcvtzu z0.s, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5d 65 fcvtzu z0.s, p0/m, z0.s // CHECK-INST: fcvtzu z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x9d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 9d 65 fcvtzu z0.s, p0/m, z0.d // CHECK-INST: fcvtzu z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d9 65 fcvtzu z0.d, p0/m, z0.h // CHECK-INST: fcvtzu z0.d, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 5f 65 fcvtzu z0.d, p0/m, z0.s // CHECK-INST: fcvtzu z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xdd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 dd 65 fcvtzu z0.d, p0/m, z0.d // CHECK-INST: fcvtzu z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 df 65 @@ -58,23 +58,23 @@ fcvtzu z0.d, p0/m, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 fcvtzu z5.d, p0/m, z0.d // CHECK-INST: fcvtzu z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 df 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 fcvtzu z5.d, p0/m, z0.d // CHECK-INST: fcvtzu z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 df 65 diff --git a/llvm/test/MC/AArch64/SVE/fdiv.s b/llvm/test/MC/AArch64/SVE/fdiv.s index 32477fbe8162d..8b137bdeb7b6c 100644 --- a/llvm/test/MC/AArch64/SVE/fdiv.s +++ b/llvm/test/MC/AArch64/SVE/fdiv.s @@ -12,19 +12,19 @@ fdiv z0.h, p7/m, z0.h, z31.h // CHECK-INST: fdiv z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x4d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 4d 65 fdiv z0.s, p7/m, z0.s, z31.s // CHECK-INST: fdiv z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x8d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 8d 65 fdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cd 65 @@ -34,23 +34,23 @@ fdiv z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cd 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cd 65 diff --git a/llvm/test/MC/AArch64/SVE/fdivr.s b/llvm/test/MC/AArch64/SVE/fdivr.s index e1b33ff6ec213..864e46271710b 100644 --- a/llvm/test/MC/AArch64/SVE/fdivr.s +++ b/llvm/test/MC/AArch64/SVE/fdivr.s @@ -12,19 +12,19 @@ fdivr z0.h, p7/m, z0.h, z31.h // CHECK-INST: fdivr z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x4c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 4c 65 fdivr z0.s, p7/m, z0.s, z31.s // CHECK-INST: fdivr z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x8c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 8c 65 fdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cc 65 @@ -34,23 +34,23 @@ fdivr z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cc 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f cc 65 diff --git a/llvm/test/MC/AArch64/SVE/fdup.s b/llvm/test/MC/AArch64/SVE/fdup.s index 39413e7fad6d2..7e68f5aaf72b8 100644 --- a/llvm/test/MC/AArch64/SVE/fdup.s +++ b/llvm/test/MC/AArch64/SVE/fdup.s @@ -12,1547 +12,1547 @@ fdup z0.h, #-0.12500000 // CHECK-INST: fmov z0.h, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x79,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 79 25 fdup z0.s, #-0.12500000 // CHECK-INST: fmov z0.s, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xb9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 b9 25 fdup z0.d, #-0.12500000 // CHECK-INST: fmov z0.d, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 f9 25 fdup z0.d, #-0.13281250 // CHECK-INST: fmov z0.d, #-0.13281250 // CHECK-ENCODING: [0x20,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d8 f9 25 fdup z0.d, #-0.14062500 // CHECK-INST: fmov z0.d, #-0.14062500 // CHECK-ENCODING: [0x40,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d8 f9 25 fdup z0.d, #-0.14843750 // CHECK-INST: fmov z0.d, #-0.14843750 // CHECK-ENCODING: [0x60,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d8 f9 25 fdup z0.d, #-0.15625000 // CHECK-INST: fmov z0.d, #-0.15625000 // CHECK-ENCODING: [0x80,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d8 f9 25 fdup z0.d, #-0.16406250 // CHECK-INST: fmov z0.d, #-0.16406250 // CHECK-ENCODING: [0xa0,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d8 f9 25 fdup z0.d, #-0.17187500 // CHECK-INST: fmov z0.d, #-0.17187500 // CHECK-ENCODING: [0xc0,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d8 f9 25 fdup z0.d, #-0.17968750 // CHECK-INST: fmov z0.d, #-0.17968750 // CHECK-ENCODING: [0xe0,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d8 f9 25 fdup z0.d, #-0.18750000 // CHECK-INST: fmov z0.d, #-0.18750000 // CHECK-ENCODING: [0x00,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d9 f9 25 fdup z0.d, #-0.19531250 // CHECK-INST: fmov z0.d, #-0.19531250 // CHECK-ENCODING: [0x20,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d9 f9 25 fdup z0.d, #-0.20312500 // CHECK-INST: fmov z0.d, #-0.20312500 // CHECK-ENCODING: [0x40,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d9 f9 25 fdup z0.d, #-0.21093750 // CHECK-INST: fmov z0.d, #-0.21093750 // CHECK-ENCODING: [0x60,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d9 f9 25 fdup z0.d, #-0.21875000 // CHECK-INST: fmov z0.d, #-0.21875000 // CHECK-ENCODING: [0x80,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d9 f9 25 fdup z0.d, #-0.22656250 // CHECK-INST: fmov z0.d, #-0.22656250 // CHECK-ENCODING: [0xa0,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d9 f9 25 fdup z0.d, #-0.23437500 // CHECK-INST: fmov z0.d, #-0.23437500 // CHECK-ENCODING: [0xc0,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d9 f9 25 fdup z0.d, #-0.24218750 // CHECK-INST: fmov z0.d, #-0.24218750 // CHECK-ENCODING: [0xe0,0xd9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d9 f9 25 fdup z0.d, #-0.25000000 // CHECK-INST: fmov z0.d, #-0.25000000 // CHECK-ENCODING: [0x00,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 da f9 25 fdup z0.d, #-0.26562500 // CHECK-INST: fmov z0.d, #-0.26562500 // CHECK-ENCODING: [0x20,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 da f9 25 fdup z0.d, #-0.28125000 // CHECK-INST: fmov z0.d, #-0.28125000 // CHECK-ENCODING: [0x40,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 da f9 25 fdup z0.d, #-0.29687500 // CHECK-INST: fmov z0.d, #-0.29687500 // CHECK-ENCODING: [0x60,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 da f9 25 fdup z0.d, #-0.31250000 // CHECK-INST: fmov z0.d, #-0.31250000 // CHECK-ENCODING: [0x80,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 da f9 25 fdup z0.d, #-0.32812500 // CHECK-INST: fmov z0.d, #-0.32812500 // CHECK-ENCODING: [0xa0,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 da f9 25 fdup z0.d, #-0.34375000 // CHECK-INST: fmov z0.d, #-0.34375000 // CHECK-ENCODING: [0xc0,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 da f9 25 fdup z0.d, #-0.35937500 // CHECK-INST: fmov z0.d, #-0.35937500 // CHECK-ENCODING: [0xe0,0xda,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 da f9 25 fdup z0.d, #-0.37500000 // CHECK-INST: fmov z0.d, #-0.37500000 // CHECK-ENCODING: [0x00,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 db f9 25 fdup z0.d, #-0.39062500 // CHECK-INST: fmov z0.d, #-0.39062500 // CHECK-ENCODING: [0x20,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 db f9 25 fdup z0.d, #-0.40625000 // CHECK-INST: fmov z0.d, #-0.40625000 // CHECK-ENCODING: [0x40,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 db f9 25 fdup z0.d, #-0.42187500 // CHECK-INST: fmov z0.d, #-0.42187500 // CHECK-ENCODING: [0x60,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 db f9 25 fdup z0.d, #-0.43750000 // CHECK-INST: fmov z0.d, #-0.43750000 // CHECK-ENCODING: [0x80,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 db f9 25 fdup z0.d, #-0.45312500 // CHECK-INST: fmov z0.d, #-0.45312500 // CHECK-ENCODING: [0xa0,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 db f9 25 fdup z0.d, #-0.46875000 // CHECK-INST: fmov z0.d, #-0.46875000 // CHECK-ENCODING: [0xc0,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 db f9 25 fdup z0.d, #-0.48437500 // CHECK-INST: fmov z0.d, #-0.48437500 // CHECK-ENCODING: [0xe0,0xdb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 db f9 25 fdup z0.d, #-0.50000000 // CHECK-INST: fmov z0.d, #-0.50000000 // CHECK-ENCODING: [0x00,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dc f9 25 fdup z0.d, #-0.53125000 // CHECK-INST: fmov z0.d, #-0.53125000 // CHECK-ENCODING: [0x20,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc f9 25 fdup z0.d, #-0.56250000 // CHECK-INST: fmov z0.d, #-0.56250000 // CHECK-ENCODING: [0x40,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dc f9 25 fdup z0.d, #-0.59375000 // CHECK-INST: fmov z0.d, #-0.59375000 // CHECK-ENCODING: [0x60,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dc f9 25 fdup z0.d, #-0.62500000 // CHECK-INST: fmov z0.d, #-0.62500000 // CHECK-ENCODING: [0x80,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dc f9 25 fdup z0.d, #-0.65625000 // CHECK-INST: fmov z0.d, #-0.65625000 // CHECK-ENCODING: [0xa0,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dc f9 25 fdup z0.d, #-0.68750000 // CHECK-INST: fmov z0.d, #-0.68750000 // CHECK-ENCODING: [0xc0,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dc f9 25 fdup z0.d, #-0.71875000 // CHECK-INST: fmov z0.d, #-0.71875000 // CHECK-ENCODING: [0xe0,0xdc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dc f9 25 fdup z0.d, #-0.75000000 // CHECK-INST: fmov z0.d, #-0.75000000 // CHECK-ENCODING: [0x00,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dd f9 25 fdup z0.d, #-0.78125000 // CHECK-INST: fmov z0.d, #-0.78125000 // CHECK-ENCODING: [0x20,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dd f9 25 fdup z0.d, #-0.81250000 // CHECK-INST: fmov z0.d, #-0.81250000 // CHECK-ENCODING: [0x40,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dd f9 25 fdup z0.d, #-0.84375000 // CHECK-INST: fmov z0.d, #-0.84375000 // CHECK-ENCODING: [0x60,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dd f9 25 fdup z0.d, #-0.87500000 // CHECK-INST: fmov z0.d, #-0.87500000 // CHECK-ENCODING: [0x80,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dd f9 25 fdup z0.d, #-0.90625000 // CHECK-INST: fmov z0.d, #-0.90625000 // CHECK-ENCODING: [0xa0,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dd f9 25 fdup z0.d, #-0.93750000 // CHECK-INST: fmov z0.d, #-0.93750000 // CHECK-ENCODING: [0xc0,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dd f9 25 fdup z0.d, #-0.96875000 // CHECK-INST: fmov z0.d, #-0.96875000 // CHECK-ENCODING: [0xe0,0xdd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dd f9 25 fdup z0.d, #-1.00000000 // CHECK-INST: fmov z0.d, #-1.00000000 // CHECK-ENCODING: [0x00,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 de f9 25 fdup z0.d, #-1.06250000 // CHECK-INST: fmov z0.d, #-1.06250000 // CHECK-ENCODING: [0x20,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 de f9 25 fdup z0.d, #-1.12500000 // CHECK-INST: fmov z0.d, #-1.12500000 // CHECK-ENCODING: [0x40,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 de f9 25 fdup z0.d, #-1.18750000 // CHECK-INST: fmov z0.d, #-1.18750000 // CHECK-ENCODING: [0x60,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 de f9 25 fdup z0.d, #-1.25000000 // CHECK-INST: fmov z0.d, #-1.25000000 // CHECK-ENCODING: [0x80,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 de f9 25 fdup z0.d, #-1.31250000 // CHECK-INST: fmov z0.d, #-1.31250000 // CHECK-ENCODING: [0xa0,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 de f9 25 fdup z0.d, #-1.37500000 // CHECK-INST: fmov z0.d, #-1.37500000 // CHECK-ENCODING: [0xc0,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 de f9 25 fdup z0.d, #-1.43750000 // CHECK-INST: fmov z0.d, #-1.43750000 // CHECK-ENCODING: [0xe0,0xde,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 de f9 25 fdup z0.d, #-1.50000000 // CHECK-INST: fmov z0.d, #-1.50000000 // CHECK-ENCODING: [0x00,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 df f9 25 fdup z0.d, #-1.56250000 // CHECK-INST: fmov z0.d, #-1.56250000 // CHECK-ENCODING: [0x20,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 df f9 25 fdup z0.d, #-1.62500000 // CHECK-INST: fmov z0.d, #-1.62500000 // CHECK-ENCODING: [0x40,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 df f9 25 fdup z0.d, #-1.68750000 // CHECK-INST: fmov z0.d, #-1.68750000 // CHECK-ENCODING: [0x60,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 df f9 25 fdup z0.d, #-1.75000000 // CHECK-INST: fmov z0.d, #-1.75000000 // CHECK-ENCODING: [0x80,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 df f9 25 fdup z0.d, #-1.81250000 // CHECK-INST: fmov z0.d, #-1.81250000 // CHECK-ENCODING: [0xa0,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 df f9 25 fdup z0.d, #-1.87500000 // CHECK-INST: fmov z0.d, #-1.87500000 // CHECK-ENCODING: [0xc0,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 df f9 25 fdup z0.d, #-1.93750000 // CHECK-INST: fmov z0.d, #-1.93750000 // CHECK-ENCODING: [0xe0,0xdf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df f9 25 fdup z0.d, #-2.00000000 // CHECK-INST: fmov z0.d, #-2.00000000 // CHECK-ENCODING: [0x00,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 f9 25 fdup z0.d, #-2.12500000 // CHECK-INST: fmov z0.d, #-2.12500000 // CHECK-ENCODING: [0x20,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d0 f9 25 fdup z0.d, #-2.25000000 // CHECK-INST: fmov z0.d, #-2.25000000 // CHECK-ENCODING: [0x40,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d0 f9 25 fdup z0.d, #-2.37500000 // CHECK-INST: fmov z0.d, #-2.37500000 // CHECK-ENCODING: [0x60,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d0 f9 25 fdup z0.d, #-2.50000000 // CHECK-INST: fmov z0.d, #-2.50000000 // CHECK-ENCODING: [0x80,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d0 f9 25 fdup z0.d, #-2.62500000 // CHECK-INST: fmov z0.d, #-2.62500000 // CHECK-ENCODING: [0xa0,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d0 f9 25 fdup z0.d, #-2.75000000 // CHECK-INST: fmov z0.d, #-2.75000000 // CHECK-ENCODING: [0xc0,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d0 f9 25 fdup z0.d, #-2.87500000 // CHECK-INST: fmov z0.d, #-2.87500000 // CHECK-ENCODING: [0xe0,0xd0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d0 f9 25 fdup z0.d, #-3.00000000 // CHECK-INST: fmov z0.d, #-3.00000000 // CHECK-ENCODING: [0x00,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d1 f9 25 fdup z0.d, #-3.12500000 // CHECK-INST: fmov z0.d, #-3.12500000 // CHECK-ENCODING: [0x20,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d1 f9 25 fdup z0.d, #-3.25000000 // CHECK-INST: fmov z0.d, #-3.25000000 // CHECK-ENCODING: [0x40,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d1 f9 25 fdup z0.d, #-3.37500000 // CHECK-INST: fmov z0.d, #-3.37500000 // CHECK-ENCODING: [0x60,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d1 f9 25 fdup z0.d, #-3.50000000 // CHECK-INST: fmov z0.d, #-3.50000000 // CHECK-ENCODING: [0x80,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d1 f9 25 fdup z0.d, #-3.62500000 // CHECK-INST: fmov z0.d, #-3.62500000 // CHECK-ENCODING: [0xa0,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d1 f9 25 fdup z0.d, #-3.75000000 // CHECK-INST: fmov z0.d, #-3.75000000 // CHECK-ENCODING: [0xc0,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d1 f9 25 fdup z0.d, #-3.87500000 // CHECK-INST: fmov z0.d, #-3.87500000 // CHECK-ENCODING: [0xe0,0xd1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d1 f9 25 fdup z0.d, #-4.00000000 // CHECK-INST: fmov z0.d, #-4.00000000 // CHECK-ENCODING: [0x00,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d2 f9 25 fdup z0.d, #-4.25000000 // CHECK-INST: fmov z0.d, #-4.25000000 // CHECK-ENCODING: [0x20,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d2 f9 25 fdup z0.d, #-4.50000000 // CHECK-INST: fmov z0.d, #-4.50000000 // CHECK-ENCODING: [0x40,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d2 f9 25 fdup z0.d, #-4.75000000 // CHECK-INST: fmov z0.d, #-4.75000000 // CHECK-ENCODING: [0x60,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d2 f9 25 fdup z0.d, #-5.00000000 // CHECK-INST: fmov z0.d, #-5.00000000 // CHECK-ENCODING: [0x80,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d2 f9 25 fdup z0.d, #-5.25000000 // CHECK-INST: fmov z0.d, #-5.25000000 // CHECK-ENCODING: [0xa0,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d2 f9 25 fdup z0.d, #-5.50000000 // CHECK-INST: fmov z0.d, #-5.50000000 // CHECK-ENCODING: [0xc0,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d2 f9 25 fdup z0.d, #-5.75000000 // CHECK-INST: fmov z0.d, #-5.75000000 // CHECK-ENCODING: [0xe0,0xd2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d2 f9 25 fdup z0.d, #-6.00000000 // CHECK-INST: fmov z0.d, #-6.00000000 // CHECK-ENCODING: [0x00,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d3 f9 25 fdup z0.d, #-6.25000000 // CHECK-INST: fmov z0.d, #-6.25000000 // CHECK-ENCODING: [0x20,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d3 f9 25 fdup z0.d, #-6.50000000 // CHECK-INST: fmov z0.d, #-6.50000000 // CHECK-ENCODING: [0x40,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d3 f9 25 fdup z0.d, #-6.75000000 // CHECK-INST: fmov z0.d, #-6.75000000 // CHECK-ENCODING: [0x60,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d3 f9 25 fdup z0.d, #-7.00000000 // CHECK-INST: fmov z0.d, #-7.00000000 // CHECK-ENCODING: [0x80,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d3 f9 25 fdup z0.d, #-7.25000000 // CHECK-INST: fmov z0.d, #-7.25000000 // CHECK-ENCODING: [0xa0,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d3 f9 25 fdup z0.d, #-7.50000000 // CHECK-INST: fmov z0.d, #-7.50000000 // CHECK-ENCODING: [0xc0,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d3 f9 25 fdup z0.d, #-7.75000000 // CHECK-INST: fmov z0.d, #-7.75000000 // CHECK-ENCODING: [0xe0,0xd3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d3 f9 25 fdup z0.d, #-8.00000000 // CHECK-INST: fmov z0.d, #-8.00000000 // CHECK-ENCODING: [0x00,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d4 f9 25 fdup z0.d, #-8.50000000 // CHECK-INST: fmov z0.d, #-8.50000000 // CHECK-ENCODING: [0x20,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d4 f9 25 fdup z0.d, #-9.00000000 // CHECK-INST: fmov z0.d, #-9.00000000 // CHECK-ENCODING: [0x40,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d4 f9 25 fdup z0.d, #-9.50000000 // CHECK-INST: fmov z0.d, #-9.50000000 // CHECK-ENCODING: [0x60,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d4 f9 25 fdup z0.d, #-10.00000000 // CHECK-INST: fmov z0.d, #-10.00000000 // CHECK-ENCODING: [0x80,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d4 f9 25 fdup z0.d, #-10.50000000 // CHECK-INST: fmov z0.d, #-10.50000000 // CHECK-ENCODING: [0xa0,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d4 f9 25 fdup z0.d, #-11.00000000 // CHECK-INST: fmov z0.d, #-11.00000000 // CHECK-ENCODING: [0xc0,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d4 f9 25 fdup z0.d, #-11.50000000 // CHECK-INST: fmov z0.d, #-11.50000000 // CHECK-ENCODING: [0xe0,0xd4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d4 f9 25 fdup z0.d, #-12.00000000 // CHECK-INST: fmov z0.d, #-12.00000000 // CHECK-ENCODING: [0x00,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d5 f9 25 fdup z0.d, #-12.50000000 // CHECK-INST: fmov z0.d, #-12.50000000 // CHECK-ENCODING: [0x20,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d5 f9 25 fdup z0.d, #-13.00000000 // CHECK-INST: fmov z0.d, #-13.00000000 // CHECK-ENCODING: [0x40,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d5 f9 25 fdup z0.d, #-13.50000000 // CHECK-INST: fmov z0.d, #-13.50000000 // CHECK-ENCODING: [0x60,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d5 f9 25 fdup z0.d, #-14.00000000 // CHECK-INST: fmov z0.d, #-14.00000000 // CHECK-ENCODING: [0x80,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d5 f9 25 fdup z0.d, #-14.50000000 // CHECK-INST: fmov z0.d, #-14.50000000 // CHECK-ENCODING: [0xa0,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d5 f9 25 fdup z0.d, #-15.00000000 // CHECK-INST: fmov z0.d, #-15.00000000 // CHECK-ENCODING: [0xc0,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d5 f9 25 fdup z0.d, #-15.50000000 // CHECK-INST: fmov z0.d, #-15.50000000 // CHECK-ENCODING: [0xe0,0xd5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d5 f9 25 fdup z0.d, #-16.00000000 // CHECK-INST: fmov z0.d, #-16.00000000 // CHECK-ENCODING: [0x00,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d6 f9 25 fdup z0.d, #-17.00000000 // CHECK-INST: fmov z0.d, #-17.00000000 // CHECK-ENCODING: [0x20,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d6 f9 25 fdup z0.d, #-18.00000000 // CHECK-INST: fmov z0.d, #-18.00000000 // CHECK-ENCODING: [0x40,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d6 f9 25 fdup z0.d, #-19.00000000 // CHECK-INST: fmov z0.d, #-19.00000000 // CHECK-ENCODING: [0x60,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d6 f9 25 fdup z0.d, #-20.00000000 // CHECK-INST: fmov z0.d, #-20.00000000 // CHECK-ENCODING: [0x80,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d6 f9 25 fdup z0.d, #-21.00000000 // CHECK-INST: fmov z0.d, #-21.00000000 // CHECK-ENCODING: [0xa0,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d6 f9 25 fdup z0.d, #-22.00000000 // CHECK-INST: fmov z0.d, #-22.00000000 // CHECK-ENCODING: [0xc0,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d6 f9 25 fdup z0.d, #-23.00000000 // CHECK-INST: fmov z0.d, #-23.00000000 // CHECK-ENCODING: [0xe0,0xd6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d6 f9 25 fdup z0.d, #-24.00000000 // CHECK-INST: fmov z0.d, #-24.00000000 // CHECK-ENCODING: [0x00,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d7 f9 25 fdup z0.d, #-25.00000000 // CHECK-INST: fmov z0.d, #-25.00000000 // CHECK-ENCODING: [0x20,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d7 f9 25 fdup z0.d, #-26.00000000 // CHECK-INST: fmov z0.d, #-26.00000000 // CHECK-ENCODING: [0x40,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d7 f9 25 fdup z0.d, #-27.00000000 // CHECK-INST: fmov z0.d, #-27.00000000 // CHECK-ENCODING: [0x60,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d7 f9 25 fdup z0.d, #-28.00000000 // CHECK-INST: fmov z0.d, #-28.00000000 // CHECK-ENCODING: [0x80,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d7 f9 25 fdup z0.d, #-29.00000000 // CHECK-INST: fmov z0.d, #-29.00000000 // CHECK-ENCODING: [0xa0,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d7 f9 25 fdup z0.d, #-30.00000000 // CHECK-INST: fmov z0.d, #-30.00000000 // CHECK-ENCODING: [0xc0,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d7 f9 25 fdup z0.d, #-31.00000000 // CHECK-INST: fmov z0.d, #-31.00000000 // CHECK-ENCODING: [0xe0,0xd7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d7 f9 25 fdup z0.d, #0.12500000 // CHECK-INST: fmov z0.d, #0.12500000 // CHECK-ENCODING: [0x00,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 f9 25 fdup z0.d, #0.13281250 // CHECK-INST: fmov z0.d, #0.13281250 // CHECK-ENCODING: [0x20,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c8 f9 25 fdup z0.d, #0.14062500 // CHECK-INST: fmov z0.d, #0.14062500 // CHECK-ENCODING: [0x40,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c8 f9 25 fdup z0.d, #0.14843750 // CHECK-INST: fmov z0.d, #0.14843750 // CHECK-ENCODING: [0x60,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c8 f9 25 fdup z0.d, #0.15625000 // CHECK-INST: fmov z0.d, #0.15625000 // CHECK-ENCODING: [0x80,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c8 f9 25 fdup z0.d, #0.16406250 // CHECK-INST: fmov z0.d, #0.16406250 // CHECK-ENCODING: [0xa0,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c8 f9 25 fdup z0.d, #0.17187500 // CHECK-INST: fmov z0.d, #0.17187500 // CHECK-ENCODING: [0xc0,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c8 f9 25 fdup z0.d, #0.17968750 // CHECK-INST: fmov z0.d, #0.17968750 // CHECK-ENCODING: [0xe0,0xc8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c8 f9 25 fdup z0.d, #0.18750000 // CHECK-INST: fmov z0.d, #0.18750000 // CHECK-ENCODING: [0x00,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c9 f9 25 fdup z0.d, #0.19531250 // CHECK-INST: fmov z0.d, #0.19531250 // CHECK-ENCODING: [0x20,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c9 f9 25 fdup z0.d, #0.20312500 // CHECK-INST: fmov z0.d, #0.20312500 // CHECK-ENCODING: [0x40,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c9 f9 25 fdup z0.d, #0.21093750 // CHECK-INST: fmov z0.d, #0.21093750 // CHECK-ENCODING: [0x60,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c9 f9 25 fdup z0.d, #0.21875000 // CHECK-INST: fmov z0.d, #0.21875000 // CHECK-ENCODING: [0x80,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c9 f9 25 fdup z0.d, #0.22656250 // CHECK-INST: fmov z0.d, #0.22656250 // CHECK-ENCODING: [0xa0,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c9 f9 25 fdup z0.d, #0.23437500 // CHECK-INST: fmov z0.d, #0.23437500 // CHECK-ENCODING: [0xc0,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c9 f9 25 fdup z0.d, #0.24218750 // CHECK-INST: fmov z0.d, #0.24218750 // CHECK-ENCODING: [0xe0,0xc9,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c9 f9 25 fdup z0.d, #0.25000000 // CHECK-INST: fmov z0.d, #0.25000000 // CHECK-ENCODING: [0x00,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ca f9 25 fdup z0.d, #0.26562500 // CHECK-INST: fmov z0.d, #0.26562500 // CHECK-ENCODING: [0x20,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ca f9 25 fdup z0.d, #0.28125000 // CHECK-INST: fmov z0.d, #0.28125000 // CHECK-ENCODING: [0x40,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ca f9 25 fdup z0.d, #0.29687500 // CHECK-INST: fmov z0.d, #0.29687500 // CHECK-ENCODING: [0x60,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ca f9 25 fdup z0.d, #0.31250000 // CHECK-INST: fmov z0.d, #0.31250000 // CHECK-ENCODING: [0x80,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ca f9 25 fdup z0.d, #0.32812500 // CHECK-INST: fmov z0.d, #0.32812500 // CHECK-ENCODING: [0xa0,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ca f9 25 fdup z0.d, #0.34375000 // CHECK-INST: fmov z0.d, #0.34375000 // CHECK-ENCODING: [0xc0,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ca f9 25 fdup z0.d, #0.35937500 // CHECK-INST: fmov z0.d, #0.35937500 // CHECK-ENCODING: [0xe0,0xca,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ca f9 25 fdup z0.d, #0.37500000 // CHECK-INST: fmov z0.d, #0.37500000 // CHECK-ENCODING: [0x00,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cb f9 25 fdup z0.d, #0.39062500 // CHECK-INST: fmov z0.d, #0.39062500 // CHECK-ENCODING: [0x20,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cb f9 25 fdup z0.d, #0.40625000 // CHECK-INST: fmov z0.d, #0.40625000 // CHECK-ENCODING: [0x40,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cb f9 25 fdup z0.d, #0.42187500 // CHECK-INST: fmov z0.d, #0.42187500 // CHECK-ENCODING: [0x60,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cb f9 25 fdup z0.d, #0.43750000 // CHECK-INST: fmov z0.d, #0.43750000 // CHECK-ENCODING: [0x80,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cb f9 25 fdup z0.d, #0.45312500 // CHECK-INST: fmov z0.d, #0.45312500 // CHECK-ENCODING: [0xa0,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cb f9 25 fdup z0.d, #0.46875000 // CHECK-INST: fmov z0.d, #0.46875000 // CHECK-ENCODING: [0xc0,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cb f9 25 fdup z0.d, #0.48437500 // CHECK-INST: fmov z0.d, #0.48437500 // CHECK-ENCODING: [0xe0,0xcb,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb f9 25 fdup z0.d, #0.50000000 // CHECK-INST: fmov z0.d, #0.50000000 // CHECK-ENCODING: [0x00,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc f9 25 fdup z0.d, #0.53125000 // CHECK-INST: fmov z0.d, #0.53125000 // CHECK-ENCODING: [0x20,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cc f9 25 fdup z0.d, #0.56250000 // CHECK-INST: fmov z0.d, #0.56250000 // CHECK-ENCODING: [0x40,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cc f9 25 fdup z0.d, #0.59375000 // CHECK-INST: fmov z0.d, #0.59375000 // CHECK-ENCODING: [0x60,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cc f9 25 fdup z0.d, #0.62500000 // CHECK-INST: fmov z0.d, #0.62500000 // CHECK-ENCODING: [0x80,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cc f9 25 fdup z0.d, #0.65625000 // CHECK-INST: fmov z0.d, #0.65625000 // CHECK-ENCODING: [0xa0,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cc f9 25 fdup z0.d, #0.68750000 // CHECK-INST: fmov z0.d, #0.68750000 // CHECK-ENCODING: [0xc0,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cc f9 25 fdup z0.d, #0.71875000 // CHECK-INST: fmov z0.d, #0.71875000 // CHECK-ENCODING: [0xe0,0xcc,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cc f9 25 fdup z0.d, #0.75000000 // CHECK-INST: fmov z0.d, #0.75000000 // CHECK-ENCODING: [0x00,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cd f9 25 fdup z0.d, #0.78125000 // CHECK-INST: fmov z0.d, #0.78125000 // CHECK-ENCODING: [0x20,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cd f9 25 fdup z0.d, #0.81250000 // CHECK-INST: fmov z0.d, #0.81250000 // CHECK-ENCODING: [0x40,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cd f9 25 fdup z0.d, #0.84375000 // CHECK-INST: fmov z0.d, #0.84375000 // CHECK-ENCODING: [0x60,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cd f9 25 fdup z0.d, #0.87500000 // CHECK-INST: fmov z0.d, #0.87500000 // CHECK-ENCODING: [0x80,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cd f9 25 fdup z0.d, #0.90625000 // CHECK-INST: fmov z0.d, #0.90625000 // CHECK-ENCODING: [0xa0,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cd f9 25 fdup z0.d, #0.93750000 // CHECK-INST: fmov z0.d, #0.93750000 // CHECK-ENCODING: [0xc0,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cd f9 25 fdup z0.d, #0.96875000 // CHECK-INST: fmov z0.d, #0.96875000 // CHECK-ENCODING: [0xe0,0xcd,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cd f9 25 fdup z0.d, #1.00000000 // CHECK-INST: fmov z0.d, #1.00000000 // CHECK-ENCODING: [0x00,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ce f9 25 fdup z0.d, #1.06250000 // CHECK-INST: fmov z0.d, #1.06250000 // CHECK-ENCODING: [0x20,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ce f9 25 fdup z0.d, #1.12500000 // CHECK-INST: fmov z0.d, #1.12500000 // CHECK-ENCODING: [0x40,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ce f9 25 fdup z0.d, #1.18750000 // CHECK-INST: fmov z0.d, #1.18750000 // CHECK-ENCODING: [0x60,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ce f9 25 fdup z0.d, #1.25000000 // CHECK-INST: fmov z0.d, #1.25000000 // CHECK-ENCODING: [0x80,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ce f9 25 fdup z0.d, #1.31250000 // CHECK-INST: fmov z0.d, #1.31250000 // CHECK-ENCODING: [0xa0,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ce f9 25 fdup z0.d, #1.37500000 // CHECK-INST: fmov z0.d, #1.37500000 // CHECK-ENCODING: [0xc0,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ce f9 25 fdup z0.d, #1.43750000 // CHECK-INST: fmov z0.d, #1.43750000 // CHECK-ENCODING: [0xe0,0xce,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ce f9 25 fdup z0.d, #1.50000000 // CHECK-INST: fmov z0.d, #1.50000000 // CHECK-ENCODING: [0x00,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cf f9 25 fdup z0.d, #1.56250000 // CHECK-INST: fmov z0.d, #1.56250000 // CHECK-ENCODING: [0x20,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cf f9 25 fdup z0.d, #1.62500000 // CHECK-INST: fmov z0.d, #1.62500000 // CHECK-ENCODING: [0x40,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cf f9 25 fdup z0.d, #1.68750000 // CHECK-INST: fmov z0.d, #1.68750000 // CHECK-ENCODING: [0x60,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cf f9 25 fdup z0.d, #1.75000000 // CHECK-INST: fmov z0.d, #1.75000000 // CHECK-ENCODING: [0x80,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cf f9 25 fdup z0.d, #1.81250000 // CHECK-INST: fmov z0.d, #1.81250000 // CHECK-ENCODING: [0xa0,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cf f9 25 fdup z0.d, #1.87500000 // CHECK-INST: fmov z0.d, #1.87500000 // CHECK-ENCODING: [0xc0,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cf f9 25 fdup z0.d, #1.93750000 // CHECK-INST: fmov z0.d, #1.93750000 // CHECK-ENCODING: [0xe0,0xcf,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf f9 25 fdup z0.d, #2.00000000 // CHECK-INST: fmov z0.d, #2.00000000 // CHECK-ENCODING: [0x00,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 f9 25 fdup z0.d, #2.12500000 // CHECK-INST: fmov z0.d, #2.12500000 // CHECK-ENCODING: [0x20,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c0 f9 25 fdup z0.d, #2.25000000 // CHECK-INST: fmov z0.d, #2.25000000 // CHECK-ENCODING: [0x40,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c0 f9 25 fdup z0.d, #2.37500000 // CHECK-INST: fmov z0.d, #2.37500000 // CHECK-ENCODING: [0x60,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c0 f9 25 fdup z0.d, #2.50000000 // CHECK-INST: fmov z0.d, #2.50000000 // CHECK-ENCODING: [0x80,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c0 f9 25 fdup z0.d, #2.62500000 // CHECK-INST: fmov z0.d, #2.62500000 // CHECK-ENCODING: [0xa0,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c0 f9 25 fdup z0.d, #2.75000000 // CHECK-INST: fmov z0.d, #2.75000000 // CHECK-ENCODING: [0xc0,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c0 f9 25 fdup z0.d, #2.87500000 // CHECK-INST: fmov z0.d, #2.87500000 // CHECK-ENCODING: [0xe0,0xc0,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c0 f9 25 fdup z0.d, #3.00000000 // CHECK-INST: fmov z0.d, #3.00000000 // CHECK-ENCODING: [0x00,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c1 f9 25 fdup z0.d, #3.12500000 // CHECK-INST: fmov z0.d, #3.12500000 // CHECK-ENCODING: [0x20,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c1 f9 25 fdup z0.d, #3.25000000 // CHECK-INST: fmov z0.d, #3.25000000 // CHECK-ENCODING: [0x40,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c1 f9 25 fdup z0.d, #3.37500000 // CHECK-INST: fmov z0.d, #3.37500000 // CHECK-ENCODING: [0x60,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c1 f9 25 fdup z0.d, #3.50000000 // CHECK-INST: fmov z0.d, #3.50000000 // CHECK-ENCODING: [0x80,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c1 f9 25 fdup z0.d, #3.62500000 // CHECK-INST: fmov z0.d, #3.62500000 // CHECK-ENCODING: [0xa0,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c1 f9 25 fdup z0.d, #3.75000000 // CHECK-INST: fmov z0.d, #3.75000000 // CHECK-ENCODING: [0xc0,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c1 f9 25 fdup z0.d, #3.87500000 // CHECK-INST: fmov z0.d, #3.87500000 // CHECK-ENCODING: [0xe0,0xc1,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c1 f9 25 fdup z0.d, #4.00000000 // CHECK-INST: fmov z0.d, #4.00000000 // CHECK-ENCODING: [0x00,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c2 f9 25 fdup z0.d, #4.25000000 // CHECK-INST: fmov z0.d, #4.25000000 // CHECK-ENCODING: [0x20,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c2 f9 25 fdup z0.d, #4.50000000 // CHECK-INST: fmov z0.d, #4.50000000 // CHECK-ENCODING: [0x40,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c2 f9 25 fdup z0.d, #4.75000000 // CHECK-INST: fmov z0.d, #4.75000000 // CHECK-ENCODING: [0x60,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c2 f9 25 fdup z0.d, #5.00000000 // CHECK-INST: fmov z0.d, #5.00000000 // CHECK-ENCODING: [0x80,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c2 f9 25 fdup z0.d, #5.25000000 // CHECK-INST: fmov z0.d, #5.25000000 // CHECK-ENCODING: [0xa0,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c2 f9 25 fdup z0.d, #5.50000000 // CHECK-INST: fmov z0.d, #5.50000000 // CHECK-ENCODING: [0xc0,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c2 f9 25 fdup z0.d, #5.75000000 // CHECK-INST: fmov z0.d, #5.75000000 // CHECK-ENCODING: [0xe0,0xc2,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c2 f9 25 fdup z0.d, #6.00000000 // CHECK-INST: fmov z0.d, #6.00000000 // CHECK-ENCODING: [0x00,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c3 f9 25 fdup z0.d, #6.25000000 // CHECK-INST: fmov z0.d, #6.25000000 // CHECK-ENCODING: [0x20,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c3 f9 25 fdup z0.d, #6.50000000 // CHECK-INST: fmov z0.d, #6.50000000 // CHECK-ENCODING: [0x40,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c3 f9 25 fdup z0.d, #6.75000000 // CHECK-INST: fmov z0.d, #6.75000000 // CHECK-ENCODING: [0x60,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c3 f9 25 fdup z0.d, #7.00000000 // CHECK-INST: fmov z0.d, #7.00000000 // CHECK-ENCODING: [0x80,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c3 f9 25 fdup z0.d, #7.25000000 // CHECK-INST: fmov z0.d, #7.25000000 // CHECK-ENCODING: [0xa0,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c3 f9 25 fdup z0.d, #7.50000000 // CHECK-INST: fmov z0.d, #7.50000000 // CHECK-ENCODING: [0xc0,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c3 f9 25 fdup z0.d, #7.75000000 // CHECK-INST: fmov z0.d, #7.75000000 // CHECK-ENCODING: [0xe0,0xc3,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f9 25 fdup z0.d, #8.00000000 // CHECK-INST: fmov z0.d, #8.00000000 // CHECK-ENCODING: [0x00,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 f9 25 fdup z0.d, #8.50000000 // CHECK-INST: fmov z0.d, #8.50000000 // CHECK-ENCODING: [0x20,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c4 f9 25 fdup z0.d, #9.00000000 // CHECK-INST: fmov z0.d, #9.00000000 // CHECK-ENCODING: [0x40,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c4 f9 25 fdup z0.d, #9.50000000 // CHECK-INST: fmov z0.d, #9.50000000 // CHECK-ENCODING: [0x60,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c4 f9 25 fdup z0.d, #10.00000000 // CHECK-INST: fmov z0.d, #10.00000000 // CHECK-ENCODING: [0x80,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c4 f9 25 fdup z0.d, #10.50000000 // CHECK-INST: fmov z0.d, #10.50000000 // CHECK-ENCODING: [0xa0,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c4 f9 25 fdup z0.d, #11.00000000 // CHECK-INST: fmov z0.d, #11.00000000 // CHECK-ENCODING: [0xc0,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c4 f9 25 fdup z0.d, #11.50000000 // CHECK-INST: fmov z0.d, #11.50000000 // CHECK-ENCODING: [0xe0,0xc4,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c4 f9 25 fdup z0.d, #12.00000000 // CHECK-INST: fmov z0.d, #12.00000000 // CHECK-ENCODING: [0x00,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c5 f9 25 fdup z0.d, #12.50000000 // CHECK-INST: fmov z0.d, #12.50000000 // CHECK-ENCODING: [0x20,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c5 f9 25 fdup z0.d, #13.00000000 // CHECK-INST: fmov z0.d, #13.00000000 // CHECK-ENCODING: [0x40,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c5 f9 25 fdup z0.d, #13.50000000 // CHECK-INST: fmov z0.d, #13.50000000 // CHECK-ENCODING: [0x60,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c5 f9 25 fdup z0.d, #14.00000000 // CHECK-INST: fmov z0.d, #14.00000000 // CHECK-ENCODING: [0x80,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c5 f9 25 fdup z0.d, #14.50000000 // CHECK-INST: fmov z0.d, #14.50000000 // CHECK-ENCODING: [0xa0,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c5 f9 25 fdup z0.d, #15.00000000 // CHECK-INST: fmov z0.d, #15.00000000 // CHECK-ENCODING: [0xc0,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c5 f9 25 fdup z0.d, #15.50000000 // CHECK-INST: fmov z0.d, #15.50000000 // CHECK-ENCODING: [0xe0,0xc5,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 f9 25 fdup z0.d, #16.00000000 // CHECK-INST: fmov z0.d, #16.00000000 // CHECK-ENCODING: [0x00,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c6 f9 25 fdup z0.d, #17.00000000 // CHECK-INST: fmov z0.d, #17.00000000 // CHECK-ENCODING: [0x20,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c6 f9 25 fdup z0.d, #18.00000000 // CHECK-INST: fmov z0.d, #18.00000000 // CHECK-ENCODING: [0x40,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c6 f9 25 fdup z0.d, #19.00000000 // CHECK-INST: fmov z0.d, #19.00000000 // CHECK-ENCODING: [0x60,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c6 f9 25 fdup z0.d, #20.00000000 // CHECK-INST: fmov z0.d, #20.00000000 // CHECK-ENCODING: [0x80,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c6 f9 25 fdup z0.d, #21.00000000 // CHECK-INST: fmov z0.d, #21.00000000 // CHECK-ENCODING: [0xa0,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c6 f9 25 fdup z0.d, #22.00000000 // CHECK-INST: fmov z0.d, #22.00000000 // CHECK-ENCODING: [0xc0,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c6 f9 25 fdup z0.d, #23.00000000 // CHECK-INST: fmov z0.d, #23.00000000 // CHECK-ENCODING: [0xe0,0xc6,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c6 f9 25 fdup z0.d, #24.00000000 // CHECK-INST: fmov z0.d, #24.00000000 // CHECK-ENCODING: [0x00,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c7 f9 25 fdup z0.d, #25.00000000 // CHECK-INST: fmov z0.d, #25.00000000 // CHECK-ENCODING: [0x20,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c7 f9 25 fdup z0.d, #26.00000000 // CHECK-INST: fmov z0.d, #26.00000000 // CHECK-ENCODING: [0x40,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c7 f9 25 fdup z0.d, #27.00000000 // CHECK-INST: fmov z0.d, #27.00000000 // CHECK-ENCODING: [0x60,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c7 f9 25 fdup z0.d, #28.00000000 // CHECK-INST: fmov z0.d, #28.00000000 // CHECK-ENCODING: [0x80,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c7 f9 25 fdup z0.d, #29.00000000 // CHECK-INST: fmov z0.d, #29.00000000 // CHECK-ENCODING: [0xa0,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c7 f9 25 fdup z0.d, #30.00000000 // CHECK-INST: fmov z0.d, #30.00000000 // CHECK-ENCODING: [0xc0,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c7 f9 25 fdup z0.d, #31.00000000 // CHECK-INST: fmov z0.d, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 f9 25 diff --git a/llvm/test/MC/AArch64/SVE/fmad.s b/llvm/test/MC/AArch64/SVE/fmad.s index 3ee0abe883c40..3b8bdedc378d4 100644 --- a/llvm/test/MC/AArch64/SVE/fmad.s +++ b/llvm/test/MC/AArch64/SVE/fmad.s @@ -12,19 +12,19 @@ fmad z0.h, p7/m, z1.h, z31.h // CHECK-INST: fmad z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x9c,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 9c 7f 65 fmad z0.s, p7/m, z1.s, z31.s // CHECK-INST: fmad z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x9c,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 9c bf 65 fmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x9c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 9c ff 65 @@ -34,23 +34,23 @@ fmad z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x9c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 9c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x9c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 9c ff 65 diff --git a/llvm/test/MC/AArch64/SVE/fmax.s b/llvm/test/MC/AArch64/SVE/fmax.s index 29616ddc92cee..be2f012f40d9f 100644 --- a/llvm/test/MC/AArch64/SVE/fmax.s +++ b/llvm/test/MC/AArch64/SVE/fmax.s @@ -12,61 +12,61 @@ fmax z0.h, p0/m, z0.h, #0.000000000000000 // CHECK-INST: fmax z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5e 65 fmax z0.h, p0/m, z0.h, #0.0 // CHECK-INST: fmax z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5e 65 fmax z0.s, p0/m, z0.s, #0.0 // CHECK-INST: fmax z0.s, p0/m, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x80,0x9e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9e 65 fmax z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmax z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c de 65 fmax z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fmax z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5e 65 fmax z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fmax z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x9e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9e 65 fmax z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 de 65 fmax z0.h, p7/m, z0.h, z31.h // CHECK-INST: fmax z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x46,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 46 65 fmax z0.s, p7/m, z0.s, z31.s // CHECK-INST: fmax z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x86,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 86 65 fmax z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c6 65 @@ -76,47 +76,47 @@ fmax z0.d, p7/m, z0.d, z31.d movprfx z0.d, p0/z, z7.d // CHECK-INST: movprfx z0.d, p0/z, z7.d // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 d0 04 fmax z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 de 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmax z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xde,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 de 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmax z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c6 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmax z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c6 65 diff --git a/llvm/test/MC/AArch64/SVE/fmaxnm.s b/llvm/test/MC/AArch64/SVE/fmaxnm.s index 0ec38de5fe824..f5b10bf20c94c 100644 --- a/llvm/test/MC/AArch64/SVE/fmaxnm.s +++ b/llvm/test/MC/AArch64/SVE/fmaxnm.s @@ -12,67 +12,67 @@ fmaxnm z0.h, p0/m, z0.h, #0.000000000000000 // CHECK-INST: fmaxnm z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5c 65 fmaxnm z0.h, p0/m, z0.h, #0.0 // CHECK-INST: fmaxnm z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5c 65 fmaxnm z0.s, p0/m, z0.s, #0.0 // CHECK-INST: fmaxnm z0.s, p0/m, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x80,0x9c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9c 65 fmaxnm z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fmaxnm z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xdc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 dc 65 fmaxnm z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fmaxnm z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5c 65 fmaxnm z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fmaxnm z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5c 65 fmaxnm z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fmaxnm z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x9c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9c 65 fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dc 65 fmaxnm z0.h, p7/m, z0.h, z31.h // CHECK-INST: fmaxnm z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x44,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 44 65 fmaxnm z0.s, p7/m, z0.s, z31.s // CHECK-INST: fmaxnm z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x84,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 84 65 fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c4 65 @@ -82,47 +82,47 @@ fmaxnm z0.d, p7/m, z0.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dc 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dc 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c4 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c4 65 diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv.s b/llvm/test/MC/AArch64/SVE/fmaxnmv.s index ee37d1cfe04cf..92f4fd7294a84 100644 --- a/llvm/test/MC/AArch64/SVE/fmaxnmv.s +++ b/llvm/test/MC/AArch64/SVE/fmaxnmv.s @@ -12,17 +12,17 @@ fmaxnmv h0, p7, z31.h // CHECK-INST: fmaxnmv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x44,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 44 65 fmaxnmv s0, p7, z31.s // CHECK-INST: fmaxnmv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x84,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 84 65 fmaxnmv d0, p7, z31.d // CHECK-INST: fmaxnmv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c4 65 diff --git a/llvm/test/MC/AArch64/SVE/fmaxv.s b/llvm/test/MC/AArch64/SVE/fmaxv.s index 922df3e8a79a2..09ea407e8b2ae 100644 --- a/llvm/test/MC/AArch64/SVE/fmaxv.s +++ b/llvm/test/MC/AArch64/SVE/fmaxv.s @@ -12,17 +12,17 @@ fmaxv h0, p7, z31.h // CHECK-INST: fmaxv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x46,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 46 65 fmaxv s0, p7, z31.s // CHECK-INST: fmaxv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x86,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 86 65 fmaxv d0, p7, z31.d // CHECK-INST: fmaxv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c6 65 diff --git a/llvm/test/MC/AArch64/SVE/fmin.s b/llvm/test/MC/AArch64/SVE/fmin.s index 57231302ffc14..16717fd704a42 100644 --- a/llvm/test/MC/AArch64/SVE/fmin.s +++ b/llvm/test/MC/AArch64/SVE/fmin.s @@ -12,67 +12,67 @@ fmin z0.h, p0/m, z0.h, #0.000000000000000 // CHECK-INST: fmin z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5f 65 fmin z0.h, p0/m, z0.h, #0.0 // CHECK-INST: fmin z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5f 65 fmin z0.s, p0/m, z0.s, #0.0 // CHECK-INST: fmin z0.s, p0/m, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x80,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9f 65 fmin z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fmin z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 df 65 fmin z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fmin z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5f 65 fmin z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fmin z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5f 65 fmin z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fmin z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9f 65 fmin z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c df 65 fmin z0.h, p7/m, z0.h, z31.h // CHECK-INST: fmin z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x47,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 47 65 fmin z0.s, p7/m, z0.s, z31.s // CHECK-INST: fmin z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x87,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 87 65 fmin z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c7 65 @@ -82,47 +82,47 @@ fmin z0.d, p7/m, z0.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fmin z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c df 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fmin z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c df 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmin z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c7 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmin z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c7 65 diff --git a/llvm/test/MC/AArch64/SVE/fminnm.s b/llvm/test/MC/AArch64/SVE/fminnm.s index cb5bcae4fd466..968a4d3cf00a6 100644 --- a/llvm/test/MC/AArch64/SVE/fminnm.s +++ b/llvm/test/MC/AArch64/SVE/fminnm.s @@ -12,67 +12,67 @@ fminnm z0.h, p0/m, z0.h, #0.000000000000000 // CHECK-INST: fminnm z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5d 65 fminnm z0.h, p0/m, z0.h, #0.0 // CHECK-INST: fminnm z0.h, p0/m, z0.h, #0.0 // CHECK-ENCODING: [0x00,0x80,0x5d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5d 65 fminnm z0.s, p0/m, z0.s, #0.0 // CHECK-INST: fminnm z0.s, p0/m, z0.s, #0.0 // CHECK-ENCODING: [0x00,0x80,0x9d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9d 65 fminnm z0.d, p0/m, z0.d, #0.0 // CHECK-INST: fminnm z0.d, p0/m, z0.d, #0.0 // CHECK-ENCODING: [0x00,0x80,0xdd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 dd 65 fminnm z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fminnm z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5d 65 fminnm z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fminnm z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5d 65 fminnm z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fminnm z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x9d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9d 65 fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dd 65 fminnm z0.h, p7/m, z0.h, z31.h // CHECK-INST: fminnm z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x45,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 45 65 fminnm z0.s, p7/m, z0.s, z31.s // CHECK-INST: fminnm z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x85,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 85 65 fminnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c5 65 @@ -82,47 +82,47 @@ fminnm z0.d, p7/m, z0.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dd 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c dd 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fminnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c5 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fminnm z0.d, p7/m, z0.d, z31.d // CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c5 65 diff --git a/llvm/test/MC/AArch64/SVE/fminnmv.s b/llvm/test/MC/AArch64/SVE/fminnmv.s index 7e80f8cdfb062..0c152446bb109 100644 --- a/llvm/test/MC/AArch64/SVE/fminnmv.s +++ b/llvm/test/MC/AArch64/SVE/fminnmv.s @@ -12,17 +12,17 @@ fminnmv h0, p7, z31.h // CHECK-INST: fminnmv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x45,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 45 65 fminnmv s0, p7, z31.s // CHECK-INST: fminnmv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x85,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 85 65 fminnmv d0, p7, z31.d // CHECK-INST: fminnmv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc5,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c5 65 diff --git a/llvm/test/MC/AArch64/SVE/fminv.s b/llvm/test/MC/AArch64/SVE/fminv.s index 0c1dde056d39f..67079ebee7201 100644 --- a/llvm/test/MC/AArch64/SVE/fminv.s +++ b/llvm/test/MC/AArch64/SVE/fminv.s @@ -12,17 +12,17 @@ fminv h0, p7, z31.h // CHECK-INST: fminv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x47,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 47 65 fminv s0, p7, z31.s // CHECK-INST: fminv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x87,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 87 65 fminv d0, p7, z31.d // CHECK-INST: fminv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c7 65 diff --git a/llvm/test/MC/AArch64/SVE/fmla.s b/llvm/test/MC/AArch64/SVE/fmla.s index 3791a498c2312..17f32f4b5c400 100644 --- a/llvm/test/MC/AArch64/SVE/fmla.s +++ b/llvm/test/MC/AArch64/SVE/fmla.s @@ -12,37 +12,37 @@ fmla z0.h, p7/m, z1.h, z31.h // CHECK-INST: fmla z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x1c,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c 7f 65 fmla z0.s, p7/m, z1.s, z31.s // CHECK-INST: fmla z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x1c,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c bf 65 fmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x1c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c ff 65 fmla z0.h, z1.h, z7.h[7] // CHECK-INST: fmla z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x00,0x7f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 7f 64 fmla z0.s, z1.s, z7.s[3] // CHECK-INST: fmla z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x00,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 bf 64 fmla z0.d, z1.d, z7.d[1] // CHECK-INST: fmla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x00,0xf7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 f7 64 @@ -52,35 +52,35 @@ fmla z0.d, z1.d, z7.d[1] movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x1c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x1c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmla z0.d, z1.d, z7.d[1] // CHECK-INST: fmla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x00,0xf7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 f7 64 diff --git a/llvm/test/MC/AArch64/SVE/fmls.s b/llvm/test/MC/AArch64/SVE/fmls.s index 860cd3c845d08..3725ee1a4cf97 100644 --- a/llvm/test/MC/AArch64/SVE/fmls.s +++ b/llvm/test/MC/AArch64/SVE/fmls.s @@ -12,37 +12,37 @@ fmls z0.h, p7/m, z1.h, z31.h // CHECK-INST: fmls z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x3c,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 3c 7f 65 fmls z0.s, p7/m, z1.s, z31.s // CHECK-INST: fmls z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x3c,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 3c bf 65 fmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x3c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 3c ff 65 fmls z0.h, z1.h, z7.h[7] // CHECK-INST: fmls z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x04,0x7f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 7f 64 fmls z0.s, z1.s, z7.s[3] // CHECK-INST: fmls z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x04,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 bf 64 fmls z0.d, z1.d, z7.d[1] // CHECK-INST: fmls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x04,0xf7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 f7 64 @@ -52,35 +52,35 @@ fmls z0.d, z1.d, z7.d[1] movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x3c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 3c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x3c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 3c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmls z0.d, z1.d, z7.d[1] // CHECK-INST: fmls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x04,0xf7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 f7 64 diff --git a/llvm/test/MC/AArch64/SVE/fmov.s b/llvm/test/MC/AArch64/SVE/fmov.s index 9209fc64819a9..41453acab3813 100644 --- a/llvm/test/MC/AArch64/SVE/fmov.s +++ b/llvm/test/MC/AArch64/SVE/fmov.s @@ -12,1591 +12,1591 @@ fmov z0.h, #0.0 // CHECK-INST: mov z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 78 25 fmov z0.s, #0.0 // CHECK-INST: mov z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 b8 25 fmov z0.d, #0.0 // CHECK-INST: mov z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 f8 25 fmov z0.h, #-0.12500000 // CHECK-INST: fmov z0.h, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x79,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 79 25 fmov z0.s, #-0.12500000 // CHECK-INST: fmov z0.s, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xb9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 b9 25 fmov z0.d, #-0.12500000 // CHECK-INST: fmov z0.d, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 f9 25 fmov z0.d, #31.00000000 // CHECK-INST: fmov z0.d, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xf9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 f9 25 fmov z0.h, p0/m, #-0.12500000 // CHECK-INST: fmov z0.h, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 50 05 fmov z0.s, p0/m, #-0.12500000 // CHECK-INST: fmov z0.s, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 90 05 fmov z0.d, p0/m, #-0.12500000 // CHECK-INST: fmov z0.d, p0/m, #-0.12500000 // CHECK-ENCODING: [0x00,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d8 d0 05 fmov z0.d, p0/m, #-0.13281250 // CHECK-INST: fmov z0.d, p0/m, #-0.13281250 // CHECK-ENCODING: [0x20,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d8 d0 05 fmov z0.d, p0/m, #-0.14062500 // CHECK-INST: fmov z0.d, p0/m, #-0.14062500 // CHECK-ENCODING: [0x40,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d8 d0 05 fmov z0.d, p0/m, #-0.14843750 // CHECK-INST: fmov z0.d, p0/m, #-0.14843750 // CHECK-ENCODING: [0x60,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d8 d0 05 fmov z0.d, p0/m, #-0.15625000 // CHECK-INST: fmov z0.d, p0/m, #-0.15625000 // CHECK-ENCODING: [0x80,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d8 d0 05 fmov z0.d, p0/m, #-0.16406250 // CHECK-INST: fmov z0.d, p0/m, #-0.16406250 // CHECK-ENCODING: [0xa0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d8 d0 05 fmov z0.d, p0/m, #-0.17187500 // CHECK-INST: fmov z0.d, p0/m, #-0.17187500 // CHECK-ENCODING: [0xc0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d8 d0 05 fmov z0.d, p0/m, #-0.17968750 // CHECK-INST: fmov z0.d, p0/m, #-0.17968750 // CHECK-ENCODING: [0xe0,0xd8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d8 d0 05 fmov z0.d, p0/m, #-0.18750000 // CHECK-INST: fmov z0.d, p0/m, #-0.18750000 // CHECK-ENCODING: [0x00,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d9 d0 05 fmov z0.d, p0/m, #-0.19531250 // CHECK-INST: fmov z0.d, p0/m, #-0.19531250 // CHECK-ENCODING: [0x20,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d9 d0 05 fmov z0.d, p0/m, #-0.20312500 // CHECK-INST: fmov z0.d, p0/m, #-0.20312500 // CHECK-ENCODING: [0x40,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d9 d0 05 fmov z0.d, p0/m, #-0.21093750 // CHECK-INST: fmov z0.d, p0/m, #-0.21093750 // CHECK-ENCODING: [0x60,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d9 d0 05 fmov z0.d, p0/m, #-0.21875000 // CHECK-INST: fmov z0.d, p0/m, #-0.21875000 // CHECK-ENCODING: [0x80,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d9 d0 05 fmov z0.d, p0/m, #-0.22656250 // CHECK-INST: fmov z0.d, p0/m, #-0.22656250 // CHECK-ENCODING: [0xa0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d9 d0 05 fmov z0.d, p0/m, #-0.23437500 // CHECK-INST: fmov z0.d, p0/m, #-0.23437500 // CHECK-ENCODING: [0xc0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d9 d0 05 fmov z0.d, p0/m, #-0.24218750 // CHECK-INST: fmov z0.d, p0/m, #-0.24218750 // CHECK-ENCODING: [0xe0,0xd9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d9 d0 05 fmov z0.d, p0/m, #-0.25000000 // CHECK-INST: fmov z0.d, p0/m, #-0.25000000 // CHECK-ENCODING: [0x00,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 da d0 05 fmov z0.d, p0/m, #-0.26562500 // CHECK-INST: fmov z0.d, p0/m, #-0.26562500 // CHECK-ENCODING: [0x20,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 da d0 05 fmov z0.d, p0/m, #-0.28125000 // CHECK-INST: fmov z0.d, p0/m, #-0.28125000 // CHECK-ENCODING: [0x40,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 da d0 05 fmov z0.d, p0/m, #-0.29687500 // CHECK-INST: fmov z0.d, p0/m, #-0.29687500 // CHECK-ENCODING: [0x60,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 da d0 05 fmov z0.d, p0/m, #-0.31250000 // CHECK-INST: fmov z0.d, p0/m, #-0.31250000 // CHECK-ENCODING: [0x80,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 da d0 05 fmov z0.d, p0/m, #-0.32812500 // CHECK-INST: fmov z0.d, p0/m, #-0.32812500 // CHECK-ENCODING: [0xa0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 da d0 05 fmov z0.d, p0/m, #-0.34375000 // CHECK-INST: fmov z0.d, p0/m, #-0.34375000 // CHECK-ENCODING: [0xc0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 da d0 05 fmov z0.d, p0/m, #-0.35937500 // CHECK-INST: fmov z0.d, p0/m, #-0.35937500 // CHECK-ENCODING: [0xe0,0xda,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 da d0 05 fmov z0.d, p0/m, #-0.37500000 // CHECK-INST: fmov z0.d, p0/m, #-0.37500000 // CHECK-ENCODING: [0x00,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 db d0 05 fmov z0.d, p0/m, #-0.39062500 // CHECK-INST: fmov z0.d, p0/m, #-0.39062500 // CHECK-ENCODING: [0x20,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 db d0 05 fmov z0.d, p0/m, #-0.40625000 // CHECK-INST: fmov z0.d, p0/m, #-0.40625000 // CHECK-ENCODING: [0x40,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 db d0 05 fmov z0.d, p0/m, #-0.42187500 // CHECK-INST: fmov z0.d, p0/m, #-0.42187500 // CHECK-ENCODING: [0x60,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 db d0 05 fmov z0.d, p0/m, #-0.43750000 // CHECK-INST: fmov z0.d, p0/m, #-0.43750000 // CHECK-ENCODING: [0x80,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 db d0 05 fmov z0.d, p0/m, #-0.45312500 // CHECK-INST: fmov z0.d, p0/m, #-0.45312500 // CHECK-ENCODING: [0xa0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 db d0 05 fmov z0.d, p0/m, #-0.46875000 // CHECK-INST: fmov z0.d, p0/m, #-0.46875000 // CHECK-ENCODING: [0xc0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 db d0 05 fmov z0.d, p0/m, #-0.48437500 // CHECK-INST: fmov z0.d, p0/m, #-0.48437500 // CHECK-ENCODING: [0xe0,0xdb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 db d0 05 fmov z0.d, p0/m, #-0.50000000 // CHECK-INST: fmov z0.d, p0/m, #-0.50000000 // CHECK-ENCODING: [0x00,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dc d0 05 fmov z0.d, p0/m, #-0.53125000 // CHECK-INST: fmov z0.d, p0/m, #-0.53125000 // CHECK-ENCODING: [0x20,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc d0 05 fmov z0.d, p0/m, #-0.56250000 // CHECK-INST: fmov z0.d, p0/m, #-0.56250000 // CHECK-ENCODING: [0x40,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dc d0 05 fmov z0.d, p0/m, #-0.59375000 // CHECK-INST: fmov z0.d, p0/m, #-0.59375000 // CHECK-ENCODING: [0x60,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dc d0 05 fmov z0.d, p0/m, #-0.62500000 // CHECK-INST: fmov z0.d, p0/m, #-0.62500000 // CHECK-ENCODING: [0x80,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dc d0 05 fmov z0.d, p0/m, #-0.65625000 // CHECK-INST: fmov z0.d, p0/m, #-0.65625000 // CHECK-ENCODING: [0xa0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dc d0 05 fmov z0.d, p0/m, #-0.68750000 // CHECK-INST: fmov z0.d, p0/m, #-0.68750000 // CHECK-ENCODING: [0xc0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dc d0 05 fmov z0.d, p0/m, #-0.71875000 // CHECK-INST: fmov z0.d, p0/m, #-0.71875000 // CHECK-ENCODING: [0xe0,0xdc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dc d0 05 fmov z0.d, p0/m, #-0.75000000 // CHECK-INST: fmov z0.d, p0/m, #-0.75000000 // CHECK-ENCODING: [0x00,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 dd d0 05 fmov z0.d, p0/m, #-0.78125000 // CHECK-INST: fmov z0.d, p0/m, #-0.78125000 // CHECK-ENCODING: [0x20,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dd d0 05 fmov z0.d, p0/m, #-0.81250000 // CHECK-INST: fmov z0.d, p0/m, #-0.81250000 // CHECK-ENCODING: [0x40,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 dd d0 05 fmov z0.d, p0/m, #-0.84375000 // CHECK-INST: fmov z0.d, p0/m, #-0.84375000 // CHECK-ENCODING: [0x60,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 dd d0 05 fmov z0.d, p0/m, #-0.87500000 // CHECK-INST: fmov z0.d, p0/m, #-0.87500000 // CHECK-ENCODING: [0x80,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 dd d0 05 fmov z0.d, p0/m, #-0.90625000 // CHECK-INST: fmov z0.d, p0/m, #-0.90625000 // CHECK-ENCODING: [0xa0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 dd d0 05 fmov z0.d, p0/m, #-0.93750000 // CHECK-INST: fmov z0.d, p0/m, #-0.93750000 // CHECK-ENCODING: [0xc0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 dd d0 05 fmov z0.d, p0/m, #-0.96875000 // CHECK-INST: fmov z0.d, p0/m, #-0.96875000 // CHECK-ENCODING: [0xe0,0xdd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 dd d0 05 fmov z0.d, p0/m, #-1.00000000 // CHECK-INST: fmov z0.d, p0/m, #-1.00000000 // CHECK-ENCODING: [0x00,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 de d0 05 fmov z0.d, p0/m, #-1.06250000 // CHECK-INST: fmov z0.d, p0/m, #-1.06250000 // CHECK-ENCODING: [0x20,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 de d0 05 fmov z0.d, p0/m, #-1.12500000 // CHECK-INST: fmov z0.d, p0/m, #-1.12500000 // CHECK-ENCODING: [0x40,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 de d0 05 fmov z0.d, p0/m, #-1.18750000 // CHECK-INST: fmov z0.d, p0/m, #-1.18750000 // CHECK-ENCODING: [0x60,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 de d0 05 fmov z0.d, p0/m, #-1.25000000 // CHECK-INST: fmov z0.d, p0/m, #-1.25000000 // CHECK-ENCODING: [0x80,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 de d0 05 fmov z0.d, p0/m, #-1.31250000 // CHECK-INST: fmov z0.d, p0/m, #-1.31250000 // CHECK-ENCODING: [0xa0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 de d0 05 fmov z0.d, p0/m, #-1.37500000 // CHECK-INST: fmov z0.d, p0/m, #-1.37500000 // CHECK-ENCODING: [0xc0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 de d0 05 fmov z0.d, p0/m, #-1.43750000 // CHECK-INST: fmov z0.d, p0/m, #-1.43750000 // CHECK-ENCODING: [0xe0,0xde,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 de d0 05 fmov z0.d, p0/m, #-1.50000000 // CHECK-INST: fmov z0.d, p0/m, #-1.50000000 // CHECK-ENCODING: [0x00,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 df d0 05 fmov z0.d, p0/m, #-1.56250000 // CHECK-INST: fmov z0.d, p0/m, #-1.56250000 // CHECK-ENCODING: [0x20,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 df d0 05 fmov z0.d, p0/m, #-1.62500000 // CHECK-INST: fmov z0.d, p0/m, #-1.62500000 // CHECK-ENCODING: [0x40,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 df d0 05 fmov z0.d, p0/m, #-1.68750000 // CHECK-INST: fmov z0.d, p0/m, #-1.68750000 // CHECK-ENCODING: [0x60,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 df d0 05 fmov z0.d, p0/m, #-1.75000000 // CHECK-INST: fmov z0.d, p0/m, #-1.75000000 // CHECK-ENCODING: [0x80,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 df d0 05 fmov z0.d, p0/m, #-1.81250000 // CHECK-INST: fmov z0.d, p0/m, #-1.81250000 // CHECK-ENCODING: [0xa0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 df d0 05 fmov z0.d, p0/m, #-1.87500000 // CHECK-INST: fmov z0.d, p0/m, #-1.87500000 // CHECK-ENCODING: [0xc0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 df d0 05 fmov z0.d, p0/m, #-1.93750000 // CHECK-INST: fmov z0.d, p0/m, #-1.93750000 // CHECK-ENCODING: [0xe0,0xdf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df d0 05 fmov z0.d, p0/m, #-2.00000000 // CHECK-INST: fmov z0.d, p0/m, #-2.00000000 // CHECK-ENCODING: [0x00,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 d0 05 fmov z0.d, p0/m, #-2.12500000 // CHECK-INST: fmov z0.d, p0/m, #-2.12500000 // CHECK-ENCODING: [0x20,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d0 d0 05 fmov z0.d, p0/m, #-2.25000000 // CHECK-INST: fmov z0.d, p0/m, #-2.25000000 // CHECK-ENCODING: [0x40,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d0 d0 05 fmov z0.d, p0/m, #-2.37500000 // CHECK-INST: fmov z0.d, p0/m, #-2.37500000 // CHECK-ENCODING: [0x60,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d0 d0 05 fmov z0.d, p0/m, #-2.50000000 // CHECK-INST: fmov z0.d, p0/m, #-2.50000000 // CHECK-ENCODING: [0x80,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d0 d0 05 fmov z0.d, p0/m, #-2.62500000 // CHECK-INST: fmov z0.d, p0/m, #-2.62500000 // CHECK-ENCODING: [0xa0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d0 d0 05 fmov z0.d, p0/m, #-2.75000000 // CHECK-INST: fmov z0.d, p0/m, #-2.75000000 // CHECK-ENCODING: [0xc0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d0 d0 05 fmov z0.d, p0/m, #-2.87500000 // CHECK-INST: fmov z0.d, p0/m, #-2.87500000 // CHECK-ENCODING: [0xe0,0xd0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d0 d0 05 fmov z0.d, p0/m, #-3.00000000 // CHECK-INST: fmov z0.d, p0/m, #-3.00000000 // CHECK-ENCODING: [0x00,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d1 d0 05 fmov z0.d, p0/m, #-3.12500000 // CHECK-INST: fmov z0.d, p0/m, #-3.12500000 // CHECK-ENCODING: [0x20,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d1 d0 05 fmov z0.d, p0/m, #-3.25000000 // CHECK-INST: fmov z0.d, p0/m, #-3.25000000 // CHECK-ENCODING: [0x40,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d1 d0 05 fmov z0.d, p0/m, #-3.37500000 // CHECK-INST: fmov z0.d, p0/m, #-3.37500000 // CHECK-ENCODING: [0x60,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d1 d0 05 fmov z0.d, p0/m, #-3.50000000 // CHECK-INST: fmov z0.d, p0/m, #-3.50000000 // CHECK-ENCODING: [0x80,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d1 d0 05 fmov z0.d, p0/m, #-3.62500000 // CHECK-INST: fmov z0.d, p0/m, #-3.62500000 // CHECK-ENCODING: [0xa0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d1 d0 05 fmov z0.d, p0/m, #-3.75000000 // CHECK-INST: fmov z0.d, p0/m, #-3.75000000 // CHECK-ENCODING: [0xc0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d1 d0 05 fmov z0.d, p0/m, #-3.87500000 // CHECK-INST: fmov z0.d, p0/m, #-3.87500000 // CHECK-ENCODING: [0xe0,0xd1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d1 d0 05 fmov z0.d, p0/m, #-4.00000000 // CHECK-INST: fmov z0.d, p0/m, #-4.00000000 // CHECK-ENCODING: [0x00,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d2 d0 05 fmov z0.d, p0/m, #-4.25000000 // CHECK-INST: fmov z0.d, p0/m, #-4.25000000 // CHECK-ENCODING: [0x20,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d2 d0 05 fmov z0.d, p0/m, #-4.50000000 // CHECK-INST: fmov z0.d, p0/m, #-4.50000000 // CHECK-ENCODING: [0x40,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d2 d0 05 fmov z0.d, p0/m, #-4.75000000 // CHECK-INST: fmov z0.d, p0/m, #-4.75000000 // CHECK-ENCODING: [0x60,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d2 d0 05 fmov z0.d, p0/m, #-5.00000000 // CHECK-INST: fmov z0.d, p0/m, #-5.00000000 // CHECK-ENCODING: [0x80,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d2 d0 05 fmov z0.d, p0/m, #-5.25000000 // CHECK-INST: fmov z0.d, p0/m, #-5.25000000 // CHECK-ENCODING: [0xa0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d2 d0 05 fmov z0.d, p0/m, #-5.50000000 // CHECK-INST: fmov z0.d, p0/m, #-5.50000000 // CHECK-ENCODING: [0xc0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d2 d0 05 fmov z0.d, p0/m, #-5.75000000 // CHECK-INST: fmov z0.d, p0/m, #-5.75000000 // CHECK-ENCODING: [0xe0,0xd2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d2 d0 05 fmov z0.d, p0/m, #-6.00000000 // CHECK-INST: fmov z0.d, p0/m, #-6.00000000 // CHECK-ENCODING: [0x00,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d3 d0 05 fmov z0.d, p0/m, #-6.25000000 // CHECK-INST: fmov z0.d, p0/m, #-6.25000000 // CHECK-ENCODING: [0x20,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d3 d0 05 fmov z0.d, p0/m, #-6.50000000 // CHECK-INST: fmov z0.d, p0/m, #-6.50000000 // CHECK-ENCODING: [0x40,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d3 d0 05 fmov z0.d, p0/m, #-6.75000000 // CHECK-INST: fmov z0.d, p0/m, #-6.75000000 // CHECK-ENCODING: [0x60,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d3 d0 05 fmov z0.d, p0/m, #-7.00000000 // CHECK-INST: fmov z0.d, p0/m, #-7.00000000 // CHECK-ENCODING: [0x80,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d3 d0 05 fmov z0.d, p0/m, #-7.25000000 // CHECK-INST: fmov z0.d, p0/m, #-7.25000000 // CHECK-ENCODING: [0xa0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d3 d0 05 fmov z0.d, p0/m, #-7.50000000 // CHECK-INST: fmov z0.d, p0/m, #-7.50000000 // CHECK-ENCODING: [0xc0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d3 d0 05 fmov z0.d, p0/m, #-7.75000000 // CHECK-INST: fmov z0.d, p0/m, #-7.75000000 // CHECK-ENCODING: [0xe0,0xd3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d3 d0 05 fmov z0.d, p0/m, #-8.00000000 // CHECK-INST: fmov z0.d, p0/m, #-8.00000000 // CHECK-ENCODING: [0x00,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d4 d0 05 fmov z0.d, p0/m, #-8.50000000 // CHECK-INST: fmov z0.d, p0/m, #-8.50000000 // CHECK-ENCODING: [0x20,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d4 d0 05 fmov z0.d, p0/m, #-9.00000000 // CHECK-INST: fmov z0.d, p0/m, #-9.00000000 // CHECK-ENCODING: [0x40,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d4 d0 05 fmov z0.d, p0/m, #-9.50000000 // CHECK-INST: fmov z0.d, p0/m, #-9.50000000 // CHECK-ENCODING: [0x60,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d4 d0 05 fmov z0.d, p0/m, #-10.00000000 // CHECK-INST: fmov z0.d, p0/m, #-10.00000000 // CHECK-ENCODING: [0x80,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d4 d0 05 fmov z0.d, p0/m, #-10.50000000 // CHECK-INST: fmov z0.d, p0/m, #-10.50000000 // CHECK-ENCODING: [0xa0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d4 d0 05 fmov z0.d, p0/m, #-11.00000000 // CHECK-INST: fmov z0.d, p0/m, #-11.00000000 // CHECK-ENCODING: [0xc0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d4 d0 05 fmov z0.d, p0/m, #-11.50000000 // CHECK-INST: fmov z0.d, p0/m, #-11.50000000 // CHECK-ENCODING: [0xe0,0xd4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d4 d0 05 fmov z0.d, p0/m, #-12.00000000 // CHECK-INST: fmov z0.d, p0/m, #-12.00000000 // CHECK-ENCODING: [0x00,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d5 d0 05 fmov z0.d, p0/m, #-12.50000000 // CHECK-INST: fmov z0.d, p0/m, #-12.50000000 // CHECK-ENCODING: [0x20,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d5 d0 05 fmov z0.d, p0/m, #-13.00000000 // CHECK-INST: fmov z0.d, p0/m, #-13.00000000 // CHECK-ENCODING: [0x40,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d5 d0 05 fmov z0.d, p0/m, #-13.50000000 // CHECK-INST: fmov z0.d, p0/m, #-13.50000000 // CHECK-ENCODING: [0x60,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d5 d0 05 fmov z0.d, p0/m, #-14.00000000 // CHECK-INST: fmov z0.d, p0/m, #-14.00000000 // CHECK-ENCODING: [0x80,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d5 d0 05 fmov z0.d, p0/m, #-14.50000000 // CHECK-INST: fmov z0.d, p0/m, #-14.50000000 // CHECK-ENCODING: [0xa0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d5 d0 05 fmov z0.d, p0/m, #-15.00000000 // CHECK-INST: fmov z0.d, p0/m, #-15.00000000 // CHECK-ENCODING: [0xc0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d5 d0 05 fmov z0.d, p0/m, #-15.50000000 // CHECK-INST: fmov z0.d, p0/m, #-15.50000000 // CHECK-ENCODING: [0xe0,0xd5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d5 d0 05 fmov z0.d, p0/m, #-16.00000000 // CHECK-INST: fmov z0.d, p0/m, #-16.00000000 // CHECK-ENCODING: [0x00,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d6 d0 05 fmov z0.d, p0/m, #-17.00000000 // CHECK-INST: fmov z0.d, p0/m, #-17.00000000 // CHECK-ENCODING: [0x20,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d6 d0 05 fmov z0.d, p0/m, #-18.00000000 // CHECK-INST: fmov z0.d, p0/m, #-18.00000000 // CHECK-ENCODING: [0x40,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d6 d0 05 fmov z0.d, p0/m, #-19.00000000 // CHECK-INST: fmov z0.d, p0/m, #-19.00000000 // CHECK-ENCODING: [0x60,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d6 d0 05 fmov z0.d, p0/m, #-20.00000000 // CHECK-INST: fmov z0.d, p0/m, #-20.00000000 // CHECK-ENCODING: [0x80,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d6 d0 05 fmov z0.d, p0/m, #-21.00000000 // CHECK-INST: fmov z0.d, p0/m, #-21.00000000 // CHECK-ENCODING: [0xa0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d6 d0 05 fmov z0.d, p0/m, #-22.00000000 // CHECK-INST: fmov z0.d, p0/m, #-22.00000000 // CHECK-ENCODING: [0xc0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d6 d0 05 fmov z0.d, p0/m, #-23.00000000 // CHECK-INST: fmov z0.d, p0/m, #-23.00000000 // CHECK-ENCODING: [0xe0,0xd6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d6 d0 05 fmov z0.d, p0/m, #-24.00000000 // CHECK-INST: fmov z0.d, p0/m, #-24.00000000 // CHECK-ENCODING: [0x00,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d7 d0 05 fmov z0.d, p0/m, #-25.00000000 // CHECK-INST: fmov z0.d, p0/m, #-25.00000000 // CHECK-ENCODING: [0x20,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 d7 d0 05 fmov z0.d, p0/m, #-26.00000000 // CHECK-INST: fmov z0.d, p0/m, #-26.00000000 // CHECK-ENCODING: [0x40,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 d7 d0 05 fmov z0.d, p0/m, #-27.00000000 // CHECK-INST: fmov z0.d, p0/m, #-27.00000000 // CHECK-ENCODING: [0x60,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 d7 d0 05 fmov z0.d, p0/m, #-28.00000000 // CHECK-INST: fmov z0.d, p0/m, #-28.00000000 // CHECK-ENCODING: [0x80,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 d7 d0 05 fmov z0.d, p0/m, #-29.00000000 // CHECK-INST: fmov z0.d, p0/m, #-29.00000000 // CHECK-ENCODING: [0xa0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 d7 d0 05 fmov z0.d, p0/m, #-30.00000000 // CHECK-INST: fmov z0.d, p0/m, #-30.00000000 // CHECK-ENCODING: [0xc0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 d7 d0 05 fmov z0.d, p0/m, #-31.00000000 // CHECK-INST: fmov z0.d, p0/m, #-31.00000000 // CHECK-ENCODING: [0xe0,0xd7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 d7 d0 05 fmov z0.d, p0/m, #0.12500000 // CHECK-INST: fmov z0.d, p0/m, #0.12500000 // CHECK-ENCODING: [0x00,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 d0 05 fmov z0.d, p0/m, #0.13281250 // CHECK-INST: fmov z0.d, p0/m, #0.13281250 // CHECK-ENCODING: [0x20,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c8 d0 05 fmov z0.d, p0/m, #0.14062500 // CHECK-INST: fmov z0.d, p0/m, #0.14062500 // CHECK-ENCODING: [0x40,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c8 d0 05 fmov z0.d, p0/m, #0.14843750 // CHECK-INST: fmov z0.d, p0/m, #0.14843750 // CHECK-ENCODING: [0x60,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c8 d0 05 fmov z0.d, p0/m, #0.15625000 // CHECK-INST: fmov z0.d, p0/m, #0.15625000 // CHECK-ENCODING: [0x80,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c8 d0 05 fmov z0.d, p0/m, #0.16406250 // CHECK-INST: fmov z0.d, p0/m, #0.16406250 // CHECK-ENCODING: [0xa0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c8 d0 05 fmov z0.d, p0/m, #0.17187500 // CHECK-INST: fmov z0.d, p0/m, #0.17187500 // CHECK-ENCODING: [0xc0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c8 d0 05 fmov z0.d, p0/m, #0.17968750 // CHECK-INST: fmov z0.d, p0/m, #0.17968750 // CHECK-ENCODING: [0xe0,0xc8,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c8 d0 05 fmov z0.d, p0/m, #0.18750000 // CHECK-INST: fmov z0.d, p0/m, #0.18750000 // CHECK-ENCODING: [0x00,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c9 d0 05 fmov z0.d, p0/m, #0.19531250 // CHECK-INST: fmov z0.d, p0/m, #0.19531250 // CHECK-ENCODING: [0x20,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c9 d0 05 fmov z0.d, p0/m, #0.20312500 // CHECK-INST: fmov z0.d, p0/m, #0.20312500 // CHECK-ENCODING: [0x40,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c9 d0 05 fmov z0.d, p0/m, #0.21093750 // CHECK-INST: fmov z0.d, p0/m, #0.21093750 // CHECK-ENCODING: [0x60,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c9 d0 05 fmov z0.d, p0/m, #0.21875000 // CHECK-INST: fmov z0.d, p0/m, #0.21875000 // CHECK-ENCODING: [0x80,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c9 d0 05 fmov z0.d, p0/m, #0.22656250 // CHECK-INST: fmov z0.d, p0/m, #0.22656250 // CHECK-ENCODING: [0xa0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c9 d0 05 fmov z0.d, p0/m, #0.23437500 // CHECK-INST: fmov z0.d, p0/m, #0.23437500 // CHECK-ENCODING: [0xc0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c9 d0 05 fmov z0.d, p0/m, #0.24218750 // CHECK-INST: fmov z0.d, p0/m, #0.24218750 // CHECK-ENCODING: [0xe0,0xc9,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c9 d0 05 fmov z0.d, p0/m, #0.25000000 // CHECK-INST: fmov z0.d, p0/m, #0.25000000 // CHECK-ENCODING: [0x00,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ca d0 05 fmov z0.d, p0/m, #0.26562500 // CHECK-INST: fmov z0.d, p0/m, #0.26562500 // CHECK-ENCODING: [0x20,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ca d0 05 fmov z0.d, p0/m, #0.28125000 // CHECK-INST: fmov z0.d, p0/m, #0.28125000 // CHECK-ENCODING: [0x40,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ca d0 05 fmov z0.d, p0/m, #0.29687500 // CHECK-INST: fmov z0.d, p0/m, #0.29687500 // CHECK-ENCODING: [0x60,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ca d0 05 fmov z0.d, p0/m, #0.31250000 // CHECK-INST: fmov z0.d, p0/m, #0.31250000 // CHECK-ENCODING: [0x80,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ca d0 05 fmov z0.d, p0/m, #0.32812500 // CHECK-INST: fmov z0.d, p0/m, #0.32812500 // CHECK-ENCODING: [0xa0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ca d0 05 fmov z0.d, p0/m, #0.34375000 // CHECK-INST: fmov z0.d, p0/m, #0.34375000 // CHECK-ENCODING: [0xc0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ca d0 05 fmov z0.d, p0/m, #0.35937500 // CHECK-INST: fmov z0.d, p0/m, #0.35937500 // CHECK-ENCODING: [0xe0,0xca,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ca d0 05 fmov z0.d, p0/m, #0.37500000 // CHECK-INST: fmov z0.d, p0/m, #0.37500000 // CHECK-ENCODING: [0x00,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cb d0 05 fmov z0.d, p0/m, #0.39062500 // CHECK-INST: fmov z0.d, p0/m, #0.39062500 // CHECK-ENCODING: [0x20,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cb d0 05 fmov z0.d, p0/m, #0.40625000 // CHECK-INST: fmov z0.d, p0/m, #0.40625000 // CHECK-ENCODING: [0x40,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cb d0 05 fmov z0.d, p0/m, #0.42187500 // CHECK-INST: fmov z0.d, p0/m, #0.42187500 // CHECK-ENCODING: [0x60,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cb d0 05 fmov z0.d, p0/m, #0.43750000 // CHECK-INST: fmov z0.d, p0/m, #0.43750000 // CHECK-ENCODING: [0x80,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cb d0 05 fmov z0.d, p0/m, #0.45312500 // CHECK-INST: fmov z0.d, p0/m, #0.45312500 // CHECK-ENCODING: [0xa0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cb d0 05 fmov z0.d, p0/m, #0.46875000 // CHECK-INST: fmov z0.d, p0/m, #0.46875000 // CHECK-ENCODING: [0xc0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cb d0 05 fmov z0.d, p0/m, #0.48437500 // CHECK-INST: fmov z0.d, p0/m, #0.48437500 // CHECK-ENCODING: [0xe0,0xcb,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb d0 05 fmov z0.d, p0/m, #0.50000000 // CHECK-INST: fmov z0.d, p0/m, #0.50000000 // CHECK-ENCODING: [0x00,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc d0 05 fmov z0.d, p0/m, #0.53125000 // CHECK-INST: fmov z0.d, p0/m, #0.53125000 // CHECK-ENCODING: [0x20,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cc d0 05 fmov z0.d, p0/m, #0.56250000 // CHECK-INST: fmov z0.d, p0/m, #0.56250000 // CHECK-ENCODING: [0x40,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cc d0 05 fmov z0.d, p0/m, #0.59375000 // CHECK-INST: fmov z0.d, p0/m, #0.59375000 // CHECK-ENCODING: [0x60,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cc d0 05 fmov z0.d, p0/m, #0.62500000 // CHECK-INST: fmov z0.d, p0/m, #0.62500000 // CHECK-ENCODING: [0x80,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cc d0 05 fmov z0.d, p0/m, #0.65625000 // CHECK-INST: fmov z0.d, p0/m, #0.65625000 // CHECK-ENCODING: [0xa0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cc d0 05 fmov z0.d, p0/m, #0.68750000 // CHECK-INST: fmov z0.d, p0/m, #0.68750000 // CHECK-ENCODING: [0xc0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cc d0 05 fmov z0.d, p0/m, #0.71875000 // CHECK-INST: fmov z0.d, p0/m, #0.71875000 // CHECK-ENCODING: [0xe0,0xcc,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cc d0 05 fmov z0.d, p0/m, #0.75000000 // CHECK-INST: fmov z0.d, p0/m, #0.75000000 // CHECK-ENCODING: [0x00,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cd d0 05 fmov z0.d, p0/m, #0.78125000 // CHECK-INST: fmov z0.d, p0/m, #0.78125000 // CHECK-ENCODING: [0x20,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cd d0 05 fmov z0.d, p0/m, #0.81250000 // CHECK-INST: fmov z0.d, p0/m, #0.81250000 // CHECK-ENCODING: [0x40,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cd d0 05 fmov z0.d, p0/m, #0.84375000 // CHECK-INST: fmov z0.d, p0/m, #0.84375000 // CHECK-ENCODING: [0x60,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cd d0 05 fmov z0.d, p0/m, #0.87500000 // CHECK-INST: fmov z0.d, p0/m, #0.87500000 // CHECK-ENCODING: [0x80,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cd d0 05 fmov z0.d, p0/m, #0.90625000 // CHECK-INST: fmov z0.d, p0/m, #0.90625000 // CHECK-ENCODING: [0xa0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cd d0 05 fmov z0.d, p0/m, #0.93750000 // CHECK-INST: fmov z0.d, p0/m, #0.93750000 // CHECK-ENCODING: [0xc0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cd d0 05 fmov z0.d, p0/m, #0.96875000 // CHECK-INST: fmov z0.d, p0/m, #0.96875000 // CHECK-ENCODING: [0xe0,0xcd,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cd d0 05 fmov z0.d, p0/m, #1.00000000 // CHECK-INST: fmov z0.d, p0/m, #1.00000000 // CHECK-ENCODING: [0x00,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ce d0 05 fmov z0.d, p0/m, #1.06250000 // CHECK-INST: fmov z0.d, p0/m, #1.06250000 // CHECK-ENCODING: [0x20,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ce d0 05 fmov z0.d, p0/m, #1.12500000 // CHECK-INST: fmov z0.d, p0/m, #1.12500000 // CHECK-ENCODING: [0x40,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ce d0 05 fmov z0.d, p0/m, #1.18750000 // CHECK-INST: fmov z0.d, p0/m, #1.18750000 // CHECK-ENCODING: [0x60,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ce d0 05 fmov z0.d, p0/m, #1.25000000 // CHECK-INST: fmov z0.d, p0/m, #1.25000000 // CHECK-ENCODING: [0x80,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ce d0 05 fmov z0.d, p0/m, #1.31250000 // CHECK-INST: fmov z0.d, p0/m, #1.31250000 // CHECK-ENCODING: [0xa0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ce d0 05 fmov z0.d, p0/m, #1.37500000 // CHECK-INST: fmov z0.d, p0/m, #1.37500000 // CHECK-ENCODING: [0xc0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 ce d0 05 fmov z0.d, p0/m, #1.43750000 // CHECK-INST: fmov z0.d, p0/m, #1.43750000 // CHECK-ENCODING: [0xe0,0xce,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ce d0 05 fmov z0.d, p0/m, #1.50000000 // CHECK-INST: fmov z0.d, p0/m, #1.50000000 // CHECK-ENCODING: [0x00,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cf d0 05 fmov z0.d, p0/m, #1.56250000 // CHECK-INST: fmov z0.d, p0/m, #1.56250000 // CHECK-ENCODING: [0x20,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 cf d0 05 fmov z0.d, p0/m, #1.62500000 // CHECK-INST: fmov z0.d, p0/m, #1.62500000 // CHECK-ENCODING: [0x40,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 cf d0 05 fmov z0.d, p0/m, #1.68750000 // CHECK-INST: fmov z0.d, p0/m, #1.68750000 // CHECK-ENCODING: [0x60,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 cf d0 05 fmov z0.d, p0/m, #1.75000000 // CHECK-INST: fmov z0.d, p0/m, #1.75000000 // CHECK-ENCODING: [0x80,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 cf d0 05 fmov z0.d, p0/m, #1.81250000 // CHECK-INST: fmov z0.d, p0/m, #1.81250000 // CHECK-ENCODING: [0xa0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 cf d0 05 fmov z0.d, p0/m, #1.87500000 // CHECK-INST: fmov z0.d, p0/m, #1.87500000 // CHECK-ENCODING: [0xc0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 cf d0 05 fmov z0.d, p0/m, #1.93750000 // CHECK-INST: fmov z0.d, p0/m, #1.93750000 // CHECK-ENCODING: [0xe0,0xcf,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf d0 05 fmov z0.d, p0/m, #2.00000000 // CHECK-INST: fmov z0.d, p0/m, #2.00000000 // CHECK-ENCODING: [0x00,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 d0 05 fmov z0.d, p0/m, #2.12500000 // CHECK-INST: fmov z0.d, p0/m, #2.12500000 // CHECK-ENCODING: [0x20,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c0 d0 05 fmov z0.d, p0/m, #2.25000000 // CHECK-INST: fmov z0.d, p0/m, #2.25000000 // CHECK-ENCODING: [0x40,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c0 d0 05 fmov z0.d, p0/m, #2.37500000 // CHECK-INST: fmov z0.d, p0/m, #2.37500000 // CHECK-ENCODING: [0x60,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c0 d0 05 fmov z0.d, p0/m, #2.50000000 // CHECK-INST: fmov z0.d, p0/m, #2.50000000 // CHECK-ENCODING: [0x80,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c0 d0 05 fmov z0.d, p0/m, #2.62500000 // CHECK-INST: fmov z0.d, p0/m, #2.62500000 // CHECK-ENCODING: [0xa0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c0 d0 05 fmov z0.d, p0/m, #2.75000000 // CHECK-INST: fmov z0.d, p0/m, #2.75000000 // CHECK-ENCODING: [0xc0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c0 d0 05 fmov z0.d, p0/m, #2.87500000 // CHECK-INST: fmov z0.d, p0/m, #2.87500000 // CHECK-ENCODING: [0xe0,0xc0,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c0 d0 05 fmov z0.d, p0/m, #3.00000000 // CHECK-INST: fmov z0.d, p0/m, #3.00000000 // CHECK-ENCODING: [0x00,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c1 d0 05 fmov z0.d, p0/m, #3.12500000 // CHECK-INST: fmov z0.d, p0/m, #3.12500000 // CHECK-ENCODING: [0x20,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c1 d0 05 fmov z0.d, p0/m, #3.25000000 // CHECK-INST: fmov z0.d, p0/m, #3.25000000 // CHECK-ENCODING: [0x40,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c1 d0 05 fmov z0.d, p0/m, #3.37500000 // CHECK-INST: fmov z0.d, p0/m, #3.37500000 // CHECK-ENCODING: [0x60,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c1 d0 05 fmov z0.d, p0/m, #3.50000000 // CHECK-INST: fmov z0.d, p0/m, #3.50000000 // CHECK-ENCODING: [0x80,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c1 d0 05 fmov z0.d, p0/m, #3.62500000 // CHECK-INST: fmov z0.d, p0/m, #3.62500000 // CHECK-ENCODING: [0xa0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c1 d0 05 fmov z0.d, p0/m, #3.75000000 // CHECK-INST: fmov z0.d, p0/m, #3.75000000 // CHECK-ENCODING: [0xc0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c1 d0 05 fmov z0.d, p0/m, #3.87500000 // CHECK-INST: fmov z0.d, p0/m, #3.87500000 // CHECK-ENCODING: [0xe0,0xc1,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c1 d0 05 fmov z0.d, p0/m, #4.00000000 // CHECK-INST: fmov z0.d, p0/m, #4.00000000 // CHECK-ENCODING: [0x00,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c2 d0 05 fmov z0.d, p0/m, #4.25000000 // CHECK-INST: fmov z0.d, p0/m, #4.25000000 // CHECK-ENCODING: [0x20,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c2 d0 05 fmov z0.d, p0/m, #4.50000000 // CHECK-INST: fmov z0.d, p0/m, #4.50000000 // CHECK-ENCODING: [0x40,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c2 d0 05 fmov z0.d, p0/m, #4.75000000 // CHECK-INST: fmov z0.d, p0/m, #4.75000000 // CHECK-ENCODING: [0x60,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c2 d0 05 fmov z0.d, p0/m, #5.00000000 // CHECK-INST: fmov z0.d, p0/m, #5.00000000 // CHECK-ENCODING: [0x80,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c2 d0 05 fmov z0.d, p0/m, #5.25000000 // CHECK-INST: fmov z0.d, p0/m, #5.25000000 // CHECK-ENCODING: [0xa0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c2 d0 05 fmov z0.d, p0/m, #5.50000000 // CHECK-INST: fmov z0.d, p0/m, #5.50000000 // CHECK-ENCODING: [0xc0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c2 d0 05 fmov z0.d, p0/m, #5.75000000 // CHECK-INST: fmov z0.d, p0/m, #5.75000000 // CHECK-ENCODING: [0xe0,0xc2,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c2 d0 05 fmov z0.d, p0/m, #6.00000000 // CHECK-INST: fmov z0.d, p0/m, #6.00000000 // CHECK-ENCODING: [0x00,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c3 d0 05 fmov z0.d, p0/m, #6.25000000 // CHECK-INST: fmov z0.d, p0/m, #6.25000000 // CHECK-ENCODING: [0x20,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c3 d0 05 fmov z0.d, p0/m, #6.50000000 // CHECK-INST: fmov z0.d, p0/m, #6.50000000 // CHECK-ENCODING: [0x40,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c3 d0 05 fmov z0.d, p0/m, #6.75000000 // CHECK-INST: fmov z0.d, p0/m, #6.75000000 // CHECK-ENCODING: [0x60,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c3 d0 05 fmov z0.d, p0/m, #7.00000000 // CHECK-INST: fmov z0.d, p0/m, #7.00000000 // CHECK-ENCODING: [0x80,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c3 d0 05 fmov z0.d, p0/m, #7.25000000 // CHECK-INST: fmov z0.d, p0/m, #7.25000000 // CHECK-ENCODING: [0xa0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c3 d0 05 fmov z0.d, p0/m, #7.50000000 // CHECK-INST: fmov z0.d, p0/m, #7.50000000 // CHECK-ENCODING: [0xc0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c3 d0 05 fmov z0.d, p0/m, #7.75000000 // CHECK-INST: fmov z0.d, p0/m, #7.75000000 // CHECK-ENCODING: [0xe0,0xc3,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 d0 05 fmov z0.d, p0/m, #8.00000000 // CHECK-INST: fmov z0.d, p0/m, #8.00000000 // CHECK-ENCODING: [0x00,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 d0 05 fmov z0.d, p0/m, #8.50000000 // CHECK-INST: fmov z0.d, p0/m, #8.50000000 // CHECK-ENCODING: [0x20,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c4 d0 05 fmov z0.d, p0/m, #9.00000000 // CHECK-INST: fmov z0.d, p0/m, #9.00000000 // CHECK-ENCODING: [0x40,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c4 d0 05 fmov z0.d, p0/m, #9.50000000 // CHECK-INST: fmov z0.d, p0/m, #9.50000000 // CHECK-ENCODING: [0x60,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c4 d0 05 fmov z0.d, p0/m, #10.00000000 // CHECK-INST: fmov z0.d, p0/m, #10.00000000 // CHECK-ENCODING: [0x80,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c4 d0 05 fmov z0.d, p0/m, #10.50000000 // CHECK-INST: fmov z0.d, p0/m, #10.50000000 // CHECK-ENCODING: [0xa0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c4 d0 05 fmov z0.d, p0/m, #11.00000000 // CHECK-INST: fmov z0.d, p0/m, #11.00000000 // CHECK-ENCODING: [0xc0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c4 d0 05 fmov z0.d, p0/m, #11.50000000 // CHECK-INST: fmov z0.d, p0/m, #11.50000000 // CHECK-ENCODING: [0xe0,0xc4,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c4 d0 05 fmov z0.d, p0/m, #12.00000000 // CHECK-INST: fmov z0.d, p0/m, #12.00000000 // CHECK-ENCODING: [0x00,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c5 d0 05 fmov z0.d, p0/m, #12.50000000 // CHECK-INST: fmov z0.d, p0/m, #12.50000000 // CHECK-ENCODING: [0x20,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c5 d0 05 fmov z0.d, p0/m, #13.00000000 // CHECK-INST: fmov z0.d, p0/m, #13.00000000 // CHECK-ENCODING: [0x40,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c5 d0 05 fmov z0.d, p0/m, #13.50000000 // CHECK-INST: fmov z0.d, p0/m, #13.50000000 // CHECK-ENCODING: [0x60,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c5 d0 05 fmov z0.d, p0/m, #14.00000000 // CHECK-INST: fmov z0.d, p0/m, #14.00000000 // CHECK-ENCODING: [0x80,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c5 d0 05 fmov z0.d, p0/m, #14.50000000 // CHECK-INST: fmov z0.d, p0/m, #14.50000000 // CHECK-ENCODING: [0xa0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c5 d0 05 fmov z0.d, p0/m, #15.00000000 // CHECK-INST: fmov z0.d, p0/m, #15.00000000 // CHECK-ENCODING: [0xc0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c5 d0 05 fmov z0.d, p0/m, #15.50000000 // CHECK-INST: fmov z0.d, p0/m, #15.50000000 // CHECK-ENCODING: [0xe0,0xc5,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 d0 05 fmov z0.d, p0/m, #16.00000000 // CHECK-INST: fmov z0.d, p0/m, #16.00000000 // CHECK-ENCODING: [0x00,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c6 d0 05 fmov z0.d, p0/m, #17.00000000 // CHECK-INST: fmov z0.d, p0/m, #17.00000000 // CHECK-ENCODING: [0x20,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c6 d0 05 fmov z0.d, p0/m, #18.00000000 // CHECK-INST: fmov z0.d, p0/m, #18.00000000 // CHECK-ENCODING: [0x40,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c6 d0 05 fmov z0.d, p0/m, #19.00000000 // CHECK-INST: fmov z0.d, p0/m, #19.00000000 // CHECK-ENCODING: [0x60,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c6 d0 05 fmov z0.d, p0/m, #20.00000000 // CHECK-INST: fmov z0.d, p0/m, #20.00000000 // CHECK-ENCODING: [0x80,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c6 d0 05 fmov z0.d, p0/m, #21.00000000 // CHECK-INST: fmov z0.d, p0/m, #21.00000000 // CHECK-ENCODING: [0xa0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c6 d0 05 fmov z0.d, p0/m, #22.00000000 // CHECK-INST: fmov z0.d, p0/m, #22.00000000 // CHECK-ENCODING: [0xc0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c6 d0 05 fmov z0.d, p0/m, #23.00000000 // CHECK-INST: fmov z0.d, p0/m, #23.00000000 // CHECK-ENCODING: [0xe0,0xc6,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c6 d0 05 fmov z0.d, p0/m, #24.00000000 // CHECK-INST: fmov z0.d, p0/m, #24.00000000 // CHECK-ENCODING: [0x00,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c7 d0 05 fmov z0.d, p0/m, #25.00000000 // CHECK-INST: fmov z0.d, p0/m, #25.00000000 // CHECK-ENCODING: [0x20,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 c7 d0 05 fmov z0.d, p0/m, #26.00000000 // CHECK-INST: fmov z0.d, p0/m, #26.00000000 // CHECK-ENCODING: [0x40,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 c7 d0 05 fmov z0.d, p0/m, #27.00000000 // CHECK-INST: fmov z0.d, p0/m, #27.00000000 // CHECK-ENCODING: [0x60,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 c7 d0 05 fmov z0.d, p0/m, #28.00000000 // CHECK-INST: fmov z0.d, p0/m, #28.00000000 // CHECK-ENCODING: [0x80,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 c7 d0 05 fmov z0.d, p0/m, #29.00000000 // CHECK-INST: fmov z0.d, p0/m, #29.00000000 // CHECK-ENCODING: [0xa0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 c7 d0 05 fmov z0.d, p0/m, #30.00000000 // CHECK-INST: fmov z0.d, p0/m, #30.00000000 // CHECK-ENCODING: [0xc0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 c7 d0 05 fmov z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 @@ -1606,23 +1606,23 @@ fmov z0.d, p0/m, #31.00000000 movprfx z0.d, p0/z, z7.d // CHECK-INST: movprfx z0.d, p0/z, z7.d // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 d0 04 fmov z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmov z0.d, p0/m, #31.00000000 // CHECK-INST: fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 d0 05 diff --git a/llvm/test/MC/AArch64/SVE/fmsb.s b/llvm/test/MC/AArch64/SVE/fmsb.s index e894ef630f88d..58413f2387a2f 100644 --- a/llvm/test/MC/AArch64/SVE/fmsb.s +++ b/llvm/test/MC/AArch64/SVE/fmsb.s @@ -12,19 +12,19 @@ fmsb z0.h, p7/m, z1.h, z31.h // CHECK-INST: fmsb z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0xbc,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc 7f 65 fmsb z0.s, p7/m, z1.s, z31.s // CHECK-INST: fmsb z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0xbc,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc bf 65 fmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xbc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc ff 65 @@ -34,23 +34,23 @@ fmsb z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xbc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xbc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc ff 65 diff --git a/llvm/test/MC/AArch64/SVE/fmul.s b/llvm/test/MC/AArch64/SVE/fmul.s index 8101f92a07f6e..9d5c7ff683ecc 100644 --- a/llvm/test/MC/AArch64/SVE/fmul.s +++ b/llvm/test/MC/AArch64/SVE/fmul.s @@ -12,115 +12,115 @@ fmul z0.h, p0/m, z0.h, #0.5000000000000 // CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5a 65 fmul z0.h, p0/m, z0.h, #0.5 // CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5a 65 fmul z0.s, p0/m, z0.s, #0.5 // CHECK-INST: fmul z0.s, p0/m, z0.s, #0.5 // CHECK-ENCODING: [0x00,0x80,0x9a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9a 65 fmul z0.d, p0/m, z0.d, #0.5 // CHECK-INST: fmul z0.d, p0/m, z0.d, #0.5 // CHECK-ENCODING: [0x00,0x80,0xda,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 da 65 fmul z31.h, p7/m, z31.h, #2.0 // CHECK-INST: fmul z31.h, p7/m, z31.h, #2.0 // CHECK-ENCODING: [0x3f,0x9c,0x5a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5a 65 fmul z31.s, p7/m, z31.s, #2.0 // CHECK-INST: fmul z31.s, p7/m, z31.s, #2.0 // CHECK-ENCODING: [0x3f,0x9c,0x9a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9a 65 fmul z31.d, p7/m, z31.d, #2.0 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c da 65 fmul z0.h, z0.h, z0.h[0] // CHECK-INST: fmul z0.h, z0.h, z0.h[0] // CHECK-ENCODING: [0x00,0x20,0x20,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 20 64 fmul z0.s, z0.s, z0.s[0] // CHECK-INST: fmul z0.s, z0.s, z0.s[0] // CHECK-ENCODING: [0x00,0x20,0xa0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 a0 64 fmul z0.d, z0.d, z0.d[0] // CHECK-INST: fmul z0.d, z0.d, z0.d[0] // CHECK-ENCODING: [0x00,0x20,0xe0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 e0 64 fmul z31.h, z31.h, z7.h[7] // CHECK-INST: fmul z31.h, z31.h, z7.h[7] // CHECK-ENCODING: [0xff,0x23,0x7f,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 7f 64 fmul z31.s, z31.s, z7.s[3] // CHECK-INST: fmul z31.s, z31.s, z7.s[3] // CHECK-ENCODING: [0xff,0x23,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 bf 64 fmul z31.d, z31.d, z15.d[1] // CHECK-INST: fmul z31.d, z31.d, z15.d[1] // CHECK-ENCODING: [0xff,0x23,0xff,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 ff 64 fmul z0.h, p7/m, z0.h, z31.h // CHECK-INST: fmul z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x42,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 42 65 fmul z0.s, p7/m, z0.s, z31.s // CHECK-INST: fmul z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x82,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 82 65 fmul z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c2 65 fmul z0.h, z1.h, z31.h // CHECK-INST: fmul z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x08,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 08 5f 65 fmul z0.s, z1.s, z31.s // CHECK-INST: fmul z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x08,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 08 9f 65 fmul z0.d, z1.d, z31.d // CHECK-INST: fmul z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x08,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 08 df 65 @@ -130,47 +130,47 @@ fmul z0.d, z1.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fmul z31.d, p7/m, z31.d, #2.0 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c da 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fmul z31.d, p7/m, z31.d, #2.0 // CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c da 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmul z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c2 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmul z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c2 65 diff --git a/llvm/test/MC/AArch64/SVE/fmulx.s b/llvm/test/MC/AArch64/SVE/fmulx.s index ed8913a78a2ff..e2f5a00895976 100644 --- a/llvm/test/MC/AArch64/SVE/fmulx.s +++ b/llvm/test/MC/AArch64/SVE/fmulx.s @@ -12,19 +12,19 @@ fmulx z0.h, p7/m, z0.h, z31.h // CHECK-INST: fmulx z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x4a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 4a 65 fmulx z0.s, p7/m, z0.s, z31.s // CHECK-INST: fmulx z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x8a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 8a 65 fmulx z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f ca 65 @@ -34,23 +34,23 @@ fmulx z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fmulx z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f ca 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fmulx z0.d, p7/m, z0.d, z31.d // CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f ca 65 diff --git a/llvm/test/MC/AArch64/SVE/fneg.s b/llvm/test/MC/AArch64/SVE/fneg.s index 850dab58fb57a..96b4ebd2fbddf 100644 --- a/llvm/test/MC/AArch64/SVE/fneg.s +++ b/llvm/test/MC/AArch64/SVE/fneg.s @@ -12,19 +12,19 @@ fneg z31.h, p7/m, z31.h // CHECK-INST: fneg z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x5d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 5d 04 fneg z31.s, p7/m, z31.s // CHECK-INST: fneg z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x9d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 9d 04 fneg z31.d, p7/m, z31.d // CHECK-INST: fneg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf dd 04 @@ -34,23 +34,23 @@ fneg z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 fneg z4.d, p7/m, z31.d // CHECK-INST: fneg z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf dd 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 fneg z4.d, p7/m, z31.d // CHECK-INST: fneg z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf dd 04 diff --git a/llvm/test/MC/AArch64/SVE/fnmad.s b/llvm/test/MC/AArch64/SVE/fnmad.s index 2ced184793d94..c2efaf73a4456 100644 --- a/llvm/test/MC/AArch64/SVE/fnmad.s +++ b/llvm/test/MC/AArch64/SVE/fnmad.s @@ -12,19 +12,19 @@ fnmad z0.h, p7/m, z1.h, z31.h // CHECK-INST: fnmad z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0xdc,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc 7f 65 fnmad z0.s, p7/m, z1.s, z31.s // CHECK-INST: fnmad z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0xdc,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc bf 65 fnmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xdc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc ff 65 @@ -34,23 +34,23 @@ fnmad z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fnmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xdc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fnmad z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xdc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 dc ff 65 diff --git a/llvm/test/MC/AArch64/SVE/fnmla.s b/llvm/test/MC/AArch64/SVE/fnmla.s index 86dcbb427e9af..5dc4da4960fa1 100644 --- a/llvm/test/MC/AArch64/SVE/fnmla.s +++ b/llvm/test/MC/AArch64/SVE/fnmla.s @@ -12,19 +12,19 @@ fnmla z0.h, p7/m, z1.h, z31.h // CHECK-INST: fnmla z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x5c,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c 7f 65 fnmla z0.s, p7/m, z1.s, z31.s // CHECK-INST: fnmla z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x5c,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c bf 65 fnmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c ff 65 @@ -34,23 +34,23 @@ fnmla z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fnmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fnmla z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c ff 65 diff --git a/llvm/test/MC/AArch64/SVE/fnmls.s b/llvm/test/MC/AArch64/SVE/fnmls.s index b46e1ab0f6416..09b53ae18d408 100644 --- a/llvm/test/MC/AArch64/SVE/fnmls.s +++ b/llvm/test/MC/AArch64/SVE/fnmls.s @@ -12,19 +12,19 @@ fnmls z0.h, p7/m, z1.h, z31.h // CHECK-INST: fnmls z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x7c,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 7f 65 fnmls z0.s, p7/m, z1.s, z31.s // CHECK-INST: fnmls z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x7c,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c bf 65 fnmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c ff 65 @@ -34,23 +34,23 @@ fnmls z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fnmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fnmls z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c ff 65 diff --git a/llvm/test/MC/AArch64/SVE/fnmsb.s b/llvm/test/MC/AArch64/SVE/fnmsb.s index eb0c6e5b60e00..c114e1e646820 100644 --- a/llvm/test/MC/AArch64/SVE/fnmsb.s +++ b/llvm/test/MC/AArch64/SVE/fnmsb.s @@ -12,19 +12,19 @@ fnmsb z0.h, p7/m, z1.h, z31.h // CHECK-INST: fnmsb z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0xfc,0x7f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc 7f 65 fnmsb z0.s, p7/m, z1.s, z31.s // CHECK-INST: fnmsb z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0xfc,0xbf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc bf 65 fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc ff 65 @@ -34,23 +34,23 @@ fnmsb z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc ff 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xff,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc ff 65 diff --git a/llvm/test/MC/AArch64/SVE/frecpe.s b/llvm/test/MC/AArch64/SVE/frecpe.s index eae3114b9d094..61883653cfd96 100644 --- a/llvm/test/MC/AArch64/SVE/frecpe.s +++ b/llvm/test/MC/AArch64/SVE/frecpe.s @@ -12,17 +12,17 @@ frecpe z0.h, z31.h // CHECK-INST: frecpe z0.h, z31.h // CHECK-ENCODING: [0xe0,0x33,0x4e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 4e 65 frecpe z0.s, z31.s // CHECK-INST: frecpe z0.s, z31.s // CHECK-ENCODING: [0xe0,0x33,0x8e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 8e 65 frecpe z0.d, z31.d // CHECK-INST: frecpe z0.d, z31.d // CHECK-ENCODING: [0xe0,0x33,0xce,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 ce 65 diff --git a/llvm/test/MC/AArch64/SVE/frecps.s b/llvm/test/MC/AArch64/SVE/frecps.s index a09ce28885099..97ac6d1fa8835 100644 --- a/llvm/test/MC/AArch64/SVE/frecps.s +++ b/llvm/test/MC/AArch64/SVE/frecps.s @@ -12,17 +12,17 @@ frecps z0.h, z1.h, z31.h // CHECK-INST: frecps z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x18,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 18 5f 65 frecps z0.s, z1.s, z31.s // CHECK-INST: frecps z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x18,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 18 9f 65 frecps z0.d, z1.d, z31.d // CHECK-INST: frecps z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x18,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 18 df 65 diff --git a/llvm/test/MC/AArch64/SVE/frecpx.s b/llvm/test/MC/AArch64/SVE/frecpx.s index 8504632e1d28b..66c717ec005c6 100644 --- a/llvm/test/MC/AArch64/SVE/frecpx.s +++ b/llvm/test/MC/AArch64/SVE/frecpx.s @@ -12,19 +12,19 @@ frecpx z31.h, p7/m, z31.h // CHECK-INST: frecpx z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x4c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 4c 65 frecpx z31.s, p7/m, z31.s // CHECK-INST: frecpx z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x8c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 8c 65 frecpx z31.d, p7/m, z31.d // CHECK-INST: frecpx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf cc 65 @@ -34,23 +34,23 @@ frecpx z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frecpx z4.d, p7/m, z31.d // CHECK-INST: frecpx z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf cc 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frecpx z4.d, p7/m, z31.d // CHECK-INST: frecpx z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf cc 65 diff --git a/llvm/test/MC/AArch64/SVE/frinta.s b/llvm/test/MC/AArch64/SVE/frinta.s index d687e79a292df..e30b83f417b30 100644 --- a/llvm/test/MC/AArch64/SVE/frinta.s +++ b/llvm/test/MC/AArch64/SVE/frinta.s @@ -12,19 +12,19 @@ frinta z31.h, p7/m, z31.h // CHECK-INST: frinta z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x44,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 44 65 frinta z31.s, p7/m, z31.s // CHECK-INST: frinta z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x84,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 84 65 frinta z31.d, p7/m, z31.d // CHECK-INST: frinta z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c4 65 @@ -34,23 +34,23 @@ frinta z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frinta z4.d, p7/m, z31.d // CHECK-INST: frinta z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c4 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frinta z4.d, p7/m, z31.d // CHECK-INST: frinta z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c4 65 diff --git a/llvm/test/MC/AArch64/SVE/frinti.s b/llvm/test/MC/AArch64/SVE/frinti.s index 210bb58d83df8..82392b67abb8c 100644 --- a/llvm/test/MC/AArch64/SVE/frinti.s +++ b/llvm/test/MC/AArch64/SVE/frinti.s @@ -12,19 +12,19 @@ frinti z31.h, p7/m, z31.h // CHECK-INST: frinti z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x47,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 47 65 frinti z31.s, p7/m, z31.s // CHECK-INST: frinti z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x87,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 87 65 frinti z31.d, p7/m, z31.d // CHECK-INST: frinti z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c7 65 @@ -34,23 +34,23 @@ frinti z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frinti z4.d, p7/m, z31.d // CHECK-INST: frinti z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c7 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frinti z4.d, p7/m, z31.d // CHECK-INST: frinti z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c7 65 diff --git a/llvm/test/MC/AArch64/SVE/frintm.s b/llvm/test/MC/AArch64/SVE/frintm.s index ed1968655b10a..b5271fc52f111 100644 --- a/llvm/test/MC/AArch64/SVE/frintm.s +++ b/llvm/test/MC/AArch64/SVE/frintm.s @@ -12,19 +12,19 @@ frintm z31.h, p7/m, z31.h // CHECK-INST: frintm z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x42,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 42 65 frintm z31.s, p7/m, z31.s // CHECK-INST: frintm z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x82,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 82 65 frintm z31.d, p7/m, z31.d // CHECK-INST: frintm z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c2 65 @@ -34,23 +34,23 @@ frintm z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frintm z4.d, p7/m, z31.d // CHECK-INST: frintm z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c2 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frintm z4.d, p7/m, z31.d // CHECK-INST: frintm z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c2 65 diff --git a/llvm/test/MC/AArch64/SVE/frintn.s b/llvm/test/MC/AArch64/SVE/frintn.s index f0549be1d9436..47666251ebff4 100644 --- a/llvm/test/MC/AArch64/SVE/frintn.s +++ b/llvm/test/MC/AArch64/SVE/frintn.s @@ -12,19 +12,19 @@ frintn z31.h, p7/m, z31.h // CHECK-INST: frintn z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x40,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 40 65 frintn z31.s, p7/m, z31.s // CHECK-INST: frintn z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x80,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 80 65 frintn z31.d, p7/m, z31.d // CHECK-INST: frintn z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c0 65 @@ -34,23 +34,23 @@ frintn z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frintn z4.d, p7/m, z31.d // CHECK-INST: frintn z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c0 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frintn z4.d, p7/m, z31.d // CHECK-INST: frintn z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c0 65 diff --git a/llvm/test/MC/AArch64/SVE/frintp.s b/llvm/test/MC/AArch64/SVE/frintp.s index 9a79bf722f884..06da956fcc1b4 100644 --- a/llvm/test/MC/AArch64/SVE/frintp.s +++ b/llvm/test/MC/AArch64/SVE/frintp.s @@ -12,19 +12,19 @@ frintp z31.h, p7/m, z31.h // CHECK-INST: frintp z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 41 65 frintp z31.s, p7/m, z31.s // CHECK-INST: frintp z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 81 65 frintp z31.d, p7/m, z31.d // CHECK-INST: frintp z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c1 65 @@ -34,23 +34,23 @@ frintp z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frintp z4.d, p7/m, z31.d // CHECK-INST: frintp z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c1 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frintp z4.d, p7/m, z31.d // CHECK-INST: frintp z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c1 65 diff --git a/llvm/test/MC/AArch64/SVE/frintx.s b/llvm/test/MC/AArch64/SVE/frintx.s index 73680454402a1..e0099ed03f875 100644 --- a/llvm/test/MC/AArch64/SVE/frintx.s +++ b/llvm/test/MC/AArch64/SVE/frintx.s @@ -12,19 +12,19 @@ frintx z31.h, p7/m, z31.h // CHECK-INST: frintx z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x46,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 46 65 frintx z31.s, p7/m, z31.s // CHECK-INST: frintx z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x86,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 86 65 frintx z31.d, p7/m, z31.d // CHECK-INST: frintx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c6 65 @@ -34,23 +34,23 @@ frintx z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frintx z4.d, p7/m, z31.d // CHECK-INST: frintx z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c6 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frintx z4.d, p7/m, z31.d // CHECK-INST: frintx z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c6 65 diff --git a/llvm/test/MC/AArch64/SVE/frintz.s b/llvm/test/MC/AArch64/SVE/frintz.s index 634c4a2c95e43..35e6df4c39c8d 100644 --- a/llvm/test/MC/AArch64/SVE/frintz.s +++ b/llvm/test/MC/AArch64/SVE/frintz.s @@ -12,19 +12,19 @@ frintz z31.h, p7/m, z31.h // CHECK-INST: frintz z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x43,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 43 65 frintz z31.s, p7/m, z31.s // CHECK-INST: frintz z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x83,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 83 65 frintz z31.d, p7/m, z31.d // CHECK-INST: frintz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf c3 65 @@ -34,23 +34,23 @@ frintz z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 frintz z4.d, p7/m, z31.d // CHECK-INST: frintz z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c3 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 frintz z4.d, p7/m, z31.d // CHECK-INST: frintz z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf c3 65 diff --git a/llvm/test/MC/AArch64/SVE/frsqrte.s b/llvm/test/MC/AArch64/SVE/frsqrte.s index b0771fd85c6c3..49a81f4419a2d 100644 --- a/llvm/test/MC/AArch64/SVE/frsqrte.s +++ b/llvm/test/MC/AArch64/SVE/frsqrte.s @@ -12,17 +12,17 @@ frsqrte z0.h, z31.h // CHECK-INST: frsqrte z0.h, z31.h // CHECK-ENCODING: [0xe0,0x33,0x4f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 4f 65 frsqrte z0.s, z31.s // CHECK-INST: frsqrte z0.s, z31.s // CHECK-ENCODING: [0xe0,0x33,0x8f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 8f 65 frsqrte z0.d, z31.d // CHECK-INST: frsqrte z0.d, z31.d // CHECK-ENCODING: [0xe0,0x33,0xcf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 33 cf 65 diff --git a/llvm/test/MC/AArch64/SVE/frsqrts.s b/llvm/test/MC/AArch64/SVE/frsqrts.s index 58232b842dc21..2064fc330ac80 100644 --- a/llvm/test/MC/AArch64/SVE/frsqrts.s +++ b/llvm/test/MC/AArch64/SVE/frsqrts.s @@ -12,17 +12,17 @@ frsqrts z0.h, z1.h, z31.h // CHECK-INST: frsqrts z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x1c,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c 5f 65 frsqrts z0.s, z1.s, z31.s // CHECK-INST: frsqrts z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x1c,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c 9f 65 frsqrts z0.d, z1.d, z31.d // CHECK-INST: frsqrts z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x1c,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 1c df 65 diff --git a/llvm/test/MC/AArch64/SVE/fscale.s b/llvm/test/MC/AArch64/SVE/fscale.s index 6d03003ae062a..68f24d75a7e86 100644 --- a/llvm/test/MC/AArch64/SVE/fscale.s +++ b/llvm/test/MC/AArch64/SVE/fscale.s @@ -12,19 +12,19 @@ fscale z0.h, p7/m, z0.h, z31.h // CHECK-INST: fscale z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x49,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 49 65 fscale z0.s, p7/m, z0.s, z31.s // CHECK-INST: fscale z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x89,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 89 65 fscale z0.d, p7/m, z0.d, z31.d // CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c9 65 @@ -34,23 +34,23 @@ fscale z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fscale z0.d, p7/m, z0.d, z31.d // CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c9 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fscale z0.d, p7/m, z0.d, z31.d // CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c9 65 diff --git a/llvm/test/MC/AArch64/SVE/fsqrt.s b/llvm/test/MC/AArch64/SVE/fsqrt.s index e453f42fee6ad..235bd63af4522 100644 --- a/llvm/test/MC/AArch64/SVE/fsqrt.s +++ b/llvm/test/MC/AArch64/SVE/fsqrt.s @@ -12,19 +12,19 @@ fsqrt z31.h, p7/m, z31.h // CHECK-INST: fsqrt z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x4d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 4d 65 fsqrt z31.s, p7/m, z31.s // CHECK-INST: fsqrt z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x8d,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 8d 65 fsqrt z31.d, p7/m, z31.d // CHECK-INST: fsqrt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf cd 65 @@ -34,23 +34,23 @@ fsqrt z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 fsqrt z4.d, p7/m, z31.d // CHECK-INST: fsqrt z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf cd 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 fsqrt z4.d, p7/m, z31.d // CHECK-INST: fsqrt z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf cd 65 diff --git a/llvm/test/MC/AArch64/SVE/fsub.s b/llvm/test/MC/AArch64/SVE/fsub.s index 9f8fbe53c6380..51daccc437fad 100644 --- a/llvm/test/MC/AArch64/SVE/fsub.s +++ b/llvm/test/MC/AArch64/SVE/fsub.s @@ -12,85 +12,85 @@ fsub z0.h, p0/m, z0.h, #0.500000000000000 // CHECK-INST: fsub z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x59,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 59 65 fsub z0.h, p0/m, z0.h, #0.5 // CHECK-INST: fsub z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x59,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 59 65 fsub z0.s, p0/m, z0.s, #0.5 // CHECK-INST: fsub z0.s, p0/m, z0.s, #0.5 // CHECK-ENCODING: [0x00,0x80,0x99,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 99 65 fsub z0.d, p0/m, z0.d, #0.5 // CHECK-INST: fsub z0.d, p0/m, z0.d, #0.5 // CHECK-ENCODING: [0x00,0x80,0xd9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d9 65 fsub z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fsub z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 59 65 fsub z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fsub z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 59 65 fsub z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fsub z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x99,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 99 65 fsub z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d9 65 fsub z0.h, p7/m, z0.h, z31.h // CHECK-INST: fsub z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x41,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 41 65 fsub z0.s, p7/m, z0.s, z31.s // CHECK-INST: fsub z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x81,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 81 65 fsub z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c1 65 fsub z0.h, z1.h, z31.h // CHECK-INST: fsub z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x04,0x5f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 5f 65 fsub z0.s, z1.s, z31.s // CHECK-INST: fsub z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x04,0x9f,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 9f 65 fsub z0.d, z1.d, z31.d // CHECK-INST: fsub z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x04,0xdf,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 df 65 @@ -100,47 +100,47 @@ fsub z0.d, z1.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fsub z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d9 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fsub z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c d9 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fsub z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c1 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fsub z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c1 65 diff --git a/llvm/test/MC/AArch64/SVE/fsubr.s b/llvm/test/MC/AArch64/SVE/fsubr.s index e7a24dce78def..975a9285c92e0 100644 --- a/llvm/test/MC/AArch64/SVE/fsubr.s +++ b/llvm/test/MC/AArch64/SVE/fsubr.s @@ -12,67 +12,67 @@ fsubr z0.h, p0/m, z0.h, #0.500000000000000 // CHECK-INST: fsubr z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x5b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5b 65 fsubr z0.h, p0/m, z0.h, #0.5 // CHECK-INST: fsubr z0.h, p0/m, z0.h, #0.5 // CHECK-ENCODING: [0x00,0x80,0x5b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 5b 65 fsubr z0.s, p0/m, z0.s, #0.5 // CHECK-INST: fsubr z0.s, p0/m, z0.s, #0.5 // CHECK-ENCODING: [0x00,0x80,0x9b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 9b 65 fsubr z0.d, p0/m, z0.d, #0.5 // CHECK-INST: fsubr z0.d, p0/m, z0.d, #0.5 // CHECK-ENCODING: [0x00,0x80,0xdb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 db 65 fsubr z31.h, p7/m, z31.h, #1.000000000000000 // CHECK-INST: fsubr z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5b 65 fsubr z31.h, p7/m, z31.h, #1.0 // CHECK-INST: fsubr z31.h, p7/m, z31.h, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 5b 65 fsubr z31.s, p7/m, z31.s, #1.0 // CHECK-INST: fsubr z31.s, p7/m, z31.s, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0x9b,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c 9b 65 fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c db 65 fsubr z0.h, p7/m, z0.h, z31.h // CHECK-INST: fsubr z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x43,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 43 65 fsubr z0.s, p7/m, z0.s, z31.s // CHECK-INST: fsubr z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x9f,0x83,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 83 65 fsubr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c3 65 @@ -82,47 +82,47 @@ fsubr z0.d, p7/m, z0.d, z31.d movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c db 65 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 3f 9c db 65 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 fsubr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c3 65 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 fsubr z0.d, p7/m, z0.d, z31.d // CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f c3 65 diff --git a/llvm/test/MC/AArch64/SVE/ftmad.s b/llvm/test/MC/AArch64/SVE/ftmad.s index fc6f5c1f22c8a..c97b4058d54f4 100644 --- a/llvm/test/MC/AArch64/SVE/ftmad.s +++ b/llvm/test/MC/AArch64/SVE/ftmad.s @@ -32,7 +32,7 @@ ftmad z0.d, z0.d, z31.d, #7 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 ftmad z0.d, z0.d, z31.d, #7 diff --git a/llvm/test/MC/AArch64/SVE/incb.s b/llvm/test/MC/AArch64/SVE/incb.s index 27b347a31f25c..6dbdb8b2ac91c 100644 --- a/llvm/test/MC/AArch64/SVE/incb.s +++ b/llvm/test/MC/AArch64/SVE/incb.s @@ -12,197 +12,197 @@ incb x0 // CHECK-INST: incb x0 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 30 04 incb x0, all // CHECK-INST: incb x0 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 30 04 incb x0, all, mul #1 // CHECK-INST: incb x0 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 30 04 incb x0, all, mul #16 // CHECK-INST: incb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 3f 04 incb x0, pow2 // CHECK-INST: incb x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 30 04 incb x0, vl1 // CHECK-INST: incb x0, vl1 // CHECK-ENCODING: [0x20,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e0 30 04 incb x0, vl2 // CHECK-INST: incb x0, vl2 // CHECK-ENCODING: [0x40,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e0 30 04 incb x0, vl3 // CHECK-INST: incb x0, vl3 // CHECK-ENCODING: [0x60,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e0 30 04 incb x0, vl4 // CHECK-INST: incb x0, vl4 // CHECK-ENCODING: [0x80,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e0 30 04 incb x0, vl5 // CHECK-INST: incb x0, vl5 // CHECK-ENCODING: [0xa0,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e0 30 04 incb x0, vl6 // CHECK-INST: incb x0, vl6 // CHECK-ENCODING: [0xc0,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e0 30 04 incb x0, vl7 // CHECK-INST: incb x0, vl7 // CHECK-ENCODING: [0xe0,0xe0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e0 30 04 incb x0, vl8 // CHECK-INST: incb x0, vl8 // CHECK-ENCODING: [0x00,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e1 30 04 incb x0, vl16 // CHECK-INST: incb x0, vl16 // CHECK-ENCODING: [0x20,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e1 30 04 incb x0, vl32 // CHECK-INST: incb x0, vl32 // CHECK-ENCODING: [0x40,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e1 30 04 incb x0, vl64 // CHECK-INST: incb x0, vl64 // CHECK-ENCODING: [0x60,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e1 30 04 incb x0, vl128 // CHECK-INST: incb x0, vl128 // CHECK-ENCODING: [0x80,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e1 30 04 incb x0, vl256 // CHECK-INST: incb x0, vl256 // CHECK-ENCODING: [0xa0,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e1 30 04 incb x0, #14 // CHECK-INST: incb x0, #14 // CHECK-ENCODING: [0xc0,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e1 30 04 incb x0, #15 // CHECK-INST: incb x0, #15 // CHECK-ENCODING: [0xe0,0xe1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e1 30 04 incb x0, #16 // CHECK-INST: incb x0, #16 // CHECK-ENCODING: [0x00,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e2 30 04 incb x0, #17 // CHECK-INST: incb x0, #17 // CHECK-ENCODING: [0x20,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e2 30 04 incb x0, #18 // CHECK-INST: incb x0, #18 // CHECK-ENCODING: [0x40,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e2 30 04 incb x0, #19 // CHECK-INST: incb x0, #19 // CHECK-ENCODING: [0x60,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e2 30 04 incb x0, #20 // CHECK-INST: incb x0, #20 // CHECK-ENCODING: [0x80,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e2 30 04 incb x0, #21 // CHECK-INST: incb x0, #21 // CHECK-ENCODING: [0xa0,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e2 30 04 incb x0, #22 // CHECK-INST: incb x0, #22 // CHECK-ENCODING: [0xc0,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e2 30 04 incb x0, #23 // CHECK-INST: incb x0, #23 // CHECK-ENCODING: [0xe0,0xe2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e2 30 04 incb x0, #24 // CHECK-INST: incb x0, #24 // CHECK-ENCODING: [0x00,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e3 30 04 incb x0, #25 // CHECK-INST: incb x0, #25 // CHECK-ENCODING: [0x20,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e3 30 04 incb x0, #26 // CHECK-INST: incb x0, #26 // CHECK-ENCODING: [0x40,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e3 30 04 incb x0, #27 // CHECK-INST: incb x0, #27 // CHECK-ENCODING: [0x60,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e3 30 04 incb x0, #28 // CHECK-INST: incb x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 30 04 diff --git a/llvm/test/MC/AArch64/SVE/incd.s b/llvm/test/MC/AArch64/SVE/incd.s index c2e3961453513..5275ed749947a 100644 --- a/llvm/test/MC/AArch64/SVE/incd.s +++ b/llvm/test/MC/AArch64/SVE/incd.s @@ -16,25 +16,25 @@ incd z0.d // CHECK-INST: incd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f0 04 incd z0.d, all // CHECK-INST: incd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f0 04 incd z0.d, all, mul #1 // CHECK-INST: incd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f0 04 incd z0.d, all, mul #16 // CHECK-INST: incd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 ff 04 @@ -45,25 +45,25 @@ incd z0.d, all, mul #16 incd x0 // CHECK-INST: incd x0 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 f0 04 incd x0, all // CHECK-INST: incd x0 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 f0 04 incd x0, all, mul #1 // CHECK-INST: incd x0 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 f0 04 incd x0, all, mul #16 // CHECK-INST: incd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 ff 04 @@ -74,97 +74,97 @@ incd x0, all, mul #16 incd x0, pow2 // CHECK-INST: incd x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 f0 04 incd x0, vl1 // CHECK-INST: incd x0, vl1 // CHECK-ENCODING: [0x20,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e0 f0 04 incd x0, vl2 // CHECK-INST: incd x0, vl2 // CHECK-ENCODING: [0x40,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e0 f0 04 incd x0, vl3 // CHECK-INST: incd x0, vl3 // CHECK-ENCODING: [0x60,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e0 f0 04 incd x0, vl4 // CHECK-INST: incd x0, vl4 // CHECK-ENCODING: [0x80,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e0 f0 04 incd x0, vl5 // CHECK-INST: incd x0, vl5 // CHECK-ENCODING: [0xa0,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e0 f0 04 incd x0, vl6 // CHECK-INST: incd x0, vl6 // CHECK-ENCODING: [0xc0,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e0 f0 04 incd x0, vl7 // CHECK-INST: incd x0, vl7 // CHECK-ENCODING: [0xe0,0xe0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e0 f0 04 incd x0, vl8 // CHECK-INST: incd x0, vl8 // CHECK-ENCODING: [0x00,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e1 f0 04 incd x0, vl16 // CHECK-INST: incd x0, vl16 // CHECK-ENCODING: [0x20,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e1 f0 04 incd x0, vl32 // CHECK-INST: incd x0, vl32 // CHECK-ENCODING: [0x40,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e1 f0 04 incd x0, vl64 // CHECK-INST: incd x0, vl64 // CHECK-ENCODING: [0x60,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e1 f0 04 incd x0, vl128 // CHECK-INST: incd x0, vl128 // CHECK-ENCODING: [0x80,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e1 f0 04 incd x0, vl256 // CHECK-INST: incd x0, vl256 // CHECK-ENCODING: [0xa0,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e1 f0 04 incd x0, #14 // CHECK-INST: incd x0, #14 // CHECK-ENCODING: [0xc0,0xe1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e1 f0 04 incd x0, #28 // CHECK-INST: incd x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 f0 04 @@ -174,35 +174,35 @@ incd x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incd z0.d // CHECK-INST: incd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incd z0.d, all, mul #16 // CHECK-INST: incd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 ff 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incd z0.d, all // CHECK-INST: incd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 f0 04 diff --git a/llvm/test/MC/AArch64/SVE/inch.s b/llvm/test/MC/AArch64/SVE/inch.s index e273f1455d668..6032830045a3d 100644 --- a/llvm/test/MC/AArch64/SVE/inch.s +++ b/llvm/test/MC/AArch64/SVE/inch.s @@ -16,25 +16,25 @@ inch z0.h // CHECK-INST: inch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 70 04 inch z0.h, all // CHECK-INST: inch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 70 04 inch z0.h, all, mul #1 // CHECK-INST: inch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 70 04 inch z0.h, all, mul #16 // CHECK-INST: inch z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 7f 04 @@ -45,25 +45,25 @@ inch z0.h, all, mul #16 inch x0 // CHECK-INST: inch x0 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 70 04 inch x0, all // CHECK-INST: inch x0 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 70 04 inch x0, all, mul #1 // CHECK-INST: inch x0 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 70 04 inch x0, all, mul #16 // CHECK-INST: inch x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 7f 04 @@ -74,97 +74,97 @@ inch x0, all, mul #16 inch x0, pow2 // CHECK-INST: inch x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 70 04 inch x0, vl1 // CHECK-INST: inch x0, vl1 // CHECK-ENCODING: [0x20,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e0 70 04 inch x0, vl2 // CHECK-INST: inch x0, vl2 // CHECK-ENCODING: [0x40,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e0 70 04 inch x0, vl3 // CHECK-INST: inch x0, vl3 // CHECK-ENCODING: [0x60,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e0 70 04 inch x0, vl4 // CHECK-INST: inch x0, vl4 // CHECK-ENCODING: [0x80,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e0 70 04 inch x0, vl5 // CHECK-INST: inch x0, vl5 // CHECK-ENCODING: [0xa0,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e0 70 04 inch x0, vl6 // CHECK-INST: inch x0, vl6 // CHECK-ENCODING: [0xc0,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e0 70 04 inch x0, vl7 // CHECK-INST: inch x0, vl7 // CHECK-ENCODING: [0xe0,0xe0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e0 70 04 inch x0, vl8 // CHECK-INST: inch x0, vl8 // CHECK-ENCODING: [0x00,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e1 70 04 inch x0, vl16 // CHECK-INST: inch x0, vl16 // CHECK-ENCODING: [0x20,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e1 70 04 inch x0, vl32 // CHECK-INST: inch x0, vl32 // CHECK-ENCODING: [0x40,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e1 70 04 inch x0, vl64 // CHECK-INST: inch x0, vl64 // CHECK-ENCODING: [0x60,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e1 70 04 inch x0, vl128 // CHECK-INST: inch x0, vl128 // CHECK-ENCODING: [0x80,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e1 70 04 inch x0, vl256 // CHECK-INST: inch x0, vl256 // CHECK-ENCODING: [0xa0,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e1 70 04 inch x0, #14 // CHECK-INST: inch x0, #14 // CHECK-ENCODING: [0xc0,0xe1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e1 70 04 inch x0, #28 // CHECK-INST: inch x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 70 04 @@ -174,35 +174,35 @@ inch x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 inch z0.h // CHECK-INST: inch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 70 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 inch z0.h, all, mul #16 // CHECK-INST: inch z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 7f 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 inch z0.h, all // CHECK-INST: inch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 70 04 diff --git a/llvm/test/MC/AArch64/SVE/incp.s b/llvm/test/MC/AArch64/SVE/incp.s index 21707711e157b..902befe4f03d8 100644 --- a/llvm/test/MC/AArch64/SVE/incp.s +++ b/llvm/test/MC/AArch64/SVE/incp.s @@ -12,85 +12,85 @@ incp x0, p0.b // CHECK-INST: incp x0, p0.b // CHECK-ENCODING: [0x00,0x88,0x2c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 2c 25 incp x0, p0.h // CHECK-INST: incp x0, p0.h // CHECK-ENCODING: [0x00,0x88,0x6c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 6c 25 incp x0, p0.s // CHECK-INST: incp x0, p0.s // CHECK-ENCODING: [0x00,0x88,0xac,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 ac 25 incp x0, p0.d // CHECK-INST: incp x0, p0.d // CHECK-ENCODING: [0x00,0x88,0xec,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 ec 25 incp xzr, p15.b // CHECK-INST: incp xzr, p15.b // CHECK-ENCODING: [0xff,0x89,0x2c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 2c 25 incp xzr, p15.h // CHECK-INST: incp xzr, p15.h // CHECK-ENCODING: [0xff,0x89,0x6c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 6c 25 incp xzr, p15.s // CHECK-INST: incp xzr, p15.s // CHECK-ENCODING: [0xff,0x89,0xac,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ac 25 incp xzr, p15.d // CHECK-INST: incp xzr, p15.d // CHECK-ENCODING: [0xff,0x89,0xec,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ec 25 incp z31.h, p15 // CHECK-INST: incp z31.h, p15.h // CHECK-ENCODING: [0xff,0x81,0x6c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 6c 25 incp z31.h, p15.h // CHECK-INST: incp z31.h, p15.h // CHECK-ENCODING: [0xff,0x81,0x6c,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 6c 25 incp z31.s, p15 // CHECK-INST: incp z31.s, p15.s // CHECK-ENCODING: [0xff,0x81,0xac,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ac 25 incp z31.s, p15.s // CHECK-INST: incp z31.s, p15.s // CHECK-ENCODING: [0xff,0x81,0xac,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ac 25 incp z31.d, p15 // CHECK-INST: incp z31.d, p15.d // CHECK-ENCODING: [0xff,0x81,0xec,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ec 25 incp z31.d, p15.d // CHECK-INST: incp z31.d, p15.d // CHECK-ENCODING: [0xff,0x81,0xec,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ec 25 @@ -100,11 +100,11 @@ incp z31.d, p15.d movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 incp z31.d, p15.d // CHECK-INST: incp z31.d, p15.d // CHECK-ENCODING: [0xff,0x81,0xec,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 ec 25 diff --git a/llvm/test/MC/AArch64/SVE/incw.s b/llvm/test/MC/AArch64/SVE/incw.s index 34285f172e485..c4514f369fcc8 100644 --- a/llvm/test/MC/AArch64/SVE/incw.s +++ b/llvm/test/MC/AArch64/SVE/incw.s @@ -16,25 +16,25 @@ incw z0.s // CHECK-INST: incw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 b0 04 incw z0.s, all // CHECK-INST: incw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 b0 04 incw z0.s, all, mul #1 // CHECK-INST: incw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 b0 04 incw z0.s, all, mul #16 // CHECK-INST: incw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 bf 04 @@ -45,25 +45,25 @@ incw z0.s, all, mul #16 incw x0 // CHECK-INST: incw x0 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 b0 04 incw x0, all // CHECK-INST: incw x0 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 b0 04 incw x0, all, mul #1 // CHECK-INST: incw x0 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 b0 04 incw x0, all, mul #16 // CHECK-INST: incw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xe3,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e3 bf 04 @@ -75,97 +75,97 @@ incw x0, all, mul #16 incw x0, pow2 // CHECK-INST: incw x0, pow2 // CHECK-ENCODING: [0x00,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 b0 04 incw x0, vl1 // CHECK-INST: incw x0, vl1 // CHECK-ENCODING: [0x20,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e0 b0 04 incw x0, vl2 // CHECK-INST: incw x0, vl2 // CHECK-ENCODING: [0x40,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e0 b0 04 incw x0, vl3 // CHECK-INST: incw x0, vl3 // CHECK-ENCODING: [0x60,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e0 b0 04 incw x0, vl4 // CHECK-INST: incw x0, vl4 // CHECK-ENCODING: [0x80,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e0 b0 04 incw x0, vl5 // CHECK-INST: incw x0, vl5 // CHECK-ENCODING: [0xa0,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e0 b0 04 incw x0, vl6 // CHECK-INST: incw x0, vl6 // CHECK-ENCODING: [0xc0,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e0 b0 04 incw x0, vl7 // CHECK-INST: incw x0, vl7 // CHECK-ENCODING: [0xe0,0xe0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 e0 b0 04 incw x0, vl8 // CHECK-INST: incw x0, vl8 // CHECK-ENCODING: [0x00,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e1 b0 04 incw x0, vl16 // CHECK-INST: incw x0, vl16 // CHECK-ENCODING: [0x20,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 e1 b0 04 incw x0, vl32 // CHECK-INST: incw x0, vl32 // CHECK-ENCODING: [0x40,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 e1 b0 04 incw x0, vl64 // CHECK-INST: incw x0, vl64 // CHECK-ENCODING: [0x60,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 e1 b0 04 incw x0, vl128 // CHECK-INST: incw x0, vl128 // CHECK-ENCODING: [0x80,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e1 b0 04 incw x0, vl256 // CHECK-INST: incw x0, vl256 // CHECK-ENCODING: [0xa0,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 e1 b0 04 incw x0, #14 // CHECK-INST: incw x0, #14 // CHECK-ENCODING: [0xc0,0xe1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 e1 b0 04 incw x0, #28 // CHECK-INST: incw x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 e3 b0 04 @@ -175,35 +175,35 @@ incw x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incw z0.s // CHECK-INST: incw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 b0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incw z0.s, all, mul #16 // CHECK-INST: incw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 bf 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 incw z0.s, all // CHECK-INST: incw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 b0 04 diff --git a/llvm/test/MC/AArch64/SVE/index.s b/llvm/test/MC/AArch64/SVE/index.s index 10723e786d792..f4aed61b32863 100644 --- a/llvm/test/MC/AArch64/SVE/index.s +++ b/llvm/test/MC/AArch64/SVE/index.s @@ -15,49 +15,49 @@ index z0.b, #0, #0 // CHECK-INST: index z0.b, #0, #0 // CHECK-ENCODING: [0x00,0x40,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 20 04 index z31.b, #-1, #-1 // CHECK-INST: index z31.b, #-1, #-1 // CHECK-ENCODING: [0xff,0x43,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 43 3f 04 index z0.h, #0, #0 // CHECK-INST: index z0.h, #0, #0 // CHECK-ENCODING: [0x00,0x40,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 04 index z31.h, #-1, #-1 // CHECK-INST: index z31.h, #-1, #-1 // CHECK-ENCODING: [0xff,0x43,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 43 7f 04 index z0.s, #0, #0 // CHECK-INST: index z0.s, #0, #0 // CHECK-ENCODING: [0x00,0x40,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 a0 04 index z31.s, #-1, #-1 // CHECK-INST: index z31.s, #-1, #-1 // CHECK-ENCODING: [0xff,0x43,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 43 bf 04 index z0.d, #0, #0 // CHECK-INST: index z0.d, #0, #0 // CHECK-ENCODING: [0x00,0x40,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 04 index z31.d, #-1, #-1 // CHECK-INST: index z31.d, #-1, #-1 // CHECK-ENCODING: [0xff,0x43,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 43 ff 04 // --------------------------------------------------------------------------// @@ -66,49 +66,49 @@ index z31.d, #-1, #-1 index z31.b, #-1, wzr // CHECK-INST: index z31.b, #-1, wzr // CHECK-ENCODING: [0xff,0x4b,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4b 3f 04 index z23.b, #13, w8 // CHECK-INST: index z23.b, #13, w8 // CHECK-ENCODING: [0xb7,0x49,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 49 28 04 index z31.h, #-1, wzr // CHECK-INST: index z31.h, #-1, wzr // CHECK-ENCODING: [0xff,0x4b,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4b 7f 04 index z23.h, #13, w8 // CHECK-INST: index z23.h, #13, w8 // CHECK-ENCODING: [0xb7,0x49,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 49 68 04 index z31.s, #-1, wzr // CHECK-INST: index z31.s, #-1, wzr // CHECK-ENCODING: [0xff,0x4b,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4b bf 04 index z23.s, #13, w8 // CHECK-INST: index z23.s, #13, w8 // CHECK-ENCODING: [0xb7,0x49,0xa8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 49 a8 04 index z31.d, #-1, xzr // CHECK-INST: index z31.d, #-1, xzr // CHECK-ENCODING: [0xff,0x4b,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4b ff 04 index z23.d, #13, x8 // CHECK-INST: index z23.d, #13, x8 // CHECK-ENCODING: [0xb7,0x49,0xe8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 49 e8 04 @@ -118,49 +118,49 @@ index z23.d, #13, x8 index z31.b, wzr, #-1 // CHECK-INST: index z31.b, wzr, #-1 // CHECK-ENCODING: [0xff,0x47,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 47 3f 04 index z23.b, w13, #8 // CHECK-INST: index z23.b, w13, #8 // CHECK-ENCODING: [0xb7,0x45,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 45 28 04 index z31.h, wzr, #-1 // CHECK-INST: index z31.h, wzr, #-1 // CHECK-ENCODING: [0xff,0x47,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 47 7f 04 index z23.h, w13, #8 // CHECK-INST: index z23.h, w13, #8 // CHECK-ENCODING: [0xb7,0x45,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 45 68 04 index z31.s, wzr, #-1 // CHECK-INST: index z31.s, wzr, #-1 // CHECK-ENCODING: [0xff,0x47,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 47 bf 04 index z23.s, w13, #8 // CHECK-INST: index z23.s, w13, #8 // CHECK-ENCODING: [0xb7,0x45,0xa8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 45 a8 04 index z31.d, xzr, #-1 // CHECK-INST: index z31.d, xzr, #-1 // CHECK-ENCODING: [0xff,0x47,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 47 ff 04 index z23.d, x13, #8 // CHECK-INST: index z23.d, x13, #8 // CHECK-ENCODING: [0xb7,0x45,0xe8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 45 e8 04 @@ -170,47 +170,47 @@ index z23.d, x13, #8 index z31.b, wzr, wzr // CHECK-INST: index z31.b, wzr, wzr // CHECK-ENCODING: [0xff,0x4f,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4f 3f 04 index z21.b, w10, w21 // CHECK-INST: index z21.b, w10, w21 // CHECK-ENCODING: [0x55,0x4d,0x35,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 4d 35 04 index z31.h, wzr, wzr // check-inst: index z31.h, wzr, wzr // check-encoding: [0xff,0x4f,0x7f,0x04] -// check-error: instruction requires: streaming-sve or sve +// check-error: instruction requires: sve or sme // check-unknown: ff 4f 7f 04 index z0.h, w0, w0 // check-inst: index z0.h, w0, w0 // check-encoding: [0x00,0x4c,0x60,0x04] -// check-error: instruction requires: streaming-sve or sve +// check-error: instruction requires: sve or sme // check-unknown: 00 4c 60 04 index z31.s, wzr, wzr // CHECK-INST: index z31.s, wzr, wzr // CHECK-ENCODING: [0xff,0x4f,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4f bf 04 index z21.s, w10, w21 // CHECK-INST: index z21.s, w10, w21 // CHECK-ENCODING: [0x55,0x4d,0xb5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 4d b5 04 index z31.d, xzr, xzr // CHECK-INST: index z31.d, xzr, xzr // CHECK-ENCODING: [0xff,0x4f,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 4f ff 04 index z21.d, x10, x21 // CHECK-INST: index z21.d, x10, x21 // CHECK-ENCODING: [0x55,0x4d,0xf5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 4d f5 04 diff --git a/llvm/test/MC/AArch64/SVE/insr.s b/llvm/test/MC/AArch64/SVE/insr.s index 3687a601985aa..37b00db8cdd9f 100644 --- a/llvm/test/MC/AArch64/SVE/insr.s +++ b/llvm/test/MC/AArch64/SVE/insr.s @@ -12,73 +12,73 @@ insr z0.b, w0 // CHECK-INST: insr z0.b, w0 // CHECK-ENCODING: [0x00,0x38,0x24,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 24 05 insr z0.h, w0 // CHECK-INST: insr z0.h, w0 // CHECK-ENCODING: [0x00,0x38,0x64,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 64 05 insr z0.s, w0 // CHECK-INST: insr z0.s, w0 // CHECK-ENCODING: [0x00,0x38,0xa4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 a4 05 insr z0.d, x0 // CHECK-INST: insr z0.d, x0 // CHECK-ENCODING: [0x00,0x38,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 e4 05 insr z31.b, wzr // CHECK-INST: insr z31.b, wzr // CHECK-ENCODING: [0xff,0x3b,0x24,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 24 05 insr z31.h, wzr // CHECK-INST: insr z31.h, wzr // CHECK-ENCODING: [0xff,0x3b,0x64,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 64 05 insr z31.s, wzr // CHECK-INST: insr z31.s, wzr // CHECK-ENCODING: [0xff,0x3b,0xa4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b a4 05 insr z31.d, xzr // CHECK-INST: insr z31.d, xzr // CHECK-ENCODING: [0xff,0x3b,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b e4 05 insr z31.b, b31 // CHECK-INST: insr z31.b, b31 // CHECK-ENCODING: [0xff,0x3b,0x34,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 34 05 insr z31.h, h31 // CHECK-INST: insr z31.h, h31 // CHECK-ENCODING: [0xff,0x3b,0x74,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 74 05 insr z31.s, s31 // CHECK-INST: insr z31.s, s31 // CHECK-ENCODING: [0xff,0x3b,0xb4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b b4 05 insr z31.d, d31 // CHECK-INST: insr z31.d, d31 // CHECK-ENCODING: [0xff,0x3b,0xf4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b f4 05 @@ -88,23 +88,23 @@ insr z31.d, d31 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 insr z31.d, xzr // CHECK-INST: insr z31.d, xzr // CHECK-ENCODING: [0xff,0x3b,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b e4 05 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 insr z4.d, d31 // CHECK-INST: insr z4.d, d31 // CHECK-ENCODING: [0xe4,0x3b,0xf4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 3b f4 05 diff --git a/llvm/test/MC/AArch64/SVE/lasta.s b/llvm/test/MC/AArch64/SVE/lasta.s index 73b436fc7da9e..d6beda10b8b10 100644 --- a/llvm/test/MC/AArch64/SVE/lasta.s +++ b/llvm/test/MC/AArch64/SVE/lasta.s @@ -12,47 +12,47 @@ lasta w0, p7, z31.b // CHECK-INST: lasta w0, p7, z31.b // CHECK-ENCODING: [0xe0,0xbf,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 20 05 lasta w0, p7, z31.h // CHECK-INST: lasta w0, p7, z31.h // CHECK-ENCODING: [0xe0,0xbf,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 60 05 lasta w0, p7, z31.s // CHECK-INST: lasta w0, p7, z31.s // CHECK-ENCODING: [0xe0,0xbf,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf a0 05 lasta x0, p7, z31.d // CHECK-INST: lasta x0, p7, z31.d // CHECK-ENCODING: [0xe0,0xbf,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf e0 05 lasta b0, p7, z31.b // CHECK-INST: lasta b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x22,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 22 05 lasta h0, p7, z31.h // CHECK-INST: lasta h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x62,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 62 05 lasta s0, p7, z31.s // CHECK-INST: lasta s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa2,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a2 05 lasta d0, p7, z31.d // CHECK-INST: lasta d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe2,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e2 05 diff --git a/llvm/test/MC/AArch64/SVE/lastb.s b/llvm/test/MC/AArch64/SVE/lastb.s index ae4e077d52750..7f581fcb42c4c 100644 --- a/llvm/test/MC/AArch64/SVE/lastb.s +++ b/llvm/test/MC/AArch64/SVE/lastb.s @@ -12,47 +12,47 @@ lastb w0, p7, z31.b // CHECK-INST: lastb w0, p7, z31.b // CHECK-ENCODING: [0xe0,0xbf,0x21,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 21 05 lastb w0, p7, z31.h // CHECK-INST: lastb w0, p7, z31.h // CHECK-ENCODING: [0xe0,0xbf,0x61,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf 61 05 lastb w0, p7, z31.s // CHECK-INST: lastb w0, p7, z31.s // CHECK-ENCODING: [0xe0,0xbf,0xa1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf a1 05 lastb x0, p7, z31.d // CHECK-INST: lastb x0, p7, z31.d // CHECK-ENCODING: [0xe0,0xbf,0xe1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bf e1 05 lastb b0, p7, z31.b // CHECK-INST: lastb b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x23,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 23 05 lastb h0, p7, z31.h // CHECK-INST: lastb h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x63,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 63 05 lastb s0, p7, z31.s // CHECK-INST: lastb s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a3 05 lastb d0, p7, z31.d // CHECK-INST: lastb d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e3 05 diff --git a/llvm/test/MC/AArch64/SVE/ld1b.s b/llvm/test/MC/AArch64/SVE/ld1b.s index 0dc1deaa249ac..cd07e49c2fa1b 100644 --- a/llvm/test/MC/AArch64/SVE/ld1b.s +++ b/llvm/test/MC/AArch64/SVE/ld1b.s @@ -12,131 +12,131 @@ ld1b z0.b, p0/z, [x0] // CHECK-INST: ld1b { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 00 a4 ld1b z0.h, p0/z, [x0] // CHECK-INST: ld1b { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x20,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 20 a4 ld1b z0.s, p0/z, [x0] // CHECK-INST: ld1b { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 a4 ld1b z0.d, p0/z, [x0] // CHECK-INST: ld1b { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x60,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 60 a4 ld1b { z0.b }, p0/z, [x0] // CHECK-INST: ld1b { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 00 a4 ld1b { z0.h }, p0/z, [x0] // CHECK-INST: ld1b { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x20,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 20 a4 ld1b { z0.s }, p0/z, [x0] // CHECK-INST: ld1b { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 a4 ld1b { z0.d }, p0/z, [x0] // CHECK-INST: ld1b { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x60,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 60 a4 ld1b { z31.b }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1b { z31.b }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x0f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 0f a4 ld1b { z21.b }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1b { z21.b }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x05,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 05 a4 ld1b { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1b { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x2f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 2f a4 ld1b { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1b { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x25,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 25 a4 ld1b { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1b { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x4f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 4f a4 ld1b { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1b { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x45,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 45 a4 ld1b { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1b { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x6f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 6f a4 ld1b { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1b { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x65,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 65 a4 ld1b { z0.b }, p0/z, [sp, x0] // CHECK-INST: ld1b { z0.b }, p0/z, [sp, x0] // CHECK-ENCODING: [0xe0,0x43,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 43 00 a4 ld1b { z0.b }, p0/z, [x0, x0] // CHECK-INST: ld1b { z0.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 a4 ld1b { z0.b }, p0/z, [x0, x0, lsl #0] // CHECK-INST: ld1b { z0.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 a4 ld1b { z5.h }, p3/z, [x17, x16] // CHECK-INST: ld1b { z5.h }, p3/z, [x17, x16] // CHECK-ENCODING: [0x25,0x4e,0x30,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 4e 30 a4 ld1b { z21.s }, p5/z, [x10, x21] // CHECK-INST: ld1b { z21.s }, p5/z, [x10, x21] // CHECK-ENCODING: [0x55,0x55,0x55,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 55 55 a4 ld1b { z23.d }, p3/z, [x13, x8] // CHECK-INST: ld1b { z23.d }, p3/z, [x13, x8] // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 68 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld1d.s b/llvm/test/MC/AArch64/SVE/ld1d.s index 9289d9e9b17a2..e3ce674fc0bb1 100644 --- a/llvm/test/MC/AArch64/SVE/ld1d.s +++ b/llvm/test/MC/AArch64/SVE/ld1d.s @@ -12,35 +12,35 @@ ld1d z0.d, p0/z, [x0] // CHECK-INST: ld1d { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e0 a5 ld1d { z0.d }, p0/z, [x0] // CHECK-INST: ld1d { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e0 a5 ld1d { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1d { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xef,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf ef a5 ld1d { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1d { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 e5 a5 ld1d { z23.d }, p3/z, [sp, x8, lsl #3] // CHECK-INST: ld1d { z23.d }, p3/z, [sp, x8, lsl #3] // CHECK-ENCODING: [0xf7,0x4f,0xe8,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f7 4f e8 a5 ld1d { z23.d }, p3/z, [x13, x8, lsl #3] // CHECK-INST: ld1d { z23.d }, p3/z, [x13, x8, lsl #3] // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d e8 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld1h.s b/llvm/test/MC/AArch64/SVE/ld1h.s index b7ec9a5ed9d01..45cfabfb84f91 100644 --- a/llvm/test/MC/AArch64/SVE/ld1h.s +++ b/llvm/test/MC/AArch64/SVE/ld1h.s @@ -12,95 +12,95 @@ ld1h z0.h, p0/z, [x0] // CHECK-INST: ld1h { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a0 a4 ld1h z0.s, p0/z, [x0] // CHECK-INST: ld1h { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 a4 ld1h z0.d, p0/z, [x0] // CHECK-INST: ld1h { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e0 a4 ld1h { z0.h }, p0/z, [x0] // CHECK-INST: ld1h { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a0 a4 ld1h { z0.s }, p0/z, [x0] // CHECK-INST: ld1h { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 a4 ld1h { z0.d }, p0/z, [x0] // CHECK-INST: ld1h { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e0 a4 ld1h { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1h { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xaf,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf af a4 ld1h { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1h { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xa5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 a5 a4 ld1h { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1h { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xcf,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf cf a4 ld1h { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1h { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xc5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 c5 a4 ld1h { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1h { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xef,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf ef a4 ld1h { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1h { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 e5 a4 ld1h { z5.h }, p3/z, [sp, x16, lsl #1] // CHECK-INST: ld1h { z5.h }, p3/z, [sp, x16, lsl #1] // CHECK-ENCODING: [0xe5,0x4f,0xb0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 4f b0 a4 ld1h { z5.h }, p3/z, [x17, x16, lsl #1] // CHECK-INST: ld1h { z5.h }, p3/z, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0x4e,0xb0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 4e b0 a4 ld1h { z21.s }, p5/z, [x10, x21, lsl #1] // CHECK-INST: ld1h { z21.s }, p5/z, [x10, x21, lsl #1] // CHECK-ENCODING: [0x55,0x55,0xd5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 55 d5 a4 ld1h { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-INST: ld1h { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d e8 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld1rb.s b/llvm/test/MC/AArch64/SVE/ld1rb.s index 59a8b25a5db87..536b9841bf3c0 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rb.s +++ b/llvm/test/MC/AArch64/SVE/ld1rb.s @@ -12,47 +12,47 @@ ld1rb { z0.b }, p0/z, [x0] // CHECK-INST: ld1rb { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x80,0x40,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 40 84 ld1rb { z0.h }, p0/z, [x0] // CHECK-INST: ld1rb { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 84 ld1rb { z0.s }, p0/z, [x0] // CHECK-INST: ld1rb { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xc0,0x40,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 40 84 ld1rb { z0.d }, p0/z, [x0] // CHECK-INST: ld1rb { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 84 ld1rb { z31.b }, p7/z, [sp, #63] // CHECK-INST: ld1rb { z31.b }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0x9f,0x7f,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 7f 84 ld1rb { z31.h }, p7/z, [sp, #63] // CHECK-INST: ld1rb { z31.h }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0xbf,0x7f,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 7f 84 ld1rb { z31.s }, p7/z, [sp, #63] // CHECK-INST: ld1rb { z31.s }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0xdf,0x7f,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 7f 84 ld1rb { z31.d }, p7/z, [sp, #63] // CHECK-INST: ld1rb { z31.d }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0xff,0x7f,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 7f 84 diff --git a/llvm/test/MC/AArch64/SVE/ld1rd.s b/llvm/test/MC/AArch64/SVE/ld1rd.s index 793f36cd6d4bf..9a32d2dc6e774 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rd.s +++ b/llvm/test/MC/AArch64/SVE/ld1rd.s @@ -12,11 +12,11 @@ ld1rd { z0.d }, p0/z, [x0] // CHECK-INST: ld1rd { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 85 ld1rd { z31.d }, p7/z, [sp, #504] // CHECK-INST: ld1rd { z31.d }, p7/z, [sp, #504] // CHECK-ENCODING: [0xff,0xff,0xff,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ff 85 diff --git a/llvm/test/MC/AArch64/SVE/ld1rh.s b/llvm/test/MC/AArch64/SVE/ld1rh.s index 063c4b53be7f5..9d5544e6c364f 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rh.s +++ b/llvm/test/MC/AArch64/SVE/ld1rh.s @@ -12,35 +12,35 @@ ld1rh { z0.h }, p0/z, [x0] // CHECK-INST: ld1rh { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 84 ld1rh { z0.s }, p0/z, [x0] // CHECK-INST: ld1rh { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xc0,0xc0,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 c0 84 ld1rh { z0.d }, p0/z, [x0] // CHECK-INST: ld1rh { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 84 ld1rh { z31.h }, p7/z, [sp, #126] // CHECK-INST: ld1rh { z31.h }, p7/z, [sp, #126] // CHECK-ENCODING: [0xff,0xbf,0xff,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf ff 84 ld1rh { z31.s }, p7/z, [sp, #126] // CHECK-INST: ld1rh { z31.s }, p7/z, [sp, #126] // CHECK-ENCODING: [0xff,0xdf,0xff,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df ff 84 ld1rh { z31.d }, p7/z, [sp, #126] // CHECK-INST: ld1rh { z31.d }, p7/z, [sp, #126] // CHECK-ENCODING: [0xff,0xff,0xff,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ff 84 diff --git a/llvm/test/MC/AArch64/SVE/ld1rqb.s b/llvm/test/MC/AArch64/SVE/ld1rqb.s index 6eaacabb1427a..9ed90e8bdaa2d 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqb.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqb.s @@ -12,29 +12,29 @@ ld1rqb { z0.b }, p0/z, [x0] // CHECK-INST: ld1rqb { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x20,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 00 a4 ld1rqb { z0.b }, p0/z, [x0, x0] // CHECK-INST: ld1rqb { z0.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0x00,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 00 a4 ld1rqb { z31.b }, p7/z, [sp, #-16] // CHECK-INST: ld1rqb { z31.b }, p7/z, [sp, #-16] // CHECK-ENCODING: [0xff,0x3f,0x0f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3f 0f a4 ld1rqb { z23.b }, p3/z, [x13, #-128] // CHECK-INST: ld1rqb { z23.b }, p3/z, [x13, #-128] // CHECK-ENCODING: [0xb7,0x2d,0x08,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 08 a4 ld1rqb { z21.b }, p5/z, [x10, #112] // CHECK-INST: ld1rqb { z21.b }, p5/z, [x10, #112] // CHECK-ENCODING: [0x55,0x35,0x07,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 35 07 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld1rqd.s b/llvm/test/MC/AArch64/SVE/ld1rqd.s index adf4bfb4bc664..f9a1abe0df8ef 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqd.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqd.s @@ -12,29 +12,29 @@ ld1rqd { z0.d }, p0/z, [x0] // CHECK-INST: ld1rqd { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x20,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 80 a5 ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3] // CHECK-INST: ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x00,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 a5 ld1rqd { z31.d }, p7/z, [sp, #-16] // CHECK-INST: ld1rqd { z31.d }, p7/z, [sp, #-16] // CHECK-ENCODING: [0xff,0x3f,0x8f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3f 8f a5 ld1rqd { z23.d }, p3/z, [x13, #-128] // CHECK-INST: ld1rqd { z23.d }, p3/z, [x13, #-128] // CHECK-ENCODING: [0xb7,0x2d,0x88,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 88 a5 ld1rqd { z23.d }, p3/z, [x13, #112] // CHECK-INST: ld1rqd { z23.d }, p3/z, [x13, #112] // CHECK-ENCODING: [0xb7,0x2d,0x87,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 87 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld1rqh.s b/llvm/test/MC/AArch64/SVE/ld1rqh.s index 4914a37d3eddb..87fb94a0154f2 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqh.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqh.s @@ -12,29 +12,29 @@ ld1rqh { z0.h }, p0/z, [x0] // CHECK-INST: ld1rqh { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x20,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 80 a4 ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1] // CHECK-INST: ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x00,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 a4 ld1rqh { z31.h }, p7/z, [sp, #-16] // CHECK-INST: ld1rqh { z31.h }, p7/z, [sp, #-16] // CHECK-ENCODING: [0xff,0x3f,0x8f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3f 8f a4 ld1rqh { z23.h }, p3/z, [x13, #-128] // CHECK-INST: ld1rqh { z23.h }, p3/z, [x13, #-128] // CHECK-ENCODING: [0xb7,0x2d,0x88,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 88 a4 ld1rqh { z23.h }, p3/z, [x13, #112] // CHECK-INST: ld1rqh { z23.h }, p3/z, [x13, #112] // CHECK-ENCODING: [0xb7,0x2d,0x87,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 87 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld1rqw.s b/llvm/test/MC/AArch64/SVE/ld1rqw.s index 4f4c3501bda21..ed2d25da5a8cd 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rqw.s +++ b/llvm/test/MC/AArch64/SVE/ld1rqw.s @@ -12,29 +12,29 @@ ld1rqw { z0.s }, p0/z, [x0] // CHECK-INST: ld1rqw { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x20,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 00 a5 ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2] // CHECK-INST: ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x00,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 00 a5 ld1rqw { z31.s }, p7/z, [sp, #-16] // CHECK-INST: ld1rqw { z31.s }, p7/z, [sp, #-16] // CHECK-ENCODING: [0xff,0x3f,0x0f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3f 0f a5 ld1rqw { z23.s }, p3/z, [x13, #-128] // CHECK-INST: ld1rqw { z23.s }, p3/z, [x13, #-128] // CHECK-ENCODING: [0xb7,0x2d,0x08,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 08 a5 ld1rqw { z23.s }, p3/z, [x13, #112] // CHECK-INST: ld1rqw { z23.s }, p3/z, [x13, #112] // CHECK-ENCODING: [0xb7,0x2d,0x07,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 2d 07 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld1rsb.s b/llvm/test/MC/AArch64/SVE/ld1rsb.s index a05ae173a288c..923869afacd08 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsb.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsb.s @@ -12,35 +12,35 @@ ld1rsb { z0.h }, p0/z, [x0] // CHECK-INST: ld1rsb { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xc0,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 c0 85 ld1rsb { z0.s }, p0/z, [x0] // CHECK-INST: ld1rsb { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 85 ld1rsb { z0.d }, p0/z, [x0] // CHECK-INST: ld1rsb { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x80,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 c0 85 ld1rsb { z31.h }, p7/z, [sp, #63] // CHECK-INST: ld1rsb { z31.h }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0xdf,0xff,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df ff 85 ld1rsb { z31.s }, p7/z, [sp, #63] // CHECK-INST: ld1rsb { z31.s }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0xbf,0xff,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf ff 85 ld1rsb { z31.d }, p7/z, [sp, #63] // CHECK-INST: ld1rsb { z31.d }, p7/z, [sp, #63] // CHECK-ENCODING: [0xff,0x9f,0xff,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f ff 85 diff --git a/llvm/test/MC/AArch64/SVE/ld1rsh.s b/llvm/test/MC/AArch64/SVE/ld1rsh.s index 26c96f1fe187d..5f5ca153691ba 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsh.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsh.s @@ -12,23 +12,23 @@ ld1rsh { z0.s }, p0/z, [x0] // CHECK-INST: ld1rsh { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 85 ld1rsh { z0.d }, p0/z, [x0] // CHECK-INST: ld1rsh { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x80,0x40,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 40 85 ld1rsh { z31.s }, p7/z, [sp, #126] // CHECK-INST: ld1rsh { z31.s }, p7/z, [sp, #126] // CHECK-ENCODING: [0xff,0xbf,0x7f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 7f 85 ld1rsh { z31.d }, p7/z, [sp, #126] // CHECK-INST: ld1rsh { z31.d }, p7/z, [sp, #126] // CHECK-ENCODING: [0xff,0x9f,0x7f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 7f 85 diff --git a/llvm/test/MC/AArch64/SVE/ld1rsw.s b/llvm/test/MC/AArch64/SVE/ld1rsw.s index 7e155f1061843..c7f9be9cfbafd 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rsw.s +++ b/llvm/test/MC/AArch64/SVE/ld1rsw.s @@ -12,11 +12,11 @@ ld1rsw { z0.d }, p0/z, [x0] // CHECK-INST: ld1rsw { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0x80,0xc0,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 c0 84 ld1rsw { z31.d }, p7/z, [sp, #252] // CHECK-INST: ld1rsw { z31.d }, p7/z, [sp, #252] // CHECK-ENCODING: [0xff,0x9f,0xff,0x84] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f ff 84 diff --git a/llvm/test/MC/AArch64/SVE/ld1rw.s b/llvm/test/MC/AArch64/SVE/ld1rw.s index 82c25d954cf99..f632f6cb5e094 100644 --- a/llvm/test/MC/AArch64/SVE/ld1rw.s +++ b/llvm/test/MC/AArch64/SVE/ld1rw.s @@ -12,23 +12,23 @@ ld1rw { z0.s }, p0/z, [x0] // CHECK-INST: ld1rw { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xc0,0x40,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 40 85 ld1rw { z0.d }, p0/z, [x0] // CHECK-INST: ld1rw { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 85 ld1rw { z31.s }, p7/z, [sp, #252] // CHECK-INST: ld1rw { z31.s }, p7/z, [sp, #252] // CHECK-ENCODING: [0xff,0xdf,0x7f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 7f 85 ld1rw { z31.d }, p7/z, [sp, #252] // CHECK-INST: ld1rw { z31.d }, p7/z, [sp, #252] // CHECK-ENCODING: [0xff,0xff,0x7f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 7f 85 diff --git a/llvm/test/MC/AArch64/SVE/ld1sb.s b/llvm/test/MC/AArch64/SVE/ld1sb.s index b945700b26c7d..9f1f47654c5ce 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sb.s +++ b/llvm/test/MC/AArch64/SVE/ld1sb.s @@ -12,101 +12,101 @@ ld1sb z0.h, p0/z, [x0] // CHECK-INST: ld1sb { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 a5 ld1sb z0.s, p0/z, [x0] // CHECK-INST: ld1sb { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a0 a5 ld1sb z0.d, p0/z, [x0] // CHECK-INST: ld1sb { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 80 a5 ld1sb { z0.h }, p0/z, [x0] // CHECK-INST: ld1sb { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 c0 a5 ld1sb { z0.s }, p0/z, [x0] // CHECK-INST: ld1sb { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a0 a5 ld1sb { z0.d }, p0/z, [x0] // CHECK-INST: ld1sb { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 80 a5 ld1sb { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sb { z31.h }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xcf,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf cf a5 ld1sb { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sb { z21.h }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xc5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 c5 a5 ld1sb { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sb { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0xaf,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf af a5 ld1sb { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sb { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0xa5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 a5 a5 ld1sb { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sb { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x8f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 8f a5 ld1sb { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sb { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x85,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 85 a5 ld1sb { z0.h }, p0/z, [sp, x0] // CHECK-INST: ld1sb { z0.h }, p0/z, [sp, x0] // CHECK-ENCODING: [0xe0,0x43,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 43 c0 a5 ld1sb { z0.h }, p0/z, [x0, x0] // CHECK-INST: ld1sb { z0.h }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 a5 ld1sb { z0.h }, p0/z, [x0, x0, lsl #0] // CHECK-INST: ld1sb { z0.h }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 a5 ld1sb { z21.s }, p5/z, [x10, x21] // CHECK-INST: ld1sb { z21.s }, p5/z, [x10, x21] // CHECK-ENCODING: [0x55,0x55,0xb5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 55 b5 a5 ld1sb { z23.d }, p3/z, [x13, x8] // CHECK-INST: ld1sb { z23.d }, p3/z, [x13, x8] // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 88 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld1sh.s b/llvm/test/MC/AArch64/SVE/ld1sh.s index 411cff2d0ae59..872e03fe10b1e 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sh.s +++ b/llvm/test/MC/AArch64/SVE/ld1sh.s @@ -12,65 +12,65 @@ ld1sh z0.s, p0/z, [x0] // CHECK-INST: ld1sh { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x20,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 20 a5 ld1sh z0.d, p0/z, [x0] // CHECK-INST: ld1sh { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 00 a5 ld1sh { z0.s }, p0/z, [x0] // CHECK-INST: ld1sh { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x20,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 20 a5 ld1sh { z0.d }, p0/z, [x0] // CHECK-INST: ld1sh { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 00 a5 ld1sh { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sh { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x2f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 2f a5 ld1sh { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sh { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x25,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 25 a5 ld1sh { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sh { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x0f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 0f a5 ld1sh { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sh { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x05,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 05 a5 ld1sh { z21.s }, p5/z, [sp, x21, lsl #1] // CHECK-INST: ld1sh { z21.s }, p5/z, [sp, x21, lsl #1] // CHECK-ENCODING: [0xf5,0x57,0x35,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 57 35 a5 ld1sh { z21.s }, p5/z, [x10, x21, lsl #1] // CHECK-INST: ld1sh { z21.s }, p5/z, [x10, x21, lsl #1] // CHECK-ENCODING: [0x55,0x55,0x35,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 55 35 a5 ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-INST: ld1sh { z23.d }, p3/z, [x13, x8, lsl #1] // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 08 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld1sw.s b/llvm/test/MC/AArch64/SVE/ld1sw.s index e5e4e856b507a..645f6b4fed8a0 100644 --- a/llvm/test/MC/AArch64/SVE/ld1sw.s +++ b/llvm/test/MC/AArch64/SVE/ld1sw.s @@ -12,35 +12,35 @@ ld1sw z0.d, p0/z, [x0] // CHECK-INST: ld1sw { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 80 a4 ld1sw { z0.d }, p0/z, [x0] // CHECK-INST: ld1sw { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 80 a4 ld1sw { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1sw { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x8f,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 8f a4 ld1sw { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1sw { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x85,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 85 a4 ld1sw { z23.d }, p3/z, [sp, x8, lsl #2] // CHECK-INST: ld1sw { z23.d }, p3/z, [sp, x8, lsl #2] // CHECK-ENCODING: [0xf7,0x4f,0x88,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f7 4f 88 a4 ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-INST: ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 88 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld1w.s b/llvm/test/MC/AArch64/SVE/ld1w.s index 1ca44289e3b81..8f82b3a433fcf 100644 --- a/llvm/test/MC/AArch64/SVE/ld1w.s +++ b/llvm/test/MC/AArch64/SVE/ld1w.s @@ -12,65 +12,65 @@ ld1w z0.s, p0/z, [x0] // CHECK-INST: ld1w { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 a5 ld1w z0.d, p0/z, [x0] // CHECK-INST: ld1w { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x60,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 60 a5 ld1w { z0.s }, p0/z, [x0] // CHECK-INST: ld1w { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x40,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 40 a5 ld1w { z0.d }, p0/z, [x0] // CHECK-INST: ld1w { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xa0,0x60,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 60 a5 ld1w { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1w { z31.s }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x4f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 4f a5 ld1w { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1w { z21.s }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x45,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 45 a5 ld1w { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-INST: ld1w { z31.d }, p7/z, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xbf,0x6f,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 6f a5 ld1w { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-INST: ld1w { z21.d }, p5/z, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xb5,0x65,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 b5 65 a5 ld1w { z21.s }, p5/z, [sp, x21, lsl #2] // CHECK-INST: ld1w { z21.s }, p5/z, [sp, x21, lsl #2] // CHECK-ENCODING: [0xf5,0x57,0x55,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 57 55 a5 ld1w { z21.s }, p5/z, [x10, x21, lsl #2] // CHECK-INST: ld1w { z21.s }, p5/z, [x10, x21, lsl #2] // CHECK-ENCODING: [0x55,0x55,0x55,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 55 55 a5 ld1w { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-INST: ld1w { z23.d }, p3/z, [x13, x8, lsl #2] // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 68 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld2b.s b/llvm/test/MC/AArch64/SVE/ld2b.s index 229935ae8fae2..a756b4afb5597 100644 --- a/llvm/test/MC/AArch64/SVE/ld2b.s +++ b/llvm/test/MC/AArch64/SVE/ld2b.s @@ -12,29 +12,29 @@ ld2b { z0.b, z1.b }, p0/z, [x0, x0] // CHECK-INST: ld2b { z0.b, z1.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0xc0,0x20,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 20 a4 ld2b { z5.b, z6.b }, p3/z, [x17, x16] // CHECK-INST: ld2b { z5.b, z6.b }, p3/z, [x17, x16] // CHECK-ENCODING: [0x25,0xce,0x30,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 30 a4 ld2b { z0.b, z1.b }, p0/z, [x0] // CHECK-INST: ld2b { z0.b, z1.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x20,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 20 a4 ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl] // CHECK-INST: ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x28,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 28 a4 ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] // CHECK-INST: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x25,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 25 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld2d.s b/llvm/test/MC/AArch64/SVE/ld2d.s index 3ac0f6561740d..6142a3a664b11 100644 --- a/llvm/test/MC/AArch64/SVE/ld2d.s +++ b/llvm/test/MC/AArch64/SVE/ld2d.s @@ -12,29 +12,29 @@ ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3] // CHECK-INST: ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0xc0,0xa0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a0 a5 ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3] // CHECK-INST: ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0xce,0xb0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce b0 a5 ld2d { z0.d, z1.d }, p0/z, [x0] // CHECK-INST: ld2d { z0.d, z1.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xa0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 a5 ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl] // CHECK-INST: ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xa8,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed a8 a5 ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] // CHECK-INST: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xa5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 a5 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld2h.s b/llvm/test/MC/AArch64/SVE/ld2h.s index c8e1ff91388bc..f92efb7099235 100644 --- a/llvm/test/MC/AArch64/SVE/ld2h.s +++ b/llvm/test/MC/AArch64/SVE/ld2h.s @@ -12,29 +12,29 @@ ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] // CHECK-INST: ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0xc0,0xa0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a0 a4 ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] // CHECK-INST: ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0xce,0xb0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce b0 a4 ld2h { z0.h, z1.h }, p0/z, [x0] // CHECK-INST: ld2h { z0.h, z1.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xa0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 a4 ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] // CHECK-INST: ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xa8,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed a8 a4 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] // CHECK-INST: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xa5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 a5 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld2w.s b/llvm/test/MC/AArch64/SVE/ld2w.s index caf2d60a3911c..355071df8b53a 100644 --- a/llvm/test/MC/AArch64/SVE/ld2w.s +++ b/llvm/test/MC/AArch64/SVE/ld2w.s @@ -12,29 +12,29 @@ ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2] // CHECK-INST: ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0xc0,0x20,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 20 a5 ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2] // CHECK-INST: ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0xce,0x30,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 30 a5 ld2w { z0.s, z1.s }, p0/z, [x0] // CHECK-INST: ld2w { z0.s, z1.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x20,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 20 a5 ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl] // CHECK-INST: ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x28,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 28 a5 ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] // CHECK-INST: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x25,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 25 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld3b.s b/llvm/test/MC/AArch64/SVE/ld3b.s index 0e074c0e53c10..b16e7b0e3e60e 100644 --- a/llvm/test/MC/AArch64/SVE/ld3b.s +++ b/llvm/test/MC/AArch64/SVE/ld3b.s @@ -12,29 +12,29 @@ ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0] // CHECK-INST: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0xc0,0x40,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 40 a4 ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16] // CHECK-INST: ld3b { z5.b, z6.b, z7.b }, p3/z, [x17, x16] // CHECK-ENCODING: [0x25,0xce,0x50,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 50 a4 ld3b { z0.b, z1.b, z2.b }, p0/z, [x0] // CHECK-INST: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 a4 ld3b { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl] // CHECK-INST: ld3b { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x48,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 48 a4 ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] // CHECK-INST: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x45,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 45 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld3d.s b/llvm/test/MC/AArch64/SVE/ld3d.s index 9f8a8ac746623..7840a3e0f8e4a 100644 --- a/llvm/test/MC/AArch64/SVE/ld3d.s +++ b/llvm/test/MC/AArch64/SVE/ld3d.s @@ -12,29 +12,29 @@ ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3] // CHECK-INST: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 c0 a5 ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3] // CHECK-INST: ld3d { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0xce,0xd0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce d0 a5 ld3d { z0.d, z1.d, z2.d }, p0/z, [x0] // CHECK-INST: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 a5 ld3d { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl] // CHECK-INST: ld3d { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed c8 a5 ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] // CHECK-INST: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 c5 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld3h.s b/llvm/test/MC/AArch64/SVE/ld3h.s index 92cab32e41604..5304481ebc515 100644 --- a/llvm/test/MC/AArch64/SVE/ld3h.s +++ b/llvm/test/MC/AArch64/SVE/ld3h.s @@ -12,29 +12,29 @@ ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1] // CHECK-INST: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 c0 a4 ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1] // CHECK-INST: ld3h { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0xce,0xd0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce d0 a4 ld3h { z0.h, z1.h, z2.h }, p0/z, [x0] // CHECK-INST: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 a4 ld3h { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl] // CHECK-INST: ld3h { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed c8 a4 ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK-INST: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 c5 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld3w.s b/llvm/test/MC/AArch64/SVE/ld3w.s index 6c7170dcb05ea..46d514ab95aae 100644 --- a/llvm/test/MC/AArch64/SVE/ld3w.s +++ b/llvm/test/MC/AArch64/SVE/ld3w.s @@ -12,29 +12,29 @@ ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2] // CHECK-INST: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0xc0,0x40,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 40 a5 ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2] // CHECK-INST: ld3w { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0xce,0x50,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 50 a5 ld3w { z0.s, z1.s, z2.s }, p0/z, [x0] // CHECK-INST: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 a5 ld3w { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl] // CHECK-INST: ld3w { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x48,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 48 a5 ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] // CHECK-INST: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x45,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 45 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld4b.s b/llvm/test/MC/AArch64/SVE/ld4b.s index c656bcdf26f21..768d366882988 100644 --- a/llvm/test/MC/AArch64/SVE/ld4b.s +++ b/llvm/test/MC/AArch64/SVE/ld4b.s @@ -12,29 +12,29 @@ ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0] // CHECK-INST: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0xc0,0x60,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 60 a4 ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16] // CHECK-INST: ld4b { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16] // CHECK-ENCODING: [0x25,0xce,0x70,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 70 a4 ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0] // CHECK-INST: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 a4 ld4b { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl] // CHECK-INST: ld4b { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x68,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 68 a4 ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] // CHECK-INST: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x65,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 65 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld4d.s b/llvm/test/MC/AArch64/SVE/ld4d.s index 46a35db517b5a..9e077d78613fb 100644 --- a/llvm/test/MC/AArch64/SVE/ld4d.s +++ b/llvm/test/MC/AArch64/SVE/ld4d.s @@ -12,29 +12,29 @@ ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3] // CHECK-INST: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e0 a5 ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3] // CHECK-INST: ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0xce,0xf0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce f0 a5 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] // CHECK-INST: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 a5 ld4d { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl] // CHECK-INST: ld4d { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed e8 a5 ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] // CHECK-INST: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 e5 a5 diff --git a/llvm/test/MC/AArch64/SVE/ld4h.s b/llvm/test/MC/AArch64/SVE/ld4h.s index c173ed140b2a0..db73e6c825f1b 100644 --- a/llvm/test/MC/AArch64/SVE/ld4h.s +++ b/llvm/test/MC/AArch64/SVE/ld4h.s @@ -12,29 +12,29 @@ ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1] // CHECK-INST: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e0 a4 ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1] // CHECK-INST: ld4h { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0xce,0xf0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce f0 a4 ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] // CHECK-INST: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 a4 ld4h { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl] // CHECK-INST: ld4h { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed e8 a4 ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] // CHECK-INST: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 e5 a4 diff --git a/llvm/test/MC/AArch64/SVE/ld4w.s b/llvm/test/MC/AArch64/SVE/ld4w.s index 29092e710d747..130309c44f8d7 100644 --- a/llvm/test/MC/AArch64/SVE/ld4w.s +++ b/llvm/test/MC/AArch64/SVE/ld4w.s @@ -12,29 +12,29 @@ ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2] // CHECK-INST: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0xc0,0x60,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 60 a5 ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2] // CHECK-INST: ld4w { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0xce,0x70,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 ce 70 a5 ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0] // CHECK-INST: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 a5 ld4w { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl] // CHECK-INST: ld4w { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x68,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 68 a5 ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] // CHECK-INST: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x65,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 65 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldnt1b.s b/llvm/test/MC/AArch64/SVE/ldnt1b.s index 0ad86883b3c9c..55fd4139198f2 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1b.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1b.s @@ -12,29 +12,29 @@ ldnt1b z0.b, p0/z, [x0] // CHECK-INST: ldnt1b { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 a4 ldnt1b { z0.b }, p0/z, [x0] // CHECK-INST: ldnt1b { z0.b }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 a4 ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl] // CHECK-INST: ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x08,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 08 a4 ldnt1b { z21.b }, p5/z, [x10, #7, mul vl] // CHECK-INST: ldnt1b { z21.b }, p5/z, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x07,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 07 a4 ldnt1b { z0.b }, p0/z, [x0, x0] // CHECK-INST: ldnt1b { z0.b }, p0/z, [x0, x0] // CHECK-ENCODING: [0x00,0xc0,0x00,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 00 a4 diff --git a/llvm/test/MC/AArch64/SVE/ldnt1d.s b/llvm/test/MC/AArch64/SVE/ldnt1d.s index 7e881b6ef43a6..627bec9917072 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1d.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1d.s @@ -12,29 +12,29 @@ ldnt1d z0.d, p0/z, [x0] // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 80 a5 ldnt1d { z0.d }, p0/z, [x0] // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 80 a5 ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl] // CHECK-INST: ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x88,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 88 a5 ldnt1d { z21.d }, p5/z, [x10, #7, mul vl] // CHECK-INST: ldnt1d { z21.d }, p5/z, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x87,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 87 a5 ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] // CHECK-INST: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0xc0,0x80,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 80 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldnt1h.s b/llvm/test/MC/AArch64/SVE/ldnt1h.s index 139fd5257cad7..51e597ae1ed44 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1h.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1h.s @@ -12,29 +12,29 @@ ldnt1h z0.h, p0/z, [x0] // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 80 a4 ldnt1h { z0.h }, p0/z, [x0] // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 80 a4 ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl] // CHECK-INST: ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x88,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 88 a4 ldnt1h { z21.h }, p5/z, [x10, #7, mul vl] // CHECK-INST: ldnt1h { z21.h }, p5/z, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x87,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 87 a4 ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] // CHECK-INST: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0xc0,0x80,0xa4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 80 a4 diff --git a/llvm/test/MC/AArch64/SVE/ldnt1w.s b/llvm/test/MC/AArch64/SVE/ldnt1w.s index f0e10ee10c82c..be21f828ca763 100644 --- a/llvm/test/MC/AArch64/SVE/ldnt1w.s +++ b/llvm/test/MC/AArch64/SVE/ldnt1w.s @@ -12,29 +12,29 @@ ldnt1w z0.s, p0/z, [x0] // CHECK-INST: ldnt1w { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 a5 ldnt1w { z0.s }, p0/z, [x0] // CHECK-INST: ldnt1w { z0.s }, p0/z, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 a5 ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl] // CHECK-INST: ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x08,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 08 a5 ldnt1w { z21.s }, p5/z, [x10, #7, mul vl] // CHECK-INST: ldnt1w { z21.s }, p5/z, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x07,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 07 a5 ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] // CHECK-INST: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0xc0,0x00,0xa5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 00 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldr.s b/llvm/test/MC/AArch64/SVE/ldr.s index 1e86e0056f896..857e9f37c6fc4 100644 --- a/llvm/test/MC/AArch64/SVE/ldr.s +++ b/llvm/test/MC/AArch64/SVE/ldr.s @@ -12,35 +12,35 @@ ldr z0, [x0] // CHECK-INST: ldr z0, [x0] // CHECK-ENCODING: [0x00,0x40,0x80,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 80 85 ldr z31, [sp, #-256, mul vl] // CHECK-INST: ldr z31, [sp, #-256, mul vl] // CHECK-ENCODING: [0xff,0x43,0xa0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 43 a0 85 ldr z23, [x13, #255, mul vl] // CHECK-INST: ldr z23, [x13, #255, mul vl] // CHECK-ENCODING: [0xb7,0x5d,0x9f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 5d 9f 85 ldr p0, [x0] // CHECK-INST: ldr p0, [x0] // CHECK-ENCODING: [0x00,0x00,0x80,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 85 ldr p7, [x13, #-256, mul vl] // CHECK-INST: ldr p7, [x13, #-256, mul vl] // CHECK-ENCODING: [0xa7,0x01,0xa0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 01 a0 85 ldr p5, [x10, #255, mul vl] // CHECK-INST: ldr p5, [x10, #255, mul vl] // CHECK-ENCODING: [0x45,0x1d,0x9f,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 45 1d 9f 85 diff --git a/llvm/test/MC/AArch64/SVE/lsl.s b/llvm/test/MC/AArch64/SVE/lsl.s index b95d973949ec2..3befa0bd5c164 100644 --- a/llvm/test/MC/AArch64/SVE/lsl.s +++ b/llvm/test/MC/AArch64/SVE/lsl.s @@ -12,157 +12,157 @@ lsl z0.b, z0.b, #0 // CHECK-INST: lsl z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0x9c,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 9c 28 04 lsl z31.b, z31.b, #7 // CHECK-INST: lsl z31.b, z31.b, #7 // CHECK-ENCODING: [0xff,0x9f,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 2f 04 lsl z0.h, z0.h, #0 // CHECK-INST: lsl z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0x9c,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 9c 30 04 lsl z31.h, z31.h, #15 // CHECK-INST: lsl z31.h, z31.h, #15 // CHECK-ENCODING: [0xff,0x9f,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 3f 04 lsl z0.s, z0.s, #0 // CHECK-INST: lsl z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0x9c,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 9c 60 04 lsl z31.s, z31.s, #31 // CHECK-INST: lsl z31.s, z31.s, #31 // CHECK-ENCODING: [0xff,0x9f,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 7f 04 lsl z0.d, z0.d, #0 // CHECK-INST: lsl z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0x9c,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 9c a0 04 lsl z31.d, z31.d, #63 // CHECK-INST: lsl z31.d, z31.d, #63 // CHECK-ENCODING: [0xff,0x9f,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f ff 04 lsl z0.b, p0/m, z0.b, #0 // CHECK-INST: lsl z0.b, p0/m, z0.b, #0 // CHECK-ENCODING: [0x00,0x81,0x03,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 81 03 04 lsl z31.b, p0/m, z31.b, #7 // CHECK-INST: lsl z31.b, p0/m, z31.b, #7 // CHECK-ENCODING: [0xff,0x81,0x03,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 81 03 04 lsl z0.h, p0/m, z0.h, #0 // CHECK-INST: lsl z0.h, p0/m, z0.h, #0 // CHECK-ENCODING: [0x00,0x82,0x03,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 82 03 04 lsl z31.h, p0/m, z31.h, #15 // CHECK-INST: lsl z31.h, p0/m, z31.h, #15 // CHECK-ENCODING: [0xff,0x83,0x03,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 83 03 04 lsl z0.s, p0/m, z0.s, #0 // CHECK-INST: lsl z0.s, p0/m, z0.s, #0 // CHECK-ENCODING: [0x00,0x80,0x43,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 43 04 lsl z31.s, p0/m, z31.s, #31 // CHECK-INST: lsl z31.s, p0/m, z31.s, #31 // CHECK-ENCODING: [0xff,0x83,0x43,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 83 43 04 lsl z0.d, p0/m, z0.d, #0 // CHECK-INST: lsl z0.d, p0/m, z0.d, #0 // CHECK-ENCODING: [0x00,0x80,0x83,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 83 04 lsl z31.d, p0/m, z31.d, #63 // CHECK-INST: lsl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 83 c3 04 lsl z0.b, p0/m, z0.b, z0.b // CHECK-INST: lsl z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x13,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 13 04 lsl z0.h, p0/m, z0.h, z0.h // CHECK-INST: lsl z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x53,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 53 04 lsl z0.s, p0/m, z0.s, z0.s // CHECK-INST: lsl z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x93,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 93 04 lsl z0.d, p0/m, z0.d, z0.d // CHECK-INST: lsl z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d3 04 lsl z0.b, p0/m, z0.b, z1.d // CHECK-INST: lsl z0.b, p0/m, z0.b, z1.d // CHECK-ENCODING: [0x20,0x80,0x1b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 1b 04 lsl z0.h, p0/m, z0.h, z1.d // CHECK-INST: lsl z0.h, p0/m, z0.h, z1.d // CHECK-ENCODING: [0x20,0x80,0x5b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 5b 04 lsl z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x9b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 9b 04 lsl z0.b, z1.b, z2.d // CHECK-INST: lsl z0.b, z1.b, z2.d // CHECK-ENCODING: [0x20,0x8c,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 8c 22 04 lsl z0.h, z1.h, z2.d // CHECK-INST: lsl z0.h, z1.h, z2.d // CHECK-ENCODING: [0x20,0x8c,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 8c 62 04 lsl z0.s, z1.s, z2.d // CHECK-INST: lsl z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x8c,0xa2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 8c a2 04 @@ -172,47 +172,47 @@ lsl z0.s, z1.s, z2.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 lsl z31.d, p0/m, z31.d, #63 // CHECK-INST: lsl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 83 c3 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 lsl z31.d, p0/m, z31.d, #63 // CHECK-INST: lsl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 83 c3 04 movprfx z0.s, p0/z, z7.s // CHECK-INST: movprfx z0.s, p0/z, z7.s // CHECK-ENCODING: [0xe0,0x20,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 90 04 lsl z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x9b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 9b 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 lsl z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x9b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 9b 04 diff --git a/llvm/test/MC/AArch64/SVE/lslr.s b/llvm/test/MC/AArch64/SVE/lslr.s index e53e09eaa0c9b..5fbb8d62f7d11 100644 --- a/llvm/test/MC/AArch64/SVE/lslr.s +++ b/llvm/test/MC/AArch64/SVE/lslr.s @@ -12,25 +12,25 @@ lslr z0.b, p0/m, z0.b, z0.b // CHECK-INST: lslr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x17,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 17 04 lslr z0.h, p0/m, z0.h, z0.h // CHECK-INST: lslr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x57,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 57 04 lslr z0.s, p0/m, z0.s, z0.s // CHECK-INST: lslr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x97,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 97 04 lslr z0.d, p0/m, z0.d, z0.d // CHECK-INST: lslr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d7 04 @@ -40,23 +40,23 @@ lslr z0.d, p0/m, z0.d, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 lslr z5.d, p0/m, z5.d, z0.d // CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d7 04 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 lslr z5.d, p0/m, z5.d, z0.d // CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d7 04 diff --git a/llvm/test/MC/AArch64/SVE/lsr.s b/llvm/test/MC/AArch64/SVE/lsr.s index d0706c8fcb53e..d0edca12d5517 100644 --- a/llvm/test/MC/AArch64/SVE/lsr.s +++ b/llvm/test/MC/AArch64/SVE/lsr.s @@ -12,157 +12,157 @@ lsr z0.b, z0.b, #1 // CHECK-INST: lsr z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0x94,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 94 2f 04 lsr z31.b, z31.b, #8 // CHECK-INST: lsr z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0x97,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 97 28 04 lsr z0.h, z0.h, #1 // CHECK-INST: lsr z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0x94,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 94 3f 04 lsr z31.h, z31.h, #16 // CHECK-INST: lsr z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0x97,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 97 30 04 lsr z0.s, z0.s, #1 // CHECK-INST: lsr z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0x94,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 94 7f 04 lsr z31.s, z31.s, #32 // CHECK-INST: lsr z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0x97,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 97 60 04 lsr z0.d, z0.d, #1 // CHECK-INST: lsr z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0x94,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 94 ff 04 lsr z31.d, z31.d, #64 // CHECK-INST: lsr z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0x97,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 97 a0 04 lsr z0.b, p0/m, z0.b, #1 // CHECK-INST: lsr z0.b, p0/m, z0.b, #1 // CHECK-ENCODING: [0xe0,0x81,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 81 01 04 lsr z31.b, p0/m, z31.b, #8 // CHECK-INST: lsr z31.b, p0/m, z31.b, #8 // CHECK-ENCODING: [0x1f,0x81,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 81 01 04 lsr z0.h, p0/m, z0.h, #1 // CHECK-INST: lsr z0.h, p0/m, z0.h, #1 // CHECK-ENCODING: [0xe0,0x83,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 01 04 lsr z31.h, p0/m, z31.h, #16 // CHECK-INST: lsr z31.h, p0/m, z31.h, #16 // CHECK-ENCODING: [0x1f,0x82,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 82 01 04 lsr z0.s, p0/m, z0.s, #1 // CHECK-INST: lsr z0.s, p0/m, z0.s, #1 // CHECK-ENCODING: [0xe0,0x83,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 41 04 lsr z31.s, p0/m, z31.s, #32 // CHECK-INST: lsr z31.s, p0/m, z31.s, #32 // CHECK-ENCODING: [0x1f,0x80,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 41 04 lsr z0.d, p0/m, z0.d, #1 // CHECK-INST: lsr z0.d, p0/m, z0.d, #1 // CHECK-ENCODING: [0xe0,0x83,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 83 c1 04 lsr z31.d, p0/m, z31.d, #64 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 81 04 lsr z0.b, p0/m, z0.b, z0.b // CHECK-INST: lsr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x11,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 11 04 lsr z0.h, p0/m, z0.h, z0.h // CHECK-INST: lsr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x51,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 51 04 lsr z0.s, p0/m, z0.s, z0.s // CHECK-INST: lsr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x91,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 91 04 lsr z0.d, p0/m, z0.d, z0.d // CHECK-INST: lsr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d1 04 lsr z0.b, p0/m, z0.b, z1.d // CHECK-INST: lsr z0.b, p0/m, z0.b, z1.d // CHECK-ENCODING: [0x20,0x80,0x19,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 19 04 lsr z0.h, p0/m, z0.h, z1.d // CHECK-INST: lsr z0.h, p0/m, z0.h, z1.d // CHECK-ENCODING: [0x20,0x80,0x59,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 59 04 lsr z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 99 04 lsr z0.b, z1.b, z2.d // CHECK-INST: lsr z0.b, z1.b, z2.d // CHECK-ENCODING: [0x20,0x84,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 84 22 04 lsr z0.h, z1.h, z2.d // CHECK-INST: lsr z0.h, z1.h, z2.d // CHECK-ENCODING: [0x20,0x84,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 84 62 04 lsr z0.s, z1.s, z2.d // CHECK-INST: lsr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x84,0xa2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 84 a2 04 @@ -172,47 +172,47 @@ lsr z0.s, z1.s, z2.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 lsr z31.d, p0/m, z31.d, #64 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 81 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 lsr z31.d, p0/m, z31.d, #64 // CHECK-INST: lsr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 80 81 04 movprfx z0.s, p0/z, z7.s // CHECK-INST: movprfx z0.s, p0/z, z7.s // CHECK-ENCODING: [0xe0,0x20,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 20 90 04 lsr z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 99 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 lsr z0.s, p0/m, z0.s, z1.d // CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d // CHECK-ENCODING: [0x20,0x80,0x99,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 80 99 04 diff --git a/llvm/test/MC/AArch64/SVE/lsrr.s b/llvm/test/MC/AArch64/SVE/lsrr.s index 9ab593abd9162..b5d4fca5382ba 100644 --- a/llvm/test/MC/AArch64/SVE/lsrr.s +++ b/llvm/test/MC/AArch64/SVE/lsrr.s @@ -12,25 +12,25 @@ lsrr z0.b, p0/m, z0.b, z0.b // CHECK-INST: lsrr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x15,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 15 04 lsrr z0.h, p0/m, z0.h, z0.h // CHECK-INST: lsrr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x55,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 55 04 lsrr z0.s, p0/m, z0.s, z0.s // CHECK-INST: lsrr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x95,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 95 04 lsrr z0.d, p0/m, z0.d, z0.d // CHECK-INST: lsrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 d5 04 @@ -40,23 +40,23 @@ lsrr z0.d, p0/m, z0.d, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 lsrr z5.d, p0/m, z5.d, z0.d // CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d5 04 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 lsrr z5.d, p0/m, z5.d, z0.d // CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x80,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 80 d5 04 diff --git a/llvm/test/MC/AArch64/SVE/mad.s b/llvm/test/MC/AArch64/SVE/mad.s index 417c8561f4dbf..a92e26262b687 100644 --- a/llvm/test/MC/AArch64/SVE/mad.s +++ b/llvm/test/MC/AArch64/SVE/mad.s @@ -12,25 +12,25 @@ mad z0.b, p7/m, z1.b, z31.b // CHECK-INST: mad z0.b, p7/m, z1.b, z31.b // CHECK-ENCODING: [0xe0,0xdf,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df 01 04 mad z0.h, p7/m, z1.h, z31.h // CHECK-INST: mad z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0xe0,0xdf,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df 41 04 mad z0.s, p7/m, z1.s, z31.s // CHECK-INST: mad z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0xe0,0xdf,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df 81 04 mad z0.d, p7/m, z1.d, z31.d // CHECK-INST: mad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df c1 04 @@ -40,23 +40,23 @@ mad z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 mad z0.d, p7/m, z1.d, z31.d // CHECK-INST: mad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df c1 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mad z0.d, p7/m, z1.d, z31.d // CHECK-INST: mad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 df c1 04 diff --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s index 9477199742edb..b80398076ab89 100644 --- a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s +++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s @@ -239,13 +239,13 @@ ld1rod z0.d, p1/z, [x2, x3, lsl #3] zip1 z0.q, z1.q, z2.q // CHECK-INST: zip1 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x00,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 00 a2 05 zip2 z0.q, z1.q, z2.q // CHECK-INST: zip2 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x04,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 04 a2 05 @@ -255,13 +255,13 @@ zip2 z0.q, z1.q, z2.q uzp1 z0.q, z1.q, z2.q // CHECK-INST: uzp1 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x08,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 08 a2 05 uzp2 z0.q, z1.q, z2.q // CHECK-INST: uzp2 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x0c,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 0c a2 05 @@ -271,11 +271,11 @@ uzp2 z0.q, z1.q, z2.q trn1 z0.q, z1.q, z2.q // CHECK-INST: trn1 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x18,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 18 a2 05 trn2 z0.q, z1.q, z2.q // CHECK-INST: trn2 z0.q, z1.q, z2.q // CHECK-ENCODING: [0x20,0x1c,0xa2,0x05] -// CHECK-ERROR: instruction requires: f64mm streaming-sve +// CHECK-ERROR: instruction requires: f64mm sve or sme // CHECK-UNKNOWN: 20 1c a2 05 diff --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s index ef0260a8d06f0..04152bd37aeb4 100644 --- a/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s +++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s @@ -72,7 +72,7 @@ usmmla z0.s, z1.b, z2.b usdot z0.s, z1.b, z2.b // CHECK-INST: usdot z0.s, z1.b, z2.b // CHECK-ENCODING: [0x20,0x78,0x82,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 78 82 44 // Test compatibility with MOVPRFX instruction. @@ -85,7 +85,7 @@ movprfx z0, z7 usdot z0.s, z1.b, z2.b // CHECK-INST: usdot z0.s, z1.b, z2.b // CHECK-ENCODING: [0x20,0x78,0x82,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 78 82 44 @@ -95,13 +95,13 @@ usdot z0.s, z1.b, z2.b usdot z0.s, z1.b, z2.b[0] // CHECK-INST: usdot z0.s, z1.b, z2.b[0] // CHECK-ENCODING: [0x20,0x18,0xa2,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 18 a2 44 sudot z0.s, z1.b, z2.b[3] // CHECK-INST: sudot z0.s, z1.b, z2.b[3] // CHECK-ENCODING: [0x20,0x1c,0xba,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 1c ba 44 // Test compatibility with MOVPRFX instruction. @@ -114,7 +114,7 @@ movprfx z0, z7 usdot z0.s, z1.b, z2.b[0] // CHECK-INST: usdot z0.s, z1.b, z2.b[0] // CHECK-ENCODING: [0x20,0x18,0xa2,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 18 a2 44 movprfx z0, z7 @@ -125,5 +125,5 @@ movprfx z0, z7 sudot z0.s, z1.b, z2.b[0] // CHECK-INST: sudot z0.s, z1.b, z2.b[0] // CHECK-ENCODING: [0x20,0x1c,0xa2,0x44] -// CHECK-ERROR: instruction requires: i8mm streaming-sve +// CHECK-ERROR: instruction requires: i8mm sve or sme // CHECK-UNKNOWN: 20 1c a2 44 diff --git a/llvm/test/MC/AArch64/SVE/mla.s b/llvm/test/MC/AArch64/SVE/mla.s index 99ec77dd1c403..5d21bb92b3402 100644 --- a/llvm/test/MC/AArch64/SVE/mla.s +++ b/llvm/test/MC/AArch64/SVE/mla.s @@ -12,25 +12,25 @@ mla z0.b, p7/m, z1.b, z31.b // CHECK-INST: mla z0.b, p7/m, z1.b, z31.b // CHECK-ENCODING: [0x20,0x5c,0x1f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c 1f 04 mla z0.h, p7/m, z1.h, z31.h // CHECK-INST: mla z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x5c,0x5f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c 5f 04 mla z0.s, p7/m, z1.s, z31.s // CHECK-INST: mla z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x5c,0x9f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c 9f 04 mla z0.d, p7/m, z1.d, z31.d // CHECK-INST: mla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c df 04 @@ -40,23 +40,23 @@ mla z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 mla z0.d, p7/m, z1.d, z31.d // CHECK-INST: mla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c df 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mla z0.d, p7/m, z1.d, z31.d // CHECK-INST: mla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 5c df 04 diff --git a/llvm/test/MC/AArch64/SVE/mls.s b/llvm/test/MC/AArch64/SVE/mls.s index dade119e9dc9a..3068c2da049cd 100644 --- a/llvm/test/MC/AArch64/SVE/mls.s +++ b/llvm/test/MC/AArch64/SVE/mls.s @@ -12,25 +12,25 @@ mls z0.b, p7/m, z1.b, z31.b // CHECK-INST: mls z0.b, p7/m, z1.b, z31.b // CHECK-ENCODING: [0x20,0x7c,0x1f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 1f 04 mls z0.h, p7/m, z1.h, z31.h // CHECK-INST: mls z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0x20,0x7c,0x5f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 5f 04 mls z0.s, p7/m, z1.s, z31.s // CHECK-INST: mls z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0x20,0x7c,0x9f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c 9f 04 mls z0.d, p7/m, z1.d, z31.d // CHECK-INST: mls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c df 04 @@ -40,23 +40,23 @@ mls z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 mls z0.d, p7/m, z1.d, z31.d // CHECK-INST: mls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c df 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mls z0.d, p7/m, z1.d, z31.d // CHECK-INST: mls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 7c df 04 diff --git a/llvm/test/MC/AArch64/SVE/mov.s b/llvm/test/MC/AArch64/SVE/mov.s index 72b25a447e341..f6af81375d9d8 100644 --- a/llvm/test/MC/AArch64/SVE/mov.s +++ b/llvm/test/MC/AArch64/SVE/mov.s @@ -12,367 +12,367 @@ mov z0.b, w0 // CHECK-INST: mov z0.b, w0 // CHECK-ENCODING: [0x00,0x38,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 20 05 mov z0.h, w0 // CHECK-INST: mov z0.h, w0 // CHECK-ENCODING: [0x00,0x38,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 60 05 mov z0.s, w0 // CHECK-INST: mov z0.s, w0 // CHECK-ENCODING: [0x00,0x38,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 a0 05 mov z0.d, x0 // CHECK-INST: mov z0.d, x0 // CHECK-ENCODING: [0x00,0x38,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 38 e0 05 mov z31.h, wsp // CHECK-INST: mov z31.h, wsp // CHECK-ENCODING: [0xff,0x3b,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 60 05 mov z31.s, wsp // CHECK-INST: mov z31.s, wsp // CHECK-ENCODING: [0xff,0x3b,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b a0 05 mov z31.d, sp // CHECK-INST: mov z31.d, sp // CHECK-ENCODING: [0xff,0x3b,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b e0 05 mov z31.b, wsp // CHECK-INST: mov z31.b, wsp // CHECK-ENCODING: [0xff,0x3b,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 20 05 mov z0.d, z0.d // CHECK-INST: mov z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 60 04 mov z31.d, z0.d // CHECK-INST: mov z31.d, z0.d // CHECK-ENCODING: [0x1f,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 30 60 04 mov z5.b, #-128 // CHECK-INST: mov z5.b, #-128 // CHECK-ENCODING: [0x05,0xd0,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 d0 38 25 mov z5.b, #127 // CHECK-INST: mov z5.b, #127 // CHECK-ENCODING: [0xe5,0xcf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 cf 38 25 mov z5.b, #255 // CHECK-INST: mov z5.b, #-1 // CHECK-ENCODING: [0xe5,0xdf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 df 38 25 mov z21.h, #-128 // CHECK-INST: mov z21.h, #-128 // CHECK-ENCODING: [0x15,0xd0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 78 25 mov z21.h, #-128, lsl #8 // CHECK-INST: mov z21.h, #-32768 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 78 25 mov z21.h, #-32768 // CHECK-INST: mov z21.h, #-32768 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 78 25 mov z21.h, #127 // CHECK-INST: mov z21.h, #127 // CHECK-ENCODING: [0xf5,0xcf,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf 78 25 mov z21.h, #127, lsl #8 // CHECK-INST: mov z21.h, #32512 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef 78 25 mov z21.h, #32512 // CHECK-INST: mov z21.h, #32512 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef 78 25 mov z21.s, #-128 // CHECK-INST: mov z21.s, #-128 // CHECK-ENCODING: [0x15,0xd0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 b8 25 mov z21.s, #-128, lsl #8 // CHECK-INST: mov z21.s, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 b8 25 mov z21.s, #-32768 // CHECK-INST: mov z21.s, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 b8 25 mov z21.s, #127 // CHECK-INST: mov z21.s, #127 // CHECK-ENCODING: [0xf5,0xcf,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf b8 25 mov z21.s, #127, lsl #8 // CHECK-INST: mov z21.s, #32512 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef b8 25 mov z21.s, #32512 // CHECK-INST: mov z21.s, #32512 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef b8 25 mov z21.d, #-128 // CHECK-INST: mov z21.d, #-128 // CHECK-ENCODING: [0x15,0xd0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 d0 f8 25 mov z21.d, #-128, lsl #8 // CHECK-INST: mov z21.d, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 f8 25 mov z21.d, #-32768 // CHECK-INST: mov z21.d, #-32768 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 f0 f8 25 mov z21.d, #127 // CHECK-INST: mov z21.d, #127 // CHECK-ENCODING: [0xf5,0xcf,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 cf f8 25 mov z21.d, #127, lsl #8 // CHECK-INST: mov z21.d, #32512 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef f8 25 mov z21.d, #32512 // CHECK-INST: mov z21.d, #32512 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 ef f8 25 mov z0.h, #32768 // CHECK-INST: mov z0.h, #-32768 // CHECK-ENCODING: [0x00,0xf0,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 78 25 mov z0.h, #65280 // CHECK-INST: mov z0.h, #-256 // CHECK-ENCODING: [0xe0,0xff,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 78 25 mov z0.h, #-33024 // CHECK-INST: mov z0.h, #32512 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ef 78 25 mov z0.h, #-32769 // CHECK-INST: mov z0.h, #32767 // CHECK-ENCODING: [0xc0,0x05,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 05 c0 05 mov z0.s, #-32769 // CHECK-INST: mov z0.s, #0xffff7fff // CHECK-ENCODING: [0xc0,0x83,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 83 c0 05 mov z0.s, #32768 // CHECK-INST: mov z0.s, #32768 // CHECK-ENCODING: [0x00,0x88,0xc0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 c0 05 mov z0.d, #-32769 // CHECK-INST: mov z0.d, #0xffffffffffff7fff // CHECK-ENCODING: [0xc0,0x87,0xc3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 87 c3 05 mov z0.d, #32768 // CHECK-INST: mov z0.d, #32768 // CHECK-ENCODING: [0x00,0x88,0xc3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 88 c3 05 mov z0.d, #0xe0000000000003ff // CHECK-INST: mov z0.d, #0xe0000000000003ff // CHECK-ENCODING: [0x80,0x19,0xc2,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 19 c2 05 mov z5.b, p0/z, #-128 // CHECK-INST: mov z5.b, p0/z, #-128 // CHECK-ENCODING: [0x05,0x10,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 10 10 05 mov z5.b, p0/z, #127 // CHECK-INST: mov z5.b, p0/z, #127 // CHECK-ENCODING: [0xe5,0x0f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 0f 10 05 mov z5.b, p0/z, #255 // CHECK-INST: mov z5.b, p0/z, #-1 // CHECK-ENCODING: [0xe5,0x1f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 1f 10 05 mov z21.h, p0/z, #-128 // CHECK-INST: mov z21.h, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 50 05 mov z21.h, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.h, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 50 05 mov z21.h, p0/z, #-32768 // CHECK-INST: mov z21.h, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 50 05 mov z21.h, p0/z, #127 // CHECK-INST: mov z21.h, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f 50 05 mov z21.h, p0/z, #127, lsl #8 // CHECK-INST: mov z21.h, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 50 05 mov z21.h, p0/z, #32512 // CHECK-INST: mov z21.h, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 50 05 mov z21.s, p0/z, #-128 // CHECK-INST: mov z21.s, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 90 05 mov z21.s, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.s, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 90 05 mov z21.s, p0/z, #-32768 // CHECK-INST: mov z21.s, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 90 05 mov z21.s, p0/z, #127 // CHECK-INST: mov z21.s, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f 90 05 mov z21.s, p0/z, #127, lsl #8 // CHECK-INST: mov z21.s, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 90 05 mov z21.s, p0/z, #32512 // CHECK-INST: mov z21.s, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f 90 05 mov z21.d, p0/z, #-128 // CHECK-INST: mov z21.d, p0/z, #-128 // CHECK-ENCODING: [0x15,0x10,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 10 d0 05 mov z21.d, p0/z, #-128, lsl #8 // CHECK-INST: mov z21.d, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 d0 05 mov z21.d, p0/z, #-32768 // CHECK-INST: mov z21.d, p0/z, #-32768 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 30 d0 05 mov z21.d, p0/z, #127 // CHECK-INST: mov z21.d, p0/z, #127 // CHECK-ENCODING: [0xf5,0x0f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 0f d0 05 mov z21.d, p0/z, #127, lsl #8 // CHECK-INST: mov z21.d, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f d0 05 mov z21.d, p0/z, #32512 // CHECK-INST: mov z21.d, p0/z, #32512 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f5 2f d0 05 @@ -383,49 +383,49 @@ mov z21.d, p0/z, #32512 mov z0.b, #-129 // CHECK-INST: mov z0.b, #127 // CHECK-ENCODING: [0xe0,0xcf,0x38,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 38 25 mov z0.h, #-129, lsl #8 // CHECK-INST: mov z0.h, #32512 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ef 78 25 mov z5.h, #0xfffa // CHECK-INST: mov z5.h, #-6 // CHECK-ENCODING: [0x45,0xdf,0x78,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 45 df 78 25 mov z5.s, #0xfffffffa // CHECK-INST: mov z5.s, #-6 // CHECK-ENCODING: [0x45,0xdf,0xb8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 45 df b8 25 mov z5.d, #0xfffffffffffffffa // CHECK-INST: mov z5.d, #-6 // CHECK-ENCODING: [0x45,0xdf,0xf8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 45 df f8 25 mov z0.b, p0/z, #-129 // CHECK-INST: mov z0.b, p0/z, #127 // CHECK-ENCODING: [0xe0,0x0f,0x10,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 0f 10 05 mov z0.h, p0/z, #-33024 // CHECK-INST: mov z0.h, p0/z, #32512 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 2f 50 05 mov z0.h, p0/z, #-129, lsl #8 // CHECK-INST: mov z0.h, p0/z, #32512 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 2f 50 05 // --------------------------------------------------------------------------// @@ -435,43 +435,43 @@ mov z0.h, p0/z, #-129, lsl #8 mov z5.b, p15/m, #-128 // CHECK-INST: mov z5.b, p15/m, #-128 // CHECK-ENCODING: [0x05,0x50,0x1f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 50 1f 05 mov z21.h, p15/m, #-128 // CHECK-INST: mov z21.h, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0x5f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 5f 05 mov z21.h, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.h, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0x5f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 5f 05 mov z21.s, p15/m, #-128 // CHECK-INST: mov z21.s, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0x9f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 9f 05 mov z21.s, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.s, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0x9f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 9f 05 mov z21.d, p15/m, #-128 // CHECK-INST: mov z21.d, p15/m, #-128 // CHECK-ENCODING: [0x15,0x50,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 50 df 05 mov z21.d, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 df 05 // --------------------------------------------------------------------------// @@ -480,91 +480,91 @@ mov z21.d, p15/m, #-128, lsl #8 mov z0.b, z0.b[0] // CHECK-INST: mov z0.b, b0 // CHECK-ENCODING: [0x00,0x20,0x21,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 21 05 mov z0.h, z0.h[0] // CHECK-INST: mov z0.h, h0 // CHECK-ENCODING: [0x00,0x20,0x22,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 22 05 mov z0.s, z0.s[0] // CHECK-INST: mov z0.s, s0 // CHECK-ENCODING: [0x00,0x20,0x24,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 24 05 mov z0.d, z0.d[0] // CHECK-INST: mov z0.d, d0 // CHECK-ENCODING: [0x00,0x20,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 28 05 mov z0.q, z0.q[0] // CHECK-INST: mov z0.q, q0 // CHECK-ENCODING: [0x00,0x20,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 30 05 mov z0.b, b0 // CHECK-INST: mov z0.b, b0 // CHECK-ENCODING: [0x00,0x20,0x21,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 21 05 mov z0.h, h0 // CHECK-INST: mov z0.h, h0 // CHECK-ENCODING: [0x00,0x20,0x22,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 22 05 mov z0.s, s0 // CHECK-INST: mov z0.s, s0 // CHECK-ENCODING: [0x00,0x20,0x24,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 24 05 mov z0.d, d0 // CHECK-INST: mov z0.d, d0 // CHECK-ENCODING: [0x00,0x20,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 28 05 mov z0.q, q0 // CHECK-INST: mov z0.q, q0 // CHECK-ENCODING: [0x00,0x20,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 30 05 mov z31.b, z31.b[63] // CHECK-INST: mov z31.b, z31.b[63] // CHECK-ENCODING: [0xff,0x23,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 ff 05 mov z31.h, z31.h[31] // CHECK-INST: mov z31.h, z31.h[31] // CHECK-ENCODING: [0xff,0x23,0xfe,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 fe 05 mov z31.s, z31.s[15] // CHECK-INST: mov z31.s, z31.s[15] // CHECK-ENCODING: [0xff,0x23,0xfc,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 fc 05 mov z31.d, z31.d[7] // CHECK-INST: mov z31.d, z31.d[7] // CHECK-ENCODING: [0xff,0x23,0xf8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 23 f8 05 mov z5.q, z17.q[3] // CHECK-INST: mov z5.q, z17.q[3] // CHECK-ENCODING: [0x25,0x22,0xf0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 22 f0 05 @@ -574,157 +574,157 @@ mov z5.q, z17.q[3] mov z0.b, p0/m, w0 // CHECK-INST: mov z0.b, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 28 05 mov z0.h, p0/m, w0 // CHECK-INST: mov z0.h, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 68 05 mov z0.s, p0/m, w0 // CHECK-INST: mov z0.s, p0/m, w0 // CHECK-ENCODING: [0x00,0xa0,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 a8 05 mov z0.d, p0/m, x0 // CHECK-INST: mov z0.d, p0/m, x0 // CHECK-ENCODING: [0x00,0xa0,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 e8 05 mov z31.b, p7/m, wsp // CHECK-INST: mov z31.b, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 28 05 mov z31.h, p7/m, wsp // CHECK-INST: mov z31.h, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 68 05 mov z31.s, p7/m, wsp // CHECK-INST: mov z31.s, p7/m, wsp // CHECK-ENCODING: [0xff,0xbf,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf a8 05 mov z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 mov z0.b, p0/m, b0 // CHECK-INST: mov z0.b, p0/m, b0 // CHECK-ENCODING: [0x00,0x80,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 20 05 mov z31.b, p7/m, b31 // CHECK-INST: mov z31.b, p7/m, b31 // CHECK-ENCODING: [0xff,0x9f,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 20 05 mov z0.h, p0/m, h0 // CHECK-INST: mov z0.h, p0/m, h0 // CHECK-ENCODING: [0x00,0x80,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 60 05 mov z31.h, p7/m, h31 // CHECK-INST: mov z31.h, p7/m, h31 // CHECK-ENCODING: [0xff,0x9f,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 60 05 mov z0.s, p0/m, s0 // CHECK-INST: mov z0.s, p0/m, s0 // CHECK-ENCODING: [0x00,0x80,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a0 05 mov z31.s, p7/m, s31 // CHECK-INST: mov z31.s, p7/m, s31 // CHECK-ENCODING: [0xff,0x9f,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f a0 05 mov z0.d, p0/m, d0 // CHECK-INST: mov z0.d, p0/m, d0 // CHECK-ENCODING: [0x00,0x80,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e0 05 mov z31.d, p7/m, d31 // CHECK-INST: mov z31.d, p7/m, d31 // CHECK-ENCODING: [0xff,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f e0 05 mov p0.b, p0/m, p0.b // CHECK-INST: mov p0.b, p0/m, p0.b // CHECK-ENCODING: [0x10,0x42,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 42 00 25 mov p15.b, p15/m, p15.b // CHECK-INST: mov p15.b, p15/m, p15.b // CHECK-ENCODING: [0xff,0x7f,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f 0f 25 mov z31.b, p15/m, z31.b // CHECK-INST: mov z31.b, p15/m, z31.b // CHECK-ENCODING: [0xff,0xff,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 3f 05 mov z31.h, p15/m, z31.h // CHECK-INST: mov z31.h, p15/m, z31.h // CHECK-ENCODING: [0xff,0xff,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 7f 05 mov z31.s, p15/m, z31.s // CHECK-INST: mov z31.s, p15/m, z31.s // CHECK-ENCODING: [0xff,0xff,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff bf 05 mov z31.d, p15/m, z31.d // CHECK-INST: mov z31.d, p15/m, z31.d // CHECK-ENCODING: [0xff,0xff,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ff 05 mov p0.b, p0.b // CHECK-INST: mov p0.b, p0.b // CHECK-ENCODING: [0x00,0x40,0x80,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 80 25 mov p15.b, p15.b // CHECK-INST: mov p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 8f 25 mov p0.b, p0/z, p0.b // CHECK-INST: mov p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x40,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 25 mov p15.b, p15/z, p15.b // CHECK-INST: mov p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 0f 25 @@ -734,71 +734,71 @@ mov p15.b, p15/z, p15.b movprfx z31.d, p7/z, z6.d // CHECK-INST: movprfx z31.d, p7/z, z6.d // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 3c d0 04 mov z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 mov z31.d, p7/m, sp // CHECK-INST: mov z31.d, p7/m, sp // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf e8 05 movprfx z21.d, p7/z, z28.d // CHECK-INST: movprfx z21.d, p7/z, z28.d // CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 3f d0 04 mov z21.d, p7/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p7/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xd7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 d7 05 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 mov z21.d, p15/m, #-128, lsl #8 // CHECK-INST: mov z21.d, p15/m, #-32768 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 70 df 05 movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 mov z4.d, p7/m, d31 // CHECK-INST: mov z4.d, p7/m, d31 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f e0 05 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 mov z4.d, p7/m, d31 // CHECK-INST: mov z4.d, p7/m, d31 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f e0 05 diff --git a/llvm/test/MC/AArch64/SVE/movprfx.s b/llvm/test/MC/AArch64/SVE/movprfx.s index 869189e1874ff..52111b6f1073a 100644 --- a/llvm/test/MC/AArch64/SVE/movprfx.s +++ b/llvm/test/MC/AArch64/SVE/movprfx.s @@ -40,7 +40,7 @@ movprfx z0, z1 // CHECK-INST: movprfx z0, z1 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc 20 04 hlt #1 @@ -50,7 +50,7 @@ hlt #1 movprfx z0.d, p0/z, z1.d // CHECK-INST: movprfx z0.d, p0/z, z1.d // CHECK-ENCODING: [0x20,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 20 d0 04 hlt #1 @@ -60,7 +60,7 @@ hlt #1 movprfx z0, z1 // CHECK-INST: movprfx z0, z1 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc 20 04 brk #1 @@ -70,7 +70,7 @@ brk #1 movprfx z0.d, p0/z, z1.d // CHECK-INST: movprfx z0.d, p0/z, z1.d // CHECK-ENCODING: [0x20,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 20 d0 04 brk #1 @@ -83,17 +83,17 @@ brk #1 movprfx z0, z1 // CHECK-INST: movprfx z0, z1 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 bc 20 04 add z0.d, p0/m, z0.d, z1.d // CHECK-INST: add z0.d, p0/m, z0.d, z1.d // CHECK-ENCODING: [0x20,0x00,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 c0 04 add z0.d, p0/m, z0.d, z1.d // CHECK-INST: add z0.d, p0/m, z0.d, z1.d // CHECK-ENCODING: [0x20,0x00,0xc0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 c0 04 diff --git a/llvm/test/MC/AArch64/SVE/movs.s b/llvm/test/MC/AArch64/SVE/movs.s index d2d14d9312622..465ae9d4f5322 100644 --- a/llvm/test/MC/AArch64/SVE/movs.s +++ b/llvm/test/MC/AArch64/SVE/movs.s @@ -12,23 +12,23 @@ movs p0.b, p0.b // CHECK-INST: movs p0.b, p0.b // CHECK-ENCODING: [0x00,0x40,0xc0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 25 movs p15.b, p15.b // CHECK-INST: movs p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d cf 25 movs p0.b, p0/z, p0.b // CHECK-INST: movs p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x40,0x40,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 40 25 movs p15.b, p15/z, p15.b // CHECK-INST: movs p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/msb.s b/llvm/test/MC/AArch64/SVE/msb.s index 0a08783b0bb86..9a3179d80e910 100644 --- a/llvm/test/MC/AArch64/SVE/msb.s +++ b/llvm/test/MC/AArch64/SVE/msb.s @@ -12,25 +12,25 @@ msb z0.b, p7/m, z1.b, z31.b // CHECK-INST: msb z0.b, p7/m, z1.b, z31.b // CHECK-ENCODING: [0xe0,0xff,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 01 04 msb z0.h, p7/m, z1.h, z31.h // CHECK-INST: msb z0.h, p7/m, z1.h, z31.h // CHECK-ENCODING: [0xe0,0xff,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 41 04 msb z0.s, p7/m, z1.s, z31.s // CHECK-INST: msb z0.s, p7/m, z1.s, z31.s // CHECK-ENCODING: [0xe0,0xff,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 81 04 msb z0.d, p7/m, z1.d, z31.d // CHECK-INST: msb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff c1 04 @@ -40,23 +40,23 @@ msb z0.d, p7/m, z1.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 msb z0.d, p7/m, z1.d, z31.d // CHECK-INST: msb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff c1 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 msb z0.d, p7/m, z1.d, z31.d // CHECK-INST: msb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff c1 04 diff --git a/llvm/test/MC/AArch64/SVE/mul.s b/llvm/test/MC/AArch64/SVE/mul.s index 5016db43d6b05..77ee314c17701 100644 --- a/llvm/test/MC/AArch64/SVE/mul.s +++ b/llvm/test/MC/AArch64/SVE/mul.s @@ -12,73 +12,73 @@ mul z0.b, p7/m, z0.b, z31.b // CHECK-INST: mul z0.b, p7/m, z0.b, z31.b // CHECK-ENCODING: [0xe0,0x1f,0x10,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 10 04 mul z0.h, p7/m, z0.h, z31.h // CHECK-INST: mul z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x1f,0x50,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 50 04 mul z0.s, p7/m, z0.s, z31.s // CHECK-INST: mul z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 90 04 mul z0.d, p7/m, z0.d, z31.d // CHECK-INST: mul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d0 04 mul z31.b, z31.b, #-128 // CHECK-INST: mul z31.b, z31.b, #-128 // CHECK-ENCODING: [0x1f,0xd0,0x30,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f d0 30 25 mul z31.b, z31.b, #127 // CHECK-INST: mul z31.b, z31.b, #127 // CHECK-ENCODING: [0xff,0xcf,0x30,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 30 25 mul z31.h, z31.h, #-128 // CHECK-INST: mul z31.h, z31.h, #-128 // CHECK-ENCODING: [0x1f,0xd0,0x70,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f d0 70 25 mul z31.h, z31.h, #127 // CHECK-INST: mul z31.h, z31.h, #127 // CHECK-ENCODING: [0xff,0xcf,0x70,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 70 25 mul z31.s, z31.s, #-128 // CHECK-INST: mul z31.s, z31.s, #-128 // CHECK-ENCODING: [0x1f,0xd0,0xb0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f d0 b0 25 mul z31.s, z31.s, #127 // CHECK-INST: mul z31.s, z31.s, #127 // CHECK-ENCODING: [0xff,0xcf,0xb0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf b0 25 mul z31.d, z31.d, #-128 // CHECK-INST: mul z31.d, z31.d, #-128 // CHECK-ENCODING: [0x1f,0xd0,0xf0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f d0 f0 25 mul z31.d, z31.d, #127 // CHECK-INST: mul z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf f0 25 @@ -88,35 +88,35 @@ mul z31.d, z31.d, #127 movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 mul z0.d, p7/m, z0.d, z31.d // CHECK-INST: mul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mul z0.d, p7/m, z0.d, z31.d // CHECK-INST: mul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d0 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 mul z31.d, z31.d, #127 // CHECK-INST: mul z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf f0 25 diff --git a/llvm/test/MC/AArch64/SVE/nand.s b/llvm/test/MC/AArch64/SVE/nand.s index cc2831c7bf513..0e6cef662a6fe 100644 --- a/llvm/test/MC/AArch64/SVE/nand.s +++ b/llvm/test/MC/AArch64/SVE/nand.s @@ -12,11 +12,11 @@ nand p0.b, p0/z, p0.b, p0.b // CHECK-INST: nand p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x42,0x80,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 42 80 25 nand p15.b, p15/z, p15.b, p15.b // CHECK-INST: nand p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7f,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f 8f 25 diff --git a/llvm/test/MC/AArch64/SVE/nands.s b/llvm/test/MC/AArch64/SVE/nands.s index d5540e3d897ea..0b80f861ef980 100644 --- a/llvm/test/MC/AArch64/SVE/nands.s +++ b/llvm/test/MC/AArch64/SVE/nands.s @@ -12,11 +12,11 @@ nands p0.b, p0/z, p0.b, p0.b // CHECK-INST: nands p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x42,0xc0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 42 c0 25 nands p15.b, p15/z, p15.b, p15.b // CHECK-INST: nands p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7f,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f cf 25 diff --git a/llvm/test/MC/AArch64/SVE/neg.s b/llvm/test/MC/AArch64/SVE/neg.s index 11881e795f9b0..b69bb5d22d8ad 100644 --- a/llvm/test/MC/AArch64/SVE/neg.s +++ b/llvm/test/MC/AArch64/SVE/neg.s @@ -12,49 +12,49 @@ neg z0.b, p0/m, z0.b // CHECK-INST: neg z0.b, p0/m, z0.b // CHECK-ENCODING: [0x00,0xa0,0x17,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 17 04 neg z0.h, p0/m, z0.h // CHECK-INST: neg z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x57,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 57 04 neg z0.s, p0/m, z0.s // CHECK-INST: neg z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x97,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 97 04 neg z0.d, p0/m, z0.d // CHECK-INST: neg z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d7 04 neg z31.b, p7/m, z31.b // CHECK-INST: neg z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x17,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 17 04 neg z31.h, p7/m, z31.h // CHECK-INST: neg z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x57,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 57 04 neg z31.s, p7/m, z31.s // CHECK-INST: neg z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x97,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 97 04 neg z31.d, p7/m, z31.d // CHECK-INST: neg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d7 04 @@ -64,23 +64,23 @@ neg z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 neg z4.d, p7/m, z31.d // CHECK-INST: neg z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d7 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 neg z4.d, p7/m, z31.d // CHECK-INST: neg z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d7 04 diff --git a/llvm/test/MC/AArch64/SVE/nor.s b/llvm/test/MC/AArch64/SVE/nor.s index a78074c6c6c58..70d6a67c7b0e1 100644 --- a/llvm/test/MC/AArch64/SVE/nor.s +++ b/llvm/test/MC/AArch64/SVE/nor.s @@ -12,11 +12,11 @@ nor p0.b, p0/z, p0.b, p0.b // CHECK-INST: nor p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x00,0x42,0x80,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 80 25 nor p15.b, p15/z, p15.b, p15.b // CHECK-INST: nor p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7f,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f 8f 25 diff --git a/llvm/test/MC/AArch64/SVE/nors.s b/llvm/test/MC/AArch64/SVE/nors.s index 76492f2603b42..2551b30e77216 100644 --- a/llvm/test/MC/AArch64/SVE/nors.s +++ b/llvm/test/MC/AArch64/SVE/nors.s @@ -12,11 +12,11 @@ nors p0.b, p0/z, p0.b, p0.b // CHECK-INST: nors p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x00,0x42,0xc0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 c0 25 nors p15.b, p15/z, p15.b, p15.b // CHECK-INST: nors p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7f,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f cf 25 diff --git a/llvm/test/MC/AArch64/SVE/not.s b/llvm/test/MC/AArch64/SVE/not.s index b13eb6fdf58cb..0fc7b36881172 100644 --- a/llvm/test/MC/AArch64/SVE/not.s +++ b/llvm/test/MC/AArch64/SVE/not.s @@ -12,37 +12,37 @@ not z31.b, p7/m, z31.b // CHECK-INST: not z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x1e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 1e 04 not z31.h, p7/m, z31.h // CHECK-INST: not z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x5e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 5e 04 not z31.s, p7/m, z31.s // CHECK-INST: not z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x9e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 9e 04 not z31.d, p7/m, z31.d // CHECK-INST: not z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xde,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf de 04 not p0.b, p0/z, p0.b // CHECK-INST: not p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x42,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 00 25 not p15.b, p15/z, p15.b // CHECK-INST: not p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f 0f 25 @@ -52,23 +52,23 @@ not p15.b, p15/z, p15.b movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 not z4.d, p7/m, z31.d // CHECK-INST: not z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf de 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 not z4.d, p7/m, z31.d // CHECK-INST: not z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf de 04 diff --git a/llvm/test/MC/AArch64/SVE/nots.s b/llvm/test/MC/AArch64/SVE/nots.s index 2a3d32ccd33cd..4b6c79c36fa90 100644 --- a/llvm/test/MC/AArch64/SVE/nots.s +++ b/llvm/test/MC/AArch64/SVE/nots.s @@ -12,11 +12,11 @@ nots p0.b, p0/z, p0.b // CHECK-INST: nots p0.b, p0/z, p0.b // CHECK-ENCODING: [0x00,0x42,0x40,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 42 40 25 nots p15.b, p15/z, p15.b // CHECK-INST: nots p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x4f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7f 4f 25 diff --git a/llvm/test/MC/AArch64/SVE/orn.s b/llvm/test/MC/AArch64/SVE/orn.s index 1eb726e2c2070..ce1b9c9f6fcd8 100644 --- a/llvm/test/MC/AArch64/SVE/orn.s +++ b/llvm/test/MC/AArch64/SVE/orn.s @@ -12,61 +12,61 @@ orn z5.b, z5.b, #0xf9 // CHECK-INST: orr z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 00 05 orn z23.h, z23.h, #0xfff9 // CHECK-INST: orr z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 00 05 orn z0.s, z0.s, #0xfffffff9 // CHECK-INST: orr z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 00 05 orn z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: orr z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 03 05 orn z5.b, z5.b, #0x6 // CHECK-INST: orr z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 00 05 orn z23.h, z23.h, #0x6 // CHECK-INST: orr z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 00 05 orn z0.s, z0.s, #0x6 // CHECK-INST: orr z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 00 05 orn z0.d, z0.d, #0x6 // CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 03 05 orn p0.b, p0/z, p0.b, p0.b // CHECK-INST: orn p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0x80,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 80 25 orn p15.b, p15/z, p15.b, p15.b // CHECK-INST: orn p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7d 8f 25 @@ -76,11 +76,11 @@ orn p15.b, p15/z, p15.b, p15.b movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 orn z0.d, z0.d, #0x6 // CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 03 05 diff --git a/llvm/test/MC/AArch64/SVE/orns.s b/llvm/test/MC/AArch64/SVE/orns.s index f0806a95892ce..de8aa4a4b736a 100644 --- a/llvm/test/MC/AArch64/SVE/orns.s +++ b/llvm/test/MC/AArch64/SVE/orns.s @@ -12,11 +12,11 @@ orns p0.b, p0/z, p0.b, p0.b // CHECK-INST: orns p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0xc0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 40 c0 25 orns p15.b, p15/z, p15.b, p15.b // CHECK-INST: orns p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7d cf 25 diff --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s index 88d24b310daef..c848a34654be2 100644 --- a/llvm/test/MC/AArch64/SVE/orr.s +++ b/llvm/test/MC/AArch64/SVE/orr.s @@ -14,103 +14,103 @@ orr z5.b, z5.b, #0xf9 // CHECK-INST: orr z5.b, z5.b, #0xf9 // CHECK-ENCODING: [0xa5,0x2e,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a5 2e 00 05 orr z23.h, z23.h, #0xfff9 // CHECK-INST: orr z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 6d 00 05 orr z0.s, z0.s, #0xfffffff9 // CHECK-INST: orr z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 eb 00 05 orr z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 ef 03 05 orr z5.b, z5.b, #0x6 // CHECK-INST: orr z5.b, z5.b, #0x6 // CHECK-ENCODING: [0x25,0x3e,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 3e 00 05 orr z23.h, z23.h, #0x6 // CHECK-INST: orr z23.h, z23.h, #0x6 // CHECK-ENCODING: [0x37,0x7c,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 37 7c 00 05 orr z0.s, z0.s, #0x6 // CHECK-INST: orr z0.s, z0.s, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x00,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 00 05 orr z0.d, z0.d, #0x6 // CHECK-INST: orr z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 03 05 orr z0.d, z0.d, z0.d // should use mov-alias // CHECK-INST: mov z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 60 04 orr z23.d, z13.d, z8.d // should not use mov-alias // CHECK-INST: orr z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 68 04 orr z31.b, p7/m, z31.b, z31.b // CHECK-INST: orr z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x18,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 18 04 orr z31.h, p7/m, z31.h, z31.h // CHECK-INST: orr z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x58,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 58 04 orr z31.s, p7/m, z31.s, z31.s // CHECK-INST: orr z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 98 04 orr z31.d, p7/m, z31.d, z31.d // CHECK-INST: orr z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f d8 04 orr p0.b, p0/z, p0.b, p1.b // CHECK-INST: orr p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x40,0x81,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 81 25 orr p0.b, p0/z, p0.b, p0.b // CHECK-INST: mov p0.b, p0.b // CHECK-ENCODING: [0x00,0x40,0x80,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 80 25 orr p15.b, p15/z, p15.b, p15.b // CHECK-INST: mov p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d 8f 25 @@ -120,37 +120,37 @@ orr p15.b, p15/z, p15.b, p15.b orr z0.s, z0.s, z0.s // CHECK-INST: mov z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 60 04 orr z0.h, z0.h, z0.h // CHECK-INST: mov z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 60 04 orr z0.b, z0.b, z0.b // CHECK-INST: mov z0.d, z0.d // CHECK-ENCODING: [0x00,0x30,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 30 60 04 orr z23.s, z13.s, z8.s // should not use mov-alias // CHECK-INST: orr z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 68 04 orr z23.h, z13.h, z8.h // should not use mov-alias // CHECK-INST: orr z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 68 04 orr z23.b, z13.b, z8.b // should not use mov-alias // CHECK-INST: orr z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x31,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 31 68 04 @@ -160,35 +160,35 @@ orr z23.b, z13.b, z8.b // should not use mov-alias movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 orr z4.d, p7/m, z4.d, z31.d // CHECK-INST: orr z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f d8 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 orr z4.d, p7/m, z4.d, z31.d // CHECK-INST: orr z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f d8 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 orr z0.d, z0.d, #0x6 // CHECK-INST: orr z0.d, z0.d, #0x6 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 03 05 diff --git a/llvm/test/MC/AArch64/SVE/orrs.s b/llvm/test/MC/AArch64/SVE/orrs.s index 1faab3826d913..2c6a4881b384f 100644 --- a/llvm/test/MC/AArch64/SVE/orrs.s +++ b/llvm/test/MC/AArch64/SVE/orrs.s @@ -12,17 +12,17 @@ orrs p0.b, p0/z, p0.b, p1.b // CHECK-INST: orrs p0.b, p0/z, p0.b, p1.b // CHECK-ENCODING: [0x00,0x40,0xc1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c1 25 orrs p0.b, p0/z, p0.b, p0.b // CHECK-INST: movs p0.b, p0.b // CHECK-ENCODING: [0x00,0x40,0xc0,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 25 orrs p15.b, p15/z, p15.b, p15.b // CHECK-INST: movs p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0xcf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 7d cf 25 diff --git a/llvm/test/MC/AArch64/SVE/orv.s b/llvm/test/MC/AArch64/SVE/orv.s index 3f07878d8de07..fefdf238d3757 100644 --- a/llvm/test/MC/AArch64/SVE/orv.s +++ b/llvm/test/MC/AArch64/SVE/orv.s @@ -12,23 +12,23 @@ orv b0, p7, z31.b // CHECK-INST: orv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x18,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 18 04 orv h0, p7, z31.h // CHECK-INST: orv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x58,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 58 04 orv s0, p7, z31.s // CHECK-INST: orv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x98,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 98 04 orv d0, p7, z31.d // CHECK-INST: orv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xd8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f d8 04 diff --git a/llvm/test/MC/AArch64/SVE/pfalse.s b/llvm/test/MC/AArch64/SVE/pfalse.s index 3eb4488cb8208..d87b12344561a 100644 --- a/llvm/test/MC/AArch64/SVE/pfalse.s +++ b/llvm/test/MC/AArch64/SVE/pfalse.s @@ -12,5 +12,5 @@ pfalse p15.b // CHECK-INST: pfalse p15.b // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f e4 18 25 diff --git a/llvm/test/MC/AArch64/SVE/pfirst.s b/llvm/test/MC/AArch64/SVE/pfirst.s index 2bf001d37a284..89db229d52663 100644 --- a/llvm/test/MC/AArch64/SVE/pfirst.s +++ b/llvm/test/MC/AArch64/SVE/pfirst.s @@ -12,11 +12,11 @@ pfirst p0.b, p15, p0.b // CHECK-INST: pfirst p0.b, p15, p0.b // CHECK-ENCODING: [0xe0,0xc1,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c1 58 25 pfirst p15.b, p15, p15.b // CHECK-INST: pfirst p15.b, p15, p15.b // CHECK-ENCODING: [0xef,0xc1,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef c1 58 25 diff --git a/llvm/test/MC/AArch64/SVE/pnext.s b/llvm/test/MC/AArch64/SVE/pnext.s index 26f524959695d..74e9830c991d1 100644 --- a/llvm/test/MC/AArch64/SVE/pnext.s +++ b/llvm/test/MC/AArch64/SVE/pnext.s @@ -12,29 +12,29 @@ pnext p15.b, p15, p15.b // CHECK-INST: pnext p15.b, p15, p15.b // CHECK-ENCODING: [0xef,0xc5,0x19,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef c5 19 25 pnext p0.b, p15, p0.b // CHECK-INST: pnext p0.b, p15, p0.b // CHECK-ENCODING: [0xe0,0xc5,0x19,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 19 25 pnext p0.h, p15, p0.h // CHECK-INST: pnext p0.h, p15, p0.h // CHECK-ENCODING: [0xe0,0xc5,0x59,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 59 25 pnext p0.s, p15, p0.s // CHECK-INST: pnext p0.s, p15, p0.s // CHECK-ENCODING: [0xe0,0xc5,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 99 25 pnext p0.d, p15, p0.d // CHECK-INST: pnext p0.d, p15, p0.d // CHECK-ENCODING: [0xe0,0xc5,0xd9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c5 d9 25 diff --git a/llvm/test/MC/AArch64/SVE/prfb.s b/llvm/test/MC/AArch64/SVE/prfb.s index 9f4e78f01237d..ea7e43b963f76 100644 --- a/llvm/test/MC/AArch64/SVE/prfb.s +++ b/llvm/test/MC/AArch64/SVE/prfb.s @@ -15,169 +15,169 @@ prfb #0, p0, [x0] // CHECK-INST: prfb pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c0 85 prfb pldl1keep, p0, [x0] // CHECK-INST: prfb pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c0 85 prfb #1, p0, [x0] // CHECK-INST: prfb pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 00 c0 85 prfb pldl1strm, p0, [x0] // CHECK-INST: prfb pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 00 c0 85 prfb #2, p0, [x0] // CHECK-INST: prfb pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 00 c0 85 prfb pldl2keep, p0, [x0] // CHECK-INST: prfb pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 00 c0 85 prfb #3, p0, [x0] // CHECK-INST: prfb pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 00 c0 85 prfb pldl2strm, p0, [x0] // CHECK-INST: prfb pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 00 c0 85 prfb #4, p0, [x0] // CHECK-INST: prfb pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 00 c0 85 prfb pldl3keep, p0, [x0] // CHECK-INST: prfb pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 00 c0 85 prfb #5, p0, [x0] // CHECK-INST: prfb pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 00 c0 85 prfb pldl3strm, p0, [x0] // CHECK-INST: prfb pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 00 c0 85 prfb #6, p0, [x0] // CHECK-INST: prfb #6, p0, [x0] // CHECK-ENCODING: [0x06,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 06 00 c0 85 prfb #7, p0, [x0] // CHECK-INST: prfb #7, p0, [x0] // CHECK-ENCODING: [0x07,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 00 c0 85 prfb #8, p0, [x0] // CHECK-INST: prfb pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 00 c0 85 prfb pstl1keep, p0, [x0] // CHECK-INST: prfb pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 00 c0 85 prfb #9, p0, [x0] // CHECK-INST: prfb pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 00 c0 85 prfb pstl1strm, p0, [x0] // CHECK-INST: prfb pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 00 c0 85 prfb #10, p0, [x0] // CHECK-INST: prfb pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 00 c0 85 prfb pstl2keep, p0, [x0] // CHECK-INST: prfb pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 00 c0 85 prfb #11, p0, [x0] // CHECK-INST: prfb pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 00 c0 85 prfb pstl2strm, p0, [x0] // CHECK-INST: prfb pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 00 c0 85 prfb #12, p0, [x0] // CHECK-INST: prfb pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 00 c0 85 prfb pstl3keep, p0, [x0] // CHECK-INST: prfb pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 00 c0 85 prfb #13, p0, [x0] // CHECK-INST: prfb pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 00 c0 85 prfb pstl3strm, p0, [x0] // CHECK-INST: prfb pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 00 c0 85 prfb #14, p0, [x0] // CHECK-INST: prfb #14, p0, [x0] // CHECK-ENCODING: [0x0e,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0e 00 c0 85 prfb #15, p0, [x0] // CHECK-INST: prfb #15, p0, [x0] // CHECK-ENCODING: [0x0f,0x00,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 00 c0 85 // --------------------------------------------------------------------------// @@ -186,11 +186,11 @@ prfb #15, p0, [x0] prfb #1, p0, [x0, #-32, mul vl] // CHECK-INST: prfb pldl1strm, p0, [x0, #-32, mul vl] // CHECK-ENCODING: [0x01,0x00,0xe0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 00 e0 85 prfb #1, p0, [x0, #31, mul vl] // CHECK-INST: prfb pldl1strm, p0, [x0, #31, mul vl] // CHECK-ENCODING: [0x01,0x00,0xdf,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 00 df 85 diff --git a/llvm/test/MC/AArch64/SVE/prfd.s b/llvm/test/MC/AArch64/SVE/prfd.s index 579fcb082629f..df2dfb5825f2b 100644 --- a/llvm/test/MC/AArch64/SVE/prfd.s +++ b/llvm/test/MC/AArch64/SVE/prfd.s @@ -15,169 +15,169 @@ prfd #0, p0, [x0] // CHECK-INST: prfd pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 c0 85 prfd pldl1keep, p0, [x0] // CHECK-INST: prfd pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 c0 85 prfd #1, p0, [x0] // CHECK-INST: prfd pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 60 c0 85 prfd pldl1strm, p0, [x0] // CHECK-INST: prfd pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 60 c0 85 prfd #2, p0, [x0] // CHECK-INST: prfd pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 60 c0 85 prfd pldl2keep, p0, [x0] // CHECK-INST: prfd pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 60 c0 85 prfd #3, p0, [x0] // CHECK-INST: prfd pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 60 c0 85 prfd pldl2strm, p0, [x0] // CHECK-INST: prfd pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 60 c0 85 prfd #4, p0, [x0] // CHECK-INST: prfd pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 60 c0 85 prfd pldl3keep, p0, [x0] // CHECK-INST: prfd pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 60 c0 85 prfd #5, p0, [x0] // CHECK-INST: prfd pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 60 c0 85 prfd pldl3strm, p0, [x0] // CHECK-INST: prfd pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 60 c0 85 prfd #6, p0, [x0] // CHECK-INST: prfd #6, p0, [x0] // CHECK-ENCODING: [0x06,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 06 60 c0 85 prfd #7, p0, [x0] // CHECK-INST: prfd #7, p0, [x0] // CHECK-ENCODING: [0x07,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 60 c0 85 prfd #8, p0, [x0] // CHECK-INST: prfd pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 60 c0 85 prfd pstl1keep, p0, [x0] // CHECK-INST: prfd pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 60 c0 85 prfd #9, p0, [x0] // CHECK-INST: prfd pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 60 c0 85 prfd pstl1strm, p0, [x0] // CHECK-INST: prfd pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 60 c0 85 prfd #10, p0, [x0] // CHECK-INST: prfd pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 60 c0 85 prfd pstl2keep, p0, [x0] // CHECK-INST: prfd pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 60 c0 85 prfd #11, p0, [x0] // CHECK-INST: prfd pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 60 c0 85 prfd pstl2strm, p0, [x0] // CHECK-INST: prfd pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 60 c0 85 prfd #12, p0, [x0] // CHECK-INST: prfd pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 60 c0 85 prfd pstl3keep, p0, [x0] // CHECK-INST: prfd pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 60 c0 85 prfd #13, p0, [x0] // CHECK-INST: prfd pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 60 c0 85 prfd pstl3strm, p0, [x0] // CHECK-INST: prfd pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 60 c0 85 prfd #14, p0, [x0] // CHECK-INST: prfd #14, p0, [x0] // CHECK-ENCODING: [0x0e,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0e 60 c0 85 prfd #15, p0, [x0] // CHECK-INST: prfd #15, p0, [x0] // CHECK-ENCODING: [0x0f,0x60,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 60 c0 85 // --------------------------------------------------------------------------// @@ -186,11 +186,11 @@ prfd #15, p0, [x0] prfd pldl1strm, p0, [x0, #-32, mul vl] // CHECK-INST: prfd pldl1strm, p0, [x0, #-32, mul vl] // CHECK-ENCODING: [0x01,0x60,0xe0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 60 e0 85 prfd pldl1strm, p0, [x0, #31, mul vl] // CHECK-INST: prfd pldl1strm, p0, [x0, #31, mul vl] // CHECK-ENCODING: [0x01,0x60,0xdf,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 60 df 85 diff --git a/llvm/test/MC/AArch64/SVE/prfh.s b/llvm/test/MC/AArch64/SVE/prfh.s index ddefe7797a891..211de5096eaf3 100644 --- a/llvm/test/MC/AArch64/SVE/prfh.s +++ b/llvm/test/MC/AArch64/SVE/prfh.s @@ -15,169 +15,169 @@ prfh #0, p0, [x0] // CHECK-INST: prfh pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 c0 85 prfh pldl1keep, p0, [x0] // CHECK-INST: prfh pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 20 c0 85 prfh #1, p0, [x0] // CHECK-INST: prfh pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 20 c0 85 prfh pldl1strm, p0, [x0] // CHECK-INST: prfh pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 20 c0 85 prfh #2, p0, [x0] // CHECK-INST: prfh pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 20 c0 85 prfh pldl2keep, p0, [x0] // CHECK-INST: prfh pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 20 c0 85 prfh #3, p0, [x0] // CHECK-INST: prfh pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 20 c0 85 prfh pldl2strm, p0, [x0] // CHECK-INST: prfh pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 20 c0 85 prfh #4, p0, [x0] // CHECK-INST: prfh pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 20 c0 85 prfh pldl3keep, p0, [x0] // CHECK-INST: prfh pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 20 c0 85 prfh #5, p0, [x0] // CHECK-INST: prfh pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 20 c0 85 prfh pldl3strm, p0, [x0] // CHECK-INST: prfh pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 20 c0 85 prfh #6, p0, [x0] // CHECK-INST: prfh #6, p0, [x0] // CHECK-ENCODING: [0x06,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 06 20 c0 85 prfh #7, p0, [x0] // CHECK-INST: prfh #7, p0, [x0] // CHECK-ENCODING: [0x07,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 20 c0 85 prfh #8, p0, [x0] // CHECK-INST: prfh pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 20 c0 85 prfh pstl1keep, p0, [x0] // CHECK-INST: prfh pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 20 c0 85 prfh #9, p0, [x0] // CHECK-INST: prfh pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 20 c0 85 prfh pstl1strm, p0, [x0] // CHECK-INST: prfh pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 20 c0 85 prfh #10, p0, [x0] // CHECK-INST: prfh pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 20 c0 85 prfh pstl2keep, p0, [x0] // CHECK-INST: prfh pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 20 c0 85 prfh #11, p0, [x0] // CHECK-INST: prfh pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 20 c0 85 prfh pstl2strm, p0, [x0] // CHECK-INST: prfh pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 20 c0 85 prfh #12, p0, [x0] // CHECK-INST: prfh pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 20 c0 85 prfh pstl3keep, p0, [x0] // CHECK-INST: prfh pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 20 c0 85 prfh #13, p0, [x0] // CHECK-INST: prfh pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 20 c0 85 prfh pstl3strm, p0, [x0] // CHECK-INST: prfh pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 20 c0 85 prfh #14, p0, [x0] // CHECK-INST: prfh #14, p0, [x0] // CHECK-ENCODING: [0x0e,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0e 20 c0 85 prfh #15, p0, [x0] // CHECK-INST: prfh #15, p0, [x0] // CHECK-ENCODING: [0x0f,0x20,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 20 c0 85 // --------------------------------------------------------------------------// @@ -186,11 +186,11 @@ prfh #15, p0, [x0] prfh pldl1strm, p0, [x0, #-32, mul vl] // CHECK-INST: prfh pldl1strm, p0, [x0, #-32, mul vl] // CHECK-ENCODING: [0x01,0x20,0xe0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 20 e0 85 prfh pldl1strm, p0, [x0, #31, mul vl] // CHECK-INST: prfh pldl1strm, p0, [x0, #31, mul vl] // CHECK-ENCODING: [0x01,0x20,0xdf,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 20 df 85 diff --git a/llvm/test/MC/AArch64/SVE/prfw.s b/llvm/test/MC/AArch64/SVE/prfw.s index 2805dd0f3d177..46d1ee2dc7910 100644 --- a/llvm/test/MC/AArch64/SVE/prfw.s +++ b/llvm/test/MC/AArch64/SVE/prfw.s @@ -15,169 +15,169 @@ prfw #0, p0, [x0] // CHECK-INST: prfw pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 85 prfw pldl1keep, p0, [x0] // CHECK-INST: prfw pldl1keep, p0, [x0] // CHECK-ENCODING: [0x00,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 85 prfw #1, p0, [x0] // CHECK-INST: prfw pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 40 c0 85 prfw pldl1strm, p0, [x0] // CHECK-INST: prfw pldl1strm, p0, [x0] // CHECK-ENCODING: [0x01,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 40 c0 85 prfw #2, p0, [x0] // CHECK-INST: prfw pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 40 c0 85 prfw pldl2keep, p0, [x0] // CHECK-INST: prfw pldl2keep, p0, [x0] // CHECK-ENCODING: [0x02,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 02 40 c0 85 prfw #3, p0, [x0] // CHECK-INST: prfw pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 40 c0 85 prfw pldl2strm, p0, [x0] // CHECK-INST: prfw pldl2strm, p0, [x0] // CHECK-ENCODING: [0x03,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 03 40 c0 85 prfw #4, p0, [x0] // CHECK-INST: prfw pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 40 c0 85 prfw pldl3keep, p0, [x0] // CHECK-INST: prfw pldl3keep, p0, [x0] // CHECK-ENCODING: [0x04,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 04 40 c0 85 prfw #5, p0, [x0] // CHECK-INST: prfw pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 40 c0 85 prfw pldl3strm, p0, [x0] // CHECK-INST: prfw pldl3strm, p0, [x0] // CHECK-ENCODING: [0x05,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 40 c0 85 prfw #6, p0, [x0] // CHECK-INST: prfw #6, p0, [x0] // CHECK-ENCODING: [0x06,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 06 40 c0 85 prfw #7, p0, [x0] // CHECK-INST: prfw #7, p0, [x0] // CHECK-ENCODING: [0x07,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 40 c0 85 prfw #8, p0, [x0] // CHECK-INST: prfw pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 40 c0 85 prfw pstl1keep, p0, [x0] // CHECK-INST: prfw pstl1keep, p0, [x0] // CHECK-ENCODING: [0x08,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 08 40 c0 85 prfw #9, p0, [x0] // CHECK-INST: prfw pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 40 c0 85 prfw pstl1strm, p0, [x0] // CHECK-INST: prfw pstl1strm, p0, [x0] // CHECK-ENCODING: [0x09,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 09 40 c0 85 prfw #10, p0, [x0] // CHECK-INST: prfw pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 40 c0 85 prfw pstl2keep, p0, [x0] // CHECK-INST: prfw pstl2keep, p0, [x0] // CHECK-ENCODING: [0x0a,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0a 40 c0 85 prfw #11, p0, [x0] // CHECK-INST: prfw pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 40 c0 85 prfw pstl2strm, p0, [x0] // CHECK-INST: prfw pstl2strm, p0, [x0] // CHECK-ENCODING: [0x0b,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0b 40 c0 85 prfw #12, p0, [x0] // CHECK-INST: prfw pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 40 c0 85 prfw pstl3keep, p0, [x0] // CHECK-INST: prfw pstl3keep, p0, [x0] // CHECK-ENCODING: [0x0c,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0c 40 c0 85 prfw #13, p0, [x0] // CHECK-INST: prfw pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 40 c0 85 prfw pstl3strm, p0, [x0] // CHECK-INST: prfw pstl3strm, p0, [x0] // CHECK-ENCODING: [0x0d,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0d 40 c0 85 prfw #14, p0, [x0] // CHECK-INST: prfw #14, p0, [x0] // CHECK-ENCODING: [0x0e,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0e 40 c0 85 prfw #15, p0, [x0] // CHECK-INST: prfw #15, p0, [x0] // CHECK-ENCODING: [0x0f,0x40,0xc0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 40 c0 85 // --------------------------------------------------------------------------// @@ -186,11 +186,11 @@ prfw #15, p0, [x0] prfw pldl1strm, p0, [x0, #-32, mul vl] // CHECK-INST: prfw pldl1strm, p0, [x0, #-32, mul vl] // CHECK-ENCODING: [0x01,0x40,0xe0,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 40 e0 85 prfw pldl1strm, p0, [x0, #31, mul vl] // CHECK-INST: prfw pldl1strm, p0, [x0, #31, mul vl] // CHECK-ENCODING: [0x01,0x40,0xdf,0x85] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 01 40 df 85 diff --git a/llvm/test/MC/AArch64/SVE/ptest.s b/llvm/test/MC/AArch64/SVE/ptest.s index 449f89dae79f7..42ed050848dc2 100644 --- a/llvm/test/MC/AArch64/SVE/ptest.s +++ b/llvm/test/MC/AArch64/SVE/ptest.s @@ -12,11 +12,11 @@ ptest p15, p0.b // CHECK-INST: ptest p15, p0.b // CHECK-ENCODING: [0x00,0xfc,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 50 25 ptest p15, p15.b // CHECK-INST: ptest p15, p15.b // CHECK-ENCODING: [0xe0,0xfd,0x50,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fd 50 25 diff --git a/llvm/test/MC/AArch64/SVE/ptrue.s b/llvm/test/MC/AArch64/SVE/ptrue.s index a9118b0901ab6..f230b1feec6d8 100644 --- a/llvm/test/MC/AArch64/SVE/ptrue.s +++ b/llvm/test/MC/AArch64/SVE/ptrue.s @@ -16,25 +16,25 @@ ptrue p0.b, pow2 // CHECK-INST: ptrue p0.b, pow2 // CHECK-ENCODING: [0x00,0xe0,0x18,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 18 25 ptrue p0.h, pow2 // CHECK-INST: ptrue p0.h, pow2 // CHECK-ENCODING: [0x00,0xe0,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 58 25 ptrue p0.s, pow2 // CHECK-INST: ptrue p0.s, pow2 // CHECK-ENCODING: [0x00,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 98 25 ptrue p0.d, pow2 // CHECK-INST: ptrue p0.d, pow2 // CHECK-ENCODING: [0x00,0xe0,0xd8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 d8 25 // ---------------------------------------------------------------------------// @@ -44,25 +44,25 @@ ptrue p0.d, pow2 ptrue p15.b // CHECK-INST: ptrue p15.b // CHECK-ENCODING: [0xef,0xe3,0x18,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 18 25 ptrue p15.h // CHECK-INST: ptrue p15.h // CHECK-ENCODING: [0xef,0xe3,0x58,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 58 25 ptrue p15.s // CHECK-INST: ptrue p15.s // CHECK-ENCODING: [0xef,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 98 25 ptrue p15.d // CHECK-INST: ptrue p15.d // CHECK-ENCODING: [0xef,0xe3,0xd8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 d8 25 // ---------------------------------------------------------------------------// @@ -72,103 +72,103 @@ ptrue p15.d ptrue p7.s, #1 // CHECK-INST: ptrue p7.s, vl1 // CHECK-ENCODING: [0x27,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e0 98 25 ptrue p7.s, vl1 // CHECK-INST: ptrue p7.s, vl1 // CHECK-ENCODING: [0x27,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e0 98 25 ptrue p7.s, vl2 // CHECK-INST: ptrue p7.s, vl2 // CHECK-ENCODING: [0x47,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e0 98 25 ptrue p7.s, vl3 // CHECK-INST: ptrue p7.s, vl3 // CHECK-ENCODING: [0x67,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e0 98 25 ptrue p7.s, vl4 // CHECK-INST: ptrue p7.s, vl4 // CHECK-ENCODING: [0x87,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e0 98 25 ptrue p7.s, vl5 // CHECK-INST: ptrue p7.s, vl5 // CHECK-ENCODING: [0xa7,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e0 98 25 ptrue p7.s, vl6 // CHECK-INST: ptrue p7.s, vl6 // CHECK-ENCODING: [0xc7,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e0 98 25 ptrue p7.s, vl7 // CHECK-INST: ptrue p7.s, vl7 // CHECK-ENCODING: [0xe7,0xe0,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e0 98 25 ptrue p7.s, vl8 // CHECK-INST: ptrue p7.s, vl8 // CHECK-ENCODING: [0x07,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e1 98 25 ptrue p7.s, vl16 // CHECK-INST: ptrue p7.s, vl16 // CHECK-ENCODING: [0x27,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e1 98 25 ptrue p7.s, vl32 // CHECK-INST: ptrue p7.s, vl32 // CHECK-ENCODING: [0x47,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e1 98 25 ptrue p7.s, vl64 // CHECK-INST: ptrue p7.s, vl64 // CHECK-ENCODING: [0x67,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e1 98 25 ptrue p7.s, vl128 // CHECK-INST: ptrue p7.s, vl128 // CHECK-ENCODING: [0x87,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e1 98 25 ptrue p7.s, vl256 // CHECK-INST: ptrue p7.s, vl256 // CHECK-ENCODING: [0xa7,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e1 98 25 ptrue p7.s, mul4 // CHECK-INST: ptrue p7.s, mul4 // CHECK-ENCODING: [0xa7,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e3 98 25 ptrue p7.s, mul3 // CHECK-INST: ptrue p7.s, mul3 // CHECK-ENCODING: [0xc7,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e3 98 25 ptrue p7.s, all // CHECK-INST: ptrue p7.s // CHECK-ENCODING: [0xe7,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e3 98 25 // ---------------------------------------------------------------------------// @@ -178,89 +178,89 @@ ptrue p7.s, all ptrue p7.s, #14 // CHECK-INST: ptrue p7.s, #14 // CHECK-ENCODING: [0xc7,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e1 98 25 ptrue p7.s, #15 // CHECK-INST: ptrue p7.s, #15 // CHECK-ENCODING: [0xe7,0xe1,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e1 98 25 ptrue p7.s, #16 // CHECK-INST: ptrue p7.s, #16 // CHECK-ENCODING: [0x07,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e2 98 25 ptrue p7.s, #17 // CHECK-INST: ptrue p7.s, #17 // CHECK-ENCODING: [0x27,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e2 98 25 ptrue p7.s, #18 // CHECK-INST: ptrue p7.s, #18 // CHECK-ENCODING: [0x47,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e2 98 25 ptrue p7.s, #19 // CHECK-INST: ptrue p7.s, #19 // CHECK-ENCODING: [0x67,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e2 98 25 ptrue p7.s, #20 // CHECK-INST: ptrue p7.s, #20 // CHECK-ENCODING: [0x87,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e2 98 25 ptrue p7.s, #21 // CHECK-INST: ptrue p7.s, #21 // CHECK-ENCODING: [0xa7,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e2 98 25 ptrue p7.s, #22 // CHECK-INST: ptrue p7.s, #22 // CHECK-ENCODING: [0xc7,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e2 98 25 ptrue p7.s, #23 // CHECK-INST: ptrue p7.s, #23 // CHECK-ENCODING: [0xe7,0xe2,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e2 98 25 ptrue p7.s, #24 // CHECK-INST: ptrue p7.s, #24 // CHECK-ENCODING: [0x07,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e3 98 25 ptrue p7.s, #25 // CHECK-INST: ptrue p7.s, #25 // CHECK-ENCODING: [0x27,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e3 98 25 ptrue p7.s, #26 // CHECK-INST: ptrue p7.s, #26 // CHECK-ENCODING: [0x47,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e3 98 25 ptrue p7.s, #27 // CHECK-INST: ptrue p7.s, #27 // CHECK-ENCODING: [0x67,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e3 98 25 ptrue p7.s, #28 // CHECK-INST: ptrue p7.s, #28 // CHECK-ENCODING: [0x87,0xe3,0x98,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e3 98 25 diff --git a/llvm/test/MC/AArch64/SVE/ptrues.s b/llvm/test/MC/AArch64/SVE/ptrues.s index f9fcb5d70a103..b8cff9e678cc5 100644 --- a/llvm/test/MC/AArch64/SVE/ptrues.s +++ b/llvm/test/MC/AArch64/SVE/ptrues.s @@ -16,25 +16,25 @@ ptrues p0.b, pow2 // CHECK-INST: ptrues p0.b, pow2 // CHECK-ENCODING: [0x00,0xe0,0x19,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 19 25 ptrues p0.h, pow2 // CHECK-INST: ptrues p0.h, pow2 // CHECK-ENCODING: [0x00,0xe0,0x59,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 59 25 ptrues p0.s, pow2 // CHECK-INST: ptrues p0.s, pow2 // CHECK-ENCODING: [0x00,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 99 25 ptrues p0.d, pow2 // CHECK-INST: ptrues p0.d, pow2 // CHECK-ENCODING: [0x00,0xe0,0xd9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 d9 25 // ---------------------------------------------------------------------------// @@ -44,25 +44,25 @@ ptrues p0.d, pow2 ptrues p15.b // CHECK-INST: ptrues p15.b // CHECK-ENCODING: [0xef,0xe3,0x19,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 19 25 ptrues p15.h // CHECK-INST: ptrues p15.h // CHECK-ENCODING: [0xef,0xe3,0x59,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 59 25 ptrues p15.s // CHECK-INST: ptrues p15.s // CHECK-ENCODING: [0xef,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 99 25 ptrues p15.d // CHECK-INST: ptrues p15.d // CHECK-ENCODING: [0xef,0xe3,0xd9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef e3 d9 25 // ---------------------------------------------------------------------------// @@ -72,103 +72,103 @@ ptrues p15.d ptrues p7.s, #1 // CHECK-INST: ptrues p7.s, vl1 // CHECK-ENCODING: [0x27,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e0 99 25 ptrues p7.s, vl1 // CHECK-INST: ptrues p7.s, vl1 // CHECK-ENCODING: [0x27,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e0 99 25 ptrues p7.s, vl2 // CHECK-INST: ptrues p7.s, vl2 // CHECK-ENCODING: [0x47,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e0 99 25 ptrues p7.s, vl3 // CHECK-INST: ptrues p7.s, vl3 // CHECK-ENCODING: [0x67,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e0 99 25 ptrues p7.s, vl4 // CHECK-INST: ptrues p7.s, vl4 // CHECK-ENCODING: [0x87,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e0 99 25 ptrues p7.s, vl5 // CHECK-INST: ptrues p7.s, vl5 // CHECK-ENCODING: [0xa7,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e0 99 25 ptrues p7.s, vl6 // CHECK-INST: ptrues p7.s, vl6 // CHECK-ENCODING: [0xc7,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e0 99 25 ptrues p7.s, vl7 // CHECK-INST: ptrues p7.s, vl7 // CHECK-ENCODING: [0xe7,0xe0,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e0 99 25 ptrues p7.s, vl8 // CHECK-INST: ptrues p7.s, vl8 // CHECK-ENCODING: [0x07,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e1 99 25 ptrues p7.s, vl16 // CHECK-INST: ptrues p7.s, vl16 // CHECK-ENCODING: [0x27,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e1 99 25 ptrues p7.s, vl32 // CHECK-INST: ptrues p7.s, vl32 // CHECK-ENCODING: [0x47,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e1 99 25 ptrues p7.s, vl64 // CHECK-INST: ptrues p7.s, vl64 // CHECK-ENCODING: [0x67,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e1 99 25 ptrues p7.s, vl128 // CHECK-INST: ptrues p7.s, vl128 // CHECK-ENCODING: [0x87,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e1 99 25 ptrues p7.s, vl256 // CHECK-INST: ptrues p7.s, vl256 // CHECK-ENCODING: [0xa7,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e1 99 25 ptrues p7.s, mul4 // CHECK-INST: ptrues p7.s, mul4 // CHECK-ENCODING: [0xa7,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e3 99 25 ptrues p7.s, mul3 // CHECK-INST: ptrues p7.s, mul3 // CHECK-ENCODING: [0xc7,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e3 99 25 ptrues p7.s, all // CHECK-INST: ptrues p7.s // CHECK-ENCODING: [0xe7,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e3 99 25 // ---------------------------------------------------------------------------// @@ -178,89 +178,89 @@ ptrues p7.s, all ptrues p7.s, #14 // CHECK-INST: ptrues p7.s, #14 // CHECK-ENCODING: [0xc7,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e1 99 25 ptrues p7.s, #15 // CHECK-INST: ptrues p7.s, #15 // CHECK-ENCODING: [0xe7,0xe1,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e1 99 25 ptrues p7.s, #16 // CHECK-INST: ptrues p7.s, #16 // CHECK-ENCODING: [0x07,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e2 99 25 ptrues p7.s, #17 // CHECK-INST: ptrues p7.s, #17 // CHECK-ENCODING: [0x27,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e2 99 25 ptrues p7.s, #18 // CHECK-INST: ptrues p7.s, #18 // CHECK-ENCODING: [0x47,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e2 99 25 ptrues p7.s, #19 // CHECK-INST: ptrues p7.s, #19 // CHECK-ENCODING: [0x67,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e2 99 25 ptrues p7.s, #20 // CHECK-INST: ptrues p7.s, #20 // CHECK-ENCODING: [0x87,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e2 99 25 ptrues p7.s, #21 // CHECK-INST: ptrues p7.s, #21 // CHECK-ENCODING: [0xa7,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a7 e2 99 25 ptrues p7.s, #22 // CHECK-INST: ptrues p7.s, #22 // CHECK-ENCODING: [0xc7,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c7 e2 99 25 ptrues p7.s, #23 // CHECK-INST: ptrues p7.s, #23 // CHECK-ENCODING: [0xe7,0xe2,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e7 e2 99 25 ptrues p7.s, #24 // CHECK-INST: ptrues p7.s, #24 // CHECK-ENCODING: [0x07,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 07 e3 99 25 ptrues p7.s, #25 // CHECK-INST: ptrues p7.s, #25 // CHECK-ENCODING: [0x27,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 27 e3 99 25 ptrues p7.s, #26 // CHECK-INST: ptrues p7.s, #26 // CHECK-ENCODING: [0x47,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 47 e3 99 25 ptrues p7.s, #27 // CHECK-INST: ptrues p7.s, #27 // CHECK-ENCODING: [0x67,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 67 e3 99 25 ptrues p7.s, #28 // CHECK-INST: ptrues p7.s, #28 // CHECK-ENCODING: [0x87,0xe3,0x99,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 87 e3 99 25 diff --git a/llvm/test/MC/AArch64/SVE/punpkhi.s b/llvm/test/MC/AArch64/SVE/punpkhi.s index 0c27f30c49749..9a368b87c2e96 100644 --- a/llvm/test/MC/AArch64/SVE/punpkhi.s +++ b/llvm/test/MC/AArch64/SVE/punpkhi.s @@ -12,11 +12,11 @@ punpkhi p0.h, p0.b // CHECK-INST: punpkhi p0.h, p0.b // CHECK-ENCODING: [0x00,0x40,0x31,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 31 05 punpkhi p15.h, p15.b // CHECK-INST: punpkhi p15.h, p15.b // CHECK-ENCODING: [0xef,0x41,0x31,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 31 05 diff --git a/llvm/test/MC/AArch64/SVE/punpklo.s b/llvm/test/MC/AArch64/SVE/punpklo.s index 3a9f076ed7dac..8ca8bb2f75678 100644 --- a/llvm/test/MC/AArch64/SVE/punpklo.s +++ b/llvm/test/MC/AArch64/SVE/punpklo.s @@ -12,11 +12,11 @@ punpklo p0.h, p0.b // CHECK-INST: punpklo p0.h, p0.b // CHECK-ENCODING: [0x00,0x40,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 30 05 punpklo p15.h, p15.b // CHECK-INST: punpklo p15.h, p15.b // CHECK-ENCODING: [0xef,0x41,0x30,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 30 05 diff --git a/llvm/test/MC/AArch64/SVE/rbit.s b/llvm/test/MC/AArch64/SVE/rbit.s index 70e2036727486..ac299bf1cbe08 100644 --- a/llvm/test/MC/AArch64/SVE/rbit.s +++ b/llvm/test/MC/AArch64/SVE/rbit.s @@ -12,25 +12,25 @@ rbit z0.b, p7/m, z31.b // CHECK-INST: rbit z0.b, p7/m, z31.b // CHECK-ENCODING: [0xe0,0x9f,0x27,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 27 05 rbit z0.h, p7/m, z31.h // CHECK-INST: rbit z0.h, p7/m, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x67,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 67 05 rbit z0.s, p7/m, z31.s // CHECK-INST: rbit z0.s, p7/m, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a7 05 rbit z0.d, p7/m, z31.d // CHECK-INST: rbit z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e7 05 @@ -40,23 +40,23 @@ rbit z0.d, p7/m, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 rbit z0.d, p7/m, z31.d // CHECK-INST: rbit z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e7 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 rbit z0.d, p7/m, z31.d // CHECK-INST: rbit z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e7 05 diff --git a/llvm/test/MC/AArch64/SVE/rdvl.s b/llvm/test/MC/AArch64/SVE/rdvl.s index 5cf8c368e9077..50877f5c7342d 100644 --- a/llvm/test/MC/AArch64/SVE/rdvl.s +++ b/llvm/test/MC/AArch64/SVE/rdvl.s @@ -12,23 +12,23 @@ rdvl x0, #0 // CHECK-INST: rdvl x0, #0 // CHECK-ENCODING: [0x00,0x50,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 50 bf 04 rdvl xzr, #-1 // CHECK-INST: rdvl xzr, #-1 // CHECK-ENCODING: [0xff,0x57,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 57 bf 04 rdvl x23, #31 // CHECK-INST: rdvl x23, #31 // CHECK-ENCODING: [0xf7,0x53,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: f7 53 bf 04 rdvl x21, #-32 // CHECK-INST: rdvl x21, #-32 // CHECK-ENCODING: [0x15,0x54,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 15 54 bf 04 diff --git a/llvm/test/MC/AArch64/SVE/rev.s b/llvm/test/MC/AArch64/SVE/rev.s index 47f9b758d5318..f562401e9567c 100644 --- a/llvm/test/MC/AArch64/SVE/rev.s +++ b/llvm/test/MC/AArch64/SVE/rev.s @@ -12,23 +12,23 @@ rev z0.b, z31.b // CHECK-INST: rev z0.b, z31.b // CHECK-ENCODING: [0xe0,0x3b,0x38,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3b 38 05 rev z0.h, z31.h // CHECK-INST: rev z0.h, z31.h // CHECK-ENCODING: [0xe0,0x3b,0x78,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3b 78 05 rev z0.s, z31.s // CHECK-INST: rev z0.s, z31.s // CHECK-ENCODING: [0xe0,0x3b,0xb8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3b b8 05 rev z0.d, z31.d // CHECK-INST: rev z0.d, z31.d // CHECK-ENCODING: [0xe0,0x3b,0xf8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3b f8 05 diff --git a/llvm/test/MC/AArch64/SVE/revb.s b/llvm/test/MC/AArch64/SVE/revb.s index c71da4bd90a6f..d8e490dbe8eb6 100644 --- a/llvm/test/MC/AArch64/SVE/revb.s +++ b/llvm/test/MC/AArch64/SVE/revb.s @@ -12,19 +12,19 @@ revb z0.h, p7/m, z31.h // CHECK-INST: revb z0.h, p7/m, z31.h // CHECK-ENCODING: [0xe0,0x9f,0x64,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f 64 05 revb z0.s, p7/m, z31.s // CHECK-INST: revb z0.s, p7/m, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a4 05 revb z0.d, p7/m, z31.d // CHECK-INST: revb z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e4 05 @@ -34,23 +34,23 @@ revb z0.d, p7/m, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 revb z0.d, p7/m, z31.d // CHECK-INST: revb z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e4 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 revb z0.d, p7/m, z31.d // CHECK-INST: revb z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e4 05 diff --git a/llvm/test/MC/AArch64/SVE/revh.s b/llvm/test/MC/AArch64/SVE/revh.s index 1cc8f81b73640..687fe9e08e7ce 100644 --- a/llvm/test/MC/AArch64/SVE/revh.s +++ b/llvm/test/MC/AArch64/SVE/revh.s @@ -12,13 +12,13 @@ revh z0.s, p7/m, z31.s // CHECK-INST: revh z0.s, p7/m, z31.s // CHECK-ENCODING: [0xe0,0x9f,0xa5,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f a5 05 revh z0.d, p7/m, z31.d // CHECK-INST: revh z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e5 05 @@ -28,23 +28,23 @@ revh z0.d, p7/m, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 revh z0.d, p7/m, z31.d // CHECK-INST: revh z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e5 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 revh z0.d, p7/m, z31.d // CHECK-INST: revh z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e5 05 diff --git a/llvm/test/MC/AArch64/SVE/revw.s b/llvm/test/MC/AArch64/SVE/revw.s index 2a7afdcfdffb6..3f50f4a95f4c7 100644 --- a/llvm/test/MC/AArch64/SVE/revw.s +++ b/llvm/test/MC/AArch64/SVE/revw.s @@ -12,7 +12,7 @@ revw z0.d, p7/m, z31.d // CHECK-INST: revw z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e6 05 @@ -22,23 +22,23 @@ revw z0.d, p7/m, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 revw z0.d, p7/m, z31.d // CHECK-INST: revw z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e6 05 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 revw z0.d, p7/m, z31.d // CHECK-INST: revw z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 9f e6 05 diff --git a/llvm/test/MC/AArch64/SVE/sabd.s b/llvm/test/MC/AArch64/SVE/sabd.s index 421d46d78699d..e03136aa64021 100644 --- a/llvm/test/MC/AArch64/SVE/sabd.s +++ b/llvm/test/MC/AArch64/SVE/sabd.s @@ -12,25 +12,25 @@ sabd z31.b, p7/m, z31.b, z31.b // CHECK-INST: sabd z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x0c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 0c 04 sabd z31.h, p7/m, z31.h, z31.h // CHECK-INST: sabd z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x4c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 4c 04 sabd z31.s, p7/m, z31.s, z31.s // CHECK-INST: sabd z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x8c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 8c 04 sabd z31.d, p7/m, z31.d, z31.d // CHECK-INST: sabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f cc 04 @@ -40,23 +40,23 @@ sabd z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 sabd z4.d, p7/m, z4.d, z31.d // CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cc 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sabd z4.d, p7/m, z4.d, z31.d // CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cc 04 diff --git a/llvm/test/MC/AArch64/SVE/saddv.s b/llvm/test/MC/AArch64/SVE/saddv.s index e449aae094579..f2ce4d91220c4 100644 --- a/llvm/test/MC/AArch64/SVE/saddv.s +++ b/llvm/test/MC/AArch64/SVE/saddv.s @@ -12,17 +12,17 @@ saddv d0, p7, z31.b // CHECK-INST: saddv d0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x00,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 00 04 saddv d0, p7, z31.h // CHECK-INST: saddv d0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x40,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 40 04 saddv d0, p7, z31.s // CHECK-INST: saddv d0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x80,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 80 04 diff --git a/llvm/test/MC/AArch64/SVE/scvtf.s b/llvm/test/MC/AArch64/SVE/scvtf.s index f10f158bd850c..a7cd2079453f5 100644 --- a/llvm/test/MC/AArch64/SVE/scvtf.s +++ b/llvm/test/MC/AArch64/SVE/scvtf.s @@ -12,43 +12,43 @@ scvtf z0.h, p0/m, z0.h // CHECK-INST: scvtf z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x52,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 52 65 scvtf z0.h, p0/m, z0.s // CHECK-INST: scvtf z0.h, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x54,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 54 65 scvtf z0.h, p0/m, z0.d // CHECK-INST: scvtf z0.h, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0x56,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 56 65 scvtf z0.s, p0/m, z0.s // CHECK-INST: scvtf z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x94,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 94 65 scvtf z0.s, p0/m, z0.d // CHECK-INST: scvtf z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd4,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d4 65 scvtf z0.d, p0/m, z0.s // CHECK-INST: scvtf z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xd0,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d0 65 scvtf z0.d, p0/m, z0.d // CHECK-INST: scvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d6 65 @@ -58,23 +58,23 @@ scvtf z0.d, p0/m, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 scvtf z5.d, p0/m, z0.d // CHECK-INST: scvtf z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 d6 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 scvtf z5.d, p0/m, z0.d // CHECK-INST: scvtf z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 d6 65 diff --git a/llvm/test/MC/AArch64/SVE/sdiv.s b/llvm/test/MC/AArch64/SVE/sdiv.s index dffad1b1198c1..d75e449292cf4 100644 --- a/llvm/test/MC/AArch64/SVE/sdiv.s +++ b/llvm/test/MC/AArch64/SVE/sdiv.s @@ -12,13 +12,13 @@ sdiv z0.s, p7/m, z0.s, z31.s // CHECK-INST: sdiv z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x94,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 94 04 sdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d4 04 @@ -28,23 +28,23 @@ sdiv z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 sdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d4 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sdiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d4 04 diff --git a/llvm/test/MC/AArch64/SVE/sdivr.s b/llvm/test/MC/AArch64/SVE/sdivr.s index 317b61a5d4c7b..6f8a75b9fa78f 100644 --- a/llvm/test/MC/AArch64/SVE/sdivr.s +++ b/llvm/test/MC/AArch64/SVE/sdivr.s @@ -12,13 +12,13 @@ sdivr z0.s, p7/m, z0.s, z31.s // CHECK-INST: sdivr z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x96,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 96 04 sdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d6 04 @@ -28,23 +28,23 @@ sdivr z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 sdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d6 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sdivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d6 04 diff --git a/llvm/test/MC/AArch64/SVE/sdot.s b/llvm/test/MC/AArch64/SVE/sdot.s index 63d4671592cc0..0fe300c399379 100644 --- a/llvm/test/MC/AArch64/SVE/sdot.s +++ b/llvm/test/MC/AArch64/SVE/sdot.s @@ -12,25 +12,25 @@ sdot z0.s, z1.b, z31.b // CHECK-INST: sdot z0.s, z1.b, z31.b // CHECK-ENCODING: [0x20,0x00,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 9f 44 sdot z0.d, z1.h, z31.h // CHECK-INST: sdot z0.d, z1.h, z31.h // CHECK-ENCODING: [0x20,0x00,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 df 44 sdot z0.s, z1.b, z7.b[3] // CHECK-INST: sdot z0.s, z1.b, z7.b[3] // CHECK-ENCODING: [0x20,0x00,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 bf 44 sdot z0.d, z1.h, z15.h[1] // CHECK-INST: sdot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x00,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 ff 44 @@ -40,23 +40,23 @@ sdot z0.d, z1.h, z15.h[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sdot z0.d, z1.h, z31.h // CHECK-INST: sdot z0.d, z1.h, z31.h // CHECK-ENCODING: [0x20,0x00,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 df 44 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sdot z0.d, z1.h, z15.h[1] // CHECK-INST: sdot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x00,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 00 ff 44 diff --git a/llvm/test/MC/AArch64/SVE/sel.s b/llvm/test/MC/AArch64/SVE/sel.s index c5c2ce435adb1..3cb4dbab39f43 100644 --- a/llvm/test/MC/AArch64/SVE/sel.s +++ b/llvm/test/MC/AArch64/SVE/sel.s @@ -12,59 +12,59 @@ sel p0.b, p0, p0.b, p0.b // CHECK-INST: mov p0.b, p0/m, p0.b // CHECK-ENCODING: [0x10,0x42,0x00,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 10 42 00 25 sel p15.b, p15, p15.b, p15.b // CHECK-INST: mov p15.b, p15/m, p15.b // CHECK-ENCODING: [0xff,0x7f,0x0f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 7f 0f 25 sel z31.b, p15, z31.b, z31.b // CHECK-INST: mov z31.b, p15/m, z31.b // CHECK-ENCODING: [0xff,0xff,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 3f 05 sel z31.h, p15, z31.h, z31.h // CHECK-INST: mov z31.h, p15/m, z31.h // CHECK-ENCODING: [0xff,0xff,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 7f 05 sel z31.s, p15, z31.s, z31.s // CHECK-INST: mov z31.s, p15/m, z31.s // CHECK-ENCODING: [0xff,0xff,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff bf 05 sel z31.d, p15, z31.d, z31.d // CHECK-INST: mov z31.d, p15/m, z31.d // CHECK-ENCODING: [0xff,0xff,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ff 05 sel z23.s, p11, z13.s, z8.s // CHECK-INST: sel z23.s, p11, z13.s, z8.s // CHECK-ENCODING: [0xb7,0xed,0xa8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed a8 05 sel z23.d, p11, z13.d, z8.d // CHECK-INST: sel z23.d, p11, z13.d, z8.d // CHECK-ENCODING: [0xb7,0xed,0xe8,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed e8 05 sel z23.h, p11, z13.h, z8.h // CHECK-INST: sel z23.h, p11, z13.h, z8.h // CHECK-ENCODING: [0xb7,0xed,0x68,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 68 05 sel z23.b, p11, z13.b, z8.b // CHECK-INST: sel z23.b, p11, z13.b, z8.b // CHECK-ENCODING: [0xb7,0xed,0x28,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 28 05 diff --git a/llvm/test/MC/AArch64/SVE/smax.s b/llvm/test/MC/AArch64/SVE/smax.s index f668029c328c2..1de6ccf907ba1 100644 --- a/llvm/test/MC/AArch64/SVE/smax.s +++ b/llvm/test/MC/AArch64/SVE/smax.s @@ -12,73 +12,73 @@ smax z0.b, z0.b, #-128 // CHECK-INST: smax z0.b, z0.b, #-128 // CHECK-ENCODING: [0x00,0xd0,0x28,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 28 25 smax z31.b, z31.b, #127 // CHECK-INST: smax z31.b, z31.b, #127 // CHECK-ENCODING: [0xff,0xcf,0x28,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 28 25 smax z0.h, z0.h, #-128 // CHECK-INST: smax z0.h, z0.h, #-128 // CHECK-ENCODING: [0x00,0xd0,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 68 25 smax z31.h, z31.h, #127 // CHECK-INST: smax z31.h, z31.h, #127 // CHECK-ENCODING: [0xff,0xcf,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 68 25 smax z0.s, z0.s, #-128 // CHECK-INST: smax z0.s, z0.s, #-128 // CHECK-ENCODING: [0x00,0xd0,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 a8 25 smax z31.s, z31.s, #127 // CHECK-INST: smax z31.s, z31.s, #127 // CHECK-ENCODING: [0xff,0xcf,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf a8 25 smax z0.d, z0.d, #-128 // CHECK-INST: smax z0.d, z0.d, #-128 // CHECK-ENCODING: [0x00,0xd0,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 e8 25 smax z31.d, z31.d, #127 // CHECK-INST: smax z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf e8 25 smax z31.b, p7/m, z31.b, z31.b // CHECK-INST: smax z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x08,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 08 04 smax z31.h, p7/m, z31.h, z31.h // CHECK-INST: smax z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x48,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 48 04 smax z31.s, p7/m, z31.s, z31.s // CHECK-INST: smax z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x88,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 88 04 smax z31.d, p7/m, z31.d, z31.d // CHECK-INST: smax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f c8 04 @@ -88,35 +88,35 @@ smax z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 smax z4.d, p7/m, z4.d, z31.d // CHECK-INST: smax z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f c8 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 smax z4.d, p7/m, z4.d, z31.d // CHECK-INST: smax z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f c8 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 smax z31.d, z31.d, #127 // CHECK-INST: smax z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf e8 25 diff --git a/llvm/test/MC/AArch64/SVE/smaxv.s b/llvm/test/MC/AArch64/SVE/smaxv.s index f3867cf05127a..01d864c8f5e64 100644 --- a/llvm/test/MC/AArch64/SVE/smaxv.s +++ b/llvm/test/MC/AArch64/SVE/smaxv.s @@ -12,23 +12,23 @@ smaxv b0, p7, z31.b // CHECK-INST: smaxv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x08,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 08 04 smaxv h0, p7, z31.h // CHECK-INST: smaxv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x48,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 48 04 smaxv s0, p7, z31.s // CHECK-INST: smaxv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x88,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 88 04 smaxv d0, p7, z31.d // CHECK-INST: smaxv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c8 04 diff --git a/llvm/test/MC/AArch64/SVE/smin.s b/llvm/test/MC/AArch64/SVE/smin.s index 4b8528167d3f1..5df5aeeb05a89 100644 --- a/llvm/test/MC/AArch64/SVE/smin.s +++ b/llvm/test/MC/AArch64/SVE/smin.s @@ -12,73 +12,73 @@ smin z0.b, z0.b, #-128 // CHECK-INST: smin z0.b, z0.b, #-128 // CHECK-ENCODING: [0x00,0xd0,0x2a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 2a 25 smin z31.b, z31.b, #127 // CHECK-INST: smin z31.b, z31.b, #127 // CHECK-ENCODING: [0xff,0xcf,0x2a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 2a 25 smin z0.h, z0.h, #-128 // CHECK-INST: smin z0.h, z0.h, #-128 // CHECK-ENCODING: [0x00,0xd0,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 6a 25 smin z31.h, z31.h, #127 // CHECK-INST: smin z31.h, z31.h, #127 // CHECK-ENCODING: [0xff,0xcf,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf 6a 25 smin z0.s, z0.s, #-128 // CHECK-INST: smin z0.s, z0.s, #-128 // CHECK-ENCODING: [0x00,0xd0,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 aa 25 smin z31.s, z31.s, #127 // CHECK-INST: smin z31.s, z31.s, #127 // CHECK-ENCODING: [0xff,0xcf,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf aa 25 smin z0.d, z0.d, #-128 // CHECK-INST: smin z0.d, z0.d, #-128 // CHECK-ENCODING: [0x00,0xd0,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 d0 ea 25 smin z31.d, z31.d, #127 // CHECK-INST: smin z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf ea 25 smin z31.b, p7/m, z31.b, z31.b // CHECK-INST: smin z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x0a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 0a 04 smin z31.h, p7/m, z31.h, z31.h // CHECK-INST: smin z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x4a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 4a 04 smin z31.s, p7/m, z31.s, z31.s // CHECK-INST: smin z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x8a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 8a 04 smin z31.d, p7/m, z31.d, z31.d // CHECK-INST: smin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xca,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f ca 04 @@ -88,35 +88,35 @@ smin z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 smin z4.d, p7/m, z4.d, z31.d // CHECK-INST: smin z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f ca 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 smin z4.d, p7/m, z4.d, z31.d // CHECK-INST: smin z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f ca 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 smin z31.d, z31.d, #127 // CHECK-INST: smin z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff cf ea 25 diff --git a/llvm/test/MC/AArch64/SVE/sminv.s b/llvm/test/MC/AArch64/SVE/sminv.s index 3ac72b9720561..c0ab800e73df4 100644 --- a/llvm/test/MC/AArch64/SVE/sminv.s +++ b/llvm/test/MC/AArch64/SVE/sminv.s @@ -12,23 +12,23 @@ sminv b0, p7, z31.b // CHECK-INST: sminv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x0a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 0a 04 sminv h0, p7, z31.h // CHECK-INST: sminv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x4a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 4a 04 sminv s0, p7, z31.s // CHECK-INST: sminv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x8a,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 8a 04 sminv d0, p7, z31.d // CHECK-INST: sminv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xca,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f ca 04 diff --git a/llvm/test/MC/AArch64/SVE/smulh.s b/llvm/test/MC/AArch64/SVE/smulh.s index 53a67673acc68..3c531620e0f68 100644 --- a/llvm/test/MC/AArch64/SVE/smulh.s +++ b/llvm/test/MC/AArch64/SVE/smulh.s @@ -12,25 +12,25 @@ smulh z0.b, p7/m, z0.b, z31.b // CHECK-INST: smulh z0.b, p7/m, z0.b, z31.b // CHECK-ENCODING: [0xe0,0x1f,0x12,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 12 04 smulh z0.h, p7/m, z0.h, z31.h // CHECK-INST: smulh z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x1f,0x52,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 52 04 smulh z0.s, p7/m, z0.s, z31.s // CHECK-INST: smulh z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x92,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 92 04 smulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d2 04 @@ -40,23 +40,23 @@ smulh z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 smulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d2 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 smulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d2 04 diff --git a/llvm/test/MC/AArch64/SVE/splice.s b/llvm/test/MC/AArch64/SVE/splice.s index 83af81e204ff4..64c7959cc2f88 100644 --- a/llvm/test/MC/AArch64/SVE/splice.s +++ b/llvm/test/MC/AArch64/SVE/splice.s @@ -12,25 +12,25 @@ splice z31.b, p7, z31.b, z31.b // CHECK-INST: splice z31.b, p7, z31.b, z31.b // CHECK-ENCODING: [0xff,0x9f,0x2c,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 2c 05 splice z31.h, p7, z31.h, z31.h // CHECK-INST: splice z31.h, p7, z31.h, z31.h // CHECK-ENCODING: [0xff,0x9f,0x6c,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f 6c 05 splice z31.s, p7, z31.s, z31.s // CHECK-INST: splice z31.s, p7, z31.s, z31.s // CHECK-ENCODING: [0xff,0x9f,0xac,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f ac 05 splice z31.d, p7, z31.d, z31.d // CHECK-INST: splice z31.d, p7, z31.d, z31.d // CHECK-ENCODING: [0xff,0x9f,0xec,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 9f ec 05 @@ -40,11 +40,11 @@ splice z31.d, p7, z31.d, z31.d movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 splice z4.d, p7, z4.d, z31.d // CHECK-INST: splice z4.d, p7, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x9f,0xec,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 9f ec 05 diff --git a/llvm/test/MC/AArch64/SVE/sqadd.s b/llvm/test/MC/AArch64/SVE/sqadd.s index 0535766d99cf1..d20343d5fa70d 100644 --- a/llvm/test/MC/AArch64/SVE/sqadd.s +++ b/llvm/test/MC/AArch64/SVE/sqadd.s @@ -13,109 +13,109 @@ sqadd z0.b, z0.b, z0.b // CHECK-INST: sqadd z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x10,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 10 20 04 sqadd z0.h, z0.h, z0.h // CHECK-INST: sqadd z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x10,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 10 60 04 sqadd z0.s, z0.s, z0.s // CHECK-INST: sqadd z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x10,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 10 a0 04 sqadd z0.d, z0.d, z0.d // CHECK-INST: sqadd z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x10,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 10 e0 04 sqadd z0.b, z0.b, #0 // CHECK-INST: sqadd z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x24,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 24 25 sqadd z31.b, z31.b, #255 // CHECK-INST: sqadd z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x24,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 24 25 sqadd z0.h, z0.h, #0 // CHECK-INST: sqadd z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x64,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 64 25 sqadd z0.h, z0.h, #0, lsl #8 // CHECK-INST: sqadd z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x64,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 64 25 sqadd z31.h, z31.h, #255, lsl #8 // CHECK-INST: sqadd z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x64,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 64 25 sqadd z31.h, z31.h, #65280 // CHECK-INST: sqadd z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x64,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 64 25 sqadd z0.s, z0.s, #0 // CHECK-INST: sqadd z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a4 25 sqadd z0.s, z0.s, #0, lsl #8 // CHECK-INST: sqadd z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a4 25 sqadd z31.s, z31.s, #255, lsl #8 // CHECK-INST: sqadd z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a4 25 sqadd z31.s, z31.s, #65280 // CHECK-INST: sqadd z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a4 25 sqadd z0.d, z0.d, #0 // CHECK-INST: sqadd z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e4 25 sqadd z0.d, z0.d, #0, lsl #8 // CHECK-INST: sqadd z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e4 25 sqadd z31.d, z31.d, #255, lsl #8 // CHECK-INST: sqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e4 25 sqadd z31.d, z31.d, #65280 // CHECK-INST: sqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e4 25 @@ -125,11 +125,11 @@ sqadd z31.d, z31.d, #65280 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqadd z31.d, z31.d, #65280 // CHECK-INST: sqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e4 25 diff --git a/llvm/test/MC/AArch64/SVE/sqdecb.s b/llvm/test/MC/AArch64/SVE/sqdecb.s index 8f4f65be2b5c4..9c9a75d315842 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecb.s +++ b/llvm/test/MC/AArch64/SVE/sqdecb.s @@ -16,25 +16,25 @@ sqdecb x0 // CHECK-INST: sqdecb x0 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 30 04 sqdecb x0, all // CHECK-INST: sqdecb x0 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 30 04 sqdecb x0, all, mul #1 // CHECK-INST: sqdecb x0 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 30 04 sqdecb x0, all, mul #16 // CHECK-INST: sqdecb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 3f 04 @@ -45,37 +45,37 @@ sqdecb x0, all, mul #16 sqdecb x0, w0 // CHECK-INST: sqdecb x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 20 04 sqdecb x0, w0, all // CHECK-INST: sqdecb x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 20 04 sqdecb x0, w0, all, mul #1 // CHECK-INST: sqdecb x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 20 04 sqdecb x0, w0, all, mul #16 // CHECK-INST: sqdecb x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 2f 04 sqdecb x0, w0, pow2 // CHECK-INST: sqdecb x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf8,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 20 04 sqdecb x0, w0, pow2, mul #16 // CHECK-INST: sqdecb x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf8,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 2f 04 @@ -86,173 +86,173 @@ sqdecb x0, w0, pow2, mul #16 sqdecb x0, pow2 // CHECK-INST: sqdecb x0, pow2 // CHECK-ENCODING: [0x00,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 30 04 sqdecb x0, vl1 // CHECK-INST: sqdecb x0, vl1 // CHECK-ENCODING: [0x20,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 30 04 sqdecb x0, vl2 // CHECK-INST: sqdecb x0, vl2 // CHECK-ENCODING: [0x40,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f8 30 04 sqdecb x0, vl3 // CHECK-INST: sqdecb x0, vl3 // CHECK-ENCODING: [0x60,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f8 30 04 sqdecb x0, vl4 // CHECK-INST: sqdecb x0, vl4 // CHECK-ENCODING: [0x80,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f8 30 04 sqdecb x0, vl5 // CHECK-INST: sqdecb x0, vl5 // CHECK-ENCODING: [0xa0,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f8 30 04 sqdecb x0, vl6 // CHECK-INST: sqdecb x0, vl6 // CHECK-ENCODING: [0xc0,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f8 30 04 sqdecb x0, vl7 // CHECK-INST: sqdecb x0, vl7 // CHECK-ENCODING: [0xe0,0xf8,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f8 30 04 sqdecb x0, vl8 // CHECK-INST: sqdecb x0, vl8 // CHECK-ENCODING: [0x00,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f9 30 04 sqdecb x0, vl16 // CHECK-INST: sqdecb x0, vl16 // CHECK-ENCODING: [0x20,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f9 30 04 sqdecb x0, vl32 // CHECK-INST: sqdecb x0, vl32 // CHECK-ENCODING: [0x40,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f9 30 04 sqdecb x0, vl64 // CHECK-INST: sqdecb x0, vl64 // CHECK-ENCODING: [0x60,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f9 30 04 sqdecb x0, vl128 // CHECK-INST: sqdecb x0, vl128 // CHECK-ENCODING: [0x80,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f9 30 04 sqdecb x0, vl256 // CHECK-INST: sqdecb x0, vl256 // CHECK-ENCODING: [0xa0,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f9 30 04 sqdecb x0, #14 // CHECK-INST: sqdecb x0, #14 // CHECK-ENCODING: [0xc0,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f9 30 04 sqdecb x0, #15 // CHECK-INST: sqdecb x0, #15 // CHECK-ENCODING: [0xe0,0xf9,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f9 30 04 sqdecb x0, #16 // CHECK-INST: sqdecb x0, #16 // CHECK-ENCODING: [0x00,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fa 30 04 sqdecb x0, #17 // CHECK-INST: sqdecb x0, #17 // CHECK-ENCODING: [0x20,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fa 30 04 sqdecb x0, #18 // CHECK-INST: sqdecb x0, #18 // CHECK-ENCODING: [0x40,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fa 30 04 sqdecb x0, #19 // CHECK-INST: sqdecb x0, #19 // CHECK-ENCODING: [0x60,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fa 30 04 sqdecb x0, #20 // CHECK-INST: sqdecb x0, #20 // CHECK-ENCODING: [0x80,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fa 30 04 sqdecb x0, #21 // CHECK-INST: sqdecb x0, #21 // CHECK-ENCODING: [0xa0,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fa 30 04 sqdecb x0, #22 // CHECK-INST: sqdecb x0, #22 // CHECK-ENCODING: [0xc0,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fa 30 04 sqdecb x0, #23 // CHECK-INST: sqdecb x0, #23 // CHECK-ENCODING: [0xe0,0xfa,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fa 30 04 sqdecb x0, #24 // CHECK-INST: sqdecb x0, #24 // CHECK-ENCODING: [0x00,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fb 30 04 sqdecb x0, #25 // CHECK-INST: sqdecb x0, #25 // CHECK-ENCODING: [0x20,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fb 30 04 sqdecb x0, #26 // CHECK-INST: sqdecb x0, #26 // CHECK-ENCODING: [0x40,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fb 30 04 sqdecb x0, #27 // CHECK-INST: sqdecb x0, #27 // CHECK-ENCODING: [0x60,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fb 30 04 sqdecb x0, #28 // CHECK-INST: sqdecb x0, #28 // CHECK-ENCODING: [0x80,0xfb,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fb 30 04 diff --git a/llvm/test/MC/AArch64/SVE/sqdecd.s b/llvm/test/MC/AArch64/SVE/sqdecd.s index cfe3b7e52b3fa..a107438889024 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecd.s +++ b/llvm/test/MC/AArch64/SVE/sqdecd.s @@ -16,25 +16,25 @@ sqdecd x0 // CHECK-INST: sqdecd x0 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb f0 04 sqdecd x0, all // CHECK-INST: sqdecd x0 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb f0 04 sqdecd x0, all, mul #1 // CHECK-INST: sqdecd x0 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb f0 04 sqdecd x0, all, mul #16 // CHECK-INST: sqdecd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb ff 04 @@ -45,37 +45,37 @@ sqdecd x0, all, mul #16 sqdecd x0, w0 // CHECK-INST: sqdecd x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb e0 04 sqdecd x0, w0, all // CHECK-INST: sqdecd x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb e0 04 sqdecd x0, w0, all, mul #1 // CHECK-INST: sqdecd x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb e0 04 sqdecd x0, w0, all, mul #16 // CHECK-INST: sqdecd x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb ef 04 sqdecd x0, w0, pow2 // CHECK-INST: sqdecd x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf8,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 e0 04 sqdecd x0, w0, pow2, mul #16 // CHECK-INST: sqdecd x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf8,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 ef 04 @@ -85,37 +85,37 @@ sqdecd x0, w0, pow2, mul #16 sqdecd z0.d // CHECK-INST: sqdecd z0.d // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb e0 04 sqdecd z0.d, all // CHECK-INST: sqdecd z0.d // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb e0 04 sqdecd z0.d, all, mul #1 // CHECK-INST: sqdecd z0.d // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb e0 04 sqdecd z0.d, all, mul #16 // CHECK-INST: sqdecd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xcb,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb ef 04 sqdecd z0.d, pow2 // CHECK-INST: sqdecd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc8,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 e0 04 sqdecd z0.d, pow2, mul #16 // CHECK-INST: sqdecd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 ef 04 @@ -126,175 +126,175 @@ sqdecd z0.d, pow2, mul #16 sqdecd x0, pow2 // CHECK-INST: sqdecd x0, pow2 // CHECK-ENCODING: [0x00,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 f0 04 sqdecd x0, vl1 // CHECK-INST: sqdecd x0, vl1 // CHECK-ENCODING: [0x20,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 f0 04 sqdecd x0, vl2 // CHECK-INST: sqdecd x0, vl2 // CHECK-ENCODING: [0x40,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f8 f0 04 sqdecd x0, vl3 // CHECK-INST: sqdecd x0, vl3 // CHECK-ENCODING: [0x60,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f8 f0 04 sqdecd x0, vl4 // CHECK-INST: sqdecd x0, vl4 // CHECK-ENCODING: [0x80,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f8 f0 04 sqdecd x0, vl5 // CHECK-INST: sqdecd x0, vl5 // CHECK-ENCODING: [0xa0,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f8 f0 04 sqdecd x0, vl6 // CHECK-INST: sqdecd x0, vl6 // CHECK-ENCODING: [0xc0,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f8 f0 04 sqdecd x0, vl7 // CHECK-INST: sqdecd x0, vl7 // CHECK-ENCODING: [0xe0,0xf8,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f8 f0 04 sqdecd x0, vl8 // CHECK-INST: sqdecd x0, vl8 // CHECK-ENCODING: [0x00,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f9 f0 04 sqdecd x0, vl16 // CHECK-INST: sqdecd x0, vl16 // CHECK-ENCODING: [0x20,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f9 f0 04 sqdecd x0, vl32 // CHECK-INST: sqdecd x0, vl32 // CHECK-ENCODING: [0x40,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f9 f0 04 sqdecd x0, vl64 // CHECK-INST: sqdecd x0, vl64 // CHECK-ENCODING: [0x60,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f9 f0 04 sqdecd x0, vl128 // CHECK-INST: sqdecd x0, vl128 // CHECK-ENCODING: [0x80,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f9 f0 04 sqdecd x0, vl256 // CHECK-INST: sqdecd x0, vl256 // CHECK-ENCODING: [0xa0,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f9 f0 04 sqdecd x0, #14 // CHECK-INST: sqdecd x0, #14 // CHECK-ENCODING: [0xc0,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f9 f0 04 sqdecd x0, #15 // CHECK-INST: sqdecd x0, #15 // CHECK-ENCODING: [0xe0,0xf9,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f9 f0 04 sqdecd x0, #16 // CHECK-INST: sqdecd x0, #16 // CHECK-ENCODING: [0x00,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fa f0 04 sqdecd x0, #17 // CHECK-INST: sqdecd x0, #17 // CHECK-ENCODING: [0x20,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fa f0 04 sqdecd x0, #18 // CHECK-INST: sqdecd x0, #18 // CHECK-ENCODING: [0x40,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fa f0 04 sqdecd x0, #19 // CHECK-INST: sqdecd x0, #19 // CHECK-ENCODING: [0x60,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fa f0 04 sqdecd x0, #20 // CHECK-INST: sqdecd x0, #20 // CHECK-ENCODING: [0x80,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fa f0 04 sqdecd x0, #21 // CHECK-INST: sqdecd x0, #21 // CHECK-ENCODING: [0xa0,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fa f0 04 sqdecd x0, #22 // CHECK-INST: sqdecd x0, #22 // CHECK-ENCODING: [0xc0,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fa f0 04 sqdecd x0, #23 // CHECK-INST: sqdecd x0, #23 // CHECK-ENCODING: [0xe0,0xfa,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fa f0 04 sqdecd x0, #24 // CHECK-INST: sqdecd x0, #24 // CHECK-ENCODING: [0x00,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fb f0 04 sqdecd x0, #25 // CHECK-INST: sqdecd x0, #25 // CHECK-ENCODING: [0x20,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fb f0 04 sqdecd x0, #26 // CHECK-INST: sqdecd x0, #26 // CHECK-ENCODING: [0x40,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fb f0 04 sqdecd x0, #27 // CHECK-INST: sqdecd x0, #27 // CHECK-ENCODING: [0x60,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fb f0 04 sqdecd x0, #28 // CHECK-INST: sqdecd x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fb f0 04 @@ -304,35 +304,35 @@ sqdecd x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecd z0.d // CHECK-INST: sqdecd z0.d // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb e0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecd z0.d, pow2, mul #16 // CHECK-INST: sqdecd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 ef 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecd z0.d, pow2 // CHECK-INST: sqdecd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc8,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 e0 04 diff --git a/llvm/test/MC/AArch64/SVE/sqdech.s b/llvm/test/MC/AArch64/SVE/sqdech.s index b6cb8991c2dbd..44ab11d90da5f 100644 --- a/llvm/test/MC/AArch64/SVE/sqdech.s +++ b/llvm/test/MC/AArch64/SVE/sqdech.s @@ -16,25 +16,25 @@ sqdech x0 // CHECK-INST: sqdech x0 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 70 04 sqdech x0, all // CHECK-INST: sqdech x0 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 70 04 sqdech x0, all, mul #1 // CHECK-INST: sqdech x0 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 70 04 sqdech x0, all, mul #16 // CHECK-INST: sqdech x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 7f 04 @@ -45,37 +45,37 @@ sqdech x0, all, mul #16 sqdech x0, w0 // CHECK-INST: sqdech x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 60 04 sqdech x0, w0, all // CHECK-INST: sqdech x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 60 04 sqdech x0, w0, all, mul #1 // CHECK-INST: sqdech x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 60 04 sqdech x0, w0, all, mul #16 // CHECK-INST: sqdech x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb 6f 04 sqdech x0, w0, pow2 // CHECK-INST: sqdech x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf8,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 60 04 sqdech x0, w0, pow2, mul #16 // CHECK-INST: sqdech x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf8,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 6f 04 @@ -85,37 +85,37 @@ sqdech x0, w0, pow2, mul #16 sqdech z0.h // CHECK-INST: sqdech z0.h // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb 60 04 sqdech z0.h, all // CHECK-INST: sqdech z0.h // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb 60 04 sqdech z0.h, all, mul #1 // CHECK-INST: sqdech z0.h // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb 60 04 sqdech z0.h, all, mul #16 // CHECK-INST: sqdech z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xcb,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb 6f 04 sqdech z0.h, pow2 // CHECK-INST: sqdech z0.h, pow2 // CHECK-ENCODING: [0x00,0xc8,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 60 04 sqdech z0.h, pow2, mul #16 // CHECK-INST: sqdech z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 6f 04 @@ -126,175 +126,175 @@ sqdech z0.h, pow2, mul #16 sqdech x0, pow2 // CHECK-INST: sqdech x0, pow2 // CHECK-ENCODING: [0x00,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 70 04 sqdech x0, vl1 // CHECK-INST: sqdech x0, vl1 // CHECK-ENCODING: [0x20,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 70 04 sqdech x0, vl2 // CHECK-INST: sqdech x0, vl2 // CHECK-ENCODING: [0x40,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f8 70 04 sqdech x0, vl3 // CHECK-INST: sqdech x0, vl3 // CHECK-ENCODING: [0x60,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f8 70 04 sqdech x0, vl4 // CHECK-INST: sqdech x0, vl4 // CHECK-ENCODING: [0x80,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f8 70 04 sqdech x0, vl5 // CHECK-INST: sqdech x0, vl5 // CHECK-ENCODING: [0xa0,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f8 70 04 sqdech x0, vl6 // CHECK-INST: sqdech x0, vl6 // CHECK-ENCODING: [0xc0,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f8 70 04 sqdech x0, vl7 // CHECK-INST: sqdech x0, vl7 // CHECK-ENCODING: [0xe0,0xf8,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f8 70 04 sqdech x0, vl8 // CHECK-INST: sqdech x0, vl8 // CHECK-ENCODING: [0x00,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f9 70 04 sqdech x0, vl16 // CHECK-INST: sqdech x0, vl16 // CHECK-ENCODING: [0x20,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f9 70 04 sqdech x0, vl32 // CHECK-INST: sqdech x0, vl32 // CHECK-ENCODING: [0x40,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f9 70 04 sqdech x0, vl64 // CHECK-INST: sqdech x0, vl64 // CHECK-ENCODING: [0x60,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f9 70 04 sqdech x0, vl128 // CHECK-INST: sqdech x0, vl128 // CHECK-ENCODING: [0x80,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f9 70 04 sqdech x0, vl256 // CHECK-INST: sqdech x0, vl256 // CHECK-ENCODING: [0xa0,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f9 70 04 sqdech x0, #14 // CHECK-INST: sqdech x0, #14 // CHECK-ENCODING: [0xc0,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f9 70 04 sqdech x0, #15 // CHECK-INST: sqdech x0, #15 // CHECK-ENCODING: [0xe0,0xf9,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f9 70 04 sqdech x0, #16 // CHECK-INST: sqdech x0, #16 // CHECK-ENCODING: [0x00,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fa 70 04 sqdech x0, #17 // CHECK-INST: sqdech x0, #17 // CHECK-ENCODING: [0x20,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fa 70 04 sqdech x0, #18 // CHECK-INST: sqdech x0, #18 // CHECK-ENCODING: [0x40,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fa 70 04 sqdech x0, #19 // CHECK-INST: sqdech x0, #19 // CHECK-ENCODING: [0x60,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fa 70 04 sqdech x0, #20 // CHECK-INST: sqdech x0, #20 // CHECK-ENCODING: [0x80,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fa 70 04 sqdech x0, #21 // CHECK-INST: sqdech x0, #21 // CHECK-ENCODING: [0xa0,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fa 70 04 sqdech x0, #22 // CHECK-INST: sqdech x0, #22 // CHECK-ENCODING: [0xc0,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fa 70 04 sqdech x0, #23 // CHECK-INST: sqdech x0, #23 // CHECK-ENCODING: [0xe0,0xfa,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fa 70 04 sqdech x0, #24 // CHECK-INST: sqdech x0, #24 // CHECK-ENCODING: [0x00,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fb 70 04 sqdech x0, #25 // CHECK-INST: sqdech x0, #25 // CHECK-ENCODING: [0x20,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fb 70 04 sqdech x0, #26 // CHECK-INST: sqdech x0, #26 // CHECK-ENCODING: [0x40,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fb 70 04 sqdech x0, #27 // CHECK-INST: sqdech x0, #27 // CHECK-ENCODING: [0x60,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fb 70 04 sqdech x0, #28 // CHECK-INST: sqdech x0, #28 // CHECK-ENCODING: [0x80,0xfb,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fb 70 04 @@ -304,35 +304,35 @@ sqdech x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdech z0.h // CHECK-INST: sqdech z0.h // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb 60 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdech z0.h, pow2, mul #16 // CHECK-INST: sqdech z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 6f 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdech z0.h, pow2 // CHECK-INST: sqdech z0.h, pow2 // CHECK-ENCODING: [0x00,0xc8,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 60 04 diff --git a/llvm/test/MC/AArch64/SVE/sqdecp.s b/llvm/test/MC/AArch64/SVE/sqdecp.s index adbc5968ab79d..16c6e984293ed 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecp.s +++ b/llvm/test/MC/AArch64/SVE/sqdecp.s @@ -12,85 +12,85 @@ sqdecp x0, p0.b // CHECK-INST: sqdecp x0, p0.b // CHECK-ENCODING: [0x00,0x8c,0x2a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 2a 25 sqdecp x0, p0.h // CHECK-INST: sqdecp x0, p0.h // CHECK-ENCODING: [0x00,0x8c,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 6a 25 sqdecp x0, p0.s // CHECK-INST: sqdecp x0, p0.s // CHECK-ENCODING: [0x00,0x8c,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c aa 25 sqdecp x0, p0.d // CHECK-INST: sqdecp x0, p0.d // CHECK-ENCODING: [0x00,0x8c,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c ea 25 sqdecp xzr, p15.b, wzr // CHECK-INST: sqdecp xzr, p15.b, wzr // CHECK-ENCODING: [0xff,0x89,0x2a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 2a 25 sqdecp xzr, p15.h, wzr // CHECK-INST: sqdecp xzr, p15.h, wzr // CHECK-ENCODING: [0xff,0x89,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 6a 25 sqdecp xzr, p15.s, wzr // CHECK-INST: sqdecp xzr, p15.s, wzr // CHECK-ENCODING: [0xff,0x89,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 aa 25 sqdecp xzr, p15.d, wzr // CHECK-INST: sqdecp xzr, p15.d, wzr // CHECK-ENCODING: [0xff,0x89,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ea 25 sqdecp z0.h, p0 // CHECK-INST: sqdecp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 6a 25 sqdecp z0.h, p0.h // CHECK-INST: sqdecp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x6a,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 6a 25 sqdecp z0.s, p0 // CHECK-INST: sqdecp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 aa 25 sqdecp z0.s, p0.s // CHECK-INST: sqdecp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xaa,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 aa 25 sqdecp z0.d, p0 // CHECK-INST: sqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 ea 25 sqdecp z0.d, p0.d // CHECK-INST: sqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 ea 25 @@ -100,11 +100,11 @@ sqdecp z0.d, p0.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecp z0.d, p0.d // CHECK-INST: sqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xea,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 ea 25 diff --git a/llvm/test/MC/AArch64/SVE/sqdecw.s b/llvm/test/MC/AArch64/SVE/sqdecw.s index 110c38eb8f433..9ce9e47498f29 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecw.s +++ b/llvm/test/MC/AArch64/SVE/sqdecw.s @@ -16,25 +16,25 @@ sqdecw x0 // CHECK-INST: sqdecw x0 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb b0 04 sqdecw x0, all // CHECK-INST: sqdecw x0 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb b0 04 sqdecw x0, all, mul #1 // CHECK-INST: sqdecw x0 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb b0 04 sqdecw x0, all, mul #16 // CHECK-INST: sqdecw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb bf 04 @@ -45,37 +45,37 @@ sqdecw x0, all, mul #16 sqdecw x0, w0 // CHECK-INST: sqdecw x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb a0 04 sqdecw x0, w0, all // CHECK-INST: sqdecw x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb a0 04 sqdecw x0, w0, all, mul #1 // CHECK-INST: sqdecw x0, w0 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb a0 04 sqdecw x0, w0, all, mul #16 // CHECK-INST: sqdecw x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fb af 04 sqdecw x0, w0, pow2 // CHECK-INST: sqdecw x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf8,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 a0 04 sqdecw x0, w0, pow2, mul #16 // CHECK-INST: sqdecw x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf8,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 af 04 @@ -85,37 +85,37 @@ sqdecw x0, w0, pow2, mul #16 sqdecw z0.s // CHECK-INST: sqdecw z0.s // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb a0 04 sqdecw z0.s, all // CHECK-INST: sqdecw z0.s // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb a0 04 sqdecw z0.s, all, mul #1 // CHECK-INST: sqdecw z0.s // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb a0 04 sqdecw z0.s, all, mul #16 // CHECK-INST: sqdecw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xcb,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb af 04 sqdecw z0.s, pow2 // CHECK-INST: sqdecw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc8,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 a0 04 sqdecw z0.s, pow2, mul #16 // CHECK-INST: sqdecw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 af 04 @@ -126,175 +126,175 @@ sqdecw z0.s, pow2, mul #16 sqdecw x0, pow2 // CHECK-INST: sqdecw x0, pow2 // CHECK-ENCODING: [0x00,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f8 b0 04 sqdecw x0, vl1 // CHECK-INST: sqdecw x0, vl1 // CHECK-ENCODING: [0x20,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f8 b0 04 sqdecw x0, vl2 // CHECK-INST: sqdecw x0, vl2 // CHECK-ENCODING: [0x40,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f8 b0 04 sqdecw x0, vl3 // CHECK-INST: sqdecw x0, vl3 // CHECK-ENCODING: [0x60,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f8 b0 04 sqdecw x0, vl4 // CHECK-INST: sqdecw x0, vl4 // CHECK-ENCODING: [0x80,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f8 b0 04 sqdecw x0, vl5 // CHECK-INST: sqdecw x0, vl5 // CHECK-ENCODING: [0xa0,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f8 b0 04 sqdecw x0, vl6 // CHECK-INST: sqdecw x0, vl6 // CHECK-ENCODING: [0xc0,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f8 b0 04 sqdecw x0, vl7 // CHECK-INST: sqdecw x0, vl7 // CHECK-ENCODING: [0xe0,0xf8,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f8 b0 04 sqdecw x0, vl8 // CHECK-INST: sqdecw x0, vl8 // CHECK-ENCODING: [0x00,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f9 b0 04 sqdecw x0, vl16 // CHECK-INST: sqdecw x0, vl16 // CHECK-ENCODING: [0x20,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f9 b0 04 sqdecw x0, vl32 // CHECK-INST: sqdecw x0, vl32 // CHECK-ENCODING: [0x40,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f9 b0 04 sqdecw x0, vl64 // CHECK-INST: sqdecw x0, vl64 // CHECK-ENCODING: [0x60,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f9 b0 04 sqdecw x0, vl128 // CHECK-INST: sqdecw x0, vl128 // CHECK-ENCODING: [0x80,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f9 b0 04 sqdecw x0, vl256 // CHECK-INST: sqdecw x0, vl256 // CHECK-ENCODING: [0xa0,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f9 b0 04 sqdecw x0, #14 // CHECK-INST: sqdecw x0, #14 // CHECK-ENCODING: [0xc0,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f9 b0 04 sqdecw x0, #15 // CHECK-INST: sqdecw x0, #15 // CHECK-ENCODING: [0xe0,0xf9,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f9 b0 04 sqdecw x0, #16 // CHECK-INST: sqdecw x0, #16 // CHECK-ENCODING: [0x00,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fa b0 04 sqdecw x0, #17 // CHECK-INST: sqdecw x0, #17 // CHECK-ENCODING: [0x20,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fa b0 04 sqdecw x0, #18 // CHECK-INST: sqdecw x0, #18 // CHECK-ENCODING: [0x40,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fa b0 04 sqdecw x0, #19 // CHECK-INST: sqdecw x0, #19 // CHECK-ENCODING: [0x60,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fa b0 04 sqdecw x0, #20 // CHECK-INST: sqdecw x0, #20 // CHECK-ENCODING: [0x80,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fa b0 04 sqdecw x0, #21 // CHECK-INST: sqdecw x0, #21 // CHECK-ENCODING: [0xa0,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fa b0 04 sqdecw x0, #22 // CHECK-INST: sqdecw x0, #22 // CHECK-ENCODING: [0xc0,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fa b0 04 sqdecw x0, #23 // CHECK-INST: sqdecw x0, #23 // CHECK-ENCODING: [0xe0,0xfa,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fa b0 04 sqdecw x0, #24 // CHECK-INST: sqdecw x0, #24 // CHECK-ENCODING: [0x00,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fb b0 04 sqdecw x0, #25 // CHECK-INST: sqdecw x0, #25 // CHECK-ENCODING: [0x20,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fb b0 04 sqdecw x0, #26 // CHECK-INST: sqdecw x0, #26 // CHECK-ENCODING: [0x40,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fb b0 04 sqdecw x0, #27 // CHECK-INST: sqdecw x0, #27 // CHECK-ENCODING: [0x60,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fb b0 04 sqdecw x0, #28 // CHECK-INST: sqdecw x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fb b0 04 @@ -304,35 +304,35 @@ sqdecw x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecw z0.s // CHECK-INST: sqdecw z0.s // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cb a0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecw z0.s, pow2, mul #16 // CHECK-INST: sqdecw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc8,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 af 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqdecw z0.s, pow2 // CHECK-INST: sqdecw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc8,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c8 a0 04 diff --git a/llvm/test/MC/AArch64/SVE/sqincb.s b/llvm/test/MC/AArch64/SVE/sqincb.s index 19858c518e299..2ad48e3035366 100644 --- a/llvm/test/MC/AArch64/SVE/sqincb.s +++ b/llvm/test/MC/AArch64/SVE/sqincb.s @@ -16,25 +16,25 @@ sqincb x0 // CHECK-INST: sqincb x0 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 30 04 sqincb x0, all // CHECK-INST: sqincb x0 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 30 04 sqincb x0, all, mul #1 // CHECK-INST: sqincb x0 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 30 04 sqincb x0, all, mul #16 // CHECK-INST: sqincb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 3f 04 @@ -45,37 +45,37 @@ sqincb x0, all, mul #16 sqincb x0, w0 // CHECK-INST: sqincb x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 20 04 sqincb x0, w0, all // CHECK-INST: sqincb x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 20 04 sqincb x0, w0, all, mul #1 // CHECK-INST: sqincb x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 20 04 sqincb x0, w0, all, mul #16 // CHECK-INST: sqincb x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 2f 04 sqincb x0, w0, pow2 // CHECK-INST: sqincb x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf0,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 20 04 sqincb x0, w0, pow2, mul #16 // CHECK-INST: sqincb x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf0,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 2f 04 @@ -86,174 +86,174 @@ sqincb x0, w0, pow2, mul #16 sqincb x0, pow2 // CHECK-INST: sqincb x0, pow2 // CHECK-ENCODING: [0x00,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 30 04 sqincb x0, vl1 // CHECK-INST: sqincb x0, vl1 // CHECK-ENCODING: [0x20,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f0 30 04 sqincb x0, vl2 // CHECK-INST: sqincb x0, vl2 // CHECK-ENCODING: [0x40,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f0 30 04 sqincb x0, vl3 // CHECK-INST: sqincb x0, vl3 // CHECK-ENCODING: [0x60,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f0 30 04 sqincb x0, vl4 // CHECK-INST: sqincb x0, vl4 // CHECK-ENCODING: [0x80,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f0 30 04 sqincb x0, vl5 // CHECK-INST: sqincb x0, vl5 // CHECK-ENCODING: [0xa0,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f0 30 04 sqincb x0, vl6 // CHECK-INST: sqincb x0, vl6 // CHECK-ENCODING: [0xc0,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f0 30 04 sqincb x0, vl7 // CHECK-INST: sqincb x0, vl7 // CHECK-ENCODING: [0xe0,0xf0,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f0 30 04 sqincb x0, vl8 // CHECK-INST: sqincb x0, vl8 // CHECK-ENCODING: [0x00,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f1 30 04 sqincb x0, vl16 // CHECK-INST: sqincb x0, vl16 // CHECK-ENCODING: [0x20,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f1 30 04 sqincb x0, vl32 // CHECK-INST: sqincb x0, vl32 // CHECK-ENCODING: [0x40,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f1 30 04 sqincb x0, vl64 // CHECK-INST: sqincb x0, vl64 // CHECK-ENCODING: [0x60,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f1 30 04 sqincb x0, vl128 // CHECK-INST: sqincb x0, vl128 // CHECK-ENCODING: [0x80,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f1 30 04 sqincb x0, vl256 // CHECK-INST: sqincb x0, vl256 // CHECK-ENCODING: [0xa0,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f1 30 04 sqincb x0, #14 // CHECK-INST: sqincb x0, #14 // CHECK-ENCODING: [0xc0,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f1 30 04 sqincb x0, #15 // CHECK-INST: sqincb x0, #15 // CHECK-ENCODING: [0xe0,0xf1,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f1 30 04 sqincb x0, #16 // CHECK-INST: sqincb x0, #16 // CHECK-ENCODING: [0x00,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f2 30 04 sqincb x0, #17 // CHECK-INST: sqincb x0, #17 // CHECK-ENCODING: [0x20,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f2 30 04 sqincb x0, #18 // CHECK-INST: sqincb x0, #18 // CHECK-ENCODING: [0x40,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f2 30 04 sqincb x0, #19 // CHECK-INST: sqincb x0, #19 // CHECK-ENCODING: [0x60,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f2 30 04 sqincb x0, #20 // CHECK-INST: sqincb x0, #20 // CHECK-ENCODING: [0x80,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f2 30 04 sqincb x0, #21 // CHECK-INST: sqincb x0, #21 // CHECK-ENCODING: [0xa0,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f2 30 04 sqincb x0, #22 // CHECK-INST: sqincb x0, #22 // CHECK-ENCODING: [0xc0,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f2 30 04 sqincb x0, #23 // CHECK-INST: sqincb x0, #23 // CHECK-ENCODING: [0xe0,0xf2,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f2 30 04 sqincb x0, #24 // CHECK-INST: sqincb x0, #24 // CHECK-ENCODING: [0x00,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f3 30 04 sqincb x0, #25 // CHECK-INST: sqincb x0, #25 // CHECK-ENCODING: [0x20,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f3 30 04 sqincb x0, #26 // CHECK-INST: sqincb x0, #26 // CHECK-ENCODING: [0x40,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f3 30 04 sqincb x0, #27 // CHECK-INST: sqincb x0, #27 // CHECK-ENCODING: [0x60,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f3 30 04 sqincb x0, #28 // CHECK-INST: sqincb x0, #28 // CHECK-ENCODING: [0x80,0xf3,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f3 30 04 diff --git a/llvm/test/MC/AArch64/SVE/sqincd.s b/llvm/test/MC/AArch64/SVE/sqincd.s index a59879b3800a7..1dd8b62c32c2b 100644 --- a/llvm/test/MC/AArch64/SVE/sqincd.s +++ b/llvm/test/MC/AArch64/SVE/sqincd.s @@ -16,25 +16,25 @@ sqincd x0 // CHECK-INST: sqincd x0 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 f0 04 sqincd x0, all // CHECK-INST: sqincd x0 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 f0 04 sqincd x0, all, mul #1 // CHECK-INST: sqincd x0 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 f0 04 sqincd x0, all, mul #16 // CHECK-INST: sqincd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 ff 04 @@ -45,37 +45,37 @@ sqincd x0, all, mul #16 sqincd x0, w0 // CHECK-INST: sqincd x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 e0 04 sqincd x0, w0, all // CHECK-INST: sqincd x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 e0 04 sqincd x0, w0, all, mul #1 // CHECK-INST: sqincd x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 e0 04 sqincd x0, w0, all, mul #16 // CHECK-INST: sqincd x0, w0, all // CHECK-ENCODING: [0xe0,0xf3,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 ef 04 sqincd x0, w0, pow2 // CHECK-INST: sqincd x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf0,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 e0 04 sqincd x0, w0, pow2, mul #16 // CHECK-INST: sqincd x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf0,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 ef 04 @@ -85,37 +85,37 @@ sqincd x0, w0, pow2, mul #16 sqincd z0.d // CHECK-INST: sqincd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 e0 04 sqincd z0.d, all // CHECK-INST: sqincd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 e0 04 sqincd z0.d, all, mul #1 // CHECK-INST: sqincd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 e0 04 sqincd z0.d, all, mul #16 // CHECK-INST: sqincd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 ef 04 sqincd z0.d, pow2 // CHECK-INST: sqincd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e0 04 sqincd z0.d, pow2, mul #16 // CHECK-INST: sqincd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 ef 04 @@ -126,175 +126,175 @@ sqincd z0.d, pow2, mul #16 sqincd x0, pow2 // CHECK-INST: sqincd x0, pow2 // CHECK-ENCODING: [0x00,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 f0 04 sqincd x0, vl1 // CHECK-INST: sqincd x0, vl1 // CHECK-ENCODING: [0x20,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f0 f0 04 sqincd x0, vl2 // CHECK-INST: sqincd x0, vl2 // CHECK-ENCODING: [0x40,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f0 f0 04 sqincd x0, vl3 // CHECK-INST: sqincd x0, vl3 // CHECK-ENCODING: [0x60,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f0 f0 04 sqincd x0, vl4 // CHECK-INST: sqincd x0, vl4 // CHECK-ENCODING: [0x80,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f0 f0 04 sqincd x0, vl5 // CHECK-INST: sqincd x0, vl5 // CHECK-ENCODING: [0xa0,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f0 f0 04 sqincd x0, vl6 // CHECK-INST: sqincd x0, vl6 // CHECK-ENCODING: [0xc0,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f0 f0 04 sqincd x0, vl7 // CHECK-INST: sqincd x0, vl7 // CHECK-ENCODING: [0xe0,0xf0,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f0 f0 04 sqincd x0, vl8 // CHECK-INST: sqincd x0, vl8 // CHECK-ENCODING: [0x00,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f1 f0 04 sqincd x0, vl16 // CHECK-INST: sqincd x0, vl16 // CHECK-ENCODING: [0x20,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f1 f0 04 sqincd x0, vl32 // CHECK-INST: sqincd x0, vl32 // CHECK-ENCODING: [0x40,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f1 f0 04 sqincd x0, vl64 // CHECK-INST: sqincd x0, vl64 // CHECK-ENCODING: [0x60,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f1 f0 04 sqincd x0, vl128 // CHECK-INST: sqincd x0, vl128 // CHECK-ENCODING: [0x80,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f1 f0 04 sqincd x0, vl256 // CHECK-INST: sqincd x0, vl256 // CHECK-ENCODING: [0xa0,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f1 f0 04 sqincd x0, #14 // CHECK-INST: sqincd x0, #14 // CHECK-ENCODING: [0xc0,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f1 f0 04 sqincd x0, #15 // CHECK-INST: sqincd x0, #15 // CHECK-ENCODING: [0xe0,0xf1,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f1 f0 04 sqincd x0, #16 // CHECK-INST: sqincd x0, #16 // CHECK-ENCODING: [0x00,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f2 f0 04 sqincd x0, #17 // CHECK-INST: sqincd x0, #17 // CHECK-ENCODING: [0x20,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f2 f0 04 sqincd x0, #18 // CHECK-INST: sqincd x0, #18 // CHECK-ENCODING: [0x40,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f2 f0 04 sqincd x0, #19 // CHECK-INST: sqincd x0, #19 // CHECK-ENCODING: [0x60,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f2 f0 04 sqincd x0, #20 // CHECK-INST: sqincd x0, #20 // CHECK-ENCODING: [0x80,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f2 f0 04 sqincd x0, #21 // CHECK-INST: sqincd x0, #21 // CHECK-ENCODING: [0xa0,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f2 f0 04 sqincd x0, #22 // CHECK-INST: sqincd x0, #22 // CHECK-ENCODING: [0xc0,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f2 f0 04 sqincd x0, #23 // CHECK-INST: sqincd x0, #23 // CHECK-ENCODING: [0xe0,0xf2,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f2 f0 04 sqincd x0, #24 // CHECK-INST: sqincd x0, #24 // CHECK-ENCODING: [0x00,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f3 f0 04 sqincd x0, #25 // CHECK-INST: sqincd x0, #25 // CHECK-ENCODING: [0x20,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f3 f0 04 sqincd x0, #26 // CHECK-INST: sqincd x0, #26 // CHECK-ENCODING: [0x40,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f3 f0 04 sqincd x0, #27 // CHECK-INST: sqincd x0, #27 // CHECK-ENCODING: [0x60,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f3 f0 04 sqincd x0, #28 // CHECK-INST: sqincd x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f3 f0 04 @@ -304,35 +304,35 @@ sqincd x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincd z0.d // CHECK-INST: sqincd z0.d // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 e0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincd z0.d, pow2, mul #16 // CHECK-INST: sqincd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 ef 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincd z0.d, pow2 // CHECK-INST: sqincd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e0 04 diff --git a/llvm/test/MC/AArch64/SVE/sqinch.s b/llvm/test/MC/AArch64/SVE/sqinch.s index e96d1c555f694..aeae6791491ba 100644 --- a/llvm/test/MC/AArch64/SVE/sqinch.s +++ b/llvm/test/MC/AArch64/SVE/sqinch.s @@ -16,25 +16,25 @@ sqinch x0 // CHECK-INST: sqinch x0 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 70 04 sqinch x0, all // CHECK-INST: sqinch x0 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 70 04 sqinch x0, all, mul #1 // CHECK-INST: sqinch x0 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 70 04 sqinch x0, all, mul #16 // CHECK-INST: sqinch x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 7f 04 @@ -45,37 +45,37 @@ sqinch x0, all, mul #16 sqinch x0, w0 // CHECK-INST: sqinch x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 60 04 sqinch x0, w0, all // CHECK-INST: sqinch x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 60 04 sqinch x0, w0, all, mul #1 // CHECK-INST: sqinch x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 60 04 sqinch x0, w0, all, mul #16 // CHECK-INST: sqinch x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 6f 04 sqinch x0, w0, pow2 // CHECK-INST: sqinch x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf0,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 60 04 sqinch x0, w0, pow2, mul #16 // CHECK-INST: sqinch x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf0,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 6f 04 @@ -85,37 +85,37 @@ sqinch x0, w0, pow2, mul #16 sqinch z0.h // CHECK-INST: sqinch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 60 04 sqinch z0.h, all // CHECK-INST: sqinch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 60 04 sqinch z0.h, all, mul #1 // CHECK-INST: sqinch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 60 04 sqinch z0.h, all, mul #16 // CHECK-INST: sqinch z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 6f 04 sqinch z0.h, pow2 // CHECK-INST: sqinch z0.h, pow2 // CHECK-ENCODING: [0x00,0xc0,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 60 04 sqinch z0.h, pow2, mul #16 // CHECK-INST: sqinch z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 6f 04 @@ -126,175 +126,175 @@ sqinch z0.h, pow2, mul #16 sqinch x0, pow2 // CHECK-INST: sqinch x0, pow2 // CHECK-ENCODING: [0x00,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 70 04 sqinch x0, vl1 // CHECK-INST: sqinch x0, vl1 // CHECK-ENCODING: [0x20,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f0 70 04 sqinch x0, vl2 // CHECK-INST: sqinch x0, vl2 // CHECK-ENCODING: [0x40,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f0 70 04 sqinch x0, vl3 // CHECK-INST: sqinch x0, vl3 // CHECK-ENCODING: [0x60,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f0 70 04 sqinch x0, vl4 // CHECK-INST: sqinch x0, vl4 // CHECK-ENCODING: [0x80,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f0 70 04 sqinch x0, vl5 // CHECK-INST: sqinch x0, vl5 // CHECK-ENCODING: [0xa0,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f0 70 04 sqinch x0, vl6 // CHECK-INST: sqinch x0, vl6 // CHECK-ENCODING: [0xc0,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f0 70 04 sqinch x0, vl7 // CHECK-INST: sqinch x0, vl7 // CHECK-ENCODING: [0xe0,0xf0,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f0 70 04 sqinch x0, vl8 // CHECK-INST: sqinch x0, vl8 // CHECK-ENCODING: [0x00,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f1 70 04 sqinch x0, vl16 // CHECK-INST: sqinch x0, vl16 // CHECK-ENCODING: [0x20,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f1 70 04 sqinch x0, vl32 // CHECK-INST: sqinch x0, vl32 // CHECK-ENCODING: [0x40,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f1 70 04 sqinch x0, vl64 // CHECK-INST: sqinch x0, vl64 // CHECK-ENCODING: [0x60,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f1 70 04 sqinch x0, vl128 // CHECK-INST: sqinch x0, vl128 // CHECK-ENCODING: [0x80,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f1 70 04 sqinch x0, vl256 // CHECK-INST: sqinch x0, vl256 // CHECK-ENCODING: [0xa0,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f1 70 04 sqinch x0, #14 // CHECK-INST: sqinch x0, #14 // CHECK-ENCODING: [0xc0,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f1 70 04 sqinch x0, #15 // CHECK-INST: sqinch x0, #15 // CHECK-ENCODING: [0xe0,0xf1,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f1 70 04 sqinch x0, #16 // CHECK-INST: sqinch x0, #16 // CHECK-ENCODING: [0x00,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f2 70 04 sqinch x0, #17 // CHECK-INST: sqinch x0, #17 // CHECK-ENCODING: [0x20,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f2 70 04 sqinch x0, #18 // CHECK-INST: sqinch x0, #18 // CHECK-ENCODING: [0x40,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f2 70 04 sqinch x0, #19 // CHECK-INST: sqinch x0, #19 // CHECK-ENCODING: [0x60,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f2 70 04 sqinch x0, #20 // CHECK-INST: sqinch x0, #20 // CHECK-ENCODING: [0x80,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f2 70 04 sqinch x0, #21 // CHECK-INST: sqinch x0, #21 // CHECK-ENCODING: [0xa0,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f2 70 04 sqinch x0, #22 // CHECK-INST: sqinch x0, #22 // CHECK-ENCODING: [0xc0,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f2 70 04 sqinch x0, #23 // CHECK-INST: sqinch x0, #23 // CHECK-ENCODING: [0xe0,0xf2,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f2 70 04 sqinch x0, #24 // CHECK-INST: sqinch x0, #24 // CHECK-ENCODING: [0x00,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f3 70 04 sqinch x0, #25 // CHECK-INST: sqinch x0, #25 // CHECK-ENCODING: [0x20,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f3 70 04 sqinch x0, #26 // CHECK-INST: sqinch x0, #26 // CHECK-ENCODING: [0x40,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f3 70 04 sqinch x0, #27 // CHECK-INST: sqinch x0, #27 // CHECK-ENCODING: [0x60,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f3 70 04 sqinch x0, #28 // CHECK-INST: sqinch x0, #28 // CHECK-ENCODING: [0x80,0xf3,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f3 70 04 @@ -304,35 +304,35 @@ sqinch x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqinch z0.h // CHECK-INST: sqinch z0.h // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 60 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqinch z0.h, pow2, mul #16 // CHECK-INST: sqinch z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 6f 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqinch z0.h, pow2 // CHECK-INST: sqinch z0.h, pow2 // CHECK-ENCODING: [0x00,0xc0,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 60 04 diff --git a/llvm/test/MC/AArch64/SVE/sqincp.s b/llvm/test/MC/AArch64/SVE/sqincp.s index 69ef677bf6ca9..f8f279e40de4c 100644 --- a/llvm/test/MC/AArch64/SVE/sqincp.s +++ b/llvm/test/MC/AArch64/SVE/sqincp.s @@ -12,85 +12,85 @@ sqincp x0, p0.b // CHECK-INST: sqincp x0, p0.b // CHECK-ENCODING: [0x00,0x8c,0x28,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 28 25 sqincp x0, p0.h // CHECK-INST: sqincp x0, p0.h // CHECK-ENCODING: [0x00,0x8c,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 68 25 sqincp x0, p0.s // CHECK-INST: sqincp x0, p0.s // CHECK-ENCODING: [0x00,0x8c,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c a8 25 sqincp x0, p0.d // CHECK-INST: sqincp x0, p0.d // CHECK-ENCODING: [0x00,0x8c,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c e8 25 sqincp xzr, p15.b, wzr // CHECK-INST: sqincp xzr, p15.b, wzr // CHECK-ENCODING: [0xff,0x89,0x28,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 28 25 sqincp xzr, p15.h, wzr // CHECK-INST: sqincp xzr, p15.h, wzr // CHECK-ENCODING: [0xff,0x89,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 68 25 sqincp xzr, p15.s, wzr // CHECK-INST: sqincp xzr, p15.s, wzr // CHECK-ENCODING: [0xff,0x89,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 a8 25 sqincp xzr, p15.d, wzr // CHECK-INST: sqincp xzr, p15.d, wzr // CHECK-ENCODING: [0xff,0x89,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 e8 25 sqincp z0.h, p0 // CHECK-INST: sqincp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 68 25 sqincp z0.h, p0.h // CHECK-INST: sqincp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x68,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 68 25 sqincp z0.s, p0 // CHECK-INST: sqincp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a8 25 sqincp z0.s, p0.s // CHECK-INST: sqincp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xa8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a8 25 sqincp z0.d, p0 // CHECK-INST: sqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e8 25 sqincp z0.d, p0.d // CHECK-INST: sqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e8 25 @@ -100,11 +100,11 @@ sqincp z0.d, p0.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincp z0.d, p0.d // CHECK-INST: sqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe8,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e8 25 diff --git a/llvm/test/MC/AArch64/SVE/sqincw.s b/llvm/test/MC/AArch64/SVE/sqincw.s index b71860c69fffd..c602ba1a28672 100644 --- a/llvm/test/MC/AArch64/SVE/sqincw.s +++ b/llvm/test/MC/AArch64/SVE/sqincw.s @@ -16,25 +16,25 @@ sqincw x0 // CHECK-INST: sqincw x0 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 b0 04 sqincw x0, all // CHECK-INST: sqincw x0 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 b0 04 sqincw x0, all, mul #1 // CHECK-INST: sqincw x0 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 b0 04 sqincw x0, all, mul #16 // CHECK-INST: sqincw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 bf 04 @@ -45,37 +45,37 @@ sqincw x0, all, mul #16 sqincw x0, w0 // CHECK-INST: sqincw x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 a0 04 sqincw x0, w0, all // CHECK-INST: sqincw x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 a0 04 sqincw x0, w0, all, mul #1 // CHECK-INST: sqincw x0, w0 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 a0 04 sqincw x0, w0, all, mul #16 // CHECK-INST: sqincw x0, w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f3 af 04 sqincw x0, w0, pow2 // CHECK-INST: sqincw x0, w0, pow2 // CHECK-ENCODING: [0x00,0xf0,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 a0 04 sqincw x0, w0, pow2, mul #16 // CHECK-INST: sqincw x0, w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf0,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 af 04 @@ -85,37 +85,37 @@ sqincw x0, w0, pow2, mul #16 sqincw z0.s // CHECK-INST: sqincw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 a0 04 sqincw z0.s, all // CHECK-INST: sqincw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 a0 04 sqincw z0.s, all, mul #1 // CHECK-INST: sqincw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 a0 04 sqincw z0.s, all, mul #16 // CHECK-INST: sqincw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xc3,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 af 04 sqincw z0.s, pow2 // CHECK-INST: sqincw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a0 04 sqincw z0.s, pow2, mul #16 // CHECK-INST: sqincw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 af 04 @@ -126,175 +126,175 @@ sqincw z0.s, pow2, mul #16 sqincw x0, pow2 // CHECK-INST: sqincw x0, pow2 // CHECK-ENCODING: [0x00,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f0 b0 04 sqincw x0, vl1 // CHECK-INST: sqincw x0, vl1 // CHECK-ENCODING: [0x20,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f0 b0 04 sqincw x0, vl2 // CHECK-INST: sqincw x0, vl2 // CHECK-ENCODING: [0x40,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f0 b0 04 sqincw x0, vl3 // CHECK-INST: sqincw x0, vl3 // CHECK-ENCODING: [0x60,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f0 b0 04 sqincw x0, vl4 // CHECK-INST: sqincw x0, vl4 // CHECK-ENCODING: [0x80,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f0 b0 04 sqincw x0, vl5 // CHECK-INST: sqincw x0, vl5 // CHECK-ENCODING: [0xa0,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f0 b0 04 sqincw x0, vl6 // CHECK-INST: sqincw x0, vl6 // CHECK-ENCODING: [0xc0,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f0 b0 04 sqincw x0, vl7 // CHECK-INST: sqincw x0, vl7 // CHECK-ENCODING: [0xe0,0xf0,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f0 b0 04 sqincw x0, vl8 // CHECK-INST: sqincw x0, vl8 // CHECK-ENCODING: [0x00,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f1 b0 04 sqincw x0, vl16 // CHECK-INST: sqincw x0, vl16 // CHECK-ENCODING: [0x20,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f1 b0 04 sqincw x0, vl32 // CHECK-INST: sqincw x0, vl32 // CHECK-ENCODING: [0x40,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f1 b0 04 sqincw x0, vl64 // CHECK-INST: sqincw x0, vl64 // CHECK-ENCODING: [0x60,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f1 b0 04 sqincw x0, vl128 // CHECK-INST: sqincw x0, vl128 // CHECK-ENCODING: [0x80,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f1 b0 04 sqincw x0, vl256 // CHECK-INST: sqincw x0, vl256 // CHECK-ENCODING: [0xa0,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f1 b0 04 sqincw x0, #14 // CHECK-INST: sqincw x0, #14 // CHECK-ENCODING: [0xc0,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f1 b0 04 sqincw x0, #15 // CHECK-INST: sqincw x0, #15 // CHECK-ENCODING: [0xe0,0xf1,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f1 b0 04 sqincw x0, #16 // CHECK-INST: sqincw x0, #16 // CHECK-ENCODING: [0x00,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f2 b0 04 sqincw x0, #17 // CHECK-INST: sqincw x0, #17 // CHECK-ENCODING: [0x20,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f2 b0 04 sqincw x0, #18 // CHECK-INST: sqincw x0, #18 // CHECK-ENCODING: [0x40,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f2 b0 04 sqincw x0, #19 // CHECK-INST: sqincw x0, #19 // CHECK-ENCODING: [0x60,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f2 b0 04 sqincw x0, #20 // CHECK-INST: sqincw x0, #20 // CHECK-ENCODING: [0x80,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f2 b0 04 sqincw x0, #21 // CHECK-INST: sqincw x0, #21 // CHECK-ENCODING: [0xa0,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f2 b0 04 sqincw x0, #22 // CHECK-INST: sqincw x0, #22 // CHECK-ENCODING: [0xc0,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f2 b0 04 sqincw x0, #23 // CHECK-INST: sqincw x0, #23 // CHECK-ENCODING: [0xe0,0xf2,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f2 b0 04 sqincw x0, #24 // CHECK-INST: sqincw x0, #24 // CHECK-ENCODING: [0x00,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f3 b0 04 sqincw x0, #25 // CHECK-INST: sqincw x0, #25 // CHECK-ENCODING: [0x20,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f3 b0 04 sqincw x0, #26 // CHECK-INST: sqincw x0, #26 // CHECK-ENCODING: [0x40,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f3 b0 04 sqincw x0, #27 // CHECK-INST: sqincw x0, #27 // CHECK-ENCODING: [0x60,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f3 b0 04 sqincw x0, #28 // CHECK-INST: sqincw x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f3 b0 04 @@ -304,35 +304,35 @@ sqincw x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincw z0.s // CHECK-INST: sqincw z0.s // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c3 a0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincw z0.s, pow2, mul #16 // CHECK-INST: sqincw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 af 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqincw z0.s, pow2 // CHECK-INST: sqincw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a0 04 diff --git a/llvm/test/MC/AArch64/SVE/sqsub.s b/llvm/test/MC/AArch64/SVE/sqsub.s index fa183bc8ab50a..88ade7e1f160b 100644 --- a/llvm/test/MC/AArch64/SVE/sqsub.s +++ b/llvm/test/MC/AArch64/SVE/sqsub.s @@ -13,109 +13,109 @@ sqsub z0.b, z0.b, z0.b // CHECK-INST: sqsub z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x18,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 18 20 04 sqsub z0.h, z0.h, z0.h // CHECK-INST: sqsub z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x18,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 18 60 04 sqsub z0.s, z0.s, z0.s // CHECK-INST: sqsub z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x18,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 18 a0 04 sqsub z0.d, z0.d, z0.d // CHECK-INST: sqsub z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x18,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 18 e0 04 sqsub z0.b, z0.b, #0 // CHECK-INST: sqsub z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x26,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 26 25 sqsub z31.b, z31.b, #255 // CHECK-INST: sqsub z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x26,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 26 25 sqsub z0.h, z0.h, #0 // CHECK-INST: sqsub z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x66,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 66 25 sqsub z0.h, z0.h, #0, lsl #8 // CHECK-INST: sqsub z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x66,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 66 25 sqsub z31.h, z31.h, #255, lsl #8 // CHECK-INST: sqsub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x66,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 66 25 sqsub z31.h, z31.h, #65280 // CHECK-INST: sqsub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x66,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 66 25 sqsub z0.s, z0.s, #0 // CHECK-INST: sqsub z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a6 25 sqsub z0.s, z0.s, #0, lsl #8 // CHECK-INST: sqsub z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a6 25 sqsub z31.s, z31.s, #255, lsl #8 // CHECK-INST: sqsub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a6 25 sqsub z31.s, z31.s, #65280 // CHECK-INST: sqsub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a6 25 sqsub z0.d, z0.d, #0 // CHECK-INST: sqsub z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e6 25 sqsub z0.d, z0.d, #0, lsl #8 // CHECK-INST: sqsub z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e6 25 sqsub z31.d, z31.d, #255, lsl #8 // CHECK-INST: sqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e6 25 sqsub z31.d, z31.d, #65280 // CHECK-INST: sqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e6 25 @@ -125,11 +125,11 @@ sqsub z31.d, z31.d, #65280 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqsub z31.d, z31.d, #65280 // CHECK-INST: sqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e6 25 diff --git a/llvm/test/MC/AArch64/SVE/st1b.s b/llvm/test/MC/AArch64/SVE/st1b.s index c65979f9900f7..c221652794da2 100644 --- a/llvm/test/MC/AArch64/SVE/st1b.s +++ b/llvm/test/MC/AArch64/SVE/st1b.s @@ -12,119 +12,119 @@ st1b z0.b, p0, [x0] // CHECK-INST: st1b { z0.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 e4 st1b z0.h, p0, [x0] // CHECK-INST: st1b { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 20 e4 st1b z0.s, p0, [x0] // CHECK-INST: st1b { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 e4 st1b z0.d, p0, [x0] // CHECK-INST: st1b { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 e4 st1b { z0.b }, p0, [x0] // CHECK-INST: st1b { z0.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 00 e4 st1b { z0.h }, p0, [x0] // CHECK-INST: st1b { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 20 e4 st1b { z0.s }, p0, [x0] // CHECK-INST: st1b { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 e4 st1b { z0.d }, p0, [x0] // CHECK-INST: st1b { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 e4 st1b { z31.b }, p7, [sp, #-1, mul vl] // CHECK-INST: st1b { z31.b }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x0f,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 0f e4 st1b { z21.b }, p5, [x10, #5, mul vl] // CHECK-INST: st1b { z21.b }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x05,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 05 e4 st1b { z31.h }, p7, [sp, #-1, mul vl] // CHECK-INST: st1b { z31.h }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x2f,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 2f e4 st1b { z21.h }, p5, [x10, #5, mul vl] // CHECK-INST: st1b { z21.h }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x25,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 25 e4 st1b { z31.s }, p7, [sp, #-1, mul vl] // CHECK-INST: st1b { z31.s }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x4f,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 4f e4 st1b { z21.s }, p5, [x10, #5, mul vl] // CHECK-INST: st1b { z21.s }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x45,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 45 e4 st1b { z31.d }, p7, [sp, #-1, mul vl] // CHECK-INST: st1b { z31.d }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x6f,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 6f e4 st1b { z21.d }, p5, [x10, #5, mul vl] // CHECK-INST: st1b { z21.d }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x65,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 65 e4 st1b { z0.b }, p0, [x0, x0] // CHECK-INST: st1b { z0.b }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x00,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 00 e4 st1b { z0.h }, p0, [x0, x0] // CHECK-INST: st1b { z0.h }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x20,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 20 e4 st1b { z0.s }, p0, [x0, x0] // CHECK-INST: st1b { z0.s }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x40,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 40 e4 st1b { z0.d }, p0, [x0, x0] // CHECK-INST: st1b { z0.d }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x40,0x60,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 e4 diff --git a/llvm/test/MC/AArch64/SVE/st1d.s b/llvm/test/MC/AArch64/SVE/st1d.s index 884a7a56a64f5..2f2911c14afa5 100644 --- a/llvm/test/MC/AArch64/SVE/st1d.s +++ b/llvm/test/MC/AArch64/SVE/st1d.s @@ -12,29 +12,29 @@ st1d z0.d, p0, [x0] // CHECK-INST: st1d { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 e5 st1d { z0.d }, p0, [x0] // CHECK-INST: st1d { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 e5 st1d { z31.d }, p7, [sp, #-1, mul vl] // CHECK-INST: st1d { z31.d }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0xef,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ef e5 st1d { z21.d }, p5, [x10, #5, mul vl] // CHECK-INST: st1d { z21.d }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 e5 e5 st1d { z0.d }, p0, [x0, x0, lsl #3] // CHECK-INST: st1d { z0.d }, p0, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x40,0xe0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 e5 diff --git a/llvm/test/MC/AArch64/SVE/st1h.s b/llvm/test/MC/AArch64/SVE/st1h.s index 035621e35b218..18ca96d5975e7 100644 --- a/llvm/test/MC/AArch64/SVE/st1h.s +++ b/llvm/test/MC/AArch64/SVE/st1h.s @@ -12,89 +12,89 @@ st1h z0.h, p0, [x0] // CHECK-INST: st1h { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xa0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 e4 st1h z0.s, p0, [x0] // CHECK-INST: st1h { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 e4 st1h z0.d, p0, [x0] // CHECK-INST: st1h { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 e4 st1h { z0.h }, p0, [x0] // CHECK-INST: st1h { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xa0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a0 e4 st1h { z0.s }, p0, [x0] // CHECK-INST: st1h { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xc0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 c0 e4 st1h { z0.d }, p0, [x0] // CHECK-INST: st1h { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e0 e4 st1h { z31.h }, p7, [sp, #-1, mul vl] // CHECK-INST: st1h { z31.h }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0xaf,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff af e4 st1h { z21.h }, p5, [x10, #5, mul vl] // CHECK-INST: st1h { z21.h }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xa5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 a5 e4 st1h { z31.s }, p7, [sp, #-1, mul vl] // CHECK-INST: st1h { z31.s }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0xcf,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff cf e4 st1h { z21.s }, p5, [x10, #5, mul vl] // CHECK-INST: st1h { z21.s }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xc5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 c5 e4 st1h { z21.d }, p5, [x10, #5, mul vl] // CHECK-INST: st1h { z21.d }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 e5 e4 st1h { z31.d }, p7, [sp, #-1, mul vl] // CHECK-INST: st1h { z31.d }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0xef,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff ef e4 st1h { z0.h }, p0, [x0, x0, lsl #1] // CHECK-INST: st1h { z0.h }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x40,0xa0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 a0 e4 st1h { z0.s }, p0, [x0, x0, lsl #1] // CHECK-INST: st1h { z0.s }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x40,0xc0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 c0 e4 st1h { z0.d }, p0, [x0, x0, lsl #1] // CHECK-INST: st1h { z0.d }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x40,0xe0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 e4 diff --git a/llvm/test/MC/AArch64/SVE/st1w.s b/llvm/test/MC/AArch64/SVE/st1w.s index 1ca2200979b48..503c7fe82db76 100644 --- a/llvm/test/MC/AArch64/SVE/st1w.s +++ b/llvm/test/MC/AArch64/SVE/st1w.s @@ -12,59 +12,59 @@ st1w z0.s, p0, [x0] // CHECK-INST: st1w { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 e5 st1w z0.d, p0, [x0] // CHECK-INST: st1w { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 e5 st1w { z0.s }, p0, [x0] // CHECK-INST: st1w { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 40 e5 st1w { z0.d }, p0, [x0] // CHECK-INST: st1w { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 60 e5 st1w { z31.s }, p7, [sp, #-1, mul vl] // CHECK-INST: st1w { z31.s }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x4f,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 4f e5 st1w { z21.s }, p5, [x10, #5, mul vl] // CHECK-INST: st1w { z21.s }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x45,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 45 e5 st1w { z31.d }, p7, [sp, #-1, mul vl] // CHECK-INST: st1w { z31.d }, p7, [sp, #-1, mul vl] // CHECK-ENCODING: [0xff,0xff,0x6f,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 6f e5 st1w { z21.d }, p5, [x10, #5, mul vl] // CHECK-INST: st1w { z21.d }, p5, [x10, #5, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x65,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 65 e5 st1w { z0.s }, p0, [x0, x0, lsl #2] // CHECK-INST: st1w { z0.s }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x40,0x40,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 40 e5 st1w { z0.d }, p0, [x0, x0, lsl #2] // CHECK-INST: st1w { z0.d }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x40,0x60,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 e5 diff --git a/llvm/test/MC/AArch64/SVE/st2b.s b/llvm/test/MC/AArch64/SVE/st2b.s index 2294c3daf23eb..c8e45eabcf6b0 100644 --- a/llvm/test/MC/AArch64/SVE/st2b.s +++ b/llvm/test/MC/AArch64/SVE/st2b.s @@ -12,29 +12,29 @@ st2b { z0.b, z1.b }, p0, [x0, x0] // CHECK-INST: st2b { z0.b, z1.b }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x60,0x20,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 20 e4 st2b { z5.b, z6.b }, p3, [x17, x16] // CHECK-INST: st2b { z5.b, z6.b }, p3, [x17, x16] // CHECK-ENCODING: [0x25,0x6e,0x30,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 30 e4 st2b { z0.b, z1.b }, p0, [x0] // CHECK-INST: st2b { z0.b, z1.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x30,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 30 e4 st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl] // CHECK-INST: st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x38,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 38 e4 st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] // CHECK-INST: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x35,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 35 e4 diff --git a/llvm/test/MC/AArch64/SVE/st2d.s b/llvm/test/MC/AArch64/SVE/st2d.s index e8c973b4bc509..afe72786feacb 100644 --- a/llvm/test/MC/AArch64/SVE/st2d.s +++ b/llvm/test/MC/AArch64/SVE/st2d.s @@ -12,29 +12,29 @@ st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3] // CHECK-INST: st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x60,0xa0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 a0 e5 st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3] // CHECK-INST: st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0x6e,0xb0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e b0 e5 st2d { z0.d, z1.d }, p0, [x0] // CHECK-INST: st2d { z0.d, z1.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 b0 e5 st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl] // CHECK-INST: st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xb8,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed b8 e5 st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] // CHECK-INST: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xb5,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 b5 e5 diff --git a/llvm/test/MC/AArch64/SVE/st2h.s b/llvm/test/MC/AArch64/SVE/st2h.s index 8f4034be72438..c60b0acf70c50 100644 --- a/llvm/test/MC/AArch64/SVE/st2h.s +++ b/llvm/test/MC/AArch64/SVE/st2h.s @@ -12,29 +12,29 @@ st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1] // CHECK-INST: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x60,0xa0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 a0 e4 st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1] // CHECK-INST: st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0x6e,0xb0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e b0 e4 st2h { z0.h, z1.h }, p0, [x0] // CHECK-INST: st2h { z0.h, z1.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 b0 e4 st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl] // CHECK-INST: st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xb8,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed b8 e4 st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] // CHECK-INST: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xb5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 b5 e4 diff --git a/llvm/test/MC/AArch64/SVE/st2w.s b/llvm/test/MC/AArch64/SVE/st2w.s index 2e18d440b188e..1407cd2600d97 100644 --- a/llvm/test/MC/AArch64/SVE/st2w.s +++ b/llvm/test/MC/AArch64/SVE/st2w.s @@ -12,29 +12,29 @@ st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2] // CHECK-INST: st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x60,0x20,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 20 e5 st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2] // CHECK-INST: st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0x6e,0x30,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 30 e5 st2w { z0.s, z1.s }, p0, [x0] // CHECK-INST: st2w { z0.s, z1.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x30,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 30 e5 st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl] // CHECK-INST: st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x38,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 38 e5 st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] // CHECK-INST: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x35,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 35 e5 diff --git a/llvm/test/MC/AArch64/SVE/st3b.s b/llvm/test/MC/AArch64/SVE/st3b.s index 3aabf5c298e18..7331e8cb21dd4 100644 --- a/llvm/test/MC/AArch64/SVE/st3b.s +++ b/llvm/test/MC/AArch64/SVE/st3b.s @@ -12,29 +12,29 @@ st3b { z0.b, z1.b, z2.b }, p0, [x0, x0] // CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x60,0x40,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 40 e4 st3b { z5.b, z6.b, z7.b }, p3, [x17, x16] // CHECK-INST: st3b { z5.b, z6.b, z7.b }, p3, [x17, x16] // CHECK-ENCODING: [0x25,0x6e,0x50,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 50 e4 st3b { z0.b, z1.b, z2.b }, p0, [x0] // CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x50,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 50 e4 st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl] // CHECK-INST: st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x58,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 58 e4 st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] // CHECK-INST: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x55,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 55 e4 diff --git a/llvm/test/MC/AArch64/SVE/st3d.s b/llvm/test/MC/AArch64/SVE/st3d.s index 688024508e24f..0ea0fb8ca53c2 100644 --- a/llvm/test/MC/AArch64/SVE/st3d.s +++ b/llvm/test/MC/AArch64/SVE/st3d.s @@ -12,29 +12,29 @@ st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3] // CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x60,0xc0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 c0 e5 st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3] // CHECK-INST: st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e d0 e5 st3d { z0.d, z1.d, z2.d }, p0, [x0] // CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 d0 e5 st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl] // CHECK-INST: st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed d8 e5 st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] // CHECK-INST: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 d5 e5 diff --git a/llvm/test/MC/AArch64/SVE/st3h.s b/llvm/test/MC/AArch64/SVE/st3h.s index a9724e83be614..a5edb651c6408 100644 --- a/llvm/test/MC/AArch64/SVE/st3h.s +++ b/llvm/test/MC/AArch64/SVE/st3h.s @@ -12,29 +12,29 @@ st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1] // CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x60,0xc0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 c0 e4 st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1] // CHECK-INST: st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e d0 e4 st3h { z0.h, z1.h, z2.h }, p0, [x0] // CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 d0 e4 st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl] // CHECK-INST: st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed d8 e4 st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] // CHECK-INST: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 d5 e4 diff --git a/llvm/test/MC/AArch64/SVE/st3w.s b/llvm/test/MC/AArch64/SVE/st3w.s index f10336f7f7211..d106184ba135d 100644 --- a/llvm/test/MC/AArch64/SVE/st3w.s +++ b/llvm/test/MC/AArch64/SVE/st3w.s @@ -12,29 +12,29 @@ st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2] // CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x60,0x40,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 40 e5 st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2] // CHECK-INST: st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0x6e,0x50,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 50 e5 st3w { z0.s, z1.s, z2.s }, p0, [x0] // CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x50,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 50 e5 st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl] // CHECK-INST: st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x58,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 58 e5 st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] // CHECK-INST: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x55,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 55 e5 diff --git a/llvm/test/MC/AArch64/SVE/st4b.s b/llvm/test/MC/AArch64/SVE/st4b.s index 10c0c86e9270e..ea270f42cce69 100644 --- a/llvm/test/MC/AArch64/SVE/st4b.s +++ b/llvm/test/MC/AArch64/SVE/st4b.s @@ -12,29 +12,29 @@ st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0] // CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x60,0x60,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 60 e4 st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16] // CHECK-INST: st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16] // CHECK-ENCODING: [0x25,0x6e,0x70,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 70 e4 st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] // CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x70,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 70 e4 st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl] // CHECK-INST: st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x78,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 78 e4 st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] // CHECK-INST: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x75,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 75 e4 diff --git a/llvm/test/MC/AArch64/SVE/st4d.s b/llvm/test/MC/AArch64/SVE/st4d.s index c0431c2807430..dab7d40bf0347 100644 --- a/llvm/test/MC/AArch64/SVE/st4d.s +++ b/llvm/test/MC/AArch64/SVE/st4d.s @@ -12,29 +12,29 @@ st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3] // CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x60,0xe0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 e0 e5 st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3] // CHECK-INST: st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3] // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e f0 e5 st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] // CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 f0 e5 st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl] // CHECK-INST: st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed f8 e5 st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] // CHECK-INST: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 f5 e5 diff --git a/llvm/test/MC/AArch64/SVE/st4h.s b/llvm/test/MC/AArch64/SVE/st4h.s index 64861380a93e2..cd1c17e6d8990 100644 --- a/llvm/test/MC/AArch64/SVE/st4h.s +++ b/llvm/test/MC/AArch64/SVE/st4h.s @@ -12,29 +12,29 @@ st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1] // CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x60,0xe0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 e0 e4 st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1] // CHECK-INST: st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1] // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e f0 e4 st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] // CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 f0 e4 st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl] // CHECK-INST: st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed f8 e4 st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] // CHECK-INST: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 f5 e4 diff --git a/llvm/test/MC/AArch64/SVE/st4w.s b/llvm/test/MC/AArch64/SVE/st4w.s index b4e1b08585cbe..4a05eb604ac3f 100644 --- a/llvm/test/MC/AArch64/SVE/st4w.s +++ b/llvm/test/MC/AArch64/SVE/st4w.s @@ -12,29 +12,29 @@ st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2] // CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x60,0x60,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 60 e5 st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2] // CHECK-INST: st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2] // CHECK-ENCODING: [0x25,0x6e,0x70,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 25 6e 70 e5 st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] // CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x70,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 70 e5 st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl] // CHECK-INST: st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x78,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 78 e5 st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] // CHECK-INST: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x75,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 75 e5 diff --git a/llvm/test/MC/AArch64/SVE/stnt1b.s b/llvm/test/MC/AArch64/SVE/stnt1b.s index 044d5ccc538d3..bb75df59f78c7 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1b.s +++ b/llvm/test/MC/AArch64/SVE/stnt1b.s @@ -12,29 +12,29 @@ stnt1b z0.b, p0, [x0] // CHECK-INST: stnt1b { z0.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x10,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 10 e4 stnt1b { z0.b }, p0, [x0] // CHECK-INST: stnt1b { z0.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x10,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 10 e4 stnt1b { z23.b }, p3, [x13, #-8, mul vl] // CHECK-INST: stnt1b { z23.b }, p3, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x18,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 18 e4 stnt1b { z21.b }, p5, [x10, #7, mul vl] // CHECK-INST: stnt1b { z21.b }, p5, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x17,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 17 e4 stnt1b { z0.b }, p0, [x0, x0] // CHECK-INST: stnt1b { z0.b }, p0, [x0, x0] // CHECK-ENCODING: [0x00,0x60,0x00,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 00 e4 diff --git a/llvm/test/MC/AArch64/SVE/stnt1d.s b/llvm/test/MC/AArch64/SVE/stnt1d.s index 1f85df8c142f0..467d2d753d2ce 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1d.s +++ b/llvm/test/MC/AArch64/SVE/stnt1d.s @@ -12,29 +12,29 @@ stnt1d z0.d, p0, [x0] // CHECK-INST: stnt1d { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x90,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 90 e5 stnt1d { z0.d }, p0, [x0] // CHECK-INST: stnt1d { z0.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x90,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 90 e5 stnt1d { z23.d }, p3, [x13, #-8, mul vl] // CHECK-INST: stnt1d { z23.d }, p3, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x98,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 98 e5 stnt1d { z21.d }, p5, [x10, #7, mul vl] // CHECK-INST: stnt1d { z21.d }, p5, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x97,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 97 e5 stnt1d { z0.d }, p0, [x0, x0, lsl #3] // CHECK-INST: stnt1d { z0.d }, p0, [x0, x0, lsl #3] // CHECK-ENCODING: [0x00,0x60,0x80,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 80 e5 diff --git a/llvm/test/MC/AArch64/SVE/stnt1h.s b/llvm/test/MC/AArch64/SVE/stnt1h.s index 8862b9c5fd75e..c98076e982dc4 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1h.s +++ b/llvm/test/MC/AArch64/SVE/stnt1h.s @@ -12,29 +12,29 @@ stnt1h z0.h, p0, [x0] // CHECK-INST: stnt1h { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x90,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 90 e4 stnt1h { z0.h }, p0, [x0] // CHECK-INST: stnt1h { z0.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x90,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 90 e4 stnt1h { z23.h }, p3, [x13, #-8, mul vl] // CHECK-INST: stnt1h { z23.h }, p3, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x98,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 98 e4 stnt1h { z21.h }, p5, [x10, #7, mul vl] // CHECK-INST: stnt1h { z21.h }, p5, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x97,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 97 e4 stnt1h { z0.h }, p0, [x0, x0, lsl #1] // CHECK-INST: stnt1h { z0.h }, p0, [x0, x0, lsl #1] // CHECK-ENCODING: [0x00,0x60,0x80,0xe4] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 80 e4 diff --git a/llvm/test/MC/AArch64/SVE/stnt1w.s b/llvm/test/MC/AArch64/SVE/stnt1w.s index 2bf56c15bfa46..bdde90686822e 100644 --- a/llvm/test/MC/AArch64/SVE/stnt1w.s +++ b/llvm/test/MC/AArch64/SVE/stnt1w.s @@ -12,29 +12,29 @@ stnt1w z0.s, p0, [x0] // CHECK-INST: stnt1w { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x10,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 10 e5 stnt1w { z0.s }, p0, [x0] // CHECK-INST: stnt1w { z0.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x10,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 10 e5 stnt1w { z23.s }, p3, [x13, #-8, mul vl] // CHECK-INST: stnt1w { z23.s }, p3, [x13, #-8, mul vl] // CHECK-ENCODING: [0xb7,0xed,0x18,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 ed 18 e5 stnt1w { z21.s }, p5, [x10, #7, mul vl] // CHECK-INST: stnt1w { z21.s }, p5, [x10, #7, mul vl] // CHECK-ENCODING: [0x55,0xf5,0x17,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 f5 17 e5 stnt1w { z0.s }, p0, [x0, x0, lsl #2] // CHECK-INST: stnt1w { z0.s }, p0, [x0, x0, lsl #2] // CHECK-ENCODING: [0x00,0x60,0x00,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 00 e5 diff --git a/llvm/test/MC/AArch64/SVE/str.s b/llvm/test/MC/AArch64/SVE/str.s index 476ace3ef6837..0294a52b81aed 100644 --- a/llvm/test/MC/AArch64/SVE/str.s +++ b/llvm/test/MC/AArch64/SVE/str.s @@ -12,35 +12,35 @@ str z0, [x0] // CHECK-INST: str z0, [x0] // CHECK-ENCODING: [0x00,0x40,0x80,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 80 e5 str z21, [x10, #-256, mul vl] // CHECK-INST: str z21, [x10, #-256, mul vl] // CHECK-ENCODING: [0x55,0x41,0xa0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 41 a0 e5 str z31, [sp, #255, mul vl] // CHECK-INST: str z31, [sp, #255, mul vl] // CHECK-ENCODING: [0xff,0x5f,0x9f,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 5f 9f e5 str p0, [x0] // CHECK-INST: str p0, [x0] // CHECK-ENCODING: [0x00,0x00,0x80,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 80 e5 str p15, [sp, #-256, mul vl] // CHECK-INST: str p15, [sp, #-256, mul vl] // CHECK-ENCODING: [0xef,0x03,0xa0,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 03 a0 e5 str p5, [x10, #255, mul vl] // CHECK-INST: str p5, [x10, #255, mul vl] // CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 45 1d 9f e5 diff --git a/llvm/test/MC/AArch64/SVE/sub.s b/llvm/test/MC/AArch64/SVE/sub.s index 67071e6910521..7a63915635787 100644 --- a/llvm/test/MC/AArch64/SVE/sub.s +++ b/llvm/test/MC/AArch64/SVE/sub.s @@ -12,193 +12,193 @@ sub z0.h, z0.h, z0.h // CHECK-INST: sub z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x04,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 04 60 04 sub z21.b, z10.b, z21.b // CHECK-INST: sub z21.b, z10.b, z21.b // CHECK-ENCODING: [0x55,0x05,0x35,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 05 35 04 sub z31.d, p7/m, z31.d, z31.d // CHECK-INST: sub z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f c1 04 sub z23.h, p3/m, z23.h, z13.h // CHECK-INST: sub z23.h, p3/m, z23.h, z13.h // CHECK-ENCODING: [0xb7,0x0d,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 41 04 sub z31.h, z31.h, z31.h // CHECK-INST: sub z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x07,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 07 7f 04 sub z21.h, z10.h, z21.h // CHECK-INST: sub z21.h, z10.h, z21.h // CHECK-ENCODING: [0x55,0x05,0x75,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 05 75 04 sub z31.b, z31.b, z31.b // CHECK-INST: sub z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x07,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 07 3f 04 sub z0.s, z0.s, z0.s // CHECK-INST: sub z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x04,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 04 a0 04 sub z23.s, p3/m, z23.s, z13.s // CHECK-INST: sub z23.s, p3/m, z23.s, z13.s // CHECK-ENCODING: [0xb7,0x0d,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 81 04 sub z23.b, z13.b, z8.b // CHECK-INST: sub z23.b, z13.b, z8.b // CHECK-ENCODING: [0xb7,0x05,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 05 28 04 sub z21.d, z10.d, z21.d // CHECK-INST: sub z21.d, z10.d, z21.d // CHECK-ENCODING: [0x55,0x05,0xf5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 05 f5 04 sub z21.s, z10.s, z21.s // CHECK-INST: sub z21.s, z10.s, z21.s // CHECK-ENCODING: [0x55,0x05,0xb5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 05 b5 04 sub z21.s, p5/m, z21.s, z10.s // CHECK-INST: sub z21.s, p5/m, z21.s, z10.s // CHECK-ENCODING: [0x55,0x15,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 81 04 sub z31.s, p7/m, z31.s, z31.s // CHECK-INST: sub z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 81 04 sub z0.d, p0/m, z0.d, z0.d // CHECK-INST: sub z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c1 04 sub z0.b, z0.b, z0.b // CHECK-INST: sub z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x04,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 04 20 04 sub z23.d, z13.d, z8.d // CHECK-INST: sub z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x05,0xe8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 05 e8 04 sub z23.d, p3/m, z23.d, z13.d // CHECK-INST: sub z23.d, p3/m, z23.d, z13.d // CHECK-ENCODING: [0xb7,0x0d,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d c1 04 sub z23.s, z13.s, z8.s // CHECK-INST: sub z23.s, z13.s, z8.s // CHECK-ENCODING: [0xb7,0x05,0xa8,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 05 a8 04 sub z31.b, p7/m, z31.b, z31.b // CHECK-INST: sub z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 01 04 sub z0.h, p0/m, z0.h, z0.h // CHECK-INST: sub z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 41 04 sub z31.d, z31.d, z31.d // CHECK-INST: sub z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x07,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 07 ff 04 sub z31.h, p7/m, z31.h, z31.h // CHECK-INST: sub z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 41 04 sub z23.h, z13.h, z8.h // CHECK-INST: sub z23.h, z13.h, z8.h // CHECK-ENCODING: [0xb7,0x05,0x68,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 05 68 04 sub z21.b, p5/m, z21.b, z10.b // CHECK-INST: sub z21.b, p5/m, z21.b, z10.b // CHECK-ENCODING: [0x55,0x15,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 01 04 sub z21.d, p5/m, z21.d, z10.d // CHECK-INST: sub z21.d, p5/m, z21.d, z10.d // CHECK-ENCODING: [0x55,0x15,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 c1 04 sub z0.d, z0.d, z0.d // CHECK-INST: sub z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x04,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 04 e0 04 sub z31.s, z31.s, z31.s // CHECK-INST: sub z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x07,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 07 bf 04 sub z0.b, p0/m, z0.b, z0.b // CHECK-INST: sub z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 01 04 sub z0.s, p0/m, z0.s, z0.s // CHECK-INST: sub z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 81 04 sub z21.h, p5/m, z21.h, z10.h // CHECK-INST: sub z21.h, p5/m, z21.h, z10.h // CHECK-ENCODING: [0x55,0x15,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 55 15 41 04 sub z23.b, p3/m, z23.b, z13.b // CHECK-INST: sub z23.b, p3/m, z23.b, z13.b // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 01 04 // ----------------------- @@ -207,85 +207,85 @@ sub z23.b, p3/m, z23.b, z13.b sub z0.b, z0.b, #0 // CHECK-INST: sub z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x21,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 21 25 sub z31.b, z31.b, #255 // CHECK-INST: sub z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x21,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 21 25 sub z0.h, z0.h, #0 // CHECK-INST: sub z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x61,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 61 25 sub z0.h, z0.h, #0, lsl #8 // CHECK-INST: sub z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x61,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 61 25 sub z31.h, z31.h, #255, lsl #8 // CHECK-INST: sub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x61,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 61 25 sub z31.h, z31.h, #65280 // CHECK-INST: sub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x61,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 61 25 sub z0.s, z0.s, #0 // CHECK-INST: sub z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a1 25 sub z0.s, z0.s, #0, lsl #8 // CHECK-INST: sub z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a1 25 sub z31.s, z31.s, #255, lsl #8 // CHECK-INST: sub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a1 25 sub z31.s, z31.s, #65280 // CHECK-INST: sub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a1 25 sub z0.d, z0.d, #0 // CHECK-INST: sub z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e1 25 sub z0.d, z0.d, #0, lsl #8 // CHECK-INST: sub z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e1 25 sub z31.d, z31.d, #255, lsl #8 // CHECK-INST: sub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e1 25 sub z31.d, z31.d, #65280 // CHECK-INST: sub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e1 25 @@ -296,35 +296,35 @@ sub z31.d, z31.d, #65280 movprfx z23.b, p3/z, z30.b // CHECK-INST: movprfx z23.b, p3/z, z30.b // CHECK-ENCODING: [0xd7,0x2f,0x10,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: d7 2f 10 04 sub z23.b, p3/m, z23.b, z13.b // CHECK-INST: sub z23.b, p3/m, z23.b, z13.b // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 01 04 movprfx z23, z30 // CHECK-INST: movprfx z23, z30 // CHECK-ENCODING: [0xd7,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: d7 bf 20 04 sub z23.b, p3/m, z23.b, z13.b // CHECK-INST: sub z23.b, p3/m, z23.b, z13.b // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 0d 01 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sub z31.d, z31.d, #65280 // CHECK-INST: sub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e1 25 diff --git a/llvm/test/MC/AArch64/SVE/subr.s b/llvm/test/MC/AArch64/SVE/subr.s index 65201aa414807..b433bd2559dc5 100644 --- a/llvm/test/MC/AArch64/SVE/subr.s +++ b/llvm/test/MC/AArch64/SVE/subr.s @@ -13,109 +13,109 @@ subr z0.b, p0/m, z0.b, z0.b // CHECK-INST: subr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x03,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 03 04 subr z0.h, p0/m, z0.h, z0.h // CHECK-INST: subr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x43,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 43 04 subr z0.s, p0/m, z0.s, z0.s // CHECK-INST: subr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0x83,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 83 04 subr z0.d, p0/m, z0.d, z0.d // CHECK-INST: subr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 00 c3 04 subr z0.b, z0.b, #0 // CHECK-INST: subr z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x23,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 23 25 subr z31.b, z31.b, #255 // CHECK-INST: subr z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x23,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 23 25 subr z0.h, z0.h, #0 // CHECK-INST: subr z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x63,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 63 25 subr z0.h, z0.h, #0, lsl #8 // CHECK-INST: subr z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x63,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 63 25 subr z31.h, z31.h, #255, lsl #8 // CHECK-INST: subr z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x63,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 63 25 subr z31.h, z31.h, #65280 // CHECK-INST: subr z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x63,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 63 25 subr z0.s, z0.s, #0 // CHECK-INST: subr z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a3 25 subr z0.s, z0.s, #0, lsl #8 // CHECK-INST: subr z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a3 25 subr z31.s, z31.s, #255, lsl #8 // CHECK-INST: subr z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a3 25 subr z31.s, z31.s, #65280 // CHECK-INST: subr z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a3 25 subr z0.d, z0.d, #0 // CHECK-INST: subr z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e3 25 subr z0.d, z0.d, #0, lsl #8 // CHECK-INST: subr z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e3 25 subr z31.d, z31.d, #255, lsl #8 // CHECK-INST: subr z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e3 25 subr z31.d, z31.d, #65280 // CHECK-INST: subr z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e3 25 @@ -125,35 +125,35 @@ subr z31.d, z31.d, #65280 movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 subr z5.d, p0/m, z5.d, z0.d // CHECK-INST: subr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x00,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 00 c3 04 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 subr z5.d, p0/m, z5.d, z0.d // CHECK-INST: subr z5.d, p0/m, z5.d, z0.d // CHECK-ENCODING: [0x05,0x00,0xc3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 00 c3 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 subr z31.d, z31.d, #65280 // CHECK-INST: subr z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e3 25 diff --git a/llvm/test/MC/AArch64/SVE/sunpkhi.s b/llvm/test/MC/AArch64/SVE/sunpkhi.s index fa4f67c5c943a..7d122c07c4eef 100644 --- a/llvm/test/MC/AArch64/SVE/sunpkhi.s +++ b/llvm/test/MC/AArch64/SVE/sunpkhi.s @@ -12,17 +12,17 @@ sunpkhi z31.h, z31.b // CHECK-INST: sunpkhi z31.h, z31.b // CHECK-ENCODING: [0xff,0x3b,0x71,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 71 05 sunpkhi z31.s, z31.h // CHECK-INST: sunpkhi z31.s, z31.h // CHECK-ENCODING: [0xff,0x3b,0xb1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b b1 05 sunpkhi z31.d, z31.s // CHECK-INST: sunpkhi z31.d, z31.s // CHECK-ENCODING: [0xff,0x3b,0xf1,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b f1 05 diff --git a/llvm/test/MC/AArch64/SVE/sunpklo.s b/llvm/test/MC/AArch64/SVE/sunpklo.s index 2106753d20c60..3dbfbbf87bd58 100644 --- a/llvm/test/MC/AArch64/SVE/sunpklo.s +++ b/llvm/test/MC/AArch64/SVE/sunpklo.s @@ -12,17 +12,17 @@ sunpklo z31.h, z31.b // CHECK-INST: sunpklo z31.h, z31.b // CHECK-ENCODING: [0xff,0x3b,0x70,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 70 05 sunpklo z31.s, z31.h // CHECK-INST: sunpklo z31.s, z31.h // CHECK-ENCODING: [0xff,0x3b,0xb0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b b0 05 sunpklo z31.d, z31.s // CHECK-INST: sunpklo z31.d, z31.s // CHECK-ENCODING: [0xff,0x3b,0xf0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b f0 05 diff --git a/llvm/test/MC/AArch64/SVE/sxtb.s b/llvm/test/MC/AArch64/SVE/sxtb.s index e4b391a57df24..17694b4b3eae7 100644 --- a/llvm/test/MC/AArch64/SVE/sxtb.s +++ b/llvm/test/MC/AArch64/SVE/sxtb.s @@ -12,37 +12,37 @@ sxtb z0.h, p0/m, z0.h // CHECK-INST: sxtb z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x50,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 50 04 sxtb z0.s, p0/m, z0.s // CHECK-INST: sxtb z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 90 04 sxtb z0.d, p0/m, z0.d // CHECK-INST: sxtb z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d0 04 sxtb z31.h, p7/m, z31.h // CHECK-INST: sxtb z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x50,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 50 04 sxtb z31.s, p7/m, z31.s // CHECK-INST: sxtb z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 90 04 sxtb z31.d, p7/m, z31.d // CHECK-INST: sxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d0 04 @@ -52,23 +52,23 @@ sxtb z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 sxtb z4.d, p7/m, z31.d // CHECK-INST: sxtb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d0 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sxtb z4.d, p7/m, z31.d // CHECK-INST: sxtb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d0 04 diff --git a/llvm/test/MC/AArch64/SVE/sxth.s b/llvm/test/MC/AArch64/SVE/sxth.s index 83ce9981097e9..a90f8338835e8 100644 --- a/llvm/test/MC/AArch64/SVE/sxth.s +++ b/llvm/test/MC/AArch64/SVE/sxth.s @@ -12,25 +12,25 @@ sxth z0.s, p0/m, z0.s // CHECK-INST: sxth z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x92,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 92 04 sxth z0.d, p0/m, z0.d // CHECK-INST: sxth z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d2 04 sxth z31.s, p7/m, z31.s // CHECK-INST: sxth z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x92,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 92 04 sxth z31.d, p7/m, z31.d // CHECK-INST: sxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d2 04 @@ -40,23 +40,23 @@ sxth z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 sxth z4.d, p7/m, z31.d // CHECK-INST: sxth z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d2 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sxth z4.d, p7/m, z31.d // CHECK-INST: sxth z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d2 04 diff --git a/llvm/test/MC/AArch64/SVE/sxtw.s b/llvm/test/MC/AArch64/SVE/sxtw.s index bd4c291f67b30..5c40fe3caa725 100644 --- a/llvm/test/MC/AArch64/SVE/sxtw.s +++ b/llvm/test/MC/AArch64/SVE/sxtw.s @@ -12,13 +12,13 @@ sxtw z0.d, p0/m, z0.d // CHECK-INST: sxtw z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d4 04 sxtw z31.d, p7/m, z31.d // CHECK-INST: sxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d4 04 @@ -28,23 +28,23 @@ sxtw z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 sxtw z4.d, p7/m, z31.d // CHECK-INST: sxtw z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d4 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sxtw z4.d, p7/m, z31.d // CHECK-INST: sxtw z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d4 04 diff --git a/llvm/test/MC/AArch64/SVE/tbl.s b/llvm/test/MC/AArch64/SVE/tbl.s index bbd692eab45db..bbfbdceb11be4 100644 --- a/llvm/test/MC/AArch64/SVE/tbl.s +++ b/llvm/test/MC/AArch64/SVE/tbl.s @@ -12,47 +12,47 @@ tbl z31.b, z31.b, z31.b // CHECK-INST: tbl z31.b, { z31.b }, z31.b // CHECK-ENCODING: [0xff,0x33,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 3f 05 tbl z31.h, z31.h, z31.h // CHECK-INST: tbl z31.h, { z31.h }, z31.h // CHECK-ENCODING: [0xff,0x33,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 7f 05 tbl z31.s, z31.s, z31.s // CHECK-INST: tbl z31.s, { z31.s }, z31.s // CHECK-ENCODING: [0xff,0x33,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 bf 05 tbl z31.d, z31.d, z31.d // CHECK-INST: tbl z31.d, { z31.d }, z31.d // CHECK-ENCODING: [0xff,0x33,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 ff 05 tbl z31.b, { z31.b }, z31.b // CHECK-INST: tbl z31.b, { z31.b }, z31.b // CHECK-ENCODING: [0xff,0x33,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 3f 05 tbl z31.h, { z31.h }, z31.h // CHECK-INST: tbl z31.h, { z31.h }, z31.h // CHECK-ENCODING: [0xff,0x33,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 7f 05 tbl z31.s, { z31.s }, z31.s // CHECK-INST: tbl z31.s, { z31.s }, z31.s // CHECK-ENCODING: [0xff,0x33,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 bf 05 tbl z31.d, { z31.d }, z31.d // CHECK-INST: tbl z31.d, { z31.d }, z31.d // CHECK-ENCODING: [0xff,0x33,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 33 ff 05 diff --git a/llvm/test/MC/AArch64/SVE/trn1.s b/llvm/test/MC/AArch64/SVE/trn1.s index 623cb3e5dd08d..e573ad85901e6 100644 --- a/llvm/test/MC/AArch64/SVE/trn1.s +++ b/llvm/test/MC/AArch64/SVE/trn1.s @@ -12,47 +12,47 @@ trn1 z31.b, z31.b, z31.b // CHECK-INST: trn1 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x73,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 73 3f 05 trn1 z31.h, z31.h, z31.h // CHECK-INST: trn1 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x73,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 73 7f 05 trn1 z31.s, z31.s, z31.s // CHECK-INST: trn1 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x73,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 73 bf 05 trn1 z31.d, z31.d, z31.d // CHECK-INST: trn1 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x73,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 73 ff 05 trn1 p15.b, p15.b, p15.b // CHECK-INST: trn1 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x51,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 51 2f 05 trn1 p15.s, p15.s, p15.s // CHECK-INST: trn1 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x51,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 51 af 05 trn1 p15.h, p15.h, p15.h // CHECK-INST: trn1 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x51,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 51 6f 05 trn1 p15.d, p15.d, p15.d // CHECK-INST: trn1 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x51,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 51 ef 05 diff --git a/llvm/test/MC/AArch64/SVE/trn2.s b/llvm/test/MC/AArch64/SVE/trn2.s index 4b73b9053e878..9ae60ffb99f96 100644 --- a/llvm/test/MC/AArch64/SVE/trn2.s +++ b/llvm/test/MC/AArch64/SVE/trn2.s @@ -12,47 +12,47 @@ trn2 z31.b, z31.b, z31.b // CHECK-INST: trn2 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x77,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 77 3f 05 trn2 z31.h, z31.h, z31.h // CHECK-INST: trn2 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x77,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 77 7f 05 trn2 z31.s, z31.s, z31.s // CHECK-INST: trn2 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x77,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 77 bf 05 trn2 z31.d, z31.d, z31.d // CHECK-INST: trn2 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x77,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 77 ff 05 trn2 p15.b, p15.b, p15.b // CHECK-INST: trn2 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x55,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 55 2f 05 trn2 p15.s, p15.s, p15.s // CHECK-INST: trn2 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x55,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 55 af 05 trn2 p15.h, p15.h, p15.h // CHECK-INST: trn2 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x55,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 55 6f 05 trn2 p15.d, p15.d, p15.d // CHECK-INST: trn2 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x55,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 55 ef 05 diff --git a/llvm/test/MC/AArch64/SVE/uabd.s b/llvm/test/MC/AArch64/SVE/uabd.s index b8ac9d8fc4e54..39745f9f09b3c 100644 --- a/llvm/test/MC/AArch64/SVE/uabd.s +++ b/llvm/test/MC/AArch64/SVE/uabd.s @@ -12,25 +12,25 @@ uabd z31.b, p7/m, z31.b, z31.b // CHECK-INST: uabd z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x0d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 0d 04 uabd z31.h, p7/m, z31.h, z31.h // CHECK-INST: uabd z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x4d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 4d 04 uabd z31.s, p7/m, z31.s, z31.s // CHECK-INST: uabd z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x8d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 8d 04 uabd z31.d, p7/m, z31.d, z31.d // CHECK-INST: uabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f cd 04 @@ -40,23 +40,23 @@ uabd z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 uabd z4.d, p7/m, z4.d, z31.d // CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cd 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 uabd z4.d, p7/m, z4.d, z31.d // CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cd 04 diff --git a/llvm/test/MC/AArch64/SVE/uaddv.s b/llvm/test/MC/AArch64/SVE/uaddv.s index 2d9e26f601b33..449c6dc4f85c0 100644 --- a/llvm/test/MC/AArch64/SVE/uaddv.s +++ b/llvm/test/MC/AArch64/SVE/uaddv.s @@ -12,23 +12,23 @@ uaddv d0, p7, z31.b // CHECK-INST: uaddv d0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x01,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 01 04 uaddv d0, p7, z31.h // CHECK-INST: uaddv d0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x41,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 41 04 uaddv d0, p7, z31.s // CHECK-INST: uaddv d0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x81,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 81 04 uaddv d0, p7, z31.d // CHECK-INST: uaddv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c1 04 diff --git a/llvm/test/MC/AArch64/SVE/ucvtf.s b/llvm/test/MC/AArch64/SVE/ucvtf.s index 231e9d900a0bb..7b380eda0997b 100644 --- a/llvm/test/MC/AArch64/SVE/ucvtf.s +++ b/llvm/test/MC/AArch64/SVE/ucvtf.s @@ -12,43 +12,43 @@ ucvtf z0.h, p0/m, z0.h // CHECK-INST: ucvtf z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x53,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 53 65 ucvtf z0.h, p0/m, z0.s // CHECK-INST: ucvtf z0.h, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x55,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 55 65 ucvtf z0.h, p0/m, z0.d // CHECK-INST: ucvtf z0.h, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0x57,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 57 65 ucvtf z0.s, p0/m, z0.s // CHECK-INST: ucvtf z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x95,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 95 65 ucvtf z0.s, p0/m, z0.d // CHECK-INST: ucvtf z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd5,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d5 65 ucvtf z0.d, p0/m, z0.s // CHECK-INST: ucvtf z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xd1,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d1 65 ucvtf z0.d, p0/m, z0.d // CHECK-INST: ucvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d7 65 @@ -58,23 +58,23 @@ ucvtf z0.d, p0/m, z0.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 ucvtf z5.d, p0/m, z0.d // CHECK-INST: ucvtf z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 d7 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 ucvtf z5.d, p0/m, z0.d // CHECK-INST: ucvtf z5.d, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 05 a0 d7 65 diff --git a/llvm/test/MC/AArch64/SVE/udiv.s b/llvm/test/MC/AArch64/SVE/udiv.s index 3a5aff16ab510..836fe20add50b 100644 --- a/llvm/test/MC/AArch64/SVE/udiv.s +++ b/llvm/test/MC/AArch64/SVE/udiv.s @@ -12,13 +12,13 @@ udiv z0.s, p7/m, z0.s, z31.s // CHECK-INST: udiv z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x95,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 95 04 udiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d5 04 @@ -28,23 +28,23 @@ udiv z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 udiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d5 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 udiv z0.d, p7/m, z0.d, z31.d // CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d5 04 diff --git a/llvm/test/MC/AArch64/SVE/udivr.s b/llvm/test/MC/AArch64/SVE/udivr.s index 4341ca8fcba10..c179d992e99b6 100644 --- a/llvm/test/MC/AArch64/SVE/udivr.s +++ b/llvm/test/MC/AArch64/SVE/udivr.s @@ -12,13 +12,13 @@ udivr z0.s, p7/m, z0.s, z31.s // CHECK-INST: udivr z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x97,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 97 04 udivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d7 04 @@ -28,23 +28,23 @@ udivr z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 udivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d7 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 udivr z0.d, p7/m, z0.d, z31.d // CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d7 04 diff --git a/llvm/test/MC/AArch64/SVE/udot.s b/llvm/test/MC/AArch64/SVE/udot.s index b5584fdc3f770..405457f54d3df 100644 --- a/llvm/test/MC/AArch64/SVE/udot.s +++ b/llvm/test/MC/AArch64/SVE/udot.s @@ -12,25 +12,25 @@ udot z0.s, z1.b, z31.b // CHECK-INST: udot z0.s, z1.b, z31.b // CHECK-ENCODING: [0x20,0x04,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 9f 44 udot z0.d, z1.h, z31.h // CHECK-INST: udot z0.d, z1.h, z31.h // CHECK-ENCODING: [0x20,0x04,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 df 44 udot z0.s, z1.b, z7.b[3] // CHECK-INST: udot z0.s, z1.b, z7.b[3] // CHECK-ENCODING: [0x20,0x04,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 bf 44 udot z0.d, z1.h, z15.h[1] // CHECK-INST: udot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x04,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 ff 44 @@ -40,23 +40,23 @@ udot z0.d, z1.h, z15.h[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 udot z0.d, z1.h, z31.h // CHECK-INST: udot z0.d, z1.h, z31.h // CHECK-ENCODING: [0x20,0x04,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 df 44 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 udot z0.d, z1.h, z15.h[1] // CHECK-INST: udot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x04,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 04 ff 44 diff --git a/llvm/test/MC/AArch64/SVE/umax.s b/llvm/test/MC/AArch64/SVE/umax.s index f1b0d6d7349d2..facb1f94c5a00 100644 --- a/llvm/test/MC/AArch64/SVE/umax.s +++ b/llvm/test/MC/AArch64/SVE/umax.s @@ -12,73 +12,73 @@ umax z0.b, z0.b, #0 // CHECK-INST: umax z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 29 25 umax z31.b, z31.b, #255 // CHECK-INST: umax z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 29 25 umax z0.b, z0.b, #0 // CHECK-INST: umax z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 29 25 umax z31.b, z31.b, #255 // CHECK-INST: umax z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 29 25 umax z0.b, z0.b, #0 // CHECK-INST: umax z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 29 25 umax z31.b, z31.b, #255 // CHECK-INST: umax z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 29 25 umax z0.b, z0.b, #0 // CHECK-INST: umax z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 29 25 umax z31.b, z31.b, #255 // CHECK-INST: umax z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 29 25 umax z31.b, p7/m, z31.b, z31.b // CHECK-INST: umax z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x09,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 09 04 umax z31.h, p7/m, z31.h, z31.h // CHECK-INST: umax z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x49,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 49 04 umax z31.s, p7/m, z31.s, z31.s // CHECK-INST: umax z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x89,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 89 04 umax z31.d, p7/m, z31.d, z31.d // CHECK-INST: umax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f c9 04 @@ -88,35 +88,35 @@ umax z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 umax z4.d, p7/m, z4.d, z31.d // CHECK-INST: umax z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f c9 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 umax z4.d, p7/m, z4.d, z31.d // CHECK-INST: umax z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f c9 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 umax z31.b, z31.b, #255 // CHECK-INST: umax z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 29 25 diff --git a/llvm/test/MC/AArch64/SVE/umaxv.s b/llvm/test/MC/AArch64/SVE/umaxv.s index db02f5e8a2c6e..e9d1d5998512d 100644 --- a/llvm/test/MC/AArch64/SVE/umaxv.s +++ b/llvm/test/MC/AArch64/SVE/umaxv.s @@ -12,23 +12,23 @@ umaxv b0, p7, z31.b // CHECK-INST: umaxv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x09,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 09 04 umaxv h0, p7, z31.h // CHECK-INST: umaxv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x49,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 49 04 umaxv s0, p7, z31.s // CHECK-INST: umaxv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x89,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 89 04 umaxv d0, p7, z31.d // CHECK-INST: umaxv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xc9,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f c9 04 diff --git a/llvm/test/MC/AArch64/SVE/umin.s b/llvm/test/MC/AArch64/SVE/umin.s index 8919d803fb7e9..7fbce57e8a3a0 100644 --- a/llvm/test/MC/AArch64/SVE/umin.s +++ b/llvm/test/MC/AArch64/SVE/umin.s @@ -12,73 +12,73 @@ umin z0.b, z0.b, #0 // CHECK-INST: umin z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 2b 25 umin z31.b, z31.b, #255 // CHECK-INST: umin z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 2b 25 umin z0.b, z0.b, #0 // CHECK-INST: umin z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 2b 25 umin z31.b, z31.b, #255 // CHECK-INST: umin z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 2b 25 umin z0.b, z0.b, #0 // CHECK-INST: umin z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 2b 25 umin z31.b, z31.b, #255 // CHECK-INST: umin z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 2b 25 umin z0.b, z0.b, #0 // CHECK-INST: umin z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 2b 25 umin z31.b, z31.b, #255 // CHECK-INST: umin z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 2b 25 umin z31.b, p7/m, z31.b, z31.b // CHECK-INST: umin z31.b, p7/m, z31.b, z31.b // CHECK-ENCODING: [0xff,0x1f,0x0b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 0b 04 umin z31.h, p7/m, z31.h, z31.h // CHECK-INST: umin z31.h, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xff,0x1f,0x4b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 4b 04 umin z31.s, p7/m, z31.s, z31.s // CHECK-INST: umin z31.s, p7/m, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0x8b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 8b 04 umin z31.d, p7/m, z31.d, z31.d // CHECK-INST: umin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f cb 04 @@ -88,35 +88,35 @@ umin z31.d, p7/m, z31.d, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 umin z4.d, p7/m, z4.d, z31.d // CHECK-INST: umin z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cb 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 umin z4.d, p7/m, z4.d, z31.d // CHECK-INST: umin z4.d, p7/m, z4.d, z31.d // CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 1f cb 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 umin z31.b, z31.b, #255 // CHECK-INST: umin z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 2b 25 diff --git a/llvm/test/MC/AArch64/SVE/uminv.s b/llvm/test/MC/AArch64/SVE/uminv.s index bca8878cb749d..c43833300f58b 100644 --- a/llvm/test/MC/AArch64/SVE/uminv.s +++ b/llvm/test/MC/AArch64/SVE/uminv.s @@ -12,23 +12,23 @@ uminv b0, p7, z31.b // CHECK-INST: uminv b0, p7, z31.b // CHECK-ENCODING: [0xe0,0x3f,0x0b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 0b 04 uminv h0, p7, z31.h // CHECK-INST: uminv h0, p7, z31.h // CHECK-ENCODING: [0xe0,0x3f,0x4b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 4b 04 uminv s0, p7, z31.s // CHECK-INST: uminv s0, p7, z31.s // CHECK-ENCODING: [0xe0,0x3f,0x8b,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f 8b 04 uminv d0, p7, z31.d // CHECK-INST: uminv d0, p7, z31.d // CHECK-ENCODING: [0xe0,0x3f,0xcb,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3f cb 04 diff --git a/llvm/test/MC/AArch64/SVE/umulh.s b/llvm/test/MC/AArch64/SVE/umulh.s index db27c8046e88e..2e9d2a89459da 100644 --- a/llvm/test/MC/AArch64/SVE/umulh.s +++ b/llvm/test/MC/AArch64/SVE/umulh.s @@ -12,25 +12,25 @@ umulh z0.b, p7/m, z0.b, z31.b // CHECK-INST: umulh z0.b, p7/m, z0.b, z31.b // CHECK-ENCODING: [0xe0,0x1f,0x13,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 13 04 umulh z0.h, p7/m, z0.h, z31.h // CHECK-INST: umulh z0.h, p7/m, z0.h, z31.h // CHECK-ENCODING: [0xe0,0x1f,0x53,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 53 04 umulh z0.s, p7/m, z0.s, z31.s // CHECK-INST: umulh z0.s, p7/m, z0.s, z31.s // CHECK-ENCODING: [0xe0,0x1f,0x93,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f 93 04 umulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d3 04 @@ -40,23 +40,23 @@ umulh z0.d, p7/m, z0.d, z31.d movprfx z0.d, p7/z, z7.d // CHECK-INST: movprfx z0.d, p7/z, z7.d // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 3c d0 04 umulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d3 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 umulh z0.d, p7/m, z0.d, z31.d // CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 1f d3 04 diff --git a/llvm/test/MC/AArch64/SVE/uqadd.s b/llvm/test/MC/AArch64/SVE/uqadd.s index 447aca0409733..047c0699dec5a 100644 --- a/llvm/test/MC/AArch64/SVE/uqadd.s +++ b/llvm/test/MC/AArch64/SVE/uqadd.s @@ -13,109 +13,109 @@ uqadd z0.b, z0.b, z0.b // CHECK-INST: uqadd z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x14,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 14 20 04 uqadd z0.h, z0.h, z0.h // CHECK-INST: uqadd z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x14,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 14 60 04 uqadd z0.s, z0.s, z0.s // CHECK-INST: uqadd z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x14,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 14 a0 04 uqadd z0.d, z0.d, z0.d // CHECK-INST: uqadd z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x14,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 14 e0 04 uqadd z0.b, z0.b, #0 // CHECK-INST: uqadd z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x25,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 25 25 uqadd z31.b, z31.b, #255 // CHECK-INST: uqadd z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x25,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 25 25 uqadd z0.h, z0.h, #0 // CHECK-INST: uqadd z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x65,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 65 25 uqadd z0.h, z0.h, #0, lsl #8 // CHECK-INST: uqadd z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x65,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 65 25 uqadd z31.h, z31.h, #255, lsl #8 // CHECK-INST: uqadd z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x65,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 65 25 uqadd z31.h, z31.h, #65280 // CHECK-INST: uqadd z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x65,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 65 25 uqadd z0.s, z0.s, #0 // CHECK-INST: uqadd z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a5 25 uqadd z0.s, z0.s, #0, lsl #8 // CHECK-INST: uqadd z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a5 25 uqadd z31.s, z31.s, #255, lsl #8 // CHECK-INST: uqadd z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a5 25 uqadd z31.s, z31.s, #65280 // CHECK-INST: uqadd z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a5 25 uqadd z0.d, z0.d, #0 // CHECK-INST: uqadd z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e5 25 uqadd z0.d, z0.d, #0, lsl #8 // CHECK-INST: uqadd z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e5 25 uqadd z31.d, z31.d, #255, lsl #8 // CHECK-INST: uqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e5 25 uqadd z31.d, z31.d, #65280 // CHECK-INST: uqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e5 25 @@ -125,11 +125,11 @@ uqadd z31.d, z31.d, #65280 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqadd z31.d, z31.d, #65280 // CHECK-INST: uqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e5 25 diff --git a/llvm/test/MC/AArch64/SVE/uqdecb.s b/llvm/test/MC/AArch64/SVE/uqdecb.s index dc2c09710ba23..10f7f893b5835 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecb.s +++ b/llvm/test/MC/AArch64/SVE/uqdecb.s @@ -16,25 +16,25 @@ uqdecb x0 // CHECK-INST: uqdecb x0 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 30 04 uqdecb x0, all // CHECK-INST: uqdecb x0 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 30 04 uqdecb x0, all, mul #1 // CHECK-INST: uqdecb x0 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 30 04 uqdecb x0, all, mul #16 // CHECK-INST: uqdecb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 3f 04 @@ -45,37 +45,37 @@ uqdecb x0, all, mul #16 uqdecb w0 // CHECK-INST: uqdecb w0 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 20 04 uqdecb w0, all // CHECK-INST: uqdecb w0 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 20 04 uqdecb w0, all, mul #1 // CHECK-INST: uqdecb w0 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 20 04 uqdecb w0, all, mul #16 // CHECK-INST: uqdecb w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 2f 04 uqdecb w0, pow2 // CHECK-INST: uqdecb w0, pow2 // CHECK-ENCODING: [0x00,0xfc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 20 04 uqdecb w0, pow2, mul #16 // CHECK-INST: uqdecb w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xfc,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 2f 04 @@ -86,173 +86,173 @@ uqdecb w0, pow2, mul #16 uqdecb x0, pow2 // CHECK-INST: uqdecb x0, pow2 // CHECK-ENCODING: [0x00,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 30 04 uqdecb x0, vl1 // CHECK-INST: uqdecb x0, vl1 // CHECK-ENCODING: [0x20,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc 30 04 uqdecb x0, vl2 // CHECK-INST: uqdecb x0, vl2 // CHECK-ENCODING: [0x40,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fc 30 04 uqdecb x0, vl3 // CHECK-INST: uqdecb x0, vl3 // CHECK-ENCODING: [0x60,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fc 30 04 uqdecb x0, vl4 // CHECK-INST: uqdecb x0, vl4 // CHECK-ENCODING: [0x80,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fc 30 04 uqdecb x0, vl5 // CHECK-INST: uqdecb x0, vl5 // CHECK-ENCODING: [0xa0,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fc 30 04 uqdecb x0, vl6 // CHECK-INST: uqdecb x0, vl6 // CHECK-ENCODING: [0xc0,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fc 30 04 uqdecb x0, vl7 // CHECK-INST: uqdecb x0, vl7 // CHECK-ENCODING: [0xe0,0xfc,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fc 30 04 uqdecb x0, vl8 // CHECK-INST: uqdecb x0, vl8 // CHECK-ENCODING: [0x00,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fd 30 04 uqdecb x0, vl16 // CHECK-INST: uqdecb x0, vl16 // CHECK-ENCODING: [0x20,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fd 30 04 uqdecb x0, vl32 // CHECK-INST: uqdecb x0, vl32 // CHECK-ENCODING: [0x40,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fd 30 04 uqdecb x0, vl64 // CHECK-INST: uqdecb x0, vl64 // CHECK-ENCODING: [0x60,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fd 30 04 uqdecb x0, vl128 // CHECK-INST: uqdecb x0, vl128 // CHECK-ENCODING: [0x80,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fd 30 04 uqdecb x0, vl256 // CHECK-INST: uqdecb x0, vl256 // CHECK-ENCODING: [0xa0,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fd 30 04 uqdecb x0, #14 // CHECK-INST: uqdecb x0, #14 // CHECK-ENCODING: [0xc0,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fd 30 04 uqdecb x0, #15 // CHECK-INST: uqdecb x0, #15 // CHECK-ENCODING: [0xe0,0xfd,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fd 30 04 uqdecb x0, #16 // CHECK-INST: uqdecb x0, #16 // CHECK-ENCODING: [0x00,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fe 30 04 uqdecb x0, #17 // CHECK-INST: uqdecb x0, #17 // CHECK-ENCODING: [0x20,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fe 30 04 uqdecb x0, #18 // CHECK-INST: uqdecb x0, #18 // CHECK-ENCODING: [0x40,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fe 30 04 uqdecb x0, #19 // CHECK-INST: uqdecb x0, #19 // CHECK-ENCODING: [0x60,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fe 30 04 uqdecb x0, #20 // CHECK-INST: uqdecb x0, #20 // CHECK-ENCODING: [0x80,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fe 30 04 uqdecb x0, #21 // CHECK-INST: uqdecb x0, #21 // CHECK-ENCODING: [0xa0,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fe 30 04 uqdecb x0, #22 // CHECK-INST: uqdecb x0, #22 // CHECK-ENCODING: [0xc0,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fe 30 04 uqdecb x0, #23 // CHECK-INST: uqdecb x0, #23 // CHECK-ENCODING: [0xe0,0xfe,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fe 30 04 uqdecb x0, #24 // CHECK-INST: uqdecb x0, #24 // CHECK-ENCODING: [0x00,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ff 30 04 uqdecb x0, #25 // CHECK-INST: uqdecb x0, #25 // CHECK-ENCODING: [0x20,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ff 30 04 uqdecb x0, #26 // CHECK-INST: uqdecb x0, #26 // CHECK-ENCODING: [0x40,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ff 30 04 uqdecb x0, #27 // CHECK-INST: uqdecb x0, #27 // CHECK-ENCODING: [0x60,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ff 30 04 uqdecb x0, #28 // CHECK-INST: uqdecb x0, #28 // CHECK-ENCODING: [0x80,0xff,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ff 30 04 diff --git a/llvm/test/MC/AArch64/SVE/uqdecd.s b/llvm/test/MC/AArch64/SVE/uqdecd.s index 05341f8ff7ca6..0c13af33f2338 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecd.s +++ b/llvm/test/MC/AArch64/SVE/uqdecd.s @@ -16,25 +16,25 @@ uqdecd x0 // CHECK-INST: uqdecd x0 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff f0 04 uqdecd x0, all // CHECK-INST: uqdecd x0 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff f0 04 uqdecd x0, all, mul #1 // CHECK-INST: uqdecd x0 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff f0 04 uqdecd x0, all, mul #16 // CHECK-INST: uqdecd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff ff 04 @@ -45,37 +45,37 @@ uqdecd x0, all, mul #16 uqdecd w0 // CHECK-INST: uqdecd w0 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff e0 04 uqdecd w0, all // CHECK-INST: uqdecd w0 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff e0 04 uqdecd w0, all, mul #1 // CHECK-INST: uqdecd w0 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff e0 04 uqdecd w0, all, mul #16 // CHECK-INST: uqdecd w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff ef 04 uqdecd w0, pow2 // CHECK-INST: uqdecd w0, pow2 // CHECK-ENCODING: [0x00,0xfc,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc e0 04 uqdecd w0, pow2, mul #16 // CHECK-INST: uqdecd w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xfc,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc ef 04 @@ -85,37 +85,37 @@ uqdecd w0, pow2, mul #16 uqdecd z0.d // CHECK-INST: uqdecd z0.d // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf e0 04 uqdecd z0.d, all // CHECK-INST: uqdecd z0.d // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf e0 04 uqdecd z0.d, all, mul #1 // CHECK-INST: uqdecd z0.d // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf e0 04 uqdecd z0.d, all, mul #16 // CHECK-INST: uqdecd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xcf,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf ef 04 uqdecd z0.d, pow2 // CHECK-INST: uqdecd z0.d, pow2 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc e0 04 uqdecd z0.d, pow2, mul #16 // CHECK-INST: uqdecd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc ef 04 @@ -126,175 +126,175 @@ uqdecd z0.d, pow2, mul #16 uqdecd x0, pow2 // CHECK-INST: uqdecd x0, pow2 // CHECK-ENCODING: [0x00,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc f0 04 uqdecd x0, vl1 // CHECK-INST: uqdecd x0, vl1 // CHECK-ENCODING: [0x20,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc f0 04 uqdecd x0, vl2 // CHECK-INST: uqdecd x0, vl2 // CHECK-ENCODING: [0x40,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fc f0 04 uqdecd x0, vl3 // CHECK-INST: uqdecd x0, vl3 // CHECK-ENCODING: [0x60,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fc f0 04 uqdecd x0, vl4 // CHECK-INST: uqdecd x0, vl4 // CHECK-ENCODING: [0x80,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fc f0 04 uqdecd x0, vl5 // CHECK-INST: uqdecd x0, vl5 // CHECK-ENCODING: [0xa0,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fc f0 04 uqdecd x0, vl6 // CHECK-INST: uqdecd x0, vl6 // CHECK-ENCODING: [0xc0,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fc f0 04 uqdecd x0, vl7 // CHECK-INST: uqdecd x0, vl7 // CHECK-ENCODING: [0xe0,0xfc,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fc f0 04 uqdecd x0, vl8 // CHECK-INST: uqdecd x0, vl8 // CHECK-ENCODING: [0x00,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fd f0 04 uqdecd x0, vl16 // CHECK-INST: uqdecd x0, vl16 // CHECK-ENCODING: [0x20,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fd f0 04 uqdecd x0, vl32 // CHECK-INST: uqdecd x0, vl32 // CHECK-ENCODING: [0x40,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fd f0 04 uqdecd x0, vl64 // CHECK-INST: uqdecd x0, vl64 // CHECK-ENCODING: [0x60,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fd f0 04 uqdecd x0, vl128 // CHECK-INST: uqdecd x0, vl128 // CHECK-ENCODING: [0x80,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fd f0 04 uqdecd x0, vl256 // CHECK-INST: uqdecd x0, vl256 // CHECK-ENCODING: [0xa0,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fd f0 04 uqdecd x0, #14 // CHECK-INST: uqdecd x0, #14 // CHECK-ENCODING: [0xc0,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fd f0 04 uqdecd x0, #15 // CHECK-INST: uqdecd x0, #15 // CHECK-ENCODING: [0xe0,0xfd,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fd f0 04 uqdecd x0, #16 // CHECK-INST: uqdecd x0, #16 // CHECK-ENCODING: [0x00,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fe f0 04 uqdecd x0, #17 // CHECK-INST: uqdecd x0, #17 // CHECK-ENCODING: [0x20,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fe f0 04 uqdecd x0, #18 // CHECK-INST: uqdecd x0, #18 // CHECK-ENCODING: [0x40,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fe f0 04 uqdecd x0, #19 // CHECK-INST: uqdecd x0, #19 // CHECK-ENCODING: [0x60,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fe f0 04 uqdecd x0, #20 // CHECK-INST: uqdecd x0, #20 // CHECK-ENCODING: [0x80,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fe f0 04 uqdecd x0, #21 // CHECK-INST: uqdecd x0, #21 // CHECK-ENCODING: [0xa0,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fe f0 04 uqdecd x0, #22 // CHECK-INST: uqdecd x0, #22 // CHECK-ENCODING: [0xc0,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fe f0 04 uqdecd x0, #23 // CHECK-INST: uqdecd x0, #23 // CHECK-ENCODING: [0xe0,0xfe,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fe f0 04 uqdecd x0, #24 // CHECK-INST: uqdecd x0, #24 // CHECK-ENCODING: [0x00,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ff f0 04 uqdecd x0, #25 // CHECK-INST: uqdecd x0, #25 // CHECK-ENCODING: [0x20,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ff f0 04 uqdecd x0, #26 // CHECK-INST: uqdecd x0, #26 // CHECK-ENCODING: [0x40,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ff f0 04 uqdecd x0, #27 // CHECK-INST: uqdecd x0, #27 // CHECK-ENCODING: [0x60,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ff f0 04 uqdecd x0, #28 // CHECK-INST: uqdecd x0, #28 // CHECK-ENCODING: [0x80,0xff,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ff f0 04 @@ -304,35 +304,35 @@ uqdecd x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecd z0.d // CHECK-INST: uqdecd z0.d // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf e0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecd z0.d, pow2, mul #16 // CHECK-INST: uqdecd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc ef 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecd z0.d, pow2 // CHECK-INST: uqdecd z0.d, pow2 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc e0 04 diff --git a/llvm/test/MC/AArch64/SVE/uqdech.s b/llvm/test/MC/AArch64/SVE/uqdech.s index 6e77f1d7a22d5..c5c4a40490fed 100644 --- a/llvm/test/MC/AArch64/SVE/uqdech.s +++ b/llvm/test/MC/AArch64/SVE/uqdech.s @@ -16,25 +16,25 @@ uqdech x0 // CHECK-INST: uqdech x0 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 70 04 uqdech x0, all // CHECK-INST: uqdech x0 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 70 04 uqdech x0, all, mul #1 // CHECK-INST: uqdech x0 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 70 04 uqdech x0, all, mul #16 // CHECK-INST: uqdech x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 7f 04 @@ -45,37 +45,37 @@ uqdech x0, all, mul #16 uqdech w0 // CHECK-INST: uqdech w0 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 60 04 uqdech w0, all // CHECK-INST: uqdech w0 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 60 04 uqdech w0, all, mul #1 // CHECK-INST: uqdech w0 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 60 04 uqdech w0, all, mul #16 // CHECK-INST: uqdech w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff 6f 04 uqdech w0, pow2 // CHECK-INST: uqdech w0, pow2 // CHECK-ENCODING: [0x00,0xfc,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 60 04 uqdech w0, pow2, mul #16 // CHECK-INST: uqdech w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xfc,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 6f 04 @@ -85,37 +85,37 @@ uqdech w0, pow2, mul #16 uqdech z0.h // CHECK-INST: uqdech z0.h // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 60 04 uqdech z0.h, all // CHECK-INST: uqdech z0.h // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 60 04 uqdech z0.h, all, mul #1 // CHECK-INST: uqdech z0.h // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 60 04 uqdech z0.h, all, mul #16 // CHECK-INST: uqdech z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xcf,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 6f 04 uqdech z0.h, pow2 // CHECK-INST: uqdech z0.h, pow2 // CHECK-ENCODING: [0x00,0xcc,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc 60 04 uqdech z0.h, pow2, mul #16 // CHECK-INST: uqdech z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc 6f 04 @@ -126,175 +126,175 @@ uqdech z0.h, pow2, mul #16 uqdech x0, pow2 // CHECK-INST: uqdech x0, pow2 // CHECK-ENCODING: [0x00,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc 70 04 uqdech x0, vl1 // CHECK-INST: uqdech x0, vl1 // CHECK-ENCODING: [0x20,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc 70 04 uqdech x0, vl2 // CHECK-INST: uqdech x0, vl2 // CHECK-ENCODING: [0x40,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fc 70 04 uqdech x0, vl3 // CHECK-INST: uqdech x0, vl3 // CHECK-ENCODING: [0x60,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fc 70 04 uqdech x0, vl4 // CHECK-INST: uqdech x0, vl4 // CHECK-ENCODING: [0x80,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fc 70 04 uqdech x0, vl5 // CHECK-INST: uqdech x0, vl5 // CHECK-ENCODING: [0xa0,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fc 70 04 uqdech x0, vl6 // CHECK-INST: uqdech x0, vl6 // CHECK-ENCODING: [0xc0,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fc 70 04 uqdech x0, vl7 // CHECK-INST: uqdech x0, vl7 // CHECK-ENCODING: [0xe0,0xfc,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fc 70 04 uqdech x0, vl8 // CHECK-INST: uqdech x0, vl8 // CHECK-ENCODING: [0x00,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fd 70 04 uqdech x0, vl16 // CHECK-INST: uqdech x0, vl16 // CHECK-ENCODING: [0x20,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fd 70 04 uqdech x0, vl32 // CHECK-INST: uqdech x0, vl32 // CHECK-ENCODING: [0x40,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fd 70 04 uqdech x0, vl64 // CHECK-INST: uqdech x0, vl64 // CHECK-ENCODING: [0x60,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fd 70 04 uqdech x0, vl128 // CHECK-INST: uqdech x0, vl128 // CHECK-ENCODING: [0x80,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fd 70 04 uqdech x0, vl256 // CHECK-INST: uqdech x0, vl256 // CHECK-ENCODING: [0xa0,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fd 70 04 uqdech x0, #14 // CHECK-INST: uqdech x0, #14 // CHECK-ENCODING: [0xc0,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fd 70 04 uqdech x0, #15 // CHECK-INST: uqdech x0, #15 // CHECK-ENCODING: [0xe0,0xfd,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fd 70 04 uqdech x0, #16 // CHECK-INST: uqdech x0, #16 // CHECK-ENCODING: [0x00,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fe 70 04 uqdech x0, #17 // CHECK-INST: uqdech x0, #17 // CHECK-ENCODING: [0x20,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fe 70 04 uqdech x0, #18 // CHECK-INST: uqdech x0, #18 // CHECK-ENCODING: [0x40,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fe 70 04 uqdech x0, #19 // CHECK-INST: uqdech x0, #19 // CHECK-ENCODING: [0x60,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fe 70 04 uqdech x0, #20 // CHECK-INST: uqdech x0, #20 // CHECK-ENCODING: [0x80,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fe 70 04 uqdech x0, #21 // CHECK-INST: uqdech x0, #21 // CHECK-ENCODING: [0xa0,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fe 70 04 uqdech x0, #22 // CHECK-INST: uqdech x0, #22 // CHECK-ENCODING: [0xc0,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fe 70 04 uqdech x0, #23 // CHECK-INST: uqdech x0, #23 // CHECK-ENCODING: [0xe0,0xfe,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fe 70 04 uqdech x0, #24 // CHECK-INST: uqdech x0, #24 // CHECK-ENCODING: [0x00,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ff 70 04 uqdech x0, #25 // CHECK-INST: uqdech x0, #25 // CHECK-ENCODING: [0x20,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ff 70 04 uqdech x0, #26 // CHECK-INST: uqdech x0, #26 // CHECK-ENCODING: [0x40,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ff 70 04 uqdech x0, #27 // CHECK-INST: uqdech x0, #27 // CHECK-ENCODING: [0x60,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ff 70 04 uqdech x0, #28 // CHECK-INST: uqdech x0, #28 // CHECK-ENCODING: [0x80,0xff,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ff 70 04 @@ -304,35 +304,35 @@ uqdech x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdech z0.h // CHECK-INST: uqdech z0.h // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf 60 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdech z0.h, pow2, mul #16 // CHECK-INST: uqdech z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc 6f 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdech z0.h, pow2 // CHECK-INST: uqdech z0.h, pow2 // CHECK-ENCODING: [0x00,0xcc,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc 60 04 diff --git a/llvm/test/MC/AArch64/SVE/uqdecp.s b/llvm/test/MC/AArch64/SVE/uqdecp.s index e5ca1c5fd7e3a..2deec983a3ddb 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecp.s +++ b/llvm/test/MC/AArch64/SVE/uqdecp.s @@ -12,85 +12,85 @@ uqdecp x0, p0.b // CHECK-INST: uqdecp x0, p0.b // CHECK-ENCODING: [0x00,0x8c,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 2b 25 uqdecp x0, p0.h // CHECK-INST: uqdecp x0, p0.h // CHECK-ENCODING: [0x00,0x8c,0x6b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 6b 25 uqdecp x0, p0.s // CHECK-INST: uqdecp x0, p0.s // CHECK-ENCODING: [0x00,0x8c,0xab,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c ab 25 uqdecp x0, p0.d // CHECK-INST: uqdecp x0, p0.d // CHECK-ENCODING: [0x00,0x8c,0xeb,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c eb 25 uqdecp wzr, p15.b // CHECK-INST: uqdecp wzr, p15.b // CHECK-ENCODING: [0xff,0x89,0x2b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 2b 25 uqdecp wzr, p15.h // CHECK-INST: uqdecp wzr, p15.h // CHECK-ENCODING: [0xff,0x89,0x6b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 6b 25 uqdecp wzr, p15.s // CHECK-INST: uqdecp wzr, p15.s // CHECK-ENCODING: [0xff,0x89,0xab,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 ab 25 uqdecp wzr, p15.d // CHECK-INST: uqdecp wzr, p15.d // CHECK-ENCODING: [0xff,0x89,0xeb,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 eb 25 uqdecp z0.h, p0 // CHECK-INST: uqdecp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x6b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 6b 25 uqdecp z0.h, p0.h // CHECK-INST: uqdecp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x6b,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 6b 25 uqdecp z0.s, p0 // CHECK-INST: uqdecp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xab,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 ab 25 uqdecp z0.s, p0.s // CHECK-INST: uqdecp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xab,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 ab 25 uqdecp z0.d, p0 // CHECK-INST: uqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xeb,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 eb 25 uqdecp z0.d, p0.d // CHECK-INST: uqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xeb,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 eb 25 @@ -100,11 +100,11 @@ uqdecp z0.d, p0.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecp z0.d, p0.d // CHECK-INST: uqdecp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xeb,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 eb 25 diff --git a/llvm/test/MC/AArch64/SVE/uqdecw.s b/llvm/test/MC/AArch64/SVE/uqdecw.s index 887219ee4d5d7..f137aaea5da45 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecw.s +++ b/llvm/test/MC/AArch64/SVE/uqdecw.s @@ -16,25 +16,25 @@ uqdecw x0 // CHECK-INST: uqdecw x0 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff b0 04 uqdecw x0, all // CHECK-INST: uqdecw x0 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff b0 04 uqdecw x0, all, mul #1 // CHECK-INST: uqdecw x0 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff b0 04 uqdecw x0, all, mul #16 // CHECK-INST: uqdecw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff bf 04 @@ -45,37 +45,37 @@ uqdecw x0, all, mul #16 uqdecw w0 // CHECK-INST: uqdecw w0 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff a0 04 uqdecw w0, all // CHECK-INST: uqdecw w0 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff a0 04 uqdecw w0, all, mul #1 // CHECK-INST: uqdecw w0 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff a0 04 uqdecw w0, all, mul #16 // CHECK-INST: uqdecw w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xff,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 ff af 04 uqdecw w0, pow2 // CHECK-INST: uqdecw w0, pow2 // CHECK-ENCODING: [0x00,0xfc,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc a0 04 uqdecw w0, pow2, mul #16 // CHECK-INST: uqdecw w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xfc,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc af 04 @@ -85,37 +85,37 @@ uqdecw w0, pow2, mul #16 uqdecw z0.s // CHECK-INST: uqdecw z0.s // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf a0 04 uqdecw z0.s, all // CHECK-INST: uqdecw z0.s // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf a0 04 uqdecw z0.s, all, mul #1 // CHECK-INST: uqdecw z0.s // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf a0 04 uqdecw z0.s, all, mul #16 // CHECK-INST: uqdecw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xcf,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf af 04 uqdecw z0.s, pow2 // CHECK-INST: uqdecw z0.s, pow2 // CHECK-ENCODING: [0x00,0xcc,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc a0 04 uqdecw z0.s, pow2, mul #16 // CHECK-INST: uqdecw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc af 04 @@ -126,175 +126,175 @@ uqdecw z0.s, pow2, mul #16 uqdecw x0, pow2 // CHECK-INST: uqdecw x0, pow2 // CHECK-ENCODING: [0x00,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fc b0 04 uqdecw x0, vl1 // CHECK-INST: uqdecw x0, vl1 // CHECK-ENCODING: [0x20,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fc b0 04 uqdecw x0, vl2 // CHECK-INST: uqdecw x0, vl2 // CHECK-ENCODING: [0x40,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fc b0 04 uqdecw x0, vl3 // CHECK-INST: uqdecw x0, vl3 // CHECK-ENCODING: [0x60,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fc b0 04 uqdecw x0, vl4 // CHECK-INST: uqdecw x0, vl4 // CHECK-ENCODING: [0x80,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fc b0 04 uqdecw x0, vl5 // CHECK-INST: uqdecw x0, vl5 // CHECK-ENCODING: [0xa0,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fc b0 04 uqdecw x0, vl6 // CHECK-INST: uqdecw x0, vl6 // CHECK-ENCODING: [0xc0,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fc b0 04 uqdecw x0, vl7 // CHECK-INST: uqdecw x0, vl7 // CHECK-ENCODING: [0xe0,0xfc,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fc b0 04 uqdecw x0, vl8 // CHECK-INST: uqdecw x0, vl8 // CHECK-ENCODING: [0x00,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fd b0 04 uqdecw x0, vl16 // CHECK-INST: uqdecw x0, vl16 // CHECK-ENCODING: [0x20,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fd b0 04 uqdecw x0, vl32 // CHECK-INST: uqdecw x0, vl32 // CHECK-ENCODING: [0x40,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fd b0 04 uqdecw x0, vl64 // CHECK-INST: uqdecw x0, vl64 // CHECK-ENCODING: [0x60,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fd b0 04 uqdecw x0, vl128 // CHECK-INST: uqdecw x0, vl128 // CHECK-ENCODING: [0x80,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fd b0 04 uqdecw x0, vl256 // CHECK-INST: uqdecw x0, vl256 // CHECK-ENCODING: [0xa0,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fd b0 04 uqdecw x0, #14 // CHECK-INST: uqdecw x0, #14 // CHECK-ENCODING: [0xc0,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fd b0 04 uqdecw x0, #15 // CHECK-INST: uqdecw x0, #15 // CHECK-ENCODING: [0xe0,0xfd,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fd b0 04 uqdecw x0, #16 // CHECK-INST: uqdecw x0, #16 // CHECK-ENCODING: [0x00,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 fe b0 04 uqdecw x0, #17 // CHECK-INST: uqdecw x0, #17 // CHECK-ENCODING: [0x20,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 fe b0 04 uqdecw x0, #18 // CHECK-INST: uqdecw x0, #18 // CHECK-ENCODING: [0x40,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 fe b0 04 uqdecw x0, #19 // CHECK-INST: uqdecw x0, #19 // CHECK-ENCODING: [0x60,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 fe b0 04 uqdecw x0, #20 // CHECK-INST: uqdecw x0, #20 // CHECK-ENCODING: [0x80,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 fe b0 04 uqdecw x0, #21 // CHECK-INST: uqdecw x0, #21 // CHECK-ENCODING: [0xa0,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 fe b0 04 uqdecw x0, #22 // CHECK-INST: uqdecw x0, #22 // CHECK-ENCODING: [0xc0,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 fe b0 04 uqdecw x0, #23 // CHECK-INST: uqdecw x0, #23 // CHECK-ENCODING: [0xe0,0xfe,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 fe b0 04 uqdecw x0, #24 // CHECK-INST: uqdecw x0, #24 // CHECK-ENCODING: [0x00,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 ff b0 04 uqdecw x0, #25 // CHECK-INST: uqdecw x0, #25 // CHECK-ENCODING: [0x20,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 ff b0 04 uqdecw x0, #26 // CHECK-INST: uqdecw x0, #26 // CHECK-ENCODING: [0x40,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 ff b0 04 uqdecw x0, #27 // CHECK-INST: uqdecw x0, #27 // CHECK-ENCODING: [0x60,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 ff b0 04 uqdecw x0, #28 // CHECK-INST: uqdecw x0, #28 // CHECK-ENCODING: [0x80,0xff,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 ff b0 04 @@ -304,35 +304,35 @@ uqdecw x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecw z0.s // CHECK-INST: uqdecw z0.s // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 cf a0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecw z0.s, pow2, mul #16 // CHECK-INST: uqdecw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xcc,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc af 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqdecw z0.s, pow2 // CHECK-INST: uqdecw z0.s, pow2 // CHECK-ENCODING: [0x00,0xcc,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 cc a0 04 diff --git a/llvm/test/MC/AArch64/SVE/uqincb.s b/llvm/test/MC/AArch64/SVE/uqincb.s index 1895ba138a986..b728cb75340d9 100644 --- a/llvm/test/MC/AArch64/SVE/uqincb.s +++ b/llvm/test/MC/AArch64/SVE/uqincb.s @@ -16,25 +16,25 @@ uqincb x0 // CHECK-INST: uqincb x0 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 30 04 uqincb x0, all // CHECK-INST: uqincb x0 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 30 04 uqincb x0, all, mul #1 // CHECK-INST: uqincb x0 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 30 04 uqincb x0, all, mul #16 // CHECK-INST: uqincb x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 3f 04 @@ -45,37 +45,37 @@ uqincb x0, all, mul #16 uqincb w0 // CHECK-INST: uqincb w0 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 20 04 uqincb w0, all // CHECK-INST: uqincb w0 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 20 04 uqincb w0, all, mul #1 // CHECK-INST: uqincb w0 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 20 04 uqincb w0, all, mul #16 // CHECK-INST: uqincb w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 2f 04 uqincb w0, pow2 // CHECK-INST: uqincb w0, pow2 // CHECK-ENCODING: [0x00,0xf4,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 20 04 uqincb w0, pow2, mul #16 // CHECK-INST: uqincb w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf4,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 2f 04 @@ -86,173 +86,173 @@ uqincb w0, pow2, mul #16 uqincb x0, pow2 // CHECK-INST: uqincb x0, pow2 // CHECK-ENCODING: [0x00,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 30 04 uqincb x0, vl1 // CHECK-INST: uqincb x0, vl1 // CHECK-ENCODING: [0x20,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f4 30 04 uqincb x0, vl2 // CHECK-INST: uqincb x0, vl2 // CHECK-ENCODING: [0x40,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f4 30 04 uqincb x0, vl3 // CHECK-INST: uqincb x0, vl3 // CHECK-ENCODING: [0x60,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f4 30 04 uqincb x0, vl4 // CHECK-INST: uqincb x0, vl4 // CHECK-ENCODING: [0x80,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f4 30 04 uqincb x0, vl5 // CHECK-INST: uqincb x0, vl5 // CHECK-ENCODING: [0xa0,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f4 30 04 uqincb x0, vl6 // CHECK-INST: uqincb x0, vl6 // CHECK-ENCODING: [0xc0,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f4 30 04 uqincb x0, vl7 // CHECK-INST: uqincb x0, vl7 // CHECK-ENCODING: [0xe0,0xf4,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f4 30 04 uqincb x0, vl8 // CHECK-INST: uqincb x0, vl8 // CHECK-ENCODING: [0x00,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f5 30 04 uqincb x0, vl16 // CHECK-INST: uqincb x0, vl16 // CHECK-ENCODING: [0x20,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f5 30 04 uqincb x0, vl32 // CHECK-INST: uqincb x0, vl32 // CHECK-ENCODING: [0x40,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f5 30 04 uqincb x0, vl64 // CHECK-INST: uqincb x0, vl64 // CHECK-ENCODING: [0x60,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f5 30 04 uqincb x0, vl128 // CHECK-INST: uqincb x0, vl128 // CHECK-ENCODING: [0x80,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f5 30 04 uqincb x0, vl256 // CHECK-INST: uqincb x0, vl256 // CHECK-ENCODING: [0xa0,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f5 30 04 uqincb x0, #14 // CHECK-INST: uqincb x0, #14 // CHECK-ENCODING: [0xc0,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f5 30 04 uqincb x0, #15 // CHECK-INST: uqincb x0, #15 // CHECK-ENCODING: [0xe0,0xf5,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f5 30 04 uqincb x0, #16 // CHECK-INST: uqincb x0, #16 // CHECK-ENCODING: [0x00,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f6 30 04 uqincb x0, #17 // CHECK-INST: uqincb x0, #17 // CHECK-ENCODING: [0x20,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f6 30 04 uqincb x0, #18 // CHECK-INST: uqincb x0, #18 // CHECK-ENCODING: [0x40,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f6 30 04 uqincb x0, #19 // CHECK-INST: uqincb x0, #19 // CHECK-ENCODING: [0x60,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f6 30 04 uqincb x0, #20 // CHECK-INST: uqincb x0, #20 // CHECK-ENCODING: [0x80,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f6 30 04 uqincb x0, #21 // CHECK-INST: uqincb x0, #21 // CHECK-ENCODING: [0xa0,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f6 30 04 uqincb x0, #22 // CHECK-INST: uqincb x0, #22 // CHECK-ENCODING: [0xc0,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f6 30 04 uqincb x0, #23 // CHECK-INST: uqincb x0, #23 // CHECK-ENCODING: [0xe0,0xf6,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f6 30 04 uqincb x0, #24 // CHECK-INST: uqincb x0, #24 // CHECK-ENCODING: [0x00,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f7 30 04 uqincb x0, #25 // CHECK-INST: uqincb x0, #25 // CHECK-ENCODING: [0x20,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f7 30 04 uqincb x0, #26 // CHECK-INST: uqincb x0, #26 // CHECK-ENCODING: [0x40,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f7 30 04 uqincb x0, #27 // CHECK-INST: uqincb x0, #27 // CHECK-ENCODING: [0x60,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f7 30 04 uqincb x0, #28 // CHECK-INST: uqincb x0, #28 // CHECK-ENCODING: [0x80,0xf7,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f7 30 04 diff --git a/llvm/test/MC/AArch64/SVE/uqincd.s b/llvm/test/MC/AArch64/SVE/uqincd.s index b585a7c58fe8e..cebea9327984d 100644 --- a/llvm/test/MC/AArch64/SVE/uqincd.s +++ b/llvm/test/MC/AArch64/SVE/uqincd.s @@ -16,25 +16,25 @@ uqincd x0 // CHECK-INST: uqincd x0 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 f0 04 uqincd x0, all // CHECK-INST: uqincd x0 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 f0 04 uqincd x0, all, mul #1 // CHECK-INST: uqincd x0 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 f0 04 uqincd x0, all, mul #16 // CHECK-INST: uqincd x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 ff 04 @@ -45,37 +45,37 @@ uqincd x0, all, mul #16 uqincd w0 // CHECK-INST: uqincd w0 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 e0 04 uqincd w0, all // CHECK-INST: uqincd w0 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 e0 04 uqincd w0, all, mul #1 // CHECK-INST: uqincd w0 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 e0 04 uqincd w0, all, mul #16 // CHECK-INST: uqincd w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 ef 04 uqincd w0, pow2 // CHECK-INST: uqincd w0, pow2 // CHECK-ENCODING: [0x00,0xf4,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 e0 04 uqincd w0, pow2, mul #16 // CHECK-INST: uqincd w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf4,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 ef 04 @@ -85,37 +85,37 @@ uqincd w0, pow2, mul #16 uqincd z0.d // CHECK-INST: uqincd z0.d // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 e0 04 uqincd z0.d, all // CHECK-INST: uqincd z0.d // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 e0 04 uqincd z0.d, all, mul #1 // CHECK-INST: uqincd z0.d // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 e0 04 uqincd z0.d, all, mul #16 // CHECK-INST: uqincd z0.d, all, mul #16 // CHECK-ENCODING: [0xe0,0xc7,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 ef 04 uqincd z0.d, pow2 // CHECK-INST: uqincd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc4,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 e0 04 uqincd z0.d, pow2, mul #16 // CHECK-INST: uqincd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 ef 04 @@ -126,175 +126,175 @@ uqincd z0.d, pow2, mul #16 uqincd x0, pow2 // CHECK-INST: uqincd x0, pow2 // CHECK-ENCODING: [0x00,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 f0 04 uqincd x0, vl1 // CHECK-INST: uqincd x0, vl1 // CHECK-ENCODING: [0x20,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f4 f0 04 uqincd x0, vl2 // CHECK-INST: uqincd x0, vl2 // CHECK-ENCODING: [0x40,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f4 f0 04 uqincd x0, vl3 // CHECK-INST: uqincd x0, vl3 // CHECK-ENCODING: [0x60,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f4 f0 04 uqincd x0, vl4 // CHECK-INST: uqincd x0, vl4 // CHECK-ENCODING: [0x80,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f4 f0 04 uqincd x0, vl5 // CHECK-INST: uqincd x0, vl5 // CHECK-ENCODING: [0xa0,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f4 f0 04 uqincd x0, vl6 // CHECK-INST: uqincd x0, vl6 // CHECK-ENCODING: [0xc0,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f4 f0 04 uqincd x0, vl7 // CHECK-INST: uqincd x0, vl7 // CHECK-ENCODING: [0xe0,0xf4,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f4 f0 04 uqincd x0, vl8 // CHECK-INST: uqincd x0, vl8 // CHECK-ENCODING: [0x00,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f5 f0 04 uqincd x0, vl16 // CHECK-INST: uqincd x0, vl16 // CHECK-ENCODING: [0x20,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f5 f0 04 uqincd x0, vl32 // CHECK-INST: uqincd x0, vl32 // CHECK-ENCODING: [0x40,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f5 f0 04 uqincd x0, vl64 // CHECK-INST: uqincd x0, vl64 // CHECK-ENCODING: [0x60,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f5 f0 04 uqincd x0, vl128 // CHECK-INST: uqincd x0, vl128 // CHECK-ENCODING: [0x80,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f5 f0 04 uqincd x0, vl256 // CHECK-INST: uqincd x0, vl256 // CHECK-ENCODING: [0xa0,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f5 f0 04 uqincd x0, #14 // CHECK-INST: uqincd x0, #14 // CHECK-ENCODING: [0xc0,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f5 f0 04 uqincd x0, #15 // CHECK-INST: uqincd x0, #15 // CHECK-ENCODING: [0xe0,0xf5,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f5 f0 04 uqincd x0, #16 // CHECK-INST: uqincd x0, #16 // CHECK-ENCODING: [0x00,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f6 f0 04 uqincd x0, #17 // CHECK-INST: uqincd x0, #17 // CHECK-ENCODING: [0x20,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f6 f0 04 uqincd x0, #18 // CHECK-INST: uqincd x0, #18 // CHECK-ENCODING: [0x40,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f6 f0 04 uqincd x0, #19 // CHECK-INST: uqincd x0, #19 // CHECK-ENCODING: [0x60,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f6 f0 04 uqincd x0, #20 // CHECK-INST: uqincd x0, #20 // CHECK-ENCODING: [0x80,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f6 f0 04 uqincd x0, #21 // CHECK-INST: uqincd x0, #21 // CHECK-ENCODING: [0xa0,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f6 f0 04 uqincd x0, #22 // CHECK-INST: uqincd x0, #22 // CHECK-ENCODING: [0xc0,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f6 f0 04 uqincd x0, #23 // CHECK-INST: uqincd x0, #23 // CHECK-ENCODING: [0xe0,0xf6,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f6 f0 04 uqincd x0, #24 // CHECK-INST: uqincd x0, #24 // CHECK-ENCODING: [0x00,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f7 f0 04 uqincd x0, #25 // CHECK-INST: uqincd x0, #25 // CHECK-ENCODING: [0x20,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f7 f0 04 uqincd x0, #26 // CHECK-INST: uqincd x0, #26 // CHECK-ENCODING: [0x40,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f7 f0 04 uqincd x0, #27 // CHECK-INST: uqincd x0, #27 // CHECK-ENCODING: [0x60,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f7 f0 04 uqincd x0, #28 // CHECK-INST: uqincd x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xf0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f7 f0 04 @@ -304,35 +304,35 @@ uqincd x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincd z0.d // CHECK-INST: uqincd z0.d // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 e0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincd z0.d, pow2, mul #16 // CHECK-INST: uqincd z0.d, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0xef,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 ef 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincd z0.d, pow2 // CHECK-INST: uqincd z0.d, pow2 // CHECK-ENCODING: [0x00,0xc4,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 e0 04 diff --git a/llvm/test/MC/AArch64/SVE/uqinch.s b/llvm/test/MC/AArch64/SVE/uqinch.s index c38656ba7edab..a98cf2bd0083b 100644 --- a/llvm/test/MC/AArch64/SVE/uqinch.s +++ b/llvm/test/MC/AArch64/SVE/uqinch.s @@ -17,25 +17,25 @@ uqinch x0 // CHECK-INST: uqinch x0 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 70 04 uqinch x0, all // CHECK-INST: uqinch x0 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 70 04 uqinch x0, all, mul #1 // CHECK-INST: uqinch x0 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 70 04 uqinch x0, all, mul #16 // CHECK-INST: uqinch x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 7f 04 @@ -46,37 +46,37 @@ uqinch x0, all, mul #16 uqinch w0 // CHECK-INST: uqinch w0 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 60 04 uqinch w0, all // CHECK-INST: uqinch w0 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 60 04 uqinch w0, all, mul #1 // CHECK-INST: uqinch w0 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 60 04 uqinch w0, all, mul #16 // CHECK-INST: uqinch w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 6f 04 uqinch w0, pow2 // CHECK-INST: uqinch w0, pow2 // CHECK-ENCODING: [0x00,0xf4,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 60 04 uqinch w0, pow2, mul #16 // CHECK-INST: uqinch w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf4,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 6f 04 @@ -87,37 +87,37 @@ uqinch w0, pow2, mul #16 uqinch z0.h // CHECK-INST: uqinch z0.h // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 60 04 uqinch z0.h, all // CHECK-INST: uqinch z0.h // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 60 04 uqinch z0.h, all, mul #1 // CHECK-INST: uqinch z0.h // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 60 04 uqinch z0.h, all, mul #16 // CHECK-INST: uqinch z0.h, all, mul #16 // CHECK-ENCODING: [0xe0,0xc7,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 6f 04 uqinch z0.h, pow2 // CHECK-INST: uqinch z0.h, pow2 // CHECK-ENCODING: [0x00,0xc4,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 60 04 uqinch z0.h, pow2, mul #16 // CHECK-INST: uqinch z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 6f 04 @@ -128,175 +128,175 @@ uqinch z0.h, pow2, mul #16 uqinch x0, pow2 // CHECK-INST: uqinch x0, pow2 // CHECK-ENCODING: [0x00,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 70 04 uqinch x0, vl1 // CHECK-INST: uqinch x0, vl1 // CHECK-ENCODING: [0x20,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f4 70 04 uqinch x0, vl2 // CHECK-INST: uqinch x0, vl2 // CHECK-ENCODING: [0x40,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f4 70 04 uqinch x0, vl3 // CHECK-INST: uqinch x0, vl3 // CHECK-ENCODING: [0x60,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f4 70 04 uqinch x0, vl4 // CHECK-INST: uqinch x0, vl4 // CHECK-ENCODING: [0x80,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f4 70 04 uqinch x0, vl5 // CHECK-INST: uqinch x0, vl5 // CHECK-ENCODING: [0xa0,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f4 70 04 uqinch x0, vl6 // CHECK-INST: uqinch x0, vl6 // CHECK-ENCODING: [0xc0,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f4 70 04 uqinch x0, vl7 // CHECK-INST: uqinch x0, vl7 // CHECK-ENCODING: [0xe0,0xf4,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f4 70 04 uqinch x0, vl8 // CHECK-INST: uqinch x0, vl8 // CHECK-ENCODING: [0x00,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f5 70 04 uqinch x0, vl16 // CHECK-INST: uqinch x0, vl16 // CHECK-ENCODING: [0x20,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f5 70 04 uqinch x0, vl32 // CHECK-INST: uqinch x0, vl32 // CHECK-ENCODING: [0x40,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f5 70 04 uqinch x0, vl64 // CHECK-INST: uqinch x0, vl64 // CHECK-ENCODING: [0x60,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f5 70 04 uqinch x0, vl128 // CHECK-INST: uqinch x0, vl128 // CHECK-ENCODING: [0x80,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f5 70 04 uqinch x0, vl256 // CHECK-INST: uqinch x0, vl256 // CHECK-ENCODING: [0xa0,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f5 70 04 uqinch x0, #14 // CHECK-INST: uqinch x0, #14 // CHECK-ENCODING: [0xc0,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f5 70 04 uqinch x0, #15 // CHECK-INST: uqinch x0, #15 // CHECK-ENCODING: [0xe0,0xf5,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f5 70 04 uqinch x0, #16 // CHECK-INST: uqinch x0, #16 // CHECK-ENCODING: [0x00,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f6 70 04 uqinch x0, #17 // CHECK-INST: uqinch x0, #17 // CHECK-ENCODING: [0x20,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f6 70 04 uqinch x0, #18 // CHECK-INST: uqinch x0, #18 // CHECK-ENCODING: [0x40,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f6 70 04 uqinch x0, #19 // CHECK-INST: uqinch x0, #19 // CHECK-ENCODING: [0x60,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f6 70 04 uqinch x0, #20 // CHECK-INST: uqinch x0, #20 // CHECK-ENCODING: [0x80,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f6 70 04 uqinch x0, #21 // CHECK-INST: uqinch x0, #21 // CHECK-ENCODING: [0xa0,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f6 70 04 uqinch x0, #22 // CHECK-INST: uqinch x0, #22 // CHECK-ENCODING: [0xc0,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f6 70 04 uqinch x0, #23 // CHECK-INST: uqinch x0, #23 // CHECK-ENCODING: [0xe0,0xf6,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f6 70 04 uqinch x0, #24 // CHECK-INST: uqinch x0, #24 // CHECK-ENCODING: [0x00,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f7 70 04 uqinch x0, #25 // CHECK-INST: uqinch x0, #25 // CHECK-ENCODING: [0x20,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f7 70 04 uqinch x0, #26 // CHECK-INST: uqinch x0, #26 // CHECK-ENCODING: [0x40,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f7 70 04 uqinch x0, #27 // CHECK-INST: uqinch x0, #27 // CHECK-ENCODING: [0x60,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f7 70 04 uqinch x0, #28 // CHECK-INST: uqinch x0, #28 // CHECK-ENCODING: [0x80,0xf7,0x70,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f7 70 04 @@ -306,35 +306,35 @@ uqinch x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqinch z0.h // CHECK-INST: uqinch z0.h // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 60 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqinch z0.h, pow2, mul #16 // CHECK-INST: uqinch z0.h, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0x6f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 6f 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqinch z0.h, pow2 // CHECK-INST: uqinch z0.h, pow2 // CHECK-ENCODING: [0x00,0xc4,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 60 04 diff --git a/llvm/test/MC/AArch64/SVE/uqincp.s b/llvm/test/MC/AArch64/SVE/uqincp.s index 28e076f86b4a5..07c4143abc3c4 100644 --- a/llvm/test/MC/AArch64/SVE/uqincp.s +++ b/llvm/test/MC/AArch64/SVE/uqincp.s @@ -12,85 +12,85 @@ uqincp x0, p0.b // CHECK-INST: uqincp x0, p0.b // CHECK-ENCODING: [0x00,0x8c,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 29 25 uqincp x0, p0.h // CHECK-INST: uqincp x0, p0.h // CHECK-ENCODING: [0x00,0x8c,0x69,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c 69 25 uqincp x0, p0.s // CHECK-INST: uqincp x0, p0.s // CHECK-ENCODING: [0x00,0x8c,0xa9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c a9 25 uqincp x0, p0.d // CHECK-INST: uqincp x0, p0.d // CHECK-ENCODING: [0x00,0x8c,0xe9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 8c e9 25 uqincp wzr, p15.b // CHECK-INST: uqincp wzr, p15.b // CHECK-ENCODING: [0xff,0x89,0x29,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 29 25 uqincp wzr, p15.h // CHECK-INST: uqincp wzr, p15.h // CHECK-ENCODING: [0xff,0x89,0x69,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 69 25 uqincp wzr, p15.s // CHECK-INST: uqincp wzr, p15.s // CHECK-ENCODING: [0xff,0x89,0xa9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 a9 25 uqincp wzr, p15.d // CHECK-INST: uqincp wzr, p15.d // CHECK-ENCODING: [0xff,0x89,0xe9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 89 e9 25 uqincp z0.h, p0 // CHECK-INST: uqincp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x69,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 69 25 uqincp z0.h, p0.h // CHECK-INST: uqincp z0.h, p0.h // CHECK-ENCODING: [0x00,0x80,0x69,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 69 25 uqincp z0.s, p0 // CHECK-INST: uqincp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xa9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a9 25 uqincp z0.s, p0.s // CHECK-INST: uqincp z0.s, p0.s // CHECK-ENCODING: [0x00,0x80,0xa9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 a9 25 uqincp z0.d, p0 // CHECK-INST: uqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e9 25 uqincp z0.d, p0.d // CHECK-INST: uqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e9 25 @@ -100,11 +100,11 @@ uqincp z0.d, p0.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincp z0.d, p0.d // CHECK-INST: uqincp z0.d, p0.d // CHECK-ENCODING: [0x00,0x80,0xe9,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 80 e9 25 diff --git a/llvm/test/MC/AArch64/SVE/uqincw.s b/llvm/test/MC/AArch64/SVE/uqincw.s index c644db8c7f3bb..5120894257047 100644 --- a/llvm/test/MC/AArch64/SVE/uqincw.s +++ b/llvm/test/MC/AArch64/SVE/uqincw.s @@ -16,25 +16,25 @@ uqincw x0 // CHECK-INST: uqincw x0 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 b0 04 uqincw x0, all // CHECK-INST: uqincw x0 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 b0 04 uqincw x0, all, mul #1 // CHECK-INST: uqincw x0 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 b0 04 uqincw x0, all, mul #16 // CHECK-INST: uqincw x0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 bf 04 @@ -45,37 +45,37 @@ uqincw x0, all, mul #16 uqincw w0 // CHECK-INST: uqincw w0 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 a0 04 uqincw w0, all // CHECK-INST: uqincw w0 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 a0 04 uqincw w0, all, mul #1 // CHECK-INST: uqincw w0 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 a0 04 uqincw w0, all, mul #16 // CHECK-INST: uqincw w0, all, mul #16 // CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f7 af 04 uqincw w0, pow2 // CHECK-INST: uqincw w0, pow2 // CHECK-ENCODING: [0x00,0xf4,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 a0 04 uqincw w0, pow2, mul #16 // CHECK-INST: uqincw w0, pow2, mul #16 // CHECK-ENCODING: [0x00,0xf4,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 af 04 @@ -85,37 +85,37 @@ uqincw w0, pow2, mul #16 uqincw z0.s // CHECK-INST: uqincw z0.s // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 a0 04 uqincw z0.s, all // CHECK-INST: uqincw z0.s // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 a0 04 uqincw z0.s, all, mul #1 // CHECK-INST: uqincw z0.s // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 a0 04 uqincw z0.s, all, mul #16 // CHECK-INST: uqincw z0.s, all, mul #16 // CHECK-ENCODING: [0xe0,0xc7,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 af 04 uqincw z0.s, pow2 // CHECK-INST: uqincw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc4,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 a0 04 uqincw z0.s, pow2, mul #16 // CHECK-INST: uqincw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 af 04 @@ -126,175 +126,175 @@ uqincw z0.s, pow2, mul #16 uqincw x0, pow2 // CHECK-INST: uqincw x0, pow2 // CHECK-ENCODING: [0x00,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f4 b0 04 uqincw x0, vl1 // CHECK-INST: uqincw x0, vl1 // CHECK-ENCODING: [0x20,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f4 b0 04 uqincw x0, vl2 // CHECK-INST: uqincw x0, vl2 // CHECK-ENCODING: [0x40,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f4 b0 04 uqincw x0, vl3 // CHECK-INST: uqincw x0, vl3 // CHECK-ENCODING: [0x60,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f4 b0 04 uqincw x0, vl4 // CHECK-INST: uqincw x0, vl4 // CHECK-ENCODING: [0x80,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f4 b0 04 uqincw x0, vl5 // CHECK-INST: uqincw x0, vl5 // CHECK-ENCODING: [0xa0,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f4 b0 04 uqincw x0, vl6 // CHECK-INST: uqincw x0, vl6 // CHECK-ENCODING: [0xc0,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f4 b0 04 uqincw x0, vl7 // CHECK-INST: uqincw x0, vl7 // CHECK-ENCODING: [0xe0,0xf4,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f4 b0 04 uqincw x0, vl8 // CHECK-INST: uqincw x0, vl8 // CHECK-ENCODING: [0x00,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f5 b0 04 uqincw x0, vl16 // CHECK-INST: uqincw x0, vl16 // CHECK-ENCODING: [0x20,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f5 b0 04 uqincw x0, vl32 // CHECK-INST: uqincw x0, vl32 // CHECK-ENCODING: [0x40,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f5 b0 04 uqincw x0, vl64 // CHECK-INST: uqincw x0, vl64 // CHECK-ENCODING: [0x60,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f5 b0 04 uqincw x0, vl128 // CHECK-INST: uqincw x0, vl128 // CHECK-ENCODING: [0x80,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f5 b0 04 uqincw x0, vl256 // CHECK-INST: uqincw x0, vl256 // CHECK-ENCODING: [0xa0,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f5 b0 04 uqincw x0, #14 // CHECK-INST: uqincw x0, #14 // CHECK-ENCODING: [0xc0,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f5 b0 04 uqincw x0, #15 // CHECK-INST: uqincw x0, #15 // CHECK-ENCODING: [0xe0,0xf5,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f5 b0 04 uqincw x0, #16 // CHECK-INST: uqincw x0, #16 // CHECK-ENCODING: [0x00,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f6 b0 04 uqincw x0, #17 // CHECK-INST: uqincw x0, #17 // CHECK-ENCODING: [0x20,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f6 b0 04 uqincw x0, #18 // CHECK-INST: uqincw x0, #18 // CHECK-ENCODING: [0x40,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f6 b0 04 uqincw x0, #19 // CHECK-INST: uqincw x0, #19 // CHECK-ENCODING: [0x60,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f6 b0 04 uqincw x0, #20 // CHECK-INST: uqincw x0, #20 // CHECK-ENCODING: [0x80,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f6 b0 04 uqincw x0, #21 // CHECK-INST: uqincw x0, #21 // CHECK-ENCODING: [0xa0,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: a0 f6 b0 04 uqincw x0, #22 // CHECK-INST: uqincw x0, #22 // CHECK-ENCODING: [0xc0,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c0 f6 b0 04 uqincw x0, #23 // CHECK-INST: uqincw x0, #23 // CHECK-ENCODING: [0xe0,0xf6,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 f6 b0 04 uqincw x0, #24 // CHECK-INST: uqincw x0, #24 // CHECK-ENCODING: [0x00,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 f7 b0 04 uqincw x0, #25 // CHECK-INST: uqincw x0, #25 // CHECK-ENCODING: [0x20,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 20 f7 b0 04 uqincw x0, #26 // CHECK-INST: uqincw x0, #26 // CHECK-ENCODING: [0x40,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 40 f7 b0 04 uqincw x0, #27 // CHECK-INST: uqincw x0, #27 // CHECK-ENCODING: [0x60,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 60 f7 b0 04 uqincw x0, #28 // CHECK-INST: uqincw x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xb0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 80 f7 b0 04 @@ -304,35 +304,35 @@ uqincw x0, #28 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincw z0.s // CHECK-INST: uqincw z0.s // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 c7 a0 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincw z0.s, pow2, mul #16 // CHECK-INST: uqincw z0.s, pow2, mul #16 // CHECK-ENCODING: [0x00,0xc4,0xaf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 af 04 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uqincw z0.s, pow2 // CHECK-INST: uqincw z0.s, pow2 // CHECK-ENCODING: [0x00,0xc4,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c4 a0 04 diff --git a/llvm/test/MC/AArch64/SVE/uqsub.s b/llvm/test/MC/AArch64/SVE/uqsub.s index af44866001758..b1e219662d108 100644 --- a/llvm/test/MC/AArch64/SVE/uqsub.s +++ b/llvm/test/MC/AArch64/SVE/uqsub.s @@ -13,109 +13,109 @@ uqsub z0.b, z0.b, z0.b // CHECK-INST: uqsub z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x1c,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 1c 20 04 uqsub z0.h, z0.h, z0.h // CHECK-INST: uqsub z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x1c,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 1c 60 04 uqsub z0.s, z0.s, z0.s // CHECK-INST: uqsub z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x1c,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 1c a0 04 uqsub z0.d, z0.d, z0.d // CHECK-INST: uqsub z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x1c,0xe0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 1c e0 04 uqsub z0.b, z0.b, #0 // CHECK-INST: uqsub z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xc0,0x27,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 27 25 uqsub z31.b, z31.b, #255 // CHECK-INST: uqsub z31.b, z31.b, #255 // CHECK-ENCODING: [0xff,0xdf,0x27,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff df 27 25 uqsub z0.h, z0.h, #0 // CHECK-INST: uqsub z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xc0,0x67,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 67 25 uqsub z0.h, z0.h, #0, lsl #8 // CHECK-INST: uqsub z0.h, z0.h, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0x67,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 67 25 uqsub z31.h, z31.h, #255, lsl #8 // CHECK-INST: uqsub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x67,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 67 25 uqsub z31.h, z31.h, #65280 // CHECK-INST: uqsub z31.h, z31.h, #65280 // CHECK-ENCODING: [0xff,0xff,0x67,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff 67 25 uqsub z0.s, z0.s, #0 // CHECK-INST: uqsub z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xc0,0xa7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 a7 25 uqsub z0.s, z0.s, #0, lsl #8 // CHECK-INST: uqsub z0.s, z0.s, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xa7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 a7 25 uqsub z31.s, z31.s, #255, lsl #8 // CHECK-INST: uqsub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a7 25 uqsub z31.s, z31.s, #65280 // CHECK-INST: uqsub z31.s, z31.s, #65280 // CHECK-ENCODING: [0xff,0xff,0xa7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff a7 25 uqsub z0.d, z0.d, #0 // CHECK-INST: uqsub z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xc0,0xe7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 c0 e7 25 uqsub z0.d, z0.d, #0, lsl #8 // CHECK-INST: uqsub z0.d, z0.d, #0, lsl #8 // CHECK-ENCODING: [0x00,0xe0,0xe7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 e0 e7 25 uqsub z31.d, z31.d, #255, lsl #8 // CHECK-INST: uqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e7 25 uqsub z31.d, z31.d, #65280 // CHECK-INST: uqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e7 25 @@ -125,11 +125,11 @@ uqsub z31.d, z31.d, #65280 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqsub z31.d, z31.d, #65280 // CHECK-INST: uqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff ff e7 25 diff --git a/llvm/test/MC/AArch64/SVE/uunpkhi.s b/llvm/test/MC/AArch64/SVE/uunpkhi.s index d1680973aabb0..32ea44637d231 100644 --- a/llvm/test/MC/AArch64/SVE/uunpkhi.s +++ b/llvm/test/MC/AArch64/SVE/uunpkhi.s @@ -12,17 +12,17 @@ uunpkhi z31.h, z31.b // CHECK-INST: uunpkhi z31.h, z31.b // CHECK-ENCODING: [0xff,0x3b,0x73,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 73 05 uunpkhi z31.s, z31.h // CHECK-INST: uunpkhi z31.s, z31.h // CHECK-ENCODING: [0xff,0x3b,0xb3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b b3 05 uunpkhi z31.d, z31.s // CHECK-INST: uunpkhi z31.d, z31.s // CHECK-ENCODING: [0xff,0x3b,0xf3,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b f3 05 diff --git a/llvm/test/MC/AArch64/SVE/uunpklo.s b/llvm/test/MC/AArch64/SVE/uunpklo.s index bdd69a35cdf8d..e9fa49ce315ec 100644 --- a/llvm/test/MC/AArch64/SVE/uunpklo.s +++ b/llvm/test/MC/AArch64/SVE/uunpklo.s @@ -12,17 +12,17 @@ uunpklo z31.h, z31.b // CHECK-INST: uunpklo z31.h, z31.b // CHECK-ENCODING: [0xff,0x3b,0x72,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b 72 05 uunpklo z31.s, z31.h // CHECK-INST: uunpklo z31.s, z31.h // CHECK-ENCODING: [0xff,0x3b,0xb2,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b b2 05 uunpklo z31.d, z31.s // CHECK-INST: uunpklo z31.d, z31.s // CHECK-ENCODING: [0xff,0x3b,0xf2,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 3b f2 05 diff --git a/llvm/test/MC/AArch64/SVE/uxtb.s b/llvm/test/MC/AArch64/SVE/uxtb.s index f4fdd6635673e..23548252a4273 100644 --- a/llvm/test/MC/AArch64/SVE/uxtb.s +++ b/llvm/test/MC/AArch64/SVE/uxtb.s @@ -12,37 +12,37 @@ uxtb z0.h, p0/m, z0.h // CHECK-INST: uxtb z0.h, p0/m, z0.h // CHECK-ENCODING: [0x00,0xa0,0x51,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 51 04 uxtb z0.s, p0/m, z0.s // CHECK-INST: uxtb z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x91,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 91 04 uxtb z0.d, p0/m, z0.d // CHECK-INST: uxtb z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d1 04 uxtb z31.h, p7/m, z31.h // CHECK-INST: uxtb z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x51,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 51 04 uxtb z31.s, p7/m, z31.s // CHECK-INST: uxtb z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x91,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 91 04 uxtb z31.d, p7/m, z31.d // CHECK-INST: uxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d1 04 @@ -52,23 +52,23 @@ uxtb z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 uxtb z4.d, p7/m, z31.d // CHECK-INST: uxtb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d1 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 uxtb z4.d, p7/m, z31.d // CHECK-INST: uxtb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d1 04 diff --git a/llvm/test/MC/AArch64/SVE/uxth.s b/llvm/test/MC/AArch64/SVE/uxth.s index 8ad1c4ce93ace..43bfa54f708c2 100644 --- a/llvm/test/MC/AArch64/SVE/uxth.s +++ b/llvm/test/MC/AArch64/SVE/uxth.s @@ -12,25 +12,25 @@ uxth z0.s, p0/m, z0.s // CHECK-INST: uxth z0.s, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0x93,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 93 04 uxth z0.d, p0/m, z0.d // CHECK-INST: uxth z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d3 04 uxth z31.s, p7/m, z31.s // CHECK-INST: uxth z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x93,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf 93 04 uxth z31.d, p7/m, z31.d // CHECK-INST: uxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d3 04 @@ -40,23 +40,23 @@ uxth z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 uxth z4.d, p7/m, z31.d // CHECK-INST: uxth z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d3 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 uxth z4.d, p7/m, z31.d // CHECK-INST: uxth z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d3 04 diff --git a/llvm/test/MC/AArch64/SVE/uxtw.s b/llvm/test/MC/AArch64/SVE/uxtw.s index 63b30f237d907..435f733c9d10b 100644 --- a/llvm/test/MC/AArch64/SVE/uxtw.s +++ b/llvm/test/MC/AArch64/SVE/uxtw.s @@ -12,13 +12,13 @@ uxtw z0.d, p0/m, z0.d // CHECK-INST: uxtw z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 a0 d5 04 uxtw z31.d, p7/m, z31.d // CHECK-INST: uxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bf d5 04 @@ -28,23 +28,23 @@ uxtw z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 uxtw z4.d, p7/m, z31.d // CHECK-INST: uxtw z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d5 04 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 uxtw z4.d, p7/m, z31.d // CHECK-INST: uxtw z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e4 bf d5 04 diff --git a/llvm/test/MC/AArch64/SVE/uzp1.s b/llvm/test/MC/AArch64/SVE/uzp1.s index f94f0629614d7..08f6300fcbae3 100644 --- a/llvm/test/MC/AArch64/SVE/uzp1.s +++ b/llvm/test/MC/AArch64/SVE/uzp1.s @@ -12,47 +12,47 @@ uzp1 z31.b, z31.b, z31.b // CHECK-INST: uzp1 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x6b,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6b 3f 05 uzp1 z31.h, z31.h, z31.h // CHECK-INST: uzp1 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x6b,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6b 7f 05 uzp1 z31.s, z31.s, z31.s // CHECK-INST: uzp1 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x6b,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6b bf 05 uzp1 z31.d, z31.d, z31.d // CHECK-INST: uzp1 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x6b,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6b ff 05 uzp1 p15.b, p15.b, p15.b // CHECK-INST: uzp1 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x49,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 49 2f 05 uzp1 p15.s, p15.s, p15.s // CHECK-INST: uzp1 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x49,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 49 af 05 uzp1 p15.h, p15.h, p15.h // CHECK-INST: uzp1 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x49,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 49 6f 05 uzp1 p15.d, p15.d, p15.d // CHECK-INST: uzp1 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x49,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 49 ef 05 diff --git a/llvm/test/MC/AArch64/SVE/uzp2.s b/llvm/test/MC/AArch64/SVE/uzp2.s index c8ccacc5b7779..5a9285042811a 100644 --- a/llvm/test/MC/AArch64/SVE/uzp2.s +++ b/llvm/test/MC/AArch64/SVE/uzp2.s @@ -12,47 +12,47 @@ uzp2 z31.b, z31.b, z31.b // CHECK-INST: uzp2 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x6f,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6f 3f 05 uzp2 z31.h, z31.h, z31.h // CHECK-INST: uzp2 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x6f,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6f 7f 05 uzp2 z31.s, z31.s, z31.s // CHECK-INST: uzp2 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x6f,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6f bf 05 uzp2 z31.d, z31.d, z31.d // CHECK-INST: uzp2 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x6f,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 6f ff 05 uzp2 p15.b, p15.b, p15.b // CHECK-INST: uzp2 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x4d,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 4d 2f 05 uzp2 p15.s, p15.s, p15.s // CHECK-INST: uzp2 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x4d,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 4d af 05 uzp2 p15.h, p15.h, p15.h // CHECK-INST: uzp2 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x4d,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 4d 6f 05 uzp2 p15.d, p15.d, p15.d // CHECK-INST: uzp2 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x4d,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 4d ef 05 diff --git a/llvm/test/MC/AArch64/SVE/whilele.s b/llvm/test/MC/AArch64/SVE/whilele.s index 6f1d519aa1bcd..a6cd350e5a4f1 100644 --- a/llvm/test/MC/AArch64/SVE/whilele.s +++ b/llvm/test/MC/AArch64/SVE/whilele.s @@ -12,59 +12,59 @@ whilele p15.b, xzr, x0 // CHECK-INST: whilele p15.b, xzr, x0 // CHECK-ENCODING: [0xff,0x17,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 17 20 25 whilele p15.b, x0, xzr // CHECK-INST: whilele p15.b, x0, xzr // CHECK-ENCODING: [0x1f,0x14,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 14 3f 25 whilele p15.b, wzr, w0 // CHECK-INST: whilele p15.b, wzr, w0 // CHECK-ENCODING: [0xff,0x07,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 07 20 25 whilele p15.b, w0, wzr // CHECK-INST: whilele p15.b, w0, wzr // CHECK-ENCODING: [0x1f,0x04,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 04 3f 25 whilele p15.h, x0, xzr // CHECK-INST: whilele p15.h, x0, xzr // CHECK-ENCODING: [0x1f,0x14,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 14 7f 25 whilele p15.h, w0, wzr // CHECK-INST: whilele p15.h, w0, wzr // CHECK-ENCODING: [0x1f,0x04,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 04 7f 25 whilele p15.s, x0, xzr // CHECK-INST: whilele p15.s, x0, xzr // CHECK-ENCODING: [0x1f,0x14,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 14 bf 25 whilele p15.s, w0, wzr // CHECK-INST: whilele p15.s, w0, wzr // CHECK-ENCODING: [0x1f,0x04,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 04 bf 25 whilele p15.d, w0, wzr // CHECK-INST: whilele p15.d, w0, wzr // CHECK-ENCODING: [0x1f,0x04,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 04 ff 25 whilele p15.d, x0, xzr // CHECK-INST: whilele p15.d, x0, xzr // CHECK-ENCODING: [0x1f,0x14,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 14 ff 25 diff --git a/llvm/test/MC/AArch64/SVE/whilelo.s b/llvm/test/MC/AArch64/SVE/whilelo.s index 0246b0f4c3917..4d083d24aec58 100644 --- a/llvm/test/MC/AArch64/SVE/whilelo.s +++ b/llvm/test/MC/AArch64/SVE/whilelo.s @@ -12,59 +12,59 @@ whilelo p15.b, xzr, x0 // CHECK-INST: whilelo p15.b, xzr, x0 // CHECK-ENCODING: [0xef,0x1f,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 1f 20 25 whilelo p15.b, x0, xzr // CHECK-INST: whilelo p15.b, x0, xzr // CHECK-ENCODING: [0x0f,0x1c,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 1c 3f 25 whilelo p15.b, wzr, w0 // CHECK-INST: whilelo p15.b, wzr, w0 // CHECK-ENCODING: [0xef,0x0f,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 0f 20 25 whilelo p15.b, w0, wzr // CHECK-INST: whilelo p15.b, w0, wzr // CHECK-ENCODING: [0x0f,0x0c,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 0c 3f 25 whilelo p15.h, x0, xzr // CHECK-INST: whilelo p15.h, x0, xzr // CHECK-ENCODING: [0x0f,0x1c,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 1c 7f 25 whilelo p15.h, w0, wzr // CHECK-INST: whilelo p15.h, w0, wzr // CHECK-ENCODING: [0x0f,0x0c,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 0c 7f 25 whilelo p15.s, x0, xzr // CHECK-INST: whilelo p15.s, x0, xzr // CHECK-ENCODING: [0x0f,0x1c,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 1c bf 25 whilelo p15.s, w0, wzr // CHECK-INST: whilelo p15.s, w0, wzr // CHECK-ENCODING: [0x0f,0x0c,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 0c bf 25 whilelo p15.d, w0, wzr // CHECK-INST: whilelo p15.d, w0, wzr // CHECK-ENCODING: [0x0f,0x0c,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 0c ff 25 whilelo p15.d, x0, xzr // CHECK-INST: whilelo p15.d, x0, xzr // CHECK-ENCODING: [0x0f,0x1c,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 1c ff 25 diff --git a/llvm/test/MC/AArch64/SVE/whilels.s b/llvm/test/MC/AArch64/SVE/whilels.s index 39342d72d3d5a..4ad0e3ef99f7b 100644 --- a/llvm/test/MC/AArch64/SVE/whilels.s +++ b/llvm/test/MC/AArch64/SVE/whilels.s @@ -12,59 +12,59 @@ whilels p15.b, xzr, x0 // CHECK-INST: whilels p15.b, xzr, x0 // CHECK-ENCODING: [0xff,0x1f,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 1f 20 25 whilels p15.b, x0, xzr // CHECK-INST: whilels p15.b, x0, xzr // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c 3f 25 whilels p15.b, wzr, w0 // CHECK-INST: whilels p15.b, wzr, w0 // CHECK-ENCODING: [0xff,0x0f,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 0f 20 25 whilels p15.b, w0, wzr // CHECK-INST: whilels p15.b, w0, wzr // CHECK-ENCODING: [0x1f,0x0c,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 0c 3f 25 whilels p15.h, x0, xzr // CHECK-INST: whilels p15.h, x0, xzr // CHECK-ENCODING: [0x1f,0x1c,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c 7f 25 whilels p15.h, w0, wzr // CHECK-INST: whilels p15.h, w0, wzr // CHECK-ENCODING: [0x1f,0x0c,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 0c 7f 25 whilels p15.s, x0, xzr // CHECK-INST: whilels p15.s, x0, xzr // CHECK-ENCODING: [0x1f,0x1c,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c bf 25 whilels p15.s, w0, wzr // CHECK-INST: whilels p15.s, w0, wzr // CHECK-ENCODING: [0x1f,0x0c,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 0c bf 25 whilels p15.d, w0, wzr // CHECK-INST: whilels p15.d, w0, wzr // CHECK-ENCODING: [0x1f,0x0c,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 0c ff 25 whilels p15.d, x0, xzr // CHECK-INST: whilels p15.d, x0, xzr // CHECK-ENCODING: [0x1f,0x1c,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 1f 1c ff 25 diff --git a/llvm/test/MC/AArch64/SVE/whilelt.s b/llvm/test/MC/AArch64/SVE/whilelt.s index 4c915305b1d3b..5b7f4f16efc00 100644 --- a/llvm/test/MC/AArch64/SVE/whilelt.s +++ b/llvm/test/MC/AArch64/SVE/whilelt.s @@ -12,59 +12,59 @@ whilelt p15.b, xzr, x0 // CHECK-INST: whilelt p15.b, xzr, x0 // CHECK-ENCODING: [0xef,0x17,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 17 20 25 whilelt p15.b, x0, xzr // CHECK-INST: whilelt p15.b, x0, xzr // CHECK-ENCODING: [0x0f,0x14,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 14 3f 25 whilelt p15.b, wzr, w0 // CHECK-INST: whilelt p15.b, wzr, w0 // CHECK-ENCODING: [0xef,0x07,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 07 20 25 whilelt p15.b, w0, wzr // CHECK-INST: whilelt p15.b, w0, wzr // CHECK-ENCODING: [0x0f,0x04,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 04 3f 25 whilelt p15.h, x0, xzr // CHECK-INST: whilelt p15.h, x0, xzr // CHECK-ENCODING: [0x0f,0x14,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 14 7f 25 whilelt p15.h, w0, wzr // CHECK-INST: whilelt p15.h, w0, wzr // CHECK-ENCODING: [0x0f,0x04,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 04 7f 25 whilelt p15.s, x0, xzr // CHECK-INST: whilelt p15.s, x0, xzr // CHECK-ENCODING: [0x0f,0x14,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 14 bf 25 whilelt p15.s, w0, wzr // CHECK-INST: whilelt p15.s, w0, wzr // CHECK-ENCODING: [0x0f,0x04,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 04 bf 25 whilelt p15.d, w0, wzr // CHECK-INST: whilelt p15.d, w0, wzr // CHECK-ENCODING: [0x0f,0x04,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 04 ff 25 whilelt p15.d, x0, xzr // CHECK-INST: whilelt p15.d, x0, xzr // CHECK-ENCODING: [0x0f,0x14,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 0f 14 ff 25 diff --git a/llvm/test/MC/AArch64/SVE/zip1.s b/llvm/test/MC/AArch64/SVE/zip1.s index bacef95cdf81f..c416bbc563a21 100644 --- a/llvm/test/MC/AArch64/SVE/zip1.s +++ b/llvm/test/MC/AArch64/SVE/zip1.s @@ -12,95 +12,95 @@ zip1 z0.b, z0.b, z0.b // CHECK-INST: zip1 z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x60,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 20 05 zip1 z0.h, z0.h, z0.h // CHECK-INST: zip1 z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x60,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 60 05 zip1 z0.s, z0.s, z0.s // CHECK-INST: zip1 z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x60,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 a0 05 zip1 z0.d, z0.d, z0.d // CHECK-INST: zip1 z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x60,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 60 e0 05 zip1 z31.b, z31.b, z31.b // CHECK-INST: zip1 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x63,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 63 3f 05 zip1 z31.h, z31.h, z31.h // CHECK-INST: zip1 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x63,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 63 7f 05 zip1 z31.s, z31.s, z31.s // CHECK-INST: zip1 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x63,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 63 bf 05 zip1 z31.d, z31.d, z31.d // CHECK-INST: zip1 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x63,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 63 ff 05 zip1 p0.b, p0.b, p0.b // CHECK-INST: zip1 p0.b, p0.b, p0.b // CHECK-ENCODING: [0x00,0x40,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 20 05 zip1 p0.h, p0.h, p0.h // CHECK-INST: zip1 p0.h, p0.h, p0.h // CHECK-ENCODING: [0x00,0x40,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 05 zip1 p0.s, p0.s, p0.s // CHECK-INST: zip1 p0.s, p0.s, p0.s // CHECK-ENCODING: [0x00,0x40,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 a0 05 zip1 p0.d, p0.d, p0.d // CHECK-INST: zip1 p0.d, p0.d, p0.d // CHECK-ENCODING: [0x00,0x40,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 05 zip1 p15.b, p15.b, p15.b // CHECK-INST: zip1 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x41,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 2f 05 zip1 p15.s, p15.s, p15.s // CHECK-INST: zip1 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x41,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 af 05 zip1 p15.h, p15.h, p15.h // CHECK-INST: zip1 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x41,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 6f 05 zip1 p15.d, p15.d, p15.d // CHECK-INST: zip1 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x41,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 41 ef 05 diff --git a/llvm/test/MC/AArch64/SVE/zip2.s b/llvm/test/MC/AArch64/SVE/zip2.s index 56eb686079659..7944b3804b8b8 100644 --- a/llvm/test/MC/AArch64/SVE/zip2.s +++ b/llvm/test/MC/AArch64/SVE/zip2.s @@ -12,95 +12,95 @@ zip2 z0.b, z0.b, z0.b // CHECK-INST: zip2 z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x64,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 64 20 05 zip2 z0.h, z0.h, z0.h // CHECK-INST: zip2 z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x64,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 64 60 05 zip2 z0.s, z0.s, z0.s // CHECK-INST: zip2 z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x64,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 64 a0 05 zip2 z0.d, z0.d, z0.d // CHECK-INST: zip2 z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x64,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 64 e0 05 zip2 z31.b, z31.b, z31.b // CHECK-INST: zip2 z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x67,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 67 3f 05 zip2 z31.h, z31.h, z31.h // CHECK-INST: zip2 z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x67,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 67 7f 05 zip2 z31.s, z31.s, z31.s // CHECK-INST: zip2 z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x67,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 67 bf 05 zip2 z31.d, z31.d, z31.d // CHECK-INST: zip2 z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x67,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff 67 ff 05 zip2 p0.b, p0.b, p0.b // CHECK-INST: zip2 p0.b, p0.b, p0.b // CHECK-ENCODING: [0x00,0x44,0x20,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 44 20 05 zip2 p0.h, p0.h, p0.h // CHECK-INST: zip2 p0.h, p0.h, p0.h // CHECK-ENCODING: [0x00,0x44,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 44 60 05 zip2 p0.s, p0.s, p0.s // CHECK-INST: zip2 p0.s, p0.s, p0.s // CHECK-ENCODING: [0x00,0x44,0xa0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 44 a0 05 zip2 p0.d, p0.d, p0.d // CHECK-INST: zip2 p0.d, p0.d, p0.d // CHECK-ENCODING: [0x00,0x44,0xe0,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 44 e0 05 zip2 p15.b, p15.b, p15.b // CHECK-INST: zip2 p15.b, p15.b, p15.b // CHECK-ENCODING: [0xef,0x45,0x2f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 45 2f 05 zip2 p15.h, p15.h, p15.h // CHECK-INST: zip2 p15.h, p15.h, p15.h // CHECK-ENCODING: [0xef,0x45,0x6f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 45 6f 05 zip2 p15.s, p15.s, p15.s // CHECK-INST: zip2 p15.s, p15.s, p15.s // CHECK-ENCODING: [0xef,0x45,0xaf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 45 af 05 zip2 p15.d, p15.d, p15.d // CHECK-INST: zip2 p15.d, p15.d, p15.d // CHECK-ENCODING: [0xef,0x45,0xef,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ef 45 ef 05 diff --git a/llvm/test/MC/AArch64/SVE2/adclb.s b/llvm/test/MC/AArch64/SVE2/adclb.s index 4903e4fbe966e..e3150a458a927 100644 --- a/llvm/test/MC/AArch64/SVE2/adclb.s +++ b/llvm/test/MC/AArch64/SVE2/adclb.s @@ -12,13 +12,13 @@ adclb z0.s, z1.s, z31.s // CHECK-INST: adclb z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xd0,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 1f 45 adclb z0.d, z1.d, z31.d // CHECK-INST: adclb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd0,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 5f 45 @@ -28,11 +28,11 @@ adclb z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 adclb z0.d, z1.d, z31.d // CHECK-INST: adclb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd0,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/adclt.s b/llvm/test/MC/AArch64/SVE2/adclt.s index 97f812875a0bf..57cfbd888e372 100644 --- a/llvm/test/MC/AArch64/SVE2/adclt.s +++ b/llvm/test/MC/AArch64/SVE2/adclt.s @@ -12,13 +12,13 @@ adclt z0.s, z1.s, z31.s // CHECK-INST: adclt z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xd4,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 1f 45 adclt z0.d, z1.d, z31.d // CHECK-INST: adclt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd4,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 5f 45 @@ -28,11 +28,11 @@ adclt z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 adclt z0.d, z1.d, z31.d // CHECK-INST: adclt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd4,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/addhnb.s b/llvm/test/MC/AArch64/SVE2/addhnb.s index 734da7ac3a039..5071e3bff0977 100644 --- a/llvm/test/MC/AArch64/SVE2/addhnb.s +++ b/llvm/test/MC/AArch64/SVE2/addhnb.s @@ -13,17 +13,17 @@ addhnb z0.b, z1.h, z31.h // CHECK-INST: addhnb z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x60,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 7f 45 addhnb z0.h, z1.s, z31.s // CHECK-INST: addhnb z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x60,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 bf 45 addhnb z0.s, z1.d, z31.d // CHECK-INST: addhnb z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x60,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/addhnt.s b/llvm/test/MC/AArch64/SVE2/addhnt.s index 120a218a41168..9b69b71fe8bc6 100644 --- a/llvm/test/MC/AArch64/SVE2/addhnt.s +++ b/llvm/test/MC/AArch64/SVE2/addhnt.s @@ -13,17 +13,17 @@ addhnt z0.b, z1.h, z31.h // CHECK-INST: addhnt z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x64,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 7f 45 addhnt z0.h, z1.s, z31.s // CHECK-INST: addhnt z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x64,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 bf 45 addhnt z0.s, z1.d, z31.d // CHECK-INST: addhnt z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x64,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/addp.s b/llvm/test/MC/AArch64/SVE2/addp.s index 4147f9c259194..9e90f8997e3b2 100644 --- a/llvm/test/MC/AArch64/SVE2/addp.s +++ b/llvm/test/MC/AArch64/SVE2/addp.s @@ -12,25 +12,25 @@ addp z0.b, p0/m, z0.b, z1.b // CHECK-INST: addp z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0xa0,0x11,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 11 44 addp z0.h, p0/m, z0.h, z1.h // CHECK-INST: addp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0xa0,0x51,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 51 44 addp z29.s, p7/m, z29.s, z30.s // CHECK-INST: addp z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0xbf,0x91,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd bf 91 44 addp z31.d, p7/m, z31.d, z30.d // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d1 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ addp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 addp z31.d, p0/m, z31.d, z30.d // CHECK-INST: addp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 d1 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 addp z31.d, p7/m, z31.d, z30.d // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d1 44 diff --git a/llvm/test/MC/AArch64/SVE2/bcax.s b/llvm/test/MC/AArch64/SVE2/bcax.s index 5c23d7fbe3c98..36752595c822d 100644 --- a/llvm/test/MC/AArch64/SVE2/bcax.s +++ b/llvm/test/MC/AArch64/SVE2/bcax.s @@ -12,7 +12,7 @@ bcax z29.d, z29.d, z30.d, z31.d // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 7e 04 @@ -22,19 +22,19 @@ bcax z29.d, z29.d, z30.d, z31.d bcax z29.b, z29.b, z30.b, z31.b // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 7e 04 bcax z29.h, z29.h, z30.h, z31.h // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 7e 04 bcax z29.s, z29.s, z30.s, z31.s // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 7e 04 @@ -44,11 +44,11 @@ bcax z29.s, z29.s, z30.s, z31.s movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 bcax z31.d, z31.d, z30.d, z29.d // CHECK-INST: bcax z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3b,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3b 7e 04 diff --git a/llvm/test/MC/AArch64/SVE2/bsl.s b/llvm/test/MC/AArch64/SVE2/bsl.s index 7a7172a885223..a3ec691c4fdfb 100644 --- a/llvm/test/MC/AArch64/SVE2/bsl.s +++ b/llvm/test/MC/AArch64/SVE2/bsl.s @@ -12,7 +12,7 @@ bsl z0.d, z0.d, z1.d, z2.d // CHECK-INST: bsl z0.d, z0.d, z1.d, z2.d // CHECK-ENCODING: [0x40,0x3c,0x21,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 40 3c 21 04 @@ -22,11 +22,11 @@ bsl z0.d, z0.d, z1.d, z2.d movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 bsl z31.d, z31.d, z30.d, z29.d // CHECK-INST: bsl z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3f,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3f 3e 04 diff --git a/llvm/test/MC/AArch64/SVE2/bsl1n.s b/llvm/test/MC/AArch64/SVE2/bsl1n.s index 49d1a7e5afbbb..15438341b3aff 100644 --- a/llvm/test/MC/AArch64/SVE2/bsl1n.s +++ b/llvm/test/MC/AArch64/SVE2/bsl1n.s @@ -12,7 +12,7 @@ bsl1n z0.d, z0.d, z1.d, z2.d // CHECK-INST: bsl1n z0.d, z0.d, z1.d, z2.d // CHECK-ENCODING: [0x40,0x3c,0x61,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 40 3c 61 04 @@ -22,11 +22,11 @@ bsl1n z0.d, z0.d, z1.d, z2.d movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 bsl1n z31.d, z31.d, z30.d, z29.d // CHECK-INST: bsl1n z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3f,0x7e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3f 7e 04 diff --git a/llvm/test/MC/AArch64/SVE2/bsl2n.s b/llvm/test/MC/AArch64/SVE2/bsl2n.s index 77d5221053672..623f6e3605a2f 100644 --- a/llvm/test/MC/AArch64/SVE2/bsl2n.s +++ b/llvm/test/MC/AArch64/SVE2/bsl2n.s @@ -12,7 +12,7 @@ bsl2n z0.d, z0.d, z1.d, z2.d // CHECK-INST: bsl2n z0.d, z0.d, z1.d, z2.d // CHECK-ENCODING: [0x40,0x3c,0xa1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 40 3c a1 04 @@ -22,11 +22,11 @@ bsl2n z0.d, z0.d, z1.d, z2.d movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 bsl2n z31.d, z31.d, z30.d, z29.d // CHECK-INST: bsl2n z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3f,0xbe,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3f be 04 diff --git a/llvm/test/MC/AArch64/SVE2/cadd.s b/llvm/test/MC/AArch64/SVE2/cadd.s index c4e4b9f0a4b2d..a27fc6c623bb7 100644 --- a/llvm/test/MC/AArch64/SVE2/cadd.s +++ b/llvm/test/MC/AArch64/SVE2/cadd.s @@ -12,49 +12,49 @@ cadd z0.b, z0.b, z0.b, #90 // CHECK-INST: cadd z0.b, z0.b, z0.b, #90 // CHECK-ENCODING: [0x00,0xd8,0x00,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 00 45 cadd z0.h, z0.h, z0.h, #90 // CHECK-INST: cadd z0.h, z0.h, z0.h, #90 // CHECK-ENCODING: [0x00,0xd8,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 40 45 cadd z0.s, z0.s, z0.s, #90 // CHECK-INST: cadd z0.s, z0.s, z0.s, #90 // CHECK-ENCODING: [0x00,0xd8,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 80 45 cadd z0.d, z0.d, z0.d, #90 // CHECK-INST: cadd z0.d, z0.d, z0.d, #90 // CHECK-ENCODING: [0x00,0xd8,0xc0,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 c0 45 cadd z31.b, z31.b, z31.b, #270 // CHECK-INST: cadd z31.b, z31.b, z31.b, #270 // CHECK-ENCODING: [0xff,0xdf,0x00,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 00 45 cadd z31.h, z31.h, z31.h, #270 // CHECK-INST: cadd z31.h, z31.h, z31.h, #270 // CHECK-ENCODING: [0xff,0xdf,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 40 45 cadd z31.s, z31.s, z31.s, #270 // CHECK-INST: cadd z31.s, z31.s, z31.s, #270 // CHECK-ENCODING: [0xff,0xdf,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 80 45 cadd z31.d, z31.d, z31.d, #270 // CHECK-INST: cadd z31.d, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0xdf,0xc0,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df c0 45 @@ -64,11 +64,11 @@ cadd z31.d, z31.d, z31.d, #270 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cadd z4.d, z4.d, z31.d, #270 // CHECK-INST: cadd z4.d, z4.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0xdf,0xc0,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 df c0 45 diff --git a/llvm/test/MC/AArch64/SVE2/cdot.s b/llvm/test/MC/AArch64/SVE2/cdot.s index 8e83f2f8ba435..1a9386fa486f8 100644 --- a/llvm/test/MC/AArch64/SVE2/cdot.s +++ b/llvm/test/MC/AArch64/SVE2/cdot.s @@ -12,61 +12,61 @@ cdot z0.s, z1.b, z31.b, #0 // CHECK-INST: cdot z0.s, z1.b, z31.b, #0 // CHECK-ENCODING: [0x20,0x10,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 9f 44 cdot z0.d, z1.h, z31.h, #0 // CHECK-INST: cdot z0.d, z1.h, z31.h, #0 // CHECK-ENCODING: [0x20,0x10,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 df 44 cdot z0.d, z1.h, z31.h, #90 // CHECK-INST: cdot z0.d, z1.h, z31.h, #90 // CHECK-ENCODING: [0x20,0x14,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 df 44 cdot z0.d, z1.h, z31.h, #180 // CHECK-INST: cdot z0.d, z1.h, z31.h, #180 // CHECK-ENCODING: [0x20,0x18,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 18 df 44 cdot z0.d, z1.h, z31.h, #270 // CHECK-INST: cdot z0.d, z1.h, z31.h, #270 // CHECK-ENCODING: [0x20,0x1c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 1c df 44 cdot z0.s, z1.b, z7.b[3], #0 // CHECK-INST: cdot z0.s, z1.b, z7.b[3], #0 // CHECK-ENCODING: [0x20,0x40,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 bf 44 cdot z0.d, z1.h, z15.h[1], #0 // CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0 // CHECK-ENCODING: [0x20,0x40,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 ff 44 cdot z5.d, z6.h, z3.h[0], #90 // CHECK-INST: cdot z5.d, z6.h, z3.h[0], #90 // CHECK-ENCODING: [0xc5,0x44,0xe3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: c5 44 e3 44 cdot z29.d, z30.h, z0.h[0], #180 // CHECK-INST: cdot z29.d, z30.h, z0.h[0], #180 // CHECK-ENCODING: [0xdd,0x4b,0xe0,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 4b e0 44 cdot z31.d, z30.h, z7.h[1], #270 // CHECK-INST: cdot z31.d, z30.h, z7.h[1], #270 // CHECK-ENCODING: [0xdf,0x4f,0xf7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 4f f7 44 @@ -76,23 +76,23 @@ cdot z31.d, z30.h, z7.h[1], #270 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 cdot z0.d, z1.h, z31.h, #0 // CHECK-INST: cdot z0.d, z1.h, z31.h, #0 // CHECK-ENCODING: [0x20,0x10,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 df 44 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 cdot z0.d, z1.h, z15.h[1], #0 // CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0 // CHECK-ENCODING: [0x20,0x40,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/cmla.s b/llvm/test/MC/AArch64/SVE2/cmla.s index b65555bb7fa19..4e93d1b384ca5 100644 --- a/llvm/test/MC/AArch64/SVE2/cmla.s +++ b/llvm/test/MC/AArch64/SVE2/cmla.s @@ -12,121 +12,121 @@ cmla z0.b, z1.b, z2.b, #0 // CHECK-INST: cmla z0.b, z1.b, z2.b, #0 // CHECK-ENCODING: [0x20,0x20,0x02,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 20 02 44 cmla z0.h, z1.h, z2.h, #0 // CHECK-INST: cmla z0.h, z1.h, z2.h, #0 // CHECK-ENCODING: [0x20,0x20,0x42,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 20 42 44 cmla z0.s, z1.s, z2.s, #0 // CHECK-INST: cmla z0.s, z1.s, z2.s, #0 // CHECK-ENCODING: [0x20,0x20,0x82,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 20 82 44 cmla z0.d, z1.d, z2.d, #0 // CHECK-INST: cmla z0.d, z1.d, z2.d, #0 // CHECK-ENCODING: [0x20,0x20,0xc2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 20 c2 44 cmla z29.b, z30.b, z31.b, #90 // CHECK-INST: cmla z29.b, z30.b, z31.b, #90 // CHECK-ENCODING: [0xdd,0x27,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 27 1f 44 cmla z29.h, z30.h, z31.h, #90 // CHECK-INST: cmla z29.h, z30.h, z31.h, #90 // CHECK-ENCODING: [0xdd,0x27,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 27 5f 44 cmla z29.s, z30.s, z31.s, #90 // CHECK-INST: cmla z29.s, z30.s, z31.s, #90 // CHECK-ENCODING: [0xdd,0x27,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 27 9f 44 cmla z29.d, z30.d, z31.d, #90 // CHECK-INST: cmla z29.d, z30.d, z31.d, #90 // CHECK-ENCODING: [0xdd,0x27,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 27 df 44 cmla z31.b, z31.b, z31.b, #180 // CHECK-INST: cmla z31.b, z31.b, z31.b, #180 // CHECK-ENCODING: [0xff,0x2b,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 1f 44 cmla z31.h, z31.h, z31.h, #180 // CHECK-INST: cmla z31.h, z31.h, z31.h, #180 // CHECK-ENCODING: [0xff,0x2b,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 5f 44 cmla z31.s, z31.s, z31.s, #180 // CHECK-INST: cmla z31.s, z31.s, z31.s, #180 // CHECK-ENCODING: [0xff,0x2b,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 9f 44 cmla z31.d, z31.d, z31.d, #180 // CHECK-INST: cmla z31.d, z31.d, z31.d, #180 // CHECK-ENCODING: [0xff,0x2b,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b df 44 cmla z15.b, z16.b, z17.b, #270 // CHECK-INST: cmla z15.b, z16.b, z17.b, #270 // CHECK-ENCODING: [0x0f,0x2e,0x11,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 2e 11 44 cmla z15.h, z16.h, z17.h, #270 // CHECK-INST: cmla z15.h, z16.h, z17.h, #270 // CHECK-ENCODING: [0x0f,0x2e,0x51,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 2e 51 44 cmla z15.s, z16.s, z17.s, #270 // CHECK-INST: cmla z15.s, z16.s, z17.s, #270 // CHECK-ENCODING: [0x0f,0x2e,0x91,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 2e 91 44 cmla z15.d, z16.d, z17.d, #270 // CHECK-INST: cmla z15.d, z16.d, z17.d, #270 // CHECK-ENCODING: [0x0f,0x2e,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 2e d1 44 cmla z0.h, z1.h, z2.h[0], #0 // CHECK-INST: cmla z0.h, z1.h, z2.h[0], #0 // CHECK-ENCODING: [0x20,0x60,0xa2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 a2 44 cmla z0.s, z1.s, z2.s[0], #0 // CHECK-INST: cmla z0.s, z1.s, z2.s[0], #0 // CHECK-ENCODING: [0x20,0x60,0xe2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 e2 44 cmla z31.h, z30.h, z7.h[0], #180 // CHECK-INST: cmla z31.h, z30.h, z7.h[0], #180 // CHECK-ENCODING: [0xdf,0x6b,0xa7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 6b a7 44 cmla z31.s, z30.s, z7.s[0], #180 // CHECK-INST: cmla z31.s, z30.s, z7.s[0], #180 // CHECK-ENCODING: [0xdf,0x6b,0xe7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 6b e7 44 @@ -136,23 +136,23 @@ cmla z31.s, z30.s, z7.s[0], #180 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 cmla z4.d, z31.d, z31.d, #270 // CHECK-INST: cmla z4.d, z31.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x2f,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 2f df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 cmla z21.s, z10.s, z5.s[1], #90 // CHECK-INST: cmla z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x65,0xf5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 65 f5 44 diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s index 6042d5692f047..767e5dc5a1513 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s @@ -3,7 +3,7 @@ .arch armv9-a+sve2 .arch armv9-a+nosve2 tbx z0.b, z1.b, z2.b -// CHECK: error: instruction requires: streaming-sve or sve2 +// CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b .arch armv9-a+sve2-aes diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s index 764531714e43f..6d90f7f057490 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s @@ -3,7 +3,7 @@ .arch_extension sve2 .arch_extension nosve2 tbx z0.b, z1.b, z2.b -// CHECK: error: instruction requires: streaming-sve or sve2 +// CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b .arch_extension sve2-aes diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s index 79a28fc6e814e..ed99aa7f00786 100644 --- a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s +++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s @@ -3,7 +3,7 @@ .cpu generic+sve2 .cpu generic+nosve2 tbx z0.b, z1.b, z2.b -// CHECK: error: instruction requires: streaming-sve or sve2 +// CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b .cpu generic+sve2-aes diff --git a/llvm/test/MC/AArch64/SVE2/eor3.s b/llvm/test/MC/AArch64/SVE2/eor3.s index 757ebd7c6a7c4..f5ac2dba9ba05 100644 --- a/llvm/test/MC/AArch64/SVE2/eor3.s +++ b/llvm/test/MC/AArch64/SVE2/eor3.s @@ -12,7 +12,7 @@ eor3 z29.d, z29.d, z30.d, z31.d // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 3e 04 @@ -22,19 +22,19 @@ eor3 z29.d, z29.d, z30.d, z31.d eor3 z29.b, z29.b, z30.b, z31.b // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 3e 04 eor3 z29.h, z29.h, z30.h, z31.h // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 3e 04 eor3 z29.s, z29.s, z30.s, z31.s // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fd 3b 3e 04 @@ -44,11 +44,11 @@ eor3 z29.s, z29.s, z30.s, z31.s movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 eor3 z31.d, z31.d, z30.d, z29.d // CHECK-INST: eor3 z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3b,0x3e,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3b 3e 04 diff --git a/llvm/test/MC/AArch64/SVE2/eorbt.s b/llvm/test/MC/AArch64/SVE2/eorbt.s index a949e022095b8..8f71c71a37f23 100644 --- a/llvm/test/MC/AArch64/SVE2/eorbt.s +++ b/llvm/test/MC/AArch64/SVE2/eorbt.s @@ -12,25 +12,25 @@ eorbt z0.b, z1.b, z31.b // CHECK-INST: eorbt z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0x90,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 90 1f 45 eorbt z0.h, z1.h, z31.h // CHECK-INST: eorbt z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x90,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 90 5f 45 eorbt z0.s, z1.s, z31.s // CHECK-INST: eorbt z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x90,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 90 9f 45 eorbt z0.d, z1.d, z31.d // CHECK-INST: eorbt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x90,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 90 df 45 @@ -40,11 +40,11 @@ eorbt z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 eorbt z0.d, z1.d, z31.d // CHECK-INST: eorbt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x90,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 90 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/eortb.s b/llvm/test/MC/AArch64/SVE2/eortb.s index 304ac1302f4b6..1d3016e90c7bc 100644 --- a/llvm/test/MC/AArch64/SVE2/eortb.s +++ b/llvm/test/MC/AArch64/SVE2/eortb.s @@ -12,25 +12,25 @@ eortb z0.b, z1.b, z31.b // CHECK-INST: eortb z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0x94,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 94 1f 45 eortb z0.h, z1.h, z31.h // CHECK-INST: eortb z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x94,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 94 5f 45 eortb z0.s, z1.s, z31.s // CHECK-INST: eortb z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x94,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 94 9f 45 eortb z0.d, z1.d, z31.d // CHECK-INST: eortb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x94,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 94 df 45 @@ -40,11 +40,11 @@ eortb z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 eortb z0.d, z1.d, z31.d // CHECK-INST: eortb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x94,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 94 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ext.s b/llvm/test/MC/AArch64/SVE2/ext.s index 3f1537f124bc4..262b5ad0def27 100644 --- a/llvm/test/MC/AArch64/SVE2/ext.s +++ b/llvm/test/MC/AArch64/SVE2/ext.s @@ -12,11 +12,11 @@ ext z0.b, { z1.b, z2.b }, #0 // CHECK-INST: ext z0.b, { z1.b, z2.b }, #0 // CHECK-ENCODING: [0x20,0x00,0x60,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 00 60 05 ext z31.b, { z30.b, z31.b }, #255 // CHECK-INST: ext z31.b, { z30.b, z31.b }, #255 // CHECK-ENCODING: [0xdf,0x1f,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 1f 7f 05 diff --git a/llvm/test/MC/AArch64/SVE2/faddp.s b/llvm/test/MC/AArch64/SVE2/faddp.s index 53a6510d1a45e..77b6dea6ff456 100644 --- a/llvm/test/MC/AArch64/SVE2/faddp.s +++ b/llvm/test/MC/AArch64/SVE2/faddp.s @@ -12,19 +12,19 @@ faddp z0.h, p0/m, z0.h, z1.h // CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x50,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 50 64 faddp z29.s, p3/m, z29.s, z30.s // CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x8f,0x90,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 8f 90 64 faddp z31.d, p7/m, z31.d, z30.d // CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d0 64 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ faddp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 faddp z31.d, p0/m, z31.d, z30.d // CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d0 64 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 faddp z31.d, p7/m, z31.d, z30.d // CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d0 64 diff --git a/llvm/test/MC/AArch64/SVE2/fcvtlt.s b/llvm/test/MC/AArch64/SVE2/fcvtlt.s index 521de9ff80e56..5120a74b19712 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtlt.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtlt.s @@ -13,11 +13,11 @@ fcvtlt z0.s, p0/m, z1.h // CHECK-INST: fcvtlt z0.s, p0/m, z1.h // CHECK-ENCODING: [0x20,0xa0,0x89,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 89 64 fcvtlt z30.d, p7/m, z31.s // CHECK-INST: fcvtlt z30.d, p7/m, z31.s // CHECK-ENCODING: [0xfe,0xbf,0xcb,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf cb 64 diff --git a/llvm/test/MC/AArch64/SVE2/fcvtnt.s b/llvm/test/MC/AArch64/SVE2/fcvtnt.s index 04a2b1db7c0c3..1d314ef65ab1b 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtnt.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtnt.s @@ -13,11 +13,11 @@ fcvtnt z0.h, p0/m, z1.s // CHECK-INST: fcvtnt z0.h, p0/m, z1.s // CHECK-ENCODING: [0x20,0xa0,0x88,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 88 64 fcvtnt z30.s, p7/m, z31.d // CHECK-INST: fcvtnt z30.s, p7/m, z31.d // CHECK-ENCODING: [0xfe,0xbf,0xca,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf ca 64 diff --git a/llvm/test/MC/AArch64/SVE2/fcvtx.s b/llvm/test/MC/AArch64/SVE2/fcvtx.s index c1a10a9227429..f22ba0f2a0bc1 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtx.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtx.s @@ -13,13 +13,13 @@ fcvtx z0.s, p0/m, z0.d // CHECK-INST: fcvtx z0.s, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0x0a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a0 0a 65 fcvtx z30.s, p7/m, z31.d // CHECK-INST: fcvtx z30.s, p7/m, z31.d // CHECK-ENCODING: [0xfe,0xbf,0x0a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf 0a 65 @@ -30,23 +30,23 @@ fcvtx z30.s, p7/m, z31.d movprfx z5.d, p0/z, z7.d // CHECK-INST: movprfx z5.d, p0/z, z7.d // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 20 d0 04 fcvtx z5.s, p0/m, z0.d // CHECK-INST: fcvtx z5.s, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0x0a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 05 a0 0a 65 movprfx z5, z7 // CHECK-INST: movprfx z5, z7 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e5 bc 20 04 fcvtx z5.s, p0/m, z0.d // CHECK-INST: fcvtx z5.s, p0/m, z0.d // CHECK-ENCODING: [0x05,0xa0,0x0a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 05 a0 0a 65 diff --git a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s index 9c77c11757535..66317d2e6f58f 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s @@ -13,11 +13,11 @@ fcvtxnt z0.s, p0/m, z1.d // CHECK-INST: fcvtxnt z0.s, p0/m, z1.d // CHECK-ENCODING: [0x20,0xa0,0x0a,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 0a 64 fcvtxnt z30.s, p7/m, z31.d // CHECK-INST: fcvtxnt z30.s, p7/m, z31.d // CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf 0a 64 diff --git a/llvm/test/MC/AArch64/SVE2/flogb.s b/llvm/test/MC/AArch64/SVE2/flogb.s index 0da0f63112030..4e7e6a6668002 100644 --- a/llvm/test/MC/AArch64/SVE2/flogb.s +++ b/llvm/test/MC/AArch64/SVE2/flogb.s @@ -12,19 +12,19 @@ flogb z31.h, p7/m, z31.h // CHECK-INST: flogb z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x1a,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 1a 65 flogb z31.s, p7/m, z31.s // CHECK-INST: flogb z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x1c,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 1c 65 flogb z31.d, p7/m, z31.d // CHECK-INST: flogb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0x1e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 1e 65 @@ -34,23 +34,23 @@ flogb z31.d, p7/m, z31.d movprfx z4.d, p7/z, z6.d // CHECK-INST: movprfx z4.d, p7/z, z6.d // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c d0 04 flogb z4.d, p7/m, z31.d // CHECK-INST: flogb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 1e 65 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 flogb z4.d, p7/m, z31.d // CHECK-INST: flogb z4.d, p7/m, z31.d // CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 1e 65 diff --git a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s index e79fa1d782a88..a006ffbcb6bd4 100644 --- a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s +++ b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s @@ -12,19 +12,19 @@ fmaxnmp z0.h, p0/m, z0.h, z1.h // CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x54,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 54 64 fmaxnmp z29.s, p3/m, z29.s, z30.s // CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x8f,0x94,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 8f 94 64 fmaxnmp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d4 64 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ fmaxnmp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 fmaxnmp z31.d, p0/m, z31.d, z30.d // CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd4,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d4 64 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fmaxnmp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d4 64 diff --git a/llvm/test/MC/AArch64/SVE2/fmaxp.s b/llvm/test/MC/AArch64/SVE2/fmaxp.s index c3a2286a32184..0e507191445bc 100644 --- a/llvm/test/MC/AArch64/SVE2/fmaxp.s +++ b/llvm/test/MC/AArch64/SVE2/fmaxp.s @@ -12,19 +12,19 @@ fmaxp z0.h, p0/m, z0.h, z1.h // CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x56,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 56 64 fmaxp z29.s, p3/m, z29.s, z30.s // CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x8f,0x96,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 8f 96 64 fmaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d6 64 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ fmaxp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 fmaxp z31.d, p0/m, z31.d, z30.d // CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd6,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d6 64 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fmaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d6 64 diff --git a/llvm/test/MC/AArch64/SVE2/fminnmp.s b/llvm/test/MC/AArch64/SVE2/fminnmp.s index e4d2d12a7a15d..5a48e6dce466d 100644 --- a/llvm/test/MC/AArch64/SVE2/fminnmp.s +++ b/llvm/test/MC/AArch64/SVE2/fminnmp.s @@ -12,19 +12,19 @@ fminnmp z0.h, p0/m, z0.h, z1.h // CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x55,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 55 64 fminnmp z29.s, p3/m, z29.s, z30.s // CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x8f,0x95,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 8f 95 64 fminnmp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d5 64 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ fminnmp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 fminnmp z31.d, p0/m, z31.d, z30.d // CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd5,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d5 64 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fminnmp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d5 64 diff --git a/llvm/test/MC/AArch64/SVE2/fminp.s b/llvm/test/MC/AArch64/SVE2/fminp.s index 2d8712ded0377..a7e5b3a3af15e 100644 --- a/llvm/test/MC/AArch64/SVE2/fminp.s +++ b/llvm/test/MC/AArch64/SVE2/fminp.s @@ -12,19 +12,19 @@ fminp z0.h, p0/m, z0.h, z1.h // CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x57,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 57 64 fminp z29.s, p3/m, z29.s, z30.s // CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x8f,0x97,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 8f 97 64 fminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d7 64 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ fminp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 fminp z31.d, p0/m, z31.d, z30.d // CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d7 64 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 fminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d7 64 diff --git a/llvm/test/MC/AArch64/SVE2/fmlalb.s b/llvm/test/MC/AArch64/SVE2/fmlalb.s index e926ce0c8d487..02edbcf9e1b04 100644 --- a/llvm/test/MC/AArch64/SVE2/fmlalb.s +++ b/llvm/test/MC/AArch64/SVE2/fmlalb.s @@ -13,19 +13,19 @@ fmlalb z29.s, z30.h, z31.h // CHECK-INST: fmlalb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x83,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 83 bf 64 fmlalb z0.s, z1.h, z7.h[0] // CHECK-INST: fmlalb z0.s, z1.h, z7.h[0] // CHECK-ENCODING: [0x20,0x40,0xa7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 a7 64 fmlalb z30.s, z31.h, z7.h[7] // CHECK-INST: fmlalb z30.s, z31.h, z7.h[7] // CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe 4b bf 64 // --------------------------------------------------------------------------// @@ -34,23 +34,23 @@ fmlalb z30.s, z31.h, z7.h[7] movprfx z29, z28 // CHECK-INST: movprfx z29, z28 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 9d bf 20 04 fmlalb z29.s, z30.h, z31.h // CHECK-INST: fmlalb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x83,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 83 bf 64 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 fmlalb z21.s, z1.h, z7.h[7] // CHECK-INST: fmlalb z21.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x35,0x48,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 48 bf 64 diff --git a/llvm/test/MC/AArch64/SVE2/fmlalt.s b/llvm/test/MC/AArch64/SVE2/fmlalt.s index e13dcf13e8410..953b05a2042b7 100644 --- a/llvm/test/MC/AArch64/SVE2/fmlalt.s +++ b/llvm/test/MC/AArch64/SVE2/fmlalt.s @@ -13,19 +13,19 @@ fmlalt z29.s, z30.h, z31.h // CHECK-INST: fmlalt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x87,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 87 bf 64 fmlalt z0.s, z1.h, z7.h[0] // CHECK-INST: fmlalt z0.s, z1.h, z7.h[0] // CHECK-ENCODING: [0x20,0x44,0xa7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 44 a7 64 fmlalt z30.s, z31.h, z7.h[7] // CHECK-INST: fmlalt z30.s, z31.h, z7.h[7] // CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe 4f bf 64 // --------------------------------------------------------------------------// @@ -34,23 +34,23 @@ fmlalt z30.s, z31.h, z7.h[7] movprfx z29, z28 // CHECK-INST: movprfx z29, z28 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 9d bf 20 04 fmlalt z29.s, z30.h, z31.h // CHECK-INST: fmlalt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x87,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 87 bf 64 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 fmlalt z21.s, z1.h, z7.h[7] // CHECK-INST: fmlalt z21.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x35,0x4c,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 4c bf 64 diff --git a/llvm/test/MC/AArch64/SVE2/fmlslb.s b/llvm/test/MC/AArch64/SVE2/fmlslb.s index 38f8db0b81b9a..e6db85233d176 100644 --- a/llvm/test/MC/AArch64/SVE2/fmlslb.s +++ b/llvm/test/MC/AArch64/SVE2/fmlslb.s @@ -13,19 +13,19 @@ fmlslb z29.s, z30.h, z31.h // CHECK-INST: fmlslb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a3 bf 64 fmlslb z0.s, z1.h, z7.h[0] // CHECK-INST: fmlslb z0.s, z1.h, z7.h[0] // CHECK-ENCODING: [0x20,0x60,0xa7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 a7 64 fmlslb z30.s, z31.h, z7.h[7] // CHECK-INST: fmlslb z30.s, z31.h, z7.h[7] // CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe 6b bf 64 // --------------------------------------------------------------------------// @@ -34,23 +34,23 @@ fmlslb z30.s, z31.h, z7.h[7] movprfx z29, z28 // CHECK-INST: movprfx z29, z28 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 9d bf 20 04 fmlslb z29.s, z30.h, z31.h // CHECK-INST: fmlslb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a3 bf 64 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 fmlslb z21.s, z1.h, z7.h[7] // CHECK-INST: fmlslb z21.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x35,0x68,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 68 bf 64 diff --git a/llvm/test/MC/AArch64/SVE2/fmlslt.s b/llvm/test/MC/AArch64/SVE2/fmlslt.s index 3f994c3a80998..96b1901d138f7 100644 --- a/llvm/test/MC/AArch64/SVE2/fmlslt.s +++ b/llvm/test/MC/AArch64/SVE2/fmlslt.s @@ -13,19 +13,19 @@ fmlslt z29.s, z30.h, z31.h // CHECK-INST: fmlslt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a7 bf 64 fmlslt z0.s, z1.h, z7.h[0] // CHECK-INST: fmlslt z0.s, z1.h, z7.h[0] // CHECK-ENCODING: [0x20,0x64,0xa7,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 a7 64 fmlslt z30.s, z31.h, z7.h[7] // CHECK-INST: fmlslt z30.s, z31.h, z7.h[7] // CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe 6f bf 64 // --------------------------------------------------------------------------// @@ -34,23 +34,23 @@ fmlslt z30.s, z31.h, z7.h[7] movprfx z29, z28 // CHECK-INST: movprfx z29, z28 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 9d bf 20 04 fmlslt z29.s, z30.h, z31.h // CHECK-INST: fmlslt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a7 bf 64 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 fmlslt z21.s, z1.h, z7.h[7] // CHECK-INST: fmlslt z21.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x35,0x6c,0xbf,0x64] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 6c bf 64 diff --git a/llvm/test/MC/AArch64/SVE2/mla.s b/llvm/test/MC/AArch64/SVE2/mla.s index 3224f20cb4207..ff5df0b9f4ece 100644 --- a/llvm/test/MC/AArch64/SVE2/mla.s +++ b/llvm/test/MC/AArch64/SVE2/mla.s @@ -12,19 +12,19 @@ mla z0.h, z1.h, z7.h[7] // CHECK-INST: mla z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x08,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 7f 44 mla z0.s, z1.s, z7.s[3] // CHECK-INST: mla z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x08,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 bf 44 mla z0.d, z1.d, z7.d[1] // CHECK-INST: mla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x08,0xf7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 f7 44 @@ -34,11 +34,11 @@ mla z0.d, z1.d, z7.d[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mla z0.d, z1.d, z7.d[1] // CHECK-INST: mla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x08,0xf7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 f7 44 diff --git a/llvm/test/MC/AArch64/SVE2/mls.s b/llvm/test/MC/AArch64/SVE2/mls.s index 15bd01cdfb843..c4ef42da09d19 100644 --- a/llvm/test/MC/AArch64/SVE2/mls.s +++ b/llvm/test/MC/AArch64/SVE2/mls.s @@ -12,19 +12,19 @@ mls z0.h, z1.h, z7.h[7] // CHECK-INST: mls z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x0c,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c 7f 44 mls z0.s, z1.s, z7.s[3] // CHECK-INST: mls z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x0c,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c bf 44 mls z0.d, z1.d, z7.d[1] // CHECK-INST: mls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c f7 44 @@ -34,11 +34,11 @@ mls z0.d, z1.d, z7.d[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 mls z0.d, z1.d, z7.d[1] // CHECK-INST: mls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c f7 44 diff --git a/llvm/test/MC/AArch64/SVE2/mul.s b/llvm/test/MC/AArch64/SVE2/mul.s index ec9b0c9b9b1f3..120ece160176a 100644 --- a/llvm/test/MC/AArch64/SVE2/mul.s +++ b/llvm/test/MC/AArch64/SVE2/mul.s @@ -12,41 +12,41 @@ mul z0.b, z1.b, z2.b // CHECK-INST: mul z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x60,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 22 04 mul z0.h, z1.h, z2.h // CHECK-INST: mul z0.h, z1.h, z2.h // CHECK-ENCODING: [0x20,0x60,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 62 04 mul z29.s, z30.s, z31.s // CHECK-INST: mul z29.s, z30.s, z31.s // CHECK-ENCODING: [0xdd,0x63,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 63 bf 04 mul z31.d, z31.d, z31.d // CHECK-INST: mul z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x63,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 63 ff 04 mul z0.h, z1.h, z7.h[7] // CHECK-INST: mul z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xf8,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 7f 44 mul z0.s, z1.s, z7.s[3] // CHECK-INST: mul z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0xf8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 bf 44 mul z0.d, z1.d, z15.d[1] // CHECK-INST: mul z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0xf8,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/nbsl.s b/llvm/test/MC/AArch64/SVE2/nbsl.s index 937390ce35654..af6ad419f0239 100644 --- a/llvm/test/MC/AArch64/SVE2/nbsl.s +++ b/llvm/test/MC/AArch64/SVE2/nbsl.s @@ -12,7 +12,7 @@ nbsl z0.d, z0.d, z1.d, z2.d // CHECK-INST: nbsl z0.d, z0.d, z1.d, z2.d // CHECK-ENCODING: [0x40,0x3c,0xe1,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 40 3c e1 04 @@ -22,11 +22,11 @@ nbsl z0.d, z0.d, z1.d, z2.d movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 nbsl z31.d, z31.d, z30.d, z29.d // CHECK-INST: nbsl z31.d, z31.d, z30.d, z29.d // CHECK-ENCODING: [0xbf,0x3f,0xfe,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bf 3f fe 04 diff --git a/llvm/test/MC/AArch64/SVE2/pmul.s b/llvm/test/MC/AArch64/SVE2/pmul.s index 69d736ac44f86..20599a9902de8 100644 --- a/llvm/test/MC/AArch64/SVE2/pmul.s +++ b/llvm/test/MC/AArch64/SVE2/pmul.s @@ -12,11 +12,11 @@ pmul z0.b, z1.b, z2.b // CHECK-INST: pmul z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x64,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 22 04 pmul z29.b, z30.b, z31.b // CHECK-INST: pmul z29.b, z30.b, z31.b // CHECK-ENCODING: [0xdd,0x67,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 67 3f 04 diff --git a/llvm/test/MC/AArch64/SVE2/pmullb.s b/llvm/test/MC/AArch64/SVE2/pmullb.s index 846e6851f2fea..edd2a0907d37f 100644 --- a/llvm/test/MC/AArch64/SVE2/pmullb.s +++ b/llvm/test/MC/AArch64/SVE2/pmullb.s @@ -13,11 +13,11 @@ pmullb z0.h, z1.b, z2.b // CHECK-INST: pmullb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x68,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 42 45 pmullb z31.d, z31.s, z31.s // CHECK-INST: pmullb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x6b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 6b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/pmullt.s b/llvm/test/MC/AArch64/SVE2/pmullt.s index 0b3758f0ca1dc..4a2328edf4e1a 100644 --- a/llvm/test/MC/AArch64/SVE2/pmullt.s +++ b/llvm/test/MC/AArch64/SVE2/pmullt.s @@ -13,11 +13,11 @@ pmullt z0.h, z1.b, z2.b // CHECK-INST: pmullt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x6c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 42 45 pmullt z31.d, z31.s, z31.s // CHECK-INST: pmullt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x6f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 6f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/raddhnb.s b/llvm/test/MC/AArch64/SVE2/raddhnb.s index 871ba909d755f..8f7678593a686 100644 --- a/llvm/test/MC/AArch64/SVE2/raddhnb.s +++ b/llvm/test/MC/AArch64/SVE2/raddhnb.s @@ -13,17 +13,17 @@ raddhnb z0.b, z1.h, z31.h // CHECK-INST: raddhnb z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x68,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 7f 45 raddhnb z0.h, z1.s, z31.s // CHECK-INST: raddhnb z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x68,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 bf 45 raddhnb z0.s, z1.d, z31.d // CHECK-INST: raddhnb z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x68,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/raddhnt.s b/llvm/test/MC/AArch64/SVE2/raddhnt.s index d5648a6ff39c3..2c8d7fa2c9592 100644 --- a/llvm/test/MC/AArch64/SVE2/raddhnt.s +++ b/llvm/test/MC/AArch64/SVE2/raddhnt.s @@ -13,17 +13,17 @@ raddhnt z0.b, z1.h, z31.h // CHECK-INST: raddhnt z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x6c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 7f 45 raddhnt z0.h, z1.s, z31.s // CHECK-INST: raddhnt z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x6c,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c bf 45 raddhnt z0.s, z1.d, z31.d // CHECK-INST: raddhnt z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x6c,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/rshrnb.s b/llvm/test/MC/AArch64/SVE2/rshrnb.s index 203e6e7ece149..aa54e46d9b5f9 100644 --- a/llvm/test/MC/AArch64/SVE2/rshrnb.s +++ b/llvm/test/MC/AArch64/SVE2/rshrnb.s @@ -12,35 +12,35 @@ rshrnb z0.b, z0.h, #1 // CHECK-INST: rshrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x18,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 18 2f 45 rshrnb z31.b, z31.h, #8 // CHECK-INST: rshrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x1b,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1b 28 45 rshrnb z0.h, z0.s, #1 // CHECK-INST: rshrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x18,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 18 3f 45 rshrnb z31.h, z31.s, #16 // CHECK-INST: rshrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x1b,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1b 30 45 rshrnb z0.s, z0.d, #1 // CHECK-INST: rshrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x18,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 18 7f 45 rshrnb z31.s, z31.d, #32 // CHECK-INST: rshrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x1b,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1b 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/rshrnt.s b/llvm/test/MC/AArch64/SVE2/rshrnt.s index 5a52e6be22678..f5ad3df778e4d 100644 --- a/llvm/test/MC/AArch64/SVE2/rshrnt.s +++ b/llvm/test/MC/AArch64/SVE2/rshrnt.s @@ -12,35 +12,35 @@ rshrnt z0.b, z0.h, #1 // CHECK-INST: rshrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x1c,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 1c 2f 45 rshrnt z31.b, z31.h, #8 // CHECK-INST: rshrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x1f,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1f 28 45 rshrnt z0.h, z0.s, #1 // CHECK-INST: rshrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x1c,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 1c 3f 45 rshrnt z31.h, z31.s, #16 // CHECK-INST: rshrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x1f,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1f 30 45 rshrnt z0.s, z0.d, #1 // CHECK-INST: rshrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x1c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 1c 7f 45 rshrnt z31.s, z31.d, #32 // CHECK-INST: rshrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x1f,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1f 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/rsubhnb.s b/llvm/test/MC/AArch64/SVE2/rsubhnb.s index c9f4c3fdcdd0b..5804679c55fea 100644 --- a/llvm/test/MC/AArch64/SVE2/rsubhnb.s +++ b/llvm/test/MC/AArch64/SVE2/rsubhnb.s @@ -13,17 +13,17 @@ rsubhnb z0.b, z1.h, z31.h // CHECK-INST: rsubhnb z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x78,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 78 7f 45 rsubhnb z0.h, z1.s, z31.s // CHECK-INST: rsubhnb z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x78,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 78 bf 45 rsubhnb z0.s, z1.d, z31.d // CHECK-INST: rsubhnb z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x78,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 78 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/rsubhnt.s b/llvm/test/MC/AArch64/SVE2/rsubhnt.s index 7c1c546c3a38c..7aa7dcd15e92b 100644 --- a/llvm/test/MC/AArch64/SVE2/rsubhnt.s +++ b/llvm/test/MC/AArch64/SVE2/rsubhnt.s @@ -13,17 +13,17 @@ rsubhnt z0.b, z1.h, z31.h // CHECK-INST: rsubhnt z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x7c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 7c 7f 45 rsubhnt z0.h, z1.s, z31.s // CHECK-INST: rsubhnt z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x7c,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 7c bf 45 rsubhnt z0.s, z1.d, z31.d // CHECK-INST: rsubhnt z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 7c ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/saba.s b/llvm/test/MC/AArch64/SVE2/saba.s index b03087b0660f2..c07649fdcd25e 100644 --- a/llvm/test/MC/AArch64/SVE2/saba.s +++ b/llvm/test/MC/AArch64/SVE2/saba.s @@ -12,25 +12,25 @@ saba z0.b, z1.b, z31.b // CHECK-INST: saba z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0xf8,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 1f 45 saba z0.h, z1.h, z31.h // CHECK-INST: saba z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0xf8,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 5f 45 saba z0.s, z1.s, z31.s // CHECK-INST: saba z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xf8,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 9f 45 saba z0.d, z1.d, z31.d // CHECK-INST: saba z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xf8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 df 45 @@ -40,11 +40,11 @@ saba z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 saba z0.d, z1.d, z31.d // CHECK-INST: saba z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xf8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f8 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sabalb.s b/llvm/test/MC/AArch64/SVE2/sabalb.s index e8cf4cec3f610..18ccaa0626c1d 100644 --- a/llvm/test/MC/AArch64/SVE2/sabalb.s +++ b/llvm/test/MC/AArch64/SVE2/sabalb.s @@ -13,19 +13,19 @@ sabalb z0.h, z1.b, z31.b // CHECK-INST: sabalb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0xc0,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c0 5f 45 sabalb z0.s, z1.h, z31.h // CHECK-INST: sabalb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0xc0,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c0 9f 45 sabalb z0.d, z1.s, z31.s // CHECK-INST: sabalb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0xc0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c0 df 45 @@ -35,11 +35,11 @@ sabalb z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sabalb z21.d, z1.s, z31.s // CHECK-INST: sabalb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0xc0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 c0 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sabalt.s b/llvm/test/MC/AArch64/SVE2/sabalt.s index 042b66a4311f6..59597f67d7031 100644 --- a/llvm/test/MC/AArch64/SVE2/sabalt.s +++ b/llvm/test/MC/AArch64/SVE2/sabalt.s @@ -13,19 +13,19 @@ sabalt z0.h, z1.b, z31.b // CHECK-INST: sabalt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0xc4,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c4 5f 45 sabalt z0.s, z1.h, z31.h // CHECK-INST: sabalt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0xc4,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c4 9f 45 sabalt z0.d, z1.s, z31.s // CHECK-INST: sabalt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0xc4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c4 df 45 @@ -35,11 +35,11 @@ sabalt z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sabalt z21.d, z1.s, z31.s // CHECK-INST: sabalt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0xc4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 c4 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sabdlb.s b/llvm/test/MC/AArch64/SVE2/sabdlb.s index 5750e11017bba..e651430aed364 100644 --- a/llvm/test/MC/AArch64/SVE2/sabdlb.s +++ b/llvm/test/MC/AArch64/SVE2/sabdlb.s @@ -13,17 +13,17 @@ sabdlb z0.h, z1.b, z2.b // CHECK-INST: sabdlb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x30,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 30 42 45 sabdlb z29.s, z30.h, z31.h // CHECK-INST: sabdlb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x33,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 33 9f 45 sabdlb z31.d, z31.s, z31.s // CHECK-INST: sabdlb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x33,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 33 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sabdlt.s b/llvm/test/MC/AArch64/SVE2/sabdlt.s index e802a4692b16d..6682d1b6fb3f8 100644 --- a/llvm/test/MC/AArch64/SVE2/sabdlt.s +++ b/llvm/test/MC/AArch64/SVE2/sabdlt.s @@ -13,17 +13,17 @@ sabdlt z0.h, z1.b, z2.b // CHECK-INST: sabdlt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x34,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 34 42 45 sabdlt z29.s, z30.h, z31.h // CHECK-INST: sabdlt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x37,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 37 9f 45 sabdlt z31.d, z31.s, z31.s // CHECK-INST: sabdlt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x37,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 37 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sadalp.s b/llvm/test/MC/AArch64/SVE2/sadalp.s index cd6e7325cd8f4..a7e4f6a6ae8fe 100644 --- a/llvm/test/MC/AArch64/SVE2/sadalp.s +++ b/llvm/test/MC/AArch64/SVE2/sadalp.s @@ -12,19 +12,19 @@ sadalp z0.h, p0/m, z1.b // CHECK-INST: sadalp z0.h, p0/m, z1.b // CHECK-ENCODING: [0x20,0xa0,0x44,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 44 44 sadalp z29.s, p0/m, z30.h // CHECK-INST: sadalp z29.s, p0/m, z30.h // CHECK-ENCODING: [0xdd,0xa3,0x84,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a3 84 44 sadalp z30.d, p7/m, z31.s // CHECK-INST: sadalp z30.d, p7/m, z31.s // CHECK-ENCODING: [0xfe,0xbf,0xc4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf c4 44 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ sadalp z30.d, p7/m, z31.s movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sadalp z31.d, p0/m, z30.s // CHECK-INST: sadalp z31.d, p0/m, z30.s // CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 c4 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sadalp z31.d, p0/m, z30.s // CHECK-INST: sadalp z31.d, p0/m, z30.s // CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 c4 44 diff --git a/llvm/test/MC/AArch64/SVE2/saddlb.s b/llvm/test/MC/AArch64/SVE2/saddlb.s index e21be54cee0b3..b425afe8bf0ce 100644 --- a/llvm/test/MC/AArch64/SVE2/saddlb.s +++ b/llvm/test/MC/AArch64/SVE2/saddlb.s @@ -13,17 +13,17 @@ saddlb z0.h, z1.b, z2.b // CHECK-INST: saddlb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x00,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 00 42 45 saddlb z29.s, z30.h, z31.h // CHECK-INST: saddlb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x03,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 03 9f 45 saddlb z31.d, z31.s, z31.s // CHECK-INST: saddlb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x03,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 03 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/saddlbt.s b/llvm/test/MC/AArch64/SVE2/saddlbt.s index 5734fb9ed189d..1f285f70567ee 100644 --- a/llvm/test/MC/AArch64/SVE2/saddlbt.s +++ b/llvm/test/MC/AArch64/SVE2/saddlbt.s @@ -13,17 +13,17 @@ saddlbt z0.h, z1.b, z31.b // CHECK-INST: saddlbt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x80,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5f 45 saddlbt z0.s, z1.h, z31.h // CHECK-INST: saddlbt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x80,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 9f 45 saddlbt z0.d, z1.s, z31.s // CHECK-INST: saddlbt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x80,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/saddlt.s b/llvm/test/MC/AArch64/SVE2/saddlt.s index fc4981b640d39..ec481e873a0bd 100644 --- a/llvm/test/MC/AArch64/SVE2/saddlt.s +++ b/llvm/test/MC/AArch64/SVE2/saddlt.s @@ -13,17 +13,17 @@ saddlt z0.h, z1.b, z2.b // CHECK-INST: saddlt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x04,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 04 42 45 saddlt z29.s, z30.h, z31.h // CHECK-INST: saddlt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x07,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 07 9f 45 saddlt z31.d, z31.s, z31.s // CHECK-INST: saddlt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x07,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 07 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/saddwb.s b/llvm/test/MC/AArch64/SVE2/saddwb.s index 8484c93d0e687..a8a7f643af312 100644 --- a/llvm/test/MC/AArch64/SVE2/saddwb.s +++ b/llvm/test/MC/AArch64/SVE2/saddwb.s @@ -13,17 +13,17 @@ saddwb z0.h, z1.h, z2.b // CHECK-INST: saddwb z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x40,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 42 45 saddwb z29.s, z30.s, z31.h // CHECK-INST: saddwb z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x43,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 43 9f 45 saddwb z31.d, z31.d, z31.s // CHECK-INST: saddwb z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x43,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 43 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/saddwt.s b/llvm/test/MC/AArch64/SVE2/saddwt.s index 393aa006945aa..f1eeacc36e2ad 100644 --- a/llvm/test/MC/AArch64/SVE2/saddwt.s +++ b/llvm/test/MC/AArch64/SVE2/saddwt.s @@ -13,17 +13,17 @@ saddwt z0.h, z1.h, z2.b // CHECK-INST: saddwt z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x44,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 44 42 45 saddwt z29.s, z30.s, z31.h // CHECK-INST: saddwt z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x47,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 47 9f 45 saddwt z31.d, z31.d, z31.s // CHECK-INST: saddwt z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x47,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 47 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sbclb.s b/llvm/test/MC/AArch64/SVE2/sbclb.s index 1cc3729f4d4ad..36c9f61b7d086 100644 --- a/llvm/test/MC/AArch64/SVE2/sbclb.s +++ b/llvm/test/MC/AArch64/SVE2/sbclb.s @@ -12,13 +12,13 @@ sbclb z0.s, z1.s, z31.s // CHECK-INST: sbclb z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xd0,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 9f 45 sbclb z0.d, z1.d, z31.d // CHECK-INST: sbclb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 df 45 @@ -28,11 +28,11 @@ sbclb z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sbclb z0.d, z1.d, z31.d // CHECK-INST: sbclb z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d0 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sbclt.s b/llvm/test/MC/AArch64/SVE2/sbclt.s index 7acc604f699aa..056a6a94e7d12 100644 --- a/llvm/test/MC/AArch64/SVE2/sbclt.s +++ b/llvm/test/MC/AArch64/SVE2/sbclt.s @@ -12,13 +12,13 @@ sbclt z0.s, z1.s, z31.s // CHECK-INST: sbclt z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xd4,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 9f 45 sbclt z0.d, z1.d, z31.d // CHECK-INST: sbclt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 df 45 @@ -28,11 +28,11 @@ sbclt z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sbclt z0.d, z1.d, z31.d // CHECK-INST: sbclt z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xd4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d4 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/shadd.s b/llvm/test/MC/AArch64/SVE2/shadd.s index edbd9275302e0..d54cbe6ebc70e 100644 --- a/llvm/test/MC/AArch64/SVE2/shadd.s +++ b/llvm/test/MC/AArch64/SVE2/shadd.s @@ -12,25 +12,25 @@ shadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x10,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 10 44 shadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x50,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 50 44 shadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x90,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 90 44 shadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d0 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ shadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 shadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd0,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d0 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 shadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d0 44 diff --git a/llvm/test/MC/AArch64/SVE2/shrnb.s b/llvm/test/MC/AArch64/SVE2/shrnb.s index 87057bd76df8f..61386522d63af 100644 --- a/llvm/test/MC/AArch64/SVE2/shrnb.s +++ b/llvm/test/MC/AArch64/SVE2/shrnb.s @@ -12,35 +12,35 @@ shrnb z0.b, z0.h, #1 // CHECK-INST: shrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x10,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 10 2f 45 shrnb z31.b, z31.h, #8 // CHECK-INST: shrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x13,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 13 28 45 shrnb z0.h, z0.s, #1 // CHECK-INST: shrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x10,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 10 3f 45 shrnb z31.h, z31.s, #16 // CHECK-INST: shrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x13,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 13 30 45 shrnb z0.s, z0.d, #1 // CHECK-INST: shrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x10,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 10 7f 45 shrnb z31.s, z31.d, #32 // CHECK-INST: shrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x13,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 13 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/shrnt.s b/llvm/test/MC/AArch64/SVE2/shrnt.s index e5b5331e5276b..070646d51a69c 100644 --- a/llvm/test/MC/AArch64/SVE2/shrnt.s +++ b/llvm/test/MC/AArch64/SVE2/shrnt.s @@ -12,35 +12,35 @@ shrnt z0.b, z0.h, #1 // CHECK-INST: shrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x14,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 14 2f 45 shrnt z31.b, z31.h, #8 // CHECK-INST: shrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x17,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 17 28 45 shrnt z0.h, z0.s, #1 // CHECK-INST: shrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x14,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 14 3f 45 shrnt z31.h, z31.s, #16 // CHECK-INST: shrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x17,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 17 30 45 shrnt z0.s, z0.d, #1 // CHECK-INST: shrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x14,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 14 7f 45 shrnt z31.s, z31.d, #32 // CHECK-INST: shrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x17,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 17 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/shsub.s b/llvm/test/MC/AArch64/SVE2/shsub.s index ed6b7e927a41b..1b9f8740e7856 100644 --- a/llvm/test/MC/AArch64/SVE2/shsub.s +++ b/llvm/test/MC/AArch64/SVE2/shsub.s @@ -12,25 +12,25 @@ shsub z0.b, p0/m, z0.b, z1.b // CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x12,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 12 44 shsub z0.h, p0/m, z0.h, z1.h // CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x52,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 52 44 shsub z29.s, p7/m, z29.s, z30.s // CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x92,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 92 44 shsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d2 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ shsub z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 shsub z31.d, p0/m, z31.d, z30.d // CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d2 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 shsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d2 44 diff --git a/llvm/test/MC/AArch64/SVE2/shsubr.s b/llvm/test/MC/AArch64/SVE2/shsubr.s index 3d4b5b612133f..61251738686c0 100644 --- a/llvm/test/MC/AArch64/SVE2/shsubr.s +++ b/llvm/test/MC/AArch64/SVE2/shsubr.s @@ -12,25 +12,25 @@ shsubr z0.b, p0/m, z0.b, z1.b // CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x16,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 16 44 shsubr z0.h, p0/m, z0.h, z1.h // CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x56,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 56 44 shsubr z29.s, p7/m, z29.s, z30.s // CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x96,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 96 44 shsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d6 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ shsubr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 shsubr z31.d, p0/m, z31.d, z30.d // CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d6 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 shsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d6 44 diff --git a/llvm/test/MC/AArch64/SVE2/sli.s b/llvm/test/MC/AArch64/SVE2/sli.s index 7a90116d8f992..a835eadfd6516 100644 --- a/llvm/test/MC/AArch64/SVE2/sli.s +++ b/llvm/test/MC/AArch64/SVE2/sli.s @@ -12,47 +12,47 @@ sli z0.b, z0.b, #0 // CHECK-INST: sli z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0xf4,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f4 08 45 sli z31.b, z31.b, #7 // CHECK-INST: sli z31.b, z31.b, #7 // CHECK-ENCODING: [0xff,0xf7,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f7 0f 45 sli z0.h, z0.h, #0 // CHECK-INST: sli z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0xf4,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f4 10 45 sli z31.h, z31.h, #15 // CHECK-INST: sli z31.h, z31.h, #15 // CHECK-ENCODING: [0xff,0xf7,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f7 1f 45 sli z0.s, z0.s, #0 // CHECK-INST: sli z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0xf4,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f4 40 45 sli z31.s, z31.s, #31 // CHECK-INST: sli z31.s, z31.s, #31 // CHECK-ENCODING: [0xff,0xf7,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f7 5f 45 sli z0.d, z0.d, #0 // CHECK-INST: sli z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0xf4,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f4 80 45 sli z31.d, z31.d, #63 // CHECK-INST: sli z31.d, z31.d, #63 // CHECK-ENCODING: [0xff,0xf7,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f7 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/smaxp.s b/llvm/test/MC/AArch64/SVE2/smaxp.s index 80f7e2bd91a40..a28af2e33c6a6 100644 --- a/llvm/test/MC/AArch64/SVE2/smaxp.s +++ b/llvm/test/MC/AArch64/SVE2/smaxp.s @@ -12,25 +12,25 @@ smaxp z0.b, p0/m, z0.b, z1.b // CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0xa0,0x14,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 14 44 smaxp z0.h, p0/m, z0.h, z1.h // CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0xa0,0x54,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 54 44 smaxp z29.s, p7/m, z29.s, z30.s // CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0xbf,0x94,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd bf 94 44 smaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d4 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ smaxp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 smaxp z31.d, p0/m, z31.d, z30.d // CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 d4 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 smaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d4 44 diff --git a/llvm/test/MC/AArch64/SVE2/sminp.s b/llvm/test/MC/AArch64/SVE2/sminp.s index ba837b94c2f5b..60f9eebe751b2 100644 --- a/llvm/test/MC/AArch64/SVE2/sminp.s +++ b/llvm/test/MC/AArch64/SVE2/sminp.s @@ -12,25 +12,25 @@ sminp z0.b, p0/m, z0.b, z1.b // CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0xa0,0x16,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 16 44 sminp z0.h, p0/m, z0.h, z1.h // CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0xa0,0x56,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 56 44 sminp z29.s, p7/m, z29.s, z30.s // CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0xbf,0x96,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd bf 96 44 sminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d6 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sminp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sminp z31.d, p0/m, z31.d, z30.d // CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 d6 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d6 44 diff --git a/llvm/test/MC/AArch64/SVE2/smlalb.s b/llvm/test/MC/AArch64/SVE2/smlalb.s index 142f104849609..d0d173185f48f 100644 --- a/llvm/test/MC/AArch64/SVE2/smlalb.s +++ b/llvm/test/MC/AArch64/SVE2/smlalb.s @@ -13,31 +13,31 @@ smlalb z0.h, z1.b, z31.b // CHECK-INST: smlalb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x40,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 5f 44 smlalb z0.s, z1.h, z31.h // CHECK-INST: smlalb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x40,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 9f 44 smlalb z0.d, z1.s, z31.s // CHECK-INST: smlalb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x40,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 40 df 44 smlalb z0.s, z1.h, z7.h[7] // CHECK-INST: smlalb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x88,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 88 bf 44 smlalb z0.d, z1.s, z15.s[1] // CHECK-INST: smlalb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0x88,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 88 ef 44 @@ -47,23 +47,23 @@ smlalb z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlalb z21.d, z1.s, z31.s // CHECK-INST: smlalb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x40,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 40 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlalb z21.d, z10.s, z5.s[1] // CHECK-INST: smlalb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x89,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 89 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/smlalt.s b/llvm/test/MC/AArch64/SVE2/smlalt.s index 767c357d61aac..6358271bcf342 100644 --- a/llvm/test/MC/AArch64/SVE2/smlalt.s +++ b/llvm/test/MC/AArch64/SVE2/smlalt.s @@ -13,31 +13,31 @@ smlalt z0.h, z1.b, z31.b // CHECK-INST: smlalt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x44,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 44 5f 44 smlalt z0.s, z1.h, z31.h // CHECK-INST: smlalt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x44,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 44 9f 44 smlalt z0.d, z1.s, z31.s // CHECK-INST: smlalt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x44,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 44 df 44 smlalt z0.s, z1.h, z7.h[7] // CHECK-INST: smlalt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x8c,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 8c bf 44 smlalt z0.d, z1.s, z15.s[1] // CHECK-INST: smlalt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0x8c,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 8c ef 44 @@ -47,23 +47,23 @@ smlalt z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlalt z21.d, z1.s, z31.s // CHECK-INST: smlalt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x44,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 44 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlalt z21.d, z10.s, z5.s[1] // CHECK-INST: smlalt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x8d,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 8d e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/smlslb.s b/llvm/test/MC/AArch64/SVE2/smlslb.s index befd21b879c55..b73fe155bd67c 100644 --- a/llvm/test/MC/AArch64/SVE2/smlslb.s +++ b/llvm/test/MC/AArch64/SVE2/smlslb.s @@ -13,31 +13,31 @@ smlslb z0.h, z1.b, z31.b // CHECK-INST: smlslb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x50,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 50 5f 44 smlslb z0.s, z1.h, z31.h // CHECK-INST: smlslb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x50,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 50 9f 44 smlslb z0.d, z1.s, z31.s // CHECK-INST: smlslb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x50,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 50 df 44 smlslb z0.s, z1.h, z7.h[7] // CHECK-INST: smlslb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xa8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a8 bf 44 smlslb z0.d, z1.s, z15.s[1] // CHECK-INST: smlslb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xa8,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a8 ef 44 @@ -47,23 +47,23 @@ smlslb z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlslb z21.d, z1.s, z31.s // CHECK-INST: smlslb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x50,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 50 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlslb z21.d, z10.s, z5.s[1] // CHECK-INST: smlslb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0xa9,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 a9 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/smlslt.s b/llvm/test/MC/AArch64/SVE2/smlslt.s index e66b1b574fbb3..689708d99ebd3 100644 --- a/llvm/test/MC/AArch64/SVE2/smlslt.s +++ b/llvm/test/MC/AArch64/SVE2/smlslt.s @@ -13,31 +13,31 @@ smlslt z0.h, z1.b, z31.b // CHECK-INST: smlslt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x54,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 54 5f 44 smlslt z0.s, z1.h, z31.h // CHECK-INST: smlslt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x54,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 54 9f 44 smlslt z0.d, z1.s, z31.s // CHECK-INST: smlslt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x54,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 54 df 44 smlslt z0.s, z1.h, z7.h[7] // CHECK-INST: smlslt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xac,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 ac bf 44 smlslt z0.d, z1.s, z15.s[1] // CHECK-INST: smlslt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xac,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 ac ef 44 @@ -47,23 +47,23 @@ smlslt z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlslt z21.d, z1.s, z31.s // CHECK-INST: smlslt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x54,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 54 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 smlslt z21.d, z10.s, z5.s[1] // CHECK-INST: smlslt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0xad,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 ad e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/smulh.s b/llvm/test/MC/AArch64/SVE2/smulh.s index 2b08ba73f1b13..dcb3696234438 100644 --- a/llvm/test/MC/AArch64/SVE2/smulh.s +++ b/llvm/test/MC/AArch64/SVE2/smulh.s @@ -12,23 +12,23 @@ smulh z0.b, z1.b, z2.b // CHECK-INST: smulh z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x68,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 22 04 smulh z0.h, z1.h, z2.h // CHECK-INST: smulh z0.h, z1.h, z2.h // CHECK-ENCODING: [0x20,0x68,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 62 04 smulh z29.s, z30.s, z31.s // CHECK-INST: smulh z29.s, z30.s, z31.s // CHECK-ENCODING: [0xdd,0x6b,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 6b bf 04 smulh z31.d, z31.d, z31.d // CHECK-INST: smulh z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x6b,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 6b ff 04 diff --git a/llvm/test/MC/AArch64/SVE2/smullb.s b/llvm/test/MC/AArch64/SVE2/smullb.s index f134660350c0b..78299c9e156ca 100644 --- a/llvm/test/MC/AArch64/SVE2/smullb.s +++ b/llvm/test/MC/AArch64/SVE2/smullb.s @@ -13,29 +13,29 @@ smullb z0.h, z1.b, z2.b // CHECK-INST: smullb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x70,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 42 45 smullb z29.s, z30.h, z31.h // CHECK-INST: smullb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x73,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 73 9f 45 smullb z31.d, z31.s, z31.s // CHECK-INST: smullb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x73,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 73 df 45 smullb z0.s, z1.h, z7.h[7] // CHECK-INST: smullb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xc8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c8 bf 44 smullb z0.d, z1.s, z15.s[1] // CHECK-INST: smullb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xc8,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c8 ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/smullt.s b/llvm/test/MC/AArch64/SVE2/smullt.s index 8e03697a40269..f25a510d978f7 100644 --- a/llvm/test/MC/AArch64/SVE2/smullt.s +++ b/llvm/test/MC/AArch64/SVE2/smullt.s @@ -13,29 +13,29 @@ smullt z0.h, z1.b, z2.b // CHECK-INST: smullt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x74,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 42 45 smullt z29.s, z30.h, z31.h // CHECK-INST: smullt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x77,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 77 9f 45 smullt z31.d, z31.s, z31.s // CHECK-INST: smullt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x77,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 77 df 45 smullt z0.s, z1.h, z7.h[7] // CHECK-INST: smullt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xcc,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 cc bf 44 smullt z0.d, z1.s, z15.s[1] // CHECK-INST: smullt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xcc,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 cc ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/splice.s b/llvm/test/MC/AArch64/SVE2/splice.s index 3ce958276f871..d23071ad600e1 100644 --- a/llvm/test/MC/AArch64/SVE2/splice.s +++ b/llvm/test/MC/AArch64/SVE2/splice.s @@ -12,23 +12,23 @@ splice z29.b, p7, { z30.b, z31.b } // CHECK-INST: splice z29.b, p7, { z30.b, z31.b } // CHECK-ENCODING: [0xdd,0x9f,0x2d,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 2d 05 splice z29.h, p7, { z30.h, z31.h } // CHECK-INST: splice z29.h, p7, { z30.h, z31.h } // CHECK-ENCODING: [0xdd,0x9f,0x6d,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 6d 05 splice z29.s, p7, { z30.s, z31.s } // CHECK-INST: splice z29.s, p7, { z30.s, z31.s } // CHECK-ENCODING: [0xdd,0x9f,0xad,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f ad 05 splice z29.d, p7, { z30.d, z31.d } // CHECK-INST: splice z29.d, p7, { z30.d, z31.d } // CHECK-ENCODING: [0xdd,0x9f,0xed,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f ed 05 diff --git a/llvm/test/MC/AArch64/SVE2/sqabs.s b/llvm/test/MC/AArch64/SVE2/sqabs.s index d3a004407bfa3..437819b79031c 100644 --- a/llvm/test/MC/AArch64/SVE2/sqabs.s +++ b/llvm/test/MC/AArch64/SVE2/sqabs.s @@ -12,25 +12,25 @@ sqabs z31.b, p7/m, z31.b // CHECK-INST: sqabs z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x08,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 08 44 sqabs z31.h, p7/m, z31.h // CHECK-INST: sqabs z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x48,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 48 44 sqabs z31.s, p7/m, z31.s // CHECK-INST: sqabs z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x88,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 88 44 sqabs z31.d, p7/m, z31.d // CHECK-INST: sqabs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf c8 44 @@ -40,23 +40,23 @@ sqabs z31.d, p7/m, z31.d movprfx z4.s, p7/z, z6.s // CHECK-INST: movprfx z4.s, p7/z, z6.s // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 90 04 sqabs z4.s, p7/m, z31.s // CHECK-INST: sqabs z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x88,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 88 44 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sqabs z4.s, p7/m, z31.s // CHECK-INST: sqabs z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x88,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 88 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqadd.s b/llvm/test/MC/AArch64/SVE2/sqadd.s index 32db82948ad6e..8e76ec6c78b5e 100644 --- a/llvm/test/MC/AArch64/SVE2/sqadd.s +++ b/llvm/test/MC/AArch64/SVE2/sqadd.s @@ -12,25 +12,25 @@ sqadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x18,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 18 44 sqadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x58,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 58 44 sqadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x98,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 98 44 sqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d8 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d8 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d8 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqcadd.s b/llvm/test/MC/AArch64/SVE2/sqcadd.s index ee1e3b4c77d8f..0349ddda6b124 100644 --- a/llvm/test/MC/AArch64/SVE2/sqcadd.s +++ b/llvm/test/MC/AArch64/SVE2/sqcadd.s @@ -12,49 +12,49 @@ sqcadd z0.b, z0.b, z0.b, #90 // CHECK-INST: sqcadd z0.b, z0.b, z0.b, #90 // CHECK-ENCODING: [0x00,0xd8,0x01,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 01 45 sqcadd z0.h, z0.h, z0.h, #90 // CHECK-INST: sqcadd z0.h, z0.h, z0.h, #90 // CHECK-ENCODING: [0x00,0xd8,0x41,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 41 45 sqcadd z0.s, z0.s, z0.s, #90 // CHECK-INST: sqcadd z0.s, z0.s, z0.s, #90 // CHECK-ENCODING: [0x00,0xd8,0x81,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 81 45 sqcadd z0.d, z0.d, z0.d, #90 // CHECK-INST: sqcadd z0.d, z0.d, z0.d, #90 // CHECK-ENCODING: [0x00,0xd8,0xc1,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 d8 c1 45 sqcadd z31.b, z31.b, z31.b, #270 // CHECK-INST: sqcadd z31.b, z31.b, z31.b, #270 // CHECK-ENCODING: [0xff,0xdf,0x01,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 01 45 sqcadd z31.h, z31.h, z31.h, #270 // CHECK-INST: sqcadd z31.h, z31.h, z31.h, #270 // CHECK-ENCODING: [0xff,0xdf,0x41,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 41 45 sqcadd z31.s, z31.s, z31.s, #270 // CHECK-INST: sqcadd z31.s, z31.s, z31.s, #270 // CHECK-ENCODING: [0xff,0xdf,0x81,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df 81 45 sqcadd z31.d, z31.d, z31.d, #270 // CHECK-INST: sqcadd z31.d, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0xdf,0xc1,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff df c1 45 @@ -64,11 +64,11 @@ sqcadd z31.d, z31.d, z31.d, #270 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sqcadd z4.d, z4.d, z31.d, #270 // CHECK-INST: sqcadd z4.d, z4.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0xdf,0xc1,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 df c1 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s index b0523ee29dfe6..7d05dcaf4cf00 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s @@ -13,31 +13,31 @@ sqdmlalb z0.h, z1.b, z31.b // CHECK-INST: sqdmlalb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x60,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 5f 44 sqdmlalb z0.s, z1.h, z31.h // CHECK-INST: sqdmlalb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x60,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 9f 44 sqdmlalb z0.d, z1.s, z31.s // CHECK-INST: sqdmlalb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x60,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 df 44 sqdmlalb z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmlalb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x28,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 28 bf 44 sqdmlalb z0.d, z1.s, z15.s[3] // CHECK-INST: sqdmlalb z0.d, z1.s, z15.s[3] // CHECK-ENCODING: [0x20,0x28,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 28 ff 44 @@ -47,23 +47,23 @@ sqdmlalb z0.d, z1.s, z15.s[3] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlalb z21.d, z1.s, z31.s // CHECK-INST: sqdmlalb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x60,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 60 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlalb z21.d, z10.s, z5.s[1] // CHECK-INST: sqdmlalb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x29,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 29 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s index d25dfc8b9e838..1fabef483cb1d 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s @@ -13,19 +13,19 @@ sqdmlalbt z0.h, z1.b, z31.b // CHECK-INST: sqdmlalbt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x08,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 5f 44 sqdmlalbt z0.s, z1.h, z31.h // CHECK-INST: sqdmlalbt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x08,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 9f 44 sqdmlalbt z0.d, z1.s, z31.s // CHECK-INST: sqdmlalbt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x08,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 df 44 // --------------------------------------------------------------------------// @@ -34,11 +34,11 @@ sqdmlalbt z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlalbt z21.d, z1.s, z31.s // CHECK-INST: sqdmlalbt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x08,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 08 df 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s index 552361b659e23..c88da9931a744 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s @@ -13,31 +13,31 @@ sqdmlalt z0.h, z1.b, z31.b // CHECK-INST: sqdmlalt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x64,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 5f 44 sqdmlalt z0.s, z1.h, z31.h // CHECK-INST: sqdmlalt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x64,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 9f 44 sqdmlalt z0.d, z1.s, z31.s // CHECK-INST: sqdmlalt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x64,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 df 44 sqdmlalt z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmlalt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x2c,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 2c bf 44 sqdmlalt z0.d, z1.s, z15.s[3] // CHECK-INST: sqdmlalt z0.d, z1.s, z15.s[3] // CHECK-ENCODING: [0x20,0x2c,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 2c ff 44 @@ -47,23 +47,23 @@ sqdmlalt z0.d, z1.s, z15.s[3] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlalt z21.d, z1.s, z31.s // CHECK-INST: sqdmlalt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x64,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 64 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlalt z21.d, z10.s, z5.s[1] // CHECK-INST: sqdmlalt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x2d,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 2d e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s index eabc8ac1a41fc..69937c8ef2444 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s @@ -13,31 +13,31 @@ sqdmlslb z0.h, z1.b, z31.b // CHECK-INST: sqdmlslb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x68,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 5f 44 sqdmlslb z0.s, z1.h, z31.h // CHECK-INST: sqdmlslb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x68,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 9f 44 sqdmlslb z0.d, z1.s, z31.s // CHECK-INST: sqdmlslb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x68,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 68 df 44 sqdmlslb z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmlslb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x38,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 38 bf 44 sqdmlslb z0.d, z1.s, z15.s[3] // CHECK-INST: sqdmlslb z0.d, z1.s, z15.s[3] // CHECK-ENCODING: [0x20,0x38,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 38 ff 44 @@ -47,23 +47,23 @@ sqdmlslb z0.d, z1.s, z15.s[3] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlslb z21.d, z1.s, z31.s // CHECK-INST: sqdmlslb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x68,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 68 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlslb z21.d, z10.s, z5.s[1] // CHECK-INST: sqdmlslb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x39,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 39 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s index 1203375b958e6..a166523ae67fa 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s @@ -13,19 +13,19 @@ sqdmlslbt z0.h, z1.b, z31.b // CHECK-INST: sqdmlslbt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x0c,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c 5f 44 sqdmlslbt z0.s, z1.h, z31.h // CHECK-INST: sqdmlslbt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x0c,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c 9f 44 sqdmlslbt z0.d, z1.s, z31.s // CHECK-INST: sqdmlslbt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x0c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c df 44 // --------------------------------------------------------------------------// @@ -34,11 +34,11 @@ sqdmlslbt z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlslbt z21.d, z1.s, z31.s // CHECK-INST: sqdmlslbt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x0c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 0c df 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s index c4e4fc1f6a00b..1eb7d15dd5c98 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s @@ -13,31 +13,31 @@ sqdmlslt z0.h, z1.b, z31.b // CHECK-INST: sqdmlslt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x6c,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 5f 44 sqdmlslt z0.s, z1.h, z31.h // CHECK-INST: sqdmlslt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x6c,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 9f 44 sqdmlslt z0.d, z1.s, z31.s // CHECK-INST: sqdmlslt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x6c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c df 44 sqdmlslt z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmlslt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x3c,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 3c bf 44 sqdmlslt z0.d, z1.s, z15.s[3] // CHECK-INST: sqdmlslt z0.d, z1.s, z15.s[3] // CHECK-ENCODING: [0x20,0x3c,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 3c ff 44 @@ -47,23 +47,23 @@ sqdmlslt z0.d, z1.s, z15.s[3] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlslt z21.d, z1.s, z31.s // CHECK-INST: sqdmlslt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x6c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 6c df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqdmlslt z21.d, z10.s, z5.s[1] // CHECK-INST: sqdmlslt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x3d,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 3d e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmulh.s b/llvm/test/MC/AArch64/SVE2/sqdmulh.s index a1115cff6b80a..e833f4c3bcfd9 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmulh.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmulh.s @@ -12,41 +12,41 @@ sqdmulh z0.b, z1.b, z2.b // CHECK-INST: sqdmulh z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x70,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 22 04 sqdmulh z0.h, z1.h, z2.h // CHECK-INST: sqdmulh z0.h, z1.h, z2.h // CHECK-ENCODING: [0x20,0x70,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 62 04 sqdmulh z29.s, z30.s, z31.s // CHECK-INST: sqdmulh z29.s, z30.s, z31.s // CHECK-ENCODING: [0xdd,0x73,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 73 bf 04 sqdmulh z31.d, z31.d, z31.d // CHECK-INST: sqdmulh z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x73,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 73 ff 04 sqdmulh z0.h, z1.h, z7.h[7] // CHECK-INST: sqdmulh z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xf0,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f0 7f 44 sqdmulh z0.s, z1.s, z7.s[3] // CHECK-INST: sqdmulh z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0xf0,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f0 bf 44 sqdmulh z0.d, z1.d, z15.d[1] // CHECK-INST: sqdmulh z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0xf0,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f0 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmullb.s b/llvm/test/MC/AArch64/SVE2/sqdmullb.s index 33525f793b635..6b06b2515186b 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmullb.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmullb.s @@ -13,29 +13,29 @@ sqdmullb z0.h, z1.b, z2.b // CHECK-INST: sqdmullb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x60,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 60 42 45 sqdmullb z29.s, z30.h, z31.h // CHECK-INST: sqdmullb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x63,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 63 9f 45 sqdmullb z31.d, z31.s, z31.s // CHECK-INST: sqdmullb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x63,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 63 df 45 sqdmullb z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmullb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xe8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 e8 bf 44 sqdmullb z0.d, z1.s, z15.s[1] // CHECK-INST: sqdmullb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xe8,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 e8 ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqdmullt.s b/llvm/test/MC/AArch64/SVE2/sqdmullt.s index 6c9e6a654ea7d..a051d3fefd2b8 100644 --- a/llvm/test/MC/AArch64/SVE2/sqdmullt.s +++ b/llvm/test/MC/AArch64/SVE2/sqdmullt.s @@ -13,29 +13,29 @@ sqdmullt z0.h, z1.b, z2.b // CHECK-INST: sqdmullt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x64,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 64 42 45 sqdmullt z29.s, z30.h, z31.h // CHECK-INST: sqdmullt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x67,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 67 9f 45 sqdmullt z31.d, z31.s, z31.s // CHECK-INST: sqdmullt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x67,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 67 df 45 sqdmullt z0.s, z1.h, z7.h[7] // CHECK-INST: sqdmullt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xec,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 ec bf 44 sqdmullt z0.d, z1.s, z15.s[1] // CHECK-INST: sqdmullt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xec,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 ec ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqneg.s b/llvm/test/MC/AArch64/SVE2/sqneg.s index 39417242a30b1..42d84836425a4 100644 --- a/llvm/test/MC/AArch64/SVE2/sqneg.s +++ b/llvm/test/MC/AArch64/SVE2/sqneg.s @@ -12,25 +12,25 @@ sqneg z31.b, p7/m, z31.b // CHECK-INST: sqneg z31.b, p7/m, z31.b // CHECK-ENCODING: [0xff,0xbf,0x09,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 09 44 sqneg z31.h, p7/m, z31.h // CHECK-INST: sqneg z31.h, p7/m, z31.h // CHECK-ENCODING: [0xff,0xbf,0x49,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 49 44 sqneg z31.s, p7/m, z31.s // CHECK-INST: sqneg z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x89,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 89 44 sqneg z31.d, p7/m, z31.d // CHECK-INST: sqneg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf c9 44 @@ -40,23 +40,23 @@ sqneg z31.d, p7/m, z31.d movprfx z4.s, p7/z, z6.s // CHECK-INST: movprfx z4.s, p7/z, z6.s // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 90 04 sqneg z4.s, p7/m, z31.s // CHECK-INST: sqneg z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x89,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 89 44 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sqneg z4.s, p7/m, z31.s // CHECK-INST: sqneg z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x89,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 89 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s index 5e8942842bd17..267ac0b4cadbc 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s +++ b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s @@ -12,121 +12,121 @@ sqrdcmlah z0.b, z1.b, z2.b, #0 // CHECK-INST: sqrdcmlah z0.b, z1.b, z2.b, #0 // CHECK-ENCODING: [0x20,0x30,0x02,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 30 02 44 sqrdcmlah z0.h, z1.h, z2.h, #0 // CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h, #0 // CHECK-ENCODING: [0x20,0x30,0x42,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 30 42 44 sqrdcmlah z0.s, z1.s, z2.s, #0 // CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s, #0 // CHECK-ENCODING: [0x20,0x30,0x82,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 30 82 44 sqrdcmlah z0.d, z1.d, z2.d, #0 // CHECK-INST: sqrdcmlah z0.d, z1.d, z2.d, #0 // CHECK-ENCODING: [0x20,0x30,0xc2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 30 c2 44 sqrdcmlah z29.b, z30.b, z31.b, #90 // CHECK-INST: sqrdcmlah z29.b, z30.b, z31.b, #90 // CHECK-ENCODING: [0xdd,0x37,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 37 1f 44 sqrdcmlah z29.h, z30.h, z31.h, #90 // CHECK-INST: sqrdcmlah z29.h, z30.h, z31.h, #90 // CHECK-ENCODING: [0xdd,0x37,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 37 5f 44 sqrdcmlah z29.s, z30.s, z31.s, #90 // CHECK-INST: sqrdcmlah z29.s, z30.s, z31.s, #90 // CHECK-ENCODING: [0xdd,0x37,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 37 9f 44 sqrdcmlah z29.d, z30.d, z31.d, #90 // CHECK-INST: sqrdcmlah z29.d, z30.d, z31.d, #90 // CHECK-ENCODING: [0xdd,0x37,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 37 df 44 sqrdcmlah z31.b, z31.b, z31.b, #180 // CHECK-INST: sqrdcmlah z31.b, z31.b, z31.b, #180 // CHECK-ENCODING: [0xff,0x3b,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 1f 44 sqrdcmlah z31.h, z31.h, z31.h, #180 // CHECK-INST: sqrdcmlah z31.h, z31.h, z31.h, #180 // CHECK-ENCODING: [0xff,0x3b,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 5f 44 sqrdcmlah z31.s, z31.s, z31.s, #180 // CHECK-INST: sqrdcmlah z31.s, z31.s, z31.s, #180 // CHECK-ENCODING: [0xff,0x3b,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 9f 44 sqrdcmlah z31.d, z31.d, z31.d, #180 // CHECK-INST: sqrdcmlah z31.d, z31.d, z31.d, #180 // CHECK-ENCODING: [0xff,0x3b,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b df 44 sqrdcmlah z15.b, z16.b, z17.b, #270 // CHECK-INST: sqrdcmlah z15.b, z16.b, z17.b, #270 // CHECK-ENCODING: [0x0f,0x3e,0x11,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 3e 11 44 sqrdcmlah z15.h, z16.h, z17.h, #270 // CHECK-INST: sqrdcmlah z15.h, z16.h, z17.h, #270 // CHECK-ENCODING: [0x0f,0x3e,0x51,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 3e 51 44 sqrdcmlah z15.s, z16.s, z17.s, #270 // CHECK-INST: sqrdcmlah z15.s, z16.s, z17.s, #270 // CHECK-ENCODING: [0x0f,0x3e,0x91,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 3e 91 44 sqrdcmlah z15.d, z16.d, z17.d, #270 // CHECK-INST: sqrdcmlah z15.d, z16.d, z17.d, #270 // CHECK-ENCODING: [0x0f,0x3e,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 3e d1 44 sqrdcmlah z0.h, z1.h, z2.h[0], #0 // CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h[0], #0 // CHECK-ENCODING: [0x20,0x70,0xa2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 a2 44 sqrdcmlah z0.s, z1.s, z2.s[0], #0 // CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s[0], #0 // CHECK-ENCODING: [0x20,0x70,0xe2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 e2 44 sqrdcmlah z31.h, z30.h, z7.h[0], #180 // CHECK-INST: sqrdcmlah z31.h, z30.h, z7.h[0], #180 // CHECK-ENCODING: [0xdf,0x7b,0xa7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 7b a7 44 sqrdcmlah z31.s, z30.s, z7.s[0], #180 // CHECK-INST: sqrdcmlah z31.s, z30.s, z7.s[0], #180 // CHECK-ENCODING: [0xdf,0x7b,0xe7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 7b e7 44 @@ -136,23 +136,23 @@ sqrdcmlah z31.s, z30.s, z7.s[0], #180 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 sqrdcmlah z4.d, z31.d, z31.d, #270 // CHECK-INST: sqrdcmlah z4.d, z31.d, z31.d, #270 // CHECK-ENCODING: [0xe4,0x3f,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 3f df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 sqrdcmlah z21.s, z10.s, z5.s[1], #90 // CHECK-INST: sqrdcmlah z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x75,0xf5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 75 f5 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s index 7c7c6117f2bfb..af31b9b9b64be 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s +++ b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s @@ -13,43 +13,43 @@ sqrdmlah z0.b, z1.b, z31.b // CHECK-INST: sqrdmlah z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0x70,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 1f 44 sqrdmlah z0.h, z1.h, z31.h // CHECK-INST: sqrdmlah z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x70,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 5f 44 sqrdmlah z0.s, z1.s, z31.s // CHECK-INST: sqrdmlah z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x70,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 9f 44 sqrdmlah z0.d, z1.d, z31.d // CHECK-INST: sqrdmlah z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x70,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 df 44 sqrdmlah z0.h, z1.h, z7.h[7] // CHECK-INST: sqrdmlah z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x10,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 7f 44 sqrdmlah z0.s, z1.s, z7.s[3] // CHECK-INST: sqrdmlah z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x10,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 bf 44 sqrdmlah z0.d, z1.d, z15.d[1] // CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0x10,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 ff 44 @@ -59,23 +59,23 @@ sqrdmlah z0.d, z1.d, z15.d[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqrdmlah z0.d, z1.d, z31.d // CHECK-INST: sqrdmlah z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x70,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 df 44 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqrdmlah z0.d, z1.d, z15.d[1] // CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0x10,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s index 1f79608ed99bc..25d7b2efd8527 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s +++ b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s @@ -12,43 +12,43 @@ sqrdmlsh z0.b, z1.b, z31.b // CHECK-INST: sqrdmlsh z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0x74,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 1f 44 sqrdmlsh z0.h, z1.h, z31.h // CHECK-INST: sqrdmlsh z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0x74,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 5f 44 sqrdmlsh z0.s, z1.s, z31.s // CHECK-INST: sqrdmlsh z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0x74,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 9f 44 sqrdmlsh z0.d, z1.d, z31.d // CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x74,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 df 44 sqrdmlsh z0.h, z1.h, z7.h[7] // CHECK-INST: sqrdmlsh z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x14,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 7f 44 sqrdmlsh z0.s, z1.s, z7.s[3] // CHECK-INST: sqrdmlsh z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0x14,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 bf 44 sqrdmlsh z0.d, z1.d, z15.d[1] // CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0x14,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 ff 44 @@ -58,23 +58,23 @@ sqrdmlsh z0.d, z1.d, z15.d[1] movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqrdmlsh z0.d, z1.d, z31.d // CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x74,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 df 44 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 sqrdmlsh z0.d, z1.d, z15.d[1] // CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0x14,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s index 249edeb326f98..3791327d40abe 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s +++ b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s @@ -12,41 +12,41 @@ sqrdmulh z0.b, z1.b, z2.b // CHECK-INST: sqrdmulh z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x74,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 22 04 sqrdmulh z0.h, z1.h, z2.h // CHECK-INST: sqrdmulh z0.h, z1.h, z2.h // CHECK-ENCODING: [0x20,0x74,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 62 04 sqrdmulh z29.s, z30.s, z31.s // CHECK-INST: sqrdmulh z29.s, z30.s, z31.s // CHECK-ENCODING: [0xdd,0x77,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 77 bf 04 sqrdmulh z31.d, z31.d, z31.d // CHECK-INST: sqrdmulh z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x77,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 77 ff 04 sqrdmulh z0.h, z1.h, z7.h[7] // CHECK-INST: sqrdmulh z0.h, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xf4,0x7f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f4 7f 44 sqrdmulh z0.s, z1.s, z7.s[3] // CHECK-INST: sqrdmulh z0.s, z1.s, z7.s[3] // CHECK-ENCODING: [0x20,0xf4,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f4 bf 44 sqrdmulh z0.d, z1.d, z15.d[1] // CHECK-INST: sqrdmulh z0.d, z1.d, z15.d[1] // CHECK-ENCODING: [0x20,0xf4,0xff,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 f4 ff 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshl.s b/llvm/test/MC/AArch64/SVE2/sqrshl.s index 59e2904191bb8..0a8c9514a6a66 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshl.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshl.s @@ -12,25 +12,25 @@ sqrshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0a 44 sqrshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4a 44 sqrshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8a 44 sqrshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f ca 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqrshl z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqrshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xca,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 ca 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqrshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f ca 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshlr.s b/llvm/test/MC/AArch64/SVE2/sqrshlr.s index 29bd8e5b99c63..70644cfea42f6 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshlr.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshlr.s @@ -12,25 +12,25 @@ sqrshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0e 44 sqrshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4e 44 sqrshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8e 44 sqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f ce 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqrshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqrshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xce,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 ce 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f ce 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s index bb7d482bf9507..9dde993312155 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s @@ -12,35 +12,35 @@ sqrshrnb z0.b, z0.h, #1 // CHECK-INST: sqrshrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x28,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 28 2f 45 sqrshrnb z31.b, z31.h, #8 // CHECK-INST: sqrshrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x2b,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 28 45 sqrshrnb z0.h, z0.s, #1 // CHECK-INST: sqrshrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x28,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 28 3f 45 sqrshrnb z31.h, z31.s, #16 // CHECK-INST: sqrshrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x2b,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 30 45 sqrshrnb z0.s, z0.d, #1 // CHECK-INST: sqrshrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x28,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 28 7f 45 sqrshrnb z31.s, z31.d, #32 // CHECK-INST: sqrshrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x2b,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2b 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s index b003cb80dfb19..afd518ea41c02 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s @@ -12,35 +12,35 @@ sqrshrnt z0.b, z0.h, #1 // CHECK-INST: sqrshrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x2c,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 2c 2f 45 sqrshrnt z31.b, z31.h, #8 // CHECK-INST: sqrshrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x2f,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f 28 45 sqrshrnt z0.h, z0.s, #1 // CHECK-INST: sqrshrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x2c,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 2c 3f 45 sqrshrnt z31.h, z31.s, #16 // CHECK-INST: sqrshrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x2f,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f 30 45 sqrshrnt z0.s, z0.d, #1 // CHECK-INST: sqrshrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x2c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 2c 7f 45 sqrshrnt z31.s, z31.d, #32 // CHECK-INST: sqrshrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x2f,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s index 89b1a05aa635b..471271cb36def 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s @@ -12,35 +12,35 @@ sqrshrunb z0.b, z0.h, #1 // CHECK-INST: sqrshrunb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x08,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 08 2f 45 sqrshrunb z31.b, z31.h, #8 // CHECK-INST: sqrshrunb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x0b,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0b 28 45 sqrshrunb z0.h, z0.s, #1 // CHECK-INST: sqrshrunb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x08,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 08 3f 45 sqrshrunb z31.h, z31.s, #16 // CHECK-INST: sqrshrunb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x0b,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0b 30 45 sqrshrunb z0.s, z0.d, #1 // CHECK-INST: sqrshrunb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x08,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 08 7f 45 sqrshrunb z31.s, z31.d, #32 // CHECK-INST: sqrshrunb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x0b,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0b 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s index a6884ba0aaa47..1c71e5240ce8b 100644 --- a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s +++ b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s @@ -12,35 +12,35 @@ sqrshrunt z0.b, z0.h, #1 // CHECK-INST: sqrshrunt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x0c,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 0c 2f 45 sqrshrunt z31.b, z31.h, #8 // CHECK-INST: sqrshrunt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x0f,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0f 28 45 sqrshrunt z0.h, z0.s, #1 // CHECK-INST: sqrshrunt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x0c,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 0c 3f 45 sqrshrunt z31.h, z31.s, #16 // CHECK-INST: sqrshrunt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x0f,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0f 30 45 sqrshrunt z0.s, z0.d, #1 // CHECK-INST: sqrshrunt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x0c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 0c 7f 45 sqrshrunt z31.s, z31.d, #32 // CHECK-INST: sqrshrunt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x0f,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0f 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqshl.s b/llvm/test/MC/AArch64/SVE2/sqshl.s index 994cdbf287afe..9548d99ba704b 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshl.s +++ b/llvm/test/MC/AArch64/SVE2/sqshl.s @@ -12,73 +12,73 @@ sqshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x08,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 08 44 sqshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x48,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 48 44 sqshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x88,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 88 44 sqshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c8 44 sqshl z0.b, p0/m, z0.b, #0 // CHECK-INST: sqshl z0.b, p0/m, z0.b, #0 // CHECK-ENCODING: [0x00,0x81,0x06,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 81 06 04 sqshl z31.b, p0/m, z31.b, #7 // CHECK-INST: sqshl z31.b, p0/m, z31.b, #7 // CHECK-ENCODING: [0xff,0x81,0x06,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 81 06 04 sqshl z0.h, p0/m, z0.h, #0 // CHECK-INST: sqshl z0.h, p0/m, z0.h, #0 // CHECK-ENCODING: [0x00,0x82,0x06,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 82 06 04 sqshl z31.h, p0/m, z31.h, #15 // CHECK-INST: sqshl z31.h, p0/m, z31.h, #15 // CHECK-ENCODING: [0xff,0x83,0x06,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 06 04 sqshl z0.s, p0/m, z0.s, #0 // CHECK-INST: sqshl z0.s, p0/m, z0.s, #0 // CHECK-ENCODING: [0x00,0x80,0x46,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 46 04 sqshl z31.s, p0/m, z31.s, #31 // CHECK-INST: sqshl z31.s, p0/m, z31.s, #31 // CHECK-ENCODING: [0xff,0x83,0x46,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 46 04 sqshl z0.d, p0/m, z0.d, #0 // CHECK-INST: sqshl z0.d, p0/m, z0.d, #0 // CHECK-ENCODING: [0x00,0x80,0x86,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 86 04 sqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c6 04 // --------------------------------------------------------------------------// @@ -87,47 +87,47 @@ sqshl z31.d, p0/m, z31.d, #63 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c8 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c8 44 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c6 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c6 04 diff --git a/llvm/test/MC/AArch64/SVE2/sqshlr.s b/llvm/test/MC/AArch64/SVE2/sqshlr.s index fcf7461d88c10..819ea1757237d 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshlr.s +++ b/llvm/test/MC/AArch64/SVE2/sqshlr.s @@ -12,25 +12,25 @@ sqshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0c 44 sqshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4c 44 sqshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8c 44 sqshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cc 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xcc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 cc 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cc 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqshlu.s b/llvm/test/MC/AArch64/SVE2/sqshlu.s index e70d1d89de0f8..cf4138027929c 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshlu.s +++ b/llvm/test/MC/AArch64/SVE2/sqshlu.s @@ -12,49 +12,49 @@ sqshlu z0.b, p0/m, z0.b, #0 // CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0 // CHECK-ENCODING: [0x00,0x81,0x0f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 81 0f 04 sqshlu z31.b, p0/m, z31.b, #7 // CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7 // CHECK-ENCODING: [0xff,0x81,0x0f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 81 0f 04 sqshlu z0.h, p0/m, z0.h, #0 // CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0 // CHECK-ENCODING: [0x00,0x82,0x0f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 82 0f 04 sqshlu z31.h, p0/m, z31.h, #15 // CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15 // CHECK-ENCODING: [0xff,0x83,0x0f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 0f 04 sqshlu z0.s, p0/m, z0.s, #0 // CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0 // CHECK-ENCODING: [0x00,0x80,0x4f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 4f 04 sqshlu z31.s, p0/m, z31.s, #31 // CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31 // CHECK-ENCODING: [0xff,0x83,0x4f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 4f 04 sqshlu z0.d, p0/m, z0.d, #0 // CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0 // CHECK-ENCODING: [0x00,0x80,0x8f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 8f 04 sqshlu z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 cf 04 // --------------------------------------------------------------------------// @@ -63,23 +63,23 @@ sqshlu z31.d, p0/m, z31.d, #63 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqshlu z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 cf 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqshlu z31.d, p0/m, z31.d, #63 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 cf 04 diff --git a/llvm/test/MC/AArch64/SVE2/sqshrnb.s b/llvm/test/MC/AArch64/SVE2/sqshrnb.s index 0a1343d90de7c..ffe672501fb56 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshrnb.s +++ b/llvm/test/MC/AArch64/SVE2/sqshrnb.s @@ -12,35 +12,35 @@ sqshrnb z0.b, z0.h, #1 // CHECK-INST: sqshrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x20,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 20 2f 45 sqshrnb z31.b, z31.h, #8 // CHECK-INST: sqshrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x23,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 23 28 45 sqshrnb z0.h, z0.s, #1 // CHECK-INST: sqshrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x20,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 20 3f 45 sqshrnb z31.h, z31.s, #16 // CHECK-INST: sqshrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x23,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 23 30 45 sqshrnb z0.s, z0.d, #1 // CHECK-INST: sqshrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x20,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 20 7f 45 sqshrnb z31.s, z31.d, #32 // CHECK-INST: sqshrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x23,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 23 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqshrnt.s b/llvm/test/MC/AArch64/SVE2/sqshrnt.s index 18fea9e797f6e..24bfcf4f829cc 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshrnt.s +++ b/llvm/test/MC/AArch64/SVE2/sqshrnt.s @@ -12,35 +12,35 @@ sqshrnt z0.b, z0.h, #1 // CHECK-INST: sqshrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x24,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 24 2f 45 sqshrnt z31.b, z31.h, #8 // CHECK-INST: sqshrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x27,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 27 28 45 sqshrnt z0.h, z0.s, #1 // CHECK-INST: sqshrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x24,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 24 3f 45 sqshrnt z31.h, z31.s, #16 // CHECK-INST: sqshrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x27,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 27 30 45 sqshrnt z0.s, z0.d, #1 // CHECK-INST: sqshrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x24,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 24 7f 45 sqshrnt z31.s, z31.d, #32 // CHECK-INST: sqshrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x27,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 27 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqshrunb.s b/llvm/test/MC/AArch64/SVE2/sqshrunb.s index 58672f00ba2b5..8811900c5ed27 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshrunb.s +++ b/llvm/test/MC/AArch64/SVE2/sqshrunb.s @@ -12,35 +12,35 @@ sqshrunb z0.b, z0.h, #1 // CHECK-INST: sqshrunb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x00,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 00 2f 45 sqshrunb z31.b, z31.h, #8 // CHECK-INST: sqshrunb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x03,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 03 28 45 sqshrunb z0.h, z0.s, #1 // CHECK-INST: sqshrunb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x00,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 00 3f 45 sqshrunb z31.h, z31.s, #16 // CHECK-INST: sqshrunb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x03,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 03 30 45 sqshrunb z0.s, z0.d, #1 // CHECK-INST: sqshrunb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x00,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 00 7f 45 sqshrunb z31.s, z31.d, #32 // CHECK-INST: sqshrunb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x03,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 03 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqshrunt.s b/llvm/test/MC/AArch64/SVE2/sqshrunt.s index 15efa20cf7b74..50005c2badc7d 100644 --- a/llvm/test/MC/AArch64/SVE2/sqshrunt.s +++ b/llvm/test/MC/AArch64/SVE2/sqshrunt.s @@ -12,35 +12,35 @@ sqshrunt z0.b, z0.h, #1 // CHECK-INST: sqshrunt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x04,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 04 2f 45 sqshrunt z31.b, z31.h, #8 // CHECK-INST: sqshrunt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x07,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 07 28 45 sqshrunt z0.h, z0.s, #1 // CHECK-INST: sqshrunt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x04,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 04 3f 45 sqshrunt z31.h, z31.s, #16 // CHECK-INST: sqshrunt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x07,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 07 30 45 sqshrunt z0.s, z0.d, #1 // CHECK-INST: sqshrunt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x04,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 04 7f 45 sqshrunt z31.s, z31.d, #32 // CHECK-INST: sqshrunt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x07,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 07 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqsub.s b/llvm/test/MC/AArch64/SVE2/sqsub.s index c9473cce0586e..4717bb3fc2d3b 100644 --- a/llvm/test/MC/AArch64/SVE2/sqsub.s +++ b/llvm/test/MC/AArch64/SVE2/sqsub.s @@ -12,25 +12,25 @@ sqsub z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqsub z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1a 44 sqsub z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqsub z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5a 44 sqsub z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqsub z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9a,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9a 44 sqsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xda,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f da 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqsub z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqsub z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqsub z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xda,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 da 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xda,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f da 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqsubr.s b/llvm/test/MC/AArch64/SVE2/sqsubr.s index 13198a5322690..6b911b6b58448 100644 --- a/llvm/test/MC/AArch64/SVE2/sqsubr.s +++ b/llvm/test/MC/AArch64/SVE2/sqsubr.s @@ -12,25 +12,25 @@ sqsubr z0.b, p0/m, z0.b, z1.b // CHECK-INST: sqsubr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1e 44 sqsubr z0.h, p0/m, z0.h, z1.h // CHECK-INST: sqsubr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5e 44 sqsubr z29.s, p7/m, z29.s, z30.s // CHECK-INST: sqsubr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9e,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9e 44 sqsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xde,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f de 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ sqsubr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 sqsubr z31.d, p0/m, z31.d, z30.d // CHECK-INST: sqsubr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xde,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 de 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 sqsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xde,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f de 44 diff --git a/llvm/test/MC/AArch64/SVE2/sqxtnb.s b/llvm/test/MC/AArch64/SVE2/sqxtnb.s index 8e3b14c0a7d60..95a7eb6ce167f 100644 --- a/llvm/test/MC/AArch64/SVE2/sqxtnb.s +++ b/llvm/test/MC/AArch64/SVE2/sqxtnb.s @@ -13,17 +13,17 @@ sqxtnb z0.b, z31.h // CHECK-INST: sqxtnb z0.b, z31.h // CHECK-ENCODING: [0xe0,0x43,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 43 28 45 sqxtnb z0.h, z31.s // CHECK-INST: sqxtnb z0.h, z31.s // CHECK-ENCODING: [0xe0,0x43,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 43 30 45 sqxtnb z0.s, z31.d // CHECK-INST: sqxtnb z0.s, z31.d // CHECK-ENCODING: [0xe0,0x43,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 43 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqxtnt.s b/llvm/test/MC/AArch64/SVE2/sqxtnt.s index 74c0ec8165bec..7db4905d71c31 100644 --- a/llvm/test/MC/AArch64/SVE2/sqxtnt.s +++ b/llvm/test/MC/AArch64/SVE2/sqxtnt.s @@ -13,17 +13,17 @@ sqxtnt z0.b, z31.h // CHECK-INST: sqxtnt z0.b, z31.h // CHECK-ENCODING: [0xe0,0x47,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 47 28 45 sqxtnt z0.h, z31.s // CHECK-INST: sqxtnt z0.h, z31.s // CHECK-ENCODING: [0xe0,0x47,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 47 30 45 sqxtnt z0.s, z31.d // CHECK-INST: sqxtnt z0.s, z31.d // CHECK-ENCODING: [0xe0,0x47,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 47 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqxtunb.s b/llvm/test/MC/AArch64/SVE2/sqxtunb.s index 5d6d9574cd0f6..6dcecc8646c70 100644 --- a/llvm/test/MC/AArch64/SVE2/sqxtunb.s +++ b/llvm/test/MC/AArch64/SVE2/sqxtunb.s @@ -13,17 +13,17 @@ sqxtunb z0.b, z31.h // CHECK-INST: sqxtunb z0.b, z31.h // CHECK-ENCODING: [0xe0,0x53,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 53 28 45 sqxtunb z0.h, z31.s // CHECK-INST: sqxtunb z0.h, z31.s // CHECK-ENCODING: [0xe0,0x53,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 53 30 45 sqxtunb z0.s, z31.d // CHECK-INST: sqxtunb z0.s, z31.d // CHECK-ENCODING: [0xe0,0x53,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 53 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/sqxtunt.s b/llvm/test/MC/AArch64/SVE2/sqxtunt.s index a75f54d70f311..2ba103a66fa28 100644 --- a/llvm/test/MC/AArch64/SVE2/sqxtunt.s +++ b/llvm/test/MC/AArch64/SVE2/sqxtunt.s @@ -13,17 +13,17 @@ sqxtunt z0.b, z31.h // CHECK-INST: sqxtunt z0.b, z31.h // CHECK-ENCODING: [0xe0,0x57,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 57 28 45 sqxtunt z0.h, z31.s // CHECK-INST: sqxtunt z0.h, z31.s // CHECK-ENCODING: [0xe0,0x57,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 57 30 45 sqxtunt z0.s, z31.d // CHECK-INST: sqxtunt z0.s, z31.d // CHECK-ENCODING: [0xe0,0x57,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 57 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/srhadd.s b/llvm/test/MC/AArch64/SVE2/srhadd.s index 0f57ab88a6319..5d0375a7f8a21 100644 --- a/llvm/test/MC/AArch64/SVE2/srhadd.s +++ b/llvm/test/MC/AArch64/SVE2/srhadd.s @@ -12,25 +12,25 @@ srhadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x14,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 14 44 srhadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x54,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 54 44 srhadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x94,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 94 44 srhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d4 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ srhadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 srhadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d4 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 srhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d4 44 diff --git a/llvm/test/MC/AArch64/SVE2/sri.s b/llvm/test/MC/AArch64/SVE2/sri.s index d264bb1fafe74..107bae5267502 100644 --- a/llvm/test/MC/AArch64/SVE2/sri.s +++ b/llvm/test/MC/AArch64/SVE2/sri.s @@ -12,47 +12,47 @@ sri z0.b, z0.b, #1 // CHECK-INST: sri z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0xf0,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f0 0f 45 sri z31.b, z31.b, #8 // CHECK-INST: sri z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0xf3,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f3 08 45 sri z0.h, z0.h, #1 // CHECK-INST: sri z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0xf0,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f0 1f 45 sri z31.h, z31.h, #16 // CHECK-INST: sri z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0xf3,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f3 10 45 sri z0.s, z0.s, #1 // CHECK-INST: sri z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0xf0,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f0 5f 45 sri z31.s, z31.s, #32 // CHECK-INST: sri z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0xf3,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f3 40 45 sri z0.d, z0.d, #1 // CHECK-INST: sri z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0xf0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 f0 df 45 sri z31.d, z31.d, #64 // CHECK-INST: sri z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0xf3,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff f3 80 45 diff --git a/llvm/test/MC/AArch64/SVE2/srshl.s b/llvm/test/MC/AArch64/SVE2/srshl.s index b9a98c79dc613..323ce653beee7 100644 --- a/llvm/test/MC/AArch64/SVE2/srshl.s +++ b/llvm/test/MC/AArch64/SVE2/srshl.s @@ -12,25 +12,25 @@ srshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: srshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x02,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 02 44 srshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: srshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x42,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 42 44 srshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: srshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x82,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 82 44 srshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c2 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ srshl z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 srshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: srshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c2 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 srshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c2 44 diff --git a/llvm/test/MC/AArch64/SVE2/srshlr.s b/llvm/test/MC/AArch64/SVE2/srshlr.s index 7c25316334e7d..e2f488f1d262c 100644 --- a/llvm/test/MC/AArch64/SVE2/srshlr.s +++ b/llvm/test/MC/AArch64/SVE2/srshlr.s @@ -12,25 +12,25 @@ srshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: srshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x06,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 06 44 srshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: srshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x46,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 46 44 srshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: srshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x86,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 86 44 srshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c6 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ srshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 srshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: srshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c6 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 srshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c6 44 diff --git a/llvm/test/MC/AArch64/SVE2/srshr.s b/llvm/test/MC/AArch64/SVE2/srshr.s index a8b71141bcba5..6a5bab3c88292 100644 --- a/llvm/test/MC/AArch64/SVE2/srshr.s +++ b/llvm/test/MC/AArch64/SVE2/srshr.s @@ -12,49 +12,49 @@ srshr z0.b, p0/m, z0.b, #1 // CHECK-INST: srshr z0.b, p0/m, z0.b, #1 // CHECK-ENCODING: [0xe0,0x81,0x0c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 81 0c 04 srshr z31.b, p0/m, z31.b, #8 // CHECK-INST: srshr z31.b, p0/m, z31.b, #8 // CHECK-ENCODING: [0x1f,0x81,0x0c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 81 0c 04 srshr z0.h, p0/m, z0.h, #1 // CHECK-INST: srshr z0.h, p0/m, z0.h, #1 // CHECK-ENCODING: [0xe0,0x83,0x0c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 0c 04 srshr z31.h, p0/m, z31.h, #16 // CHECK-INST: srshr z31.h, p0/m, z31.h, #16 // CHECK-ENCODING: [0x1f,0x82,0x0c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 82 0c 04 srshr z0.s, p0/m, z0.s, #1 // CHECK-INST: srshr z0.s, p0/m, z0.s, #1 // CHECK-ENCODING: [0xe0,0x83,0x4c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 4c 04 srshr z31.s, p0/m, z31.s, #32 // CHECK-INST: srshr z31.s, p0/m, z31.s, #32 // CHECK-ENCODING: [0x1f,0x80,0x4c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 4c 04 srshr z0.d, p0/m, z0.d, #1 // CHECK-INST: srshr z0.d, p0/m, z0.d, #1 // CHECK-ENCODING: [0xe0,0x83,0xcc,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 cc 04 srshr z31.d, p0/m, z31.d, #64 // CHECK-INST: srshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8c 04 @@ -64,23 +64,23 @@ srshr z31.d, p0/m, z31.d, #64 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 srshr z31.d, p0/m, z31.d, #64 // CHECK-INST: srshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8c 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 srshr z31.d, p0/m, z31.d, #64 // CHECK-INST: srshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8c 04 diff --git a/llvm/test/MC/AArch64/SVE2/srsra.s b/llvm/test/MC/AArch64/SVE2/srsra.s index 3deecc3805d70..ef6f95efa0ef3 100644 --- a/llvm/test/MC/AArch64/SVE2/srsra.s +++ b/llvm/test/MC/AArch64/SVE2/srsra.s @@ -12,49 +12,49 @@ srsra z0.b, z0.b, #1 // CHECK-INST: srsra z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0xe8,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e8 0f 45 srsra z31.b, z31.b, #8 // CHECK-INST: srsra z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0xeb,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff eb 08 45 srsra z0.h, z0.h, #1 // CHECK-INST: srsra z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0xe8,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e8 1f 45 srsra z31.h, z31.h, #16 // CHECK-INST: srsra z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0xeb,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff eb 10 45 srsra z0.s, z0.s, #1 // CHECK-INST: srsra z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0xe8,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e8 5f 45 srsra z31.s, z31.s, #32 // CHECK-INST: srsra z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0xeb,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff eb 40 45 srsra z0.d, z0.d, #1 // CHECK-INST: srsra z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0xe8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e8 df 45 srsra z31.d, z31.d, #64 // CHECK-INST: srsra z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0xeb,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff eb 80 45 @@ -64,11 +64,11 @@ srsra z31.d, z31.d, #64 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 srsra z0.d, z1.d, #1 // CHECK-INST: srsra z0.d, z1.d, #1 // CHECK-ENCODING: [0x20,0xe8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 e8 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/sshllb.s b/llvm/test/MC/AArch64/SVE2/sshllb.s index 11d40ed616670..8b486050b9f08 100644 --- a/llvm/test/MC/AArch64/SVE2/sshllb.s +++ b/llvm/test/MC/AArch64/SVE2/sshllb.s @@ -12,35 +12,35 @@ sshllb z0.h, z0.b, #0 // CHECK-INST: sshllb z0.h, z0.b, #0 // CHECK-ENCODING: [0x00,0xa0,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a0 08 45 sshllb z31.h, z31.b, #7 // CHECK-INST: sshllb z31.h, z31.b, #7 // CHECK-ENCODING: [0xff,0xa3,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a3 0f 45 sshllb z0.s, z0.h, #0 // CHECK-INST: sshllb z0.s, z0.h, #0 // CHECK-ENCODING: [0x00,0xa0,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a0 10 45 sshllb z31.s, z31.h, #15 // CHECK-INST: sshllb z31.s, z31.h, #15 // CHECK-ENCODING: [0xff,0xa3,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a3 1f 45 sshllb z0.d, z0.s, #0 // CHECK-INST: sshllb z0.d, z0.s, #0 // CHECK-ENCODING: [0x00,0xa0,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a0 40 45 sshllb z31.d, z31.s, #31 // CHECK-INST: sshllb z31.d, z31.s, #31 // CHECK-ENCODING: [0xff,0xa3,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a3 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/sshllt.s b/llvm/test/MC/AArch64/SVE2/sshllt.s index 600d27c543720..70e766ff46680 100644 --- a/llvm/test/MC/AArch64/SVE2/sshllt.s +++ b/llvm/test/MC/AArch64/SVE2/sshllt.s @@ -12,35 +12,35 @@ sshllt z0.h, z0.b, #0 // CHECK-INST: sshllt z0.h, z0.b, #0 // CHECK-ENCODING: [0x00,0xa4,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a4 08 45 sshllt z31.h, z31.b, #7 // CHECK-INST: sshllt z31.h, z31.b, #7 // CHECK-ENCODING: [0xff,0xa7,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a7 0f 45 sshllt z0.s, z0.h, #0 // CHECK-INST: sshllt z0.s, z0.h, #0 // CHECK-ENCODING: [0x00,0xa4,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a4 10 45 sshllt z31.s, z31.h, #15 // CHECK-INST: sshllt z31.s, z31.h, #15 // CHECK-ENCODING: [0xff,0xa7,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a7 1f 45 sshllt z0.d, z0.s, #0 // CHECK-INST: sshllt z0.d, z0.s, #0 // CHECK-ENCODING: [0x00,0xa4,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a4 40 45 sshllt z31.d, z31.s, #31 // CHECK-INST: sshllt z31.d, z31.s, #31 // CHECK-ENCODING: [0xff,0xa7,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff a7 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssra.s b/llvm/test/MC/AArch64/SVE2/ssra.s index b894595238d01..ab836a1b8a629 100644 --- a/llvm/test/MC/AArch64/SVE2/ssra.s +++ b/llvm/test/MC/AArch64/SVE2/ssra.s @@ -12,49 +12,49 @@ ssra z0.b, z0.b, #1 // CHECK-INST: ssra z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0xe0,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e0 0f 45 ssra z31.b, z31.b, #8 // CHECK-INST: ssra z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0xe3,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e3 08 45 ssra z0.h, z0.h, #1 // CHECK-INST: ssra z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0xe0,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e0 1f 45 ssra z31.h, z31.h, #16 // CHECK-INST: ssra z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0xe3,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e3 10 45 ssra z0.s, z0.s, #1 // CHECK-INST: ssra z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0xe0,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e0 5f 45 ssra z31.s, z31.s, #32 // CHECK-INST: ssra z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0xe3,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e3 40 45 ssra z0.d, z0.d, #1 // CHECK-INST: ssra z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0xe0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e0 df 45 ssra z31.d, z31.d, #64 // CHECK-INST: ssra z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0xe3,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e3 80 45 @@ -64,11 +64,11 @@ ssra z31.d, z31.d, #64 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 ssra z0.d, z1.d, #1 // CHECK-INST: ssra z0.d, z1.d, #1 // CHECK-ENCODING: [0x20,0xe0,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 e0 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssublb.s b/llvm/test/MC/AArch64/SVE2/ssublb.s index d1ce3743ee567..c006b0b2758a6 100644 --- a/llvm/test/MC/AArch64/SVE2/ssublb.s +++ b/llvm/test/MC/AArch64/SVE2/ssublb.s @@ -13,17 +13,17 @@ ssublb z0.h, z1.b, z2.b // CHECK-INST: ssublb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x10,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 10 42 45 ssublb z29.s, z30.h, z31.h // CHECK-INST: ssublb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x13,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 13 9f 45 ssublb z31.d, z31.s, z31.s // CHECK-INST: ssublb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x13,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 13 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssublbt.s b/llvm/test/MC/AArch64/SVE2/ssublbt.s index 214a201f9bf4f..c9fd11f35f932 100644 --- a/llvm/test/MC/AArch64/SVE2/ssublbt.s +++ b/llvm/test/MC/AArch64/SVE2/ssublbt.s @@ -13,17 +13,17 @@ ssublbt z0.h, z1.b, z31.b // CHECK-INST: ssublbt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x88,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 88 5f 45 ssublbt z0.s, z1.h, z31.h // CHECK-INST: ssublbt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x88,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 88 9f 45 ssublbt z0.d, z1.s, z31.s // CHECK-INST: ssublbt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x88,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 88 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssublt.s b/llvm/test/MC/AArch64/SVE2/ssublt.s index 52e532ff802ae..d92135ea3abc3 100644 --- a/llvm/test/MC/AArch64/SVE2/ssublt.s +++ b/llvm/test/MC/AArch64/SVE2/ssublt.s @@ -13,17 +13,17 @@ ssublt z0.h, z1.b, z2.b // CHECK-INST: ssublt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x14,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 14 42 45 ssublt z29.s, z30.h, z31.h // CHECK-INST: ssublt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x17,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 17 9f 45 ssublt z31.d, z31.s, z31.s // CHECK-INST: ssublt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x17,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 17 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssubltb.s b/llvm/test/MC/AArch64/SVE2/ssubltb.s index 47d6a701fc559..889ea63a9b6e5 100644 --- a/llvm/test/MC/AArch64/SVE2/ssubltb.s +++ b/llvm/test/MC/AArch64/SVE2/ssubltb.s @@ -13,17 +13,17 @@ ssubltb z0.h, z1.b, z31.b // CHECK-INST: ssubltb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x8c,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 8c 5f 45 ssubltb z0.s, z1.h, z31.h // CHECK-INST: ssubltb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x8c,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 8c 9f 45 ssubltb z0.d, z1.s, z31.s // CHECK-INST: ssubltb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x8c,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 8c df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssubwb.s b/llvm/test/MC/AArch64/SVE2/ssubwb.s index e8dce2aaaff32..ae625fc83d8ab 100644 --- a/llvm/test/MC/AArch64/SVE2/ssubwb.s +++ b/llvm/test/MC/AArch64/SVE2/ssubwb.s @@ -13,17 +13,17 @@ ssubwb z0.h, z1.h, z2.b // CHECK-INST: ssubwb z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x50,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 50 42 45 ssubwb z29.s, z30.s, z31.h // CHECK-INST: ssubwb z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x53,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 53 9f 45 ssubwb z31.d, z31.d, z31.s // CHECK-INST: ssubwb z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x53,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 53 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ssubwt.s b/llvm/test/MC/AArch64/SVE2/ssubwt.s index 08ea2d3fdc288..13bad073db887 100644 --- a/llvm/test/MC/AArch64/SVE2/ssubwt.s +++ b/llvm/test/MC/AArch64/SVE2/ssubwt.s @@ -13,17 +13,17 @@ ssubwt z0.h, z1.h, z2.b // CHECK-INST: ssubwt z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x54,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 54 42 45 ssubwt z29.s, z30.s, z31.h // CHECK-INST: ssubwt z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x57,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 57 9f 45 ssubwt z31.d, z31.d, z31.s // CHECK-INST: ssubwt z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x57,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 57 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/subhnb.s b/llvm/test/MC/AArch64/SVE2/subhnb.s index d58e944123992..8a3a434a158dd 100644 --- a/llvm/test/MC/AArch64/SVE2/subhnb.s +++ b/llvm/test/MC/AArch64/SVE2/subhnb.s @@ -13,17 +13,17 @@ subhnb z0.b, z1.h, z31.h // CHECK-INST: subhnb z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x70,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 7f 45 subhnb z0.h, z1.s, z31.s // CHECK-INST: subhnb z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x70,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 bf 45 subhnb z0.s, z1.d, z31.d // CHECK-INST: subhnb z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x70,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 70 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/subhnt.s b/llvm/test/MC/AArch64/SVE2/subhnt.s index 01c46e7d2705a..ec3599dffb459 100644 --- a/llvm/test/MC/AArch64/SVE2/subhnt.s +++ b/llvm/test/MC/AArch64/SVE2/subhnt.s @@ -13,17 +13,17 @@ subhnt z0.b, z1.h, z31.h // CHECK-INST: subhnt z0.b, z1.h, z31.h // CHECK-ENCODING: [0x20,0x74,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 7f 45 subhnt z0.h, z1.s, z31.s // CHECK-INST: subhnt z0.h, z1.s, z31.s // CHECK-ENCODING: [0x20,0x74,0xbf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 bf 45 subhnt z0.s, z1.d, z31.d // CHECK-INST: subhnt z0.s, z1.d, z31.d // CHECK-ENCODING: [0x20,0x74,0xff,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 74 ff 45 diff --git a/llvm/test/MC/AArch64/SVE2/suqadd.s b/llvm/test/MC/AArch64/SVE2/suqadd.s index d69c3dfd2df08..e450fa7e20179 100644 --- a/llvm/test/MC/AArch64/SVE2/suqadd.s +++ b/llvm/test/MC/AArch64/SVE2/suqadd.s @@ -12,25 +12,25 @@ suqadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: suqadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1c 44 suqadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: suqadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5c 44 suqadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: suqadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9c,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9c 44 suqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f dc 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ suqadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 suqadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: suqadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xdc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 dc 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 suqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f dc 44 diff --git a/llvm/test/MC/AArch64/SVE2/tbl.s b/llvm/test/MC/AArch64/SVE2/tbl.s index c2bb20ac21a27..e3f764a78acd7 100644 --- a/llvm/test/MC/AArch64/SVE2/tbl.s +++ b/llvm/test/MC/AArch64/SVE2/tbl.s @@ -12,23 +12,23 @@ tbl z28.b, { z29.b, z30.b }, z31.b // CHECK-INST: tbl z28.b, { z29.b, z30.b }, z31.b // CHECK-ENCODING: [0xbc,0x2b,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bc 2b 3f 05 tbl z28.h, { z29.h, z30.h }, z31.h // CHECK-INST: tbl z28.h, { z29.h, z30.h }, z31.h // CHECK-ENCODING: [0xbc,0x2b,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bc 2b 7f 05 tbl z28.s, { z29.s, z30.s }, z31.s // CHECK-INST: tbl z28.s, { z29.s, z30.s }, z31.s // CHECK-ENCODING: [0xbc,0x2b,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bc 2b bf 05 tbl z28.d, { z29.d, z30.d }, z31.d // CHECK-INST: tbl z28.d, { z29.d, z30.d }, z31.d // CHECK-ENCODING: [0xbc,0x2b,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: bc 2b ff 05 diff --git a/llvm/test/MC/AArch64/SVE2/tbx.s b/llvm/test/MC/AArch64/SVE2/tbx.s index e2a6c827a7471..45f3c5d0ce2a6 100644 --- a/llvm/test/MC/AArch64/SVE2/tbx.s +++ b/llvm/test/MC/AArch64/SVE2/tbx.s @@ -12,23 +12,23 @@ tbx z31.b, z31.b, z31.b // CHECK-INST: tbx z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x2f,0x3f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f 3f 05 tbx z31.h, z31.h, z31.h // CHECK-INST: tbx z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x2f,0x7f,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f 7f 05 tbx z31.s, z31.s, z31.s // CHECK-INST: tbx z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x2f,0xbf,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f bf 05 tbx z31.d, z31.d, z31.d // CHECK-INST: tbx z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x2f,0xff,0x05] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 2f ff 05 diff --git a/llvm/test/MC/AArch64/SVE2/uaba.s b/llvm/test/MC/AArch64/SVE2/uaba.s index e18a598872d9f..ff241366f7879 100644 --- a/llvm/test/MC/AArch64/SVE2/uaba.s +++ b/llvm/test/MC/AArch64/SVE2/uaba.s @@ -12,25 +12,25 @@ uaba z0.b, z1.b, z31.b // CHECK-INST: uaba z0.b, z1.b, z31.b // CHECK-ENCODING: [0x20,0xfc,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 fc 1f 45 uaba z0.h, z1.h, z31.h // CHECK-INST: uaba z0.h, z1.h, z31.h // CHECK-ENCODING: [0x20,0xfc,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 fc 5f 45 uaba z0.s, z1.s, z31.s // CHECK-INST: uaba z0.s, z1.s, z31.s // CHECK-ENCODING: [0x20,0xfc,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 fc 9f 45 uaba z0.d, z1.d, z31.d // CHECK-INST: uaba z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 fc df 45 @@ -40,11 +40,11 @@ uaba z0.d, z1.d, z31.d movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 uaba z0.d, z1.d, z31.d // CHECK-INST: uaba z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 fc df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uabalb.s b/llvm/test/MC/AArch64/SVE2/uabalb.s index 1e2e5111f9102..964b9f79edd78 100644 --- a/llvm/test/MC/AArch64/SVE2/uabalb.s +++ b/llvm/test/MC/AArch64/SVE2/uabalb.s @@ -13,19 +13,19 @@ uabalb z0.h, z1.b, z31.b // CHECK-INST: uabalb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0xc8,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c8 5f 45 uabalb z0.s, z1.h, z31.h // CHECK-INST: uabalb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0xc8,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c8 9f 45 uabalb z0.d, z1.s, z31.s // CHECK-INST: uabalb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0xc8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 c8 df 45 @@ -35,11 +35,11 @@ uabalb z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 uabalb z21.d, z1.s, z31.s // CHECK-INST: uabalb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0xc8,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 c8 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uabalt.s b/llvm/test/MC/AArch64/SVE2/uabalt.s index 6ed5465237770..db529fed0f0a2 100644 --- a/llvm/test/MC/AArch64/SVE2/uabalt.s +++ b/llvm/test/MC/AArch64/SVE2/uabalt.s @@ -13,19 +13,19 @@ uabalt z0.h, z1.b, z31.b // CHECK-INST: uabalt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0xcc,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 cc 5f 45 uabalt z0.s, z1.h, z31.h // CHECK-INST: uabalt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0xcc,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 cc 9f 45 uabalt z0.d, z1.s, z31.s // CHECK-INST: uabalt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0xcc,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 cc df 45 @@ -35,11 +35,11 @@ uabalt z0.d, z1.s, z31.s movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 uabalt z21.d, z1.s, z31.s // CHECK-INST: uabalt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0xcc,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 cc df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uabdlb.s b/llvm/test/MC/AArch64/SVE2/uabdlb.s index 17205ec560d4d..d38b1b0db4303 100644 --- a/llvm/test/MC/AArch64/SVE2/uabdlb.s +++ b/llvm/test/MC/AArch64/SVE2/uabdlb.s @@ -13,17 +13,17 @@ uabdlb z0.h, z1.b, z2.b // CHECK-INST: uabdlb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x38,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 38 42 45 uabdlb z29.s, z30.h, z31.h // CHECK-INST: uabdlb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x3b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 3b 9f 45 uabdlb z31.d, z31.s, z31.s // CHECK-INST: uabdlb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x3b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uabdlt.s b/llvm/test/MC/AArch64/SVE2/uabdlt.s index 9a2ddddcd0230..70b746e88bb99 100644 --- a/llvm/test/MC/AArch64/SVE2/uabdlt.s +++ b/llvm/test/MC/AArch64/SVE2/uabdlt.s @@ -13,17 +13,17 @@ uabdlt z0.h, z1.b, z2.b // CHECK-INST: uabdlt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x3c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 3c 42 45 uabdlt z29.s, z30.h, z31.h // CHECK-INST: uabdlt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x3f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 3f 9f 45 uabdlt z31.d, z31.s, z31.s // CHECK-INST: uabdlt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x3f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uadalp.s b/llvm/test/MC/AArch64/SVE2/uadalp.s index 8887f132db16a..31d2d8ace3373 100644 --- a/llvm/test/MC/AArch64/SVE2/uadalp.s +++ b/llvm/test/MC/AArch64/SVE2/uadalp.s @@ -12,19 +12,19 @@ uadalp z0.h, p0/m, z1.b // CHECK-INST: uadalp z0.h, p0/m, z1.b // CHECK-ENCODING: [0x20,0xa0,0x45,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 45 44 uadalp z29.s, p0/m, z30.h // CHECK-INST: uadalp z29.s, p0/m, z30.h // CHECK-ENCODING: [0xdd,0xa3,0x85,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd a3 85 44 uadalp z30.d, p7/m, z31.s // CHECK-INST: uadalp z30.d, p7/m, z31.s // CHECK-ENCODING: [0xfe,0xbf,0xc5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: fe bf c5 44 // --------------------------------------------------------------------------// @@ -33,23 +33,23 @@ uadalp z30.d, p7/m, z31.s movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uadalp z31.d, p0/m, z30.s // CHECK-INST: uadalp z31.d, p0/m, z30.s // CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 c5 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uadalp z31.d, p0/m, z30.s // CHECK-INST: uadalp z31.d, p0/m, z30.s // CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 c5 44 diff --git a/llvm/test/MC/AArch64/SVE2/uaddlb.s b/llvm/test/MC/AArch64/SVE2/uaddlb.s index aba06d215b55d..9f44ab38e99cc 100644 --- a/llvm/test/MC/AArch64/SVE2/uaddlb.s +++ b/llvm/test/MC/AArch64/SVE2/uaddlb.s @@ -13,17 +13,17 @@ uaddlb z0.h, z1.b, z2.b // CHECK-INST: uaddlb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x08,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 08 42 45 uaddlb z29.s, z30.h, z31.h // CHECK-INST: uaddlb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x0b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 0b 9f 45 uaddlb z31.d, z31.s, z31.s // CHECK-INST: uaddlb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x0b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uaddlt.s b/llvm/test/MC/AArch64/SVE2/uaddlt.s index 458c33d1564c2..19626f08aae64 100644 --- a/llvm/test/MC/AArch64/SVE2/uaddlt.s +++ b/llvm/test/MC/AArch64/SVE2/uaddlt.s @@ -13,17 +13,17 @@ uaddlt z0.h, z1.b, z2.b // CHECK-INST: uaddlt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x0c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 0c 42 45 uaddlt z29.s, z30.h, z31.h // CHECK-INST: uaddlt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x0f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 0f 9f 45 uaddlt z31.d, z31.s, z31.s // CHECK-INST: uaddlt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x0f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uaddwb.s b/llvm/test/MC/AArch64/SVE2/uaddwb.s index 84a8b876245e1..ce7395152ddd3 100644 --- a/llvm/test/MC/AArch64/SVE2/uaddwb.s +++ b/llvm/test/MC/AArch64/SVE2/uaddwb.s @@ -13,17 +13,17 @@ uaddwb z0.h, z1.h, z2.b // CHECK-INST: uaddwb z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x48,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 48 42 45 uaddwb z29.s, z30.s, z31.h // CHECK-INST: uaddwb z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x4b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 4b 9f 45 uaddwb z31.d, z31.d, z31.s // CHECK-INST: uaddwb z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x4b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 4b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uaddwt.s b/llvm/test/MC/AArch64/SVE2/uaddwt.s index 83421f2e3fea7..7adab15d8a14d 100644 --- a/llvm/test/MC/AArch64/SVE2/uaddwt.s +++ b/llvm/test/MC/AArch64/SVE2/uaddwt.s @@ -13,17 +13,17 @@ uaddwt z0.h, z1.h, z2.b // CHECK-INST: uaddwt z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x4c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 4c 42 45 uaddwt z29.s, z30.s, z31.h // CHECK-INST: uaddwt z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x4f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 4f 9f 45 uaddwt z31.d, z31.d, z31.s // CHECK-INST: uaddwt z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x4f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 4f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/uhadd.s b/llvm/test/MC/AArch64/SVE2/uhadd.s index 3642a704b247f..5fbffc13f4cd7 100644 --- a/llvm/test/MC/AArch64/SVE2/uhadd.s +++ b/llvm/test/MC/AArch64/SVE2/uhadd.s @@ -12,25 +12,25 @@ uhadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x11,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 11 44 uhadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x51,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 51 44 uhadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x91,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 91 44 uhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d1 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uhadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uhadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d1 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d1 44 diff --git a/llvm/test/MC/AArch64/SVE2/uhsub.s b/llvm/test/MC/AArch64/SVE2/uhsub.s index c26ba6a31b6ec..1a12620c940f8 100644 --- a/llvm/test/MC/AArch64/SVE2/uhsub.s +++ b/llvm/test/MC/AArch64/SVE2/uhsub.s @@ -12,25 +12,25 @@ uhsub z0.b, p0/m, z0.b, z1.b // CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x13,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 13 44 uhsub z0.h, p0/m, z0.h, z1.h // CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x53,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 53 44 uhsub z29.s, p7/m, z29.s, z30.s // CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x93,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 93 44 uhsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d3 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uhsub z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uhsub z31.d, p0/m, z31.d, z30.d // CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d3 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uhsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d3 44 diff --git a/llvm/test/MC/AArch64/SVE2/uhsubr.s b/llvm/test/MC/AArch64/SVE2/uhsubr.s index 227e8bed66aa6..d8eeb4124527b 100644 --- a/llvm/test/MC/AArch64/SVE2/uhsubr.s +++ b/llvm/test/MC/AArch64/SVE2/uhsubr.s @@ -12,25 +12,25 @@ uhsubr z0.b, p0/m, z0.b, z1.b // CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x17,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 17 44 uhsubr z0.h, p0/m, z0.h, z1.h // CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x57,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 57 44 uhsubr z29.s, p7/m, z29.s, z30.s // CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x97,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 97 44 uhsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d7 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uhsubr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uhsubr z31.d, p0/m, z31.d, z30.d // CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d7 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uhsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d7 44 diff --git a/llvm/test/MC/AArch64/SVE2/umaxp.s b/llvm/test/MC/AArch64/SVE2/umaxp.s index d88801f87fd80..65e9555a6e02a 100644 --- a/llvm/test/MC/AArch64/SVE2/umaxp.s +++ b/llvm/test/MC/AArch64/SVE2/umaxp.s @@ -12,25 +12,25 @@ umaxp z0.b, p0/m, z0.b, z1.b // CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0xa0,0x15,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 15 44 umaxp z0.h, p0/m, z0.h, z1.h // CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0xa0,0x55,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 55 44 umaxp z29.s, p7/m, z29.s, z30.s // CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0xbf,0x95,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd bf 95 44 umaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d5 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ umaxp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 umaxp z31.d, p0/m, z31.d, z30.d // CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 d5 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 umaxp z31.d, p7/m, z31.d, z30.d // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d5 44 diff --git a/llvm/test/MC/AArch64/SVE2/uminp.s b/llvm/test/MC/AArch64/SVE2/uminp.s index 056338cef3ccb..3b9033f4758cc 100644 --- a/llvm/test/MC/AArch64/SVE2/uminp.s +++ b/llvm/test/MC/AArch64/SVE2/uminp.s @@ -12,25 +12,25 @@ uminp z0.b, p0/m, z0.b, z1.b // CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0xa0,0x17,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 17 44 uminp z0.h, p0/m, z0.h, z1.h // CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0xa0,0x57,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 a0 57 44 uminp z29.s, p7/m, z29.s, z30.s // CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0xbf,0x97,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd bf 97 44 uminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d7 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uminp z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uminp z31.d, p0/m, z31.d, z30.d // CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df a3 d7 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uminp z31.d, p7/m, z31.d, z30.d // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df bf d7 44 diff --git a/llvm/test/MC/AArch64/SVE2/umlalb.s b/llvm/test/MC/AArch64/SVE2/umlalb.s index a302be198d2b3..82660736b385e 100644 --- a/llvm/test/MC/AArch64/SVE2/umlalb.s +++ b/llvm/test/MC/AArch64/SVE2/umlalb.s @@ -13,31 +13,31 @@ umlalb z0.h, z1.b, z31.b // CHECK-INST: umlalb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x48,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 48 5f 44 umlalb z0.s, z1.h, z31.h // CHECK-INST: umlalb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x48,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 48 9f 44 umlalb z0.d, z1.s, z31.s // CHECK-INST: umlalb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x48,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 48 df 44 umlalb z0.s, z1.h, z7.h[7] // CHECK-INST: umlalb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x98,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 98 bf 44 umlalb z0.d, z1.s, z15.s[1] // CHECK-INST: umlalb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0x98,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 98 ef 44 @@ -47,23 +47,23 @@ umlalb z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlalb z21.d, z1.s, z31.s // CHECK-INST: umlalb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x48,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 48 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlalb z21.d, z10.s, z5.s[1] // CHECK-INST: umlalb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x99,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 99 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/umlalt.s b/llvm/test/MC/AArch64/SVE2/umlalt.s index 3aa8183fc975e..4077df70545f5 100644 --- a/llvm/test/MC/AArch64/SVE2/umlalt.s +++ b/llvm/test/MC/AArch64/SVE2/umlalt.s @@ -13,31 +13,31 @@ umlalt z0.h, z1.b, z31.b // CHECK-INST: umlalt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x4c,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 4c 5f 44 umlalt z0.s, z1.h, z31.h // CHECK-INST: umlalt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x4c,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 4c 9f 44 umlalt z0.d, z1.s, z31.s // CHECK-INST: umlalt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x4c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 4c df 44 umlalt z0.s, z1.h, z7.h[7] // CHECK-INST: umlalt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0x9c,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 9c bf 44 umlalt z0.d, z1.s, z15.s[1] // CHECK-INST: umlalt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0x9c,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 9c ef 44 @@ -47,23 +47,23 @@ umlalt z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlalt z21.d, z1.s, z31.s // CHECK-INST: umlalt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x4c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 4c df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlalt z21.d, z10.s, z5.s[1] // CHECK-INST: umlalt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0x9d,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 9d e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/umlslb.s b/llvm/test/MC/AArch64/SVE2/umlslb.s index 05b03ed461f2d..9dd1f977bb50d 100644 --- a/llvm/test/MC/AArch64/SVE2/umlslb.s +++ b/llvm/test/MC/AArch64/SVE2/umlslb.s @@ -13,31 +13,31 @@ umlslb z0.h, z1.b, z31.b // CHECK-INST: umlslb z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x58,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 58 5f 44 umlslb z0.s, z1.h, z31.h // CHECK-INST: umlslb z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x58,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 58 9f 44 umlslb z0.d, z1.s, z31.s // CHECK-INST: umlslb z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x58,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 58 df 44 umlslb z0.s, z1.h, z7.h[7] // CHECK-INST: umlslb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xb8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 b8 bf 44 umlslb z0.d, z1.s, z15.s[1] // CHECK-INST: umlslb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xb8,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 b8 ef 44 @@ -47,23 +47,23 @@ umlslb z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlslb z21.d, z1.s, z31.s // CHECK-INST: umlslb z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x58,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 58 df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlslb z21.d, z10.s, z5.s[1] // CHECK-INST: umlslb z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0xb9,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 b9 e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/umlslt.s b/llvm/test/MC/AArch64/SVE2/umlslt.s index f0e50a0691c28..3f8de7dff2cad 100644 --- a/llvm/test/MC/AArch64/SVE2/umlslt.s +++ b/llvm/test/MC/AArch64/SVE2/umlslt.s @@ -13,31 +13,31 @@ umlslt z0.h, z1.b, z31.b // CHECK-INST: umlslt z0.h, z1.b, z31.b // CHECK-ENCODING: [0x20,0x5c,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 5c 5f 44 umlslt z0.s, z1.h, z31.h // CHECK-INST: umlslt z0.s, z1.h, z31.h // CHECK-ENCODING: [0x20,0x5c,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 5c 9f 44 umlslt z0.d, z1.s, z31.s // CHECK-INST: umlslt z0.d, z1.s, z31.s // CHECK-ENCODING: [0x20,0x5c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 5c df 44 umlslt z0.s, z1.h, z7.h[7] // CHECK-INST: umlslt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xbc,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 bc bf 44 umlslt z0.d, z1.s, z15.s[1] // CHECK-INST: umlslt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xbc,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 bc ef 44 @@ -47,23 +47,23 @@ umlslt z0.d, z1.s, z15.s[1] movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlslt z21.d, z1.s, z31.s // CHECK-INST: umlslt z21.d, z1.s, z31.s // CHECK-ENCODING: [0x35,0x5c,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 35 5c df 44 movprfx z21, z28 // CHECK-INST: movprfx z21, z28 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 95 bf 20 04 umlslt z21.d, z10.s, z5.s[1] // CHECK-INST: umlslt z21.d, z10.s, z5.s[1] // CHECK-ENCODING: [0x55,0xbd,0xe5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 55 bd e5 44 diff --git a/llvm/test/MC/AArch64/SVE2/umulh.s b/llvm/test/MC/AArch64/SVE2/umulh.s index 58dde1dff0f0c..749c27571efa1 100644 --- a/llvm/test/MC/AArch64/SVE2/umulh.s +++ b/llvm/test/MC/AArch64/SVE2/umulh.s @@ -12,23 +12,23 @@ umulh z0.b, z1.b, z2.b // CHECK-INST: umulh z0.b, z1.b, z2.b // CHECK-ENCODING: [0x20,0x6c,0x22,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 22 04 umulh z0.h, z1.h, z2.h // CHECK-INST: umulh z0.h, z1.h, z2.h // CHECK-ENCODING: [0x20,0x6c,0x62,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 6c 62 04 umulh z29.s, z30.s, z31.s // CHECK-INST: umulh z29.s, z30.s, z31.s // CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 6f bf 04 umulh z31.d, z31.d, z31.d // CHECK-INST: umulh z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x6f,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 6f ff 04 diff --git a/llvm/test/MC/AArch64/SVE2/umullb.s b/llvm/test/MC/AArch64/SVE2/umullb.s index d8a98e2c1bfbb..37cd499cd2e1b 100644 --- a/llvm/test/MC/AArch64/SVE2/umullb.s +++ b/llvm/test/MC/AArch64/SVE2/umullb.s @@ -13,29 +13,29 @@ umullb z0.h, z1.b, z2.b // CHECK-INST: umullb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x78,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 78 42 45 umullb z29.s, z30.h, z31.h // CHECK-INST: umullb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x7b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 7b 9f 45 umullb z31.d, z31.s, z31.s // CHECK-INST: umullb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x7b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 7b df 45 umullb z0.s, z1.h, z7.h[7] // CHECK-INST: umullb z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xd8,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d8 bf 44 umullb z0.d, z1.s, z15.s[1] // CHECK-INST: umullb z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xd8,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 d8 ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/umullt.s b/llvm/test/MC/AArch64/SVE2/umullt.s index 2bd8d6f80c44c..3acaaae293e54 100644 --- a/llvm/test/MC/AArch64/SVE2/umullt.s +++ b/llvm/test/MC/AArch64/SVE2/umullt.s @@ -13,29 +13,29 @@ umullt z0.h, z1.b, z2.b // CHECK-INST: umullt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x7c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 7c 42 45 umullt z29.s, z30.h, z31.h // CHECK-INST: umullt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x7f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 7f 9f 45 umullt z31.d, z31.s, z31.s // CHECK-INST: umullt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x7f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 7f df 45 umullt z0.s, z1.h, z7.h[7] // CHECK-INST: umullt z0.s, z1.h, z7.h[7] // CHECK-ENCODING: [0x20,0xdc,0xbf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 dc bf 44 umullt z0.d, z1.s, z15.s[1] // CHECK-INST: umullt z0.d, z1.s, z15.s[1] // CHECK-ENCODING: [0x20,0xdc,0xef,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 dc ef 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqadd.s b/llvm/test/MC/AArch64/SVE2/uqadd.s index 19a935611487b..be127c4333395 100644 --- a/llvm/test/MC/AArch64/SVE2/uqadd.s +++ b/llvm/test/MC/AArch64/SVE2/uqadd.s @@ -12,25 +12,25 @@ uqadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x19,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 19 44 uqadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x59,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 59 44 uqadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x99,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 99 44 uqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d9 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d9 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d9 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshl.s b/llvm/test/MC/AArch64/SVE2/uqrshl.s index e424a354ce324..d25e6d80779a4 100644 --- a/llvm/test/MC/AArch64/SVE2/uqrshl.s +++ b/llvm/test/MC/AArch64/SVE2/uqrshl.s @@ -12,25 +12,25 @@ uqrshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqrshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0b 44 uqrshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqrshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4b 44 uqrshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqrshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8b 44 uqrshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cb 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqrshl z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqrshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqrshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xcb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 cb 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqrshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cb 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshlr.s b/llvm/test/MC/AArch64/SVE2/uqrshlr.s index 0f9159cc4abac..68aee0cafdb6d 100644 --- a/llvm/test/MC/AArch64/SVE2/uqrshlr.s +++ b/llvm/test/MC/AArch64/SVE2/uqrshlr.s @@ -12,25 +12,25 @@ uqrshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqrshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0f 44 uqrshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqrshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4f 44 uqrshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqrshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8f 44 uqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cf 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqrshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqrshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqrshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xcf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 cf 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cf 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s index d6935f9d8d0a7..7da923d55b0af 100644 --- a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s +++ b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s @@ -12,35 +12,35 @@ uqrshrnb z0.b, z0.h, #1 // CHECK-INST: uqrshrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x38,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 38 2f 45 uqrshrnb z31.b, z31.h, #8 // CHECK-INST: uqrshrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x3b,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 28 45 uqrshrnb z0.h, z0.s, #1 // CHECK-INST: uqrshrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x38,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 38 3f 45 uqrshrnb z31.h, z31.s, #16 // CHECK-INST: uqrshrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x3b,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 30 45 uqrshrnb z0.s, z0.d, #1 // CHECK-INST: uqrshrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x38,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 38 7f 45 uqrshrnb z31.s, z31.d, #32 // CHECK-INST: uqrshrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x3b,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3b 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s index 2232881bb9918..ce831f5f26cce 100644 --- a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s +++ b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s @@ -12,35 +12,35 @@ uqrshrnt z0.b, z0.h, #1 // CHECK-INST: uqrshrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x3c,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 3c 2f 45 uqrshrnt z31.b, z31.h, #8 // CHECK-INST: uqrshrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x3f,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3f 28 45 uqrshrnt z0.h, z0.s, #1 // CHECK-INST: uqrshrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x3c,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 3c 3f 45 uqrshrnt z31.h, z31.s, #16 // CHECK-INST: uqrshrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x3f,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3f 30 45 uqrshrnt z0.s, z0.d, #1 // CHECK-INST: uqrshrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x3c,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 3c 7f 45 uqrshrnt z31.s, z31.d, #32 // CHECK-INST: uqrshrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x3f,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 3f 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/uqshl.s b/llvm/test/MC/AArch64/SVE2/uqshl.s index 93d93abb67618..fbe8501651d15 100644 --- a/llvm/test/MC/AArch64/SVE2/uqshl.s +++ b/llvm/test/MC/AArch64/SVE2/uqshl.s @@ -12,73 +12,73 @@ uqshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x09,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 09 44 uqshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x49,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 49 44 uqshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x89,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 89 44 uqshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c9 44 uqshl z0.b, p0/m, z0.b, #0 // CHECK-INST: uqshl z0.b, p0/m, z0.b, #0 // CHECK-ENCODING: [0x00,0x81,0x07,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 81 07 04 uqshl z31.b, p0/m, z31.b, #7 // CHECK-INST: uqshl z31.b, p0/m, z31.b, #7 // CHECK-ENCODING: [0xff,0x81,0x07,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 81 07 04 uqshl z0.h, p0/m, z0.h, #0 // CHECK-INST: uqshl z0.h, p0/m, z0.h, #0 // CHECK-ENCODING: [0x00,0x82,0x07,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 82 07 04 uqshl z31.h, p0/m, z31.h, #15 // CHECK-INST: uqshl z31.h, p0/m, z31.h, #15 // CHECK-ENCODING: [0xff,0x83,0x07,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 07 04 uqshl z0.s, p0/m, z0.s, #0 // CHECK-INST: uqshl z0.s, p0/m, z0.s, #0 // CHECK-ENCODING: [0x00,0x80,0x47,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 47 04 uqshl z31.s, p0/m, z31.s, #31 // CHECK-INST: uqshl z31.s, p0/m, z31.s, #31 // CHECK-ENCODING: [0xff,0x83,0x47,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 47 04 uqshl z0.d, p0/m, z0.d, #0 // CHECK-INST: uqshl z0.d, p0/m, z0.d, #0 // CHECK-ENCODING: [0x00,0x80,0x87,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 80 87 04 uqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c7 04 // --------------------------------------------------------------------------// @@ -87,47 +87,47 @@ uqshl z31.d, p0/m, z31.d, #63 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c9 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c9 44 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c7 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqshl z31.d, p0/m, z31.d, #63 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 83 c7 04 diff --git a/llvm/test/MC/AArch64/SVE2/uqshlr.s b/llvm/test/MC/AArch64/SVE2/uqshlr.s index 13c374b5a6ff1..1d41a4beb51d3 100644 --- a/llvm/test/MC/AArch64/SVE2/uqshlr.s +++ b/llvm/test/MC/AArch64/SVE2/uqshlr.s @@ -12,25 +12,25 @@ uqshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x0d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 0d 44 uqshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x4d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 4d 44 uqshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x8d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 8d 44 uqshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cd 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xcd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 cd 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f cd 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqshrnb.s b/llvm/test/MC/AArch64/SVE2/uqshrnb.s index 35e13254eb5f8..23a0e30803f36 100644 --- a/llvm/test/MC/AArch64/SVE2/uqshrnb.s +++ b/llvm/test/MC/AArch64/SVE2/uqshrnb.s @@ -12,35 +12,35 @@ uqshrnb z0.b, z0.h, #1 // CHECK-INST: uqshrnb z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x30,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 30 2f 45 uqshrnb z31.b, z31.h, #8 // CHECK-INST: uqshrnb z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x33,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 33 28 45 uqshrnb z0.h, z0.s, #1 // CHECK-INST: uqshrnb z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x30,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 30 3f 45 uqshrnb z31.h, z31.s, #16 // CHECK-INST: uqshrnb z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x33,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 33 30 45 uqshrnb z0.s, z0.d, #1 // CHECK-INST: uqshrnb z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x30,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 30 7f 45 uqshrnb z31.s, z31.d, #32 // CHECK-INST: uqshrnb z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x33,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 33 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/uqshrnt.s b/llvm/test/MC/AArch64/SVE2/uqshrnt.s index d8bfd2bebe43d..d3a0ffab3cfe3 100644 --- a/llvm/test/MC/AArch64/SVE2/uqshrnt.s +++ b/llvm/test/MC/AArch64/SVE2/uqshrnt.s @@ -12,35 +12,35 @@ uqshrnt z0.b, z0.h, #1 // CHECK-INST: uqshrnt z0.b, z0.h, #1 // CHECK-ENCODING: [0x00,0x34,0x2f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 34 2f 45 uqshrnt z31.b, z31.h, #8 // CHECK-INST: uqshrnt z31.b, z31.h, #8 // CHECK-ENCODING: [0xff,0x37,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 37 28 45 uqshrnt z0.h, z0.s, #1 // CHECK-INST: uqshrnt z0.h, z0.s, #1 // CHECK-ENCODING: [0x00,0x34,0x3f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 34 3f 45 uqshrnt z31.h, z31.s, #16 // CHECK-INST: uqshrnt z31.h, z31.s, #16 // CHECK-ENCODING: [0xff,0x37,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 37 30 45 uqshrnt z0.s, z0.d, #1 // CHECK-INST: uqshrnt z0.s, z0.d, #1 // CHECK-ENCODING: [0x00,0x34,0x7f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 34 7f 45 uqshrnt z31.s, z31.d, #32 // CHECK-INST: uqshrnt z31.s, z31.d, #32 // CHECK-ENCODING: [0xff,0x37,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 37 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/uqsub.s b/llvm/test/MC/AArch64/SVE2/uqsub.s index f9ed9e4c3ff1e..ecb108acb69f8 100644 --- a/llvm/test/MC/AArch64/SVE2/uqsub.s +++ b/llvm/test/MC/AArch64/SVE2/uqsub.s @@ -12,25 +12,25 @@ uqsub z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqsub z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1b 44 uqsub z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqsub z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5b 44 uqsub z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqsub z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9b,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9b 44 uqsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f db 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqsub z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqsub z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqsub z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xdb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 db 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqsub z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f db 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqsubr.s b/llvm/test/MC/AArch64/SVE2/uqsubr.s index 85597559c9862..ede46a645ad57 100644 --- a/llvm/test/MC/AArch64/SVE2/uqsubr.s +++ b/llvm/test/MC/AArch64/SVE2/uqsubr.s @@ -12,25 +12,25 @@ uqsubr z0.b, p0/m, z0.b, z1.b // CHECK-INST: uqsubr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1f 44 uqsubr z0.h, p0/m, z0.h, z1.h // CHECK-INST: uqsubr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5f 44 uqsubr z29.s, p7/m, z29.s, z30.s // CHECK-INST: uqsubr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9f,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9f 44 uqsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f df 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ uqsubr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 uqsubr z31.d, p0/m, z31.d, z30.d // CHECK-INST: uqsubr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 df 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 uqsubr z31.d, p7/m, z31.d, z30.d // CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f df 44 diff --git a/llvm/test/MC/AArch64/SVE2/uqxtnb.s b/llvm/test/MC/AArch64/SVE2/uqxtnb.s index 4e1f68d1c2348..9dea65c2d2e6c 100644 --- a/llvm/test/MC/AArch64/SVE2/uqxtnb.s +++ b/llvm/test/MC/AArch64/SVE2/uqxtnb.s @@ -13,17 +13,17 @@ uqxtnb z0.b, z31.h // CHECK-INST: uqxtnb z0.b, z31.h // CHECK-ENCODING: [0xe0,0x4b,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4b 28 45 uqxtnb z0.h, z31.s // CHECK-INST: uqxtnb z0.h, z31.s // CHECK-ENCODING: [0xe0,0x4b,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4b 30 45 uqxtnb z0.s, z31.d // CHECK-INST: uqxtnb z0.s, z31.d // CHECK-ENCODING: [0xe0,0x4b,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4b 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/uqxtnt.s b/llvm/test/MC/AArch64/SVE2/uqxtnt.s index cde4f590f5d99..c12405805f888 100644 --- a/llvm/test/MC/AArch64/SVE2/uqxtnt.s +++ b/llvm/test/MC/AArch64/SVE2/uqxtnt.s @@ -13,17 +13,17 @@ uqxtnt z0.b, z31.h // CHECK-INST: uqxtnt z0.b, z31.h // CHECK-ENCODING: [0xe0,0x4f,0x28,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4f 28 45 uqxtnt z0.h, z31.s // CHECK-INST: uqxtnt z0.h, z31.s // CHECK-ENCODING: [0xe0,0x4f,0x30,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4f 30 45 uqxtnt z0.s, z31.d // CHECK-INST: uqxtnt z0.s, z31.d // CHECK-ENCODING: [0xe0,0x4f,0x60,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 4f 60 45 diff --git a/llvm/test/MC/AArch64/SVE2/urecpe.s b/llvm/test/MC/AArch64/SVE2/urecpe.s index 4063f78c7e024..ff91435f60d75 100644 --- a/llvm/test/MC/AArch64/SVE2/urecpe.s +++ b/llvm/test/MC/AArch64/SVE2/urecpe.s @@ -12,7 +12,7 @@ urecpe z31.s, p7/m, z31.s // CHECK-INST: urecpe z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x80,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 80 44 @@ -22,23 +22,23 @@ urecpe z31.s, p7/m, z31.s movprfx z4.s, p7/z, z6.s // CHECK-INST: movprfx z4.s, p7/z, z6.s // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 90 04 urecpe z4.s, p7/m, z31.s // CHECK-INST: urecpe z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x80,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 80 44 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 urecpe z4.s, p7/m, z31.s // CHECK-INST: urecpe z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x80,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 80 44 diff --git a/llvm/test/MC/AArch64/SVE2/urhadd.s b/llvm/test/MC/AArch64/SVE2/urhadd.s index 776717f16f19b..7fc35f598de57 100644 --- a/llvm/test/MC/AArch64/SVE2/urhadd.s +++ b/llvm/test/MC/AArch64/SVE2/urhadd.s @@ -12,25 +12,25 @@ urhadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x15,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 15 44 urhadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x55,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 55 44 urhadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x95,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 95 44 urhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d5 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ urhadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 urhadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 d5 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 urhadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f d5 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshl.s b/llvm/test/MC/AArch64/SVE2/urshl.s index 068534e924383..fd425df9533bd 100644 --- a/llvm/test/MC/AArch64/SVE2/urshl.s +++ b/llvm/test/MC/AArch64/SVE2/urshl.s @@ -12,25 +12,25 @@ urshl z0.b, p0/m, z0.b, z1.b // CHECK-INST: urshl z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x03,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 03 44 urshl z0.h, p0/m, z0.h, z1.h // CHECK-INST: urshl z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x43,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 43 44 urshl z29.s, p7/m, z29.s, z30.s // CHECK-INST: urshl z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x83,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 83 44 urshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c3 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ urshl z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 urshl z31.d, p0/m, z31.d, z30.d // CHECK-INST: urshl z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c3 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 urshl z31.d, p7/m, z31.d, z30.d // CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c3 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshlr.s b/llvm/test/MC/AArch64/SVE2/urshlr.s index 0b5facea1b786..fee2aaf4c4fdd 100644 --- a/llvm/test/MC/AArch64/SVE2/urshlr.s +++ b/llvm/test/MC/AArch64/SVE2/urshlr.s @@ -12,25 +12,25 @@ urshlr z0.b, p0/m, z0.b, z1.b // CHECK-INST: urshlr z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x07,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 07 44 urshlr z0.h, p0/m, z0.h, z1.h // CHECK-INST: urshlr z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x47,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 47 44 urshlr z29.s, p7/m, z29.s, z30.s // CHECK-INST: urshlr z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x87,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 87 44 urshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c7 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ urshlr z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 urshlr z31.d, p0/m, z31.d, z30.d // CHECK-INST: urshlr z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xc7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 c7 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 urshlr z31.d, p7/m, z31.d, z30.d // CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f c7 44 diff --git a/llvm/test/MC/AArch64/SVE2/urshr.s b/llvm/test/MC/AArch64/SVE2/urshr.s index 4e0b8b0436b59..f2e95b9800238 100644 --- a/llvm/test/MC/AArch64/SVE2/urshr.s +++ b/llvm/test/MC/AArch64/SVE2/urshr.s @@ -12,49 +12,49 @@ urshr z0.b, p0/m, z0.b, #1 // CHECK-INST: urshr z0.b, p0/m, z0.b, #1 // CHECK-ENCODING: [0xe0,0x81,0x0d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 81 0d 04 urshr z31.b, p0/m, z31.b, #8 // CHECK-INST: urshr z31.b, p0/m, z31.b, #8 // CHECK-ENCODING: [0x1f,0x81,0x0d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 81 0d 04 urshr z0.h, p0/m, z0.h, #1 // CHECK-INST: urshr z0.h, p0/m, z0.h, #1 // CHECK-ENCODING: [0xe0,0x83,0x0d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 0d 04 urshr z31.h, p0/m, z31.h, #16 // CHECK-INST: urshr z31.h, p0/m, z31.h, #16 // CHECK-ENCODING: [0x1f,0x82,0x0d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 82 0d 04 urshr z0.s, p0/m, z0.s, #1 // CHECK-INST: urshr z0.s, p0/m, z0.s, #1 // CHECK-ENCODING: [0xe0,0x83,0x4d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 4d 04 urshr z31.s, p0/m, z31.s, #32 // CHECK-INST: urshr z31.s, p0/m, z31.s, #32 // CHECK-ENCODING: [0x1f,0x80,0x4d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 4d 04 urshr z0.d, p0/m, z0.d, #1 // CHECK-INST: urshr z0.d, p0/m, z0.d, #1 // CHECK-ENCODING: [0xe0,0x83,0xcd,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e0 83 cd 04 urshr z31.d, p0/m, z31.d, #64 // CHECK-INST: urshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8d 04 @@ -64,23 +64,23 @@ urshr z31.d, p0/m, z31.d, #64 movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 urshr z31.d, p0/m, z31.d, #64 // CHECK-INST: urshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8d 04 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 urshr z31.d, p0/m, z31.d, #64 // CHECK-INST: urshr z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 80 8d 04 diff --git a/llvm/test/MC/AArch64/SVE2/ursqrte.s b/llvm/test/MC/AArch64/SVE2/ursqrte.s index 981cd6a511ef9..ac66a15ab566e 100644 --- a/llvm/test/MC/AArch64/SVE2/ursqrte.s +++ b/llvm/test/MC/AArch64/SVE2/ursqrte.s @@ -12,7 +12,7 @@ ursqrte z31.s, p7/m, z31.s // CHECK-INST: ursqrte z31.s, p7/m, z31.s // CHECK-ENCODING: [0xff,0xbf,0x81,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff bf 81 44 @@ -22,23 +22,23 @@ ursqrte z31.s, p7/m, z31.s movprfx z4.s, p7/z, z6.s // CHECK-INST: movprfx z4.s, p7/z, z6.s // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 3c 90 04 ursqrte z4.s, p7/m, z31.s // CHECK-INST: ursqrte z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x81,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 81 44 movprfx z4, z6 // CHECK-INST: movprfx z4, z6 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: c4 bc 20 04 ursqrte z4.s, p7/m, z31.s // CHECK-INST: ursqrte z4.s, p7/m, z31.s // CHECK-ENCODING: [0xe4,0xbf,0x81,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: e4 bf 81 44 diff --git a/llvm/test/MC/AArch64/SVE2/ursra.s b/llvm/test/MC/AArch64/SVE2/ursra.s index d2509e1a63b29..005e5511e7087 100644 --- a/llvm/test/MC/AArch64/SVE2/ursra.s +++ b/llvm/test/MC/AArch64/SVE2/ursra.s @@ -12,49 +12,49 @@ ursra z0.b, z0.b, #1 // CHECK-INST: ursra z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0xec,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ec 0f 45 ursra z31.b, z31.b, #8 // CHECK-INST: ursra z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0xef,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ef 08 45 ursra z0.h, z0.h, #1 // CHECK-INST: ursra z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0xec,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ec 1f 45 ursra z31.h, z31.h, #16 // CHECK-INST: ursra z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0xef,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ef 10 45 ursra z0.s, z0.s, #1 // CHECK-INST: ursra z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0xec,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ec 5f 45 ursra z31.s, z31.s, #32 // CHECK-INST: ursra z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0xef,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ef 40 45 ursra z0.d, z0.d, #1 // CHECK-INST: ursra z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0xec,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ec df 45 ursra z31.d, z31.d, #64 // CHECK-INST: ursra z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0xef,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ef 80 45 @@ -64,11 +64,11 @@ ursra z31.d, z31.d, #64 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 ursra z0.d, z1.d, #1 // CHECK-INST: ursra z0.d, z1.d, #1 // CHECK-ENCODING: [0x20,0xec,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 ec df 45 diff --git a/llvm/test/MC/AArch64/SVE2/ushllb.s b/llvm/test/MC/AArch64/SVE2/ushllb.s index 04bf78a7f8af1..ea1d85052f42d 100644 --- a/llvm/test/MC/AArch64/SVE2/ushllb.s +++ b/llvm/test/MC/AArch64/SVE2/ushllb.s @@ -12,35 +12,35 @@ ushllb z0.h, z0.b, #0 // CHECK-INST: ushllb z0.h, z0.b, #0 // CHECK-ENCODING: [0x00,0xa8,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a8 08 45 ushllb z31.h, z31.b, #7 // CHECK-INST: ushllb z31.h, z31.b, #7 // CHECK-ENCODING: [0xff,0xab,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ab 0f 45 ushllb z0.s, z0.h, #0 // CHECK-INST: ushllb z0.s, z0.h, #0 // CHECK-ENCODING: [0x00,0xa8,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a8 10 45 ushllb z31.s, z31.h, #15 // CHECK-INST: ushllb z31.s, z31.h, #15 // CHECK-ENCODING: [0xff,0xab,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ab 1f 45 ushllb z0.d, z0.s, #0 // CHECK-INST: ushllb z0.d, z0.s, #0 // CHECK-ENCODING: [0x00,0xa8,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 a8 40 45 ushllb z31.d, z31.s, #31 // CHECK-INST: ushllb z31.d, z31.s, #31 // CHECK-ENCODING: [0xff,0xab,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff ab 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/ushllt.s b/llvm/test/MC/AArch64/SVE2/ushllt.s index 1261942d0f6ca..c4f351fb72429 100644 --- a/llvm/test/MC/AArch64/SVE2/ushllt.s +++ b/llvm/test/MC/AArch64/SVE2/ushllt.s @@ -12,35 +12,35 @@ ushllt z0.h, z0.b, #0 // CHECK-INST: ushllt z0.h, z0.b, #0 // CHECK-ENCODING: [0x00,0xac,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ac 08 45 ushllt z31.h, z31.b, #7 // CHECK-INST: ushllt z31.h, z31.b, #7 // CHECK-ENCODING: [0xff,0xaf,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff af 0f 45 ushllt z0.s, z0.h, #0 // CHECK-INST: ushllt z0.s, z0.h, #0 // CHECK-ENCODING: [0x00,0xac,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ac 10 45 ushllt z31.s, z31.h, #15 // CHECK-INST: ushllt z31.s, z31.h, #15 // CHECK-ENCODING: [0xff,0xaf,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff af 1f 45 ushllt z0.d, z0.s, #0 // CHECK-INST: ushllt z0.d, z0.s, #0 // CHECK-ENCODING: [0x00,0xac,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 ac 40 45 ushllt z31.d, z31.s, #31 // CHECK-INST: ushllt z31.d, z31.s, #31 // CHECK-ENCODING: [0xff,0xaf,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff af 5f 45 diff --git a/llvm/test/MC/AArch64/SVE2/usqadd.s b/llvm/test/MC/AArch64/SVE2/usqadd.s index 3d16be59673c8..4fa372118547d 100644 --- a/llvm/test/MC/AArch64/SVE2/usqadd.s +++ b/llvm/test/MC/AArch64/SVE2/usqadd.s @@ -12,25 +12,25 @@ usqadd z0.b, p0/m, z0.b, z1.b // CHECK-INST: usqadd z0.b, p0/m, z0.b, z1.b // CHECK-ENCODING: [0x20,0x80,0x1d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 1d 44 usqadd z0.h, p0/m, z0.h, z1.h // CHECK-INST: usqadd z0.h, p0/m, z0.h, z1.h // CHECK-ENCODING: [0x20,0x80,0x5d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 80 5d 44 usqadd z29.s, p7/m, z29.s, z30.s // CHECK-INST: usqadd z29.s, p7/m, z29.s, z30.s // CHECK-ENCODING: [0xdd,0x9f,0x9d,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 9f 9d 44 usqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f dd 44 // --------------------------------------------------------------------------// @@ -39,23 +39,23 @@ usqadd z31.d, p7/m, z31.d, z30.d movprfx z31.d, p0/z, z6.d // CHECK-INST: movprfx z31.d, p0/z, z6.d // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df 20 d0 04 usqadd z31.d, p0/m, z31.d, z30.d // CHECK-INST: usqadd z31.d, p0/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x83,0xdd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 83 dd 44 movprfx z31, z6 // CHECK-INST: movprfx z31, z6 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: df bc 20 04 usqadd z31.d, p7/m, z31.d, z30.d // CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d // CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 9f dd 44 diff --git a/llvm/test/MC/AArch64/SVE2/usra.s b/llvm/test/MC/AArch64/SVE2/usra.s index 83cad939b6dc7..51e942a49e09e 100644 --- a/llvm/test/MC/AArch64/SVE2/usra.s +++ b/llvm/test/MC/AArch64/SVE2/usra.s @@ -12,49 +12,49 @@ usra z0.b, z0.b, #1 // CHECK-INST: usra z0.b, z0.b, #1 // CHECK-ENCODING: [0x00,0xe4,0x0f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e4 0f 45 usra z31.b, z31.b, #8 // CHECK-INST: usra z31.b, z31.b, #8 // CHECK-ENCODING: [0xff,0xe7,0x08,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e7 08 45 usra z0.h, z0.h, #1 // CHECK-INST: usra z0.h, z0.h, #1 // CHECK-ENCODING: [0x00,0xe4,0x1f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e4 1f 45 usra z31.h, z31.h, #16 // CHECK-INST: usra z31.h, z31.h, #16 // CHECK-ENCODING: [0xff,0xe7,0x10,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e7 10 45 usra z0.s, z0.s, #1 // CHECK-INST: usra z0.s, z0.s, #1 // CHECK-ENCODING: [0x00,0xe4,0x5f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e4 5f 45 usra z31.s, z31.s, #32 // CHECK-INST: usra z31.s, z31.s, #32 // CHECK-ENCODING: [0xff,0xe7,0x40,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e7 40 45 usra z0.d, z0.d, #1 // CHECK-INST: usra z0.d, z0.d, #1 // CHECK-ENCODING: [0x00,0xe4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 00 e4 df 45 usra z31.d, z31.d, #64 // CHECK-INST: usra z31.d, z31.d, #64 // CHECK-ENCODING: [0xff,0xe7,0x80,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff e7 80 45 @@ -64,11 +64,11 @@ usra z31.d, z31.d, #64 movprfx z0, z7 // CHECK-INST: movprfx z0, z7 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: e0 bc 20 04 usra z0.d, z1.d, #1 // CHECK-INST: usra z0.d, z1.d, #1 // CHECK-ENCODING: [0x20,0xe4,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 e4 df 45 diff --git a/llvm/test/MC/AArch64/SVE2/usublb.s b/llvm/test/MC/AArch64/SVE2/usublb.s index 7225b6baa1ec5..86ab0485f82ec 100644 --- a/llvm/test/MC/AArch64/SVE2/usublb.s +++ b/llvm/test/MC/AArch64/SVE2/usublb.s @@ -13,17 +13,17 @@ usublb z0.h, z1.b, z2.b // CHECK-INST: usublb z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x18,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 18 42 45 usublb z29.s, z30.h, z31.h // CHECK-INST: usublb z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x1b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 1b 9f 45 usublb z31.d, z31.s, z31.s // CHECK-INST: usublb z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/usublt.s b/llvm/test/MC/AArch64/SVE2/usublt.s index d4000116e59f7..5cc9f7eeb255d 100644 --- a/llvm/test/MC/AArch64/SVE2/usublt.s +++ b/llvm/test/MC/AArch64/SVE2/usublt.s @@ -13,17 +13,17 @@ usublt z0.h, z1.b, z2.b // CHECK-INST: usublt z0.h, z1.b, z2.b // CHECK-ENCODING: [0x20,0x1c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 1c 42 45 usublt z29.s, z30.h, z31.h // CHECK-INST: usublt z29.s, z30.h, z31.h // CHECK-ENCODING: [0xdd,0x1f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 1f 9f 45 usublt z31.d, z31.s, z31.s // CHECK-INST: usublt z31.d, z31.s, z31.s // CHECK-ENCODING: [0xff,0x1f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/usubwb.s b/llvm/test/MC/AArch64/SVE2/usubwb.s index 15764300da959..34ce06e520f0b 100644 --- a/llvm/test/MC/AArch64/SVE2/usubwb.s +++ b/llvm/test/MC/AArch64/SVE2/usubwb.s @@ -13,17 +13,17 @@ usubwb z0.h, z1.h, z2.b // CHECK-INST: usubwb z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x58,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 58 42 45 usubwb z29.s, z30.s, z31.h // CHECK-INST: usubwb z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x5b,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 5b 9f 45 usubwb z31.d, z31.d, z31.s // CHECK-INST: usubwb z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x5b,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 5b df 45 diff --git a/llvm/test/MC/AArch64/SVE2/usubwt.s b/llvm/test/MC/AArch64/SVE2/usubwt.s index 4c3575cd65214..3fa8ef34cab47 100644 --- a/llvm/test/MC/AArch64/SVE2/usubwt.s +++ b/llvm/test/MC/AArch64/SVE2/usubwt.s @@ -13,17 +13,17 @@ usubwt z0.h, z1.h, z2.b // CHECK-INST: usubwt z0.h, z1.h, z2.b // CHECK-ENCODING: [0x20,0x5c,0x42,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 5c 42 45 usubwt z29.s, z30.s, z31.h // CHECK-INST: usubwt z29.s, z30.s, z31.h // CHECK-ENCODING: [0xdd,0x5f,0x9f,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: dd 5f 9f 45 usubwt z31.d, z31.d, z31.s // CHECK-INST: usubwt z31.d, z31.d, z31.s // CHECK-ENCODING: [0xff,0x5f,0xdf,0x45] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 5f df 45 diff --git a/llvm/test/MC/AArch64/SVE2/whilege.s b/llvm/test/MC/AArch64/SVE2/whilege.s index 374987e2d1752..566699a17a2a1 100644 --- a/llvm/test/MC/AArch64/SVE2/whilege.s +++ b/llvm/test/MC/AArch64/SVE2/whilege.s @@ -12,59 +12,59 @@ whilege p15.b, xzr, x0 // CHECK-INST: whilege p15.b, xzr, x0 // CHECK-ENCODING: [0xef,0x13,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ef 13 20 25 whilege p15.b, x0, xzr // CHECK-INST: whilege p15.b, x0, xzr // CHECK-ENCODING: [0x0f,0x10,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 10 3f 25 whilege p15.b, wzr, w0 // CHECK-INST: whilege p15.b, wzr, w0 // CHECK-ENCODING: [0xef,0x03,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ef 03 20 25 whilege p15.b, w0, wzr // CHECK-INST: whilege p15.b, w0, wzr // CHECK-ENCODING: [0x0f,0x00,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 00 3f 25 whilege p15.h, x0, xzr // CHECK-INST: whilege p15.h, x0, xzr // CHECK-ENCODING: [0x0f,0x10,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 10 7f 25 whilege p15.h, w0, wzr // CHECK-INST: whilege p15.h, w0, wzr // CHECK-ENCODING: [0x0f,0x00,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 00 7f 25 whilege p15.s, x0, xzr // CHECK-INST: whilege p15.s, x0, xzr // CHECK-ENCODING: [0x0f,0x10,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 10 bf 25 whilege p15.s, w0, wzr // CHECK-INST: whilege p15.s, w0, wzr // CHECK-ENCODING: [0x0f,0x00,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 00 bf 25 whilege p15.d, w0, wzr // CHECK-INST: whilege p15.d, w0, wzr // CHECK-ENCODING: [0x0f,0x00,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 00 ff 25 whilege p15.d, x0, xzr // CHECK-INST: whilege p15.d, x0, xzr // CHECK-ENCODING: [0x0f,0x10,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 10 ff 25 diff --git a/llvm/test/MC/AArch64/SVE2/whilegt.s b/llvm/test/MC/AArch64/SVE2/whilegt.s index db2bd8cc2596c..4c14d50a40d17 100644 --- a/llvm/test/MC/AArch64/SVE2/whilegt.s +++ b/llvm/test/MC/AArch64/SVE2/whilegt.s @@ -12,59 +12,59 @@ whilegt p15.b, xzr, x0 // CHECK-INST: whilegt p15.b, xzr, x0 // CHECK-ENCODING: [0xff,0x13,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 13 20 25 whilegt p15.b, x0, xzr // CHECK-INST: whilegt p15.b, x0, xzr // CHECK-ENCODING: [0x1f,0x10,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 10 3f 25 whilegt p15.b, wzr, w0 // CHECK-INST: whilegt p15.b, wzr, w0 // CHECK-ENCODING: [0xff,0x03,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 03 20 25 whilegt p15.b, w0, wzr // CHECK-INST: whilegt p15.b, w0, wzr // CHECK-ENCODING: [0x1f,0x00,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 00 3f 25 whilegt p15.h, x0, xzr // CHECK-INST: whilegt p15.h, x0, xzr // CHECK-ENCODING: [0x1f,0x10,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 10 7f 25 whilegt p15.h, w0, wzr // CHECK-INST: whilegt p15.h, w0, wzr // CHECK-ENCODING: [0x1f,0x00,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 00 7f 25 whilegt p15.s, x0, xzr // CHECK-INST: whilegt p15.s, x0, xzr // CHECK-ENCODING: [0x1f,0x10,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 10 bf 25 whilegt p15.s, w0, wzr // CHECK-INST: whilegt p15.s, w0, wzr // CHECK-ENCODING: [0x1f,0x00,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 00 bf 25 whilegt p15.d, w0, wzr // CHECK-INST: whilegt p15.d, w0, wzr // CHECK-ENCODING: [0x1f,0x00,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 00 ff 25 whilegt p15.d, x0, xzr // CHECK-INST: whilegt p15.d, x0, xzr // CHECK-ENCODING: [0x1f,0x10,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 10 ff 25 diff --git a/llvm/test/MC/AArch64/SVE2/whilehi.s b/llvm/test/MC/AArch64/SVE2/whilehi.s index cdb9a048e636c..ae6404e07e53d 100644 --- a/llvm/test/MC/AArch64/SVE2/whilehi.s +++ b/llvm/test/MC/AArch64/SVE2/whilehi.s @@ -12,59 +12,59 @@ whilehi p15.b, xzr, x0 // CHECK-INST: whilehi p15.b, xzr, x0 // CHECK-ENCODING: [0xff,0x1b,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 1b 20 25 whilehi p15.b, x0, xzr // CHECK-INST: whilehi p15.b, x0, xzr // CHECK-ENCODING: [0x1f,0x18,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 18 3f 25 whilehi p15.b, wzr, w0 // CHECK-INST: whilehi p15.b, wzr, w0 // CHECK-ENCODING: [0xff,0x0b,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ff 0b 20 25 whilehi p15.b, w0, wzr // CHECK-INST: whilehi p15.b, w0, wzr // CHECK-ENCODING: [0x1f,0x08,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 08 3f 25 whilehi p15.h, x0, xzr // CHECK-INST: whilehi p15.h, x0, xzr // CHECK-ENCODING: [0x1f,0x18,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 18 7f 25 whilehi p15.h, w0, wzr // CHECK-INST: whilehi p15.h, w0, wzr // CHECK-ENCODING: [0x1f,0x08,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 08 7f 25 whilehi p15.s, x0, xzr // CHECK-INST: whilehi p15.s, x0, xzr // CHECK-ENCODING: [0x1f,0x18,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 18 bf 25 whilehi p15.s, w0, wzr // CHECK-INST: whilehi p15.s, w0, wzr // CHECK-ENCODING: [0x1f,0x08,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 08 bf 25 whilehi p15.d, w0, wzr // CHECK-INST: whilehi p15.d, w0, wzr // CHECK-ENCODING: [0x1f,0x08,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 08 ff 25 whilehi p15.d, x0, xzr // CHECK-INST: whilehi p15.d, x0, xzr // CHECK-ENCODING: [0x1f,0x18,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 1f 18 ff 25 diff --git a/llvm/test/MC/AArch64/SVE2/whilehs.s b/llvm/test/MC/AArch64/SVE2/whilehs.s index 58aa22d331b16..390d61cf79279 100644 --- a/llvm/test/MC/AArch64/SVE2/whilehs.s +++ b/llvm/test/MC/AArch64/SVE2/whilehs.s @@ -12,59 +12,59 @@ whilehs p15.b, xzr, x0 // CHECK-INST: whilehs p15.b, xzr, x0 // CHECK-ENCODING: [0xef,0x1b,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ef 1b 20 25 whilehs p15.b, x0, xzr // CHECK-INST: whilehs p15.b, x0, xzr // CHECK-ENCODING: [0x0f,0x18,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 18 3f 25 whilehs p15.b, wzr, w0 // CHECK-INST: whilehs p15.b, wzr, w0 // CHECK-ENCODING: [0xef,0x0b,0x20,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: ef 0b 20 25 whilehs p15.b, w0, wzr // CHECK-INST: whilehs p15.b, w0, wzr // CHECK-ENCODING: [0x0f,0x08,0x3f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 08 3f 25 whilehs p15.h, x0, xzr // CHECK-INST: whilehs p15.h, x0, xzr // CHECK-ENCODING: [0x0f,0x18,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 18 7f 25 whilehs p15.h, w0, wzr // CHECK-INST: whilehs p15.h, w0, wzr // CHECK-ENCODING: [0x0f,0x08,0x7f,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 08 7f 25 whilehs p15.s, x0, xzr // CHECK-INST: whilehs p15.s, x0, xzr // CHECK-ENCODING: [0x0f,0x18,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 18 bf 25 whilehs p15.s, w0, wzr // CHECK-INST: whilehs p15.s, w0, wzr // CHECK-ENCODING: [0x0f,0x08,0xbf,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 08 bf 25 whilehs p15.d, w0, wzr // CHECK-INST: whilehs p15.d, w0, wzr // CHECK-ENCODING: [0x0f,0x08,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 08 ff 25 whilehs p15.d, x0, xzr // CHECK-INST: whilehs p15.d, x0, xzr // CHECK-ENCODING: [0x0f,0x18,0xff,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 0f 18 ff 25 diff --git a/llvm/test/MC/AArch64/SVE2/whilerw.s b/llvm/test/MC/AArch64/SVE2/whilerw.s index 611593a2107ae..4772eff64a8fd 100644 --- a/llvm/test/MC/AArch64/SVE2/whilerw.s +++ b/llvm/test/MC/AArch64/SVE2/whilerw.s @@ -12,23 +12,23 @@ whilerw p15.b, x30, x30 // CHECK-INST: whilerw p15.b, x30, x30 // CHECK-ENCODING: [0xdf,0x33,0x3e,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 33 3e 25 whilerw p15.h, x30, x30 // CHECK-INST: whilerw p15.h, x30, x30 // CHECK-ENCODING: [0xdf,0x33,0x7e,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 33 7e 25 whilerw p15.s, x30, x30 // CHECK-INST: whilerw p15.s, x30, x30 // CHECK-ENCODING: [0xdf,0x33,0xbe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 33 be 25 whilerw p15.d, x30, x30 // CHECK-INST: whilerw p15.d, x30, x30 // CHECK-ENCODING: [0xdf,0x33,0xfe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 33 fe 25 diff --git a/llvm/test/MC/AArch64/SVE2/whilewr.s b/llvm/test/MC/AArch64/SVE2/whilewr.s index 63f21f44d0266..c4b4c40ae4cfe 100644 --- a/llvm/test/MC/AArch64/SVE2/whilewr.s +++ b/llvm/test/MC/AArch64/SVE2/whilewr.s @@ -12,23 +12,23 @@ whilewr p15.b, x30, x30 // CHECK-INST: whilewr p15.b, x30, x30 // CHECK-ENCODING: [0xcf,0x33,0x3e,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: cf 33 3e 25 whilewr p15.h, x30, x30 // CHECK-INST: whilewr p15.h, x30, x30 // CHECK-ENCODING: [0xcf,0x33,0x7e,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: cf 33 7e 25 whilewr p15.s, x30, x30 // CHECK-INST: whilewr p15.s, x30, x30 // CHECK-ENCODING: [0xcf,0x33,0xbe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: cf 33 be 25 whilewr p15.d, x30, x30 // CHECK-INST: whilewr p15.d, x30, x30 // CHECK-ENCODING: [0xcf,0x33,0xfe,0x25] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: cf 33 fe 25 diff --git a/llvm/test/MC/AArch64/SVE2/xar.s b/llvm/test/MC/AArch64/SVE2/xar.s index 4aed0590f69d1..1e40aba3fae5e 100644 --- a/llvm/test/MC/AArch64/SVE2/xar.s +++ b/llvm/test/MC/AArch64/SVE2/xar.s @@ -12,49 +12,49 @@ xar z0.b, z0.b, z1.b, #1 // CHECK-INST: xar z0.b, z0.b, z1.b, #1 // CHECK-ENCODING: [0x20,0x34,0x2f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 34 2f 04 xar z31.b, z31.b, z30.b, #8 // CHECK-INST: xar z31.b, z31.b, z30.b, #8 // CHECK-ENCODING: [0xdf,0x37,0x28,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 37 28 04 xar z0.h, z0.h, z1.h, #1 // CHECK-INST: xar z0.h, z0.h, z1.h, #1 // CHECK-ENCODING: [0x20,0x34,0x3f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 34 3f 04 xar z31.h, z31.h, z30.h, #16 // CHECK-INST: xar z31.h, z31.h, z30.h, #16 // CHECK-ENCODING: [0xdf,0x37,0x30,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 37 30 04 xar z0.s, z0.s, z1.s, #1 // CHECK-INST: xar z0.s, z0.s, z1.s, #1 // CHECK-ENCODING: [0x20,0x34,0x7f,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 34 7f 04 xar z31.s, z31.s, z30.s, #32 // CHECK-INST: xar z31.s, z31.s, z30.s, #32 // CHECK-ENCODING: [0xdf,0x37,0x60,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 37 60 04 xar z0.d, z0.d, z1.d, #1 // CHECK-INST: xar z0.d, z0.d, z1.d, #1 // CHECK-ENCODING: [0x20,0x34,0xff,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: 20 34 ff 04 xar z31.d, z31.d, z30.d, #64 // CHECK-INST: xar z31.d, z31.d, z30.d, #64 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 37 a0 04 @@ -64,11 +64,11 @@ xar z31.d, z31.d, z30.d, #64 movprfx z31, z7 // CHECK-INST: movprfx z31, z7 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve +// CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: ff bc 20 04 xar z31.d, z31.d, z30.d, #64 // CHECK-INST: xar z31.d, z31.d, z30.d, #64 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04] -// CHECK-ERROR: instruction requires: streaming-sve or sve2 +// CHECK-ERROR: instruction requires: sve2 or sme // CHECK-UNKNOWN: df 37 a0 04 From d245bcf536a36430a0354bd90a7ef00c39ccbcb1 Mon Sep 17 00:00:00 2001 From: Amanieu d'Antras Date: Fri, 25 Feb 2022 22:06:47 +0000 Subject: [PATCH 199/316] [Mangler] Mangle aliases to fastcall/vectorcall functions correctly These aliases are produced by MergeFunctions and need to be mangled according to the calling convention of the function they are pointing to instead of defaulting to the C calling convention. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D120382 (cherry picked from commit 54b909de682bfa4e3389b680b0916ab18c99952a) --- llvm/lib/IR/Mangler.cpp | 2 +- llvm/test/CodeGen/X86/fastcall-correct-mangling.ll | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/llvm/lib/IR/Mangler.cpp b/llvm/lib/IR/Mangler.cpp index 2399ea27ee9d4..b8e3e40e4c1d5 100644 --- a/llvm/lib/IR/Mangler.cpp +++ b/llvm/lib/IR/Mangler.cpp @@ -144,7 +144,7 @@ void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, // Mangle functions with Microsoft calling conventions specially. Only do // this mangling for x86_64 vectorcall and 32-bit x86. - const Function *MSFunc = dyn_cast(GV); + const Function *MSFunc = dyn_cast_or_null(GV->getAliaseeObject()); // Don't add byte count suffixes when '\01' or '?' are in the first // character. diff --git a/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll b/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll index 00dc44e75e8f5..dd8ce0f0ef505 100644 --- a/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll +++ b/llvm/test/CodeGen/X86/fastcall-correct-mangling.ll @@ -31,3 +31,7 @@ define private x86_fastcallcc void @dontCrash() { ; CHECK64-LABEL: {{^}}.LdontCrash: ret void } + +@alias = alias void(i64, i8, i8, i16), void(i64, i8, i8, i16)* @func +; CHECK32-LABEL: {{^}}.set @alias@20, @func@20 +; CHECK64-LABEL: {{^}}.set alias, func From 41d4f89e38b718b3a291fb24ff0e2b654ee1ff79 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Thu, 17 Feb 2022 10:43:12 -0800 Subject: [PATCH 200/316] [X86ISelLowering] permit BlockAddressSDNode "i" constraints for PIC When building 32b x86 code as PIC, the existing handling of "i" constraints is conservative since generally we have to go through the GOT to find references to functions. But generally, BlockAddresses from C code refer to the Function in the current TU. Permit BlockAddresses to be used with the "i" constraint for those cases. I regressed this in commit 4edb9983cb8c ("[SelectionDAG] treat X constrained labels as i for asm") Fixes: https://github.com/llvm/llvm-project/issues/53868 Reviewed By: efriedma, MaskRay Differential Revision: https://reviews.llvm.org/D119905 (cherry picked from commit 027c16bef4b727095eea00bbef9266f1f4a78c27) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 5 ++-- llvm/test/CodeGen/X86/inline-asm-pic.ll | 38 +++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a1c387574ebb7..77c2e7d169907 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -54599,8 +54599,9 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, // In any sort of PIC mode addresses need to be computed at runtime by // adding in a register or some sort of table lookup. These can't - // be used as immediates. - if (Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC()) + // be used as immediates. BlockAddresses are fine though. + if ((Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC()) && + !isa(Op)) return; // If we are in non-pic codegen mode, we allow the address of a global (with diff --git a/llvm/test/CodeGen/X86/inline-asm-pic.ll b/llvm/test/CodeGen/X86/inline-asm-pic.ll index 7aeb1bfbdf416..503f8db91a29b 100644 --- a/llvm/test/CodeGen/X86/inline-asm-pic.ll +++ b/llvm/test/CodeGen/X86/inline-asm-pic.ll @@ -18,3 +18,41 @@ entry: tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** elementtype(i8*) inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind ret void } + +; The intent of this test is to ensure that we handle blockaddress' correctly +; with "i" constraints for -m32 -fPIC. + +define void @x() { +; CHECK-LABEL: x: +; CHECK: ## %bb.0: +; CHECK-NEXT: ## InlineAsm Start +; CHECK-NEXT: ## Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: ## InlineAsm End +; CHECK-NEXT: ## %bb.2: ## %return +; CHECK-NEXT: retl +; CHECK-NEXT: Ltmp0: ## Block address taken +; CHECK-NEXT: LBB1_1: ## %overflow +; CHECK-NEXT: retl + callbr void asm "# ${0:l}\0A", "i"(i8* blockaddress(@x, %overflow)) + to label %return [label %overflow] + +overflow: + br label %return + +return: + ret void +} + +; Test unusual case of blockaddress from @x in @y's asm. +define void @y() { +; CHECK-LABEL: y: +; CHECK: ## %bb.0: +; CHECK-NEXT: ## InlineAsm Start +; CHECK-NEXT: ## Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: ## InlineAsm End +; CHECK-NEXT: retl + call void asm "# ${0:l}\0A", "i"(i8* blockaddress(@x, %overflow)) + ret void +} From 3001b0d519630e2f1f0e2c4710379b3dbb43b715 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Thu, 10 Feb 2022 16:09:50 +0100 Subject: [PATCH 201/316] [fir] Fix FlangOptimizerTests link on Solaris As reported in Issue #53690, `tools/flang/unittests/Optimizer/FlangOptimizerTests` `FAIL`s to link on Solaris: Undefined first referenced symbol in file _ZN3fir7runtimeL8getModelIcEEPFN4mlir4TypeEPNS2_11MLIRContextEEv lib/libFIRBuilder.a(Reduction.cpp.o) which is `mlir::Type (*fir::runtime::getModel())(mlir::MLIRContext*)`. `clang++` warn's In file included from /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp:14: /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h:60:34: warning: function 'fir::runtime::getModel' has internal linkage but is not defined [-Wundefined-internal] static constexpr TypeBuilderFunc getModel(); ^ /var/llvm/llvm-14.0.0-rc1/rc1/llvm-project/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h:289:29: note: used here TypeBuilderFunc ret = getModel(); ^ Fixed by adding an explicit template instantiation for `getModel`. I suppose this is necessary because on Solaris `char` is `signed`. Tested on `sparcv9-sun-solaris2.11`. Differential Revision: https://reviews.llvm.org/D119438 (cherry picked from commit c2b9e9674d5259c12a055055f4e06eba5b8d0fa6) --- flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h b/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h index 072e3f26a49b0..8fea99e008735 100644 --- a/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h +++ b/flang/include/flang/Optimizer/Builder/Runtime/RTBuilder.h @@ -100,6 +100,12 @@ constexpr TypeBuilderFunc getModel() { }; } template <> +constexpr TypeBuilderFunc getModel() { + return [](mlir::MLIRContext *context) -> mlir::Type { + return mlir::IntegerType::get(context, 8 * sizeof(char)); + }; +} +template <> constexpr TypeBuilderFunc getModel() { return [](mlir::MLIRContext *context) -> mlir::Type { return mlir::IntegerType::get(context, 8 * sizeof(signed char)); From da33d400682a8cf93062fe61a9f0b6ec1d60c8ad Mon Sep 17 00:00:00 2001 From: Anton Afanasyev Date: Sat, 12 Feb 2022 11:46:49 +0300 Subject: [PATCH 202/316] [SLP] Don't try to vectorize pair with insertelement Particularly this breaks vectorization of insertelements where some of intermediate (i.e. not last) insertelements are used externally. Fixes PR52275 Fixes #51617 Reviewed by: ABataev Differential Revision: https://reviews.llvm.org/D119679 (cherry picked from commit b7574b0) --- .../Transforms/Vectorize/SLPVectorizer.cpp | 10 +- .../Transforms/SLPVectorizer/X86/pr52275.ll | 147 ++++++++++++++++-- 2 files changed, 140 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 9eafd94efea28..644372483edde 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -3849,13 +3849,7 @@ void BoUpSLP::buildTree_rec(ArrayRef VL, unsigned Depth, ValueSet SourceVectors; for (Value *V : VL) { SourceVectors.insert(cast(V)->getOperand(0)); - if (getInsertIndex(V) == None) { - LLVM_DEBUG(dbgs() << "SLP: Gather of insertelement vectors with " - "non-constant or undef index.\n"); - newTreeEntry(VL, None /*not vectorized*/, S, UserTreeIdx); - BS.cancelScheduling(VL, VL0); - return; - } + assert(getInsertIndex(V) != None && "Non-constant or undef index?"); } if (count_if(VL, [&SourceVectors](Value *V) { @@ -8343,6 +8337,8 @@ void SLPVectorizerPass::collectSeedInstructions(BasicBlock *BB) { bool SLPVectorizerPass::tryToVectorizePair(Value *A, Value *B, BoUpSLP &R) { if (!A || !B) return false; + if (isa(A) || isa(B)) + return false; Value *VL[] = {A, B}; return tryToVectorizeList(VL, R); } diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr52275.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr52275.ll index 6794553ffd6d0..9205ef0b375d1 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/pr52275.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/pr52275.ll @@ -1,16 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -slp-vectorizer -S -mtriple=x86_64-- | FileCheck %s -define <4 x i8> @pr52275(<4 x i8> %v, i8* %x) { -; CHECK-LABEL: @pr52275( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[X:%.*]], i64 1 -; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[X]] to <2 x i8>* -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i8>, <2 x i8>* [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i8> [[TMP2]], <2 x i8> poison, <4 x i32> -; CHECK-NEXT: [[V11:%.*]] = shufflevector <4 x i8> [[V:%.*]], <4 x i8> [[TMP3]], <4 x i32> -; CHECK-NEXT: [[V2:%.*]] = add <4 x i8> [[V11]], [[V11]] -; CHECK-NEXT: ret <4 x i8> [[V2]] -; +define <4 x i8> @test(<4 x i8> %v, i8* %x) { %x0 = load i8, i8* %x, align 4 %g1 = getelementptr inbounds i8, i8* %x, i64 1 %x1 = load i8, i8* %g1, align 4 @@ -19,3 +10,139 @@ define <4 x i8> @pr52275(<4 x i8> %v, i8* %x) { %v2 = add <4 x i8> %v0, %v1 ret <4 x i8> %v2 } + +define <2 x i8> @test2(<2 x i8> %t6, i32* %t1) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; CHECK-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 0 +; CHECK-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; CHECK-NEXT: [[T10:%.*]] = insertelement <2 x i8> [[T8]], i8 [[T9]], i64 1 +; CHECK-NEXT: [[T11:%.*]] = add <2 x i8> [[T10]], [[T8]] +; CHECK-NEXT: ret <2 x i8> [[T11]] +; +; FORCE_SLP-LABEL: @test2( +; FORCE_SLP-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; FORCE_SLP-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; FORCE_SLP-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 0 +; FORCE_SLP-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; FORCE_SLP-NEXT: [[T10:%.*]] = insertelement <2 x i8> [[T8]], i8 [[T9]], i64 1 +; FORCE_SLP-NEXT: [[T11:%.*]] = add <2 x i8> [[T10]], [[T8]] +; FORCE_SLP-NEXT: ret <2 x i8> [[T11]] +; + %t3 = load i32, i32* %t1, align 4 + %t4 = getelementptr inbounds i32, i32* %t1, i64 1 + %t5 = load i32, i32* %t4, align 4 + %t7 = trunc i32 %t3 to i8 + %t8 = insertelement <2 x i8> %t6, i8 %t7, i64 0 + %t9 = trunc i32 %t5 to i8 + %t10 = insertelement <2 x i8> %t8, i8 %t9, i64 1 + %t11 = add <2 x i8> %t10, %t8 + ret <2 x i8> %t11 +} + +define <2 x i8> @test_reorder(<2 x i8> %t6, i32* %t1) { +; CHECK-LABEL: @test_reorder( +; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; CHECK-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 1 +; CHECK-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; CHECK-NEXT: [[T10:%.*]] = insertelement <2 x i8> [[T8]], i8 [[T9]], i64 0 +; CHECK-NEXT: [[T11:%.*]] = add <2 x i8> [[T10]], [[T8]] +; CHECK-NEXT: ret <2 x i8> [[T11]] +; +; FORCE_SLP-LABEL: @test_reorder( +; FORCE_SLP-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; FORCE_SLP-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; FORCE_SLP-NEXT: [[T8:%.*]] = insertelement <2 x i8> [[T6:%.*]], i8 [[T7]], i64 1 +; FORCE_SLP-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; FORCE_SLP-NEXT: [[T10:%.*]] = insertelement <2 x i8> [[T8]], i8 [[T9]], i64 0 +; FORCE_SLP-NEXT: [[T11:%.*]] = add <2 x i8> [[T10]], [[T8]] +; FORCE_SLP-NEXT: ret <2 x i8> [[T11]] +; + %t3 = load i32, i32* %t1, align 4 + %t4 = getelementptr inbounds i32, i32* %t1, i64 1 + %t5 = load i32, i32* %t4, align 4 + %t7 = trunc i32 %t3 to i8 + %t8 = insertelement <2 x i8> %t6, i8 %t7, i64 1 + %t9 = trunc i32 %t5 to i8 + %t10 = insertelement <2 x i8> %t8, i8 %t9, i64 0 + %t11 = add <2 x i8> %t10, %t8 + ret <2 x i8> %t11 +} + +define <4 x i8> @test_subvector(<4 x i8> %t6, i32* %t1) { +; CHECK-LABEL: @test_subvector( +; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; CHECK-NEXT: [[T8:%.*]] = insertelement <4 x i8> [[T6:%.*]], i8 [[T7]], i64 0 +; CHECK-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; CHECK-NEXT: [[T10:%.*]] = insertelement <4 x i8> [[T8]], i8 [[T9]], i64 1 +; CHECK-NEXT: [[T11:%.*]] = add <4 x i8> [[T10]], [[T8]] +; CHECK-NEXT: ret <4 x i8> [[T11]] +; +; FORCE_SLP-LABEL: @test_subvector( +; FORCE_SLP-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; FORCE_SLP-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; FORCE_SLP-NEXT: [[T8:%.*]] = insertelement <4 x i8> [[T6:%.*]], i8 [[T7]], i64 0 +; FORCE_SLP-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; FORCE_SLP-NEXT: [[T10:%.*]] = insertelement <4 x i8> [[T8]], i8 [[T9]], i64 1 +; FORCE_SLP-NEXT: [[T11:%.*]] = add <4 x i8> [[T10]], [[T8]] +; FORCE_SLP-NEXT: ret <4 x i8> [[T11]] +; + %t3 = load i32, i32* %t1, align 4 + %t4 = getelementptr inbounds i32, i32* %t1, i64 1 + %t5 = load i32, i32* %t4, align 4 + %t7 = trunc i32 %t3 to i8 + %t8 = insertelement <4 x i8> %t6, i8 %t7, i64 0 + %t9 = trunc i32 %t5 to i8 + %t10 = insertelement <4 x i8> %t8, i8 %t9, i64 1 + %t11 = add <4 x i8> %t10, %t8 + ret <4 x i8> %t11 +} + +define <4 x i8> @test_subvector_reorder(<4 x i8> %t6, i32* %t1) { +; CHECK-LABEL: @test_subvector_reorder( +; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; CHECK-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; CHECK-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; CHECK-NEXT: [[T8:%.*]] = insertelement <4 x i8> [[T6:%.*]], i8 [[T7]], i64 3 +; CHECK-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; CHECK-NEXT: [[T10:%.*]] = insertelement <4 x i8> [[T8]], i8 [[T9]], i64 2 +; CHECK-NEXT: [[T11:%.*]] = add <4 x i8> [[T10]], [[T8]] +; CHECK-NEXT: ret <4 x i8> [[T11]] +; +; FORCE_SLP-LABEL: @test_subvector_reorder( +; FORCE_SLP-NEXT: [[T3:%.*]] = load i32, i32* [[T1:%.*]], align 4 +; FORCE_SLP-NEXT: [[T4:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 1 +; FORCE_SLP-NEXT: [[T5:%.*]] = load i32, i32* [[T4]], align 4 +; FORCE_SLP-NEXT: [[T7:%.*]] = trunc i32 [[T3]] to i8 +; FORCE_SLP-NEXT: [[T8:%.*]] = insertelement <4 x i8> [[T6:%.*]], i8 [[T7]], i64 3 +; FORCE_SLP-NEXT: [[T9:%.*]] = trunc i32 [[T5]] to i8 +; FORCE_SLP-NEXT: [[T10:%.*]] = insertelement <4 x i8> [[T8]], i8 [[T9]], i64 2 +; FORCE_SLP-NEXT: [[T11:%.*]] = add <4 x i8> [[T10]], [[T8]] +; FORCE_SLP-NEXT: ret <4 x i8> [[T11]] +; + %t3 = load i32, i32* %t1, align 4 + %t4 = getelementptr inbounds i32, i32* %t1, i64 1 + %t5 = load i32, i32* %t4, align 4 + %t7 = trunc i32 %t3 to i8 + %t8 = insertelement <4 x i8> %t6, i8 %t7, i64 3 + %t9 = trunc i32 %t5 to i8 + %t10 = insertelement <4 x i8> %t8, i8 %t9, i64 2 + %t11 = add <4 x i8> %t10, %t8 + ret <4 x i8> %t11 +} From 19149538e9a9fce91bcdf70b69dc6defc9e8a533 Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Wed, 16 Feb 2022 11:54:38 -0800 Subject: [PATCH 203/316] [BPF] Fix a BTF type pruning bug In BPF backend, BTF type generation may skip some debuginfo types if they are the pointee type of a struct member. For example, struct task_struct { ... struct mm_struct *mm; ... }; BPF backend may generate a forward decl for 'struct mm_struct' instead of full type if there are no other usage of 'struct mm_struct'. The reason is to avoid bringing too much unneeded types in BTF. Alexei found a pruning bug where we may miss some full type generation. The following is an illustrating example: struct t1 { ... } struct t2 { struct t1 *p; }; struct t2 g; void foo(struct t1 *arg) { ... } In the above case, we will have partial debuginfo chain like below: struct t2 -> member p \ -> ptr -> struct t1 / foo -> argument arg During traversing struct t2 -> member p -> ptr -> struct t1 The corresponding BTF types are generated except 'struct t1' which will be in FixUp stage. Later, when traversing foo -> argument arg -> ptr -> struct t1 The 'ptr' BTF type has been generated and currently implementation ignores 'pointer' type hence 'struct t1' is not generated. This patch fixed the issue not just for the above case, but for general case with multiple derived types, e.g., struct t2 -> member p \ -> const -> ptr -> volatile -> struct t1 / foo -> argument arg Differential Revision: https://reviews.llvm.org/D119986 --- llvm/lib/Target/BPF/BTFDebug.cpp | 30 +++++-- .../BPF/BTF/pruning-multi-derived-type.ll | 87 +++++++++++++++++++ 2 files changed, 110 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index d536aed1d2114..166b62bd62269 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -773,15 +773,31 @@ void BTFDebug::visitTypeEntry(const DIType *Ty, uint32_t &TypeId, // already defined, we should keep moving to eventually // bring in types for "struct t". Otherwise, the "struct s2" // definition won't be correct. + // + // In the above, we have following debuginfo: + // {ptr, struct_member} -> typedef -> struct + // and BTF type for 'typedef' is generated while 'struct' may + // be in FixUp. But let us generalize the above to handle + // {different types} -> [various derived types]+ -> another type. + // For example, + // {func_param, struct_member} -> const -> ptr -> volatile -> struct + // We will traverse const/ptr/volatile which already have corresponding + // BTF types and generate type for 'struct' which might be in Fixup + // state. if (Ty && (!CheckPointer || !SeenPointer)) { if (const auto *DTy = dyn_cast(Ty)) { - unsigned Tag = DTy->getTag(); - if (Tag == dwarf::DW_TAG_typedef || Tag == dwarf::DW_TAG_const_type || - Tag == dwarf::DW_TAG_volatile_type || - Tag == dwarf::DW_TAG_restrict_type) { - uint32_t TmpTypeId; - visitTypeEntry(DTy->getBaseType(), TmpTypeId, CheckPointer, - SeenPointer); + while (DTy) { + const DIType *BaseTy = DTy->getBaseType(); + if (!BaseTy) + break; + + if (DIToIdMap.find(BaseTy) != DIToIdMap.end()) { + DTy = dyn_cast(BaseTy); + } else { + uint32_t TmpTypeId; + visitTypeEntry(BaseTy, TmpTypeId, CheckPointer, SeenPointer); + break; + } } } } diff --git a/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll b/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll new file mode 100644 index 0000000000000..63c864fd0e3a8 --- /dev/null +++ b/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s +; RUN: llc -march=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s +; Source: +; struct t1 { +; int a; +; }; +; struct t2 { +; const struct t1 * const a; +; }; +; int foo(struct t2 *arg) { return 0; } +; int bar(const struct t1 * const arg) { return 0; } +; Compilation flags: +; clang -target bpf -O2 -g -S -emit-llvm t.c + +%struct.t2 = type { %struct.t1* } +%struct.t1 = type { i32 } + +; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn +define dso_local i32 @foo(%struct.t2* nocapture noundef readnone %arg) local_unnamed_addr #0 !dbg !7 { +entry: + call void @llvm.dbg.value(metadata %struct.t2* %arg, metadata !22, metadata !DIExpression()), !dbg !23 + ret i32 0, !dbg !24 +} + +; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn +define dso_local i32 @bar(%struct.t1* nocapture noundef readnone %arg) local_unnamed_addr #0 !dbg !25 { +entry: + call void @llvm.dbg.value(metadata %struct.t1* %arg, metadata !29, metadata !DIExpression()), !dbg !30 + ret i32 0, !dbg !31 +} + +; CHECK: .long 10 # BTF_KIND_INT(id = 7) +; CHECK-NEXT: .long 16777216 # 0x1000000 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .long 16777248 # 0x1000020 + +; CHECK: .long 69 # BTF_KIND_STRUCT(id = 9) +; CHECK-NEXT: .long 67108865 # 0x4000001 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .long 7 + +; CHECK: .byte 97 # string offset=4 +; CHECK: .ascii "t1" # string offset=69 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + +attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 15.0.0 (https://github.com/llvm/llvm-project.git c34c8afcb85ae9142d0f783bb899c464e8bd2356)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.c", directory: "/tmp/home/yhs/work/tests/llvm/btf_ptr", checksumkind: CSK_MD5, checksum: "d43a0541e830263021772349589e47a5") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 7, !"frame-pointer", i32 2} +!6 = !{!"clang version 15.0.0 (https://github.com/llvm/llvm-project.git c34c8afcb85ae9142d0f783bb899c464e8bd2356)"} +!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 7, type: !8, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !21) +!8 = !DISubroutineType(types: !9) +!9 = !{!10, !11} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) +!12 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t2", file: !1, line: 4, size: 64, elements: !13) +!13 = !{!14} +!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !12, file: !1, line: 5, baseType: !15, size: 64) +!15 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !16) +!16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !17, size: 64) +!17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !18) +!18 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t1", file: !1, line: 1, size: 32, elements: !19) +!19 = !{!20} +!20 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !18, file: !1, line: 2, baseType: !10, size: 32) +!21 = !{!22} +!22 = !DILocalVariable(name: "arg", arg: 1, scope: !7, file: !1, line: 7, type: !11) +!23 = !DILocation(line: 0, scope: !7) +!24 = !DILocation(line: 7, column: 27, scope: !7) +!25 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 8, type: !26, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !28) +!26 = !DISubroutineType(types: !27) +!27 = !{!10, !15} +!28 = !{!29} +!29 = !DILocalVariable(name: "arg", arg: 1, scope: !25, file: !1, line: 8, type: !15) +!30 = !DILocation(line: 0, scope: !25) +!31 = !DILocation(line: 8, column: 40, scope: !25) From ce3d57ad61db88beba0126cade242c0c3ddc4cf5 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 1 Mar 2022 16:42:37 -0800 Subject: [PATCH 204/316] Revert "[BPF] Fix a BTF type pruning bug" This reverts commit 19149538e9a9fce91bcdf70b69dc6defc9e8a533. This fix was accidentally committed. --- llvm/lib/Target/BPF/BTFDebug.cpp | 30 ++----- .../BPF/BTF/pruning-multi-derived-type.ll | 87 ------------------- 2 files changed, 7 insertions(+), 110 deletions(-) delete mode 100644 llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index 166b62bd62269..d536aed1d2114 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -773,31 +773,15 @@ void BTFDebug::visitTypeEntry(const DIType *Ty, uint32_t &TypeId, // already defined, we should keep moving to eventually // bring in types for "struct t". Otherwise, the "struct s2" // definition won't be correct. - // - // In the above, we have following debuginfo: - // {ptr, struct_member} -> typedef -> struct - // and BTF type for 'typedef' is generated while 'struct' may - // be in FixUp. But let us generalize the above to handle - // {different types} -> [various derived types]+ -> another type. - // For example, - // {func_param, struct_member} -> const -> ptr -> volatile -> struct - // We will traverse const/ptr/volatile which already have corresponding - // BTF types and generate type for 'struct' which might be in Fixup - // state. if (Ty && (!CheckPointer || !SeenPointer)) { if (const auto *DTy = dyn_cast(Ty)) { - while (DTy) { - const DIType *BaseTy = DTy->getBaseType(); - if (!BaseTy) - break; - - if (DIToIdMap.find(BaseTy) != DIToIdMap.end()) { - DTy = dyn_cast(BaseTy); - } else { - uint32_t TmpTypeId; - visitTypeEntry(BaseTy, TmpTypeId, CheckPointer, SeenPointer); - break; - } + unsigned Tag = DTy->getTag(); + if (Tag == dwarf::DW_TAG_typedef || Tag == dwarf::DW_TAG_const_type || + Tag == dwarf::DW_TAG_volatile_type || + Tag == dwarf::DW_TAG_restrict_type) { + uint32_t TmpTypeId; + visitTypeEntry(DTy->getBaseType(), TmpTypeId, CheckPointer, + SeenPointer); } } } diff --git a/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll b/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll deleted file mode 100644 index 63c864fd0e3a8..0000000000000 --- a/llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll +++ /dev/null @@ -1,87 +0,0 @@ -; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s -; RUN: llc -march=bpfeb -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s -; Source: -; struct t1 { -; int a; -; }; -; struct t2 { -; const struct t1 * const a; -; }; -; int foo(struct t2 *arg) { return 0; } -; int bar(const struct t1 * const arg) { return 0; } -; Compilation flags: -; clang -target bpf -O2 -g -S -emit-llvm t.c - -%struct.t2 = type { %struct.t1* } -%struct.t1 = type { i32 } - -; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn -define dso_local i32 @foo(%struct.t2* nocapture noundef readnone %arg) local_unnamed_addr #0 !dbg !7 { -entry: - call void @llvm.dbg.value(metadata %struct.t2* %arg, metadata !22, metadata !DIExpression()), !dbg !23 - ret i32 0, !dbg !24 -} - -; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn -define dso_local i32 @bar(%struct.t1* nocapture noundef readnone %arg) local_unnamed_addr #0 !dbg !25 { -entry: - call void @llvm.dbg.value(metadata %struct.t1* %arg, metadata !29, metadata !DIExpression()), !dbg !30 - ret i32 0, !dbg !31 -} - -; CHECK: .long 10 # BTF_KIND_INT(id = 7) -; CHECK-NEXT: .long 16777216 # 0x1000000 -; CHECK-NEXT: .long 4 -; CHECK-NEXT: .long 16777248 # 0x1000020 - -; CHECK: .long 69 # BTF_KIND_STRUCT(id = 9) -; CHECK-NEXT: .long 67108865 # 0x4000001 -; CHECK-NEXT: .long 4 -; CHECK-NEXT: .long 4 -; CHECK-NEXT: .long 7 - -; CHECK: .byte 97 # string offset=4 -; CHECK: .ascii "t1" # string offset=69 - -; Function Attrs: nofree nosync nounwind readnone speculatable willreturn -declare void @llvm.dbg.value(metadata, metadata, metadata) #1 - -attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5} -!llvm.ident = !{!6} - -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 15.0.0 (https://github.com/llvm/llvm-project.git c34c8afcb85ae9142d0f783bb899c464e8bd2356)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "test.c", directory: "/tmp/home/yhs/work/tests/llvm/btf_ptr", checksumkind: CSK_MD5, checksum: "d43a0541e830263021772349589e47a5") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 7, !"frame-pointer", i32 2} -!6 = !{!"clang version 15.0.0 (https://github.com/llvm/llvm-project.git c34c8afcb85ae9142d0f783bb899c464e8bd2356)"} -!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 7, type: !8, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !21) -!8 = !DISubroutineType(types: !9) -!9 = !{!10, !11} -!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) -!12 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t2", file: !1, line: 4, size: 64, elements: !13) -!13 = !{!14} -!14 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !12, file: !1, line: 5, baseType: !15, size: 64) -!15 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !16) -!16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !17, size: 64) -!17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !18) -!18 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t1", file: !1, line: 1, size: 32, elements: !19) -!19 = !{!20} -!20 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !18, file: !1, line: 2, baseType: !10, size: 32) -!21 = !{!22} -!22 = !DILocalVariable(name: "arg", arg: 1, scope: !7, file: !1, line: 7, type: !11) -!23 = !DILocation(line: 0, scope: !7) -!24 = !DILocation(line: 7, column: 27, scope: !7) -!25 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 8, type: !26, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !28) -!26 = !DISubroutineType(types: !27) -!27 = !{!10, !15} -!28 = !{!29} -!29 = !DILocalVariable(name: "arg", arg: 1, scope: !25, file: !1, line: 8, type: !15) -!30 = !DILocation(line: 0, scope: !25) -!31 = !DILocation(line: 8, column: 40, scope: !25) From 4c9110a5f37b99d831887ebc1365cec7c3281f36 Mon Sep 17 00:00:00 2001 From: Simon Atanasyan Date: Wed, 23 Feb 2022 15:53:41 +0300 Subject: [PATCH 205/316] [MIPS] Recognize DT_MIPS_XHASH dynamic table tag LLVM tools do not emit `DT_MIPS_XHASH` dynamic table tag. But now `llvm-objdump` and `llvm-readelf` recognize this tag and print it. Fixes https://github.com/llvm/llvm-project/issues/53996 (cherry picked from commit 3c840e3c00e910c47a3f61f755fdc402d51e9fb6) --- llvm/include/llvm/BinaryFormat/DynamicTags.def | 1 + .../ELF/dynamic-section-machine-specific.test | 3 +++ .../llvm-readobj/ELF/dynamic-tags-machine-specific.test | 8 ++++++-- .../tools/obj2yaml/ELF/dynamic-section-arch-tags.yaml | 4 ++++ llvm/tools/llvm-readobj/ELFDumper.cpp | 1 + 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/BinaryFormat/DynamicTags.def b/llvm/include/llvm/BinaryFormat/DynamicTags.def index 814d8b113ec4e..ae25ec53813c7 100644 --- a/llvm/include/llvm/BinaryFormat/DynamicTags.def +++ b/llvm/include/llvm/BinaryFormat/DynamicTags.def @@ -209,6 +209,7 @@ MIPS_DYNAMIC_TAG(MIPS_RWPLT, 0x70000034) // Points to the base // of a writable PLT. MIPS_DYNAMIC_TAG(MIPS_RLD_MAP_REL, 0x70000035) // Relative offset of run time loader // map, used for debugging. +MIPS_DYNAMIC_TAG(MIPS_XHASH, 0x70000036) // GNU-style hash table with xlat. // PPC specific dynamic table entries. PPC_DYNAMIC_TAG(PPC_GOT, 0x70000000) // Uses Secure PLT ABI. diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test index 08d7d2e9c7c73..20219dd4893b7 100644 --- a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test +++ b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test @@ -86,6 +86,7 @@ ProgramHeaders: # MIPS-NEXT: MIPS_PLTGOT 0x0000000000001000 # MIPS-NEXT: MIPS_RWPLT 0x0000000000001000 # MIPS-NEXT: MIPS_RLD_MAP_REL 0x0000000000001000 +# MIPS-NEXT: MIPS_XHASH 0x0000000000002000 --- !ELF FileHeader: @@ -187,6 +188,8 @@ Sections: Value: 0x1000 - Tag: DT_MIPS_RLD_MAP_REL Value: 0x1000 + - Tag: DT_MIPS_XHASH + Value: 0x2000 - Tag: DT_NULL Value: 0 ProgramHeaders: diff --git a/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test b/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test index 970edccd7777d..c32ea33b9b3cb 100644 --- a/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test +++ b/llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test @@ -53,7 +53,7 @@ ProgramHeaders: # RUN: llvm-readelf --dynamic-table %t.mips \ # RUN: | FileCheck %s --strict-whitespace --match-full-lines --check-prefix=GNU-MIPS -# LLVM-MIPS:DynamicSection [ (47 entries) +# LLVM-MIPS:DynamicSection [ (48 entries) # LLVM-MIPS-NEXT: Tag Type Name/Value # LLVM-MIPS-NEXT: 0x0000000000000004 HASH 0x1000 # LLVM-MIPS-NEXT: 0x0000000070000001 MIPS_RLD_VERSION 305419896 @@ -101,10 +101,11 @@ ProgramHeaders: # LLVM-MIPS-NEXT: 0x0000000070000032 MIPS_PLTGOT 0x1000 # LLVM-MIPS-NEXT: 0x0000000070000034 MIPS_RWPLT 0x1000 # LLVM-MIPS-NEXT: 0x0000000070000035 MIPS_RLD_MAP_REL 0x1000 +# LLVM-MIPS-NEXT: 0x0000000070000036 MIPS_XHASH 0x2000 # LLVM-MIPS-NEXT: 0x0000000000000000 NULL 0x0 # LLVM-MIPS-NEXT:] -# GNU-MIPS:Dynamic section at offset {{.*}} contains 47 entries: +# GNU-MIPS:Dynamic section at offset {{.*}} contains 48 entries: # GNU-MIPS-NEXT: Tag Type Name/Value # GNU-MIPS-NEXT: 0x0000000000000004 (HASH) 0x1000 # GNU-MIPS-NEXT: 0x0000000070000001 (MIPS_RLD_VERSION) 305419896 @@ -152,6 +153,7 @@ ProgramHeaders: # GNU-MIPS-NEXT: 0x0000000070000032 (MIPS_PLTGOT) 0x1000 # GNU-MIPS-NEXT: 0x0000000070000034 (MIPS_RWPLT) 0x1000 # GNU-MIPS-NEXT: 0x0000000070000035 (MIPS_RLD_MAP_REL) 0x1000 +# GNU-MIPS-NEXT: 0x0000000070000036 (MIPS_XHASH) 0x2000 # GNU-MIPS-NEXT: 0x0000000000000000 (NULL) 0x0 --- !ELF @@ -256,6 +258,8 @@ Sections: Value: 0x1000 - Tag: DT_MIPS_RLD_MAP_REL Value: 0x1000 + - Tag: DT_MIPS_XHASH + Value: 0x2000 - Tag: DT_NULL Value: 0 ProgramHeaders: diff --git a/llvm/test/tools/obj2yaml/ELF/dynamic-section-arch-tags.yaml b/llvm/test/tools/obj2yaml/ELF/dynamic-section-arch-tags.yaml index 5523b2fee37df..538838ff7c1e8 100644 --- a/llvm/test/tools/obj2yaml/ELF/dynamic-section-arch-tags.yaml +++ b/llvm/test/tools/obj2yaml/ELF/dynamic-section-arch-tags.yaml @@ -97,6 +97,8 @@ # MIPS-NEXT: Value: 0x2D # MIPS-NEXT: - Tag: DT_MIPS_RLD_MAP_REL # MIPS-NEXT: Value: 0x2E +# MIPS-NEXT: - Tag: DT_MIPS_XHASH +# MIPS-NEXT: Value: 0x2F --- !ELF FileHeader: @@ -200,6 +202,8 @@ Sections: Value: 0x000000000000002D - Tag: DT_MIPS_RLD_MAP_REL Value: 0x000000000000002E + - Tag: DT_MIPS_XHASH + Value: 0x000000000000002F ## Check we can handle Hexagon specific tags. # RUN: yaml2obj --docnum=2 %s -o %t2 diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp index 04a67225401f1..3d43d1a72e7e8 100644 --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -2265,6 +2265,7 @@ std::string ELFDumper::getDynamicEntry(uint64_t Type, case DT_MIPS_PLTGOT: case DT_MIPS_RWPLT: case DT_MIPS_RLD_MAP_REL: + case DT_MIPS_XHASH: return FormatHexValue(Value); case DT_MIPS_FLAGS: return FormatFlags(Value, makeArrayRef(ElfDynamicDTMipsFlags)); From 967296bfefee9740b1dfb4644970d776e1b37b5b Mon Sep 17 00:00:00 2001 From: Shao-Ce SUN Date: Wed, 2 Mar 2022 14:31:23 +0800 Subject: [PATCH 206/316] [RISCV] Fix inline asm errors in zfinx Patch is from craig.topper's comments in https://reviews.llvm.org/D93298 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 24 ++++++++++++++++++++- llvm/test/CodeGen/RISCV/zfinx-types.ll | 19 ++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/RISCV/zfinx-types.ll diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7f5555b9b7a85..19935caa34dfb 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10466,7 +10466,29 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } } - return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); + std::pair Res = + TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); + + if (Res.second == &RISCV::GPRF32RegClass) { + if (!Subtarget.is64Bit() || VT == MVT::Other) + return std::make_pair(Res.first, &RISCV::GPRRegClass); + return std::make_pair(0, nullptr); + } + + if (Res.second == &RISCV::GPRF64RegClass || + Res.second == &RISCV::GPRPF64RegClass) { + if (Subtarget.is64Bit() || VT == MVT::Other) + return std::make_pair(Res.first, &RISCV::GPRRegClass); + return std::make_pair(0, nullptr); + } + + if (Res.second == &RISCV::GPRF16RegClass) { + if (VT == MVT::Other) + return std::make_pair(Res.first, &RISCV::GPRRegClass); + return std::make_pair(0, nullptr); + } + + return Res; } unsigned diff --git a/llvm/test/CodeGen/RISCV/zfinx-types.ll b/llvm/test/CodeGen/RISCV/zfinx-types.ll new file mode 100644 index 0000000000000..9cbc7d9ce219b --- /dev/null +++ b/llvm/test/CodeGen/RISCV/zfinx-types.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RVZFINX %s +; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ +; RUN: -target-abi=lp64f | FileCheck -check-prefix=RVZFINX %s + +define float @test_float(float %x) { +; RVZFINX-LABEL: test_float: +; RVZFINX: # %bb.0: +; RVZFINX-NEXT: .cfi_def_cfa_offset 0 +; RVZFINX-NEXT: li a0, 0 +; RVZFINX-NEXT: #APP +; RVZFINX-NEXT: mv a0, a0 +; RVZFINX-NEXT: #NO_APP +; RVZFINX-NEXT: li a0, 0 +; RVZFINX-NEXT: ret + %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00) + ret float 0.000000e+00 +} From 261253aa60cc10f21788fb55ae27152242a65989 Mon Sep 17 00:00:00 2001 From: Michael Kruse Date: Wed, 2 Mar 2022 12:47:42 -0600 Subject: [PATCH 207/316] [Clang][docs] Add preprocessor changes to ReleaseNotes. --- clang/docs/ReleaseNotes.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 869d62aebfb18..a6cbf25fd48a5 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -76,6 +76,9 @@ Non-comprehensive list of changes in this release - Configuration file syntax extended with ```` token. This expands to the base path of the current config file. See :ref:`configuration-files` for details. +- The ``-E -P`` preprocessor output now always omits blank lines, matching + gcc behaviour. Previously, up to 8 consecutive blank lines could appear + in the output. New Compiler Flags ------------------ @@ -91,6 +94,14 @@ New Compiler Flags outside of such a region. - ``-falign-loops=N`` (N is a power of 2) is now supported for non-LTO cases. (`D106701 `_) +- The ``-fminimize-whitespace`` flag allows removing redundant whitespace + from preprocessor output (``-E`` flag). When combined with ``-P``, this + includes newlines. Otherwise, only indention is removed (other horizontal + whitespace is always collapsed). + The motivation is to improve compiler cache hit rate by becoming invariant + to whitespace changes, such as reformatting using clang-format. Patches + for `ccache `_ and + `sccache `_ are under review. Deprecated Compiler Flags ------------------------- From a98c04d58930814f4ff00293ffd14feca57feafa Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 4 Feb 2022 03:17:20 -0600 Subject: [PATCH 208/316] [Attributor][FIX] Use liveness information of the right function When we use liveness for edges during the `genericValueTraversal` we need to make sure to use the AAIsDead of the correct function. This patch adds the proper logic and some simple caching scheme. We also add an assertion to the `isEdgeDead` call to make sure future misuse is detected earlier. Fixes https://github.com/llvm/llvm-project/issues/53872 --- .../Transforms/IPO/AttributorAttributes.cpp | 43 ++++--- .../IPConstantProp/return-constant.ll | 4 +- .../IPConstantProp/return-constants.ll | 4 +- llvm/test/Transforms/Attributor/align.ll | 106 ++++++++++-------- .../read_write_returned_arguments_scc.ll | 16 +-- .../Transforms/Attributor/value-simplify.ll | 21 ++++ 6 files changed, 121 insertions(+), 73 deletions(-) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 5593a297d2d89..61a973f869d41 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -266,13 +266,18 @@ static bool genericValueTraversal( function_ref StripCB = nullptr, bool Intraprocedural = false) { - const AAIsDead *LivenessAA = nullptr; - if (IRP.getAnchorScope()) - LivenessAA = &A.getAAFor( - QueryingAA, - IRPosition::function(*IRP.getAnchorScope(), IRP.getCallBaseContext()), - DepClassTy::NONE); - bool AnyDead = false; + struct LivenessInfo { + const AAIsDead *LivenessAA = nullptr; + bool AnyDead = false; + }; + DenseMap LivenessAAs; + auto GetLivenessInfo = [&](const Function &F) -> LivenessInfo & { + LivenessInfo &LI = LivenessAAs[&F]; + if (!LI.LivenessAA) + LI.LivenessAA = &A.getAAFor(QueryingAA, IRPosition::function(F), + DepClassTy::NONE); + return LI; + }; Value *InitialV = &IRP.getAssociatedValue(); using Item = std::pair; @@ -342,13 +347,12 @@ static bool genericValueTraversal( // Look through phi nodes, visit all live operands. if (auto *PHI = dyn_cast(V)) { - assert(LivenessAA && - "Expected liveness in the presence of instructions!"); + LivenessInfo &LI = GetLivenessInfo(*PHI->getFunction()); for (unsigned u = 0, e = PHI->getNumIncomingValues(); u < e; u++) { BasicBlock *IncomingBB = PHI->getIncomingBlock(u); - if (LivenessAA->isEdgeDead(IncomingBB, PHI->getParent())) { - AnyDead = true; - UsedAssumedInformation |= !LivenessAA->isAtFixpoint(); + if (LI.LivenessAA->isEdgeDead(IncomingBB, PHI->getParent())) { + LI.AnyDead = true; + UsedAssumedInformation |= !LI.LivenessAA->isAtFixpoint(); continue; } Worklist.push_back( @@ -402,8 +406,10 @@ static bool genericValueTraversal( } while (!Worklist.empty()); // If we actually used liveness information so we have to record a dependence. - if (AnyDead) - A.recordDependence(*LivenessAA, QueryingAA, DepClassTy::OPTIONAL); + for (auto &It : LivenessAAs) + if (It.second.AnyDead) + A.recordDependence(*It.second.LivenessAA, QueryingAA, + DepClassTy::OPTIONAL); // All values have been visited. return true; @@ -1248,11 +1254,13 @@ struct AAPointerInfoImpl // Run the user callback on all writes we cannot skip and return if that // succeeded for all or not. unsigned NumInterferingWrites = InterferingWrites.size(); - for (auto &It : InterferingWrites) + for (auto &It : InterferingWrites) { if (!DT || NumInterferingWrites > MaxInterferingWrites || - !CanSkipAccess(*It.first, It.second)) + !CanSkipAccess(*It.first, It.second)) { if (!UserCB(*It.first, It.second)) return false; + } + } return true; } @@ -3839,6 +3847,9 @@ struct AAIsDeadFunction : public AAIsDead { ChangeStatus updateImpl(Attributor &A) override; bool isEdgeDead(const BasicBlock *From, const BasicBlock *To) const override { + assert(From->getParent() == getAnchorScope() && + To->getParent() == getAnchorScope() && + "Used AAIsDead of the wrong function"); return isValidState() && !AssumedLiveEdges.count(std::make_pair(From, To)); } diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll index 5eda27957e6b8..cdec3a09fdfb8 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll index 9129d25f6bbaf..954840c1207e0 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll index 9084185ed41b5..2ba15f77ffdbd 100644 --- a/llvm/test/Transforms/Attributor/align.ll +++ b/llvm/test/Transforms/Attributor/align.ll @@ -171,24 +171,30 @@ define internal i8* @f2(i8* readnone %0) local_unnamed_addr #0 { ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2 ; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { -; IS__CGSCC_OPM-NEXT: unreachable -; IS__CGSCC_OPM: 2: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_OPM-NEXT: br i1 [[TMP2]], label [[TMP4:%.*]], label [[TMP3:%.*]] ; IS__CGSCC_OPM: 3: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: br label [[TMP6:%.*]] ; IS__CGSCC_OPM: 4: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: [[TMP5:%.*]] = tail call i8* @f3(i8* nonnull @a2) +; IS__CGSCC_OPM-NEXT: br label [[TMP6]] +; IS__CGSCC_OPM: 6: +; IS__CGSCC_OPM-NEXT: [[TMP7:%.*]] = phi i8* [ undef, [[TMP3]] ], [ [[TMP5]], [[TMP4]] ] +; IS__CGSCC_OPM-NEXT: ret i8* [[TMP7]] ; -; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM: Function Attrs: noinline norecurse nounwind uwtable ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f2 ; IS__CGSCC_NPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { -; IS__CGSCC_NPM-NEXT: unreachable -; IS__CGSCC_NPM: 2: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_NPM-NEXT: br i1 [[TMP2]], label [[TMP4:%.*]], label [[TMP3:%.*]] ; IS__CGSCC_NPM: 3: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: br label [[TMP6:%.*]] ; IS__CGSCC_NPM: 4: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i8* @f3() +; IS__CGSCC_NPM-NEXT: br label [[TMP6]] +; IS__CGSCC_NPM: 6: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i8* [ undef, [[TMP3]] ], [ @a1, [[TMP4]] ] +; IS__CGSCC_NPM-NEXT: ret i8* [[TMP7]] ; %2 = icmp eq i8* %0, null br i1 %2, label %5, label %3 @@ -211,21 +217,23 @@ define internal i8* @f2(i8* readnone %0) local_unnamed_addr #0 { define internal i8* @f3(i8* readnone %0) local_unnamed_addr #0 { ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3 -; IS__CGSCC_OPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { -; IS__CGSCC_OPM-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC_OPM: 2: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { +; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_OPM-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]] ; IS__CGSCC_OPM: 3: -; IS__CGSCC_OPM-NEXT: ret i8* @a1 +; IS__CGSCC_OPM-NEXT: br label [[TMP4]] +; IS__CGSCC_OPM: 4: +; IS__CGSCC_OPM-NEXT: [[TMP5:%.*]] = phi i8* [ @a2, [[TMP3]] ], [ @a1, [[TMP1:%.*]] ] +; IS__CGSCC_OPM-NEXT: ret i8* [[TMP5]] ; -; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f3 -; IS__CGSCC_NPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-SAME: () local_unnamed_addr #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: br label [[TMP2:%.*]] +; IS__CGSCC_NPM: 1: ; IS__CGSCC_NPM-NEXT: unreachable -; IS__CGSCC_NPM: 3: -; IS__CGSCC_NPM-NEXT: ret i8* @a1 +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: ret i8* undef ; %2 = icmp eq i8* %0, null br i1 %2, label %3, label %5 @@ -292,24 +300,30 @@ define internal i8* @f2b(i8* readnone %0) local_unnamed_addr #0 { ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2b ; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { -; IS__CGSCC_OPM-NEXT: unreachable -; IS__CGSCC_OPM: 2: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_OPM-NEXT: br i1 [[TMP2]], label [[TMP4:%.*]], label [[TMP3:%.*]] ; IS__CGSCC_OPM: 3: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: br label [[TMP6:%.*]] ; IS__CGSCC_OPM: 4: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-NEXT: [[TMP5:%.*]] = tail call i8* @f3b(i8* nonnull @a2) +; IS__CGSCC_OPM-NEXT: br label [[TMP6]] +; IS__CGSCC_OPM: 6: +; IS__CGSCC_OPM-NEXT: [[TMP7:%.*]] = phi i8* [ undef, [[TMP3]] ], [ [[TMP5]], [[TMP4]] ] +; IS__CGSCC_OPM-NEXT: ret i8* [[TMP7]] ; -; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM: Function Attrs: noinline norecurse nounwind uwtable ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f2b ; IS__CGSCC_NPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC_NPM-NEXT: unreachable -; IS__CGSCC_NPM: 2: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_NPM-NEXT: br i1 [[TMP2]], label [[TMP4:%.*]], label [[TMP3:%.*]] ; IS__CGSCC_NPM: 3: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: br label [[TMP6:%.*]] ; IS__CGSCC_NPM: 4: -; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = tail call i8* @f3b() +; IS__CGSCC_NPM-NEXT: br label [[TMP6]] +; IS__CGSCC_NPM: 6: +; IS__CGSCC_NPM-NEXT: [[TMP7:%.*]] = phi i8* [ undef, [[TMP3]] ], [ @a1, [[TMP4]] ] +; IS__CGSCC_NPM-NEXT: ret i8* [[TMP7]] ; %2 = icmp eq i8* %0, null br i1 %2, label %5, label %3 @@ -333,21 +347,23 @@ define internal i8* @f3b(i8* readnone %0) local_unnamed_addr #0 { ; ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3b -; IS__CGSCC_OPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { -; IS__CGSCC_OPM-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC_OPM: 2: -; IS__CGSCC_OPM-NEXT: unreachable +; IS__CGSCC_OPM-SAME: (i8* readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR2]] { +; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP0]], null +; IS__CGSCC_OPM-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]] ; IS__CGSCC_OPM: 3: -; IS__CGSCC_OPM-NEXT: ret i8* @a1 +; IS__CGSCC_OPM-NEXT: br label [[TMP4]] +; IS__CGSCC_OPM: 4: +; IS__CGSCC_OPM-NEXT: [[TMP5:%.*]] = phi i8* [ @a2, [[TMP3]] ], [ @a1, [[TMP1:%.*]] ] +; IS__CGSCC_OPM-NEXT: ret i8* [[TMP5]] ; -; IS__CGSCC_NPM: Function Attrs: noinline nounwind uwtable +; IS__CGSCC_NPM: Function Attrs: nofree noinline norecurse nosync nounwind readnone uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f3b -; IS__CGSCC_NPM-SAME: (i8* nonnull readnone [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { -; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] -; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-SAME: () local_unnamed_addr #[[ATTR0]] { +; IS__CGSCC_NPM-NEXT: br label [[TMP2:%.*]] +; IS__CGSCC_NPM: 1: ; IS__CGSCC_NPM-NEXT: unreachable -; IS__CGSCC_NPM: 3: -; IS__CGSCC_NPM-NEXT: ret i8* @a1 +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: ret i8* undef ; %2 = icmp eq i8* %0, null br i1 %2, label %3, label %5 @@ -1131,7 +1147,7 @@ attributes #2 = { null_pointer_is_valid } ; IS__CGSCC_OPM: attributes #[[ATTR12]] = { readonly willreturn } ;. ; IS__CGSCC_NPM: attributes #[[ATTR0]] = { nofree noinline norecurse nosync nounwind readnone uwtable willreturn } -; IS__CGSCC_NPM: attributes #[[ATTR1]] = { noinline nounwind uwtable } +; IS__CGSCC_NPM: attributes #[[ATTR1]] = { noinline norecurse nounwind uwtable } ; IS__CGSCC_NPM: attributes #[[ATTR2]] = { nounwind } ; IS__CGSCC_NPM: attributes #[[ATTR3]] = { nofree nosync nounwind } ; IS__CGSCC_NPM: attributes #[[ATTR4]] = { argmemonly nofree norecurse nosync nounwind readonly willreturn } diff --git a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll index 2c8e29b007e51..f3439816628d7 100644 --- a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll +++ b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals -; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=10 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=10 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -40,8 +40,8 @@ define i32* @external_ret2_nrw(i32* %n0, i32* %r0, i32* %w0) { ; IS__TUNIT____-SAME: (i32* nofree [[N0:%.*]], i32* nofree [[R0:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR0:[0-9]+]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: [[CALL:%.*]] = call i32* @internal_ret0_nw(i32* nofree [[N0]], i32* nofree [[W0]]) #[[ATTR3:[0-9]+]] -; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32* @internal_ret1_rrw(i32* nofree align 4 [[R0]], i32* nofree [[R0]], i32* nofree [[W0]]) #[[ATTR3]] -; IS__TUNIT____-NEXT: [[CALL2:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree [[N0]], i32* nocapture nofree readonly align 4 [[R0]], i32* nofree writeonly "no-capture-maybe-returned" [[W0]]) #[[ATTR3]] +; IS__TUNIT____-NEXT: [[CALL1:%.*]] = call i32* @internal_ret1_rrw(i32* nofree align 4 [[R0]], i32* nofree align 4 [[R0]], i32* nofree [[W0]]) #[[ATTR3]] +; IS__TUNIT____-NEXT: [[CALL2:%.*]] = call i32* @external_sink_ret2_nrw(i32* nofree [[N0]], i32* nocapture nofree readonly [[R0]], i32* nofree writeonly "no-capture-maybe-returned" [[W0]]) #[[ATTR3]] ; IS__TUNIT____-NEXT: [[CALL3:%.*]] = call i32* @internal_ret1_rw(i32* nofree align 4 [[R0]], i32* nofree [[W0]]) #[[ATTR3]] ; IS__TUNIT____-NEXT: ret i32* [[CALL3]] ; @@ -91,7 +91,7 @@ define internal i32* @internal_ret0_nw(i32* %n0, i32* %w0) { ; ; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind ; IS__CGSCC____-LABEL: define {{[^@]+}}@internal_ret0_nw -; IS__CGSCC____-SAME: (i32* nofree returned [[N0:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR0]] { +; IS__CGSCC____-SAME: (i32* nofree [[N0:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR0]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: [[R0:%.*]] = alloca i32, align 4 ; IS__CGSCC____-NEXT: [[R1:%.*]] = alloca i32, align 4 @@ -112,7 +112,7 @@ define internal i32* @internal_ret0_nw(i32* %n0, i32* %w0) { ; IS__CGSCC____-NEXT: br label [[RETURN]] ; IS__CGSCC____: return: ; IS__CGSCC____-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[N0]], [[IF_END]] ], [ [[N0]], [[IF_THEN]] ] -; IS__CGSCC____-NEXT: ret i32* [[N0]] +; IS__CGSCC____-NEXT: ret i32* undef ; entry: %r0 = alloca i32, align 4 @@ -143,7 +143,7 @@ return: ; preds = %if.end, %if.then define internal i32* @internal_ret1_rrw(i32* %r0, i32* %r1, i32* %w0) { ; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind ; IS__TUNIT____-LABEL: define {{[^@]+}}@internal_ret1_rrw -; IS__TUNIT____-SAME: (i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0:%.*]], i32* nofree [[R1:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR0]] { +; IS__TUNIT____-SAME: (i32* nofree noundef nonnull align 4 dereferenceable(4) [[R0:%.*]], i32* nofree align 4 [[R1:%.*]], i32* nofree [[W0:%.*]]) #[[ATTR0]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* [[R0]], align 4 ; IS__TUNIT____-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 @@ -166,7 +166,7 @@ define internal i32* @internal_ret1_rrw(i32* %r0, i32* %r1, i32* %w0) { ; IS__TUNIT____-NEXT: [[CALL8:%.*]] = call i32* @internal_ret0_nw(i32* nofree nonnull align 4 dereferenceable(4) [[R1]], i32* nofree nonnull align 4 dereferenceable(4) [[W0]]) #[[ATTR3]] ; IS__TUNIT____-NEXT: br label [[RETURN]] ; IS__TUNIT____: return: -; IS__TUNIT____-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[CALL8]], [[IF_END]] ], [ [[R1]], [[IF_THEN]] ] +; IS__TUNIT____-NEXT: [[RETVAL_0:%.*]] = phi i32* [ [[R1]], [[IF_END]] ], [ [[R1]], [[IF_THEN]] ] ; IS__TUNIT____-NEXT: ret i32* undef ; ; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll index 52a0146fc2caa..5500e5c4ab1dd 100644 --- a/llvm/test/Transforms/Attributor/value-simplify.ll +++ b/llvm/test/Transforms/Attributor/value-simplify.ll @@ -1099,6 +1099,27 @@ join: uselistorder label %join, { 1, 0 } } +define i1 @test_liveness(i1 %c) { +entry: + br i1 %c, label %t, label %f +t: + br label %f +f: + %p = phi i1 [true, %entry], [false, %t] + %rc1 = call i1 @ret(i1 %p) + ret i1 %rc1 +} + +define internal i1 @ret(i1 %c) { +entry: + br i1 %c, label %t, label %f +t: + br label %f +f: + %p = phi i1 [%c, %entry], [false, %t] + ret i1 %p +} + ;. ; IS__TUNIT_OPM: attributes #[[ATTR0]] = { nofree nosync nounwind willreturn } ; IS__TUNIT_OPM: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind readnone willreturn } From 4fde843cd5c08c16f15d11308bdefc7bd2af0302 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Tue, 1 Mar 2022 15:52:19 -0800 Subject: [PATCH 209/316] [ORC] Set ResolverBlockAddr in EPCIndirectionUtils::writeResolverBlock. Without this, EPCIndirectionUtils::getResolverBlockAddr (and lazy compilation via EPC) won't work. No test case: lli is still using LocalLazyCallThroughManager. I'll revisit this soon when I look at adding lazy compilation support to the ORC runtime. (cherry picked from commit 34e539dcd78ab828210ecf7f7d2e9d2c986511b3) --- llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h | 2 +- llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h b/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h index 92de5882bafe4..354984b540a9f 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h @@ -148,7 +148,7 @@ class EPCIndirectionUtils { std::mutex EPCUIMutex; ExecutorProcessControl &EPC; std::unique_ptr ABI; - JITTargetAddress ResolverBlockAddr; + JITTargetAddress ResolverBlockAddr = 0; FinalizedAlloc ResolverBlock; std::unique_ptr TP; std::unique_ptr LCTM; diff --git a/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp index b901a2d2da236..249f02f36bae4 100644 --- a/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp +++ b/llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp @@ -302,7 +302,8 @@ EPCIndirectionUtils::writeResolverBlock(JITTargetAddress ReentryFnAddr, return Alloc.takeError(); auto SegInfo = Alloc->getSegInfo(MemProt::Read | MemProt::Exec); - ABI->writeResolverCode(SegInfo.WorkingMem.data(), SegInfo.Addr.getValue(), + ResolverBlockAddr = SegInfo.Addr.getValue(); + ABI->writeResolverCode(SegInfo.WorkingMem.data(), ResolverBlockAddr, ReentryFnAddr, ReentryCtxAddr); auto FA = Alloc->finalize(); @@ -310,7 +311,7 @@ EPCIndirectionUtils::writeResolverBlock(JITTargetAddress ReentryFnAddr, return FA.takeError(); ResolverBlock = std::move(*FA); - return SegInfo.Addr.getValue(); + return ResolverBlockAddr; } std::unique_ptr From 6d5afef3a7e6c2c9cc3bdb79e9d0fc88345e0e51 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Tue, 1 Mar 2022 16:43:39 -0800 Subject: [PATCH 210/316] [examples][BuildingAJIT] Use the right layer when adding code in Chapter 3. We were incorrectly using the OptimizeLayer and bypassing the COD layer. (cherry picked from commit 1e16272ba793e5a6e7308898ecf6ef0dc99e2ad3) --- .../Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h index 130310da92748..de169804b06f3 100644 --- a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h +++ b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h @@ -120,7 +120,7 @@ class KaleidoscopeJIT { if (!RT) RT = MainJD.getDefaultResourceTracker(); - return OptimizeLayer.add(RT, std::move(TSM)); + return CODLayer.add(RT, std::move(TSM)); } Expected lookup(StringRef Name) { From f1e7f848bf3e84906fda52975dbcfc6825710987 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 28 Feb 2022 07:45:35 +0100 Subject: [PATCH 211/316] [clang][tests] Fix ve-toolchain tests with CLANG_DEFAULT_UNWINDLIB Otherwise, the driver will insert e.g. -lgcc_s when CLANG_DEFAULT_UNWINDLIB=libgcc is set during the clang build. Differential Revision: https://reviews.llvm.org/D120644 (cherry picked from commit 12d3679256c9a544699f9894c16c2918da17e4af) --- clang/test/Driver/ve-toolchain.c | 1 + clang/test/Driver/ve-toolchain.cpp | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/test/Driver/ve-toolchain.c b/clang/test/Driver/ve-toolchain.c index 35af3c81c4c6f..753dee19fcbfb 100644 --- a/clang/test/Driver/ve-toolchain.c +++ b/clang/test/Driver/ve-toolchain.c @@ -83,6 +83,7 @@ // RUN: %clang -### -target ve-unknown-linux-gnu \ // RUN: --sysroot %S/Inputs/basic_ve_tree \ // RUN: -resource-dir=%S/Inputs/basic_ve_tree/resource_dir \ +// RUN: --unwindlib=none \ // RUN: -fuse-ld=ld \ // RUN: %s 2>&1 | FileCheck -check-prefix=DEF %s diff --git a/clang/test/Driver/ve-toolchain.cpp b/clang/test/Driver/ve-toolchain.cpp index 7447f34b70e0c..4b2b9c5747fe4 100644 --- a/clang/test/Driver/ve-toolchain.cpp +++ b/clang/test/Driver/ve-toolchain.cpp @@ -133,7 +133,8 @@ // RUN: --sysroot %S/Inputs/basic_ve_tree \ // RUN: -fuse-ld=ld \ // RUN: -resource-dir=%S/Inputs/basic_ve_tree/resource_dir \ -// RUN: --stdlib=c++ %s 2>&1 | FileCheck -check-prefix=DEF %s +// RUN: --unwindlib=none \ +// RUN: --stdlib=libc++ %s 2>&1 | FileCheck -check-prefix=DEF %s // DEF: clang{{.*}}" "-cc1" // DEF-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" From 65d53279b1fddeae4bd455d588ea7527aed50bb9 Mon Sep 17 00:00:00 2001 From: Shao-Ce SUN Date: Thu, 3 Mar 2022 14:52:36 +0800 Subject: [PATCH 212/316] [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. Until Zfinx is supported in CodeGen we need to convert all Zfinx register classes to GPR. Remove the zfinx-types.ll test which didn't test anything meaningful since -mattr=zfinx isn't implemented completely in llc. Follow up to D93298. (cherry picked from commit 6cb42cd6669785f3b611106e1b6b38bbe65733a9) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 +++-------- .../RISCV/inline-asm-d-constraint-f.ll | 34 ++++++++++++++ .../RISCV/inline-asm-f-constraint-f.ll | 20 +++++++++ .../RISCV/inline-asm-zfh-constraint-f.ll | 44 +++++++++++++++++++ llvm/test/CodeGen/RISCV/zfinx-types.ll | 19 -------- 5 files changed, 105 insertions(+), 37 deletions(-) delete mode 100644 llvm/test/CodeGen/RISCV/zfinx-types.ll diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 19935caa34dfb..e7672a7652cdd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -10469,24 +10469,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, std::pair Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); - if (Res.second == &RISCV::GPRF32RegClass) { - if (!Subtarget.is64Bit() || VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } - - if (Res.second == &RISCV::GPRF64RegClass || - Res.second == &RISCV::GPRPF64RegClass) { - if (Subtarget.is64Bit() || VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } - - if (Res.second == &RISCV::GPRF16RegClass) { - if (VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } + // If we picked one of the Zfinx register classes, remap it to the GPR class. + // FIXME: When Zfinx is supported in CodeGen this will need to take the + // Subtarget into account. + if (Res.second == &RISCV::GPRF16RegClass || + Res.second == &RISCV::GPRF32RegClass || + Res.second == &RISCV::GPRF64RegClass) + return std::make_pair(Res.first, &RISCV::GPRRegClass); return Res; } diff --git a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll index 37ce0f89e7ec5..2e7ae0847f20f 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll @@ -71,3 +71,37 @@ define double @constraint_f_double_abi_name(double %a) nounwind { %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1) ret double %2 } + +define double @constraint_gpr(double %x) { +; RV32F-LABEL: constraint_gpr: +; RV32F: # %bb.0: +; RV32F-NEXT: addi sp, sp, -32 +; RV32F-NEXT: .cfi_def_cfa_offset 32 +; RV32F-NEXT: sw a0, 8(sp) +; RV32F-NEXT: sw a1, 12(sp) +; RV32F-NEXT: fld ft0, 8(sp) +; RV32F-NEXT: fsd ft0, 24(sp) +; RV32F-NEXT: lw a0, 24(sp) +; RV32F-NEXT: lw a1, 28(sp) +; RV32F-NEXT: #APP +; RV32F-NEXT: mv a0, a0 +; RV32F-NEXT: #NO_APP +; RV32F-NEXT: sw a1, 20(sp) +; RV32F-NEXT: sw a0, 16(sp) +; RV32F-NEXT: fld ft0, 16(sp) +; RV32F-NEXT: fsd ft0, 8(sp) +; RV32F-NEXT: lw a0, 8(sp) +; RV32F-NEXT: lw a1, 12(sp) +; RV32F-NEXT: addi sp, sp, 32 +; RV32F-NEXT: ret +; +; RV64F-LABEL: constraint_gpr: +; RV64F: # %bb.0: +; RV64F-NEXT: .cfi_def_cfa_offset 0 +; RV64F-NEXT: #APP +; RV64F-NEXT: mv a0, a0 +; RV64F-NEXT: #NO_APP +; RV64F-NEXT: ret + %1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x) + ret double %1 +} diff --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll index 07d6d1a365cd8..d6df31e878313 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll @@ -63,3 +63,23 @@ define float @constraint_f_float_abi_name(float %a) nounwind { %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1) ret float %2 } + +define float @constraint_gpr(float %x) { +; RV32F-LABEL: constraint_gpr: +; RV32F: # %bb.0: +; RV32F-NEXT: .cfi_def_cfa_offset 0 +; RV32F-NEXT: #APP +; RV32F-NEXT: mv a0, a0 +; RV32F-NEXT: #NO_APP +; RV32F-NEXT: ret +; +; RV64F-LABEL: constraint_gpr: +; RV64F: # %bb.0: +; RV64F-NEXT: .cfi_def_cfa_offset 0 +; RV64F-NEXT: #APP +; RV64F-NEXT: mv a0, a0 +; RV64F-NEXT: #NO_APP +; RV64F-NEXT: ret + %1 = tail call float asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(float %x) + ret float %1 +} diff --git a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll index dae55de1198ff..91e7011407425 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll @@ -111,3 +111,47 @@ define half @constraint_f_half_abi_name(half %a) nounwind { %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1) ret half %2 } + +define half @constraint_gpr(half %x) { +; RV32ZFH-LABEL: constraint_gpr: +; RV32ZFH: # %bb.0: +; RV32ZFH-NEXT: .cfi_def_cfa_offset 0 +; RV32ZFH-NEXT: fmv.x.h a0, fa0 +; RV32ZFH-NEXT: #APP +; RV32ZFH-NEXT: mv a0, a0 +; RV32ZFH-NEXT: #NO_APP +; RV32ZFH-NEXT: fmv.h.x fa0, a0 +; RV32ZFH-NEXT: ret +; +; RV64ZFH-LABEL: constraint_gpr: +; RV64ZFH: # %bb.0: +; RV64ZFH-NEXT: .cfi_def_cfa_offset 0 +; RV64ZFH-NEXT: fmv.x.h a0, fa0 +; RV64ZFH-NEXT: #APP +; RV64ZFH-NEXT: mv a0, a0 +; RV64ZFH-NEXT: #NO_APP +; RV64ZFH-NEXT: fmv.h.x fa0, a0 +; RV64ZFH-NEXT: ret +; +; RV32DZFH-LABEL: constraint_gpr: +; RV32DZFH: # %bb.0: +; RV32DZFH-NEXT: .cfi_def_cfa_offset 0 +; RV32DZFH-NEXT: fmv.x.h a0, fa0 +; RV32DZFH-NEXT: #APP +; RV32DZFH-NEXT: mv a0, a0 +; RV32DZFH-NEXT: #NO_APP +; RV32DZFH-NEXT: fmv.h.x fa0, a0 +; RV32DZFH-NEXT: ret +; +; RV64DZFH-LABEL: constraint_gpr: +; RV64DZFH: # %bb.0: +; RV64DZFH-NEXT: .cfi_def_cfa_offset 0 +; RV64DZFH-NEXT: fmv.x.h a0, fa0 +; RV64DZFH-NEXT: #APP +; RV64DZFH-NEXT: mv a0, a0 +; RV64DZFH-NEXT: #NO_APP +; RV64DZFH-NEXT: fmv.h.x fa0, a0 +; RV64DZFH-NEXT: ret + %1 = tail call half asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(half %x) + ret half %1 +} diff --git a/llvm/test/CodeGen/RISCV/zfinx-types.ll b/llvm/test/CodeGen/RISCV/zfinx-types.ll deleted file mode 100644 index 9cbc7d9ce219b..0000000000000 --- a/llvm/test/CodeGen/RISCV/zfinx-types.ll +++ /dev/null @@ -1,19 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RVZFINX %s -; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RVZFINX %s - -define float @test_float(float %x) { -; RVZFINX-LABEL: test_float: -; RVZFINX: # %bb.0: -; RVZFINX-NEXT: .cfi_def_cfa_offset 0 -; RVZFINX-NEXT: li a0, 0 -; RVZFINX-NEXT: #APP -; RVZFINX-NEXT: mv a0, a0 -; RVZFINX-NEXT: #NO_APP -; RVZFINX-NEXT: li a0, 0 -; RVZFINX-NEXT: ret - %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00) - ret float 0.000000e+00 -} From ce1e90fc8dbacdaff0310e50090ec3cfdfce4def Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Thu, 3 Mar 2022 08:41:48 -0600 Subject: [PATCH 213/316] [docs] Add PowerPC release notes for LLVM 14 Reviewed By: jsji, #libc, ldionne Differential Revision: https://reviews.llvm.org/D120907 --- clang/docs/ReleaseNotes.rst | 21 ++++++++++++++++++++- libcxx/docs/ReleaseNotes.rst | 3 +++ llvm/docs/ReleaseNotes.rst | 33 ++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a6cbf25fd48a5..0b723d67ec4ae 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -51,7 +51,19 @@ Major New Features For more details refer to :ref:`the SPIR-V support section `. - Completed support of OpenCL C 3.0 and C++ for OpenCL 2021 at experimental state. -- ... + +- Prebuilt AIX7.2 TL5 SP3+ binary available with following notes and + limitations: + - C++ driver modes use the system libc++ headers. These headers are included + in the optional ``libc++.adt.include`` fileset on AIX. + - LTO, although not disabled, is not recommended. + - Shared libraries builds (``-shared``) must use explicit symbol export + options and/or export lists (e.g., with ``-bE:``) on the link step. Clang + currently will not automatically generate symbol export lists as implicit + linker inputs. + +- ``float.h`` now exposes (in hosted mode) extensions made available from the + AIX system header. Improvements to Clang's diagnostics ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -79,6 +91,9 @@ Non-comprehensive list of changes in this release - The ``-E -P`` preprocessor output now always omits blank lines, matching gcc behaviour. Previously, up to 8 consecutive blank lines could appear in the output. +- AIX platform-related predefined macros added: + ``_ARCH_PPC64``, ``__HOS_AIX__``, ``__PPC``, ``__THW_BIG_ENDIAN__``, + ``__THW_PPC__``, and ``__powerpc`` New Compiler Flags ------------------ @@ -103,6 +118,8 @@ New Compiler Flags for `ccache `_ and `sccache `_ are under review. +- Clang now accepts "allowlist" spelling for ``-objcmt-allowlist-dir-path``. + Deprecated Compiler Flags ------------------------- @@ -169,6 +186,8 @@ Attribute Changes in Clang attributes, but will now issue an error due to the expansion of the predefined ``__clang__`` macro. +- Improved handling of ``__attribute__((__aligned__))`` on AIX to match GCC. + Windows Support --------------- diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index b7e07d17755a0..8a5f7099b82a8 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -77,6 +77,9 @@ New Features - More C++2b features have been implemented. :doc:`Status/Cxx2b` has the full overview of libc++'s C++2b implementation status. +- 16-bit ``wchar_t`` handling added for ``codecvt_utf8``, ``codecvt_utf16`` and + ``codecvt_utf8_utf16``. + API Changes ----------- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index c6e6e445f709d..4c6b2fac99ca6 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -105,7 +105,31 @@ Changes to the Hexagon Target Changes to the PowerPC Target ----------------------------- -During this release ... +Linux improvements: +* Provided a number of builtins for compatibility with the XL compiler. +* Allow MMA builtin types in pre-P10 compilation units. +* Add support for Return Oriented Programming (ROP) protection for 32 bit. +* Refactored code to use more inclusive language. +* Switched to LLD as the default linker for pre-built Linux binaries. +* Enabled IEEE quad long double on Linux via ``PPC_LINUX_DEFAULT_IEEELONGDOUBLE`` + in cmake config. + * Added ``__ibm128`` type to represent IBM double-double format, also available + as ``__attribute__((mode(IF)))``. + * ``-mfloat128`` can now be used in Linux subtargets with VSX enabled. +* Added quadword atomic load/store support in codegen; not enabled by default. +* Codegen improvements for splat load, byval parameter, stack lowering, etc. +* Implemented P10 instruction scheduling model. +* Implemented P10 instruction fusion pairs. +* Improved handling of ``#pragma clang loop unroll_and_jam``. +* Various bug fixes. + +AIX Support/improvements: +* variadic (ellipsis) functions with C complex types are now supported. +* Added toc-data support for AIX 64-bit. +* Added toc-data support for read-only globals. +* Updated default target on AIX from pwr4 to pwr7. +* AIX 64-bit now use fast-isel for O0. +* Added DWARF support for 32-bit XCOFF. Changes to the X86 Target ------------------------- @@ -224,6 +248,13 @@ Changes to the LLVM tools * llvm-readobj now supports several dump styles (``--needed-libs, --relocs, --syms``) for XCOFF. * llvm-symbolizer now supports `--debuginfod `. (`D113717 `_) +* ``llvm-cov`` now accepts "allowlist" spelling for ``-name-allowlist``. +* ``llvm-nm`` now supports XCOFF object files. +* Added ``--needed-libs``, aux header, and symbols support in ``llvm-readobj``. +* Added ``--symbolize-operands`` support in ``llvm-objdump``. +* Tools that read archive files now support reading AIX big format archive files. +* Added dump section support in ``obj2yaml``. +* Added ``yaml2obj`` support for 64-bit XCOFF. Changes to LLDB --------------------------------- From acf67b7a0dfc867d93e6f18d9d98239bcaeb28e2 Mon Sep 17 00:00:00 2001 From: Hubert Tong Date: Thu, 3 Mar 2022 14:09:06 -0500 Subject: [PATCH 214/316] [docs] Tweak wording of note re: LTO on AIX --- clang/docs/ReleaseNotes.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 0b723d67ec4ae..d4641b0bc476f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -56,7 +56,8 @@ Major New Features limitations: - C++ driver modes use the system libc++ headers. These headers are included in the optional ``libc++.adt.include`` fileset on AIX. - - LTO, although not disabled, is not recommended. + - LTO, although not disabled, is not meaningfully functional for practical + use. - Shared libraries builds (``-shared``) must use explicit symbol export options and/or export lists (e.g., with ``-bE:``) on the link step. Clang currently will not automatically generate symbol export lists as implicit From aab33202d23999788df475fc07bb14cfabf5db52 Mon Sep 17 00:00:00 2001 From: Hubert Tong Date: Thu, 3 Mar 2022 14:27:15 -0500 Subject: [PATCH 215/316] [docs] PowerPC release notes formatting/grammar fixes At least insofar as GitHub's rendering is concerned, the lists need a blank line prior to the first item. --- llvm/docs/ReleaseNotes.rst | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 4c6b2fac99ca6..28282c54e7390 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -106,6 +106,7 @@ Changes to the PowerPC Target ----------------------------- Linux improvements: + * Provided a number of builtins for compatibility with the XL compiler. * Allow MMA builtin types in pre-P10 compilation units. * Add support for Return Oriented Programming (ROP) protection for 32 bit. @@ -113,9 +114,11 @@ Linux improvements: * Switched to LLD as the default linker for pre-built Linux binaries. * Enabled IEEE quad long double on Linux via ``PPC_LINUX_DEFAULT_IEEELONGDOUBLE`` in cmake config. + * Added ``__ibm128`` type to represent IBM double-double format, also available as ``__attribute__((mode(IF)))``. * ``-mfloat128`` can now be used in Linux subtargets with VSX enabled. + * Added quadword atomic load/store support in codegen; not enabled by default. * Codegen improvements for splat load, byval parameter, stack lowering, etc. * Implemented P10 instruction scheduling model. @@ -124,11 +127,12 @@ Linux improvements: * Various bug fixes. AIX Support/improvements: -* variadic (ellipsis) functions with C complex types are now supported. + +* Variadic (ellipsis) functions with C complex types are now supported. * Added toc-data support for AIX 64-bit. * Added toc-data support for read-only globals. * Updated default target on AIX from pwr4 to pwr7. -* AIX 64-bit now use fast-isel for O0. +* AIX 64-bit code generation now uses fast-isel for O0. * Added DWARF support for 32-bit XCOFF. Changes to the X86 Target From 8f9f84c6873ec00babd51da4a1c3c6651e611d18 Mon Sep 17 00:00:00 2001 From: Hubert Tong Date: Thu, 3 Mar 2022 14:34:46 -0500 Subject: [PATCH 216/316] [docs] clang/docs/ReleaseNotes.rst: Add blank line At least insofar as GitHub's rendering is concerned, the nested list needs a blank line prior to its first item. --- clang/docs/ReleaseNotes.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index d4641b0bc476f..4eaa589b542dd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -54,6 +54,7 @@ Major New Features - Prebuilt AIX7.2 TL5 SP3+ binary available with following notes and limitations: + - C++ driver modes use the system libc++ headers. These headers are included in the optional ``libc++.adt.include`` fileset on AIX. - LTO, although not disabled, is not meaningfully functional for practical From 09546e1b5103a9d4c148e6af0ace1673ab55b893 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Thu, 3 Mar 2022 21:39:13 +0100 Subject: [PATCH 217/316] [libc++][doc] Update the release notes. Fixes the incorrect removal version of the experimental coroutine header. Reviewed By: #libc, ldionne Differential Revision: https://reviews.llvm.org/D120935 --- libcxx/docs/ReleaseNotes.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index 8a5f7099b82a8..20303382d790c 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -148,7 +148,7 @@ API Changes - The ```` header is deprecated, as is any use of coroutines without C++20. Use C++20's ```` header instead. The ```` header will be removed - in LLVM 15. + in LLVM 16. - ``_VSTD`` is now an alias for ``std`` instead of ``std::_LIBCPP_ABI_NAMESPACE``. This is technically not a functional change, except for folks that might have been From 0826716786cd4a8c7cbcb8c01e4d9fac46b7a17a Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Thu, 3 Mar 2022 13:42:10 -0800 Subject: [PATCH 218/316] [Mips] support "sp" named register After Linux kernel commit commit 200ed341b864 ("mips: Implement "current_stack_pointer"") We observe the following build error when compiling the Linux kernel targeting Mips: fatal error: error in backend: Invalid register name global variable Fixes: https://github.com/llvm/llvm-project/issues/54174 Link: https://github.com/ClangBuiltLinux/linux/issues/1608 Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D120926 (cherry picked from commit e0adc3be132922776a867a623959e176f29f9965) --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 13 ++++---- llvm/test/CodeGen/Mips/named-register-n32.ll | 31 +++++++++++++------- llvm/test/CodeGen/Mips/named-register-n64.ll | 30 +++++++++++++------ llvm/test/CodeGen/Mips/named-register-o32.ll | 30 +++++++++++++------ 4 files changed, 70 insertions(+), 34 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 0c2e129b8f1fc..8534a0ad886ec 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -4732,18 +4732,19 @@ MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, Register MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { - // Named registers is expected to be fairly rare. For now, just support $28 - // since the linux kernel uses it. + // The Linux kernel uses $28 and sp. if (Subtarget.isGP64bit()) { Register Reg = StringSwitch(RegName) - .Case("$28", Mips::GP_64) - .Default(Register()); + .Case("$28", Mips::GP_64) + .Case("sp", Mips::SP_64) + .Default(Register()); if (Reg) return Reg; } else { Register Reg = StringSwitch(RegName) - .Case("$28", Mips::GP) - .Default(Register()); + .Case("$28", Mips::GP) + .Case("sp", Mips::SP) + .Default(Register()); if (Reg) return Reg; } diff --git a/llvm/test/CodeGen/Mips/named-register-n32.ll b/llvm/test/CodeGen/Mips/named-register-n32.ll index 5074438255ba7..112e04e14b2ac 100644 --- a/llvm/test/CodeGen/Mips/named-register-n32.ll +++ b/llvm/test/CodeGen/Mips/named-register-n32.ll @@ -1,18 +1,29 @@ -; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \ +; RUN: -target-abi n32 < %s | FileCheck %s -define i32* @get_gp() { -entry: - %0 = call i64 @llvm.read_register.i64(metadata !0) - %1 = trunc i64 %0 to i32 - %2 = inttoptr i32 %1 to i32* - ret i32* %2 -} +declare i64 @llvm.read_register.i64(metadata) +define i64 @get_gp() { ; CHECK-LABEL: get_gp: -; CHECK: sll $2, $gp, 0 +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $gp + %1 = call i64 @llvm.read_register.i64(metadata !0) + ret i64 %1 +} -declare i64 @llvm.read_register.i64(metadata) +define i64 @get_sp() { +; CHECK-LABEL: get_sp: +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $sp + %1 = call i64 @llvm.read_register.i64(metadata !1) + ret i64 %1 +} !llvm.named.register.$28 = !{!0} +!llvm.named.register.sp = !{!1} !0 = !{!"$28"} +!1 = !{!"sp"} diff --git a/llvm/test/CodeGen/Mips/named-register-n64.ll b/llvm/test/CodeGen/Mips/named-register-n64.ll index c771b2b1d0b57..42d9ba1e1f15c 100644 --- a/llvm/test/CodeGen/Mips/named-register-n64.ll +++ b/llvm/test/CodeGen/Mips/named-register-n64.ll @@ -1,17 +1,29 @@ -; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \ +; RUN: < %s | FileCheck %s -define i32* @get_gp() { -entry: - %0 = call i64 @llvm.read_register.i64(metadata !0) - %1 = inttoptr i64 %0 to i32* - ret i32* %1 -} +declare i64 @llvm.read_register.i64(metadata) +define i64 @get_gp() { ; CHECK-LABEL: get_gp: -; CHECK: move $2, $gp +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $gp + %1 = call i64 @llvm.read_register.i64(metadata !0) + ret i64 %1 +} -declare i64 @llvm.read_register.i64(metadata) +define i64 @get_sp() { +; CHECK-LABEL: get_sp: +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $sp + %1 = call i64 @llvm.read_register.i64(metadata !1) + ret i64 %1 +} !llvm.named.register.$28 = !{!0} +!llvm.named.register.sp = !{!1} !0 = !{!"$28"} +!1 = !{!"sp"} diff --git a/llvm/test/CodeGen/Mips/named-register-o32.ll b/llvm/test/CodeGen/Mips/named-register-o32.ll index 3e74e0c3846f7..280c56e4db6a4 100644 --- a/llvm/test/CodeGen/Mips/named-register-o32.ll +++ b/llvm/test/CodeGen/Mips/named-register-o32.ll @@ -1,17 +1,29 @@ -; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls \ +; RUN: < %s | FileCheck %s -define i32* @get_gp() { -entry: - %0 = call i32 @llvm.read_register.i32(metadata !0) - %1 = inttoptr i32 %0 to i32* - ret i32* %1 -} +declare i32 @llvm.read_register.i32(metadata) +define i32 @get_gp() { ; CHECK-LABEL: get_gp: -; CHECK: move $2, $gp +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $gp + %1 = call i32 @llvm.read_register.i32(metadata !0) + ret i32 %1 +} -declare i32 @llvm.read_register.i32(metadata) +define i32 @get_sp() { +; CHECK-LABEL: get_sp: +; CHECK: # %bb.0: +; CHECK-NEXT: jr $ra +; CHECK-NEXT: move $2, $sp + %1 = call i32 @llvm.read_register.i32(metadata !1) + ret i32 %1 +} !llvm.named.register.$28 = !{!0} +!llvm.named.register.sp = !{!1} !0 = !{!"$28"} +!1 = !{!"sp"} From 0205cc086e506fe85fdc48734e9a297299160eb1 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 4 Mar 2022 13:16:29 -0500 Subject: [PATCH 219/316] [OpenMP][FIX] Ensure custom state machine works The custom state machine had a check for surplus threads that filtered the main thread if the kernel was executed by a single warp only. We now first check for the main thread, then for surplus threads, avoiding to filter the former out. Fixes #54214. Reviewed By: jhuber6 Differential Revision: https://reviews.llvm.org/D121011 (cherry picked from commit f9c2d6005ef06a37a99e324e72ce247d0472cf4e) --- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 38 +++--- .../OpenMP/custom_state_machines.ll | 112 +++++++-------- llvm/test/Transforms/OpenMP/spmdization.ll | 128 +++++++++--------- .../Transforms/OpenMP/spmdization_guarding.ll | 8 +- ...mdization_guarding_two_reaching_kernels.ll | 8 +- 5 files changed, 147 insertions(+), 147 deletions(-) diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index 5113c0c67acc6..7205ae178d21f 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -3712,9 +3712,9 @@ struct AAKernelInfoFunction : AAKernelInfo { // __kmpc_get_hardware_num_threads_in_block(); // WarpSize = __kmpc_get_warp_size(); // BlockSize = BlockHwSize - WarpSize; - // if (InitCB >= BlockSize) return; - // IsWorkerCheckBB: bool IsWorker = InitCB >= 0; + // IsWorkerCheckBB: bool IsWorker = InitCB != -1; // if (IsWorker) { + // if (InitCB >= BlockSize) return; // SMBeginBB: __kmpc_barrier_simple_generic(...); // void *WorkFn; // bool Active = __kmpc_kernel_parallel(&WorkFn); @@ -3771,6 +3771,13 @@ struct AAKernelInfoFunction : AAKernelInfo { ReturnInst::Create(Ctx, StateMachineFinishedBB)->setDebugLoc(DLoc); InitBB->getTerminator()->eraseFromParent(); + Instruction *IsWorker = + ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_NE, KernelInitCB, + ConstantInt::get(KernelInitCB->getType(), -1), + "thread.is_worker", InitBB); + IsWorker->setDebugLoc(DLoc); + BranchInst::Create(IsWorkerCheckBB, UserCodeEntryBB, IsWorker, InitBB); + Module &M = *Kernel->getParent(); auto &OMPInfoCache = static_cast(A.getInfoCache()); FunctionCallee BlockHwSizeFn = @@ -3780,29 +3787,22 @@ struct AAKernelInfoFunction : AAKernelInfo { OMPInfoCache.OMPBuilder.getOrCreateRuntimeFunction( M, OMPRTL___kmpc_get_warp_size); CallInst *BlockHwSize = - CallInst::Create(BlockHwSizeFn, "block.hw_size", InitBB); + CallInst::Create(BlockHwSizeFn, "block.hw_size", IsWorkerCheckBB); OMPInfoCache.setCallingConvention(BlockHwSizeFn, BlockHwSize); BlockHwSize->setDebugLoc(DLoc); - CallInst *WarpSize = CallInst::Create(WarpSizeFn, "warp.size", InitBB); + CallInst *WarpSize = + CallInst::Create(WarpSizeFn, "warp.size", IsWorkerCheckBB); OMPInfoCache.setCallingConvention(WarpSizeFn, WarpSize); WarpSize->setDebugLoc(DLoc); - Instruction *BlockSize = - BinaryOperator::CreateSub(BlockHwSize, WarpSize, "block.size", InitBB); + Instruction *BlockSize = BinaryOperator::CreateSub( + BlockHwSize, WarpSize, "block.size", IsWorkerCheckBB); BlockSize->setDebugLoc(DLoc); - Instruction *IsMainOrWorker = - ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_SLT, KernelInitCB, - BlockSize, "thread.is_main_or_worker", InitBB); + Instruction *IsMainOrWorker = ICmpInst::Create( + ICmpInst::ICmp, llvm::CmpInst::ICMP_SLT, KernelInitCB, BlockSize, + "thread.is_main_or_worker", IsWorkerCheckBB); IsMainOrWorker->setDebugLoc(DLoc); - BranchInst::Create(IsWorkerCheckBB, StateMachineFinishedBB, IsMainOrWorker, - InitBB); - - Instruction *IsWorker = - ICmpInst::Create(ICmpInst::ICmp, llvm::CmpInst::ICMP_NE, KernelInitCB, - ConstantInt::get(KernelInitCB->getType(), -1), - "thread.is_worker", IsWorkerCheckBB); - IsWorker->setDebugLoc(DLoc); - BranchInst::Create(StateMachineBeginBB, UserCodeEntryBB, IsWorker, - IsWorkerCheckBB); + BranchInst::Create(StateMachineBeginBB, StateMachineFinishedBB, + IsMainOrWorker, IsWorkerCheckBB); // Create local storage for the work function pointer. const DataLayout &DL = M.getDataLayout(); diff --git a/llvm/test/Transforms/OpenMP/custom_state_machines.ll b/llvm/test/Transforms/OpenMP/custom_state_machines.ll index c0f51d3bbcf64..2e68c60a3cff2 100644 --- a/llvm/test/Transforms/OpenMP/custom_state_machines.ll +++ b/llvm/test/Transforms/OpenMP/custom_state_machines.ll @@ -912,14 +912,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1037,14 +1037,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1188,14 +1188,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1314,14 +1314,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1438,14 +1438,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1562,14 +1562,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1668,14 +1668,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1888,14 +1888,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2012,14 +2012,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2162,14 +2162,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2287,14 +2287,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2410,14 +2410,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2533,14 +2533,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2638,14 +2638,14 @@ attributes #9 = { convergent nounwind readonly willreturn } ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) diff --git a/llvm/test/Transforms/OpenMP/spmdization.ll b/llvm/test/Transforms/OpenMP/spmdization.ll index 752ccff9354ad..2166e01c01b8d 100644 --- a/llvm/test/Transforms/OpenMP/spmdization.ll +++ b/llvm/test/Transforms/OpenMP/spmdization.ll @@ -208,14 +208,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_l5() #0 { ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -262,14 +262,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_l5() #0 { ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -553,14 +553,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l2 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -607,14 +607,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l2 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -916,14 +916,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -970,14 +970,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -1304,14 +1304,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_g ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1358,14 +1358,14 @@ define weak void @__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_g ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -1693,14 +1693,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1740,14 +1740,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 ; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -1786,14 +1786,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1833,14 +1833,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65() #0 ; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -1930,14 +1930,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 { ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5) ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU: is_worker_check: ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU: is_worker_check: -; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU: worker_state_machine.begin: ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -1986,14 +1986,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 { ; NVPTX-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8 ; NVPTX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; NVPTX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX: is_worker_check: ; NVPTX-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX: is_worker_check: -; NVPTX-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX: worker_state_machine.begin: ; NVPTX-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) @@ -2041,14 +2041,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 { ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5) ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED: is_worker_check: ; AMDGPU-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; AMDGPU-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; AMDGPU-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; AMDGPU-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; AMDGPU-DISABLED: is_worker_check: -; AMDGPU-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; AMDGPU-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; AMDGPU-DISABLED: worker_state_machine.begin: ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; AMDGPU-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WORK_FN_ADDR]] to i8** @@ -2097,14 +2097,14 @@ define weak void @__omp_offloading_fd02_2044372e_do_not_spmdize_task_l74() #0 { ; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8 ; NVPTX-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8 ; NVPTX-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED: is_worker_check: ; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; NVPTX-DISABLED: is_worker_check: -; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; NVPTX-DISABLED: worker_state_machine.begin: ; NVPTX-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; NVPTX-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) diff --git a/llvm/test/Transforms/OpenMP/spmdization_guarding.ll b/llvm/test/Transforms/OpenMP/spmdization_guarding.ll index b2c4aca9d5e53..8d200a560f366 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_guarding.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_guarding.ll @@ -178,14 +178,14 @@ define weak void @__omp_offloading_2a_fbfa7a_sequential_loop_l6(i32* %x, i64 %N) ; CHECK-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8 ; CHECK-DISABLED-NEXT: [[N_ADDR_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[N]] to i32 ; CHECK-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* nonnull @[[GLOB1]], i8 1, i1 false, i1 true) #[[ATTR4:[0-9]+]] +; CHECK-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; CHECK-DISABLED: is_worker_check: ; CHECK-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; CHECK-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; CHECK-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; CHECK-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK-DISABLED: is_worker_check: -; CHECK-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; CHECK-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; CHECK-DISABLED: worker_state_machine.begin: ; CHECK-DISABLED-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; CHECK-DISABLED-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) diff --git a/llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll b/llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll index 2112a22bc8d6a..1c78a53b3c8a7 100644 --- a/llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll +++ b/llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll @@ -55,14 +55,14 @@ define weak void @__omp_offloading_2b_10393b5_spmd_l12() #0 { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1 false, i1 true) +; CHECK-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 +; CHECK-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; CHECK: is_worker_check: ; CHECK-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() ; CHECK-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size() ; CHECK-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]] ; CHECK-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]] -; CHECK-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] -; CHECK: is_worker_check: -; CHECK-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1 -; CHECK-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[THREAD_USER_CODE_CHECK:%.*]] +; CHECK-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], label [[WORKER_STATE_MACHINE_FINISHED:%.*]] ; CHECK: worker_state_machine.begin: ; CHECK-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) ; CHECK-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_ADDR]]) From 1e3d5ccab6b616baa91448462951b43f28bd5601 Mon Sep 17 00:00:00 2001 From: Konrad Kleine Date: Fri, 11 Feb 2022 11:50:33 +0100 Subject: [PATCH 220/316] Add cmake to source release tarballs I've split the git archive generation into three steps: 1. generate pure tarball 2. append top-level cmake directory to all tarballs 3. compress the archive This was inspired by D118252 and can be considered an alternative approach for all projects to have access to the shared cmake directory when building in standalone mode. When generating source tarballs on my local laptop it takes 9 minutes and 45 seconds WITH this patch applied. When this patch is not applied, it takes 9minutes and 38 seconds. That means, this patch introduces a slowdown of 7 seconds, which seems fair. Reviewed By: tstellar Differential Revision: https://reviews.llvm.org/D118481 --- llvm/utils/release/export.sh | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/llvm/utils/release/export.sh b/llvm/utils/release/export.sh index 3a318aee10d3d..43bb71d09bea8 100755 --- a/llvm/utils/release/export.sh +++ b/llvm/utils/release/export.sh @@ -131,7 +131,14 @@ export_sources() { for proj in $projects; do echo "Creating tarball for $proj ..." pushd $llvm_src_dir/$proj - git archive --prefix=$proj-$release$rc.src/ $tree_id . | xz >$target_dir/$(template_file $proj) + target_archive_file=$target_dir/$(template_file $proj) + trap "rm -fv $target_archive_file.tmp" EXIT + git archive --prefix=$proj-$release$rc.src/ -o $target_archive_file.tmp $tree_id . + # Get relative path to top-level cmake directory to be packaged + # alongside the project. Append that path to the tarball. + cmake_rel_path=$(realpath --relative-to=. $llvm_src_dir/cmake) + tar --append -f $target_archive_file.tmp $cmake_rel_path + cat $target_archive_file.tmp | xz > $target_archive_file popd done } From 9d54fe21c67fdb76bfd95c329a31bda2cb91c520 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Mon, 7 Mar 2022 10:57:39 +0000 Subject: [PATCH 221/316] [docs] Add RISC-V release notes for LLVM 14 Differential Revision: https://reviews.llvm.org/D120047 --- llvm/docs/ReleaseNotes.rst | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 28282c54e7390..e8934f79181a7 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -135,6 +135,30 @@ AIX Support/improvements: * AIX 64-bit code generation now uses fast-isel for O0. * Added DWARF support for 32-bit XCOFF. +Changes to the RISC-V Target +---------------------------- + +* Codegen improvements for RV64 around the selection of addw/subw/mulw/slliw + instructions and removal of redundant sext.w instructions (using the new + RISCVSExtWRemoval pass). +* The various RISC-V vector extensions were updated to version 1.0 and are no + longer experimental. +* The Zba, Zbb, Zbc, and Zbs bit-manipulation extensions were updated to + version 1.0 and are no longer experimental. +* Added MC layer support for the ratified scalar cryptography extensions. +* The Zfh and Zfhmin extensions for half-precision floating point were updated + to version 1.0 and are no longer experimental. +* Added support for the ``.insn`` directive. +* Various improvements to immediate materialisation, including when + bit-manipulation extensions are enabled. Additionally, the constant pool is + now used for large integers. +* Added support for constrained FP intrinsics for scalar types. +* Added support for CSRs introduced in the Sscofpmf, Smstateen, and Sstc + extensions. +* The experimental 'Zbproposedc' extension was removed, as was the 'B' + extension (including all bit-manipulation sub-extensions). Individual 'Zb*' + extensions should be used instead. + Changes to the X86 Target ------------------------- From f6a4df3a0a3d570c65231187a730595b1cf8dc71 Mon Sep 17 00:00:00 2001 From: Sam Clegg Date: Thu, 24 Feb 2022 14:37:40 -0800 Subject: [PATCH 222/316] [WebAssembly] Covert llvm/test/MC/WebAssembly/reloc-code.ll to asm. NFC Also increase coverage of call_indirect via explict function table (enabled when reference types is enabled) in llvm/test/CodeGen/WebAssembly/call-indirect.ll (I believe this was an oversight that it was not added in https://reviews.llvm.org/D90948) Differential Revision: https://reviews.llvm.org/D120521 (cherry picked from commit db7b1af8ef8f59600cbb6e529164acdbe4c8f0a2) --- .../test/CodeGen/WebAssembly/call-indirect.ll | 6 +- llvm/test/MC/WebAssembly/reloc-code.ll | 110 --------------- llvm/test/MC/WebAssembly/reloc-code.s | 129 ++++++++++++++++++ 3 files changed, 133 insertions(+), 112 deletions(-) delete mode 100644 llvm/test/MC/WebAssembly/reloc-code.ll create mode 100644 llvm/test/MC/WebAssembly/reloc-code.s diff --git a/llvm/test/CodeGen/WebAssembly/call-indirect.ll b/llvm/test/CodeGen/WebAssembly/call-indirect.ll index 7a174318d4732..d5bb749d8a1d7 100644 --- a/llvm/test/CodeGen/WebAssembly/call-indirect.ll +++ b/llvm/test/CodeGen/WebAssembly/call-indirect.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -asm-verbose=false -O2 | FileCheck --check-prefix=CHECK %s +; RUN: llc < %s -asm-verbose=false -O2 | FileCheck --check-prefixes=CHECK,NOREF %s +; RUN: llc < %s -asm-verbose=false -mattr=+reference-types -O2 | FileCheck --check-prefixes=CHECK,REF %s ; RUN: llc < %s -asm-verbose=false -O2 --filetype=obj | obj2yaml | FileCheck --check-prefix=OBJ %s ; Test that compilation units with call_indirect but without any @@ -9,7 +10,8 @@ target triple = "wasm32-unknown-unknown" ; CHECK-LABEL: call_indirect_void: ; CHECK-NEXT: .functype call_indirect_void (i32) -> () ; CHECK-NEXT: local.get 0 -; CHECK-NEXT: call_indirect () -> () +; REF: call_indirect __indirect_function_table, () -> () +; NOREF: call_indirect () -> () ; CHECK-NEXT: end_function define void @call_indirect_void(void ()* %callee) { call void %callee() diff --git a/llvm/test/MC/WebAssembly/reloc-code.ll b/llvm/test/MC/WebAssembly/reloc-code.ll deleted file mode 100644 index e80fbcf80cd35..0000000000000 --- a/llvm/test/MC/WebAssembly/reloc-code.ll +++ /dev/null @@ -1,110 +0,0 @@ -; RUN: llc -filetype=obj %s -o - | llvm-readobj -r --expand-relocs - | FileCheck %s -; RUN: llc -filetype=obj -mattr=+reference-types %s -o - | llvm-readobj -r --expand-relocs - | FileCheck --check-prefix=REF %s - -target triple = "wasm32-unknown-unknown" - -; Pointers to functions of two different types -@a = global i64 ()* inttoptr (i64 5 to i64 ()*), align 8 -@b = global i32 ()* inttoptr (i32 7 to i32 ()*), align 8 - -; External functions -declare i32 @c() -declare i32 @d() - -define i32 @f1() { -entry: - %aa = load i64 ()*, i64 ()** @a, align 8 - %bb = load i32 ()*, i32 ()** @b, align 8 - %tmp1 = call i64 %aa() - %tmp2 = call i32 %bb() - %tmp3 = call i32 @c() - %tmp4 = call i32 @d() - ret i32 %tmp2 -} - - -; CHECK: Format: WASM -; CHECK: Relocations [ -; CHECK-NEXT: Section (5) CODE { -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) -; CHECK-NEXT: Offset: 0x9 -; CHECK-NEXT: Symbol: b -; CHECK-NEXT: Addend: 0 -; CHECK-NEXT: } -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) -; CHECK-NEXT: Offset: 0x14 -; CHECK-NEXT: Symbol: a -; CHECK-NEXT: Addend: 0 -; CHECK-NEXT: } -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) -; CHECK-NEXT: Offset: 0x1A -; CHECK-NEXT: Index: 0x1 -; CHECK-NEXT: } -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) -; CHECK-NEXT: Offset: 0x24 -; CHECK-NEXT: Index: 0x0 -; CHECK-NEXT: } -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) -; CHECK-NEXT: Offset: 0x2D -; CHECK-NEXT: Symbol: c -; CHECK-NEXT: } -; CHECK-NEXT: Relocation { -; CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) -; CHECK-NEXT: Offset: 0x34 -; CHECK-NEXT: Symbol: d -; CHECK-NEXT: } -; CHECK-NEXT: } -; CHECK-NEXT: ] - -; REF: Format: WASM -; REF: Relocations [ -; REF-NEXT: Section (5) CODE { -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) -; REF-NEXT: Offset: 0x9 -; REF-NEXT: Symbol: b -; REF-NEXT: Addend: 0 -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) -; REF-NEXT: Offset: 0x14 -; REF-NEXT: Symbol: a -; REF-NEXT: Addend: 0 -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) -; REF-NEXT: Offset: 0x1A -; REF-NEXT: Index: 0x1 -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_TABLE_NUMBER_LEB (20) -; REF-NEXT: Offset: 0x1F -; REF-NEXT: Symbol: __indirect_function_table -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) -; REF-NEXT: Offset: 0x28 -; REF-NEXT: Index: 0x0 -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_TABLE_NUMBER_LEB (20) -; REF-NEXT: Offset: 0x2D -; REF-NEXT: Symbol: __indirect_function_table -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) -; REF-NEXT: Offset: 0x35 -; REF-NEXT: Symbol: c -; REF-NEXT: } -; REF-NEXT: Relocation { -; REF-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) -; REF-NEXT: Offset: 0x3C -; REF-NEXT: Symbol: d -; REF-NEXT: } -; REF-NEXT: } -; REF-NEXT: ] diff --git a/llvm/test/MC/WebAssembly/reloc-code.s b/llvm/test/MC/WebAssembly/reloc-code.s new file mode 100644 index 0000000000000..cd301098f9a8c --- /dev/null +++ b/llvm/test/MC/WebAssembly/reloc-code.s @@ -0,0 +1,129 @@ +# RUN: llvm-mc -triple=wasm32-unknown-unknown -filetype=obj %s -o - | llvm-readobj -r --expand-relocs - | FileCheck %s +# RUN: llvm-mc -triple=wasm32-unknown-unknown -mattr=+reference-types -filetype=obj %s -o - | llvm-readobj -r --expand-relocs - | FileCheck --check-prefix=REF %s + +# External functions +.functype c () -> (i32) +.functype d () -> (i32) + +.globl f1 +.globl a +.globl b + +f1: + .functype f1 () -> (i32) + + # Call functions at `a` and `b` indirectly. + i32.const 0 + i32.load a + call_indirect () -> (i64) + drop + + i32.const 0 + i32.load b + call_indirect () -> (i32) + drop + + # Call functions `c` and `d` directly + call c + drop + call d + end_function + +# Pointers to functions of two different types +.section .data.a,"",@ +.p2align 3 +a: + .int32 5 + .size a, 4 + +.section .data.b,"",@ +.p2align 3 +b: + .int32 7 + .size b, 4 + +# CHECK: Format: WASM +# CHECK: Relocations [ +# CHECK-NEXT: Section (5) CODE { +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) +# CHECK-NEXT: Offset: 0x7 +# CHECK-NEXT: Symbol: a +# CHECK-NEXT: Addend: 0 +# CHECK-NEXT: } +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) +# CHECK-NEXT: Offset: 0xD +# CHECK-NEXT: Index: 0x1 +# CHECK-NEXT: } +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) +# CHECK-NEXT: Offset: 0x18 +# CHECK-NEXT: Symbol: b +# CHECK-NEXT: Addend: 0 +# CHECK-NEXT: } +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) +# CHECK-NEXT: Offset: 0x1E +# CHECK-NEXT: Index: 0x0 +# CHECK-NEXT: } +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) +# CHECK-NEXT: Offset: 0x26 +# CHECK-NEXT: Symbol: c +# CHECK-NEXT: } +# CHECK-NEXT: Relocation { +# CHECK-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) +# CHECK-NEXT: Offset: 0x2D +# CHECK-NEXT: Symbol: d +# CHECK-NEXT: } +# CHECK-NEXT: } +# CHECK-NEXT: ] + +# REF: Format: WASM +# REF: Relocations [ +# REF-NEXT: Section (5) CODE { +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) +# REF-NEXT: Offset: 0x7 +# REF-NEXT: Symbol: a +# REF-NEXT: Addend: 0 +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) +# REF-NEXT: Offset: 0xD +# REF-NEXT: Index: 0x1 +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_TABLE_NUMBER_LEB (20) +# REF-NEXT: Offset: 0x12 +# REF-NEXT: Symbol: __indirect_function_table +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) +# REF-NEXT: Offset: 0x1C +# REF-NEXT: Symbol: b +# REF-NEXT: Addend: 0 +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) +# REF-NEXT: Offset: 0x22 +# REF-NEXT: Index: 0x0 +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_TABLE_NUMBER_LEB (20) +# REF-NEXT: Offset: 0x27 +# REF-NEXT: Symbol: __indirect_function_table +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) +# REF-NEXT: Offset: 0x2E +# REF-NEXT: Symbol: c +# REF-NEXT: } +# REF-NEXT: Relocation { +# REF-NEXT: Type: R_WASM_FUNCTION_INDEX_LEB (0) +# REF-NEXT: Offset: 0x35 +# REF-NEXT: Symbol: d +# REF-NEXT: } +# REF-NEXT: } +# REF-NEXT: ] From e6d2aa9b0f131a141166d1d90560f1a2d1d9ec5c Mon Sep 17 00:00:00 2001 From: Sam Clegg Date: Wed, 23 Feb 2022 22:23:05 -0800 Subject: [PATCH 223/316] [MC][WebAssembly] Fix crash when relocation addend underlows U32 For the object file writer we need to allow the underflow (ar write zero), but for the final linker output we should probably generate an error (I've left that as a TODO for now). Fixes: https://github.com/llvm/llvm-project/issues/54012 Differential Revision: https://reviews.llvm.org/D120522 (cherry picked from commit 4c75521ce0b1ac55fba1a91ef5156fc811f5dfcb) --- lld/test/wasm/reloc-addend.s | 48 +++++++++++++++++++++ lld/wasm/InputChunks.cpp | 7 ++- lld/wasm/InputFiles.cpp | 2 +- lld/wasm/InputFiles.h | 2 +- llvm/lib/MC/WasmObjectWriter.cpp | 62 ++++++++++++++++++--------- llvm/test/MC/WebAssembly/reloc-code.s | 12 +++--- 6 files changed, 103 insertions(+), 30 deletions(-) diff --git a/lld/test/wasm/reloc-addend.s b/lld/test/wasm/reloc-addend.s index acd57ce357a72..4b23ed1120faa 100644 --- a/lld/test/wasm/reloc-addend.s +++ b/lld/test/wasm/reloc-addend.s @@ -1,6 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -o %t.o %s # RUN: wasm-ld -r -o %t.wasm %t.o # RUN: obj2yaml %t.wasm | FileCheck %s +# RUN: llvm-objdump --disassemble-symbols=_start --no-show-raw-insn --no-leading-addr %t.wasm | FileCheck %s --check-prefixes DIS .hidden foo .hidden bar @@ -30,6 +31,39 @@ negative_addend: .int32 foo-16 .size negative_addend, 4 +.globl _start +.section .text,"",@ +_start: + .functype _start () -> () + i32.const 0 + i32.load foo + 10 + drop + i32.const 0 + i32.load foo - 10 + drop + i32.const 0 + # This will underflow because i32.load (and the + # corresponding relocation type) take an unsgiend (U32) + # immediate. + i32.load foo - 2048 + drop + end_function + +# CHECK: - Type: CODE +# CHECK-NEXT: Relocations: +# CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_LEB +# CHECK-NEXT: Index: 0 +# CHECK-NEXT: Offset: 0x7 +# CHECK-NEXT: Addend: 10 +# CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_LEB +# CHECK-NEXT: Index: 0 +# CHECK-NEXT: Offset: 0x11 +# CHECK-NEXT: Addend: -10 +# CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_LEB +# CHECK-NEXT: Index: 0 +# CHECK-NEXT: Offset: 0x1B +# CHECK-NEXT: Addend: -2048 + # CHECK: - Type: DATA # CHECK-NEXT: Relocations: # CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_I32 @@ -40,3 +74,17 @@ negative_addend: # CHECK-NEXT: Index: 0 # CHECK-NEXT: Offset: 0xF # CHECK-NEXT: Addend: -16 + +# DIS: <_start>: +# DIS-EMPTY: +# DIS-NEXT: i32.const 0 +# DIS-NEXT: i32.load 26 +# DIS-NEXT: drop +# DIS-NEXT: i32.const 0 +# DIS-NEXT: i32.load 6 +# DIS-NEXT: drop +# DIS-NEXT: i32.const 0 +# TODO(sbc): We should probably error here rather than allowing u32 to wrap +# DIS-NEXT: i32.load 4294965264 +# DIS-NEXT: drop +# DIS-NEXT: end diff --git a/lld/wasm/InputChunks.cpp b/lld/wasm/InputChunks.cpp index 7973dce6827e2..242378504c3b8 100644 --- a/lld/wasm/InputChunks.cpp +++ b/lld/wasm/InputChunks.cpp @@ -116,7 +116,10 @@ void InputChunk::relocate(uint8_t *buf) const { LLVM_DEBUG(dbgs() << " sym=" << file->getSymbols()[rel.Index]->getName()); LLVM_DEBUG(dbgs() << " addend=" << rel.Addend << " index=" << rel.Index << " offset=" << rel.Offset << "\n"); - auto value = file->calcNewValue(rel, tombstone, this); + // TODO(sbc): Check that the value is within the range of the + // relocation type below. Most likely we must error out here + // if its not with range. + uint64_t value = file->calcNewValue(rel, tombstone, this); switch (rel.Type) { case R_WASM_TYPE_INDEX_LEB: @@ -125,7 +128,7 @@ void InputChunk::relocate(uint8_t *buf) const { case R_WASM_TAG_INDEX_LEB: case R_WASM_MEMORY_ADDR_LEB: case R_WASM_TABLE_NUMBER_LEB: - encodeULEB128(value, loc, 5); + encodeULEB128(static_cast(value), loc, 5); break; case R_WASM_MEMORY_ADDR_LEB64: encodeULEB128(value, loc, 10); diff --git a/lld/wasm/InputFiles.cpp b/lld/wasm/InputFiles.cpp index 0758bb922a3bc..1e69f16cc5f97 100644 --- a/lld/wasm/InputFiles.cpp +++ b/lld/wasm/InputFiles.cpp @@ -106,7 +106,7 @@ uint32_t ObjFile::calcNewIndex(const WasmRelocation &reloc) const { // Relocations can contain addend for combined sections. This function takes a // relocation and returns updated addend by offset in the output section. -uint64_t ObjFile::calcNewAddend(const WasmRelocation &reloc) const { +int64_t ObjFile::calcNewAddend(const WasmRelocation &reloc) const { switch (reloc.Type) { case R_WASM_MEMORY_ADDR_LEB: case R_WASM_MEMORY_ADDR_LEB64: diff --git a/lld/wasm/InputFiles.h b/lld/wasm/InputFiles.h index cf2c1739e3220..c14d763ff30cd 100644 --- a/lld/wasm/InputFiles.h +++ b/lld/wasm/InputFiles.h @@ -119,7 +119,7 @@ class ObjFile : public InputFile { uint32_t calcNewIndex(const WasmRelocation &reloc) const; uint64_t calcNewValue(const WasmRelocation &reloc, uint64_t tombstone, const InputChunk *chunk) const; - uint64_t calcNewAddend(const WasmRelocation &reloc) const; + int64_t calcNewAddend(const WasmRelocation &reloc) const; Symbol *getSymbol(const WasmRelocation &reloc) const { return symbols[reloc.Index]; }; diff --git a/llvm/lib/MC/WasmObjectWriter.cpp b/llvm/lib/MC/WasmObjectWriter.cpp index 636c1d238932f..a016b7085a000 100644 --- a/llvm/lib/MC/WasmObjectWriter.cpp +++ b/llvm/lib/MC/WasmObjectWriter.cpp @@ -140,36 +140,58 @@ raw_ostream &operator<<(raw_ostream &OS, const WasmRelocationEntry &Rel) { } #endif -// Write X as an (unsigned) LEB value at offset Offset in Stream, padded +// Write Value as an (unsigned) LEB value at offset Offset in Stream, padded // to allow patching. -template -void writePatchableLEB(raw_pwrite_stream &Stream, uint64_t X, uint64_t Offset) { +template +void writePatchableULEB(raw_pwrite_stream &Stream, T Value, uint64_t Offset) { uint8_t Buffer[W]; - unsigned SizeLen = encodeULEB128(X, Buffer, W); + unsigned SizeLen = encodeULEB128(Value, Buffer, W); assert(SizeLen == W); Stream.pwrite((char *)Buffer, SizeLen, Offset); } -// Write X as an signed LEB value at offset Offset in Stream, padded +// Write Value as an signed LEB value at offset Offset in Stream, padded // to allow patching. -template -void writePatchableSLEB(raw_pwrite_stream &Stream, int64_t X, uint64_t Offset) { +template +void writePatchableSLEB(raw_pwrite_stream &Stream, T Value, uint64_t Offset) { uint8_t Buffer[W]; - unsigned SizeLen = encodeSLEB128(X, Buffer, W); + unsigned SizeLen = encodeSLEB128(Value, Buffer, W); assert(SizeLen == W); Stream.pwrite((char *)Buffer, SizeLen, Offset); } -// Write X as a plain integer value at offset Offset in Stream. -static void patchI32(raw_pwrite_stream &Stream, uint32_t X, uint64_t Offset) { +static void writePatchableU32(raw_pwrite_stream &Stream, uint32_t Value, + uint64_t Offset) { + writePatchableULEB(Stream, Value, Offset); +} + +static void writePatchableS32(raw_pwrite_stream &Stream, int32_t Value, + uint64_t Offset) { + writePatchableSLEB(Stream, Value, Offset); +} + +static void writePatchableU64(raw_pwrite_stream &Stream, uint64_t Value, + uint64_t Offset) { + writePatchableSLEB(Stream, Value, Offset); +} + +static void writePatchableS64(raw_pwrite_stream &Stream, int64_t Value, + uint64_t Offset) { + writePatchableSLEB(Stream, Value, Offset); +} + +// Write Value as a plain integer value at offset Offset in Stream. +static void patchI32(raw_pwrite_stream &Stream, uint32_t Value, + uint64_t Offset) { uint8_t Buffer[4]; - support::endian::write32le(Buffer, X); + support::endian::write32le(Buffer, Value); Stream.pwrite((char *)Buffer, sizeof(Buffer), Offset); } -static void patchI64(raw_pwrite_stream &Stream, uint64_t X, uint64_t Offset) { +static void patchI64(raw_pwrite_stream &Stream, uint64_t Value, + uint64_t Offset) { uint8_t Buffer[8]; - support::endian::write64le(Buffer, X); + support::endian::write64le(Buffer, Value); Stream.pwrite((char *)Buffer, sizeof(Buffer), Offset); } @@ -423,8 +445,8 @@ void WasmObjectWriter::endSection(SectionBookkeeping &Section) { // Write the final section size to the payload_len field, which follows // the section id byte. - writePatchableLEB<5>(static_cast(W->OS), Size, - Section.SizeOffset); + writePatchableU32(static_cast(W->OS), Size, + Section.SizeOffset); } // Emit the Wasm header. @@ -755,7 +777,7 @@ void WasmObjectWriter::applyRelocations( RelEntry.Offset; LLVM_DEBUG(dbgs() << "applyRelocation: " << RelEntry << "\n"); - auto Value = getProvisionalValue(RelEntry, Layout); + uint64_t Value = getProvisionalValue(RelEntry, Layout); switch (RelEntry.Type) { case wasm::R_WASM_FUNCTION_INDEX_LEB: @@ -764,10 +786,10 @@ void WasmObjectWriter::applyRelocations( case wasm::R_WASM_MEMORY_ADDR_LEB: case wasm::R_WASM_TAG_INDEX_LEB: case wasm::R_WASM_TABLE_NUMBER_LEB: - writePatchableLEB<5>(Stream, Value, Offset); + writePatchableU32(Stream, Value, Offset); break; case wasm::R_WASM_MEMORY_ADDR_LEB64: - writePatchableLEB<10>(Stream, Value, Offset); + writePatchableU64(Stream, Value, Offset); break; case wasm::R_WASM_TABLE_INDEX_I32: case wasm::R_WASM_MEMORY_ADDR_I32: @@ -787,14 +809,14 @@ void WasmObjectWriter::applyRelocations( case wasm::R_WASM_MEMORY_ADDR_SLEB: case wasm::R_WASM_MEMORY_ADDR_REL_SLEB: case wasm::R_WASM_MEMORY_ADDR_TLS_SLEB: - writePatchableSLEB<5>(Stream, Value, Offset); + writePatchableS32(Stream, Value, Offset); break; case wasm::R_WASM_TABLE_INDEX_SLEB64: case wasm::R_WASM_TABLE_INDEX_REL_SLEB64: case wasm::R_WASM_MEMORY_ADDR_SLEB64: case wasm::R_WASM_MEMORY_ADDR_REL_SLEB64: case wasm::R_WASM_MEMORY_ADDR_TLS_SLEB64: - writePatchableSLEB<10>(Stream, Value, Offset); + writePatchableS64(Stream, Value, Offset); break; default: llvm_unreachable("invalid relocation type"); diff --git a/llvm/test/MC/WebAssembly/reloc-code.s b/llvm/test/MC/WebAssembly/reloc-code.s index cd301098f9a8c..c7b05f81a7ff7 100644 --- a/llvm/test/MC/WebAssembly/reloc-code.s +++ b/llvm/test/MC/WebAssembly/reloc-code.s @@ -14,12 +14,12 @@ f1: # Call functions at `a` and `b` indirectly. i32.const 0 - i32.load a + i32.load a - 10 call_indirect () -> (i64) drop i32.const 0 - i32.load b + i32.load b + 20 call_indirect () -> (i32) drop @@ -49,7 +49,7 @@ b: # CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) # CHECK-NEXT: Offset: 0x7 # CHECK-NEXT: Symbol: a -# CHECK-NEXT: Addend: 0 +# CHECK-NEXT: Addend: -10 # CHECK-NEXT: } # CHECK-NEXT: Relocation { # CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) @@ -60,7 +60,7 @@ b: # CHECK-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) # CHECK-NEXT: Offset: 0x18 # CHECK-NEXT: Symbol: b -# CHECK-NEXT: Addend: 0 +# CHECK-NEXT: Addend: 20 # CHECK-NEXT: } # CHECK-NEXT: Relocation { # CHECK-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) @@ -87,7 +87,7 @@ b: # REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) # REF-NEXT: Offset: 0x7 # REF-NEXT: Symbol: a -# REF-NEXT: Addend: 0 +# REF-NEXT: Addend: -10 # REF-NEXT: } # REF-NEXT: Relocation { # REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) @@ -103,7 +103,7 @@ b: # REF-NEXT: Type: R_WASM_MEMORY_ADDR_LEB (3) # REF-NEXT: Offset: 0x1C # REF-NEXT: Symbol: b -# REF-NEXT: Addend: 0 +# REF-NEXT: Addend: 20 # REF-NEXT: } # REF-NEXT: Relocation { # REF-NEXT: Type: R_WASM_TYPE_INDEX_LEB (6) From 43b4544023b73d334b5f60edaf7e1dcce4c75d3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 2 Mar 2022 12:33:31 +0200 Subject: [PATCH 224/316] [LLD] [COFF] Order .debug_* sections at the end, to avoid leaving gaps if stripped So far, we sort all discardable sections at the end, with only some extra logic to make sure that the .reloc section is at the start of that group of sections. But if there are other discardable sections, other than .reloc, they must also be ordered before .debug_* sections, to avoid leaving gaps if the executable is stripped. (Stripping executables doesn't remove all discardable sections, only the ones named .debug_*). Rust binaries seem to include a .rmeta section, which is marked discardable. This fixes stripping such binaries if built with dwarf debug info included. This fixes issues observed in MSYS2 in https://github.com/msys2/MINGW-packages/pull/10555. Differential Revision: https://reviews.llvm.org/D120805 (cherry picked from commit 4c3b74b7f5d6192d1731c88f1aeb396bc51d4949) --- lld/COFF/Writer.cpp | 8 +++++++- lld/test/COFF/sort-debug.test | 6 ++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp index 12db942f1db55..1ed2327ea630d 100644 --- a/lld/COFF/Writer.cpp +++ b/lld/COFF/Writer.cpp @@ -926,8 +926,14 @@ void Writer::createSections() { // Move DISCARDABLE (or non-memory-mapped) sections to the end of file // because the loader cannot handle holes. Stripping can remove other // discardable ones than .reloc, which is first of them (created early). - if (s->header.Characteristics & IMAGE_SCN_MEM_DISCARDABLE) + if (s->header.Characteristics & IMAGE_SCN_MEM_DISCARDABLE) { + // Move discardable sections named .debug_ to the end, after other + // discardable sections. Stripping only removes the sections named + // .debug_* - thus try to avoid leaving holes after stripping. + if (s->name.startswith(".debug_")) + return 3; return 2; + } // .rsrc should come at the end of the non-discardable sections because its // size may change by the Win32 UpdateResources() function, causing // subsequent sections to move (see https://crbug.com/827082). diff --git a/lld/test/COFF/sort-debug.test b/lld/test/COFF/sort-debug.test index d8fd7ae605645..bbe2ecd0efd8d 100644 --- a/lld/test/COFF/sort-debug.test +++ b/lld/test/COFF/sort-debug.test @@ -10,6 +10,7 @@ # CHECK: Name: .text # CHECK: Name: .reloc +# CHECK: Name: .rmeta # CHECK: Name: .debug_abbrev # CHECK: Name: .debug_info # CHECK: Name: .debug_line @@ -18,6 +19,7 @@ # NODEBUG: Name: .text # NODEBUG: Name: .reloc +# NODEBUG: Name: .rmeta # NODEBUG-NOT: Name: .debug_abbrev # NODEBUG-NOT: Name: .debug_info # NODEBUG-NOT: Name: .debug_line @@ -183,6 +185,10 @@ sections: - VirtualAddress: 43 SymbolName: .text Type: IMAGE_REL_I386_DIR32 + - Name: .rmeta + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + SectionData: 00112233 symbols: - Name: .text Value: 0 From bfaed485756a4e2eb7b771cc2ef1d9acef39dc8a Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Mon, 7 Mar 2022 18:41:12 -0800 Subject: [PATCH 225/316] [BOLT][CMAKE] Remove CMake 3.13.4 incompatible parameter Remove `TYPE BIN` parameter that is introduced in CMake 3.14 and revert back to the equivalent compatible form `DESTINATION ${CMAKE_INSTALL_BINDIR}`. Addresses https://github.com/llvm/llvm-project/issues/54099 Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D121012 (cherry picked from commit 018ad03efae2503a5e0590881a3b8078b9f0c3c8) --- bolt/tools/driver/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bolt/tools/driver/CMakeLists.txt b/bolt/tools/driver/CMakeLists.txt index c8027197b056d..d50781615663f 100644 --- a/bolt/tools/driver/CMakeLists.txt +++ b/bolt/tools/driver/CMakeLists.txt @@ -38,7 +38,7 @@ install(PROGRAMS ${CMAKE_BINARY_DIR}/bin/perf2bolt ${CMAKE_BINARY_DIR}/bin/llvm-boltdiff ${CMAKE_BINARY_DIR}/bin/llvm-bolt-heatmap - TYPE BIN + DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT bolt ) add_llvm_install_targets(install-bolt DEPENDS bolt COMPONENT bolt) From 1e4fd59253c60c78a222f85c42501302142a3586 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 22 Feb 2022 16:31:46 +0100 Subject: [PATCH 226/316] [CodeGen] Add test for PR53990 (NFC) (cherry picked from commit e075bf6bdbcaa2652891ebff3e7ce9ca00cadd8a) --- .../X86/pr53990-incorrect-machine-sink.ll | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll diff --git a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll new file mode 100644 index 0000000000000..3d7ff6cbe676a --- /dev/null +++ b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll @@ -0,0 +1,67 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s + +declare void @clobber() + +define void @test(i1 %c, i64* %p, i64* noalias %p2) nounwind { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rbp +; CHECK-NEXT: pushq %r15 +; CHECK-NEXT: pushq %r14 +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: movq %rdx, %rbx +; CHECK-NEXT: movq %rsi, %r14 +; CHECK-NEXT: movl %edi, %r15d +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) +; CHECK-NEXT: .LBB0_1: # %split.3 +; CHECK-NEXT: movq (%r14), %rbp +; CHECK-NEXT: testb $1, %r15b +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # %bb.2: # %clobber +; CHECK-NEXT: callq clobber@PLT +; CHECK-NEXT: .LBB0_3: # %sink +; CHECK-NEXT: movq %rbp, (%rbx) +; CHECK-NEXT: .LBB0_4: # %latch +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) +entry: + %val = load i64, i64* %p, align 8 + br label %loop + +loop: + switch i8 undef, label %unreachable [ + i8 0, label %latch + i8 1, label %split.1 + i8 2, label %split.2 + i8 3, label %split.3 + ] + +unreachable: + unreachable + +split.3: + br i1 %c, label %clobber, label %sink + +split.1: + br label %latch + +split.2: + br label %latch + +clobber: + call void @clobber() + br label %sink + +sink: + store i64 %val, i64* %p2, align 8 + br label %latch + +latch: + %phi = phi i64 [ 0, %sink ], [ 0, %split.2 ], [ 1, %split.1 ], [ 0, %loop ] + %phi.live = add i64 %phi, 0 + br label %loop +} From 67555104d23aaef9b4ce4995ccb98b2ba9aff07d Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 24 Feb 2022 10:09:49 +0100 Subject: [PATCH 227/316] [MachineSink] Disable if there are any irreducible cycles This is an alternative to D120330, which disables MachineSink for functions with irreducible cycles entirely. This avoids both the correctness problem, and ensures we don't perform non-profitable sinks into cycles. At the same time, it may also disable profitable sinks in the same function. This can be made more precise by using MachineCycleInfo in the future. Fixes https://github.com/llvm/llvm-project/issues/53990. Differential Revision: https://reviews.llvm.org/D120800 (cherry picked from commit 6fde0439512580df793f3f48f95757b47de40d2b) --- llvm/lib/CodeGen/MachineSink.cpp | 12 +++ .../CodeGen/X86/callbr-asm-branch-folding.ll | 22 ++--- llvm/test/CodeGen/X86/pr38795.ll | 93 +++++++++---------- .../X86/pr53990-incorrect-machine-sink.ll | 9 +- llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 36 ++++--- 5 files changed, 87 insertions(+), 85 deletions(-) diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 0dbbc218e9464..bc03776bde19d 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -18,12 +18,14 @@ #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/MapVector.h" #include "llvm/ADT/PointerIntPair.h" +#include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SparseBitVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/CFG.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" @@ -429,6 +431,16 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { AA = &getAnalysis().getAAResults(); RegClassInfo.runOnMachineFunction(MF); + // MachineSink currently uses MachineLoopInfo, which only recognizes natural + // loops. As such, we could sink instructions into irreducible cycles, which + // would be non-profitable. + // WARNING: The current implementation of hasStoreBetween() is incorrect for + // sinking into irreducible cycles (PR53990), this bailout is currently + // necessary for correctness, not just profitability. + ReversePostOrderTraversal RPOT(&*MF.begin()); + if (containsIrreducibleCFG(RPOT, *LI)) + return false; + bool EverMadeChange = false; while (true) { diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll index 024b6c608abab..f93e181d157c7 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll @@ -24,7 +24,7 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { ; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: callq l ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: jne .LBB0_10 +; CHECK-NEXT: jne .LBB0_9 ; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: movl %ebx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; CHECK-NEXT: cmpl $0, e(%rip) @@ -44,21 +44,19 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { ; CHECK-NEXT: callq i ; CHECK-NEXT: movl %eax, %ebp ; CHECK-NEXT: orl %r14d, %ebp -; CHECK-NEXT: testl %r13d, %r13d -; CHECK-NEXT: je .LBB0_6 -; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: andl $4, %ebx -; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_6: # %if.end12 +; CHECK-NEXT: testl %r13d, %r13d +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # %bb.5: # %if.end12 ; CHECK-NEXT: testl %ebp, %ebp -; CHECK-NEXT: je .LBB0_9 -; CHECK-NEXT: # %bb.7: # %if.then14 +; CHECK-NEXT: je .LBB0_8 +; CHECK-NEXT: # %bb.6: # %if.then14 ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: jmp .LBB0_10 +; CHECK-NEXT: jmp .LBB0_9 ; CHECK-NEXT: .Ltmp0: # Block address taken -; CHECK-NEXT: # %bb.8: # %if.then20.critedge +; CHECK-NEXT: # %bb.7: # %if.then20.critedge ; CHECK-NEXT: movl j(%rip), %edi ; CHECK-NEXT: movslq %eax, %rcx ; CHECK-NEXT: movl $1, %esi @@ -71,9 +69,9 @@ define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind { ; CHECK-NEXT: popq %r15 ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: jmp k # TAILCALL -; CHECK-NEXT: .LBB0_9: # %if.else +; CHECK-NEXT: .LBB0_8: # %if.else ; CHECK-NEXT: incq 0 -; CHECK-NEXT: .LBB0_10: # %cleanup +; CHECK-NEXT: .LBB0_9: # %cleanup ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r12 diff --git a/llvm/test/CodeGen/X86/pr38795.ll b/llvm/test/CodeGen/X86/pr38795.ll index d805dcad8b6e6..b526e4f471b1a 100644 --- a/llvm/test/CodeGen/X86/pr38795.ll +++ b/llvm/test/CodeGen/X86/pr38795.ll @@ -32,13 +32,14 @@ define dso_local void @fn() { ; CHECK-NEXT: # implicit-def: $ebp ; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_16: # %for.inc +; CHECK-NEXT: .LBB0_15: # %for.inc ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: movb %dh, %dl ; CHECK-NEXT: .LBB0_1: # %for.cond ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_20 Depth 2 +; CHECK-NEXT: # Child Loop BB0_19 Depth 2 ; CHECK-NEXT: cmpb $8, %dl ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: ja .LBB0_3 @@ -55,7 +56,7 @@ define dso_local void @fn() { ; CHECK-NEXT: movb %cl, %dh ; CHECK-NEXT: movl $0, h ; CHECK-NEXT: cmpb $8, %dl -; CHECK-NEXT: jg .LBB0_8 +; CHECK-NEXT: jg .LBB0_9 ; CHECK-NEXT: # %bb.5: # %if.then13 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl %eax, %esi @@ -64,12 +65,10 @@ define dso_local void @fn() { ; CHECK-NEXT: calll printf ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: # implicit-def: $eax -; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload -; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill +; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload ; CHECK-NEXT: movb %dh, %dl -; CHECK-NEXT: jne .LBB0_16 +; CHECK-NEXT: jne .LBB0_15 ; CHECK-NEXT: jmp .LBB0_6 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_3: # %if.then @@ -78,82 +77,82 @@ define dso_local void @fn() { ; CHECK-NEXT: calll printf ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload ; CHECK-NEXT: # implicit-def: $eax +; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload +; CHECK-NEXT: jmp .LBB0_6 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB0_9: # %if.end21 +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: # implicit-def: $ebp +; CHECK-NEXT: jmp .LBB0_10 +; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_6: # %for.cond35 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movb %dl, %dh ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB0_7 -; CHECK-NEXT: .LBB0_11: # %af +; CHECK-NEXT: movl %edi, %esi +; CHECK-NEXT: movl $0, %edi +; CHECK-NEXT: movb %cl, %dl +; CHECK-NEXT: je .LBB0_19 +; CHECK-NEXT: # %bb.7: # %af ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_12 -; CHECK-NEXT: .LBB0_17: # %if.end39 +; CHECK-NEXT: jne .LBB0_8 +; CHECK-NEXT: .LBB0_16: # %if.end39 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_19 -; CHECK-NEXT: # %bb.18: # %if.then41 +; CHECK-NEXT: je .LBB0_18 +; CHECK-NEXT: # %bb.17: # %if.then41 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $fn, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $.str, (%esp) ; CHECK-NEXT: calll printf -; CHECK-NEXT: .LBB0_19: # %for.end46 +; CHECK-NEXT: .LBB0_18: # %for.end46 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl %esi, %edi ; CHECK-NEXT: # implicit-def: $dl ; CHECK-NEXT: # implicit-def: $dh ; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: jmp .LBB0_20 -; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_8: # %if.end21 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: jmp .LBB0_9 ; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_7: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: xorl %edi, %edi -; CHECK-NEXT: movb %dl, %dh -; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload -; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_20: # %for.cond47 +; CHECK-NEXT: .LBB0_19: # %for.cond47 ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_20 -; CHECK-NEXT: # %bb.21: # %for.cond47 -; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2 +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: # %bb.20: # %for.cond47 +; CHECK-NEXT: # in Loop: Header=BB0_19 Depth=2 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_20 -; CHECK-NEXT: .LBB0_9: # %ae +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: .LBB0_10: # %ae ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_10 -; CHECK-NEXT: # %bb.13: # %if.end26 +; CHECK-NEXT: jne .LBB0_11 +; CHECK-NEXT: # %bb.12: # %if.end26 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: testb %dl, %dl -; CHECK-NEXT: je .LBB0_16 -; CHECK-NEXT: # %bb.14: # %if.end26 +; CHECK-NEXT: je .LBB0_15 +; CHECK-NEXT: # %bb.13: # %if.end26 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testl %ebp, %ebp -; CHECK-NEXT: jne .LBB0_16 -; CHECK-NEXT: # %bb.15: # %if.then31 +; CHECK-NEXT: jne .LBB0_15 +; CHECK-NEXT: # %bb.14: # %if.then31 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %ebp, %ebp -; CHECK-NEXT: jmp .LBB0_16 +; CHECK-NEXT: jmp .LBB0_15 ; CHECK-NEXT: .p2align 4, 0x90 -; CHECK-NEXT: .LBB0_10: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_11: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl %edi, %esi ; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB0_17 -; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_16 +; CHECK-NEXT: .LBB0_8: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # implicit-def: $edi ; CHECK-NEXT: # implicit-def: $cl -; CHECK-NEXT: # kill: killed $cl ; CHECK-NEXT: # implicit-def: $dl ; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB0_11 -; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: jmp .LBB0_6 entry: br label %for.cond diff --git a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll index 3d7ff6cbe676a..4f56d7b16a879 100644 --- a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll +++ b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll @@ -7,18 +7,15 @@ define void @test(i1 %c, i64* %p, i64* noalias %p2) nounwind { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rbp -; CHECK-NEXT: pushq %r15 ; CHECK-NEXT: pushq %r14 ; CHECK-NEXT: pushq %rbx -; CHECK-NEXT: pushq %rax ; CHECK-NEXT: movq %rdx, %rbx -; CHECK-NEXT: movq %rsi, %r14 -; CHECK-NEXT: movl %edi, %r15d +; CHECK-NEXT: movl %edi, %r14d +; CHECK-NEXT: movq (%rsi), %rbp ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) ; CHECK-NEXT: .LBB0_1: # %split.3 -; CHECK-NEXT: movq (%r14), %rbp -; CHECK-NEXT: testb $1, %r15b +; CHECK-NEXT: testb $1, %r14b ; CHECK-NEXT: je .LBB0_3 ; CHECK-NEXT: # %bb.2: # %clobber ; CHECK-NEXT: callq clobber@PLT diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll index 0f8bb837f82a5..b44895293b411 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -1377,6 +1377,8 @@ define i32 @irreducibleCFG() #4 { ; ENABLE-NEXT: pushq %rbx ; ENABLE-NEXT: pushq %rax ; ENABLE-NEXT: .cfi_offset %rbx, -24 +; ENABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax +; ENABLE-NEXT: movl (%rax), %edi ; ENABLE-NEXT: movq _irreducibleCFGf@GOTPCREL(%rip), %rax ; ENABLE-NEXT: cmpb $0, (%rax) ; ENABLE-NEXT: je LBB16_2 @@ -1386,24 +1388,20 @@ define i32 @irreducibleCFG() #4 { ; ENABLE-NEXT: jmp LBB16_1 ; ENABLE-NEXT: LBB16_2: ## %split ; ENABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax +; ENABLE-NEXT: xorl %ebx, %ebx ; ENABLE-NEXT: cmpl $0, (%rax) -; ENABLE-NEXT: je LBB16_3 -; ENABLE-NEXT: ## %bb.4: ## %for.body4.i -; ENABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax -; ENABLE-NEXT: movl (%rax), %edi +; ENABLE-NEXT: je LBB16_4 +; ENABLE-NEXT: ## %bb.3: ## %for.body4.i ; ENABLE-NEXT: xorl %ebx, %ebx ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: callq _something -; ENABLE-NEXT: jmp LBB16_5 -; ENABLE-NEXT: LBB16_3: -; ENABLE-NEXT: xorl %ebx, %ebx ; ENABLE-NEXT: .p2align 4, 0x90 -; ENABLE-NEXT: LBB16_5: ## %for.inc +; ENABLE-NEXT: LBB16_4: ## %for.inc ; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: incl %ebx ; ENABLE-NEXT: cmpl $7, %ebx -; ENABLE-NEXT: jl LBB16_5 -; ENABLE-NEXT: ## %bb.6: ## %fn1.exit +; ENABLE-NEXT: jl LBB16_4 +; ENABLE-NEXT: ## %bb.5: ## %fn1.exit ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: addq $8, %rsp ; ENABLE-NEXT: popq %rbx @@ -1420,6 +1418,8 @@ define i32 @irreducibleCFG() #4 { ; DISABLE-NEXT: pushq %rbx ; DISABLE-NEXT: pushq %rax ; DISABLE-NEXT: .cfi_offset %rbx, -24 +; DISABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax +; DISABLE-NEXT: movl (%rax), %edi ; DISABLE-NEXT: movq _irreducibleCFGf@GOTPCREL(%rip), %rax ; DISABLE-NEXT: cmpb $0, (%rax) ; DISABLE-NEXT: je LBB16_2 @@ -1429,24 +1429,20 @@ define i32 @irreducibleCFG() #4 { ; DISABLE-NEXT: jmp LBB16_1 ; DISABLE-NEXT: LBB16_2: ## %split ; DISABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax +; DISABLE-NEXT: xorl %ebx, %ebx ; DISABLE-NEXT: cmpl $0, (%rax) -; DISABLE-NEXT: je LBB16_3 -; DISABLE-NEXT: ## %bb.4: ## %for.body4.i -; DISABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax -; DISABLE-NEXT: movl (%rax), %edi +; DISABLE-NEXT: je LBB16_4 +; DISABLE-NEXT: ## %bb.3: ## %for.body4.i ; DISABLE-NEXT: xorl %ebx, %ebx ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: callq _something -; DISABLE-NEXT: jmp LBB16_5 -; DISABLE-NEXT: LBB16_3: -; DISABLE-NEXT: xorl %ebx, %ebx ; DISABLE-NEXT: .p2align 4, 0x90 -; DISABLE-NEXT: LBB16_5: ## %for.inc +; DISABLE-NEXT: LBB16_4: ## %for.inc ; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: incl %ebx ; DISABLE-NEXT: cmpl $7, %ebx -; DISABLE-NEXT: jl LBB16_5 -; DISABLE-NEXT: ## %bb.6: ## %fn1.exit +; DISABLE-NEXT: jl LBB16_4 +; DISABLE-NEXT: ## %bb.5: ## %fn1.exit ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: addq $8, %rsp ; DISABLE-NEXT: popq %rbx From 36bf1a9e628dd086537ec14db3fcf4feed1393e9 Mon Sep 17 00:00:00 2001 From: "William S. Moses" Date: Wed, 16 Feb 2022 23:29:42 +0300 Subject: [PATCH 228/316] [NFC][PhaseOrdering] Precommit tests from D119965 (cherry picked from commit 73ee82871e60ab87af7a722ef089ede17e97ea9f) --- .../PhaseOrdering/X86/speculation-vs-tbaa.ll | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll diff --git a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll new file mode 100644 index 0000000000000..6b349b57e5faa --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll @@ -0,0 +1,228 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1 %s +; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2 %s +; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3 %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; We should retain the TBAA on the load here, not lose it. + +define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) { +; OLDPM_O1-LABEL: @licm( +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; OLDPM_O1-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; OLDPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]] +; OLDPM_O1: for.body: +; OLDPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ] +; OLDPM_O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; OLDPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O1-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; OLDPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; OLDPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] +; OLDPM_O1: for.cond.cleanup: +; OLDPM_O1-NEXT: ret void +; +; OLDPM_O2-LABEL: @licm( +; OLDPM_O2-NEXT: entry: +; OLDPM_O2-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; OLDPM_O2-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; OLDPM_O2-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; OLDPM_O2: for.body.preheader: +; OLDPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; OLDPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; OLDPM_O2: vector.ph: +; OLDPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; OLDPM_O2-NEXT: br label [[VECTOR_BODY:%.*]] +; OLDPM_O2: vector.body: +; OLDPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; OLDPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; OLDPM_O2-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; OLDPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; OLDPM_O2-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; OLDPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; OLDPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; OLDPM_O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; OLDPM_O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O2: middle.block: +; OLDPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; OLDPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; OLDPM_O2: for.body.preheader3: +; OLDPM_O2-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O2-NEXT: br label [[FOR_BODY:%.*]] +; OLDPM_O2: for.body: +; OLDPM_O2-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; OLDPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; OLDPM_O2-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; OLDPM_O2-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; OLDPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; OLDPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; OLDPM_O2: for.cond.cleanup: +; OLDPM_O2-NEXT: ret void +; +; OLDPM_O3-LABEL: @licm( +; OLDPM_O3-NEXT: entry: +; OLDPM_O3-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; OLDPM_O3-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; OLDPM_O3-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; OLDPM_O3: for.body.preheader: +; OLDPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; OLDPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; OLDPM_O3: vector.ph: +; OLDPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; OLDPM_O3-NEXT: br label [[VECTOR_BODY:%.*]] +; OLDPM_O3: vector.body: +; OLDPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; OLDPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; OLDPM_O3-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; OLDPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; OLDPM_O3-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; OLDPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; OLDPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; OLDPM_O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; OLDPM_O3-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O3: middle.block: +; OLDPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; OLDPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; OLDPM_O3: for.body.preheader3: +; OLDPM_O3-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O3-NEXT: br label [[FOR_BODY:%.*]] +; OLDPM_O3: for.body: +; OLDPM_O3-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; OLDPM_O3-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; OLDPM_O3-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; OLDPM_O3-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; OLDPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; OLDPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; OLDPM_O3: for.cond.cleanup: +; OLDPM_O3-NEXT: ret void +; +; NEWPM_O1-LABEL: @licm( +; NEWPM_O1-NEXT: entry: +; NEWPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; NEWPM_O1-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; NEWPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]] +; NEWPM_O1: for.body: +; NEWPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ] +; NEWPM_O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; NEWPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O1-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; NEWPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; NEWPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] +; NEWPM_O1: for.cond.cleanup: +; NEWPM_O1-NEXT: ret void +; +; NEWPM_O2-LABEL: @licm( +; NEWPM_O2-NEXT: entry: +; NEWPM_O2-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; NEWPM_O2-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; NEWPM_O2-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; NEWPM_O2: for.body.preheader: +; NEWPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; NEWPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; NEWPM_O2: vector.ph: +; NEWPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; NEWPM_O2-NEXT: br label [[VECTOR_BODY:%.*]] +; NEWPM_O2: vector.body: +; NEWPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; NEWPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; NEWPM_O2-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; NEWPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; NEWPM_O2-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; NEWPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; NEWPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; NEWPM_O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; NEWPM_O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O2: middle.block: +; NEWPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; NEWPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; NEWPM_O2: for.body.preheader3: +; NEWPM_O2-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O2-NEXT: br label [[FOR_BODY:%.*]] +; NEWPM_O2: for.body: +; NEWPM_O2-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; NEWPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; NEWPM_O2-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; NEWPM_O2-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; NEWPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; NEWPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; NEWPM_O2: for.cond.cleanup: +; NEWPM_O2-NEXT: ret void +; +; NEWPM_O3-LABEL: @licm( +; NEWPM_O3-NEXT: entry: +; NEWPM_O3-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; NEWPM_O3-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; NEWPM_O3-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; NEWPM_O3: for.body.preheader: +; NEWPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; NEWPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; NEWPM_O3: vector.ph: +; NEWPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; NEWPM_O3-NEXT: br label [[VECTOR_BODY:%.*]] +; NEWPM_O3: vector.body: +; NEWPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; NEWPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; NEWPM_O3-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; NEWPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; NEWPM_O3-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; NEWPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; NEWPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; NEWPM_O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; NEWPM_O3-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O3: middle.block: +; NEWPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; NEWPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; NEWPM_O3: for.body.preheader3: +; NEWPM_O3-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O3-NEXT: br label [[FOR_BODY:%.*]] +; NEWPM_O3: for.body: +; NEWPM_O3-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; NEWPM_O3-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; NEWPM_O3-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; NEWPM_O3-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; NEWPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; NEWPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; NEWPM_O3: for.cond.cleanup: +; NEWPM_O3-NEXT: ret void +; +entry: + br label %for.cond + +for.cond: ; preds = %for.body, %entry + %k.0 = phi i64 [ 0, %entry ], [ %inc, %for.body ] + %cmp = icmp ult i64 %k.0, %numElem + br i1 %cmp, label %for.body, label %for.cond.cleanup + +for.body: ; preds = %for.cond + %0 = load double*, double** %_M_start.i, align 8, !tbaa !3 + %add.ptr.i = getelementptr inbounds double, double* %0, i64 %k.0 + store double 2.000000e+00, double* %add.ptr.i, align 8, !tbaa !8 + %inc = add nuw i64 %k.0, 1 + br label %for.cond + +for.cond.cleanup: ; preds = %for.cond + ret void +} + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"uwtable", i32 1} +!2 = !{!"clang version 15.0.0 (https://github.com/llvm/llvm-project.git fc510998f7c287df2bc1304673e0cd8452d50b31)"} +!3 = !{!4, !5, i64 0} +!4 = !{!"_ZTSNSt12_Vector_baseIdSaIdEE17_Vector_impl_dataE", !5, i64 0, !5, i64 8, !5, i64 16} +!5 = !{!"any pointer", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C++ TBAA"} +!8 = !{!9, !9, i64 0} +!9 = !{!"double", !6, i64 0} From 1f4613675051f029a769c21996f19aa451ed17db Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 16 Feb 2022 23:39:26 +0300 Subject: [PATCH 229/316] [NFC][PhaseOrdering] spurious-peeling.ll: also test -O1/-O2 results (cherry picked from commit a5b9987aab7601176902bf939fed2653f978450c) --- .../PhaseOrdering/X86/spurious-peeling.ll | 278 ++++++++++++++---- 1 file changed, 215 insertions(+), 63 deletions(-) diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll index 4661bd8a36cce..e8e5ed90e60f1 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll @@ -1,6 +1,10 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck %s --check-prefixes=OLDPM -; RUN: opt -passes='default' -S < %s | FileCheck %s --check-prefixes=NEWPM +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature +; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1 %s +; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2 %s +; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3 %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -12,67 +16,170 @@ target triple = "x86_64-unknown-linux-gnu" $_ZN12FloatVecPair6vecIncEv = comdat any define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FVP) { -; OLDPM-LABEL: @_Z13vecIncFromPtrP12FloatVecPair( -; OLDPM-NEXT: entry: -; OLDPM-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP:%.*]], i64 0, i32 1, i32 0 -; OLDPM-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; OLDPM-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; OLDPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; OLDPM-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; OLDPM-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; OLDPM: for.body7.lr.ph.i: -; OLDPM-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; OLDPM-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; OLDPM-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; OLDPM-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; OLDPM-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] -; OLDPM-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; OLDPM-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] -; OLDPM-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; OLDPM-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; OLDPM-NEXT: br label [[FOR_BODY7_I:%.*]] -; OLDPM: for.body7.i: -; OLDPM-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] -; OLDPM-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; OLDPM-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] -; OLDPM-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; OLDPM-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; OLDPM-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; OLDPM: _ZN12FloatVecPair6vecIncEv.exit: -; OLDPM-NEXT: ret void +; OLDPM_O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; OLDPM_O1-SAME: (%class.FloatVecPair* [[FVP:%.*]]) local_unnamed_addr { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: call void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPair* [[FVP]]) +; OLDPM_O1-NEXT: ret void ; -; NEWPM-LABEL: @_Z13vecIncFromPtrP12FloatVecPair( -; NEWPM-NEXT: entry: -; NEWPM-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP:%.*]], i64 0, i32 1, i32 0 -; NEWPM-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; NEWPM-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; NEWPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; NEWPM-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; NEWPM-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; NEWPM: for.body7.lr.ph.i: -; NEWPM-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; NEWPM-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; NEWPM-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; NEWPM-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; NEWPM-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] -; NEWPM-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; NEWPM-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] -; NEWPM-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; NEWPM-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; NEWPM-NEXT: br label [[FOR_BODY7_I:%.*]] -; NEWPM: for.body7.i: -; NEWPM-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] -; NEWPM-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; NEWPM-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] -; NEWPM-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; NEWPM-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; NEWPM-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; NEWPM: _ZN12FloatVecPair6vecIncEv.exit: -; NEWPM-NEXT: ret void +; OLDPM_O2-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; OLDPM_O2-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; OLDPM_O2-NEXT: entry: +; OLDPM_O2-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; OLDPM_O2-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O2-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; OLDPM_O2-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; OLDPM_O2-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; OLDPM_O2-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; OLDPM_O2: for.body7.lr.ph.i: +; OLDPM_O2-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; OLDPM_O2-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; OLDPM_O2-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; OLDPM_O2-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; OLDPM_O2-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; OLDPM_O2-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] +; OLDPM_O2-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; OLDPM_O2-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; OLDPM_O2-NEXT: br label [[FOR_BODY7_I:%.*]] +; OLDPM_O2: for.body7.i: +; OLDPM_O2-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O2-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O2-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O2-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; OLDPM_O2-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O2-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; OLDPM_O2-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; OLDPM_O2-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; OLDPM_O2: _ZN12FloatVecPair6vecIncEv.exit: +; OLDPM_O2-NEXT: ret void +; +; OLDPM_O3-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; OLDPM_O3-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; OLDPM_O3-NEXT: entry: +; OLDPM_O3-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; OLDPM_O3-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O3-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; OLDPM_O3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; OLDPM_O3-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; OLDPM_O3-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; OLDPM_O3: for.body7.lr.ph.i: +; OLDPM_O3-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; OLDPM_O3-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; OLDPM_O3-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; OLDPM_O3-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; OLDPM_O3-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; OLDPM_O3-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] +; OLDPM_O3-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; OLDPM_O3-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; OLDPM_O3-NEXT: br label [[FOR_BODY7_I:%.*]] +; OLDPM_O3: for.body7.i: +; OLDPM_O3-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O3-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O3-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O3-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; OLDPM_O3-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O3-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; OLDPM_O3-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; OLDPM_O3-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; OLDPM_O3: _ZN12FloatVecPair6vecIncEv.exit: +; OLDPM_O3-NEXT: ret void +; +; NEWPM_O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; NEWPM_O1-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O1-NEXT: entry: +; NEWPM_O1-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; NEWPM_O1-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O1-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; NEWPM_O1-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; NEWPM_O1-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; NEWPM_O1-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; NEWPM_O1: for.body7.lr.ph.i: +; NEWPM_O1-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; NEWPM_O1-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; NEWPM_O1-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; NEWPM_O1-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O1-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] +; NEWPM_O1-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; NEWPM_O1-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] +; NEWPM_O1-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; NEWPM_O1-NEXT: br label [[FOR_BODY7_I:%.*]] +; NEWPM_O1: for.body7.i: +; NEWPM_O1-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O1-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; NEWPM_O1-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O1-NEXT: [[ADD_I:%.*]] = fadd float [[TMP5]], [[TMP6]] +; NEWPM_O1-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O1-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; NEWPM_O1-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; NEWPM_O1-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; NEWPM_O1: _ZN12FloatVecPair6vecIncEv.exit: +; NEWPM_O1-NEXT: ret void +; +; NEWPM_O2-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; NEWPM_O2-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O2-NEXT: entry: +; NEWPM_O2-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; NEWPM_O2-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O2-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; NEWPM_O2-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; NEWPM_O2-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; NEWPM_O2-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; NEWPM_O2: for.body7.lr.ph.i: +; NEWPM_O2-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; NEWPM_O2-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; NEWPM_O2-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; NEWPM_O2-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O2-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; NEWPM_O2-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] +; NEWPM_O2-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; NEWPM_O2-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; NEWPM_O2-NEXT: br label [[FOR_BODY7_I:%.*]] +; NEWPM_O2: for.body7.i: +; NEWPM_O2-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O2-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O2-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O2-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; NEWPM_O2-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O2-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; NEWPM_O2-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; NEWPM_O2-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; NEWPM_O2: _ZN12FloatVecPair6vecIncEv.exit: +; NEWPM_O2-NEXT: ret void +; +; NEWPM_O3-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; NEWPM_O3-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O3-NEXT: entry: +; NEWPM_O3-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; NEWPM_O3-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O3-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; NEWPM_O3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; NEWPM_O3-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; NEWPM_O3-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; NEWPM_O3: for.body7.lr.ph.i: +; NEWPM_O3-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; NEWPM_O3-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; NEWPM_O3-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; NEWPM_O3-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O3-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; NEWPM_O3-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] +; NEWPM_O3-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; NEWPM_O3-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; NEWPM_O3-NEXT: br label [[FOR_BODY7_I:%.*]] +; NEWPM_O3: for.body7.i: +; NEWPM_O3-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O3-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O3-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O3-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; NEWPM_O3-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O3-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; NEWPM_O3-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; NEWPM_O3-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; NEWPM_O3: _ZN12FloatVecPair6vecIncEv.exit: +; NEWPM_O3-NEXT: ret void ; entry: %FVP.addr = alloca %class.FloatVecPair*, align 8 @@ -83,6 +190,35 @@ entry: } define linkonce_odr dso_local void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPair* %this) comdat align 2 { +; OLDPM_O1-LABEL: define {{[^@]+}}@_ZN12FloatVecPair6vecIncEv +; OLDPM_O1-SAME: (%class.FloatVecPair* [[THIS:%.*]]) local_unnamed_addr comdat align 2 { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[VSRC23:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[THIS]], i64 0, i32 1 +; OLDPM_O1-NEXT: [[VSRCDST:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[THIS]], i64 0, i32 0 +; OLDPM_O1-NEXT: [[CALL2:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* nonnull [[VSRC23]]) +; OLDPM_O1-NEXT: [[SIZE43:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[CALL2]], i64 0, i32 1 +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load i32, i32* [[SIZE43]], align 8, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O1-NEXT: [[CMP54_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 +; OLDPM_O1-NEXT: br i1 [[CMP54_NOT]], label [[FOR_COND_CLEANUP6:%.*]], label [[FOR_BODY7:%.*]] +; OLDPM_O1: for.cond.cleanup6: +; OLDPM_O1-NEXT: ret void +; OLDPM_O1: for.body7: +; OLDPM_O1-NEXT: [[J_05:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY7]] ], [ 0, [[ENTRY:%.*]] ] +; OLDPM_O1-NEXT: [[CALL9:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* nonnull [[VSRC23]]) +; OLDPM_O1-NEXT: [[CALL10:%.*]] = call float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* [[CALL9]]) +; OLDPM_O1-NEXT: [[TMP1:%.*]] = load float, float* [[CALL10]], align 4, !tbaa [[TBAA6:![0-9]+]] +; OLDPM_O1-NEXT: [[CALL11:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* [[VSRCDST]]) +; OLDPM_O1-NEXT: [[CALL12:%.*]] = call float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* [[CALL11]]) +; OLDPM_O1-NEXT: [[TMP2:%.*]] = load float, float* [[CALL12]], align 4, !tbaa [[TBAA6]] +; OLDPM_O1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[TMP2]] +; OLDPM_O1-NEXT: store float [[ADD]], float* [[CALL12]], align 4, !tbaa [[TBAA6]] +; OLDPM_O1-NEXT: [[INC]] = add nuw i32 [[J_05]], 1 +; OLDPM_O1-NEXT: [[CALL:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* nonnull [[VSRC23]]) +; OLDPM_O1-NEXT: [[SIZE4:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[CALL]], i64 0, i32 1 +; OLDPM_O1-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIZE4]], align 8, !tbaa [[TBAA0]] +; OLDPM_O1-NEXT: [[CMP5:%.*]] = icmp ult i32 [[INC]], [[TMP3]] +; OLDPM_O1-NEXT: br i1 [[CMP5]], label [[FOR_BODY7]], label [[FOR_COND_CLEANUP6]], !llvm.loop [[LOOP8:![0-9]+]] +; entry: %this.addr = alloca %class.FloatVecPair*, align 8 %j = alloca i32, align 4 @@ -130,6 +266,14 @@ for.inc: ; preds = %for.body7 } define linkonce_odr dso_local %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* %this) align 2 { +; OLDPM_O1-LABEL: define {{[^@]+}}@_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj +; OLDPM_O1-SAME: (%class.HomemadeVector* [[THIS:%.*]]) local_unnamed_addr align 2 { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[BASE:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR:%.*]], %class.HomemadeVector* [[THIS]], i64 0, i32 0 +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE]], align 8, !tbaa [[TBAA10:![0-9]+]] +; OLDPM_O1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef +; OLDPM_O1-NEXT: ret %class.HomemadeVector.0* [[ARRAYIDX]] +; entry: %this.addr = alloca %class.HomemadeVector*, align 8 store %class.HomemadeVector* %this, %class.HomemadeVector** %this.addr, align 8, !tbaa !0 @@ -143,6 +287,14 @@ entry: } define linkonce_odr dso_local float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* %this) align 2 { +; OLDPM_O1-LABEL: define {{[^@]+}}@_ZN14HomemadeVectorIfLj8EEixEj +; OLDPM_O1-SAME: (%class.HomemadeVector.0* [[THIS:%.*]]) local_unnamed_addr align 2 { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[BASE:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[THIS]], i64 0, i32 0 +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load float*, float** [[BASE]], align 8, !tbaa [[TBAA12:![0-9]+]] +; OLDPM_O1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP0]], i64 undef +; OLDPM_O1-NEXT: ret float* [[ARRAYIDX]] +; entry: %this.addr = alloca %class.HomemadeVector.0*, align 8 store %class.HomemadeVector.0* %this, %class.HomemadeVector.0** %this.addr, align 8, !tbaa !0 From 7d1cd3380add0e3ab6e8040717fc1413604d78bf Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Thu, 17 Feb 2022 14:30:02 +0300 Subject: [PATCH 230/316] [NFC][PhaseOrdering] Improve test coverage for D119975 (cherry picked from commit 07cf95942f57a85d9626a1c9ef8b90deb123bdb6) --- .../X86/hoist-load-of-baseptr.ll | 398 ++++++++++++++++++ .../PhaseOrdering/X86/speculation-vs-tbaa.ll | 232 ++++------ .../PhaseOrdering/X86/spurious-peeling.ll | 196 +++------ 3 files changed, 542 insertions(+), 284 deletions(-) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll diff --git a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll new file mode 100644 index 0000000000000..20c3cb029d2ae --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll @@ -0,0 +1,398 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature +; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1 %s +; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2 %s +; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3 %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%"class.std::vector" = type { %"struct.std::_Vector_base" } +%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base>::_Vector_impl" } +%"struct.std::_Vector_base>::_Vector_impl" = type { %"struct.std::_Vector_base>::_Vector_impl_data" } +%"struct.std::_Vector_base>::_Vector_impl_data" = type { i32*, i32*, i32* } + +$_ZNSt6vectorIiSaIiEEixEm = comdat any + +define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %data, i64 noundef %numElems) { +; OLDPM_O1-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; OLDPM_O1-SAME: (%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; OLDPM_O1-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] +; OLDPM_O1: for.cond1.preheader: +; OLDPM_O1-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] +; OLDPM_O1-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4:%.*]] +; OLDPM_O1: for.cond.cleanup: +; OLDPM_O1-NEXT: ret void +; OLDPM_O1: for.cond.cleanup3: +; OLDPM_O1-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1 +; OLDPM_O1-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100 +; OLDPM_O1-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]] +; OLDPM_O1: for.body4: +; OLDPM_O1-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ 0, [[FOR_COND1_PREHEADER]] ] +; OLDPM_O1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) [[DATA]], i64 noundef [[J_07]]) +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CALL]], align 4, !tbaa [[TBAA2:![0-9]+]] +; OLDPM_O1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 +; OLDPM_O1-NEXT: store i32 [[INC]], i32* [[CALL]], align 4, !tbaa [[TBAA2]] +; OLDPM_O1-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1 +; OLDPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]] +; OLDPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP6:![0-9]+]] +; +; OLDPM_O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; OLDPM_O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; OLDPM_O2-NEXT: entry: +; OLDPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; OLDPM_O2-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; OLDPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 +; OLDPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 +; OLDPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] +; OLDPM_O2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] +; OLDPM_O2: for.cond1.preheader: +; OLDPM_O2-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] +; OLDPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 +; OLDPM_O2-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]] +; OLDPM_O2: for.body4.preheader: +; OLDPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER11:%.*]], label [[VECTOR_BODY:%.*]] +; OLDPM_O2: vector.body: +; OLDPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_BODY4_PREHEADER]] ] +; OLDPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]] +; OLDPM_O2-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; OLDPM_O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4 +; OLDPM_O2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; OLDPM_O2-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], +; OLDPM_O2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD10]], +; OLDPM_O2-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; OLDPM_O2-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; OLDPM_O2-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; OLDPM_O2-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; OLDPM_O2-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; OLDPM_O2: middle.block: +; OLDPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER11]] +; OLDPM_O2: for.body4.preheader11: +; OLDPM_O2-NEXT: [[J_07_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O2-NEXT: br label [[FOR_BODY4:%.*]] +; OLDPM_O2: for.cond.cleanup: +; OLDPM_O2-NEXT: ret void +; OLDPM_O2: for.cond.cleanup3: +; OLDPM_O2-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1 +; OLDPM_O2-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100 +; OLDPM_O2-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O2: for.body4: +; OLDPM_O2-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ [[J_07_PH]], [[FOR_BODY4_PREHEADER11]] ] +; OLDPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07]] +; OLDPM_O2-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +; OLDPM_O2-NEXT: store i32 [[INC]], i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]] +; OLDPM_O2-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1 +; OLDPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]] +; OLDPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP8:![0-9]+]] +; +; OLDPM_O3-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; OLDPM_O3-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; OLDPM_O3-NEXT: entry: +; OLDPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; OLDPM_O3-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; OLDPM_O3-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] +; OLDPM_O3: for.cond1.preheader.us.preheader: +; OLDPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 +; OLDPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 +; OLDPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] +; OLDPM_O3-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] +; OLDPM_O3: for.cond1.preheader.us: +; OLDPM_O3-NEXT: [[I_08_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] +; OLDPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 +; OLDPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_US_PREHEADER:%.*]], label [[VECTOR_BODY:%.*]] +; OLDPM_O3: vector.body: +; OLDPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ] +; OLDPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]] +; OLDPM_O3-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; OLDPM_O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4 +; OLDPM_O3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; OLDPM_O3-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], +; OLDPM_O3-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD11]], +; OLDPM_O3-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; OLDPM_O3-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; OLDPM_O3-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; OLDPM_O3-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; OLDPM_O3-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; OLDPM_O3: middle.block: +; OLDPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US_PREHEADER]] +; OLDPM_O3: for.body4.us.preheader: +; OLDPM_O3-NEXT: [[J_07_US_PH:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O3-NEXT: br label [[FOR_BODY4_US:%.*]] +; OLDPM_O3: for.body4.us: +; OLDPM_O3-NEXT: [[J_07_US:%.*]] = phi i64 [ [[INC5_US:%.*]], [[FOR_BODY4_US]] ], [ [[J_07_US_PH]], [[FOR_BODY4_US_PREHEADER]] ] +; OLDPM_O3-NEXT: [[ADD_PTR_I_US:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07_US]] +; OLDPM_O3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[INC_US:%.*]] = add nsw i32 [[TMP10]], 1 +; OLDPM_O3-NEXT: store i32 [[INC_US]], i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]] +; OLDPM_O3-NEXT: [[INC5_US]] = add nuw i64 [[J_07_US]], 1 +; OLDPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5_US]], [[NUMELEMS]] +; OLDPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O3: for.cond1.for.cond.cleanup3_crit_edge.us: +; OLDPM_O3-NEXT: [[INC7_US]] = add nuw nsw i64 [[I_08_US]], 1 +; OLDPM_O3-NEXT: [[EXITCOND10_NOT:%.*]] = icmp eq i64 [[INC7_US]], 100 +; OLDPM_O3-NEXT: br i1 [[EXITCOND10_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]], !llvm.loop [[LOOP9:![0-9]+]] +; OLDPM_O3: for.cond.cleanup: +; OLDPM_O3-NEXT: ret void +; +; NEWPM_O1-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; NEWPM_O1-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O1-NEXT: entry: +; NEWPM_O1-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O1-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O1-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] +; NEWPM_O1: for.cond1.preheader: +; NEWPM_O1-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] +; NEWPM_O1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 +; NEWPM_O1-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4:%.*]] +; NEWPM_O1: for.cond.cleanup: +; NEWPM_O1-NEXT: ret void +; NEWPM_O1: for.cond.cleanup3: +; NEWPM_O1-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1 +; NEWPM_O1-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100 +; NEWPM_O1-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]] +; NEWPM_O1: for.body4: +; NEWPM_O1-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ 0, [[FOR_COND1_PREHEADER]] ] +; NEWPM_O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07]] +; NEWPM_O1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA2:![0-9]+]] +; NEWPM_O1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 +; NEWPM_O1-NEXT: store i32 [[INC]], i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA2]] +; NEWPM_O1-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1 +; NEWPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]] +; NEWPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP6:![0-9]+]] +; +; NEWPM_O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; NEWPM_O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O2-NEXT: entry: +; NEWPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O2-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 +; NEWPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 +; NEWPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] +; NEWPM_O2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] +; NEWPM_O2: for.cond1.preheader: +; NEWPM_O2-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] +; NEWPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 +; NEWPM_O2-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]] +; NEWPM_O2: for.body4.preheader: +; NEWPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER11:%.*]], label [[VECTOR_BODY:%.*]] +; NEWPM_O2: vector.body: +; NEWPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_BODY4_PREHEADER]] ] +; NEWPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]] +; NEWPM_O2-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; NEWPM_O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4 +; NEWPM_O2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; NEWPM_O2-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], +; NEWPM_O2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD10]], +; NEWPM_O2-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; NEWPM_O2-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; NEWPM_O2-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; NEWPM_O2-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; NEWPM_O2-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; NEWPM_O2: middle.block: +; NEWPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER11]] +; NEWPM_O2: for.body4.preheader11: +; NEWPM_O2-NEXT: [[J_07_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O2-NEXT: br label [[FOR_BODY4:%.*]] +; NEWPM_O2: for.cond.cleanup: +; NEWPM_O2-NEXT: ret void +; NEWPM_O2: for.cond.cleanup3: +; NEWPM_O2-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1 +; NEWPM_O2-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100 +; NEWPM_O2-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O2: for.body4: +; NEWPM_O2-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ [[J_07_PH]], [[FOR_BODY4_PREHEADER11]] ] +; NEWPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07]] +; NEWPM_O2-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +; NEWPM_O2-NEXT: store i32 [[INC]], i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]] +; NEWPM_O2-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1 +; NEWPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]] +; NEWPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP8:![0-9]+]] +; +; NEWPM_O3-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy +; NEWPM_O3-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O3-NEXT: entry: +; NEWPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O3-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O3-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] +; NEWPM_O3: for.cond1.preheader.us.preheader: +; NEWPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 +; NEWPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 +; NEWPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] +; NEWPM_O3-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] +; NEWPM_O3: for.cond1.preheader.us: +; NEWPM_O3-NEXT: [[I_08_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] +; NEWPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 +; NEWPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_US_PREHEADER:%.*]], label [[VECTOR_BODY:%.*]] +; NEWPM_O3: vector.body: +; NEWPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ] +; NEWPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]] +; NEWPM_O3-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; NEWPM_O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4 +; NEWPM_O3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; NEWPM_O3-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], +; NEWPM_O3-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD11]], +; NEWPM_O3-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>* +; NEWPM_O3-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>* +; NEWPM_O3-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; NEWPM_O3-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; NEWPM_O3-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; NEWPM_O3: middle.block: +; NEWPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US_PREHEADER]] +; NEWPM_O3: for.body4.us.preheader: +; NEWPM_O3-NEXT: [[J_07_US_PH:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O3-NEXT: br label [[FOR_BODY4_US:%.*]] +; NEWPM_O3: for.body4.us: +; NEWPM_O3-NEXT: [[J_07_US:%.*]] = phi i64 [ [[INC5_US:%.*]], [[FOR_BODY4_US]] ], [ [[J_07_US_PH]], [[FOR_BODY4_US_PREHEADER]] ] +; NEWPM_O3-NEXT: [[ADD_PTR_I_US:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07_US]] +; NEWPM_O3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[INC_US:%.*]] = add nsw i32 [[TMP10]], 1 +; NEWPM_O3-NEXT: store i32 [[INC_US]], i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]] +; NEWPM_O3-NEXT: [[INC5_US]] = add nuw i64 [[J_07_US]], 1 +; NEWPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5_US]], [[NUMELEMS]] +; NEWPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O3: for.cond1.for.cond.cleanup3_crit_edge.us: +; NEWPM_O3-NEXT: [[INC7_US]] = add nuw nsw i64 [[I_08_US]], 1 +; NEWPM_O3-NEXT: [[EXITCOND10_NOT:%.*]] = icmp eq i64 [[INC7_US]], 100 +; NEWPM_O3-NEXT: br i1 [[EXITCOND10_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]], !llvm.loop [[LOOP9:![0-9]+]] +; NEWPM_O3: for.cond.cleanup: +; NEWPM_O3-NEXT: ret void +; +entry: + %data.addr = alloca %"class.std::vector"*, align 8 + %numElems.addr = alloca i64, align 8 + %i = alloca i64, align 8 + %cleanup.dest.slot = alloca i32, align 4 + %j = alloca i64, align 8 + store %"class.std::vector"* %data, %"class.std::vector"** %data.addr, align 8, !tbaa !3 + store i64 %numElems, i64* %numElems.addr, align 8, !tbaa !7 + %0 = bitcast i64* %i to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) + store i64 0, i64* %i, align 8, !tbaa !7 + br label %for.cond + +for.cond: + %1 = load i64, i64* %i, align 8, !tbaa !7 + %cmp = icmp ult i64 %1, 100 + br i1 %cmp, label %for.body, label %for.cond.cleanup + +for.cond.cleanup: + store i32 2, i32* %cleanup.dest.slot, align 4 + %2 = bitcast i64* %i to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %2) + br label %for.end8 + +for.body: + %3 = bitcast i64* %j to i8* + call void @llvm.lifetime.start.p0i8(i64 8, i8* %3) + store i64 0, i64* %j, align 8, !tbaa !7 + br label %for.cond1 + +for.cond1: + %4 = load i64, i64* %j, align 8, !tbaa !7 + %5 = load i64, i64* %numElems.addr, align 8, !tbaa !7 + %cmp2 = icmp ult i64 %4, %5 + br i1 %cmp2, label %for.body4, label %for.cond.cleanup3 + +for.cond.cleanup3: + store i32 5, i32* %cleanup.dest.slot, align 4 + %6 = bitcast i64* %j to i8* + call void @llvm.lifetime.end.p0i8(i64 8, i8* %6) + br label %for.end + +for.body4: + %7 = load %"class.std::vector"*, %"class.std::vector"** %data.addr, align 8, !tbaa !3 + %8 = load i64, i64* %j, align 8, !tbaa !7 + %call = call noundef nonnull align 4 dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %8) + %9 = load i32, i32* %call, align 4, !tbaa !9 + %inc = add nsw i32 %9, 1 + store i32 %inc, i32* %call, align 4, !tbaa !9 + br label %for.inc + +for.inc: + %10 = load i64, i64* %j, align 8, !tbaa !7 + %inc5 = add i64 %10, 1 + store i64 %inc5, i64* %j, align 8, !tbaa !7 + br label %for.cond1, !llvm.loop !11 + +for.end: + br label %for.inc6 + +for.inc6: + %11 = load i64, i64* %i, align 8, !tbaa !7 + %inc7 = add i64 %11, 1 + store i64 %inc7, i64* %i, align 8, !tbaa !7 + br label %for.cond, !llvm.loop !13 + +for.end8: + ret void +} + +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + +define linkonce_odr dso_local noundef nonnull align 4 dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %this, i64 noundef %__n) comdat align 2 { +; OLDPM_O1-LABEL: define {{[^@]+}}@_ZNSt6vectorIiSaIiEEixEm +; OLDPM_O1-SAME: (%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[__N:%.*]]) local_unnamed_addr comdat align 2 { +; OLDPM_O1-NEXT: entry: +; OLDPM_O1-NEXT: [[_M_START:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[THIS]], i64 0, i32 0, i32 0, i32 0, i32 0 +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START]], align 8, !tbaa [[TBAA7:![0-9]+]] +; OLDPM_O1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[__N]] +; OLDPM_O1-NEXT: ret i32* [[ADD_PTR]] +; +entry: + %this.addr = alloca %"class.std::vector"*, align 8 + %__n.addr = alloca i64, align 8 + store %"class.std::vector"* %this, %"class.std::vector"** %this.addr, align 8, !tbaa !3 + store i64 %__n, i64* %__n.addr, align 8, !tbaa !14 + %this1 = load %"class.std::vector"*, %"class.std::vector"** %this.addr, align 8 + %0 = bitcast %"class.std::vector"* %this1 to %"struct.std::_Vector_base"* + %_M_impl = getelementptr inbounds %"struct.std::_Vector_base", %"struct.std::_Vector_base"* %0, i32 0, i32 0 + %1 = bitcast %"struct.std::_Vector_base>::_Vector_impl"* %_M_impl to %"struct.std::_Vector_base>::_Vector_impl_data"* + %_M_start = getelementptr inbounds %"struct.std::_Vector_base>::_Vector_impl_data", %"struct.std::_Vector_base>::_Vector_impl_data"* %1, i32 0, i32 0 + %2 = load i32*, i32** %_M_start, align 8, !tbaa !16 + %3 = load i64, i64* %__n.addr, align 8, !tbaa !14 + %add.ptr = getelementptr inbounds i32, i32* %2, i64 %3 + ret i32* %add.ptr +} + +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"uwtable", i32 2} +!2 = !{!"clang version 15.0.0 (https://github.com/llvm/llvm-project.git 69297cf639044acf48dd5d9b39b95c54dd50561d)"} +!3 = !{!4, !4, i64 0} +!4 = !{!"any pointer", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C++ TBAA"} +!7 = !{!8, !8, i64 0} +!8 = !{!"long long", !5, i64 0} +!9 = !{!10, !10, i64 0} +!10 = !{!"int", !5, i64 0} +!11 = distinct !{!11, !12} +!12 = !{!"llvm.loop.mustprogress"} +!13 = distinct !{!13, !12} +!14 = !{!15, !15, i64 0} +!15 = !{!"long", !5, i64 0} +!16 = !{!17, !4, i64 0} +!17 = !{!"_ZTSNSt12_Vector_baseIiSaIiEE17_Vector_impl_dataE", !4, i64 0, !4, i64 8, !4, i64 16} diff --git a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll index 6b349b57e5faa..3ac9104708405 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1 %s -; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2 %s -; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3 %s +; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O23 %s +; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O23 %s ; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1 %s -; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2 %s -; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O23 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O23 %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -27,81 +27,43 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; OLDPM_O1: for.cond.cleanup: ; OLDPM_O1-NEXT: ret void ; -; OLDPM_O2-LABEL: @licm( -; OLDPM_O2-NEXT: entry: -; OLDPM_O2-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 -; OLDPM_O2-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; OLDPM_O2-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; OLDPM_O2: for.body.preheader: -; OLDPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; OLDPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] -; OLDPM_O2: vector.ph: -; OLDPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 -; OLDPM_O2-NEXT: br label [[VECTOR_BODY:%.*]] -; OLDPM_O2: vector.body: -; OLDPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; OLDPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] -; OLDPM_O2-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; OLDPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] -; OLDPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 -; OLDPM_O2-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; OLDPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] -; OLDPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; OLDPM_O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; OLDPM_O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] -; OLDPM_O2: middle.block: -; OLDPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; OLDPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; OLDPM_O2: for.body.preheader3: -; OLDPM_O2-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] -; OLDPM_O2-NEXT: br label [[FOR_BODY:%.*]] -; OLDPM_O2: for.body: -; OLDPM_O2-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] -; OLDPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; OLDPM_O2-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] -; OLDPM_O2-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 -; OLDPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; OLDPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] -; OLDPM_O2: for.cond.cleanup: -; OLDPM_O2-NEXT: ret void -; -; OLDPM_O3-LABEL: @licm( -; OLDPM_O3-NEXT: entry: -; OLDPM_O3-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 -; OLDPM_O3-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; OLDPM_O3-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; OLDPM_O3: for.body.preheader: -; OLDPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; OLDPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] -; OLDPM_O3: vector.ph: -; OLDPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 -; OLDPM_O3-NEXT: br label [[VECTOR_BODY:%.*]] -; OLDPM_O3: vector.body: -; OLDPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; OLDPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] -; OLDPM_O3-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; OLDPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] -; OLDPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 -; OLDPM_O3-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; OLDPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] -; OLDPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; OLDPM_O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; OLDPM_O3-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] -; OLDPM_O3: middle.block: -; OLDPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; OLDPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; OLDPM_O3: for.body.preheader3: -; OLDPM_O3-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] -; OLDPM_O3-NEXT: br label [[FOR_BODY:%.*]] -; OLDPM_O3: for.body: -; OLDPM_O3-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] -; OLDPM_O3-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; OLDPM_O3-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] -; OLDPM_O3-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 -; OLDPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; OLDPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] -; OLDPM_O3: for.cond.cleanup: -; OLDPM_O3-NEXT: ret void +; OLDPM_O23-LABEL: @licm( +; OLDPM_O23-NEXT: entry: +; OLDPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; OLDPM_O23-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; OLDPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; OLDPM_O23: for.body.preheader: +; OLDPM_O23-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; OLDPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; OLDPM_O23: vector.ph: +; OLDPM_O23-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; OLDPM_O23-NEXT: br label [[VECTOR_BODY:%.*]] +; OLDPM_O23: vector.body: +; OLDPM_O23-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; OLDPM_O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; OLDPM_O23-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; OLDPM_O23-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; OLDPM_O23-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; OLDPM_O23-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; OLDPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O23: middle.block: +; OLDPM_O23-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; OLDPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; OLDPM_O23: for.body.preheader3: +; OLDPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O23-NEXT: br label [[FOR_BODY:%.*]] +; OLDPM_O23: for.body: +; OLDPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; OLDPM_O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; OLDPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; OLDPM_O23-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; OLDPM_O23-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; OLDPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; OLDPM_O23: for.cond.cleanup: +; OLDPM_O23-NEXT: ret void ; ; NEWPM_O1-LABEL: @licm( ; NEWPM_O1-NEXT: entry: @@ -118,81 +80,43 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; NEWPM_O1: for.cond.cleanup: ; NEWPM_O1-NEXT: ret void ; -; NEWPM_O2-LABEL: @licm( -; NEWPM_O2-NEXT: entry: -; NEWPM_O2-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 -; NEWPM_O2-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; NEWPM_O2-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; NEWPM_O2: for.body.preheader: -; NEWPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; NEWPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] -; NEWPM_O2: vector.ph: -; NEWPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 -; NEWPM_O2-NEXT: br label [[VECTOR_BODY:%.*]] -; NEWPM_O2: vector.body: -; NEWPM_O2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; NEWPM_O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] -; NEWPM_O2-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; NEWPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] -; NEWPM_O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 -; NEWPM_O2-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; NEWPM_O2-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] -; NEWPM_O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; NEWPM_O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; NEWPM_O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] -; NEWPM_O2: middle.block: -; NEWPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; NEWPM_O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; NEWPM_O2: for.body.preheader3: -; NEWPM_O2-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] -; NEWPM_O2-NEXT: br label [[FOR_BODY:%.*]] -; NEWPM_O2: for.body: -; NEWPM_O2-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] -; NEWPM_O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; NEWPM_O2-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] -; NEWPM_O2-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 -; NEWPM_O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; NEWPM_O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] -; NEWPM_O2: for.cond.cleanup: -; NEWPM_O2-NEXT: ret void -; -; NEWPM_O3-LABEL: @licm( -; NEWPM_O3-NEXT: entry: -; NEWPM_O3-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 -; NEWPM_O3-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; NEWPM_O3-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; NEWPM_O3: for.body.preheader: -; NEWPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; NEWPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] -; NEWPM_O3: vector.ph: -; NEWPM_O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 -; NEWPM_O3-NEXT: br label [[VECTOR_BODY:%.*]] -; NEWPM_O3: vector.body: -; NEWPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; NEWPM_O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] -; NEWPM_O3-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; NEWPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] -; NEWPM_O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 -; NEWPM_O3-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; NEWPM_O3-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] -; NEWPM_O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; NEWPM_O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; NEWPM_O3-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] -; NEWPM_O3: middle.block: -; NEWPM_O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; NEWPM_O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; NEWPM_O3: for.body.preheader3: -; NEWPM_O3-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] -; NEWPM_O3-NEXT: br label [[FOR_BODY:%.*]] -; NEWPM_O3: for.body: -; NEWPM_O3-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] -; NEWPM_O3-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; NEWPM_O3-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] -; NEWPM_O3-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 -; NEWPM_O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; NEWPM_O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] -; NEWPM_O3: for.cond.cleanup: -; NEWPM_O3-NEXT: ret void +; NEWPM_O23-LABEL: @licm( +; NEWPM_O23-NEXT: entry: +; NEWPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 +; NEWPM_O23-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 +; NEWPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; NEWPM_O23: for.body.preheader: +; NEWPM_O23-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 +; NEWPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; NEWPM_O23: vector.ph: +; NEWPM_O23-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 +; NEWPM_O23-NEXT: br label [[VECTOR_BODY:%.*]] +; NEWPM_O23: vector.body: +; NEWPM_O23-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; NEWPM_O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] +; NEWPM_O23-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* +; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 +; NEWPM_O23-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* +; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; NEWPM_O23-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; NEWPM_O23-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; NEWPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O23: middle.block: +; NEWPM_O23-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] +; NEWPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] +; NEWPM_O23: for.body.preheader3: +; NEWPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O23-NEXT: br label [[FOR_BODY:%.*]] +; NEWPM_O23: for.body: +; NEWPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; NEWPM_O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] +; NEWPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; NEWPM_O23-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 +; NEWPM_O23-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] +; NEWPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; NEWPM_O23: for.cond.cleanup: +; NEWPM_O23-NEXT: ret void ; entry: br label %for.cond diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll index e8e5ed90e60f1..f75c7d6ea1316 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature ; RUN: opt -O1 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O1 %s -; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O2 %s -; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O3 %s +; RUN: opt -O2 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O23 %s +; RUN: opt -O3 -S -enable-new-pm=0 < %s | FileCheck --check-prefixes=OLDPM_O23 %s ; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O1 %s -; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O2 %s -; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O3 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O23 %s +; RUN: opt -passes='default' -S < %s | FileCheck --check-prefixes=NEWPM_O23 %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -22,69 +22,37 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FV ; OLDPM_O1-NEXT: call void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPair* [[FVP]]) ; OLDPM_O1-NEXT: ret void ; -; OLDPM_O2-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair -; OLDPM_O2-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -; OLDPM_O2-NEXT: entry: -; OLDPM_O2-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 -; OLDPM_O2-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; OLDPM_O2-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; OLDPM_O2-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; OLDPM_O2-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; OLDPM_O2-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; OLDPM_O2: for.body7.lr.ph.i: -; OLDPM_O2-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; OLDPM_O2-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; OLDPM_O2-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; OLDPM_O2-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; OLDPM_O2-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] -; OLDPM_O2-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; OLDPM_O2-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] -; OLDPM_O2-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; OLDPM_O2-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; OLDPM_O2-NEXT: br label [[FOR_BODY7_I:%.*]] -; OLDPM_O2: for.body7.i: -; OLDPM_O2-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM_O2-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM_O2-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] -; OLDPM_O2-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; OLDPM_O2-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] -; OLDPM_O2-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; OLDPM_O2-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; OLDPM_O2-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; OLDPM_O2: _ZN12FloatVecPair6vecIncEv.exit: -; OLDPM_O2-NEXT: ret void -; -; OLDPM_O3-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair -; OLDPM_O3-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -; OLDPM_O3-NEXT: entry: -; OLDPM_O3-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 -; OLDPM_O3-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; OLDPM_O3-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; OLDPM_O3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; OLDPM_O3-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; OLDPM_O3-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; OLDPM_O3: for.body7.lr.ph.i: -; OLDPM_O3-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; OLDPM_O3-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; OLDPM_O3-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; OLDPM_O3-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; OLDPM_O3-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] -; OLDPM_O3-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; OLDPM_O3-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] -; OLDPM_O3-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; OLDPM_O3-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; OLDPM_O3-NEXT: br label [[FOR_BODY7_I:%.*]] -; OLDPM_O3: for.body7.i: -; OLDPM_O3-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM_O3-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; OLDPM_O3-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] -; OLDPM_O3-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; OLDPM_O3-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] -; OLDPM_O3-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; OLDPM_O3-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; OLDPM_O3-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; OLDPM_O3: _ZN12FloatVecPair6vecIncEv.exit: -; OLDPM_O3-NEXT: ret void +; OLDPM_O23-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; OLDPM_O23-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; OLDPM_O23-NEXT: entry: +; OLDPM_O23-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; OLDPM_O23-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; OLDPM_O23-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; OLDPM_O23-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; OLDPM_O23-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; OLDPM_O23-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; OLDPM_O23: for.body7.lr.ph.i: +; OLDPM_O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; OLDPM_O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; OLDPM_O23-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; OLDPM_O23-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; OLDPM_O23-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] +; OLDPM_O23-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; OLDPM_O23-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] +; OLDPM_O23-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; OLDPM_O23-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; OLDPM_O23-NEXT: br label [[FOR_BODY7_I:%.*]] +; OLDPM_O23: for.body7.i: +; OLDPM_O23-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O23-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; OLDPM_O23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I7_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O23-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; OLDPM_O23-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]] +; OLDPM_O23-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; OLDPM_O23-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; OLDPM_O23-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; OLDPM_O23: _ZN12FloatVecPair6vecIncEv.exit: +; OLDPM_O23-NEXT: ret void ; ; NEWPM_O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair ; NEWPM_O1-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { @@ -117,69 +85,37 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FV ; NEWPM_O1: _ZN12FloatVecPair6vecIncEv.exit: ; NEWPM_O1-NEXT: ret void ; -; NEWPM_O2-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair -; NEWPM_O2-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -; NEWPM_O2-NEXT: entry: -; NEWPM_O2-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 -; NEWPM_O2-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; NEWPM_O2-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; NEWPM_O2-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; NEWPM_O2-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; NEWPM_O2-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; NEWPM_O2: for.body7.lr.ph.i: -; NEWPM_O2-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; NEWPM_O2-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; NEWPM_O2-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; NEWPM_O2-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; NEWPM_O2-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] -; NEWPM_O2-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; NEWPM_O2-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] -; NEWPM_O2-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; NEWPM_O2-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; NEWPM_O2-NEXT: br label [[FOR_BODY7_I:%.*]] -; NEWPM_O2: for.body7.i: -; NEWPM_O2-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM_O2-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM_O2-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] -; NEWPM_O2-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; NEWPM_O2-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] -; NEWPM_O2-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; NEWPM_O2-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; NEWPM_O2-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; NEWPM_O2: _ZN12FloatVecPair6vecIncEv.exit: -; NEWPM_O2-NEXT: ret void -; -; NEWPM_O3-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair -; NEWPM_O3-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -; NEWPM_O3-NEXT: entry: -; NEWPM_O3-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 -; NEWPM_O3-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] -; NEWPM_O3-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 -; NEWPM_O3-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] -; NEWPM_O3-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 -; NEWPM_O3-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] -; NEWPM_O3: for.body7.lr.ph.i: -; NEWPM_O3-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 -; NEWPM_O3-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 -; NEWPM_O3-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] -; NEWPM_O3-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef -; NEWPM_O3-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] -; NEWPM_O3-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 -; NEWPM_O3-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] -; NEWPM_O3-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef -; NEWPM_O3-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] -; NEWPM_O3-NEXT: br label [[FOR_BODY7_I:%.*]] -; NEWPM_O3: for.body7.i: -; NEWPM_O3-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM_O3-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] -; NEWPM_O3-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] -; NEWPM_O3-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] -; NEWPM_O3-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] -; NEWPM_O3-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 -; NEWPM_O3-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] -; NEWPM_O3-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] -; NEWPM_O3: _ZN12FloatVecPair6vecIncEv.exit: -; NEWPM_O3-NEXT: ret void +; NEWPM_O23-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair +; NEWPM_O23-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; NEWPM_O23-NEXT: entry: +; NEWPM_O23-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0 +; NEWPM_O23-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]] +; NEWPM_O23-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1 +; NEWPM_O23-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]] +; NEWPM_O23-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 +; NEWPM_O23-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] +; NEWPM_O23: for.body7.lr.ph.i: +; NEWPM_O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 +; NEWPM_O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 +; NEWPM_O23-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] +; NEWPM_O23-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O23-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] +; NEWPM_O23-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 +; NEWPM_O23-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] +; NEWPM_O23-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef +; NEWPM_O23-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]] +; NEWPM_O23-NEXT: br label [[FOR_BODY7_I:%.*]] +; NEWPM_O23: for.body7.i: +; NEWPM_O23-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O23-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ] +; NEWPM_O23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O23-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]] +; NEWPM_O23-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]] +; NEWPM_O23-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1 +; NEWPM_O23-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]] +; NEWPM_O23-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]] +; NEWPM_O23: _ZN12FloatVecPair6vecIncEv.exit: +; NEWPM_O23-NEXT: ret void ; entry: %FVP.addr = alloca %class.FloatVecPair*, align 8 From 2de2a2bba998f4145cfd4298d39bfd5e98485bdd Mon Sep 17 00:00:00 2001 From: "William S. Moses" Date: Sat, 12 Feb 2022 16:33:22 -0500 Subject: [PATCH 231/316] [LICM][PhaseOrder] Don't speculate in LICM until after running loop rotate LICM will speculatively hoist code outside of loops. This requires removing information, like alias analysis (https://github.com/llvm/llvm-project/issues/53794), range information (https://bugs.llvm.org/show_bug.cgi?id=50550), among others. Prior to https://reviews.llvm.org/D99249 , LICM would only be run after LoopRotate. Running Loop Rotate prior to LICM prevents a instruction hoist from being speculative, if it was conditionally executed by the iteration (as is commonly emitted by clang and other frontends). Adding the additional LICM pass first, however, forces all of these instructions to be considered speculative, even if they are not speculative after LoopRotate. This destroys information, resulting in performance losses for discarding this additional information. This PR modifies LICM to accept a ``speculative'' parameter which allows LICM to be set to perform information-loss speculative hoists or not. Phase ordering is then modified to not perform the information-losing speculative hoists until after loop rotate is performed, preserving this additional information. Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D119965 (cherry picked from commit d9da6a535f21946cfaac1516ef28ac7646211d56) --- llvm/include/llvm/Transforms/Scalar.h | 3 +- llvm/include/llvm/Transforms/Scalar/LICM.h | 20 ++++-- .../include/llvm/Transforms/Utils/LoopUtils.h | 9 ++- llvm/lib/Passes/PassBuilderPipelines.cpp | 34 ++++++--- .../lib/Transforms/IPO/PassManagerBuilder.cpp | 26 ++++--- llvm/lib/Transforms/Scalar/LICM.cpp | 71 +++++++++--------- .../AArch64/runtime-unroll-generic.ll | 20 +++--- .../AArch64/matrix-extract-insert.ll | 12 ++-- .../X86/hoist-load-of-baseptr.ll | 20 +++--- .../PhaseOrdering/X86/speculation-vs-tbaa.ll | 72 ++++++++++--------- .../PhaseOrdering/X86/spurious-peeling.ll | 14 ++-- 11 files changed, 177 insertions(+), 124 deletions(-) diff --git a/llvm/include/llvm/Transforms/Scalar.h b/llvm/include/llvm/Transforms/Scalar.h index d6228700aa9ac..4d6874f784efb 100644 --- a/llvm/include/llvm/Transforms/Scalar.h +++ b/llvm/include/llvm/Transforms/Scalar.h @@ -133,7 +133,8 @@ Pass *createIndVarSimplifyPass(); // Pass *createLICMPass(); Pass *createLICMPass(unsigned LicmMssaOptCap, - unsigned LicmMssaNoAccForPromotionCap); + unsigned LicmMssaNoAccForPromotionCap, + bool AllowSpeculation); //===----------------------------------------------------------------------===// // diff --git a/llvm/include/llvm/Transforms/Scalar/LICM.h b/llvm/include/llvm/Transforms/Scalar/LICM.h index 751f75c0ccb24..503c8792d3092 100644 --- a/llvm/include/llvm/Transforms/Scalar/LICM.h +++ b/llvm/include/llvm/Transforms/Scalar/LICM.h @@ -46,14 +46,18 @@ extern cl::opt SetLicmMssaNoAccForPromotionCap; class LICMPass : public PassInfoMixin { unsigned LicmMssaOptCap; unsigned LicmMssaNoAccForPromotionCap; + bool LicmAllowSpeculation; public: LICMPass() : LicmMssaOptCap(SetLicmMssaOptCap), - LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap) {} - LICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap) + LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap), + LicmAllowSpeculation(true) {} + LICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap, + bool LicmAllowSpeculation) : LicmMssaOptCap(LicmMssaOptCap), - LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap) {} + LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap), + LicmAllowSpeculation(LicmAllowSpeculation) {} PreservedAnalyses run(Loop &L, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &U); }; @@ -62,14 +66,18 @@ class LICMPass : public PassInfoMixin { class LNICMPass : public PassInfoMixin { unsigned LicmMssaOptCap; unsigned LicmMssaNoAccForPromotionCap; + bool LicmAllowSpeculation; public: LNICMPass() : LicmMssaOptCap(SetLicmMssaOptCap), - LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap) {} - LNICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap) + LicmMssaNoAccForPromotionCap(SetLicmMssaNoAccForPromotionCap), + LicmAllowSpeculation(true) {} + LNICMPass(unsigned LicmMssaOptCap, unsigned LicmMssaNoAccForPromotionCap, + bool LicmAllowSpeculation) : LicmMssaOptCap(LicmMssaOptCap), - LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap) {} + LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap), + LicmAllowSpeculation(LicmAllowSpeculation) {} PreservedAnalyses run(LoopNest &L, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &U); }; diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h index 3a712d78df671..134f8bcfd8886 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h +++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h @@ -171,10 +171,13 @@ bool sinkRegionForLoopNest(DomTreeNode *, AAResults *, LoopInfo *, /// BlockFrequencyInfo, TargetLibraryInfo, Loop, AliasSet information for all /// instructions of the loop and loop safety information as arguments. /// Diagnostics is emitted via \p ORE. It returns changed status. +/// \p AllowSpeculation is whether values should be hoisted even if they are not +/// guaranteed to execute in the loop, but are safe to speculatively execute. bool hoistRegion(DomTreeNode *, AAResults *, LoopInfo *, DominatorTree *, BlockFrequencyInfo *, TargetLibraryInfo *, Loop *, MemorySSAUpdater *, ScalarEvolution *, ICFLoopSafetyInfo *, - SinkAndHoistLICMFlags &, OptimizationRemarkEmitter *, bool); + SinkAndHoistLICMFlags &, OptimizationRemarkEmitter *, bool, + bool AllowSpeculation); /// This function deletes dead loops. The caller of this function needs to /// guarantee that the loop is infact dead. @@ -204,12 +207,14 @@ void breakLoopBackedge(Loop *L, DominatorTree &DT, ScalarEvolution &SE, /// LoopInfo, DominatorTree, Loop, AliasSet information for all instructions /// of the loop and loop safety information as arguments. /// Diagnostics is emitted via \p ORE. It returns changed status. +/// \p AllowSpeculation is whether values should be hoisted even if they are not +/// guaranteed to execute in the loop, but are safe to speculatively execute. bool promoteLoopAccessesToScalars( const SmallSetVector &, SmallVectorImpl &, SmallVectorImpl &, SmallVectorImpl &, PredIteratorCache &, LoopInfo *, DominatorTree *, const TargetLibraryInfo *, Loop *, MemorySSAUpdater *, ICFLoopSafetyInfo *, - OptimizationRemarkEmitter *); + OptimizationRemarkEmitter *, bool AllowSpeculation); /// Does a BFS from a given node to all of its children inside a given loop. /// The returned vector of nodes includes the starting point. diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index 93637c890c4fa..194bff054fd72 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -291,14 +291,19 @@ PassBuilder::buildO1FunctionSimplificationPipeline(OptimizationLevel Level, LPM1.addPass(LoopSimplifyCFGPass()); // Try to remove as much code from the loop header as possible, - // to reduce amount of IR that will have to be duplicated. + // to reduce amount of IR that will have to be duplicated. However, + // do not perform speculative hoisting the first time as LICM + // will destroy metadata that may not need to be destroyed if run + // after loop rotation. // TODO: Investigate promotion cap for O1. - LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); + LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/false)); LPM1.addPass(LoopRotatePass(/* Disable header duplication */ true, isLTOPreLink(Phase))); // TODO: Investigate promotion cap for O1. - LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); + LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); LPM1.addPass(SimpleLoopUnswitchPass()); if (EnableLoopFlatten) LPM1.addPass(LoopFlattenPass()); @@ -463,15 +468,20 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, LPM1.addPass(LoopSimplifyCFGPass()); // Try to remove as much code from the loop header as possible, - // to reduce amount of IR that will have to be duplicated. + // to reduce amount of IR that will have to be duplicated. However, + // do not perform speculative hoisting the first time as LICM + // will destroy metadata that may not need to be destroyed if run + // after loop rotation. // TODO: Investigate promotion cap for O1. - LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); + LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/false)); // Disable header duplication in loop rotation at -Oz. LPM1.addPass( LoopRotatePass(Level != OptimizationLevel::Oz, isLTOPreLink(Phase))); // TODO: Investigate promotion cap for O1. - LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); + LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); LPM1.addPass( SimpleLoopUnswitchPass(/* NonTrivial */ Level == OptimizationLevel::O3 && EnableO3NonTrivialUnswitching)); @@ -567,7 +577,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(DSEPass()); FPM.addPass(createFunctionToLoopPassAdaptor( - LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap), + LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true), /*UseMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); FPM.addPass(CoroElidePass()); @@ -1007,7 +1018,8 @@ void PassBuilder::addVectorPasses(OptimizationLevel Level, ExtraPasses.addPass(CorrelatedValuePropagationPass()); ExtraPasses.addPass(InstCombinePass()); LoopPassManager LPM; - LPM.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); + LPM.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); LPM.addPass(SimpleLoopUnswitchPass(/* NonTrivial */ Level == OptimizationLevel::O3)); ExtraPasses.addPass( @@ -1073,7 +1085,8 @@ void PassBuilder::addVectorPasses(OptimizationLevel Level, FPM.addPass( RequireAnalysisPass()); FPM.addPass(createFunctionToLoopPassAdaptor( - LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap), + LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true), /*UseMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); } @@ -1612,7 +1625,8 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, FunctionPassManager MainFPM; MainFPM.addPass(createFunctionToLoopPassAdaptor( - LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap), + LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true), /*USeMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); if (RunNewGVN) diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index 74f68531b89a7..fcfc7a90cf8b0 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -451,13 +451,18 @@ void PassManagerBuilder::addFunctionSimplificationPasses( MPM.add(createLoopSimplifyCFGPass()); } // Try to remove as much code from the loop header as possible, - // to reduce amount of IR that will have to be duplicated. + // to reduce amount of IR that will have to be duplicated. However, + // do not perform speculative hoisting the first time as LICM + // will destroy metadata that may not need to be destroyed if run + // after loop rotation. // TODO: Investigate promotion cap for O1. - MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/false)); // Rotate Loop - disable header duplication at -Oz MPM.add(createLoopRotatePass(SizeLevel == 2 ? 0 : -1, PrepareForLTO)); // TODO: Investigate promotion cap for O1. - MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); if (EnableSimpleLoopUnswitch) MPM.add(createSimpleLoopUnswitchLegacyPass()); else @@ -521,7 +526,8 @@ void PassManagerBuilder::addFunctionSimplificationPasses( // TODO: Investigate if this is too expensive at O1. if (OptLevel > 1) { MPM.add(createDeadStoreEliminationPass()); // Delete dead stores - MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); } addExtensionsToPM(EP_ScalarOptimizerLate, MPM); @@ -580,7 +586,8 @@ void PassManagerBuilder::addVectorPasses(legacy::PassManagerBase &PM, PM.add(createEarlyCSEPass()); PM.add(createCorrelatedValuePropagationPass()); PM.add(createInstructionCombiningPass()); - PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); PM.add(createLoopUnswitchPass(SizeLevel || OptLevel < 3, DivergentTarget)); PM.add(createCFGSimplificationPass()); PM.add(createInstructionCombiningPass()); @@ -641,7 +648,8 @@ void PassManagerBuilder::addVectorPasses(legacy::PassManagerBase &PM, // unrolled loop is a inner loop, then the prologue will be inside the // outer loop. LICM pass can help to promote the runtime check out if the // checked value is loop invariant. - PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); } PM.add(createWarnMissedTransformationsPass()); @@ -886,7 +894,8 @@ void PassManagerBuilder::populateModulePassManager( // later might get benefit of no-alias assumption in clone loop. if (UseLoopVersioningLICM) { MPM.add(createLoopVersioningLICMPass()); // Do LoopVersioningLICM - MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + MPM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); } // We add a fresh GlobalsModRef run at this point. This is particularly @@ -1120,7 +1129,8 @@ void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) { // Run a few AA driven optimizations here and now, to cleanup the code. PM.add(createGlobalsAAWrapperPass()); // IP alias analysis. - PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap)); + PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + /*AllowSpeculation=*/true)); PM.add(NewGVN ? createNewGVNPass() : createGVNPass(DisableGVNLoadPRE)); // Remove redundancies. PM.add(createMemCpyOptPass()); // Remove dead memcpys. diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp index 7fb1a25bdf13e..6372ce19f8eec 100644 --- a/llvm/lib/Transforms/Scalar/LICM.cpp +++ b/llvm/lib/Transforms/Scalar/LICM.cpp @@ -149,13 +149,11 @@ static bool sink(Instruction &I, LoopInfo *LI, DominatorTree *DT, BlockFrequencyInfo *BFI, const Loop *CurLoop, ICFLoopSafetyInfo *SafetyInfo, MemorySSAUpdater *MSSAU, OptimizationRemarkEmitter *ORE); -static bool isSafeToExecuteUnconditionally(Instruction &Inst, - const DominatorTree *DT, - const TargetLibraryInfo *TLI, - const Loop *CurLoop, - const LoopSafetyInfo *SafetyInfo, - OptimizationRemarkEmitter *ORE, - const Instruction *CtxI = nullptr); +static bool isSafeToExecuteUnconditionally( + Instruction &Inst, const DominatorTree *DT, const TargetLibraryInfo *TLI, + const Loop *CurLoop, const LoopSafetyInfo *SafetyInfo, + OptimizationRemarkEmitter *ORE, const Instruction *CtxI, + bool AllowSpeculation); static bool pointerInvalidatedByLoop(MemoryLocation MemLoc, AliasSetTracker *CurAST, Loop *CurLoop, AAResults *AA); @@ -188,21 +186,26 @@ struct LoopInvariantCodeMotion { OptimizationRemarkEmitter *ORE, bool LoopNestMode = false); LoopInvariantCodeMotion(unsigned LicmMssaOptCap, - unsigned LicmMssaNoAccForPromotionCap) + unsigned LicmMssaNoAccForPromotionCap, + bool LicmAllowSpeculation) : LicmMssaOptCap(LicmMssaOptCap), - LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap) {} + LicmMssaNoAccForPromotionCap(LicmMssaNoAccForPromotionCap), + LicmAllowSpeculation(LicmAllowSpeculation) {} private: unsigned LicmMssaOptCap; unsigned LicmMssaNoAccForPromotionCap; + bool LicmAllowSpeculation; }; struct LegacyLICMPass : public LoopPass { static char ID; // Pass identification, replacement for typeid LegacyLICMPass( unsigned LicmMssaOptCap = SetLicmMssaOptCap, - unsigned LicmMssaNoAccForPromotionCap = SetLicmMssaNoAccForPromotionCap) - : LoopPass(ID), LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap) { + unsigned LicmMssaNoAccForPromotionCap = SetLicmMssaNoAccForPromotionCap, + bool LicmAllowSpeculation = true) + : LoopPass(ID), LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + LicmAllowSpeculation) { initializeLegacyLICMPassPass(*PassRegistry::getPassRegistry()); } @@ -265,7 +268,8 @@ PreservedAnalyses LICMPass::run(Loop &L, LoopAnalysisManager &AM, // but ORE cannot be preserved (see comment before the pass definition). OptimizationRemarkEmitter ORE(L.getHeader()->getParent()); - LoopInvariantCodeMotion LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap); + LoopInvariantCodeMotion LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + LicmAllowSpeculation); if (!LICM.runOnLoop(&L, &AR.AA, &AR.LI, &AR.DT, AR.BFI, &AR.TLI, &AR.TTI, &AR.SE, AR.MSSA, &ORE)) return PreservedAnalyses::all(); @@ -290,7 +294,8 @@ PreservedAnalyses LNICMPass::run(LoopNest &LN, LoopAnalysisManager &AM, // but ORE cannot be preserved (see comment before the pass definition). OptimizationRemarkEmitter ORE(LN.getParent()); - LoopInvariantCodeMotion LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap); + LoopInvariantCodeMotion LICM(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + LicmAllowSpeculation); Loop &OutermostLoop = LN.getOutermostLoop(); bool Changed = LICM.runOnLoop(&OutermostLoop, &AR.AA, &AR.LI, &AR.DT, AR.BFI, @@ -321,8 +326,10 @@ INITIALIZE_PASS_END(LegacyLICMPass, "licm", "Loop Invariant Code Motion", false, Pass *llvm::createLICMPass() { return new LegacyLICMPass(); } Pass *llvm::createLICMPass(unsigned LicmMssaOptCap, - unsigned LicmMssaNoAccForPromotionCap) { - return new LegacyLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap); + unsigned LicmMssaNoAccForPromotionCap, + bool LicmAllowSpeculation) { + return new LegacyLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, + LicmAllowSpeculation); } llvm::SinkAndHoistLICMFlags::SinkAndHoistLICMFlags(bool IsSink, Loop *L, @@ -418,7 +425,8 @@ bool LoopInvariantCodeMotion::runOnLoop( Flags.setIsSink(false); if (Preheader) Changed |= hoistRegion(DT->getNode(L->getHeader()), AA, LI, DT, BFI, TLI, L, - &MSSAU, SE, &SafetyInfo, Flags, ORE, LoopNestMode); + &MSSAU, SE, &SafetyInfo, Flags, ORE, LoopNestMode, + LicmAllowSpeculation); // Now that all loop invariants have been removed from the loop, promote any // memory references to scalars that we can. @@ -460,8 +468,8 @@ bool LoopInvariantCodeMotion::runOnLoop( for (const SmallSetVector &PointerMustAliases : collectPromotionCandidates(MSSA, AA, L)) { LocalPromoted |= promoteLoopAccessesToScalars( - PointerMustAliases, ExitBlocks, InsertPts, MSSAInsertPts, PIC, - LI, DT, TLI, L, &MSSAU, &SafetyInfo, ORE); + PointerMustAliases, ExitBlocks, InsertPts, MSSAInsertPts, PIC, LI, + DT, TLI, L, &MSSAU, &SafetyInfo, ORE, LicmAllowSpeculation); } Promoted |= LocalPromoted; } while (LocalPromoted); @@ -825,7 +833,8 @@ bool llvm::hoistRegion(DomTreeNode *N, AAResults *AA, LoopInfo *LI, MemorySSAUpdater *MSSAU, ScalarEvolution *SE, ICFLoopSafetyInfo *SafetyInfo, SinkAndHoistLICMFlags &Flags, - OptimizationRemarkEmitter *ORE, bool LoopNestMode) { + OptimizationRemarkEmitter *ORE, bool LoopNestMode, + bool AllowSpeculation) { // Verify inputs. assert(N != nullptr && AA != nullptr && LI != nullptr && DT != nullptr && CurLoop != nullptr && MSSAU != nullptr && SafetyInfo != nullptr && @@ -877,7 +886,7 @@ bool llvm::hoistRegion(DomTreeNode *N, AAResults *AA, LoopInfo *LI, true, &Flags, ORE) && isSafeToExecuteUnconditionally( I, DT, TLI, CurLoop, SafetyInfo, ORE, - CurLoop->getLoopPreheader()->getTerminator())) { + CurLoop->getLoopPreheader()->getTerminator(), AllowSpeculation)) { hoist(I, DT, CurLoop, CFH.getOrCreateHoistedBlock(BB), SafetyInfo, MSSAU, SE, ORE); HoistedInstructions.push_back(&I); @@ -1774,14 +1783,12 @@ static void hoist(Instruction &I, const DominatorTree *DT, const Loop *CurLoop, /// Only sink or hoist an instruction if it is not a trapping instruction, /// or if the instruction is known not to trap when moved to the preheader. /// or if it is a trapping instruction and is guaranteed to execute. -static bool isSafeToExecuteUnconditionally(Instruction &Inst, - const DominatorTree *DT, - const TargetLibraryInfo *TLI, - const Loop *CurLoop, - const LoopSafetyInfo *SafetyInfo, - OptimizationRemarkEmitter *ORE, - const Instruction *CtxI) { - if (isSafeToSpeculativelyExecute(&Inst, CtxI, DT, TLI)) +static bool isSafeToExecuteUnconditionally( + Instruction &Inst, const DominatorTree *DT, const TargetLibraryInfo *TLI, + const Loop *CurLoop, const LoopSafetyInfo *SafetyInfo, + OptimizationRemarkEmitter *ORE, const Instruction *CtxI, + bool AllowSpeculation) { + if (AllowSpeculation && isSafeToSpeculativelyExecute(&Inst, CtxI, DT, TLI)) return true; bool GuaranteedToExecute = @@ -1949,7 +1956,7 @@ bool llvm::promoteLoopAccessesToScalars( SmallVectorImpl &MSSAInsertPts, PredIteratorCache &PIC, LoopInfo *LI, DominatorTree *DT, const TargetLibraryInfo *TLI, Loop *CurLoop, MemorySSAUpdater *MSSAU, ICFLoopSafetyInfo *SafetyInfo, - OptimizationRemarkEmitter *ORE) { + OptimizationRemarkEmitter *ORE, bool AllowSpeculation) { // Verify inputs. assert(LI != nullptr && DT != nullptr && CurLoop != nullptr && SafetyInfo != nullptr && @@ -2054,9 +2061,9 @@ bool llvm::promoteLoopAccessesToScalars( // to execute does as well. Thus we can increase our guaranteed // alignment as well. if (!DereferenceableInPH || (InstAlignment > Alignment)) - if (isSafeToExecuteUnconditionally(*Load, DT, TLI, CurLoop, - SafetyInfo, ORE, - Preheader->getTerminator())) { + if (isSafeToExecuteUnconditionally( + *Load, DT, TLI, CurLoop, SafetyInfo, ORE, + Preheader->getTerminator(), AllowSpeculation)) { DereferenceableInPH = true; Alignment = std::max(Alignment, InstAlignment); } diff --git a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll index 4f0c07343bda8..428eccc2761bf 100644 --- a/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll +++ b/llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll @@ -6,21 +6,21 @@ define void @runtime_unroll_generic(i32 %arg_0, i32* %arg_1, i16* %arg_2, i16* %arg_3) { ; CHECK-A55-LABEL: @runtime_unroll_generic( ; CHECK-A55-NEXT: entry: +; CHECK-A55-NEXT: [[CMP52_NOT:%.*]] = icmp eq i32 [[ARG_0:%.*]], 0 +; CHECK-A55-NEXT: br i1 [[CMP52_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY6_LR_PH:%.*]] +; CHECK-A55: for.body6.lr.ph: ; CHECK-A55-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, i16* [[ARG_2:%.*]], i64 undef ; CHECK-A55-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i16, i16* [[ARG_3:%.*]], i64 undef ; CHECK-A55-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARG_1:%.*]], i64 undef -; CHECK-A55-NEXT: [[CMP52_NOT:%.*]] = icmp eq i32 [[ARG_0:%.*]], 0 -; CHECK-A55-NEXT: br i1 [[CMP52_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY6_PREHEADER:%.*]] -; CHECK-A55: for.body6.preheader: ; CHECK-A55-NEXT: [[TMP0:%.*]] = add i32 [[ARG_0]], -1 ; CHECK-A55-NEXT: [[XTRAITER:%.*]] = and i32 [[ARG_0]], 3 ; CHECK-A55-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 3 -; CHECK-A55-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY6_PREHEADER_NEW:%.*]] -; CHECK-A55: for.body6.preheader.new: +; CHECK-A55-NEXT: br i1 [[TMP1]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY6_LR_PH_NEW:%.*]] +; CHECK-A55: for.body6.lr.ph.new: ; CHECK-A55-NEXT: [[UNROLL_ITER:%.*]] = and i32 [[ARG_0]], -4 ; CHECK-A55-NEXT: br label [[FOR_BODY6:%.*]] ; CHECK-A55: for.body6: -; CHECK-A55-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_BODY6_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_BODY6]] ] +; CHECK-A55-NEXT: [[NITER:%.*]] = phi i32 [ 0, [[FOR_BODY6_LR_PH_NEW]] ], [ [[NITER_NEXT_3:%.*]], [[FOR_BODY6]] ] ; CHECK-A55-NEXT: [[TMP2:%.*]] = load i16, i16* [[ARRAYIDX10]], align 2 ; CHECK-A55-NEXT: [[CONV:%.*]] = sext i16 [[TMP2]] to i32 ; CHECK-A55-NEXT: [[TMP3:%.*]] = load i16, i16* [[ARRAYIDX14]], align 2 @@ -93,13 +93,15 @@ define void @runtime_unroll_generic(i32 %arg_0, i32* %arg_1, i16* %arg_2, i16* % ; ; CHECK-GENERIC-LABEL: @runtime_unroll_generic( ; CHECK-GENERIC-NEXT: entry: +; CHECK-GENERIC-NEXT: [[CMP52_NOT:%.*]] = icmp eq i32 [[ARG_0:%.*]], 0 +; CHECK-GENERIC-NEXT: br i1 [[CMP52_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY6_LR_PH:%.*]] +; CHECK-GENERIC: for.body6.lr.ph: ; CHECK-GENERIC-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, i16* [[ARG_2:%.*]], i64 undef ; CHECK-GENERIC-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i16, i16* [[ARG_3:%.*]], i64 undef ; CHECK-GENERIC-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i32, i32* [[ARG_1:%.*]], i64 undef -; CHECK-GENERIC-NEXT: [[CMP52_NOT:%.*]] = icmp eq i32 [[ARG_0:%.*]], 0 -; CHECK-GENERIC-NEXT: br i1 [[CMP52_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY6:%.*]] +; CHECK-GENERIC-NEXT: br label [[FOR_BODY6:%.*]] ; CHECK-GENERIC: for.body6: -; CHECK-GENERIC-NEXT: [[K_03:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY6]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-GENERIC-NEXT: [[K_03:%.*]] = phi i32 [ 0, [[FOR_BODY6_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY6]] ] ; CHECK-GENERIC-NEXT: [[TMP0:%.*]] = load i16, i16* [[ARRAYIDX10]], align 2 ; CHECK-GENERIC-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 ; CHECK-GENERIC-NEXT: [[TMP1:%.*]] = load i16, i16* [[ARRAYIDX14]], align 2 diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll index 33cd004d43482..eee888d2e18c0 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll @@ -88,10 +88,10 @@ entry: define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8 dereferenceable(1800) %A, [225 x double]* nonnull align 8 dereferenceable(1800) %B) { ; CHECK-LABEL: @matrix_extract_insert_loop( ; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP212_NOT:%.*]] = icmp eq i32 [[I:%.*]], 0 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast [225 x double]* [[A:%.*]] to <225 x double>* -; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[I:%.*]] to i64 +; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[I]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast [225 x double]* [[B:%.*]] to <225 x double>* -; CHECK-NEXT: [[CMP212_NOT:%.*]] = icmp eq i32 [[I]], 0 ; CHECK-NEXT: br i1 [[CMP212_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US:%.*]] ; CHECK: for.cond1.preheader.us: ; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[I]], 225 @@ -145,8 +145,8 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8 ; CHECK-NEXT: br label [[FOR_BODY4_US_2:%.*]] ; CHECK: for.body4.us.2: ; CHECK-NEXT: [[K_013_US_2:%.*]] = phi i32 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_1]] ], [ [[INC_US_2:%.*]], [[FOR_BODY4_US_2]] ] -; CHECK-NEXT: [[NARROW16:%.*]] = add nuw nsw i32 [[K_013_US_2]], 30 -; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[NARROW16]] to i64 +; CHECK-NEXT: [[NARROW17:%.*]] = add nuw nsw i32 [[K_013_US_2]], 30 +; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[NARROW17]] to i64 ; CHECK-NEXT: [[TMP18:%.*]] = icmp ult i32 [[K_013_US_2]], 195 ; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP18]]) ; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP17]] @@ -168,8 +168,8 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8 ; CHECK-NEXT: br label [[FOR_BODY4_US_3:%.*]] ; CHECK: for.body4.us.3: ; CHECK-NEXT: [[K_013_US_3:%.*]] = phi i32 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_2]] ], [ [[INC_US_3:%.*]], [[FOR_BODY4_US_3]] ] -; CHECK-NEXT: [[NARROW17:%.*]] = add nuw nsw i32 [[K_013_US_3]], 45 -; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[NARROW17]] to i64 +; CHECK-NEXT: [[NARROW18:%.*]] = add nuw nsw i32 [[K_013_US_3]], 45 +; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[NARROW18]] to i64 ; CHECK-NEXT: [[TMP25:%.*]] = icmp ult i32 [[K_013_US_3]], 180 ; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP25]]) ; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP24]] diff --git a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll index 20c3cb029d2ae..9b602750974af 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll @@ -44,15 +44,15 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; OLDPM_O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy ; OLDPM_O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; OLDPM_O2-NEXT: entry: -; OLDPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 ; OLDPM_O2-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; OLDPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; OLDPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; OLDPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 ; OLDPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 ; OLDPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] ; OLDPM_O2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] ; OLDPM_O2: for.cond1.preheader: ; OLDPM_O2-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] -; OLDPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; OLDPM_O2-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]] ; OLDPM_O2: for.body4.preheader: ; OLDPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER11:%.*]], label [[VECTOR_BODY:%.*]] @@ -97,8 +97,9 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; OLDPM_O3-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy ; OLDPM_O3-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; OLDPM_O3-NEXT: entry: -; OLDPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 ; OLDPM_O3-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; OLDPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; OLDPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; OLDPM_O3-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] ; OLDPM_O3: for.cond1.preheader.us.preheader: ; OLDPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 @@ -107,7 +108,6 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; OLDPM_O3-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] ; OLDPM_O3: for.cond1.preheader.us: ; OLDPM_O3-NEXT: [[I_08_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] -; OLDPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; OLDPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_US_PREHEADER:%.*]], label [[VECTOR_BODY:%.*]] ; OLDPM_O3: vector.body: ; OLDPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ] @@ -150,12 +150,12 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; NEWPM_O1-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy ; NEWPM_O1-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; NEWPM_O1-NEXT: entry: -; NEWPM_O1-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 ; NEWPM_O1-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O1-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O1-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] ; NEWPM_O1: for.cond1.preheader: ; NEWPM_O1-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] -; NEWPM_O1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O1-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4:%.*]] ; NEWPM_O1: for.cond.cleanup: ; NEWPM_O1-NEXT: ret void @@ -176,15 +176,15 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; NEWPM_O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy ; NEWPM_O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; NEWPM_O2-NEXT: entry: -; NEWPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 ; NEWPM_O2-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 ; NEWPM_O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8 ; NEWPM_O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]] ; NEWPM_O2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] ; NEWPM_O2: for.cond1.preheader: ; NEWPM_O2-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ] -; NEWPM_O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O2-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]] ; NEWPM_O2: for.body4.preheader: ; NEWPM_O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER11:%.*]], label [[VECTOR_BODY:%.*]] @@ -229,8 +229,9 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; NEWPM_O3-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy ; NEWPM_O3-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; NEWPM_O3-NEXT: entry: -; NEWPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 ; NEWPM_O3-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0 +; NEWPM_O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0 +; NEWPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O3-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] ; NEWPM_O3: for.cond1.preheader.us.preheader: ; NEWPM_O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8 @@ -239,7 +240,6 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* nound ; NEWPM_O3-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] ; NEWPM_O3: for.cond1.preheader.us: ; NEWPM_O3-NEXT: [[I_08_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] -; NEWPM_O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8 ; NEWPM_O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_US_PREHEADER:%.*]], label [[VECTOR_BODY:%.*]] ; NEWPM_O3: vector.body: ; NEWPM_O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ] diff --git a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll index 3ac9104708405..41dbdcb0c5bd3 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll @@ -14,13 +14,15 @@ target triple = "x86_64-unknown-linux-gnu" define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) { ; OLDPM_O1-LABEL: @licm( ; OLDPM_O1-NEXT: entry: -; OLDPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 ; OLDPM_O1-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; OLDPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]] +; OLDPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]] +; OLDPM_O1: for.body.lr.ph: +; OLDPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O1-NEXT: br label [[FOR_BODY:%.*]] ; OLDPM_O1: for.body: -; OLDPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ] +; OLDPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; OLDPM_O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; OLDPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8:![0-9]+]] ; OLDPM_O1-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 ; OLDPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] ; OLDPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] @@ -29,12 +31,12 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; ; OLDPM_O23-LABEL: @licm( ; OLDPM_O23-NEXT: entry: -; OLDPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 ; OLDPM_O23-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; OLDPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; OLDPM_O23: for.body.preheader: +; OLDPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]] +; OLDPM_O23: for.body.lr.ph: +; OLDPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]] ; OLDPM_O23-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; OLDPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; OLDPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_PH:%.*]] ; OLDPM_O23: vector.ph: ; OLDPM_O23-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 ; OLDPM_O23-NEXT: br label [[VECTOR_BODY:%.*]] @@ -42,38 +44,40 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; OLDPM_O23-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; OLDPM_O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] ; OLDPM_O23-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA8:![0-9]+]] ; OLDPM_O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 ; OLDPM_O23-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; OLDPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA8]] ; OLDPM_O23-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; OLDPM_O23-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; OLDPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; OLDPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; OLDPM_O23: middle.block: ; OLDPM_O23-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; OLDPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; OLDPM_O23: for.body.preheader3: -; OLDPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; OLDPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER]] +; OLDPM_O23: for.body.preheader: +; OLDPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] ; OLDPM_O23-NEXT: br label [[FOR_BODY:%.*]] ; OLDPM_O23: for.body: -; OLDPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; OLDPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER]] ] ; OLDPM_O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; OLDPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; OLDPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8]] ; OLDPM_O23-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 ; OLDPM_O23-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; OLDPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; OLDPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] ; OLDPM_O23: for.cond.cleanup: ; OLDPM_O23-NEXT: ret void ; ; NEWPM_O1-LABEL: @licm( ; NEWPM_O1-NEXT: entry: -; NEWPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 ; NEWPM_O1-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; NEWPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]] +; NEWPM_O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]] +; NEWPM_O1: for.body.lr.ph: +; NEWPM_O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O1-NEXT: br label [[FOR_BODY:%.*]] ; NEWPM_O1: for.body: -; NEWPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ] +; NEWPM_O1-NEXT: [[K_02:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ] ; NEWPM_O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; NEWPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8:![0-9]+]] ; NEWPM_O1-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 ; NEWPM_O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] ; NEWPM_O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] @@ -82,12 +86,12 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; ; NEWPM_O23-LABEL: @licm( ; NEWPM_O23-NEXT: entry: -; NEWPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8 ; NEWPM_O23-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0 -; NEWPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] -; NEWPM_O23: for.body.preheader: +; NEWPM_O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]] +; NEWPM_O23: for.body.lr.ph: +; NEWPM_O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]] ; NEWPM_O23-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4 -; NEWPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER3:%.*]], label [[VECTOR_PH:%.*]] +; NEWPM_O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_PH:%.*]] ; NEWPM_O23: vector.ph: ; NEWPM_O23-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEM]], -4 ; NEWPM_O23-NEXT: br label [[VECTOR_BODY:%.*]] @@ -95,26 +99,26 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) ; NEWPM_O23-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; NEWPM_O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]] ; NEWPM_O23-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>* -; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA3:![0-9]+]] +; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA8:![0-9]+]] ; NEWPM_O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2 ; NEWPM_O23-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>* -; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA3]] +; NEWPM_O23-NEXT: store <2 x double> , <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA8]] ; NEWPM_O23-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; NEWPM_O23-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; NEWPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; NEWPM_O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; NEWPM_O23: middle.block: ; NEWPM_O23-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEM]] -; NEWPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER3]] -; NEWPM_O23: for.body.preheader3: -; NEWPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] +; NEWPM_O23-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER]] +; NEWPM_O23: for.body.preheader: +; NEWPM_O23-NEXT: [[K_02_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] ; NEWPM_O23-NEXT: br label [[FOR_BODY:%.*]] ; NEWPM_O23: for.body: -; NEWPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER3]] ] +; NEWPM_O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER]] ] ; NEWPM_O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]] -; NEWPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA3]] +; NEWPM_O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8]] ; NEWPM_O23-NEXT: [[INC]] = add nuw i64 [[K_02]], 1 ; NEWPM_O23-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]] -; NEWPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; NEWPM_O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] ; NEWPM_O23: for.cond.cleanup: ; NEWPM_O23-NEXT: ret void ; diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll index f75c7d6ea1316..c37bd29041575 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll @@ -32,10 +32,10 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FV ; OLDPM_O23-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 ; OLDPM_O23-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] ; OLDPM_O23: for.body7.lr.ph.i: -; OLDPM_O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; OLDPM_O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 ; OLDPM_O23-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I6_I]], align 8, !tbaa [[TBAA8:![0-9]+]] ; OLDPM_O23-NEXT: [[ARRAYIDX_I7_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; OLDPM_O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; OLDPM_O23-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I4_I]], align 8, !tbaa [[TBAA0]] ; OLDPM_O23-NEXT: [[BASE_I2_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 ; OLDPM_O23-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I2_I]], align 8, !tbaa [[TBAA8]] @@ -64,10 +64,10 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FV ; NEWPM_O1-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 ; NEWPM_O1-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] ; NEWPM_O1: for.body7.lr.ph.i: -; NEWPM_O1-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; NEWPM_O1-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 ; NEWPM_O1-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] ; NEWPM_O1-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O1-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; NEWPM_O1-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] ; NEWPM_O1-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 ; NEWPM_O1-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] @@ -95,10 +95,10 @@ define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FV ; NEWPM_O23-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0 ; NEWPM_O23-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]] ; NEWPM_O23: for.body7.lr.ph.i: -; NEWPM_O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; NEWPM_O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0 ; NEWPM_O23-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]] ; NEWPM_O23-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef +; NEWPM_O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0 ; NEWPM_O23-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]] ; NEWPM_O23-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0 ; NEWPM_O23-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]] @@ -130,16 +130,18 @@ define linkonce_odr dso_local void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPa ; OLDPM_O1-SAME: (%class.FloatVecPair* [[THIS:%.*]]) local_unnamed_addr comdat align 2 { ; OLDPM_O1-NEXT: entry: ; OLDPM_O1-NEXT: [[VSRC23:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[THIS]], i64 0, i32 1 -; OLDPM_O1-NEXT: [[VSRCDST:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[THIS]], i64 0, i32 0 ; OLDPM_O1-NEXT: [[CALL2:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* nonnull [[VSRC23]]) ; OLDPM_O1-NEXT: [[SIZE43:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[CALL2]], i64 0, i32 1 ; OLDPM_O1-NEXT: [[TMP0:%.*]] = load i32, i32* [[SIZE43]], align 8, !tbaa [[TBAA0:![0-9]+]] ; OLDPM_O1-NEXT: [[CMP54_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 -; OLDPM_O1-NEXT: br i1 [[CMP54_NOT]], label [[FOR_COND_CLEANUP6:%.*]], label [[FOR_BODY7:%.*]] +; OLDPM_O1-NEXT: br i1 [[CMP54_NOT]], label [[FOR_COND_CLEANUP6:%.*]], label [[FOR_BODY7_LR_PH:%.*]] +; OLDPM_O1: for.body7.lr.ph: +; OLDPM_O1-NEXT: [[VSRCDST:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[THIS]], i64 0, i32 0 +; OLDPM_O1-NEXT: br label [[FOR_BODY7:%.*]] ; OLDPM_O1: for.cond.cleanup6: ; OLDPM_O1-NEXT: ret void ; OLDPM_O1: for.body7: -; OLDPM_O1-NEXT: [[J_05:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY7]] ], [ 0, [[ENTRY:%.*]] ] +; OLDPM_O1-NEXT: [[J_05:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY7]] ] ; OLDPM_O1-NEXT: [[CALL9:%.*]] = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* nonnull [[VSRC23]]) ; OLDPM_O1-NEXT: [[CALL10:%.*]] = call float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* [[CALL9]]) ; OLDPM_O1-NEXT: [[TMP1:%.*]] = load float, float* [[CALL10]], align 4, !tbaa [[TBAA6:![0-9]+]] From 6a713120502abc0a42b8d518edea345b60e829f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 15 Feb 2022 21:21:12 +0100 Subject: [PATCH 232/316] [llvm] [bindings/OCaml] Remove unused dep on ounit2 Remove the dependency on ounit2 and the relevant lit code. It seems that ounit2 is not used at all and all OCaml binding tests pass without it installed. Thanks for Shiwei Weng and Josh Berdine for bringing this to my attention. Differential Revision: https://reviews.llvm.org/D119884 (cherry picked from commit 2c5c243bb5152de35c41f5880271451fce6165d0) --- llvm/bindings/ocaml/README.txt | 1 - llvm/cmake/config-ix.cmake | 6 ------ llvm/test/Bindings/OCaml/lit.local.cfg | 3 --- llvm/test/CMakeLists.txt | 1 - llvm/test/lit.site.cfg.py.in | 1 - llvm/utils/gn/secondary/llvm/test/BUILD.gn | 1 - 6 files changed, 13 deletions(-) diff --git a/llvm/bindings/ocaml/README.txt b/llvm/bindings/ocaml/README.txt index a6a595e75bb5f..08b5514e0a664 100644 --- a/llvm/bindings/ocaml/README.txt +++ b/llvm/bindings/ocaml/README.txt @@ -6,7 +6,6 @@ Prerequisites * OCaml 4.00.0+. * ctypes 0.4+. -* oUnit 2+ (only required for tests). * CMake (to build LLVM). Building the bindings diff --git a/llvm/cmake/config-ix.cmake b/llvm/cmake/config-ix.cmake index c70b8b3787a0a..18d78879c968f 100644 --- a/llvm/cmake/config-ix.cmake +++ b/llvm/cmake/config-ix.cmake @@ -650,12 +650,6 @@ else() find_ocamlfind_package(ctypes VERSION 0.4 OPTIONAL) if( HAVE_OCAML_CTYPES ) message(STATUS "OCaml bindings enabled.") - find_ocamlfind_package(ounit2 OPTIONAL) - if ( HAVE_OCAML_OUNIT2 ) - set(HAVE_OCAML_OUNIT TRUE) - else() - find_ocamlfind_package(oUnit VERSION 2 OPTIONAL) - endif() set(LLVM_BINDINGS "${LLVM_BINDINGS} ocaml") set(LLVM_OCAML_INSTALL_PATH "${OCAML_STDLIB_PATH}" CACHE STRING diff --git a/llvm/test/Bindings/OCaml/lit.local.cfg b/llvm/test/Bindings/OCaml/lit.local.cfg index fd9e1c50e990c..364b97c632e83 100644 --- a/llvm/test/Bindings/OCaml/lit.local.cfg +++ b/llvm/test/Bindings/OCaml/lit.local.cfg @@ -2,6 +2,3 @@ config.suffixes = ['.ml'] if not 'ocaml' in config.root.llvm_bindings: config.unsupported = True - -if not config.root.have_ocaml_ounit: - config.unsupported = True diff --git a/llvm/test/CMakeLists.txt b/llvm/test/CMakeLists.txt index 2d18625e86133..495dccc392046 100644 --- a/llvm/test/CMakeLists.txt +++ b/llvm/test/CMakeLists.txt @@ -2,7 +2,6 @@ llvm_canonicalize_cmake_booleans( BUILD_SHARED_LIBS LLVM_HAVE_LIBXAR HAVE_OCAMLOPT - HAVE_OCAML_OUNIT LLVM_ENABLE_DIA_SDK LLVM_ENABLE_FFI LLVM_ENABLE_THREADS diff --git a/llvm/test/lit.site.cfg.py.in b/llvm/test/lit.site.cfg.py.in index e92cb0caa4e1c..5836c8e62b0d4 100644 --- a/llvm/test/lit.site.cfg.py.in +++ b/llvm/test/lit.site.cfg.py.in @@ -20,7 +20,6 @@ config.ld64_executable = "@LD64_EXECUTABLE@" config.osx_sysroot = path(r"@CMAKE_OSX_SYSROOT@") config.ocamlfind_executable = "@OCAMLFIND@" config.have_ocamlopt = @HAVE_OCAMLOPT@ -config.have_ocaml_ounit = @HAVE_OCAML_OUNIT@ config.ocaml_flags = "@OCAMLFLAGS@" config.include_go_tests = @LLVM_INCLUDE_GO_TESTS@ config.go_executable = "@GO_EXECUTABLE@" diff --git a/llvm/utils/gn/secondary/llvm/test/BUILD.gn b/llvm/utils/gn/secondary/llvm/test/BUILD.gn index 042972aff276f..41abe22ef5710 100644 --- a/llvm/utils/gn/secondary/llvm/test/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/test/BUILD.gn @@ -84,7 +84,6 @@ write_lit_config("lit_site_cfg") { "LLVM_INCLUDE_GO_TESTS=0", "HAVE_OCAMLOPT=0", - "HAVE_OCAML_OUNIT=0", "OCAMLFIND=OCAMLFIND-NOTFOUND", "OCAMLFLAGS=", "LLVM_BUILD_EXAMPLES=0", From 8b51e5ee0a2e6a38886e7ededd3267443cb99f1e Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Mon, 7 Mar 2022 10:17:09 -0800 Subject: [PATCH 233/316] [NewPM][Inliner] Make inlined calls to functions in same SCC as callee exponentially expensive Introduce a new attribute "function-inline-cost-multiplier" which multiplies the inline cost of a call site (or all calls to a callee) by the multiplier. When processing the list of calls created by inlining, check each call to see if the new call's callee is in the same SCC as the original callee. If so, set the "function-inline-cost-multiplier" attribute of the new call site to double the original call site's attribute value. This does not happen when the original call site is intra-SCC. This is an alternative to D120584, which marks the call sites as noinline. Hopefully fixes PR45253. Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D121084 (cherry picked from commit 53e5e586709a329370ea268a8e8191b16fd641b7) --- llvm/include/llvm/Analysis/InlineCost.h | 5 ++ llvm/lib/Analysis/InlineCost.cpp | 13 +++- llvm/lib/Transforms/IPO/Inliner.cpp | 45 ++++++++++- .../Inline/inline-cost-attributes.ll | 8 +- llvm/test/Transforms/Inline/mut-rec-scc-2.ll | 19 +++++ llvm/test/Transforms/Inline/mut-rec-scc.ll | 75 +++++++++++++++++++ 6 files changed, 157 insertions(+), 8 deletions(-) create mode 100644 llvm/test/Transforms/Inline/mut-rec-scc-2.ll create mode 100644 llvm/test/Transforms/Inline/mut-rec-scc.ll diff --git a/llvm/include/llvm/Analysis/InlineCost.h b/llvm/include/llvm/Analysis/InlineCost.h index f86ee5a148749..d3fa3b879125f 100644 --- a/llvm/include/llvm/Analysis/InlineCost.h +++ b/llvm/include/llvm/Analysis/InlineCost.h @@ -52,6 +52,9 @@ const unsigned TotalAllocaSizeRecursiveCaller = 1024; /// Do not inline dynamic allocas that have been constant propagated to be /// static allocas above this amount in bytes. const uint64_t MaxSimplifiedDynamicAllocaToInline = 65536; + +const char FunctionInlineCostMultiplierAttributeName[] = + "function-inline-cost-multiplier"; } // namespace InlineConstants // The cost-benefit pair computed by cost-benefit analysis. @@ -217,6 +220,8 @@ struct InlineParams { Optional AllowRecursiveCall = false; }; +Optional getStringFnAttrAsInt(CallBase &CB, StringRef AttrKind); + /// Generate the parameters to tune the inline cost analysis based only on the /// commandline options. InlineParams getInlineParams(); diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index d5411d916c777..cd5314e7a17a1 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -133,8 +133,6 @@ static cl::opt DisableGEPConstOperand( cl::desc("Disables evaluation of GetElementPtr with constant operands")); namespace { -class InlineCostCallAnalyzer; - /// This function behaves more like CallBase::hasFnAttr: when it looks for the /// requested attribute, it check both the call instruction and the called /// function (if it's available and operand bundles don't prohibit that). @@ -151,7 +149,9 @@ Attribute getFnAttr(CallBase &CB, StringRef AttrKind) { return {}; } +} // namespace +namespace llvm { Optional getStringFnAttrAsInt(CallBase &CB, StringRef AttrKind) { Attribute Attr = getFnAttr(CB, AttrKind); int AttrValue; @@ -159,6 +159,10 @@ Optional getStringFnAttrAsInt(CallBase &CB, StringRef AttrKind) { return None; return AttrValue; } +} // namespace llvm + +namespace { +class InlineCostCallAnalyzer; // This struct is used to store information about inline cost of a // particular instruction @@ -904,6 +908,11 @@ class InlineCostCallAnalyzer final : public CallAnalyzer { getStringFnAttrAsInt(CandidateCall, "function-inline-cost")) Cost = *AttrCost; + if (Optional AttrCostMult = getStringFnAttrAsInt( + CandidateCall, + InlineConstants::FunctionInlineCostMultiplierAttributeName)) + Cost *= *AttrCostMult; + if (Optional AttrThreshold = getStringFnAttrAsInt(CandidateCall, "function-inline-threshold")) Threshold = *AttrThreshold; diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cpp index 49babc24cb82c..10abea7ebd321 100644 --- a/llvm/lib/Transforms/IPO/Inliner.cpp +++ b/llvm/lib/Transforms/IPO/Inliner.cpp @@ -22,6 +22,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Analysis/AssumptionCache.h" #include "llvm/Analysis/BasicAliasAnalysis.h" @@ -92,6 +93,18 @@ static cl::opt DisableInlinedAllocaMerging("disable-inlined-alloca-merging", cl::init(false), cl::Hidden); +static cl::opt IntraSCCCostMultiplier( + "intra-scc-cost-multiplier", cl::init(2), cl::Hidden, + cl::desc( + "Cost multiplier to multiply onto inlined call sites where the " + "new call was previously an intra-SCC call (not relevant when the " + "original call was already intra-SCC). This can accumulate over " + "multiple inlinings (e.g. if a call site already had a cost " + "multiplier and one of its inlined calls was also subject to " + "this, the inlined call would have the original multiplier " + "multiplied by intra-scc-cost-multiplier). This is to prevent tons of " + "inlining through a child SCC which can cause terrible compile times")); + /// A flag for test, so we can print the content of the advisor when running it /// as part of the default (e.g. -O3) pipeline. static cl::opt KeepAdvisorForPrinting("keep-inline-advisor-for-printing", @@ -876,8 +889,8 @@ PreservedAnalyses InlinerPass::run(LazyCallGraph::SCC &InitialC, // trigger infinite inlining, much like is prevented within the inliner // itself by the InlineHistory above, but spread across CGSCC iterations // and thus hidden from the full inline history. - if (CG.lookupSCC(*CG.lookup(Callee)) == C && - UR.InlinedInternalEdges.count({&N, C})) { + LazyCallGraph::SCC *CalleeSCC = CG.lookupSCC(*CG.lookup(Callee)); + if (CalleeSCC == C && UR.InlinedInternalEdges.count({&N, C})) { LLVM_DEBUG(dbgs() << "Skipping inlining internal SCC edge from a node " "previously split out of this SCC by inlining: " << F.getName() << " -> " << Callee.getName() << "\n"); @@ -897,6 +910,11 @@ PreservedAnalyses InlinerPass::run(LazyCallGraph::SCC &InitialC, continue; } + int CBCostMult = + getStringFnAttrAsInt( + *CB, InlineConstants::FunctionInlineCostMultiplierAttributeName) + .getValueOr(1); + // Setup the data structure used to plumb customization into the // `InlineFunction` routine. InlineFunctionInfo IFI( @@ -935,9 +953,28 @@ PreservedAnalyses InlinerPass::run(LazyCallGraph::SCC &InitialC, if (tryPromoteCall(*ICB)) NewCallee = ICB->getCalledFunction(); } - if (NewCallee) - if (!NewCallee->isDeclaration()) + if (NewCallee) { + if (!NewCallee->isDeclaration()) { Calls->push({ICB, NewHistoryID}); + // Continually inlining through an SCC can result in huge compile + // times and bloated code since we arbitrarily stop at some point + // when the inliner decides it's not profitable to inline anymore. + // We attempt to mitigate this by making these calls exponentially + // more expensive. + // This doesn't apply to calls in the same SCC since if we do + // inline through the SCC the function will end up being + // self-recursive which the inliner bails out on, and inlining + // within an SCC is necessary for performance. + if (CalleeSCC != C && + CalleeSCC == CG.lookupSCC(CG.get(*NewCallee))) { + Attribute NewCBCostMult = Attribute::get( + M.getContext(), + InlineConstants::FunctionInlineCostMultiplierAttributeName, + itostr(CBCostMult * IntraSCCCostMultiplier)); + ICB->addFnAttr(NewCBCostMult); + } + } + } } } diff --git a/llvm/test/Transforms/Inline/inline-cost-attributes.ll b/llvm/test/Transforms/Inline/inline-cost-attributes.ll index b412a5fac0c44..71264ab6c389f 100644 --- a/llvm/test/Transforms/Inline/inline-cost-attributes.ll +++ b/llvm/test/Transforms/Inline/inline-cost-attributes.ll @@ -11,8 +11,9 @@ entry: define void @fn2() "function-inline-threshold"="41" { ; INLINER-LABEL: Inlining calls in: fn2 -; INLINER-NEXT: Function size: 6 +; INLINER-NEXT: Function size: 7 ; INLINER-NEXT: NOT Inlining (cost=321, threshold=123), Call: call void @fn1() +; INLINER-NEXT: NOT Inlining (cost=963, threshold=123), Call: call void @fn1() ; INLINER-NEXT: NOT Inlining (cost=321, threshold=321), Call: call void @fn1() ; INLINER-NEXT: NOT Inlining (cost=197, threshold=123), Call: call void @fn1() ; INLINER-NEXT: Inlining (cost=197, threshold=321), Call: call void @fn1() @@ -23,6 +24,8 @@ define void @fn2() "function-inline-threshold"="41" { ; COST-NEXT: call void @extern() ; COST-NEXT: cost delta = 132, threshold delta = 193 ; COST-NEXT: call void @fn1() +; COST-NEXT: cost delta = 132, threshold delta = 193 +; COST-NEXT: call void @fn1() ; COST-NEXT: cost delta = 0 ; COST-NEXT: call void @fn1() ; COST-NEXT: cost delta = 271, threshold delta = 17 @@ -33,6 +36,7 @@ define void @fn2() "function-inline-threshold"="41" { entry: call void @extern() call void @fn1() "call-inline-cost"="132" "call-threshold-bonus"="193" + call void @fn1() "call-inline-cost"="132" "call-threshold-bonus"="193" "function-inline-cost-multiplier"="3" call void @fn1() "call-inline-cost"="0" "function-inline-threshold"="321" call void @fn1() "call-threshold-bonus"="17" "function-inline-cost"="197" call void @fn1() "call-inline-cost"="473" "function-inline-cost"="197" "function-inline-threshold"="321" @@ -44,7 +48,7 @@ define void @fn3() { ; INLINER-NEXT: Function size: 3 ; INLINER-NEXT: Inlining (cost=386, threshold=849), Call: call void @fn1() ; INLINER-NEXT: Size after inlining: 2 -; INLINER-NEXT: NOT Inlining (cost=403, threshold=41), Call: call void @fn2() +; INLINER-NEXT: NOT Inlining (cost=535, threshold=41), Call: call void @fn2() entry: call void @fn1() "function-inline-cost"="386" "function-inline-threshold"="849" diff --git a/llvm/test/Transforms/Inline/mut-rec-scc-2.ll b/llvm/test/Transforms/Inline/mut-rec-scc-2.ll new file mode 100644 index 0000000000000..df7a6aa5fc71c --- /dev/null +++ b/llvm/test/Transforms/Inline/mut-rec-scc-2.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -passes='inline' < %s | FileCheck %s + +; Make sure we don't mark calls within the same SCC as original function with noinline. +; CHECK-NOT: function-inline-cost-multiplier + +define void @samescc1() { + call void @samescc2() + ret void +} + +define void @samescc2() { + call void @samescc3() + ret void +} + +define void @samescc3() { + call void @samescc1() + ret void +} diff --git a/llvm/test/Transforms/Inline/mut-rec-scc.ll b/llvm/test/Transforms/Inline/mut-rec-scc.ll new file mode 100644 index 0000000000000..f7336a731f6e0 --- /dev/null +++ b/llvm/test/Transforms/Inline/mut-rec-scc.ll @@ -0,0 +1,75 @@ +; RUN: opt -S -passes='cgscc(inline,instcombine)' < %s | FileCheck %s +; RUN: opt -S -intra-scc-cost-multiplier=3 -passes='cgscc(inline,instcombine)' < %s | FileCheck %s --check-prefix=THREE + +; We use call to a dummy function to avoid inlining test1 into test2 or vice +; versa, such that we aren't left with a trivial cycle, as trivial cycles are +; special-cased to never be inlined. +; However, InstCombine will eliminate these calls after inlining, and thus +; make the functions eligible for inlining in their callers. +declare void @dummy() readnone nounwind willreturn + +define void @test1() { +; CHECK-LABEL: define void @test1( +; CHECK-NEXT: call void @test2() +; CHECK-NEXT: call void @test2() +; CHECK-NEXT: ret void +; + call void @test2() + call void @test2() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + ret void +} + +define void @test2() { +; CHECK-LABEL: define void @test2( +; CHECK-NEXT: call void @test1() +; CHECK-NEXT: call void @test1() +; CHECK-NEXT: ret void +; + call void @test1() + call void @test1() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + call void @dummy() + ret void +} + +; The inlined call sites should have the "function-inline-cost-multiplier" call site attribute. +; This test is a bit fragile in the exact number of inlining that happens based on thresholds. +define void @test3() { +; CHECK-LABEL: define void @test3( +; CHECK-NEXT: call void @test2() #[[COSTMULT:[0-9]+]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: call void @test2() #[[COSTMULT]] +; CHECK-NEXT: ret void +; + call void @test2() + call void @test2() + ret void +} + +; CHECK: [[COSTMULT]] = { "function-inline-cost-multiplier"="4" } +; THREE: "function-inline-cost-multiplier"="9" From da3953fb0315c0e65cc12479f3cd56a1dad7bc3f Mon Sep 17 00:00:00 2001 From: Andrew Wei Date: Tue, 15 Feb 2022 18:50:50 +0300 Subject: [PATCH 234/316] [NFC][PhaseOrdering] Add some tests from D119839 Based on original tests from D119839. See https://github.com/llvm/llvm-project/issues/53853 --- ...witch-lowering-vs-correlatedpropagation.ll | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll diff --git a/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll b/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll new file mode 100644 index 0000000000000..4e1863304e6ba --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll @@ -0,0 +1,143 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -O1 -S < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -O2 -S < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -O3 -S < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -passes='default' -S < %s | FileCheck %s +; RUN: opt -passes='default' -S < %s | FileCheck %s +; RUN: opt -passes='default' -S < %s | FileCheck %s + +; We are worse at propagating correlation facts when in select form +; as compared to the PHI form, so if we lower switches to early, +; we may make further optimizations problematic. + +; propagate value to bb2. +define i64 @test1(i64 %x) { +; CHECK-LABEL: @test1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[X]], 100 +; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TMP0]], i64 200, i64 10 +; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[SWITCH]], i64 0, i64 [[DOT]] +; CHECK-NEXT: ret i64 [[COMMON_RET_OP]] +; +entry: + switch i64 %x, label %bb3 [ + i64 0, label %bb1 + i64 1, label %bb2 + ] +bb1: + ret i64 0 +bb2: + %0 = icmp eq i64 %x, 100 + br i1 %0, label %bb4, label %bb5 +bb3: + unreachable +bb4: + ret i64 200 +bb5: + ret i64 10 +} + +; propagate value both to bb1 and bb2. +define i64 @test2(i64 %x) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i64 [[X:%.*]], 101 +; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i64 200, i64 10 +; CHECK-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i64 [[X]], 1 +; CHECK-NEXT: [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], i64 0, i64 [[SWITCH_SELECT]] +; CHECK-NEXT: ret i64 [[SWITCH_SELECT2]] +; +entry: + switch i64 %x, label %bb3 [ + i64 1, label %bb1 + i64 2, label %bb2 + ] +bb1: + %0 = icmp eq i64 %x, 100 + br i1 %0, label %bb4, label %return +return: + ret i64 0 +bb2: + %1 = icmp eq i64 %x, 101 + br i1 %1, label %bb4, label %bb5 +bb3: + unreachable +bb4: + ret i64 200 +bb5: + ret i64 10 +} + +define i64 @test3(i64 %x) { +; CHECK-LABEL: @test3( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[X:%.*]], 1 +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[COND]], i64 10, i64 0 +; CHECK-NEXT: ret i64 [[SPEC_SELECT]] +; +entry: + switch i64 %x, label %bb1 [ + i64 1, label %bb2 + ] +bb1: + ret i64 0 +bb2: + %0 = icmp eq i64 %x, 100 + br i1 %0, label %bb4, label %bb5 +bb4: + ret i64 200 +bb5: + ret i64 10 +} + +; bb2 has two predecessors with case value 1 and 2. +define i64 @test_fail1(i64 %x) { +; CHECK-LABEL: @test_fail1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[X]], 100 +; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TMP0]], i64 200, i64 10 +; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[SWITCH]], i64 0, i64 [[DOT]] +; CHECK-NEXT: ret i64 [[COMMON_RET_OP]] +; +entry: + switch i64 %x, label %bb3 [ + i64 0, label %bb1 + i64 1, label %bb2 + i64 2, label %bb2 + ] +bb1: + ret i64 0 +bb2: + %0 = icmp eq i64 %x, 100 + br i1 %0, label %bb4, label %bb5 +bb3: + unreachable +bb4: + ret i64 200 +bb5: + ret i64 10 +} + +; return block has two predecessors. +define i64 @test_fail2(i64 %x) { +; CHECK-LABEL: @test_fail2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i64 2, i64 [[X]] +; CHECK-NEXT: ret i64 [[SPEC_SELECT]] +; +entry: + switch i64 %x, label %bb2 [ + i64 0, label %bb1 + i64 1, label %return + ] +bb1: + br label %return +return: + %retval.0 = phi i64 [ %x, %entry ], [ 2, %bb1 ] + ret i64 %retval.0 +bb2: + unreachable +} From ba9ff030d302910e0d2155536558f71da98d5a5a Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Thu, 17 Feb 2022 12:07:17 +0300 Subject: [PATCH 235/316] [SimplifyCFG][PhaseOrdering] Defer lowering switch into an integer range comparison and branch until after at least the IPSCCP That transformation is lossy, as discussed in https://github.com/llvm/llvm-project/issues/53853 and https://github.com/rust-lang/rust/issues/85133#issuecomment-904185574 This is an alternative to D119839, which would add a limited IPSCCP into SimplifyCFG. Unlike lowering switch to lookup, we still want this transformation to happen relatively early, but after giving a chance for the things like CVP to do their thing. It seems like deferring it just until the IPSCCP is enough for the tests at hand, but perhaps we need to be more aggressive and disable it until CVP. Fixes https://github.com/llvm/llvm-project/issues/53853 Refs. https://github.com/rust-lang/rust/issues/85133 Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D119854 --- .../Transforms/Utils/SimplifyCFGOptions.h | 5 ++ llvm/lib/Passes/PassBuilder.cpp | 2 + llvm/lib/Passes/PassBuilderPipelines.cpp | 48 ++++++++++++------- llvm/lib/Passes/PassRegistry.def | 1 + .../Target/AArch64/AArch64TargetMachine.cpp | 1 + .../Target/Hexagon/HexagonTargetMachine.cpp | 1 + .../lib/Transforms/IPO/PassManagerBuilder.cpp | 29 +++++++---- .../lib/Transforms/Scalar/SimplifyCFGPass.cpp | 9 ++++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 4 +- llvm/test/Other/new-pm-print-pipeline.ll | 4 +- .../Coroutines/coro-catchswitch-cleanuppad.ll | 2 +- .../Transforms/LoopUnroll/ARM/upperbound.ll | 2 +- ...witch-lowering-vs-correlatedpropagation.ll | 28 +++++------ llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll | 2 +- .../SimplifyCFG/EqualPHIEdgeBlockMerge.ll | 2 +- ...risonIntoPredecessors-no-new-successors.ll | 2 +- .../ForwardSwitchConditionToPHI.ll | 8 ++-- .../SimplifyCFG/preserve-branchweights.ll | 2 +- .../SimplifyCFG/switch-dead-default.ll | 2 +- .../SimplifyCFG/switch-range-to-icmp.ll | 2 +- .../Transforms/SimplifyCFG/switch-to-icmp.ll | 2 +- .../SimplifyCFG/switch_create-custom-dl.ll | 2 +- .../Transforms/SimplifyCFG/switch_create.ll | 4 +- 23 files changed, 104 insertions(+), 60 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h b/llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h index fb3a7490346f4..7af879638a4d8 100644 --- a/llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h +++ b/llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h @@ -23,6 +23,7 @@ class AssumptionCache; struct SimplifyCFGOptions { int BonusInstThreshold = 1; bool ForwardSwitchCondToPhi = false; + bool ConvertSwitchRangeToICmp = false; bool ConvertSwitchToLookupTable = false; bool NeedCanonicalLoop = true; bool HoistCommonInsts = false; @@ -41,6 +42,10 @@ struct SimplifyCFGOptions { ForwardSwitchCondToPhi = B; return *this; } + SimplifyCFGOptions &convertSwitchRangeToICmp(bool B) { + ConvertSwitchRangeToICmp = B; + return *this; + } SimplifyCFGOptions &convertSwitchToLookupTable(bool B) { ConvertSwitchToLookupTable = B; return *this; diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 015ca1eec4df3..dedfc81f11bba 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -679,6 +679,8 @@ Expected parseSimplifyCFGOptions(StringRef Params) { bool Enable = !ParamName.consume_front("no-"); if (ParamName == "forward-switch-cond") { Result.forwardSwitchCondToPhi(Enable); + } else if (ParamName == "switch-range-to-icmp") { + Result.convertSwitchRangeToICmp(Enable); } else if (ParamName == "switch-to-lookup") { Result.convertSwitchToLookupTable(Enable); } else if (ParamName == "keep-loops") { diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index 194bff054fd72..e838665eb9ce9 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -259,14 +259,16 @@ PassBuilder::buildO1FunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(EarlyCSEPass(true /* Enable mem-ssa. */)); // Hoisting of scalars and load expressions. - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); FPM.addPass(InstCombinePass()); FPM.addPass(LibCallsShrinkWrapPass()); invokePeepholeEPCallbacks(FPM, Level); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); // Form canonically associated expression trees, and simplify the trees using // basic mathematical properties. For example, this will form (nearly) @@ -340,7 +342,8 @@ PassBuilder::buildO1FunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(createFunctionToLoopPassAdaptor(std::move(LPM1), /*UseMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); FPM.addPass(InstCombinePass()); // The loop passes in LPM2 (LoopFullUnrollPass) do not preserve MemorySSA. // *All* loop passes must preserve it, in order to be able to use it. @@ -378,7 +381,8 @@ PassBuilder::buildO1FunctionSimplificationPipeline(OptimizationLevel Level, // the simplifications and basic cleanup after all the simplifications. // TODO: Investigate if this is too expensive. FPM.addPass(ADCEPass()); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); FPM.addPass(InstCombinePass()); invokePeepholeEPCallbacks(FPM, Level); @@ -413,7 +417,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, // Global value numbering based sinking. if (EnableGVNSink) { FPM.addPass(GVNSinkPass()); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); } if (EnableConstraintElimination) @@ -426,7 +431,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(JumpThreadingPass()); FPM.addPass(CorrelatedValuePropagationPass()); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); FPM.addPass(InstCombinePass()); if (Level == OptimizationLevel::O3) FPM.addPass(AggressiveInstCombinePass()); @@ -443,7 +449,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(PGOMemOPSizeOpt()); FPM.addPass(TailCallElimPass()); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); // Form canonically associated expression trees, and simplify the trees using // basic mathematical properties. For example, this will form (nearly) @@ -520,7 +527,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, FPM.addPass(createFunctionToLoopPassAdaptor(std::move(LPM1), /*UseMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); - FPM.addPass(SimplifyCFGPass()); + FPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); FPM.addPass(InstCombinePass()); // The loop passes in LPM2 (LoopIdiomRecognizePass, IndVarSimplifyPass, // LoopDeletionPass and LoopFullUnrollPass) do not preserve MemorySSA. @@ -586,8 +594,10 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, for (auto &C : ScalarOptimizerLateEPCallbacks) C(FPM, Level); - FPM.addPass(SimplifyCFGPass( - SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true))); + FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions() + .convertSwitchRangeToICmp(true) + .hoistCommonInsts(true) + .sinkCommonInsts(true))); FPM.addPass(InstCombinePass()); invokePeepholeEPCallbacks(FPM, Level); @@ -625,7 +635,8 @@ void PassBuilder::addPGOInstrPasses(ModulePassManager &MPM, FunctionPassManager FPM; FPM.addPass(SROAPass()); FPM.addPass(EarlyCSEPass()); // Catch trivial redundancies. - FPM.addPass(SimplifyCFGPass()); // Merge & remove basic blocks. + FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp( + true))); // Merge & remove basic blocks. FPM.addPass(InstCombinePass()); // Combine silly sequences. invokePeepholeEPCallbacks(FPM, Level); @@ -939,7 +950,8 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, GlobalCleanupPM.addPass(InstCombinePass()); invokePeepholeEPCallbacks(GlobalCleanupPM, Level); - GlobalCleanupPM.addPass(SimplifyCFGPass()); + GlobalCleanupPM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); MPM.addPass(createModuleToFunctionPassAdaptor(std::move(GlobalCleanupPM), PTO.EagerlyInvalidateAnalyses)); @@ -1027,7 +1039,8 @@ void PassBuilder::addVectorPasses(OptimizationLevel Level, ExtraPasses.addPass( createFunctionToLoopPassAdaptor(std::move(LPM), /*UseMemorySSA=*/true, /*UseBlockFrequencyInfo=*/true)); - ExtraPasses.addPass(SimplifyCFGPass()); + ExtraPasses.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); ExtraPasses.addPass(InstCombinePass()); FPM.addPass(std::move(ExtraPasses)); } @@ -1043,6 +1056,7 @@ void PassBuilder::addVectorPasses(OptimizationLevel Level, // before SLP vectorization. FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions() .forwardSwitchCondToPhi(true) + .convertSwitchRangeToICmp(true) .convertSwitchToLookupTable(true) .needCanonicalLoops(false) .hoistCommonInsts(true) @@ -1215,7 +1229,8 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level, // LoopSink (and other loop passes since the last simplifyCFG) might have // resulted in single-entry-single-exit or empty blocks. Clean up the CFG. - OptimizePM.addPass(SimplifyCFGPass()); + OptimizePM.addPass( + SimplifyCFGPass(SimplifyCFGOptions().convertSwitchRangeToICmp(true))); OptimizePM.addPass(CoroCleanupPass()); @@ -1690,8 +1705,9 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, // Add late LTO optimization passes. // Delete basic blocks, which optimization passes may have killed. - MPM.addPass(createModuleToFunctionPassAdaptor( - SimplifyCFGPass(SimplifyCFGOptions().hoistCommonInsts(true)))); + MPM.addPass(createModuleToFunctionPassAdaptor(SimplifyCFGPass( + SimplifyCFGOptions().convertSwitchRangeToICmp(true).hoistCommonInsts( + true)))); // Drop bodies of available eternally objects to improve GlobalDCE. MPM.addPass(EliminateAvailableExternallyPass()); diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 8e0af11b854d0..69d8d8c432675 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -423,6 +423,7 @@ FUNCTION_PASS_WITH_PARAMS("simplifycfg", }, parseSimplifyCFGOptions, "no-forward-switch-cond;forward-switch-cond;" + "no-switch-range-to-icmp;switch-range-to-icmp;" "no-switch-to-lookup;switch-to-lookup;" "no-keep-loops;keep-loops;" "no-hoist-common-insts;hoist-common-insts;" diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 4af28fc070dd0..6a751da7ad554 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -531,6 +531,7 @@ void AArch64PassConfig::addIRPasses() { if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) addPass(createCFGSimplificationPass(SimplifyCFGOptions() .forwardSwitchCondToPhi(true) + .convertSwitchRangeToICmp(true) .convertSwitchToLookupTable(true) .needCanonicalLoops(false) .hoistCommonInsts(true) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index c6703bb8a62a5..08acf81961a3d 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -345,6 +345,7 @@ void HexagonPassConfig::addIRPasses() { if (EnableInitialCFGCleanup) addPass(createCFGSimplificationPass(SimplifyCFGOptions() .forwardSwitchCondToPhi(true) + .convertSwitchRangeToICmp(true) .convertSwitchToLookupTable(true) .needCanonicalLoops(false) .hoistCommonInsts(true) diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index fcfc7a90cf8b0..6e5aeb9c41f6f 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -365,7 +365,9 @@ void PassManagerBuilder::addPGOInstrPasses(legacy::PassManagerBase &MPM, MPM.add(createFunctionInliningPass(IP)); MPM.add(createSROAPass()); MPM.add(createEarlyCSEPass()); // Catch trivial redundancies - MPM.add(createCFGSimplificationPass()); // Merge & remove BBs + MPM.add(createCFGSimplificationPass( + SimplifyCFGOptions().convertSwitchRangeToICmp( + true))); // Merge & remove BBs MPM.add(createInstructionCombiningPass()); // Combine silly seq's addExtensionsToPM(EP_Peephole, MPM); } @@ -404,7 +406,8 @@ void PassManagerBuilder::addFunctionSimplificationPasses( MPM.add(createGVNHoistPass()); if (EnableGVNSink) { MPM.add(createGVNSinkPass()); - MPM.add(createCFGSimplificationPass()); + MPM.add(createCFGSimplificationPass( + SimplifyCFGOptions().convertSwitchRangeToICmp(true))); } } @@ -418,7 +421,9 @@ void PassManagerBuilder::addFunctionSimplificationPasses( MPM.add(createJumpThreadingPass()); // Thread jumps. MPM.add(createCorrelatedValuePropagationPass()); // Propagate conditionals } - MPM.add(createCFGSimplificationPass()); // Merge & remove BBs + MPM.add( + createCFGSimplificationPass(SimplifyCFGOptions().convertSwitchRangeToICmp( + true))); // Merge & remove BBs // Combine silly seq's if (OptLevel > 2) MPM.add(createAggressiveInstCombinerPass()); @@ -434,7 +439,9 @@ void PassManagerBuilder::addFunctionSimplificationPasses( // TODO: Investigate the cost/benefit of tail call elimination on debugging. if (OptLevel > 1) MPM.add(createTailCallEliminationPass()); // Eliminate tail calls - MPM.add(createCFGSimplificationPass()); // Merge & remove BBs + MPM.add( + createCFGSimplificationPass(SimplifyCFGOptions().convertSwitchRangeToICmp( + true))); // Merge & remove BBs MPM.add(createReassociatePass()); // Reassociate expressions // The matrix extension can introduce large vector operations early, which can @@ -470,7 +477,8 @@ void PassManagerBuilder::addFunctionSimplificationPasses( // FIXME: We break the loop pass pipeline here in order to do full // simplifycfg. Eventually loop-simplifycfg should be enhanced to replace the // need for this. - MPM.add(createCFGSimplificationPass()); + MPM.add(createCFGSimplificationPass( + SimplifyCFGOptions().convertSwitchRangeToICmp(true))); MPM.add(createInstructionCombiningPass()); // We resume loop passes creating a second loop pipeline here. if (EnableLoopFlatten) { @@ -589,7 +597,8 @@ void PassManagerBuilder::addVectorPasses(legacy::PassManagerBase &PM, PM.add(createLICMPass(LicmMssaOptCap, LicmMssaNoAccForPromotionCap, /*AllowSpeculation=*/true)); PM.add(createLoopUnswitchPass(SizeLevel || OptLevel < 3, DivergentTarget)); - PM.add(createCFGSimplificationPass()); + PM.add(createCFGSimplificationPass( + SimplifyCFGOptions().convertSwitchRangeToICmp(true))); PM.add(createInstructionCombiningPass()); } @@ -604,6 +613,7 @@ void PassManagerBuilder::addVectorPasses(legacy::PassManagerBase &PM, // before SLP vectorization. PM.add(createCFGSimplificationPass(SimplifyCFGOptions() .forwardSwitchCondToPhi(true) + .convertSwitchRangeToICmp(true) .convertSwitchToLookupTable(true) .needCanonicalLoops(false) .hoistCommonInsts(true) @@ -780,7 +790,9 @@ void PassManagerBuilder::populateModulePassManager( MPM.add(createInstructionCombiningPass()); // Clean up after IPCP & DAE addExtensionsToPM(EP_Peephole, MPM); - MPM.add(createCFGSimplificationPass()); // Clean up after IPCP & DAE + MPM.add( + createCFGSimplificationPass(SimplifyCFGOptions().convertSwitchRangeToICmp( + true))); // Clean up after IPCP & DAE // For SamplePGO in ThinLTO compile phase, we do not want to do indirect // call promotion as it will change the CFG too much to make the 2nd @@ -981,7 +993,8 @@ void PassManagerBuilder::populateModulePassManager( // LoopSink (and other loop passes since the last simplifyCFG) might have // resulted in single-entry-single-exit or empty blocks. Clean up the CFG. - MPM.add(createCFGSimplificationPass()); + MPM.add(createCFGSimplificationPass( + SimplifyCFGOptions().convertSwitchRangeToICmp(true))); addExtensionsToPM(EP_OptimizerLast, MPM); diff --git a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp index ee17da1875e50..b8972751066d8 100644 --- a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp +++ b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp @@ -59,6 +59,11 @@ static cl::opt UserKeepLoops( "keep-loops", cl::Hidden, cl::init(true), cl::desc("Preserve canonical loop structure (default = true)")); +static cl::opt UserSwitchRangeToICmp( + "switch-range-to-icmp", cl::Hidden, cl::init(false), + cl::desc( + "Convert switches into an integer range comparison (default = false)")); + static cl::opt UserSwitchToLookup( "switch-to-lookup", cl::Hidden, cl::init(false), cl::desc("Convert switches to lookup tables (default = false)")); @@ -311,6 +316,8 @@ static void applyCommandLineOverridesToOptions(SimplifyCFGOptions &Options) { Options.BonusInstThreshold = UserBonusInstThreshold; if (UserForwardSwitchCond.getNumOccurrences()) Options.ForwardSwitchCondToPhi = UserForwardSwitchCond; + if (UserSwitchRangeToICmp.getNumOccurrences()) + Options.ConvertSwitchRangeToICmp = UserSwitchRangeToICmp; if (UserSwitchToLookup.getNumOccurrences()) Options.ConvertSwitchToLookupTable = UserSwitchToLookup; if (UserKeepLoops.getNumOccurrences()) @@ -337,6 +344,8 @@ void SimplifyCFGPass::printPipeline( OS << "<"; OS << "bonus-inst-threshold=" << Options.BonusInstThreshold << ";"; OS << (Options.ForwardSwitchCondToPhi ? "" : "no-") << "forward-switch-cond;"; + OS << (Options.ConvertSwitchRangeToICmp ? "" : "no-") + << "switch-range-to-icmp;"; OS << (Options.ConvertSwitchToLookupTable ? "" : "no-") << "switch-to-lookup;"; OS << (Options.NeedCanonicalLoop ? "" : "no-") << "keep-loops;"; diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 335ac03ccb52a..8c4e1b381b4d4 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -6211,7 +6211,9 @@ bool SimplifyCFGOpt::simplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) { } // Try to transform the switch into an icmp and a branch. - if (TurnSwitchRangeIntoICmp(SI, Builder)) + // The conversion from switch to comparison may lose information on + // impossible switch values, so disable it early in the pipeline. + if (Options.ConvertSwitchRangeToICmp && TurnSwitchRangeIntoICmp(SI, Builder)) return requestResimplify(); // Remove unreachable cases. diff --git a/llvm/test/Other/new-pm-print-pipeline.ll b/llvm/test/Other/new-pm-print-pipeline.ll index 20d624a968526..3abf54ff4b491 100644 --- a/llvm/test/Other/new-pm-print-pipeline.ll +++ b/llvm/test/Other/new-pm-print-pipeline.ll @@ -1,7 +1,7 @@ ;; Test that the -print-pipeline-passes option correctly prints some explicitly specified pipelines. ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='function(adce),function(simplifycfg)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-0 -; CHECK-0: function(adce),function(simplifycfg) +; CHECK-0: function(adce),function(simplifycfg) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='module(rpo-function-attrs,require,function(float2int,lower-constant-intrinsics,loop(loop-rotate)),invalidate)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-1 ; CHECK-1: rpo-function-attrs,require,function(float2int,lower-constant-intrinsics,loop(loop-rotate)),invalidate @@ -56,7 +56,7 @@ ; CHECK-17: function(print,print) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='function(simplifycfg,simplifycfg)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-18 -; CHECK-18: function(simplifycfg,simplifycfg) +; CHECK-18: function(simplifycfg,simplifycfg) ; RUN: opt -disable-output -disable-verify -print-pipeline-passes -passes='function(loop-vectorize,loop-vectorize)' < %s | FileCheck %s --match-full-lines --check-prefixes=CHECK-19 ; CHECK-19: function(loop-vectorize,loop-vectorize) diff --git a/llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll b/llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll index 4650820c84eac..c14094e5b48df 100644 --- a/llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll +++ b/llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll @@ -1,6 +1,6 @@ ; Tests the PHI nodes in cleanuppads for catchswitch instructions are correctly ; split up. -; RUN: opt < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -S | FileCheck %s +; RUN: opt < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -S | FileCheck %s declare i32 @__CxxFrameHandler3(...) define i8* @f2(i1 %val) "coroutine.presplit"="1" personality i32 (...)* @__CxxFrameHandler3 { diff --git a/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll b/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll index 33151c68b3198..ffa474afcd508 100644 --- a/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll +++ b/llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -loop-unroll -simplifycfg -instcombine -simplifycfg -S -mtriple arm-none-eabi -mcpu=cortex-m7 %s | FileCheck %s +; RUN: opt -loop-unroll -simplifycfg -switch-range-to-icmp -instcombine -simplifycfg -S -mtriple arm-none-eabi -mcpu=cortex-m7 %s | FileCheck %s ; This test is meant to check that this loop is unrolled into three iterations. define void @test(i32* %x, i32 %n) { diff --git a/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll b/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll index 4e1863304e6ba..0ca042f9ad7ff 100644 --- a/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll +++ b/llvm/test/Transforms/PhaseOrdering/simplifycfg-switch-lowering-vs-correlatedpropagation.ll @@ -14,11 +14,9 @@ define i64 @test1(i64 %x) { ; CHECK-LABEL: @test1( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[X]], 100 -; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TMP0]], i64 200, i64 10 -; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[SWITCH]], i64 0, i64 [[DOT]] -; CHECK-NEXT: ret i64 [[COMMON_RET_OP]] +; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i64 [[X:%.*]], 0 +; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i64 0, i64 10 +; CHECK-NEXT: ret i64 [[SWITCH_SELECT]] ; entry: switch i64 %x, label %bb3 [ @@ -42,11 +40,9 @@ bb5: define i64 @test2(i64 %x) { ; CHECK-LABEL: @test2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i64 [[X:%.*]], 101 -; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i64 200, i64 10 -; CHECK-NEXT: [[SWITCH_SELECTCMP1:%.*]] = icmp eq i64 [[X]], 1 -; CHECK-NEXT: [[SWITCH_SELECT2:%.*]] = select i1 [[SWITCH_SELECTCMP1]], i64 0, i64 [[SWITCH_SELECT]] -; CHECK-NEXT: ret i64 [[SWITCH_SELECT2]] +; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i64 [[X:%.*]], 1 +; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i64 0, i64 10 +; CHECK-NEXT: ret i64 [[SWITCH_SELECT]] ; entry: switch i64 %x, label %bb3 [ @@ -96,10 +92,8 @@ define i64 @test_fail1(i64 %x) { ; CHECK-LABEL: @test_fail1( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[X]], 100 -; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TMP0]], i64 200, i64 10 -; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[SWITCH]], i64 0, i64 [[DOT]] -; CHECK-NEXT: ret i64 [[COMMON_RET_OP]] +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i64 0, i64 10 +; CHECK-NEXT: ret i64 [[SPEC_SELECT]] ; entry: switch i64 %x, label %bb3 [ @@ -124,9 +118,9 @@ bb5: define i64 @test_fail2(i64 %x) { ; CHECK-LABEL: @test_fail2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[SWITCH:%.*]] = icmp eq i64 [[X:%.*]], 0 -; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[SWITCH]], i64 2, i64 [[X]] -; CHECK-NEXT: ret i64 [[SPEC_SELECT]] +; CHECK-NEXT: [[SWITCH_SELECTCMP:%.*]] = icmp eq i64 [[X:%.*]], 0 +; CHECK-NEXT: [[SWITCH_SELECT:%.*]] = select i1 [[SWITCH_SELECTCMP]], i64 2, i64 1 +; CHECK-NEXT: ret i64 [[SWITCH_SELECT]] ; entry: switch i64 %x, label %bb2 [ diff --git a/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll b/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll index fd322a938f8f2..ff9c3be3397d4 100644 --- a/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll +++ b/llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s +; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp -S | FileCheck %s ; Check that simplifycfg deletes a dead 'seteq' instruction when it ; folds a conditional branch into a switch instruction. diff --git a/llvm/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll b/llvm/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll index 96cd0469a38d7..c550abd9ad822 100644 --- a/llvm/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll +++ b/llvm/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; Test merging of blocks with phi nodes. ; -; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s +; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp -S | FileCheck %s ; ; ModuleID = '' diff --git a/llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll b/llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll index 04d5d4d5a645b..3fbd5bfe4574b 100644 --- a/llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll +++ b/llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp < %s | FileCheck %s define void @widget(i32 %arg) { ; CHECK-LABEL: @widget( diff --git a/llvm/test/Transforms/SimplifyCFG/ForwardSwitchConditionToPHI.ll b/llvm/test/Transforms/SimplifyCFG/ForwardSwitchConditionToPHI.ll index b57284d16688b..bebe18abfb73a 100644 --- a/llvm/test/Transforms/SimplifyCFG/ForwardSwitchConditionToPHI.ll +++ b/llvm/test/Transforms/SimplifyCFG/ForwardSwitchConditionToPHI.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -forward-switch-cond=false -S | FileCheck %s --check-prefix=NO_FWD -; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -forward-switch-cond=true -S | FileCheck %s --check-prefix=FWD +; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -forward-switch-cond=false -switch-range-to-icmp -S | FileCheck %s --check-prefix=NO_FWD +; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -forward-switch-cond=true -switch-range-to-icmp -S | FileCheck %s --check-prefix=FWD -; RUN: opt < %s -passes='simplifycfg' -S | FileCheck %s --check-prefix=NO_FWD -; RUN: opt < %s -passes='simplifycfg' -S | FileCheck %s --check-prefix=FWD +; RUN: opt < %s -passes='simplifycfg' -S | FileCheck %s --check-prefix=NO_FWD +; RUN: opt < %s -passes='simplifycfg' -S | FileCheck %s --check-prefix=FWD ; PR10131 diff --git a/llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll b/llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll index f113ad84dc8fc..fc200e041125e 100644 --- a/llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll +++ b/llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals -; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -o - < %s | FileCheck %s +; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp -S -o - < %s | FileCheck %s declare void @helper(i32) diff --git a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll index 154ecb2166310..1662bb99f27bc 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt %s -S -passes='simplifycfg' -simplifycfg-require-and-preserve-domtree=1 | FileCheck %s +; RUN: opt %s -S -passes='simplifycfg' -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" declare void @foo(i32) diff --git a/llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll b/llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll index 56a6895f29b8f..5a6cb463bd6f1 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s +; RUN: opt %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp -S | FileCheck %s declare i32 @f(i32) diff --git a/llvm/test/Transforms/SimplifyCFG/switch-to-icmp.ll b/llvm/test/Transforms/SimplifyCFG/switch-to-icmp.ll index bfb27cd461147..c9ba839ec0a5b 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-to-icmp.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-to-icmp.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp < %s | FileCheck %s define zeroext i1 @test1(i32 %x) nounwind readnone ssp noredzone { entry: diff --git a/llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll b/llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll index 499064e40a907..59064fbd8dc1a 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp < %s | FileCheck %s target datalayout="p:40:64:64:32" declare void @foo1() diff --git a/llvm/test/Transforms/SimplifyCFG/switch_create.ll b/llvm/test/Transforms/SimplifyCFG/switch_create.ll index 1ba0971fc4f01..d4ae9471a2810 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch_create.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch_create.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s -; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s +; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp < %s | FileCheck %s +; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s declare void @foo1() From d843bde69aab7fbb3efff34229e8876b1ce80a5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 8 Mar 2022 14:21:37 +0100 Subject: [PATCH 236/316] [clang][driver] Fix float128 diagnostics with glibc >= 2.32 Fix checking for an unsupported stdlib++. Differential Revision: https://reviews.llvm.org/D121209 (cherry picked from commit 5b7941ad7c893b4bb019e3c96b760b0f2670ccfc) --- clang/lib/Driver/ToolChains/PPCLinux.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/clang/lib/Driver/ToolChains/PPCLinux.cpp b/clang/lib/Driver/ToolChains/PPCLinux.cpp index e480d8bd8703c..2fea262fd109c 100644 --- a/clang/lib/Driver/ToolChains/PPCLinux.cpp +++ b/clang/lib/Driver/ToolChains/PPCLinux.cpp @@ -76,9 +76,11 @@ bool PPCLinuxToolChain::SupportIEEEFloat128( if (Args.hasArg(options::OPT_nostdlib, options::OPT_nostdlibxx)) return true; + CXXStdlibType StdLib = ToolChain::GetCXXStdlibType(Args); bool HasUnsupportedCXXLib = - ToolChain::GetCXXStdlibType(Args) == CST_Libcxx && - GCCInstallation.getVersion().isOlderThan(12, 1, 0); + StdLib == CST_Libcxx || + (StdLib == CST_Libstdcxx && + GCCInstallation.getVersion().isOlderThan(12, 1, 0)); return GlibcSupportsFloat128(Linux::getDynamicLinker(Args)) && !(D.CCCIsCXX() && HasUnsupportedCXXLib); From eb84577cbc23d44735f10bca9dbd2151aba96a60 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 8 Mar 2022 20:35:53 -0800 Subject: [PATCH 237/316] Revert "[release] Use the Bootstrapping build for building LLVM releases" This reverts commit c8bb1777fff5d1ae28a2deac0d6677e081d4200f to fix https://github.com/llvm/llvm-project/issues/54154 on the release branch. Differential Revision: https://reviews.llvm.org/D121258 --- llvm/utils/release/test-release.sh | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index 009f9358145f3..e27e857935376 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -244,17 +244,16 @@ projects="llvm clang" if [ $do_clang_tools = "yes" ]; then projects="$projects clang-tools-extra" fi -runtimes="" if [ $do_rt = "yes" ]; then - runtimes="$runtimes compiler-rt" + projects="$projects compiler-rt" fi if [ $do_libs = "yes" ]; then - runtimes="$runtimes libcxx" + projects="$projects libcxx" if [ $do_libcxxabi = "yes" ]; then - runtimes="$runtimes libcxxabi" + projects="$projects libcxxabi" fi if [ $do_libunwind = "yes" ]; then - runtimes="$runtimes libunwind" + projects="$projects libunwind" fi fi if [ $do_openmp = "yes" ]; then @@ -381,7 +380,6 @@ function configure_llvmCore() { esac project_list=${projects// /;} - runtime_list=${runtimes// /;} echo "# Using C compiler: $c_compiler" echo "# Using C++ compiler: $cxx_compiler" @@ -394,7 +392,6 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ - -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log env CC="$c_compiler" CXX="$cxx_compiler" \ @@ -403,7 +400,6 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ - -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log From f7007c570a216c0fa87b863733a1011bdb2ff9ca Mon Sep 17 00:00:00 2001 From: David Stone Date: Fri, 18 Feb 2022 05:54:33 -0800 Subject: [PATCH 238/316] Lambdas are not necessarily locals. This resolves DR48250. Differential Revision: https://reviews.llvm.org/D99134 (cherry picked from commit 0bff3a965022647fcdd17cc8f2217f5a2cd30b4c) --- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 4 +++- .../SemaCXX/lambdas-implicit-explicit-template.cpp | 10 ++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index 1da0dfec3f230..467372c71496a 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -6012,7 +6012,9 @@ NamedDecl *Sema::FindInstantiatedDecl(SourceLocation Loc, NamedDecl *D, (ParentDependsOnArgs && (ParentDC->isFunctionOrMethod() || isa(ParentDC) || isa(ParentDC))) || - (isa(D) && cast(D)->isLambda())) { + (isa(D) && cast(D)->isLambda() && + cast(D)->getTemplateDepth() > + TemplateArgs.getNumRetainedOuterLevels())) { // D is a local of some kind. Look into the map of local // declarations to their instantiations. if (CurrentInstantiationScope) { diff --git a/clang/test/SemaCXX/lambdas-implicit-explicit-template.cpp b/clang/test/SemaCXX/lambdas-implicit-explicit-template.cpp index 13fe12abe9e9d..a5410d2aed597 100644 --- a/clang/test/SemaCXX/lambdas-implicit-explicit-template.cpp +++ b/clang/test/SemaCXX/lambdas-implicit-explicit-template.cpp @@ -39,3 +39,13 @@ void c2() { const auto lambda = [&](auto arg1) {}; [&](auto arg2) { lambda.operator()(arg2); }(0); } + +auto d = [](auto) {}; + +template +void d1(T x) { d.operator()(x); } + +void d2() { d1(0); } + +template int e1 = [](auto){ return T(); }.operator()(T()); +int e2 = e1; From 569b773323a3a1c174ae794741c7e1191f8deefc Mon Sep 17 00:00:00 2001 From: David Spickett Date: Wed, 16 Feb 2022 15:47:16 +0000 Subject: [PATCH 239/316] [libcxx][CI] Set Arm triples to match native clang build's default We were using: armv8-linux-gnueabihf But for a native clang build the default target is: armv8l-linux-gnueabihf (ditto for v7) Add the "l" to the target triples and update the one test that is unsupported to look for the various possible names. armv(7 or 8)(m or l, optionally) The UNSUPPORTED does not include aarch64 because aarch64 Linux (and others that follow Arm's AAPCS64) use quad precision for long double where arm64 (darwin) does not: https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#811arithmetic-types Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D119948 --- libcxx/cmake/caches/Armv7Arm.cmake | 2 +- libcxx/cmake/caches/Armv7Thumb-noexceptions.cmake | 2 +- libcxx/cmake/caches/Armv8Arm.cmake | 2 +- libcxx/cmake/caches/Armv8Thumb-noexceptions.cmake | 2 +- .../cmp/cmp.alg/strong_order_long_double.verify.cpp | 3 ++- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/libcxx/cmake/caches/Armv7Arm.cmake b/libcxx/cmake/caches/Armv7Arm.cmake index 8b2b54eba13ce..0e9dc10e9d41f 100644 --- a/libcxx/cmake/caches/Armv7Arm.cmake +++ b/libcxx/cmake/caches/Armv7Arm.cmake @@ -1,4 +1,4 @@ set(LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(LIBCXX_TARGET_TRIPLE "armv7-linux-gnueabihf" CACHE STRING "") +set(LIBCXX_TARGET_TRIPLE "armv7l-linux-gnueabihf" CACHE STRING "") set(CMAKE_CXX_FLAGS "-marm" CACHE STRING "") set(CMAKE_C_FLAGS "-marm" CACHE STRING "") diff --git a/libcxx/cmake/caches/Armv7Thumb-noexceptions.cmake b/libcxx/cmake/caches/Armv7Thumb-noexceptions.cmake index 67ec43b93f207..61cd3bf7376ea 100644 --- a/libcxx/cmake/caches/Armv7Thumb-noexceptions.cmake +++ b/libcxx/cmake/caches/Armv7Thumb-noexceptions.cmake @@ -1,5 +1,5 @@ set(LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(LIBCXX_TARGET_TRIPLE "armv7-linux-gnueabihf" CACHE STRING "") +set(LIBCXX_TARGET_TRIPLE "armv7l-linux-gnueabihf" CACHE STRING "") set(CMAKE_CXX_FLAGS "-mthumb" CACHE STRING "") set(CMAKE_C_FLAGS "-mthumb" CACHE STRING "") set(LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Armv8Arm.cmake b/libcxx/cmake/caches/Armv8Arm.cmake index 55dfa908b3d01..eee2eb46da56d 100644 --- a/libcxx/cmake/caches/Armv8Arm.cmake +++ b/libcxx/cmake/caches/Armv8Arm.cmake @@ -1,4 +1,4 @@ set(LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(LIBCXX_TARGET_TRIPLE "armv8-linux-gnueabihf" CACHE STRING "") +set(LIBCXX_TARGET_TRIPLE "armv8l-linux-gnueabihf" CACHE STRING "") set(CMAKE_CXX_FLAGS "-marm" CACHE STRING "") set(CMAKE_C_FLAGS "-marm" CACHE STRING "") diff --git a/libcxx/cmake/caches/Armv8Thumb-noexceptions.cmake b/libcxx/cmake/caches/Armv8Thumb-noexceptions.cmake index fb1d10efaddce..9c2f90661ef8d 100644 --- a/libcxx/cmake/caches/Armv8Thumb-noexceptions.cmake +++ b/libcxx/cmake/caches/Armv8Thumb-noexceptions.cmake @@ -1,5 +1,5 @@ set(LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(LIBCXX_TARGET_TRIPLE "armv8-linux-gnueabihf" CACHE STRING "") +set(LIBCXX_TARGET_TRIPLE "armv8l-linux-gnueabihf" CACHE STRING "") set(CMAKE_CXX_FLAGS "-mthumb" CACHE STRING "") set(CMAKE_C_FLAGS "-mthumb" CACHE STRING "") set(LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "") diff --git a/libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_double.verify.cpp b/libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_double.verify.cpp index b35a50e0a5894..3d777d9d81b60 100644 --- a/libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_double.verify.cpp +++ b/libcxx/test/std/language.support/cmp/cmp.alg/strong_order_long_double.verify.cpp @@ -10,7 +10,8 @@ // UNSUPPORTED: libcpp-no-concepts // The following platforms have sizeof(long double) == sizeof(double), so this test doesn't apply to them. -// UNSUPPORTED: target={{arm64|armv8|armv7|armv7m|powerpc|powerpc64}}-{{.+}} +// This test does apply to aarch64 where Arm's AAPCS64 is followed. There they are different sizes. +// UNSUPPORTED: target={{arm64|armv(7|8)(l|m)?|powerpc|powerpc64}}-{{.+}} // UNSUPPORTED: target=x86_64-pc-windows-{{.+}} // From e879b2bf82ef2d096d2c0e5147ebac541a7b8828 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Fri, 11 Feb 2022 12:48:31 +0100 Subject: [PATCH 240/316] [libcxxabi] [test] Depend on unwind only if available When building libcxxabi via LLVM_ENABLE_RUNTIMES=libcxxabi the CMake invocation fails because of missing "unwind" target. However, if the extraneous dependency is removed, the library builds just fine against installed libunwind and tests work fine. To fix this, add the dependency only if the target actually exists. Differential Revision: https://reviews.llvm.org/D119538 (cherry picked from commit 5244ef0faf5595495c1adedfa16c346d35caebdf) --- libcxxabi/test/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxxabi/test/CMakeLists.txt b/libcxxabi/test/CMakeLists.txt index 6baaf40ca7b11..57b5fccab8008 100644 --- a/libcxxabi/test/CMakeLists.txt +++ b/libcxxabi/test/CMakeLists.txt @@ -63,7 +63,7 @@ endif() if (NOT LIBCXXABI_STANDALONE_BUILD) list(APPEND LIBCXXABI_TEST_DEPS cxx) - if (LIBCXXABI_USE_LLVM_UNWINDER) + if (LIBCXXABI_USE_LLVM_UNWINDER AND TARGET unwind) list(APPEND LIBCXXABI_TEST_DEPS unwind) endif() endif() From e54a7bf0c0f14115ec3bd7738850ee83f8428319 Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Wed, 9 Mar 2022 00:48:49 -0800 Subject: [PATCH 241/316] [CMake] Include runtimes test suites in check-all Prior to this change, we would make check-all depend on check-runtimes which is a target that runs tests in the runtimes build. This means that the runtimes tests are going to run prior to other test suites in check-all, and if one of them fails, we won't run the other test suites at all. To address this issue, we instead collect the list of test suites and their dependencies from the runtimes subbuild, and include them in check-all, so a failure of runtimes test suite doesn't prevent other test suites from being executed. This addresses https://github.com/llvm/llvm-project/issues/54154. Differential Revision: https://reviews.llvm.org/D121276 (cherry picked from commit f39a971d821097df1936469b3fd5ba6a9b8e4b69) --- llvm/CMakeLists.txt | 3 --- llvm/runtimes/CMakeLists.txt | 15 ++++++++++++++- runtimes/CMakeLists.txt | 10 ++++++++++ runtimes/Tests.cmake.in | 3 +++ 4 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 runtimes/Tests.cmake.in diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 00d01f4ddbbd2..123998df34c84 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -1138,9 +1138,6 @@ if( LLVM_INCLUDE_TESTS ) DEPENDS ${LLVM_LIT_DEPENDS} ${LLVM_ADDITIONAL_TEST_TARGETS} ARGS ${LLVM_LIT_EXTRA_ARGS} ) - if(TARGET check-runtimes) - add_dependencies(check-all check-runtimes) - endif() add_custom_target(test-depends DEPENDS ${LLVM_LIT_DEPENDS} ${LLVM_ADDITIONAL_TEST_DEPENDS}) set_target_properties(test-depends PROPERTIES FOLDER "Tests") diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt index 05567b5234eea..d7918c211e40e 100644 --- a/llvm/runtimes/CMakeLists.txt +++ b/llvm/runtimes/CMakeLists.txt @@ -220,6 +220,13 @@ function(runtime_default_target) endforeach() if(LLVM_INCLUDE_TESTS) + include(${LLVM_BINARY_DIR}/runtimes/Tests.cmake OPTIONAL RESULT_VARIABLE have_tests) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${LLVM_BINARY_DIR}/runtimes/Tests.cmake) + if(have_tests) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_TESTSUITES ${RUNTIMES_LIT_TESTSUITES}) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_PARAMS ${RUNTIMES_LIT_PARAMS}) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_EXTRA_ARGS ${RUNTIMES_LIT_EXTRA_ARGS}) + endif() list(APPEND test_targets runtimes-test-depends check-runtimes) endif() @@ -296,6 +303,13 @@ function(runtime_register_target name target) endforeach() if(LLVM_INCLUDE_TESTS) + include(${LLVM_BINARY_DIR}/runtimes/${name}/Tests.cmake OPTIONAL RESULT_VARIABLE have_tests) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${LLVM_BINARY_DIR}/runtimes/${name}/Tests.cmake) + if(have_tests) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_TESTSUITES ${RUNTIMES_LIT_TESTSUITES}) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_PARAMS ${RUNTIMES_LIT_PARAMS}) + set_property(GLOBAL APPEND PROPERTY LLVM_LIT_EXTRA_ARGS ${RUNTIMES_LIT_EXTRA_ARGS}) + endif() set(runtimes-test-depends-${name} runtimes-test-depends) set(check-runtimes-${name} check-runtimes) list(APPEND ${name}_test_targets runtimes-test-depends-${name} check-runtimes-${name}) @@ -468,7 +482,6 @@ if(runtimes) if(LLVM_INCLUDE_TESTS) set_property(GLOBAL APPEND PROPERTY LLVM_ADDITIONAL_TEST_DEPENDS runtimes-test-depends) - set_property(GLOBAL APPEND PROPERTY LLVM_ADDITIONAL_TEST_TARGETS check-runtimes) set(RUNTIMES_TEST_DEPENDS FileCheck diff --git a/runtimes/CMakeLists.txt b/runtimes/CMakeLists.txt index 1400233b73f6d..945d3de9ec44b 100644 --- a/runtimes/CMakeLists.txt +++ b/runtimes/CMakeLists.txt @@ -221,6 +221,16 @@ if(LLVM_INCLUDE_TESTS) add_subdirectory(${LLVM_MAIN_SRC_DIR}/utils/llvm-lit ${CMAKE_CURRENT_BINARY_DIR}/llvm-lit) endif() + + if(LLVM_RUNTIMES_TARGET) + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/Tests.cmake.in + ${LLVM_BINARY_DIR}/runtimes/${LLVM_RUNTIMES_TARGET}/Tests.cmake) + else() + configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/Tests.cmake.in + ${LLVM_BINARY_DIR}/runtimes/Tests.cmake) + endif() endif() get_property(SUB_COMPONENTS GLOBAL PROPERTY SUB_COMPONENTS) diff --git a/runtimes/Tests.cmake.in b/runtimes/Tests.cmake.in new file mode 100644 index 0000000000000..4df40f237b3f5 --- /dev/null +++ b/runtimes/Tests.cmake.in @@ -0,0 +1,3 @@ +set(RUNTIMES_LIT_TESTSUITES @RUNTIMES_LIT_TESTSUITES@) +set(RUNTIMES_LIT_PARAMS @RUNTIMES_LIT_PARAMS@) +set(RUNTIMES_LIT_EXTRA_ARGS @RUNTIMES_LIT_EXTRA_ARGS@) From a9415df334f09c1bea51ce2be1684b4391eac245 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 10 Mar 2022 12:51:05 -0800 Subject: [PATCH 242/316] Revert "Revert "[release] Use the Bootstrapping build for building LLVM releases"" This reverts commit eb84577cbc23d44735f10bca9dbd2151aba96a60. The issues with check-all were fixed in e54a7bf0c0f14115ec3bd7738850ee83f8428319, so we can re-enable bootstrap build for test-release.sh. --- llvm/utils/release/test-release.sh | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index e27e857935376..009f9358145f3 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -244,16 +244,17 @@ projects="llvm clang" if [ $do_clang_tools = "yes" ]; then projects="$projects clang-tools-extra" fi +runtimes="" if [ $do_rt = "yes" ]; then - projects="$projects compiler-rt" + runtimes="$runtimes compiler-rt" fi if [ $do_libs = "yes" ]; then - projects="$projects libcxx" + runtimes="$runtimes libcxx" if [ $do_libcxxabi = "yes" ]; then - projects="$projects libcxxabi" + runtimes="$runtimes libcxxabi" fi if [ $do_libunwind = "yes" ]; then - projects="$projects libunwind" + runtimes="$runtimes libunwind" fi fi if [ $do_openmp = "yes" ]; then @@ -380,6 +381,7 @@ function configure_llvmCore() { esac project_list=${projects// /;} + runtime_list=${runtimes// /;} echo "# Using C compiler: $c_compiler" echo "# Using C++ compiler: $cxx_compiler" @@ -392,6 +394,7 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ + -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log env CC="$c_compiler" CXX="$cxx_compiler" \ @@ -400,6 +403,7 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ + -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log From 893b864cb855e624c0f72da4b66e758e1f073f20 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 10 Mar 2022 12:52:12 -0800 Subject: [PATCH 243/316] Revert "GCC ABI Compatibility: Preserve alignment of non-pod members in packed structs" This reverts commit 277123376ce08c98b07c154bf83e4092a5d4d3c6. There are still some issues with this change to be worked out, so revert this patch to avoid having to change ABIs from LLVM 13->14 and then again from LLVM 14->15. See discussion in https://reviews.llvm.org/D118511 --- clang/docs/ReleaseNotes.rst | 6 ---- clang/include/clang/Basic/LangOptions.h | 4 --- clang/lib/AST/RecordLayoutBuilder.cpp | 7 +---- clang/lib/Frontend/CompilerInvocation.cpp | 4 --- clang/test/SemaCXX/class-layout.cpp | 37 ----------------------- 5 files changed, 1 insertion(+), 57 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4eaa589b542dd..5821e41fc7332 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -338,12 +338,6 @@ ABI Changes in Clang is still in the process of being stabilized, so this type should not yet be used in interfaces that require ABI stability. -- GCC doesn't pack non-POD members in packed structs unless the packed - attribute is also specified on the member. Clang historically did perform - such packing. Clang now matches the gcc behavior (except on Darwin and PS4). - You can switch back to the old ABI behavior with the flag: - ``-fclang-abi-compat=13.0``. - OpenMP Support in Clang ----------------------- diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index 50c7f038fc6be..09afa641acf9b 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -181,10 +181,6 @@ class LangOptions : public LangOptionsBase { /// global-scope inline variables incorrectly. Ver12, - /// Attempt to be ABI-compatible with code generated by Clang 13.0.x. - /// This causes clang to not pack non-POD members of packed structs. - Ver13, - /// Conform to the underlying platform's C and C++ ABIs as closely /// as we can. Latest diff --git a/clang/lib/AST/RecordLayoutBuilder.cpp b/clang/lib/AST/RecordLayoutBuilder.cpp index 709e05716a562..61a30ead165ef 100644 --- a/clang/lib/AST/RecordLayoutBuilder.cpp +++ b/clang/lib/AST/RecordLayoutBuilder.cpp @@ -1887,12 +1887,7 @@ void ItaniumRecordLayoutBuilder::LayoutField(const FieldDecl *D, UnfilledBitsInLastUnit = 0; LastBitfieldStorageUnitSize = 0; - llvm::Triple Target = Context.getTargetInfo().getTriple(); - bool FieldPacked = (Packed && (!FieldClass || FieldClass->isPOD() || - Context.getLangOpts().getClangABICompat() <= - LangOptions::ClangABI::Ver13 || - Target.isPS4() || Target.isOSDarwin())) || - D->hasAttr(); + bool FieldPacked = Packed || D->hasAttr(); AlignRequirementKind AlignRequirement = AlignRequirementKind::None; CharUnits FieldSize; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 553a0b31c0ab3..7f1ce3da7e7eb 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -3560,8 +3560,6 @@ void CompilerInvocation::GenerateLangArgs(const LangOptions &Opts, GenerateArg(Args, OPT_fclang_abi_compat_EQ, "11.0", SA); else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver12) GenerateArg(Args, OPT_fclang_abi_compat_EQ, "12.0", SA); - else if (Opts.getClangABICompat() == LangOptions::ClangABI::Ver13) - GenerateArg(Args, OPT_fclang_abi_compat_EQ, "13.0", SA); if (Opts.getSignReturnAddressScope() == LangOptions::SignReturnAddressScopeKind::All) @@ -4064,8 +4062,6 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, Opts.setClangABICompat(LangOptions::ClangABI::Ver11); else if (Major <= 12) Opts.setClangABICompat(LangOptions::ClangABI::Ver12); - else if (Major <= 13) - Opts.setClangABICompat(LangOptions::ClangABI::Ver13); } else if (Ver != "latest") { Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << A->getValue(); diff --git a/clang/test/SemaCXX/class-layout.cpp b/clang/test/SemaCXX/class-layout.cpp index 79fa677071109..5403bd6e6a6f6 100644 --- a/clang/test/SemaCXX/class-layout.cpp +++ b/clang/test/SemaCXX/class-layout.cpp @@ -1,9 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -fsyntax-only -verify -std=c++98 -Wno-inaccessible-base // RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -fsyntax-only -verify -std=c++11 -Wno-inaccessible-base -// RUN: %clang_cc1 -triple x86_64-apple-darwin %s -fsyntax-only -verify -std=c++11 -Wno-inaccessible-base -DCLANG_ABI_COMPAT=13 -// RUN: %clang_cc1 -triple x86_64-scei-ps4 %s -fsyntax-only -verify -std=c++11 -Wno-inaccessible-base -DCLANG_ABI_COMPAT=6 // RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -fsyntax-only -verify -std=c++11 -Wno-inaccessible-base -fclang-abi-compat=6 -DCLANG_ABI_COMPAT=6 -// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -fsyntax-only -verify -std=c++11 -Wno-inaccessible-base -fclang-abi-compat=13 -DCLANG_ABI_COMPAT=13 // expected-no-diagnostics #define SA(n, p) int a##n[(p) ? 1 : -1] @@ -607,37 +604,3 @@ namespace PR37275 { #endif #pragma pack(pop) } - -namespace non_pod { -struct t1 { -protected: - int a; -}; -// GCC prints warning: ignoring packed attribute because of unpacked non-POD field 't1 t2::v1'` -struct t2 { - char c1; - short s1; - char c2; - t1 v1; -} __attribute__((packed)); -#if defined(CLANG_ABI_COMPAT) && CLANG_ABI_COMPAT <= 13 -_Static_assert(_Alignof(t1) == 4, ""); -_Static_assert(_Alignof(t2) == 1, ""); -#else -_Static_assert(_Alignof(t1) == 4, ""); -_Static_assert(_Alignof(t2) == 4, ""); -#endif -_Static_assert(sizeof(t2) == 8, ""); // it's still packing the rest of the struct -} // namespace non_pod - -namespace non_pod_packed { -struct t1 { -protected: - int a; -} __attribute__((packed)); -struct t2 { - t1 v1; -} __attribute__((packed)); -_Static_assert(_Alignof(t1) == 1, ""); -_Static_assert(_Alignof(t2) == 1, ""); -} // namespace non_pod_packed From df2fcea78fb8496ab20551ea040872015fd54b5d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 11 Mar 2022 10:13:59 -0800 Subject: [PATCH 244/316] Revert "Revert "Revert "[release] Use the Bootstrapping build for building LLVM releases""" This reverts commit a9415df334f09c1bea51ce2be1684b4391eac245. There are still bugs reported with the new bootstraping build. See https://reviews.llvm.org/D121276#3375464 --- llvm/utils/release/test-release.sh | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index 009f9358145f3..e27e857935376 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -244,17 +244,16 @@ projects="llvm clang" if [ $do_clang_tools = "yes" ]; then projects="$projects clang-tools-extra" fi -runtimes="" if [ $do_rt = "yes" ]; then - runtimes="$runtimes compiler-rt" + projects="$projects compiler-rt" fi if [ $do_libs = "yes" ]; then - runtimes="$runtimes libcxx" + projects="$projects libcxx" if [ $do_libcxxabi = "yes" ]; then - runtimes="$runtimes libcxxabi" + projects="$projects libcxxabi" fi if [ $do_libunwind = "yes" ]; then - runtimes="$runtimes libunwind" + projects="$projects libunwind" fi fi if [ $do_openmp = "yes" ]; then @@ -381,7 +380,6 @@ function configure_llvmCore() { esac project_list=${projects// /;} - runtime_list=${runtimes// /;} echo "# Using C compiler: $c_compiler" echo "# Using C++ compiler: $cxx_compiler" @@ -394,7 +392,6 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ - -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log env CC="$c_compiler" CXX="$cxx_compiler" \ @@ -403,7 +400,6 @@ function configure_llvmCore() { -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ -DLLVM_ENABLE_PROJECTS="$project_list" \ -DLLVM_LIT_ARGS="-j $NumJobs" \ - -DLLVM_ENABLE_RUNTIMES="$runtime_list" \ $ExtraConfigureFlags $BuildDir/llvm-project/llvm \ 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log From ac3398a0b0035f15948ca605ee1884585bad04c0 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 11 Mar 2022 10:14:45 -0800 Subject: [PATCH 245/316] Revert "[CMake] Include runtimes test suites in check-all" This reverts commit e54a7bf0c0f14115ec3bd7738850ee83f8428319. There was a bug reported with this patch, see: https://reviews.llvm.org/D121276#3375464 --- llvm/CMakeLists.txt | 3 +++ llvm/runtimes/CMakeLists.txt | 15 +-------------- runtimes/CMakeLists.txt | 10 ---------- runtimes/Tests.cmake.in | 3 --- 4 files changed, 4 insertions(+), 27 deletions(-) delete mode 100644 runtimes/Tests.cmake.in diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 123998df34c84..00d01f4ddbbd2 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -1138,6 +1138,9 @@ if( LLVM_INCLUDE_TESTS ) DEPENDS ${LLVM_LIT_DEPENDS} ${LLVM_ADDITIONAL_TEST_TARGETS} ARGS ${LLVM_LIT_EXTRA_ARGS} ) + if(TARGET check-runtimes) + add_dependencies(check-all check-runtimes) + endif() add_custom_target(test-depends DEPENDS ${LLVM_LIT_DEPENDS} ${LLVM_ADDITIONAL_TEST_DEPENDS}) set_target_properties(test-depends PROPERTIES FOLDER "Tests") diff --git a/llvm/runtimes/CMakeLists.txt b/llvm/runtimes/CMakeLists.txt index d7918c211e40e..05567b5234eea 100644 --- a/llvm/runtimes/CMakeLists.txt +++ b/llvm/runtimes/CMakeLists.txt @@ -220,13 +220,6 @@ function(runtime_default_target) endforeach() if(LLVM_INCLUDE_TESTS) - include(${LLVM_BINARY_DIR}/runtimes/Tests.cmake OPTIONAL RESULT_VARIABLE have_tests) - set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${LLVM_BINARY_DIR}/runtimes/Tests.cmake) - if(have_tests) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_TESTSUITES ${RUNTIMES_LIT_TESTSUITES}) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_PARAMS ${RUNTIMES_LIT_PARAMS}) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_EXTRA_ARGS ${RUNTIMES_LIT_EXTRA_ARGS}) - endif() list(APPEND test_targets runtimes-test-depends check-runtimes) endif() @@ -303,13 +296,6 @@ function(runtime_register_target name target) endforeach() if(LLVM_INCLUDE_TESTS) - include(${LLVM_BINARY_DIR}/runtimes/${name}/Tests.cmake OPTIONAL RESULT_VARIABLE have_tests) - set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${LLVM_BINARY_DIR}/runtimes/${name}/Tests.cmake) - if(have_tests) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_TESTSUITES ${RUNTIMES_LIT_TESTSUITES}) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_PARAMS ${RUNTIMES_LIT_PARAMS}) - set_property(GLOBAL APPEND PROPERTY LLVM_LIT_EXTRA_ARGS ${RUNTIMES_LIT_EXTRA_ARGS}) - endif() set(runtimes-test-depends-${name} runtimes-test-depends) set(check-runtimes-${name} check-runtimes) list(APPEND ${name}_test_targets runtimes-test-depends-${name} check-runtimes-${name}) @@ -482,6 +468,7 @@ if(runtimes) if(LLVM_INCLUDE_TESTS) set_property(GLOBAL APPEND PROPERTY LLVM_ADDITIONAL_TEST_DEPENDS runtimes-test-depends) + set_property(GLOBAL APPEND PROPERTY LLVM_ADDITIONAL_TEST_TARGETS check-runtimes) set(RUNTIMES_TEST_DEPENDS FileCheck diff --git a/runtimes/CMakeLists.txt b/runtimes/CMakeLists.txt index 945d3de9ec44b..1400233b73f6d 100644 --- a/runtimes/CMakeLists.txt +++ b/runtimes/CMakeLists.txt @@ -221,16 +221,6 @@ if(LLVM_INCLUDE_TESTS) add_subdirectory(${LLVM_MAIN_SRC_DIR}/utils/llvm-lit ${CMAKE_CURRENT_BINARY_DIR}/llvm-lit) endif() - - if(LLVM_RUNTIMES_TARGET) - configure_file( - ${CMAKE_CURRENT_SOURCE_DIR}/Tests.cmake.in - ${LLVM_BINARY_DIR}/runtimes/${LLVM_RUNTIMES_TARGET}/Tests.cmake) - else() - configure_file( - ${CMAKE_CURRENT_SOURCE_DIR}/Tests.cmake.in - ${LLVM_BINARY_DIR}/runtimes/Tests.cmake) - endif() endif() get_property(SUB_COMPONENTS GLOBAL PROPERTY SUB_COMPONENTS) diff --git a/runtimes/Tests.cmake.in b/runtimes/Tests.cmake.in deleted file mode 100644 index 4df40f237b3f5..0000000000000 --- a/runtimes/Tests.cmake.in +++ /dev/null @@ -1,3 +0,0 @@ -set(RUNTIMES_LIT_TESTSUITES @RUNTIMES_LIT_TESTSUITES@) -set(RUNTIMES_LIT_PARAMS @RUNTIMES_LIT_PARAMS@) -set(RUNTIMES_LIT_EXTRA_ARGS @RUNTIMES_LIT_EXTRA_ARGS@) From 69ba522c58d0cf43097a08087b1b31d6edb46706 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 4 Feb 2022 16:14:13 -0800 Subject: [PATCH 246/316] [Hexagon] Fix crash with shuffle_vector of v128f16 (cherry picked from commit 7403c02f06d4c405215aa97452f1af18dfc02dc0) --- .../Target/Hexagon/HexagonISelLoweringHVX.cpp | 8 +-- .../test/CodeGen/Hexagon/vector-sint-to-fp.ll | 51 +++++++++++++++++++ 2 files changed, 55 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 0ba75a544c048..14b4f7c56c57b 100755 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -118,9 +118,10 @@ HexagonTargetLowering::initializeHVXLowering() { setOperationAction(ISD::SPLAT_VECTOR, MVT::v32f32, Legal); // Vector shuffle is always promoted to ByteV and a bitcast to f16 is // generated. - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); // Custom-lower BUILD_VECTOR for vector pairs. The standard (target- // independent) handling of it would convert it to a load, which is @@ -780,7 +781,6 @@ HexagonTargetLowering::buildHvxVectorReg(ArrayRef Values, SDValue N = HalfV0; SDValue M = HalfV1; for (unsigned i = 0; i != NumWords/2; ++i) { - // Rotate by element count since last insertion. if (Words[i] != Words[n] || VecHist[n] <= 1) { Sn = DAG.getConstant(Rn, dl, MVT::i32); diff --git a/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll new file mode 100644 index 0000000000000..726ee8f061714 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Test that code is generated for the vector sint_to_fp node. The compiler +; asserts with a cannot select message if the node is not expanded. When +; expanded, the generated code is very inefficient, so iwe need to find a more +; efficient code sequence to generate. + +; CHECK: convert_w2sf +; CHECK: call floorf + +target triple = "hexagon" + +define dllexport void @f0() #0 { +b0: + br label %b1 + +b1: ; preds = %b1, %b0 + %v0 = phi i32 [ 0, %b0 ], [ %v17, %b1 ] + %v1 = mul nsw i32 %v0, 2 + %v2 = add nsw i32 undef, %v1 + %v3 = insertelement <64 x i32> undef, i32 %v2, i32 0 + %v4 = shufflevector <64 x i32> %v3, <64 x i32> undef, <64 x i32> zeroinitializer + %v5 = add nsw <64 x i32> %v4, + %v6 = sitofp <64 x i32> %v5 to <64 x float> + %v7 = fmul <64 x float> %v6, + %v8 = fsub <64 x float> %v7, zeroinitializer + %v9 = call <64 x float> @llvm.floor.v64f32(<64 x float> %v8) + %v10 = fsub <64 x float> zeroinitializer, %v9 + %v11 = fptrunc <64 x float> %v10 to <64 x half> + %v12 = call <64 x half> @llvm.fmuladd.v64f16(<64 x half> %v11, <64 x half> zeroinitializer, <64 x half> zeroinitializer) + %v13 = fsub <64 x half> %v12, zeroinitializer + %v14 = call <64 x half> @llvm.fmuladd.v64f16(<64 x half> zeroinitializer, <64 x half> %v13, <64 x half> zeroinitializer) + %v15 = shufflevector <64 x half> %v14, <64 x half> undef, <128 x i32> + %v16 = shufflevector <128 x half> %v15, <128 x half> undef, <64 x i32> + call void @llvm.masked.store.v64f16.p0v64f16(<64 x half> %v16, <64 x half>* undef, i32 64, <64 x i1> ) + %v17 = add nsw i32 %v0, 1 + br label %b1 +} + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare <64 x float> @llvm.floor.v64f32(<64 x float>) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare <64 x half> @llvm.fmuladd.v64f16(<64 x half>, <64 x half>, <64 x half>) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly +declare void @llvm.masked.store.v64f16.p0v64f16(<64 x half>, <64 x half>*, i32 immarg, <64 x i1>) #2 + +attributes #0 = { "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" } +attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } +attributes #2 = { argmemonly nofree nosync nounwind willreturn writeonly } From 329fda39c507e8740978d10458451dcdb21563be Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Mon, 14 Mar 2022 09:44:33 +0000 Subject: [PATCH 247/316] NFC: Mention auto-vec support for SVE in release notes. --- llvm/docs/ReleaseNotes.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index e8934f79181a7..b2d8d8c2640e2 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -82,6 +82,7 @@ Changes to the AArch64 Backend "tune-cpu" attribute is absent it tunes according to the "target-cpu". * Fixed relocations against temporary symbols (e.g. in jump tables and constant pools) in large COFF object files. +* Auto-vectorization now targets SVE by default when available. Changes to the ARM Backend -------------------------- From add3ab7f4c8a7f25c2940889d397cbdc9f267666 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Mon, 14 Mar 2022 11:50:02 -0400 Subject: [PATCH 248/316] [libc++] Add workaround to avoid breaking users of when are disabled Back in 3a208c68942e, we implemented the range-based constructor for . However, in doing so, we removed a previous non-standard constructor that we provided before shipping . Unfortunately, that breaks code that was relying on a range-based constructor until we ship all of . This patch reintroduces the old non-conforming constructors and tests that were removed in 3a208c68942e and uses them whenever is not provided (e.g. in LLVM 14). This is only a temporary workaround until we enable by default in C++20, which should hopefully happen by LLVM 15. The goal is to cherry-pick this workaround back to the LLVM 14 release branch, since I suspect the constructor removal may otherwise cause breakage out there, like the breakage I saw internally. We could have avoided this situation by waiting for C++20 to be finalized before shipping std::span. For example, we could have guarded it with something like _LIBCPP_HAS_NO_INCOMPLETE_RANGES to prevent users from accidentally starting to depend on it before it is stable. We did not have these mechanisms when std::span was first implemented, though. NOTE: This is a pretty modified version of d4c39f1ab94 since that one didn't apply properly onto the release/14.x branch. (cherry picked from commit d4c39f1ab94abc1dd4fff1e82dd4fa97265940e1) Differential Revision: https://reviews.llvm.org/D121739 --- libcxx/include/span | 50 ++++++- .../containers/views/span.cons/range.pass.cpp | 141 ++++++++++++++++++ .../views/span.cons/range.verify.cpp | 118 +++++++++++++++ 3 files changed, 306 insertions(+), 3 deletions(-) create mode 100644 libcxx/test/libcxx/containers/views/span.cons/range.pass.cpp create mode 100644 libcxx/test/libcxx/containers/views/span.cons/range.verify.cpp diff --git a/libcxx/include/span b/libcxx/include/span index fd95ecca17f7b..b8dbc7e01fd61 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -170,7 +170,25 @@ struct __is_std_span : false_type {}; template struct __is_std_span> : true_type {}; -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +#if defined(_LIBCPP_HAS_NO_CONCEPTS) || defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +// This is a temporary workaround until we ship -- we've unfortunately been +// shipping before its API was finalized, and we used to provide a constructor +// from container types that had the requirements below. To avoid breaking code that +// has started relying on the range-based constructor until we ship all of , +// we emulate the constructor requirements like this. +template +struct __span_compatible_range : false_type { }; + +template +struct __span_compatible_range<_Range, _ElementType, void_t< + enable_if_t>::value>, + enable_if_t>::value>, + enable_if_t>>, + decltype(data(declval<_Range>())), + decltype(size(declval<_Range>())), + enable_if_t()))>(*)[], _ElementType(*)[]>> +>> : true_type { }; +#else template concept __span_compatible_range = ranges::contiguous_range<_Range> && @@ -248,7 +266,22 @@ public: _LIBCPP_INLINE_VISIBILITY constexpr span(const array<_OtherElementType, _Extent>& __arr) noexcept : __data{__arr.data()} {} -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +#if defined(_LIBCPP_HAS_NO_CONCEPTS) || defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + template ::value + >> + _LIBCPP_INLINE_VISIBILITY + constexpr explicit span(_Container& __c) : __data{std::data(__c)} { + _LIBCPP_ASSERT(std::size(__c) == _Extent, "size mismatch in span's constructor (range)"); + } + template ::value + >> + _LIBCPP_INLINE_VISIBILITY + constexpr explicit span(const _Container& __c) : __data{std::data(__c)} { + _LIBCPP_ASSERT(std::size(__c) == _Extent, "size mismatch in span's constructor (range)"); + } +#else template <__span_compatible_range _Range> _LIBCPP_INLINE_VISIBILITY constexpr explicit span(_Range&& __r) : __data{ranges::data(__r)} { @@ -434,7 +467,18 @@ public: _LIBCPP_INLINE_VISIBILITY constexpr span(const array<_OtherElementType, _Sz>& __arr) noexcept : __data{__arr.data()}, __size{_Sz} {} -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +#if defined(_LIBCPP_HAS_NO_CONCEPTS) || defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + template ::value + >> + _LIBCPP_INLINE_VISIBILITY + constexpr span(_Container& __c) : __data(std::data(__c)), __size{std::size(__c)} {} + template ::value + >> + _LIBCPP_INLINE_VISIBILITY + constexpr span(const _Container& __c) : __data(std::data(__c)), __size{std::size(__c)} {} +#else template <__span_compatible_range _Range> _LIBCPP_INLINE_VISIBILITY constexpr span(_Range&& __r) : __data(ranges::data(__r)), __size{ranges::size(__r)} {} diff --git a/libcxx/test/libcxx/containers/views/span.cons/range.pass.cpp b/libcxx/test/libcxx/containers/views/span.cons/range.pass.cpp new file mode 100644 index 0000000000000..efa1001bdb5b8 --- /dev/null +++ b/libcxx/test/libcxx/containers/views/span.cons/range.pass.cpp @@ -0,0 +1,141 @@ +//===---------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +// + +// template +// constexpr explicit(Extent != dynamic_extent) span(Container&); +// template +// constexpr explicit(Extent != dynamic_extent) span(Container const&); + +// This test checks for libc++'s non-conforming temporary extension to std::span +// to support construction from containers that look like contiguous ranges. +// +// This extension is only supported when we don't ship , and we can +// remove it once we get rid of _LIBCPP_HAS_NO_INCOMPLETE_RANGES. + +#include +#include +#include +#include + +#include "test_macros.h" + +// Look ma - I'm a container! +template +struct IsAContainer { + constexpr IsAContainer() : v_{} {} + constexpr size_t size() const {return 1;} + constexpr T *data() {return &v_;} + constexpr const T *data() const {return &v_;} + constexpr T *begin() {return &v_;} + constexpr const T *begin() const {return &v_;} + constexpr T *end() {return &v_ + 1;} + constexpr const T *end() const {return &v_ + 1;} + + constexpr T const *getV() const {return &v_;} // for checking + T v_; +}; + + +void checkCV() +{ + std::vector v = {1,2,3}; + +// Types the same + { + std::span< int> s1{v}; // a span< int> pointing at int. + } + +// types different + { + std::span s1{v}; // a span pointing at int. + std::span< volatile int> s2{v}; // a span< volatile int> pointing at int. + std::span< volatile int> s3{v}; // a span< volatile int> pointing at const int. + std::span s4{v}; // a span pointing at int. + } + +// Constructing a const view from a temporary + { + std::span s1{IsAContainer()}; + std::span s3{std::vector()}; + (void) s1; + (void) s3; + } +} + + +template +constexpr bool testConstexprSpan() +{ + constexpr IsAContainer val{}; + std::span s1{val}; + return s1.data() == val.getV() && s1.size() == 1; +} + +template +constexpr bool testConstexprSpanStatic() +{ + constexpr IsAContainer val{}; + std::span s1{val}; + return s1.data() == val.getV() && s1.size() == 1; +} + +template +void testRuntimeSpan() +{ + IsAContainer val{}; + const IsAContainer cVal; + std::span s1{val}; + std::span s2{cVal}; + assert(s1.data() == val.getV() && s1.size() == 1); + assert(s2.data() == cVal.getV() && s2.size() == 1); +} + +template +void testRuntimeSpanStatic() +{ + IsAContainer val{}; + const IsAContainer cVal; + std::span s1{val}; + std::span s2{cVal}; + assert(s1.data() == val.getV() && s1.size() == 1); + assert(s2.data() == cVal.getV() && s2.size() == 1); +} + +struct A{}; + +int main(int, char**) +{ + static_assert(testConstexprSpan(), ""); + static_assert(testConstexprSpan(), ""); + static_assert(testConstexprSpan(), ""); + static_assert(testConstexprSpan(), ""); + + static_assert(testConstexprSpanStatic(), ""); + static_assert(testConstexprSpanStatic(), ""); + static_assert(testConstexprSpanStatic(), ""); + static_assert(testConstexprSpanStatic(), ""); + + testRuntimeSpan(); + testRuntimeSpan(); + testRuntimeSpan(); + testRuntimeSpan(); + testRuntimeSpan(); + + testRuntimeSpanStatic(); + testRuntimeSpanStatic(); + testRuntimeSpanStatic(); + testRuntimeSpanStatic(); + testRuntimeSpanStatic(); + + checkCV(); + + return 0; +} diff --git a/libcxx/test/libcxx/containers/views/span.cons/range.verify.cpp b/libcxx/test/libcxx/containers/views/span.cons/range.verify.cpp new file mode 100644 index 0000000000000..f0edf4f935367 --- /dev/null +++ b/libcxx/test/libcxx/containers/views/span.cons/range.verify.cpp @@ -0,0 +1,118 @@ +//===---------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +// + +// template +// constexpr explicit(Extent != dynamic_extent) span(Container&); +// template +// constexpr explicit(Extent != dynamic_extent) span(Container const&); + +// This test checks for libc++'s non-conforming temporary extension to std::span +// to support construction from containers that look like contiguous ranges. +// +// This extension is only supported when we don't ship , and we can +// remove it once we get rid of _LIBCPP_HAS_NO_INCOMPLETE_RANGES. + +#include +#include +#include +#include +#include +#include + +#include "test_macros.h" + +// Look ma - I'm a container! +template +struct IsAContainer { + constexpr IsAContainer() : v_{} {} + constexpr size_t size() const {return 1;} + constexpr T *data() {return &v_;} + constexpr const T *data() const {return &v_;} + + constexpr const T *getV() const {return &v_;} // for checking + T v_; +}; + +template +struct NotAContainerNoData { + size_t size() const {return 0;} +}; + +template +struct NotAContainerNoSize { + const T *data() const {return nullptr;} +}; + +template +struct NotAContainerPrivate { +private: + size_t size() const {return 0;} + const T *data() const {return nullptr;} +}; + +template +std::span createImplicitSpan(container c) { + return {c}; // expected-error {{chosen constructor is explicit in copy-initialization}} +} + +int main(int, char**) +{ + +// Making non-const spans from const sources (a temporary binds to `const &`) + { + std::span s1{IsAContainer()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s3{std::vector()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + } + +// Missing size and/or data + { + std::span s1{NotAContainerNoData()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s3{NotAContainerNoSize()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s5{NotAContainerPrivate()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + +// Again with the standard containers + std::span s11{std::deque()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s13{std::list()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s15{std::forward_list()}; // expected-error {{no matching constructor for initialization of 'std::span'}} + } + +// Not the same type + { + IsAContainer c; + std::span s1{c}; // expected-error {{no matching constructor for initialization of 'std::span'}} + } + +// CV wrong + { + IsAContainer c; + IsAContainer cv; + IsAContainer< volatile int> v; + + std::span< int> s1{c}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span< int> s2{v}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span< int> s3{cv}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s4{v}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span s5{cv}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span< volatile int> s6{c}; // expected-error {{no matching constructor for initialization of 'std::span'}} + std::span< volatile int> s7{cv}; // expected-error {{no matching constructor for initialization of 'std::span'}} + } + +// explicit constructor necessary + { + IsAContainer c; + const IsAContainer cc; + + createImplicitSpan(c); + createImplicitSpan(cc); + } + + return 0; +} From 3f43d803382d57e3fc010ca19833077d1023e9c9 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Mon, 21 Mar 2022 17:05:06 -0400 Subject: [PATCH 249/316] [libc++] Re-enable workaround for pre-ranges CTAD in std::span See https://reviews.llvm.org/D121626 for details -- this re-enables the CTAD we removed, since it does break some stuff as well (even though it's not nearly as bad as the removed constructors fixed by D121626). (cherry picked from commit 6a7f0551178e966a686dd48dfa2ea045a35addef) Differential Revision: https://reviews.llvm.org/D122201 --- libcxx/include/span | 8 +++++++- .../test/std/containers/views/span.cons/deduct.pass.cpp | 6 ------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/libcxx/include/span b/libcxx/include/span index b8dbc7e01fd61..f33569031730a 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -622,7 +622,13 @@ template template span(const array<_Tp, _Sz>&) -> span; -#if !defined(_LIBCPP_HAS_NO_CONCEPTS) && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +#if defined(_LIBCPP_HAS_NO_CONCEPTS) || defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) +template + span(_Container&) -> span; + +template + span(const _Container&) -> span; +#else template span(_Range&&) -> span>>; #endif diff --git a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp index 81632fed711d3..e632feca2e1f1 100644 --- a/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp +++ b/libcxx/test/std/containers/views/span.cons/deduct.pass.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14, c++17 -// UNSUPPORTED: libcpp-no-concepts // @@ -86,7 +85,6 @@ void test_std_array() { } } -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES void test_range_std_container() { { std::string str{"ABCDE"}; @@ -104,17 +102,13 @@ void test_range_std_container() { assert(s.data() == str.data()); } } -#endif // _LIBCPP_HAS_NO_INCOMPLETE_RANGES int main(int, char**) { test_iterator_sentinel(); test_c_array(); test_std_array(); - -#ifndef _LIBCPP_HAS_NO_INCOMPLETE_RANGES test_range_std_container(); -#endif // _LIBCPP_HAS_NO_INCOMPLETE_RANGES return 0; } From bd8dc965cff14115415f18d7dc8922f806f7a93a Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 28 Mar 2022 23:48:47 -0700 Subject: [PATCH 250/316] Bump version to 14.0.1 --- libcxx/CMakeLists.txt | 2 +- libcxxabi/CMakeLists.txt | 2 +- libunwind/CMakeLists.txt | 2 +- llvm/CMakeLists.txt | 2 +- llvm/utils/gn/secondary/llvm/version.gni | 2 +- llvm/utils/lit/lit/__init__.py | 2 +- llvm/utils/release/build_llvm_package.bat | 4 ++-- .../llvm/include/llvm/Config/llvm-config.h | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 35c2ce515dd19..8cd86ddfc5cbf 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -32,7 +32,7 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBCXX_STANDALONE_BUIL project(libcxx CXX C) set(PACKAGE_NAME libcxx) - set(PACKAGE_VERSION 14.0.0git) + set(PACKAGE_VERSION 14.0.1) set(PACKAGE_STRING "${PACKAGE_NAME} ${PACKAGE_VERSION}") set(PACKAGE_BUGREPORT "llvm-bugs@lists.llvm.org") diff --git a/libcxxabi/CMakeLists.txt b/libcxxabi/CMakeLists.txt index 8e8cdf8ad737b..5ef85c9cfc408 100644 --- a/libcxxabi/CMakeLists.txt +++ b/libcxxabi/CMakeLists.txt @@ -34,7 +34,7 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBCXXABI_STANDALONE_B project(libcxxabi CXX C) set(PACKAGE_NAME libcxxabi) - set(PACKAGE_VERSION 11.0.0git) + set(PACKAGE_VERSION 14.0.1) set(PACKAGE_STRING "${PACKAGE_NAME} ${PACKAGE_VERSION}") set(PACKAGE_BUGREPORT "llvm-bugs@lists.llvm.org") diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index 6523fb0d307df..660bbadb29073 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -33,7 +33,7 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR OR LIBUNWIND_STANDALONE_B project(libunwind LANGUAGES NONE) set(PACKAGE_NAME libunwind) - set(PACKAGE_VERSION 14.0.0git) + set(PACKAGE_VERSION 14.0.1) set(PACKAGE_STRING "${PACKAGE_NAME} ${PACKAGE_VERSION}") set(PACKAGE_BUGREPORT "llvm-bugs@lists.llvm.org") diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 00d01f4ddbbd2..f8a25354978b5 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -17,7 +17,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 0) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 0) + set(LLVM_VERSION_PATCH 1) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX) diff --git a/llvm/utils/gn/secondary/llvm/version.gni b/llvm/utils/gn/secondary/llvm/version.gni index 458db94e6986f..4ff580a602377 100644 --- a/llvm/utils/gn/secondary/llvm/version.gni +++ b/llvm/utils/gn/secondary/llvm/version.gni @@ -1,4 +1,4 @@ llvm_version_major = 14 llvm_version_minor = 0 -llvm_version_patch = 0 +llvm_version_patch = 1 llvm_version = "$llvm_version_major.$llvm_version_minor.$llvm_version_patch" diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py index 570cd7405292d..627586b698aa9 100644 --- a/llvm/utils/lit/lit/__init__.py +++ b/llvm/utils/lit/lit/__init__.py @@ -2,7 +2,7 @@ __author__ = 'Daniel Dunbar' __email__ = 'daniel@minormatter.com' -__versioninfo__ = (14, 0, 0) +__versioninfo__ = (14, 0, 1) __version__ = '.'.join(str(v) for v in __versioninfo__) + 'dev' __all__ = [] diff --git a/llvm/utils/release/build_llvm_package.bat b/llvm/utils/release/build_llvm_package.bat index 4c3f48e0c48b5..32f7fae60c7bb 100755 --- a/llvm/utils/release/build_llvm_package.bat +++ b/llvm/utils/release/build_llvm_package.bat @@ -27,8 +27,8 @@ set python64_dir=C:\Users\%USERNAME%\AppData\Local\Programs\Python\Python36 for /f "usebackq" %%i in (`PowerShell ^(Get-Date^).ToString^('yyyyMMdd'^)`) do set datestamp=%%i set revision=%1 -set package_version=14.0.0-%revision:~0,8% -set clang_format_vs_version=14.0.0.%datestamp% +set package_version=14.0.1-%revision:~0,8% +set clang_format_vs_version=14.0.1.%datestamp% set build_dir=llvm_package_%revision:~0,8% echo Revision: %revision% diff --git a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h index 5aeceb4ac1cca..e4254177af02f 100644 --- a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h +++ b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/llvm-config.h @@ -83,7 +83,7 @@ #define LLVM_VERSION_PATCH 0 /* LLVM version string */ -#define LLVM_VERSION_STRING "14.0.0git" +#define LLVM_VERSION_STRING "14.0.1" /* Whether LLVM records statistics for use with GetStatistics(), * PrintStatistics() or PrintStatisticsJSON() From 0547ffef5d39c864715ba02f8f6d031f71583682 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 30 Mar 2022 23:51:27 -0700 Subject: [PATCH 251/316] workflows: Consolidate tests to reduce the number of build jobs Merge the llvm, clang, and libclc tests into a single job. This is the most sub-projects we can test at once without running out of disk space on the GitHub runners. Reviewed By: thieta Differential Revision: https://reviews.llvm.org/D120872 --- .github/workflows/clang-tests.yml | 38 ++++----------- .github/workflows/libclc-tests.yml | 51 +++++-------------- .github/workflows/lld-tests.yml | 38 ++++----------- .github/workflows/lldb-tests.yml | 45 +++++------------ .github/workflows/llvm-project-tests.yml | 62 ++++++++++++++++++++++++ .github/workflows/llvm-tests.yml | 49 +++++++++---------- 6 files changed, 129 insertions(+), 154 deletions(-) create mode 100644 .github/workflows/llvm-project-tests.yml diff --git a/.github/workflows/clang-tests.yml b/.github/workflows/clang-tests.yml index 71783e8ba8484..1ae93ab5d610b 100644 --- a/.github/workflows/clang-tests.yml +++ b/.github/workflows/clang-tests.yml @@ -6,13 +6,15 @@ on: - 'release/**' paths: - 'clang/**' - - 'llvm/**' - '.github/workflows/clang-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' pull_request: paths: - 'clang/**' - - 'llvm/**' - '.github/workflows/clang-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' concurrency: # Skip intermediate builds: always. @@ -21,29 +23,9 @@ concurrency: cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} jobs: - build_clang: - name: clang check-all - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: - - ubuntu-latest - - windows-latest - - macOS-latest - steps: - - name: Setup Windows - if: startsWith(matrix.os, 'windows') - uses: llvm/actions/setup-windows@main - with: - arch: amd64 - - name: Install Ninja - uses: llvm/actions/install-ninja@main - - uses: actions/checkout@v1 - with: - fetch-depth: 250 - - name: Test clang - uses: llvm/actions/build-test-llvm-project@main - with: - cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release - build_target: check-clang + check_clang: + name: Test clang,lldb,libclc + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: check-clang + projects: clang;lldb;libclc diff --git a/.github/workflows/libclc-tests.yml b/.github/workflows/libclc-tests.yml index d4dbbc6bc6a02..4334b3dd23d69 100644 --- a/.github/workflows/libclc-tests.yml +++ b/.github/workflows/libclc-tests.yml @@ -5,16 +5,18 @@ on: branches: - 'release/**' paths: - - 'clang/**' - - 'llvm/**' - 'libclc/**' - '.github/workflows/libclc-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!clang/**' + - '!llvm/**' pull_request: paths: - - 'clang/**' - - 'llvm/**' - 'libclc/**' - '.github/workflows/libclc-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!clang/**' + - '!llvm/**' concurrency: # Skip intermediate builds: always. @@ -22,39 +24,10 @@ concurrency: group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} - jobs: - build_libclc: - name: libclc test - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: - - ubuntu-latest - # Disable build on windows, because I can't figure out where llvm-config is. - #- windows-latest - - macOS-latest - steps: - - name: Setup Windows - if: startsWith(matrix.os, 'windows') - uses: llvm/actions/setup-windows@main - with: - arch: amd64 - - name: Install Ninja - uses: llvm/actions/install-ninja@main - - uses: actions/checkout@v1 - with: - fetch-depth: 250 - - name: Build clang - uses: llvm/actions/build-test-llvm-project@main - with: - cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang" -DCMAKE_BUILD_TYPE=Release - build_target: "" - - name: Build and test libclc - # spirv targets require llvm-spirv, so skip building them until we figure out - # how to install this tool. - run: | - cmake -G Ninja -S libclc -B libclc-build -DLLVM_CONFIG=`pwd`/build/bin/llvm-config -DLIBCLC_TARGETS_TO_BUILD="amdgcn--;amdgcn--amdhsa;r600--;nvptx--;nvptx64--;nvptx--nvidiacl;nvptx64--nvidiacl" - ninja -C libclc-build - ninja -C libclc-build test + check_libclc: + name: Test libclc + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: '' + projects: clang;libclc diff --git a/.github/workflows/lld-tests.yml b/.github/workflows/lld-tests.yml index 5cbcfcf515abb..720983e14caee 100644 --- a/.github/workflows/lld-tests.yml +++ b/.github/workflows/lld-tests.yml @@ -6,13 +6,15 @@ on: - 'release/**' paths: - 'lld/**' - - 'llvm/**' - '.github/workflows/lld-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' pull_request: paths: - 'lld/**' - - 'llvm/**' - '.github/workflows/lld-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!llvm/**' concurrency: # Skip intermediate builds: always. @@ -21,29 +23,9 @@ concurrency: cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} jobs: - build_lld: - name: lld check-all - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: - - ubuntu-latest - - windows-latest - - macOS-latest - steps: - - name: Setup Windows - if: startsWith(matrix.os, 'windows') - uses: llvm/actions/setup-windows@main - with: - arch: amd64 - - name: Install Ninja - uses: llvm/actions/install-ninja@main - - uses: actions/checkout@v1 - with: - fetch-depth: 250 - - name: Test lld - uses: llvm/actions/build-test-llvm-project@main - with: - cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="lld" -DCMAKE_BUILD_TYPE=Release - build_target: check-lld + check_lld: + name: Test lld + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: check-lld + projects: lld diff --git a/.github/workflows/lldb-tests.yml b/.github/workflows/lldb-tests.yml index 761a5788ac99f..f6792b58b0504 100644 --- a/.github/workflows/lldb-tests.yml +++ b/.github/workflows/lldb-tests.yml @@ -5,16 +5,18 @@ on: branches: - 'release/**' paths: - - 'clang/**' - - 'llvm/**' - 'lldb/**' - '.github/workflows/lldb-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!clang/**' + - '!llvm/**' pull_request: paths: - - 'clang/**' - - 'llvm/**' - 'lldb/**' - '.github/workflows/lldb-tests.yml' + - '.github/workflows/llvm-project-tests.yml' + - '!clang/**' + - '!llvm/**' concurrency: # Skip intermediate builds: always. @@ -25,33 +27,8 @@ concurrency: jobs: build_lldb: - name: lldb build - runs-on: ${{ matrix.os }} - # Workaround for build faliure on Mac OS X: llvm.org/PR46190, https://github.com/actions/virtual-environments/issues/2274 - env: - CPLUS_INCLUDE_PATH: /usr/local/opt/llvm/include/c++/v1:/Library/Developer/CommandLineTools/SDKs/MacOSX10.15.sdk/usr/include - strategy: - fail-fast: false - matrix: - os: - - ubuntu-latest - - windows-latest - - macOS-10.15 - steps: - - name: Setup Windows - if: startsWith(matrix.os, 'windows') - uses: llvm/actions/setup-windows@main - with: - arch: amd64 - - name: Install Ninja - uses: llvm/actions/install-ninja@main - - uses: actions/checkout@v1 - with: - fetch-depth: 250 - - name: Build lldb - uses: llvm/actions/build-test-llvm-project@main - with: - # Mac OS requries that libcxx is enabled for lldb tests, so we need to disable them. - cmake_args: -G Ninja -DLLVM_ENABLE_PROJECTS="clang;lldb" -DCMAKE_BUILD_TYPE=Release -DLLDB_INCLUDE_TESTS=OFF - # check-lldb is not consistent, so we only build lldb. - build_target: "" + name: Build lldb + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: '' + projects: clang;lldb diff --git a/.github/workflows/llvm-project-tests.yml b/.github/workflows/llvm-project-tests.yml new file mode 100644 index 0000000000000..1f2b67fd24f8e --- /dev/null +++ b/.github/workflows/llvm-project-tests.yml @@ -0,0 +1,62 @@ +name: LLVM Project Tests + +on: + workflow_call: + inputs: + build_target: + required: true + type: string + + projects: + required: true + type: string + +concurrency: + # Skip intermediate builds: always. + # Cancel intermediate builds: only if it is a pull request build. + # If the group name here is the same as the group name in the workflow that includes + # this one, then the action will try to wait on itself and get stuck. + group: llvm-project-${{ github.workflow }}-${{ inputs.projects}}${{ github.ref }} + cancel-in-progress: ${{ startsWith(github.ref, 'refs/pull/') }} + +env: + # Workaround for build faliure on Mac OS X: llvm.org/PR46190, https://github.com/actions/virtual-environments/issues/2274 + CPLUS_INCLUDE_PATH: /usr/local/opt/llvm/include/c++/v1:/Library/Developer/CommandLineTools/SDKs/MacOSX10.15.sdk/usr/include + +jobs: + lit-tests: + name: Lit Tests + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: + - ubuntu-latest + - windows-latest + # Use a specific version of macOS to ensure the CPLUS_INCLUDE_PATH workaround works. + - macOS-10.15 + steps: + - name: Setup Windows + if: startsWith(matrix.os, 'windows') + uses: llvm/actions/setup-windows@main + with: + arch: amd64 + - name: Install Ninja + uses: llvm/actions/install-ninja@main + - uses: actions/checkout@v1 + with: + fetch-depth: 250 + - name: Build and Test + uses: llvm/actions/build-test-llvm-project@main + with: + cmake_args: '-GNinja -DLLVM_ENABLE_PROJECTS="${{ inputs.projects }}" -DCMAKE_BUILD_TYPE=Release -DLLDB_INCLUDE_TESTS=OFF' + build_target: '${{ inputs.build_target }}' + + - name: Build and Test libclc + if: "!startsWith(matrix.os, 'windows') && contains(inputs.projects, 'libclc')" + run: | + # Make sure all of LLVM libraries that llvm-config needs are built. + ninja -C build + cmake -G Ninja -S libclc -B libclc-build -DLLVM_CONFIG=`pwd`/build/bin/llvm-config -DLIBCLC_TARGETS_TO_BUILD="amdgcn--;amdgcn--amdhsa;r600--;nvptx--;nvptx64--;nvptx--nvidiacl;nvptx64--nvidiacl" + ninja -C libclc-build + ninja -C libclc-build test diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml index 2fc44e9599367..8347352f359e3 100644 --- a/.github/workflows/llvm-tests.yml +++ b/.github/workflows/llvm-tests.yml @@ -7,10 +7,12 @@ on: paths: - 'llvm/**' - '.github/workflows/llvm-tests.yml' + - '.github/workflows/llvm-project-tests.yml' pull_request: paths: - 'llvm/**' - '.github/workflows/llvm-tests.yml' + - '.github/workflows/llvm-project-tests.yml' concurrency: # Skip intermediate builds: always. @@ -20,31 +22,28 @@ concurrency: jobs: - build_llvm: - name: llvm check-all - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: - - ubuntu-latest - - windows-latest - - macOS-latest - steps: - - name: Setup Windows - if: startsWith(matrix.os, 'windows') - uses: llvm/actions/setup-windows@main - with: - arch: amd64 - - name: Install Ninja - uses: llvm/actions/install-ninja@main - - uses: actions/checkout@v1 - with: - fetch-depth: 250 - - name: Test llvm - uses: llvm/actions/build-test-llvm-project@main - with: - cmake_args: -G Ninja -DCMAKE_BUILD_TYPE=Release + check_all: + name: Test llvm,clang,libclc + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: check-all + projects: clang;libclc + + # These need to be separate from the check_all job, becuase there is not enough disk + # space to build all these projects on Windows. + build_lldb: + name: Build lldb + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: '' + projects: clang;lldb + + check_lld: + name: Test lld + uses: llvm/llvm-project/.github/workflows/llvm-project-tests.yml@release/14.x + with: + build_target: check-lld + projects: lld abi-dump-setup: runs-on: ubuntu-latest From 99c0f85ef992e9aa6465f27a8b05601667412bc7 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 22 Mar 2022 23:17:39 -0700 Subject: [PATCH 252/316] Re-commit: Driver: Don't warn on -mbranch-protection when linking This is a re-commit of 98fd3b359866f474ab1c097c22fb5c3be356b996. The newly added test was failing on the bots, and I've fixed the test now so that it doesn't actually invoke the linker. (cherry picked from commit fed96f31bb5b68f77dd617ee8e698dd8171ee71b) --- clang/include/clang/Driver/Options.td | 1 + clang/test/Driver/aarch64-security-options.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 53e68ed2cef90..602586f94603f 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3400,6 +3400,7 @@ def msign_return_address_EQ : Joined<["-"], "msign-return-address=">, Flags<[CC1Option]>, Group, Values<"none,all,non-leaf">, HelpText<"Select return address signing scope">; def mbranch_protection_EQ : Joined<["-"], "mbranch-protection=">, + Group, HelpText<"Enforce targets of indirect branches and function returns">; def mharden_sls_EQ : Joined<["-"], "mharden-sls=">, diff --git a/clang/test/Driver/aarch64-security-options.c b/clang/test/Driver/aarch64-security-options.c index 6ea4b8ae58385..4bd73e06d255a 100644 --- a/clang/test/Driver/aarch64-security-options.c +++ b/clang/test/Driver/aarch64-security-options.c @@ -27,6 +27,9 @@ // RUN: %clang -target aarch64--none-eabi -c %s -### -mbranch-protection=bar 2>&1 | \ // RUN: FileCheck %s --check-prefix=BAD-BP-PROTECTION --check-prefix=WARN +// RUN: %clang -target aarch64--none-eabi -### -o /dev/null -mbranch-protection=standard /dev/null 2>&1 | \ +// RUN: FileCheck --allow-empty %s --check-prefix=LINKER-DRIVER + // WARN-NOT: warning: ignoring '-mbranch-protection=' option because the 'aarch64' architecture does not support it [-Wbranch-protection] // RA-OFF: "-msign-return-address=none" @@ -46,3 +49,7 @@ // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}' // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}' + +// Check that the linker driver doesn't warn about -mbranch-protection=standard +// as an unused option. +// LINKER-DRIVER-NOT: warning: From fe5c24e937548f97f24ec864b1c420e1cca0c110 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 16 Mar 2022 11:42:32 -0700 Subject: [PATCH 253/316] [docs] Fix typo in tutorial Use "operands" instead of "operators" Closes #54397 (cherry picked from commit 114a8903b86929f621c6b00f15e549931d912737) --- llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst index 7170b0fb25de0..fb23f9fe3f18b 100644 --- a/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst +++ b/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl03.rst @@ -197,7 +197,7 @@ suffix. Local value names for instructions are purely optional, but it makes it much easier to read the IR dumps. `LLVM instructions <../../LangRef.html#instruction-reference>`_ are constrained by strict -rules: for example, the Left and Right operators of an `add +rules: for example, the Left and Right operands of an `add instruction <../../LangRef.html#add-instruction>`_ must have the same type, and the result type of the add must match the operand types. Because all values in Kaleidoscope are doubles, this makes for very simple code for add, From f3b89727716a99a48b61a0c94025e35d363ececc Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Wed, 9 Mar 2022 20:29:49 -0500 Subject: [PATCH 254/316] [Driver][OpenBSD] Disable unwind tables on Arm Arm is not quite ready for unwinding yet. (cherry picked from commit 9abeb80e80d0f2e9dd7603491d33fa0683a33ac1) --- clang/lib/Driver/ToolChains/OpenBSD.cpp | 9 +++++++++ clang/lib/Driver/ToolChains/OpenBSD.h | 4 +--- clang/test/Driver/openbsd.c | 3 ++- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp b/clang/lib/Driver/ToolChains/OpenBSD.cpp index bcd54bedfa897..86a10ce4b0e75 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.cpp +++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp @@ -342,3 +342,12 @@ Tool *OpenBSD::buildAssembler() const { Tool *OpenBSD::buildLinker() const { return new tools::openbsd::Linker(*this); } bool OpenBSD::HasNativeLLVMSupport() const { return true; } + +bool OpenBSD::IsUnwindTablesDefault(const ArgList &Args) const { + switch (getArch()) { + case llvm::Triple::arm: + return false; + default: + return true; + } +} diff --git a/clang/lib/Driver/ToolChains/OpenBSD.h b/clang/lib/Driver/ToolChains/OpenBSD.h index 9d668711b91b3..2d4c4e34520b7 100644 --- a/clang/lib/Driver/ToolChains/OpenBSD.h +++ b/clang/lib/Driver/ToolChains/OpenBSD.h @@ -82,9 +82,7 @@ class LLVM_LIBRARY_VISIBILITY OpenBSD : public Generic_ELF { std::string getCompilerRT(const llvm::opt::ArgList &Args, StringRef Component, FileType Type = ToolChain::FT_Static) const override; - bool IsUnwindTablesDefault(const llvm::opt::ArgList &Args) const override { - return true; - } + bool IsUnwindTablesDefault(const llvm::opt::ArgList &Args) const override; LangOptions::StackProtectorMode GetDefaultStackProtectorLevel(bool KernelOrKext) const override { diff --git a/clang/test/Driver/openbsd.c b/clang/test/Driver/openbsd.c index e46de575aec09..8d91ce0e53e53 100644 --- a/clang/test/Driver/openbsd.c +++ b/clang/test/Driver/openbsd.c @@ -124,7 +124,8 @@ // Check that unwind tables are enabled // RUN: %clang -target arm-unknown-openbsd -### -S %s 2>&1 | \ -// RUN: FileCheck -check-prefix=UNWIND-TABLES %s +// RUN: FileCheck -check-prefix=NO-UNWIND-TABLES %s // RUN: %clang -target mips64-unknown-openbsd -### -S %s 2>&1 | \ // RUN: FileCheck -check-prefix=UNWIND-TABLES %s // UNWIND-TABLES: "-funwind-tables=2" +// NO-UNWIND-TABLES-NOT: "-funwind-tables=2" From 63e7af77ec42de9ac0b2fca6f7876b6b67c40050 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Wed, 23 Mar 2022 09:30:50 -0700 Subject: [PATCH 255/316] [Clang][NeonEmitter] emit ret decl first for -Wdeclaration-after-statement The generated arm_neon.h header isn't -Wdeclaration-after-statement compliant when targeting -mbig-endian. Update the generator to declare the return value, if any, first before any other arguments that might need to be "reversed" from little endian to big. Another approach would have been to try to ignore this warning in system headers, though that might not be precise for tokens involved in macro expansion. See also: https://reviews.llvm.org/D116833#3236209. Link: https://github.com/ClangBuiltLinux/linux/issues/1603 Fixes: https://github.com/llvm/llvm-project/issues/54062 Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D122189 (cherry picked from commit 5a2e56b70e2fa7ad0d82e54bc4c741b16f05e475) --- clang/test/CodeGen/aarch64-neon-ldst-one.c | 168 ++++++++++----------- clang/test/CodeGen/arm_neon_intrinsics.c | 102 ++++++------- clang/test/Sema/arm-neon-decl-after-stmt.c | 12 ++ clang/utils/TableGen/NeonEmitter.cpp | 23 ++- 4 files changed, 163 insertions(+), 142 deletions(-) create mode 100644 clang/test/Sema/arm-neon-decl-after-stmt.c diff --git a/clang/test/CodeGen/aarch64-neon-ldst-one.c b/clang/test/CodeGen/aarch64-neon-ldst-one.c index 1ecdd3e73724e..12f364b4425d0 100644 --- a/clang/test/CodeGen/aarch64-neon-ldst-one.c +++ b/clang/test/CodeGen/aarch64-neon-ldst-one.c @@ -947,8 +947,8 @@ poly64x1_t test_vld1_lane_p64(poly64_t *a, poly64x1_t b) { // CHECK-LABEL: define{{.*}} %struct.int8x16x2_t @test_vld2q_lane_s8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.int8x16x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[SRC]], i32 0, i32 0 // CHECK: store [2 x <16 x i8>] [[SRC]].coerce, [2 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x2_t* [[__S1]] to i8* @@ -976,8 +976,8 @@ int8x16x2_t test_vld2q_lane_s8(int8_t const * ptr, int8x16x2_t src) { // CHECK-LABEL: define{{.*}} %struct.uint8x16x2_t @test_vld2q_lane_u8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.uint8x16x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[SRC]], i32 0, i32 0 // CHECK: store [2 x <16 x i8>] [[SRC]].coerce, [2 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x2_t* [[__S1]] to i8* @@ -1005,8 +1005,8 @@ uint8x16x2_t test_vld2q_lane_u8(uint8_t const * ptr, uint8x16x2_t src) { // CHECK-LABEL: define{{.*}} %struct.poly8x16x2_t @test_vld2q_lane_p8(i8* noundef %ptr, [2 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.poly8x16x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[SRC]], i32 0, i32 0 // CHECK: store [2 x <16 x i8>] [[SRC]].coerce, [2 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x2_t* [[__S1]] to i8* @@ -1034,8 +1034,8 @@ poly8x16x2_t test_vld2q_lane_p8(poly8_t const * ptr, poly8x16x2_t src) { // CHECK-LABEL: define{{.*}} %struct.int8x16x3_t @test_vld3q_lane_s8(i8* noundef %ptr, [3 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.int8x16x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[SRC]], i32 0, i32 0 // CHECK: store [3 x <16 x i8>] [[SRC]].coerce, [3 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x3_t* [[__S1]] to i8* @@ -1066,8 +1066,8 @@ int8x16x3_t test_vld3q_lane_s8(int8_t const * ptr, int8x16x3_t src) { // CHECK-LABEL: define{{.*}} %struct.uint8x16x3_t @test_vld3q_lane_u8(i8* noundef %ptr, [3 x <16 x i8>] %src.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[SRC:%.*]] = alloca %struct.uint8x16x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[SRC]], i32 0, i32 0 // CHECK: store [3 x <16 x i8>] [[SRC]].coerce, [3 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x3_t* [[__S1]] to i8* @@ -1098,8 +1098,8 @@ uint8x16x3_t test_vld3q_lane_u8(uint8_t const * ptr, uint8x16x3_t src) { // CHECK-LABEL: define{{.*}} %struct.uint16x8x2_t @test_vld2q_lane_u16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x2_t, %struct.uint16x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i16>] [[B]].coerce, [2 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x2_t* [[__S1]] to i8* @@ -1132,8 +1132,8 @@ uint16x8x2_t test_vld2q_lane_u16(uint16_t *a, uint16x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x4x2_t @test_vld2q_lane_u32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x2_t, %struct.uint32x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x i32>] [[B]].coerce, [2 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x2_t* [[__S1]] to i8* @@ -1166,8 +1166,8 @@ uint32x4x2_t test_vld2q_lane_u32(uint32_t *a, uint32x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x2x2_t @test_vld2q_lane_u64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x2_t, %struct.uint64x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x i64>] [[B]].coerce, [2 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x2_t* [[__S1]] to i8* @@ -1200,8 +1200,8 @@ uint64x2x2_t test_vld2q_lane_u64(uint64_t *a, uint64x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x8x2_t @test_vld2q_lane_s16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i16>] [[B]].coerce, [2 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x2_t* [[__S1]] to i8* @@ -1234,8 +1234,8 @@ int16x8x2_t test_vld2q_lane_s16(int16_t *a, int16x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x4x2_t @test_vld2q_lane_s32(i32* noundef %a, [2 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x2_t, %struct.int32x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x i32>] [[B]].coerce, [2 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x2_t* [[__S1]] to i8* @@ -1268,8 +1268,8 @@ int32x4x2_t test_vld2q_lane_s32(int32_t *a, int32x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x2x2_t @test_vld2q_lane_s64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x2_t, %struct.int64x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x i64>] [[B]].coerce, [2 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x2_t* [[__S1]] to i8* @@ -1302,8 +1302,8 @@ int64x2x2_t test_vld2q_lane_s64(int64_t *a, int64x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x8x2_t @test_vld2q_lane_f16(half* noundef %a, [2 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x2_t, %struct.float16x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x half>] [[B]].coerce, [2 x <8 x half>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__S1]] to i8* @@ -1336,8 +1336,8 @@ float16x8x2_t test_vld2q_lane_f16(float16_t *a, float16x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x4x2_t @test_vld2q_lane_f32(float* noundef %a, [2 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x2_t, %struct.float32x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x float>] [[B]].coerce, [2 x <4 x float>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x2_t* [[__S1]] to i8* @@ -1370,8 +1370,8 @@ float32x4x2_t test_vld2q_lane_f32(float32_t *a, float32x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x2x2_t @test_vld2q_lane_f64(double* noundef %a, [2 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x2_t, %struct.float64x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x double>] [[B]].coerce, [2 x <2 x double>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x2_t* [[__S1]] to i8* @@ -1404,8 +1404,8 @@ float64x2x2_t test_vld2q_lane_f64(float64_t *a, float64x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x8x2_t @test_vld2q_lane_p16(i16* noundef %a, [2 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x2_t, %struct.poly16x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i16>] [[B]].coerce, [2 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x2_t* [[__S1]] to i8* @@ -1438,8 +1438,8 @@ poly16x8x2_t test_vld2q_lane_p16(poly16_t *a, poly16x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_lane_p64(i64* noundef %a, [2 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x i64>] [[B]].coerce, [2 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__S1]] to i8* @@ -1472,8 +1472,8 @@ poly64x2x2_t test_vld2q_lane_p64(poly64_t *a, poly64x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint8x8x2_t @test_vld2_lane_u8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i8>] [[B]].coerce, [2 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x2_t* [[__S1]] to i8* @@ -1501,8 +1501,8 @@ uint8x8x2_t test_vld2_lane_u8(uint8_t *a, uint8x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint16x4x2_t @test_vld2_lane_u16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x2_t, %struct.uint16x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x i16>] [[B]].coerce, [2 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x2_t* [[__S1]] to i8* @@ -1535,8 +1535,8 @@ uint16x4x2_t test_vld2_lane_u16(uint16_t *a, uint16x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x2x2_t @test_vld2_lane_u32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x2_t, %struct.uint32x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x i32>] [[B]].coerce, [2 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x2_t* [[__S1]] to i8* @@ -1569,8 +1569,8 @@ uint32x2x2_t test_vld2_lane_u32(uint32_t *a, uint32x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x1x2_t @test_vld2_lane_u64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x2_t, %struct.uint64x1x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <1 x i64>] [[B]].coerce, [2 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x2_t* [[__S1]] to i8* @@ -1603,8 +1603,8 @@ uint64x1x2_t test_vld2_lane_u64(uint64_t *a, uint64x1x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int8x8x2_t @test_vld2_lane_s8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i8>] [[B]].coerce, [2 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x2_t* [[__S1]] to i8* @@ -1632,8 +1632,8 @@ int8x8x2_t test_vld2_lane_s8(int8_t *a, int8x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x4x2_t @test_vld2_lane_s16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x2_t, %struct.int16x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x i16>] [[B]].coerce, [2 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x2_t* [[__S1]] to i8* @@ -1666,8 +1666,8 @@ int16x4x2_t test_vld2_lane_s16(int16_t *a, int16x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x2x2_t @test_vld2_lane_s32(i32* noundef %a, [2 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x2_t, %struct.int32x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x i32>] [[B]].coerce, [2 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x2_t* [[__S1]] to i8* @@ -1700,8 +1700,8 @@ int32x2x2_t test_vld2_lane_s32(int32_t *a, int32x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x1x2_t @test_vld2_lane_s64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x2_t, %struct.int64x1x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <1 x i64>] [[B]].coerce, [2 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x2_t* [[__S1]] to i8* @@ -1734,8 +1734,8 @@ int64x1x2_t test_vld2_lane_s64(int64_t *a, int64x1x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x4x2_t @test_vld2_lane_f16(half* noundef %a, [2 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x2_t, %struct.float16x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x half>] [[B]].coerce, [2 x <4 x half>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__S1]] to i8* @@ -1768,8 +1768,8 @@ float16x4x2_t test_vld2_lane_f16(float16_t *a, float16x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x2x2_t @test_vld2_lane_f32(float* noundef %a, [2 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x2_t, %struct.float32x2x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <2 x float>] [[B]].coerce, [2 x <2 x float>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x2_t* [[__S1]] to i8* @@ -1802,8 +1802,8 @@ float32x2x2_t test_vld2_lane_f32(float32_t *a, float32x2x2_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x1x2_t @test_vld2_lane_f64(double* noundef %a, [2 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x2_t, %struct.float64x1x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <1 x double>] [[B]].coerce, [2 x <1 x double>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x2_t* [[__S1]] to i8* @@ -1836,8 +1836,8 @@ float64x1x2_t test_vld2_lane_f64(float64_t *a, float64x1x2_t b) { // CHECK-LABEL: define{{.*}} %struct.poly8x8x2_t @test_vld2_lane_p8(i8* noundef %a, [2 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <8 x i8>] [[B]].coerce, [2 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x2_t* [[__S1]] to i8* @@ -1865,8 +1865,8 @@ poly8x8x2_t test_vld2_lane_p8(poly8_t *a, poly8x8x2_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x4x2_t @test_vld2_lane_p16(i16* noundef %a, [2 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x2_t, %struct.poly16x4x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <4 x i16>] [[B]].coerce, [2 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x2_t* [[__S1]] to i8* @@ -1899,8 +1899,8 @@ poly16x4x2_t test_vld2_lane_p16(poly16_t *a, poly16x4x2_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_lane_p64(i64* noundef %a, [2 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[B]], i32 0, i32 0 // CHECK: store [2 x <1 x i64>] [[B]].coerce, [2 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__S1]] to i8* @@ -1933,8 +1933,8 @@ poly64x1x2_t test_vld2_lane_p64(poly64_t *a, poly64x1x2_t b) { // CHECK-LABEL: define{{.*}} %struct.uint16x8x3_t @test_vld3q_lane_u16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x3_t, %struct.uint16x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i16>] [[B]].coerce, [3 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x3_t* [[__S1]] to i8* @@ -1972,8 +1972,8 @@ uint16x8x3_t test_vld3q_lane_u16(uint16_t *a, uint16x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x4x3_t @test_vld3q_lane_u32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x3_t, %struct.uint32x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x i32>] [[B]].coerce, [3 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x3_t* [[__S1]] to i8* @@ -2011,8 +2011,8 @@ uint32x4x3_t test_vld3q_lane_u32(uint32_t *a, uint32x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x2x3_t @test_vld3q_lane_u64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x3_t, %struct.uint64x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x i64>] [[B]].coerce, [3 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x3_t* [[__S1]] to i8* @@ -2050,8 +2050,8 @@ uint64x2x3_t test_vld3q_lane_u64(uint64_t *a, uint64x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x8x3_t @test_vld3q_lane_s16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x3_t, %struct.int16x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i16>] [[B]].coerce, [3 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x3_t* [[__S1]] to i8* @@ -2089,8 +2089,8 @@ int16x8x3_t test_vld3q_lane_s16(int16_t *a, int16x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x4x3_t @test_vld3q_lane_s32(i32* noundef %a, [3 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x3_t, %struct.int32x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x i32>] [[B]].coerce, [3 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x3_t* [[__S1]] to i8* @@ -2128,8 +2128,8 @@ int32x4x3_t test_vld3q_lane_s32(int32_t *a, int32x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x2x3_t @test_vld3q_lane_s64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x3_t, %struct.int64x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x i64>] [[B]].coerce, [3 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x3_t* [[__S1]] to i8* @@ -2167,8 +2167,8 @@ int64x2x3_t test_vld3q_lane_s64(int64_t *a, int64x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x8x3_t @test_vld3q_lane_f16(half* noundef %a, [3 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x3_t, %struct.float16x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x half>] [[B]].coerce, [3 x <8 x half>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__S1]] to i8* @@ -2206,8 +2206,8 @@ float16x8x3_t test_vld3q_lane_f16(float16_t *a, float16x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x4x3_t @test_vld3q_lane_f32(float* noundef %a, [3 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x3_t, %struct.float32x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x float>] [[B]].coerce, [3 x <4 x float>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x3_t* [[__S1]] to i8* @@ -2245,8 +2245,8 @@ float32x4x3_t test_vld3q_lane_f32(float32_t *a, float32x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x2x3_t @test_vld3q_lane_f64(double* noundef %a, [3 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x3_t, %struct.float64x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x double>] [[B]].coerce, [3 x <2 x double>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x3_t* [[__S1]] to i8* @@ -2284,8 +2284,8 @@ float64x2x3_t test_vld3q_lane_f64(float64_t *a, float64x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly8x16x3_t @test_vld3q_lane_p8(i8* noundef %a, [3 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <16 x i8>] [[B]].coerce, [3 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x3_t* [[__S1]] to i8* @@ -2316,8 +2316,8 @@ poly8x16x3_t test_vld3q_lane_p8(poly8_t *a, poly8x16x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x8x3_t @test_vld3q_lane_p16(i16* noundef %a, [3 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x3_t, %struct.poly16x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i16>] [[B]].coerce, [3 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x3_t* [[__S1]] to i8* @@ -2355,8 +2355,8 @@ poly16x8x3_t test_vld3q_lane_p16(poly16_t *a, poly16x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_lane_p64(i64* noundef %a, [3 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x i64>] [[B]].coerce, [3 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__S1]] to i8* @@ -2394,8 +2394,8 @@ poly64x2x3_t test_vld3q_lane_p64(poly64_t *a, poly64x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint8x8x3_t @test_vld3_lane_u8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i8>] [[B]].coerce, [3 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x3_t* [[__S1]] to i8* @@ -2426,8 +2426,8 @@ uint8x8x3_t test_vld3_lane_u8(uint8_t *a, uint8x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint16x4x3_t @test_vld3_lane_u16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x3_t, %struct.uint16x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x i16>] [[B]].coerce, [3 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x3_t* [[__S1]] to i8* @@ -2465,8 +2465,8 @@ uint16x4x3_t test_vld3_lane_u16(uint16_t *a, uint16x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x2x3_t @test_vld3_lane_u32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x3_t, %struct.uint32x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x i32>] [[B]].coerce, [3 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x3_t* [[__S1]] to i8* @@ -2504,8 +2504,8 @@ uint32x2x3_t test_vld3_lane_u32(uint32_t *a, uint32x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x1x3_t @test_vld3_lane_u64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x3_t, %struct.uint64x1x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <1 x i64>] [[B]].coerce, [3 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x3_t* [[__S1]] to i8* @@ -2543,8 +2543,8 @@ uint64x1x3_t test_vld3_lane_u64(uint64_t *a, uint64x1x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int8x8x3_t @test_vld3_lane_s8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i8>] [[B]].coerce, [3 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x3_t* [[__S1]] to i8* @@ -2575,8 +2575,8 @@ int8x8x3_t test_vld3_lane_s8(int8_t *a, int8x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x4x3_t @test_vld3_lane_s16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x3_t, %struct.int16x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x i16>] [[B]].coerce, [3 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x3_t* [[__S1]] to i8* @@ -2614,8 +2614,8 @@ int16x4x3_t test_vld3_lane_s16(int16_t *a, int16x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x2x3_t @test_vld3_lane_s32(i32* noundef %a, [3 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x3_t, %struct.int32x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x i32>] [[B]].coerce, [3 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x3_t* [[__S1]] to i8* @@ -2653,8 +2653,8 @@ int32x2x3_t test_vld3_lane_s32(int32_t *a, int32x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x1x3_t @test_vld3_lane_s64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x3_t, %struct.int64x1x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <1 x i64>] [[B]].coerce, [3 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x3_t* [[__S1]] to i8* @@ -2692,8 +2692,8 @@ int64x1x3_t test_vld3_lane_s64(int64_t *a, int64x1x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x4x3_t @test_vld3_lane_f16(half* noundef %a, [3 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x3_t, %struct.float16x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x half>] [[B]].coerce, [3 x <4 x half>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__S1]] to i8* @@ -2731,8 +2731,8 @@ float16x4x3_t test_vld3_lane_f16(float16_t *a, float16x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x2x3_t @test_vld3_lane_f32(float* noundef %a, [3 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x3_t, %struct.float32x2x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <2 x float>] [[B]].coerce, [3 x <2 x float>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x3_t* [[__S1]] to i8* @@ -2770,8 +2770,8 @@ float32x2x3_t test_vld3_lane_f32(float32_t *a, float32x2x3_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x1x3_t @test_vld3_lane_f64(double* noundef %a, [3 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x3_t, %struct.float64x1x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <1 x double>] [[B]].coerce, [3 x <1 x double>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x3_t* [[__S1]] to i8* @@ -2809,8 +2809,8 @@ float64x1x3_t test_vld3_lane_f64(float64_t *a, float64x1x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly8x8x3_t @test_vld3_lane_p8(i8* noundef %a, [3 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <8 x i8>] [[B]].coerce, [3 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x3_t* [[__S1]] to i8* @@ -2841,8 +2841,8 @@ poly8x8x3_t test_vld3_lane_p8(poly8_t *a, poly8x8x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x4x3_t @test_vld3_lane_p16(i16* noundef %a, [3 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x3_t, %struct.poly16x4x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <4 x i16>] [[B]].coerce, [3 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x3_t* [[__S1]] to i8* @@ -2880,8 +2880,8 @@ poly16x4x3_t test_vld3_lane_p16(poly16_t *a, poly16x4x3_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_lane_p64(i64* noundef %a, [3 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[B]], i32 0, i32 0 // CHECK: store [3 x <1 x i64>] [[B]].coerce, [3 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__S1]] to i8* @@ -2919,8 +2919,8 @@ poly64x1x3_t test_vld3_lane_p64(poly64_t *a, poly64x1x3_t b) { // CHECK-LABEL: define{{.*}} %struct.uint8x16x4_t @test_vld4q_lane_u8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <16 x i8>] [[B]].coerce, [4 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x16x4_t* [[__S1]] to i8* @@ -2954,8 +2954,8 @@ uint8x16x4_t test_vld4q_lane_u8(uint8_t *a, uint8x16x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint16x8x4_t @test_vld4q_lane_u16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x4_t, %struct.uint16x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i16>] [[B]].coerce, [4 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x8x4_t* [[__S1]] to i8* @@ -2998,8 +2998,8 @@ uint16x8x4_t test_vld4q_lane_u16(uint16_t *a, uint16x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x4x4_t @test_vld4q_lane_u32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x4_t, %struct.uint32x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x i32>] [[B]].coerce, [4 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x4x4_t* [[__S1]] to i8* @@ -3042,8 +3042,8 @@ uint32x4x4_t test_vld4q_lane_u32(uint32_t *a, uint32x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x2x4_t @test_vld4q_lane_u64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.uint64x2x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x2x4_t, %struct.uint64x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x i64>] [[B]].coerce, [4 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x2x4_t* [[__S1]] to i8* @@ -3086,8 +3086,8 @@ uint64x2x4_t test_vld4q_lane_u64(uint64_t *a, uint64x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int8x16x4_t @test_vld4q_lane_s8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <16 x i8>] [[B]].coerce, [4 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x16x4_t* [[__S1]] to i8* @@ -3121,8 +3121,8 @@ int8x16x4_t test_vld4q_lane_s8(int8_t *a, int8x16x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x8x4_t @test_vld4q_lane_s16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x4_t, %struct.int16x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i16>] [[B]].coerce, [4 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x8x4_t* [[__S1]] to i8* @@ -3165,8 +3165,8 @@ int16x8x4_t test_vld4q_lane_s16(int16_t *a, int16x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x4x4_t @test_vld4q_lane_s32(i32* noundef %a, [4 x <4 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x4_t, %struct.int32x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x i32>] [[B]].coerce, [4 x <4 x i32>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x4x4_t* [[__S1]] to i8* @@ -3209,8 +3209,8 @@ int32x4x4_t test_vld4q_lane_s32(int32_t *a, int32x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x2x4_t @test_vld4q_lane_s64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.int64x2x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x2x4_t, %struct.int64x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x i64>] [[B]].coerce, [4 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x2x4_t* [[__S1]] to i8* @@ -3253,8 +3253,8 @@ int64x2x4_t test_vld4q_lane_s64(int64_t *a, int64x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x8x4_t @test_vld4q_lane_f16(half* noundef %a, [4 x <8 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x4_t, %struct.float16x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x half>] [[B]].coerce, [4 x <8 x half>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__S1]] to i8* @@ -3297,8 +3297,8 @@ float16x8x4_t test_vld4q_lane_f16(float16_t *a, float16x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x4x4_t @test_vld4q_lane_f32(float* noundef %a, [4 x <4 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x4_t, %struct.float32x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x float>] [[B]].coerce, [4 x <4 x float>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x4x4_t* [[__S1]] to i8* @@ -3341,8 +3341,8 @@ float32x4x4_t test_vld4q_lane_f32(float32_t *a, float32x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x2x4_t @test_vld4q_lane_f64(double* noundef %a, [4 x <2 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.float64x2x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float64x2x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x2x4_t, %struct.float64x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x double>] [[B]].coerce, [4 x <2 x double>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x2x4_t* [[__S1]] to i8* @@ -3385,8 +3385,8 @@ float64x2x4_t test_vld4q_lane_f64(float64_t *a, float64x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly8x16x4_t @test_vld4q_lane_p8(i8* noundef %a, [4 x <16 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x16x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <16 x i8>] [[B]].coerce, [4 x <16 x i8>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x16x4_t* [[__S1]] to i8* @@ -3420,8 +3420,8 @@ poly8x16x4_t test_vld4q_lane_p8(poly8_t *a, poly8x16x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x8x4_t @test_vld4q_lane_p16(i16* noundef %a, [4 x <8 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x4_t, %struct.poly16x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i16>] [[B]].coerce, [4 x <8 x i16>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x8x4_t* [[__S1]] to i8* @@ -3464,8 +3464,8 @@ poly16x8x4_t test_vld4q_lane_p16(poly16_t *a, poly16x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_lane_p64(i64* noundef %a, [4 x <2 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[B:%.*]] = alloca %struct.poly64x2x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x i64>] [[B]].coerce, [4 x <2 x i64>]* [[COERCE_DIVE]], align 16 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__S1]] to i8* @@ -3508,8 +3508,8 @@ poly64x2x4_t test_vld4q_lane_p64(poly64_t *a, poly64x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint8x8x4_t @test_vld4_lane_u8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i8>] [[B]].coerce, [4 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint8x8x4_t* [[__S1]] to i8* @@ -3543,8 +3543,8 @@ uint8x8x4_t test_vld4_lane_u8(uint8_t *a, uint8x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint16x4x4_t @test_vld4_lane_u16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x4_t, %struct.uint16x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x i16>] [[B]].coerce, [4 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint16x4x4_t* [[__S1]] to i8* @@ -3587,8 +3587,8 @@ uint16x4x4_t test_vld4_lane_u16(uint16_t *a, uint16x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint32x2x4_t @test_vld4_lane_u32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x4_t, %struct.uint32x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x i32>] [[B]].coerce, [4 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint32x2x4_t* [[__S1]] to i8* @@ -3631,8 +3631,8 @@ uint32x2x4_t test_vld4_lane_u32(uint32_t *a, uint32x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.uint64x1x4_t @test_vld4_lane_u64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.uint64x1x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint64x1x4_t, %struct.uint64x1x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <1 x i64>] [[B]].coerce, [4 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.uint64x1x4_t* [[__S1]] to i8* @@ -3675,8 +3675,8 @@ uint64x1x4_t test_vld4_lane_u64(uint64_t *a, uint64x1x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int8x8x4_t @test_vld4_lane_s8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i8>] [[B]].coerce, [4 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int8x8x4_t* [[__S1]] to i8* @@ -3710,8 +3710,8 @@ int8x8x4_t test_vld4_lane_s8(int8_t *a, int8x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int16x4x4_t @test_vld4_lane_s16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x4_t, %struct.int16x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x i16>] [[B]].coerce, [4 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int16x4x4_t* [[__S1]] to i8* @@ -3754,8 +3754,8 @@ int16x4x4_t test_vld4_lane_s16(int16_t *a, int16x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int32x2x4_t @test_vld4_lane_s32(i32* noundef %a, [4 x <2 x i32>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x4_t, %struct.int32x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x i32>] [[B]].coerce, [4 x <2 x i32>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int32x2x4_t* [[__S1]] to i8* @@ -3798,8 +3798,8 @@ int32x2x4_t test_vld4_lane_s32(int32_t *a, int32x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.int64x1x4_t @test_vld4_lane_s64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.int64x1x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int64x1x4_t, %struct.int64x1x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <1 x i64>] [[B]].coerce, [4 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.int64x1x4_t* [[__S1]] to i8* @@ -3842,8 +3842,8 @@ int64x1x4_t test_vld4_lane_s64(int64_t *a, int64x1x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float16x4x4_t @test_vld4_lane_f16(half* noundef %a, [4 x <4 x half>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x4_t, %struct.float16x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x half>] [[B]].coerce, [4 x <4 x half>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__S1]] to i8* @@ -3886,8 +3886,8 @@ float16x4x4_t test_vld4_lane_f16(float16_t *a, float16x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float32x2x4_t @test_vld4_lane_f32(float* noundef %a, [4 x <2 x float>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x4_t, %struct.float32x2x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <2 x float>] [[B]].coerce, [4 x <2 x float>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float32x2x4_t* [[__S1]] to i8* @@ -3930,8 +3930,8 @@ float32x2x4_t test_vld4_lane_f32(float32_t *a, float32x2x4_t b) { // CHECK-LABEL: define{{.*}} %struct.float64x1x4_t @test_vld4_lane_f64(double* noundef %a, [4 x <1 x double>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.float64x1x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float64x1x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float64x1x4_t, %struct.float64x1x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <1 x double>] [[B]].coerce, [4 x <1 x double>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.float64x1x4_t* [[__S1]] to i8* @@ -3974,8 +3974,8 @@ float64x1x4_t test_vld4_lane_f64(float64_t *a, float64x1x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly8x8x4_t @test_vld4_lane_p8(i8* noundef %a, [4 x <8 x i8>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <8 x i8>] [[B]].coerce, [4 x <8 x i8>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly8x8x4_t* [[__S1]] to i8* @@ -4009,8 +4009,8 @@ poly8x8x4_t test_vld4_lane_p8(poly8_t *a, poly8x8x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly16x4x4_t @test_vld4_lane_p16(i16* noundef %a, [4 x <4 x i16>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x4_t, %struct.poly16x4x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <4 x i16>] [[B]].coerce, [4 x <4 x i16>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly16x4x4_t* [[__S1]] to i8* @@ -4053,8 +4053,8 @@ poly16x4x4_t test_vld4_lane_p16(poly16_t *a, poly16x4x4_t b) { // CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_lane_p64(i64* noundef %a, [4 x <1 x i64>] %b.coerce) #2 { // CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[B:%.*]] = alloca %struct.poly64x1x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[B]], i32 0, i32 0 // CHECK: store [4 x <1 x i64>] [[B]].coerce, [4 x <1 x i64>]* [[COERCE_DIVE]], align 8 // CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__S1]] to i8* diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c b/clang/test/CodeGen/arm_neon_intrinsics.c index d7d22eb35a5ed..09ceae21a6ad8 100644 --- a/clang/test/CodeGen/arm_neon_intrinsics.c +++ b/clang/test/CodeGen/arm_neon_intrinsics.c @@ -4785,8 +4785,8 @@ poly16x4x2_t test_vld2_p16(poly16_t const * a) { // CHECK-LABEL: @test_vld2q_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x2_t, %struct.uint16x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4812,8 +4812,8 @@ uint16x8x2_t test_vld2q_lane_u16(uint16_t const * a, uint16x8x2_t b) { // CHECK-LABEL: @test_vld2q_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x2_t, %struct.uint32x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x i32>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4839,8 +4839,8 @@ uint32x4x2_t test_vld2q_lane_u32(uint32_t const * a, uint32x4x2_t b) { // CHECK-LABEL: @test_vld2q_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4866,8 +4866,8 @@ int16x8x2_t test_vld2q_lane_s16(int16_t const * a, int16x8x2_t b) { // CHECK-LABEL: @test_vld2q_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x2_t, %struct.int32x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x i32>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4893,8 +4893,8 @@ int32x4x2_t test_vld2q_lane_s32(int32_t const * a, int32x4x2_t b) { // CHECK-LABEL: @test_vld2q_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x2_t, %struct.float16x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x half>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4920,8 +4920,8 @@ float16x8x2_t test_vld2q_lane_f16(float16_t const * a, float16x8x2_t b) { // CHECK-LABEL: @test_vld2q_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x4x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x2_t, %struct.float32x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x float>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4947,8 +4947,8 @@ float32x4x2_t test_vld2q_lane_f32(float32_t const * a, float32x4x2_t b) { // CHECK-LABEL: @test_vld2q_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x8x2_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x2_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x2_t, %struct.poly16x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 16 @@ -4974,8 +4974,8 @@ poly16x8x2_t test_vld2q_lane_p16(poly16_t const * a, poly16x8x2_t b) { // CHECK-LABEL: @test_vld2_lane_u8( // CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i8>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -4996,8 +4996,8 @@ uint8x8x2_t test_vld2_lane_u8(uint8_t const * a, uint8x8x2_t b) { // CHECK-LABEL: @test_vld2_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x2_t, %struct.uint16x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x i16>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5023,8 +5023,8 @@ uint16x4x2_t test_vld2_lane_u16(uint16_t const * a, uint16x4x2_t b) { // CHECK-LABEL: @test_vld2_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x2_t, %struct.uint32x2x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <2 x i32>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5050,8 +5050,8 @@ uint32x2x2_t test_vld2_lane_u32(uint32_t const * a, uint32x2x2_t b) { // CHECK-LABEL: @test_vld2_lane_s8( // CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i8>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5072,8 +5072,8 @@ int8x8x2_t test_vld2_lane_s8(int8_t const * a, int8x8x2_t b) { // CHECK-LABEL: @test_vld2_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x2_t, %struct.int16x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x i16>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5099,8 +5099,8 @@ int16x4x2_t test_vld2_lane_s16(int16_t const * a, int16x4x2_t b) { // CHECK-LABEL: @test_vld2_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x2_t, %struct.int32x2x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <2 x i32>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5126,8 +5126,8 @@ int32x2x2_t test_vld2_lane_s32(int32_t const * a, int32x2x2_t b) { // CHECK-LABEL: @test_vld2_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x2_t, %struct.float16x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x half>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5153,8 +5153,8 @@ float16x4x2_t test_vld2_lane_f16(float16_t const * a, float16x4x2_t b) { // CHECK-LABEL: @test_vld2_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x2x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x2_t, %struct.float32x2x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <2 x float>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5180,8 +5180,8 @@ float32x2x2_t test_vld2_lane_f32(float32_t const * a, float32x2x2_t b) { // CHECK-LABEL: @test_vld2_lane_p8( // CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <8 x i8>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5202,8 +5202,8 @@ poly8x8x2_t test_vld2_lane_p8(poly8_t const * a, poly8x8x2_t b) { // CHECK-LABEL: @test_vld2_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x4x2_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x2_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x2_t, %struct.poly16x4x2_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [2 x <4 x i16>]* [[COERCE_DIVE]] to [2 x i64]* // CHECK: store [2 x i64] [[B]].coerce, [2 x i64]* [[TMP0]], align 8 @@ -5421,8 +5421,8 @@ poly16x4x3_t test_vld3_p16(poly16_t const * a) { // CHECK-LABEL: @test_vld3q_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x3_t, %struct.uint16x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i16>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5453,8 +5453,8 @@ uint16x8x3_t test_vld3q_lane_u16(uint16_t const * a, uint16x8x3_t b) { // CHECK-LABEL: @test_vld3q_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x3_t, %struct.uint32x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x i32>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5485,8 +5485,8 @@ uint32x4x3_t test_vld3q_lane_u32(uint32_t const * a, uint32x4x3_t b) { // CHECK-LABEL: @test_vld3q_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x3_t, %struct.int16x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i16>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5517,8 +5517,8 @@ int16x8x3_t test_vld3q_lane_s16(int16_t const * a, int16x8x3_t b) { // CHECK-LABEL: @test_vld3q_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x3_t, %struct.int32x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x i32>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5549,8 +5549,8 @@ int32x4x3_t test_vld3q_lane_s32(int32_t const * a, int32x4x3_t b) { // CHECK-LABEL: @test_vld3q_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x3_t, %struct.float16x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x half>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5581,8 +5581,8 @@ float16x8x3_t test_vld3q_lane_f16(float16_t const * a, float16x8x3_t b) { // CHECK-LABEL: @test_vld3q_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x4x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x3_t, %struct.float32x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x float>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5613,8 +5613,8 @@ float32x4x3_t test_vld3q_lane_f32(float32_t const * a, float32x4x3_t b) { // CHECK-LABEL: @test_vld3q_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x8x3_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x3_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x3_t, %struct.poly16x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i16>]* [[COERCE_DIVE]] to [6 x i64]* // CHECK: store [6 x i64] [[B]].coerce, [6 x i64]* [[TMP0]], align 16 @@ -5645,8 +5645,8 @@ poly16x8x3_t test_vld3q_lane_p16(poly16_t const * a, poly16x8x3_t b) { // CHECK-LABEL: @test_vld3_lane_u8( // CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i8>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5670,8 +5670,8 @@ uint8x8x3_t test_vld3_lane_u8(uint8_t const * a, uint8x8x3_t b) { // CHECK-LABEL: @test_vld3_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x3_t, %struct.uint16x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x i16>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5702,8 +5702,8 @@ uint16x4x3_t test_vld3_lane_u16(uint16_t const * a, uint16x4x3_t b) { // CHECK-LABEL: @test_vld3_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x3_t, %struct.uint32x2x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <2 x i32>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5734,8 +5734,8 @@ uint32x2x3_t test_vld3_lane_u32(uint32_t const * a, uint32x2x3_t b) { // CHECK-LABEL: @test_vld3_lane_s8( // CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i8>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5759,8 +5759,8 @@ int8x8x3_t test_vld3_lane_s8(int8_t const * a, int8x8x3_t b) { // CHECK-LABEL: @test_vld3_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x3_t, %struct.int16x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x i16>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5791,8 +5791,8 @@ int16x4x3_t test_vld3_lane_s16(int16_t const * a, int16x4x3_t b) { // CHECK-LABEL: @test_vld3_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x3_t, %struct.int32x2x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <2 x i32>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5823,8 +5823,8 @@ int32x2x3_t test_vld3_lane_s32(int32_t const * a, int32x2x3_t b) { // CHECK-LABEL: @test_vld3_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x3_t, %struct.float16x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x half>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5855,8 +5855,8 @@ float16x4x3_t test_vld3_lane_f16(float16_t const * a, float16x4x3_t b) { // CHECK-LABEL: @test_vld3_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x2x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x3_t, %struct.float32x2x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <2 x float>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5887,8 +5887,8 @@ float32x2x3_t test_vld3_lane_f32(float32_t const * a, float32x2x3_t b) { // CHECK-LABEL: @test_vld3_lane_p8( // CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <8 x i8>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -5912,8 +5912,8 @@ poly8x8x3_t test_vld3_lane_p8(poly8_t const * a, poly8x8x3_t b) { // CHECK-LABEL: @test_vld3_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x4x3_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x3_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x3_t, %struct.poly16x4x3_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [3 x <4 x i16>]* [[COERCE_DIVE]] to [3 x i64]* // CHECK: store [3 x i64] [[B]].coerce, [3 x i64]* [[TMP0]], align 8 @@ -6136,8 +6136,8 @@ poly16x4x4_t test_vld4_p16(poly16_t const * a) { // CHECK-LABEL: @test_vld4q_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x8x4_t, %struct.uint16x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i16>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6173,8 +6173,8 @@ uint16x8x4_t test_vld4q_lane_u16(uint16_t const * a, uint16x8x4_t b) { // CHECK-LABEL: @test_vld4q_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x4x4_t, %struct.uint32x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x i32>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6210,8 +6210,8 @@ uint32x4x4_t test_vld4q_lane_u32(uint32_t const * a, uint32x4x4_t b) { // CHECK-LABEL: @test_vld4q_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x8x4_t, %struct.int16x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i16>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6247,8 +6247,8 @@ int16x8x4_t test_vld4q_lane_s16(int16_t const * a, int16x8x4_t b) { // CHECK-LABEL: @test_vld4q_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x4x4_t, %struct.int32x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x i32>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6284,8 +6284,8 @@ int32x4x4_t test_vld4q_lane_s32(int32_t const * a, int32x4x4_t b) { // CHECK-LABEL: @test_vld4q_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x8x4_t, %struct.float16x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x half>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6321,8 +6321,8 @@ float16x8x4_t test_vld4q_lane_f16(float16_t const * a, float16x8x4_t b) { // CHECK-LABEL: @test_vld4q_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x4x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x4x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x4x4_t, %struct.float32x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x float>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6358,8 +6358,8 @@ float32x4x4_t test_vld4q_lane_f32(float32_t const * a, float32x4x4_t b) { // CHECK-LABEL: @test_vld4q_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x8x4_t, align 16 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align 16 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x8x4_t, align 16 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x8x4_t, %struct.poly16x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i16>]* [[COERCE_DIVE]] to [8 x i64]* // CHECK: store [8 x i64] [[B]].coerce, [8 x i64]* [[TMP0]], align 16 @@ -6395,8 +6395,8 @@ poly16x8x4_t test_vld4q_lane_p16(poly16_t const * a, poly16x8x4_t b) { // CHECK-LABEL: @test_vld4_lane_u8( // CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i8>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6423,8 +6423,8 @@ uint8x8x4_t test_vld4_lane_u8(uint8_t const * a, uint8x8x4_t b) { // CHECK-LABEL: @test_vld4_lane_u16( // CHECK: [[B:%.*]] = alloca %struct.uint16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint16x4x4_t, %struct.uint16x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6460,8 +6460,8 @@ uint16x4x4_t test_vld4_lane_u16(uint16_t const * a, uint16x4x4_t b) { // CHECK-LABEL: @test_vld4_lane_u32( // CHECK: [[B:%.*]] = alloca %struct.uint32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.uint32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint32x2x4_t, %struct.uint32x2x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <2 x i32>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6497,8 +6497,8 @@ uint32x2x4_t test_vld4_lane_u32(uint32_t const * a, uint32x2x4_t b) { // CHECK-LABEL: @test_vld4_lane_s8( // CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i8>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6525,8 +6525,8 @@ int8x8x4_t test_vld4_lane_s8(int8_t const * a, int8x8x4_t b) { // CHECK-LABEL: @test_vld4_lane_s16( // CHECK: [[B:%.*]] = alloca %struct.int16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int16x4x4_t, %struct.int16x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6562,8 +6562,8 @@ int16x4x4_t test_vld4_lane_s16(int16_t const * a, int16x4x4_t b) { // CHECK-LABEL: @test_vld4_lane_s32( // CHECK: [[B:%.*]] = alloca %struct.int32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.int32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int32x2x4_t, %struct.int32x2x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <2 x i32>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6599,8 +6599,8 @@ int32x2x4_t test_vld4_lane_s32(int32_t const * a, int32x2x4_t b) { // CHECK-LABEL: @test_vld4_lane_f16( // CHECK: [[B:%.*]] = alloca %struct.float16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float16x4x4_t, %struct.float16x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x half>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6636,8 +6636,8 @@ float16x4x4_t test_vld4_lane_f16(float16_t const * a, float16x4x4_t b) { // CHECK-LABEL: @test_vld4_lane_f32( // CHECK: [[B:%.*]] = alloca %struct.float32x2x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.float32x2x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.float32x2x4_t, %struct.float32x2x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <2 x float>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6673,8 +6673,8 @@ float32x2x4_t test_vld4_lane_f32(float32_t const * a, float32x2x4_t b) { // CHECK-LABEL: @test_vld4_lane_p8( // CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly8x8x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <8 x i8>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 @@ -6701,8 +6701,8 @@ poly8x8x4_t test_vld4_lane_p8(poly8_t const * a, poly8x8x4_t b) { // CHECK-LABEL: @test_vld4_lane_p16( // CHECK: [[B:%.*]] = alloca %struct.poly16x4x4_t, align 8 -// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 +// CHECK: [[__S1:%.*]] = alloca %struct.poly16x4x4_t, align 8 // CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly16x4x4_t, %struct.poly16x4x4_t* [[B]], i32 0, i32 0 // CHECK: [[TMP0:%.*]] = bitcast [4 x <4 x i16>]* [[COERCE_DIVE]] to [4 x i64]* // CHECK: store [4 x i64] [[B]].coerce, [4 x i64]* [[TMP0]], align 8 diff --git a/clang/test/Sema/arm-neon-decl-after-stmt.c b/clang/test/Sema/arm-neon-decl-after-stmt.c new file mode 100644 index 0000000000000..c6529445c6f5b --- /dev/null +++ b/clang/test/Sema/arm-neon-decl-after-stmt.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -triple armebv7-linux-gnueabihf -target-feature +neon \ +// RUN: -Wdeclaration-after-statement -fsyntax-only -verify %s +// REQUIRES: arm-registered-target +// https://github.com/llvm/llvm-project/issues/54062 +#include + +uint8x16_t a; + +uint8x16_t x(void) { + return vshrq_n_u8(a, 8); +} +// expected-no-diagnostics diff --git a/clang/utils/TableGen/NeonEmitter.cpp b/clang/utils/TableGen/NeonEmitter.cpp index a69fbe0e42dcd..1550a8a1e273e 100644 --- a/clang/utils/TableGen/NeonEmitter.cpp +++ b/clang/utils/TableGen/NeonEmitter.cpp @@ -502,6 +502,7 @@ class Intrinsic { void emitBody(StringRef CallPrefix); void emitShadowedArgs(); void emitArgumentReversal(); + void emitReturnVarDecl(); void emitReturnReversal(); void emitReverseVariable(Variable &Dest, Variable &Src); void emitNewLine(); @@ -1228,6 +1229,15 @@ void Intrinsic::emitArgumentReversal() { } } +void Intrinsic::emitReturnVarDecl() { + assert(RetVar.getType() == Types[0]); + // Create a return variable, if we're not void. + if (!RetVar.getType().isVoid()) { + OS << " " << RetVar.getType().str() << " " << RetVar.getName() << ";"; + emitNewLine(); + } +} + void Intrinsic::emitReturnReversal() { if (isBigEndianSafe()) return; @@ -1353,13 +1363,6 @@ void Intrinsic::emitBodyAsBuiltinCall() { void Intrinsic::emitBody(StringRef CallPrefix) { std::vector Lines; - assert(RetVar.getType() == Types[0]); - // Create a return variable, if we're not void. - if (!RetVar.getType().isVoid()) { - OS << " " << RetVar.getType().str() << " " << RetVar.getName() << ";"; - emitNewLine(); - } - if (!Body || Body->getValues().empty()) { // Nothing specific to output - must output a builtin. emitBodyAsBuiltinCall(); @@ -1849,6 +1852,9 @@ void Intrinsic::generateImpl(bool ReverseArguments, OS << " __attribute__((unavailable));"; } else { emitOpeningBrace(); + // Emit return variable declaration first as to not trigger + // -Wdeclaration-after-statement. + emitReturnVarDecl(); emitShadowedArgs(); if (ReverseArguments) emitArgumentReversal(); @@ -1867,6 +1873,9 @@ void Intrinsic::indexBody() { CurrentRecord = R; initVariables(); + // Emit return variable declaration first as to not trigger + // -Wdeclaration-after-statement. + emitReturnVarDecl(); emitBody(""); OS.str(""); From b69247dcbd80196af7f3b3942a51be3f2f82023b Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Mon, 28 Mar 2022 22:27:28 -0400 Subject: [PATCH 256/316] [libcxx] random_device, specify optimal entropy properties for all OS's using arc4random() Reviewed By: ldionne Differential Revision: https://reviews.llvm.org/D122522 (cherry picked from commit 6e2c6c9def394c79a65bb216ac3d5261d39cc960) --- libcxx/src/random.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/src/random.cpp b/libcxx/src/random.cpp index 6472a8dbcba3e..146b7c56bdebf 100644 --- a/libcxx/src/random.cpp +++ b/libcxx/src/random.cpp @@ -210,7 +210,7 @@ random_device::entropy() const noexcept return std::numeric_limits::digits; return ent; -#elif defined(__OpenBSD__) || defined(_LIBCPP_USING_FUCHSIA_CPRNG) +#elif defined(_LIBCPP_USING_ARC4_RANDOM) || defined(_LIBCPP_USING_FUCHSIA_CPRNG) return std::numeric_limits::digits; #else return 0; From 23d08271a4b24f21a88bfe73a5ea31c1e2c6365c Mon Sep 17 00:00:00 2001 From: Aaron Puchert Date: Mon, 21 Mar 2022 15:28:27 +0100 Subject: [PATCH 257/316] Add cmake/ to release tarballs via concatenation The solution using append was reported not to work, but additionally it would use the contents of the checked-out source tree instead of the git tag or commit. This uses `git archive`, so it will use the right commit, and at least for me (with GNU tar) it seems to work as intended. Should fix #53281. Reviewed By: kwk Differential Revision: https://reviews.llvm.org/D121972 (cherry picked from commit 3a33664e8838e8b77acd1bbb13b1cf5e580a1077) --- llvm/utils/release/export.sh | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/llvm/utils/release/export.sh b/llvm/utils/release/export.sh index 43bb71d09bea8..55e38ab12bc7a 100755 --- a/llvm/utils/release/export.sh +++ b/llvm/utils/release/export.sh @@ -128,17 +128,21 @@ export_sources() { -cJf test-suite-$release$rc.src.tar.xz test-suite-$release$rc.src fi + # Package up top-level cmake directory so that we can append it to all projects. + tmp_dir=$(mktemp -d) + cmake_archive_file=$tmp_dir/cmake.tar + trap "rm -rv $tmp_dir" EXIT + pushd $llvm_src_dir + git archive -o $cmake_archive_file $tree_id cmake/ + popd + for proj in $projects; do echo "Creating tarball for $proj ..." pushd $llvm_src_dir/$proj - target_archive_file=$target_dir/$(template_file $proj) - trap "rm -fv $target_archive_file.tmp" EXIT - git archive --prefix=$proj-$release$rc.src/ -o $target_archive_file.tmp $tree_id . - # Get relative path to top-level cmake directory to be packaged - # alongside the project. Append that path to the tarball. - cmake_rel_path=$(realpath --relative-to=. $llvm_src_dir/cmake) - tar --append -f $target_archive_file.tmp $cmake_rel_path - cat $target_archive_file.tmp | xz > $target_archive_file + tmp_archive_file=$tmp_dir/$proj.tar + git archive --prefix=$proj-$release$rc.src/ -o $tmp_archive_file $tree_id . + tar -Af $tmp_archive_file $cmake_archive_file + xz < $tmp_archive_file > $target_dir/$(template_file $proj) popd done } From 22d7bee01a5af14e16e3ecc610e8e50e072385bc Mon Sep 17 00:00:00 2001 From: Aaron Puchert Date: Sun, 20 Mar 2022 20:59:06 +0100 Subject: [PATCH 258/316] [PPCISelLowering] Avoid emitting calls to __multi3, __muloti4 After D108936, @llvm.smul.with.overflow.i64 was lowered to __multi3 instead of __mulodi4, which also doesn't exist on PowerPC 32-bit, not even with compiler-rt. Block it as well so that we get inline code. Because libgcc doesn't have __muloti4, we block that as well. Fixes #54460. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D122090 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 + .../overflow-intrinsic-optimizations.ll | 12 ++ .../umulo-128-legalisation-lowering.ll | 169 +++++++++--------- .../PowerPC/urem-seteq-illegal-types.ll | 61 ++++--- 4 files changed, 127 insertions(+), 117 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index cbeae0ab03b83..6c9d43ad8c03f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1305,11 +1305,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); } + setLibcallName(RTLIB::MULO_I128, nullptr); if (!isPPC64) { // These libcalls are not available in 32-bit. setLibcallName(RTLIB::SHL_I128, nullptr); setLibcallName(RTLIB::SRL_I128, nullptr); setLibcallName(RTLIB::SRA_I128, nullptr); + setLibcallName(RTLIB::MUL_I128, nullptr); setLibcallName(RTLIB::MULO_I64, nullptr); } diff --git a/llvm/test/CodeGen/PowerPC/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/PowerPC/overflow-intrinsic-optimizations.ll index 83e9d8ee627e4..353dac3d2c951 100644 --- a/llvm/test/CodeGen/PowerPC/overflow-intrinsic-optimizations.ll +++ b/llvm/test/CodeGen/PowerPC/overflow-intrinsic-optimizations.ll @@ -1,8 +1,10 @@ ; RUN: llc %s -mtriple=powerpc -o - | FileCheck %s +; RUN: llc %s -mtriple=powerpc64 -o - | FileCheck %s define i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) { ; CHECK-LABEL: no__mulodi4 ; CHECK-NOT: bl __mulodi4 +; CHECK-NOT: bl __multi3 entry: %0 = sext i32 %a to i64 %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b) @@ -16,4 +18,14 @@ entry: ret i1 %7 } +define i1 @no__muloti4(i128 %a, i128 %b) { +; CHECK-LABEL: no__muloti4 +; CHECK-NOT: bl __muloti4 +entry: + %0 = call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %a, i128 %b) + %1 = extractvalue { i128, i1 } %0, 1 + ret i1 %1 +} + declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64) +declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128) diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll index 335946cb24de2..778edba2719a6 100644 --- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll +++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll @@ -32,110 +32,103 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 { ; ; PPC32-LABEL: muloti_test: ; PPC32: # %bb.0: # %start -; PPC32-NEXT: mflr 0 -; PPC32-NEXT: stw 0, 4(1) ; PPC32-NEXT: stwu 1, -64(1) -; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill -; PPC32-NEXT: mfcr 12 ; PPC32-NEXT: stw 26, 40(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 26, 7 -; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 28, 4 -; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 29, 8 -; PPC32-NEXT: mr 24, 3 -; PPC32-NEXT: li 3, 0 -; PPC32-NEXT: li 4, 0 -; PPC32-NEXT: li 7, 0 -; PPC32-NEXT: li 8, 0 +; PPC32-NEXT: mulhwu. 26, 7, 6 +; PPC32-NEXT: mcrf 1, 0 +; PPC32-NEXT: mfcr 12 +; PPC32-NEXT: cmpwi 7, 5, 0 +; PPC32-NEXT: cmpwi 2, 7, 0 +; PPC32-NEXT: stw 22, 24(1) # 4-byte Folded Spill +; PPC32-NEXT: mulhwu. 26, 5, 8 +; PPC32-NEXT: mcrf 5, 0 ; PPC32-NEXT: stw 23, 28(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 23, 5 +; PPC32-NEXT: crnor 28, 30, 10 +; PPC32-NEXT: stw 29, 52(1) # 4-byte Folded Spill +; PPC32-NEXT: cmpwi 2, 9, 0 +; PPC32-NEXT: mulhwu. 26, 3, 10 +; PPC32-NEXT: mcrf 6, 0 +; PPC32-NEXT: cmpwi 3, 3, 0 +; PPC32-NEXT: stw 24, 32(1) # 4-byte Folded Spill +; PPC32-NEXT: crnor 29, 10, 14 ; PPC32-NEXT: stw 25, 36(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 25, 9 +; PPC32-NEXT: mulhwu. 26, 9, 4 ; PPC32-NEXT: stw 27, 44(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 27, 6 +; PPC32-NEXT: crorc 28, 28, 6 +; PPC32-NEXT: stw 28, 48(1) # 4-byte Folded Spill +; PPC32-NEXT: crorc 20, 28, 22 ; PPC32-NEXT: stw 30, 56(1) # 4-byte Folded Spill -; PPC32-NEXT: mr 30, 10 -; PPC32-NEXT: stw 12, 24(1) -; PPC32-NEXT: bl __multi3 -; PPC32-NEXT: mulhwu. 9, 26, 27 -; PPC32-NEXT: mfcr 9 # cr0 -; PPC32-NEXT: cmpwi 2, 26, 0 -; PPC32-NEXT: stw 9, 20(1) -; PPC32-NEXT: cmpwi 3, 23, 0 -; PPC32-NEXT: crnor 12, 14, 10 -; PPC32-NEXT: cmpwi 4, 24, 0 -; PPC32-NEXT: mulhwu. 9, 23, 29 -; PPC32-NEXT: mcrf 5, 0 -; PPC32-NEXT: cmpwi 1, 25, 0 -; PPC32-NEXT: crnor 4, 6, 18 -; PPC32-NEXT: mulhwu. 9, 24, 30 -; PPC32-NEXT: mcrf 6, 0 -; PPC32-NEXT: mulhwu. 0, 25, 28 -; PPC32-NEXT: mcrf 7, 0 -; PPC32-NEXT: or. 0, 28, 24 -; PPC32-NEXT: mcrf 2, 0 -; PPC32-NEXT: or. 0, 29, 26 -; PPC32-NEXT: crnor 5, 2, 10 -; PPC32-NEXT: mullw 10, 26, 27 -; PPC32-NEXT: lwz 26, 20(1) -; PPC32-NEXT: mullw 9, 23, 29 -; PPC32-NEXT: add 9, 10, 9 -; PPC32-NEXT: mtcrf 128, 26 # cr0 -; PPC32-NEXT: crorc 6, 12, 2 -; PPC32-NEXT: crorc 20, 6, 22 -; PPC32-NEXT: mulhwu 7, 29, 27 -; PPC32-NEXT: add 9, 7, 9 -; PPC32-NEXT: cmplw 9, 7 -; PPC32-NEXT: crorc 21, 4, 26 -; PPC32-NEXT: cror 20, 20, 0 -; PPC32-NEXT: crorc 21, 21, 30 -; PPC32-NEXT: mullw 11, 25, 28 -; PPC32-NEXT: mullw 12, 24, 30 -; PPC32-NEXT: add 10, 12, 11 -; PPC32-NEXT: lwz 12, 24(1) -; PPC32-NEXT: lwz 26, 40(1) # 4-byte Folded Reload -; PPC32-NEXT: mulhwu 8, 28, 30 -; PPC32-NEXT: add 10, 8, 10 -; PPC32-NEXT: cmplw 10, 8 -; PPC32-NEXT: cror 21, 21, 0 -; PPC32-NEXT: cror 21, 5, 21 +; PPC32-NEXT: mulhwu 0, 6, 10 +; PPC32-NEXT: stw 12, 20(1) +; PPC32-NEXT: crorc 21, 29, 26 +; PPC32-NEXT: crorc 21, 21, 2 +; PPC32-NEXT: li 11, 0 +; PPC32-NEXT: mullw 26, 5, 10 +; PPC32-NEXT: addc 0, 26, 0 +; PPC32-NEXT: mulhwu 29, 5, 10 +; PPC32-NEXT: addze 29, 29 +; PPC32-NEXT: mullw 23, 5, 8 +; PPC32-NEXT: mullw 22, 7, 6 +; PPC32-NEXT: mulhwu 30, 6, 9 +; PPC32-NEXT: mulhwu 12, 5, 9 +; PPC32-NEXT: mulhwu 28, 8, 6 +; PPC32-NEXT: mullw 25, 6, 9 +; PPC32-NEXT: mullw 24, 5, 9 +; PPC32-NEXT: mullw 5, 9, 4 +; PPC32-NEXT: add 9, 22, 23 +; PPC32-NEXT: add 9, 28, 9 +; PPC32-NEXT: cmplw 1, 9, 28 +; PPC32-NEXT: cror 20, 20, 4 +; PPC32-NEXT: mullw 23, 3, 10 +; PPC32-NEXT: add 26, 23, 5 +; PPC32-NEXT: addc 5, 25, 0 +; PPC32-NEXT: addze 30, 30 +; PPC32-NEXT: or. 3, 4, 3 +; PPC32-NEXT: mulhwu 27, 4, 10 +; PPC32-NEXT: mcrf 1, 0 +; PPC32-NEXT: addc 3, 29, 30 +; PPC32-NEXT: add 26, 27, 26 +; PPC32-NEXT: cmplw 6, 26, 27 +; PPC32-NEXT: cror 21, 21, 24 +; PPC32-NEXT: mullw 0, 4, 10 +; PPC32-NEXT: or. 4, 8, 7 +; PPC32-NEXT: addze 4, 11 +; PPC32-NEXT: addc 7, 24, 3 +; PPC32-NEXT: crnor 22, 2, 6 +; PPC32-NEXT: mullw 28, 8, 6 +; PPC32-NEXT: adde 8, 12, 4 +; PPC32-NEXT: addc 3, 0, 28 +; PPC32-NEXT: adde 9, 26, 9 +; PPC32-NEXT: addc 4, 7, 3 +; PPC32-NEXT: adde 3, 8, 9 +; PPC32-NEXT: cror 21, 22, 21 +; PPC32-NEXT: cmplw 4, 7 +; PPC32-NEXT: cmplw 1, 3, 8 +; PPC32-NEXT: lwz 12, 20(1) ; PPC32-NEXT: cror 20, 21, 20 -; PPC32-NEXT: mullw 0, 29, 27 +; PPC32-NEXT: crandc 21, 4, 6 +; PPC32-NEXT: crand 22, 6, 0 +; PPC32-NEXT: cror 21, 22, 21 +; PPC32-NEXT: crnor 20, 20, 21 +; PPC32-NEXT: li 7, 1 +; PPC32-NEXT: mullw 6, 6, 10 +; PPC32-NEXT: bc 12, 20, .LBB0_1 +; PPC32-NEXT: b .LBB0_2 +; PPC32-NEXT: .LBB0_1: # %start +; PPC32-NEXT: li 7, 0 +; PPC32-NEXT: .LBB0_2: # %start ; PPC32-NEXT: mtcrf 32, 12 # cr2 ; PPC32-NEXT: mtcrf 16, 12 # cr3 -; PPC32-NEXT: mtcrf 8, 12 # cr4 -; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload -; PPC32-NEXT: mullw 7, 28, 30 -; PPC32-NEXT: addc 7, 7, 0 -; PPC32-NEXT: adde 11, 10, 9 -; PPC32-NEXT: addc 9, 4, 7 -; PPC32-NEXT: adde 8, 3, 11 -; PPC32-NEXT: cmplw 6, 9, 4 -; PPC32-NEXT: cmplw 8, 3 -; PPC32-NEXT: crand 22, 2, 24 -; PPC32-NEXT: crandc 23, 0, 2 -; PPC32-NEXT: cror 22, 22, 23 -; PPC32-NEXT: crnor 20, 20, 22 -; PPC32-NEXT: li 3, 1 -; PPC32-NEXT: bc 12, 20, .LBB0_2 -; PPC32-NEXT: # %bb.1: # %start -; PPC32-NEXT: ori 7, 3, 0 -; PPC32-NEXT: b .LBB0_3 -; PPC32-NEXT: .LBB0_2: # %start -; PPC32-NEXT: li 7, 0 -; PPC32-NEXT: .LBB0_3: # %start -; PPC32-NEXT: mr 3, 8 -; PPC32-NEXT: mr 4, 9 ; PPC32-NEXT: lwz 30, 56(1) # 4-byte Folded Reload +; PPC32-NEXT: lwz 29, 52(1) # 4-byte Folded Reload ; PPC32-NEXT: lwz 28, 48(1) # 4-byte Folded Reload ; PPC32-NEXT: lwz 27, 44(1) # 4-byte Folded Reload +; PPC32-NEXT: lwz 26, 40(1) # 4-byte Folded Reload ; PPC32-NEXT: lwz 25, 36(1) # 4-byte Folded Reload ; PPC32-NEXT: lwz 24, 32(1) # 4-byte Folded Reload ; PPC32-NEXT: lwz 23, 28(1) # 4-byte Folded Reload -; PPC32-NEXT: lwz 0, 68(1) +; PPC32-NEXT: lwz 22, 24(1) # 4-byte Folded Reload ; PPC32-NEXT: addi 1, 1, 64 -; PPC32-NEXT: mtlr 0 ; PPC32-NEXT: blr start: %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 diff --git a/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll index ef73fa686b3c6..65ea57eaf3b9f 100644 --- a/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll @@ -208,43 +208,46 @@ define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind { define i1 @test_urem_oversized(i66 %X) nounwind { ; PPC-LABEL: test_urem_oversized: ; PPC: # %bb.0: -; PPC-NEXT: mflr 0 -; PPC-NEXT: stw 0, 4(1) -; PPC-NEXT: stwu 1, -16(1) -; PPC-NEXT: mr 6, 5 -; PPC-NEXT: mr 5, 4 -; PPC-NEXT: mr 4, 3 -; PPC-NEXT: lis 3, 12057 -; PPC-NEXT: lis 7, -12795 -; PPC-NEXT: ori 9, 3, 37186 -; PPC-NEXT: ori 10, 7, 40665 -; PPC-NEXT: li 3, 0 -; PPC-NEXT: li 7, 0 -; PPC-NEXT: li 8, 2 -; PPC-NEXT: bl __multi3 -; PPC-NEXT: rotlwi 7, 6, 31 -; PPC-NEXT: lis 3, -5526 -; PPC-NEXT: rlwimi 7, 5, 31, 0, 0 -; PPC-NEXT: rotlwi 5, 5, 31 -; PPC-NEXT: rlwimi 5, 4, 31, 0, 0 -; PPC-NEXT: ori 3, 3, 61135 -; PPC-NEXT: cmplwi 1, 5, 13 -; PPC-NEXT: cmplw 7, 3 -; PPC-NEXT: rlwinm 4, 4, 31, 31, 31 +; PPC-NEXT: lis 6, -12795 +; PPC-NEXT: ori 6, 6, 40665 +; PPC-NEXT: mulhwu 7, 5, 6 +; PPC-NEXT: lis 9, 12057 +; PPC-NEXT: ori 9, 9, 37186 +; PPC-NEXT: mullw 11, 4, 6 +; PPC-NEXT: addc 7, 11, 7 +; PPC-NEXT: lis 11, -5526 +; PPC-NEXT: ori 11, 11, 61135 +; PPC-NEXT: mulhwu 8, 4, 6 +; PPC-NEXT: addze 8, 8 +; PPC-NEXT: mulhwu 10, 5, 9 +; PPC-NEXT: mullw 4, 4, 9 +; PPC-NEXT: mullw 9, 5, 9 +; PPC-NEXT: addc 7, 9, 7 +; PPC-NEXT: addze 9, 10 +; PPC-NEXT: rotlwi 10, 7, 31 +; PPC-NEXT: mullw 3, 3, 6 +; PPC-NEXT: mullw 6, 5, 6 +; PPC-NEXT: slwi 5, 5, 1 +; PPC-NEXT: add 3, 5, 3 +; PPC-NEXT: rotlwi 5, 6, 31 +; PPC-NEXT: rlwimi 5, 7, 31, 0, 0 +; PPC-NEXT: add 7, 8, 9 +; PPC-NEXT: add 4, 4, 7 +; PPC-NEXT: add 3, 4, 3 +; PPC-NEXT: rlwimi 10, 3, 31, 0, 0 +; PPC-NEXT: cmplw 5, 11 +; PPC-NEXT: cmplwi 1, 10, 13 +; PPC-NEXT: rlwinm 3, 3, 31, 31, 31 ; PPC-NEXT: crand 20, 6, 0 ; PPC-NEXT: crandc 21, 4, 6 -; PPC-NEXT: rlwimi. 4, 6, 1, 30, 30 +; PPC-NEXT: rlwimi. 3, 6, 1, 30, 30 ; PPC-NEXT: cror 20, 20, 21 ; PPC-NEXT: crnand 20, 2, 20 ; PPC-NEXT: li 3, 1 ; PPC-NEXT: bc 12, 20, .LBB5_1 -; PPC-NEXT: b .LBB5_2 +; PPC-NEXT: blr ; PPC-NEXT: .LBB5_1: ; PPC-NEXT: li 3, 0 -; PPC-NEXT: .LBB5_2: -; PPC-NEXT: lwz 0, 20(1) -; PPC-NEXT: addi 1, 1, 16 -; PPC-NEXT: mtlr 0 ; PPC-NEXT: blr ; ; PPC64LE-LABEL: test_urem_oversized: From db07d9f098b3c8f180c1f3d2d21b509bc6e94113 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 13:40:48 -0700 Subject: [PATCH 259/316] [MC] Fix llvm_unreachable when a STB_GNU_UNIQUE symbol needs a relocation STB_GNU_UNIQUE should be treated in a way similar to STB_GLOBAL. This fixes an "Invalid Binding" failure in an LLVM_ENABLE_ASSERTIONS=on build for source files like glibc elf/tst-unique1mod1.c . This bug has been benign so far because (a) Clang does not produce %gnu_unique_object by itself (b) a non-assertion build likely picks the STB_GLOBAL code path anyway. (cherry picked from commit 6bdad85b26fbfd064772f2b382b27fbbf0b0afce) --- llvm/lib/MC/ELFObjectWriter.cpp | 1 + llvm/test/MC/ELF/gnu-unique.s | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index 883735fcc293a..6fd2f7e7a7185 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -1336,6 +1336,7 @@ bool ELFObjectWriter::shouldRelocateWithSymbol(const MCAssembler &Asm, // can update it. return true; case ELF::STB_GLOBAL: + case ELF::STB_GNU_UNIQUE: // Global ELF symbols can be preempted by the dynamic linker. The relocation // has to point to the symbol for a reason analogous to the STB_WEAK case. return true; diff --git a/llvm/test/MC/ELF/gnu-unique.s b/llvm/test/MC/ELF/gnu-unique.s index 8948b33b9afbd..21609365d5277 100644 --- a/llvm/test/MC/ELF/gnu-unique.s +++ b/llvm/test/MC/ELF/gnu-unique.s @@ -1,5 +1,7 @@ # RUN: llvm-mc -triple=x86_64 %s | FileCheck %s --check-prefix=ASM -# RUN: llvm-mc -filetype=obj -triple=x86_64 %s | llvm-readelf -h -s - | FileCheck %s --check-prefix=OBJ +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t +# RUN: llvm-readelf -h -s %t | FileCheck %s --check-prefix=OBJ +# RUN: llvm-objdump -d -r --no-show-raw-insn %t | FileCheck %s --check-prefix=DISASM # ASM: .type unique,@gnu_unique_object @@ -7,6 +9,13 @@ # OBJ: Type Bind Vis Ndx Name # OBJ: OBJECT UNIQUE DEFAULT [[#]] unique +# DISASM-LABEL: <.text>: +# DISASM-NEXT: movl $1, 0 +## unique has a non-local binding. Reference unique instead of .data +# DISASM-NEXT: R_X86_64_32S unique + + movl $1, unique + .data .globl unique .type unique, @gnu_unique_object From a4681df0202cd4967ee499c6ee640b0d09263971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 30 Mar 2022 13:34:02 +0300 Subject: [PATCH 260/316] [libcxx] [test] Avoid spurious test breakage in clang-cl-dll configs with newer CMake The pointer.volatile.pass.cpp test was already marked as XFAIL for mingw-dll (for reasons explained in the comment above it). The same issue also appears in clang-cl-dll when built with newer CMake versions. (It didn't appear with older versions of CMake, as CMake built the library with the clang-cl flag `-std:c++latest` when we've requested C++ 20 - which practically built it in c++2b mode with current clang versions. With current versions of CMake, it passes `-std:c++20` instead.) As it succeeds/fails dependent on factors we don't directly control, mark it as UNSUPPORTED instead of XFAIL. Differential Revision: https://reviews.llvm.org/D122718 (cherry picked from commit b048397db8027fedf9380e7cf9213239d558fa29) --- .../pointer.volatile.pass.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp index 392e50d7f3f97..0538dcd4ac142 100644 --- a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.inserters.arithmetic/pointer.volatile.pass.cpp @@ -10,12 +10,22 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 -// This test fails on MinGW DLL configurations, due to +// This test fails in Windows DLL configurations, due to // __exclude_from_explicit_instantiation__ not behaving as it should in // combination with dllimport (https://llvm.org/PR41018), in combination // with running tests in c++2b mode while building the library in c++20 mode. -// (If the library was built in c++2b mode, this test would succeed.) -// XFAIL: target={{.+}}-windows-gnu && windows-dll +// +// If the library was built in c++2b mode, this test would succeed. +// +// Older CMake passed -std:c++latest to set C++ 20 mode on clang-cl, which +// hid this issue. With newer CMake versions, it passes -std:c++20 which +// makes this fail. +// +// Marking as UNSUPPORTED instead of XFAIL to avoid spurious failures/successes +// depending on the version of CMake used. +// TODO: Remove this when the library is built in c++2b mode. +// +// UNSUPPORTED: windows-dll // template > // class basic_ostream; From e9b26b5b2a709156f6d68927fa01c0a0540ea625 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 18 Mar 2022 18:32:23 -0700 Subject: [PATCH 261/316] [RISCV] Add test case for miscompile caused by treating ANY_EXTEND of constants as SIGN_EXTEND. The code that inserts AssertZExt based on predecessor information assumes constants are zero extended for phi incoming values this allows AssertZExt to be created in blocks consuming a Phi. SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV. The code that creates phi incoming values in the predecessors creates an any_extend for the constants which then gets treated as a sext by getNode. This makes the AssertZExt incorrect and can cause zexts to be incorrectly removed. This bug was introduced by D105918 Differential Revision: https://reviews.llvm.org/D122052 (cherry picked from commit 268371cf7b9f6fd3b9320564f1abd3615eecd2e8) --- llvm/test/CodeGen/RISCV/aext-to-sext.ll | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll index df90981508a9b..0ffdf085109ec 100644 --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -75,3 +75,36 @@ bb: bar: ret i32 %b } + +; The code that inserts AssertZExt based on predecessor information assumes +; constants are zero extended for phi incoming values so an AssertZExt is +; created in 'merge' allowing the zext to be removed. +; SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV. +; The code that creates phi incoming values in the predecessors creates an +; any_extend for the constants which then gets treated as a sext by getNode. +; This means the zext was not safe to remove. +define i64 @miscompile(i32 %c) { +; RV64I-LABEL: miscompile: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: li a0, -1 +; RV64I-NEXT: beqz a1, .LBB2_2 +; RV64I-NEXT: # %bb.1: # %merge +; RV64I-NEXT: ret +; RV64I-NEXT: .LBB2_2: # %iffalse +; RV64I-NEXT: li a0, -2 +; RV64I-NEXT: ret + %a = icmp ne i32 %c, 0 + br i1 %a, label %iftrue, label %iffalse + +iftrue: + br label %merge + +iffalse: + br label %merge + +merge: + %b = phi i32 [-1, %iftrue], [-2, %iffalse] + %d = zext i32 %b to i64 + ret i64 %d +} From 5b9dd016bec7652c311266055e5f89342cb90e60 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 18 Mar 2022 18:33:30 -0700 Subject: [PATCH 262/316] [SelectionDAG][RISCV] Make RegsForValue::getCopyToRegs explicitly zero_extend constants. ComputePHILiveOutRegInfo assumes that constant incoming values to Phis will be zero extended if they aren't a legal type. To guarantee that we should zero_extend rather than any_extend constants. This fixes a bug for RISCV where any_extend of constants can be treated as a sign_extend. Differential Revision: https://reviews.llvm.org/D122053 (cherry picked from commit 4eb59f017903c8b70b5c5aad892bdc73516a6766) --- .../SelectionDAG/SelectionDAGBuilder.cpp | 5 ++++- llvm/test/CodeGen/RISCV/aext-to-sext.ll | 20 ++++++++++++------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 01230a36e744a..c61716ba16761 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -926,7 +926,10 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, CallConv.getValue(), RegVTs[Value]) : RegVTs[Value]; - if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) + // We need to zero extend constants that are liveout to match assumptions + // in FunctionLoweringInfo::ComputePHILiveOutRegInfo. + if (ExtendKind == ISD::ANY_EXTEND && + (TLI.isZExtFree(Val, RegisterVT) || isa(Val))) ExtendKind = ISD::ZERO_EXTEND; getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll index 0ffdf085109ec..b5455973c7840 100644 --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -80,19 +80,25 @@ bar: ; constants are zero extended for phi incoming values so an AssertZExt is ; created in 'merge' allowing the zext to be removed. ; SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV. -; The code that creates phi incoming values in the predecessors creates an -; any_extend for the constants which then gets treated as a sext by getNode. -; This means the zext was not safe to remove. +; This code used to miscompile because the code that creates phi incoming values +; in the predecessors created any_extend for the constants which then gets +; treated as a sext by getNode. This made the removal of the zext incorrect. +; SelectionDAGBuilder now creates a zero_extend instead of an any_extend to +; match the assumption. +; FIXME: RISCV would prefer constant inputs to phis to be sign extended. define i64 @miscompile(i32 %c) { ; RV64I-LABEL: miscompile: ; RV64I: # %bb.0: -; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: beqz a0, .LBB2_2 +; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: li a0, -1 -; RV64I-NEXT: beqz a1, .LBB2_2 -; RV64I-NEXT: # %bb.1: # %merge +; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB2_2: # %iffalse -; RV64I-NEXT: li a0, -2 +; RV64I-NEXT: li a0, 1 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, -2 ; RV64I-NEXT: ret %a = icmp ne i32 %c, 0 br i1 %a, label %iftrue, label %iffalse From c9ec4902c3e32ce329db26e3f42c5e93c3135e57 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 00:58:14 -0700 Subject: [PATCH 263/316] [llvm-objdump][test] dos2unix some files (cherry picked from commit 423af54cbef7b90199e01162dcea6d3e62539e8c) --- .../llvm-objdump/ELF/private-headers.test | 130 ++-- .../llvm-objdump/ELF/program-headers.test | 648 +++++++++--------- 2 files changed, 389 insertions(+), 389 deletions(-) diff --git a/llvm/test/tools/llvm-objdump/ELF/private-headers.test b/llvm/test/tools/llvm-objdump/ELF/private-headers.test index bf18f5810c571..eefdc8440385c 100644 --- a/llvm/test/tools/llvm-objdump/ELF/private-headers.test +++ b/llvm/test/tools/llvm-objdump/ELF/private-headers.test @@ -1,65 +1,65 @@ -## Check that with ELF input --private-headers outputs the program header, -## dynamic section and version definitions. -# RUN: yaml2obj %s -o %t -# RUN: llvm-objdump --private-headers %t | FileCheck %s - -# CHECK: Program Header: -# CHECK-NEXT: LOAD off 0x00000000000000b0 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# CHECK-NEXT: filesz 0x000000000000003d memsz 0x000000000000003d flags --- -# CHECK-NEXT: DYNAMIC off 0x00000000000000cd vaddr 0x000000000000101d paddr 0x000000000000101d align 2**0 -# CHECK-NEXT: filesz 0x0000000000000020 memsz 0x0000000000000020 flags --- -# CHECK: Dynamic Section: -# CHECK-NEXT: NEEDED bar -# CHECK: Version definitions: -# CHECK-NEXT: 1 0x01 0x075bcd15 foo -# CHECK-NEXT: 2 0x02 0x3ade68b1 VERSION_1 -# CHECK-NEXT: VERSION_2 - ---- !ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB - Type: ET_EXEC - Machine: EM_X86_64 -Sections: - - Name: .dynstr - Type: SHT_STRTAB - Address: 0x1000 - Content: "0062617200666F6F0056455253494F4E5F320056455253494F4E5F3100" - # Content is: bar, foo, VERSION_2, VERSION_1 - - Name: .dynamic - Type: SHT_DYNAMIC - Flags: [ SHF_ALLOC ] - Entries: - - Tag: DT_NEEDED - Value: 0x1 - - Tag: DT_NULL - Value: 0x0 - - Name: .gnu.version_d - Type: SHT_GNU_verdef - Entries: - - Version: 1 - Flags: 1 - VersionNdx: 1 - Hash: 123456789 - Names: - - foo - - Version: 1 - Flags: 2 - VersionNdx: 2 - Hash: 987654321 - Names: - - VERSION_1 - - VERSION_2 -ProgramHeaders: - - Type: PT_LOAD - VAddr: 0x1000 - FirstSec: .dynstr - LastSec: .dynamic - - Type: PT_DYNAMIC - VAddr: 0x101D - FirstSec: .dynamic - LastSec: .dynamic -DynamicSymbols: - - Name: bar - Binding: STB_GLOBAL +## Check that with ELF input --private-headers outputs the program header, +## dynamic section and version definitions. +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --private-headers %t | FileCheck %s + +# CHECK: Program Header: +# CHECK-NEXT: LOAD off 0x00000000000000b0 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# CHECK-NEXT: filesz 0x000000000000003d memsz 0x000000000000003d flags --- +# CHECK-NEXT: DYNAMIC off 0x00000000000000cd vaddr 0x000000000000101d paddr 0x000000000000101d align 2**0 +# CHECK-NEXT: filesz 0x0000000000000020 memsz 0x0000000000000020 flags --- +# CHECK: Dynamic Section: +# CHECK-NEXT: NEEDED bar +# CHECK: Version definitions: +# CHECK-NEXT: 1 0x01 0x075bcd15 foo +# CHECK-NEXT: 2 0x02 0x3ade68b1 VERSION_1 +# CHECK-NEXT: VERSION_2 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .dynstr + Type: SHT_STRTAB + Address: 0x1000 + Content: "0062617200666F6F0056455253494F4E5F320056455253494F4E5F3100" + # Content is: bar, foo, VERSION_2, VERSION_1 + - Name: .dynamic + Type: SHT_DYNAMIC + Flags: [ SHF_ALLOC ] + Entries: + - Tag: DT_NEEDED + Value: 0x1 + - Tag: DT_NULL + Value: 0x0 + - Name: .gnu.version_d + Type: SHT_GNU_verdef + Entries: + - Version: 1 + Flags: 1 + VersionNdx: 1 + Hash: 123456789 + Names: + - foo + - Version: 1 + Flags: 2 + VersionNdx: 2 + Hash: 987654321 + Names: + - VERSION_1 + - VERSION_2 +ProgramHeaders: + - Type: PT_LOAD + VAddr: 0x1000 + FirstSec: .dynstr + LastSec: .dynamic + - Type: PT_DYNAMIC + VAddr: 0x101D + FirstSec: .dynamic + LastSec: .dynamic +DynamicSymbols: + - Name: bar + Binding: STB_GLOBAL diff --git a/llvm/test/tools/llvm-objdump/ELF/program-headers.test b/llvm/test/tools/llvm-objdump/ELF/program-headers.test index 4c61e974d6db5..1e11334d7172f 100644 --- a/llvm/test/tools/llvm-objdump/ELF/program-headers.test +++ b/llvm/test/tools/llvm-objdump/ELF/program-headers.test @@ -1,324 +1,324 @@ -## Check that program headers are output correctly - -# RUN: yaml2obj --docnum=1 -DBITS=32 -DMACHINE=EM_386 %s -o %t32.elf -# RUN: llvm-objdump --private-headers %t32.elf | FileCheck %s --check-prefixes=ELF32 - -# ELF32: Program Header: -# ELF32-NEXT: PHDR off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags -w- -# ELF32-NEXT: PHDR off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0 -# ELF32-NEXT: filesz 0x00000007 memsz 0x00000007 flags --x -# ELF32-NEXT: UNKNOWN off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0 -# ELF32-NEXT: filesz 0x00000007 memsz 0x00000007 flags --x -# ELF32-NEXT: DYNAMIC off 0x00000324 vaddr 0x00006000 paddr 0x00006000 align 2**0 -# ELF32-NEXT: filesz 0x00000010 memsz 0x00000010 flags rwx -# ELF32-NEXT: INTERP off 0x0000031e vaddr 0x00003000 paddr 0x00003000 align 2**0 -# ELF32-NEXT: filesz 0x00000004 memsz 0x00000004 flags rw- -# ELF32-NEXT: NOTE off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000001 memsz 0x00000001 flags --- -# ELF32-NEXT: TLS off 0x00000322 vaddr 0x00004000 paddr 0x00004000 align 2**0 -# ELF32-NEXT: filesz 0x00000001 memsz 0x00000001 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT:EH_FRAME off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: STACK off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: RELRO off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT:PROPERTY off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: OPENBSD_RANDOMIZE off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: OPENBSD_WXNEEDED off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: OPENBSD_BOOTDATA off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 -# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- -# ELF32-EMPTY: - -# RUN: yaml2obj --docnum=1 -DBITS=64 -DMACHINE=EM_X86_64 %s -o %t64.elf -# RUN: llvm-objdump --private-headers %t64.elf | FileCheck %s --check-prefixes=ELF64 - -# ELF64: Program Header: -# ELF64-NEXT: PHDR off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags -w- -# ELF64-NEXT: PHDR off 0x000000000000054b vaddr 0x0000000000002000 paddr 0x0000000000002000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000007 memsz 0x0000000000000007 flags --x -# ELF64-NEXT: UNKNOWN off 0x000000000000054b vaddr 0x0000000000002000 paddr 0x0000000000002000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000007 memsz 0x0000000000000007 flags --x -# ELF64-NEXT: DYNAMIC off 0x0000000000000558 vaddr 0x0000000000006000 paddr 0x0000000000006000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000020 memsz 0x0000000000000020 flags rwx -# ELF64-NEXT: INTERP off 0x0000000000000552 vaddr 0x0000000000003000 paddr 0x0000000000003000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000004 memsz 0x0000000000000004 flags rw- -# ELF64-NEXT: NOTE off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000001 memsz 0x0000000000000001 flags --- -# ELF64-NEXT: TLS off 0x0000000000000556 vaddr 0x0000000000004000 paddr 0x0000000000004000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000001 memsz 0x0000000000000001 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT:EH_FRAME off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: STACK off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: RELRO off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: PROPERTY off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: OPENBSD_RANDOMIZE off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: OPENBSD_WXNEEDED off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: OPENBSD_BOOTDATA off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 -# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- -# ELF64-EMPTY: - ---- !ELF -FileHeader: - Class: ELFCLASS[[BITS]] - Data: ELFDATA2LSB - Type: ET_EXEC - Machine: [[MACHINE]] -Sections: - - Name: .foo.begin - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC ] - Address: 0x1000 - Size: 0x1 - - Name: .foo.end - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC ] - Size: 0x2 - - Name: .bar.begin - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC ] - Address: 0x2000 - Size: 0x3 - - Name: .bar.end - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC ] - Size: 0x4 - - Name: .interp - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC ] - Address: 0x3000 - Content: "41424300" ## "ABC" - - Name: .tls - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC, SHF_TLS ] - Address: 0x4000 - Size: 0x1 - - Name: .unused - Type: SHT_PROGBITS - Flags: [ SHF_ALLOC, SHF_TLS ] - Address: 0x5000 - Size: 0x1 - - Name: .dynamic - Type: SHT_DYNAMIC - Flags: [ SHF_ALLOC ] - Address: 0x6000 - Entries: - - Tag: DT_NEEDED - Value: 0x1 - - Tag: DT_NULL - Value: 0x0 -ProgramHeaders: -## Case 1: an arbitrary segment with sections. - - Type: PT_PHDR - Flags: [ PF_W ] - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 2: another segment with different sections. - - Type: PT_PHDR - Flags: [ PF_X ] - VAddr: 0x2000 - FirstSec: .bar.begin - LastSec: .bar.end -## Case 3: the PT_NULL segment. - - Type: PT_NULL - Flags: [ PF_X ] - VAddr: 0x2000 - FirstSec: .bar.begin - LastSec: .bar.end -## Case 4: the PT_DYNAMIC segment. - - Type: PT_DYNAMIC - Flags: [ PF_R, PF_W, PF_X ] - VAddr: 0x6000 - FirstSec: .dynamic - LastSec: .dynamic -## Case 5: the PT_INTERP segment. - - Type: PT_INTERP - Flags: [ PF_R, PF_W ] - VAddr: 0x3000 - FirstSec: .interp - LastSec: .interp -## Case 6: the PT_NOTE segment. - - Type: PT_NOTE - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 7: the PT_SHLIB segment. - - Type: PT_SHLIB - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.begin -## Case 8: the PT_TLS segment. - - Type: PT_TLS - VAddr: 0x4000 - FirstSec: .tls - LastSec: .tls -## Case 9: the PT_LOOS segment. - - Type: 0x60000000 ## PT_LOOS - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 10: the PT_GNU_EH_FRAME segment. - - Type: PT_GNU_EH_FRAME - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 11: the PT_SUNW_UNWIND segment. - - Type: 0x6464e550 ## PT_SUNW_UNWIND - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 12: the PT_GNU_STACK segment. - - Type: PT_GNU_STACK - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 13: the PT_GNU_RELRO segment. - - Type: PT_GNU_RELRO - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 14: the PT_GNU_PROPERTY segment. - - Type: PT_GNU_PROPERTY - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 15: the PT_OPENBSD_RANDOMIZE segment. - - Type: 0x65a3dbe6 ## PT_OPENBSD_RANDOMIZE - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 16: the PT_OPENBSD_WXNEEDED segment. - - Type: 0x65a3dbe7 ## PT_OPENBSD_WXNEEDED - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 17: the PT_OPENBSD_BOOTDATA segment. - - Type: 0x65a41be6 ## PT_OPENBSD_BOOTDATA - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 18: the PT_HIOS segment. - - Type: 0x6fffffff ## PT_HIOS - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 19: the PT_LOPROC/PT_ARM_ARCHEXT/PT_MIPS_REGINFO segment. - - Type: 0x70000000 ## PT_LOPROC/PT_ARM_ARCHEXT/PT_MIPS_REGINFO - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 20: the PT_ARM_EXIDX/PT_MIPS_RTPROC segment. - - Type: 0x70000001 ## PT_ARM_EXIDX, PT_MIPS_RTPROC - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 20: the PT_MIPS_OPTIONS segment. - - Type: 0x70000002 ## PT_MIPS_OPTIONS - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 21: the PT_MIPS_ABIFLAGS segment. - - Type: 0x70000003 ## PT_MIPS_ABIFLAGS - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end -## Case 22: the PT_HIPROC segment. - - Type: 0x7fffffff ## PT_HIPROC - VAddr: 0x1000 - FirstSec: .foo.begin - LastSec: .foo.end - -## Check we report an error / warning when we are unable to read program headers. -## Case A: the e_phentsize field is invalid. -# RUN: yaml2obj --docnum=2 -DPHENTSIZE=1 %s -o %t.phdr.err -# RUN: not llvm-objdump --private-headers %t.phdr.err 2>&1 | \ -# RUN: FileCheck %s -DFILE=%t.phdr.err --check-prefix=PHENTSIZE - -# PHENTSIZE: Program Header: -# PHENTSIZE-NEXT: warning: '[[FILE]]': unable to read program headers: invalid e_phentsize: 1 -# PHENTSIZE-NEXT: error: '[[FILE]]': invalid e_phentsize: 1 - ---- !ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB - Type: ET_EXEC - EPhEntSize: [[PHENTSIZE=]] - EPhOff: [[PHOFF=]] -Sections: - - Name: .foo - Type: SHT_PROGBITS -ProgramHeaders: - - Type: PT_PHDR - FirstSec: .foo - LastSec: .foo - -## Case B: the value of the e_phoff field is invalid. - -## Check that we do not report a warning when the program header table ends right before the end of the file. -## 0x160 + size of headers (56) == file size. -# RUN: yaml2obj --docnum=2 -DPHOFF=0x160 %s -o %t.phdr.no.err2 -# RUN: llvm-objdump %t.phdr.no.err2 --private-headers 2>&1 | FileCheck %s --implicit-check-not=warning: - -## Check we report a warning / error when e_phoff goes 1 byte past the end of the file. -# RUN: yaml2obj --docnum=2 -DPHOFF=0x161 %s -o %t.phdr.err2 -# RUN: not llvm-objdump --private-headers %t.phdr.err2 2>&1 | \ -# RUN: FileCheck %s -DFILE=%t.phdr.err2 --check-prefix=PHOFF -DOFF=0x161 - -# PHOFF: Program Header: -# PHOFF-NEXT: warning: '[[FILE]]': unable to read program headers: program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 -# PHOFF-NEXT: error: '[[FILE]]': program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 - - -## Check we report a warning / error when the value of e_phoff is so large that -## e_phoff + e_phnum * e_phentsize > UINT64_MAX. -# RUN: yaml2obj --docnum=2 -DPHOFF=0xffffffffffffffff %s -o %t.phdr.err3 -# RUN: not llvm-objdump --private-headers %t.phdr.err3 2>&1 | \ -# RUN: FileCheck %s -DFILE=%t.phdr.err3 --check-prefix=PHOFF -DOFF=0xffffffffffffffff +## Check that program headers are output correctly + +# RUN: yaml2obj --docnum=1 -DBITS=32 -DMACHINE=EM_386 %s -o %t32.elf +# RUN: llvm-objdump --private-headers %t32.elf | FileCheck %s --check-prefixes=ELF32 + +# ELF32: Program Header: +# ELF32-NEXT: PHDR off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags -w- +# ELF32-NEXT: PHDR off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0 +# ELF32-NEXT: filesz 0x00000007 memsz 0x00000007 flags --x +# ELF32-NEXT: UNKNOWN off 0x00000317 vaddr 0x00002000 paddr 0x00002000 align 2**0 +# ELF32-NEXT: filesz 0x00000007 memsz 0x00000007 flags --x +# ELF32-NEXT: DYNAMIC off 0x00000324 vaddr 0x00006000 paddr 0x00006000 align 2**0 +# ELF32-NEXT: filesz 0x00000010 memsz 0x00000010 flags rwx +# ELF32-NEXT: INTERP off 0x0000031e vaddr 0x00003000 paddr 0x00003000 align 2**0 +# ELF32-NEXT: filesz 0x00000004 memsz 0x00000004 flags rw- +# ELF32-NEXT: NOTE off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000001 memsz 0x00000001 flags --- +# ELF32-NEXT: TLS off 0x00000322 vaddr 0x00004000 paddr 0x00004000 align 2**0 +# ELF32-NEXT: filesz 0x00000001 memsz 0x00000001 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT:EH_FRAME off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: STACK off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: RELRO off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT:PROPERTY off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: OPENBSD_RANDOMIZE off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: OPENBSD_WXNEEDED off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: OPENBSD_BOOTDATA off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-NEXT: UNKNOWN off 0x00000314 vaddr 0x00001000 paddr 0x00001000 align 2**0 +# ELF32-NEXT: filesz 0x00000003 memsz 0x00000003 flags --- +# ELF32-EMPTY: + +# RUN: yaml2obj --docnum=1 -DBITS=64 -DMACHINE=EM_X86_64 %s -o %t64.elf +# RUN: llvm-objdump --private-headers %t64.elf | FileCheck %s --check-prefixes=ELF64 + +# ELF64: Program Header: +# ELF64-NEXT: PHDR off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags -w- +# ELF64-NEXT: PHDR off 0x000000000000054b vaddr 0x0000000000002000 paddr 0x0000000000002000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000007 memsz 0x0000000000000007 flags --x +# ELF64-NEXT: UNKNOWN off 0x000000000000054b vaddr 0x0000000000002000 paddr 0x0000000000002000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000007 memsz 0x0000000000000007 flags --x +# ELF64-NEXT: DYNAMIC off 0x0000000000000558 vaddr 0x0000000000006000 paddr 0x0000000000006000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000020 memsz 0x0000000000000020 flags rwx +# ELF64-NEXT: INTERP off 0x0000000000000552 vaddr 0x0000000000003000 paddr 0x0000000000003000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000004 memsz 0x0000000000000004 flags rw- +# ELF64-NEXT: NOTE off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000001 memsz 0x0000000000000001 flags --- +# ELF64-NEXT: TLS off 0x0000000000000556 vaddr 0x0000000000004000 paddr 0x0000000000004000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000001 memsz 0x0000000000000001 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT:EH_FRAME off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: STACK off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: RELRO off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: PROPERTY off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: OPENBSD_RANDOMIZE off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: OPENBSD_WXNEEDED off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: OPENBSD_BOOTDATA off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-NEXT: UNKNOWN off 0x0000000000000548 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2**0 +# ELF64-NEXT: filesz 0x0000000000000003 memsz 0x0000000000000003 flags --- +# ELF64-EMPTY: + +--- !ELF +FileHeader: + Class: ELFCLASS[[BITS]] + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: [[MACHINE]] +Sections: + - Name: .foo.begin + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x1000 + Size: 0x1 + - Name: .foo.end + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x2 + - Name: .bar.begin + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x2000 + Size: 0x3 + - Name: .bar.end + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x4 + - Name: .interp + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x3000 + Content: "41424300" ## "ABC" + - Name: .tls + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_TLS ] + Address: 0x4000 + Size: 0x1 + - Name: .unused + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_TLS ] + Address: 0x5000 + Size: 0x1 + - Name: .dynamic + Type: SHT_DYNAMIC + Flags: [ SHF_ALLOC ] + Address: 0x6000 + Entries: + - Tag: DT_NEEDED + Value: 0x1 + - Tag: DT_NULL + Value: 0x0 +ProgramHeaders: +## Case 1: an arbitrary segment with sections. + - Type: PT_PHDR + Flags: [ PF_W ] + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 2: another segment with different sections. + - Type: PT_PHDR + Flags: [ PF_X ] + VAddr: 0x2000 + FirstSec: .bar.begin + LastSec: .bar.end +## Case 3: the PT_NULL segment. + - Type: PT_NULL + Flags: [ PF_X ] + VAddr: 0x2000 + FirstSec: .bar.begin + LastSec: .bar.end +## Case 4: the PT_DYNAMIC segment. + - Type: PT_DYNAMIC + Flags: [ PF_R, PF_W, PF_X ] + VAddr: 0x6000 + FirstSec: .dynamic + LastSec: .dynamic +## Case 5: the PT_INTERP segment. + - Type: PT_INTERP + Flags: [ PF_R, PF_W ] + VAddr: 0x3000 + FirstSec: .interp + LastSec: .interp +## Case 6: the PT_NOTE segment. + - Type: PT_NOTE + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 7: the PT_SHLIB segment. + - Type: PT_SHLIB + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.begin +## Case 8: the PT_TLS segment. + - Type: PT_TLS + VAddr: 0x4000 + FirstSec: .tls + LastSec: .tls +## Case 9: the PT_LOOS segment. + - Type: 0x60000000 ## PT_LOOS + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 10: the PT_GNU_EH_FRAME segment. + - Type: PT_GNU_EH_FRAME + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 11: the PT_SUNW_UNWIND segment. + - Type: 0x6464e550 ## PT_SUNW_UNWIND + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 12: the PT_GNU_STACK segment. + - Type: PT_GNU_STACK + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 13: the PT_GNU_RELRO segment. + - Type: PT_GNU_RELRO + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 14: the PT_GNU_PROPERTY segment. + - Type: PT_GNU_PROPERTY + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 15: the PT_OPENBSD_RANDOMIZE segment. + - Type: 0x65a3dbe6 ## PT_OPENBSD_RANDOMIZE + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 16: the PT_OPENBSD_WXNEEDED segment. + - Type: 0x65a3dbe7 ## PT_OPENBSD_WXNEEDED + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 17: the PT_OPENBSD_BOOTDATA segment. + - Type: 0x65a41be6 ## PT_OPENBSD_BOOTDATA + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 18: the PT_HIOS segment. + - Type: 0x6fffffff ## PT_HIOS + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 19: the PT_LOPROC/PT_ARM_ARCHEXT/PT_MIPS_REGINFO segment. + - Type: 0x70000000 ## PT_LOPROC/PT_ARM_ARCHEXT/PT_MIPS_REGINFO + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 20: the PT_ARM_EXIDX/PT_MIPS_RTPROC segment. + - Type: 0x70000001 ## PT_ARM_EXIDX, PT_MIPS_RTPROC + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 20: the PT_MIPS_OPTIONS segment. + - Type: 0x70000002 ## PT_MIPS_OPTIONS + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 21: the PT_MIPS_ABIFLAGS segment. + - Type: 0x70000003 ## PT_MIPS_ABIFLAGS + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end +## Case 22: the PT_HIPROC segment. + - Type: 0x7fffffff ## PT_HIPROC + VAddr: 0x1000 + FirstSec: .foo.begin + LastSec: .foo.end + +## Check we report an error / warning when we are unable to read program headers. +## Case A: the e_phentsize field is invalid. +# RUN: yaml2obj --docnum=2 -DPHENTSIZE=1 %s -o %t.phdr.err +# RUN: not llvm-objdump --private-headers %t.phdr.err 2>&1 | \ +# RUN: FileCheck %s -DFILE=%t.phdr.err --check-prefix=PHENTSIZE + +# PHENTSIZE: Program Header: +# PHENTSIZE-NEXT: warning: '[[FILE]]': unable to read program headers: invalid e_phentsize: 1 +# PHENTSIZE-NEXT: error: '[[FILE]]': invalid e_phentsize: 1 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + EPhEntSize: [[PHENTSIZE=]] + EPhOff: [[PHOFF=]] +Sections: + - Name: .foo + Type: SHT_PROGBITS +ProgramHeaders: + - Type: PT_PHDR + FirstSec: .foo + LastSec: .foo + +## Case B: the value of the e_phoff field is invalid. + +## Check that we do not report a warning when the program header table ends right before the end of the file. +## 0x160 + size of headers (56) == file size. +# RUN: yaml2obj --docnum=2 -DPHOFF=0x160 %s -o %t.phdr.no.err2 +# RUN: llvm-objdump %t.phdr.no.err2 --private-headers 2>&1 | FileCheck %s --implicit-check-not=warning: + +## Check we report a warning / error when e_phoff goes 1 byte past the end of the file. +# RUN: yaml2obj --docnum=2 -DPHOFF=0x161 %s -o %t.phdr.err2 +# RUN: not llvm-objdump --private-headers %t.phdr.err2 2>&1 | \ +# RUN: FileCheck %s -DFILE=%t.phdr.err2 --check-prefix=PHOFF -DOFF=0x161 + +# PHOFF: Program Header: +# PHOFF-NEXT: warning: '[[FILE]]': unable to read program headers: program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 +# PHOFF-NEXT: error: '[[FILE]]': program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 + + +## Check we report a warning / error when the value of e_phoff is so large that +## e_phoff + e_phnum * e_phentsize > UINT64_MAX. +# RUN: yaml2obj --docnum=2 -DPHOFF=0xffffffffffffffff %s -o %t.phdr.err3 +# RUN: not llvm-objdump --private-headers %t.phdr.err3 2>&1 | \ +# RUN: FileCheck %s -DFILE=%t.phdr.err3 --check-prefix=PHOFF -DOFF=0xffffffffffffffff From 1007cb795a3c82eab231b58569ea06a2b613636a Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 01:00:43 -0700 Subject: [PATCH 264/316] [llvm-objdump] --private-headers: change errors to warnings for dynamic section dumping Fix #54456: `objcopy --only-keep-debug` produces a linked image with invalid empty dynamic section. llvm-objdump -p currently reports an error which seems excessive. ``` % llvm-readelf -l a.out llvm-readelf: warning: 'a.out': no valid dynamic table was found ... ``` Follow the spirit of llvm-readelf -l (D64472) and report a warning instead. This allows later files to be dumped despite warnings for an input file, and improves objdump compatibility in that the exit code is now 0 instead of 1. ``` % llvm-objdump -p a.out # new behavior ... Program Header: llvm-objdump: warning: 'a.out': invalid empty dynamic section % objdump -p a.out ... Dynamic Section: ``` Reviewed By: jhenderson, raj.khem Differential Revision: https://reviews.llvm.org/D122505 (cherry picked from commit 11a8fc685692f56b011f851d974f0cac534f2cb8) --- llvm/lib/Object/ELF.cpp | 2 - .../llvm-objdump/ELF/dynamic-malformed.test | 38 +++++++++++++++++++ .../tools/llvm-objdump/ELF/invalid-phdr.test | 5 ++- .../llvm-objdump/ELF/program-headers.test | 13 ++++--- llvm/tools/llvm-objdump/ELFDump.cpp | 8 +++- 5 files changed, 54 insertions(+), 12 deletions(-) create mode 100644 llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test diff --git a/llvm/lib/Object/ELF.cpp b/llvm/lib/Object/ELF.cpp index 6e56da1a31f3e..56a4262117551 100644 --- a/llvm/lib/Object/ELF.cpp +++ b/llvm/lib/Object/ELF.cpp @@ -561,11 +561,9 @@ Expected ELFFile::dynamicEntries() const { } if (Dyn.empty()) - // TODO: this error is untested. return createError("invalid empty dynamic section"); if (Dyn.back().d_tag != ELF::DT_NULL) - // TODO: this error is untested. return createError("dynamic sections must be DT_NULL terminated"); return Dyn; diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test new file mode 100644 index 0000000000000..b10e4f5e44f18 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test @@ -0,0 +1,38 @@ +## An empty dynamic section is invalid. Test we report a warning instead of an +## error, so that dumping can continue with other objects. +# RUN: yaml2obj %s --docnum=1 -o %t.empty +# RUN: llvm-objdump -p %t.empty 2>&1 | FileCheck %s -DFILE=%t.empty --check-prefix=EMPTY + +# EMPTY: Program Header: +# EMPTY-NEXT: warning: '[[FILE]]': invalid empty dynamic section +# EMPTY-EMPTY: + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .dynamic + Type: SHT_DYNAMIC + +# RUN: yaml2obj %s --docnum=2 -o %t.nonull +# RUN: llvm-objdump -p %t.nonull 2>&1 | FileCheck %s -DFILE=%t.nonull --check-prefix=NONULL + +# NONULL: Program Header: +# NONULL-NEXT: warning: '[[FILE]]': dynamic sections must be DT_NULL terminated +# NONULL-EMPTY: + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .dynamic + Type: SHT_DYNAMIC + Entries: + - Tag: DT_SONAME + Value: 1 diff --git a/llvm/test/tools/llvm-objdump/ELF/invalid-phdr.test b/llvm/test/tools/llvm-objdump/ELF/invalid-phdr.test index 94de7eacc3eca..188c8eeeff491 100644 --- a/llvm/test/tools/llvm-objdump/ELF/invalid-phdr.test +++ b/llvm/test/tools/llvm-objdump/ELF/invalid-phdr.test @@ -1,11 +1,12 @@ ## Test how we handle the case when the e_phoff field is invalid. # RUN: yaml2obj %s -o %t -# RUN: not llvm-objdump --private-headers %t 2>&1 | \ +# RUN: llvm-objdump --private-headers %t 2>&1 | \ # RUN: FileCheck -DFILE=%t %s --check-prefix=INVALID-PHOFF # INVALID-PHOFF: Program Header: # INVALID-PHOFF-NEXT: warning: '[[FILE]]': unable to read program headers: program headers are longer than binary of size 280: e_phoff = 0xffffff, e_phnum = 0, e_phentsize = 0 -# INVALID-PHOFF-NEXT: error: '[[FILE]]': program headers are longer than binary of size 280: e_phoff = 0xffffff, e_phnum = 0, e_phentsize = 0 +# INVALID-PHOFF-NEXT: warning: '[[FILE]]': program headers are longer than binary of size 280: e_phoff = 0xffffff, e_phnum = 0, e_phentsize = 0 +# INVALID-PHOFF-EMPTY: --- !ELF FileHeader: diff --git a/llvm/test/tools/llvm-objdump/ELF/program-headers.test b/llvm/test/tools/llvm-objdump/ELF/program-headers.test index 1e11334d7172f..abd4894c45124 100644 --- a/llvm/test/tools/llvm-objdump/ELF/program-headers.test +++ b/llvm/test/tools/llvm-objdump/ELF/program-headers.test @@ -278,12 +278,13 @@ ProgramHeaders: ## Check we report an error / warning when we are unable to read program headers. ## Case A: the e_phentsize field is invalid. # RUN: yaml2obj --docnum=2 -DPHENTSIZE=1 %s -o %t.phdr.err -# RUN: not llvm-objdump --private-headers %t.phdr.err 2>&1 | \ +# RUN: llvm-objdump --private-headers %t.phdr.err 2>&1 | \ # RUN: FileCheck %s -DFILE=%t.phdr.err --check-prefix=PHENTSIZE # PHENTSIZE: Program Header: # PHENTSIZE-NEXT: warning: '[[FILE]]': unable to read program headers: invalid e_phentsize: 1 -# PHENTSIZE-NEXT: error: '[[FILE]]': invalid e_phentsize: 1 +# PHENTSIZE-NEXT: warning: '[[FILE]]': invalid e_phentsize: 1 +# PHENTSIZE-EMPTY: --- !ELF FileHeader: @@ -309,16 +310,16 @@ ProgramHeaders: ## Check we report a warning / error when e_phoff goes 1 byte past the end of the file. # RUN: yaml2obj --docnum=2 -DPHOFF=0x161 %s -o %t.phdr.err2 -# RUN: not llvm-objdump --private-headers %t.phdr.err2 2>&1 | \ +# RUN: llvm-objdump --private-headers %t.phdr.err2 2>&1 | \ # RUN: FileCheck %s -DFILE=%t.phdr.err2 --check-prefix=PHOFF -DOFF=0x161 # PHOFF: Program Header: # PHOFF-NEXT: warning: '[[FILE]]': unable to read program headers: program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 -# PHOFF-NEXT: error: '[[FILE]]': program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 - +# PHOFF-NEXT: warning: '[[FILE]]': program headers are longer than binary of size 408: e_phoff = [[OFF]], e_phnum = 1, e_phentsize = 56 +# PHOFF-EMPTY: ## Check we report a warning / error when the value of e_phoff is so large that ## e_phoff + e_phnum * e_phentsize > UINT64_MAX. # RUN: yaml2obj --docnum=2 -DPHOFF=0xffffffffffffffff %s -o %t.phdr.err3 -# RUN: not llvm-objdump --private-headers %t.phdr.err3 2>&1 | \ +# RUN: llvm-objdump --private-headers %t.phdr.err3 2>&1 | \ # RUN: FileCheck %s -DFILE=%t.phdr.err3 --check-prefix=PHOFF -DOFF=0xffffffffffffffff diff --git a/llvm/tools/llvm-objdump/ELFDump.cpp b/llvm/tools/llvm-objdump/ELFDump.cpp index 98e71497d022a..ca73dafe2b8ed 100644 --- a/llvm/tools/llvm-objdump/ELFDump.cpp +++ b/llvm/tools/llvm-objdump/ELFDump.cpp @@ -171,8 +171,12 @@ uint64_t objdump::getELFSectionLMA(const object::ELFSectionRef &Sec) { template static void printDynamicSection(const ELFFile &Elf, StringRef Filename) { - ArrayRef DynamicEntries = - unwrapOrError(Elf.dynamicEntries(), Filename); + auto DynamicEntriesOrErr = Elf.dynamicEntries(); + if (!DynamicEntriesOrErr) { + reportWarning(toString(DynamicEntriesOrErr.takeError()), Filename); + return; + } + ArrayRef DynamicEntries = *DynamicEntriesOrErr; // Find the maximum tag name length to format the value column properly. size_t MaxLen = 0; From 311a622edd31422c0969913285e54d4778477a12 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 01:27:16 -0700 Subject: [PATCH 265/316] [Object][test] Fix invalid.test (cherry picked from commit f7086401b7c03179b755768845956bc8e84ab266) --- llvm/test/Object/invalid.test | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/test/Object/invalid.test b/llvm/test/Object/invalid.test index ea95f6f5abcf9..58ec3cbeadd19 100644 --- a/llvm/test/Object/invalid.test +++ b/llvm/test/Object/invalid.test @@ -671,9 +671,10 @@ Sections: ## Check the case when the e_phoff field is invalid. # RUN: yaml2obj --docnum=31 %s -o %t31 -# RUN: not llvm-objdump --private-headers %t31 2>&1 | FileCheck -DFILE=%t31 %s --check-prefix=INVALID-PHOFF +# RUN: llvm-objdump --private-headers %t31 2>&1 | FileCheck -DFILE=%t31 %s --check-prefix=INVALID-PHOFF -# INVALID-PHOFF: error: '[[FILE]]': program headers are longer than binary of size 280: e_phoff = 0xffffff, e_phnum = 0, e_phentsize = 0 +# INVALID-PHOFF: warning: '[[FILE]]': program headers are longer than binary of size 280: e_phoff = 0xffffff, e_phnum = 0, e_phentsize = 0 +# INVALID-PHOFF-EMPTY: --- !ELF FileHeader: From 353068233f21bd8b904da854072e85114c566562 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 11:05:52 -0700 Subject: [PATCH 266/316] [ELF] Fix llvm_unreachable failure when COMMON is placed in SHT_PROGBITS output section Fix a regression in aa27bab5a1a17e9c4168a741a6298ecaa92c1ecb: COMMON in an SHT_PROGBITS output section caused llvm_unreachable failure. (cherry picked from commit 1db59dc8e28819b1960dae8e7fe6d79ad4b03340) --- lld/ELF/SyntheticSections.h | 4 +- lld/test/ELF/linkerscript/common.s | 75 ++++++++++++++---------------- 2 files changed, 37 insertions(+), 42 deletions(-) diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index e609b3d7982a5..3161785988f64 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -187,9 +187,7 @@ class BuildIdSection : public SyntheticSection { class BssSection final : public SyntheticSection { public: BssSection(StringRef name, uint64_t size, uint32_t alignment); - void writeTo(uint8_t *) override { - llvm_unreachable("unexpected writeTo() call for SHT_NOBITS section"); - } + void writeTo(uint8_t *) override {} bool isNeeded() const override { return size != 0; } size_t getSize() const override { return size; } diff --git a/lld/test/ELF/linkerscript/common.s b/lld/test/ELF/linkerscript/common.s index 04b667f659128..69376011656f3 100644 --- a/lld/test/ELF/linkerscript/common.s +++ b/lld/test/ELF/linkerscript/common.s @@ -1,47 +1,44 @@ # REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t -# RUN: echo "SECTIONS { . = SIZEOF_HEADERS; .common : { *(COMMON) } }" > %t.script -# RUN: ld.lld -o %t1 --script %t.script %t -# RUN: llvm-readobj -S --symbols %t1 | FileCheck %s - -# CHECK: Section { -# CHECK: Index: -# CHECK: Name: .common -# CHECK-NEXT: Type: SHT_NOBITS -# CHECK-NEXT: Flags [ -# CHECK-NEXT: SHF_ALLOC -# CHECK-NEXT: SHF_WRITE -# CHECK-NEXT: ] -# CHECK-NEXT: Address: 0x200 -# CHECK-NEXT: Offset: 0x -# CHECK-NEXT: Size: 384 -# CHECK-NEXT: Link: 0 -# CHECK-NEXT: Info: 0 -# CHECK-NEXT: AddressAlignment: 256 -# CHECK-NEXT: EntrySize: 0 -# CHECK-NEXT: } -# CHECK: Symbol { -# CHECK: Name: q1 -# CHECK-NEXT: Value: 0x200 -# CHECK-NEXT: Size: 128 -# CHECK-NEXT: Binding: Global -# CHECK-NEXT: Type: Object -# CHECK-NEXT: Other: 0 -# CHECK-NEXT: Section: .common -# CHECK-NEXT: } -# CHECK-NEXT: Symbol { -# CHECK-NEXT: Name: q2 -# CHECK-NEXT: Value: 0x300 -# CHECK-NEXT: Size: 128 -# CHECK-NEXT: Binding: Global -# CHECK-NEXT: Type: Object -# CHECK-NEXT: Other: 0 -# CHECK-NEXT: Section: .common -# CHECK-NEXT: } +## Test that COMMON matches common symbols. +# RUN: rm -rf %t && split-file %s %t +# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %t/a.s -o %t/a.o +# RUN: ld.lld -T %t/1.t %t/a.o -o %t/a1 +# RUN: llvm-readelf -S -s %t/a1 | FileCheck %s --check-prefix=CHECK1 +# RUN: ld.lld -T %t/2.t %t/a.o -o %t/a2 +# RUN: llvm-readelf -S -s %t/a2 | FileCheck %s --check-prefix=CHECK2 + +# CHECK1: [Nr] Name Type Address Off Size ES Flg Lk Inf Al +# CHECK1-NEXT: [ 0] NULL [[#%x,]] [[#%x,]] 000000 00 0 0 0 +# CHECK1-NEXT: [ 1] .text PROGBITS [[#%x,]] [[#%x,]] 000005 00 AX 0 0 4 +# CHECK1-NEXT: [ 2] .data PROGBITS [[#%x,]] [[#%x,]] 000001 00 WA 0 0 1 +# CHECK1-NEXT: [ 3] .common NOBITS [[#%x,]] [[#%x,]] 000180 00 WA 0 0 256 +# CHECK1: Value Size Type Bind Vis Ndx Name +# CHECK1-DAG: [[#%x,]] 128 OBJECT GLOBAL DEFAULT [[#]] q1 +# CHECK1-DAG: [[#%x,]] 128 OBJECT GLOBAL DEFAULT [[#]] q2 + +# CHECK2: [Nr] Name Type Address Off Size ES Flg Lk Inf Al +# CHECK2-NEXT: [ 0] NULL [[#%x,]] [[#%x,]] 000000 00 0 0 0 +# CHECK2-NEXT: [ 1] .text PROGBITS [[#%x,]] [[#%x,]] 000005 00 AX 0 0 4 +# CHECK2-NEXT: [ 2] .data PROGBITS [[#%x,]] [[#%x,]] 000180 00 WA 0 0 256 +# CHECK2: Value Size Type Bind Vis Ndx Name +# CHECK2-DAG: [[#%x,]] 128 OBJECT GLOBAL DEFAULT [[#]] q1 +# CHECK2-DAG: [[#%x,]] 128 OBJECT GLOBAL DEFAULT [[#]] q2 + +#--- a.s .globl _start _start: jmp _start +.section .data,"aw",@progbits +.byte 0 + .comm q1,128,8 .comm q2,128,256 + +#--- 1.t +SECTIONS { . = SIZEOF_HEADERS; .common : { *(COMMON) } } + +#--- 2.t +## COMMON can be placed in a SHT_PROGBITS section. +SECTIONS { . = SIZEOF_HEADERS; .data : { *(.data) *(COMMON) } } From 67a290460c374d5e0d18a06c798896cac0b19e59 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Wed, 16 Mar 2022 10:14:07 +0000 Subject: [PATCH 267/316] [VectorCombine] Insert addrspacecast when crossing address space boundaries We can not bitcast pointers across different address spaces. This was previously fixed in D89577 but then in D93229 an enhancement was added which peeks further through the ponter operand, opening up the possibility that address-space violations could be introduced. Instead of bailing as the previous fix did, simply insert an addrspacecast cast instruction. Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D121787 (cherry picked from commit 2e44b7872bc638ed884ae4aa86e38b3b47e0b65a) --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 8 ++------ .../AMDGPU/as-transition-inseltpoison.ll | 4 +--- .../VectorCombine/AMDGPU/as-transition.ll | 4 +--- .../VectorCombine/X86/load-inseltpoison.ll | 17 +++++++++++++++++ 4 files changed, 21 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 620d388199e0f..258f6c67e54d5 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -152,12 +152,7 @@ bool VectorCombine::vectorizeLoadInsert(Instruction &I) { Value *SrcPtr = Load->getPointerOperand()->stripPointerCasts(); assert(isa(SrcPtr->getType()) && "Expected a pointer type"); - // If original AS != Load's AS, we can't bitcast the original pointer and have - // to use Load's operand instead. Ideally we would want to strip pointer casts - // without changing AS, but there's no API to do that ATM. unsigned AS = Load->getPointerAddressSpace(); - if (AS != SrcPtr->getType()->getPointerAddressSpace()) - SrcPtr = Load->getPointerOperand(); // We are potentially transforming byte-sized (8-bit) memory accesses, so make // sure we have all of our type-based constraints in place for this target. @@ -245,7 +240,8 @@ bool VectorCombine::vectorizeLoadInsert(Instruction &I) { // It is safe and potentially profitable to load a vector directly: // inselt undef, load Scalar, 0 --> load VecPtr IRBuilder<> Builder(Load); - Value *CastedPtr = Builder.CreateBitCast(SrcPtr, MinVecTy->getPointerTo(AS)); + Value *CastedPtr = Builder.CreatePointerBitCastOrAddrSpaceCast( + SrcPtr, MinVecTy->getPointerTo(AS)); Value *VecLd = Builder.CreateAlignedLoad(MinVecTy, CastedPtr, Alignment); VecLd = Builder.CreateShuffleVector(VecLd, Mask); diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll index 688e3c4cf6c7a..b493c2a4f8bb5 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll @@ -11,9 +11,7 @@ define protected amdgpu_kernel void @load_from_other_as(<4 x float>* nocapture n ; CHECK-LABEL: @load_from_other_as( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5) -; CHECK-NEXT: [[B:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]] to %struct.hoge* -; CHECK-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_HOGE]], %struct.hoge* [[B]], i64 0, i32 0 -; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[C]] to <1 x float>* +; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]] to <1 x float>* ; CHECK-NEXT: [[TMP1:%.*]] = load <1 x float>, <1 x float>* [[TMP0]], align 4 ; CHECK-NEXT: [[E:%.*]] = shufflevector <1 x float> [[TMP1]], <1 x float> poison, <4 x i32> ; CHECK-NEXT: store <4 x float> [[E]], <4 x float>* [[RESULTPTR:%.*]], align 16 diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll index 3468cb540903e..8e36856714b24 100644 --- a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll +++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll @@ -11,9 +11,7 @@ define protected amdgpu_kernel void @load_from_other_as(<4 x float>* nocapture n ; CHECK-LABEL: @load_from_other_as( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5) -; CHECK-NEXT: [[B:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]] to %struct.hoge* -; CHECK-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_HOGE]], %struct.hoge* [[B]], i64 0, i32 0 -; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[C]] to <1 x float>* +; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]] to <1 x float>* ; CHECK-NEXT: [[TMP1:%.*]] = load <1 x float>, <1 x float>* [[TMP0]], align 4 ; CHECK-NEXT: [[E:%.*]] = shufflevector <1 x float> [[TMP1]], <1 x float> poison, <4 x i32> ; CHECK-NEXT: store <4 x float> [[E]], <4 x float>* [[RESULTPTR:%.*]], align 16 diff --git a/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll index cf5a6c0772f7f..e4ea44ae6e572 100644 --- a/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll +++ b/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll @@ -253,6 +253,23 @@ define <4 x float> @gep00_load_f32_insert_v4f32_addrspace(<4 x float> addrspace( ret <4 x float> %r } +; Should work with addrspace even when peeking past unsafe loads through geps + +define <4 x i32> @unsafe_load_i32_insert_v4i32_addrspace(i32* align 16 dereferenceable(16) %v3) { +; CHECK-LABEL: @unsafe_load_i32_insert_v4i32_addrspace( +; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast i32* [[V3:%.*]] to <4 x i32> addrspace(42)* +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32> addrspace(42)* [[TMP1]], align 16 +; CHECK-NEXT: [[INSELT:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[INSELT]] +; + %t0 = getelementptr inbounds i32, i32* %v3, i32 1 + %t1 = addrspacecast i32* %t0 to i32 addrspace(42)* + %t2 = getelementptr inbounds i32, i32 addrspace(42)* %t1, i64 1 + %val = load i32, i32 addrspace(42)* %t2, align 4 + %inselt = insertelement <4 x i32> poison, i32 %val, i32 0 + ret <4 x i32> %inselt +} + ; If there are enough dereferenceable bytes, we can offset the vector load. define <8 x i16> @gep01_load_i16_insert_v8i16(<8 x i16>* align 16 dereferenceable(18) %p) nofree nosync { From d53e2603383a1304c3ee081169b1bf8dac93f8e4 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 28 Mar 2022 17:52:27 -0700 Subject: [PATCH 268/316] [AArch64] Allow .variant_pcs before the symbol is registered glibc sysdeps/aarch64/tst-vpcs-mod.S has something like: ``` .variant_pcs vpcs_call .global vpcs_call ``` This is supported by GNU as but leads to an error in MC. Use getOrCreateSymbol to support a not-yet-registered symbol: call `registerSymbol` to ensure the symbol exists even if there is no binding directive/label, to match GNU as. While here, improve tests to check (1) a local symbol can get STO_AARCH64_VARIANT_PCS (2) undefined .variant_pcs (3) an alias does not inherit STO_AARCH64_VARIANT_PCS. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D122507 (cherry picked from commit cfbd5c8e4aa1ba3fc11fb408eeedbb05bd235956) --- .../AArch64/AsmParser/AArch64AsmParser.cpp | 16 ++----- .../MCTargetDesc/AArch64ELFStreamer.cpp | 1 + .../MC/AArch64/directive-variant_pcs-err.s | 3 -- llvm/test/MC/AArch64/directive-variant_pcs.s | 42 +++++++++++++++---- 4 files changed, 39 insertions(+), 23 deletions(-) diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 33ed7ae9780e6..8f71eb3095cfe 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -6515,21 +6515,13 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() { /// parseDirectiveVariantPCS /// ::= .variant_pcs symbolname bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) { - const AsmToken &Tok = getTok(); - if (Tok.isNot(AsmToken::Identifier)) + StringRef Name; + if (getParser().parseIdentifier(Name)) return TokError("expected symbol name"); - - StringRef SymbolName = Tok.getIdentifier(); - - MCSymbol *Sym = getContext().lookupSymbol(SymbolName); - if (!Sym) - return TokError("unknown symbol"); - - Lex(); // Eat the symbol - if (parseEOL()) return true; - getTargetStreamer().emitDirectiveVariantPCS(Sym); + getTargetStreamer().emitDirectiveVariantPCS( + getContext().getOrCreateSymbol(Name)); return false; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp index 78c0e90b13845..46edb12959d28 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp @@ -254,6 +254,7 @@ void AArch64TargetELFStreamer::emitInst(uint32_t Inst) { } void AArch64TargetELFStreamer::emitDirectiveVariantPCS(MCSymbol *Symbol) { + getStreamer().getAssembler().registerSymbol(*Symbol); cast(Symbol)->setOther(ELF::STO_AARCH64_VARIANT_PCS); } diff --git a/llvm/test/MC/AArch64/directive-variant_pcs-err.s b/llvm/test/MC/AArch64/directive-variant_pcs-err.s index 70bb5451d3716..6aa63d8298776 100644 --- a/llvm/test/MC/AArch64/directive-variant_pcs-err.s +++ b/llvm/test/MC/AArch64/directive-variant_pcs-err.s @@ -3,9 +3,6 @@ // CHECK: [[#@LINE+1]]:13: error: expected symbol name .variant_pcs -// CHECK: [[#@LINE+1]]:14: error: unknown symbol -.variant_pcs foo - .global foo // CHECK: [[#@LINE+1]]:18: error: expected newline .variant_pcs foo bar diff --git a/llvm/test/MC/AArch64/directive-variant_pcs.s b/llvm/test/MC/AArch64/directive-variant_pcs.s index f6f9c9c272f78..26ed7aef90cce 100644 --- a/llvm/test/MC/AArch64/directive-variant_pcs.s +++ b/llvm/test/MC/AArch64/directive-variant_pcs.s @@ -1,11 +1,37 @@ -// RUN: llvm-mc -triple aarch64-elf -filetype asm -o - %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-elf -filetype obj -o - %s \ -// RUN: | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-ST_OTHER +// RUN: llvm-mc -triple aarch64-elf -filetype asm %s | FileCheck %s --check-prefix=ASM +// RUN: llvm-mc -triple aarch64-elf -filetype obj %s \ +// RUN: | llvm-readelf -s - | FileCheck %s --check-prefix=OBJ +// ASM: .variant_pcs local +// ASM-NEXT: local: .text -.global foo -.variant_pcs foo -// CHECK: .variant_pcs foo +.variant_pcs local +local: -// CHECK-ST_OTHER: Name: foo -// CHECK-ST_OTHER: Other [ (0x80) +/// Binding directive before .variant_pcs. +// ASM: .globl def1 +// ASM-NEXT: .variant_pcs def1 +// ASM-NEXT: def1: +.global def1 +.variant_pcs def1 +def1: + +/// .variant_pcs before binding directive. +// ASM: .variant_pcs def2 +// ASM-NEXT: .weak def2 +// ASM-NEXT: def2: +.variant_pcs def2 +.weak def2 +def2: + +.globl alias_def1 +.set alias_def1, def1 + +// ASM: .variant_pcs undef +.variant_pcs undef + +// OBJ: NOTYPE LOCAL DEFAULT [VARIANT_PCS] [[#]] local +// OBJ-NEXT: NOTYPE GLOBAL DEFAULT [VARIANT_PCS] [[#]] def1 +// OBJ-NEXT: NOTYPE WEAK DEFAULT [VARIANT_PCS] [[#]] def2 +// OBJ-NEXT: NOTYPE GLOBAL DEFAULT [[#]] alias_def1 +// OBJ-NEXT: NOTYPE GLOBAL DEFAULT [VARIANT_PCS] UND undef From fd98b0f1a6a1c57bd368c78c7cf86fc9f527d452 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Thu, 24 Mar 2022 11:03:26 +0000 Subject: [PATCH 269/316] [SelectionDAG] Don't create illegally-typed nodes while constant folding This patch fixes a (seemingly very rare) crash during vector constant folding introduced in D113300. Normally, during legalization, if we create an illegally-typed node during a failed attempt at constant folding it's cleaned up before being visited, due to it having no uses. If, however, an illegally-typed node is created during one round of legalization and isn't cleaned up, it's possible for a second round of legalization to create new illegally-typed nodes which add extra uses to the old illegal nodes. This means that we can end up visiting the old nodes before they're known to be dead, at which point we crash. I'm not happy about this fix. Creating illegal types at all seems like a bad idea, but we all-too-often rely on illegal constants being successfully folded and being fixed up afterwards. However, we can't rely on constant folding actually happening, and we don't have a foolproof way of peering into the future. Perhaps the correct fix is to revisit the node-iteration order during legalization, ensuring we visit all uses of nodes before the nodes themselves. Or alternatively we could try and clean up dead nodes immediately after failing constant folding. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D122382 (cherry picked from commit 43a91a8474f55241404199f6b8798ac6467c2687) --- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 ++- .../RISCV/rvv/constant-folding-crash.ll | 85 +++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index d5998d166d255..40d861702e86c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5494,8 +5494,18 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, // Build vector (integer) scalar operands may need implicit // truncation - do this before constant folding. - if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) + if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) { + // Don't create illegally-typed nodes unless they're constants or undef + // - if we fail to constant fold we can't guarantee the (dead) nodes + // we're creating will be cleaned up before being visited for + // legalization. + if (NewNodesMustHaveLegalTypes && !ScalarOp.isUndef() && + !isa(ScalarOp) && + TLI->getTypeAction(*getContext(), InSVT) != + TargetLowering::TypeLegal) + return SDValue(); ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp); + } ScalarOps.push_back(ScalarOp); } diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll new file mode 100644 index 0000000000000..1fae357540b7e --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll @@ -0,0 +1,85 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefix RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefix RV64 + +; This used to crash during type legalization, where lowering (v4i1 = +; BUILD_VECTOR) created a (v4i1 = SETCC v4i8) which during constant-folding +; created illegally-typed i8 nodes. Ultimately, constant-folding failed and so +; the new illegal nodes had no uses. However, during a second round of +; legalization, this same pattern was generated from another BUILD_VECTOR. This +; meant one of the illegally-typed (i8 = Constant<0>) nodes now had two dead +; uses. Because the Constant and one of the uses were from round 1, they were +; further up in the node order than the new second use, so the constant was +; visited while it wasn't "dead". At the point of visiting the constant, we +; crashed. + +define void @constant_folding_crash(i8* %v54, <4 x <4 x i32>*> %lanes.a, <4 x <4 x i32>*> %lanes.b, <4 x i1> %sel) { +; RV32-LABEL: constant_folding_crash: +; RV32: # %bb.0: # %entry +; RV32-NEXT: lw a0, 8(a0) +; RV32-NEXT: vmv1r.v v10, v0 +; RV32-NEXT: andi a0, a0, 1 +; RV32-NEXT: seqz a0, a0 +; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; RV32-NEXT: vmv.v.x v11, a0 +; RV32-NEXT: vmsne.vi v0, v11, 0 +; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu +; RV32-NEXT: vmerge.vvm v8, v9, v8, v0 +; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu +; RV32-NEXT: vmv.v.i v9, 0 +; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu +; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; RV32-NEXT: vmv1r.v v0, v10 +; RV32-NEXT: vmerge.vim v8, v9, 1, v0 +; RV32-NEXT: vmv.x.s a1, v8 +; RV32-NEXT: andi a1, a1, 1 +; RV32-NEXT: vmv.v.x v8, a1 +; RV32-NEXT: vmsne.vi v0, v8, 0 +; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu +; RV32-NEXT: vmv.v.i v8, 10 +; RV32-NEXT: vse32.v v8, (a0), v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: constant_folding_crash: +; RV64: # %bb.0: # %entry +; RV64-NEXT: ld a0, 8(a0) +; RV64-NEXT: vmv1r.v v12, v0 +; RV64-NEXT: andi a0, a0, 1 +; RV64-NEXT: seqz a0, a0 +; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; RV64-NEXT: vmv.v.x v13, a0 +; RV64-NEXT: vmsne.vi v0, v13, 0 +; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu +; RV64-NEXT: vmerge.vvm v8, v10, v8, v0 +; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, mu +; RV64-NEXT: vmv.v.i v10, 0 +; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu +; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; RV64-NEXT: vmv1r.v v0, v12 +; RV64-NEXT: vmerge.vim v8, v10, 1, v0 +; RV64-NEXT: vmv.x.s a1, v8 +; RV64-NEXT: andi a1, a1, 1 +; RV64-NEXT: vmv.v.x v8, a1 +; RV64-NEXT: vmsne.vi v0, v8, 0 +; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu +; RV64-NEXT: vmv.v.i v8, 10 +; RV64-NEXT: vse32.v v8, (a0), v0.t +; RV64-NEXT: ret +entry: + %sunkaddr = getelementptr i8, i8* %v54, i64 8 + %v55 = bitcast i8* %sunkaddr to i64* + %v56 = load i64, i64* %v55, align 8 + %trunc = and i64 %v56, 1 + %cmp = icmp eq i64 %trunc, 0 + %ptrs = select i1 %cmp, <4 x <4 x i32>*> %lanes.a, <4 x <4 x i32>*> %lanes.b + %v67 = extractelement <4 x <4 x i32>*> %ptrs, i64 0 + %mask = shufflevector <4 x i1> %sel, <4 x i1> undef, <4 x i32> zeroinitializer + call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> , <4 x i32>* %v67, i32 16, <4 x i1> %mask) + ret void +} + +declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>) From d150523f0776da96a1a6b694f800f15365318e20 Mon Sep 17 00:00:00 2001 From: Philippe Valembois Date: Thu, 10 Mar 2022 15:05:29 -0800 Subject: [PATCH 270/316] [AArch64] Use correct calling convention for each vararg While checking is tail call optimization is possible, the calling convention applied to fixed arguments is not the correct one. This implies for DarwinPCS that all arguments of a vararg function will go to the stack although fixed ones can go in registers. This prevents non-virtual thunks to be tail optimized although they are marked as musttail. Differential Revision: https://reviews.llvm.org/D120622 (cherry picked from commit 26cd258420c774254cc48330b1f4d23d353baf05) --- .../Target/AArch64/AArch64ISelLowering.cpp | 146 +++++++++--------- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 7 +- llvm/test/CodeGen/AArch64/darwinpcs-tail.ll | 36 +++++ 3 files changed, 113 insertions(+), 76 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/darwinpcs-tail.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ac5e51e47ddf1..3008466159bb2 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -5843,14 +5843,62 @@ static bool mayTailCallThisCC(CallingConv::ID CC) { } } +static void analyzeCallOperands(const AArch64TargetLowering &TLI, + const AArch64Subtarget *Subtarget, + const TargetLowering::CallLoweringInfo &CLI, + CCState &CCInfo) { + const SelectionDAG &DAG = CLI.DAG; + CallingConv::ID CalleeCC = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + const SmallVector &Outs = CLI.Outs; + bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC); + + unsigned NumArgs = Outs.size(); + for (unsigned i = 0; i != NumArgs; ++i) { + MVT ArgVT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + + bool UseVarArgCC = false; + if (IsVarArg) { + // On Windows, the fixed arguments in a vararg call are passed in GPRs + // too, so use the vararg CC to force them to integer registers. + if (IsCalleeWin64) { + UseVarArgCC = true; + } else { + UseVarArgCC = !Outs[i].IsFixed; + } + } else { + // Get type of the original argument. + EVT ActualVT = + TLI.getValueType(DAG.getDataLayout(), CLI.Args[Outs[i].OrigArgIndex].Ty, + /*AllowUnknown*/ true); + MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ArgVT; + // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. + if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) + ArgVT = MVT::i8; + else if (ActualMVT == MVT::i16) + ArgVT = MVT::i16; + } + + CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CalleeCC, UseVarArgCC); + bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); + assert(!Res && "Call operand has unhandled type"); + (void)Res; + } +} + bool AArch64TargetLowering::isEligibleForTailCallOptimization( - SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, - const SmallVectorImpl &Outs, - const SmallVectorImpl &OutVals, - const SmallVectorImpl &Ins, SelectionDAG &DAG) const { + const CallLoweringInfo &CLI) const { + CallingConv::ID CalleeCC = CLI.CallConv; if (!mayTailCallThisCC(CalleeCC)) return false; + SDValue Callee = CLI.Callee; + bool IsVarArg = CLI.IsVarArg; + const SmallVector &Outs = CLI.Outs; + const SmallVector &OutVals = CLI.OutVals; + const SmallVector &Ins = CLI.Ins; + const SelectionDAG &DAG = CLI.DAG; MachineFunction &MF = DAG.getMachineFunction(); const Function &CallerF = MF.getFunction(); CallingConv::ID CallerCC = CallerF.getCallingConv(); @@ -5915,30 +5963,14 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization( // I want anyone implementing a new calling convention to think long and hard // about this assert. - assert((!isVarArg || CalleeCC == CallingConv::C) && + assert((!IsVarArg || CalleeCC == CallingConv::C) && "Unexpected variadic calling convention"); LLVMContext &C = *DAG.getContext(); - if (isVarArg && !Outs.empty()) { - // At least two cases here: if caller is fastcc then we can't have any - // memory arguments (we'd be expected to clean up the stack afterwards). If - // caller is C then we could potentially use its argument area. - - // FIXME: for now we take the most conservative of these in both cases: - // disallow all variadic memory operands. - SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C); - - CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true)); - for (const CCValAssign &ArgLoc : ArgLocs) - if (!ArgLoc.isRegLoc()) - return false; - } - // Check that the call results are passed in the same way. if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, - CCAssignFnForCall(CalleeCC, isVarArg), - CCAssignFnForCall(CallerCC, isVarArg))) + CCAssignFnForCall(CalleeCC, IsVarArg), + CCAssignFnForCall(CallerCC, IsVarArg))) return false; // The callee has to preserve all registers the caller needs to preserve. const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo(); @@ -5958,9 +5990,22 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization( return true; SmallVector ArgLocs; - CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C); + CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C); + + analyzeCallOperands(*this, Subtarget, CLI, CCInfo); + + if (IsVarArg && !(CLI.CB && CLI.CB->isMustTailCall())) { + // When we are musttail, additional checks have been done and we can safely ignore this check + // At least two cases here: if caller is fastcc then we can't have any + // memory arguments (we'd be expected to clean up the stack afterwards). If + // caller is C then we could potentially use its argument area. - CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg)); + // FIXME: for now we take the most conservative of these in both cases: + // disallow all variadic memory operands. + for (const CCValAssign &ArgLoc : ArgLocs) + if (!ArgLoc.isRegLoc()) + return false; + } const AArch64FunctionInfo *FuncInfo = MF.getInfo(); @@ -6051,7 +6096,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, SDValue Chain = CLI.Chain; SDValue Callee = CLI.Callee; bool &IsTailCall = CLI.IsTailCall; - CallingConv::ID CallConv = CLI.CallConv; + CallingConv::ID &CallConv = CLI.CallConv; bool IsVarArg = CLI.IsVarArg; MachineFunction &MF = DAG.getMachineFunction(); @@ -6061,7 +6106,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, AArch64FunctionInfo *FuncInfo = MF.getInfo(); bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; bool IsSibCall = false; - bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CallConv); // Check callee args/returns for SVE registers and set calling convention // accordingly. @@ -6079,8 +6123,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, if (IsTailCall) { // Check if it's really possible to do a tail call. - IsTailCall = isEligibleForTailCallOptimization( - Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG); + IsTailCall = isEligibleForTailCallOptimization(CLI); // A sibling call is one where we're under the usual C ABI and not planning // to change that but can still do a tail call: @@ -6101,56 +6144,17 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); if (IsVarArg) { - // Handle fixed and variable vector arguments differently. - // Variable vector arguments always go into memory. unsigned NumArgs = Outs.size(); for (unsigned i = 0; i != NumArgs; ++i) { - MVT ArgVT = Outs[i].VT; - if (!Outs[i].IsFixed && ArgVT.isScalableVector()) + if (!Outs[i].IsFixed && Outs[i].VT.isScalableVector()) report_fatal_error("Passing SVE types to variadic functions is " "currently not supported"); - - ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; - bool UseVarArgCC = !Outs[i].IsFixed; - // On Windows, the fixed arguments in a vararg call are passed in GPRs - // too, so use the vararg CC to force them to integer registers. - if (IsCalleeWin64) - UseVarArgCC = true; - CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, UseVarArgCC); - bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); - assert(!Res && "Call operand has unhandled type"); - (void)Res; - } - } else { - // At this point, Outs[].VT may already be promoted to i32. To correctly - // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and - // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT. - // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here - // we use a special version of AnalyzeCallOperands to pass in ValVT and - // LocVT. - unsigned NumArgs = Outs.size(); - for (unsigned i = 0; i != NumArgs; ++i) { - MVT ValVT = Outs[i].VT; - // Get type of the original argument. - EVT ActualVT = getValueType(DAG.getDataLayout(), - CLI.getArgs()[Outs[i].OrigArgIndex].Ty, - /*AllowUnknown*/ true); - MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT; - ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; - // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. - if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) - ValVT = MVT::i8; - else if (ActualMVT == MVT::i16) - ValVT = MVT::i16; - - CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); - bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo); - assert(!Res && "Call operand has unhandled type"); - (void)Res; } } + analyzeCallOperands(*this, Subtarget, CLI, CCInfo); + // Get a count of how many bytes are to be pushed on the stack. unsigned NumBytes = CCInfo.getNextStackOffset(); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 2138c0ffe70ae..0ffaf08b8bbed 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -898,11 +898,8 @@ class AArch64TargetLowering : public TargetLowering { SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; - bool isEligibleForTailCallOptimization( - SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, - const SmallVectorImpl &Outs, - const SmallVectorImpl &OutVals, - const SmallVectorImpl &Ins, SelectionDAG &DAG) const; + bool + isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const; /// Finds the incoming stack arguments which overlap the given fixed stack /// object and incorporates their load into the current chain. This prevents diff --git a/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll b/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll new file mode 100644 index 0000000000000..9d13ed6269245 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/darwinpcs-tail.ll @@ -0,0 +1,36 @@ +; With Darwin PCS, non-virtual thunks generated are generated with musttail +; and are expected to build +; In general Darwin PCS should be tail optimized +; RUN: llc -mtriple=arm64-apple-ios5.0.0 < %s | FileCheck %s + +; CHECK-LABEL: __ZThn16_N1C3addEPKcz: +; CHECK: b __ZN1C3addEPKcz +; CHECK-LABEL: _tailTest: +; CHECK: b __ZN1C3addEPKcz +; CHECK-LABEL: __ZThn8_N1C1fEiiiiiiiiiz: +; CHECK: ldr w9, [sp, #4] +; CHECK: str w9, [sp, #4] +; CHECK: b __ZN1C1fEiiiiiiiiiz + +%class.C = type { %class.A.base, [4 x i8], %class.B.base, [4 x i8] } +%class.A.base = type <{ i32 (...)**, i32 }> +%class.B.base = type <{ i32 (...)**, i32 }> + +declare void @_ZN1C3addEPKcz(%class.C*, i8*, ...) unnamed_addr #0 align 2 + +define void @_ZThn16_N1C3addEPKcz(%class.C* %0, i8* %1, ...) unnamed_addr #0 align 2 { + musttail call void (%class.C*, i8*, ...) @_ZN1C3addEPKcz(%class.C* noundef nonnull align 8 dereferenceable(28) undef, i8* noundef %1, ...) + ret void +} + +define void @tailTest(%class.C* %0, i8* %1, ...) unnamed_addr #0 align 2 { + tail call void (%class.C*, i8*, ...) @_ZN1C3addEPKcz(%class.C* noundef nonnull align 8 dereferenceable(28) undef, i8* noundef %1) + ret void +} + +declare void @_ZN1C1fEiiiiiiiiiz(%class.C* %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 noundef %9, ...) unnamed_addr #1 align 2 + +define void @_ZThn8_N1C1fEiiiiiiiiiz(%class.C* %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 noundef %9, ...) unnamed_addr #1 align 2 { + musttail call void (%class.C*, i32, i32, i32, i32, i32, i32, i32, i32, i32, ...) @_ZN1C1fEiiiiiiiiiz(%class.C* nonnull align 8 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 noundef %9, ...) + ret void +} From aaf0c921a54ac9f9d9bc0e74566f3153d25e0c00 Mon Sep 17 00:00:00 2001 From: Vassil Vassilev Date: Fri, 11 Mar 2022 08:12:11 +0000 Subject: [PATCH 271/316] [clang-repl] Add an accessor to our underlying execution engine This patch will allow better incremental adoption of these changes in downstream cling and other users which want to experiment by customizing the execution engine. (cherry picked from commit 788e0f7f3e96a9d61c2412e452c4589e2693b79a) --- clang/include/clang/Interpreter/Interpreter.h | 2 ++ clang/lib/Interpreter/IncrementalExecutor.h | 1 + clang/lib/Interpreter/Interpreter.cpp | 6 ++++++ 3 files changed, 9 insertions(+) diff --git a/clang/include/clang/Interpreter/Interpreter.h b/clang/include/clang/Interpreter/Interpreter.h index 721a649deb43b..f2fdb90f5ba48 100644 --- a/clang/include/clang/Interpreter/Interpreter.h +++ b/clang/include/clang/Interpreter/Interpreter.h @@ -26,6 +26,7 @@ namespace llvm { namespace orc { +class LLJIT; class ThreadSafeContext; } } // namespace llvm @@ -56,6 +57,7 @@ class Interpreter { static llvm::Expected> create(std::unique_ptr CI); const CompilerInstance *getCompilerInstance() const; + const llvm::orc::LLJIT *getExecutionEngine() const; llvm::Expected Parse(llvm::StringRef Code); llvm::Error Execute(PartialTranslationUnit &T); llvm::Error ParseAndExecute(llvm::StringRef Code) { diff --git a/clang/lib/Interpreter/IncrementalExecutor.h b/clang/lib/Interpreter/IncrementalExecutor.h index 24447994d5f1d..51b4d83d10b1c 100644 --- a/clang/lib/Interpreter/IncrementalExecutor.h +++ b/clang/lib/Interpreter/IncrementalExecutor.h @@ -45,6 +45,7 @@ class IncrementalExecutor { llvm::Error runCtors() const; llvm::Expected getSymbolAddress(llvm::StringRef Name, SymbolNameKind NameKind) const; + llvm::orc::LLJIT *getExecutionEngine() const { return Jit.get(); } }; } // end namespace clang diff --git a/clang/lib/Interpreter/Interpreter.cpp b/clang/lib/Interpreter/Interpreter.cpp index b2e7727be39a0..470c9c289a749 100644 --- a/clang/lib/Interpreter/Interpreter.cpp +++ b/clang/lib/Interpreter/Interpreter.cpp @@ -196,6 +196,12 @@ const CompilerInstance *Interpreter::getCompilerInstance() const { return IncrParser->getCI(); } +const llvm::orc::LLJIT *Interpreter::getExecutionEngine() const { + if (IncrExecutor) + return IncrExecutor->getExecutionEngine(); + return nullptr; +} + llvm::Expected Interpreter::Parse(llvm::StringRef Code) { return IncrParser->Parse(Code); From ec13fed5867f674bb96ab5502629ec209ef5a73a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 1 Apr 2022 10:54:14 +0100 Subject: [PATCH 272/316] [X86] lowerV8I16Shuffle - use explicit SmallVector width to avoid MSVC AVX alignment bug As discussed on Issue #54645 - building llc with /AVX can result in incorrectly aligned structs (cherry picked from commit cb5c4a5917889bd12c5662c8b550cde11924d570) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 77c2e7d169907..600d146cb1245 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15796,7 +15796,8 @@ static SDValue lowerV8I16Shuffle(const SDLoc &DL, ArrayRef Mask, V1 = extract128BitVector(V1V2, 0, DAG, DL); V2 = extract128BitVector(V1V2, 4, DAG, DL); } else { - SmallVector DWordClearOps(4, DAG.getConstant(0, DL, MVT::i32)); + SmallVector DWordClearOps(4, + DAG.getConstant(0, DL, MVT::i32)); for (unsigned i = 0; i != 4; i += 1 << (NumEvenDrops - 1)) DWordClearOps[i] = DAG.getConstant(0xFFFF, DL, MVT::i32); SDValue DWordClearMask = From d4e3c50b2bda796636bb283ab1a615f3333f75d9 Mon Sep 17 00:00:00 2001 From: Arthur O'Dwyer Date: Wed, 2 Feb 2022 12:23:51 -0500 Subject: [PATCH 273/316] [libc++] Define `namespace views` in its own detail header. Discovered in the comments on D118748: we would like this namespace to exist anytime Ranges exists, regardless of whether concepts syntax is supported. Also, we'd like to fully granularize the header, which means not putting any loose declarations at the top level. Differential Revision: https://reviews.llvm.org/D118809 (cherry picked from commit 44cdca37c01a58da94087be8ebd0ee2bd2ba724e) --- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__ranges/views.h | 35 +++++++++++++++++++ libcxx/include/module.modulemap | 1 + libcxx/include/ranges | 11 +----- .../ranges/views.module.verify.cpp | 15 ++++++++ 5 files changed, 53 insertions(+), 10 deletions(-) create mode 100644 libcxx/include/__ranges/views.h create mode 100644 libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index 7fdf2ff27b344..53700fc9e2c46 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -350,6 +350,7 @@ set(files __ranges/take_view.h __ranges/transform_view.h __ranges/view_interface.h + __ranges/views.h __split_buffer __std_stream __string diff --git a/libcxx/include/__ranges/views.h b/libcxx/include/__ranges/views.h new file mode 100644 index 0000000000000..8cc5ba3d2aca5 --- /dev/null +++ b/libcxx/include/__ranges/views.h @@ -0,0 +1,35 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP___RANGES_VIEWS +#define _LIBCPP___RANGES_VIEWS + +#include <__config> + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +#if _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + +namespace ranges { + +namespace views { } + +} // namespace ranges + +namespace views = ranges::views; + +#endif // _LIBCPP_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP___RANGES_VIEWS diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index 749c17f8bc08f..9e3643faee095 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -817,6 +817,7 @@ module std [system] { export functional.__functional.perfect_forward } module view_interface { private header "__ranges/view_interface.h" } + module views { private header "__ranges/views.h" } } } module ratio { diff --git a/libcxx/include/ranges b/libcxx/include/ranges index 82ad7f4d507f2..9b831160d683a 100644 --- a/libcxx/include/ranges +++ b/libcxx/include/ranges @@ -223,6 +223,7 @@ namespace std::ranges { #include <__ranges/take_view.h> #include <__ranges/transform_view.h> #include <__ranges/view_interface.h> +#include <__ranges/views.h> #include // Required by the standard. #include // Required by the standard. #include // Required by the standard. @@ -233,14 +234,4 @@ namespace std::ranges { #pragma GCC system_header #endif -#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) - -_LIBCPP_BEGIN_NAMESPACE_STD - -namespace views = ranges::views; - -_LIBCPP_END_NAMESPACE_STD - -#endif // !defined(_LIBCPP_HAS_NO_INCOMPLETE_RANGES) - #endif // _LIBCPP_RANGES diff --git a/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp b/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp new file mode 100644 index 0000000000000..3b5b617096870 --- /dev/null +++ b/libcxx/test/libcxx/diagnostics/detail.headers/ranges/views.module.verify.cpp @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: modules-build + +// WARNING: This test was generated by 'generate_private_header_tests.py' +// and should not be edited manually. + +// expected-error@*:* {{use of private header from outside its module: '__ranges/views.h'}} +#include <__ranges/views.h> From 8475349bd6398edb4b2f13dead70e143b71d2263 Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Tue, 15 Mar 2022 13:24:32 +0000 Subject: [PATCH 274/316] [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77 Reviewed By: amilendra Differential Revision: https://reviews.llvm.org/D121206 --- clang/test/Driver/aarch64-ssbs.c | 4 ++++ clang/test/Preprocessor/aarch64-target-features.c | 2 +- llvm/lib/Support/AArch64TargetParser.cpp | 2 ++ llvm/lib/Target/AArch64/AArch64.td | 7 ++++--- 4 files changed, 11 insertions(+), 4 deletions(-) diff --git a/clang/test/Driver/aarch64-ssbs.c b/clang/test/Driver/aarch64-ssbs.c index 86c93ae926404..209255405d28d 100644 --- a/clang/test/Driver/aarch64-ssbs.c +++ b/clang/test/Driver/aarch64-ssbs.c @@ -1,7 +1,11 @@ // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+ssbs %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1 %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-a77 %s 2>&1 | FileCheck %s // CHECK: "-target-feature" "+ssbs" // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+nossbs %s 2>&1 | FileCheck %s --check-prefix=NOSSBS +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c+nossbs %s 2>&1 | FileCheck %s --check-prefix=NOSSBS // NOSSBS: "-target-feature" "-ssbs" // RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTSSBS diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 3461af3ecbd20..839fc08031c92 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -285,7 +285,7 @@ // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16" +// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" "+fullfp16" // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16" // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp index cdf7c8ade9aac..bb19e2714be10 100644 --- a/llvm/lib/Support/AArch64TargetParser.cpp +++ b/llvm/lib/Support/AArch64TargetParser.cpp @@ -120,6 +120,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions, Features.push_back("+mops"); if (Extensions & AArch64::AEK_PERFMON) Features.push_back("+perfmon"); + if (Extensions & AArch64::AEK_SSBS) + Features.push_back("+ssbs"); return true; } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 9a04b28a8b8f1..70a79864d2c56 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -953,7 +953,7 @@ def ProcessorFeatures { FeatureRCPC, FeatureSSBS]; list A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, - FeatureRCPC]; + FeatureRCPC, FeatureSSBS]; list A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon, FeatureSPE, @@ -971,11 +971,12 @@ def ProcessorFeatures { FeatureSB, FeatureSpecRestrict]; list X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, - FeatureSPE, FeatureFullFP16, FeatureDotProd]; + FeatureSPE, FeatureFullFP16, FeatureDotProd, + FeatureSSBS]; list X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, - FeaturePAuth]; + FeaturePAuth, FeatureSSBS]; list X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, From 6697c5bc3a1e3e7a3ffbee6680b58338df4b5818 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= Date: Thu, 31 Mar 2022 09:55:25 +0200 Subject: [PATCH 275/316] [compiler-rt] [scudo] Use -mcrc32 on x86 when available Update the hardware CRC32 logic in scudo to support using `-mcrc32` instead of `-msse4.2`. The CRC32 intrinsics use the former flag in the newer compiler versions, e.g. in clang since 12fa608af44a. With these versions of clang, passing `-msse4.2` is insufficient to enable the instructions and causes build failures when `-march` does not enable CRC32 implicitly: /var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/scudo_crc32.cpp:20:10: error: always_inline function '_mm_crc32_u32' requires target feature 'crc32', but would be inlined into function 'computeHardwareCRC32' that is compiled without support for 'crc32' return CRC32_INTRINSIC(Crc, Data); ^ /var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/scudo_crc32.h:27:27: note: expanded from macro 'CRC32_INTRINSIC' # define CRC32_INTRINSIC FIRST_32_SECOND_64(_mm_crc32_u32, _mm_crc32_u64) ^ /var/tmp/portage/sys-libs/compiler-rt-sanitizers-14.0.0/work/compiler-rt/lib/scudo/../sanitizer_common/sanitizer_platform.h:132:36: note: expanded from macro 'FIRST_32_SECOND_64' # define FIRST_32_SECOND_64(a, b) (a) ^ 1 error generated. For backwards compatibility, use `-mcrc32` when available and fall back to `-msse4.2`. The `` header remains in use as it still works and is compatible with GCC, while clang's `` is not. Use __builtin_ia32*() rather than _mm_crc32*() when using `-mcrc32` to preserve compatibility with GCC. _mm_crc32*() are aliases to __builtin_ia32*() in both compilers but GCC requires `-msse4.2` for the former, while both use `-mcrc32` for the latter. Originally reported in https://bugs.gentoo.org/835870. Differential Revision: https://reviews.llvm.org/D122789 (cherry picked from commit fd1da784ac644492f8ca40064baf3ef360352f55) --- compiler-rt/cmake/config-ix.cmake | 1 + compiler-rt/lib/scudo/CMakeLists.txt | 7 +++++-- compiler-rt/lib/scudo/scudo_allocator.cpp | 4 ++-- compiler-rt/lib/scudo/scudo_crc32.cpp | 4 ++-- compiler-rt/lib/scudo/scudo_crc32.h | 12 ++++++++---- compiler-rt/lib/scudo/standalone/CMakeLists.txt | 7 +++++-- compiler-rt/lib/scudo/standalone/checksum.h | 8 ++++++-- compiler-rt/lib/scudo/standalone/chunk.h | 4 ++-- compiler-rt/lib/scudo/standalone/crc32_hw.cpp | 4 ++-- 9 files changed, 33 insertions(+), 18 deletions(-) diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake index 4299a0589a7b7..fc62d5ecc0a94 100644 --- a/compiler-rt/cmake/config-ix.cmake +++ b/compiler-rt/cmake/config-ix.cmake @@ -78,6 +78,7 @@ check_cxx_compiler_flag(-fno-profile-generate COMPILER_RT_HAS_FNO_PROFILE_GENERA check_cxx_compiler_flag(-fno-profile-instr-generate COMPILER_RT_HAS_FNO_PROFILE_INSTR_GENERATE_FLAG) check_cxx_compiler_flag(-fno-profile-instr-use COMPILER_RT_HAS_FNO_PROFILE_INSTR_USE_FLAG) check_cxx_compiler_flag(-fno-coverage-mapping COMPILER_RT_HAS_FNO_COVERAGE_MAPPING_FLAG) +check_cxx_compiler_flag("-Werror -mcrc32" COMPILER_RT_HAS_MCRC32_FLAG) check_cxx_compiler_flag("-Werror -msse3" COMPILER_RT_HAS_MSSE3_FLAG) check_cxx_compiler_flag("-Werror -msse4.2" COMPILER_RT_HAS_MSSE4_2_FLAG) check_cxx_compiler_flag(--sysroot=. COMPILER_RT_HAS_SYSROOT_FLAG) diff --git a/compiler-rt/lib/scudo/CMakeLists.txt b/compiler-rt/lib/scudo/CMakeLists.txt index 995e853e2a4d7..31a6976960f76 100644 --- a/compiler-rt/lib/scudo/CMakeLists.txt +++ b/compiler-rt/lib/scudo/CMakeLists.txt @@ -86,8 +86,11 @@ set(SCUDO_HEADERS scudo_tsd_shared.inc scudo_utils.h) -# Enable the SSE 4.2 instruction set for scudo_crc32.cpp, if available. -if (COMPILER_RT_HAS_MSSE4_2_FLAG) +# Enable the necessary instruction set for scudo_crc32.cpp, if available. +# Newer compiler versions use -mcrc32 rather than -msse4.2. +if (COMPILER_RT_HAS_MCRC32_FLAG) + set_source_files_properties(scudo_crc32.cpp PROPERTIES COMPILE_FLAGS -mcrc32) +elseif (COMPILER_RT_HAS_MSSE4_2_FLAG) set_source_files_properties(scudo_crc32.cpp PROPERTIES COMPILE_FLAGS -msse4.2) endif() diff --git a/compiler-rt/lib/scudo/scudo_allocator.cpp b/compiler-rt/lib/scudo/scudo_allocator.cpp index 5b6ac8b354934..6a6b577ab0025 100644 --- a/compiler-rt/lib/scudo/scudo_allocator.cpp +++ b/compiler-rt/lib/scudo/scudo_allocator.cpp @@ -49,7 +49,7 @@ inline u32 computeCRC32(u32 Crc, uptr Value, uptr *Array, uptr ArraySize) { // as opposed to only for scudo_crc32.cpp. This means that other hardware // specific instructions were likely emitted at other places, and as a // result there is no reason to not use it here. -#if defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#if defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) Crc = CRC32_INTRINSIC(Crc, Value); for (uptr i = 0; i < ArraySize; i++) Crc = CRC32_INTRINSIC(Crc, Array[i]); @@ -65,7 +65,7 @@ inline u32 computeCRC32(u32 Crc, uptr Value, uptr *Array, uptr ArraySize) { for (uptr i = 0; i < ArraySize; i++) Crc = computeSoftwareCRC32(Crc, Array[i]); return Crc; -#endif // defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#endif // defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) } static BackendT &getBackend(); diff --git a/compiler-rt/lib/scudo/scudo_crc32.cpp b/compiler-rt/lib/scudo/scudo_crc32.cpp index 87473505fe792..137c44c5c1cda 100644 --- a/compiler-rt/lib/scudo/scudo_crc32.cpp +++ b/compiler-rt/lib/scudo/scudo_crc32.cpp @@ -15,10 +15,10 @@ namespace __scudo { -#if defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#if defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) u32 computeHardwareCRC32(u32 Crc, uptr Data) { return CRC32_INTRINSIC(Crc, Data); } -#endif // defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#endif // defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) } // namespace __scudo diff --git a/compiler-rt/lib/scudo/scudo_crc32.h b/compiler-rt/lib/scudo/scudo_crc32.h index ef40595a56d1f..4314d30e929fe 100644 --- a/compiler-rt/lib/scudo/scudo_crc32.h +++ b/compiler-rt/lib/scudo/scudo_crc32.h @@ -16,13 +16,17 @@ #include "sanitizer_common/sanitizer_internal_defs.h" // Hardware CRC32 is supported at compilation via the following: -// - for i386 & x86_64: -msse4.2 +// - for i386 & x86_64: -mcrc32 (earlier: -msse4.2) // - for ARM & AArch64: -march=armv8-a+crc or -mcrc // An additional check must be performed at runtime as well to make sure the // emitted instructions are valid on the target host. -#if defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) -# ifdef __SSE4_2__ +#if defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +# if defined(__CRC32__) +// NB: clang has but GCC does not +# include +# define CRC32_INTRINSIC FIRST_32_SECOND_64(__builtin_ia32_crc32si, __builtin_ia32_crc32di) +# elif defined(__SSE4_2__) # include # define CRC32_INTRINSIC FIRST_32_SECOND_64(_mm_crc32_u32, _mm_crc32_u64) # endif @@ -30,7 +34,7 @@ # include # define CRC32_INTRINSIC FIRST_32_SECOND_64(__crc32cw, __crc32cd) # endif -#endif // defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#endif // defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) namespace __scudo { diff --git a/compiler-rt/lib/scudo/standalone/CMakeLists.txt b/compiler-rt/lib/scudo/standalone/CMakeLists.txt index 739f131bdefdf..ae5c354768c89 100644 --- a/compiler-rt/lib/scudo/standalone/CMakeLists.txt +++ b/compiler-rt/lib/scudo/standalone/CMakeLists.txt @@ -97,8 +97,11 @@ set(SCUDO_SOURCES string_utils.cpp ) -# Enable the SSE 4.2 instruction set for crc32_hw.cpp, if available. -if (COMPILER_RT_HAS_MSSE4_2_FLAG) +# Enable the necessary instruction set for scudo_crc32.cpp, if available. +# Newer compiler versions use -mcrc32 rather than -msse4.2. +if (COMPILER_RT_HAS_MCRC32_FLAG) + set_source_files_properties(crc32_hw.cpp PROPERTIES COMPILE_FLAGS -mcrc32) +elseif (COMPILER_RT_HAS_MSSE4_2_FLAG) set_source_files_properties(crc32_hw.cpp PROPERTIES COMPILE_FLAGS -msse4.2) endif() diff --git a/compiler-rt/lib/scudo/standalone/checksum.h b/compiler-rt/lib/scudo/standalone/checksum.h index a63b1b4f064d1..0f787ce2b5cde 100644 --- a/compiler-rt/lib/scudo/standalone/checksum.h +++ b/compiler-rt/lib/scudo/standalone/checksum.h @@ -12,12 +12,16 @@ #include "internal_defs.h" // Hardware CRC32 is supported at compilation via the following: -// - for i386 & x86_64: -msse4.2 +// - for i386 & x86_64: -mcrc32 (earlier: -msse4.2) // - for ARM & AArch64: -march=armv8-a+crc or -mcrc // An additional check must be performed at runtime as well to make sure the // emitted instructions are valid on the target host. -#ifdef __SSE4_2__ +#if defined(__CRC32__) +// NB: clang has but GCC does not +#include +#define CRC32_INTRINSIC FIRST_32_SECOND_64(__builtin_ia32_crc32si, __builtin_ia32_crc32di) +#elif defined(__SSE4_2__) #include #define CRC32_INTRINSIC FIRST_32_SECOND_64(_mm_crc32_u32, _mm_crc32_u64) #endif diff --git a/compiler-rt/lib/scudo/standalone/chunk.h b/compiler-rt/lib/scudo/standalone/chunk.h index 69b8e1b12a91c..0581420dfc99a 100644 --- a/compiler-rt/lib/scudo/standalone/chunk.h +++ b/compiler-rt/lib/scudo/standalone/chunk.h @@ -25,7 +25,7 @@ inline u16 computeChecksum(u32 Seed, uptr Value, uptr *Array, uptr ArraySize) { // as opposed to only for crc32_hw.cpp. This means that other hardware // specific instructions were likely emitted at other places, and as a result // there is no reason to not use it here. -#if defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#if defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) u32 Crc = static_cast(CRC32_INTRINSIC(Seed, Value)); for (uptr I = 0; I < ArraySize; I++) Crc = static_cast(CRC32_INTRINSIC(Crc, Array[I])); @@ -42,7 +42,7 @@ inline u16 computeChecksum(u32 Seed, uptr Value, uptr *Array, uptr ArraySize) { Checksum = computeBSDChecksum(Checksum, Array[I]); return Checksum; } -#endif // defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#endif // defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) } namespace Chunk { diff --git a/compiler-rt/lib/scudo/standalone/crc32_hw.cpp b/compiler-rt/lib/scudo/standalone/crc32_hw.cpp index 62841ba510199..d13c615498fff 100644 --- a/compiler-rt/lib/scudo/standalone/crc32_hw.cpp +++ b/compiler-rt/lib/scudo/standalone/crc32_hw.cpp @@ -10,10 +10,10 @@ namespace scudo { -#if defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#if defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) u32 computeHardwareCRC32(u32 Crc, uptr Data) { return static_cast(CRC32_INTRINSIC(Crc, Data)); } -#endif // defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) +#endif // defined(__CRC32__) || defined(__SSE4_2__) || defined(__ARM_FEATURE_CRC32) } // namespace scudo From c62053979489ccb002efe411c3af059addcb5d7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Wed, 6 Apr 2022 00:44:38 +0300 Subject: [PATCH 276/316] [AArch64] Fix the upper limit for folded address offsets for COFF In COFF, the immediates in IMAGE_REL_ARM64_PAGEBASE_REL21 relocations are limited to 21 bit signed, i.e. the offset has to be less than (1 << 20). The previous limit did intend to cover for this case, but had missed that the 21 bit field was signed. This fixes issue https://github.com/llvm/llvm-project/issues/54753. Differential Revision: https://reviews.llvm.org/D123160 (cherry picked from commit 8d7a17b7c8b7151b8453903db96fc7f45d9b1bae) --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 7 ++++--- .../GISel/AArch64PreLegalizerCombiner.cpp | 7 ++++--- llvm/test/CodeGen/AArch64/fold-global-offsets.ll | 16 ++++++++-------- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 3008466159bb2..77260c89df115 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -17115,13 +17115,14 @@ static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG, // Check whether folding this offset is legal. It must not go out of bounds of // the referenced object to avoid violating the code model, and must be - // smaller than 2^21 because this is the largest offset expressible in all - // object formats. + // smaller than 2^20 because this is the largest offset expressible in all + // object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF + // stores an immediate signed 21 bit offset.) // // This check also prevents us from folding negative offsets, which will end // up being treated in the same way as large positive ones. They could also // cause code model violations, and aren't really common enough to matter. - if (Offset >= (1 << 21)) + if (Offset >= (1 << 20)) return SDValue(); const GlobalValue *GV = GN->getGlobal(); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp index d3f4130d2ba14..3730030aa140e 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -162,13 +162,14 @@ static bool matchFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI, // Check whether folding this offset is legal. It must not go out of bounds of // the referenced object to avoid violating the code model, and must be - // smaller than 2^21 because this is the largest offset expressible in all - // object formats. + // smaller than 2^20 because this is the largest offset expressible in all + // object formats. (The IMAGE_REL_ARM64_PAGEBASE_REL21 relocation in COFF + // stores an immediate signed 21 bit offset.) // // This check also prevents us from folding negative offsets, which will end // up being treated in the same way as large positive ones. They could also // cause code model violations, and aren't really common enough to matter. - if (NewOffset >= (1 << 21)) + if (NewOffset >= (1 << 20)) return false; Type *T = GV->getValueType(); diff --git a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll index c57de0d796bda..aa5435c4fd6b3 100644 --- a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll +++ b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll @@ -84,23 +84,23 @@ define [2 x i64] @f4() { define i64 @f5() { ; CHECK-LABEL: f5: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, x2+2097144 -; CHECK-NEXT: ldr x0, [x8, :lo12:x2+2097144] +; CHECK-NEXT: adrp x8, x2+1048568 +; CHECK-NEXT: ldr x0, [x8, :lo12:x2+1048568] ; CHECK-NEXT: ret ; ; GISEL-LABEL: f5: ; GISEL: // %bb.0: -; GISEL-NEXT: adrp x8, x2+2097144 -; GISEL-NEXT: ldr x0, [x8, :lo12:x2+2097144] +; GISEL-NEXT: adrp x8, x2+1048568 +; GISEL-NEXT: ldr x0, [x8, :lo12:x2+1048568] ; GISEL-NEXT: ret - %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262143) + %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 131071) ret i64 %l } define i64 @f6() { ; CHECK-LABEL: f6: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #2097152 +; CHECK-NEXT: mov w8, #1048576 ; CHECK-NEXT: adrp x9, x2 ; CHECK-NEXT: add x9, x9, :lo12:x2 ; CHECK-NEXT: ldr x0, [x9, x8] @@ -108,12 +108,12 @@ define i64 @f6() { ; ; GISEL-LABEL: f6: ; GISEL: // %bb.0: -; GISEL-NEXT: mov w8, #2097152 +; GISEL-NEXT: mov w8, #1048576 ; GISEL-NEXT: adrp x9, x2 ; GISEL-NEXT: add x9, x9, :lo12:x2 ; GISEL-NEXT: ldr x0, [x9, x8] ; GISEL-NEXT: ret - %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262144) + %l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 131072) ret i64 %l } From 5c9eed741dbd32bf3de6ba177a56224822e976bb Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 14 Mar 2022 22:05:35 +0100 Subject: [PATCH 277/316] [libc++] Make __dir_stream visibility declaration consistent The class `__dir_stream` is currently declared in two places: as a top-level forward declaration in `directory_iterator.h`, and as a friend declaration in class `directory_entry`, in `directory_entry.h`. The former has a `_LIBCPP_HIDDEN` attribute, but the latter does not, causing the Firefox build to complain about the visibility not matching the previous declaration. This is because Firefox plays games with pushing and popping visibility. Work around this by making both `__dir_stream` declarations consistently use `_LIBCPP_HIDDEN`. Reviewed By: ldionne, philnik, #libc Differential Revision: https://reviews.llvm.org/D121639 (cherry picked from commit 7ab1ab0db40158e6f0794637054c98376e236a6d) --- libcxx/include/__filesystem/directory_entry.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/include/__filesystem/directory_entry.h b/libcxx/include/__filesystem/directory_entry.h index 91dd1a2145883..95e45c02307fa 100644 --- a/libcxx/include/__filesystem/directory_entry.h +++ b/libcxx/include/__filesystem/directory_entry.h @@ -249,7 +249,7 @@ class directory_entry { private: friend class directory_iterator; friend class recursive_directory_iterator; - friend class __dir_stream; + friend class _LIBCPP_HIDDEN __dir_stream; enum _CacheType : unsigned char { _Empty, From 87599bdabbd16f109d317af1164de5a02ff0aca4 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 6 Apr 2022 09:41:57 +0800 Subject: [PATCH 278/316] [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file RISCVMachineFunctionInfo has some fields like VarArgsFrameIndex and VarArgsSaveSize are calculated at ISel lowering stage, those info are not contained in MIR files, that cause test cases rely on those field can't not reproduce correctly by MIR dump files. This patch adding the MIR read/write for those fields. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D123178 --- llvm/lib/Target/RISCV/CMakeLists.txt | 1 + .../Target/RISCV/RISCVMachineFunctionInfo.cpp | 30 ++++ .../Target/RISCV/RISCVMachineFunctionInfo.h | 25 ++++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 23 +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h | 8 + .../MIR/RISCV/machine-function-info.mir | 138 ++++++++++++++++++ 6 files changed, 225 insertions(+) create mode 100644 llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp create mode 100644 llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt index d1b0863d439b2..1e042147223af 100644 --- a/llvm/lib/Target/RISCV/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/CMakeLists.txt @@ -31,6 +31,7 @@ add_llvm_target(RISCVCodeGen RISCVISelDAGToDAG.cpp RISCVISelLowering.cpp RISCVLegalizerInfo.cpp + RISCVMachineFunctionInfo.cpp RISCVMCInstLower.cpp RISCVMergeBaseOffset.cpp RISCVRegisterBankInfo.cpp diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp new file mode 100644 index 0000000000000..bde0326a8de41 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp @@ -0,0 +1,30 @@ +//=- RISCVMachineFunctionInfo.cpp - RISCV machine function info ---*- C++ -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares RISCV-specific per-machine-function information. +// +//===----------------------------------------------------------------------===// + +#include "RISCVMachineFunctionInfo.h" + +using namespace llvm; + +yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo( + const llvm::RISCVMachineFunctionInfo &MFI) + : VarArgsFrameIndex(MFI.getVarArgsFrameIndex()), + VarArgsSaveSize(MFI.getVarArgsSaveSize()) {} + +void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) { + MappingTraits::mapping(YamlIO, *this); +} + +void RISCVMachineFunctionInfo::initializeBaseYamlFields( + const yaml::RISCVMachineFunctionInfo &YamlMFI) { + VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex; + VarArgsSaveSize = YamlMFI.VarArgsSaveSize; +} diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h index b5609e9a3890d..a549ec211a940 100644 --- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -14,11 +14,34 @@ #define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H #include "RISCVSubtarget.h" +#include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" namespace llvm { +class RISCVMachineFunctionInfo; + +namespace yaml { +struct RISCVMachineFunctionInfo final : public yaml::MachineFunctionInfo { + int VarArgsFrameIndex; + int VarArgsSaveSize; + + RISCVMachineFunctionInfo() = default; + RISCVMachineFunctionInfo(const llvm::RISCVMachineFunctionInfo &MFI); + + void mappingImpl(yaml::IO &YamlIO) override; + ~RISCVMachineFunctionInfo() = default; +}; + +template <> struct MappingTraits { + static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) { + YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex); + YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize); + } +}; +} // end namespace yaml + /// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo /// and contains private RISCV-specific information for each MachineFunction. class RISCVMachineFunctionInfo : public MachineFunctionInfo { @@ -74,6 +97,8 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo { unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; } void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; } + + void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI); }; } // end namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index db5e2f1eeb6f0..0248ea0039bc2 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -13,6 +13,7 @@ #include "RISCVTargetMachine.h" #include "MCTargetDesc/RISCVBaseInfo.h" #include "RISCV.h" +#include "RISCVMachineFunctionInfo.h" #include "RISCVTargetObjectFile.h" #include "RISCVTargetTransformInfo.h" #include "TargetInfo/RISCVTargetInfo.h" @@ -22,6 +23,8 @@ #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" +#include "llvm/CodeGen/MIRParser/MIParser.h" +#include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/TargetPassConfig.h" @@ -208,3 +211,23 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVMergeBaseOffsetOptPass()); addPass(createRISCVInsertVSETVLIPass()); } + +yaml::MachineFunctionInfo * +RISCVTargetMachine::createDefaultFuncInfoYAML() const { + return new yaml::RISCVMachineFunctionInfo(); +} + +yaml::MachineFunctionInfo * +RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const { + const auto *MFI = MF.getInfo(); + return new yaml::RISCVMachineFunctionInfo(*MFI); +} + +bool RISCVTargetMachine::parseMachineFunctionInfo( + const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS, + SMDiagnostic &Error, SMRange &SourceRange) const { + const auto &YamlMFI = + static_cast(MFI); + PFS.MF.getInfo()->initializeBaseYamlFields(YamlMFI); + return false; +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h index 3156333f7ee17..2a0212c846a04 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -46,6 +46,14 @@ class RISCVTargetMachine : public LLVMTargetMachine { virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override; + + yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; + yaml::MachineFunctionInfo * + convertFuncInfoToYAML(const MachineFunction &MF) const override; + bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, + PerFunctionMIParsingState &PFS, + SMDiagnostic &Error, + SMRange &SourceRange) const override; }; } // namespace llvm diff --git a/llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir b/llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir new file mode 100644 index 0000000000000..1861c61c30f63 --- /dev/null +++ b/llvm/test/CodeGen/MIR/RISCV/machine-function-info.mir @@ -0,0 +1,138 @@ +# RUN: llc -mtriple=riscv64 -run-pass none %s -o - | FileCheck %s + +--- | + ; ModuleID = 'foo.ll' + source_filename = "foo.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + define void @foo(i32 %0, ...) { + ret void + } + +... +--- +name: foo +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } + - { id: 4, class: gpr, preferred-register: '' } + - { id: 5, class: gpr, preferred-register: '' } + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: gpr, preferred-register: '' } +liveins: + - { reg: '$x11', virtual-reg: '%1' } + - { reg: '$x12', virtual-reg: '%2' } + - { reg: '$x13', virtual-reg: '%3' } + - { reg: '$x14', virtual-reg: '%4' } + - { reg: '$x15', virtual-reg: '%5' } + - { reg: '$x16', virtual-reg: '%6' } + - { reg: '$x17', virtual-reg: '%7' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: + - { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, type: default, offset: -24, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, type: default, offset: -32, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, type: default, offset: -40, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, type: default, offset: -48, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, type: default, offset: -56, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 7, type: default, offset: -64, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 8, type: default, offset: -56, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 64 +body: | + bb.0 (%ir-block.1): + liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-LABEL: name: foo + ; CHECK: machineFunctionInfo: + ; CHECK-NEXT: varArgsFrameIndex: -1 + ; CHECK-NEXT: varArgsSaveSize: 64 + ; CHECK: liveins: $x11, $x12, $x13, $x14, $x15, $x16, $x17 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x17 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x16 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x14 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x13 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: SD [[COPY]], %fixed-stack.8, 0 :: (store (s64)) + ; CHECK-NEXT: SD [[COPY1]], %fixed-stack.7, 0 :: (store (s64) into %fixed-stack.7, align 16) + ; CHECK-NEXT: SD [[COPY2]], %fixed-stack.6, 0 :: (store (s64)) + ; CHECK-NEXT: SD [[COPY3]], %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16) + ; CHECK-NEXT: SD [[COPY4]], %fixed-stack.4, 0 :: (store (s64)) + ; CHECK-NEXT: SD [[COPY5]], %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16) + ; CHECK-NEXT: SD [[COPY6]], %fixed-stack.2, 0 :: (store (s64)) + ; CHECK-NEXT: PseudoRET + %7:gpr = COPY $x17 + %6:gpr = COPY $x16 + %5:gpr = COPY $x15 + %4:gpr = COPY $x14 + %3:gpr = COPY $x13 + %2:gpr = COPY $x12 + %1:gpr = COPY $x11 + SD %7, %fixed-stack.0, 0 :: (store (s64)) + SD %6, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16) + SD %5, %fixed-stack.2, 0 :: (store (s64)) + SD %4, %fixed-stack.3, 0 :: (store (s64) into %fixed-stack.3, align 16) + SD %3, %fixed-stack.4, 0 :: (store (s64)) + SD %2, %fixed-stack.5, 0 :: (store (s64) into %fixed-stack.5, align 16) + SD %1, %fixed-stack.6, 0 :: (store (s64)) + PseudoRET + +... From b6e91d4a331e6e3af178f16347ad308237f90340 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 6 Apr 2022 09:51:09 +0800 Subject: [PATCH 279/316] [RISCV] Pre-commit for fixing stack offset for RVV object Reviewed By: rogfer01, frasercrmck Differential Revision: https://reviews.llvm.org/D123179 --- .../rvv/wrong-stack-offset-for-rvv-object.mir | 220 ++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir new file mode 100644 index 0000000000000..93471f65d5753 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir @@ -0,0 +1,220 @@ +# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog \ +# RUN: -riscv-v-vector-bits-min=512 -o - %s | FileCheck %s +# +# Stack layout of this program +# |--------------------------| -- <-- Incoming SP +# | a7 (Vaarg) | +# | ------------------------ | -- <-- New SP + vlenb + 56 +# | a6 (Vaarg) | +# | ------------------------ | -- <-- New SP + vlenb + 48 +# | ra (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 40 +# | s0 (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 32 +# | s1 (Callee-saved reg) | +# | ------------------------ | -- <-- New SP + vlenb + 24 +# | v8 (RVV objects) | +# | ------------------------ | -- <-- New SP + 24 +# | buf1 | +# |--------------------------| -- <-- New SP + 16 +# | Stack ID 5 | +# |--------------------------| -- <-- New SP + 8 +# | Stack ID 6 | +# |--------------------------| -- <-- New SP + +--- | + ; ModuleID = 'wrong-stack-offset-for-rvv-object.ll' + source_filename = "wrong-stack-offset-for-rvv-object.ll" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" + target triple = "riscv64" + + %struct = type { i32 } + + define void @asm_fprintf(%struct %file, i8* %p, [10 x i8]* %buf, i8* %arrayidx3, <2 x i8>* %0, i8* %1, ...) #0 { + entry: + %buf1 = alloca [10 x i8], i32 0, align 8 + %arrayidx32 = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 1 + br label %while.cond + + while.cond: ; preds = %while.cond, %sw.bb, %entry + %incdec.ptr = getelementptr inbounds i8, i8* undef, i64 1 + %2 = load i8, i8* null, align 1 + %3 = zext i8 0 to i64 + %cond = icmp eq i64 %3, 0 + br i1 %cond, label %sw.bb, label %while.cond + + sw.bb: ; preds = %while.cond + %4 = load i8, i8* null, align 1 + store <2 x i8> zeroinitializer, <2 x i8>* %0, align 1 + %call = call i32 (i8*, ...) @fprintf(i8* %p) + br label %while.cond + } + + declare i32 @fprintf(i8*, ...) #0 + + attributes #0 = { "target-features"="+m,+v" } + +... +--- +name: asm_fprintf +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +failsVerification: false +tracksDebugUserValues: true +registers: [] +liveins: + - { reg: '$x11', virtual-reg: '' } + - { reg: '$x14', virtual-reg: '' } + - { reg: '$x16', virtual-reg: '' } + - { reg: '$x17', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: + - { id: 0, type: default, offset: -8, size: 8, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: -16, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, type: default, offset: -16, size: 8, alignment: 16, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: buf1, type: default, offset: 0, size: 1, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8, + stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: -1 + varArgsSaveSize: 16 +body: | + ; CHECK-LABEL: name: asm_fprintf + ; CHECK: stack: + ; CHECK-NEXT: - { id: 0, name: buf1, type: default, offset: -48, size: 1, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 1, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '$x1', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '$x8', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 4, name: '', type: spill-slot, offset: -40, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '$x9', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 5, name: '', type: default, offset: -56, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK-NEXT: - { id: 6, name: '', type: default, offset: -64, size: 8, alignment: 8, + ; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true, + ; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x11, $x14, $x16, $x17, $x1, $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -64 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-NEXT: SD killed $x1, $x2, 40 :: (store (s64) into %stack.2) + ; CHECK-NEXT: SD killed $x8, $x2, 32 :: (store (s64) into %stack.3) + ; CHECK-NEXT: SD killed $x9, $x2, 24 :: (store (s64) into %stack.4) + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40 + ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB + ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 + ; CHECK-NEXT: renamable $x8 = COPY $x14 + ; CHECK-NEXT: renamable $x9 = COPY $x11 + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: SD killed renamable $x17, killed $x10, 56 :: (store (s64)) + ; CHECK-NEXT: $x10 = PseudoReadVLENB + ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 + ; CHECK-NEXT: SD killed renamable $x16, killed $x10, 48 :: (store (s64) into %fixed-stack.1, align 16) + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype + ; CHECK-NEXT: $x10 = ADDI $x2, 40 + ; CHECK-NEXT: PseudoVSPILL_M1 killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.while.cond: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BNE $x0, $x0, %bb.1 + ; CHECK-NEXT: PseudoBR %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.sw.bb: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x8, $x9 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: $x10 = ADDI $x2, 40 + ; CHECK-NEXT: renamable $v8 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.1, align 8) + ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) + ; CHECK-NEXT: $x10 = COPY renamable $x9 + ; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + ; CHECK-NEXT: PseudoBR %bb.1 + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $x11, $x14, $x16, $x17 + + renamable $x8 = COPY $x14 + renamable $x9 = COPY $x11 + SD killed renamable $x17, %fixed-stack.0, 0 :: (store (s64)) + SD killed renamable $x16, %fixed-stack.1, 0 :: (store (s64) into %fixed-stack.1, align 16) + dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype + PseudoVSPILL_M1 killed renamable $v8, %stack.1 :: (store unknown-size into %stack.1, align 8) + + bb.1.while.cond: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + liveins: $x8, $x9 + + BNE $x0, $x0, %bb.1 + PseudoBR %bb.2 + + bb.2.sw.bb: + successors: %bb.1(0x80000000) + liveins: $x8, $x9 + + dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype + renamable $v8 = PseudoVRELOAD_M1 %stack.1 :: (load unknown-size from %stack.1, align 8) + PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) + ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2 + $x10 = COPY renamable $x9 + PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 + ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2 + PseudoBR %bb.1 + +... From d0f27fb449525528a5688b7678dd9a8082bb6c41 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 5 Apr 2022 23:29:37 +0800 Subject: [PATCH 280/316] [RISCV] Fixing stack offset for RVV object with vararg in stack. We found LLVM generate wrong stack offset for RVV object when stack having variable argument, that cause by we didn't count vaarg part during calculate RVV stack objects. Also update the stack layout diagram for including vaarg in the diagram. Stack layout ref: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.cc#L3941 Reviewed By: rogfer01 Differential Revision: https://reviews.llvm.org/D123180 --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 23 +++++++++++++++---- .../rvv/wrong-stack-offset-for-rvv-object.mir | 4 ++-- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index f3cc7d3fb46fa..8f250eeb7248a 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -674,7 +674,10 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, if (hasBP(MF)) { FrameReg = RISCVABI::getBPReg(); // |--------------------------| -- <-- FP - // | callee-saved registers | | <----. + // | callee-allocated save | | <----| + // | area for register varargs| | | + // |--------------------------| | | + // | callee-saved registers | | | // |--------------------------| -- | // | realignment (the size of | | | // | this area is not counted | | | @@ -699,7 +702,10 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, } else { FrameReg = RISCV::X2; // |--------------------------| -- <-- FP - // | callee-saved registers | | <----. + // | callee-allocated save | | <----| + // | area for register varargs| | | + // |--------------------------| | | + // | callee-saved registers | | | // |--------------------------| -- | // | realignment (the size of | | | // | this area is not counted | | | @@ -742,6 +748,9 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, // the frame size. // // |--------------------------| -- <-- FP + // | callee-allocated save | | + // | area for register varargs| | + // |--------------------------| | // | callee-saved registers | | // |--------------------------| | MFI.getStackSize() // | scalar local variables | | @@ -756,7 +765,10 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, // When using SP to access frame objects, we need to add RVV stack size. // // |--------------------------| -- <-- FP - // | callee-saved registers | | <----. + // | callee-allocated save | | <----| + // | area for register varargs| | | + // |--------------------------| | | + // | callee-saved registers | | | // |--------------------------| -- | // | Padding after RVV | | | // | (not counted in | | | @@ -786,8 +798,11 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Offset += StackOffset::getFixed(MFI.getStackSize()); } } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) { + int ScalarLocalVarSize = MFI.getStackSize() - + RVFI->getCalleeSavedStackSize() - + RVFI->getVarArgsSaveSize(); Offset += StackOffset::get( - alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8), + alignTo(ScalarLocalVarSize, 8), RVFI->getRVVStackSize()); } } diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir index 93471f65d5753..2fdd749eb2da7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir @@ -164,7 +164,7 @@ body: | ; CHECK-NEXT: SD killed renamable $x16, killed $x10, 48 :: (store (s64) into %fixed-stack.1, align 16) ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype - ; CHECK-NEXT: $x10 = ADDI $x2, 40 + ; CHECK-NEXT: $x10 = ADDI $x2, 24 ; CHECK-NEXT: PseudoVSPILL_M1 killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.while.cond: @@ -179,7 +179,7 @@ body: | ; CHECK-NEXT: liveins: $x8, $x9 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $x10 = ADDI $x2, 40 + ; CHECK-NEXT: $x10 = ADDI $x2, 24 ; CHECK-NEXT: renamable $v8 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.1, align 8) ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) ; CHECK-NEXT: $x10 = COPY renamable $x9 From 2c4d288eae8b21f0f62d4831113b131fdb15f1da Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 8 Apr 2022 12:09:54 +0800 Subject: [PATCH 281/316] [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ --- llvm/test/CodeGen/MIR/RISCV/lit.local.cfg | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 llvm/test/CodeGen/MIR/RISCV/lit.local.cfg diff --git a/llvm/test/CodeGen/MIR/RISCV/lit.local.cfg b/llvm/test/CodeGen/MIR/RISCV/lit.local.cfg new file mode 100644 index 0000000000000..c63820126f8ca --- /dev/null +++ b/llvm/test/CodeGen/MIR/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'RISCV' in config.root.targets: + config.unsupported = True From fe8a27acd716a42667f5a572f52f2b04636010ff Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 29 Mar 2022 22:52:42 +0100 Subject: [PATCH 282/316] [LV] Handle zero cost loops in selectInterleaveCount. In some case, like in the added test case, we can reach selectInterleaveCount with loops that actually have a cost of 0. Unfortunately a loop cost of 0 is also used to communicate that the cost has not been computed yet. To resolve the crash, bail out if the cost remains zero after computing it. This seems like the best option, as there are multiple code paths that return a cost of 0 to force a computation in selectInterleaveCount. Computing the cost at multiple places up front there would unnecessarily complicate the logic. Fixes #54413. (cherry picked from commit ecb4171dcbf1b433c9963fd605a74898303e850d) --- .../Transforms/Vectorize/LoopVectorize.cpp | 22 ++++---- ...ct-interleave-count-loop-with-cost-zero.ll | 50 +++++++++++++++++++ 2 files changed, 62 insertions(+), 10 deletions(-) create mode 100644 llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleave-count-loop-with-cost-zero.ll diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 21c16f07e2377..e1cc7946073ea 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -6035,6 +6035,18 @@ unsigned LoopVectorizationCostModel::selectInterleaveCount(ElementCount VF, !(InterleaveSmallLoopScalarReduction && HasReductions && VF.isScalar())) return 1; + // If we did not calculate the cost for VF (because the user selected the VF) + // then we calculate the cost of VF here. + if (LoopCost == 0) { + InstructionCost C = expectedCost(VF).first; + assert(C.isValid() && "Expected to have chosen a VF with valid cost"); + LoopCost = *C.getValue(); + + // Loop body is free and there is no need for interleaving. + if (LoopCost == 0) + return 1; + } + RegisterUsage R = calculateRegisterUsage({VF})[0]; // We divide by these constants so assume that we have at least one // instruction that uses at least one register. @@ -6126,16 +6138,6 @@ unsigned LoopVectorizationCostModel::selectInterleaveCount(ElementCount VF, assert(IC > 0 && "Interleave count must be greater than 0."); - // If we did not calculate the cost for VF (because the user selected the VF) - // then we calculate the cost of VF here. - if (LoopCost == 0) { - InstructionCost C = expectedCost(VF).first; - assert(C.isValid() && "Expected to have chosen a VF with valid cost"); - LoopCost = *C.getValue(); - } - - assert(LoopCost && "Non-zero loop cost expected"); - // Interleave if we vectorized this loop and there is a reduction that could // benefit from interleaving. if (VF.isVector() && HasReductions) { diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleave-count-loop-with-cost-zero.ll b/llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleave-count-loop-with-cost-zero.ll new file mode 100644 index 0000000000000..3b7fa43eea8e7 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/X86/pr54413-select-interleave-count-loop-with-cost-zero.ll @@ -0,0 +1,50 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -passes='loop(indvars),loop-vectorize' -S %s | FileCheck %s + +target triple = "x86_64-unknown-linux-gnu" + +; After indvars, the backedge taken count for %loop2 becomes 1, but SCEV +; retains the cached original BTC, as the loop is in dead code. Make sure +; LV does not crash when trying to select an interleave count for a loop with zero cost. +define void @pr54413(i64* %ptr.base) { +; CHECK-LABEL: @pr54413( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP1:%.*]] +; CHECK: loop1: +; CHECK-NEXT: br i1 true, label [[LOOP1_LATCH:%.*]], label [[LOOP2_PREHEADER:%.*]] +; CHECK: loop2.preheader: +; CHECK-NEXT: br label [[LOOP2:%.*]] +; CHECK: loop2: +; CHECK-NEXT: [[PTR:%.*]] = phi i64* [ [[PTR_BASE:%.*]], [[LOOP2_PREHEADER]] ], [ [[PTR_NEXT:%.*]], [[LOOP2]] ] +; CHECK-NEXT: [[PTR_NEXT]] = getelementptr inbounds i64, i64* [[PTR]], i64 1 +; CHECK-NEXT: br i1 true, label [[LOOP2_EXIT:%.*]], label [[LOOP2]] +; CHECK: loop2.exit: +; CHECK-NEXT: [[PTR_NEXT_LCSSA:%.*]] = phi i64* [ [[PTR_NEXT]], [[LOOP2]] ] +; CHECK-NEXT: br label [[LOOP1_LATCH]] +; CHECK: loop1.latch: +; CHECK-NEXT: br label [[LOOP1]] +; +entry: + br label %loop1 + +loop1: + br i1 true, label %loop1.latch, label %loop2.preheader + +loop2.preheader: + br label %loop2 + +loop2: + %iv = phi i64 [ 0, %loop2.preheader ], [ %iv.next, %loop2 ] + %ptr = phi i64* [ %ptr.base, %loop2.preheader ], [ %ptr.next, %loop2 ] + %iv.next = add nuw nsw i64 %iv, 1 + %ptr.next = getelementptr inbounds i64, i64* %ptr, i64 1 + %cmp = icmp eq i64 %iv, 1024 + br i1 %cmp, label %loop2.exit, label %loop2 + +loop2.exit: + %ptr.next.lcssa = phi i64* [ %ptr.next, %loop2 ] + br label %loop1.latch + +loop1.latch: + br label %loop1 +} From 5ea5e3c01b7be01c9a9689233b4ab3e8aa4dc7dc Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 11 Apr 2022 10:48:47 -0400 Subject: [PATCH 283/316] [InstCombine] add tests for low-mask of ashr; NFC (cherry picked from commit 141892d481fcf446c9bf1ae5fb600d797295debc) --- llvm/test/Transforms/InstCombine/and.ll | 80 ++++++++++++++++++++++--- 1 file changed, 72 insertions(+), 8 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll index 53c7f09189ff5..786535fe67e43 100644 --- a/llvm/test/Transforms/InstCombine/and.ll +++ b/llvm/test/Transforms/InstCombine/and.ll @@ -390,17 +390,81 @@ define i8 @test27(i8 %A) { ret i8 %E } -;; This is just a zero-extending shr. -define i32 @test28(i32 %X) { -; CHECK-LABEL: @test28( +;; No demand for extra sign bits. + +define i32 @ashr_lowmask(i32 %x) { +; CHECK-LABEL: @ashr_lowmask( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 24 ; CHECK-NEXT: ret i32 [[TMP1]] ; - ;; Sign extend - %Y = ashr i32 %X, 24 - ;; Mask out sign bits - %Z = and i32 %Y, 255 - ret i32 %Z + %a = ashr i32 %x, 24 + %r = and i32 %a, 255 + ret i32 %r +} + +define i32 @ashr_lowmask_use(i32 %x) { +; CHECK-LABEL: @ashr_lowmask_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 1 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 2147483647 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 1 + call void @use32(i32 %a) + %r = and i32 %a, 2147483647 + ret i32 %r +} + +define <2 x i8> @ashr_lowmask_use_splat(<2 x i8> %x, <2 x i8>* %p) { +; CHECK-LABEL: @ashr_lowmask_use_splat( +; CHECK-NEXT: [[A:%.*]] = ashr <2 x i8> [[X:%.*]], +; CHECK-NEXT: store <2 x i8> [[A]], <2 x i8>* [[P:%.*]], align 2 +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[A]], +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %a = ashr <2 x i8> %x, + store <2 x i8> %a, <2 x i8>* %p + %r = and <2 x i8> %a, + ret <2 x i8> %r +} + +define i32 @ashr_not_lowmask1_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask1_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 254 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 254 + ret i32 %r +} + +define i32 @ashr_not_lowmask2_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask2_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 127 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 127 + ret i32 %r +} + +define i32 @ashr_not_lowmask3_use(i32 %x) { +; CHECK-LABEL: @ashr_not_lowmask3_use( +; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 +; CHECK-NEXT: call void @use32(i32 [[A]]) +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 511 +; CHECK-NEXT: ret i32 [[R]] +; + %a = ashr i32 %x, 24 + call void @use32(i32 %a) + %r = and i32 %a, 511 + ret i32 %r } define i32 @test29(i8 %X) { From 43ee392dd462f218af0fe18207e6dba347927de2 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 11 Apr 2022 11:16:11 -0400 Subject: [PATCH 284/316] [InstCombine] try to fold low-mask of ashr to lshr With one-use, we handle this via demanded-bits. But We need to handle extra uses to improve issue #54750. https://alive2.llvm.org/ce/z/aDYkPv (cherry picked from commit 7783db55afefd3b0d83f4d1b727b6aaa2c2286d6) --- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 6 ++++++ llvm/test/Transforms/InstCombine/and.ll | 14 ++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 6bbb0251f2bc0..2aab79e890786 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1961,6 +1961,12 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) { } } + // If this 'and' clears the sign-bits added by ashr, replace with lshr: + // and (ashr X, ShiftC), C --> lshr X, ShiftC + if (match(Op0, m_AShr(m_Value(X), m_APInt(ShiftC))) && ShiftC->ult(Width) && + C->isMask(Width - ShiftC->getZExtValue())) + return BinaryOperator::CreateLShr(X, ConstantInt::get(Ty, *ShiftC)); + const APInt *AddC; if (match(Op0, m_Add(m_Value(X), m_APInt(AddC)))) { // If we add zeros to every bit below a mask, the add has no effect: diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll index 786535fe67e43..f6585343a9290 100644 --- a/llvm/test/Transforms/InstCombine/and.ll +++ b/llvm/test/Transforms/InstCombine/and.ll @@ -406,7 +406,7 @@ define i32 @ashr_lowmask_use(i32 %x) { ; CHECK-LABEL: @ashr_lowmask_use( ; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 1 ; CHECK-NEXT: call void @use32(i32 [[A]]) -; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], 2147483647 +; CHECK-NEXT: [[R:%.*]] = lshr i32 [[X]], 1 ; CHECK-NEXT: ret i32 [[R]] ; %a = ashr i32 %x, 1 @@ -419,7 +419,7 @@ define <2 x i8> @ashr_lowmask_use_splat(<2 x i8> %x, <2 x i8>* %p) { ; CHECK-LABEL: @ashr_lowmask_use_splat( ; CHECK-NEXT: [[A:%.*]] = ashr <2 x i8> [[X:%.*]], ; CHECK-NEXT: store <2 x i8> [[A]], <2 x i8>* [[P:%.*]], align 2 -; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[A]], +; CHECK-NEXT: [[R:%.*]] = lshr <2 x i8> [[X]], ; CHECK-NEXT: ret <2 x i8> [[R]] ; %a = ashr <2 x i8> %x, @@ -428,6 +428,8 @@ define <2 x i8> @ashr_lowmask_use_splat(<2 x i8> %x, <2 x i8>* %p) { ret <2 x i8> %r } +; negative test - must keep all low bits + define i32 @ashr_not_lowmask1_use(i32 %x) { ; CHECK-LABEL: @ashr_not_lowmask1_use( ; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 @@ -441,6 +443,8 @@ define i32 @ashr_not_lowmask1_use(i32 %x) { ret i32 %r } +; negative test - must keep all low bits + define i32 @ashr_not_lowmask2_use(i32 %x) { ; CHECK-LABEL: @ashr_not_lowmask2_use( ; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 @@ -454,6 +458,8 @@ define i32 @ashr_not_lowmask2_use(i32 %x) { ret i32 %r } +; negative test - must keep only low bits + define i32 @ashr_not_lowmask3_use(i32 %x) { ; CHECK-LABEL: @ashr_not_lowmask3_use( ; CHECK-NEXT: [[A:%.*]] = ashr i32 [[X:%.*]], 24 @@ -1231,14 +1237,14 @@ define i32 @lowmask_sext_in_reg(i32 %x) { ret i32 %and } -; Negative test - mismatched shift amounts +; Mismatched shift amounts, but the mask op can be replaced by a shift. define i32 @lowmask_not_sext_in_reg(i32 %x) { ; CHECK-LABEL: @lowmask_not_sext_in_reg( ; CHECK-NEXT: [[L:%.*]] = shl i32 [[X:%.*]], 19 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[L]], 20 ; CHECK-NEXT: call void @use32(i32 [[R]]) -; CHECK-NEXT: [[AND:%.*]] = and i32 [[R]], 4095 +; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[L]], 20 ; CHECK-NEXT: ret i32 [[AND]] ; %l = shl i32 %x, 19 From 8c3445ac1c8b92cfc34282f6c8f6cdc3495878bf Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Tue, 12 Apr 2022 09:23:11 -0700 Subject: [PATCH 285/316] [AArch64][LOH] Don't ignore regmasks in bundles by iterating over instrs. The LOH pass iterates over instructions to build its custom register state machine, but it uses the top-level bundle iterator. This should be okay, because when the wrapper BUNDLE MI is built, it aggregates the register defs/uses in its instructions into MOs. However, that doesn't apply to regmasks, and accumulating regmasks across multiple instructions would be messy business. There are a couple AnalyzePhysRegInBundle (/Virt) helpers that do look at regmasks, but those don't fit in very well here. AArch64 has started to use a few bundle instructions, specifically as glorified pseudos for variant call instructions, which have regmasks. So the LOH pass ends up ignoring regmasks. Concretely, this has been wrong for a while, but, on aarch64, the most common bundle (rv_marker call) was always followed by the attached call instruction, a plain BL with a regmask. Which was properly detected by the pass. However, we recently started keeping the attached call in the bundle, so the regmask is now ignored. And the pass happily combines ADRPs, of say, x8, across the bundle, resulting in corrupt pointers later. (cherry picked from commit cfa4fe7c51870fe6b480d541938f556cf0736fa2) --- llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 2 +- llvm/test/CodeGen/AArch64/loh.mir | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp index ac243347b24d9..b31b709c0c0a9 100644 --- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp @@ -559,7 +559,7 @@ bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) { // Walk the basic block backwards and update the per register state machine // in the process. for (const MachineInstr &MI : - instructionsWithoutDebug(MBB.rbegin(), MBB.rend())) { + instructionsWithoutDebug(MBB.instr_rbegin(), MBB.instr_rend())) { unsigned Opcode = MI.getOpcode(); switch (Opcode) { case AArch64::ADDXri: diff --git a/llvm/test/CodeGen/AArch64/loh.mir b/llvm/test/CodeGen/AArch64/loh.mir index 8c482fa27b1db..c816a5344bdbf 100644 --- a/llvm/test/CodeGen/AArch64/loh.mir +++ b/llvm/test/CodeGen/AArch64/loh.mir @@ -190,4 +190,13 @@ body: | bb.14: liveins: $x10 $x12 = ADDXri $x10, target-flags(aarch64-pageoff) @g0, 0 + + bb.15: + ; Should not produce a LOH when reg is clobbered by bundled regmask + ; CHECK-NOT: MCLOH_AdrpAdrp + $x8 = ADRP target-flags(aarch64-page) @g0 + BUNDLE { + BL @extfunc, csr_aarch64_aapcs + } + $x8 = ADRP target-flags(aarch64-page) @g1 ... From d800180f6bee3b5fd91d63095c3b06f26ae8076d Mon Sep 17 00:00:00 2001 From: Tobias Hieta Date: Thu, 24 Mar 2022 16:07:39 +0100 Subject: [PATCH 286/316] [lld][COFF] Fix TypeServerSource lookup on GUID collisions Microsoft shipped a bunch of PDB files with broken/invalid GUIDs which lead lld to use 0xFF as the key for these files in an internal cache. When multiple files have this key it will lead to collisions and confused symbol lookup. Several approaches to fix this was considered. Including making the key the path to the PDB file, but this requires some filesystem operations in order to normalize the file path. Since this only happens with malformatted PDB files and we haven't seen this before they malformatted files where shipped with visual studio we probably shouldn't optimize for this use-case. Instead we now just don't insert files with Guid == 0xFF into the cache map and warn if we get collisions so similar problems can be found in the future instead of being silent. Discussion about the root issue and the approach to this fix can be found on Github: https://github.com/llvm/llvm-project/issues/54487 Reviewed By: aganea Differential Revision: https://reviews.llvm.org/D122372 (cherry picked from commit 98bc304e9faded44f1d8988ffa4c5d8b50c759ec) --- lld/COFF/DebugTypes.cpp | 11 +- .../pdb-type-server-guid-collision-a-pdb.yaml | 1018 +++++++++++++++++ .../pdb-type-server-guid-collision-a.yaml | 171 +++ .../pdb-type-server-guid-collision-b-pdb.yaml | 1018 +++++++++++++++++ .../pdb-type-server-guid-collision-b.yaml | 171 +++ ...db-type-server-guid-collision-invalid.test | 20 + .../pdb-type-server-guid-collision-valid.test | 19 + 7 files changed, 2426 insertions(+), 2 deletions(-) create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-a-pdb.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-a.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-b-pdb.yaml create mode 100644 lld/test/COFF/Inputs/pdb-type-server-guid-collision-b.yaml create mode 100644 lld/test/COFF/pdb-type-server-guid-collision-invalid.test create mode 100644 lld/test/COFF/pdb-type-server-guid-collision-valid.test diff --git a/lld/COFF/DebugTypes.cpp b/lld/COFF/DebugTypes.cpp index 67b708c5b36a7..3b3f43f1bf15b 100644 --- a/lld/COFF/DebugTypes.cpp +++ b/lld/COFF/DebugTypes.cpp @@ -56,8 +56,15 @@ class TypeServerSource : public TpiSource { return; Guid = expectedInfo->getGuid(); auto it = ctx.typeServerSourceMappings.emplace(Guid, this); - assert(it.second); - (void)it; + if (!it.second) { + // If we hit here we have collision on Guid's in two PDB files. + // This can happen if the PDB Guid is invalid or if we are really + // unlucky. This should fall back on stright file-system lookup. + TypeServerSource *tSrc = (TypeServerSource *)it.first->second; + log("GUID collision between " + file.getFilePath() + " and " + + tSrc->pdbInputFile->session->getPDBFile().getFilePath()); + ctx.typeServerSourceMappings.erase(Guid); + } } Error mergeDebugT(TypeMerger *m) override; diff --git a/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a-pdb.yaml b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a-pdb.yaml new file mode 100644 index 0000000000000..5092a4102f827 --- /dev/null +++ b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a-pdb.yaml @@ -0,0 +1,1018 @@ +--- +PdbStream: + Age: 1 + Guid: '{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}' + Features: [ VC140 ] + Version: VC70 +TpiStream: + Version: VC80 + Records: + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::moduleAttribute' + UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: dll + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: exe + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: service + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4 + Name: unspecified + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: EXE + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: SERVICE + - Kind: LF_ENUM + Enum: + NumEnumerators: 6 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4097 + Name: '__vc_attributes::moduleAttribute::type_e' + UniqueName: '.?AW4type_e@moduleAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_MODIFIER + Modifier: + ModifiedType: 112 + Modifiers: [ None, Const ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4099 + Attrs: 65548 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4098, 4100, 4100, 4100, 116, 48, 4100, 116, + 4100, 4100, 116, 48, 48, 4100, 4100 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4096 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4096 + ThisType: 4102 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 15 + ArgumentList: 4101 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4098 ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4096 + ThisType: 4102 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4104 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4096 + ThisType: 4102 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4106 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4103 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4105 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4107 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4098 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 3 + MethodList: 4108 + Name: moduleAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4098 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 8 + Name: name + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 16 + Name: version + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 24 + Name: uuid + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 32 + Name: lcid + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 36 + Name: control + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 40 + Name: helpstring + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 48 + Name: helpstringcontext + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 56 + Name: helpstringdll + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 64 + Name: helpfile + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 72 + Name: helpcontext + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 76 + Name: hidden + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 77 + Name: restricted + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 80 + Name: custom + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4100 + FieldOffset: 88 + Name: resource_name + - Kind: LF_STRUCTURE + Class: + MemberCount: 19 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4109 + Name: '__vc_attributes::moduleAttribute' + UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 96 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::event_receiverAttribute' + UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: native + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: com + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: managed + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4112 + Name: '__vc_attributes::event_receiverAttribute::type_e' + UniqueName: '.?AW4type_e@event_receiverAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4113, 48 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4111 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4111 + ThisType: 4115 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 2 + ArgumentList: 4114 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4113 ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4111 + ThisType: 4115 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4117 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4111 + ThisType: 4115 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4106 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4116 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4118 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4119 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4113 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 3 + MethodList: 4120 + Name: event_receiverAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4113 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 4 + Name: layout_dependent + - Kind: LF_STRUCTURE + Class: + MemberCount: 6 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4121 + Name: '__vc_attributes::event_receiverAttribute' + UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 8 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::aggregatableAttribute' + UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: never + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: allowed + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: always + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4124 + Name: '__vc_attributes::aggregatableAttribute::type_e' + UniqueName: '.?AW4type_e@aggregatableAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4125 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4123 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4123 + ThisType: 4127 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4126 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4123 + ThisType: 4127 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4106 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4128 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4129 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4125 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4130 + Name: aggregatableAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4125 + FieldOffset: 0 + Name: type + - Kind: LF_STRUCTURE + Class: + MemberCount: 4 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4131 + Name: '__vc_attributes::aggregatableAttribute' + UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::threadingAttribute' + UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: apartment + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: single + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: free + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4 + Name: neutral + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 5 + Name: both + - Kind: LF_ENUM + Enum: + NumEnumerators: 5 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4134 + Name: '__vc_attributes::threadingAttribute::threading_e' + UniqueName: '.?AW4threading_e@threadingAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4135 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4133 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4133 + ThisType: 4137 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4136 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4133 + ThisType: 4137 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4106 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4138 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4139 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4135 + Name: threading_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4140 + Name: threadingAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4135 + FieldOffset: 0 + Name: value + - Kind: LF_STRUCTURE + Class: + MemberCount: 4 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4141 + Name: '__vc_attributes::threadingAttribute' + UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::helper_attributes::usageAttribute' + UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: eAnyUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: eCoClassUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: eCOMInterfaceUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 6 + Name: eInterfaceUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 8 + Name: eMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16 + Name: eMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 32 + Name: eInterfaceMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 64 + Name: eInterfaceMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 128 + Name: eCoClassMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 256 + Name: eCoClassMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 768 + Name: eGlobalMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1024 + Name: eGlobalDataUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2048 + Name: eClassUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4096 + Name: eInterfaceParameterUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 12288 + Name: eMethodParameterUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16384 + Name: eIDLModuleUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 32768 + Name: eAnonymousUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 65536 + Name: eTypedefUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 131072 + Name: eUnionUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 262144 + Name: eEnumUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 524288 + Name: eDefineTagUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1048576 + Name: eStructUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2097152 + Name: eLocalUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4194304 + Name: ePropertyUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 8388608 + Name: eEventUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16777216 + Name: eTemplateUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16777216 + Name: eModuleUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 33554432 + Name: eIllegalUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 67108864 + Name: eAsynchronousUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4161535 + Name: eAnyIDLUsage + - Kind: LF_ENUM + Enum: + NumEnumerators: 30 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4144 + Name: '__vc_attributes::helper_attributes::usageAttribute::usage_e' + UniqueName: '.?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 117 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4143 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4143 + ThisType: 4147 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4146 + ThisPointerAdjustment: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4145 + Name: usage_e + - Kind: LF_ONEMETHOD + OneMethod: + Type: 4148 + Attrs: 3 + VFTableOffset: -1 + Name: usageAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 117 + FieldOffset: 0 + Name: value + - Kind: LF_STRUCTURE + Class: + MemberCount: 3 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4149 + Name: '__vc_attributes::helper_attributes::usageAttribute' + UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' + UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: eBoolean + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: eInteger + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: eFloat + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: eDouble + - Kind: LF_ENUM + Enum: + NumEnumerators: 4 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4152 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e' + UniqueName: '.?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4153 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4151 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4151 + ThisType: 4155 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4154 + ThisPointerAdjustment: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4153 + Name: type_e + - Kind: LF_ONEMETHOD + OneMethod: + Type: 4156 + Attrs: 3 + VFTableOffset: -1 + Name: v1_alttypeAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4153 + FieldOffset: 0 + Name: type + - Kind: LF_STRUCTURE + Class: + MemberCount: 3 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4157 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' + UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::event_sourceAttribute' + UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4112 + Name: '__vc_attributes::event_sourceAttribute::type_e' + UniqueName: '.?AW4type_e@event_sourceAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: speed + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: size + - Kind: LF_ENUM + Enum: + NumEnumerators: 2 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4161 + Name: '__vc_attributes::event_sourceAttribute::optimize_e' + UniqueName: '.?AW4optimize_e@event_sourceAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4160 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4159 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4159 + ThisType: 4164 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4163 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4159 + ThisType: 4164 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4106 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4165 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4166 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4160 + Name: type_e + - Kind: LF_NESTTYPE + NestedType: + Type: 4162 + Name: optimize_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4167 + Name: event_sourceAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4160 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4162 + FieldOffset: 4 + Name: optimize + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 8 + Name: decorate + - Kind: LF_STRUCTURE + Class: + MemberCount: 7 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4168 + Name: '__vc_attributes::event_sourceAttribute' + UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 12 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: Foo + UniqueName: '.?AUFoo@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 0 + Name: x + - Kind: LF_STRUCTURE + Class: + MemberCount: 1 + Options: [ None, HasUniqueName ] + FieldList: 4171 + Name: Foo + UniqueName: '.?AUFoo@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 +... diff --git a/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a.yaml b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a.yaml new file mode 100644 index 0000000000000..1881d85ce76cd --- /dev/null +++ b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-a.yaml @@ -0,0 +1,171 @@ +--- !COFF +header: + Machine: IMAGE_FILE_MACHINE_AMD64 + Characteristics: [ ] +sections: + - Name: .drectve + Characteristics: [ IMAGE_SCN_LNK_INFO, IMAGE_SCN_LNK_REMOVE ] + Alignment: 1 + SectionData: 2020202F44454641554C544C49423A224C4942434D5422202F44454641554C544C49423A224F4C444E414D45532220 + - Name: '.debug$S' + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + Subsections: + - !Symbols + Records: + - Kind: S_OBJNAME + ObjNameSym: + Signature: 0 + ObjectName: 'C:\Users\tobia\code\tmp\a.obj' + - Kind: S_COMPILE3 + Compile3Sym: + Flags: [ SecurityChecks, HotPatch ] + Machine: X64 + FrontendMajor: 19 + FrontendMinor: 29 + FrontendBuild: 30140 + FrontendQFE: 0 + BackendMajor: 19 + BackendMinor: 29 + BackendBuild: 30140 + BackendQFE: 0 + Version: 'Microsoft (R) Optimizing Compiler' + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: __vc_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: helper_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: atl + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: std + - !Symbols + Records: + - Kind: S_GDATA32 + DataSym: + Type: 4172 + DisplayName: foo_gv + - Kind: S_UDT + UDTSym: + Type: 4172 + UDTName: Foo + - !StringTable + Strings: [] + - !Symbols + Records: + - Kind: S_BUILDINFO + BuildInfoSym: + BuildId: 4122 + Relocations: + - VirtualAddress: 184 + SymbolName: '?foo_gv@@3UFoo@@A' + Type: IMAGE_REL_AMD64_SECREL + - VirtualAddress: 188 + SymbolName: '?foo_gv@@3UFoo@@A' + Type: IMAGE_REL_AMD64_SECTION + - Name: '.debug$T' + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + Types: + - Kind: LF_TYPESERVER2 + TypeServer2: + Guid: '{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}' + Age: 1 + Name: 'C:\Users\tobia\code\tmp\a.pdb' + - Name: .bss + Characteristics: [ IMAGE_SCN_CNT_UNINITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ] + Alignment: 4 + SectionData: '' + SizeOfRawData: 4 + - Name: .chks64 + Characteristics: [ IMAGE_SCN_LNK_INFO, IMAGE_SCN_LNK_REMOVE ] + SectionData: 23076615271ABF1A3D62E233B91184E60A19DCEE7A1989FD00000000000000000000000000000000 +symbols: + - Name: '@comp.id' + Value: 17135036 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: '@feat.00' + Value: 2147549584 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: '@vol.md' + Value: 2 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: .drectve + Value: 0 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 47 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '.debug$S' + Value: 0 + SectionNumber: 2 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 1060 + NumberOfRelocations: 2 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '.debug$T' + Value: 0 + SectionNumber: 3 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 60 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: .bss + Value: 0 + SectionNumber: 4 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 4 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '?foo_gv@@3UFoo@@A' + Value: 0 + SectionNumber: 4 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: .chks64 + Value: 0 + SectionNumber: 5 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 40 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 +... diff --git a/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b-pdb.yaml b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b-pdb.yaml new file mode 100644 index 0000000000000..55e8b616ca36f --- /dev/null +++ b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b-pdb.yaml @@ -0,0 +1,1018 @@ +--- +PdbStream: + Age: 1 + Guid: '{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}' + Features: [ VC140 ] + Version: VC70 +TpiStream: + Version: VC80 + Records: + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: Bar + UniqueName: '.?AUBar@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 0 + Name: x + - Kind: LF_STRUCTURE + Class: + MemberCount: 1 + Options: [ None, HasUniqueName ] + FieldList: 4097 + Name: Bar + UniqueName: '.?AUBar@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::moduleAttribute' + UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: dll + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: exe + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: service + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4 + Name: unspecified + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: EXE + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: SERVICE + - Kind: LF_ENUM + Enum: + NumEnumerators: 6 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4100 + Name: '__vc_attributes::moduleAttribute::type_e' + UniqueName: '.?AW4type_e@moduleAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_MODIFIER + Modifier: + ModifiedType: 112 + Modifiers: [ None, Const ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4102 + Attrs: 65548 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4101, 4103, 4103, 4103, 116, 48, 4103, 116, + 4103, 4103, 116, 48, 48, 4103, 4103 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4099 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4099 + ThisType: 4105 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 15 + ArgumentList: 4104 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4101 ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4099 + ThisType: 4105 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4107 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4099 + ThisType: 4105 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4109 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4106 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4108 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4110 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4101 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 3 + MethodList: 4111 + Name: moduleAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4101 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 8 + Name: name + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 16 + Name: version + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 24 + Name: uuid + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 32 + Name: lcid + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 36 + Name: control + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 40 + Name: helpstring + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 48 + Name: helpstringcontext + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 56 + Name: helpstringdll + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 64 + Name: helpfile + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 116 + FieldOffset: 72 + Name: helpcontext + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 76 + Name: hidden + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 77 + Name: restricted + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 80 + Name: custom + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4103 + FieldOffset: 88 + Name: resource_name + - Kind: LF_STRUCTURE + Class: + MemberCount: 19 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4112 + Name: '__vc_attributes::moduleAttribute' + UniqueName: '.?AUmoduleAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 96 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::event_receiverAttribute' + UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: native + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: com + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: managed + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4115 + Name: '__vc_attributes::event_receiverAttribute::type_e' + UniqueName: '.?AW4type_e@event_receiverAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4116, 48 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4114 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4114 + ThisType: 4118 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 2 + ArgumentList: 4117 + ThisPointerAdjustment: 0 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4116 ] + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4114 + ThisType: 4118 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4120 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4114 + ThisType: 4118 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4109 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4119 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4121 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4122 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4116 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 3 + MethodList: 4123 + Name: event_receiverAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4116 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 4 + Name: layout_dependent + - Kind: LF_STRUCTURE + Class: + MemberCount: 6 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4124 + Name: '__vc_attributes::event_receiverAttribute' + UniqueName: '.?AUevent_receiverAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 8 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::aggregatableAttribute' + UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: never + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: allowed + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: always + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4127 + Name: '__vc_attributes::aggregatableAttribute::type_e' + UniqueName: '.?AW4type_e@aggregatableAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4128 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4126 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4126 + ThisType: 4130 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4129 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4126 + ThisType: 4130 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4109 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4131 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4132 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4128 + Name: type_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4133 + Name: aggregatableAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4128 + FieldOffset: 0 + Name: type + - Kind: LF_STRUCTURE + Class: + MemberCount: 4 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4134 + Name: '__vc_attributes::aggregatableAttribute' + UniqueName: '.?AUaggregatableAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::threadingAttribute' + UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: apartment + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: single + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: free + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4 + Name: neutral + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 5 + Name: both + - Kind: LF_ENUM + Enum: + NumEnumerators: 5 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4137 + Name: '__vc_attributes::threadingAttribute::threading_e' + UniqueName: '.?AW4threading_e@threadingAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4138 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4136 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4136 + ThisType: 4140 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4139 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4136 + ThisType: 4140 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4109 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4141 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4142 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4138 + Name: threading_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4143 + Name: threadingAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4138 + FieldOffset: 0 + Name: value + - Kind: LF_STRUCTURE + Class: + MemberCount: 4 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4144 + Name: '__vc_attributes::threadingAttribute' + UniqueName: '.?AUthreadingAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::helper_attributes::usageAttribute' + UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: eAnyUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: eCoClassUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: eCOMInterfaceUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 6 + Name: eInterfaceUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 8 + Name: eMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16 + Name: eMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 32 + Name: eInterfaceMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 64 + Name: eInterfaceMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 128 + Name: eCoClassMemberUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 256 + Name: eCoClassMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 768 + Name: eGlobalMethodUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1024 + Name: eGlobalDataUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2048 + Name: eClassUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4096 + Name: eInterfaceParameterUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 12288 + Name: eMethodParameterUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16384 + Name: eIDLModuleUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 32768 + Name: eAnonymousUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 65536 + Name: eTypedefUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 131072 + Name: eUnionUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 262144 + Name: eEnumUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 524288 + Name: eDefineTagUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1048576 + Name: eStructUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2097152 + Name: eLocalUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4194304 + Name: ePropertyUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 8388608 + Name: eEventUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16777216 + Name: eTemplateUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 16777216 + Name: eModuleUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 33554432 + Name: eIllegalUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 67108864 + Name: eAsynchronousUsage + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 4161535 + Name: eAnyIDLUsage + - Kind: LF_ENUM + Enum: + NumEnumerators: 30 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4147 + Name: '__vc_attributes::helper_attributes::usageAttribute::usage_e' + UniqueName: '.?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 117 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4146 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4146 + ThisType: 4150 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4149 + ThisPointerAdjustment: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4148 + Name: usage_e + - Kind: LF_ONEMETHOD + OneMethod: + Type: 4151 + Attrs: 3 + VFTableOffset: -1 + Name: usageAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 117 + FieldOffset: 0 + Name: value + - Kind: LF_STRUCTURE + Class: + MemberCount: 3 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4152 + Name: '__vc_attributes::helper_attributes::usageAttribute' + UniqueName: '.?AUusageAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' + UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: eBoolean + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: eInteger + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 2 + Name: eFloat + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 3 + Name: eDouble + - Kind: LF_ENUM + Enum: + NumEnumerators: 4 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4155 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e' + UniqueName: '.?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4156 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4154 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4154 + ThisType: 4158 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4157 + ThisPointerAdjustment: 0 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4156 + Name: type_e + - Kind: LF_ONEMETHOD + OneMethod: + Type: 4159 + Attrs: 3 + VFTableOffset: -1 + Name: v1_alttypeAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4156 + FieldOffset: 0 + Name: type + - Kind: LF_STRUCTURE + Class: + MemberCount: 3 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4160 + Name: '__vc_attributes::helper_attributes::v1_alttypeAttribute' + UniqueName: '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 4 + - Kind: LF_STRUCTURE + Class: + MemberCount: 0 + Options: [ None, ForwardReference, HasUniqueName ] + FieldList: 0 + Name: '__vc_attributes::event_sourceAttribute' + UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 0 + - Kind: LF_ENUM + Enum: + NumEnumerators: 3 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4115 + Name: '__vc_attributes::event_sourceAttribute::type_e' + UniqueName: '.?AW4type_e@event_sourceAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 0 + Name: speed + - Kind: LF_ENUMERATE + Enumerator: + Attrs: 3 + Value: 1 + Name: size + - Kind: LF_ENUM + Enum: + NumEnumerators: 2 + Options: [ None, Nested, HasUniqueName ] + FieldList: 4164 + Name: '__vc_attributes::event_sourceAttribute::optimize_e' + UniqueName: '.?AW4optimize_e@event_sourceAttribute@__vc_attributes@@' + UnderlyingType: 116 + - Kind: LF_ARGLIST + ArgList: + ArgIndices: [ 4163 ] + - Kind: LF_POINTER + Pointer: + ReferentType: 4162 + Attrs: 66572 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4162 + ThisType: 4167 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 1 + ArgumentList: 4166 + ThisPointerAdjustment: 0 + - Kind: LF_MFUNCTION + MemberFunction: + ReturnType: 3 + ClassType: 4162 + ThisType: 4167 + CallConv: NearC + Options: [ None, Constructor ] + ParameterCount: 0 + ArgumentList: 4109 + ThisPointerAdjustment: 0 + - Kind: LF_METHODLIST + MethodOverloadList: + Methods: + - Type: 4168 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Type: 4169 + Attrs: 3 + VFTableOffset: -1 + Name: '' + - Kind: LF_FIELDLIST + FieldList: + - Kind: LF_NESTTYPE + NestedType: + Type: 4163 + Name: type_e + - Kind: LF_NESTTYPE + NestedType: + Type: 4165 + Name: optimize_e + - Kind: LF_METHOD + OverloadedMethod: + NumOverloads: 2 + MethodList: 4170 + Name: event_sourceAttribute + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4163 + FieldOffset: 0 + Name: type + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 4165 + FieldOffset: 4 + Name: optimize + - Kind: LF_MEMBER + DataMember: + Attrs: 3 + Type: 48 + FieldOffset: 8 + Name: decorate + - Kind: LF_STRUCTURE + Class: + MemberCount: 7 + Options: [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ] + FieldList: 4171 + Name: '__vc_attributes::event_sourceAttribute' + UniqueName: '.?AUevent_sourceAttribute@__vc_attributes@@' + DerivationList: 0 + VTableShape: 0 + Size: 12 +... diff --git a/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b.yaml b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b.yaml new file mode 100644 index 0000000000000..54e12527ae228 --- /dev/null +++ b/lld/test/COFF/Inputs/pdb-type-server-guid-collision-b.yaml @@ -0,0 +1,171 @@ +--- !COFF +header: + Machine: IMAGE_FILE_MACHINE_AMD64 + Characteristics: [ ] +sections: + - Name: .drectve + Characteristics: [ IMAGE_SCN_LNK_INFO, IMAGE_SCN_LNK_REMOVE ] + Alignment: 1 + SectionData: 2020202F44454641554C544C49423A224C4942434D5422202F44454641554C544C49423A224F4C444E414D45532220 + - Name: '.debug$S' + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + Subsections: + - !Symbols + Records: + - Kind: S_OBJNAME + ObjNameSym: + Signature: 0 + ObjectName: 'C:\Users\tobia\code\tmp\b.obj' + - Kind: S_COMPILE3 + Compile3Sym: + Flags: [ SecurityChecks, HotPatch ] + Machine: X64 + FrontendMajor: 19 + FrontendMinor: 29 + FrontendBuild: 30140 + FrontendQFE: 0 + BackendMajor: 19 + BackendMinor: 29 + BackendBuild: 30140 + BackendQFE: 0 + Version: 'Microsoft (R) Optimizing Compiler' + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: __vc_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: helper_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: atl + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: std + - !Symbols + Records: + - Kind: S_GDATA32 + DataSym: + Type: 4098 + DisplayName: bar_gv + - Kind: S_UDT + UDTSym: + Type: 4098 + UDTName: Bar + - !StringTable + Strings: [] + - !Symbols + Records: + - Kind: S_BUILDINFO + BuildInfoSym: + BuildId: 4122 + Relocations: + - VirtualAddress: 184 + SymbolName: '?bar_gv@@3UBar@@A' + Type: IMAGE_REL_AMD64_SECREL + - VirtualAddress: 188 + SymbolName: '?bar_gv@@3UBar@@A' + Type: IMAGE_REL_AMD64_SECTION + - Name: '.debug$T' + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + Types: + - Kind: LF_TYPESERVER2 + TypeServer2: + Guid: '{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}' + Age: 1 + Name: 'C:\Users\tobia\code\tmp\b.pdb' + - Name: .bss + Characteristics: [ IMAGE_SCN_CNT_UNINITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ] + Alignment: 4 + SectionData: '' + SizeOfRawData: 4 + - Name: .chks64 + Characteristics: [ IMAGE_SCN_LNK_INFO, IMAGE_SCN_LNK_REMOVE ] + SectionData: 23076615271ABF1A7B0457106301BDC96209C2204ABFB8A500000000000000000000000000000000 +symbols: + - Name: '@comp.id' + Value: 17135036 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: '@feat.00' + Value: 2147549584 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: '@vol.md' + Value: 2 + SectionNumber: -1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + - Name: .drectve + Value: 0 + SectionNumber: 1 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 47 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '.debug$S' + Value: 0 + SectionNumber: 2 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 1060 + NumberOfRelocations: 2 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '.debug$T' + Value: 0 + SectionNumber: 3 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 60 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: .bss + Value: 0 + SectionNumber: 4 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 4 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 + - Name: '?bar_gv@@3UBar@@A' + Value: 0 + SectionNumber: 4 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_EXTERNAL + - Name: .chks64 + Value: 0 + SectionNumber: 5 + SimpleType: IMAGE_SYM_TYPE_NULL + ComplexType: IMAGE_SYM_DTYPE_NULL + StorageClass: IMAGE_SYM_CLASS_STATIC + SectionDefinition: + Length: 40 + NumberOfRelocations: 0 + NumberOfLinenumbers: 0 + CheckSum: 0 + Number: 0 +... diff --git a/lld/test/COFF/pdb-type-server-guid-collision-invalid.test b/lld/test/COFF/pdb-type-server-guid-collision-invalid.test new file mode 100644 index 0000000000000..d73695577de81 --- /dev/null +++ b/lld/test/COFF/pdb-type-server-guid-collision-invalid.test @@ -0,0 +1,20 @@ +Check that the linker behaves when you have multiple +PDB files with the same Guid. This was first a problem +with Visual Studio 2022 that shipped PDB's with Guid's +that was set to FFFFFF... + +RUN: rm -rf %t && mkdir -p %t && cd %t +RUN: yaml2obj %p/Inputs/pdb-type-server-guid-collision-a.yaml -o a.obj +RUN: yaml2obj %p/Inputs/pdb-type-server-guid-collision-b.yaml -o b.obj +RUN: llvm-pdbutil yaml2pdb %S/Inputs/pdb-type-server-guid-collision-a-pdb.yaml -pdb a.pdb +RUN: llvm-pdbutil yaml2pdb %S/Inputs/pdb-type-server-guid-collision-b-pdb.yaml -pdb b.pdb +RUN: lld-link a.obj b.obj -out:collision.dll /debug:ghash -pdb:collision.pdb -nodefaultlib /noentry /dll +RUN: lld-link a.obj b.obj -out:collision.dll /debug:noghash -pdb:collision_noghash.pdb -nodefaultlib /noentry /dll +RUN: llvm-pdbutil dump -globals collision.pdb | FileCheck %s +RUN: llvm-pdbutil dump -globals collision_noghash.pdb | FileCheck %s + +CHECK-LABEL: Global Symbols +CHECK: ============================================================ + +CHECK: 100 | S_GDATA32 [size = 24] `bar_gv` +CHECK-NEXT: type = 0x104E (Bar), addr = 0002:0004 diff --git a/lld/test/COFF/pdb-type-server-guid-collision-valid.test b/lld/test/COFF/pdb-type-server-guid-collision-valid.test new file mode 100644 index 0000000000000..115168c4cf79b --- /dev/null +++ b/lld/test/COFF/pdb-type-server-guid-collision-valid.test @@ -0,0 +1,19 @@ +Check that the linker behaves when you have multiple +PDB files with the same Guid. This checks the case +where the Guids are duplicates but not invalid (i.e. not FFFFFF) + +RUN: rm -rf %t && mkdir -p %t && cd %t +RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-a.yaml | yaml2obj > a.obj +RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-b.yaml | yaml2obj > b.obj +RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-a-pdb.yaml | llvm-pdbutil yaml2pdb - -pdb a.pdb +RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-b-pdb.yaml | llvm-pdbutil yaml2pdb - -pdb b.pdb +RUN: lld-link a.obj b.obj -out:collision.dll -debug -pdb:collision.pdb -nodefaultlib /noentry /dll -verbose 2>&1 | FileCheck %s -check-prefix LOG +RUN: llvm-pdbutil dump -globals collision.pdb | FileCheck %s -check-prefix DUMP + +LOG: lld-link: GUID collision between b.pdb and a.pdb + +DUMP-LABEL: Global Symbols +DUMP: ============================================================ + +DUMP: 100 | S_GDATA32 [size = 24] `bar_gv` +DUMP-NEXT: type = 0x104E (Bar), addr = 0002:0004 From e11b929a3c97d8b22a2765bab1a86b84d322dfd1 Mon Sep 17 00:00:00 2001 From: Tobias Hieta Date: Wed, 6 Apr 2022 17:06:37 +0200 Subject: [PATCH 287/316] [LLD][COFF] Fix TypeServerSource matcher with more than one collision Follow-up from 98bc304e9faded44f1d8988ffa4c5d8b50c759ec - while that commit fixed when you had two PDBs colliding on the same Guid it didn't fix the case where you had more than two PDBs using the same Guid. This commit fixes that and also tests much more carefully that all the types are correct no matter the order. Reviewed By: aganea, saudi Differential Revision: https://reviews.llvm.org/D123185 (cherry picked from commit 0dfa8a019d9a64d7706eb82bdb083fd9b815e088) --- lld/COFF/DebugTypes.cpp | 10 ++++------ .../pdb-type-server-guid-collision-invalid.test | 14 ++++++++++---- .../COFF/pdb-type-server-guid-collision-valid.test | 4 +--- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/lld/COFF/DebugTypes.cpp b/lld/COFF/DebugTypes.cpp index 3b3f43f1bf15b..aa2ce3bd9bbbf 100644 --- a/lld/COFF/DebugTypes.cpp +++ b/lld/COFF/DebugTypes.cpp @@ -60,10 +60,7 @@ class TypeServerSource : public TpiSource { // If we hit here we have collision on Guid's in two PDB files. // This can happen if the PDB Guid is invalid or if we are really // unlucky. This should fall back on stright file-system lookup. - TypeServerSource *tSrc = (TypeServerSource *)it.first->second; - log("GUID collision between " + file.getFilePath() + " and " + - tSrc->pdbInputFile->session->getPDBFile().getFilePath()); - ctx.typeServerSourceMappings.erase(Guid); + it.first->second = nullptr; } } @@ -405,11 +402,12 @@ Expected UseTypeServerSource::getTypeServerSource() { const codeview::GUID &tsId = typeServerDependency.getGuid(); StringRef tsPath = typeServerDependency.getName(); - TypeServerSource *tsSrc; + TypeServerSource *tsSrc = nullptr; auto it = ctx.typeServerSourceMappings.find(tsId); if (it != ctx.typeServerSourceMappings.end()) { tsSrc = (TypeServerSource *)it->second; - } else { + } + if (tsSrc == nullptr) { // The file failed to load, lookup by name PDBInputFile *pdb = PDBInputFile::findFromRecordPath(ctx, tsPath, file); if (!pdb) diff --git a/lld/test/COFF/pdb-type-server-guid-collision-invalid.test b/lld/test/COFF/pdb-type-server-guid-collision-invalid.test index d73695577de81..2418924df4ae5 100644 --- a/lld/test/COFF/pdb-type-server-guid-collision-invalid.test +++ b/lld/test/COFF/pdb-type-server-guid-collision-invalid.test @@ -6,15 +6,21 @@ that was set to FFFFFF... RUN: rm -rf %t && mkdir -p %t && cd %t RUN: yaml2obj %p/Inputs/pdb-type-server-guid-collision-a.yaml -o a.obj RUN: yaml2obj %p/Inputs/pdb-type-server-guid-collision-b.yaml -o b.obj +RUN: sed s/b.pdb/c.pdb/ %S/Inputs/pdb-type-server-guid-collision-b.yaml | sed s/b.obj/c.obj/ | sed s/bar_gv/rab_gv/ | sed s/Bar/Rab/ | yaml2obj > c.obj RUN: llvm-pdbutil yaml2pdb %S/Inputs/pdb-type-server-guid-collision-a-pdb.yaml -pdb a.pdb RUN: llvm-pdbutil yaml2pdb %S/Inputs/pdb-type-server-guid-collision-b-pdb.yaml -pdb b.pdb -RUN: lld-link a.obj b.obj -out:collision.dll /debug:ghash -pdb:collision.pdb -nodefaultlib /noentry /dll -RUN: lld-link a.obj b.obj -out:collision.dll /debug:noghash -pdb:collision_noghash.pdb -nodefaultlib /noentry /dll +RUN: sed s/b.pdb/c.pdb/ %S/Inputs/pdb-type-server-guid-collision-b-pdb.yaml | sed s/bar_gv/rab_gv/ | sed s/Bar/Rab/ | llvm-pdbutil yaml2pdb - -pdb c.pdb +RUN: lld-link b.obj a.obj c.obj -out:collision.dll /debug:ghash -pdb:collision.pdb -nodefaultlib /noentry /dll +RUN: lld-link a.obj b.obj c.obj -out:collision.dll /debug:noghash -pdb:collision_noghash.pdb -nodefaultlib /noentry /dll RUN: llvm-pdbutil dump -globals collision.pdb | FileCheck %s RUN: llvm-pdbutil dump -globals collision_noghash.pdb | FileCheck %s CHECK-LABEL: Global Symbols CHECK: ============================================================ -CHECK: 100 | S_GDATA32 [size = 24] `bar_gv` -CHECK-NEXT: type = 0x104E (Bar), addr = 0002:0004 +CHECK-DAG: {{[0-9]+}} | S_GDATA32 [size = 24] `rab_gv` +CHECK-NEXT: type = {{[^\s]+}} (Rab), addr = 0002:{{[0-9]+}} +CHECK-DAG: {{[0-9]+}} | S_GDATA32 [size = 24] `bar_gv` +CHECK-NEXT: type = {{[^\s]+}} (Bar), addr = 0002:{{[0-9]+}} +CHECK-DAG: {{[0-9]+}} | S_GDATA32 [size = 24] `foo_gv` +CHECK-NEXT: type = {{[^\s]+}} (Foo), addr = 0002:{{[0-9]+}} diff --git a/lld/test/COFF/pdb-type-server-guid-collision-valid.test b/lld/test/COFF/pdb-type-server-guid-collision-valid.test index 115168c4cf79b..a3819eb278860 100644 --- a/lld/test/COFF/pdb-type-server-guid-collision-valid.test +++ b/lld/test/COFF/pdb-type-server-guid-collision-valid.test @@ -7,11 +7,9 @@ RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820 RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-b.yaml | yaml2obj > b.obj RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-a-pdb.yaml | llvm-pdbutil yaml2pdb - -pdb a.pdb RUN: sed s/{FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF}/{6C633EB7-46FE-4609-BA83-EB820E6F5683}/ %S/Inputs/pdb-type-server-guid-collision-b-pdb.yaml | llvm-pdbutil yaml2pdb - -pdb b.pdb -RUN: lld-link a.obj b.obj -out:collision.dll -debug -pdb:collision.pdb -nodefaultlib /noentry /dll -verbose 2>&1 | FileCheck %s -check-prefix LOG +RUN: lld-link a.obj b.obj -out:collision.dll -debug -pdb:collision.pdb -nodefaultlib /noentry /dll RUN: llvm-pdbutil dump -globals collision.pdb | FileCheck %s -check-prefix DUMP -LOG: lld-link: GUID collision between b.pdb and a.pdb - DUMP-LABEL: Global Symbols DUMP: ============================================================ From 46d19f3a8699da61210a45dbb518bcba863de0c3 Mon Sep 17 00:00:00 2001 From: Vladimir Vereschaka Date: Wed, 16 Feb 2022 17:20:39 -0800 Subject: [PATCH 288/316] [CMake] Use CMAKE_SYSROOT to build libs for Win to ARM cross tooolchain. NFC. Provide CMAKE_SYSROOT for the libc++/libc++abi/libunwind libraries instead of specific _SYSROOT for each of them. Fixed passing some CMake arguments for the runtimes. Referenced Differentials: * https://reviews.llvm.org/D119836 * https://reviews.llvm.org/D112155 * https://reviews.llvm.org/D111672 Differential Revision: https://reviews.llvm.org/D120383 (cherry picked from commit 18fa0b15ccf610f34af1231440f89d20cb99e7a0) --- clang/cmake/caches/CrossWinToARMLinux.cmake | 151 +++++++++++--------- 1 file changed, 84 insertions(+), 67 deletions(-) diff --git a/clang/cmake/caches/CrossWinToARMLinux.cmake b/clang/cmake/caches/CrossWinToARMLinux.cmake index dd03a37b4b8f9..5165992b7b923 100644 --- a/clang/cmake/caches/CrossWinToARMLinux.cmake +++ b/clang/cmake/caches/CrossWinToARMLinux.cmake @@ -10,7 +10,7 @@ # # Configure: # cmake -G Ninja ^ -# -DTARGET_TRIPLE=armv7-linux-gnueabihf ^ +# -DTARGET_TRIPLE=armv7-unknown-linux-gnueabihf ^ # -DCMAKE_INSTALL_PREFIX=../install ^ # -DDEFAULT_SYSROOT= ^ # -DLLVM_AR=/bin/llvm-ar[.exe] ^ @@ -25,10 +25,10 @@ # cmake --build . --target check-llvm # cmake --build . --target check-clang # cmake --build . --target check-lld -# cmake --build . --target check-compiler-rt -# cmake --build . --target check-cxxabi -# cmake --build . --target check-unwind -# cmake --build . --target check-cxx +# cmake --build . --target check-compiler-rt- +# cmake --build . --target check-cxxabi- +# cmake --build . --target check-unwind- +# cmake --build . --target check-cxx- # LLVM_PROJECT_DIR is the path to the llvm-project directory. # The right way to compute it would probably be to use "${CMAKE_SOURCE_DIR}/../", @@ -86,49 +86,20 @@ message(STATUS "Toolchain target triple: ${TARGET_TRIPLE}") set(CMAKE_CROSSCOMPILING ON CACHE BOOL "") set(CMAKE_CL_SHOWINCLUDES_PREFIX "Note: including file: " CACHE STRING "") # Required if COMPILER_RT_DEFAULT_TARGET_ONLY is ON -set(CMAKE_C_COMPILER_TARGET "${TARGET_TRIPLE}" CACHE STRING "") +set(CMAKE_C_COMPILER_TARGET "${TARGET_TRIPLE}" CACHE STRING "") +set(CMAKE_CXX_COMPILER_TARGET "${TARGET_TRIPLE}" CACHE STRING "") -set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR ON CACHE BOOL "") +set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR ON CACHE BOOL "") set(LLVM_DEFAULT_TARGET_TRIPLE "${TARGET_TRIPLE}" CACHE STRING "") set(LLVM_TARGET_ARCH "${TARGET_TRIPLE}" CACHE STRING "") set(LLVM_LIT_ARGS "-vv ${LLVM_LIT_ARGS}" CACHE STRING "" FORCE) set(CLANG_DEFAULT_LINKER "lld" CACHE STRING "") -set(COMPILER_RT_BUILD_BUILTINS ON CACHE BOOL "") -set(COMPILER_RT_BUILD_SANITIZERS OFF CACHE BOOL "") -set(COMPILER_RT_BUILD_XRAY OFF CACHE BOOL "") -set(COMPILER_RT_BUILD_LIBFUZZER OFF CACHE BOOL "") -set(COMPILER_RT_BUILD_PROFILE OFF CACHE BOOL "") -set(COMPILER_RT_BUILD_CRT OFF CACHE BOOL "") -set(COMPILER_RT_BUILD_ORC OFF CACHE BOOL "") -set(COMPILER_RT_DEFAULT_TARGET_ONLY ON CACHE BOOL "") -set(COMPILER_RT_INCLUDE_TESTS ON CACHE BOOL "") - -set(LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") -set(LIBUNWIND_TARGET_TRIPLE "${TARGET_TRIPLE}" CACHE STRING "") -set(LIBUNWIND_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(LIBUNWIND_ENABLE_SHARED OFF CACHE BOOL "") - -set(LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(LIBCXXABI_ENABLE_STATIC_UNWINDER ON CACHE BOOL "") -set(LIBCXXABI_USE_COMPILER_RT ON CACHE BOOL "") -set(LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") -set(LIBCXXABI_TARGET_TRIPLE "${TARGET_TRIPLE}" CACHE STRING "") -set(LIBCXXABI_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") -set(LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") -set(LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") -set(LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") - -set(LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") -set(LIBCXX_TARGET_TRIPLE "${TARGET_TRIPLE}" CACHE STRING "") -set(LIBCXX_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(LIBCXX_ENABLE_SHARED OFF CACHE BOOL "") -set(LIBCXX_CXX_ABI "libcxxabi" CACHE STRING "") -set(LIBCXX_CXX_ABI_INCLUDE_PATHS "${LLVM_PROJECT_DIR}/libcxxabi/include" CACHE PATH "") -set(LIBCXX_CXX_ABI_LIBRARY_PATH "${CMAKE_BINARY_DIR}/lib/${LIBCXX_TARGET_TRIPLE}" CACHE PATH "") -set(LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") +if(WIN32) + set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreaded" CACHE STRING "") + set(LLVM_USE_CRT_RELEASE "MT" CACHE STRING "") +endif() # Set up RPATH for the target runtime/builtin libraries. # See some details here: https://reviews.llvm.org/D91099 @@ -136,44 +107,90 @@ if (NOT DEFINED RUNTIMES_INSTALL_RPATH) set(RUNTIMES_INSTALL_RPATH "\$ORIGIN/../lib;${CMAKE_INSTALL_PREFIX}/lib") endif() -set(BUILTINS_CMAKE_ARGS "-DCMAKE_SYSTEM_NAME=Linux;-DCMAKE_AR=${CMAKE_AR};-DCMAKE_INSTALL_RPATH=${RUNTIMES_INSTALL_RPATH};-DCMAKE_BUILD_WITH_INSTALL_RPATH=ON" CACHE STRING "") -set(RUNTIMES_CMAKE_ARGS "-DCMAKE_SYSTEM_NAME=Linux;-DCMAKE_AR=${CMAKE_AR};-DCMAKE_INSTALL_RPATH=${RUNTIMES_INSTALL_RPATH};-DCMAKE_BUILD_WITH_INSTALL_RPATH=ON" CACHE STRING "") +set(LLVM_BUILTIN_TARGETS "${TARGET_TRIPLE}" CACHE STRING "") + +set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") +set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") +set(BUILTINS_${TARGET_TRIPLE}_CMAKE_AR "${CMAKE_AR}" CACHE STRING "") +set(BUILTINS_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") +set(BUILTINS_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") + + +set(LLVM_RUNTIME_TARGETS "${TARGET_TRIPLE}" CACHE STRING "") + +set(RUNTIMES_${TARGET_TRIPLE}_LLVM_ENABLE_RUNTIMES "${LLVM_ENABLE_RUNTIMES}" CACHE STRING "") + +set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") +set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") +set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_AR "${CMAKE_AR}" CACHE STRING "") +set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") +set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_BUILTINS ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_SANITIZERS OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_XRAY OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_LIBFUZZER OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_PROFILE OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_CRT OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_ORC OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_DEFAULT_TARGET_ONLY ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_INCLUDE_TESTS ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_CAN_EXECUTE_TESTS ON CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_USE_BUILTINS_LIBRARY ON CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_ENABLE_SHARED OFF CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_ENABLE_STATIC_UNWINDER ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") + +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ENABLE_SHARED OFF CACHE BOOL "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ABI_VERSION 2 CACHE STRING "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI "libcxxabi" CACHE STRING "") #!!! +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI_INCLUDE_PATHS "${LLVM_PROJECT_DIR}/libcxxabi/include" CACHE PATH "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI_LIBRARY_PATH "${CMAKE_BINARY_DIR}/lib/${TARGET_TRIPLE}" CACHE PATH "") +set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") + find_package(Python3 COMPONENTS Interpreter) # Remote test configuration. if(DEFINED REMOTE_TEST_HOST) - set(DEFAULT_TEST_EXECUTOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/libcxx/utils/ssh.py\\\" --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'") - set(DEFAULT_TEST_TARGET_INFO "libcxx.test.target_info.LinuxRemoteTI") - # Allow override with the custom values. - if(NOT DEFINED COMPILER_RT_EMULATOR) - set(COMPILER_RT_EMULATOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --execdir %%T --exec-pattern='.*\\.c.*\\.tmp.*' --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'" CACHE STRING "") - endif() - if(NOT DEFINED LIBUNWIND_TARGET_INFO) - set(LIBUNWIND_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + if(NOT DEFINED DEFAULT_TEST_EXECUTOR) + set(DEFAULT_TEST_EXECUTOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/libcxx/utils/ssh.py\\\" --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'") endif() - if(NOT DEFINED LIBUNWIND_EXECUTOR) - set(LIBUNWIND_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + if(NOT DEFINED DEFAULT_TEST_TARGET_INFO) + set(DEFAULT_TEST_TARGET_INFO "libcxx.test.target_info.LinuxRemoteTI") endif() + + set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_EMULATOR + "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --execdir %%T --exec-pattern='.*\\.c.*\\.tmp.*' --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'" + CACHE STRING "") + + set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + #NOTE: temporary workaround to fix the remote execution for libunwind tests. # https://reviews.llvm.org/D112082 - set(LIBUNWIND_TEST_CONFIG "${LLVM_PROJECT_DIR}/libunwind/test/lit.site.cfg.in" CACHE PATH "") - if(NOT DEFINED LIBCXXABI_TARGET_INFO) - set(LIBCXXABI_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") - endif() - if(NOT DEFINED LIBCXXABI_EXECUTOR) - set(LIBCXXABI_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") - endif() - if(NOT DEFINED LIBCXX_TARGET_INFO) - set(LIBCXX_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") - endif() - if(NOT DEFINED LIBCXX_EXECUTOR) - set(LIBCXX_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") - endif() + set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_TEST_CONFIG "${LLVM_PROJECT_DIR}/libunwind/test/lit.site.cfg.in" CACHE PATH "") + + set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") endif() -set(LLVM_INSTALL_TOOLCHAIN_ONLY ON CACHE BOOL "") +set(LLVM_INSTALL_TOOLCHAIN_ONLY ON CACHE BOOL "") set(LLVM_TOOLCHAIN_TOOLS llvm-ar llvm-cov From b6dbee34387de2347e48198c8115053802ad71cb Mon Sep 17 00:00:00 2001 From: Vladimir Vereschaka Date: Thu, 3 Mar 2022 14:32:16 -0800 Subject: [PATCH 289/316] [CMake] Update cache file for Win to ARM cross tooolchain. NFC. Removed passing CMAKE_AR from the library configurations. (cherry picked from commit 19c1b084a7da9087fcdc16071b461ea33b6a68b4) --- clang/cmake/caches/CrossWinToARMLinux.cmake | 5 ----- 1 file changed, 5 deletions(-) diff --git a/clang/cmake/caches/CrossWinToARMLinux.cmake b/clang/cmake/caches/CrossWinToARMLinux.cmake index 5165992b7b923..5e62d01b297c2 100644 --- a/clang/cmake/caches/CrossWinToARMLinux.cmake +++ b/clang/cmake/caches/CrossWinToARMLinux.cmake @@ -42,9 +42,6 @@ if (NOT DEFINED DEFAULT_SYSROOT) message(WARNING "DEFAULT_SYSROOT must be specified for the cross toolchain build.") endif() -if (DEFINED LLVM_AR) - set(CMAKE_AR "${LLVM_AR}" CACHE STRING "") -endif() if (NOT DEFINED LLVM_TARGETS_TO_BUILD) set(LLVM_TARGETS_TO_BUILD "ARM" CACHE STRING "") endif() @@ -111,7 +108,6 @@ set(LLVM_BUILTIN_TARGETS "${TARGET_TRIPLE}" CACHE STRING "") set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(BUILTINS_${TARGET_TRIPLE}_CMAKE_AR "${CMAKE_AR}" CACHE STRING "") set(BUILTINS_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") set(BUILTINS_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") @@ -122,7 +118,6 @@ set(RUNTIMES_${TARGET_TRIPLE}_LLVM_ENABLE_RUNTIMES "${LLVM_ set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_AR "${CMAKE_AR}" CACHE STRING "") set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") From 6c41c8edb0ccc0a3502bd417cb6fb652e2205dd6 Mon Sep 17 00:00:00 2001 From: Vladimir Vereschaka Date: Fri, 4 Mar 2022 16:36:57 -0800 Subject: [PATCH 290/316] [CMake] Replace `TARGET_TRIPLE` with `TOOLCHAIN_TARGET_TRIPLE` for Win-to-Arm cross toolchain cache file. NFC. Avoid using TARGET_TRIPLE argument for the cross toolchain cmake cache file and replace it with TOOLCHAIN_TARGET_TRIPLE. Reference: https://reviews.llvm.org/D119918 Differential Revision: https://reviews.llvm.org/D121029 (cherry picked from commit d860ac5da6d71dd759d347a3c7d5e63705443694) --- clang/cmake/caches/CrossWinToARMLinux.cmake | 130 ++++++++++---------- 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/clang/cmake/caches/CrossWinToARMLinux.cmake b/clang/cmake/caches/CrossWinToARMLinux.cmake index 5e62d01b297c2..63461ea2ddbe3 100644 --- a/clang/cmake/caches/CrossWinToARMLinux.cmake +++ b/clang/cmake/caches/CrossWinToARMLinux.cmake @@ -10,7 +10,7 @@ # # Configure: # cmake -G Ninja ^ -# -DTARGET_TRIPLE=armv7-unknown-linux-gnueabihf ^ +# -DTOOLCHAIN_TARGET_TRIPLE=armv7-unknown-linux-gnueabihf ^ # -DCMAKE_INSTALL_PREFIX=../install ^ # -DDEFAULT_SYSROOT= ^ # -DLLVM_AR=/bin/llvm-ar[.exe] ^ @@ -25,10 +25,10 @@ # cmake --build . --target check-llvm # cmake --build . --target check-clang # cmake --build . --target check-lld -# cmake --build . --target check-compiler-rt- -# cmake --build . --target check-cxxabi- -# cmake --build . --target check-unwind- -# cmake --build . --target check-cxx- +# cmake --build . --target check-compiler-rt- +# cmake --build . --target check-cxxabi- +# cmake --build . --target check-unwind- +# cmake --build . --target check-cxx- # LLVM_PROJECT_DIR is the path to the llvm-project directory. # The right way to compute it would probably be to use "${CMAKE_SOURCE_DIR}/../", @@ -55,40 +55,40 @@ if (NOT DEFINED LLVM_ENABLE_RUNTIMES) set(LLVM_ENABLE_RUNTIMES "compiler-rt;libunwind;libcxxabi;libcxx" CACHE STRING "") endif() -if (NOT DEFINED TARGET_TRIPLE) - set(TARGET_TRIPLE "armv7-unknown-linux-gnueabihf") +if (NOT DEFINED TOOLCHAIN_TARGET_TRIPLE) + set(TOOLCHAIN_TARGET_TRIPLE "armv7-unknown-linux-gnueabihf") else() #NOTE: we must normalize specified target triple to a fully specified triple, # including the vendor part. It is necessary to synchronize the runtime library # installation path and operable target triple by Clang to get a correct runtime # path through `-print-runtime-dir` Clang option. - string(REPLACE "-" ";" TARGET_TRIPLE "${TARGET_TRIPLE}") - list(LENGTH TARGET_TRIPLE TARGET_TRIPLE_LEN) - if (TARGET_TRIPLE_LEN LESS 3) + string(REPLACE "-" ";" TOOLCHAIN_TARGET_TRIPLE "${TOOLCHAIN_TARGET_TRIPLE}") + list(LENGTH TOOLCHAIN_TARGET_TRIPLE TOOLCHAIN_TARGET_TRIPLE_LEN) + if (TOOLCHAIN_TARGET_TRIPLE_LEN LESS 3) message(FATAL_ERROR "invalid target triple") endif() # We suppose missed vendor's part. - if (TARGET_TRIPLE_LEN LESS 4) - list(INSERT TARGET_TRIPLE 1 "unknown") + if (TOOLCHAIN_TARGET_TRIPLE_LEN LESS 4) + list(INSERT TOOLCHAIN_TARGET_TRIPLE 1 "unknown") endif() - string(REPLACE ";" "-" TARGET_TRIPLE "${TARGET_TRIPLE}") + string(REPLACE ";" "-" TOOLCHAIN_TARGET_TRIPLE "${TOOLCHAIN_TARGET_TRIPLE}") endif() if (NOT DEFINED CMAKE_BUILD_TYPE) set(CMAKE_BUILD_TYPE "Release" CACHE STRING "") endif() -message(STATUS "Toolchain target triple: ${TARGET_TRIPLE}") +message(STATUS "Toolchain target triple: ${TOOLCHAIN_TARGET_TRIPLE}") set(CMAKE_CROSSCOMPILING ON CACHE BOOL "") set(CMAKE_CL_SHOWINCLUDES_PREFIX "Note: including file: " CACHE STRING "") # Required if COMPILER_RT_DEFAULT_TARGET_ONLY is ON -set(CMAKE_C_COMPILER_TARGET "${TARGET_TRIPLE}" CACHE STRING "") -set(CMAKE_CXX_COMPILER_TARGET "${TARGET_TRIPLE}" CACHE STRING "") +set(CMAKE_C_COMPILER_TARGET "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") +set(CMAKE_CXX_COMPILER_TARGET "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR ON CACHE BOOL "") -set(LLVM_DEFAULT_TARGET_TRIPLE "${TARGET_TRIPLE}" CACHE STRING "") -set(LLVM_TARGET_ARCH "${TARGET_TRIPLE}" CACHE STRING "") +set(LLVM_DEFAULT_TARGET_TRIPLE "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") +set(LLVM_TARGET_ARCH "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") set(LLVM_LIT_ARGS "-vv ${LLVM_LIT_ARGS}" CACHE STRING "" FORCE) set(CLANG_DEFAULT_LINKER "lld" CACHE STRING "") @@ -104,56 +104,56 @@ if (NOT DEFINED RUNTIMES_INSTALL_RPATH) set(RUNTIMES_INSTALL_RPATH "\$ORIGIN/../lib;${CMAKE_INSTALL_PREFIX}/lib") endif() -set(LLVM_BUILTIN_TARGETS "${TARGET_TRIPLE}" CACHE STRING "") +set(LLVM_BUILTIN_TARGETS "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") -set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") -set(BUILTINS_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(BUILTINS_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") -set(BUILTINS_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") +set(BUILTINS_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") +set(BUILTINS_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") +set(BUILTINS_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") +set(BUILTINS_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") -set(LLVM_RUNTIME_TARGETS "${TARGET_TRIPLE}" CACHE STRING "") +set(LLVM_RUNTIME_TARGETS "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_LLVM_ENABLE_RUNTIMES "${LLVM_ENABLE_RUNTIMES}" CACHE STRING "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LLVM_ENABLE_RUNTIMES "${LLVM_ENABLE_RUNTIMES}" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_SYSROOT "${DEFAULT_SYSROOT}" CACHE STRING "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_BUILTINS ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_SANITIZERS OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_XRAY OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_LIBFUZZER OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_PROFILE OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_CRT OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_BUILD_ORC OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_DEFAULT_TARGET_ONLY ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_INCLUDE_TESTS ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_CAN_EXECUTE_TESTS ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_BUILTINS ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_SANITIZERS OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_XRAY OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_LIBFUZZER OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_PROFILE OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_CRT OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_BUILD_ORC OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_DEFAULT_TARGET_ONLY ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_INCLUDE_TESTS ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_CAN_EXECUTE_TESTS ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_USE_BUILTINS_LIBRARY ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_USE_BUILTINS_LIBRARY ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_ENABLE_SHARED OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_ENABLE_SHARED OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_ENABLE_STATIC_UNWINDER ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_USE_COMPILER_RT ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_ENABLE_STATIC_UNWINDER ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ENABLE_SHARED OFF CACHE BOOL "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ABI_VERSION 2 CACHE STRING "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI "libcxxabi" CACHE STRING "") #!!! -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI_INCLUDE_PATHS "${LLVM_PROJECT_DIR}/libcxxabi/include" CACHE PATH "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_CXX_ABI_LIBRARY_PATH "${CMAKE_BINARY_DIR}/lib/${TARGET_TRIPLE}" CACHE PATH "") -set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_ENABLE_SHARED OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_ABI_VERSION 2 CACHE STRING "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_CXX_ABI "libcxxabi" CACHE STRING "") #!!! +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_CXX_ABI_INCLUDE_PATHS "${LLVM_PROJECT_DIR}/libcxxabi/include" CACHE PATH "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_CXX_ABI_LIBRARY_PATH "${CMAKE_BINARY_DIR}/lib/${TOOLCHAIN_TARGET_TRIPLE}" CACHE PATH "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") find_package(Python3 COMPONENTS Interpreter) @@ -168,21 +168,21 @@ if(DEFINED REMOTE_TEST_HOST) set(DEFAULT_TEST_TARGET_INFO "libcxx.test.target_info.LinuxRemoteTI") endif() - set(RUNTIMES_${TARGET_TRIPLE}_COMPILER_RT_EMULATOR + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_EMULATOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --execdir %%T --exec-pattern='.*\\.c.*\\.tmp.*' --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'" CACHE STRING "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") #NOTE: temporary workaround to fix the remote execution for libunwind tests. # https://reviews.llvm.org/D112082 - set(RUNTIMES_${TARGET_TRIPLE}_LIBUNWIND_TEST_CONFIG "${LLVM_PROJECT_DIR}/libunwind/test/lit.site.cfg.in" CACHE PATH "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_TEST_CONFIG "${LLVM_PROJECT_DIR}/libunwind/test/lit.site.cfg.in" CACHE PATH "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBCXXABI_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") - set(RUNTIMES_${TARGET_TRIPLE}_LIBCXX_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") + set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_EXECUTOR "${DEFAULT_TEST_EXECUTOR}" CACHE STRING "") endif() set(LLVM_INSTALL_TOOLCHAIN_ONLY ON CACHE BOOL "") From 3400d0293a14d385a7b8e39e65be72f0c6adecb8 Mon Sep 17 00:00:00 2001 From: Vladimir Vereschaka Date: Fri, 18 Mar 2022 21:16:08 -0700 Subject: [PATCH 291/316] [CMake] Update cache file for Win to ARM Linux cross toolchain builders. NFC. * fixed remote test script arguments for libc++/compiler-rt libraries. * disabled shared libc++abi libraries (to let remote tests get passed). (cherry picked from commit 41f74bc7ae33d9cd9a1eaacfc29ba53a933c042f) --- clang/cmake/caches/CrossWinToARMLinux.cmake | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/clang/cmake/caches/CrossWinToARMLinux.cmake b/clang/cmake/caches/CrossWinToARMLinux.cmake index 63461ea2ddbe3..525432f9c861a 100644 --- a/clang/cmake/caches/CrossWinToARMLinux.cmake +++ b/clang/cmake/caches/CrossWinToARMLinux.cmake @@ -143,6 +143,7 @@ set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_USE_COMPILER_RT set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") +set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXXABI_ENABLE_SHARED OFF CACHE BOOL "") set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXXABI OFF CACHE BOOL "") set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBCXX_LINK_TESTS_WITH_SHARED_LIBCXX OFF CACHE BOOL "") @@ -162,14 +163,14 @@ find_package(Python3 COMPONENTS Interpreter) if(DEFINED REMOTE_TEST_HOST) # Allow override with the custom values. if(NOT DEFINED DEFAULT_TEST_EXECUTOR) - set(DEFAULT_TEST_EXECUTOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/libcxx/utils/ssh.py\\\" --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'") + set(DEFAULT_TEST_EXECUTOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/libcxx/utils/ssh.py\\\" --host=${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}") endif() if(NOT DEFINED DEFAULT_TEST_TARGET_INFO) set(DEFAULT_TEST_TARGET_INFO "libcxx.test.target_info.LinuxRemoteTI") endif() set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_COMPILER_RT_EMULATOR - "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --execdir %%T --exec-pattern='.*\\.c.*\\.tmp.*' --host='${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}'" + "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --execdir %%T --exec-pattern='.*\\.c.*\\.tmp.*' --host=${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}" CACHE STRING "") set(RUNTIMES_${TOOLCHAIN_TARGET_TRIPLE}_LIBUNWIND_TARGET_INFO "${DEFAULT_TEST_TARGET_INFO}" CACHE STRING "") From 33504b3bbe10d5d4caae13efcb99bd159c126070 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Tue, 22 Feb 2022 09:52:19 -0600 Subject: [PATCH 292/316] [PowerPC] Allow absolute expressions in relocations The Linux kernel build uses absolute expressions suffixed with @lo/@ha relocations. This currently doesn't work for DS/DQ form instructions and there is no reason for it not to. It also works with GAS. This patch allows this as long as the value is a multiple of 4/16 for DS/DQ form. Differential revision: https://reviews.llvm.org/D115419 (cherry picked from commit 2aaba44b5c2265f90ac9f0ae188417ef79201c82) --- .../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 63 +++++++------------ .../PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 2 + .../MCTargetDesc/PPCELFObjectWriter.cpp | 2 + .../PowerPC/MCTargetDesc/PPCFixupKinds.h | 4 ++ .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 4 +- .../Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp | 13 +++- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 +- llvm/test/MC/PowerPC/ppc64-abs-reloc.s | 22 +++++++ 8 files changed, 69 insertions(+), 45 deletions(-) create mode 100644 llvm/test/MC/PowerPC/ppc64-abs-reloc.s diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 715cff72dcab4..7113fe33b5d7a 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -341,31 +341,11 @@ struct PPCOperand : public MCParsedAsmOperand { bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } - bool isU16Imm() const { - switch (Kind) { - case Expression: - return true; - case Immediate: - case ContextImmediate: - return isUInt<16>(getImmU16Context()); - default: - return false; - } - } - bool isS16Imm() const { - switch (Kind) { - case Expression: - return true; - case Immediate: - case ContextImmediate: - return isInt<16>(getImmS16Context()); - default: - return false; - } - } - bool isS16ImmX4() const { return Kind == Expression || - (Kind == Immediate && isInt<16>(getImm()) && - (getImm() & 3) == 0); } + bool isU16Imm() const { return isExtImm<16>(/*Signed*/ false, 1); } + bool isS16Imm() const { return isExtImm<16>(/*Signed*/ true, 1); } + bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); } + bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); } + bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); } bool isHashImmX8() const { // The Hash Imm form is used for instructions that check or store a hash. @@ -375,9 +355,6 @@ struct PPCOperand : public MCParsedAsmOperand { (getImm() & 7) == 0); } - bool isS16ImmX16() const { return Kind == Expression || - (Kind == Immediate && isInt<16>(getImm()) && - (getImm() & 15) == 0); } bool isS34ImmX16() const { return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); @@ -388,17 +365,6 @@ struct PPCOperand : public MCParsedAsmOperand { return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); } - bool isS17Imm() const { - switch (Kind) { - case Expression: - return true; - case Immediate: - case ContextImmediate: - return isInt<17>(getImmS16Context()); - default: - return false; - } - } bool isTLSReg() const { return Kind == TLSRegister; } bool isDirectBr() const { if (Kind == Expression) @@ -712,6 +678,25 @@ struct PPCOperand : public MCParsedAsmOperand { return CreateExpr(Val, S, E, IsPPC64); } + +private: + template + bool isExtImm(bool Signed, unsigned Multiple) const { + switch (Kind) { + default: + return false; + case Expression: + return true; + case Immediate: + case ContextImmediate: + if (Signed) + return isInt(getImmS16Context()) && + (getImmS16Context() & (Multiple - 1)) == 0; + else + return isUInt(getImmU16Context()) && + (getImmU16Context() & (Multiple - 1)) == 0; + } + } }; } // end anonymous namespace. diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 9df94edc8cdff..2e678ffd58c2a 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -44,6 +44,7 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { case PPC::fixup_ppc_half16: return Value & 0xffff; case PPC::fixup_ppc_half16ds: + case PPC::fixup_ppc_half16dq: return Value & 0xfffc; case PPC::fixup_ppc_pcrel34: case PPC::fixup_ppc_imm34: @@ -60,6 +61,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case FK_Data_2: case PPC::fixup_ppc_half16: case PPC::fixup_ppc_half16ds: + case PPC::fixup_ppc_half16dq: return 2; case FK_Data_4: case PPC::fixup_ppc_brcond14: diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index 94ef7b45434f3..1e58039582c25 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -125,6 +125,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, } break; case PPC::fixup_ppc_half16ds: + case PPC::fixup_ppc_half16dq: Target.print(errs()); errs() << '\n'; report_fatal_error("Invalid PC-relative half16ds relocation"); @@ -349,6 +350,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, } break; case PPC::fixup_ppc_half16ds: + case PPC::fixup_ppc_half16dq: switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); case MCSymbolRefExpr::VK_None: diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h index 73292f7b7938f..df0c666f5b113 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h @@ -51,6 +51,10 @@ enum Fixups { /// register number. fixup_ppc_nofixup, + /// A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for + /// instrs like 'lxv'. Produces the same relocation as fixup_ppc_half16ds. + fixup_ppc_half16dq, + // Marker LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 4dfa7d5e600c1..d76795fcebc45 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -198,8 +198,8 @@ unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, } // Otherwise add a fixup for the displacement field. - Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), - (MCFixupKind)PPC::fixup_ppc_half16ds)); + Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(), + (MCFixupKind)PPC::fixup_ppc_half16dq)); return RegBits; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp index abff444491313..6cd04ee018fd7 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp @@ -110,9 +110,18 @@ PPCMCExpr::evaluateAsRelocatableImpl(MCValue &Res, if (Value.isAbsolute()) { int64_t Result = evaluateAsInt64(Value.getConstant()); - if ((Fixup == nullptr || (unsigned)Fixup->getKind() != PPC::fixup_ppc_half16) && - (Result >= 0x8000)) + bool IsHalf16 = Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16; + bool IsHalf16DS = + Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16ds; + bool IsHalf16DQ = + Fixup && Fixup->getTargetKind() == PPC::fixup_ppc_half16dq; + bool IsHalf = IsHalf16 || IsHalf16DS || IsHalf16DQ; + + if (!IsHalf && Result >= 0x8000) return false; + if ((IsHalf16DS && (Result & 0x3)) || (IsHalf16DQ && (Result & 0xf))) + return false; + Res = MCValue::get(Result); } else { if (!Layout) diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index c26b4f6ceb7d5..53e73e33b003b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1016,7 +1016,7 @@ def dispRI : Operand { } def PPCDispRIXOperand : AsmOperandClass { let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; - let RenderMethod = "addImmOperands"; + let RenderMethod = "addS16ImmOperands"; } def dispRIX : Operand { let ParserMatchClass = PPCDispRIXOperand; @@ -1030,7 +1030,7 @@ def dispRIHash : Operand { } def PPCDispRIX16Operand : AsmOperandClass { let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; - let RenderMethod = "addImmOperands"; + let RenderMethod = "addS16ImmOperands"; } def dispRIX16 : Operand { let ParserMatchClass = PPCDispRIX16Operand; diff --git a/llvm/test/MC/PowerPC/ppc64-abs-reloc.s b/llvm/test/MC/PowerPC/ppc64-abs-reloc.s new file mode 100644 index 0000000000000..8b0d0b4471783 --- /dev/null +++ b/llvm/test/MC/PowerPC/ppc64-abs-reloc.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu %s -filetype=obj -o - | \ +# RUN: llvm-objdump -D -r - | FileCheck %s + .text +test: # @test + add 5, 3, 4 + extsw 3, 5 + .space 32776 +lab2: + lxv 5, (lab2-test)@l(4) + ld 5, (lab2-test)@l(4) + lwz 5, (lab2-test)@l(4) + lxv 5, 8389632@l(4) + ld 5, 8389632@l(4) + lwz 5, 8389632@l(4) + blr + +# CHECK: lxv 5, -32752(4) +# CHECK: ld 5, -32752(4) +# CHECK: lwz 5, -32752(4) +# CHECK: lxv 5, 1024(4) +# CHECK: ld 5, 1024(4) +# CHECK: lwz 5, 1024(4) From 09fba23d41f775e1cee48f56061710d5861c48d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Carlo=20Marcelo=20Arenas=20Bel=C3=B3n?= Date: Thu, 31 Mar 2022 13:46:45 +0000 Subject: [PATCH 293/316] [compiler-rt] Implement __clear_cache on FreeBSD/powerpc dd9173420f06 (Add clear_cache implementation for ppc64. Fix buffer to meet ppc64 alignment., 2017-07-28), adds an implementation for __builtin___clear_cache on powerpc64, which was promptly ammended to also be used with big endian mode in f67036b62c0c (This ppc64 implementation of clear_cache works for both big and little endian., 2017-08-02) clang will use this implementation for it's builtin on FreeBSD and result in an abort() in the cases where 32-bit generation was requested (ex in macppc or when the big endian powerpc64 build was done with "-m32") and as reported[1] recently with pcre2, but there is no reason why the same code couldn't be used in those cases, so use instead the more generic identifier for the PowerPC architecture. While at it, update the comment to reflect that POWER8/9 have a 128 byte wide cache line and so the code could instead use 64 byte windows instead but that possible optimization has been punted for now. [1] https://github.com/PhilipHazel/pcre2/issues/92 Reviewed By: jhibbits, #powerpc, MaskRay Differential Revision: https://reviews.llvm.org/D122640 (cherry picked from commit 81f5c6270cdfcdf80e6296df216b696a7a37c8b5) --- compiler-rt/lib/builtins/clear_cache.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler-rt/lib/builtins/clear_cache.c b/compiler-rt/lib/builtins/clear_cache.c index da0715914b416..1f1efbff3ab2a 100644 --- a/compiler-rt/lib/builtins/clear_cache.c +++ b/compiler-rt/lib/builtins/clear_cache.c @@ -130,7 +130,10 @@ void __clear_cache(void *start, void *end) { __asm __volatile("dsb ish"); } __asm __volatile("isb sy"); -#elif defined(__powerpc64__) +#elif defined(__powerpc__) + // Newer CPUs have a bigger line size made of multiple blocks, so the + // following value is a minimal common denominator for what used to be + // a single block cache line and is therefore inneficient. const size_t line_size = 32; const size_t len = (uintptr_t)end - (uintptr_t)start; From e8f03f2057ee783439229391a14b2ffe17346100 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Fri, 15 Apr 2022 13:03:39 -0700 Subject: [PATCH 294/316] Force GHashCell to be 8-byte-aligned. Otherwise, with recent versions of libstdc++, clang can't tell that the atomic operations are properly aligned, and generates calls to libatomic. (Actually, because of the use of reinterpret_cast, it wasn't guaranteed to be aligned, but I think it ended up being aligned in practice.) Fixes https://github.com/llvm/llvm-project/issues/54790 , the part where LLVM failed to build. Differential Revision: https://reviews.llvm.org/D123872 (cherry picked from commit 13fc1781735a327699d9522e8e44899acf92a61a) --- lld/COFF/DebugTypes.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lld/COFF/DebugTypes.cpp b/lld/COFF/DebugTypes.cpp index aa2ce3bd9bbbf..0d25de464f9f6 100644 --- a/lld/COFF/DebugTypes.cpp +++ b/lld/COFF/DebugTypes.cpp @@ -902,7 +902,11 @@ struct GHashTable { /// A ghash table cell for deduplicating types from TpiSources. class GHashCell { - uint64_t data = 0; + // Force "data" to be 64-bit aligned; otherwise, some versions of clang + // will generate calls to libatomic when using some versions of libstdc++ + // on 32-bit targets. (Also, in theory, there could be a target where + // new[] doesn't always return an 8-byte-aligned allocation.) + alignas(sizeof(uint64_t)) uint64_t data = 0; public: GHashCell() = default; From 0f56ce0fb2079c8f1fdcb7f7199d7313f81a863d Mon Sep 17 00:00:00 2001 From: Jeremy Morse Date: Wed, 6 Apr 2022 11:50:51 +0100 Subject: [PATCH 295/316] [DebugInfo][InstrRef] Avoid a crash from mixed variable location modes Variable locations now come in two modes, instruction referencing and DBG_VALUE. At -O0 we pick DBG_VALUE to allow fast construction of variable information. Unfortunately, SelectionDAG edits the optimisation level in the presence of opt-bisect-limit, meaning different passes have different views of what variable location mode we should use. That causes assertions when they're mixed. This patch plumbs through a boolean in SelectionDAG from start to instruction emission, so that we don't rely on the current optimisation level for correctness. Differential Revision: https://reviews.llvm.org/D123033 (cherry picked from commit fb6596f1ecab652b5b90cf2e395d64112504c1f8) --- llvm/include/llvm/CodeGen/FastISel.h | 7 ++ llvm/include/llvm/CodeGen/SelectionDAG.h | 13 ++ llvm/include/llvm/CodeGen/SelectionDAGISel.h | 1 + llvm/lib/CodeGen/MachineFunction.cpp | 3 - llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 4 +- .../lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 3 +- .../CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 3 +- .../SelectionDAG/ScheduleDAGSDNodes.cpp | 3 +- .../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 10 +- .../DebugInfo/X86/instr-ref-opt-bisect.ll | 117 ++++++++++++++++++ 11 files changed, 158 insertions(+), 11 deletions(-) create mode 100644 llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h index 775698a66adae..6de8ac4273f73 100644 --- a/llvm/include/llvm/CodeGen/FastISel.h +++ b/llvm/include/llvm/CodeGen/FastISel.h @@ -212,6 +212,7 @@ class FastISel { const TargetRegisterInfo &TRI; const TargetLibraryInfo *LibInfo; bool SkipTargetIndependentISel; + bool UseInstrRefDebugInfo = false; /// The position of the last instruction for materializing constants /// for use in the current block. It resets to EmitStartPt when it makes sense @@ -318,6 +319,12 @@ class FastISel { /// Reset InsertPt to the given old insert position. void leaveLocalValueArea(SavePoint Old); + /// Signal whether instruction referencing variable locations are desired for + /// this function's debug-info. + void useInstrRefDebugInfo(bool Flag) { + UseInstrRefDebugInfo = Flag; + } + protected: explicit FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index e31719bcff0b9..4f348c9feaa5f 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -278,6 +278,9 @@ class SelectionDAG { uint16_t NextPersistentId = 0; + /// Are instruction referencing variable locations desired for this function? + bool UseInstrRefDebugInfo = false; + public: /// Clients of various APIs that cause global effects on /// the DAG can optionally implement this interface. This allows the clients @@ -1702,6 +1705,16 @@ class SelectionDAG { /// function mirrors \c llvm::salvageDebugInfo. void salvageDebugInfo(SDNode &N); + /// Signal whether instruction referencing variable locations are desired for + /// this function's debug-info. + void useInstrRefDebugInfo(bool Flag) { + UseInstrRefDebugInfo = Flag; + } + + bool getUseInstrRefDebugInfo() const { + return UseInstrRefDebugInfo; + } + void dump() const; /// In most cases this function returns the ABI alignment for a given type, diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 9cea197724cc6..fc3fdf3e4583d 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -53,6 +53,7 @@ class SelectionDAGISel : public MachineFunctionPass { const TargetLowering *TLI; bool FastISelFailed; SmallPtrSet ElidedArgCopyInstrs; + bool UseInstrRefDebugInfo = false; /// Current optimization remark emitter. /// Used to report things like combines and FastISel failures. diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index fd5ea5cad072c..02f58ca5eef05 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -1181,9 +1181,6 @@ void MachineFunction::finalizeDebugInstrRefs() { MI.getOperand(1).ChangeToRegister(0, false); }; - if (!useDebugInstrRef()) - return; - for (auto &MBB : *this) { for (auto &MI : MBB) { if (!MI.isDebugRef() || !MI.getOperand(0).isReg()) diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index d8ef79fe9a7bc..87a1ebe4c1db7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1265,7 +1265,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { // If using instruction referencing, mutate this into a DBG_INSTR_REF, // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto // the expression, we don't have an "indirect" flag in DBG_INSTR_REF. - if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) { + if (UseInstrRefDebugInfo && Op->isReg()) { Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF)); Builder->getOperand(1).ChangeToImmediate(0); auto *NewExpr = @@ -1324,7 +1324,7 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { // If using instruction referencing, mutate this into a DBG_INSTR_REF, // to be later patched up by finalizeDebugInstrRefs. - if (FuncInfo.MF->useDebugInstrRef()) { + if (UseInstrRefDebugInfo) { Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF)); Builder->getOperand(1).ChangeToImmediate(0); } diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 331e0325aea30..e3e05c868102c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -1341,11 +1341,12 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos) + MachineBasicBlock::iterator insertpos, + bool UseInstrRefDebugInfo) : MF(mbb->getParent()), MRI(&MF->getRegInfo()), TII(MF->getSubtarget().getInstrInfo()), TRI(MF->getSubtarget().getRegisterInfo()), TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), InsertPos(insertpos) { - EmitDebugInstrRefs = MF->useDebugInstrRef(); + EmitDebugInstrRefs = UseInstrRefDebugInfo; } diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h index ac8a70156522a..ced8f064b9be7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h @@ -154,7 +154,8 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter { /// InstrEmitter - Construct an InstrEmitter and set it to start inserting /// at the given position in the given block. InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, - MachineBasicBlock::iterator insertpos); + MachineBasicBlock::iterator insertpos, + bool UseInstrRefDebugInfo); private: void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 1b89864116cb9..1a6be0cc2091a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -758,7 +758,8 @@ void ScheduleDAGLinearize::Schedule() { MachineBasicBlock* ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, + DAG->getUseInstrRefDebugInfo()); DenseMap VRBaseMap; LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; }); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 55f6f288f3e3a..92897aca7f6b0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -843,7 +843,8 @@ EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap, /// not necessarily refer to returned BB. The emitter may split blocks. MachineBasicBlock *ScheduleDAGSDNodes:: EmitSchedule(MachineBasicBlock::iterator &InsertPos) { - InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos); + InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos, + DAG->getUseInstrRefDebugInfo()); DenseMap VRBaseMap; DenseMap CopyVRBaseMap; SmallVector, 32> Orders; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 3c786904620a1..b83a60129c786 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -425,6 +425,11 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { const Function &Fn = mf.getFunction(); MF = &mf; + // Decide what flavour of variable location debug-info will be used, before + // we change the optimisation level. + UseInstrRefDebugInfo = mf.useDebugInstrRef(); + CurDAG->useInstrRefDebugInfo(UseInstrRefDebugInfo); + // Reset the target options before resetting the optimization // level below. // FIXME: This is a horrible hack and should be processed via @@ -654,7 +659,8 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // For debug-info, in instruction referencing mode, we need to perform some // post-isel maintenence. - MF->finalizeDebugInstrRefs(); + if (UseInstrRefDebugInfo) + MF->finalizeDebugInstrRefs(); // Determine if there are any calls in this machine function. MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -1380,6 +1386,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { if (TM.Options.EnableFastISel) { LLVM_DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); + if (FastIS) + FastIS->useInstrRefDebugInfo(UseInstrRefDebugInfo); } ReversePostOrderTraversal RPOT(&Fn); diff --git a/llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll b/llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll new file mode 100644 index 0000000000000..3afa9e611c121 --- /dev/null +++ b/llvm/test/DebugInfo/X86/instr-ref-opt-bisect.ll @@ -0,0 +1,117 @@ +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=0 \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=10 \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=20 \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=30 \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=40 \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -opt-bisect-limit=100 \ +; RUN: | FileCheck %s +;; Test fast-isel for good measure too, +; RUN: llc %s -o - -stop-after=livedebugvalues -fast-isel=true \ +; RUN: | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -fast-isel=true \ +; RUN: -opt-bisect-limit=0 | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -fast-isel=true \ +; RUN: -opt-bisect-limit=10 | FileCheck %s +; RUN: llc %s -o - -stop-after=livedebugvalues -fast-isel=true \ +; RUN: -opt-bisect-limit=100 | FileCheck %s + +; The function below should be optimised with the "default" optimisation level. +; However, opt-bisect-limit causes SelectionDAG to change the target settings +; for the duration of SelectionDAG. This can lead to variable locations created +; in one mode, but the rest of the debug-info analyses expecting the other. +; Test that opt-bisect-limit can be used without any assertions firing, and +; that instruction referencing instructions are seen each time. +; +; The selection of bisect positions above are not picked meaningfully, the +; pass order and positioning will change over time. The most important part +; is that the bisect limit sits between SelectionDAG and debug-info passes at +; some point. + +; CHECK: DBG_INSTR_REF +; CHECK: DBG_PHI + +; ModuleID = '/tmp/test.cpp' +source_filename = "/tmp/test.cpp" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%class.Class = type { i8 } + +; Function Attrs: mustprogress uwtable +define dso_local void @_Z4FuncP5Class(%class.Class* noundef %c) local_unnamed_addr !dbg !7 { +entry: + call void @llvm.dbg.value(metadata %class.Class* %c, metadata !15, metadata !DIExpression()), !dbg !16 + %tobool.not = icmp eq %class.Class* %c, null, !dbg !17 + br i1 %tobool.not, label %land.lhs.true, label %if.end, !dbg !19 + +land.lhs.true: ; preds = %entry + %call = call noundef zeroext i1 @_Z4Condv(), !dbg !20 + call void @llvm.assume(i1 %call), !dbg !21 + %call1 = call noalias noundef nonnull dereferenceable(1) i8* @_Znwm(i64 noundef 1), !dbg !22, !heapallocsite !12 + %0 = bitcast i8* %call1 to %class.Class*, !dbg !22 + call void @llvm.dbg.value(metadata %class.Class* %0, metadata !15, metadata !DIExpression()), !dbg !16 + br label %if.end, !dbg !23 + +if.end: ; preds = %land.lhs.true, %entry + %c.addr.0 = phi %class.Class* [ %c, %entry ], [ %0, %land.lhs.true ] + call void @llvm.dbg.value(metadata %class.Class* %c.addr.0, metadata !15, metadata !DIExpression()), !dbg !16 + call void @_Z11DoSomethingR5Class(%class.Class* noundef nonnull align 1 dereferenceable(1) %c.addr.0), !dbg !24 + ret void, !dbg !25 +} + +declare !dbg !26 dso_local noundef zeroext i1 @_Z4Condv() local_unnamed_addr + +; Function Attrs: nobuiltin allocsize(0) +declare dso_local noundef nonnull i8* @_Znwm(i64 noundef) local_unnamed_addr + +declare !dbg !30 dso_local void @_Z11DoSomethingR5Class(%class.Class* noundef nonnull align 1 dereferenceable(1)) local_unnamed_addr + +; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.value(metadata, metadata, metadata) + +; Function Attrs: inaccessiblememonly nocallback nofree nosync nounwind willreturn +declare void @llvm.assume(i1 noundef) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "/tmp/test.cpp", directory: ".") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 7, !"uwtable", i32 2} +!6 = !{!"clang"} +!7 = distinct !DISubprogram(name: "Func", linkageName: "_Z4FuncP5Class", scope: !8, file: !8, line: 6, type: !9, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !14) +!8 = !DIFile(filename: "/tmp/test.cpp", directory: "") +!9 = !DISubroutineType(types: !10) +!10 = !{null, !11} +!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) +!12 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "Class", file: !8, line: 3, size: 8, flags: DIFlagTypePassByValue, elements: !13, identifier: "_ZTS5Class") +!13 = !{} +!14 = !{!15} +!15 = !DILocalVariable(name: "c", arg: 1, scope: !7, file: !8, line: 6, type: !11) +!16 = !DILocation(line: 0, scope: !7) +!17 = !DILocation(line: 7, column: 10, scope: !18) +!18 = distinct !DILexicalBlock(scope: !7, file: !8, line: 7, column: 9) +!19 = !DILocation(line: 7, column: 12, scope: !18) +!20 = !DILocation(line: 7, column: 15, scope: !18) +!21 = !DILocation(line: 7, column: 9, scope: !7) +!22 = !DILocation(line: 8, column: 13, scope: !18) +!23 = !DILocation(line: 8, column: 9, scope: !18) +!24 = !DILocation(line: 10, column: 5, scope: !7) +!25 = !DILocation(line: 11, column: 1, scope: !7) +!26 = !DISubprogram(name: "Cond", linkageName: "_Z4Condv", scope: !8, file: !8, line: 5, type: !27, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !13) +!27 = !DISubroutineType(types: !28) +!28 = !{!29} +!29 = !DIBasicType(name: "bool", size: 8, encoding: DW_ATE_boolean) +!30 = !DISubprogram(name: "DoSomething", linkageName: "_Z11DoSomethingR5Class", scope: !8, file: !8, line: 4, type: !31, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !13) +!31 = !DISubroutineType(types: !32) +!32 = !{null, !33} +!33 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !12, size: 64) From 571c7d8f6dae1a8797ae3271c0c09fc648b1940b Mon Sep 17 00:00:00 2001 From: David Spickett Date: Wed, 23 Mar 2022 10:51:08 +0000 Subject: [PATCH 296/316] Reland "[llvm][AArch64] Insert "bti j" after call to setjmp" Cherry-picked from c3b98194df5572bc9b33024b48457538a7213b4c which was originally reviewed as https://reviews.llvm.org/D121707. This reverts commit edb7ba714acba1d18a20d9f4986d2e38aee1d109. This changes BLR_BTI to take variable_ops meaning that we can accept a register or a label. The pattern still expects one argument so we'll never get more than one. Then later we can check the type of the operand to choose BL or BLR to emit. (this is what BLR_RVMARKER does but I missed this detail of it first time around) Also require NoSLSBLRMitigation which I missed in the first version. --- clang/docs/ClangCommandLineReference.rst | 2 +- clang/docs/ReleaseNotes.rst | 6 +- clang/include/clang/Driver/Options.td | 2 +- clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 3 + llvm/lib/Target/AArch64/AArch64.td | 5 ++ .../AArch64/AArch64ExpandPseudoInsts.cpp | 34 ++++++++ llvm/lib/Target/AArch64/AArch64FastISel.cpp | 8 ++ .../Target/AArch64/AArch64ISelLowering.cpp | 10 ++- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 11 +++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 ++ .../AArch64/GISel/AArch64CallLowering.cpp | 12 ++- .../AArch64/setjmp-bti-no-enforcement.ll | 51 ++++++++++++ .../CodeGen/AArch64/setjmp-bti-outliner.ll | 83 +++++++++++++++++++ llvm/test/CodeGen/AArch64/setjmp-bti.ll | 55 ++++++++++++ 15 files changed, 284 insertions(+), 6 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll create mode 100644 llvm/test/CodeGen/AArch64/setjmp-bti.ll diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst index 8ae7d7f49f168..e41d00c2d4c3c 100644 --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -3293,7 +3293,7 @@ Work around VLLDM erratum CVE-2021-35465 (ARM only) .. option:: -mno-bti-at-return-twice -Do not add a BTI instruction after a setjmp or other return-twice construct (Arm only) +Do not add a BTI instruction after a setjmp or other return-twice construct (AArch32/AArch64 only) .. option:: -mno-movt diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5821e41fc7332..0c50e168bf48e 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -381,6 +381,11 @@ Arm and AArch64 Support in Clang - The ``attribute((target("branch-protection=...)))`` attributes will now also work for the ARM backend. +- When using ``-mbranch-protection=bti`` with AArch64, calls to setjmp will + now be followed by a BTI instruction. This is done to be compatible with + setjmp implementations that return with a br instead of a ret. You can + disable this behaviour using the ``-mno-bti-at-return-twice`` option. + SPIR-V Support in Clang ----------------------- @@ -391,7 +396,6 @@ SPIR-V Support in Clang - Added linking of separate object files in SPIR-V format using external ``spirv-link`` tool. - Floating Point Support in Clang ------------------------------- - The default setting of FP contraction (FMA) is now -ffp-contract=on (for diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 602586f94603f..e0d2158407145 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3372,7 +3372,7 @@ def mmark_bti_property : Flag<["-"], "mmark-bti-property">, def mno_bti_at_return_twice : Flag<["-"], "mno-bti-at-return-twice">, Group, HelpText<"Do not add a BTI instruction after a setjmp or other" - " return-twice construct (Arm only)">; + " return-twice construct (Arm/AArch64 only)">; foreach i = {1-31} in def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group, diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index ca0ca4bf4eeac..53610f0909a2a 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -592,4 +592,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, // Enabled A53 errata (835769) workaround by default on android Features.push_back("+fix-cortex-a53-835769"); } + + if (Args.getLastArg(options::OPT_mno_bti_at_return_twice)) + Features.push_back("+no-bti-at-return-twice"); } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 70a79864d2c56..70c7b7b3f5dc7 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -464,6 +464,11 @@ def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true", def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769", "FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">; +def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", + "NoBTIAtReturnTwice", "true", + "Don't place a BTI instruction " + "after a return-twice">; + //===----------------------------------------------------------------------===// // Architectures. // diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index b0f739cc26e69..910f8cdede753 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -86,6 +86,7 @@ class AArch64ExpandPseudo : public MachineFunctionPass { unsigned N); bool expandCALL_RVMARKER(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); + bool expandCALL_BTI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); bool expandStoreSwiftAsyncContext(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI); }; @@ -759,6 +760,37 @@ bool AArch64ExpandPseudo::expandCALL_RVMARKER( return true; } +bool AArch64ExpandPseudo::expandCALL_BTI(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI) { + // Expand CALL_BTI pseudo to: + // - a branch to the call target + // - a BTI instruction + // Mark the sequence as a bundle, to avoid passes moving other code in + // between. + + MachineInstr &MI = *MBBI; + MachineOperand &CallTarget = MI.getOperand(0); + assert((CallTarget.isGlobal() || CallTarget.isReg()) && + "invalid operand for regular call"); + unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR; + MachineInstr *Call = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr(); + Call->addOperand(CallTarget); + + MachineInstr *BTI = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::HINT)) + // BTI J so that setjmp can to BR to this. + .addImm(36) + .getInstr(); + + if (MI.shouldUpdateCallSiteInfo()) + MBB.getParent()->moveCallSiteInfo(&MI, Call); + + MI.eraseFromParent(); + finalizeBundle(MBB, Call->getIterator(), std::next(BTI->getIterator())); + return true; +} + bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { Register CtxReg = MBBI->getOperand(0).getReg(); @@ -1238,6 +1270,8 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB, return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2); case AArch64::BLR_RVMARKER: return expandCALL_RVMARKER(MBB, MBBI); + case AArch64::BLR_BTI: + return expandCALL_BTI(MBB, MBBI); case AArch64::StoreSwiftAsyncContext: return expandStoreSwiftAsyncContext(MBB, MBBI); } diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index c67fa62c7a926..dc5e6807945d7 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -14,6 +14,7 @@ #include "AArch64.h" #include "AArch64CallingConvention.h" +#include "AArch64MachineFunctionInfo.h" #include "AArch64RegisterInfo.h" #include "AArch64Subtarget.h" #include "MCTargetDesc/AArch64AddressingModes.h" @@ -3127,6 +3128,13 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) { if (!Callee && !Symbol) return false; + // Allow SelectionDAG isel to handle calls to functions like setjmp that need + // a bti instruction following the call. + if (CLI.CB && CLI.CB->hasFnAttr(Attribute::ReturnsTwice) && + !Subtarget->noBTIAtReturnTwice() && + MF->getInfo()->branchTargetEnforcement()) + return false; + // Allow SelectionDAG isel to handle tail calls. if (IsTailCall) return false; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 77260c89df115..4d1cb0720a5a8 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2278,6 +2278,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { MAKE_CASE(AArch64ISD::MOPS_MEMSET_TAGGING) MAKE_CASE(AArch64ISD::MOPS_MEMCOPY) MAKE_CASE(AArch64ISD::MOPS_MEMMOVE) + MAKE_CASE(AArch64ISD::CALL_BTI) } #undef MAKE_CASE return nullptr; @@ -6106,6 +6107,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, AArch64FunctionInfo *FuncInfo = MF.getInfo(); bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; bool IsSibCall = false; + bool GuardWithBTI = false; + + if (CLI.CB && CLI.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) && + !Subtarget->noBTIAtReturnTwice()) { + GuardWithBTI = FuncInfo->branchTargetEnforcement(); + } // Check callee args/returns for SVE registers and set calling convention // accordingly. @@ -6540,7 +6547,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, Function *ARCFn = *objcarc::getAttachedARCFunction(CLI.CB); auto GA = DAG.getTargetGlobalAddress(ARCFn, DL, PtrVT); Ops.insert(Ops.begin() + 1, GA); - } + } else if (GuardWithBTI) + CallOpc = AArch64ISD::CALL_BTI; // Returns a chain and a flag for retval copy to use. Chain = DAG.getNode(CallOpc, DL, NodeTys, Ops); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 0ffaf08b8bbed..80b7e84872cde 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -55,6 +55,8 @@ enum NodeType : unsigned { // x29, x29` marker instruction. CALL_RVMARKER, + CALL_BTI, // Function call followed by a BTI instruction. + // Produces the full sequence of instructions for getting the thread pointer // offset of a variable into X0, using the TLSDesc model. TLSDESC_CALLSEQ, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 1316161f05f10..2680b5ac094e3 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -473,6 +473,11 @@ def AArch64call : SDNode<"AArch64ISD::CALL", [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; +def AArch64call_bti : SDNode<"AArch64ISD::CALL_BTI", + SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, + SDNPVariadic]>; + def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER", SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, @@ -2320,6 +2325,8 @@ let isCall = 1, Defs = [LR], Uses = [SP] in { PseudoInstExpansion<(BLR GPR64:$Rn)>; def BLR_RVMARKER : Pseudo<(outs), (ins variable_ops), []>, Sched<[WriteBrReg]>; + def BLR_BTI : Pseudo<(outs), (ins variable_ops), []>, + Sched<[WriteBrReg]>; } // isCall def : Pat<(AArch64call GPR64:$Rn), @@ -2333,6 +2340,10 @@ def : Pat<(AArch64call_rvmarker (i64 tglobaladdr:$rvfunc), GPR64:$Rn), (BLR_RVMARKER tglobaladdr:$rvfunc, GPR64:$Rn)>, Requires<[NoSLSBLRMitigation]>; +def : Pat<(AArch64call_bti GPR64:$Rn), + (BLR_BTI GPR64:$Rn)>, + Requires<[NoSLSBLRMitigation]>; + let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>; } // isBranch, isTerminator, isBarrier, isIndirectBranch diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 7b2bbad30f853..061db926ee2b5 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -243,6 +243,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { // Enable 64-bit vectorization in SLP. unsigned MinVectorRegisterBitWidth = 64; + // Do not place a BTI instruction after a call to a return twice function like + // setjmp. + bool NoBTIAtReturnTwice = false; + bool OutlineAtomics = false; bool PredictableSelectIsExpensive = false; bool BalanceFPOps = false; @@ -588,6 +592,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { bool fixCortexA53_835769() const { return FixCortexA53_835769; } + bool noBTIAtReturnTwice() const { return NoBTIAtReturnTwice; } + bool addrSinkUsingGEPs() const override { // Keeping GEPs inbounds is important for exploiting AArch64 // addressing-modes in ILP32 mode. diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp index 097b93e4fccae..bb6c7938791ee 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -1127,14 +1127,22 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // Create a temporarily-floating call instruction so we can add the implicit // uses of arg registers. - unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false); + const AArch64Subtarget &Subtarget = MF.getSubtarget(); + unsigned Opc = 0; + // A call to a returns twice function like setjmp must be followed by a bti + // instruction. + if (Info.CB && Info.CB->getAttributes().hasFnAttr(Attribute::ReturnsTwice) && + !Subtarget.noBTIAtReturnTwice() && + MF.getInfo()->branchTargetEnforcement()) + Opc = AArch64::BLR_BTI; + else + Opc = getCallOpcode(MF, Info.Callee.isReg(), false); auto MIB = MIRBuilder.buildInstrNoInsert(Opc); MIB.add(Info.Callee); // Tell the call which registers are clobbered. const uint32_t *Mask; - const AArch64Subtarget &Subtarget = MF.getSubtarget(); const auto *TRI = Subtarget.getRegisterInfo(); AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg, diff --git a/llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll b/llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll new file mode 100644 index 0000000000000..cd48245e0a22f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll @@ -0,0 +1,51 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel < %s | FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel < %s | FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI + +; Same as setjmp-bti.ll except that we do not enable branch target enforcement for this +; module. There should be no combination of options that leads to a bti being emitted. + +; C source +; -------- +; extern int setjmp(void*); +; extern void notsetjmp(void); +; +; void bbb(void) { +; setjmp(0); +; int (*fnptr)(void*) = setjmp; +; fnptr(0); +; notsetjmp(); +; } + +define void @bbb() { +; NOBTI-LABEL: bbb: +; NOBTI: bl setjmp +; NOBTI-NOT: hint #36 +; NOBTI: blr x{{[0-9]+}} +; NOBTI-NOT: hint #36 +; NOBTI: bl notsetjmp +; NOBTI-NOT: hint #36 + +entry: + %fnptr = alloca i32 (i8*)*, align 8 + %call = call i32 @setjmp(i8* noundef null) #0 + store i32 (i8*)* @setjmp, i32 (i8*)** %fnptr, align 8 + %0 = load i32 (i8*)*, i32 (i8*)** %fnptr, align 8 + %call1 = call i32 %0(i8* noundef null) #0 + call void @notsetjmp() + ret void +} + +declare i32 @setjmp(i8* noundef) #0 +declare void @notsetjmp() + +attributes #0 = { returns_twice } + +; !llvm.module.flags = !{!0} +; !0 = !{i32 1, !"branch-target-enforcement", i32 1} diff --git a/llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll b/llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll new file mode 100644 index 0000000000000..f9c5416d6daae --- /dev/null +++ b/llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll @@ -0,0 +1,83 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -enable-machine-outliner < %s | FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -enable-machine-outliner < %s | \ +; RUN: FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -enable-machine-outliner < %s | \ +; RUN: FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI + +; Check that the outliner does not split up the call to setjmp and the bti after it. +; When we do not insert a bti, it is allowed to move the setjmp call into an outlined function. + +; C source +; -------- +; extern int setjmp(void*); +; +; int f(int a, int b, int c, int d) { +; setjmp(0); +; return 1 + a * (a + b) / (c + d); +; } +; +; int g(int a, int b, int c, int d) { +; setjmp(0); +; return 2 + a * (a + b) / (c + d); +; } + +define i32 @f(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d) { +; BTI-LABEL: f: +; BTI: bl OUTLINED_FUNCTION_1 +; BTI-NEXT: bl setjmp +; BTI-NEXT: hint #36 +; BTI-NEXT: bl OUTLINED_FUNCTION_0 + +; NOBTI: f: +; NOBTI: bl OUTLINED_FUNCTION_0 +; NOBTI-NEXT: bl OUTLINED_FUNCTION_1 + +entry: + %call = call i32 @setjmp(i8* noundef null) #0 + %add = add nsw i32 %b, %a + %mul = mul nsw i32 %add, %a + %add1 = add nsw i32 %d, %c + %div = sdiv i32 %mul, %add1 + %add2 = add nsw i32 %div, 1 + ret i32 %add2 +} + +declare i32 @setjmp(i8* noundef) #0 + +define i32 @g(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d) { +; BTI-LABEL: g: +; BTI: bl OUTLINED_FUNCTION_1 +; BTI-NEXT: bl setjmp +; BTI-NEXT: hint #36 +; BTI-NEXT: bl OUTLINED_FUNCTION_0 + +; NOBTI: g: +; NOBTI: bl OUTLINED_FUNCTION_0 +; NOBTI-NEXT: bl OUTLINED_FUNCTION_1 + +entry: + %call = call i32 @setjmp(i8* noundef null) #0 + %add = add nsw i32 %b, %a + %mul = mul nsw i32 %add, %a + %add1 = add nsw i32 %d, %c + %div = sdiv i32 %mul, %add1 + %add2 = add nsw i32 %div, 2 + ret i32 %add2 +} + +; NOBTI-LABEL: OUTLINED_FUNCTION_0: +; NOBTI: b setjmp +; NOBTI: OUTLINED_FUNCTION_1: +; NOBTI-LABEL: ret + +attributes #0 = { returns_twice } + +!llvm.module.flags = !{!0} + +!0 = !{i32 1, !"branch-target-enforcement", i32 1} diff --git a/llvm/test/CodeGen/AArch64/setjmp-bti.ll b/llvm/test/CodeGen/AArch64/setjmp-bti.ll new file mode 100644 index 0000000000000..ceea80c839a89 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/setjmp-bti.ll @@ -0,0 +1,55 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel < %s | FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel < %s | FileCheck %s --check-prefix=BTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI +; RUN: llc -mtriple=aarch64-none-linux-gnu -fast-isel -mattr=+no-bti-at-return-twice < %s | \ +; RUN: FileCheck %s --check-prefix=NOBTI + +; C source +; -------- +; extern int setjmp(void*); +; extern void notsetjmp(void); +; +; void bbb(void) { +; setjmp(0); +; int (*fnptr)(void*) = setjmp; +; fnptr(0); +; notsetjmp(); +; } + +define void @bbb() { +; BTI-LABEL: bbb: +; BTI: bl setjmp +; BTI-NEXT: hint #36 +; BTI: blr x{{[0-9]+}} +; BTI-NEXT: hint #36 +; BTI: bl notsetjmp +; BTI-NOT: hint #36 + +; NOBTI-LABEL: bbb: +; NOBTI: bl setjmp +; NOBTI-NOT: hint #36 +; NOBTI: blr x{{[0-9]+}} +; NOBTI-NOT: hint #36 +; NOBTI: bl notsetjmp +; NOBTI-NOT: hint #36 +entry: + %fnptr = alloca i32 (i8*)*, align 8 + %call = call i32 @setjmp(i8* noundef null) #0 + store i32 (i8*)* @setjmp, i32 (i8*)** %fnptr, align 8 + %0 = load i32 (i8*)*, i32 (i8*)** %fnptr, align 8 + %call1 = call i32 %0(i8* noundef null) #0 + call void @notsetjmp() + ret void +} + +declare i32 @setjmp(i8* noundef) #0 +declare void @notsetjmp() + +attributes #0 = { returns_twice } + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"branch-target-enforcement", i32 1} From 0fbe860711be2af4dc8454feb64506595e928e7f Mon Sep 17 00:00:00 2001 From: serge-sans-paille Date: Thu, 7 Apr 2022 15:21:40 +0200 Subject: [PATCH 297/316] [Clang][Fortify] drop inline decls when redeclared When an inline builtin declaration is shadowed by an actual declaration, we must reference the actual declaration, even if it's not the last, following GCC behavior. This fixes #54715 Differential Revision: https://reviews.llvm.org/D123308 (cherry picked from commit 301e0d91354b853addb63a35e72e552e8059413e) --- clang/lib/CodeGen/CGExpr.cpp | 14 ++++++++-- .../fread-inline-builtin-late-redecl.c | 26 +++++++++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) create mode 100644 clang/test/CodeGen/fread-inline-builtin-late-redecl.c diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index bb5d18b748947..2a9b108c31bc9 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -4895,6 +4895,16 @@ RValue CodeGenFunction::EmitSimpleCallExpr(const CallExpr *E, return EmitCall(E->getCallee()->getType(), Callee, E, ReturnValue); } +// Detect the unusual situation where an inline version is shadowed by a +// non-inline version. In that case we should pick the external one +// everywhere. That's GCC behavior too. +static bool OnlyHasInlineBuiltinDeclaration(const FunctionDecl *FD) { + for (const FunctionDecl *PD = FD; PD; PD = PD->getPreviousDecl()) + if (!PD->isInlineBuiltinDeclaration()) + return false; + return true; +} + static CGCallee EmitDirectCallee(CodeGenFunction &CGF, GlobalDecl GD) { const FunctionDecl *FD = cast(GD.getDecl()); @@ -4902,8 +4912,8 @@ static CGCallee EmitDirectCallee(CodeGenFunction &CGF, GlobalDecl GD) { std::string FDInlineName = (FD->getName() + ".inline").str(); // When directing calling an inline builtin, call it through it's mangled // name to make it clear it's not the actual builtin. - if (FD->isInlineBuiltinDeclaration() && - CGF.CurFn->getName() != FDInlineName) { + if (CGF.CurFn->getName() != FDInlineName && + OnlyHasInlineBuiltinDeclaration(FD)) { llvm::Constant *CalleePtr = EmitFunctionDeclPointer(CGF.CGM, GD); llvm::Function *Fn = llvm::cast(CalleePtr); llvm::Module *M = Fn->getParent(); diff --git a/clang/test/CodeGen/fread-inline-builtin-late-redecl.c b/clang/test/CodeGen/fread-inline-builtin-late-redecl.c new file mode 100644 index 0000000000000..bc629fa09f498 --- /dev/null +++ b/clang/test/CodeGen/fread-inline-builtin-late-redecl.c @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -triple x86_64 -S -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s +// +// Verifies that clang-generated *.inline are removed when shadowed by an +// external definition, even when that definition appears at the end of the +// file. + +// CHECK-NOT: strlen.inline + +extern unsigned long strlen(char const *s); + +extern __inline __attribute__((__always_inline__)) __attribute__((__gnu_inline__)) unsigned long strlen(char const *s) { + return 1; +} + +static unsigned long chesterfield(char const *s) { + return strlen(s); +} +static unsigned long (*_strlen)(char const *ptr); + +unsigned long blutch(char const *s) { + return chesterfield(s); +} + +unsigned long strlen(char const *s) { + return _strlen(s); +} From b83c4a2dc0fb620761301f57e92118a3971f66cd Mon Sep 17 00:00:00 2001 From: Pierre Gousseau Date: Tue, 5 Apr 2022 17:30:25 +0100 Subject: [PATCH 298/316] [x86] Fix infinite loop inside DAG combiner with lzcnt feature. The issue affects targets supporting fast-lzcnt such as btver2. This removes extraneous zext/trunc node insertions to fix the infinite loop. This fixes Issue https://github.com/llvm/llvm-project/issues/54694 Differential Revision: https://reviews.llvm.org/D122900 Reviewed By: RKSimon, spatel, lebedev.ri (cherry picked from commit a3d5f1cf5d88dfbbed931951e07f328d5ceba510) Signed-off-by: Warren Ristow In https://reviews.llvm.org/D122900 a new function (to exercise the infinite-loop bug) was added to llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll. In applying the fix in the main branch, two previously existing functions in that test also changed behavior slightly, and in the review it was noted: The instructions generated end up being reordered in some cases but I think it is equivalent. That reordering did not happen in those pre-existing functions when applying the fix to the slightly older code-base of the llvm14 branch, and so they are suppressed here. So the updated version of the test in this commit has the additional function added to it, but it is otherwise identical to the previous llvm14 version of the test. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 21 ++++++--------- llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll | 34 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 600d146cb1245..682932b8f3e66 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -47110,8 +47110,7 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG, // into: // srl(ctlz x), log2(bitsize(x)) // Input pattern is checked by caller. -static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, - SelectionDAG &DAG) { +static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) { SDValue Cmp = Op.getOperand(1); EVT VT = Cmp.getOperand(0).getValueType(); unsigned Log2b = Log2_32(VT.getSizeInBits()); @@ -47122,7 +47121,7 @@ static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, SDValue Trunc = DAG.getZExtOrTrunc(Clz, dl, MVT::i32); SDValue Scc = DAG.getNode(ISD::SRL, dl, MVT::i32, Trunc, DAG.getConstant(Log2b, dl, MVT::i8)); - return DAG.getZExtOrTrunc(Scc, dl, ExtTy); + return Scc; } // Try to transform: @@ -47182,11 +47181,10 @@ static SDValue combineOrCmpEqZeroToCtlzSrl(SDNode *N, SelectionDAG &DAG, // or(srl(ctlz),srl(ctlz)). // The dag combiner can then fold it into: // srl(or(ctlz, ctlz)). - EVT VT = OR->getValueType(0); - SDValue NewLHS = lowerX86CmpEqZeroToCtlzSrl(LHS, VT, DAG); + SDValue NewLHS = lowerX86CmpEqZeroToCtlzSrl(LHS, DAG); SDValue Ret, NewRHS; - if (NewLHS && (NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG))) - Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, NewLHS, NewRHS); + if (NewLHS && (NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, DAG))) + Ret = DAG.getNode(ISD::OR, SDLoc(OR), MVT::i32, NewLHS, NewRHS); if (!Ret) return SDValue(); @@ -47199,16 +47197,13 @@ static SDValue combineOrCmpEqZeroToCtlzSrl(SDNode *N, SelectionDAG &DAG, // Swap rhs with lhs to match or(setcc(eq, cmp, 0), or). if (RHS->getOpcode() == ISD::OR) std::swap(LHS, RHS); - NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG); + NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, DAG); if (!NewRHS) return SDValue(); - Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, Ret, NewRHS); + Ret = DAG.getNode(ISD::OR, SDLoc(OR), MVT::i32, Ret, NewRHS); } - if (Ret) - Ret = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret); - - return Ret; + return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret); } static SDValue foldMaskedMergeImpl(SDValue And0_L, SDValue And0_R, diff --git a/llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll b/llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll index 0c5450a59e422..e291a1923f1dc 100644 --- a/llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll +++ b/llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll @@ -335,3 +335,37 @@ entry: %conv = zext i1 %0 to i32 ret i32 %conv } + +; PR54694 Fix an infinite loop in DAG combiner. +define i32 @test_zext_cmp12(i32 %0, i32 %1) { +; FASTLZCNT-LABEL: test_zext_cmp12: +; FASTLZCNT: # %bb.0: +; FASTLZCNT-NEXT: andl $131072, %edi # imm = 0x20000 +; FASTLZCNT-NEXT: andl $131072, %esi # imm = 0x20000 +; FASTLZCNT-NEXT: lzcntl %edi, %eax +; FASTLZCNT-NEXT: lzcntl %esi, %ecx +; FASTLZCNT-NEXT: orl %eax, %ecx +; FASTLZCNT-NEXT: movl $2, %eax +; FASTLZCNT-NEXT: shrl $5, %ecx +; FASTLZCNT-NEXT: subl %ecx, %eax +; FASTLZCNT-NEXT: retq +; +; NOFASTLZCNT-LABEL: test_zext_cmp12: +; NOFASTLZCNT: # %bb.0: +; NOFASTLZCNT-NEXT: testl $131072, %edi # imm = 0x20000 +; NOFASTLZCNT-NEXT: sete %al +; NOFASTLZCNT-NEXT: testl $131072, %esi # imm = 0x20000 +; NOFASTLZCNT-NEXT: sete %cl +; NOFASTLZCNT-NEXT: orb %al, %cl +; NOFASTLZCNT-NEXT: movl $2, %eax +; NOFASTLZCNT-NEXT: movzbl %cl, %ecx +; NOFASTLZCNT-NEXT: subl %ecx, %eax +; NOFASTLZCNT-NEXT: retq + %3 = and i32 %0, 131072 + %4 = icmp eq i32 %3, 0 + %5 = and i32 %1, 131072 + %6 = icmp eq i32 %5, 0 + %7 = select i1 %4, i1 true, i1 %6 + %8 = select i1 %7, i32 1, i32 2 + ret i32 %8 +} From 9a3e81e1f91fa8793857fdfdacfd7e70ac365bb8 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Thu, 14 Apr 2022 14:02:56 -0400 Subject: [PATCH 299/316] [InstCombine] canonicalize select with signbit test This is part of solving issue #54750 - in that example we have both forms of the compare and do not recognize the equivalence. (cherry picked from commit 2c2568f39ec641aa8f1dcc011f2ce642c2d3423f) --- .../InstCombine/InstCombineSelect.cpp | 17 ++++ llvm/test/Transforms/InstCombine/ashr-lshr.ll | 80 +++++++++---------- .../Transforms/InstCombine/logical-select.ll | 4 +- .../InstCombine/truncating-saturate.ll | 4 +- 4 files changed, 61 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 65e60498ff954..881b00f2a55ae 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1572,6 +1572,23 @@ Instruction *InstCombinerImpl::foldSelectInstWithICmp(SelectInst &SI, } } + // Canonicalize a signbit condition to use zero constant by swapping: + // (CmpLHS > -1) ? TV : FV --> (CmpLHS < 0) ? FV : TV + // To avoid conflicts (infinite loops) with other canonicalizations, this is + // not applied with any constant select arm. + if (Pred == ICmpInst::ICMP_SGT && match(CmpRHS, m_AllOnes()) && + !match(TrueVal, m_Constant()) && !match(FalseVal, m_Constant()) && + ICI->hasOneUse()) { + InstCombiner::BuilderTy::InsertPointGuard Guard(Builder); + Builder.SetInsertPoint(&SI); + Value *IsNeg = Builder.CreateICmpSLT( + CmpLHS, ConstantInt::getNullValue(CmpLHS->getType()), ICI->getName()); + replaceOperand(SI, 0, IsNeg); + SI.swapValues(); + SI.swapProfMetadata(); + return &SI; + } + // FIXME: This code is nearly duplicated in InstSimplify. Using/refactoring // decomposeBitTestICmp() might help. { diff --git a/llvm/test/Transforms/InstCombine/ashr-lshr.ll b/llvm/test/Transforms/InstCombine/ashr-lshr.ll index 72fa0252d8395..110227242ab67 100644 --- a/llvm/test/Transforms/InstCombine/ashr-lshr.ll +++ b/llvm/test/Transforms/InstCombine/ashr-lshr.ll @@ -3,8 +3,8 @@ define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_exact_ashr_only( -; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[CMP12]] ; %cmp = icmp sgt i32 %x, -1 %l = lshr i32 %x, %y @@ -15,8 +15,8 @@ define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) { define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_no_exact( -; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[CMP12]] ; %cmp = icmp sgt i32 %x, -1 %l = lshr i32 %x, %y @@ -27,8 +27,8 @@ define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) { define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_exact_both( -; CHECK-NEXT: [[CMP1:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[CMP12]] ; %cmp = icmp sgt i32 %x, -1 %l = lshr exact i32 %x, %y @@ -39,8 +39,8 @@ define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) { define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_exact_lshr_only( -; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret i32 [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret i32 [[CMP12]] ; %cmp = icmp sgt i32 %x, -1 %l = lshr exact i32 %x, %y @@ -63,8 +63,8 @@ define i32 @ashr_lshr2(i32 %x, i32 %y) { define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_splat_vec( -; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[CMP12]] ; %cmp = icmp sgt <2 x i32> %x, %l = lshr <2 x i32> %x, %y @@ -75,8 +75,8 @@ define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) { define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_splat_vec2( -; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[CMP12]] ; %cmp = icmp sgt <2 x i32> %x, %l = lshr exact <2 x i32> %x, %y @@ -87,8 +87,8 @@ define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) { define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_splat_vec3( -; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[CMP12]] ; %cmp = icmp sgt <2 x i32> %x, %l = lshr exact <2 x i32> %x, %y @@ -99,8 +99,8 @@ define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) { define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_splat_vec4( -; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[CMP12]] ; %cmp = icmp sgt <2 x i32> %x, %l = lshr <2 x i32> %x, %y @@ -171,8 +171,8 @@ define i32 @ashr_lshr_cst(i32 %x, i32 %y) { define i32 @ashr_lshr_cst2(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_cst2( -; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8 -; CHECK-NEXT: ret i32 [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr i32 [[X:%.*]], 8 +; CHECK-NEXT: ret i32 [[CMP12]] ; %cmp = icmp sgt i32 %x, -1 %l = lshr i32 %x, 8 @@ -231,8 +231,8 @@ define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) { define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_vec_undef( -; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: ret <2 x i32> [[CMP1]] +; CHECK-NEXT: [[CMP12:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: ret <2 x i32> [[CMP12]] ; %cmp = icmp sgt <2 x i32> %x, %l = lshr <2 x i32> %x, %y @@ -317,10 +317,10 @@ define i32 @ashr_lshr_shift_wrong_pred(i32 %x, i32 %y, i32 %z) { define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) { ; CHECK-LABEL: @ashr_lshr_shift_wrong_pred2( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[Z:%.*]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %z, 0 @@ -332,10 +332,10 @@ define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) { define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_wrong_operands( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[L]], i32 [[R]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %x, 0 @@ -347,10 +347,10 @@ define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) { define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_no_ashr( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %x, 0 @@ -362,10 +362,10 @@ define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) { define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) { ; CHECK-LABEL: @ashr_lshr_shift_amt_mismatch( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %x, 0 @@ -377,10 +377,10 @@ define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) { define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) { ; CHECK-LABEL: @ashr_lshr_shift_base_mismatch( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %x, 0 @@ -392,10 +392,10 @@ define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) { define i32 @ashr_lshr_no_lshr(i32 %x, i32 %y) { ; CHECK-LABEL: @ashr_lshr_no_lshr( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1 -; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = add i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X]], 0 +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP1]], i32 [[R]], i32 [[L]] ; CHECK-NEXT: ret i32 [[RET]] ; %cmp = icmp sge i32 %x, 0 @@ -422,10 +422,10 @@ define <2 x i32> @ashr_lshr_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) { define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @ashr_lshr_inv_vec_wrong_pred( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]] +; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]] -; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer +; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[L]], <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[RET]] ; %cmp = icmp sge <2 x i32> %x, zeroinitializer diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index c23f851bf8da7..b847d92c8c095 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -758,10 +758,10 @@ define <2 x i16> @bitcast_vec_cond_commute3(<4 x i8> %cond, <2 x i16> %pc, <2 x ; CHECK-LABEL: @bitcast_vec_cond_commute3( ; CHECK-NEXT: [[C:%.*]] = mul <2 x i16> [[PC:%.*]], [[PC]] ; CHECK-NEXT: [[D:%.*]] = mul <2 x i16> [[PD:%.*]], [[PD]] -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[D]] to <4 x i8> ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[C]] to <4 x i8> -; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i8> [[TMP2]], <4 x i8> [[TMP1]] +; CHECK-NEXT: [[DOTNOT2:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[DOTNOT2]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[TMP4]] ; diff --git a/llvm/test/Transforms/InstCombine/truncating-saturate.ll b/llvm/test/Transforms/InstCombine/truncating-saturate.ll index 0446b21a33d31..3194b026af5e0 100644 --- a/llvm/test/Transforms/InstCombine/truncating-saturate.ll +++ b/llvm/test/Transforms/InstCombine/truncating-saturate.ll @@ -123,8 +123,8 @@ define i16 @testtrunclowhigh(i32 %add, i16 %low, i16 %high) { ; CHECK-NEXT: [[A:%.*]] = add i32 [[ADD:%.*]], 128 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[A]], 256 ; CHECK-NEXT: [[T:%.*]] = trunc i32 [[ADD]] to i16 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[ADD]], -1 -; CHECK-NEXT: [[F:%.*]] = select i1 [[C]], i16 [[HIGH:%.*]], i16 [[LOW:%.*]] +; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[ADD]], 0 +; CHECK-NEXT: [[F:%.*]] = select i1 [[C1]], i16 [[LOW:%.*]], i16 [[HIGH:%.*]] ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i16 [[T]], i16 [[F]] ; CHECK-NEXT: ret i16 [[R]] ; From e7a9fd4f57d6c51c2c97a545da6552c698eea347 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 7 Apr 2022 23:21:21 +0200 Subject: [PATCH 300/316] [LV] Add test case for PR54427. Reduced test for #54427. --- .../LoopVectorize/induction-unroll-novec.ll | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll diff --git a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll new file mode 100644 index 0000000000000..a4e595e98fb7b --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll @@ -0,0 +1,46 @@ +; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -S %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + + +; Test for PR54427. +define void @test_nonconst_start_and_step(i32* %dst, i32 %start, i32 %step, i64 %N) { +; CHECK-LABEL: @test_nonconst_start_and_step( +; CHECK: [[NEG_STEP:%.+]] = sub i32 0, %step +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] +; CHECK-NEXT: [[INDUCTION3:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[INDUCTION4:%.*]] = add i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[NEG_STEP]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 %start, [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = mul i32 0, [[NEG_STEP]] +; CHECK-NEXT: [[INDUCTION:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = mul i32 1, [[NEG_STEP]] +; CHECK-NEXT: [[INDUCTION2:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP5]] +; CHECK-NEXT: [[TMP6:%.*]] = sub nsw i32 [[INDUCTION]], %step +; CHECK-NEXT: [[TMP7:%.*]] = sub nsw i32 [[INDUCTION2]], %step +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 [[INDUCTION3]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 [[INDUCTION4]] +; CHECK-NEXT: store i32 [[TMP6]], i32* [[TMP8]], align 2 +; CHECK-NEXT: store i32 [[TMP7]], i32* [[TMP9]], align 2 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]] +; CHECK-NEXT: br i1 [[TMP10]], label %middle.block, label %vector.body +; +entry: + br label %loop + +loop: + %primary.iv = phi i64 [ 0, %entry ], [ %primary.iv.next, %loop ] + %iv.down = phi i32 [ %start, %entry ], [ %iv.down.next, %loop ] + %iv.down.next = sub nsw i32 %iv.down, %step + %gep.dst = getelementptr inbounds i32, i32* %dst, i64 %primary.iv + store i32 %iv.down.next, i32* %gep.dst, align 2 + %primary.iv.next = add nuw nsw i64 %primary.iv, 1 + %exitcond = icmp eq i64 %primary.iv.next, %N + br i1 %exitcond, label %exit, label %loop + +exit: + ret void +} From 0d2efbb8b82c13ea6e4aef727c5360eea6679605 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 7 Apr 2022 23:36:17 +0200 Subject: [PATCH 301/316] [LV] Always use add to add scalar iv and (startidx + step) for ints. In the integer case, step will be negative and InductionOpCode will be Sub for inductions counting down. By using the InductionOpCode for integers, we would incorrectly subtract a negative value, when it should be added instead. This fixes #54427 on the 14.x branch. --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 16 ++++++++-------- .../LoopVectorize/induction-unroll-novec.ll | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index e1cc7946073ea..93eaed6551302 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -2544,19 +2544,19 @@ void InnerLoopVectorizer::widenIntOrFpInduction( Type *ScalarTy = IntegerType::get(ScalarIV->getContext(), Step->getType()->getScalarSizeInBits()); - Instruction::BinaryOps IncOp = ID.getInductionOpcode(); - if (IncOp == Instruction::BinaryOpsEnd) - IncOp = Instruction::Add; for (unsigned Part = 0; Part < UF; ++Part) { Value *StartIdx = ConstantInt::get(ScalarTy, Part); - Instruction::BinaryOps MulOp = Instruction::Mul; + Value *EntryPart; if (Step->getType()->isFloatingPointTy()) { StartIdx = Builder.CreateUIToFP(StartIdx, Step->getType()); - MulOp = Instruction::FMul; + Value *MulOp = Builder.CreateFMul(StartIdx, Step); + EntryPart = Builder.CreateBinOp(ID.getInductionOpcode(), ScalarIV, + MulOp, "induction"); + } else { + EntryPart = Builder.CreateAdd( + ScalarIV, Builder.CreateMul(StartIdx, Step), "induction"); + EntryPart->dump(); } - - Value *Mul = Builder.CreateBinOp(MulOp, StartIdx, Step); - Value *EntryPart = Builder.CreateBinOp(IncOp, ScalarIV, Mul, "induction"); State.set(Def, EntryPart, Part); if (Trunc) { assert(!Step->getType()->isFloatingPointTy() && diff --git a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll index a4e595e98fb7b..5266b3f9eaecd 100644 --- a/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll +++ b/llvm/test/Transforms/LoopVectorize/induction-unroll-novec.ll @@ -15,9 +15,9 @@ define void @test_nonconst_start_and_step(i32* %dst, i32 %start, i32 %step, i64 ; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[NEG_STEP]] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 %start, [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = mul i32 0, [[NEG_STEP]] -; CHECK-NEXT: [[INDUCTION:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP4]] +; CHECK-NEXT: [[INDUCTION:%.*]] = add i32 [[OFFSET_IDX]], [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = mul i32 1, [[NEG_STEP]] -; CHECK-NEXT: [[INDUCTION2:%.*]] = sub i32 [[OFFSET_IDX]], [[TMP5]] +; CHECK-NEXT: [[INDUCTION2:%.*]] = add i32 [[OFFSET_IDX]], [[TMP5]] ; CHECK-NEXT: [[TMP6:%.*]] = sub nsw i32 [[INDUCTION]], %step ; CHECK-NEXT: [[TMP7:%.*]] = sub nsw i32 [[INDUCTION2]], %step ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 [[INDUCTION3]] From ebf29ba9f0a3a1076c613aef59e65d65435daaee Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Mon, 25 Apr 2022 14:48:12 +0100 Subject: [PATCH 302/316] [LV] Remove stray debug dump added in 0d2efbb8b82c. --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 93eaed6551302..46ff0994e04e7 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -2555,7 +2555,6 @@ void InnerLoopVectorizer::widenIntOrFpInduction( } else { EntryPart = Builder.CreateAdd( ScalarIV, Builder.CreateMul(StartIdx, Step), "induction"); - EntryPart->dump(); } State.set(Def, EntryPart, Part); if (Trunc) { From 324127d8da95554086c02d609c5b05d3405f73a0 Mon Sep 17 00:00:00 2001 From: Brad Smith Date: Thu, 21 Apr 2022 20:00:59 -0400 Subject: [PATCH 303/316] [libcxx] Add some missing xlocale wrapper functions for OpenBSD Reviewed By: Mordante Differential Revision: https://reviews.llvm.org/D122861 (cherry picked from commit a0d40a579a6f27a1b1cdb7d68b2145e332c02c4e) --- libcxx/include/__support/openbsd/xlocale.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/libcxx/include/__support/openbsd/xlocale.h b/libcxx/include/__support/openbsd/xlocale.h index 49d66fde1e8ed..f3917f333fb37 100644 --- a/libcxx/include/__support/openbsd/xlocale.h +++ b/libcxx/include/__support/openbsd/xlocale.h @@ -16,4 +16,24 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + + +inline _LIBCPP_HIDE_FROM_ABI long +strtol_l(const char *nptr, char **endptr, int base, locale_t) { + return ::strtol(nptr, endptr, base); +} + +inline _LIBCPP_HIDE_FROM_ABI unsigned long +strtoul_l(const char *nptr, char **endptr, int base, locale_t) { + return ::strtoul(nptr, endptr, base); +} + + +#ifdef __cplusplus +} +#endif + #endif From dc30b0d3320da810f402a3fd1f79720cfa8eb98d Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 29 Mar 2022 08:56:21 -0700 Subject: [PATCH 304/316] [ELF] --emit-relocs: fix missing STT_SECTION when the first input section is synthetic addSectionSymbols suppresses the STT_SECTION symbol if the first input section is non-SHF_MERGE synthetic. This is incorrect when the first input section is synthetic while a non-synthetic input section exists: * `.bss : { *(COMMON) *(.bss) }` (abc388ed3cf0ef7e617ebe243d3b0b32d29e69a5 regressed the case because COMMON symbols precede .bss in the absence of a linker script) * Place a synthetic section in another section: `.data : { *(.got) *(.data) }` For `%t/a1` in the new test emit-relocs-synthetic.s, ld.lld produces incorrect relocations with symbol index 0. ``` 0000000000000000 <_start>: 0: 8b 05 33 00 00 00 movl 51(%rip), %eax # 0x39 0000000000000002: R_X86_64_PC32 *ABS*+0xd 6: 8b 05 1c 00 00 00 movl 28(%rip), %eax # 0x28 0000000000000008: R_X86_64_PC32 common-0x4 c: 8b 05 06 00 00 00 movl 6(%rip), %eax # 0x18 000000000000000e: R_X86_64_GOTPCRELX *ABS*+0x4 ``` Fix the issue by checking every input section. Reviewed By: ikudrin Differential Revision: https://reviews.llvm.org/D122463 (cherry picked from commit 7370a489b1005e424b23bd0009af2365aef4db53) --- lld/ELF/Writer.cpp | 41 ++++++++++++--------- lld/test/ELF/emit-relocs-synthetic.s | 54 ++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 17 deletions(-) create mode 100644 lld/test/ELF/emit-relocs-synthetic.s diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 9383ac46c8e72..5794f048c9909 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -722,23 +722,30 @@ template void Writer::addSectionSymbols() { auto *sec = dyn_cast(cmd); if (!sec) continue; - auto i = llvm::find_if(sec->commands, [](SectionCommand *cmd) { - if (auto *isd = dyn_cast(cmd)) - return !isd->sections.empty(); - return false; - }); - if (i == sec->commands.end()) - continue; - InputSectionBase *isec = cast(*i)->sections[0]; - - // Relocations are not using REL[A] section symbols. - if (isec->type == SHT_REL || isec->type == SHT_RELA) - continue; - - // Unlike other synthetic sections, mergeable output sections contain data - // copied from input sections, and there may be a relocation pointing to its - // contents if -r or --emit-reloc is given. - if (isa(isec) && !(isec->flags & SHF_MERGE)) + OutputSection &osec = *sec; + InputSectionBase *isec = nullptr; + // Iterate over all input sections and add a STT_SECTION symbol if any input + // section may be a relocation target. + for (SectionCommand *cmd : osec.commands) { + auto *isd = dyn_cast(cmd); + if (!isd) + continue; + for (InputSectionBase *s : isd->sections) { + // Relocations are not using REL[A] section symbols. + if (s->type == SHT_REL || s->type == SHT_RELA) + continue; + + // Unlike other synthetic sections, mergeable output sections contain + // data copied from input sections, and there may be a relocation + // pointing to its contents if -r or --emit-reloc is given. + if (isa(s) && !(s->flags & SHF_MERGE)) + continue; + + isec = s; + break; + } + } + if (!isec) continue; // Set the symbol to be relative to the output section so that its st_value diff --git a/lld/test/ELF/emit-relocs-synthetic.s b/lld/test/ELF/emit-relocs-synthetic.s new file mode 100644 index 0000000000000..737f96e5e191c --- /dev/null +++ b/lld/test/ELF/emit-relocs-synthetic.s @@ -0,0 +1,54 @@ +# REQUIRES: x86 +## Regression test: add STT_SECTION even if synthetic sections are interleaved +## with regular input sections. + +# RUN: rm -rf %t && split-file %s %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/a.s -o %t/a.o +# RUN: ld.lld --emit-relocs --no-relax -T %t/1.t %t/a.o -o %t/a1 +# RUN: llvm-objdump -dr %t/a1 | FileCheck %s --check-prefixes=CHECK,CHECK1 +# RUN: ld.lld --emit-relocs --no-relax -T %t/2.t %t/a.o -o %t/a2 +# RUN: llvm-objdump -dr %t/a2 | FileCheck %s --check-prefixes=CHECK,CHECK2 + +# CHECK: <_start>: +## %t/a1: bss is at offset 17. bss-4 = .bss + 0xd +## %t/a2: bss is at offset 16. bss-4 = .bss + 0xc +# CHECK-NEXT: movl [[#]](%rip), %eax +# CHECK1-NEXT: R_X86_64_PC32 .bss+0xd +# CHECK2-NEXT: R_X86_64_PC32 .bss+0xc +# CHECK-NEXT: movl [[#]](%rip), %eax +# CHECK-NEXT: R_X86_64_PC32 common-0x4 +# CHECK-NEXT: movl [[#]](%rip), %eax +## %t/a1: input .data is at offset 8. 8-4 = 0x4 +## %t/a2: input .data is at offset 0. 0-4 = -0x4 +# CHECK1-NEXT: R_X86_64_GOTPCRELX .data+0x4 +# CHECK2-NEXT: R_X86_64_GOTPCRELX .data-0x4 + +#--- a.s +.globl _start +_start: + movl bss(%rip), %eax + movl common(%rip), %eax +## Compilers don't produce this. We just check the behavior. + movl .data@gotpcrel(%rip), %eax + +.section .data,"aw",@progbits +.quad 0 + +.section .bss,"aw",@nobits +.space 16 +bss: +.byte 0 + +.comm common,1,1 + +#--- 1.t +SECTIONS { + .data : { *(.got) *(.data) } + .bss : { *(COMMON) *(.bss) } +} + +#--- 2.t +SECTIONS { + .data : { *(.data) *(.got) } + .bss : { *(.bss) *(COMMON) } +} From 50c6ba751fa2c3ae8854ba09229bda62b3617c55 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 9 Apr 2022 08:32:42 -0700 Subject: [PATCH 305/316] [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if LUI+ADDI+SH*ADD failed. There's an assert in LUI+SH*ADD+ADDI materialization that makes sure the lower 12 bits aren't zero since that case should have been handled as LUI+ADDI+SH*ADD. But nothing prevented the LUI+SH*ADD+ADDI checks from running after the earlier code handled it. The sequence would be the same length or longer so it wouldn't replace the earlier sequence, but the assert happened before that was checked. The vector holding the sequence also wasn't reset before the second check so that guaranteed the sequence would never be found to be shorter. This patch fixes this by only trying the second expansion when the earlier fails. Fixes PR54812. Reviewed By: benshi001 Differential Revision: https://reviews.llvm.org/D123406 (cherry picked from commit 70046438d02ba1ec6bc2e2fc496b610cc1068b0f) --- .../Target/RISCV/MCTargetDesc/RISCVMatInt.cpp | 54 ++++++++++--------- llvm/test/CodeGen/RISCV/imm.ll | 36 +++++++++++++ 2 files changed, 64 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp index e935179e5f9b0..4adcd25600f20 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -302,32 +302,34 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) { TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0)); if (TmpSeq.size() < Res.size()) Res = TmpSeq; - } - // Try to use LUI+SH*ADD+ADDI. - int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull; - int64_t Lo12 = SignExtend64<12>(Val); - Div = 0; - if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) { - Div = 3; - Opc = RISCV::SH1ADD; - } else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) { - Div = 5; - Opc = RISCV::SH2ADD; - } else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) { - Div = 9; - Opc = RISCV::SH3ADD; - } - // Build the new instruction sequence. - if (Div > 0) { - // For Val that has zero Lo12 (implies Val equals to Hi52) should has - // already been processed to LUI+SH*ADD by previous optimization. - assert(Lo12 != 0 && - "unexpected instruction sequence for immediate materialisation"); - generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq); - TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0)); - TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); - if (TmpSeq.size() < Res.size()) - Res = TmpSeq; + } else { + // Try to use LUI+SH*ADD+ADDI. + int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull; + int64_t Lo12 = SignExtend64<12>(Val); + Div = 0; + if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) { + Div = 3; + Opc = RISCV::SH1ADD; + } else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) { + Div = 5; + Opc = RISCV::SH2ADD; + } else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) { + Div = 9; + Opc = RISCV::SH3ADD; + } + // Build the new instruction sequence. + if (Div > 0) { + // For Val that has zero Lo12 (implies Val equals to Hi52) should has + // already been processed to LUI+SH*ADD by previous optimization. + assert(Lo12 != 0 && + "unexpected instruction sequence for immediate materialisation"); + assert(TmpSeq.empty() && "Expected empty TmpSeq"); + generateInstSeqImpl(Hi52 / Div, ActiveFeatures, TmpSeq); + TmpSeq.push_back(RISCVMatInt::Inst(Opc, 0)); + TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); + if (TmpSeq.size() < Res.size()) + Res = TmpSeq; + } } } diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index 5de49d8a7f2cb..9fa688b6f75d5 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -2401,3 +2401,39 @@ define i64 @li_rori_3() { ; RV64IZBS-NEXT: ret ret i64 -2281701377 } + +; This used to assert when compiled with Zba. +define i64 @PR54812() { +; RV32I-LABEL: PR54812: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a0, 521599 +; RV32I-NEXT: li a1, -1 +; RV32I-NEXT: ret +; +; RV64I-LABEL: PR54812: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a0, 1048447 +; RV64I-NEXT: addiw a0, a0, 1407 +; RV64I-NEXT: slli a0, a0, 12 +; RV64I-NEXT: ret +; +; RV64IZBA-LABEL: PR54812: +; RV64IZBA: # %bb.0: +; RV64IZBA-NEXT: lui a0, 872917 +; RV64IZBA-NEXT: sh1add a0, a0, a0 +; RV64IZBA-NEXT: ret +; +; RV64IZBB-LABEL: PR54812: +; RV64IZBB: # %bb.0: +; RV64IZBB-NEXT: lui a0, 1048447 +; RV64IZBB-NEXT: addiw a0, a0, 1407 +; RV64IZBB-NEXT: slli a0, a0, 12 +; RV64IZBB-NEXT: ret +; +; RV64IZBS-LABEL: PR54812: +; RV64IZBS: # %bb.0: +; RV64IZBS-NEXT: lui a0, 1045887 +; RV64IZBS-NEXT: bclri a0, a0, 31 +; RV64IZBS-NEXT: ret + ret i64 -2158497792; +} From 58d5fbe2c20bbd2499675c2d7a35dc157c767fec Mon Sep 17 00:00:00 2001 From: Alex Brachet Date: Fri, 11 Mar 2022 03:46:46 +0000 Subject: [PATCH 306/316] [llvm-mt] Add support /notify_update `/notify_update` is an undocumented feature used by CMake. From their usage, it looks like this feature just changes `mt`'s exit code if the output file was changed. See https://gitlab.kitware.com/cmake/cmake/-/blob/master/Source/cmcmd.cxx#L2300 this is also consistent with some testing I have done of the mt.exeshipped with Visual Studio. See also the comment at https://gitlab.kitware.com/cmake/cmake/-/blob/master/Source/cmcmd.cxx#L2440. There might be a more performant way to implement this by first checking calling `llvm::sys::fs::file_size()` and if it is the same as the new output's size use `llvm::WritableMemoryBuffer` and fallback to `llvm::FileOutputBuffer` otherwise, but these don't inherit from a common ancestor so any implementation doing this would be really ugly. Fixes https://github.com/llvm/llvm-project/issues/54329 Reviewed By: phosek Differential Revision: https://reviews.llvm.org/D121438 (cherry picked from commit e970d2823cf2a666cb597bf06ff8e0d0b880d361) --- llvm/test/tools/llvm-mt/notify_update.test | 16 ++++++++++++++ llvm/tools/llvm-mt/Opts.td | 2 +- llvm/tools/llvm-mt/llvm-mt.cpp | 25 +++++++++++++++++++++- 3 files changed, 41 insertions(+), 2 deletions(-) create mode 100644 llvm/test/tools/llvm-mt/notify_update.test diff --git a/llvm/test/tools/llvm-mt/notify_update.test b/llvm/test/tools/llvm-mt/notify_update.test new file mode 100644 index 0000000000000..f3461b3ec8fc5 --- /dev/null +++ b/llvm/test/tools/llvm-mt/notify_update.test @@ -0,0 +1,16 @@ +REQUIRES: libxml2 +UNSUPPORTED: system-windows + +Exits normally without /notify_update +RUN: llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest +RUN: rm -f %t.manifest + +We can't check exit code so all we can do is see if not considered it as a failure + +File didn't exist previously so it's an update +RUN: not llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest /notify_update +RUN: llvm-mt /manifest %p/Inputs/test_manifest.manifest /out:%t.manifest /notify_update + +New manifest, so it's an update +RUN: not llvm-mt /manifest %p/Inputs/additional.manifest /out:%t.manifest /notify_update +RUN: llvm-mt /manifest %p/Inputs/additional.manifest /out:%t.manifest /notify_update diff --git a/llvm/tools/llvm-mt/Opts.td b/llvm/tools/llvm-mt/Opts.td index da5b2c992ee35..c4f7375c6d8fa 100644 --- a/llvm/tools/llvm-mt/Opts.td +++ b/llvm/tools/llvm-mt/Opts.td @@ -23,7 +23,7 @@ def validate_file_hashes : Joined<["/", "-"], "validate_file_hashes:">, HelpText def canonicalize : Flag<["/", "-"], "canonicalize:">, HelpText<"Not supported">, Group; def check_for_duplicates : Flag<["/", "-"], "check_for_duplicates:">, HelpText<"Not supported">, Group; def make_cdfs : Flag<["/", "-"], "makecdfs:">, HelpText<"Not supported">, Group; -def notify_update : Flag<["/", "-"], "notify_update">, HelpText<"Not supported">, Group; +def notify_update : Flag<["/", "-"], "notify_update">, HelpText<"Exit with a special exit code if the output file has changed">; def verbose : Flag<["/", "-"], "verbose">, HelpText<"Not supported">, Group; def help : Flag<["/", "-"], "?">; def help_long : Flag<["/", "-"], "help">, Alias; diff --git a/llvm/tools/llvm-mt/llvm-mt.cpp b/llvm/tools/llvm-mt/llvm-mt.cpp index 60735a95efa97..74885ec28f1c3 100644 --- a/llvm/tools/llvm-mt/llvm-mt.cpp +++ b/llvm/tools/llvm-mt/llvm-mt.cpp @@ -141,6 +141,29 @@ int main(int Argc, const char **Argv) { std::unique_ptr OutputBuffer = Merger.getMergedManifest(); if (!OutputBuffer) reportError("empty manifest not written"); + + int ExitCode = 0; + if (InputArgs.hasArg(OPT_notify_update)) { + ErrorOr> OutBuffOrErr = + MemoryBuffer::getFile(OutputFile); + // Assume if we couldn't open the output file then it doesn't exist meaning + // there was a change. + bool Same = false; + if (OutBuffOrErr) { + const std::unique_ptr &FileBuffer = *OutBuffOrErr; + Same = std::equal(OutputBuffer->getBufferStart(), + OutputBuffer->getBufferEnd(), + FileBuffer->getBufferStart()); + } + if (!Same) { +#if LLVM_ON_UNIX + ExitCode = 0xbb; +#elif defined(_WIN32) + ExitCode = 0x41020001; +#endif + } + } + Expected> FileOrErr = FileOutputBuffer::create(OutputFile, OutputBuffer->getBufferSize()); if (!FileOrErr) @@ -149,5 +172,5 @@ int main(int Argc, const char **Argv) { std::copy(OutputBuffer->getBufferStart(), OutputBuffer->getBufferEnd(), FileBuffer->getBufferStart()); error(FileBuffer->commit()); - return 0; + return ExitCode; } From 21ce6cfd1d9357b54173d43e3d18960f487f6663 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Thu, 14 Apr 2022 13:03:56 +0100 Subject: [PATCH 307/316] [RISCV] Add tests showing incorrect BUILD_VECTOR lowering These tests both use vector constants misidentified as VID sequences. Because the initial run of elements has a zero step, the elements are skipped until such a step can be identified. The bug is that the skipped elements are never validated, even though the computed step is incompatible across the entire sequence. A fix will follow in a subseqeuent patch. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123785 (cherry picked from commit 00537946aa29928894ba140687de1b6f9494e44d) --- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 80c4ad8662b14..6fb669feb462a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -704,3 +704,24 @@ define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) { %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer ret <8 x i16> %splat } + +; FIXME: This is not a vid sequence! +define <4 x i8> @buildvec_not_vid_v4i8_1() { +; CHECK-LABEL: buildvec_not_vid_v4i8_1: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: ret + ret <4 x i8> +} + +; FIXME: This is not a vid sequence! +define <4 x i8> @buildvec_not_vid_v4i8_2() { +; CHECK-LABEL: buildvec_not_vid_v4i8_2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vrsub.vi v8, v8, 3 +; CHECK-NEXT: ret + ret <4 x i8> +} From 9efcce92b55bc87627b52dd1139fb9031e400b52 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Thu, 14 Apr 2022 13:09:09 +0100 Subject: [PATCH 308/316] [RISCV] Fix lowering of BUILD_VECTORs as VID sequences This patch fixes a bug when lowering BUILD_VECTOR via VID sequences. After adding support for fractional steps in D106533, elements with zero steps may be skipped if no step has yet been computed. This allowed certain sequences to slip through the cracks, being identified as VID sequences when in fact they are not. The fix for this is to perform a second loop over the BUILD_VECTOR to validate the entire sequence once the step has been computed. This isn't the most efficient, but on balance the code is more readable and maintainable than doing back-validation during the first loop. Fixes the tests introduced in D123785. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123786 (cherry picked from commit c5cac48549ed254cd5ad5eef770ebfb22ccd9f64) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 68 +++++++++++-------- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 11 +-- 2 files changed, 44 insertions(+), 35 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index e7672a7652cdd..73a29a1d9dcc3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1908,37 +1908,27 @@ static Optional isSimpleVIDSequence(SDValue Op) { // A zero-value value difference means that we're somewhere in the middle // of a fractional step, e.g. <0,0,0*,0,1,1,1,1>. Wait until we notice a // step change before evaluating the sequence. - if (ValDiff != 0) { - int64_t Remainder = ValDiff % IdxDiff; - // Normalize the step if it's greater than 1. - if (Remainder != ValDiff) { - // The difference must cleanly divide the element span. - if (Remainder != 0) - return None; - ValDiff /= IdxDiff; - IdxDiff = 1; - } - - if (!SeqStepNum) - SeqStepNum = ValDiff; - else if (ValDiff != SeqStepNum) - return None; + if (ValDiff == 0) + continue; - if (!SeqStepDenom) - SeqStepDenom = IdxDiff; - else if (IdxDiff != *SeqStepDenom) + int64_t Remainder = ValDiff % IdxDiff; + // Normalize the step if it's greater than 1. + if (Remainder != ValDiff) { + // The difference must cleanly divide the element span. + if (Remainder != 0) return None; + ValDiff /= IdxDiff; + IdxDiff = 1; } - } - // Record and/or check any addend. - if (SeqStepNum && SeqStepDenom) { - uint64_t ExpectedVal = - (int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom; - int64_t Addend = SignExtend64(Val - ExpectedVal, EltSizeInBits); - if (!SeqAddend) - SeqAddend = Addend; - else if (SeqAddend != Addend) + if (!SeqStepNum) + SeqStepNum = ValDiff; + else if (ValDiff != SeqStepNum) + return None; + + if (!SeqStepDenom) + SeqStepDenom = IdxDiff; + else if (IdxDiff != *SeqStepDenom) return None; } @@ -1946,11 +1936,29 @@ static Optional isSimpleVIDSequence(SDValue Op) { if (!PrevElt || PrevElt->first != Val) PrevElt = std::make_pair(Val, Idx); } - // We need to have logged both a step and an addend for this to count as - // a legal index sequence. - if (!SeqStepNum || !SeqStepDenom || !SeqAddend) + + // We need to have logged a step for this to count as a legal index sequence. + if (!SeqStepNum || !SeqStepDenom) return None; + // Loop back through the sequence and validate elements we might have skipped + // while waiting for a valid step. While doing this, log any sequence addend. + for (unsigned Idx = 0; Idx < NumElts; Idx++) { + if (Op.getOperand(Idx).isUndef()) + continue; + uint64_t Val = Op.getConstantOperandVal(Idx) & + maskTrailingOnes(EltSizeInBits); + uint64_t ExpectedVal = + (int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom; + int64_t Addend = SignExtend64(Val - ExpectedVal, EltSizeInBits); + if (!SeqAddend) + SeqAddend = Addend; + else if (Addend != SeqAddend) + return None; + } + + assert(SeqAddend && "Must have an addend if we have a step"); + return VIDSequence{*SeqStepNum, *SeqStepDenom, *SeqAddend}; } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 6fb669feb462a..085f5bc1d8493 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -705,23 +705,24 @@ define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) { ret <8 x i16> %splat } -; FIXME: This is not a vid sequence! define <4 x i8> @buildvec_not_vid_v4i8_1() { ; CHECK-LABEL: buildvec_not_vid_v4i8_1: ; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI37_0) +; CHECK-NEXT: addi a0, a0, %lo(.LCPI37_0) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret ret <4 x i8> } -; FIXME: This is not a vid sequence! define <4 x i8> @buildvec_not_vid_v4i8_2() { ; CHECK-LABEL: buildvec_not_vid_v4i8_2: ; CHECK: # %bb.0: +; CHECK-NEXT: lui a0, %hi(.LCPI38_0) +; CHECK-NEXT: addi a0, a0, %lo(.LCPI38_0) ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu -; CHECK-NEXT: vid.v v8 -; CHECK-NEXT: vrsub.vi v8, v8, 3 +; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret ret <4 x i8> } From e19be4195b8700ee48a84a50e65b1d4612b22cca Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Tue, 19 Apr 2022 09:25:40 +0100 Subject: [PATCH 309/316] [RISCV] Add another test showing incorrect BUILD_VECTOR lowering This test shows a (contrived) BUILD_VECTOR which is correctly identified as a sequence of ((vid * -3) / 8) + 5. However, the issue is that using shift-right for the divide is invalid as the step values are negative. This patch just adds the test: the fix is added in D123796. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123989 (cherry picked from commit 627e21048a2c040d3e353cc4f0eb8f207b6ea61c) --- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 085f5bc1d8493..3e10b0f3a49c5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -726,3 +726,18 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() { ; CHECK-NEXT: ret ret <4 x i8> } + +; FIXME: This is not a valid way to emit this vid sequence: shift-right for +; division only works for non-negative numbers! +define <16 x i8> @buildvec_not_vid_v16i8() { +; CHECK-LABEL: buildvec_not_vid_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: li a0, -3 +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: vsrl.vi v8, v8, 3 +; CHECK-NEXT: vadd.vi v8, v8, 5 +; CHECK-NEXT: ret + ret <16 x i8> +} From 1f4c7b2a9120357c2ee91bc407bf443734df54ec Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Tue, 19 Apr 2022 09:25:40 +0100 Subject: [PATCH 310/316] [RISCV] Don't emit fractional VIDs with negative steps We can't shift-right negative numbers to divide them, so avoid emitting such sequences. Use negative numerators as a proxy for this situation, since the indices are always non-negative. An alternative strategy could be to add a compiler flag to emit division instructions, which would at least allow us to test the VID sequence matching itself. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123796 (cherry picked from commit 3e678cb77264907fbc2899c291ce23af308073ff) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++- .../RISCV/rvv/fixed-vectors-int-buildvec.ll | 14 +++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 73a29a1d9dcc3..274b86593e0fd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2117,7 +2117,8 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, // a single addi instruction. if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) || (StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) && - isPowerOf2_32(StepDenominator) && isInt<5>(Addend)) { + isPowerOf2_32(StepDenominator) && + (SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) { SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL); // Convert right out of the scalable type so we can use standard ISD // nodes for the rest of the computation. If we used scalable types with diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 3e10b0f3a49c5..b623d838de3eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -727,17 +727,17 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() { ret <4 x i8> } -; FIXME: This is not a valid way to emit this vid sequence: shift-right for -; division only works for non-negative numbers! +; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce +; division to compute it. define <16 x i8> @buildvec_not_vid_v16i8() { ; CHECK-LABEL: buildvec_not_vid_v16i8: ; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 3 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v8 -; CHECK-NEXT: li a0, -3 -; CHECK-NEXT: vmul.vx v8, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v8, 3 -; CHECK-NEXT: vadd.vi v8, v8, 5 +; CHECK-NEXT: vmv.s.x v9, a0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, mu +; CHECK-NEXT: vslideup.vi v8, v9, 6 ; CHECK-NEXT: ret ret <16 x i8> } From a36801750327d05d5f8a19aec33819ae3f8f5e35 Mon Sep 17 00:00:00 2001 From: Michael Forney Date: Thu, 7 Apr 2022 22:35:24 -0700 Subject: [PATCH 311/316] [asan] Always skip first object from dl_iterate_phdr All platforms return the main executable as the first dl_phdr_info. FreeBSD, NetBSD, Solaris, and Linux-musl place the executable name in the dlpi_name field of this entry. It appears that only Linux-glibc uses the empty string. To make this work generically on all platforms, unconditionally skip the first object (like is currently done for FreeBSD and NetBSD). This fixes first DSO detection on Linux-musl. It also would likely fix detection on Solaris/Illumos if it were to gain PIE support (since dlpi_addr would not be NULL). Additionally, only skip the Linux VDSO on linux. Finally, use the empty string as the "seen first dl_phdr_info" marker rather than (char *)-1. If there was no other object, we would try to dereference it for a string comparison. Reviewed By: MaskRay, vitalybuka Differential Revision: https://reviews.llvm.org/D119515 (cherry picked from commit 795b07f5498c7e5783237418f34d7ea69e801f87) --- compiler-rt/lib/asan/asan_linux.cpp | 30 ++++++++++++----------------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/compiler-rt/lib/asan/asan_linux.cpp b/compiler-rt/lib/asan/asan_linux.cpp index 1d92c530bd110..defd81bc19e22 100644 --- a/compiler-rt/lib/asan/asan_linux.cpp +++ b/compiler-rt/lib/asan/asan_linux.cpp @@ -131,30 +131,24 @@ static int FindFirstDSOCallback(struct dl_phdr_info *info, size_t size, VReport(2, "info->dlpi_name = %s\tinfo->dlpi_addr = %p\n", info->dlpi_name, (void *)info->dlpi_addr); - // Continue until the first dynamic library is found - if (!info->dlpi_name || info->dlpi_name[0] == 0) - return 0; - - // Ignore vDSO - if (internal_strncmp(info->dlpi_name, "linux-", sizeof("linux-") - 1) == 0) - return 0; + const char **name = (const char **)data; -#if SANITIZER_FREEBSD || SANITIZER_NETBSD // Ignore first entry (the main program) - char **p = (char **)data; - if (!(*p)) { - *p = (char *)-1; + if (!*name) { + *name = ""; return 0; } -#endif -#if SANITIZER_SOLARIS - // Ignore executable on Solaris - if (info->dlpi_addr == 0) +# if SANITIZER_LINUX + // Ignore vDSO. glibc versions earlier than 2.15 (and some patched + // by distributors) return an empty name for the vDSO entry, so + // detect this as well. + if (!info->dlpi_name[0] || + internal_strncmp(info->dlpi_name, "linux-", sizeof("linux-") - 1) == 0) return 0; -#endif +# endif - *(const char **)data = info->dlpi_name; + *name = info->dlpi_name; return 1; } @@ -175,7 +169,7 @@ void AsanCheckDynamicRTPrereqs() { // Ensure that dynamic RT is the first DSO in the list const char *first_dso_name = nullptr; dl_iterate_phdr(FindFirstDSOCallback, &first_dso_name); - if (first_dso_name && !IsDynamicRTName(first_dso_name)) { + if (first_dso_name && first_dso_name[0] && !IsDynamicRTName(first_dso_name)) { Report("ASan runtime does not come first in initial library list; " "you should either link runtime to your application or " "manually preload it with LD_PRELOAD.\n"); From 0e27d08cdeb338766a477fba071b3df7a06ea6e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Marques?= Date: Thu, 7 Apr 2022 12:00:41 +0100 Subject: [PATCH 312/316] [RISCV] Fix crash for section alignment with .option norvc The existing code wasn't getting the subtarget info from the fragment, so the current status of RVC would be ignored. This would cause a crash for the new test case when the target then reported it couldn't write the requested number of code alignment bytes. Differential Revision: https://reviews.llvm.org/D122236 (cherry picked from commit d09d297c5d28bd0af4dd8bf3ca66d8dbbd196d9d) --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 8 +++++--- llvm/test/MC/RISCV/align-option-relax.s | 8 ++++++++ llvm/test/MC/RISCV/align.s | 8 ++++++++ 3 files changed, 21 insertions(+), 3 deletions(-) create mode 100644 llvm/test/MC/RISCV/align-option-relax.s diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 514789b3f6459..4b940093482f5 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -583,10 +583,11 @@ void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign( const MCAlignFragment &AF, unsigned &Size) { // Calculate Nops Size only when linker relaxation enabled. - if (!STI.getFeatureBits()[RISCV::FeatureRelax]) + const MCSubtargetInfo *STI = AF.getSubtargetInfo(); + if (!STI->getFeatureBits()[RISCV::FeatureRelax]) return false; - bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; + bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC]; unsigned MinNopLen = HasStdExtC ? 2 : 4; if (AF.getAlignment() <= MinNopLen) { @@ -606,7 +607,8 @@ bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) { // Insert the fixup only when linker relaxation enabled. - if (!STI.getFeatureBits()[RISCV::FeatureRelax]) + const MCSubtargetInfo *STI = AF.getSubtargetInfo(); + if (!STI->getFeatureBits()[RISCV::FeatureRelax]) return false; // Calculate total Nops we need to insert. If there are none to insert diff --git a/llvm/test/MC/RISCV/align-option-relax.s b/llvm/test/MC/RISCV/align-option-relax.s new file mode 100644 index 0000000000000..890e1e72d7706 --- /dev/null +++ b/llvm/test/MC/RISCV/align-option-relax.s @@ -0,0 +1,8 @@ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \ +# RUN: | llvm-readobj -r - | FileCheck %s + +# Check that .option relax overrides -mno-relax and enables R_RISCV_ALIGN +# relocations. +# CHECK: R_RISCV_ALIGN + .option relax + .align 4 diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s index 804effb6600b2..75ea8eb77bbd4 100644 --- a/llvm/test/MC/RISCV/align.s +++ b/llvm/test/MC/RISCV/align.s @@ -112,3 +112,11 @@ data1: # C-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN data2: .word 9 +# Check that the initial alignment is properly handled when using .option to +# disable the C extension. This used to crash. +# C-EXT-RELAX-INST: <.text2>: +# C-EXT-RELAX-INST-NEXT: add a0, a0, a1 + .section .text2, "x" + .option norvc + .balign 4 + add a0, a0, a1 From 06b0a94619ca20f2ecbfca3440f02db0efe7a269 Mon Sep 17 00:00:00 2001 From: Mark Shinwell Date: Thu, 28 Apr 2022 16:00:36 +0100 Subject: [PATCH 313/316] Update README.md --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index f79f4fc2ae0b5..e0675815ca88d 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,7 @@ +# ocaml-flambda/llvm-project + +This repository is currently for development of a version of lldb that works well in conjunction with the flambda-backend compiler. The `main` branch is being used here, but this isn't quite the same as the upstream `main` branch: it is based off a recent LLVM release to ensure everything compiles. + # The LLVM Compiler Infrastructure This directory and its sub-directories contain source code for LLVM, From ce79eea47d7840ae5cf0e5b6768f770c19dfab1d Mon Sep 17 00:00:00 2001 From: Mark Shinwell Date: Thu, 28 Apr 2022 16:13:38 +0100 Subject: [PATCH 314/316] Delete PULL_REQUEST_TEMPLATE.md --- .github/PULL_REQUEST_TEMPLATE.md | 5 ----- 1 file changed, 5 deletions(-) delete mode 100644 .github/PULL_REQUEST_TEMPLATE.md diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md deleted file mode 100644 index a3d33bdb4d438..0000000000000 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ /dev/null @@ -1,5 +0,0 @@ -# **DO NOT FILE A PULL REQUEST** - -This repository does not accept pull requests. Please follow http://llvm.org/docs/Contributing.html#how-to-submit-a-patch for contribution to LLVM. - -# **DO NOT FILE A PULL REQUEST** From 394b0b9e6e469c2b326d13ce807af4d3e688c82c Mon Sep 17 00:00:00 2001 From: Mark Shinwell Date: Fri, 29 Apr 2022 08:46:56 +0100 Subject: [PATCH 315/316] Use Clang TypeSystem for OCaml debugging (#1) --- lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 418f613e5cc95..486b8297229ae 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -109,7 +109,9 @@ TypeSystemClangSupportsLanguage(lldb::LanguageType language) { // Use Clang for D until there is a proper language plugin for it language == eLanguageTypeD || // Open Dylan compiler debug info is designed to be Clang-compatible - language == eLanguageTypeDylan; + language == eLanguageTypeDylan || + // For the moment use the Clang code for OCaml + language == eLanguageTypeOCaml; } // Checks whether m1 is an overload of m2 (as opposed to an override). This is From e94c5aa14a7b57e5e9de6e2b2df565f765bce85a Mon Sep 17 00:00:00 2001 From: poechsel Date: Thu, 13 Oct 2022 11:44:03 -0400 Subject: [PATCH 316/316] Add redhat to vendor list --- llvm/include/llvm/ADT/Triple.h | 3 ++- llvm/lib/Support/Triple.cpp | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h index 42277c0130359..5e8e1e37ad2b0 100644 --- a/llvm/include/llvm/ADT/Triple.h +++ b/llvm/include/llvm/ADT/Triple.h @@ -165,7 +165,8 @@ class Triple { Mesa, SUSE, OpenEmbedded, - LastVendorType = OpenEmbedded + RedHat, + LastVendorType = RedHat }; enum OSType { UnknownOS, diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp index a9afcc9db96ab..b6268608a8a2f 100644 --- a/llvm/lib/Support/Triple.cpp +++ b/llvm/lib/Support/Triple.cpp @@ -185,6 +185,7 @@ StringRef Triple::getVendorTypeName(VendorType Kind) { case PC: return "pc"; case SCEI: return "scei"; case SUSE: return "suse"; + case RedHat: return "redhat"; } llvm_unreachable("Invalid VendorType!"); @@ -507,6 +508,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) { .Case("mesa", Triple::Mesa) .Case("suse", Triple::SUSE) .Case("oe", Triple::OpenEmbedded) + .Case("redhat", Triple::RedHat) .Default(Triple::UnknownVendor); }