diff --git a/rtl/verilog/mor1kx_execute_alu.v b/rtl/verilog/mor1kx_execute_alu.v
index 8bd771ff..eecf66da 100644
--- a/rtl/verilog/mor1kx_execute_alu.v
+++ b/rtl/verilog/mor1kx_execute_alu.v
@@ -285,6 +285,7 @@ endgenerate
 
 	 // Can't detect unsigned overflow in this implementation
 	 assign mul_unsigned_overflow = 0;
+         assign mul_signed_overflow = 0;
 
       end // if (FEATURE_MULTIPLIER=="PIPELINED")
       else if (FEATURE_MULTIPLIER=="SERIAL") begin : serialmultiply
@@ -379,6 +380,7 @@ endgenerate
          assign mul_result = 0;
          assign mul_valid = 1'b1;
 	 assign mul_unsigned_overflow = 0;
+         assign mul_signed_overflow = 0;
       end
       else begin
          // Incorrect configuration option
@@ -390,19 +392,22 @@ endgenerate
       end
    endgenerate
 
-   // One signed overflow detection for all multiplication implmentations
-   assign mul_signed_overflow = (FEATURE_MULTIPLIER=="NONE") ||
-				(FEATURE_MULTIPLIER=="PIPELINED") ? 1'b0 :
-				// Same signs, check for negative result
-				// (should be positive)
-				((a[OPTION_OPERAND_WIDTH-1] ==
-				  b[OPTION_OPERAND_WIDTH-1]) &&
-				 mul_result[OPTION_OPERAND_WIDTH-1]) ||
-				// Differring signs, check for positive result
-				// (should be negative)
-				((a[OPTION_OPERAND_WIDTH-1] ^
-				  b[OPTION_OPERAND_WIDTH-1]) &&
-				 !mul_result[OPTION_OPERAND_WIDTH-1]);
+    // One signed overflow detection for all multiplication implmentations
+    assign mul_signed_overflow = (FEATURE_MULTIPLIER=="NONE") ||
+ 				(FEATURE_MULTIPLIER=="PIPELINED") ? 1'b0 :
+                                // When either a or b is 0, result should not
+                                // be negative
+                                ((a == 0 || b == 0) && mul_result[OPTION_OPERAND_WIDTH-1]) ||
+ 				// Same signs, check for negative result
+ 				// (should be positive)
+ 				((a[OPTION_OPERAND_WIDTH-1] ==
+ 				  b[OPTION_OPERAND_WIDTH-1]) &&
+ 				 mul_result[OPTION_OPERAND_WIDTH-1]) ||
+ 				// Differring signs, check for positive result
+ 				// (should be negative)
+ 				((a[OPTION_OPERAND_WIDTH-1] ^
+ 				  b[OPTION_OPERAND_WIDTH-1]) &&
+ 				 !mul_result[OPTION_OPERAND_WIDTH-1]);
 
    assign mul_result_o = mul_result;