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wallentowallento
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Adopt OpenRISC patch to recent changes
1 parent 1413e9a commit b7dfedc

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4 files changed

+55
-59
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4 files changed

+55
-59
lines changed

‎gcc/config/or1k/or1k.c

Lines changed: 35 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -26,13 +26,20 @@
2626
#include "config.h"
2727
#include "system.h"
2828
#include "coretypes.h"
29-
#include "tm.h"
29+
#include "backend.h"
30+
#include "target.h"
3031
#include "rtl.h"
32+
#include "tree.h"
33+
#include "df.h"
34+
#include "tm.h"
35+
#include "tm_p.h"
36+
#include "stringpool.h"
37+
#include "optabs.h"
3138
#include "hash-set.h"
39+
#include "emit-rtl.h"
40+
#include "recog.h"
3241
#include "inchash.h"
3342
#include "symtab.h"
34-
#include "tree.h"
35-
#include "stringpool.h"
3643
#include "stor-layout.h"
3744
#include "calls.h"
3845
#include "varasm.h"
@@ -48,24 +55,19 @@
4855
#include "reload.h"
4956
#include "function.h"
5057
#include "explow.h"
51-
#include "emit-rtl.h"
5258
#include "expr.h"
5359
#include "toplev.h"
54-
#include "recog.h"
5560
#include "ggc.h"
5661
#include "except.h"
57-
#include "tm_p.h"
58-
#include "target.h"
5962
#include "target-def.h"
6063
#include "debug.h"
6164
#include "langhooks.h"
6265
#include "predict.h"
6366
#include "basic-block.h"
64-
#include "df.h"
65-
#include "optabs.h"
6667
#include "dwarf2.h"
6768
#include "ansidecl.h"
6869
#include "builtins.h"
70+
#include "sbitmap.h"
6971

7072
/* ========================================================================== */
7173
/* Local macros */
@@ -379,7 +381,7 @@ or1k_expand_int_compare (enum rtx_code code,
379381
/* This is very simple, but making the interface the same as in the
380382
FP case makes the rest of the code easier. */
381383
tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
382-
emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
384+
emit_insn (gen_rtx_SET (flags, tmp));
383385

384386
/* Return the test that should be put into the flags user, i.e.
385387
the bcc, scc, or cmov instruction. */
@@ -434,14 +436,14 @@ or1k_expand_cmpxchg_qihi (rtx bval, rtx retval, rtx mem, rtx oldval, rtx newval,
434436

435437
mask_const = gen_rtx_CONST_INT (VOIDmode,
436438
mode == QImode ? 0xff : 0xffff);
437-
emit_insn (gen_rtx_SET (VOIDmode, mask, mask_const));
439+
emit_insn (gen_rtx_SET (mask, mask_const));
438440

439441
/* align address and retrieve the offset. */
440-
emit_insn (gen_rtx_SET (VOIDmode, addr,
442+
emit_insn (gen_rtx_SET (addr,
441443
gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
442-
emit_insn (gen_rtx_SET (VOIDmode, off,
444+
emit_insn (gen_rtx_SET (off,
443445
gen_rtx_AND (SImode, addr1, GEN_INT (3))));
444-
emit_insn (gen_rtx_SET (VOIDmode, off,
446+
emit_insn (gen_rtx_SET (off,
445447
gen_rtx_XOR (SImode, off,
446448
GEN_INT (GET_MODE (mem) == QImode
447449
? 3 : 2))));
@@ -450,7 +452,7 @@ or1k_expand_cmpxchg_qihi (rtx bval, rtx retval, rtx mem, rtx oldval, rtx newval,
450452

451453
/* shift all arguments to be aligned to where the data we want
452454
* to operate on is located. */
453-
emit_insn (gen_rtx_SET (VOIDmode, shifter,
455+
emit_insn (gen_rtx_SET (shifter,
454456
gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
455457

456458
emit_insn (gen_ashlsi3 (shifted_oldval, oldval, shifter));
@@ -490,14 +492,14 @@ or1k_expand_fetch_op_qihi (rtx oldval, rtx mem, rtx operand, rtx newval,
490492

491493
mask_const = gen_rtx_CONST_INT (VOIDmode,
492494
mode == QImode ? 0xff : 0xffff);
493-
emit_insn (gen_rtx_SET (VOIDmode, mask, mask_const));
495+
emit_insn (gen_rtx_SET (mask, mask_const));
494496

495497
/* align address and retrieve the offset. */
496-
emit_insn (gen_rtx_SET (VOIDmode, addr,
498+
emit_insn (gen_rtx_SET (addr,
497499
gen_rtx_AND (Pmode, addr1, GEN_INT (-4))));
498-
emit_insn (gen_rtx_SET (VOIDmode, off,
500+
emit_insn (gen_rtx_SET (off,
499501
gen_rtx_AND (SImode, addr1, GEN_INT (3))));
500-
emit_insn (gen_rtx_SET (VOIDmode, off,
502+
emit_insn (gen_rtx_SET (off,
501503
gen_rtx_XOR (SImode, off,
502504
GEN_INT (GET_MODE (mem) == QImode
503505
? 3 : 2))));
@@ -506,7 +508,7 @@ or1k_expand_fetch_op_qihi (rtx oldval, rtx mem, rtx operand, rtx newval,
506508

507509
/* shift all arguments to be aligned to where the data we want
508510
* to operate on is located. */
509-
emit_insn (gen_rtx_SET (VOIDmode, shifter,
511+
emit_insn (gen_rtx_SET (shifter,
510512
gen_rtx_ASHIFT (SImode, off, GEN_INT (3))));
511513

512514
emit_insn (gen_ashlsi3 (shifted_operand, operand, shifter));
@@ -565,7 +567,7 @@ or1k_emit_int_cmove (rtx dest,
565567

566568

567569
static void
568-
or1k_print_operand_address (FILE *stream, rtx addr)
570+
or1k_print_operand_address (FILE *stream, machine_mode /* mode */, rtx addr)
569571
{
570572
rtx offset;
571573

@@ -595,7 +597,7 @@ or1k_print_operand_address (FILE *stream, rtx addr)
595597
offset = XEXP (addr, 0);
596598
addr = XEXP (addr, 1);
597599
}
598-
output_address (offset);
600+
output_address (GET_MODE(addr), offset);
599601
fprintf (stream, "(%s)", reg_names[REGNO (addr)]);
600602
break;
601603

@@ -999,7 +1001,7 @@ or1k_emit_binary (enum rtx_code code,
9991001
rtx op0,
10001002
rtx op1)
10011003
{
1002-
emit_insn (gen_rtx_SET (VOIDmode, target,
1004+
emit_insn (gen_rtx_SET (target,
10031005
gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
10041006

10051007
} /* or1k_emit_binary () */
@@ -1102,8 +1104,7 @@ or1k_expand_prologue (void)
11021104
GEN_INT (-frame_info.gpr_frame)));
11031105
if (frame_info.save_fp_p)
11041106
{
1105-
emit_frame_insn (gen_rtx_SET (Pmode,
1106-
stack_disp_mem (frame_info.fp_save_offset),
1107+
emit_frame_insn (gen_rtx_SET (stack_disp_mem (frame_info.fp_save_offset),
11071108
hard_frame_pointer_rtx));
11081109

11091110
emit_frame_insn
@@ -1112,7 +1113,7 @@ or1k_expand_prologue (void)
11121113
if (frame_info.save_lr_p)
11131114
{
11141115
emit_frame_insn
1115-
(gen_rtx_SET (Pmode, stack_disp_mem (frame_info.lr_save_offset),
1116+
(gen_rtx_SET (stack_disp_mem (frame_info.lr_save_offset),
11161117
gen_rtx_REG (Pmode, LINK_REGNUM)));
11171118
}
11181119
if (frame_info.gpr_size)
@@ -1134,8 +1135,7 @@ or1k_expand_prologue (void)
11341135
!= frame_info.fp_save_offset));
11351136

11361137
emit_frame_insn
1137-
(gen_rtx_SET (Pmode,
1138-
stack_disp_mem (frame_info.gpr_offset + offset),
1138+
(gen_rtx_SET (stack_disp_mem (frame_info.gpr_offset + offset),
11391139
gen_rtx_REG (Pmode, regno)));
11401140
offset = offset + UNITS_PER_WORD;
11411141
}
@@ -1194,7 +1194,7 @@ or1k_expand_epilogue (void)
11941194
{
11951195
emit_insn (gen_frame_dealloc_fp ());
11961196
emit_insn
1197-
(gen_rtx_SET (Pmode, hard_frame_pointer_rtx,
1197+
(gen_rtx_SET (hard_frame_pointer_rtx,
11981198
stack_disp_mem (frame_info.fp_save_offset)));
11991199
}
12001200
else
@@ -1217,7 +1217,7 @@ or1k_expand_epilogue (void)
12171217
if (frame_info.save_lr_p && !crtl->calls_eh_return)
12181218
{
12191219
emit_insn
1220-
(gen_rtx_SET (Pmode, gen_rtx_REG (Pmode, LINK_REGNUM),
1220+
(gen_rtx_SET (gen_rtx_REG (Pmode, LINK_REGNUM),
12211221
stack_disp_mem (frame_info.lr_save_offset)));
12221222
}
12231223

@@ -1233,7 +1233,7 @@ or1k_expand_epilogue (void)
12331233

12341234
if (regno != FIRST_PSEUDO_REGISTER)
12351235
emit_insn
1236-
(gen_rtx_SET (Pmode, gen_rtx_REG (Pmode, regno),
1236+
(gen_rtx_SET (gen_rtx_REG (Pmode, regno),
12371237
stack_disp_mem (frame_info.gpr_offset + offset)));
12381238
offset = offset + UNITS_PER_WORD;
12391239
}
@@ -1414,7 +1414,7 @@ or1k_expand_conditional_branch (rtx *operands,
14141414
tmp,
14151415
gen_rtx_LABEL_REF (VOIDmode, operands[3]),
14161416
pc_rtx);
1417-
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
1417+
emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
14181418
return;
14191419

14201420
case SFmode:
@@ -1423,7 +1423,7 @@ or1k_expand_conditional_branch (rtx *operands,
14231423
tmp,
14241424
gen_rtx_LABEL_REF (VOIDmode, operands[3]),
14251425
pc_rtx);
1426-
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
1426+
emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
14271427
return;
14281428

14291429
default:
@@ -1554,12 +1554,11 @@ or1k_emit_set_const32 (rtx op0,
15541554
/* Emit them as real moves instead of a HIGH/LO_SUM,
15551555
this way CSE can see everything and reuse intermediate
15561556
values if it wants. */
1557-
emit_insn (gen_rtx_SET (VOIDmode, temp,
1557+
emit_insn (gen_rtx_SET (temp,
15581558
GEN_INT (INTVAL (op1)
15591559
& ~(HOST_WIDE_INT) 0xffff)));
15601560

1561-
emit_insn (gen_rtx_SET (VOIDmode,
1562-
op0,
1561+
emit_insn (gen_rtx_SET (op0,
15631562
gen_rtx_IOR (mode, temp,
15641563
GEN_INT (INTVAL (op1) & 0xffff))));
15651564
}

‎gcc/config/or1k/or1k.h

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ Boston, MA 02111-1307, USA. */
166166

167167
/* Define if operations between registers always perform the operation
168168
on the full register even if a narrower mode is specified. */
169-
#define WORD_REGISTER_OPERATIONS /* CHECK */
169+
#define WORD_REGISTER_OPERATIONS 1
170170

171171

172172
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
@@ -344,9 +344,6 @@ Boston, MA 02111-1307, USA. */
344344
is passed to a function. */
345345
/*#define STRUCT_VALUE_REGNUM 0*/
346346

347-
/* Pass address of result struct to callee as "invisible" first argument */
348-
#define STRUCT_VALUE 0
349-
350347
/* -----------------------[ PHX start ]-------------------------------- */
351348

352349
/* Define the classes of registers for register constraints in the
@@ -1153,7 +1150,7 @@ enum reg_class
11531150
else if (GET_CODE (x) == REG) \
11541151
fprintf (stream, "%s", reg_names[REGNO (x)]); \
11551152
else if (GET_CODE (x) == MEM) \
1156-
output_address (XEXP (x, 0)); \
1153+
output_address (GET_MODE(x), XEXP (x, 0)); \
11571154
else \
11581155
output_addr_const (stream, x); \
11591156
}

‎gcc/config/or1k/or1k.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@
192192
{
193193
rtx reg = gen_reg_rtx (SImode);
194194

195-
emit_insn (gen_rtx_SET (SImode, reg,
195+
emit_insn (gen_rtx_SET (reg,
196196
gen_rtx_ZERO_EXTEND (SImode,
197197
operands[1])));
198198

@@ -238,7 +238,7 @@
238238
{
239239
rtx reg = gen_reg_rtx (SImode);
240240

241-
emit_insn (gen_rtx_SET (SImode, reg,
241+
emit_insn (gen_rtx_SET (reg,
242242
gen_rtx_ZERO_EXTEND (SImode,
243243
operands[1])));
244244
operands[1] = gen_lowpart (HImode, reg);

‎gcc/config/or1k/or1k.opt

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -25,71 +25,71 @@ enum or1k_delay or1k_delay_selected = OR1K_DELAY_DEFAULT
2525

2626
mdelay
2727
Target RejectNegative Negative(mno-delay) Var(or1k_delay_selected, OR1K_DELAY_ON)
28-
Assume branches and jumps have a delay slot
28+
Assume branches and jumps have a delay slot.
2929

3030
mno-delay
3131
Target RejectNegative Negative(mcompat-delay) Var(or1k_delay_selected, OR1K_DELAY_OFF)
32-
Assume branches and jumps do not have a delay slot
32+
Assume branches and jumps do not have a delay slot.
3333

3434
mcompat-delay
3535
Target RejectNegative Negative(mdelay) Var(or1k_delay_selected, OR1K_DELAY_COMPAT)
36-
Assume branches and jumps have a delay slot, but fill them with nops
36+
Assume branches and jumps have a delay slot, but fill them with nops.
3737

3838
mhard-float
3939
Target RejectNegative Mask(HARD_FLOAT)
40-
Use hardware floating point
40+
Use hardware floating point.
4141

4242
msoft-float
4343
Target RejectNegative InverseMask(HARD_FLOAT)
44-
Do not use hardware floating point
44+
Do not use hardware floating point.
4545

4646
mdouble-float
4747
Target Report RejectNegative Mask(DOUBLE_FLOAT)
48-
Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations
48+
Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
4949

5050
mhard-div
5151
Target RejectNegative Mask(HARD_DIV)
52-
Use hardware division
52+
Use hardware division.
5353

5454
msoft-div
5555
Target RejectNegative InverseMask(HARD_DIV)
56-
Do not use hardware division
56+
Do not use hardware division.
5757

5858
mhard-mul
5959
Target RejectNegative Mask(HARD_MUL)
60-
Use hardware multiplication
60+
Use hardware multiplication.
6161

6262
msoft-mul
6363
Target RejectNegative InverseMask(HARD_MUL)
64-
Do not use hardware multiplication
64+
Do not use hardware multiplication.
6565

6666
msext
6767
Target Mask(MASK_SEXT)
68-
Use sign-extending instructions
68+
Use sign-extending instructions.
6969

7070
mcmov
7171
Target Mask(MASK_CMOV)
72-
Use conditional move instructions
72+
Use conditional move instructions.
7373

7474
mror
7575
Target Mask(MASK_ROR)
76-
Emit ROR instructions
76+
Emit ROR instructions.
7777

7878
mboard=
7979
Target RejectNegative Joined
80-
Link with libgloss configuration suitable for this board
80+
Link with libgloss configuration suitable for this board.
8181

8282
mnewlib
8383
Target Report RejectNegative
84-
Compile for the Linux/Gnu/newlib based toolchain
84+
Compile for the Linux/Gnu/newlib based toolchain.
8585

8686
;; provide struct padding as in previous releases.
8787
;; Note that this will only affect STRUCTURE_SIZE_BOUNDARY, in particular
8888
;; make 2 byte structs 4-byte alignned and sized.
8989
;; We still use ROUND_TYPE_ALIGN to increase alignment of larger structs.
9090
mpadstruct
9191
Target Report RejectNegative Mask(PADSTRUCT)
92-
Make structs a multiple of 4 bytes (warning: ABI altered)
92+
Make structs a multiple of 4 bytes (warning: ABI altered).
9393

9494
mredzone=
9595
Target RejectNegative Joined UInteger Var(or1k_redzone) Init(128)

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