Support for spec 1.3 #13
Description
Changes
- ORFPX64A32 double-precision floating point operations on 32-bit hardware using register pairs (P14)
- Define CPUCFGR[15] for ORFPX64A32 presence flag
- New instructions lf.stod.d lf.dtos.d for converting between single and double precision floats (P7)
New instruction l.adrp for constructing addresses (P9) - New instructions lf.sfun* to support unordered compares (P11)
- New instruction l.lf to load floats with NaN boxing on 64-bit hardware