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    14 repositories

    • LoongsonSDCardExpander

      Public
      1•0•0•0•Updated Jul 14, 2023Jul 14, 2023

    • linux

      Public
      Linux kernel source tree
      C
      •
      Other
      •55k•2•0•0•Updated Jul 31, 2022Jul 31, 2022

    • uboot

      Public
      C
      •0•1•0•0•Updated Jul 27, 2022Jul 27, 2022

    • SoC

      Public archive
      SystemVerilog
      •0•0•0•0•Updated May 15, 2021May 15, 2021

    • loongson-blocks

      Public
      Verilog
      •0•0•0•0•Updated May 15, 2021May 15, 2021

    • t123yh-NaiveMIPS

      Public archive
      Assembly
      •0•0•0•0•Updated May 13, 2021May 13, 2021

    • Xilinx-primitive

      Public
      Verilog
      •0•0•0•0•Updated May 11, 2021May 11, 2021

    • dukelec-cdbus_ip

      Public archive
      CDBUS Protocol and the IP Core for FPGA users
      Verilog
      •57•0•0•0•Updated May 10, 2021May 10, 2021

    • ZipCPU-wb2axip

      Public archive
      Bus bridges and other odds and ends
      Verilog
      •105•0•0•0•Updated May 9, 2021May 9, 2021

    • opencores-i2c

      Public archive
      I2C controller core
      Verilog
      •36•0•0•0•Updated May 1, 2021May 1, 2021

    • mczerski-SD-card-controller

      Public archive
      WISHBONE SD Card Controller IP Core
      Verilog
      •48•0•0•0•Updated Apr 27, 2021Apr 27, 2021

    • pulp-axi

      Public archive
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •275•0•0•0•Updated Apr 23, 2021Apr 23, 2021

    • pulp-common_cells

      Public archive
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •153•0•0•0•Updated Apr 7, 2021Apr 7, 2021

    • Xilinx-AXI-Intc

      Public archive
      VHDL
      •0•0•0•0•Updated Apr 3, 2021Apr 3, 2021