Users following svunit
Hua-Chen (Nora) Wu
trista-csee
Dynamic Verification Engineer proficient in FPGA co-design, UVM verification, and award-winning privacy solutions.
National Yang Ming Chiao Tung University Taiwan
Andrew Plumb
clothbot
E.Eng, EDA/CAD hacker, VE3SLG, bassist, violist, 3dprinting, reprap, open source bits & atoms, dabbler in everything.
ClothBot Designs Ottawa, Ontario, Canada
Santhoshkumar Singuru
ssanthoshvlsi
Iam intrested in VLSI frontend. Here i want to put my projects of verilog, systemverilog, UVM, protocols like AXI,SPI etc....
Vishakhapatnam, Hyderabad