-
Notifications
You must be signed in to change notification settings - Fork 6
/
Copy pathsw_pe_array_mux_25to1_sel5_8_1.v
148 lines (136 loc) · 4.43 KB
/
sw_pe_array_mux_25to1_sel5_8_1.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sw_pe_array_mux_25to1_sel5_8_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
din11_WIDTH = 32,
din12_WIDTH = 32,
din13_WIDTH = 32,
din14_WIDTH = 32,
din15_WIDTH = 32,
din16_WIDTH = 32,
din17_WIDTH = 32,
din18_WIDTH = 32,
din19_WIDTH = 32,
din20_WIDTH = 32,
din21_WIDTH = 32,
din22_WIDTH = 32,
din23_WIDTH = 32,
din24_WIDTH = 32,
din25_WIDTH = 32,
din26_WIDTH = 32,
dout_WIDTH = 32
)(
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [7 : 0] din4,
input [7 : 0] din5,
input [7 : 0] din6,
input [7 : 0] din7,
input [7 : 0] din8,
input [7 : 0] din9,
input [7 : 0] din10,
input [7 : 0] din11,
input [7 : 0] din12,
input [7 : 0] din13,
input [7 : 0] din14,
input [7 : 0] din15,
input [7 : 0] din16,
input [7 : 0] din17,
input [7 : 0] din18,
input [7 : 0] din19,
input [7 : 0] din20,
input [7 : 0] din21,
input [7 : 0] din22,
input [7 : 0] din23,
input [7 : 0] din24,
input [7 : 0] din25,
input [4 : 0] din26,
output [7 : 0] dout);
// puts internal signals
wire [4 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
wire [7 : 0] mux_1_2;
wire [7 : 0] mux_1_3;
wire [7 : 0] mux_1_4;
wire [7 : 0] mux_1_5;
wire [7 : 0] mux_1_6;
wire [7 : 0] mux_1_7;
wire [7 : 0] mux_1_8;
wire [7 : 0] mux_1_9;
wire [7 : 0] mux_1_10;
wire [7 : 0] mux_1_11;
wire [7 : 0] mux_1_12;
// level 2 signals
wire [7 : 0] mux_2_0;
wire [7 : 0] mux_2_1;
wire [7 : 0] mux_2_2;
wire [7 : 0] mux_2_3;
wire [7 : 0] mux_2_4;
wire [7 : 0] mux_2_5;
wire [7 : 0] mux_2_6;
// level 3 signals
wire [7 : 0] mux_3_0;
wire [7 : 0] mux_3_1;
wire [7 : 0] mux_3_2;
wire [7 : 0] mux_3_3;
// level 4 signals
wire [7 : 0] mux_4_0;
wire [7 : 0] mux_4_1;
// level 5 signals
wire [7 : 0] mux_5_0;
assign sel = din26;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = (sel[0] == 0)? din5 : din6;
assign mux_1_3 = (sel[0] == 0)? din7 : din8;
assign mux_1_4 = (sel[0] == 0)? din9 : din10;
assign mux_1_5 = (sel[0] == 0)? din11 : din12;
assign mux_1_6 = (sel[0] == 0)? din13 : din14;
assign mux_1_7 = (sel[0] == 0)? din15 : din16;
assign mux_1_8 = (sel[0] == 0)? din17 : din18;
assign mux_1_9 = (sel[0] == 0)? din19 : din20;
assign mux_1_10 = (sel[0] == 0)? din21 : din22;
assign mux_1_11 = (sel[0] == 0)? din23 : din24;
assign mux_1_12 = din25;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3;
assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5;
assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7;
assign mux_2_4 = (sel[1] == 0)? mux_1_8 : mux_1_9;
assign mux_2_5 = (sel[1] == 0)? mux_1_10 : mux_1_11;
assign mux_2_6 = mux_1_12;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3;
assign mux_3_2 = (sel[2] == 0)? mux_2_4 : mux_2_5;
assign mux_3_3 = mux_2_6;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1;
assign mux_4_1 = (sel[3] == 0)? mux_3_2 : mux_3_3;
// Generate level 5 logic
assign mux_5_0 = (sel[4] == 0)? mux_4_0 : mux_4_1;
// output logic
assign dout = mux_5_0;
endmodule