diff --git a/.gitignore b/.gitignore index 3901de0..ebc50ae 100644 --- a/.gitignore +++ b/.gitignore @@ -2,7 +2,9 @@ Bender.lock bender scripts/compile.tcl +scripts/synth_compile.tcl update-ips.log +synth-ips.log build-hw.log profile-ips.log magia_venv/ diff --git a/Bender.local b/Bender.local index ff6b321..c7a6a13 100644 --- a/Bender.local +++ b/Bender.local @@ -2,7 +2,7 @@ overrides: fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 } hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 } cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 1a93f340e9dadb9f7c8c471f27a40932c8b1c62e } - cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: e51af131252027374d083a745ab6727fb9959daa } + cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } axi : { git: "https://github.com/pulp-platform/axi.git" , version: 0.39.5 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git", rev: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 } idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: c12caf59bb482fe44b27361f6924ad346b2d22fe } diff --git a/Bender.yml b/Bender.yml index 751105f..33fb6e3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,21 +23,21 @@ package: dependencies: redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 9a1aa14be0b23f0ade84bab57e7e434397ac9876 } # branch: vi/scale_up - cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: e51af131252027374d083a745ab6727fb9959daa } # branch: vi/redmule_scaleup + cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } # branch: vi/redmule_scaleup idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: a6b190c7991331432afa9a2899d032bc1b176830 } # branch: vi/redmule_scaleup hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , version: 1.6 } hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , rev: c35d5b0886ab549fb9144c3c14a4682112330e21 } # branch: yt/reqrsp hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 5a48a854573fca5bbabc1cfd4110fa4530a50ed7 } # branch: vi/redmule_scaleup cluster_icache : { git: "https://github.com/pulp-platform/cluster_icache.git" , rev: 917ecbf908bdaa22c5713bbcff277d142506bb16 } # branch: michaero/astral fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: "pulp-v0.1.3" } - fpu_ss : { git: "https://github.com/pulp-platform/fpu_ss.git" , rev: 6a83b1754196c3d4509ce823118a190917f3b88a } # branch: vi/bender_manifest + fpu_ss : { git: "https://github.com/pulp-platform/fpu_ss.git" , rev: 8e2eff774d9d38a1e17a46bd56a0936dac9522f0 } # branch: vi/bender_manifest obi : { git: "https://github.com/pulp-platform/obi.git" , version: 0.1.6 } axi : { git: "https://github.com/pulp-platform/axi.git" , version: 0.39.5 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } safety_island : { git: "https://github.com/pulp-platform/safety_island.git" , rev: 2273db6c780ab7c582feaf0c9645ad644c35aa11 } # branch: vi/redmule_scaleup common_cells : { git: "https://github.com/pulp-platform/common_cells.git" , version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } - fractal_sync : { git: "https://github.com/VictorIsachi/fractal_sync" , rev: 7eb581d5e39f18498d30607263a000f444b4b63e } # branch: main + fractal_sync : { git: "https://github.com/VictorIsachi/fractal_sync" , rev: fdb619f40f99d769cfceb20ac2117ff8d99e98a3 } # branch: main floo_noc : { git: "https://github.com/pulp-platform/FlooNoC.git" , rev: f4a36265cda8b56faee45692afb20ddfffba6dee } # branch: main export_include_dirs: @@ -124,6 +124,12 @@ sources: - target: all(not(magia_dv), asic) files: + # NoC + - hw/mesh/noc/floo_axi_mesh_2x2_noc.sv + - hw/mesh/noc/floo_axi_mesh_4x4_noc.sv + - hw/mesh/noc/floo_axi_mesh_8x8_noc.sv + - hw/mesh/noc/floo_axi_mesh_16x16_noc.sv + - hw/mesh/noc/floo_axi_mesh_32x32_noc.sv # MAGIA Packages - hw/mesh/magia_pkg.sv - hw/tile/magia_tile_pkg.sv @@ -154,5 +160,5 @@ sources: - hw/mesh/noc/floo_axi_mesh_32x32_noc.sv - hw/mesh/magia.sv # Tech - - redmule_mesh_gf12/sourcecode/tc_sram.sv - - redmule_mesh_gf12/sourcecode/tc_clk.sv + - pd/sourcecode/tc_sram.sv + - pd/sourcecode/tc_clk.sv diff --git a/Makefile b/Makefile index ecd7409..81b7b0b 100644 --- a/Makefile +++ b/Makefile @@ -343,4 +343,4 @@ MAGIA_NONFREE_COMMIT ?= main .PHONY: magia-nonfree-init magia-nonfree-init: git clone $(MAGIA_NONFREE_REMOTE) $(MAGIA_NONFREE_DIR) - cd $(MAGIA_NONFREE_DIR) && git checkout $(MAGIA_NONFREE_COMMIT) \ No newline at end of file + cd $(MAGIA_NONFREE_DIR) && git checkout $(MAGIA_NONFREE_COMMIT) diff --git a/bender_synth.mk b/bender_synth.mk index 4f8a70d..4bd5430 100644 --- a/bender_synth.mk +++ b/bender_synth.mk @@ -24,4 +24,5 @@ synth_targs += -t synopsys # synth_defs += -D REDMULE_HWPE_SYNTH #endif -synth_defs += -D REDMULE_COMPLEX_SYNTH \ No newline at end of file +synth_defs += -D REDMULE_COMPLEX_SYNTH +synth_defs += -D SYNTHESIS diff --git a/hw/mesh/magia.sv b/hw/mesh/magia.sv index d92d707..ac88c10 100644 --- a/hw/mesh/magia.sv +++ b/hw/mesh/magia.sv @@ -415,7 +415,7 @@ module magia .v_2d_fsync_req_o ( v_root_fsync_req ), .v_2d_fsync_rsp_i ( v_root_fsync_rsp ) ); - end else $fatal("Unsupported Mesh configuration"); + end else $fatal(1,"Unsupported Mesh configuration"); /*******************************************************/ /** FractalSync Network End **/ diff --git a/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv b/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv index 5e994d9..22c3f43 100644 --- a/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv +++ b/hw/mesh/noc/floo_axi_mesh_16x16_noc.sv @@ -629,26969 +629,3 @@ typedef logic[0:0] axi_data_slv_user_t; endpackage - -module floo_axi_mesh_16x16_noc - import floo_pkg::*; - import floo_axi_mesh_16x16_noc_pkg::*; -( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input axi_data_slv_req_t [15:0][15:0] magia_tile_data_slv_req_i, - output axi_data_slv_rsp_t [15:0][15:0] magia_tile_data_slv_rsp_o, - output axi_data_mst_req_t [15:0][15:0] magia_tile_data_mst_req_o, - input axi_data_mst_rsp_t [15:0][15:0] magia_tile_data_mst_rsp_i, - output axi_data_mst_req_t [15:0] L2_data_mst_req_o, - input axi_data_mst_rsp_t [15:0] L2_data_mst_rsp_i - -); - -floo_req_t router_0_0_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_0_rsp; - -floo_req_t router_0_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_magia_tile_ni_0_0_req; -floo_rsp_t magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_L2_ni_0_req; -floo_rsp_t L2_ni_0_to_router_0_0_rsp; - -floo_req_t router_0_1_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_magia_tile_ni_0_1_req; -floo_rsp_t magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_L2_ni_1_req; -floo_rsp_t L2_ni_1_to_router_0_1_rsp; - -floo_req_t router_0_2_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_magia_tile_ni_0_2_req; -floo_rsp_t magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_L2_ni_2_req; -floo_rsp_t L2_ni_2_to_router_0_2_rsp; - -floo_req_t router_0_3_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_magia_tile_ni_0_3_req; -floo_rsp_t magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_L2_ni_3_req; -floo_rsp_t L2_ni_3_to_router_0_3_rsp; - -floo_req_t router_0_4_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_magia_tile_ni_0_4_req; -floo_rsp_t magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_L2_ni_4_req; -floo_rsp_t L2_ni_4_to_router_0_4_rsp; - -floo_req_t router_0_5_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_magia_tile_ni_0_5_req; -floo_rsp_t magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_L2_ni_5_req; -floo_rsp_t L2_ni_5_to_router_0_5_rsp; - -floo_req_t router_0_6_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_magia_tile_ni_0_6_req; -floo_rsp_t magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_L2_ni_6_req; -floo_rsp_t L2_ni_6_to_router_0_6_rsp; - -floo_req_t router_0_7_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_7_rsp; - -floo_req_t router_0_7_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_0_7_rsp; - -floo_req_t router_0_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_magia_tile_ni_0_7_req; -floo_rsp_t magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_L2_ni_7_req; -floo_rsp_t L2_ni_7_to_router_0_7_rsp; - -floo_req_t router_0_8_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_0_8_rsp; - -floo_req_t router_0_8_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_0_8_rsp; - -floo_req_t router_0_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_0_8_rsp; - -floo_req_t router_0_8_to_magia_tile_ni_0_8_req; -floo_rsp_t magia_tile_ni_0_8_to_router_0_8_rsp; - -floo_req_t router_0_8_to_L2_ni_8_req; -floo_rsp_t L2_ni_8_to_router_0_8_rsp; - -floo_req_t router_0_9_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_0_9_rsp; - -floo_req_t router_0_9_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_0_9_rsp; - -floo_req_t router_0_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_0_9_rsp; - -floo_req_t router_0_9_to_magia_tile_ni_0_9_req; -floo_rsp_t magia_tile_ni_0_9_to_router_0_9_rsp; - -floo_req_t router_0_9_to_L2_ni_9_req; -floo_rsp_t L2_ni_9_to_router_0_9_rsp; - -floo_req_t router_0_10_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_0_10_rsp; - -floo_req_t router_0_10_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_0_10_rsp; - -floo_req_t router_0_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_0_10_rsp; - -floo_req_t router_0_10_to_magia_tile_ni_0_10_req; -floo_rsp_t magia_tile_ni_0_10_to_router_0_10_rsp; - -floo_req_t router_0_10_to_L2_ni_10_req; -floo_rsp_t L2_ni_10_to_router_0_10_rsp; - -floo_req_t router_0_11_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_0_11_rsp; - -floo_req_t router_0_11_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_0_11_rsp; - -floo_req_t router_0_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_0_11_rsp; - -floo_req_t router_0_11_to_magia_tile_ni_0_11_req; -floo_rsp_t magia_tile_ni_0_11_to_router_0_11_rsp; - -floo_req_t router_0_11_to_L2_ni_11_req; -floo_rsp_t L2_ni_11_to_router_0_11_rsp; - -floo_req_t router_0_12_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_0_12_rsp; - -floo_req_t router_0_12_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_0_12_rsp; - -floo_req_t router_0_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_0_12_rsp; - -floo_req_t router_0_12_to_magia_tile_ni_0_12_req; -floo_rsp_t magia_tile_ni_0_12_to_router_0_12_rsp; - -floo_req_t router_0_12_to_L2_ni_12_req; -floo_rsp_t L2_ni_12_to_router_0_12_rsp; - -floo_req_t router_0_13_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_0_13_rsp; - -floo_req_t router_0_13_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_0_13_rsp; - -floo_req_t router_0_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_0_13_rsp; - -floo_req_t router_0_13_to_magia_tile_ni_0_13_req; -floo_rsp_t magia_tile_ni_0_13_to_router_0_13_rsp; - -floo_req_t router_0_13_to_L2_ni_13_req; -floo_rsp_t L2_ni_13_to_router_0_13_rsp; - -floo_req_t router_0_14_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_0_14_rsp; - -floo_req_t router_0_14_to_router_0_15_req; -floo_rsp_t router_0_15_to_router_0_14_rsp; - -floo_req_t router_0_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_0_14_rsp; - -floo_req_t router_0_14_to_magia_tile_ni_0_14_req; -floo_rsp_t magia_tile_ni_0_14_to_router_0_14_rsp; - -floo_req_t router_0_14_to_L2_ni_14_req; -floo_rsp_t L2_ni_14_to_router_0_14_rsp; - -floo_req_t router_0_15_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_0_15_rsp; - -floo_req_t router_0_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_0_15_rsp; - -floo_req_t router_0_15_to_magia_tile_ni_0_15_req; -floo_rsp_t magia_tile_ni_0_15_to_router_0_15_rsp; - -floo_req_t router_0_15_to_L2_ni_15_req; -floo_rsp_t L2_ni_15_to_router_0_15_rsp; - -floo_req_t router_1_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_magia_tile_ni_1_0_req; -floo_rsp_t magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_req_t router_1_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_magia_tile_ni_1_1_req; -floo_rsp_t magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_req_t router_1_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_magia_tile_ni_1_2_req; -floo_rsp_t magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_req_t router_1_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_magia_tile_ni_1_3_req; -floo_rsp_t magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_req_t router_1_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_magia_tile_ni_1_4_req; -floo_rsp_t magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_req_t router_1_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_magia_tile_ni_1_5_req; -floo_rsp_t magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_req_t router_1_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_magia_tile_ni_1_6_req; -floo_rsp_t magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_req_t router_1_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_magia_tile_ni_1_7_req; -floo_rsp_t magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_req_t router_1_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_1_8_rsp; - -floo_req_t router_1_8_to_magia_tile_ni_1_8_req; -floo_rsp_t magia_tile_ni_1_8_to_router_1_8_rsp; - -floo_req_t router_1_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_1_9_rsp; - -floo_req_t router_1_9_to_magia_tile_ni_1_9_req; -floo_rsp_t magia_tile_ni_1_9_to_router_1_9_rsp; - -floo_req_t router_1_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_1_10_rsp; - -floo_req_t router_1_10_to_magia_tile_ni_1_10_req; -floo_rsp_t magia_tile_ni_1_10_to_router_1_10_rsp; - -floo_req_t router_1_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_1_11_rsp; - -floo_req_t router_1_11_to_magia_tile_ni_1_11_req; -floo_rsp_t magia_tile_ni_1_11_to_router_1_11_rsp; - -floo_req_t router_1_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_1_12_rsp; - -floo_req_t router_1_12_to_magia_tile_ni_1_12_req; -floo_rsp_t magia_tile_ni_1_12_to_router_1_12_rsp; - -floo_req_t router_1_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_1_13_rsp; - -floo_req_t router_1_13_to_magia_tile_ni_1_13_req; -floo_rsp_t magia_tile_ni_1_13_to_router_1_13_rsp; - -floo_req_t router_1_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_1_14_rsp; - -floo_req_t router_1_14_to_magia_tile_ni_1_14_req; -floo_rsp_t magia_tile_ni_1_14_to_router_1_14_rsp; - -floo_req_t router_1_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_router_1_15_rsp; - -floo_req_t router_1_15_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_1_15_rsp; - -floo_req_t router_1_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_1_15_rsp; - -floo_req_t router_1_15_to_magia_tile_ni_1_15_req; -floo_rsp_t magia_tile_ni_1_15_to_router_1_15_rsp; - -floo_req_t router_2_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_magia_tile_ni_2_0_req; -floo_rsp_t magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_req_t router_2_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_magia_tile_ni_2_1_req; -floo_rsp_t magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_req_t router_2_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_magia_tile_ni_2_2_req; -floo_rsp_t magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_req_t router_2_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_magia_tile_ni_2_3_req; -floo_rsp_t magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_req_t router_2_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_magia_tile_ni_2_4_req; -floo_rsp_t magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_req_t router_2_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_magia_tile_ni_2_5_req; -floo_rsp_t magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_req_t router_2_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_magia_tile_ni_2_6_req; -floo_rsp_t magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_req_t router_2_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_magia_tile_ni_2_7_req; -floo_rsp_t magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_req_t router_2_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_2_8_rsp; - -floo_req_t router_2_8_to_magia_tile_ni_2_8_req; -floo_rsp_t magia_tile_ni_2_8_to_router_2_8_rsp; - -floo_req_t router_2_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_2_9_rsp; - -floo_req_t router_2_9_to_magia_tile_ni_2_9_req; -floo_rsp_t magia_tile_ni_2_9_to_router_2_9_rsp; - -floo_req_t router_2_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_2_10_rsp; - -floo_req_t router_2_10_to_magia_tile_ni_2_10_req; -floo_rsp_t magia_tile_ni_2_10_to_router_2_10_rsp; - -floo_req_t router_2_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_2_11_rsp; - -floo_req_t router_2_11_to_magia_tile_ni_2_11_req; -floo_rsp_t magia_tile_ni_2_11_to_router_2_11_rsp; - -floo_req_t router_2_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_2_12_rsp; - -floo_req_t router_2_12_to_magia_tile_ni_2_12_req; -floo_rsp_t magia_tile_ni_2_12_to_router_2_12_rsp; - -floo_req_t router_2_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_2_13_rsp; - -floo_req_t router_2_13_to_magia_tile_ni_2_13_req; -floo_rsp_t magia_tile_ni_2_13_to_router_2_13_rsp; - -floo_req_t router_2_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_2_14_rsp; - -floo_req_t router_2_14_to_magia_tile_ni_2_14_req; -floo_rsp_t magia_tile_ni_2_14_to_router_2_14_rsp; - -floo_req_t router_2_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_2_15_rsp; - -floo_req_t router_2_15_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_2_15_rsp; - -floo_req_t router_2_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_2_15_rsp; - -floo_req_t router_2_15_to_magia_tile_ni_2_15_req; -floo_rsp_t magia_tile_ni_2_15_to_router_2_15_rsp; - -floo_req_t router_3_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_magia_tile_ni_3_0_req; -floo_rsp_t magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_req_t router_3_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_magia_tile_ni_3_1_req; -floo_rsp_t magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_req_t router_3_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_magia_tile_ni_3_2_req; -floo_rsp_t magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_req_t router_3_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_magia_tile_ni_3_3_req; -floo_rsp_t magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_req_t router_3_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_magia_tile_ni_3_4_req; -floo_rsp_t magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_req_t router_3_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_magia_tile_ni_3_5_req; -floo_rsp_t magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_req_t router_3_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_magia_tile_ni_3_6_req; -floo_rsp_t magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_req_t router_3_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_magia_tile_ni_3_7_req; -floo_rsp_t magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_req_t router_3_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_3_8_rsp; - -floo_req_t router_3_8_to_magia_tile_ni_3_8_req; -floo_rsp_t magia_tile_ni_3_8_to_router_3_8_rsp; - -floo_req_t router_3_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_3_9_rsp; - -floo_req_t router_3_9_to_magia_tile_ni_3_9_req; -floo_rsp_t magia_tile_ni_3_9_to_router_3_9_rsp; - -floo_req_t router_3_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_3_10_rsp; - -floo_req_t router_3_10_to_magia_tile_ni_3_10_req; -floo_rsp_t magia_tile_ni_3_10_to_router_3_10_rsp; - -floo_req_t router_3_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_3_11_rsp; - -floo_req_t router_3_11_to_magia_tile_ni_3_11_req; -floo_rsp_t magia_tile_ni_3_11_to_router_3_11_rsp; - -floo_req_t router_3_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_3_12_rsp; - -floo_req_t router_3_12_to_magia_tile_ni_3_12_req; -floo_rsp_t magia_tile_ni_3_12_to_router_3_12_rsp; - -floo_req_t router_3_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_3_13_rsp; - -floo_req_t router_3_13_to_magia_tile_ni_3_13_req; -floo_rsp_t magia_tile_ni_3_13_to_router_3_13_rsp; - -floo_req_t router_3_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_3_14_rsp; - -floo_req_t router_3_14_to_magia_tile_ni_3_14_req; -floo_rsp_t magia_tile_ni_3_14_to_router_3_14_rsp; - -floo_req_t router_3_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_3_15_rsp; - -floo_req_t router_3_15_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_3_15_rsp; - -floo_req_t router_3_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_3_15_rsp; - -floo_req_t router_3_15_to_magia_tile_ni_3_15_req; -floo_rsp_t magia_tile_ni_3_15_to_router_3_15_rsp; - -floo_req_t router_4_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_magia_tile_ni_4_0_req; -floo_rsp_t magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_req_t router_4_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_magia_tile_ni_4_1_req; -floo_rsp_t magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_req_t router_4_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_magia_tile_ni_4_2_req; -floo_rsp_t magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_req_t router_4_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_magia_tile_ni_4_3_req; -floo_rsp_t magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_req_t router_4_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_magia_tile_ni_4_4_req; -floo_rsp_t magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_req_t router_4_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_magia_tile_ni_4_5_req; -floo_rsp_t magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_req_t router_4_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_magia_tile_ni_4_6_req; -floo_rsp_t magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_req_t router_4_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_magia_tile_ni_4_7_req; -floo_rsp_t magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_req_t router_4_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_4_8_rsp; - -floo_req_t router_4_8_to_magia_tile_ni_4_8_req; -floo_rsp_t magia_tile_ni_4_8_to_router_4_8_rsp; - -floo_req_t router_4_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_4_9_rsp; - -floo_req_t router_4_9_to_magia_tile_ni_4_9_req; -floo_rsp_t magia_tile_ni_4_9_to_router_4_9_rsp; - -floo_req_t router_4_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_4_10_rsp; - -floo_req_t router_4_10_to_magia_tile_ni_4_10_req; -floo_rsp_t magia_tile_ni_4_10_to_router_4_10_rsp; - -floo_req_t router_4_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_4_11_rsp; - -floo_req_t router_4_11_to_magia_tile_ni_4_11_req; -floo_rsp_t magia_tile_ni_4_11_to_router_4_11_rsp; - -floo_req_t router_4_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_4_12_rsp; - -floo_req_t router_4_12_to_magia_tile_ni_4_12_req; -floo_rsp_t magia_tile_ni_4_12_to_router_4_12_rsp; - -floo_req_t router_4_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_4_13_rsp; - -floo_req_t router_4_13_to_magia_tile_ni_4_13_req; -floo_rsp_t magia_tile_ni_4_13_to_router_4_13_rsp; - -floo_req_t router_4_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_4_14_rsp; - -floo_req_t router_4_14_to_magia_tile_ni_4_14_req; -floo_rsp_t magia_tile_ni_4_14_to_router_4_14_rsp; - -floo_req_t router_4_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_4_15_rsp; - -floo_req_t router_4_15_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_4_15_rsp; - -floo_req_t router_4_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_4_15_rsp; - -floo_req_t router_4_15_to_magia_tile_ni_4_15_req; -floo_rsp_t magia_tile_ni_4_15_to_router_4_15_rsp; - -floo_req_t router_5_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_magia_tile_ni_5_0_req; -floo_rsp_t magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_req_t router_5_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_magia_tile_ni_5_1_req; -floo_rsp_t magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_req_t router_5_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_magia_tile_ni_5_2_req; -floo_rsp_t magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_req_t router_5_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_magia_tile_ni_5_3_req; -floo_rsp_t magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_req_t router_5_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_magia_tile_ni_5_4_req; -floo_rsp_t magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_req_t router_5_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_magia_tile_ni_5_5_req; -floo_rsp_t magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_req_t router_5_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_magia_tile_ni_5_6_req; -floo_rsp_t magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_req_t router_5_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_magia_tile_ni_5_7_req; -floo_rsp_t magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_req_t router_5_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_5_8_rsp; - -floo_req_t router_5_8_to_magia_tile_ni_5_8_req; -floo_rsp_t magia_tile_ni_5_8_to_router_5_8_rsp; - -floo_req_t router_5_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_5_9_rsp; - -floo_req_t router_5_9_to_magia_tile_ni_5_9_req; -floo_rsp_t magia_tile_ni_5_9_to_router_5_9_rsp; - -floo_req_t router_5_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_5_10_rsp; - -floo_req_t router_5_10_to_magia_tile_ni_5_10_req; -floo_rsp_t magia_tile_ni_5_10_to_router_5_10_rsp; - -floo_req_t router_5_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_5_11_rsp; - -floo_req_t router_5_11_to_magia_tile_ni_5_11_req; -floo_rsp_t magia_tile_ni_5_11_to_router_5_11_rsp; - -floo_req_t router_5_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_5_12_rsp; - -floo_req_t router_5_12_to_magia_tile_ni_5_12_req; -floo_rsp_t magia_tile_ni_5_12_to_router_5_12_rsp; - -floo_req_t router_5_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_5_13_rsp; - -floo_req_t router_5_13_to_magia_tile_ni_5_13_req; -floo_rsp_t magia_tile_ni_5_13_to_router_5_13_rsp; - -floo_req_t router_5_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_5_14_rsp; - -floo_req_t router_5_14_to_magia_tile_ni_5_14_req; -floo_rsp_t magia_tile_ni_5_14_to_router_5_14_rsp; - -floo_req_t router_5_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_5_15_rsp; - -floo_req_t router_5_15_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_5_15_rsp; - -floo_req_t router_5_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_5_15_rsp; - -floo_req_t router_5_15_to_magia_tile_ni_5_15_req; -floo_rsp_t magia_tile_ni_5_15_to_router_5_15_rsp; - -floo_req_t router_6_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_magia_tile_ni_6_0_req; -floo_rsp_t magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_req_t router_6_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_magia_tile_ni_6_1_req; -floo_rsp_t magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_req_t router_6_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_magia_tile_ni_6_2_req; -floo_rsp_t magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_req_t router_6_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_magia_tile_ni_6_3_req; -floo_rsp_t magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_req_t router_6_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_magia_tile_ni_6_4_req; -floo_rsp_t magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_req_t router_6_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_magia_tile_ni_6_5_req; -floo_rsp_t magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_req_t router_6_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_magia_tile_ni_6_6_req; -floo_rsp_t magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_req_t router_6_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_magia_tile_ni_6_7_req; -floo_rsp_t magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_req_t router_6_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_6_8_rsp; - -floo_req_t router_6_8_to_magia_tile_ni_6_8_req; -floo_rsp_t magia_tile_ni_6_8_to_router_6_8_rsp; - -floo_req_t router_6_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_6_9_rsp; - -floo_req_t router_6_9_to_magia_tile_ni_6_9_req; -floo_rsp_t magia_tile_ni_6_9_to_router_6_9_rsp; - -floo_req_t router_6_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_6_10_rsp; - -floo_req_t router_6_10_to_magia_tile_ni_6_10_req; -floo_rsp_t magia_tile_ni_6_10_to_router_6_10_rsp; - -floo_req_t router_6_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_6_11_rsp; - -floo_req_t router_6_11_to_magia_tile_ni_6_11_req; -floo_rsp_t magia_tile_ni_6_11_to_router_6_11_rsp; - -floo_req_t router_6_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_6_12_rsp; - -floo_req_t router_6_12_to_magia_tile_ni_6_12_req; -floo_rsp_t magia_tile_ni_6_12_to_router_6_12_rsp; - -floo_req_t router_6_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_6_13_rsp; - -floo_req_t router_6_13_to_magia_tile_ni_6_13_req; -floo_rsp_t magia_tile_ni_6_13_to_router_6_13_rsp; - -floo_req_t router_6_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_6_14_rsp; - -floo_req_t router_6_14_to_magia_tile_ni_6_14_req; -floo_rsp_t magia_tile_ni_6_14_to_router_6_14_rsp; - -floo_req_t router_6_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_6_15_rsp; - -floo_req_t router_6_15_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_6_15_rsp; - -floo_req_t router_6_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_6_15_rsp; - -floo_req_t router_6_15_to_magia_tile_ni_6_15_req; -floo_rsp_t magia_tile_ni_6_15_to_router_6_15_rsp; - -floo_req_t router_7_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_7_0_rsp; - -floo_req_t router_7_0_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_0_rsp; - -floo_req_t router_7_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_7_0_rsp; - -floo_req_t router_7_0_to_magia_tile_ni_7_0_req; -floo_rsp_t magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_req_t router_7_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_7_1_rsp; - -floo_req_t router_7_1_to_magia_tile_ni_7_1_req; -floo_rsp_t magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_req_t router_7_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_7_2_rsp; - -floo_req_t router_7_2_to_magia_tile_ni_7_2_req; -floo_rsp_t magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_req_t router_7_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_7_3_rsp; - -floo_req_t router_7_3_to_magia_tile_ni_7_3_req; -floo_rsp_t magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_req_t router_7_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_7_4_rsp; - -floo_req_t router_7_4_to_magia_tile_ni_7_4_req; -floo_rsp_t magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_req_t router_7_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_7_5_rsp; - -floo_req_t router_7_5_to_magia_tile_ni_7_5_req; -floo_rsp_t magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_req_t router_7_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_7_6_rsp; - -floo_req_t router_7_6_to_magia_tile_ni_7_6_req; -floo_rsp_t magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_req_t router_7_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_7_7_rsp; - -floo_req_t router_7_7_to_magia_tile_ni_7_7_req; -floo_rsp_t magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_req_t router_7_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_7_8_rsp; - -floo_req_t router_7_8_to_magia_tile_ni_7_8_req; -floo_rsp_t magia_tile_ni_7_8_to_router_7_8_rsp; - -floo_req_t router_7_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_7_9_rsp; - -floo_req_t router_7_9_to_magia_tile_ni_7_9_req; -floo_rsp_t magia_tile_ni_7_9_to_router_7_9_rsp; - -floo_req_t router_7_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_7_10_rsp; - -floo_req_t router_7_10_to_magia_tile_ni_7_10_req; -floo_rsp_t magia_tile_ni_7_10_to_router_7_10_rsp; - -floo_req_t router_7_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_7_11_rsp; - -floo_req_t router_7_11_to_magia_tile_ni_7_11_req; -floo_rsp_t magia_tile_ni_7_11_to_router_7_11_rsp; - -floo_req_t router_7_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_7_12_rsp; - -floo_req_t router_7_12_to_magia_tile_ni_7_12_req; -floo_rsp_t magia_tile_ni_7_12_to_router_7_12_rsp; - -floo_req_t router_7_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_7_13_rsp; - -floo_req_t router_7_13_to_magia_tile_ni_7_13_req; -floo_rsp_t magia_tile_ni_7_13_to_router_7_13_rsp; - -floo_req_t router_7_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_7_14_rsp; - -floo_req_t router_7_14_to_magia_tile_ni_7_14_req; -floo_rsp_t magia_tile_ni_7_14_to_router_7_14_rsp; - -floo_req_t router_7_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_7_15_rsp; - -floo_req_t router_7_15_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_7_15_rsp; - -floo_req_t router_7_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_7_15_rsp; - -floo_req_t router_7_15_to_magia_tile_ni_7_15_req; -floo_rsp_t magia_tile_ni_7_15_to_router_7_15_rsp; - -floo_req_t router_8_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_8_0_rsp; - -floo_req_t router_8_0_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_8_0_rsp; - -floo_req_t router_8_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_8_0_rsp; - -floo_req_t router_8_0_to_magia_tile_ni_8_0_req; -floo_rsp_t magia_tile_ni_8_0_to_router_8_0_rsp; - -floo_req_t router_8_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_8_1_rsp; - -floo_req_t router_8_1_to_magia_tile_ni_8_1_req; -floo_rsp_t magia_tile_ni_8_1_to_router_8_1_rsp; - -floo_req_t router_8_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_8_2_rsp; - -floo_req_t router_8_2_to_magia_tile_ni_8_2_req; -floo_rsp_t magia_tile_ni_8_2_to_router_8_2_rsp; - -floo_req_t router_8_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_8_3_rsp; - -floo_req_t router_8_3_to_magia_tile_ni_8_3_req; -floo_rsp_t magia_tile_ni_8_3_to_router_8_3_rsp; - -floo_req_t router_8_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_8_4_rsp; - -floo_req_t router_8_4_to_magia_tile_ni_8_4_req; -floo_rsp_t magia_tile_ni_8_4_to_router_8_4_rsp; - -floo_req_t router_8_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_8_5_rsp; - -floo_req_t router_8_5_to_magia_tile_ni_8_5_req; -floo_rsp_t magia_tile_ni_8_5_to_router_8_5_rsp; - -floo_req_t router_8_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_8_6_rsp; - -floo_req_t router_8_6_to_magia_tile_ni_8_6_req; -floo_rsp_t magia_tile_ni_8_6_to_router_8_6_rsp; - -floo_req_t router_8_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_8_7_rsp; - -floo_req_t router_8_7_to_magia_tile_ni_8_7_req; -floo_rsp_t magia_tile_ni_8_7_to_router_8_7_rsp; - -floo_req_t router_8_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_8_8_rsp; - -floo_req_t router_8_8_to_magia_tile_ni_8_8_req; -floo_rsp_t magia_tile_ni_8_8_to_router_8_8_rsp; - -floo_req_t router_8_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_8_9_rsp; - -floo_req_t router_8_9_to_magia_tile_ni_8_9_req; -floo_rsp_t magia_tile_ni_8_9_to_router_8_9_rsp; - -floo_req_t router_8_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_8_10_rsp; - -floo_req_t router_8_10_to_magia_tile_ni_8_10_req; -floo_rsp_t magia_tile_ni_8_10_to_router_8_10_rsp; - -floo_req_t router_8_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_8_11_rsp; - -floo_req_t router_8_11_to_magia_tile_ni_8_11_req; -floo_rsp_t magia_tile_ni_8_11_to_router_8_11_rsp; - -floo_req_t router_8_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_8_12_rsp; - -floo_req_t router_8_12_to_magia_tile_ni_8_12_req; -floo_rsp_t magia_tile_ni_8_12_to_router_8_12_rsp; - -floo_req_t router_8_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_8_13_rsp; - -floo_req_t router_8_13_to_magia_tile_ni_8_13_req; -floo_rsp_t magia_tile_ni_8_13_to_router_8_13_rsp; - -floo_req_t router_8_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_8_14_rsp; - -floo_req_t router_8_14_to_magia_tile_ni_8_14_req; -floo_rsp_t magia_tile_ni_8_14_to_router_8_14_rsp; - -floo_req_t router_8_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_8_15_rsp; - -floo_req_t router_8_15_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_8_15_rsp; - -floo_req_t router_8_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_8_15_rsp; - -floo_req_t router_8_15_to_magia_tile_ni_8_15_req; -floo_rsp_t magia_tile_ni_8_15_to_router_8_15_rsp; - -floo_req_t router_9_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_9_0_rsp; - -floo_req_t router_9_0_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_9_0_rsp; - -floo_req_t router_9_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_9_0_rsp; - -floo_req_t router_9_0_to_magia_tile_ni_9_0_req; -floo_rsp_t magia_tile_ni_9_0_to_router_9_0_rsp; - -floo_req_t router_9_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_9_1_rsp; - -floo_req_t router_9_1_to_magia_tile_ni_9_1_req; -floo_rsp_t magia_tile_ni_9_1_to_router_9_1_rsp; - -floo_req_t router_9_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_9_2_rsp; - -floo_req_t router_9_2_to_magia_tile_ni_9_2_req; -floo_rsp_t magia_tile_ni_9_2_to_router_9_2_rsp; - -floo_req_t router_9_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_9_3_rsp; - -floo_req_t router_9_3_to_magia_tile_ni_9_3_req; -floo_rsp_t magia_tile_ni_9_3_to_router_9_3_rsp; - -floo_req_t router_9_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_9_4_rsp; - -floo_req_t router_9_4_to_magia_tile_ni_9_4_req; -floo_rsp_t magia_tile_ni_9_4_to_router_9_4_rsp; - -floo_req_t router_9_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_9_5_rsp; - -floo_req_t router_9_5_to_magia_tile_ni_9_5_req; -floo_rsp_t magia_tile_ni_9_5_to_router_9_5_rsp; - -floo_req_t router_9_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_9_6_rsp; - -floo_req_t router_9_6_to_magia_tile_ni_9_6_req; -floo_rsp_t magia_tile_ni_9_6_to_router_9_6_rsp; - -floo_req_t router_9_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_9_7_rsp; - -floo_req_t router_9_7_to_magia_tile_ni_9_7_req; -floo_rsp_t magia_tile_ni_9_7_to_router_9_7_rsp; - -floo_req_t router_9_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_9_8_rsp; - -floo_req_t router_9_8_to_magia_tile_ni_9_8_req; -floo_rsp_t magia_tile_ni_9_8_to_router_9_8_rsp; - -floo_req_t router_9_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_9_9_rsp; - -floo_req_t router_9_9_to_magia_tile_ni_9_9_req; -floo_rsp_t magia_tile_ni_9_9_to_router_9_9_rsp; - -floo_req_t router_9_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_9_10_rsp; - -floo_req_t router_9_10_to_magia_tile_ni_9_10_req; -floo_rsp_t magia_tile_ni_9_10_to_router_9_10_rsp; - -floo_req_t router_9_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_9_11_rsp; - -floo_req_t router_9_11_to_magia_tile_ni_9_11_req; -floo_rsp_t magia_tile_ni_9_11_to_router_9_11_rsp; - -floo_req_t router_9_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_9_12_rsp; - -floo_req_t router_9_12_to_magia_tile_ni_9_12_req; -floo_rsp_t magia_tile_ni_9_12_to_router_9_12_rsp; - -floo_req_t router_9_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_9_13_rsp; - -floo_req_t router_9_13_to_magia_tile_ni_9_13_req; -floo_rsp_t magia_tile_ni_9_13_to_router_9_13_rsp; - -floo_req_t router_9_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_9_14_rsp; - -floo_req_t router_9_14_to_magia_tile_ni_9_14_req; -floo_rsp_t magia_tile_ni_9_14_to_router_9_14_rsp; - -floo_req_t router_9_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_9_15_rsp; - -floo_req_t router_9_15_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_9_15_rsp; - -floo_req_t router_9_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_9_15_rsp; - -floo_req_t router_9_15_to_magia_tile_ni_9_15_req; -floo_rsp_t magia_tile_ni_9_15_to_router_9_15_rsp; - -floo_req_t router_10_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_10_0_rsp; - -floo_req_t router_10_0_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_10_0_rsp; - -floo_req_t router_10_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_10_0_rsp; - -floo_req_t router_10_0_to_magia_tile_ni_10_0_req; -floo_rsp_t magia_tile_ni_10_0_to_router_10_0_rsp; - -floo_req_t router_10_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_10_1_rsp; - -floo_req_t router_10_1_to_magia_tile_ni_10_1_req; -floo_rsp_t magia_tile_ni_10_1_to_router_10_1_rsp; - -floo_req_t router_10_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_10_2_rsp; - -floo_req_t router_10_2_to_magia_tile_ni_10_2_req; -floo_rsp_t magia_tile_ni_10_2_to_router_10_2_rsp; - -floo_req_t router_10_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_10_3_rsp; - -floo_req_t router_10_3_to_magia_tile_ni_10_3_req; -floo_rsp_t magia_tile_ni_10_3_to_router_10_3_rsp; - -floo_req_t router_10_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_10_4_rsp; - -floo_req_t router_10_4_to_magia_tile_ni_10_4_req; -floo_rsp_t magia_tile_ni_10_4_to_router_10_4_rsp; - -floo_req_t router_10_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_10_5_rsp; - -floo_req_t router_10_5_to_magia_tile_ni_10_5_req; -floo_rsp_t magia_tile_ni_10_5_to_router_10_5_rsp; - -floo_req_t router_10_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_10_6_rsp; - -floo_req_t router_10_6_to_magia_tile_ni_10_6_req; -floo_rsp_t magia_tile_ni_10_6_to_router_10_6_rsp; - -floo_req_t router_10_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_10_7_rsp; - -floo_req_t router_10_7_to_magia_tile_ni_10_7_req; -floo_rsp_t magia_tile_ni_10_7_to_router_10_7_rsp; - -floo_req_t router_10_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_10_8_rsp; - -floo_req_t router_10_8_to_magia_tile_ni_10_8_req; -floo_rsp_t magia_tile_ni_10_8_to_router_10_8_rsp; - -floo_req_t router_10_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_10_9_rsp; - -floo_req_t router_10_9_to_magia_tile_ni_10_9_req; -floo_rsp_t magia_tile_ni_10_9_to_router_10_9_rsp; - -floo_req_t router_10_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_10_10_rsp; - -floo_req_t router_10_10_to_magia_tile_ni_10_10_req; -floo_rsp_t magia_tile_ni_10_10_to_router_10_10_rsp; - -floo_req_t router_10_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_10_11_rsp; - -floo_req_t router_10_11_to_magia_tile_ni_10_11_req; -floo_rsp_t magia_tile_ni_10_11_to_router_10_11_rsp; - -floo_req_t router_10_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_10_12_rsp; - -floo_req_t router_10_12_to_magia_tile_ni_10_12_req; -floo_rsp_t magia_tile_ni_10_12_to_router_10_12_rsp; - -floo_req_t router_10_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_10_13_rsp; - -floo_req_t router_10_13_to_magia_tile_ni_10_13_req; -floo_rsp_t magia_tile_ni_10_13_to_router_10_13_rsp; - -floo_req_t router_10_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_10_14_rsp; - -floo_req_t router_10_14_to_magia_tile_ni_10_14_req; -floo_rsp_t magia_tile_ni_10_14_to_router_10_14_rsp; - -floo_req_t router_10_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_10_15_rsp; - -floo_req_t router_10_15_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_10_15_rsp; - -floo_req_t router_10_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_10_15_rsp; - -floo_req_t router_10_15_to_magia_tile_ni_10_15_req; -floo_rsp_t magia_tile_ni_10_15_to_router_10_15_rsp; - -floo_req_t router_11_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_11_0_rsp; - -floo_req_t router_11_0_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_11_0_rsp; - -floo_req_t router_11_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_11_0_rsp; - -floo_req_t router_11_0_to_magia_tile_ni_11_0_req; -floo_rsp_t magia_tile_ni_11_0_to_router_11_0_rsp; - -floo_req_t router_11_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_11_1_rsp; - -floo_req_t router_11_1_to_magia_tile_ni_11_1_req; -floo_rsp_t magia_tile_ni_11_1_to_router_11_1_rsp; - -floo_req_t router_11_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_11_2_rsp; - -floo_req_t router_11_2_to_magia_tile_ni_11_2_req; -floo_rsp_t magia_tile_ni_11_2_to_router_11_2_rsp; - -floo_req_t router_11_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_11_3_rsp; - -floo_req_t router_11_3_to_magia_tile_ni_11_3_req; -floo_rsp_t magia_tile_ni_11_3_to_router_11_3_rsp; - -floo_req_t router_11_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_11_4_rsp; - -floo_req_t router_11_4_to_magia_tile_ni_11_4_req; -floo_rsp_t magia_tile_ni_11_4_to_router_11_4_rsp; - -floo_req_t router_11_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_11_5_rsp; - -floo_req_t router_11_5_to_magia_tile_ni_11_5_req; -floo_rsp_t magia_tile_ni_11_5_to_router_11_5_rsp; - -floo_req_t router_11_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_11_6_rsp; - -floo_req_t router_11_6_to_magia_tile_ni_11_6_req; -floo_rsp_t magia_tile_ni_11_6_to_router_11_6_rsp; - -floo_req_t router_11_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_11_7_rsp; - -floo_req_t router_11_7_to_magia_tile_ni_11_7_req; -floo_rsp_t magia_tile_ni_11_7_to_router_11_7_rsp; - -floo_req_t router_11_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_11_8_rsp; - -floo_req_t router_11_8_to_magia_tile_ni_11_8_req; -floo_rsp_t magia_tile_ni_11_8_to_router_11_8_rsp; - -floo_req_t router_11_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_11_9_rsp; - -floo_req_t router_11_9_to_magia_tile_ni_11_9_req; -floo_rsp_t magia_tile_ni_11_9_to_router_11_9_rsp; - -floo_req_t router_11_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_11_10_rsp; - -floo_req_t router_11_10_to_magia_tile_ni_11_10_req; -floo_rsp_t magia_tile_ni_11_10_to_router_11_10_rsp; - -floo_req_t router_11_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_11_11_rsp; - -floo_req_t router_11_11_to_magia_tile_ni_11_11_req; -floo_rsp_t magia_tile_ni_11_11_to_router_11_11_rsp; - -floo_req_t router_11_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_11_12_rsp; - -floo_req_t router_11_12_to_magia_tile_ni_11_12_req; -floo_rsp_t magia_tile_ni_11_12_to_router_11_12_rsp; - -floo_req_t router_11_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_11_13_rsp; - -floo_req_t router_11_13_to_magia_tile_ni_11_13_req; -floo_rsp_t magia_tile_ni_11_13_to_router_11_13_rsp; - -floo_req_t router_11_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_11_14_rsp; - -floo_req_t router_11_14_to_magia_tile_ni_11_14_req; -floo_rsp_t magia_tile_ni_11_14_to_router_11_14_rsp; - -floo_req_t router_11_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_11_15_rsp; - -floo_req_t router_11_15_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_11_15_rsp; - -floo_req_t router_11_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_11_15_rsp; - -floo_req_t router_11_15_to_magia_tile_ni_11_15_req; -floo_rsp_t magia_tile_ni_11_15_to_router_11_15_rsp; - -floo_req_t router_12_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_12_0_rsp; - -floo_req_t router_12_0_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_12_0_rsp; - -floo_req_t router_12_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_12_0_rsp; - -floo_req_t router_12_0_to_magia_tile_ni_12_0_req; -floo_rsp_t magia_tile_ni_12_0_to_router_12_0_rsp; - -floo_req_t router_12_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_12_1_rsp; - -floo_req_t router_12_1_to_magia_tile_ni_12_1_req; -floo_rsp_t magia_tile_ni_12_1_to_router_12_1_rsp; - -floo_req_t router_12_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_12_2_rsp; - -floo_req_t router_12_2_to_magia_tile_ni_12_2_req; -floo_rsp_t magia_tile_ni_12_2_to_router_12_2_rsp; - -floo_req_t router_12_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_12_3_rsp; - -floo_req_t router_12_3_to_magia_tile_ni_12_3_req; -floo_rsp_t magia_tile_ni_12_3_to_router_12_3_rsp; - -floo_req_t router_12_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_12_4_rsp; - -floo_req_t router_12_4_to_magia_tile_ni_12_4_req; -floo_rsp_t magia_tile_ni_12_4_to_router_12_4_rsp; - -floo_req_t router_12_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_12_5_rsp; - -floo_req_t router_12_5_to_magia_tile_ni_12_5_req; -floo_rsp_t magia_tile_ni_12_5_to_router_12_5_rsp; - -floo_req_t router_12_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_12_6_rsp; - -floo_req_t router_12_6_to_magia_tile_ni_12_6_req; -floo_rsp_t magia_tile_ni_12_6_to_router_12_6_rsp; - -floo_req_t router_12_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_12_7_rsp; - -floo_req_t router_12_7_to_magia_tile_ni_12_7_req; -floo_rsp_t magia_tile_ni_12_7_to_router_12_7_rsp; - -floo_req_t router_12_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_12_8_rsp; - -floo_req_t router_12_8_to_magia_tile_ni_12_8_req; -floo_rsp_t magia_tile_ni_12_8_to_router_12_8_rsp; - -floo_req_t router_12_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_12_9_rsp; - -floo_req_t router_12_9_to_magia_tile_ni_12_9_req; -floo_rsp_t magia_tile_ni_12_9_to_router_12_9_rsp; - -floo_req_t router_12_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_12_10_rsp; - -floo_req_t router_12_10_to_magia_tile_ni_12_10_req; -floo_rsp_t magia_tile_ni_12_10_to_router_12_10_rsp; - -floo_req_t router_12_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_12_11_rsp; - -floo_req_t router_12_11_to_magia_tile_ni_12_11_req; -floo_rsp_t magia_tile_ni_12_11_to_router_12_11_rsp; - -floo_req_t router_12_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_12_12_rsp; - -floo_req_t router_12_12_to_magia_tile_ni_12_12_req; -floo_rsp_t magia_tile_ni_12_12_to_router_12_12_rsp; - -floo_req_t router_12_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_12_13_rsp; - -floo_req_t router_12_13_to_magia_tile_ni_12_13_req; -floo_rsp_t magia_tile_ni_12_13_to_router_12_13_rsp; - -floo_req_t router_12_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_12_14_rsp; - -floo_req_t router_12_14_to_magia_tile_ni_12_14_req; -floo_rsp_t magia_tile_ni_12_14_to_router_12_14_rsp; - -floo_req_t router_12_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_12_15_rsp; - -floo_req_t router_12_15_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_12_15_rsp; - -floo_req_t router_12_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_12_15_rsp; - -floo_req_t router_12_15_to_magia_tile_ni_12_15_req; -floo_rsp_t magia_tile_ni_12_15_to_router_12_15_rsp; - -floo_req_t router_13_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_13_0_rsp; - -floo_req_t router_13_0_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_13_0_rsp; - -floo_req_t router_13_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_13_0_rsp; - -floo_req_t router_13_0_to_magia_tile_ni_13_0_req; -floo_rsp_t magia_tile_ni_13_0_to_router_13_0_rsp; - -floo_req_t router_13_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_13_1_rsp; - -floo_req_t router_13_1_to_magia_tile_ni_13_1_req; -floo_rsp_t magia_tile_ni_13_1_to_router_13_1_rsp; - -floo_req_t router_13_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_13_2_rsp; - -floo_req_t router_13_2_to_magia_tile_ni_13_2_req; -floo_rsp_t magia_tile_ni_13_2_to_router_13_2_rsp; - -floo_req_t router_13_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_13_3_rsp; - -floo_req_t router_13_3_to_magia_tile_ni_13_3_req; -floo_rsp_t magia_tile_ni_13_3_to_router_13_3_rsp; - -floo_req_t router_13_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_13_4_rsp; - -floo_req_t router_13_4_to_magia_tile_ni_13_4_req; -floo_rsp_t magia_tile_ni_13_4_to_router_13_4_rsp; - -floo_req_t router_13_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_13_5_rsp; - -floo_req_t router_13_5_to_magia_tile_ni_13_5_req; -floo_rsp_t magia_tile_ni_13_5_to_router_13_5_rsp; - -floo_req_t router_13_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_13_6_rsp; - -floo_req_t router_13_6_to_magia_tile_ni_13_6_req; -floo_rsp_t magia_tile_ni_13_6_to_router_13_6_rsp; - -floo_req_t router_13_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_13_7_rsp; - -floo_req_t router_13_7_to_magia_tile_ni_13_7_req; -floo_rsp_t magia_tile_ni_13_7_to_router_13_7_rsp; - -floo_req_t router_13_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_13_8_rsp; - -floo_req_t router_13_8_to_magia_tile_ni_13_8_req; -floo_rsp_t magia_tile_ni_13_8_to_router_13_8_rsp; - -floo_req_t router_13_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_13_9_rsp; - -floo_req_t router_13_9_to_magia_tile_ni_13_9_req; -floo_rsp_t magia_tile_ni_13_9_to_router_13_9_rsp; - -floo_req_t router_13_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_13_10_rsp; - -floo_req_t router_13_10_to_magia_tile_ni_13_10_req; -floo_rsp_t magia_tile_ni_13_10_to_router_13_10_rsp; - -floo_req_t router_13_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_13_11_rsp; - -floo_req_t router_13_11_to_magia_tile_ni_13_11_req; -floo_rsp_t magia_tile_ni_13_11_to_router_13_11_rsp; - -floo_req_t router_13_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_13_12_rsp; - -floo_req_t router_13_12_to_magia_tile_ni_13_12_req; -floo_rsp_t magia_tile_ni_13_12_to_router_13_12_rsp; - -floo_req_t router_13_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_13_13_rsp; - -floo_req_t router_13_13_to_magia_tile_ni_13_13_req; -floo_rsp_t magia_tile_ni_13_13_to_router_13_13_rsp; - -floo_req_t router_13_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_13_14_rsp; - -floo_req_t router_13_14_to_magia_tile_ni_13_14_req; -floo_rsp_t magia_tile_ni_13_14_to_router_13_14_rsp; - -floo_req_t router_13_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_13_15_rsp; - -floo_req_t router_13_15_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_13_15_rsp; - -floo_req_t router_13_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_13_15_rsp; - -floo_req_t router_13_15_to_magia_tile_ni_13_15_req; -floo_rsp_t magia_tile_ni_13_15_to_router_13_15_rsp; - -floo_req_t router_14_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_14_0_rsp; - -floo_req_t router_14_0_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_14_0_rsp; - -floo_req_t router_14_0_to_router_15_0_req; -floo_rsp_t router_15_0_to_router_14_0_rsp; - -floo_req_t router_14_0_to_magia_tile_ni_14_0_req; -floo_rsp_t magia_tile_ni_14_0_to_router_14_0_rsp; - -floo_req_t router_14_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_14_1_rsp; - -floo_req_t router_14_1_to_magia_tile_ni_14_1_req; -floo_rsp_t magia_tile_ni_14_1_to_router_14_1_rsp; - -floo_req_t router_14_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_14_2_rsp; - -floo_req_t router_14_2_to_magia_tile_ni_14_2_req; -floo_rsp_t magia_tile_ni_14_2_to_router_14_2_rsp; - -floo_req_t router_14_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_14_3_rsp; - -floo_req_t router_14_3_to_magia_tile_ni_14_3_req; -floo_rsp_t magia_tile_ni_14_3_to_router_14_3_rsp; - -floo_req_t router_14_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_14_4_rsp; - -floo_req_t router_14_4_to_magia_tile_ni_14_4_req; -floo_rsp_t magia_tile_ni_14_4_to_router_14_4_rsp; - -floo_req_t router_14_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_14_5_rsp; - -floo_req_t router_14_5_to_magia_tile_ni_14_5_req; -floo_rsp_t magia_tile_ni_14_5_to_router_14_5_rsp; - -floo_req_t router_14_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_14_6_rsp; - -floo_req_t router_14_6_to_magia_tile_ni_14_6_req; -floo_rsp_t magia_tile_ni_14_6_to_router_14_6_rsp; - -floo_req_t router_14_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_14_7_rsp; - -floo_req_t router_14_7_to_magia_tile_ni_14_7_req; -floo_rsp_t magia_tile_ni_14_7_to_router_14_7_rsp; - -floo_req_t router_14_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_14_8_rsp; - -floo_req_t router_14_8_to_magia_tile_ni_14_8_req; -floo_rsp_t magia_tile_ni_14_8_to_router_14_8_rsp; - -floo_req_t router_14_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_14_9_rsp; - -floo_req_t router_14_9_to_magia_tile_ni_14_9_req; -floo_rsp_t magia_tile_ni_14_9_to_router_14_9_rsp; - -floo_req_t router_14_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_14_10_rsp; - -floo_req_t router_14_10_to_magia_tile_ni_14_10_req; -floo_rsp_t magia_tile_ni_14_10_to_router_14_10_rsp; - -floo_req_t router_14_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_14_11_rsp; - -floo_req_t router_14_11_to_magia_tile_ni_14_11_req; -floo_rsp_t magia_tile_ni_14_11_to_router_14_11_rsp; - -floo_req_t router_14_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_14_12_rsp; - -floo_req_t router_14_12_to_magia_tile_ni_14_12_req; -floo_rsp_t magia_tile_ni_14_12_to_router_14_12_rsp; - -floo_req_t router_14_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_14_13_rsp; - -floo_req_t router_14_13_to_magia_tile_ni_14_13_req; -floo_rsp_t magia_tile_ni_14_13_to_router_14_13_rsp; - -floo_req_t router_14_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_14_14_rsp; - -floo_req_t router_14_14_to_magia_tile_ni_14_14_req; -floo_rsp_t magia_tile_ni_14_14_to_router_14_14_rsp; - -floo_req_t router_14_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_14_15_rsp; - -floo_req_t router_14_15_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_14_15_rsp; - -floo_req_t router_14_15_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_14_15_rsp; - -floo_req_t router_14_15_to_magia_tile_ni_14_15_req; -floo_rsp_t magia_tile_ni_14_15_to_router_14_15_rsp; - -floo_req_t router_15_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_15_0_rsp; - -floo_req_t router_15_0_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_15_0_rsp; - -floo_req_t router_15_0_to_magia_tile_ni_15_0_req; -floo_rsp_t magia_tile_ni_15_0_to_router_15_0_rsp; - -floo_req_t router_15_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_15_1_rsp; - -floo_req_t router_15_1_to_router_15_0_req; -floo_rsp_t router_15_0_to_router_15_1_rsp; - -floo_req_t router_15_1_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_15_1_rsp; - -floo_req_t router_15_1_to_magia_tile_ni_15_1_req; -floo_rsp_t magia_tile_ni_15_1_to_router_15_1_rsp; - -floo_req_t router_15_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_15_2_rsp; - -floo_req_t router_15_2_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_15_2_rsp; - -floo_req_t router_15_2_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_15_2_rsp; - -floo_req_t router_15_2_to_magia_tile_ni_15_2_req; -floo_rsp_t magia_tile_ni_15_2_to_router_15_2_rsp; - -floo_req_t router_15_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_15_3_rsp; - -floo_req_t router_15_3_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_15_3_rsp; - -floo_req_t router_15_3_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_15_3_rsp; - -floo_req_t router_15_3_to_magia_tile_ni_15_3_req; -floo_rsp_t magia_tile_ni_15_3_to_router_15_3_rsp; - -floo_req_t router_15_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_15_4_rsp; - -floo_req_t router_15_4_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_15_4_rsp; - -floo_req_t router_15_4_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_15_4_rsp; - -floo_req_t router_15_4_to_magia_tile_ni_15_4_req; -floo_rsp_t magia_tile_ni_15_4_to_router_15_4_rsp; - -floo_req_t router_15_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_15_5_rsp; - -floo_req_t router_15_5_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_15_5_rsp; - -floo_req_t router_15_5_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_15_5_rsp; - -floo_req_t router_15_5_to_magia_tile_ni_15_5_req; -floo_rsp_t magia_tile_ni_15_5_to_router_15_5_rsp; - -floo_req_t router_15_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_15_6_rsp; - -floo_req_t router_15_6_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_15_6_rsp; - -floo_req_t router_15_6_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_15_6_rsp; - -floo_req_t router_15_6_to_magia_tile_ni_15_6_req; -floo_rsp_t magia_tile_ni_15_6_to_router_15_6_rsp; - -floo_req_t router_15_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_15_7_rsp; - -floo_req_t router_15_7_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_15_7_rsp; - -floo_req_t router_15_7_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_15_7_rsp; - -floo_req_t router_15_7_to_magia_tile_ni_15_7_req; -floo_rsp_t magia_tile_ni_15_7_to_router_15_7_rsp; - -floo_req_t router_15_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_15_8_rsp; - -floo_req_t router_15_8_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_15_8_rsp; - -floo_req_t router_15_8_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_15_8_rsp; - -floo_req_t router_15_8_to_magia_tile_ni_15_8_req; -floo_rsp_t magia_tile_ni_15_8_to_router_15_8_rsp; - -floo_req_t router_15_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_15_9_rsp; - -floo_req_t router_15_9_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_15_9_rsp; - -floo_req_t router_15_9_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_15_9_rsp; - -floo_req_t router_15_9_to_magia_tile_ni_15_9_req; -floo_rsp_t magia_tile_ni_15_9_to_router_15_9_rsp; - -floo_req_t router_15_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_15_10_rsp; - -floo_req_t router_15_10_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_15_10_rsp; - -floo_req_t router_15_10_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_15_10_rsp; - -floo_req_t router_15_10_to_magia_tile_ni_15_10_req; -floo_rsp_t magia_tile_ni_15_10_to_router_15_10_rsp; - -floo_req_t router_15_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_15_11_rsp; - -floo_req_t router_15_11_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_15_11_rsp; - -floo_req_t router_15_11_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_15_11_rsp; - -floo_req_t router_15_11_to_magia_tile_ni_15_11_req; -floo_rsp_t magia_tile_ni_15_11_to_router_15_11_rsp; - -floo_req_t router_15_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_15_12_rsp; - -floo_req_t router_15_12_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_15_12_rsp; - -floo_req_t router_15_12_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_15_12_rsp; - -floo_req_t router_15_12_to_magia_tile_ni_15_12_req; -floo_rsp_t magia_tile_ni_15_12_to_router_15_12_rsp; - -floo_req_t router_15_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_15_13_rsp; - -floo_req_t router_15_13_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_15_13_rsp; - -floo_req_t router_15_13_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_15_13_rsp; - -floo_req_t router_15_13_to_magia_tile_ni_15_13_req; -floo_rsp_t magia_tile_ni_15_13_to_router_15_13_rsp; - -floo_req_t router_15_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_15_14_rsp; - -floo_req_t router_15_14_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_15_14_rsp; - -floo_req_t router_15_14_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_15_14_rsp; - -floo_req_t router_15_14_to_magia_tile_ni_15_14_req; -floo_rsp_t magia_tile_ni_15_14_to_router_15_14_rsp; - -floo_req_t router_15_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_15_15_rsp; - -floo_req_t router_15_15_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_15_15_rsp; - -floo_req_t router_15_15_to_magia_tile_ni_15_15_req; -floo_rsp_t magia_tile_ni_15_15_to_router_15_15_rsp; - -floo_req_t magia_tile_ni_0_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_magia_tile_ni_0_0_rsp; - -floo_req_t magia_tile_ni_0_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_magia_tile_ni_0_1_rsp; - -floo_req_t magia_tile_ni_0_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_magia_tile_ni_0_2_rsp; - -floo_req_t magia_tile_ni_0_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_magia_tile_ni_0_3_rsp; - -floo_req_t magia_tile_ni_0_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_magia_tile_ni_0_4_rsp; - -floo_req_t magia_tile_ni_0_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_magia_tile_ni_0_5_rsp; - -floo_req_t magia_tile_ni_0_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_magia_tile_ni_0_6_rsp; - -floo_req_t magia_tile_ni_0_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_magia_tile_ni_0_7_rsp; - -floo_req_t magia_tile_ni_0_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_magia_tile_ni_0_8_rsp; - -floo_req_t magia_tile_ni_0_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_magia_tile_ni_0_9_rsp; - -floo_req_t magia_tile_ni_0_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_magia_tile_ni_0_10_rsp; - -floo_req_t magia_tile_ni_0_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_magia_tile_ni_0_11_rsp; - -floo_req_t magia_tile_ni_0_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_magia_tile_ni_0_12_rsp; - -floo_req_t magia_tile_ni_0_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_magia_tile_ni_0_13_rsp; - -floo_req_t magia_tile_ni_0_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_magia_tile_ni_0_14_rsp; - -floo_req_t magia_tile_ni_0_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_magia_tile_ni_0_15_rsp; - -floo_req_t magia_tile_ni_1_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_magia_tile_ni_1_0_rsp; - -floo_req_t magia_tile_ni_1_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_magia_tile_ni_1_1_rsp; - -floo_req_t magia_tile_ni_1_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_magia_tile_ni_1_2_rsp; - -floo_req_t magia_tile_ni_1_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_magia_tile_ni_1_3_rsp; - -floo_req_t magia_tile_ni_1_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_magia_tile_ni_1_4_rsp; - -floo_req_t magia_tile_ni_1_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_magia_tile_ni_1_5_rsp; - -floo_req_t magia_tile_ni_1_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_magia_tile_ni_1_6_rsp; - -floo_req_t magia_tile_ni_1_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_magia_tile_ni_1_7_rsp; - -floo_req_t magia_tile_ni_1_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_magia_tile_ni_1_8_rsp; - -floo_req_t magia_tile_ni_1_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_magia_tile_ni_1_9_rsp; - -floo_req_t magia_tile_ni_1_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_magia_tile_ni_1_10_rsp; - -floo_req_t magia_tile_ni_1_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_magia_tile_ni_1_11_rsp; - -floo_req_t magia_tile_ni_1_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_magia_tile_ni_1_12_rsp; - -floo_req_t magia_tile_ni_1_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_magia_tile_ni_1_13_rsp; - -floo_req_t magia_tile_ni_1_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_magia_tile_ni_1_14_rsp; - -floo_req_t magia_tile_ni_1_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_magia_tile_ni_1_15_rsp; - -floo_req_t magia_tile_ni_2_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_magia_tile_ni_2_0_rsp; - -floo_req_t magia_tile_ni_2_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_magia_tile_ni_2_1_rsp; - -floo_req_t magia_tile_ni_2_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_magia_tile_ni_2_2_rsp; - -floo_req_t magia_tile_ni_2_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_magia_tile_ni_2_3_rsp; - -floo_req_t magia_tile_ni_2_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_magia_tile_ni_2_4_rsp; - -floo_req_t magia_tile_ni_2_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_magia_tile_ni_2_5_rsp; - -floo_req_t magia_tile_ni_2_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_magia_tile_ni_2_6_rsp; - -floo_req_t magia_tile_ni_2_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_magia_tile_ni_2_7_rsp; - -floo_req_t magia_tile_ni_2_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_magia_tile_ni_2_8_rsp; - -floo_req_t magia_tile_ni_2_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_magia_tile_ni_2_9_rsp; - -floo_req_t magia_tile_ni_2_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_magia_tile_ni_2_10_rsp; - -floo_req_t magia_tile_ni_2_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_magia_tile_ni_2_11_rsp; - -floo_req_t magia_tile_ni_2_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_magia_tile_ni_2_12_rsp; - -floo_req_t magia_tile_ni_2_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_magia_tile_ni_2_13_rsp; - -floo_req_t magia_tile_ni_2_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_magia_tile_ni_2_14_rsp; - -floo_req_t magia_tile_ni_2_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_magia_tile_ni_2_15_rsp; - -floo_req_t magia_tile_ni_3_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_magia_tile_ni_3_0_rsp; - -floo_req_t magia_tile_ni_3_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_magia_tile_ni_3_1_rsp; - -floo_req_t magia_tile_ni_3_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_magia_tile_ni_3_2_rsp; - -floo_req_t magia_tile_ni_3_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_magia_tile_ni_3_3_rsp; - -floo_req_t magia_tile_ni_3_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_magia_tile_ni_3_4_rsp; - -floo_req_t magia_tile_ni_3_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_magia_tile_ni_3_5_rsp; - -floo_req_t magia_tile_ni_3_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_magia_tile_ni_3_6_rsp; - -floo_req_t magia_tile_ni_3_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_magia_tile_ni_3_7_rsp; - -floo_req_t magia_tile_ni_3_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_magia_tile_ni_3_8_rsp; - -floo_req_t magia_tile_ni_3_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_magia_tile_ni_3_9_rsp; - -floo_req_t magia_tile_ni_3_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_magia_tile_ni_3_10_rsp; - -floo_req_t magia_tile_ni_3_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_magia_tile_ni_3_11_rsp; - -floo_req_t magia_tile_ni_3_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_magia_tile_ni_3_12_rsp; - -floo_req_t magia_tile_ni_3_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_magia_tile_ni_3_13_rsp; - -floo_req_t magia_tile_ni_3_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_magia_tile_ni_3_14_rsp; - -floo_req_t magia_tile_ni_3_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_magia_tile_ni_3_15_rsp; - -floo_req_t magia_tile_ni_4_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_magia_tile_ni_4_0_rsp; - -floo_req_t magia_tile_ni_4_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_magia_tile_ni_4_1_rsp; - -floo_req_t magia_tile_ni_4_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_magia_tile_ni_4_2_rsp; - -floo_req_t magia_tile_ni_4_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_magia_tile_ni_4_3_rsp; - -floo_req_t magia_tile_ni_4_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_magia_tile_ni_4_4_rsp; - -floo_req_t magia_tile_ni_4_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_magia_tile_ni_4_5_rsp; - -floo_req_t magia_tile_ni_4_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_magia_tile_ni_4_6_rsp; - -floo_req_t magia_tile_ni_4_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_magia_tile_ni_4_7_rsp; - -floo_req_t magia_tile_ni_4_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_magia_tile_ni_4_8_rsp; - -floo_req_t magia_tile_ni_4_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_magia_tile_ni_4_9_rsp; - -floo_req_t magia_tile_ni_4_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_magia_tile_ni_4_10_rsp; - -floo_req_t magia_tile_ni_4_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_magia_tile_ni_4_11_rsp; - -floo_req_t magia_tile_ni_4_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_magia_tile_ni_4_12_rsp; - -floo_req_t magia_tile_ni_4_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_magia_tile_ni_4_13_rsp; - -floo_req_t magia_tile_ni_4_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_magia_tile_ni_4_14_rsp; - -floo_req_t magia_tile_ni_4_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_magia_tile_ni_4_15_rsp; - -floo_req_t magia_tile_ni_5_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_magia_tile_ni_5_0_rsp; - -floo_req_t magia_tile_ni_5_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_magia_tile_ni_5_1_rsp; - -floo_req_t magia_tile_ni_5_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_magia_tile_ni_5_2_rsp; - -floo_req_t magia_tile_ni_5_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_magia_tile_ni_5_3_rsp; - -floo_req_t magia_tile_ni_5_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_magia_tile_ni_5_4_rsp; - -floo_req_t magia_tile_ni_5_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_magia_tile_ni_5_5_rsp; - -floo_req_t magia_tile_ni_5_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_magia_tile_ni_5_6_rsp; - -floo_req_t magia_tile_ni_5_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_magia_tile_ni_5_7_rsp; - -floo_req_t magia_tile_ni_5_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_magia_tile_ni_5_8_rsp; - -floo_req_t magia_tile_ni_5_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_magia_tile_ni_5_9_rsp; - -floo_req_t magia_tile_ni_5_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_magia_tile_ni_5_10_rsp; - -floo_req_t magia_tile_ni_5_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_magia_tile_ni_5_11_rsp; - -floo_req_t magia_tile_ni_5_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_magia_tile_ni_5_12_rsp; - -floo_req_t magia_tile_ni_5_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_magia_tile_ni_5_13_rsp; - -floo_req_t magia_tile_ni_5_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_magia_tile_ni_5_14_rsp; - -floo_req_t magia_tile_ni_5_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_magia_tile_ni_5_15_rsp; - -floo_req_t magia_tile_ni_6_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_magia_tile_ni_6_0_rsp; - -floo_req_t magia_tile_ni_6_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_magia_tile_ni_6_1_rsp; - -floo_req_t magia_tile_ni_6_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_magia_tile_ni_6_2_rsp; - -floo_req_t magia_tile_ni_6_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_magia_tile_ni_6_3_rsp; - -floo_req_t magia_tile_ni_6_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_magia_tile_ni_6_4_rsp; - -floo_req_t magia_tile_ni_6_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_magia_tile_ni_6_5_rsp; - -floo_req_t magia_tile_ni_6_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_magia_tile_ni_6_6_rsp; - -floo_req_t magia_tile_ni_6_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_magia_tile_ni_6_7_rsp; - -floo_req_t magia_tile_ni_6_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_magia_tile_ni_6_8_rsp; - -floo_req_t magia_tile_ni_6_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_magia_tile_ni_6_9_rsp; - -floo_req_t magia_tile_ni_6_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_magia_tile_ni_6_10_rsp; - -floo_req_t magia_tile_ni_6_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_magia_tile_ni_6_11_rsp; - -floo_req_t magia_tile_ni_6_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_magia_tile_ni_6_12_rsp; - -floo_req_t magia_tile_ni_6_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_magia_tile_ni_6_13_rsp; - -floo_req_t magia_tile_ni_6_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_magia_tile_ni_6_14_rsp; - -floo_req_t magia_tile_ni_6_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_magia_tile_ni_6_15_rsp; - -floo_req_t magia_tile_ni_7_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_magia_tile_ni_7_0_rsp; - -floo_req_t magia_tile_ni_7_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_magia_tile_ni_7_1_rsp; - -floo_req_t magia_tile_ni_7_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_magia_tile_ni_7_2_rsp; - -floo_req_t magia_tile_ni_7_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_magia_tile_ni_7_3_rsp; - -floo_req_t magia_tile_ni_7_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_magia_tile_ni_7_4_rsp; - -floo_req_t magia_tile_ni_7_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_magia_tile_ni_7_5_rsp; - -floo_req_t magia_tile_ni_7_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_magia_tile_ni_7_6_rsp; - -floo_req_t magia_tile_ni_7_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_magia_tile_ni_7_7_rsp; - -floo_req_t magia_tile_ni_7_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_magia_tile_ni_7_8_rsp; - -floo_req_t magia_tile_ni_7_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_magia_tile_ni_7_9_rsp; - -floo_req_t magia_tile_ni_7_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_magia_tile_ni_7_10_rsp; - -floo_req_t magia_tile_ni_7_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_magia_tile_ni_7_11_rsp; - -floo_req_t magia_tile_ni_7_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_magia_tile_ni_7_12_rsp; - -floo_req_t magia_tile_ni_7_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_magia_tile_ni_7_13_rsp; - -floo_req_t magia_tile_ni_7_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_magia_tile_ni_7_14_rsp; - -floo_req_t magia_tile_ni_7_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_magia_tile_ni_7_15_rsp; - -floo_req_t magia_tile_ni_8_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_magia_tile_ni_8_0_rsp; - -floo_req_t magia_tile_ni_8_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_magia_tile_ni_8_1_rsp; - -floo_req_t magia_tile_ni_8_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_magia_tile_ni_8_2_rsp; - -floo_req_t magia_tile_ni_8_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_magia_tile_ni_8_3_rsp; - -floo_req_t magia_tile_ni_8_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_magia_tile_ni_8_4_rsp; - -floo_req_t magia_tile_ni_8_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_magia_tile_ni_8_5_rsp; - -floo_req_t magia_tile_ni_8_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_magia_tile_ni_8_6_rsp; - -floo_req_t magia_tile_ni_8_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_magia_tile_ni_8_7_rsp; - -floo_req_t magia_tile_ni_8_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_magia_tile_ni_8_8_rsp; - -floo_req_t magia_tile_ni_8_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_magia_tile_ni_8_9_rsp; - -floo_req_t magia_tile_ni_8_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_magia_tile_ni_8_10_rsp; - -floo_req_t magia_tile_ni_8_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_magia_tile_ni_8_11_rsp; - -floo_req_t magia_tile_ni_8_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_magia_tile_ni_8_12_rsp; - -floo_req_t magia_tile_ni_8_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_magia_tile_ni_8_13_rsp; - -floo_req_t magia_tile_ni_8_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_magia_tile_ni_8_14_rsp; - -floo_req_t magia_tile_ni_8_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_magia_tile_ni_8_15_rsp; - -floo_req_t magia_tile_ni_9_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_magia_tile_ni_9_0_rsp; - -floo_req_t magia_tile_ni_9_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_magia_tile_ni_9_1_rsp; - -floo_req_t magia_tile_ni_9_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_magia_tile_ni_9_2_rsp; - -floo_req_t magia_tile_ni_9_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_magia_tile_ni_9_3_rsp; - -floo_req_t magia_tile_ni_9_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_magia_tile_ni_9_4_rsp; - -floo_req_t magia_tile_ni_9_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_magia_tile_ni_9_5_rsp; - -floo_req_t magia_tile_ni_9_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_magia_tile_ni_9_6_rsp; - -floo_req_t magia_tile_ni_9_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_magia_tile_ni_9_7_rsp; - -floo_req_t magia_tile_ni_9_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_magia_tile_ni_9_8_rsp; - -floo_req_t magia_tile_ni_9_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_magia_tile_ni_9_9_rsp; - -floo_req_t magia_tile_ni_9_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_magia_tile_ni_9_10_rsp; - -floo_req_t magia_tile_ni_9_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_magia_tile_ni_9_11_rsp; - -floo_req_t magia_tile_ni_9_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_magia_tile_ni_9_12_rsp; - -floo_req_t magia_tile_ni_9_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_magia_tile_ni_9_13_rsp; - -floo_req_t magia_tile_ni_9_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_magia_tile_ni_9_14_rsp; - -floo_req_t magia_tile_ni_9_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_magia_tile_ni_9_15_rsp; - -floo_req_t magia_tile_ni_10_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_magia_tile_ni_10_0_rsp; - -floo_req_t magia_tile_ni_10_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_magia_tile_ni_10_1_rsp; - -floo_req_t magia_tile_ni_10_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_magia_tile_ni_10_2_rsp; - -floo_req_t magia_tile_ni_10_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_magia_tile_ni_10_3_rsp; - -floo_req_t magia_tile_ni_10_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_magia_tile_ni_10_4_rsp; - -floo_req_t magia_tile_ni_10_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_magia_tile_ni_10_5_rsp; - -floo_req_t magia_tile_ni_10_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_magia_tile_ni_10_6_rsp; - -floo_req_t magia_tile_ni_10_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_magia_tile_ni_10_7_rsp; - -floo_req_t magia_tile_ni_10_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_magia_tile_ni_10_8_rsp; - -floo_req_t magia_tile_ni_10_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_magia_tile_ni_10_9_rsp; - -floo_req_t magia_tile_ni_10_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_magia_tile_ni_10_10_rsp; - -floo_req_t magia_tile_ni_10_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_magia_tile_ni_10_11_rsp; - -floo_req_t magia_tile_ni_10_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_magia_tile_ni_10_12_rsp; - -floo_req_t magia_tile_ni_10_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_magia_tile_ni_10_13_rsp; - -floo_req_t magia_tile_ni_10_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_magia_tile_ni_10_14_rsp; - -floo_req_t magia_tile_ni_10_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_magia_tile_ni_10_15_rsp; - -floo_req_t magia_tile_ni_11_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_magia_tile_ni_11_0_rsp; - -floo_req_t magia_tile_ni_11_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_magia_tile_ni_11_1_rsp; - -floo_req_t magia_tile_ni_11_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_magia_tile_ni_11_2_rsp; - -floo_req_t magia_tile_ni_11_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_magia_tile_ni_11_3_rsp; - -floo_req_t magia_tile_ni_11_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_magia_tile_ni_11_4_rsp; - -floo_req_t magia_tile_ni_11_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_magia_tile_ni_11_5_rsp; - -floo_req_t magia_tile_ni_11_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_magia_tile_ni_11_6_rsp; - -floo_req_t magia_tile_ni_11_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_magia_tile_ni_11_7_rsp; - -floo_req_t magia_tile_ni_11_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_magia_tile_ni_11_8_rsp; - -floo_req_t magia_tile_ni_11_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_magia_tile_ni_11_9_rsp; - -floo_req_t magia_tile_ni_11_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_magia_tile_ni_11_10_rsp; - -floo_req_t magia_tile_ni_11_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_magia_tile_ni_11_11_rsp; - -floo_req_t magia_tile_ni_11_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_magia_tile_ni_11_12_rsp; - -floo_req_t magia_tile_ni_11_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_magia_tile_ni_11_13_rsp; - -floo_req_t magia_tile_ni_11_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_magia_tile_ni_11_14_rsp; - -floo_req_t magia_tile_ni_11_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_magia_tile_ni_11_15_rsp; - -floo_req_t magia_tile_ni_12_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_magia_tile_ni_12_0_rsp; - -floo_req_t magia_tile_ni_12_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_magia_tile_ni_12_1_rsp; - -floo_req_t magia_tile_ni_12_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_magia_tile_ni_12_2_rsp; - -floo_req_t magia_tile_ni_12_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_magia_tile_ni_12_3_rsp; - -floo_req_t magia_tile_ni_12_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_magia_tile_ni_12_4_rsp; - -floo_req_t magia_tile_ni_12_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_magia_tile_ni_12_5_rsp; - -floo_req_t magia_tile_ni_12_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_magia_tile_ni_12_6_rsp; - -floo_req_t magia_tile_ni_12_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_magia_tile_ni_12_7_rsp; - -floo_req_t magia_tile_ni_12_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_magia_tile_ni_12_8_rsp; - -floo_req_t magia_tile_ni_12_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_magia_tile_ni_12_9_rsp; - -floo_req_t magia_tile_ni_12_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_magia_tile_ni_12_10_rsp; - -floo_req_t magia_tile_ni_12_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_magia_tile_ni_12_11_rsp; - -floo_req_t magia_tile_ni_12_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_magia_tile_ni_12_12_rsp; - -floo_req_t magia_tile_ni_12_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_magia_tile_ni_12_13_rsp; - -floo_req_t magia_tile_ni_12_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_magia_tile_ni_12_14_rsp; - -floo_req_t magia_tile_ni_12_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_magia_tile_ni_12_15_rsp; - -floo_req_t magia_tile_ni_13_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_magia_tile_ni_13_0_rsp; - -floo_req_t magia_tile_ni_13_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_magia_tile_ni_13_1_rsp; - -floo_req_t magia_tile_ni_13_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_magia_tile_ni_13_2_rsp; - -floo_req_t magia_tile_ni_13_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_magia_tile_ni_13_3_rsp; - -floo_req_t magia_tile_ni_13_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_magia_tile_ni_13_4_rsp; - -floo_req_t magia_tile_ni_13_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_magia_tile_ni_13_5_rsp; - -floo_req_t magia_tile_ni_13_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_magia_tile_ni_13_6_rsp; - -floo_req_t magia_tile_ni_13_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_magia_tile_ni_13_7_rsp; - -floo_req_t magia_tile_ni_13_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_magia_tile_ni_13_8_rsp; - -floo_req_t magia_tile_ni_13_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_magia_tile_ni_13_9_rsp; - -floo_req_t magia_tile_ni_13_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_magia_tile_ni_13_10_rsp; - -floo_req_t magia_tile_ni_13_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_magia_tile_ni_13_11_rsp; - -floo_req_t magia_tile_ni_13_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_magia_tile_ni_13_12_rsp; - -floo_req_t magia_tile_ni_13_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_magia_tile_ni_13_13_rsp; - -floo_req_t magia_tile_ni_13_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_magia_tile_ni_13_14_rsp; - -floo_req_t magia_tile_ni_13_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_magia_tile_ni_13_15_rsp; - -floo_req_t magia_tile_ni_14_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_magia_tile_ni_14_0_rsp; - -floo_req_t magia_tile_ni_14_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_magia_tile_ni_14_1_rsp; - -floo_req_t magia_tile_ni_14_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_magia_tile_ni_14_2_rsp; - -floo_req_t magia_tile_ni_14_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_magia_tile_ni_14_3_rsp; - -floo_req_t magia_tile_ni_14_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_magia_tile_ni_14_4_rsp; - -floo_req_t magia_tile_ni_14_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_magia_tile_ni_14_5_rsp; - -floo_req_t magia_tile_ni_14_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_magia_tile_ni_14_6_rsp; - -floo_req_t magia_tile_ni_14_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_magia_tile_ni_14_7_rsp; - -floo_req_t magia_tile_ni_14_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_magia_tile_ni_14_8_rsp; - -floo_req_t magia_tile_ni_14_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_magia_tile_ni_14_9_rsp; - -floo_req_t magia_tile_ni_14_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_magia_tile_ni_14_10_rsp; - -floo_req_t magia_tile_ni_14_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_magia_tile_ni_14_11_rsp; - -floo_req_t magia_tile_ni_14_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_magia_tile_ni_14_12_rsp; - -floo_req_t magia_tile_ni_14_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_magia_tile_ni_14_13_rsp; - -floo_req_t magia_tile_ni_14_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_magia_tile_ni_14_14_rsp; - -floo_req_t magia_tile_ni_14_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_magia_tile_ni_14_15_rsp; - -floo_req_t magia_tile_ni_15_0_to_router_15_0_req; -floo_rsp_t router_15_0_to_magia_tile_ni_15_0_rsp; - -floo_req_t magia_tile_ni_15_1_to_router_15_1_req; -floo_rsp_t router_15_1_to_magia_tile_ni_15_1_rsp; - -floo_req_t magia_tile_ni_15_2_to_router_15_2_req; -floo_rsp_t router_15_2_to_magia_tile_ni_15_2_rsp; - -floo_req_t magia_tile_ni_15_3_to_router_15_3_req; -floo_rsp_t router_15_3_to_magia_tile_ni_15_3_rsp; - -floo_req_t magia_tile_ni_15_4_to_router_15_4_req; -floo_rsp_t router_15_4_to_magia_tile_ni_15_4_rsp; - -floo_req_t magia_tile_ni_15_5_to_router_15_5_req; -floo_rsp_t router_15_5_to_magia_tile_ni_15_5_rsp; - -floo_req_t magia_tile_ni_15_6_to_router_15_6_req; -floo_rsp_t router_15_6_to_magia_tile_ni_15_6_rsp; - -floo_req_t magia_tile_ni_15_7_to_router_15_7_req; -floo_rsp_t router_15_7_to_magia_tile_ni_15_7_rsp; - -floo_req_t magia_tile_ni_15_8_to_router_15_8_req; -floo_rsp_t router_15_8_to_magia_tile_ni_15_8_rsp; - -floo_req_t magia_tile_ni_15_9_to_router_15_9_req; -floo_rsp_t router_15_9_to_magia_tile_ni_15_9_rsp; - -floo_req_t magia_tile_ni_15_10_to_router_15_10_req; -floo_rsp_t router_15_10_to_magia_tile_ni_15_10_rsp; - -floo_req_t magia_tile_ni_15_11_to_router_15_11_req; -floo_rsp_t router_15_11_to_magia_tile_ni_15_11_rsp; - -floo_req_t magia_tile_ni_15_12_to_router_15_12_req; -floo_rsp_t router_15_12_to_magia_tile_ni_15_12_rsp; - -floo_req_t magia_tile_ni_15_13_to_router_15_13_req; -floo_rsp_t router_15_13_to_magia_tile_ni_15_13_rsp; - -floo_req_t magia_tile_ni_15_14_to_router_15_14_req; -floo_rsp_t router_15_14_to_magia_tile_ni_15_14_rsp; - -floo_req_t magia_tile_ni_15_15_to_router_15_15_req; -floo_rsp_t router_15_15_to_magia_tile_ni_15_15_rsp; - -floo_req_t L2_ni_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_L2_ni_0_rsp; - -floo_req_t L2_ni_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_L2_ni_1_rsp; - -floo_req_t L2_ni_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_L2_ni_2_rsp; - -floo_req_t L2_ni_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_L2_ni_3_rsp; - -floo_req_t L2_ni_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_L2_ni_4_rsp; - -floo_req_t L2_ni_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_L2_ni_5_rsp; - -floo_req_t L2_ni_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_L2_ni_6_rsp; - -floo_req_t L2_ni_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_L2_ni_7_rsp; - -floo_req_t L2_ni_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_L2_ni_8_rsp; - -floo_req_t L2_ni_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_L2_ni_9_rsp; - -floo_req_t L2_ni_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_L2_ni_10_rsp; - -floo_req_t L2_ni_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_L2_ni_11_rsp; - -floo_req_t L2_ni_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_L2_ni_12_rsp; - -floo_req_t L2_ni_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_L2_ni_13_rsp; - -floo_req_t L2_ni_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_L2_ni_14_rsp; - -floo_req_t L2_ni_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_L2_ni_15_rsp; - - - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][0] ), - .id_i ( '{x: 1, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_magia_tile_ni_0_0_rsp ), - .floo_req_i ( router_0_0_to_magia_tile_ni_0_0_req ), - .floo_rsp_o ( magia_tile_ni_0_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][1] ), - .id_i ( '{x: 1, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_magia_tile_ni_0_1_rsp ), - .floo_req_i ( router_0_1_to_magia_tile_ni_0_1_req ), - .floo_rsp_o ( magia_tile_ni_0_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][2] ), - .id_i ( '{x: 1, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_magia_tile_ni_0_2_rsp ), - .floo_req_i ( router_0_2_to_magia_tile_ni_0_2_req ), - .floo_rsp_o ( magia_tile_ni_0_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][3] ), - .id_i ( '{x: 1, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_magia_tile_ni_0_3_rsp ), - .floo_req_i ( router_0_3_to_magia_tile_ni_0_3_req ), - .floo_rsp_o ( magia_tile_ni_0_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][4] ), - .id_i ( '{x: 1, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_magia_tile_ni_0_4_rsp ), - .floo_req_i ( router_0_4_to_magia_tile_ni_0_4_req ), - .floo_rsp_o ( magia_tile_ni_0_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][5] ), - .id_i ( '{x: 1, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_magia_tile_ni_0_5_rsp ), - .floo_req_i ( router_0_5_to_magia_tile_ni_0_5_req ), - .floo_rsp_o ( magia_tile_ni_0_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][6] ), - .id_i ( '{x: 1, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_magia_tile_ni_0_6_rsp ), - .floo_req_i ( router_0_6_to_magia_tile_ni_0_6_req ), - .floo_rsp_o ( magia_tile_ni_0_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][7] ), - .id_i ( '{x: 1, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_magia_tile_ni_0_7_rsp ), - .floo_req_i ( router_0_7_to_magia_tile_ni_0_7_req ), - .floo_rsp_o ( magia_tile_ni_0_7_to_router_0_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][8] ), - .id_i ( '{x: 1, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_8_to_router_0_8_req ), - .floo_rsp_i ( router_0_8_to_magia_tile_ni_0_8_rsp ), - .floo_req_i ( router_0_8_to_magia_tile_ni_0_8_req ), - .floo_rsp_o ( magia_tile_ni_0_8_to_router_0_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][9] ), - .id_i ( '{x: 1, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_9_to_router_0_9_req ), - .floo_rsp_i ( router_0_9_to_magia_tile_ni_0_9_rsp ), - .floo_req_i ( router_0_9_to_magia_tile_ni_0_9_req ), - .floo_rsp_o ( magia_tile_ni_0_9_to_router_0_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][10] ), - .id_i ( '{x: 1, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_10_to_router_0_10_req ), - .floo_rsp_i ( router_0_10_to_magia_tile_ni_0_10_rsp ), - .floo_req_i ( router_0_10_to_magia_tile_ni_0_10_req ), - .floo_rsp_o ( magia_tile_ni_0_10_to_router_0_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][11] ), - .id_i ( '{x: 1, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_11_to_router_0_11_req ), - .floo_rsp_i ( router_0_11_to_magia_tile_ni_0_11_rsp ), - .floo_req_i ( router_0_11_to_magia_tile_ni_0_11_req ), - .floo_rsp_o ( magia_tile_ni_0_11_to_router_0_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][12] ), - .id_i ( '{x: 1, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_12_to_router_0_12_req ), - .floo_rsp_i ( router_0_12_to_magia_tile_ni_0_12_rsp ), - .floo_req_i ( router_0_12_to_magia_tile_ni_0_12_req ), - .floo_rsp_o ( magia_tile_ni_0_12_to_router_0_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][13] ), - .id_i ( '{x: 1, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_13_to_router_0_13_req ), - .floo_rsp_i ( router_0_13_to_magia_tile_ni_0_13_rsp ), - .floo_req_i ( router_0_13_to_magia_tile_ni_0_13_req ), - .floo_rsp_o ( magia_tile_ni_0_13_to_router_0_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][14] ), - .id_i ( '{x: 1, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_14_to_router_0_14_req ), - .floo_rsp_i ( router_0_14_to_magia_tile_ni_0_14_rsp ), - .floo_req_i ( router_0_14_to_magia_tile_ni_0_14_req ), - .floo_rsp_o ( magia_tile_ni_0_14_to_router_0_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][15] ), - .id_i ( '{x: 1, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_15_to_router_0_15_req ), - .floo_rsp_i ( router_0_15_to_magia_tile_ni_0_15_rsp ), - .floo_req_i ( router_0_15_to_magia_tile_ni_0_15_req ), - .floo_rsp_o ( magia_tile_ni_0_15_to_router_0_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][0] ), - .id_i ( '{x: 2, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_0_to_router_1_0_req ), - .floo_rsp_i ( router_1_0_to_magia_tile_ni_1_0_rsp ), - .floo_req_i ( router_1_0_to_magia_tile_ni_1_0_req ), - .floo_rsp_o ( magia_tile_ni_1_0_to_router_1_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][1] ), - .id_i ( '{x: 2, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_1_to_router_1_1_req ), - .floo_rsp_i ( router_1_1_to_magia_tile_ni_1_1_rsp ), - .floo_req_i ( router_1_1_to_magia_tile_ni_1_1_req ), - .floo_rsp_o ( magia_tile_ni_1_1_to_router_1_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][2] ), - .id_i ( '{x: 2, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_2_to_router_1_2_req ), - .floo_rsp_i ( router_1_2_to_magia_tile_ni_1_2_rsp ), - .floo_req_i ( router_1_2_to_magia_tile_ni_1_2_req ), - .floo_rsp_o ( magia_tile_ni_1_2_to_router_1_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][3] ), - .id_i ( '{x: 2, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_3_to_router_1_3_req ), - .floo_rsp_i ( router_1_3_to_magia_tile_ni_1_3_rsp ), - .floo_req_i ( router_1_3_to_magia_tile_ni_1_3_req ), - .floo_rsp_o ( magia_tile_ni_1_3_to_router_1_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][4] ), - .id_i ( '{x: 2, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_4_to_router_1_4_req ), - .floo_rsp_i ( router_1_4_to_magia_tile_ni_1_4_rsp ), - .floo_req_i ( router_1_4_to_magia_tile_ni_1_4_req ), - .floo_rsp_o ( magia_tile_ni_1_4_to_router_1_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][5] ), - .id_i ( '{x: 2, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_5_to_router_1_5_req ), - .floo_rsp_i ( router_1_5_to_magia_tile_ni_1_5_rsp ), - .floo_req_i ( router_1_5_to_magia_tile_ni_1_5_req ), - .floo_rsp_o ( magia_tile_ni_1_5_to_router_1_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][6] ), - .id_i ( '{x: 2, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_6_to_router_1_6_req ), - .floo_rsp_i ( router_1_6_to_magia_tile_ni_1_6_rsp ), - .floo_req_i ( router_1_6_to_magia_tile_ni_1_6_req ), - .floo_rsp_o ( magia_tile_ni_1_6_to_router_1_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][7] ), - .id_i ( '{x: 2, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_7_to_router_1_7_req ), - .floo_rsp_i ( router_1_7_to_magia_tile_ni_1_7_rsp ), - .floo_req_i ( router_1_7_to_magia_tile_ni_1_7_req ), - .floo_rsp_o ( magia_tile_ni_1_7_to_router_1_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][8] ), - .id_i ( '{x: 2, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_8_to_router_1_8_req ), - .floo_rsp_i ( router_1_8_to_magia_tile_ni_1_8_rsp ), - .floo_req_i ( router_1_8_to_magia_tile_ni_1_8_req ), - .floo_rsp_o ( magia_tile_ni_1_8_to_router_1_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][9] ), - .id_i ( '{x: 2, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_9_to_router_1_9_req ), - .floo_rsp_i ( router_1_9_to_magia_tile_ni_1_9_rsp ), - .floo_req_i ( router_1_9_to_magia_tile_ni_1_9_req ), - .floo_rsp_o ( magia_tile_ni_1_9_to_router_1_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][10] ), - .id_i ( '{x: 2, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_10_to_router_1_10_req ), - .floo_rsp_i ( router_1_10_to_magia_tile_ni_1_10_rsp ), - .floo_req_i ( router_1_10_to_magia_tile_ni_1_10_req ), - .floo_rsp_o ( magia_tile_ni_1_10_to_router_1_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][11] ), - .id_i ( '{x: 2, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_11_to_router_1_11_req ), - .floo_rsp_i ( router_1_11_to_magia_tile_ni_1_11_rsp ), - .floo_req_i ( router_1_11_to_magia_tile_ni_1_11_req ), - .floo_rsp_o ( magia_tile_ni_1_11_to_router_1_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][12] ), - .id_i ( '{x: 2, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_12_to_router_1_12_req ), - .floo_rsp_i ( router_1_12_to_magia_tile_ni_1_12_rsp ), - .floo_req_i ( router_1_12_to_magia_tile_ni_1_12_req ), - .floo_rsp_o ( magia_tile_ni_1_12_to_router_1_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][13] ), - .id_i ( '{x: 2, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_13_to_router_1_13_req ), - .floo_rsp_i ( router_1_13_to_magia_tile_ni_1_13_rsp ), - .floo_req_i ( router_1_13_to_magia_tile_ni_1_13_req ), - .floo_rsp_o ( magia_tile_ni_1_13_to_router_1_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][14] ), - .id_i ( '{x: 2, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_14_to_router_1_14_req ), - .floo_rsp_i ( router_1_14_to_magia_tile_ni_1_14_rsp ), - .floo_req_i ( router_1_14_to_magia_tile_ni_1_14_req ), - .floo_rsp_o ( magia_tile_ni_1_14_to_router_1_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][15] ), - .id_i ( '{x: 2, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_15_to_router_1_15_req ), - .floo_rsp_i ( router_1_15_to_magia_tile_ni_1_15_rsp ), - .floo_req_i ( router_1_15_to_magia_tile_ni_1_15_req ), - .floo_rsp_o ( magia_tile_ni_1_15_to_router_1_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][0] ), - .id_i ( '{x: 3, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_0_to_router_2_0_req ), - .floo_rsp_i ( router_2_0_to_magia_tile_ni_2_0_rsp ), - .floo_req_i ( router_2_0_to_magia_tile_ni_2_0_req ), - .floo_rsp_o ( magia_tile_ni_2_0_to_router_2_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][1] ), - .id_i ( '{x: 3, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_1_to_router_2_1_req ), - .floo_rsp_i ( router_2_1_to_magia_tile_ni_2_1_rsp ), - .floo_req_i ( router_2_1_to_magia_tile_ni_2_1_req ), - .floo_rsp_o ( magia_tile_ni_2_1_to_router_2_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][2] ), - .id_i ( '{x: 3, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_2_to_router_2_2_req ), - .floo_rsp_i ( router_2_2_to_magia_tile_ni_2_2_rsp ), - .floo_req_i ( router_2_2_to_magia_tile_ni_2_2_req ), - .floo_rsp_o ( magia_tile_ni_2_2_to_router_2_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][3] ), - .id_i ( '{x: 3, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_3_to_router_2_3_req ), - .floo_rsp_i ( router_2_3_to_magia_tile_ni_2_3_rsp ), - .floo_req_i ( router_2_3_to_magia_tile_ni_2_3_req ), - .floo_rsp_o ( magia_tile_ni_2_3_to_router_2_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][4] ), - .id_i ( '{x: 3, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_4_to_router_2_4_req ), - .floo_rsp_i ( router_2_4_to_magia_tile_ni_2_4_rsp ), - .floo_req_i ( router_2_4_to_magia_tile_ni_2_4_req ), - .floo_rsp_o ( magia_tile_ni_2_4_to_router_2_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][5] ), - .id_i ( '{x: 3, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_5_to_router_2_5_req ), - .floo_rsp_i ( router_2_5_to_magia_tile_ni_2_5_rsp ), - .floo_req_i ( router_2_5_to_magia_tile_ni_2_5_req ), - .floo_rsp_o ( magia_tile_ni_2_5_to_router_2_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][6] ), - .id_i ( '{x: 3, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_6_to_router_2_6_req ), - .floo_rsp_i ( router_2_6_to_magia_tile_ni_2_6_rsp ), - .floo_req_i ( router_2_6_to_magia_tile_ni_2_6_req ), - .floo_rsp_o ( magia_tile_ni_2_6_to_router_2_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][7] ), - .id_i ( '{x: 3, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_7_to_router_2_7_req ), - .floo_rsp_i ( router_2_7_to_magia_tile_ni_2_7_rsp ), - .floo_req_i ( router_2_7_to_magia_tile_ni_2_7_req ), - .floo_rsp_o ( magia_tile_ni_2_7_to_router_2_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][8] ), - .id_i ( '{x: 3, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_8_to_router_2_8_req ), - .floo_rsp_i ( router_2_8_to_magia_tile_ni_2_8_rsp ), - .floo_req_i ( router_2_8_to_magia_tile_ni_2_8_req ), - .floo_rsp_o ( magia_tile_ni_2_8_to_router_2_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][9] ), - .id_i ( '{x: 3, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_9_to_router_2_9_req ), - .floo_rsp_i ( router_2_9_to_magia_tile_ni_2_9_rsp ), - .floo_req_i ( router_2_9_to_magia_tile_ni_2_9_req ), - .floo_rsp_o ( magia_tile_ni_2_9_to_router_2_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][10] ), - .id_i ( '{x: 3, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_10_to_router_2_10_req ), - .floo_rsp_i ( router_2_10_to_magia_tile_ni_2_10_rsp ), - .floo_req_i ( router_2_10_to_magia_tile_ni_2_10_req ), - .floo_rsp_o ( magia_tile_ni_2_10_to_router_2_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][11] ), - .id_i ( '{x: 3, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_11_to_router_2_11_req ), - .floo_rsp_i ( router_2_11_to_magia_tile_ni_2_11_rsp ), - .floo_req_i ( router_2_11_to_magia_tile_ni_2_11_req ), - .floo_rsp_o ( magia_tile_ni_2_11_to_router_2_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][12] ), - .id_i ( '{x: 3, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_12_to_router_2_12_req ), - .floo_rsp_i ( router_2_12_to_magia_tile_ni_2_12_rsp ), - .floo_req_i ( router_2_12_to_magia_tile_ni_2_12_req ), - .floo_rsp_o ( magia_tile_ni_2_12_to_router_2_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][13] ), - .id_i ( '{x: 3, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_13_to_router_2_13_req ), - .floo_rsp_i ( router_2_13_to_magia_tile_ni_2_13_rsp ), - .floo_req_i ( router_2_13_to_magia_tile_ni_2_13_req ), - .floo_rsp_o ( magia_tile_ni_2_13_to_router_2_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][14] ), - .id_i ( '{x: 3, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_14_to_router_2_14_req ), - .floo_rsp_i ( router_2_14_to_magia_tile_ni_2_14_rsp ), - .floo_req_i ( router_2_14_to_magia_tile_ni_2_14_req ), - .floo_rsp_o ( magia_tile_ni_2_14_to_router_2_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][15] ), - .id_i ( '{x: 3, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_15_to_router_2_15_req ), - .floo_rsp_i ( router_2_15_to_magia_tile_ni_2_15_rsp ), - .floo_req_i ( router_2_15_to_magia_tile_ni_2_15_req ), - .floo_rsp_o ( magia_tile_ni_2_15_to_router_2_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][0] ), - .id_i ( '{x: 4, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_0_to_router_3_0_req ), - .floo_rsp_i ( router_3_0_to_magia_tile_ni_3_0_rsp ), - .floo_req_i ( router_3_0_to_magia_tile_ni_3_0_req ), - .floo_rsp_o ( magia_tile_ni_3_0_to_router_3_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][1] ), - .id_i ( '{x: 4, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_1_to_router_3_1_req ), - .floo_rsp_i ( router_3_1_to_magia_tile_ni_3_1_rsp ), - .floo_req_i ( router_3_1_to_magia_tile_ni_3_1_req ), - .floo_rsp_o ( magia_tile_ni_3_1_to_router_3_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][2] ), - .id_i ( '{x: 4, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_2_to_router_3_2_req ), - .floo_rsp_i ( router_3_2_to_magia_tile_ni_3_2_rsp ), - .floo_req_i ( router_3_2_to_magia_tile_ni_3_2_req ), - .floo_rsp_o ( magia_tile_ni_3_2_to_router_3_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][3] ), - .id_i ( '{x: 4, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_3_to_router_3_3_req ), - .floo_rsp_i ( router_3_3_to_magia_tile_ni_3_3_rsp ), - .floo_req_i ( router_3_3_to_magia_tile_ni_3_3_req ), - .floo_rsp_o ( magia_tile_ni_3_3_to_router_3_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][4] ), - .id_i ( '{x: 4, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_4_to_router_3_4_req ), - .floo_rsp_i ( router_3_4_to_magia_tile_ni_3_4_rsp ), - .floo_req_i ( router_3_4_to_magia_tile_ni_3_4_req ), - .floo_rsp_o ( magia_tile_ni_3_4_to_router_3_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][5] ), - .id_i ( '{x: 4, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_5_to_router_3_5_req ), - .floo_rsp_i ( router_3_5_to_magia_tile_ni_3_5_rsp ), - .floo_req_i ( router_3_5_to_magia_tile_ni_3_5_req ), - .floo_rsp_o ( magia_tile_ni_3_5_to_router_3_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][6] ), - .id_i ( '{x: 4, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_6_to_router_3_6_req ), - .floo_rsp_i ( router_3_6_to_magia_tile_ni_3_6_rsp ), - .floo_req_i ( router_3_6_to_magia_tile_ni_3_6_req ), - .floo_rsp_o ( magia_tile_ni_3_6_to_router_3_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][7] ), - .id_i ( '{x: 4, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_7_to_router_3_7_req ), - .floo_rsp_i ( router_3_7_to_magia_tile_ni_3_7_rsp ), - .floo_req_i ( router_3_7_to_magia_tile_ni_3_7_req ), - .floo_rsp_o ( magia_tile_ni_3_7_to_router_3_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][8] ), - .id_i ( '{x: 4, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_8_to_router_3_8_req ), - .floo_rsp_i ( router_3_8_to_magia_tile_ni_3_8_rsp ), - .floo_req_i ( router_3_8_to_magia_tile_ni_3_8_req ), - .floo_rsp_o ( magia_tile_ni_3_8_to_router_3_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][9] ), - .id_i ( '{x: 4, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_9_to_router_3_9_req ), - .floo_rsp_i ( router_3_9_to_magia_tile_ni_3_9_rsp ), - .floo_req_i ( router_3_9_to_magia_tile_ni_3_9_req ), - .floo_rsp_o ( magia_tile_ni_3_9_to_router_3_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][10] ), - .id_i ( '{x: 4, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_10_to_router_3_10_req ), - .floo_rsp_i ( router_3_10_to_magia_tile_ni_3_10_rsp ), - .floo_req_i ( router_3_10_to_magia_tile_ni_3_10_req ), - .floo_rsp_o ( magia_tile_ni_3_10_to_router_3_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][11] ), - .id_i ( '{x: 4, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_11_to_router_3_11_req ), - .floo_rsp_i ( router_3_11_to_magia_tile_ni_3_11_rsp ), - .floo_req_i ( router_3_11_to_magia_tile_ni_3_11_req ), - .floo_rsp_o ( magia_tile_ni_3_11_to_router_3_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][12] ), - .id_i ( '{x: 4, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_12_to_router_3_12_req ), - .floo_rsp_i ( router_3_12_to_magia_tile_ni_3_12_rsp ), - .floo_req_i ( router_3_12_to_magia_tile_ni_3_12_req ), - .floo_rsp_o ( magia_tile_ni_3_12_to_router_3_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][13] ), - .id_i ( '{x: 4, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_13_to_router_3_13_req ), - .floo_rsp_i ( router_3_13_to_magia_tile_ni_3_13_rsp ), - .floo_req_i ( router_3_13_to_magia_tile_ni_3_13_req ), - .floo_rsp_o ( magia_tile_ni_3_13_to_router_3_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][14] ), - .id_i ( '{x: 4, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_14_to_router_3_14_req ), - .floo_rsp_i ( router_3_14_to_magia_tile_ni_3_14_rsp ), - .floo_req_i ( router_3_14_to_magia_tile_ni_3_14_req ), - .floo_rsp_o ( magia_tile_ni_3_14_to_router_3_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][15] ), - .id_i ( '{x: 4, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_15_to_router_3_15_req ), - .floo_rsp_i ( router_3_15_to_magia_tile_ni_3_15_rsp ), - .floo_req_i ( router_3_15_to_magia_tile_ni_3_15_req ), - .floo_rsp_o ( magia_tile_ni_3_15_to_router_3_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][0] ), - .id_i ( '{x: 5, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_0_to_router_4_0_req ), - .floo_rsp_i ( router_4_0_to_magia_tile_ni_4_0_rsp ), - .floo_req_i ( router_4_0_to_magia_tile_ni_4_0_req ), - .floo_rsp_o ( magia_tile_ni_4_0_to_router_4_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][1] ), - .id_i ( '{x: 5, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_1_to_router_4_1_req ), - .floo_rsp_i ( router_4_1_to_magia_tile_ni_4_1_rsp ), - .floo_req_i ( router_4_1_to_magia_tile_ni_4_1_req ), - .floo_rsp_o ( magia_tile_ni_4_1_to_router_4_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][2] ), - .id_i ( '{x: 5, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_2_to_router_4_2_req ), - .floo_rsp_i ( router_4_2_to_magia_tile_ni_4_2_rsp ), - .floo_req_i ( router_4_2_to_magia_tile_ni_4_2_req ), - .floo_rsp_o ( magia_tile_ni_4_2_to_router_4_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][3] ), - .id_i ( '{x: 5, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_3_to_router_4_3_req ), - .floo_rsp_i ( router_4_3_to_magia_tile_ni_4_3_rsp ), - .floo_req_i ( router_4_3_to_magia_tile_ni_4_3_req ), - .floo_rsp_o ( magia_tile_ni_4_3_to_router_4_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][4] ), - .id_i ( '{x: 5, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_4_to_router_4_4_req ), - .floo_rsp_i ( router_4_4_to_magia_tile_ni_4_4_rsp ), - .floo_req_i ( router_4_4_to_magia_tile_ni_4_4_req ), - .floo_rsp_o ( magia_tile_ni_4_4_to_router_4_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][5] ), - .id_i ( '{x: 5, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_5_to_router_4_5_req ), - .floo_rsp_i ( router_4_5_to_magia_tile_ni_4_5_rsp ), - .floo_req_i ( router_4_5_to_magia_tile_ni_4_5_req ), - .floo_rsp_o ( magia_tile_ni_4_5_to_router_4_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][6] ), - .id_i ( '{x: 5, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_6_to_router_4_6_req ), - .floo_rsp_i ( router_4_6_to_magia_tile_ni_4_6_rsp ), - .floo_req_i ( router_4_6_to_magia_tile_ni_4_6_req ), - .floo_rsp_o ( magia_tile_ni_4_6_to_router_4_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][7] ), - .id_i ( '{x: 5, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_7_to_router_4_7_req ), - .floo_rsp_i ( router_4_7_to_magia_tile_ni_4_7_rsp ), - .floo_req_i ( router_4_7_to_magia_tile_ni_4_7_req ), - .floo_rsp_o ( magia_tile_ni_4_7_to_router_4_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][8] ), - .id_i ( '{x: 5, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_8_to_router_4_8_req ), - .floo_rsp_i ( router_4_8_to_magia_tile_ni_4_8_rsp ), - .floo_req_i ( router_4_8_to_magia_tile_ni_4_8_req ), - .floo_rsp_o ( magia_tile_ni_4_8_to_router_4_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][9] ), - .id_i ( '{x: 5, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_9_to_router_4_9_req ), - .floo_rsp_i ( router_4_9_to_magia_tile_ni_4_9_rsp ), - .floo_req_i ( router_4_9_to_magia_tile_ni_4_9_req ), - .floo_rsp_o ( magia_tile_ni_4_9_to_router_4_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][10] ), - .id_i ( '{x: 5, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_10_to_router_4_10_req ), - .floo_rsp_i ( router_4_10_to_magia_tile_ni_4_10_rsp ), - .floo_req_i ( router_4_10_to_magia_tile_ni_4_10_req ), - .floo_rsp_o ( magia_tile_ni_4_10_to_router_4_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][11] ), - .id_i ( '{x: 5, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_11_to_router_4_11_req ), - .floo_rsp_i ( router_4_11_to_magia_tile_ni_4_11_rsp ), - .floo_req_i ( router_4_11_to_magia_tile_ni_4_11_req ), - .floo_rsp_o ( magia_tile_ni_4_11_to_router_4_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][12] ), - .id_i ( '{x: 5, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_12_to_router_4_12_req ), - .floo_rsp_i ( router_4_12_to_magia_tile_ni_4_12_rsp ), - .floo_req_i ( router_4_12_to_magia_tile_ni_4_12_req ), - .floo_rsp_o ( magia_tile_ni_4_12_to_router_4_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][13] ), - .id_i ( '{x: 5, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_13_to_router_4_13_req ), - .floo_rsp_i ( router_4_13_to_magia_tile_ni_4_13_rsp ), - .floo_req_i ( router_4_13_to_magia_tile_ni_4_13_req ), - .floo_rsp_o ( magia_tile_ni_4_13_to_router_4_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][14] ), - .id_i ( '{x: 5, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_14_to_router_4_14_req ), - .floo_rsp_i ( router_4_14_to_magia_tile_ni_4_14_rsp ), - .floo_req_i ( router_4_14_to_magia_tile_ni_4_14_req ), - .floo_rsp_o ( magia_tile_ni_4_14_to_router_4_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][15] ), - .id_i ( '{x: 5, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_15_to_router_4_15_req ), - .floo_rsp_i ( router_4_15_to_magia_tile_ni_4_15_rsp ), - .floo_req_i ( router_4_15_to_magia_tile_ni_4_15_req ), - .floo_rsp_o ( magia_tile_ni_4_15_to_router_4_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][0] ), - .id_i ( '{x: 6, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_0_to_router_5_0_req ), - .floo_rsp_i ( router_5_0_to_magia_tile_ni_5_0_rsp ), - .floo_req_i ( router_5_0_to_magia_tile_ni_5_0_req ), - .floo_rsp_o ( magia_tile_ni_5_0_to_router_5_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][1] ), - .id_i ( '{x: 6, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_1_to_router_5_1_req ), - .floo_rsp_i ( router_5_1_to_magia_tile_ni_5_1_rsp ), - .floo_req_i ( router_5_1_to_magia_tile_ni_5_1_req ), - .floo_rsp_o ( magia_tile_ni_5_1_to_router_5_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][2] ), - .id_i ( '{x: 6, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_2_to_router_5_2_req ), - .floo_rsp_i ( router_5_2_to_magia_tile_ni_5_2_rsp ), - .floo_req_i ( router_5_2_to_magia_tile_ni_5_2_req ), - .floo_rsp_o ( magia_tile_ni_5_2_to_router_5_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][3] ), - .id_i ( '{x: 6, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_3_to_router_5_3_req ), - .floo_rsp_i ( router_5_3_to_magia_tile_ni_5_3_rsp ), - .floo_req_i ( router_5_3_to_magia_tile_ni_5_3_req ), - .floo_rsp_o ( magia_tile_ni_5_3_to_router_5_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][4] ), - .id_i ( '{x: 6, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_4_to_router_5_4_req ), - .floo_rsp_i ( router_5_4_to_magia_tile_ni_5_4_rsp ), - .floo_req_i ( router_5_4_to_magia_tile_ni_5_4_req ), - .floo_rsp_o ( magia_tile_ni_5_4_to_router_5_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][5] ), - .id_i ( '{x: 6, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_5_to_router_5_5_req ), - .floo_rsp_i ( router_5_5_to_magia_tile_ni_5_5_rsp ), - .floo_req_i ( router_5_5_to_magia_tile_ni_5_5_req ), - .floo_rsp_o ( magia_tile_ni_5_5_to_router_5_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][6] ), - .id_i ( '{x: 6, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_6_to_router_5_6_req ), - .floo_rsp_i ( router_5_6_to_magia_tile_ni_5_6_rsp ), - .floo_req_i ( router_5_6_to_magia_tile_ni_5_6_req ), - .floo_rsp_o ( magia_tile_ni_5_6_to_router_5_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][7] ), - .id_i ( '{x: 6, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_7_to_router_5_7_req ), - .floo_rsp_i ( router_5_7_to_magia_tile_ni_5_7_rsp ), - .floo_req_i ( router_5_7_to_magia_tile_ni_5_7_req ), - .floo_rsp_o ( magia_tile_ni_5_7_to_router_5_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][8] ), - .id_i ( '{x: 6, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_8_to_router_5_8_req ), - .floo_rsp_i ( router_5_8_to_magia_tile_ni_5_8_rsp ), - .floo_req_i ( router_5_8_to_magia_tile_ni_5_8_req ), - .floo_rsp_o ( magia_tile_ni_5_8_to_router_5_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][9] ), - .id_i ( '{x: 6, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_9_to_router_5_9_req ), - .floo_rsp_i ( router_5_9_to_magia_tile_ni_5_9_rsp ), - .floo_req_i ( router_5_9_to_magia_tile_ni_5_9_req ), - .floo_rsp_o ( magia_tile_ni_5_9_to_router_5_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][10] ), - .id_i ( '{x: 6, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_10_to_router_5_10_req ), - .floo_rsp_i ( router_5_10_to_magia_tile_ni_5_10_rsp ), - .floo_req_i ( router_5_10_to_magia_tile_ni_5_10_req ), - .floo_rsp_o ( magia_tile_ni_5_10_to_router_5_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][11] ), - .id_i ( '{x: 6, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_11_to_router_5_11_req ), - .floo_rsp_i ( router_5_11_to_magia_tile_ni_5_11_rsp ), - .floo_req_i ( router_5_11_to_magia_tile_ni_5_11_req ), - .floo_rsp_o ( magia_tile_ni_5_11_to_router_5_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][12] ), - .id_i ( '{x: 6, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_12_to_router_5_12_req ), - .floo_rsp_i ( router_5_12_to_magia_tile_ni_5_12_rsp ), - .floo_req_i ( router_5_12_to_magia_tile_ni_5_12_req ), - .floo_rsp_o ( magia_tile_ni_5_12_to_router_5_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][13] ), - .id_i ( '{x: 6, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_13_to_router_5_13_req ), - .floo_rsp_i ( router_5_13_to_magia_tile_ni_5_13_rsp ), - .floo_req_i ( router_5_13_to_magia_tile_ni_5_13_req ), - .floo_rsp_o ( magia_tile_ni_5_13_to_router_5_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][14] ), - .id_i ( '{x: 6, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_14_to_router_5_14_req ), - .floo_rsp_i ( router_5_14_to_magia_tile_ni_5_14_rsp ), - .floo_req_i ( router_5_14_to_magia_tile_ni_5_14_req ), - .floo_rsp_o ( magia_tile_ni_5_14_to_router_5_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][15] ), - .id_i ( '{x: 6, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_15_to_router_5_15_req ), - .floo_rsp_i ( router_5_15_to_magia_tile_ni_5_15_rsp ), - .floo_req_i ( router_5_15_to_magia_tile_ni_5_15_req ), - .floo_rsp_o ( magia_tile_ni_5_15_to_router_5_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][0] ), - .id_i ( '{x: 7, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_0_to_router_6_0_req ), - .floo_rsp_i ( router_6_0_to_magia_tile_ni_6_0_rsp ), - .floo_req_i ( router_6_0_to_magia_tile_ni_6_0_req ), - .floo_rsp_o ( magia_tile_ni_6_0_to_router_6_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][1] ), - .id_i ( '{x: 7, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_1_to_router_6_1_req ), - .floo_rsp_i ( router_6_1_to_magia_tile_ni_6_1_rsp ), - .floo_req_i ( router_6_1_to_magia_tile_ni_6_1_req ), - .floo_rsp_o ( magia_tile_ni_6_1_to_router_6_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][2] ), - .id_i ( '{x: 7, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_2_to_router_6_2_req ), - .floo_rsp_i ( router_6_2_to_magia_tile_ni_6_2_rsp ), - .floo_req_i ( router_6_2_to_magia_tile_ni_6_2_req ), - .floo_rsp_o ( magia_tile_ni_6_2_to_router_6_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][3] ), - .id_i ( '{x: 7, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_3_to_router_6_3_req ), - .floo_rsp_i ( router_6_3_to_magia_tile_ni_6_3_rsp ), - .floo_req_i ( router_6_3_to_magia_tile_ni_6_3_req ), - .floo_rsp_o ( magia_tile_ni_6_3_to_router_6_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][4] ), - .id_i ( '{x: 7, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_4_to_router_6_4_req ), - .floo_rsp_i ( router_6_4_to_magia_tile_ni_6_4_rsp ), - .floo_req_i ( router_6_4_to_magia_tile_ni_6_4_req ), - .floo_rsp_o ( magia_tile_ni_6_4_to_router_6_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][5] ), - .id_i ( '{x: 7, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_5_to_router_6_5_req ), - .floo_rsp_i ( router_6_5_to_magia_tile_ni_6_5_rsp ), - .floo_req_i ( router_6_5_to_magia_tile_ni_6_5_req ), - .floo_rsp_o ( magia_tile_ni_6_5_to_router_6_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][6] ), - .id_i ( '{x: 7, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_6_to_router_6_6_req ), - .floo_rsp_i ( router_6_6_to_magia_tile_ni_6_6_rsp ), - .floo_req_i ( router_6_6_to_magia_tile_ni_6_6_req ), - .floo_rsp_o ( magia_tile_ni_6_6_to_router_6_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][7] ), - .id_i ( '{x: 7, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_7_to_router_6_7_req ), - .floo_rsp_i ( router_6_7_to_magia_tile_ni_6_7_rsp ), - .floo_req_i ( router_6_7_to_magia_tile_ni_6_7_req ), - .floo_rsp_o ( magia_tile_ni_6_7_to_router_6_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][8] ), - .id_i ( '{x: 7, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_8_to_router_6_8_req ), - .floo_rsp_i ( router_6_8_to_magia_tile_ni_6_8_rsp ), - .floo_req_i ( router_6_8_to_magia_tile_ni_6_8_req ), - .floo_rsp_o ( magia_tile_ni_6_8_to_router_6_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][9] ), - .id_i ( '{x: 7, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_9_to_router_6_9_req ), - .floo_rsp_i ( router_6_9_to_magia_tile_ni_6_9_rsp ), - .floo_req_i ( router_6_9_to_magia_tile_ni_6_9_req ), - .floo_rsp_o ( magia_tile_ni_6_9_to_router_6_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][10] ), - .id_i ( '{x: 7, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_10_to_router_6_10_req ), - .floo_rsp_i ( router_6_10_to_magia_tile_ni_6_10_rsp ), - .floo_req_i ( router_6_10_to_magia_tile_ni_6_10_req ), - .floo_rsp_o ( magia_tile_ni_6_10_to_router_6_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][11] ), - .id_i ( '{x: 7, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_11_to_router_6_11_req ), - .floo_rsp_i ( router_6_11_to_magia_tile_ni_6_11_rsp ), - .floo_req_i ( router_6_11_to_magia_tile_ni_6_11_req ), - .floo_rsp_o ( magia_tile_ni_6_11_to_router_6_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][12] ), - .id_i ( '{x: 7, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_12_to_router_6_12_req ), - .floo_rsp_i ( router_6_12_to_magia_tile_ni_6_12_rsp ), - .floo_req_i ( router_6_12_to_magia_tile_ni_6_12_req ), - .floo_rsp_o ( magia_tile_ni_6_12_to_router_6_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][13] ), - .id_i ( '{x: 7, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_13_to_router_6_13_req ), - .floo_rsp_i ( router_6_13_to_magia_tile_ni_6_13_rsp ), - .floo_req_i ( router_6_13_to_magia_tile_ni_6_13_req ), - .floo_rsp_o ( magia_tile_ni_6_13_to_router_6_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][14] ), - .id_i ( '{x: 7, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_14_to_router_6_14_req ), - .floo_rsp_i ( router_6_14_to_magia_tile_ni_6_14_rsp ), - .floo_req_i ( router_6_14_to_magia_tile_ni_6_14_req ), - .floo_rsp_o ( magia_tile_ni_6_14_to_router_6_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][15] ), - .id_i ( '{x: 7, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_15_to_router_6_15_req ), - .floo_rsp_i ( router_6_15_to_magia_tile_ni_6_15_rsp ), - .floo_req_i ( router_6_15_to_magia_tile_ni_6_15_req ), - .floo_rsp_o ( magia_tile_ni_6_15_to_router_6_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][0] ), - .id_i ( '{x: 8, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_0_to_router_7_0_req ), - .floo_rsp_i ( router_7_0_to_magia_tile_ni_7_0_rsp ), - .floo_req_i ( router_7_0_to_magia_tile_ni_7_0_req ), - .floo_rsp_o ( magia_tile_ni_7_0_to_router_7_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][1] ), - .id_i ( '{x: 8, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_1_to_router_7_1_req ), - .floo_rsp_i ( router_7_1_to_magia_tile_ni_7_1_rsp ), - .floo_req_i ( router_7_1_to_magia_tile_ni_7_1_req ), - .floo_rsp_o ( magia_tile_ni_7_1_to_router_7_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][2] ), - .id_i ( '{x: 8, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_2_to_router_7_2_req ), - .floo_rsp_i ( router_7_2_to_magia_tile_ni_7_2_rsp ), - .floo_req_i ( router_7_2_to_magia_tile_ni_7_2_req ), - .floo_rsp_o ( magia_tile_ni_7_2_to_router_7_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][3] ), - .id_i ( '{x: 8, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_3_to_router_7_3_req ), - .floo_rsp_i ( router_7_3_to_magia_tile_ni_7_3_rsp ), - .floo_req_i ( router_7_3_to_magia_tile_ni_7_3_req ), - .floo_rsp_o ( magia_tile_ni_7_3_to_router_7_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][4] ), - .id_i ( '{x: 8, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_4_to_router_7_4_req ), - .floo_rsp_i ( router_7_4_to_magia_tile_ni_7_4_rsp ), - .floo_req_i ( router_7_4_to_magia_tile_ni_7_4_req ), - .floo_rsp_o ( magia_tile_ni_7_4_to_router_7_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][5] ), - .id_i ( '{x: 8, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_5_to_router_7_5_req ), - .floo_rsp_i ( router_7_5_to_magia_tile_ni_7_5_rsp ), - .floo_req_i ( router_7_5_to_magia_tile_ni_7_5_req ), - .floo_rsp_o ( magia_tile_ni_7_5_to_router_7_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][6] ), - .id_i ( '{x: 8, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_6_to_router_7_6_req ), - .floo_rsp_i ( router_7_6_to_magia_tile_ni_7_6_rsp ), - .floo_req_i ( router_7_6_to_magia_tile_ni_7_6_req ), - .floo_rsp_o ( magia_tile_ni_7_6_to_router_7_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][7] ), - .id_i ( '{x: 8, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_7_to_router_7_7_req ), - .floo_rsp_i ( router_7_7_to_magia_tile_ni_7_7_rsp ), - .floo_req_i ( router_7_7_to_magia_tile_ni_7_7_req ), - .floo_rsp_o ( magia_tile_ni_7_7_to_router_7_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][8] ), - .id_i ( '{x: 8, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_8_to_router_7_8_req ), - .floo_rsp_i ( router_7_8_to_magia_tile_ni_7_8_rsp ), - .floo_req_i ( router_7_8_to_magia_tile_ni_7_8_req ), - .floo_rsp_o ( magia_tile_ni_7_8_to_router_7_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][9] ), - .id_i ( '{x: 8, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_9_to_router_7_9_req ), - .floo_rsp_i ( router_7_9_to_magia_tile_ni_7_9_rsp ), - .floo_req_i ( router_7_9_to_magia_tile_ni_7_9_req ), - .floo_rsp_o ( magia_tile_ni_7_9_to_router_7_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][10] ), - .id_i ( '{x: 8, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_10_to_router_7_10_req ), - .floo_rsp_i ( router_7_10_to_magia_tile_ni_7_10_rsp ), - .floo_req_i ( router_7_10_to_magia_tile_ni_7_10_req ), - .floo_rsp_o ( magia_tile_ni_7_10_to_router_7_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][11] ), - .id_i ( '{x: 8, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_11_to_router_7_11_req ), - .floo_rsp_i ( router_7_11_to_magia_tile_ni_7_11_rsp ), - .floo_req_i ( router_7_11_to_magia_tile_ni_7_11_req ), - .floo_rsp_o ( magia_tile_ni_7_11_to_router_7_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][12] ), - .id_i ( '{x: 8, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_12_to_router_7_12_req ), - .floo_rsp_i ( router_7_12_to_magia_tile_ni_7_12_rsp ), - .floo_req_i ( router_7_12_to_magia_tile_ni_7_12_req ), - .floo_rsp_o ( magia_tile_ni_7_12_to_router_7_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][13] ), - .id_i ( '{x: 8, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_13_to_router_7_13_req ), - .floo_rsp_i ( router_7_13_to_magia_tile_ni_7_13_rsp ), - .floo_req_i ( router_7_13_to_magia_tile_ni_7_13_req ), - .floo_rsp_o ( magia_tile_ni_7_13_to_router_7_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][14] ), - .id_i ( '{x: 8, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_14_to_router_7_14_req ), - .floo_rsp_i ( router_7_14_to_magia_tile_ni_7_14_rsp ), - .floo_req_i ( router_7_14_to_magia_tile_ni_7_14_req ), - .floo_rsp_o ( magia_tile_ni_7_14_to_router_7_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][15] ), - .id_i ( '{x: 8, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_15_to_router_7_15_req ), - .floo_rsp_i ( router_7_15_to_magia_tile_ni_7_15_rsp ), - .floo_req_i ( router_7_15_to_magia_tile_ni_7_15_req ), - .floo_rsp_o ( magia_tile_ni_7_15_to_router_7_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][0] ), - .id_i ( '{x: 9, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_0_to_router_8_0_req ), - .floo_rsp_i ( router_8_0_to_magia_tile_ni_8_0_rsp ), - .floo_req_i ( router_8_0_to_magia_tile_ni_8_0_req ), - .floo_rsp_o ( magia_tile_ni_8_0_to_router_8_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][1] ), - .id_i ( '{x: 9, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_1_to_router_8_1_req ), - .floo_rsp_i ( router_8_1_to_magia_tile_ni_8_1_rsp ), - .floo_req_i ( router_8_1_to_magia_tile_ni_8_1_req ), - .floo_rsp_o ( magia_tile_ni_8_1_to_router_8_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][2] ), - .id_i ( '{x: 9, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_2_to_router_8_2_req ), - .floo_rsp_i ( router_8_2_to_magia_tile_ni_8_2_rsp ), - .floo_req_i ( router_8_2_to_magia_tile_ni_8_2_req ), - .floo_rsp_o ( magia_tile_ni_8_2_to_router_8_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][3] ), - .id_i ( '{x: 9, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_3_to_router_8_3_req ), - .floo_rsp_i ( router_8_3_to_magia_tile_ni_8_3_rsp ), - .floo_req_i ( router_8_3_to_magia_tile_ni_8_3_req ), - .floo_rsp_o ( magia_tile_ni_8_3_to_router_8_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][4] ), - .id_i ( '{x: 9, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_4_to_router_8_4_req ), - .floo_rsp_i ( router_8_4_to_magia_tile_ni_8_4_rsp ), - .floo_req_i ( router_8_4_to_magia_tile_ni_8_4_req ), - .floo_rsp_o ( magia_tile_ni_8_4_to_router_8_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][5] ), - .id_i ( '{x: 9, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_5_to_router_8_5_req ), - .floo_rsp_i ( router_8_5_to_magia_tile_ni_8_5_rsp ), - .floo_req_i ( router_8_5_to_magia_tile_ni_8_5_req ), - .floo_rsp_o ( magia_tile_ni_8_5_to_router_8_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][6] ), - .id_i ( '{x: 9, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_6_to_router_8_6_req ), - .floo_rsp_i ( router_8_6_to_magia_tile_ni_8_6_rsp ), - .floo_req_i ( router_8_6_to_magia_tile_ni_8_6_req ), - .floo_rsp_o ( magia_tile_ni_8_6_to_router_8_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][7] ), - .id_i ( '{x: 9, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_7_to_router_8_7_req ), - .floo_rsp_i ( router_8_7_to_magia_tile_ni_8_7_rsp ), - .floo_req_i ( router_8_7_to_magia_tile_ni_8_7_req ), - .floo_rsp_o ( magia_tile_ni_8_7_to_router_8_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][8] ), - .id_i ( '{x: 9, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_8_to_router_8_8_req ), - .floo_rsp_i ( router_8_8_to_magia_tile_ni_8_8_rsp ), - .floo_req_i ( router_8_8_to_magia_tile_ni_8_8_req ), - .floo_rsp_o ( magia_tile_ni_8_8_to_router_8_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][9] ), - .id_i ( '{x: 9, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_9_to_router_8_9_req ), - .floo_rsp_i ( router_8_9_to_magia_tile_ni_8_9_rsp ), - .floo_req_i ( router_8_9_to_magia_tile_ni_8_9_req ), - .floo_rsp_o ( magia_tile_ni_8_9_to_router_8_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][10] ), - .id_i ( '{x: 9, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_10_to_router_8_10_req ), - .floo_rsp_i ( router_8_10_to_magia_tile_ni_8_10_rsp ), - .floo_req_i ( router_8_10_to_magia_tile_ni_8_10_req ), - .floo_rsp_o ( magia_tile_ni_8_10_to_router_8_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][11] ), - .id_i ( '{x: 9, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_11_to_router_8_11_req ), - .floo_rsp_i ( router_8_11_to_magia_tile_ni_8_11_rsp ), - .floo_req_i ( router_8_11_to_magia_tile_ni_8_11_req ), - .floo_rsp_o ( magia_tile_ni_8_11_to_router_8_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][12] ), - .id_i ( '{x: 9, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_12_to_router_8_12_req ), - .floo_rsp_i ( router_8_12_to_magia_tile_ni_8_12_rsp ), - .floo_req_i ( router_8_12_to_magia_tile_ni_8_12_req ), - .floo_rsp_o ( magia_tile_ni_8_12_to_router_8_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][13] ), - .id_i ( '{x: 9, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_13_to_router_8_13_req ), - .floo_rsp_i ( router_8_13_to_magia_tile_ni_8_13_rsp ), - .floo_req_i ( router_8_13_to_magia_tile_ni_8_13_req ), - .floo_rsp_o ( magia_tile_ni_8_13_to_router_8_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][14] ), - .id_i ( '{x: 9, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_14_to_router_8_14_req ), - .floo_rsp_i ( router_8_14_to_magia_tile_ni_8_14_rsp ), - .floo_req_i ( router_8_14_to_magia_tile_ni_8_14_req ), - .floo_rsp_o ( magia_tile_ni_8_14_to_router_8_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][15] ), - .id_i ( '{x: 9, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_15_to_router_8_15_req ), - .floo_rsp_i ( router_8_15_to_magia_tile_ni_8_15_rsp ), - .floo_req_i ( router_8_15_to_magia_tile_ni_8_15_req ), - .floo_rsp_o ( magia_tile_ni_8_15_to_router_8_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][0] ), - .id_i ( '{x: 10, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_0_to_router_9_0_req ), - .floo_rsp_i ( router_9_0_to_magia_tile_ni_9_0_rsp ), - .floo_req_i ( router_9_0_to_magia_tile_ni_9_0_req ), - .floo_rsp_o ( magia_tile_ni_9_0_to_router_9_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][1] ), - .id_i ( '{x: 10, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_1_to_router_9_1_req ), - .floo_rsp_i ( router_9_1_to_magia_tile_ni_9_1_rsp ), - .floo_req_i ( router_9_1_to_magia_tile_ni_9_1_req ), - .floo_rsp_o ( magia_tile_ni_9_1_to_router_9_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][2] ), - .id_i ( '{x: 10, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_2_to_router_9_2_req ), - .floo_rsp_i ( router_9_2_to_magia_tile_ni_9_2_rsp ), - .floo_req_i ( router_9_2_to_magia_tile_ni_9_2_req ), - .floo_rsp_o ( magia_tile_ni_9_2_to_router_9_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][3] ), - .id_i ( '{x: 10, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_3_to_router_9_3_req ), - .floo_rsp_i ( router_9_3_to_magia_tile_ni_9_3_rsp ), - .floo_req_i ( router_9_3_to_magia_tile_ni_9_3_req ), - .floo_rsp_o ( magia_tile_ni_9_3_to_router_9_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][4] ), - .id_i ( '{x: 10, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_4_to_router_9_4_req ), - .floo_rsp_i ( router_9_4_to_magia_tile_ni_9_4_rsp ), - .floo_req_i ( router_9_4_to_magia_tile_ni_9_4_req ), - .floo_rsp_o ( magia_tile_ni_9_4_to_router_9_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][5] ), - .id_i ( '{x: 10, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_5_to_router_9_5_req ), - .floo_rsp_i ( router_9_5_to_magia_tile_ni_9_5_rsp ), - .floo_req_i ( router_9_5_to_magia_tile_ni_9_5_req ), - .floo_rsp_o ( magia_tile_ni_9_5_to_router_9_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][6] ), - .id_i ( '{x: 10, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_6_to_router_9_6_req ), - .floo_rsp_i ( router_9_6_to_magia_tile_ni_9_6_rsp ), - .floo_req_i ( router_9_6_to_magia_tile_ni_9_6_req ), - .floo_rsp_o ( magia_tile_ni_9_6_to_router_9_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][7] ), - .id_i ( '{x: 10, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_7_to_router_9_7_req ), - .floo_rsp_i ( router_9_7_to_magia_tile_ni_9_7_rsp ), - .floo_req_i ( router_9_7_to_magia_tile_ni_9_7_req ), - .floo_rsp_o ( magia_tile_ni_9_7_to_router_9_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][8] ), - .id_i ( '{x: 10, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_8_to_router_9_8_req ), - .floo_rsp_i ( router_9_8_to_magia_tile_ni_9_8_rsp ), - .floo_req_i ( router_9_8_to_magia_tile_ni_9_8_req ), - .floo_rsp_o ( magia_tile_ni_9_8_to_router_9_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][9] ), - .id_i ( '{x: 10, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_9_to_router_9_9_req ), - .floo_rsp_i ( router_9_9_to_magia_tile_ni_9_9_rsp ), - .floo_req_i ( router_9_9_to_magia_tile_ni_9_9_req ), - .floo_rsp_o ( magia_tile_ni_9_9_to_router_9_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][10] ), - .id_i ( '{x: 10, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_10_to_router_9_10_req ), - .floo_rsp_i ( router_9_10_to_magia_tile_ni_9_10_rsp ), - .floo_req_i ( router_9_10_to_magia_tile_ni_9_10_req ), - .floo_rsp_o ( magia_tile_ni_9_10_to_router_9_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][11] ), - .id_i ( '{x: 10, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_11_to_router_9_11_req ), - .floo_rsp_i ( router_9_11_to_magia_tile_ni_9_11_rsp ), - .floo_req_i ( router_9_11_to_magia_tile_ni_9_11_req ), - .floo_rsp_o ( magia_tile_ni_9_11_to_router_9_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][12] ), - .id_i ( '{x: 10, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_12_to_router_9_12_req ), - .floo_rsp_i ( router_9_12_to_magia_tile_ni_9_12_rsp ), - .floo_req_i ( router_9_12_to_magia_tile_ni_9_12_req ), - .floo_rsp_o ( magia_tile_ni_9_12_to_router_9_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][13] ), - .id_i ( '{x: 10, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_13_to_router_9_13_req ), - .floo_rsp_i ( router_9_13_to_magia_tile_ni_9_13_rsp ), - .floo_req_i ( router_9_13_to_magia_tile_ni_9_13_req ), - .floo_rsp_o ( magia_tile_ni_9_13_to_router_9_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][14] ), - .id_i ( '{x: 10, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_14_to_router_9_14_req ), - .floo_rsp_i ( router_9_14_to_magia_tile_ni_9_14_rsp ), - .floo_req_i ( router_9_14_to_magia_tile_ni_9_14_req ), - .floo_rsp_o ( magia_tile_ni_9_14_to_router_9_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][15] ), - .id_i ( '{x: 10, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_15_to_router_9_15_req ), - .floo_rsp_i ( router_9_15_to_magia_tile_ni_9_15_rsp ), - .floo_req_i ( router_9_15_to_magia_tile_ni_9_15_req ), - .floo_rsp_o ( magia_tile_ni_9_15_to_router_9_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][0] ), - .id_i ( '{x: 11, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_0_to_router_10_0_req ), - .floo_rsp_i ( router_10_0_to_magia_tile_ni_10_0_rsp ), - .floo_req_i ( router_10_0_to_magia_tile_ni_10_0_req ), - .floo_rsp_o ( magia_tile_ni_10_0_to_router_10_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][1] ), - .id_i ( '{x: 11, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_1_to_router_10_1_req ), - .floo_rsp_i ( router_10_1_to_magia_tile_ni_10_1_rsp ), - .floo_req_i ( router_10_1_to_magia_tile_ni_10_1_req ), - .floo_rsp_o ( magia_tile_ni_10_1_to_router_10_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][2] ), - .id_i ( '{x: 11, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_2_to_router_10_2_req ), - .floo_rsp_i ( router_10_2_to_magia_tile_ni_10_2_rsp ), - .floo_req_i ( router_10_2_to_magia_tile_ni_10_2_req ), - .floo_rsp_o ( magia_tile_ni_10_2_to_router_10_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][3] ), - .id_i ( '{x: 11, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_3_to_router_10_3_req ), - .floo_rsp_i ( router_10_3_to_magia_tile_ni_10_3_rsp ), - .floo_req_i ( router_10_3_to_magia_tile_ni_10_3_req ), - .floo_rsp_o ( magia_tile_ni_10_3_to_router_10_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][4] ), - .id_i ( '{x: 11, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_4_to_router_10_4_req ), - .floo_rsp_i ( router_10_4_to_magia_tile_ni_10_4_rsp ), - .floo_req_i ( router_10_4_to_magia_tile_ni_10_4_req ), - .floo_rsp_o ( magia_tile_ni_10_4_to_router_10_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][5] ), - .id_i ( '{x: 11, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_5_to_router_10_5_req ), - .floo_rsp_i ( router_10_5_to_magia_tile_ni_10_5_rsp ), - .floo_req_i ( router_10_5_to_magia_tile_ni_10_5_req ), - .floo_rsp_o ( magia_tile_ni_10_5_to_router_10_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][6] ), - .id_i ( '{x: 11, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_6_to_router_10_6_req ), - .floo_rsp_i ( router_10_6_to_magia_tile_ni_10_6_rsp ), - .floo_req_i ( router_10_6_to_magia_tile_ni_10_6_req ), - .floo_rsp_o ( magia_tile_ni_10_6_to_router_10_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][7] ), - .id_i ( '{x: 11, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_7_to_router_10_7_req ), - .floo_rsp_i ( router_10_7_to_magia_tile_ni_10_7_rsp ), - .floo_req_i ( router_10_7_to_magia_tile_ni_10_7_req ), - .floo_rsp_o ( magia_tile_ni_10_7_to_router_10_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][8] ), - .id_i ( '{x: 11, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_8_to_router_10_8_req ), - .floo_rsp_i ( router_10_8_to_magia_tile_ni_10_8_rsp ), - .floo_req_i ( router_10_8_to_magia_tile_ni_10_8_req ), - .floo_rsp_o ( magia_tile_ni_10_8_to_router_10_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][9] ), - .id_i ( '{x: 11, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_9_to_router_10_9_req ), - .floo_rsp_i ( router_10_9_to_magia_tile_ni_10_9_rsp ), - .floo_req_i ( router_10_9_to_magia_tile_ni_10_9_req ), - .floo_rsp_o ( magia_tile_ni_10_9_to_router_10_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][10] ), - .id_i ( '{x: 11, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_10_to_router_10_10_req ), - .floo_rsp_i ( router_10_10_to_magia_tile_ni_10_10_rsp ), - .floo_req_i ( router_10_10_to_magia_tile_ni_10_10_req ), - .floo_rsp_o ( magia_tile_ni_10_10_to_router_10_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][11] ), - .id_i ( '{x: 11, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_11_to_router_10_11_req ), - .floo_rsp_i ( router_10_11_to_magia_tile_ni_10_11_rsp ), - .floo_req_i ( router_10_11_to_magia_tile_ni_10_11_req ), - .floo_rsp_o ( magia_tile_ni_10_11_to_router_10_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][12] ), - .id_i ( '{x: 11, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_12_to_router_10_12_req ), - .floo_rsp_i ( router_10_12_to_magia_tile_ni_10_12_rsp ), - .floo_req_i ( router_10_12_to_magia_tile_ni_10_12_req ), - .floo_rsp_o ( magia_tile_ni_10_12_to_router_10_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][13] ), - .id_i ( '{x: 11, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_13_to_router_10_13_req ), - .floo_rsp_i ( router_10_13_to_magia_tile_ni_10_13_rsp ), - .floo_req_i ( router_10_13_to_magia_tile_ni_10_13_req ), - .floo_rsp_o ( magia_tile_ni_10_13_to_router_10_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][14] ), - .id_i ( '{x: 11, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_14_to_router_10_14_req ), - .floo_rsp_i ( router_10_14_to_magia_tile_ni_10_14_rsp ), - .floo_req_i ( router_10_14_to_magia_tile_ni_10_14_req ), - .floo_rsp_o ( magia_tile_ni_10_14_to_router_10_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][15] ), - .id_i ( '{x: 11, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_15_to_router_10_15_req ), - .floo_rsp_i ( router_10_15_to_magia_tile_ni_10_15_rsp ), - .floo_req_i ( router_10_15_to_magia_tile_ni_10_15_req ), - .floo_rsp_o ( magia_tile_ni_10_15_to_router_10_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][0] ), - .id_i ( '{x: 12, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_0_to_router_11_0_req ), - .floo_rsp_i ( router_11_0_to_magia_tile_ni_11_0_rsp ), - .floo_req_i ( router_11_0_to_magia_tile_ni_11_0_req ), - .floo_rsp_o ( magia_tile_ni_11_0_to_router_11_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][1] ), - .id_i ( '{x: 12, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_1_to_router_11_1_req ), - .floo_rsp_i ( router_11_1_to_magia_tile_ni_11_1_rsp ), - .floo_req_i ( router_11_1_to_magia_tile_ni_11_1_req ), - .floo_rsp_o ( magia_tile_ni_11_1_to_router_11_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][2] ), - .id_i ( '{x: 12, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_2_to_router_11_2_req ), - .floo_rsp_i ( router_11_2_to_magia_tile_ni_11_2_rsp ), - .floo_req_i ( router_11_2_to_magia_tile_ni_11_2_req ), - .floo_rsp_o ( magia_tile_ni_11_2_to_router_11_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][3] ), - .id_i ( '{x: 12, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_3_to_router_11_3_req ), - .floo_rsp_i ( router_11_3_to_magia_tile_ni_11_3_rsp ), - .floo_req_i ( router_11_3_to_magia_tile_ni_11_3_req ), - .floo_rsp_o ( magia_tile_ni_11_3_to_router_11_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][4] ), - .id_i ( '{x: 12, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_4_to_router_11_4_req ), - .floo_rsp_i ( router_11_4_to_magia_tile_ni_11_4_rsp ), - .floo_req_i ( router_11_4_to_magia_tile_ni_11_4_req ), - .floo_rsp_o ( magia_tile_ni_11_4_to_router_11_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][5] ), - .id_i ( '{x: 12, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_5_to_router_11_5_req ), - .floo_rsp_i ( router_11_5_to_magia_tile_ni_11_5_rsp ), - .floo_req_i ( router_11_5_to_magia_tile_ni_11_5_req ), - .floo_rsp_o ( magia_tile_ni_11_5_to_router_11_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][6] ), - .id_i ( '{x: 12, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_6_to_router_11_6_req ), - .floo_rsp_i ( router_11_6_to_magia_tile_ni_11_6_rsp ), - .floo_req_i ( router_11_6_to_magia_tile_ni_11_6_req ), - .floo_rsp_o ( magia_tile_ni_11_6_to_router_11_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][7] ), - .id_i ( '{x: 12, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_7_to_router_11_7_req ), - .floo_rsp_i ( router_11_7_to_magia_tile_ni_11_7_rsp ), - .floo_req_i ( router_11_7_to_magia_tile_ni_11_7_req ), - .floo_rsp_o ( magia_tile_ni_11_7_to_router_11_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][8] ), - .id_i ( '{x: 12, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_8_to_router_11_8_req ), - .floo_rsp_i ( router_11_8_to_magia_tile_ni_11_8_rsp ), - .floo_req_i ( router_11_8_to_magia_tile_ni_11_8_req ), - .floo_rsp_o ( magia_tile_ni_11_8_to_router_11_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][9] ), - .id_i ( '{x: 12, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_9_to_router_11_9_req ), - .floo_rsp_i ( router_11_9_to_magia_tile_ni_11_9_rsp ), - .floo_req_i ( router_11_9_to_magia_tile_ni_11_9_req ), - .floo_rsp_o ( magia_tile_ni_11_9_to_router_11_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][10] ), - .id_i ( '{x: 12, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_10_to_router_11_10_req ), - .floo_rsp_i ( router_11_10_to_magia_tile_ni_11_10_rsp ), - .floo_req_i ( router_11_10_to_magia_tile_ni_11_10_req ), - .floo_rsp_o ( magia_tile_ni_11_10_to_router_11_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][11] ), - .id_i ( '{x: 12, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_11_to_router_11_11_req ), - .floo_rsp_i ( router_11_11_to_magia_tile_ni_11_11_rsp ), - .floo_req_i ( router_11_11_to_magia_tile_ni_11_11_req ), - .floo_rsp_o ( magia_tile_ni_11_11_to_router_11_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][12] ), - .id_i ( '{x: 12, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_12_to_router_11_12_req ), - .floo_rsp_i ( router_11_12_to_magia_tile_ni_11_12_rsp ), - .floo_req_i ( router_11_12_to_magia_tile_ni_11_12_req ), - .floo_rsp_o ( magia_tile_ni_11_12_to_router_11_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][13] ), - .id_i ( '{x: 12, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_13_to_router_11_13_req ), - .floo_rsp_i ( router_11_13_to_magia_tile_ni_11_13_rsp ), - .floo_req_i ( router_11_13_to_magia_tile_ni_11_13_req ), - .floo_rsp_o ( magia_tile_ni_11_13_to_router_11_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][14] ), - .id_i ( '{x: 12, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_14_to_router_11_14_req ), - .floo_rsp_i ( router_11_14_to_magia_tile_ni_11_14_rsp ), - .floo_req_i ( router_11_14_to_magia_tile_ni_11_14_req ), - .floo_rsp_o ( magia_tile_ni_11_14_to_router_11_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][15] ), - .id_i ( '{x: 12, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_15_to_router_11_15_req ), - .floo_rsp_i ( router_11_15_to_magia_tile_ni_11_15_rsp ), - .floo_req_i ( router_11_15_to_magia_tile_ni_11_15_req ), - .floo_rsp_o ( magia_tile_ni_11_15_to_router_11_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][0] ), - .id_i ( '{x: 13, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_0_to_router_12_0_req ), - .floo_rsp_i ( router_12_0_to_magia_tile_ni_12_0_rsp ), - .floo_req_i ( router_12_0_to_magia_tile_ni_12_0_req ), - .floo_rsp_o ( magia_tile_ni_12_0_to_router_12_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][1] ), - .id_i ( '{x: 13, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_1_to_router_12_1_req ), - .floo_rsp_i ( router_12_1_to_magia_tile_ni_12_1_rsp ), - .floo_req_i ( router_12_1_to_magia_tile_ni_12_1_req ), - .floo_rsp_o ( magia_tile_ni_12_1_to_router_12_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][2] ), - .id_i ( '{x: 13, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_2_to_router_12_2_req ), - .floo_rsp_i ( router_12_2_to_magia_tile_ni_12_2_rsp ), - .floo_req_i ( router_12_2_to_magia_tile_ni_12_2_req ), - .floo_rsp_o ( magia_tile_ni_12_2_to_router_12_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][3] ), - .id_i ( '{x: 13, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_3_to_router_12_3_req ), - .floo_rsp_i ( router_12_3_to_magia_tile_ni_12_3_rsp ), - .floo_req_i ( router_12_3_to_magia_tile_ni_12_3_req ), - .floo_rsp_o ( magia_tile_ni_12_3_to_router_12_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][4] ), - .id_i ( '{x: 13, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_4_to_router_12_4_req ), - .floo_rsp_i ( router_12_4_to_magia_tile_ni_12_4_rsp ), - .floo_req_i ( router_12_4_to_magia_tile_ni_12_4_req ), - .floo_rsp_o ( magia_tile_ni_12_4_to_router_12_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][5] ), - .id_i ( '{x: 13, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_5_to_router_12_5_req ), - .floo_rsp_i ( router_12_5_to_magia_tile_ni_12_5_rsp ), - .floo_req_i ( router_12_5_to_magia_tile_ni_12_5_req ), - .floo_rsp_o ( magia_tile_ni_12_5_to_router_12_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][6] ), - .id_i ( '{x: 13, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_6_to_router_12_6_req ), - .floo_rsp_i ( router_12_6_to_magia_tile_ni_12_6_rsp ), - .floo_req_i ( router_12_6_to_magia_tile_ni_12_6_req ), - .floo_rsp_o ( magia_tile_ni_12_6_to_router_12_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][7] ), - .id_i ( '{x: 13, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_7_to_router_12_7_req ), - .floo_rsp_i ( router_12_7_to_magia_tile_ni_12_7_rsp ), - .floo_req_i ( router_12_7_to_magia_tile_ni_12_7_req ), - .floo_rsp_o ( magia_tile_ni_12_7_to_router_12_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][8] ), - .id_i ( '{x: 13, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_8_to_router_12_8_req ), - .floo_rsp_i ( router_12_8_to_magia_tile_ni_12_8_rsp ), - .floo_req_i ( router_12_8_to_magia_tile_ni_12_8_req ), - .floo_rsp_o ( magia_tile_ni_12_8_to_router_12_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][9] ), - .id_i ( '{x: 13, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_9_to_router_12_9_req ), - .floo_rsp_i ( router_12_9_to_magia_tile_ni_12_9_rsp ), - .floo_req_i ( router_12_9_to_magia_tile_ni_12_9_req ), - .floo_rsp_o ( magia_tile_ni_12_9_to_router_12_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][10] ), - .id_i ( '{x: 13, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_10_to_router_12_10_req ), - .floo_rsp_i ( router_12_10_to_magia_tile_ni_12_10_rsp ), - .floo_req_i ( router_12_10_to_magia_tile_ni_12_10_req ), - .floo_rsp_o ( magia_tile_ni_12_10_to_router_12_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][11] ), - .id_i ( '{x: 13, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_11_to_router_12_11_req ), - .floo_rsp_i ( router_12_11_to_magia_tile_ni_12_11_rsp ), - .floo_req_i ( router_12_11_to_magia_tile_ni_12_11_req ), - .floo_rsp_o ( magia_tile_ni_12_11_to_router_12_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][12] ), - .id_i ( '{x: 13, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_12_to_router_12_12_req ), - .floo_rsp_i ( router_12_12_to_magia_tile_ni_12_12_rsp ), - .floo_req_i ( router_12_12_to_magia_tile_ni_12_12_req ), - .floo_rsp_o ( magia_tile_ni_12_12_to_router_12_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][13] ), - .id_i ( '{x: 13, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_13_to_router_12_13_req ), - .floo_rsp_i ( router_12_13_to_magia_tile_ni_12_13_rsp ), - .floo_req_i ( router_12_13_to_magia_tile_ni_12_13_req ), - .floo_rsp_o ( magia_tile_ni_12_13_to_router_12_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][14] ), - .id_i ( '{x: 13, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_14_to_router_12_14_req ), - .floo_rsp_i ( router_12_14_to_magia_tile_ni_12_14_rsp ), - .floo_req_i ( router_12_14_to_magia_tile_ni_12_14_req ), - .floo_rsp_o ( magia_tile_ni_12_14_to_router_12_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][15] ), - .id_i ( '{x: 13, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_15_to_router_12_15_req ), - .floo_rsp_i ( router_12_15_to_magia_tile_ni_12_15_rsp ), - .floo_req_i ( router_12_15_to_magia_tile_ni_12_15_req ), - .floo_rsp_o ( magia_tile_ni_12_15_to_router_12_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][0] ), - .id_i ( '{x: 14, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_0_to_router_13_0_req ), - .floo_rsp_i ( router_13_0_to_magia_tile_ni_13_0_rsp ), - .floo_req_i ( router_13_0_to_magia_tile_ni_13_0_req ), - .floo_rsp_o ( magia_tile_ni_13_0_to_router_13_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][1] ), - .id_i ( '{x: 14, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_1_to_router_13_1_req ), - .floo_rsp_i ( router_13_1_to_magia_tile_ni_13_1_rsp ), - .floo_req_i ( router_13_1_to_magia_tile_ni_13_1_req ), - .floo_rsp_o ( magia_tile_ni_13_1_to_router_13_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][2] ), - .id_i ( '{x: 14, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_2_to_router_13_2_req ), - .floo_rsp_i ( router_13_2_to_magia_tile_ni_13_2_rsp ), - .floo_req_i ( router_13_2_to_magia_tile_ni_13_2_req ), - .floo_rsp_o ( magia_tile_ni_13_2_to_router_13_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][3] ), - .id_i ( '{x: 14, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_3_to_router_13_3_req ), - .floo_rsp_i ( router_13_3_to_magia_tile_ni_13_3_rsp ), - .floo_req_i ( router_13_3_to_magia_tile_ni_13_3_req ), - .floo_rsp_o ( magia_tile_ni_13_3_to_router_13_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][4] ), - .id_i ( '{x: 14, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_4_to_router_13_4_req ), - .floo_rsp_i ( router_13_4_to_magia_tile_ni_13_4_rsp ), - .floo_req_i ( router_13_4_to_magia_tile_ni_13_4_req ), - .floo_rsp_o ( magia_tile_ni_13_4_to_router_13_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][5] ), - .id_i ( '{x: 14, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_5_to_router_13_5_req ), - .floo_rsp_i ( router_13_5_to_magia_tile_ni_13_5_rsp ), - .floo_req_i ( router_13_5_to_magia_tile_ni_13_5_req ), - .floo_rsp_o ( magia_tile_ni_13_5_to_router_13_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][6] ), - .id_i ( '{x: 14, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_6_to_router_13_6_req ), - .floo_rsp_i ( router_13_6_to_magia_tile_ni_13_6_rsp ), - .floo_req_i ( router_13_6_to_magia_tile_ni_13_6_req ), - .floo_rsp_o ( magia_tile_ni_13_6_to_router_13_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][7] ), - .id_i ( '{x: 14, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_7_to_router_13_7_req ), - .floo_rsp_i ( router_13_7_to_magia_tile_ni_13_7_rsp ), - .floo_req_i ( router_13_7_to_magia_tile_ni_13_7_req ), - .floo_rsp_o ( magia_tile_ni_13_7_to_router_13_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][8] ), - .id_i ( '{x: 14, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_8_to_router_13_8_req ), - .floo_rsp_i ( router_13_8_to_magia_tile_ni_13_8_rsp ), - .floo_req_i ( router_13_8_to_magia_tile_ni_13_8_req ), - .floo_rsp_o ( magia_tile_ni_13_8_to_router_13_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][9] ), - .id_i ( '{x: 14, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_9_to_router_13_9_req ), - .floo_rsp_i ( router_13_9_to_magia_tile_ni_13_9_rsp ), - .floo_req_i ( router_13_9_to_magia_tile_ni_13_9_req ), - .floo_rsp_o ( magia_tile_ni_13_9_to_router_13_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][10] ), - .id_i ( '{x: 14, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_10_to_router_13_10_req ), - .floo_rsp_i ( router_13_10_to_magia_tile_ni_13_10_rsp ), - .floo_req_i ( router_13_10_to_magia_tile_ni_13_10_req ), - .floo_rsp_o ( magia_tile_ni_13_10_to_router_13_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][11] ), - .id_i ( '{x: 14, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_11_to_router_13_11_req ), - .floo_rsp_i ( router_13_11_to_magia_tile_ni_13_11_rsp ), - .floo_req_i ( router_13_11_to_magia_tile_ni_13_11_req ), - .floo_rsp_o ( magia_tile_ni_13_11_to_router_13_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][12] ), - .id_i ( '{x: 14, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_12_to_router_13_12_req ), - .floo_rsp_i ( router_13_12_to_magia_tile_ni_13_12_rsp ), - .floo_req_i ( router_13_12_to_magia_tile_ni_13_12_req ), - .floo_rsp_o ( magia_tile_ni_13_12_to_router_13_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][13] ), - .id_i ( '{x: 14, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_13_to_router_13_13_req ), - .floo_rsp_i ( router_13_13_to_magia_tile_ni_13_13_rsp ), - .floo_req_i ( router_13_13_to_magia_tile_ni_13_13_req ), - .floo_rsp_o ( magia_tile_ni_13_13_to_router_13_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][14] ), - .id_i ( '{x: 14, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_14_to_router_13_14_req ), - .floo_rsp_i ( router_13_14_to_magia_tile_ni_13_14_rsp ), - .floo_req_i ( router_13_14_to_magia_tile_ni_13_14_req ), - .floo_rsp_o ( magia_tile_ni_13_14_to_router_13_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][15] ), - .id_i ( '{x: 14, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_15_to_router_13_15_req ), - .floo_rsp_i ( router_13_15_to_magia_tile_ni_13_15_rsp ), - .floo_req_i ( router_13_15_to_magia_tile_ni_13_15_req ), - .floo_rsp_o ( magia_tile_ni_13_15_to_router_13_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][0] ), - .id_i ( '{x: 15, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_0_to_router_14_0_req ), - .floo_rsp_i ( router_14_0_to_magia_tile_ni_14_0_rsp ), - .floo_req_i ( router_14_0_to_magia_tile_ni_14_0_req ), - .floo_rsp_o ( magia_tile_ni_14_0_to_router_14_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][1] ), - .id_i ( '{x: 15, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_1_to_router_14_1_req ), - .floo_rsp_i ( router_14_1_to_magia_tile_ni_14_1_rsp ), - .floo_req_i ( router_14_1_to_magia_tile_ni_14_1_req ), - .floo_rsp_o ( magia_tile_ni_14_1_to_router_14_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][2] ), - .id_i ( '{x: 15, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_2_to_router_14_2_req ), - .floo_rsp_i ( router_14_2_to_magia_tile_ni_14_2_rsp ), - .floo_req_i ( router_14_2_to_magia_tile_ni_14_2_req ), - .floo_rsp_o ( magia_tile_ni_14_2_to_router_14_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][3] ), - .id_i ( '{x: 15, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_3_to_router_14_3_req ), - .floo_rsp_i ( router_14_3_to_magia_tile_ni_14_3_rsp ), - .floo_req_i ( router_14_3_to_magia_tile_ni_14_3_req ), - .floo_rsp_o ( magia_tile_ni_14_3_to_router_14_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][4] ), - .id_i ( '{x: 15, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_4_to_router_14_4_req ), - .floo_rsp_i ( router_14_4_to_magia_tile_ni_14_4_rsp ), - .floo_req_i ( router_14_4_to_magia_tile_ni_14_4_req ), - .floo_rsp_o ( magia_tile_ni_14_4_to_router_14_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][5] ), - .id_i ( '{x: 15, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_5_to_router_14_5_req ), - .floo_rsp_i ( router_14_5_to_magia_tile_ni_14_5_rsp ), - .floo_req_i ( router_14_5_to_magia_tile_ni_14_5_req ), - .floo_rsp_o ( magia_tile_ni_14_5_to_router_14_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][6] ), - .id_i ( '{x: 15, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_6_to_router_14_6_req ), - .floo_rsp_i ( router_14_6_to_magia_tile_ni_14_6_rsp ), - .floo_req_i ( router_14_6_to_magia_tile_ni_14_6_req ), - .floo_rsp_o ( magia_tile_ni_14_6_to_router_14_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][7] ), - .id_i ( '{x: 15, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_7_to_router_14_7_req ), - .floo_rsp_i ( router_14_7_to_magia_tile_ni_14_7_rsp ), - .floo_req_i ( router_14_7_to_magia_tile_ni_14_7_req ), - .floo_rsp_o ( magia_tile_ni_14_7_to_router_14_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][8] ), - .id_i ( '{x: 15, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_8_to_router_14_8_req ), - .floo_rsp_i ( router_14_8_to_magia_tile_ni_14_8_rsp ), - .floo_req_i ( router_14_8_to_magia_tile_ni_14_8_req ), - .floo_rsp_o ( magia_tile_ni_14_8_to_router_14_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][9] ), - .id_i ( '{x: 15, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_9_to_router_14_9_req ), - .floo_rsp_i ( router_14_9_to_magia_tile_ni_14_9_rsp ), - .floo_req_i ( router_14_9_to_magia_tile_ni_14_9_req ), - .floo_rsp_o ( magia_tile_ni_14_9_to_router_14_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][10] ), - .id_i ( '{x: 15, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_10_to_router_14_10_req ), - .floo_rsp_i ( router_14_10_to_magia_tile_ni_14_10_rsp ), - .floo_req_i ( router_14_10_to_magia_tile_ni_14_10_req ), - .floo_rsp_o ( magia_tile_ni_14_10_to_router_14_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][11] ), - .id_i ( '{x: 15, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_11_to_router_14_11_req ), - .floo_rsp_i ( router_14_11_to_magia_tile_ni_14_11_rsp ), - .floo_req_i ( router_14_11_to_magia_tile_ni_14_11_req ), - .floo_rsp_o ( magia_tile_ni_14_11_to_router_14_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][12] ), - .id_i ( '{x: 15, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_12_to_router_14_12_req ), - .floo_rsp_i ( router_14_12_to_magia_tile_ni_14_12_rsp ), - .floo_req_i ( router_14_12_to_magia_tile_ni_14_12_req ), - .floo_rsp_o ( magia_tile_ni_14_12_to_router_14_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][13] ), - .id_i ( '{x: 15, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_13_to_router_14_13_req ), - .floo_rsp_i ( router_14_13_to_magia_tile_ni_14_13_rsp ), - .floo_req_i ( router_14_13_to_magia_tile_ni_14_13_req ), - .floo_rsp_o ( magia_tile_ni_14_13_to_router_14_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][14] ), - .id_i ( '{x: 15, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_14_to_router_14_14_req ), - .floo_rsp_i ( router_14_14_to_magia_tile_ni_14_14_rsp ), - .floo_req_i ( router_14_14_to_magia_tile_ni_14_14_req ), - .floo_rsp_o ( magia_tile_ni_14_14_to_router_14_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][15] ), - .id_i ( '{x: 15, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_15_to_router_14_15_req ), - .floo_rsp_i ( router_14_15_to_magia_tile_ni_14_15_rsp ), - .floo_req_i ( router_14_15_to_magia_tile_ni_14_15_req ), - .floo_rsp_o ( magia_tile_ni_14_15_to_router_14_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][0] ), - .id_i ( '{x: 16, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_0_to_router_15_0_req ), - .floo_rsp_i ( router_15_0_to_magia_tile_ni_15_0_rsp ), - .floo_req_i ( router_15_0_to_magia_tile_ni_15_0_req ), - .floo_rsp_o ( magia_tile_ni_15_0_to_router_15_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][1] ), - .id_i ( '{x: 16, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_1_to_router_15_1_req ), - .floo_rsp_i ( router_15_1_to_magia_tile_ni_15_1_rsp ), - .floo_req_i ( router_15_1_to_magia_tile_ni_15_1_req ), - .floo_rsp_o ( magia_tile_ni_15_1_to_router_15_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][2] ), - .id_i ( '{x: 16, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_2_to_router_15_2_req ), - .floo_rsp_i ( router_15_2_to_magia_tile_ni_15_2_rsp ), - .floo_req_i ( router_15_2_to_magia_tile_ni_15_2_req ), - .floo_rsp_o ( magia_tile_ni_15_2_to_router_15_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][3] ), - .id_i ( '{x: 16, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_3_to_router_15_3_req ), - .floo_rsp_i ( router_15_3_to_magia_tile_ni_15_3_rsp ), - .floo_req_i ( router_15_3_to_magia_tile_ni_15_3_req ), - .floo_rsp_o ( magia_tile_ni_15_3_to_router_15_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][4] ), - .id_i ( '{x: 16, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_4_to_router_15_4_req ), - .floo_rsp_i ( router_15_4_to_magia_tile_ni_15_4_rsp ), - .floo_req_i ( router_15_4_to_magia_tile_ni_15_4_req ), - .floo_rsp_o ( magia_tile_ni_15_4_to_router_15_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][5] ), - .id_i ( '{x: 16, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_5_to_router_15_5_req ), - .floo_rsp_i ( router_15_5_to_magia_tile_ni_15_5_rsp ), - .floo_req_i ( router_15_5_to_magia_tile_ni_15_5_req ), - .floo_rsp_o ( magia_tile_ni_15_5_to_router_15_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][6] ), - .id_i ( '{x: 16, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_6_to_router_15_6_req ), - .floo_rsp_i ( router_15_6_to_magia_tile_ni_15_6_rsp ), - .floo_req_i ( router_15_6_to_magia_tile_ni_15_6_req ), - .floo_rsp_o ( magia_tile_ni_15_6_to_router_15_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][7] ), - .id_i ( '{x: 16, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_7_to_router_15_7_req ), - .floo_rsp_i ( router_15_7_to_magia_tile_ni_15_7_rsp ), - .floo_req_i ( router_15_7_to_magia_tile_ni_15_7_req ), - .floo_rsp_o ( magia_tile_ni_15_7_to_router_15_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][8] ), - .id_i ( '{x: 16, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_8_to_router_15_8_req ), - .floo_rsp_i ( router_15_8_to_magia_tile_ni_15_8_rsp ), - .floo_req_i ( router_15_8_to_magia_tile_ni_15_8_req ), - .floo_rsp_o ( magia_tile_ni_15_8_to_router_15_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][9] ), - .id_i ( '{x: 16, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_9_to_router_15_9_req ), - .floo_rsp_i ( router_15_9_to_magia_tile_ni_15_9_rsp ), - .floo_req_i ( router_15_9_to_magia_tile_ni_15_9_req ), - .floo_rsp_o ( magia_tile_ni_15_9_to_router_15_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][10] ), - .id_i ( '{x: 16, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_10_to_router_15_10_req ), - .floo_rsp_i ( router_15_10_to_magia_tile_ni_15_10_rsp ), - .floo_req_i ( router_15_10_to_magia_tile_ni_15_10_req ), - .floo_rsp_o ( magia_tile_ni_15_10_to_router_15_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][11] ), - .id_i ( '{x: 16, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_11_to_router_15_11_req ), - .floo_rsp_i ( router_15_11_to_magia_tile_ni_15_11_rsp ), - .floo_req_i ( router_15_11_to_magia_tile_ni_15_11_req ), - .floo_rsp_o ( magia_tile_ni_15_11_to_router_15_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][12] ), - .id_i ( '{x: 16, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_12_to_router_15_12_req ), - .floo_rsp_i ( router_15_12_to_magia_tile_ni_15_12_rsp ), - .floo_req_i ( router_15_12_to_magia_tile_ni_15_12_req ), - .floo_rsp_o ( magia_tile_ni_15_12_to_router_15_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][13] ), - .id_i ( '{x: 16, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_13_to_router_15_13_req ), - .floo_rsp_i ( router_15_13_to_magia_tile_ni_15_13_rsp ), - .floo_req_i ( router_15_13_to_magia_tile_ni_15_13_req ), - .floo_rsp_o ( magia_tile_ni_15_13_to_router_15_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][14] ), - .id_i ( '{x: 16, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_14_to_router_15_14_req ), - .floo_rsp_i ( router_15_14_to_magia_tile_ni_15_14_rsp ), - .floo_req_i ( router_15_14_to_magia_tile_ni_15_14_req ), - .floo_rsp_o ( magia_tile_ni_15_14_to_router_15_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][15] ), - .id_i ( '{x: 16, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_15_to_router_15_15_req ), - .floo_rsp_i ( router_15_15_to_magia_tile_ni_15_15_rsp ), - .floo_req_i ( router_15_15_to_magia_tile_ni_15_15_req ), - .floo_rsp_o ( magia_tile_ni_15_15_to_router_15_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[0] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[0] ), - .id_i ( '{x: 0, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_L2_ni_0_rsp ), - .floo_req_i ( router_0_0_to_L2_ni_0_req ), - .floo_rsp_o ( L2_ni_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[1] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[1] ), - .id_i ( '{x: 0, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_L2_ni_1_rsp ), - .floo_req_i ( router_0_1_to_L2_ni_1_req ), - .floo_rsp_o ( L2_ni_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[2] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[2] ), - .id_i ( '{x: 0, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_L2_ni_2_rsp ), - .floo_req_i ( router_0_2_to_L2_ni_2_req ), - .floo_rsp_o ( L2_ni_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[3] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[3] ), - .id_i ( '{x: 0, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_L2_ni_3_rsp ), - .floo_req_i ( router_0_3_to_L2_ni_3_req ), - .floo_rsp_o ( L2_ni_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[4] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[4] ), - .id_i ( '{x: 0, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_L2_ni_4_rsp ), - .floo_req_i ( router_0_4_to_L2_ni_4_req ), - .floo_rsp_o ( L2_ni_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[5] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[5] ), - .id_i ( '{x: 0, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_L2_ni_5_rsp ), - .floo_req_i ( router_0_5_to_L2_ni_5_req ), - .floo_rsp_o ( L2_ni_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[6] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[6] ), - .id_i ( '{x: 0, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_L2_ni_6_rsp ), - .floo_req_i ( router_0_6_to_L2_ni_6_req ), - .floo_rsp_o ( L2_ni_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[7] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[7] ), - .id_i ( '{x: 0, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_L2_ni_7_rsp ), - .floo_req_i ( router_0_7_to_L2_ni_7_req ), - .floo_rsp_o ( L2_ni_7_to_router_0_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[8] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[8] ), - .id_i ( '{x: 0, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_8_to_router_0_8_req ), - .floo_rsp_i ( router_0_8_to_L2_ni_8_rsp ), - .floo_req_i ( router_0_8_to_L2_ni_8_req ), - .floo_rsp_o ( L2_ni_8_to_router_0_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[9] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[9] ), - .id_i ( '{x: 0, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_9_to_router_0_9_req ), - .floo_rsp_i ( router_0_9_to_L2_ni_9_rsp ), - .floo_req_i ( router_0_9_to_L2_ni_9_req ), - .floo_rsp_o ( L2_ni_9_to_router_0_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[10] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[10] ), - .id_i ( '{x: 0, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_10_to_router_0_10_req ), - .floo_rsp_i ( router_0_10_to_L2_ni_10_rsp ), - .floo_req_i ( router_0_10_to_L2_ni_10_req ), - .floo_rsp_o ( L2_ni_10_to_router_0_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[11] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[11] ), - .id_i ( '{x: 0, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_11_to_router_0_11_req ), - .floo_rsp_i ( router_0_11_to_L2_ni_11_rsp ), - .floo_req_i ( router_0_11_to_L2_ni_11_req ), - .floo_rsp_o ( L2_ni_11_to_router_0_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[12] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[12] ), - .id_i ( '{x: 0, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_12_to_router_0_12_req ), - .floo_rsp_i ( router_0_12_to_L2_ni_12_rsp ), - .floo_req_i ( router_0_12_to_L2_ni_12_req ), - .floo_rsp_o ( L2_ni_12_to_router_0_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[13] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[13] ), - .id_i ( '{x: 0, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_13_to_router_0_13_req ), - .floo_rsp_i ( router_0_13_to_L2_ni_13_rsp ), - .floo_req_i ( router_0_13_to_L2_ni_13_req ), - .floo_rsp_o ( L2_ni_13_to_router_0_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[14] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[14] ), - .id_i ( '{x: 0, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_14_to_router_0_14_req ), - .floo_rsp_i ( router_0_14_to_L2_ni_14_rsp ), - .floo_req_i ( router_0_14_to_L2_ni_14_req ), - .floo_rsp_o ( L2_ni_14_to_router_0_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[15] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[15] ), - .id_i ( '{x: 0, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_15_to_router_0_15_req ), - .floo_rsp_i ( router_0_15_to_L2_ni_15_rsp ), - .floo_req_i ( router_0_15_to_L2_ni_15_req ), - .floo_rsp_o ( L2_ni_15_to_router_0_15_rsp ) -); - - -floo_req_t [4:0] router_0_0_req_in; -floo_rsp_t [4:0] router_0_0_rsp_out; -floo_req_t [4:0] router_0_0_req_out; -floo_rsp_t [4:0] router_0_0_rsp_in; - - assign router_0_0_req_in[0] = router_0_1_to_router_0_0_req; - assign router_0_0_req_in[1] = router_1_0_to_router_0_0_req; - assign router_0_0_req_in[2] = '0; - assign router_0_0_req_in[3] = L2_ni_0_to_router_0_0_req; - assign router_0_0_req_in[4] = magia_tile_ni_0_0_to_router_0_0_req; - - assign router_0_0_to_router_0_1_rsp = router_0_0_rsp_out[0]; - assign router_0_0_to_router_1_0_rsp = router_0_0_rsp_out[1]; - assign router_0_0_to_L2_ni_0_rsp = router_0_0_rsp_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_rsp = router_0_0_rsp_out[4]; - - assign router_0_0_to_router_0_1_req = router_0_0_req_out[0]; - assign router_0_0_to_router_1_0_req = router_0_0_req_out[1]; - assign router_0_0_to_L2_ni_0_req = router_0_0_req_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_req = router_0_0_req_out[4]; - - assign router_0_0_rsp_in[0] = router_0_1_to_router_0_0_rsp; - assign router_0_0_rsp_in[1] = router_1_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[2] = '0; - assign router_0_0_rsp_in[3] = L2_ni_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[4] = magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_0_req_in), - .floo_rsp_o (router_0_0_rsp_out), - .floo_req_o (router_0_0_req_out), - .floo_rsp_i (router_0_0_rsp_in) -); - - -floo_req_t [4:0] router_0_1_req_in; -floo_rsp_t [4:0] router_0_1_rsp_out; -floo_req_t [4:0] router_0_1_req_out; -floo_rsp_t [4:0] router_0_1_rsp_in; - - assign router_0_1_req_in[0] = router_0_2_to_router_0_1_req; - assign router_0_1_req_in[1] = router_1_1_to_router_0_1_req; - assign router_0_1_req_in[2] = router_0_0_to_router_0_1_req; - assign router_0_1_req_in[3] = L2_ni_1_to_router_0_1_req; - assign router_0_1_req_in[4] = magia_tile_ni_0_1_to_router_0_1_req; - - assign router_0_1_to_router_0_2_rsp = router_0_1_rsp_out[0]; - assign router_0_1_to_router_1_1_rsp = router_0_1_rsp_out[1]; - assign router_0_1_to_router_0_0_rsp = router_0_1_rsp_out[2]; - assign router_0_1_to_L2_ni_1_rsp = router_0_1_rsp_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_rsp = router_0_1_rsp_out[4]; - - assign router_0_1_to_router_0_2_req = router_0_1_req_out[0]; - assign router_0_1_to_router_1_1_req = router_0_1_req_out[1]; - assign router_0_1_to_router_0_0_req = router_0_1_req_out[2]; - assign router_0_1_to_L2_ni_1_req = router_0_1_req_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_req = router_0_1_req_out[4]; - - assign router_0_1_rsp_in[0] = router_0_2_to_router_0_1_rsp; - assign router_0_1_rsp_in[1] = router_1_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[2] = router_0_0_to_router_0_1_rsp; - assign router_0_1_rsp_in[3] = L2_ni_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[4] = magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_1_req_in), - .floo_rsp_o (router_0_1_rsp_out), - .floo_req_o (router_0_1_req_out), - .floo_rsp_i (router_0_1_rsp_in) -); - - -floo_req_t [4:0] router_0_2_req_in; -floo_rsp_t [4:0] router_0_2_rsp_out; -floo_req_t [4:0] router_0_2_req_out; -floo_rsp_t [4:0] router_0_2_rsp_in; - - assign router_0_2_req_in[0] = router_0_3_to_router_0_2_req; - assign router_0_2_req_in[1] = router_1_2_to_router_0_2_req; - assign router_0_2_req_in[2] = router_0_1_to_router_0_2_req; - assign router_0_2_req_in[3] = L2_ni_2_to_router_0_2_req; - assign router_0_2_req_in[4] = magia_tile_ni_0_2_to_router_0_2_req; - - assign router_0_2_to_router_0_3_rsp = router_0_2_rsp_out[0]; - assign router_0_2_to_router_1_2_rsp = router_0_2_rsp_out[1]; - assign router_0_2_to_router_0_1_rsp = router_0_2_rsp_out[2]; - assign router_0_2_to_L2_ni_2_rsp = router_0_2_rsp_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_rsp = router_0_2_rsp_out[4]; - - assign router_0_2_to_router_0_3_req = router_0_2_req_out[0]; - assign router_0_2_to_router_1_2_req = router_0_2_req_out[1]; - assign router_0_2_to_router_0_1_req = router_0_2_req_out[2]; - assign router_0_2_to_L2_ni_2_req = router_0_2_req_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_req = router_0_2_req_out[4]; - - assign router_0_2_rsp_in[0] = router_0_3_to_router_0_2_rsp; - assign router_0_2_rsp_in[1] = router_1_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[2] = router_0_1_to_router_0_2_rsp; - assign router_0_2_rsp_in[3] = L2_ni_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[4] = magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_2_req_in), - .floo_rsp_o (router_0_2_rsp_out), - .floo_req_o (router_0_2_req_out), - .floo_rsp_i (router_0_2_rsp_in) -); - - -floo_req_t [4:0] router_0_3_req_in; -floo_rsp_t [4:0] router_0_3_rsp_out; -floo_req_t [4:0] router_0_3_req_out; -floo_rsp_t [4:0] router_0_3_rsp_in; - - assign router_0_3_req_in[0] = router_0_4_to_router_0_3_req; - assign router_0_3_req_in[1] = router_1_3_to_router_0_3_req; - assign router_0_3_req_in[2] = router_0_2_to_router_0_3_req; - assign router_0_3_req_in[3] = L2_ni_3_to_router_0_3_req; - assign router_0_3_req_in[4] = magia_tile_ni_0_3_to_router_0_3_req; - - assign router_0_3_to_router_0_4_rsp = router_0_3_rsp_out[0]; - assign router_0_3_to_router_1_3_rsp = router_0_3_rsp_out[1]; - assign router_0_3_to_router_0_2_rsp = router_0_3_rsp_out[2]; - assign router_0_3_to_L2_ni_3_rsp = router_0_3_rsp_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_rsp = router_0_3_rsp_out[4]; - - assign router_0_3_to_router_0_4_req = router_0_3_req_out[0]; - assign router_0_3_to_router_1_3_req = router_0_3_req_out[1]; - assign router_0_3_to_router_0_2_req = router_0_3_req_out[2]; - assign router_0_3_to_L2_ni_3_req = router_0_3_req_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_req = router_0_3_req_out[4]; - - assign router_0_3_rsp_in[0] = router_0_4_to_router_0_3_rsp; - assign router_0_3_rsp_in[1] = router_1_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[2] = router_0_2_to_router_0_3_rsp; - assign router_0_3_rsp_in[3] = L2_ni_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[4] = magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_3_req_in), - .floo_rsp_o (router_0_3_rsp_out), - .floo_req_o (router_0_3_req_out), - .floo_rsp_i (router_0_3_rsp_in) -); - - -floo_req_t [4:0] router_0_4_req_in; -floo_rsp_t [4:0] router_0_4_rsp_out; -floo_req_t [4:0] router_0_4_req_out; -floo_rsp_t [4:0] router_0_4_rsp_in; - - assign router_0_4_req_in[0] = router_0_5_to_router_0_4_req; - assign router_0_4_req_in[1] = router_1_4_to_router_0_4_req; - assign router_0_4_req_in[2] = router_0_3_to_router_0_4_req; - assign router_0_4_req_in[3] = L2_ni_4_to_router_0_4_req; - assign router_0_4_req_in[4] = magia_tile_ni_0_4_to_router_0_4_req; - - assign router_0_4_to_router_0_5_rsp = router_0_4_rsp_out[0]; - assign router_0_4_to_router_1_4_rsp = router_0_4_rsp_out[1]; - assign router_0_4_to_router_0_3_rsp = router_0_4_rsp_out[2]; - assign router_0_4_to_L2_ni_4_rsp = router_0_4_rsp_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_rsp = router_0_4_rsp_out[4]; - - assign router_0_4_to_router_0_5_req = router_0_4_req_out[0]; - assign router_0_4_to_router_1_4_req = router_0_4_req_out[1]; - assign router_0_4_to_router_0_3_req = router_0_4_req_out[2]; - assign router_0_4_to_L2_ni_4_req = router_0_4_req_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_req = router_0_4_req_out[4]; - - assign router_0_4_rsp_in[0] = router_0_5_to_router_0_4_rsp; - assign router_0_4_rsp_in[1] = router_1_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[2] = router_0_3_to_router_0_4_rsp; - assign router_0_4_rsp_in[3] = L2_ni_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[4] = magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_4_req_in), - .floo_rsp_o (router_0_4_rsp_out), - .floo_req_o (router_0_4_req_out), - .floo_rsp_i (router_0_4_rsp_in) -); - - -floo_req_t [4:0] router_0_5_req_in; -floo_rsp_t [4:0] router_0_5_rsp_out; -floo_req_t [4:0] router_0_5_req_out; -floo_rsp_t [4:0] router_0_5_rsp_in; - - assign router_0_5_req_in[0] = router_0_6_to_router_0_5_req; - assign router_0_5_req_in[1] = router_1_5_to_router_0_5_req; - assign router_0_5_req_in[2] = router_0_4_to_router_0_5_req; - assign router_0_5_req_in[3] = L2_ni_5_to_router_0_5_req; - assign router_0_5_req_in[4] = magia_tile_ni_0_5_to_router_0_5_req; - - assign router_0_5_to_router_0_6_rsp = router_0_5_rsp_out[0]; - assign router_0_5_to_router_1_5_rsp = router_0_5_rsp_out[1]; - assign router_0_5_to_router_0_4_rsp = router_0_5_rsp_out[2]; - assign router_0_5_to_L2_ni_5_rsp = router_0_5_rsp_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_rsp = router_0_5_rsp_out[4]; - - assign router_0_5_to_router_0_6_req = router_0_5_req_out[0]; - assign router_0_5_to_router_1_5_req = router_0_5_req_out[1]; - assign router_0_5_to_router_0_4_req = router_0_5_req_out[2]; - assign router_0_5_to_L2_ni_5_req = router_0_5_req_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_req = router_0_5_req_out[4]; - - assign router_0_5_rsp_in[0] = router_0_6_to_router_0_5_rsp; - assign router_0_5_rsp_in[1] = router_1_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[2] = router_0_4_to_router_0_5_rsp; - assign router_0_5_rsp_in[3] = L2_ni_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[4] = magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_5_req_in), - .floo_rsp_o (router_0_5_rsp_out), - .floo_req_o (router_0_5_req_out), - .floo_rsp_i (router_0_5_rsp_in) -); - - -floo_req_t [4:0] router_0_6_req_in; -floo_rsp_t [4:0] router_0_6_rsp_out; -floo_req_t [4:0] router_0_6_req_out; -floo_rsp_t [4:0] router_0_6_rsp_in; - - assign router_0_6_req_in[0] = router_0_7_to_router_0_6_req; - assign router_0_6_req_in[1] = router_1_6_to_router_0_6_req; - assign router_0_6_req_in[2] = router_0_5_to_router_0_6_req; - assign router_0_6_req_in[3] = L2_ni_6_to_router_0_6_req; - assign router_0_6_req_in[4] = magia_tile_ni_0_6_to_router_0_6_req; - - assign router_0_6_to_router_0_7_rsp = router_0_6_rsp_out[0]; - assign router_0_6_to_router_1_6_rsp = router_0_6_rsp_out[1]; - assign router_0_6_to_router_0_5_rsp = router_0_6_rsp_out[2]; - assign router_0_6_to_L2_ni_6_rsp = router_0_6_rsp_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_rsp = router_0_6_rsp_out[4]; - - assign router_0_6_to_router_0_7_req = router_0_6_req_out[0]; - assign router_0_6_to_router_1_6_req = router_0_6_req_out[1]; - assign router_0_6_to_router_0_5_req = router_0_6_req_out[2]; - assign router_0_6_to_L2_ni_6_req = router_0_6_req_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_req = router_0_6_req_out[4]; - - assign router_0_6_rsp_in[0] = router_0_7_to_router_0_6_rsp; - assign router_0_6_rsp_in[1] = router_1_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[2] = router_0_5_to_router_0_6_rsp; - assign router_0_6_rsp_in[3] = L2_ni_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[4] = magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_6_req_in), - .floo_rsp_o (router_0_6_rsp_out), - .floo_req_o (router_0_6_req_out), - .floo_rsp_i (router_0_6_rsp_in) -); - - -floo_req_t [4:0] router_0_7_req_in; -floo_rsp_t [4:0] router_0_7_rsp_out; -floo_req_t [4:0] router_0_7_req_out; -floo_rsp_t [4:0] router_0_7_rsp_in; - - assign router_0_7_req_in[0] = router_0_8_to_router_0_7_req; - assign router_0_7_req_in[1] = router_1_7_to_router_0_7_req; - assign router_0_7_req_in[2] = router_0_6_to_router_0_7_req; - assign router_0_7_req_in[3] = L2_ni_7_to_router_0_7_req; - assign router_0_7_req_in[4] = magia_tile_ni_0_7_to_router_0_7_req; - - assign router_0_7_to_router_0_8_rsp = router_0_7_rsp_out[0]; - assign router_0_7_to_router_1_7_rsp = router_0_7_rsp_out[1]; - assign router_0_7_to_router_0_6_rsp = router_0_7_rsp_out[2]; - assign router_0_7_to_L2_ni_7_rsp = router_0_7_rsp_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_rsp = router_0_7_rsp_out[4]; - - assign router_0_7_to_router_0_8_req = router_0_7_req_out[0]; - assign router_0_7_to_router_1_7_req = router_0_7_req_out[1]; - assign router_0_7_to_router_0_6_req = router_0_7_req_out[2]; - assign router_0_7_to_L2_ni_7_req = router_0_7_req_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_req = router_0_7_req_out[4]; - - assign router_0_7_rsp_in[0] = router_0_8_to_router_0_7_rsp; - assign router_0_7_rsp_in[1] = router_1_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[2] = router_0_6_to_router_0_7_rsp; - assign router_0_7_rsp_in[3] = L2_ni_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[4] = magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_7_req_in), - .floo_rsp_o (router_0_7_rsp_out), - .floo_req_o (router_0_7_req_out), - .floo_rsp_i (router_0_7_rsp_in) -); - - -floo_req_t [4:0] router_0_8_req_in; -floo_rsp_t [4:0] router_0_8_rsp_out; -floo_req_t [4:0] router_0_8_req_out; -floo_rsp_t [4:0] router_0_8_rsp_in; - - assign router_0_8_req_in[0] = router_0_9_to_router_0_8_req; - assign router_0_8_req_in[1] = router_1_8_to_router_0_8_req; - assign router_0_8_req_in[2] = router_0_7_to_router_0_8_req; - assign router_0_8_req_in[3] = L2_ni_8_to_router_0_8_req; - assign router_0_8_req_in[4] = magia_tile_ni_0_8_to_router_0_8_req; - - assign router_0_8_to_router_0_9_rsp = router_0_8_rsp_out[0]; - assign router_0_8_to_router_1_8_rsp = router_0_8_rsp_out[1]; - assign router_0_8_to_router_0_7_rsp = router_0_8_rsp_out[2]; - assign router_0_8_to_L2_ni_8_rsp = router_0_8_rsp_out[3]; - assign router_0_8_to_magia_tile_ni_0_8_rsp = router_0_8_rsp_out[4]; - - assign router_0_8_to_router_0_9_req = router_0_8_req_out[0]; - assign router_0_8_to_router_1_8_req = router_0_8_req_out[1]; - assign router_0_8_to_router_0_7_req = router_0_8_req_out[2]; - assign router_0_8_to_L2_ni_8_req = router_0_8_req_out[3]; - assign router_0_8_to_magia_tile_ni_0_8_req = router_0_8_req_out[4]; - - assign router_0_8_rsp_in[0] = router_0_9_to_router_0_8_rsp; - assign router_0_8_rsp_in[1] = router_1_8_to_router_0_8_rsp; - assign router_0_8_rsp_in[2] = router_0_7_to_router_0_8_rsp; - assign router_0_8_rsp_in[3] = L2_ni_8_to_router_0_8_rsp; - assign router_0_8_rsp_in[4] = magia_tile_ni_0_8_to_router_0_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_8_req_in), - .floo_rsp_o (router_0_8_rsp_out), - .floo_req_o (router_0_8_req_out), - .floo_rsp_i (router_0_8_rsp_in) -); - - -floo_req_t [4:0] router_0_9_req_in; -floo_rsp_t [4:0] router_0_9_rsp_out; -floo_req_t [4:0] router_0_9_req_out; -floo_rsp_t [4:0] router_0_9_rsp_in; - - assign router_0_9_req_in[0] = router_0_10_to_router_0_9_req; - assign router_0_9_req_in[1] = router_1_9_to_router_0_9_req; - assign router_0_9_req_in[2] = router_0_8_to_router_0_9_req; - assign router_0_9_req_in[3] = L2_ni_9_to_router_0_9_req; - assign router_0_9_req_in[4] = magia_tile_ni_0_9_to_router_0_9_req; - - assign router_0_9_to_router_0_10_rsp = router_0_9_rsp_out[0]; - assign router_0_9_to_router_1_9_rsp = router_0_9_rsp_out[1]; - assign router_0_9_to_router_0_8_rsp = router_0_9_rsp_out[2]; - assign router_0_9_to_L2_ni_9_rsp = router_0_9_rsp_out[3]; - assign router_0_9_to_magia_tile_ni_0_9_rsp = router_0_9_rsp_out[4]; - - assign router_0_9_to_router_0_10_req = router_0_9_req_out[0]; - assign router_0_9_to_router_1_9_req = router_0_9_req_out[1]; - assign router_0_9_to_router_0_8_req = router_0_9_req_out[2]; - assign router_0_9_to_L2_ni_9_req = router_0_9_req_out[3]; - assign router_0_9_to_magia_tile_ni_0_9_req = router_0_9_req_out[4]; - - assign router_0_9_rsp_in[0] = router_0_10_to_router_0_9_rsp; - assign router_0_9_rsp_in[1] = router_1_9_to_router_0_9_rsp; - assign router_0_9_rsp_in[2] = router_0_8_to_router_0_9_rsp; - assign router_0_9_rsp_in[3] = L2_ni_9_to_router_0_9_rsp; - assign router_0_9_rsp_in[4] = magia_tile_ni_0_9_to_router_0_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_9_req_in), - .floo_rsp_o (router_0_9_rsp_out), - .floo_req_o (router_0_9_req_out), - .floo_rsp_i (router_0_9_rsp_in) -); - - -floo_req_t [4:0] router_0_10_req_in; -floo_rsp_t [4:0] router_0_10_rsp_out; -floo_req_t [4:0] router_0_10_req_out; -floo_rsp_t [4:0] router_0_10_rsp_in; - - assign router_0_10_req_in[0] = router_0_11_to_router_0_10_req; - assign router_0_10_req_in[1] = router_1_10_to_router_0_10_req; - assign router_0_10_req_in[2] = router_0_9_to_router_0_10_req; - assign router_0_10_req_in[3] = L2_ni_10_to_router_0_10_req; - assign router_0_10_req_in[4] = magia_tile_ni_0_10_to_router_0_10_req; - - assign router_0_10_to_router_0_11_rsp = router_0_10_rsp_out[0]; - assign router_0_10_to_router_1_10_rsp = router_0_10_rsp_out[1]; - assign router_0_10_to_router_0_9_rsp = router_0_10_rsp_out[2]; - assign router_0_10_to_L2_ni_10_rsp = router_0_10_rsp_out[3]; - assign router_0_10_to_magia_tile_ni_0_10_rsp = router_0_10_rsp_out[4]; - - assign router_0_10_to_router_0_11_req = router_0_10_req_out[0]; - assign router_0_10_to_router_1_10_req = router_0_10_req_out[1]; - assign router_0_10_to_router_0_9_req = router_0_10_req_out[2]; - assign router_0_10_to_L2_ni_10_req = router_0_10_req_out[3]; - assign router_0_10_to_magia_tile_ni_0_10_req = router_0_10_req_out[4]; - - assign router_0_10_rsp_in[0] = router_0_11_to_router_0_10_rsp; - assign router_0_10_rsp_in[1] = router_1_10_to_router_0_10_rsp; - assign router_0_10_rsp_in[2] = router_0_9_to_router_0_10_rsp; - assign router_0_10_rsp_in[3] = L2_ni_10_to_router_0_10_rsp; - assign router_0_10_rsp_in[4] = magia_tile_ni_0_10_to_router_0_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_10_req_in), - .floo_rsp_o (router_0_10_rsp_out), - .floo_req_o (router_0_10_req_out), - .floo_rsp_i (router_0_10_rsp_in) -); - - -floo_req_t [4:0] router_0_11_req_in; -floo_rsp_t [4:0] router_0_11_rsp_out; -floo_req_t [4:0] router_0_11_req_out; -floo_rsp_t [4:0] router_0_11_rsp_in; - - assign router_0_11_req_in[0] = router_0_12_to_router_0_11_req; - assign router_0_11_req_in[1] = router_1_11_to_router_0_11_req; - assign router_0_11_req_in[2] = router_0_10_to_router_0_11_req; - assign router_0_11_req_in[3] = L2_ni_11_to_router_0_11_req; - assign router_0_11_req_in[4] = magia_tile_ni_0_11_to_router_0_11_req; - - assign router_0_11_to_router_0_12_rsp = router_0_11_rsp_out[0]; - assign router_0_11_to_router_1_11_rsp = router_0_11_rsp_out[1]; - assign router_0_11_to_router_0_10_rsp = router_0_11_rsp_out[2]; - assign router_0_11_to_L2_ni_11_rsp = router_0_11_rsp_out[3]; - assign router_0_11_to_magia_tile_ni_0_11_rsp = router_0_11_rsp_out[4]; - - assign router_0_11_to_router_0_12_req = router_0_11_req_out[0]; - assign router_0_11_to_router_1_11_req = router_0_11_req_out[1]; - assign router_0_11_to_router_0_10_req = router_0_11_req_out[2]; - assign router_0_11_to_L2_ni_11_req = router_0_11_req_out[3]; - assign router_0_11_to_magia_tile_ni_0_11_req = router_0_11_req_out[4]; - - assign router_0_11_rsp_in[0] = router_0_12_to_router_0_11_rsp; - assign router_0_11_rsp_in[1] = router_1_11_to_router_0_11_rsp; - assign router_0_11_rsp_in[2] = router_0_10_to_router_0_11_rsp; - assign router_0_11_rsp_in[3] = L2_ni_11_to_router_0_11_rsp; - assign router_0_11_rsp_in[4] = magia_tile_ni_0_11_to_router_0_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_11_req_in), - .floo_rsp_o (router_0_11_rsp_out), - .floo_req_o (router_0_11_req_out), - .floo_rsp_i (router_0_11_rsp_in) -); - - -floo_req_t [4:0] router_0_12_req_in; -floo_rsp_t [4:0] router_0_12_rsp_out; -floo_req_t [4:0] router_0_12_req_out; -floo_rsp_t [4:0] router_0_12_rsp_in; - - assign router_0_12_req_in[0] = router_0_13_to_router_0_12_req; - assign router_0_12_req_in[1] = router_1_12_to_router_0_12_req; - assign router_0_12_req_in[2] = router_0_11_to_router_0_12_req; - assign router_0_12_req_in[3] = L2_ni_12_to_router_0_12_req; - assign router_0_12_req_in[4] = magia_tile_ni_0_12_to_router_0_12_req; - - assign router_0_12_to_router_0_13_rsp = router_0_12_rsp_out[0]; - assign router_0_12_to_router_1_12_rsp = router_0_12_rsp_out[1]; - assign router_0_12_to_router_0_11_rsp = router_0_12_rsp_out[2]; - assign router_0_12_to_L2_ni_12_rsp = router_0_12_rsp_out[3]; - assign router_0_12_to_magia_tile_ni_0_12_rsp = router_0_12_rsp_out[4]; - - assign router_0_12_to_router_0_13_req = router_0_12_req_out[0]; - assign router_0_12_to_router_1_12_req = router_0_12_req_out[1]; - assign router_0_12_to_router_0_11_req = router_0_12_req_out[2]; - assign router_0_12_to_L2_ni_12_req = router_0_12_req_out[3]; - assign router_0_12_to_magia_tile_ni_0_12_req = router_0_12_req_out[4]; - - assign router_0_12_rsp_in[0] = router_0_13_to_router_0_12_rsp; - assign router_0_12_rsp_in[1] = router_1_12_to_router_0_12_rsp; - assign router_0_12_rsp_in[2] = router_0_11_to_router_0_12_rsp; - assign router_0_12_rsp_in[3] = L2_ni_12_to_router_0_12_rsp; - assign router_0_12_rsp_in[4] = magia_tile_ni_0_12_to_router_0_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_12_req_in), - .floo_rsp_o (router_0_12_rsp_out), - .floo_req_o (router_0_12_req_out), - .floo_rsp_i (router_0_12_rsp_in) -); - - -floo_req_t [4:0] router_0_13_req_in; -floo_rsp_t [4:0] router_0_13_rsp_out; -floo_req_t [4:0] router_0_13_req_out; -floo_rsp_t [4:0] router_0_13_rsp_in; - - assign router_0_13_req_in[0] = router_0_14_to_router_0_13_req; - assign router_0_13_req_in[1] = router_1_13_to_router_0_13_req; - assign router_0_13_req_in[2] = router_0_12_to_router_0_13_req; - assign router_0_13_req_in[3] = L2_ni_13_to_router_0_13_req; - assign router_0_13_req_in[4] = magia_tile_ni_0_13_to_router_0_13_req; - - assign router_0_13_to_router_0_14_rsp = router_0_13_rsp_out[0]; - assign router_0_13_to_router_1_13_rsp = router_0_13_rsp_out[1]; - assign router_0_13_to_router_0_12_rsp = router_0_13_rsp_out[2]; - assign router_0_13_to_L2_ni_13_rsp = router_0_13_rsp_out[3]; - assign router_0_13_to_magia_tile_ni_0_13_rsp = router_0_13_rsp_out[4]; - - assign router_0_13_to_router_0_14_req = router_0_13_req_out[0]; - assign router_0_13_to_router_1_13_req = router_0_13_req_out[1]; - assign router_0_13_to_router_0_12_req = router_0_13_req_out[2]; - assign router_0_13_to_L2_ni_13_req = router_0_13_req_out[3]; - assign router_0_13_to_magia_tile_ni_0_13_req = router_0_13_req_out[4]; - - assign router_0_13_rsp_in[0] = router_0_14_to_router_0_13_rsp; - assign router_0_13_rsp_in[1] = router_1_13_to_router_0_13_rsp; - assign router_0_13_rsp_in[2] = router_0_12_to_router_0_13_rsp; - assign router_0_13_rsp_in[3] = L2_ni_13_to_router_0_13_rsp; - assign router_0_13_rsp_in[4] = magia_tile_ni_0_13_to_router_0_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_13_req_in), - .floo_rsp_o (router_0_13_rsp_out), - .floo_req_o (router_0_13_req_out), - .floo_rsp_i (router_0_13_rsp_in) -); - - -floo_req_t [4:0] router_0_14_req_in; -floo_rsp_t [4:0] router_0_14_rsp_out; -floo_req_t [4:0] router_0_14_req_out; -floo_rsp_t [4:0] router_0_14_rsp_in; - - assign router_0_14_req_in[0] = router_0_15_to_router_0_14_req; - assign router_0_14_req_in[1] = router_1_14_to_router_0_14_req; - assign router_0_14_req_in[2] = router_0_13_to_router_0_14_req; - assign router_0_14_req_in[3] = L2_ni_14_to_router_0_14_req; - assign router_0_14_req_in[4] = magia_tile_ni_0_14_to_router_0_14_req; - - assign router_0_14_to_router_0_15_rsp = router_0_14_rsp_out[0]; - assign router_0_14_to_router_1_14_rsp = router_0_14_rsp_out[1]; - assign router_0_14_to_router_0_13_rsp = router_0_14_rsp_out[2]; - assign router_0_14_to_L2_ni_14_rsp = router_0_14_rsp_out[3]; - assign router_0_14_to_magia_tile_ni_0_14_rsp = router_0_14_rsp_out[4]; - - assign router_0_14_to_router_0_15_req = router_0_14_req_out[0]; - assign router_0_14_to_router_1_14_req = router_0_14_req_out[1]; - assign router_0_14_to_router_0_13_req = router_0_14_req_out[2]; - assign router_0_14_to_L2_ni_14_req = router_0_14_req_out[3]; - assign router_0_14_to_magia_tile_ni_0_14_req = router_0_14_req_out[4]; - - assign router_0_14_rsp_in[0] = router_0_15_to_router_0_14_rsp; - assign router_0_14_rsp_in[1] = router_1_14_to_router_0_14_rsp; - assign router_0_14_rsp_in[2] = router_0_13_to_router_0_14_rsp; - assign router_0_14_rsp_in[3] = L2_ni_14_to_router_0_14_rsp; - assign router_0_14_rsp_in[4] = magia_tile_ni_0_14_to_router_0_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_14_req_in), - .floo_rsp_o (router_0_14_rsp_out), - .floo_req_o (router_0_14_req_out), - .floo_rsp_i (router_0_14_rsp_in) -); - - -floo_req_t [4:0] router_0_15_req_in; -floo_rsp_t [4:0] router_0_15_rsp_out; -floo_req_t [4:0] router_0_15_req_out; -floo_rsp_t [4:0] router_0_15_rsp_in; - - assign router_0_15_req_in[0] = '0; - assign router_0_15_req_in[1] = router_1_15_to_router_0_15_req; - assign router_0_15_req_in[2] = router_0_14_to_router_0_15_req; - assign router_0_15_req_in[3] = L2_ni_15_to_router_0_15_req; - assign router_0_15_req_in[4] = magia_tile_ni_0_15_to_router_0_15_req; - - assign router_0_15_to_router_1_15_rsp = router_0_15_rsp_out[1]; - assign router_0_15_to_router_0_14_rsp = router_0_15_rsp_out[2]; - assign router_0_15_to_L2_ni_15_rsp = router_0_15_rsp_out[3]; - assign router_0_15_to_magia_tile_ni_0_15_rsp = router_0_15_rsp_out[4]; - - assign router_0_15_to_router_1_15_req = router_0_15_req_out[1]; - assign router_0_15_to_router_0_14_req = router_0_15_req_out[2]; - assign router_0_15_to_L2_ni_15_req = router_0_15_req_out[3]; - assign router_0_15_to_magia_tile_ni_0_15_req = router_0_15_req_out[4]; - - assign router_0_15_rsp_in[0] = '0; - assign router_0_15_rsp_in[1] = router_1_15_to_router_0_15_rsp; - assign router_0_15_rsp_in[2] = router_0_14_to_router_0_15_rsp; - assign router_0_15_rsp_in[3] = L2_ni_15_to_router_0_15_rsp; - assign router_0_15_rsp_in[4] = magia_tile_ni_0_15_to_router_0_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_15_req_in), - .floo_rsp_o (router_0_15_rsp_out), - .floo_req_o (router_0_15_req_out), - .floo_rsp_i (router_0_15_rsp_in) -); - - -floo_req_t [4:0] router_1_0_req_in; -floo_rsp_t [4:0] router_1_0_rsp_out; -floo_req_t [4:0] router_1_0_req_out; -floo_rsp_t [4:0] router_1_0_rsp_in; - - assign router_1_0_req_in[0] = router_1_1_to_router_1_0_req; - assign router_1_0_req_in[1] = router_2_0_to_router_1_0_req; - assign router_1_0_req_in[2] = '0; - assign router_1_0_req_in[3] = router_0_0_to_router_1_0_req; - assign router_1_0_req_in[4] = magia_tile_ni_1_0_to_router_1_0_req; - - assign router_1_0_to_router_1_1_rsp = router_1_0_rsp_out[0]; - assign router_1_0_to_router_2_0_rsp = router_1_0_rsp_out[1]; - assign router_1_0_to_router_0_0_rsp = router_1_0_rsp_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_rsp = router_1_0_rsp_out[4]; - - assign router_1_0_to_router_1_1_req = router_1_0_req_out[0]; - assign router_1_0_to_router_2_0_req = router_1_0_req_out[1]; - assign router_1_0_to_router_0_0_req = router_1_0_req_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_req = router_1_0_req_out[4]; - - assign router_1_0_rsp_in[0] = router_1_1_to_router_1_0_rsp; - assign router_1_0_rsp_in[1] = router_2_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[2] = '0; - assign router_1_0_rsp_in[3] = router_0_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[4] = magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_0_req_in), - .floo_rsp_o (router_1_0_rsp_out), - .floo_req_o (router_1_0_req_out), - .floo_rsp_i (router_1_0_rsp_in) -); - - -floo_req_t [4:0] router_1_1_req_in; -floo_rsp_t [4:0] router_1_1_rsp_out; -floo_req_t [4:0] router_1_1_req_out; -floo_rsp_t [4:0] router_1_1_rsp_in; - - assign router_1_1_req_in[0] = router_1_2_to_router_1_1_req; - assign router_1_1_req_in[1] = router_2_1_to_router_1_1_req; - assign router_1_1_req_in[2] = router_1_0_to_router_1_1_req; - assign router_1_1_req_in[3] = router_0_1_to_router_1_1_req; - assign router_1_1_req_in[4] = magia_tile_ni_1_1_to_router_1_1_req; - - assign router_1_1_to_router_1_2_rsp = router_1_1_rsp_out[0]; - assign router_1_1_to_router_2_1_rsp = router_1_1_rsp_out[1]; - assign router_1_1_to_router_1_0_rsp = router_1_1_rsp_out[2]; - assign router_1_1_to_router_0_1_rsp = router_1_1_rsp_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_rsp = router_1_1_rsp_out[4]; - - assign router_1_1_to_router_1_2_req = router_1_1_req_out[0]; - assign router_1_1_to_router_2_1_req = router_1_1_req_out[1]; - assign router_1_1_to_router_1_0_req = router_1_1_req_out[2]; - assign router_1_1_to_router_0_1_req = router_1_1_req_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_req = router_1_1_req_out[4]; - - assign router_1_1_rsp_in[0] = router_1_2_to_router_1_1_rsp; - assign router_1_1_rsp_in[1] = router_2_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[2] = router_1_0_to_router_1_1_rsp; - assign router_1_1_rsp_in[3] = router_0_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[4] = magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_1_req_in), - .floo_rsp_o (router_1_1_rsp_out), - .floo_req_o (router_1_1_req_out), - .floo_rsp_i (router_1_1_rsp_in) -); - - -floo_req_t [4:0] router_1_2_req_in; -floo_rsp_t [4:0] router_1_2_rsp_out; -floo_req_t [4:0] router_1_2_req_out; -floo_rsp_t [4:0] router_1_2_rsp_in; - - assign router_1_2_req_in[0] = router_1_3_to_router_1_2_req; - assign router_1_2_req_in[1] = router_2_2_to_router_1_2_req; - assign router_1_2_req_in[2] = router_1_1_to_router_1_2_req; - assign router_1_2_req_in[3] = router_0_2_to_router_1_2_req; - assign router_1_2_req_in[4] = magia_tile_ni_1_2_to_router_1_2_req; - - assign router_1_2_to_router_1_3_rsp = router_1_2_rsp_out[0]; - assign router_1_2_to_router_2_2_rsp = router_1_2_rsp_out[1]; - assign router_1_2_to_router_1_1_rsp = router_1_2_rsp_out[2]; - assign router_1_2_to_router_0_2_rsp = router_1_2_rsp_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_rsp = router_1_2_rsp_out[4]; - - assign router_1_2_to_router_1_3_req = router_1_2_req_out[0]; - assign router_1_2_to_router_2_2_req = router_1_2_req_out[1]; - assign router_1_2_to_router_1_1_req = router_1_2_req_out[2]; - assign router_1_2_to_router_0_2_req = router_1_2_req_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_req = router_1_2_req_out[4]; - - assign router_1_2_rsp_in[0] = router_1_3_to_router_1_2_rsp; - assign router_1_2_rsp_in[1] = router_2_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[2] = router_1_1_to_router_1_2_rsp; - assign router_1_2_rsp_in[3] = router_0_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[4] = magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_2_req_in), - .floo_rsp_o (router_1_2_rsp_out), - .floo_req_o (router_1_2_req_out), - .floo_rsp_i (router_1_2_rsp_in) -); - - -floo_req_t [4:0] router_1_3_req_in; -floo_rsp_t [4:0] router_1_3_rsp_out; -floo_req_t [4:0] router_1_3_req_out; -floo_rsp_t [4:0] router_1_3_rsp_in; - - assign router_1_3_req_in[0] = router_1_4_to_router_1_3_req; - assign router_1_3_req_in[1] = router_2_3_to_router_1_3_req; - assign router_1_3_req_in[2] = router_1_2_to_router_1_3_req; - assign router_1_3_req_in[3] = router_0_3_to_router_1_3_req; - assign router_1_3_req_in[4] = magia_tile_ni_1_3_to_router_1_3_req; - - assign router_1_3_to_router_1_4_rsp = router_1_3_rsp_out[0]; - assign router_1_3_to_router_2_3_rsp = router_1_3_rsp_out[1]; - assign router_1_3_to_router_1_2_rsp = router_1_3_rsp_out[2]; - assign router_1_3_to_router_0_3_rsp = router_1_3_rsp_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_rsp = router_1_3_rsp_out[4]; - - assign router_1_3_to_router_1_4_req = router_1_3_req_out[0]; - assign router_1_3_to_router_2_3_req = router_1_3_req_out[1]; - assign router_1_3_to_router_1_2_req = router_1_3_req_out[2]; - assign router_1_3_to_router_0_3_req = router_1_3_req_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_req = router_1_3_req_out[4]; - - assign router_1_3_rsp_in[0] = router_1_4_to_router_1_3_rsp; - assign router_1_3_rsp_in[1] = router_2_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[2] = router_1_2_to_router_1_3_rsp; - assign router_1_3_rsp_in[3] = router_0_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[4] = magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_3_req_in), - .floo_rsp_o (router_1_3_rsp_out), - .floo_req_o (router_1_3_req_out), - .floo_rsp_i (router_1_3_rsp_in) -); - - -floo_req_t [4:0] router_1_4_req_in; -floo_rsp_t [4:0] router_1_4_rsp_out; -floo_req_t [4:0] router_1_4_req_out; -floo_rsp_t [4:0] router_1_4_rsp_in; - - assign router_1_4_req_in[0] = router_1_5_to_router_1_4_req; - assign router_1_4_req_in[1] = router_2_4_to_router_1_4_req; - assign router_1_4_req_in[2] = router_1_3_to_router_1_4_req; - assign router_1_4_req_in[3] = router_0_4_to_router_1_4_req; - assign router_1_4_req_in[4] = magia_tile_ni_1_4_to_router_1_4_req; - - assign router_1_4_to_router_1_5_rsp = router_1_4_rsp_out[0]; - assign router_1_4_to_router_2_4_rsp = router_1_4_rsp_out[1]; - assign router_1_4_to_router_1_3_rsp = router_1_4_rsp_out[2]; - assign router_1_4_to_router_0_4_rsp = router_1_4_rsp_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_rsp = router_1_4_rsp_out[4]; - - assign router_1_4_to_router_1_5_req = router_1_4_req_out[0]; - assign router_1_4_to_router_2_4_req = router_1_4_req_out[1]; - assign router_1_4_to_router_1_3_req = router_1_4_req_out[2]; - assign router_1_4_to_router_0_4_req = router_1_4_req_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_req = router_1_4_req_out[4]; - - assign router_1_4_rsp_in[0] = router_1_5_to_router_1_4_rsp; - assign router_1_4_rsp_in[1] = router_2_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[2] = router_1_3_to_router_1_4_rsp; - assign router_1_4_rsp_in[3] = router_0_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[4] = magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_4_req_in), - .floo_rsp_o (router_1_4_rsp_out), - .floo_req_o (router_1_4_req_out), - .floo_rsp_i (router_1_4_rsp_in) -); - - -floo_req_t [4:0] router_1_5_req_in; -floo_rsp_t [4:0] router_1_5_rsp_out; -floo_req_t [4:0] router_1_5_req_out; -floo_rsp_t [4:0] router_1_5_rsp_in; - - assign router_1_5_req_in[0] = router_1_6_to_router_1_5_req; - assign router_1_5_req_in[1] = router_2_5_to_router_1_5_req; - assign router_1_5_req_in[2] = router_1_4_to_router_1_5_req; - assign router_1_5_req_in[3] = router_0_5_to_router_1_5_req; - assign router_1_5_req_in[4] = magia_tile_ni_1_5_to_router_1_5_req; - - assign router_1_5_to_router_1_6_rsp = router_1_5_rsp_out[0]; - assign router_1_5_to_router_2_5_rsp = router_1_5_rsp_out[1]; - assign router_1_5_to_router_1_4_rsp = router_1_5_rsp_out[2]; - assign router_1_5_to_router_0_5_rsp = router_1_5_rsp_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_rsp = router_1_5_rsp_out[4]; - - assign router_1_5_to_router_1_6_req = router_1_5_req_out[0]; - assign router_1_5_to_router_2_5_req = router_1_5_req_out[1]; - assign router_1_5_to_router_1_4_req = router_1_5_req_out[2]; - assign router_1_5_to_router_0_5_req = router_1_5_req_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_req = router_1_5_req_out[4]; - - assign router_1_5_rsp_in[0] = router_1_6_to_router_1_5_rsp; - assign router_1_5_rsp_in[1] = router_2_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[2] = router_1_4_to_router_1_5_rsp; - assign router_1_5_rsp_in[3] = router_0_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[4] = magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_5_req_in), - .floo_rsp_o (router_1_5_rsp_out), - .floo_req_o (router_1_5_req_out), - .floo_rsp_i (router_1_5_rsp_in) -); - - -floo_req_t [4:0] router_1_6_req_in; -floo_rsp_t [4:0] router_1_6_rsp_out; -floo_req_t [4:0] router_1_6_req_out; -floo_rsp_t [4:0] router_1_6_rsp_in; - - assign router_1_6_req_in[0] = router_1_7_to_router_1_6_req; - assign router_1_6_req_in[1] = router_2_6_to_router_1_6_req; - assign router_1_6_req_in[2] = router_1_5_to_router_1_6_req; - assign router_1_6_req_in[3] = router_0_6_to_router_1_6_req; - assign router_1_6_req_in[4] = magia_tile_ni_1_6_to_router_1_6_req; - - assign router_1_6_to_router_1_7_rsp = router_1_6_rsp_out[0]; - assign router_1_6_to_router_2_6_rsp = router_1_6_rsp_out[1]; - assign router_1_6_to_router_1_5_rsp = router_1_6_rsp_out[2]; - assign router_1_6_to_router_0_6_rsp = router_1_6_rsp_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_rsp = router_1_6_rsp_out[4]; - - assign router_1_6_to_router_1_7_req = router_1_6_req_out[0]; - assign router_1_6_to_router_2_6_req = router_1_6_req_out[1]; - assign router_1_6_to_router_1_5_req = router_1_6_req_out[2]; - assign router_1_6_to_router_0_6_req = router_1_6_req_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_req = router_1_6_req_out[4]; - - assign router_1_6_rsp_in[0] = router_1_7_to_router_1_6_rsp; - assign router_1_6_rsp_in[1] = router_2_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[2] = router_1_5_to_router_1_6_rsp; - assign router_1_6_rsp_in[3] = router_0_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[4] = magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_6_req_in), - .floo_rsp_o (router_1_6_rsp_out), - .floo_req_o (router_1_6_req_out), - .floo_rsp_i (router_1_6_rsp_in) -); - - -floo_req_t [4:0] router_1_7_req_in; -floo_rsp_t [4:0] router_1_7_rsp_out; -floo_req_t [4:0] router_1_7_req_out; -floo_rsp_t [4:0] router_1_7_rsp_in; - - assign router_1_7_req_in[0] = router_1_8_to_router_1_7_req; - assign router_1_7_req_in[1] = router_2_7_to_router_1_7_req; - assign router_1_7_req_in[2] = router_1_6_to_router_1_7_req; - assign router_1_7_req_in[3] = router_0_7_to_router_1_7_req; - assign router_1_7_req_in[4] = magia_tile_ni_1_7_to_router_1_7_req; - - assign router_1_7_to_router_1_8_rsp = router_1_7_rsp_out[0]; - assign router_1_7_to_router_2_7_rsp = router_1_7_rsp_out[1]; - assign router_1_7_to_router_1_6_rsp = router_1_7_rsp_out[2]; - assign router_1_7_to_router_0_7_rsp = router_1_7_rsp_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_rsp = router_1_7_rsp_out[4]; - - assign router_1_7_to_router_1_8_req = router_1_7_req_out[0]; - assign router_1_7_to_router_2_7_req = router_1_7_req_out[1]; - assign router_1_7_to_router_1_6_req = router_1_7_req_out[2]; - assign router_1_7_to_router_0_7_req = router_1_7_req_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_req = router_1_7_req_out[4]; - - assign router_1_7_rsp_in[0] = router_1_8_to_router_1_7_rsp; - assign router_1_7_rsp_in[1] = router_2_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[2] = router_1_6_to_router_1_7_rsp; - assign router_1_7_rsp_in[3] = router_0_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[4] = magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_7_req_in), - .floo_rsp_o (router_1_7_rsp_out), - .floo_req_o (router_1_7_req_out), - .floo_rsp_i (router_1_7_rsp_in) -); - - -floo_req_t [4:0] router_1_8_req_in; -floo_rsp_t [4:0] router_1_8_rsp_out; -floo_req_t [4:0] router_1_8_req_out; -floo_rsp_t [4:0] router_1_8_rsp_in; - - assign router_1_8_req_in[0] = router_1_9_to_router_1_8_req; - assign router_1_8_req_in[1] = router_2_8_to_router_1_8_req; - assign router_1_8_req_in[2] = router_1_7_to_router_1_8_req; - assign router_1_8_req_in[3] = router_0_8_to_router_1_8_req; - assign router_1_8_req_in[4] = magia_tile_ni_1_8_to_router_1_8_req; - - assign router_1_8_to_router_1_9_rsp = router_1_8_rsp_out[0]; - assign router_1_8_to_router_2_8_rsp = router_1_8_rsp_out[1]; - assign router_1_8_to_router_1_7_rsp = router_1_8_rsp_out[2]; - assign router_1_8_to_router_0_8_rsp = router_1_8_rsp_out[3]; - assign router_1_8_to_magia_tile_ni_1_8_rsp = router_1_8_rsp_out[4]; - - assign router_1_8_to_router_1_9_req = router_1_8_req_out[0]; - assign router_1_8_to_router_2_8_req = router_1_8_req_out[1]; - assign router_1_8_to_router_1_7_req = router_1_8_req_out[2]; - assign router_1_8_to_router_0_8_req = router_1_8_req_out[3]; - assign router_1_8_to_magia_tile_ni_1_8_req = router_1_8_req_out[4]; - - assign router_1_8_rsp_in[0] = router_1_9_to_router_1_8_rsp; - assign router_1_8_rsp_in[1] = router_2_8_to_router_1_8_rsp; - assign router_1_8_rsp_in[2] = router_1_7_to_router_1_8_rsp; - assign router_1_8_rsp_in[3] = router_0_8_to_router_1_8_rsp; - assign router_1_8_rsp_in[4] = magia_tile_ni_1_8_to_router_1_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_8_req_in), - .floo_rsp_o (router_1_8_rsp_out), - .floo_req_o (router_1_8_req_out), - .floo_rsp_i (router_1_8_rsp_in) -); - - -floo_req_t [4:0] router_1_9_req_in; -floo_rsp_t [4:0] router_1_9_rsp_out; -floo_req_t [4:0] router_1_9_req_out; -floo_rsp_t [4:0] router_1_9_rsp_in; - - assign router_1_9_req_in[0] = router_1_10_to_router_1_9_req; - assign router_1_9_req_in[1] = router_2_9_to_router_1_9_req; - assign router_1_9_req_in[2] = router_1_8_to_router_1_9_req; - assign router_1_9_req_in[3] = router_0_9_to_router_1_9_req; - assign router_1_9_req_in[4] = magia_tile_ni_1_9_to_router_1_9_req; - - assign router_1_9_to_router_1_10_rsp = router_1_9_rsp_out[0]; - assign router_1_9_to_router_2_9_rsp = router_1_9_rsp_out[1]; - assign router_1_9_to_router_1_8_rsp = router_1_9_rsp_out[2]; - assign router_1_9_to_router_0_9_rsp = router_1_9_rsp_out[3]; - assign router_1_9_to_magia_tile_ni_1_9_rsp = router_1_9_rsp_out[4]; - - assign router_1_9_to_router_1_10_req = router_1_9_req_out[0]; - assign router_1_9_to_router_2_9_req = router_1_9_req_out[1]; - assign router_1_9_to_router_1_8_req = router_1_9_req_out[2]; - assign router_1_9_to_router_0_9_req = router_1_9_req_out[3]; - assign router_1_9_to_magia_tile_ni_1_9_req = router_1_9_req_out[4]; - - assign router_1_9_rsp_in[0] = router_1_10_to_router_1_9_rsp; - assign router_1_9_rsp_in[1] = router_2_9_to_router_1_9_rsp; - assign router_1_9_rsp_in[2] = router_1_8_to_router_1_9_rsp; - assign router_1_9_rsp_in[3] = router_0_9_to_router_1_9_rsp; - assign router_1_9_rsp_in[4] = magia_tile_ni_1_9_to_router_1_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_9_req_in), - .floo_rsp_o (router_1_9_rsp_out), - .floo_req_o (router_1_9_req_out), - .floo_rsp_i (router_1_9_rsp_in) -); - - -floo_req_t [4:0] router_1_10_req_in; -floo_rsp_t [4:0] router_1_10_rsp_out; -floo_req_t [4:0] router_1_10_req_out; -floo_rsp_t [4:0] router_1_10_rsp_in; - - assign router_1_10_req_in[0] = router_1_11_to_router_1_10_req; - assign router_1_10_req_in[1] = router_2_10_to_router_1_10_req; - assign router_1_10_req_in[2] = router_1_9_to_router_1_10_req; - assign router_1_10_req_in[3] = router_0_10_to_router_1_10_req; - assign router_1_10_req_in[4] = magia_tile_ni_1_10_to_router_1_10_req; - - assign router_1_10_to_router_1_11_rsp = router_1_10_rsp_out[0]; - assign router_1_10_to_router_2_10_rsp = router_1_10_rsp_out[1]; - assign router_1_10_to_router_1_9_rsp = router_1_10_rsp_out[2]; - assign router_1_10_to_router_0_10_rsp = router_1_10_rsp_out[3]; - assign router_1_10_to_magia_tile_ni_1_10_rsp = router_1_10_rsp_out[4]; - - assign router_1_10_to_router_1_11_req = router_1_10_req_out[0]; - assign router_1_10_to_router_2_10_req = router_1_10_req_out[1]; - assign router_1_10_to_router_1_9_req = router_1_10_req_out[2]; - assign router_1_10_to_router_0_10_req = router_1_10_req_out[3]; - assign router_1_10_to_magia_tile_ni_1_10_req = router_1_10_req_out[4]; - - assign router_1_10_rsp_in[0] = router_1_11_to_router_1_10_rsp; - assign router_1_10_rsp_in[1] = router_2_10_to_router_1_10_rsp; - assign router_1_10_rsp_in[2] = router_1_9_to_router_1_10_rsp; - assign router_1_10_rsp_in[3] = router_0_10_to_router_1_10_rsp; - assign router_1_10_rsp_in[4] = magia_tile_ni_1_10_to_router_1_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_10_req_in), - .floo_rsp_o (router_1_10_rsp_out), - .floo_req_o (router_1_10_req_out), - .floo_rsp_i (router_1_10_rsp_in) -); - - -floo_req_t [4:0] router_1_11_req_in; -floo_rsp_t [4:0] router_1_11_rsp_out; -floo_req_t [4:0] router_1_11_req_out; -floo_rsp_t [4:0] router_1_11_rsp_in; - - assign router_1_11_req_in[0] = router_1_12_to_router_1_11_req; - assign router_1_11_req_in[1] = router_2_11_to_router_1_11_req; - assign router_1_11_req_in[2] = router_1_10_to_router_1_11_req; - assign router_1_11_req_in[3] = router_0_11_to_router_1_11_req; - assign router_1_11_req_in[4] = magia_tile_ni_1_11_to_router_1_11_req; - - assign router_1_11_to_router_1_12_rsp = router_1_11_rsp_out[0]; - assign router_1_11_to_router_2_11_rsp = router_1_11_rsp_out[1]; - assign router_1_11_to_router_1_10_rsp = router_1_11_rsp_out[2]; - assign router_1_11_to_router_0_11_rsp = router_1_11_rsp_out[3]; - assign router_1_11_to_magia_tile_ni_1_11_rsp = router_1_11_rsp_out[4]; - - assign router_1_11_to_router_1_12_req = router_1_11_req_out[0]; - assign router_1_11_to_router_2_11_req = router_1_11_req_out[1]; - assign router_1_11_to_router_1_10_req = router_1_11_req_out[2]; - assign router_1_11_to_router_0_11_req = router_1_11_req_out[3]; - assign router_1_11_to_magia_tile_ni_1_11_req = router_1_11_req_out[4]; - - assign router_1_11_rsp_in[0] = router_1_12_to_router_1_11_rsp; - assign router_1_11_rsp_in[1] = router_2_11_to_router_1_11_rsp; - assign router_1_11_rsp_in[2] = router_1_10_to_router_1_11_rsp; - assign router_1_11_rsp_in[3] = router_0_11_to_router_1_11_rsp; - assign router_1_11_rsp_in[4] = magia_tile_ni_1_11_to_router_1_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_11_req_in), - .floo_rsp_o (router_1_11_rsp_out), - .floo_req_o (router_1_11_req_out), - .floo_rsp_i (router_1_11_rsp_in) -); - - -floo_req_t [4:0] router_1_12_req_in; -floo_rsp_t [4:0] router_1_12_rsp_out; -floo_req_t [4:0] router_1_12_req_out; -floo_rsp_t [4:0] router_1_12_rsp_in; - - assign router_1_12_req_in[0] = router_1_13_to_router_1_12_req; - assign router_1_12_req_in[1] = router_2_12_to_router_1_12_req; - assign router_1_12_req_in[2] = router_1_11_to_router_1_12_req; - assign router_1_12_req_in[3] = router_0_12_to_router_1_12_req; - assign router_1_12_req_in[4] = magia_tile_ni_1_12_to_router_1_12_req; - - assign router_1_12_to_router_1_13_rsp = router_1_12_rsp_out[0]; - assign router_1_12_to_router_2_12_rsp = router_1_12_rsp_out[1]; - assign router_1_12_to_router_1_11_rsp = router_1_12_rsp_out[2]; - assign router_1_12_to_router_0_12_rsp = router_1_12_rsp_out[3]; - assign router_1_12_to_magia_tile_ni_1_12_rsp = router_1_12_rsp_out[4]; - - assign router_1_12_to_router_1_13_req = router_1_12_req_out[0]; - assign router_1_12_to_router_2_12_req = router_1_12_req_out[1]; - assign router_1_12_to_router_1_11_req = router_1_12_req_out[2]; - assign router_1_12_to_router_0_12_req = router_1_12_req_out[3]; - assign router_1_12_to_magia_tile_ni_1_12_req = router_1_12_req_out[4]; - - assign router_1_12_rsp_in[0] = router_1_13_to_router_1_12_rsp; - assign router_1_12_rsp_in[1] = router_2_12_to_router_1_12_rsp; - assign router_1_12_rsp_in[2] = router_1_11_to_router_1_12_rsp; - assign router_1_12_rsp_in[3] = router_0_12_to_router_1_12_rsp; - assign router_1_12_rsp_in[4] = magia_tile_ni_1_12_to_router_1_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_12_req_in), - .floo_rsp_o (router_1_12_rsp_out), - .floo_req_o (router_1_12_req_out), - .floo_rsp_i (router_1_12_rsp_in) -); - - -floo_req_t [4:0] router_1_13_req_in; -floo_rsp_t [4:0] router_1_13_rsp_out; -floo_req_t [4:0] router_1_13_req_out; -floo_rsp_t [4:0] router_1_13_rsp_in; - - assign router_1_13_req_in[0] = router_1_14_to_router_1_13_req; - assign router_1_13_req_in[1] = router_2_13_to_router_1_13_req; - assign router_1_13_req_in[2] = router_1_12_to_router_1_13_req; - assign router_1_13_req_in[3] = router_0_13_to_router_1_13_req; - assign router_1_13_req_in[4] = magia_tile_ni_1_13_to_router_1_13_req; - - assign router_1_13_to_router_1_14_rsp = router_1_13_rsp_out[0]; - assign router_1_13_to_router_2_13_rsp = router_1_13_rsp_out[1]; - assign router_1_13_to_router_1_12_rsp = router_1_13_rsp_out[2]; - assign router_1_13_to_router_0_13_rsp = router_1_13_rsp_out[3]; - assign router_1_13_to_magia_tile_ni_1_13_rsp = router_1_13_rsp_out[4]; - - assign router_1_13_to_router_1_14_req = router_1_13_req_out[0]; - assign router_1_13_to_router_2_13_req = router_1_13_req_out[1]; - assign router_1_13_to_router_1_12_req = router_1_13_req_out[2]; - assign router_1_13_to_router_0_13_req = router_1_13_req_out[3]; - assign router_1_13_to_magia_tile_ni_1_13_req = router_1_13_req_out[4]; - - assign router_1_13_rsp_in[0] = router_1_14_to_router_1_13_rsp; - assign router_1_13_rsp_in[1] = router_2_13_to_router_1_13_rsp; - assign router_1_13_rsp_in[2] = router_1_12_to_router_1_13_rsp; - assign router_1_13_rsp_in[3] = router_0_13_to_router_1_13_rsp; - assign router_1_13_rsp_in[4] = magia_tile_ni_1_13_to_router_1_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_13_req_in), - .floo_rsp_o (router_1_13_rsp_out), - .floo_req_o (router_1_13_req_out), - .floo_rsp_i (router_1_13_rsp_in) -); - - -floo_req_t [4:0] router_1_14_req_in; -floo_rsp_t [4:0] router_1_14_rsp_out; -floo_req_t [4:0] router_1_14_req_out; -floo_rsp_t [4:0] router_1_14_rsp_in; - - assign router_1_14_req_in[0] = router_1_15_to_router_1_14_req; - assign router_1_14_req_in[1] = router_2_14_to_router_1_14_req; - assign router_1_14_req_in[2] = router_1_13_to_router_1_14_req; - assign router_1_14_req_in[3] = router_0_14_to_router_1_14_req; - assign router_1_14_req_in[4] = magia_tile_ni_1_14_to_router_1_14_req; - - assign router_1_14_to_router_1_15_rsp = router_1_14_rsp_out[0]; - assign router_1_14_to_router_2_14_rsp = router_1_14_rsp_out[1]; - assign router_1_14_to_router_1_13_rsp = router_1_14_rsp_out[2]; - assign router_1_14_to_router_0_14_rsp = router_1_14_rsp_out[3]; - assign router_1_14_to_magia_tile_ni_1_14_rsp = router_1_14_rsp_out[4]; - - assign router_1_14_to_router_1_15_req = router_1_14_req_out[0]; - assign router_1_14_to_router_2_14_req = router_1_14_req_out[1]; - assign router_1_14_to_router_1_13_req = router_1_14_req_out[2]; - assign router_1_14_to_router_0_14_req = router_1_14_req_out[3]; - assign router_1_14_to_magia_tile_ni_1_14_req = router_1_14_req_out[4]; - - assign router_1_14_rsp_in[0] = router_1_15_to_router_1_14_rsp; - assign router_1_14_rsp_in[1] = router_2_14_to_router_1_14_rsp; - assign router_1_14_rsp_in[2] = router_1_13_to_router_1_14_rsp; - assign router_1_14_rsp_in[3] = router_0_14_to_router_1_14_rsp; - assign router_1_14_rsp_in[4] = magia_tile_ni_1_14_to_router_1_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_14_req_in), - .floo_rsp_o (router_1_14_rsp_out), - .floo_req_o (router_1_14_req_out), - .floo_rsp_i (router_1_14_rsp_in) -); - - -floo_req_t [4:0] router_1_15_req_in; -floo_rsp_t [4:0] router_1_15_rsp_out; -floo_req_t [4:0] router_1_15_req_out; -floo_rsp_t [4:0] router_1_15_rsp_in; - - assign router_1_15_req_in[0] = '0; - assign router_1_15_req_in[1] = router_2_15_to_router_1_15_req; - assign router_1_15_req_in[2] = router_1_14_to_router_1_15_req; - assign router_1_15_req_in[3] = router_0_15_to_router_1_15_req; - assign router_1_15_req_in[4] = magia_tile_ni_1_15_to_router_1_15_req; - - assign router_1_15_to_router_2_15_rsp = router_1_15_rsp_out[1]; - assign router_1_15_to_router_1_14_rsp = router_1_15_rsp_out[2]; - assign router_1_15_to_router_0_15_rsp = router_1_15_rsp_out[3]; - assign router_1_15_to_magia_tile_ni_1_15_rsp = router_1_15_rsp_out[4]; - - assign router_1_15_to_router_2_15_req = router_1_15_req_out[1]; - assign router_1_15_to_router_1_14_req = router_1_15_req_out[2]; - assign router_1_15_to_router_0_15_req = router_1_15_req_out[3]; - assign router_1_15_to_magia_tile_ni_1_15_req = router_1_15_req_out[4]; - - assign router_1_15_rsp_in[0] = '0; - assign router_1_15_rsp_in[1] = router_2_15_to_router_1_15_rsp; - assign router_1_15_rsp_in[2] = router_1_14_to_router_1_15_rsp; - assign router_1_15_rsp_in[3] = router_0_15_to_router_1_15_rsp; - assign router_1_15_rsp_in[4] = magia_tile_ni_1_15_to_router_1_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_15_req_in), - .floo_rsp_o (router_1_15_rsp_out), - .floo_req_o (router_1_15_req_out), - .floo_rsp_i (router_1_15_rsp_in) -); - - -floo_req_t [4:0] router_2_0_req_in; -floo_rsp_t [4:0] router_2_0_rsp_out; -floo_req_t [4:0] router_2_0_req_out; -floo_rsp_t [4:0] router_2_0_rsp_in; - - assign router_2_0_req_in[0] = router_2_1_to_router_2_0_req; - assign router_2_0_req_in[1] = router_3_0_to_router_2_0_req; - assign router_2_0_req_in[2] = '0; - assign router_2_0_req_in[3] = router_1_0_to_router_2_0_req; - assign router_2_0_req_in[4] = magia_tile_ni_2_0_to_router_2_0_req; - - assign router_2_0_to_router_2_1_rsp = router_2_0_rsp_out[0]; - assign router_2_0_to_router_3_0_rsp = router_2_0_rsp_out[1]; - assign router_2_0_to_router_1_0_rsp = router_2_0_rsp_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_rsp = router_2_0_rsp_out[4]; - - assign router_2_0_to_router_2_1_req = router_2_0_req_out[0]; - assign router_2_0_to_router_3_0_req = router_2_0_req_out[1]; - assign router_2_0_to_router_1_0_req = router_2_0_req_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_req = router_2_0_req_out[4]; - - assign router_2_0_rsp_in[0] = router_2_1_to_router_2_0_rsp; - assign router_2_0_rsp_in[1] = router_3_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[2] = '0; - assign router_2_0_rsp_in[3] = router_1_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[4] = magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_0_req_in), - .floo_rsp_o (router_2_0_rsp_out), - .floo_req_o (router_2_0_req_out), - .floo_rsp_i (router_2_0_rsp_in) -); - - -floo_req_t [4:0] router_2_1_req_in; -floo_rsp_t [4:0] router_2_1_rsp_out; -floo_req_t [4:0] router_2_1_req_out; -floo_rsp_t [4:0] router_2_1_rsp_in; - - assign router_2_1_req_in[0] = router_2_2_to_router_2_1_req; - assign router_2_1_req_in[1] = router_3_1_to_router_2_1_req; - assign router_2_1_req_in[2] = router_2_0_to_router_2_1_req; - assign router_2_1_req_in[3] = router_1_1_to_router_2_1_req; - assign router_2_1_req_in[4] = magia_tile_ni_2_1_to_router_2_1_req; - - assign router_2_1_to_router_2_2_rsp = router_2_1_rsp_out[0]; - assign router_2_1_to_router_3_1_rsp = router_2_1_rsp_out[1]; - assign router_2_1_to_router_2_0_rsp = router_2_1_rsp_out[2]; - assign router_2_1_to_router_1_1_rsp = router_2_1_rsp_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_rsp = router_2_1_rsp_out[4]; - - assign router_2_1_to_router_2_2_req = router_2_1_req_out[0]; - assign router_2_1_to_router_3_1_req = router_2_1_req_out[1]; - assign router_2_1_to_router_2_0_req = router_2_1_req_out[2]; - assign router_2_1_to_router_1_1_req = router_2_1_req_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_req = router_2_1_req_out[4]; - - assign router_2_1_rsp_in[0] = router_2_2_to_router_2_1_rsp; - assign router_2_1_rsp_in[1] = router_3_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[2] = router_2_0_to_router_2_1_rsp; - assign router_2_1_rsp_in[3] = router_1_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[4] = magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_1_req_in), - .floo_rsp_o (router_2_1_rsp_out), - .floo_req_o (router_2_1_req_out), - .floo_rsp_i (router_2_1_rsp_in) -); - - -floo_req_t [4:0] router_2_2_req_in; -floo_rsp_t [4:0] router_2_2_rsp_out; -floo_req_t [4:0] router_2_2_req_out; -floo_rsp_t [4:0] router_2_2_rsp_in; - - assign router_2_2_req_in[0] = router_2_3_to_router_2_2_req; - assign router_2_2_req_in[1] = router_3_2_to_router_2_2_req; - assign router_2_2_req_in[2] = router_2_1_to_router_2_2_req; - assign router_2_2_req_in[3] = router_1_2_to_router_2_2_req; - assign router_2_2_req_in[4] = magia_tile_ni_2_2_to_router_2_2_req; - - assign router_2_2_to_router_2_3_rsp = router_2_2_rsp_out[0]; - assign router_2_2_to_router_3_2_rsp = router_2_2_rsp_out[1]; - assign router_2_2_to_router_2_1_rsp = router_2_2_rsp_out[2]; - assign router_2_2_to_router_1_2_rsp = router_2_2_rsp_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_rsp = router_2_2_rsp_out[4]; - - assign router_2_2_to_router_2_3_req = router_2_2_req_out[0]; - assign router_2_2_to_router_3_2_req = router_2_2_req_out[1]; - assign router_2_2_to_router_2_1_req = router_2_2_req_out[2]; - assign router_2_2_to_router_1_2_req = router_2_2_req_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_req = router_2_2_req_out[4]; - - assign router_2_2_rsp_in[0] = router_2_3_to_router_2_2_rsp; - assign router_2_2_rsp_in[1] = router_3_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[2] = router_2_1_to_router_2_2_rsp; - assign router_2_2_rsp_in[3] = router_1_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[4] = magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_2_req_in), - .floo_rsp_o (router_2_2_rsp_out), - .floo_req_o (router_2_2_req_out), - .floo_rsp_i (router_2_2_rsp_in) -); - - -floo_req_t [4:0] router_2_3_req_in; -floo_rsp_t [4:0] router_2_3_rsp_out; -floo_req_t [4:0] router_2_3_req_out; -floo_rsp_t [4:0] router_2_3_rsp_in; - - assign router_2_3_req_in[0] = router_2_4_to_router_2_3_req; - assign router_2_3_req_in[1] = router_3_3_to_router_2_3_req; - assign router_2_3_req_in[2] = router_2_2_to_router_2_3_req; - assign router_2_3_req_in[3] = router_1_3_to_router_2_3_req; - assign router_2_3_req_in[4] = magia_tile_ni_2_3_to_router_2_3_req; - - assign router_2_3_to_router_2_4_rsp = router_2_3_rsp_out[0]; - assign router_2_3_to_router_3_3_rsp = router_2_3_rsp_out[1]; - assign router_2_3_to_router_2_2_rsp = router_2_3_rsp_out[2]; - assign router_2_3_to_router_1_3_rsp = router_2_3_rsp_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_rsp = router_2_3_rsp_out[4]; - - assign router_2_3_to_router_2_4_req = router_2_3_req_out[0]; - assign router_2_3_to_router_3_3_req = router_2_3_req_out[1]; - assign router_2_3_to_router_2_2_req = router_2_3_req_out[2]; - assign router_2_3_to_router_1_3_req = router_2_3_req_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_req = router_2_3_req_out[4]; - - assign router_2_3_rsp_in[0] = router_2_4_to_router_2_3_rsp; - assign router_2_3_rsp_in[1] = router_3_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[2] = router_2_2_to_router_2_3_rsp; - assign router_2_3_rsp_in[3] = router_1_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[4] = magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_3_req_in), - .floo_rsp_o (router_2_3_rsp_out), - .floo_req_o (router_2_3_req_out), - .floo_rsp_i (router_2_3_rsp_in) -); - - -floo_req_t [4:0] router_2_4_req_in; -floo_rsp_t [4:0] router_2_4_rsp_out; -floo_req_t [4:0] router_2_4_req_out; -floo_rsp_t [4:0] router_2_4_rsp_in; - - assign router_2_4_req_in[0] = router_2_5_to_router_2_4_req; - assign router_2_4_req_in[1] = router_3_4_to_router_2_4_req; - assign router_2_4_req_in[2] = router_2_3_to_router_2_4_req; - assign router_2_4_req_in[3] = router_1_4_to_router_2_4_req; - assign router_2_4_req_in[4] = magia_tile_ni_2_4_to_router_2_4_req; - - assign router_2_4_to_router_2_5_rsp = router_2_4_rsp_out[0]; - assign router_2_4_to_router_3_4_rsp = router_2_4_rsp_out[1]; - assign router_2_4_to_router_2_3_rsp = router_2_4_rsp_out[2]; - assign router_2_4_to_router_1_4_rsp = router_2_4_rsp_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_rsp = router_2_4_rsp_out[4]; - - assign router_2_4_to_router_2_5_req = router_2_4_req_out[0]; - assign router_2_4_to_router_3_4_req = router_2_4_req_out[1]; - assign router_2_4_to_router_2_3_req = router_2_4_req_out[2]; - assign router_2_4_to_router_1_4_req = router_2_4_req_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_req = router_2_4_req_out[4]; - - assign router_2_4_rsp_in[0] = router_2_5_to_router_2_4_rsp; - assign router_2_4_rsp_in[1] = router_3_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[2] = router_2_3_to_router_2_4_rsp; - assign router_2_4_rsp_in[3] = router_1_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[4] = magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_4_req_in), - .floo_rsp_o (router_2_4_rsp_out), - .floo_req_o (router_2_4_req_out), - .floo_rsp_i (router_2_4_rsp_in) -); - - -floo_req_t [4:0] router_2_5_req_in; -floo_rsp_t [4:0] router_2_5_rsp_out; -floo_req_t [4:0] router_2_5_req_out; -floo_rsp_t [4:0] router_2_5_rsp_in; - - assign router_2_5_req_in[0] = router_2_6_to_router_2_5_req; - assign router_2_5_req_in[1] = router_3_5_to_router_2_5_req; - assign router_2_5_req_in[2] = router_2_4_to_router_2_5_req; - assign router_2_5_req_in[3] = router_1_5_to_router_2_5_req; - assign router_2_5_req_in[4] = magia_tile_ni_2_5_to_router_2_5_req; - - assign router_2_5_to_router_2_6_rsp = router_2_5_rsp_out[0]; - assign router_2_5_to_router_3_5_rsp = router_2_5_rsp_out[1]; - assign router_2_5_to_router_2_4_rsp = router_2_5_rsp_out[2]; - assign router_2_5_to_router_1_5_rsp = router_2_5_rsp_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_rsp = router_2_5_rsp_out[4]; - - assign router_2_5_to_router_2_6_req = router_2_5_req_out[0]; - assign router_2_5_to_router_3_5_req = router_2_5_req_out[1]; - assign router_2_5_to_router_2_4_req = router_2_5_req_out[2]; - assign router_2_5_to_router_1_5_req = router_2_5_req_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_req = router_2_5_req_out[4]; - - assign router_2_5_rsp_in[0] = router_2_6_to_router_2_5_rsp; - assign router_2_5_rsp_in[1] = router_3_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[2] = router_2_4_to_router_2_5_rsp; - assign router_2_5_rsp_in[3] = router_1_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[4] = magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_5_req_in), - .floo_rsp_o (router_2_5_rsp_out), - .floo_req_o (router_2_5_req_out), - .floo_rsp_i (router_2_5_rsp_in) -); - - -floo_req_t [4:0] router_2_6_req_in; -floo_rsp_t [4:0] router_2_6_rsp_out; -floo_req_t [4:0] router_2_6_req_out; -floo_rsp_t [4:0] router_2_6_rsp_in; - - assign router_2_6_req_in[0] = router_2_7_to_router_2_6_req; - assign router_2_6_req_in[1] = router_3_6_to_router_2_6_req; - assign router_2_6_req_in[2] = router_2_5_to_router_2_6_req; - assign router_2_6_req_in[3] = router_1_6_to_router_2_6_req; - assign router_2_6_req_in[4] = magia_tile_ni_2_6_to_router_2_6_req; - - assign router_2_6_to_router_2_7_rsp = router_2_6_rsp_out[0]; - assign router_2_6_to_router_3_6_rsp = router_2_6_rsp_out[1]; - assign router_2_6_to_router_2_5_rsp = router_2_6_rsp_out[2]; - assign router_2_6_to_router_1_6_rsp = router_2_6_rsp_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_rsp = router_2_6_rsp_out[4]; - - assign router_2_6_to_router_2_7_req = router_2_6_req_out[0]; - assign router_2_6_to_router_3_6_req = router_2_6_req_out[1]; - assign router_2_6_to_router_2_5_req = router_2_6_req_out[2]; - assign router_2_6_to_router_1_6_req = router_2_6_req_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_req = router_2_6_req_out[4]; - - assign router_2_6_rsp_in[0] = router_2_7_to_router_2_6_rsp; - assign router_2_6_rsp_in[1] = router_3_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[2] = router_2_5_to_router_2_6_rsp; - assign router_2_6_rsp_in[3] = router_1_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[4] = magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_6_req_in), - .floo_rsp_o (router_2_6_rsp_out), - .floo_req_o (router_2_6_req_out), - .floo_rsp_i (router_2_6_rsp_in) -); - - -floo_req_t [4:0] router_2_7_req_in; -floo_rsp_t [4:0] router_2_7_rsp_out; -floo_req_t [4:0] router_2_7_req_out; -floo_rsp_t [4:0] router_2_7_rsp_in; - - assign router_2_7_req_in[0] = router_2_8_to_router_2_7_req; - assign router_2_7_req_in[1] = router_3_7_to_router_2_7_req; - assign router_2_7_req_in[2] = router_2_6_to_router_2_7_req; - assign router_2_7_req_in[3] = router_1_7_to_router_2_7_req; - assign router_2_7_req_in[4] = magia_tile_ni_2_7_to_router_2_7_req; - - assign router_2_7_to_router_2_8_rsp = router_2_7_rsp_out[0]; - assign router_2_7_to_router_3_7_rsp = router_2_7_rsp_out[1]; - assign router_2_7_to_router_2_6_rsp = router_2_7_rsp_out[2]; - assign router_2_7_to_router_1_7_rsp = router_2_7_rsp_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_rsp = router_2_7_rsp_out[4]; - - assign router_2_7_to_router_2_8_req = router_2_7_req_out[0]; - assign router_2_7_to_router_3_7_req = router_2_7_req_out[1]; - assign router_2_7_to_router_2_6_req = router_2_7_req_out[2]; - assign router_2_7_to_router_1_7_req = router_2_7_req_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_req = router_2_7_req_out[4]; - - assign router_2_7_rsp_in[0] = router_2_8_to_router_2_7_rsp; - assign router_2_7_rsp_in[1] = router_3_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[2] = router_2_6_to_router_2_7_rsp; - assign router_2_7_rsp_in[3] = router_1_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[4] = magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_7_req_in), - .floo_rsp_o (router_2_7_rsp_out), - .floo_req_o (router_2_7_req_out), - .floo_rsp_i (router_2_7_rsp_in) -); - - -floo_req_t [4:0] router_2_8_req_in; -floo_rsp_t [4:0] router_2_8_rsp_out; -floo_req_t [4:0] router_2_8_req_out; -floo_rsp_t [4:0] router_2_8_rsp_in; - - assign router_2_8_req_in[0] = router_2_9_to_router_2_8_req; - assign router_2_8_req_in[1] = router_3_8_to_router_2_8_req; - assign router_2_8_req_in[2] = router_2_7_to_router_2_8_req; - assign router_2_8_req_in[3] = router_1_8_to_router_2_8_req; - assign router_2_8_req_in[4] = magia_tile_ni_2_8_to_router_2_8_req; - - assign router_2_8_to_router_2_9_rsp = router_2_8_rsp_out[0]; - assign router_2_8_to_router_3_8_rsp = router_2_8_rsp_out[1]; - assign router_2_8_to_router_2_7_rsp = router_2_8_rsp_out[2]; - assign router_2_8_to_router_1_8_rsp = router_2_8_rsp_out[3]; - assign router_2_8_to_magia_tile_ni_2_8_rsp = router_2_8_rsp_out[4]; - - assign router_2_8_to_router_2_9_req = router_2_8_req_out[0]; - assign router_2_8_to_router_3_8_req = router_2_8_req_out[1]; - assign router_2_8_to_router_2_7_req = router_2_8_req_out[2]; - assign router_2_8_to_router_1_8_req = router_2_8_req_out[3]; - assign router_2_8_to_magia_tile_ni_2_8_req = router_2_8_req_out[4]; - - assign router_2_8_rsp_in[0] = router_2_9_to_router_2_8_rsp; - assign router_2_8_rsp_in[1] = router_3_8_to_router_2_8_rsp; - assign router_2_8_rsp_in[2] = router_2_7_to_router_2_8_rsp; - assign router_2_8_rsp_in[3] = router_1_8_to_router_2_8_rsp; - assign router_2_8_rsp_in[4] = magia_tile_ni_2_8_to_router_2_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_8_req_in), - .floo_rsp_o (router_2_8_rsp_out), - .floo_req_o (router_2_8_req_out), - .floo_rsp_i (router_2_8_rsp_in) -); - - -floo_req_t [4:0] router_2_9_req_in; -floo_rsp_t [4:0] router_2_9_rsp_out; -floo_req_t [4:0] router_2_9_req_out; -floo_rsp_t [4:0] router_2_9_rsp_in; - - assign router_2_9_req_in[0] = router_2_10_to_router_2_9_req; - assign router_2_9_req_in[1] = router_3_9_to_router_2_9_req; - assign router_2_9_req_in[2] = router_2_8_to_router_2_9_req; - assign router_2_9_req_in[3] = router_1_9_to_router_2_9_req; - assign router_2_9_req_in[4] = magia_tile_ni_2_9_to_router_2_9_req; - - assign router_2_9_to_router_2_10_rsp = router_2_9_rsp_out[0]; - assign router_2_9_to_router_3_9_rsp = router_2_9_rsp_out[1]; - assign router_2_9_to_router_2_8_rsp = router_2_9_rsp_out[2]; - assign router_2_9_to_router_1_9_rsp = router_2_9_rsp_out[3]; - assign router_2_9_to_magia_tile_ni_2_9_rsp = router_2_9_rsp_out[4]; - - assign router_2_9_to_router_2_10_req = router_2_9_req_out[0]; - assign router_2_9_to_router_3_9_req = router_2_9_req_out[1]; - assign router_2_9_to_router_2_8_req = router_2_9_req_out[2]; - assign router_2_9_to_router_1_9_req = router_2_9_req_out[3]; - assign router_2_9_to_magia_tile_ni_2_9_req = router_2_9_req_out[4]; - - assign router_2_9_rsp_in[0] = router_2_10_to_router_2_9_rsp; - assign router_2_9_rsp_in[1] = router_3_9_to_router_2_9_rsp; - assign router_2_9_rsp_in[2] = router_2_8_to_router_2_9_rsp; - assign router_2_9_rsp_in[3] = router_1_9_to_router_2_9_rsp; - assign router_2_9_rsp_in[4] = magia_tile_ni_2_9_to_router_2_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_9_req_in), - .floo_rsp_o (router_2_9_rsp_out), - .floo_req_o (router_2_9_req_out), - .floo_rsp_i (router_2_9_rsp_in) -); - - -floo_req_t [4:0] router_2_10_req_in; -floo_rsp_t [4:0] router_2_10_rsp_out; -floo_req_t [4:0] router_2_10_req_out; -floo_rsp_t [4:0] router_2_10_rsp_in; - - assign router_2_10_req_in[0] = router_2_11_to_router_2_10_req; - assign router_2_10_req_in[1] = router_3_10_to_router_2_10_req; - assign router_2_10_req_in[2] = router_2_9_to_router_2_10_req; - assign router_2_10_req_in[3] = router_1_10_to_router_2_10_req; - assign router_2_10_req_in[4] = magia_tile_ni_2_10_to_router_2_10_req; - - assign router_2_10_to_router_2_11_rsp = router_2_10_rsp_out[0]; - assign router_2_10_to_router_3_10_rsp = router_2_10_rsp_out[1]; - assign router_2_10_to_router_2_9_rsp = router_2_10_rsp_out[2]; - assign router_2_10_to_router_1_10_rsp = router_2_10_rsp_out[3]; - assign router_2_10_to_magia_tile_ni_2_10_rsp = router_2_10_rsp_out[4]; - - assign router_2_10_to_router_2_11_req = router_2_10_req_out[0]; - assign router_2_10_to_router_3_10_req = router_2_10_req_out[1]; - assign router_2_10_to_router_2_9_req = router_2_10_req_out[2]; - assign router_2_10_to_router_1_10_req = router_2_10_req_out[3]; - assign router_2_10_to_magia_tile_ni_2_10_req = router_2_10_req_out[4]; - - assign router_2_10_rsp_in[0] = router_2_11_to_router_2_10_rsp; - assign router_2_10_rsp_in[1] = router_3_10_to_router_2_10_rsp; - assign router_2_10_rsp_in[2] = router_2_9_to_router_2_10_rsp; - assign router_2_10_rsp_in[3] = router_1_10_to_router_2_10_rsp; - assign router_2_10_rsp_in[4] = magia_tile_ni_2_10_to_router_2_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_10_req_in), - .floo_rsp_o (router_2_10_rsp_out), - .floo_req_o (router_2_10_req_out), - .floo_rsp_i (router_2_10_rsp_in) -); - - -floo_req_t [4:0] router_2_11_req_in; -floo_rsp_t [4:0] router_2_11_rsp_out; -floo_req_t [4:0] router_2_11_req_out; -floo_rsp_t [4:0] router_2_11_rsp_in; - - assign router_2_11_req_in[0] = router_2_12_to_router_2_11_req; - assign router_2_11_req_in[1] = router_3_11_to_router_2_11_req; - assign router_2_11_req_in[2] = router_2_10_to_router_2_11_req; - assign router_2_11_req_in[3] = router_1_11_to_router_2_11_req; - assign router_2_11_req_in[4] = magia_tile_ni_2_11_to_router_2_11_req; - - assign router_2_11_to_router_2_12_rsp = router_2_11_rsp_out[0]; - assign router_2_11_to_router_3_11_rsp = router_2_11_rsp_out[1]; - assign router_2_11_to_router_2_10_rsp = router_2_11_rsp_out[2]; - assign router_2_11_to_router_1_11_rsp = router_2_11_rsp_out[3]; - assign router_2_11_to_magia_tile_ni_2_11_rsp = router_2_11_rsp_out[4]; - - assign router_2_11_to_router_2_12_req = router_2_11_req_out[0]; - assign router_2_11_to_router_3_11_req = router_2_11_req_out[1]; - assign router_2_11_to_router_2_10_req = router_2_11_req_out[2]; - assign router_2_11_to_router_1_11_req = router_2_11_req_out[3]; - assign router_2_11_to_magia_tile_ni_2_11_req = router_2_11_req_out[4]; - - assign router_2_11_rsp_in[0] = router_2_12_to_router_2_11_rsp; - assign router_2_11_rsp_in[1] = router_3_11_to_router_2_11_rsp; - assign router_2_11_rsp_in[2] = router_2_10_to_router_2_11_rsp; - assign router_2_11_rsp_in[3] = router_1_11_to_router_2_11_rsp; - assign router_2_11_rsp_in[4] = magia_tile_ni_2_11_to_router_2_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_11_req_in), - .floo_rsp_o (router_2_11_rsp_out), - .floo_req_o (router_2_11_req_out), - .floo_rsp_i (router_2_11_rsp_in) -); - - -floo_req_t [4:0] router_2_12_req_in; -floo_rsp_t [4:0] router_2_12_rsp_out; -floo_req_t [4:0] router_2_12_req_out; -floo_rsp_t [4:0] router_2_12_rsp_in; - - assign router_2_12_req_in[0] = router_2_13_to_router_2_12_req; - assign router_2_12_req_in[1] = router_3_12_to_router_2_12_req; - assign router_2_12_req_in[2] = router_2_11_to_router_2_12_req; - assign router_2_12_req_in[3] = router_1_12_to_router_2_12_req; - assign router_2_12_req_in[4] = magia_tile_ni_2_12_to_router_2_12_req; - - assign router_2_12_to_router_2_13_rsp = router_2_12_rsp_out[0]; - assign router_2_12_to_router_3_12_rsp = router_2_12_rsp_out[1]; - assign router_2_12_to_router_2_11_rsp = router_2_12_rsp_out[2]; - assign router_2_12_to_router_1_12_rsp = router_2_12_rsp_out[3]; - assign router_2_12_to_magia_tile_ni_2_12_rsp = router_2_12_rsp_out[4]; - - assign router_2_12_to_router_2_13_req = router_2_12_req_out[0]; - assign router_2_12_to_router_3_12_req = router_2_12_req_out[1]; - assign router_2_12_to_router_2_11_req = router_2_12_req_out[2]; - assign router_2_12_to_router_1_12_req = router_2_12_req_out[3]; - assign router_2_12_to_magia_tile_ni_2_12_req = router_2_12_req_out[4]; - - assign router_2_12_rsp_in[0] = router_2_13_to_router_2_12_rsp; - assign router_2_12_rsp_in[1] = router_3_12_to_router_2_12_rsp; - assign router_2_12_rsp_in[2] = router_2_11_to_router_2_12_rsp; - assign router_2_12_rsp_in[3] = router_1_12_to_router_2_12_rsp; - assign router_2_12_rsp_in[4] = magia_tile_ni_2_12_to_router_2_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_12_req_in), - .floo_rsp_o (router_2_12_rsp_out), - .floo_req_o (router_2_12_req_out), - .floo_rsp_i (router_2_12_rsp_in) -); - - -floo_req_t [4:0] router_2_13_req_in; -floo_rsp_t [4:0] router_2_13_rsp_out; -floo_req_t [4:0] router_2_13_req_out; -floo_rsp_t [4:0] router_2_13_rsp_in; - - assign router_2_13_req_in[0] = router_2_14_to_router_2_13_req; - assign router_2_13_req_in[1] = router_3_13_to_router_2_13_req; - assign router_2_13_req_in[2] = router_2_12_to_router_2_13_req; - assign router_2_13_req_in[3] = router_1_13_to_router_2_13_req; - assign router_2_13_req_in[4] = magia_tile_ni_2_13_to_router_2_13_req; - - assign router_2_13_to_router_2_14_rsp = router_2_13_rsp_out[0]; - assign router_2_13_to_router_3_13_rsp = router_2_13_rsp_out[1]; - assign router_2_13_to_router_2_12_rsp = router_2_13_rsp_out[2]; - assign router_2_13_to_router_1_13_rsp = router_2_13_rsp_out[3]; - assign router_2_13_to_magia_tile_ni_2_13_rsp = router_2_13_rsp_out[4]; - - assign router_2_13_to_router_2_14_req = router_2_13_req_out[0]; - assign router_2_13_to_router_3_13_req = router_2_13_req_out[1]; - assign router_2_13_to_router_2_12_req = router_2_13_req_out[2]; - assign router_2_13_to_router_1_13_req = router_2_13_req_out[3]; - assign router_2_13_to_magia_tile_ni_2_13_req = router_2_13_req_out[4]; - - assign router_2_13_rsp_in[0] = router_2_14_to_router_2_13_rsp; - assign router_2_13_rsp_in[1] = router_3_13_to_router_2_13_rsp; - assign router_2_13_rsp_in[2] = router_2_12_to_router_2_13_rsp; - assign router_2_13_rsp_in[3] = router_1_13_to_router_2_13_rsp; - assign router_2_13_rsp_in[4] = magia_tile_ni_2_13_to_router_2_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_13_req_in), - .floo_rsp_o (router_2_13_rsp_out), - .floo_req_o (router_2_13_req_out), - .floo_rsp_i (router_2_13_rsp_in) -); - - -floo_req_t [4:0] router_2_14_req_in; -floo_rsp_t [4:0] router_2_14_rsp_out; -floo_req_t [4:0] router_2_14_req_out; -floo_rsp_t [4:0] router_2_14_rsp_in; - - assign router_2_14_req_in[0] = router_2_15_to_router_2_14_req; - assign router_2_14_req_in[1] = router_3_14_to_router_2_14_req; - assign router_2_14_req_in[2] = router_2_13_to_router_2_14_req; - assign router_2_14_req_in[3] = router_1_14_to_router_2_14_req; - assign router_2_14_req_in[4] = magia_tile_ni_2_14_to_router_2_14_req; - - assign router_2_14_to_router_2_15_rsp = router_2_14_rsp_out[0]; - assign router_2_14_to_router_3_14_rsp = router_2_14_rsp_out[1]; - assign router_2_14_to_router_2_13_rsp = router_2_14_rsp_out[2]; - assign router_2_14_to_router_1_14_rsp = router_2_14_rsp_out[3]; - assign router_2_14_to_magia_tile_ni_2_14_rsp = router_2_14_rsp_out[4]; - - assign router_2_14_to_router_2_15_req = router_2_14_req_out[0]; - assign router_2_14_to_router_3_14_req = router_2_14_req_out[1]; - assign router_2_14_to_router_2_13_req = router_2_14_req_out[2]; - assign router_2_14_to_router_1_14_req = router_2_14_req_out[3]; - assign router_2_14_to_magia_tile_ni_2_14_req = router_2_14_req_out[4]; - - assign router_2_14_rsp_in[0] = router_2_15_to_router_2_14_rsp; - assign router_2_14_rsp_in[1] = router_3_14_to_router_2_14_rsp; - assign router_2_14_rsp_in[2] = router_2_13_to_router_2_14_rsp; - assign router_2_14_rsp_in[3] = router_1_14_to_router_2_14_rsp; - assign router_2_14_rsp_in[4] = magia_tile_ni_2_14_to_router_2_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_14_req_in), - .floo_rsp_o (router_2_14_rsp_out), - .floo_req_o (router_2_14_req_out), - .floo_rsp_i (router_2_14_rsp_in) -); - - -floo_req_t [4:0] router_2_15_req_in; -floo_rsp_t [4:0] router_2_15_rsp_out; -floo_req_t [4:0] router_2_15_req_out; -floo_rsp_t [4:0] router_2_15_rsp_in; - - assign router_2_15_req_in[0] = '0; - assign router_2_15_req_in[1] = router_3_15_to_router_2_15_req; - assign router_2_15_req_in[2] = router_2_14_to_router_2_15_req; - assign router_2_15_req_in[3] = router_1_15_to_router_2_15_req; - assign router_2_15_req_in[4] = magia_tile_ni_2_15_to_router_2_15_req; - - assign router_2_15_to_router_3_15_rsp = router_2_15_rsp_out[1]; - assign router_2_15_to_router_2_14_rsp = router_2_15_rsp_out[2]; - assign router_2_15_to_router_1_15_rsp = router_2_15_rsp_out[3]; - assign router_2_15_to_magia_tile_ni_2_15_rsp = router_2_15_rsp_out[4]; - - assign router_2_15_to_router_3_15_req = router_2_15_req_out[1]; - assign router_2_15_to_router_2_14_req = router_2_15_req_out[2]; - assign router_2_15_to_router_1_15_req = router_2_15_req_out[3]; - assign router_2_15_to_magia_tile_ni_2_15_req = router_2_15_req_out[4]; - - assign router_2_15_rsp_in[0] = '0; - assign router_2_15_rsp_in[1] = router_3_15_to_router_2_15_rsp; - assign router_2_15_rsp_in[2] = router_2_14_to_router_2_15_rsp; - assign router_2_15_rsp_in[3] = router_1_15_to_router_2_15_rsp; - assign router_2_15_rsp_in[4] = magia_tile_ni_2_15_to_router_2_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_15_req_in), - .floo_rsp_o (router_2_15_rsp_out), - .floo_req_o (router_2_15_req_out), - .floo_rsp_i (router_2_15_rsp_in) -); - - -floo_req_t [4:0] router_3_0_req_in; -floo_rsp_t [4:0] router_3_0_rsp_out; -floo_req_t [4:0] router_3_0_req_out; -floo_rsp_t [4:0] router_3_0_rsp_in; - - assign router_3_0_req_in[0] = router_3_1_to_router_3_0_req; - assign router_3_0_req_in[1] = router_4_0_to_router_3_0_req; - assign router_3_0_req_in[2] = '0; - assign router_3_0_req_in[3] = router_2_0_to_router_3_0_req; - assign router_3_0_req_in[4] = magia_tile_ni_3_0_to_router_3_0_req; - - assign router_3_0_to_router_3_1_rsp = router_3_0_rsp_out[0]; - assign router_3_0_to_router_4_0_rsp = router_3_0_rsp_out[1]; - assign router_3_0_to_router_2_0_rsp = router_3_0_rsp_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_rsp = router_3_0_rsp_out[4]; - - assign router_3_0_to_router_3_1_req = router_3_0_req_out[0]; - assign router_3_0_to_router_4_0_req = router_3_0_req_out[1]; - assign router_3_0_to_router_2_0_req = router_3_0_req_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_req = router_3_0_req_out[4]; - - assign router_3_0_rsp_in[0] = router_3_1_to_router_3_0_rsp; - assign router_3_0_rsp_in[1] = router_4_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[2] = '0; - assign router_3_0_rsp_in[3] = router_2_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[4] = magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_0_req_in), - .floo_rsp_o (router_3_0_rsp_out), - .floo_req_o (router_3_0_req_out), - .floo_rsp_i (router_3_0_rsp_in) -); - - -floo_req_t [4:0] router_3_1_req_in; -floo_rsp_t [4:0] router_3_1_rsp_out; -floo_req_t [4:0] router_3_1_req_out; -floo_rsp_t [4:0] router_3_1_rsp_in; - - assign router_3_1_req_in[0] = router_3_2_to_router_3_1_req; - assign router_3_1_req_in[1] = router_4_1_to_router_3_1_req; - assign router_3_1_req_in[2] = router_3_0_to_router_3_1_req; - assign router_3_1_req_in[3] = router_2_1_to_router_3_1_req; - assign router_3_1_req_in[4] = magia_tile_ni_3_1_to_router_3_1_req; - - assign router_3_1_to_router_3_2_rsp = router_3_1_rsp_out[0]; - assign router_3_1_to_router_4_1_rsp = router_3_1_rsp_out[1]; - assign router_3_1_to_router_3_0_rsp = router_3_1_rsp_out[2]; - assign router_3_1_to_router_2_1_rsp = router_3_1_rsp_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_rsp = router_3_1_rsp_out[4]; - - assign router_3_1_to_router_3_2_req = router_3_1_req_out[0]; - assign router_3_1_to_router_4_1_req = router_3_1_req_out[1]; - assign router_3_1_to_router_3_0_req = router_3_1_req_out[2]; - assign router_3_1_to_router_2_1_req = router_3_1_req_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_req = router_3_1_req_out[4]; - - assign router_3_1_rsp_in[0] = router_3_2_to_router_3_1_rsp; - assign router_3_1_rsp_in[1] = router_4_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[2] = router_3_0_to_router_3_1_rsp; - assign router_3_1_rsp_in[3] = router_2_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[4] = magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_1_req_in), - .floo_rsp_o (router_3_1_rsp_out), - .floo_req_o (router_3_1_req_out), - .floo_rsp_i (router_3_1_rsp_in) -); - - -floo_req_t [4:0] router_3_2_req_in; -floo_rsp_t [4:0] router_3_2_rsp_out; -floo_req_t [4:0] router_3_2_req_out; -floo_rsp_t [4:0] router_3_2_rsp_in; - - assign router_3_2_req_in[0] = router_3_3_to_router_3_2_req; - assign router_3_2_req_in[1] = router_4_2_to_router_3_2_req; - assign router_3_2_req_in[2] = router_3_1_to_router_3_2_req; - assign router_3_2_req_in[3] = router_2_2_to_router_3_2_req; - assign router_3_2_req_in[4] = magia_tile_ni_3_2_to_router_3_2_req; - - assign router_3_2_to_router_3_3_rsp = router_3_2_rsp_out[0]; - assign router_3_2_to_router_4_2_rsp = router_3_2_rsp_out[1]; - assign router_3_2_to_router_3_1_rsp = router_3_2_rsp_out[2]; - assign router_3_2_to_router_2_2_rsp = router_3_2_rsp_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_rsp = router_3_2_rsp_out[4]; - - assign router_3_2_to_router_3_3_req = router_3_2_req_out[0]; - assign router_3_2_to_router_4_2_req = router_3_2_req_out[1]; - assign router_3_2_to_router_3_1_req = router_3_2_req_out[2]; - assign router_3_2_to_router_2_2_req = router_3_2_req_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_req = router_3_2_req_out[4]; - - assign router_3_2_rsp_in[0] = router_3_3_to_router_3_2_rsp; - assign router_3_2_rsp_in[1] = router_4_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[2] = router_3_1_to_router_3_2_rsp; - assign router_3_2_rsp_in[3] = router_2_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[4] = magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_2_req_in), - .floo_rsp_o (router_3_2_rsp_out), - .floo_req_o (router_3_2_req_out), - .floo_rsp_i (router_3_2_rsp_in) -); - - -floo_req_t [4:0] router_3_3_req_in; -floo_rsp_t [4:0] router_3_3_rsp_out; -floo_req_t [4:0] router_3_3_req_out; -floo_rsp_t [4:0] router_3_3_rsp_in; - - assign router_3_3_req_in[0] = router_3_4_to_router_3_3_req; - assign router_3_3_req_in[1] = router_4_3_to_router_3_3_req; - assign router_3_3_req_in[2] = router_3_2_to_router_3_3_req; - assign router_3_3_req_in[3] = router_2_3_to_router_3_3_req; - assign router_3_3_req_in[4] = magia_tile_ni_3_3_to_router_3_3_req; - - assign router_3_3_to_router_3_4_rsp = router_3_3_rsp_out[0]; - assign router_3_3_to_router_4_3_rsp = router_3_3_rsp_out[1]; - assign router_3_3_to_router_3_2_rsp = router_3_3_rsp_out[2]; - assign router_3_3_to_router_2_3_rsp = router_3_3_rsp_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_rsp = router_3_3_rsp_out[4]; - - assign router_3_3_to_router_3_4_req = router_3_3_req_out[0]; - assign router_3_3_to_router_4_3_req = router_3_3_req_out[1]; - assign router_3_3_to_router_3_2_req = router_3_3_req_out[2]; - assign router_3_3_to_router_2_3_req = router_3_3_req_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_req = router_3_3_req_out[4]; - - assign router_3_3_rsp_in[0] = router_3_4_to_router_3_3_rsp; - assign router_3_3_rsp_in[1] = router_4_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[2] = router_3_2_to_router_3_3_rsp; - assign router_3_3_rsp_in[3] = router_2_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[4] = magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_3_req_in), - .floo_rsp_o (router_3_3_rsp_out), - .floo_req_o (router_3_3_req_out), - .floo_rsp_i (router_3_3_rsp_in) -); - - -floo_req_t [4:0] router_3_4_req_in; -floo_rsp_t [4:0] router_3_4_rsp_out; -floo_req_t [4:0] router_3_4_req_out; -floo_rsp_t [4:0] router_3_4_rsp_in; - - assign router_3_4_req_in[0] = router_3_5_to_router_3_4_req; - assign router_3_4_req_in[1] = router_4_4_to_router_3_4_req; - assign router_3_4_req_in[2] = router_3_3_to_router_3_4_req; - assign router_3_4_req_in[3] = router_2_4_to_router_3_4_req; - assign router_3_4_req_in[4] = magia_tile_ni_3_4_to_router_3_4_req; - - assign router_3_4_to_router_3_5_rsp = router_3_4_rsp_out[0]; - assign router_3_4_to_router_4_4_rsp = router_3_4_rsp_out[1]; - assign router_3_4_to_router_3_3_rsp = router_3_4_rsp_out[2]; - assign router_3_4_to_router_2_4_rsp = router_3_4_rsp_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_rsp = router_3_4_rsp_out[4]; - - assign router_3_4_to_router_3_5_req = router_3_4_req_out[0]; - assign router_3_4_to_router_4_4_req = router_3_4_req_out[1]; - assign router_3_4_to_router_3_3_req = router_3_4_req_out[2]; - assign router_3_4_to_router_2_4_req = router_3_4_req_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_req = router_3_4_req_out[4]; - - assign router_3_4_rsp_in[0] = router_3_5_to_router_3_4_rsp; - assign router_3_4_rsp_in[1] = router_4_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[2] = router_3_3_to_router_3_4_rsp; - assign router_3_4_rsp_in[3] = router_2_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[4] = magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_4_req_in), - .floo_rsp_o (router_3_4_rsp_out), - .floo_req_o (router_3_4_req_out), - .floo_rsp_i (router_3_4_rsp_in) -); - - -floo_req_t [4:0] router_3_5_req_in; -floo_rsp_t [4:0] router_3_5_rsp_out; -floo_req_t [4:0] router_3_5_req_out; -floo_rsp_t [4:0] router_3_5_rsp_in; - - assign router_3_5_req_in[0] = router_3_6_to_router_3_5_req; - assign router_3_5_req_in[1] = router_4_5_to_router_3_5_req; - assign router_3_5_req_in[2] = router_3_4_to_router_3_5_req; - assign router_3_5_req_in[3] = router_2_5_to_router_3_5_req; - assign router_3_5_req_in[4] = magia_tile_ni_3_5_to_router_3_5_req; - - assign router_3_5_to_router_3_6_rsp = router_3_5_rsp_out[0]; - assign router_3_5_to_router_4_5_rsp = router_3_5_rsp_out[1]; - assign router_3_5_to_router_3_4_rsp = router_3_5_rsp_out[2]; - assign router_3_5_to_router_2_5_rsp = router_3_5_rsp_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_rsp = router_3_5_rsp_out[4]; - - assign router_3_5_to_router_3_6_req = router_3_5_req_out[0]; - assign router_3_5_to_router_4_5_req = router_3_5_req_out[1]; - assign router_3_5_to_router_3_4_req = router_3_5_req_out[2]; - assign router_3_5_to_router_2_5_req = router_3_5_req_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_req = router_3_5_req_out[4]; - - assign router_3_5_rsp_in[0] = router_3_6_to_router_3_5_rsp; - assign router_3_5_rsp_in[1] = router_4_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[2] = router_3_4_to_router_3_5_rsp; - assign router_3_5_rsp_in[3] = router_2_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[4] = magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_5_req_in), - .floo_rsp_o (router_3_5_rsp_out), - .floo_req_o (router_3_5_req_out), - .floo_rsp_i (router_3_5_rsp_in) -); - - -floo_req_t [4:0] router_3_6_req_in; -floo_rsp_t [4:0] router_3_6_rsp_out; -floo_req_t [4:0] router_3_6_req_out; -floo_rsp_t [4:0] router_3_6_rsp_in; - - assign router_3_6_req_in[0] = router_3_7_to_router_3_6_req; - assign router_3_6_req_in[1] = router_4_6_to_router_3_6_req; - assign router_3_6_req_in[2] = router_3_5_to_router_3_6_req; - assign router_3_6_req_in[3] = router_2_6_to_router_3_6_req; - assign router_3_6_req_in[4] = magia_tile_ni_3_6_to_router_3_6_req; - - assign router_3_6_to_router_3_7_rsp = router_3_6_rsp_out[0]; - assign router_3_6_to_router_4_6_rsp = router_3_6_rsp_out[1]; - assign router_3_6_to_router_3_5_rsp = router_3_6_rsp_out[2]; - assign router_3_6_to_router_2_6_rsp = router_3_6_rsp_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_rsp = router_3_6_rsp_out[4]; - - assign router_3_6_to_router_3_7_req = router_3_6_req_out[0]; - assign router_3_6_to_router_4_6_req = router_3_6_req_out[1]; - assign router_3_6_to_router_3_5_req = router_3_6_req_out[2]; - assign router_3_6_to_router_2_6_req = router_3_6_req_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_req = router_3_6_req_out[4]; - - assign router_3_6_rsp_in[0] = router_3_7_to_router_3_6_rsp; - assign router_3_6_rsp_in[1] = router_4_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[2] = router_3_5_to_router_3_6_rsp; - assign router_3_6_rsp_in[3] = router_2_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[4] = magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_6_req_in), - .floo_rsp_o (router_3_6_rsp_out), - .floo_req_o (router_3_6_req_out), - .floo_rsp_i (router_3_6_rsp_in) -); - - -floo_req_t [4:0] router_3_7_req_in; -floo_rsp_t [4:0] router_3_7_rsp_out; -floo_req_t [4:0] router_3_7_req_out; -floo_rsp_t [4:0] router_3_7_rsp_in; - - assign router_3_7_req_in[0] = router_3_8_to_router_3_7_req; - assign router_3_7_req_in[1] = router_4_7_to_router_3_7_req; - assign router_3_7_req_in[2] = router_3_6_to_router_3_7_req; - assign router_3_7_req_in[3] = router_2_7_to_router_3_7_req; - assign router_3_7_req_in[4] = magia_tile_ni_3_7_to_router_3_7_req; - - assign router_3_7_to_router_3_8_rsp = router_3_7_rsp_out[0]; - assign router_3_7_to_router_4_7_rsp = router_3_7_rsp_out[1]; - assign router_3_7_to_router_3_6_rsp = router_3_7_rsp_out[2]; - assign router_3_7_to_router_2_7_rsp = router_3_7_rsp_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_rsp = router_3_7_rsp_out[4]; - - assign router_3_7_to_router_3_8_req = router_3_7_req_out[0]; - assign router_3_7_to_router_4_7_req = router_3_7_req_out[1]; - assign router_3_7_to_router_3_6_req = router_3_7_req_out[2]; - assign router_3_7_to_router_2_7_req = router_3_7_req_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_req = router_3_7_req_out[4]; - - assign router_3_7_rsp_in[0] = router_3_8_to_router_3_7_rsp; - assign router_3_7_rsp_in[1] = router_4_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[2] = router_3_6_to_router_3_7_rsp; - assign router_3_7_rsp_in[3] = router_2_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[4] = magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_7_req_in), - .floo_rsp_o (router_3_7_rsp_out), - .floo_req_o (router_3_7_req_out), - .floo_rsp_i (router_3_7_rsp_in) -); - - -floo_req_t [4:0] router_3_8_req_in; -floo_rsp_t [4:0] router_3_8_rsp_out; -floo_req_t [4:0] router_3_8_req_out; -floo_rsp_t [4:0] router_3_8_rsp_in; - - assign router_3_8_req_in[0] = router_3_9_to_router_3_8_req; - assign router_3_8_req_in[1] = router_4_8_to_router_3_8_req; - assign router_3_8_req_in[2] = router_3_7_to_router_3_8_req; - assign router_3_8_req_in[3] = router_2_8_to_router_3_8_req; - assign router_3_8_req_in[4] = magia_tile_ni_3_8_to_router_3_8_req; - - assign router_3_8_to_router_3_9_rsp = router_3_8_rsp_out[0]; - assign router_3_8_to_router_4_8_rsp = router_3_8_rsp_out[1]; - assign router_3_8_to_router_3_7_rsp = router_3_8_rsp_out[2]; - assign router_3_8_to_router_2_8_rsp = router_3_8_rsp_out[3]; - assign router_3_8_to_magia_tile_ni_3_8_rsp = router_3_8_rsp_out[4]; - - assign router_3_8_to_router_3_9_req = router_3_8_req_out[0]; - assign router_3_8_to_router_4_8_req = router_3_8_req_out[1]; - assign router_3_8_to_router_3_7_req = router_3_8_req_out[2]; - assign router_3_8_to_router_2_8_req = router_3_8_req_out[3]; - assign router_3_8_to_magia_tile_ni_3_8_req = router_3_8_req_out[4]; - - assign router_3_8_rsp_in[0] = router_3_9_to_router_3_8_rsp; - assign router_3_8_rsp_in[1] = router_4_8_to_router_3_8_rsp; - assign router_3_8_rsp_in[2] = router_3_7_to_router_3_8_rsp; - assign router_3_8_rsp_in[3] = router_2_8_to_router_3_8_rsp; - assign router_3_8_rsp_in[4] = magia_tile_ni_3_8_to_router_3_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_8_req_in), - .floo_rsp_o (router_3_8_rsp_out), - .floo_req_o (router_3_8_req_out), - .floo_rsp_i (router_3_8_rsp_in) -); - - -floo_req_t [4:0] router_3_9_req_in; -floo_rsp_t [4:0] router_3_9_rsp_out; -floo_req_t [4:0] router_3_9_req_out; -floo_rsp_t [4:0] router_3_9_rsp_in; - - assign router_3_9_req_in[0] = router_3_10_to_router_3_9_req; - assign router_3_9_req_in[1] = router_4_9_to_router_3_9_req; - assign router_3_9_req_in[2] = router_3_8_to_router_3_9_req; - assign router_3_9_req_in[3] = router_2_9_to_router_3_9_req; - assign router_3_9_req_in[4] = magia_tile_ni_3_9_to_router_3_9_req; - - assign router_3_9_to_router_3_10_rsp = router_3_9_rsp_out[0]; - assign router_3_9_to_router_4_9_rsp = router_3_9_rsp_out[1]; - assign router_3_9_to_router_3_8_rsp = router_3_9_rsp_out[2]; - assign router_3_9_to_router_2_9_rsp = router_3_9_rsp_out[3]; - assign router_3_9_to_magia_tile_ni_3_9_rsp = router_3_9_rsp_out[4]; - - assign router_3_9_to_router_3_10_req = router_3_9_req_out[0]; - assign router_3_9_to_router_4_9_req = router_3_9_req_out[1]; - assign router_3_9_to_router_3_8_req = router_3_9_req_out[2]; - assign router_3_9_to_router_2_9_req = router_3_9_req_out[3]; - assign router_3_9_to_magia_tile_ni_3_9_req = router_3_9_req_out[4]; - - assign router_3_9_rsp_in[0] = router_3_10_to_router_3_9_rsp; - assign router_3_9_rsp_in[1] = router_4_9_to_router_3_9_rsp; - assign router_3_9_rsp_in[2] = router_3_8_to_router_3_9_rsp; - assign router_3_9_rsp_in[3] = router_2_9_to_router_3_9_rsp; - assign router_3_9_rsp_in[4] = magia_tile_ni_3_9_to_router_3_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_9_req_in), - .floo_rsp_o (router_3_9_rsp_out), - .floo_req_o (router_3_9_req_out), - .floo_rsp_i (router_3_9_rsp_in) -); - - -floo_req_t [4:0] router_3_10_req_in; -floo_rsp_t [4:0] router_3_10_rsp_out; -floo_req_t [4:0] router_3_10_req_out; -floo_rsp_t [4:0] router_3_10_rsp_in; - - assign router_3_10_req_in[0] = router_3_11_to_router_3_10_req; - assign router_3_10_req_in[1] = router_4_10_to_router_3_10_req; - assign router_3_10_req_in[2] = router_3_9_to_router_3_10_req; - assign router_3_10_req_in[3] = router_2_10_to_router_3_10_req; - assign router_3_10_req_in[4] = magia_tile_ni_3_10_to_router_3_10_req; - - assign router_3_10_to_router_3_11_rsp = router_3_10_rsp_out[0]; - assign router_3_10_to_router_4_10_rsp = router_3_10_rsp_out[1]; - assign router_3_10_to_router_3_9_rsp = router_3_10_rsp_out[2]; - assign router_3_10_to_router_2_10_rsp = router_3_10_rsp_out[3]; - assign router_3_10_to_magia_tile_ni_3_10_rsp = router_3_10_rsp_out[4]; - - assign router_3_10_to_router_3_11_req = router_3_10_req_out[0]; - assign router_3_10_to_router_4_10_req = router_3_10_req_out[1]; - assign router_3_10_to_router_3_9_req = router_3_10_req_out[2]; - assign router_3_10_to_router_2_10_req = router_3_10_req_out[3]; - assign router_3_10_to_magia_tile_ni_3_10_req = router_3_10_req_out[4]; - - assign router_3_10_rsp_in[0] = router_3_11_to_router_3_10_rsp; - assign router_3_10_rsp_in[1] = router_4_10_to_router_3_10_rsp; - assign router_3_10_rsp_in[2] = router_3_9_to_router_3_10_rsp; - assign router_3_10_rsp_in[3] = router_2_10_to_router_3_10_rsp; - assign router_3_10_rsp_in[4] = magia_tile_ni_3_10_to_router_3_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_10_req_in), - .floo_rsp_o (router_3_10_rsp_out), - .floo_req_o (router_3_10_req_out), - .floo_rsp_i (router_3_10_rsp_in) -); - - -floo_req_t [4:0] router_3_11_req_in; -floo_rsp_t [4:0] router_3_11_rsp_out; -floo_req_t [4:0] router_3_11_req_out; -floo_rsp_t [4:0] router_3_11_rsp_in; - - assign router_3_11_req_in[0] = router_3_12_to_router_3_11_req; - assign router_3_11_req_in[1] = router_4_11_to_router_3_11_req; - assign router_3_11_req_in[2] = router_3_10_to_router_3_11_req; - assign router_3_11_req_in[3] = router_2_11_to_router_3_11_req; - assign router_3_11_req_in[4] = magia_tile_ni_3_11_to_router_3_11_req; - - assign router_3_11_to_router_3_12_rsp = router_3_11_rsp_out[0]; - assign router_3_11_to_router_4_11_rsp = router_3_11_rsp_out[1]; - assign router_3_11_to_router_3_10_rsp = router_3_11_rsp_out[2]; - assign router_3_11_to_router_2_11_rsp = router_3_11_rsp_out[3]; - assign router_3_11_to_magia_tile_ni_3_11_rsp = router_3_11_rsp_out[4]; - - assign router_3_11_to_router_3_12_req = router_3_11_req_out[0]; - assign router_3_11_to_router_4_11_req = router_3_11_req_out[1]; - assign router_3_11_to_router_3_10_req = router_3_11_req_out[2]; - assign router_3_11_to_router_2_11_req = router_3_11_req_out[3]; - assign router_3_11_to_magia_tile_ni_3_11_req = router_3_11_req_out[4]; - - assign router_3_11_rsp_in[0] = router_3_12_to_router_3_11_rsp; - assign router_3_11_rsp_in[1] = router_4_11_to_router_3_11_rsp; - assign router_3_11_rsp_in[2] = router_3_10_to_router_3_11_rsp; - assign router_3_11_rsp_in[3] = router_2_11_to_router_3_11_rsp; - assign router_3_11_rsp_in[4] = magia_tile_ni_3_11_to_router_3_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_11_req_in), - .floo_rsp_o (router_3_11_rsp_out), - .floo_req_o (router_3_11_req_out), - .floo_rsp_i (router_3_11_rsp_in) -); - - -floo_req_t [4:0] router_3_12_req_in; -floo_rsp_t [4:0] router_3_12_rsp_out; -floo_req_t [4:0] router_3_12_req_out; -floo_rsp_t [4:0] router_3_12_rsp_in; - - assign router_3_12_req_in[0] = router_3_13_to_router_3_12_req; - assign router_3_12_req_in[1] = router_4_12_to_router_3_12_req; - assign router_3_12_req_in[2] = router_3_11_to_router_3_12_req; - assign router_3_12_req_in[3] = router_2_12_to_router_3_12_req; - assign router_3_12_req_in[4] = magia_tile_ni_3_12_to_router_3_12_req; - - assign router_3_12_to_router_3_13_rsp = router_3_12_rsp_out[0]; - assign router_3_12_to_router_4_12_rsp = router_3_12_rsp_out[1]; - assign router_3_12_to_router_3_11_rsp = router_3_12_rsp_out[2]; - assign router_3_12_to_router_2_12_rsp = router_3_12_rsp_out[3]; - assign router_3_12_to_magia_tile_ni_3_12_rsp = router_3_12_rsp_out[4]; - - assign router_3_12_to_router_3_13_req = router_3_12_req_out[0]; - assign router_3_12_to_router_4_12_req = router_3_12_req_out[1]; - assign router_3_12_to_router_3_11_req = router_3_12_req_out[2]; - assign router_3_12_to_router_2_12_req = router_3_12_req_out[3]; - assign router_3_12_to_magia_tile_ni_3_12_req = router_3_12_req_out[4]; - - assign router_3_12_rsp_in[0] = router_3_13_to_router_3_12_rsp; - assign router_3_12_rsp_in[1] = router_4_12_to_router_3_12_rsp; - assign router_3_12_rsp_in[2] = router_3_11_to_router_3_12_rsp; - assign router_3_12_rsp_in[3] = router_2_12_to_router_3_12_rsp; - assign router_3_12_rsp_in[4] = magia_tile_ni_3_12_to_router_3_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_12_req_in), - .floo_rsp_o (router_3_12_rsp_out), - .floo_req_o (router_3_12_req_out), - .floo_rsp_i (router_3_12_rsp_in) -); - - -floo_req_t [4:0] router_3_13_req_in; -floo_rsp_t [4:0] router_3_13_rsp_out; -floo_req_t [4:0] router_3_13_req_out; -floo_rsp_t [4:0] router_3_13_rsp_in; - - assign router_3_13_req_in[0] = router_3_14_to_router_3_13_req; - assign router_3_13_req_in[1] = router_4_13_to_router_3_13_req; - assign router_3_13_req_in[2] = router_3_12_to_router_3_13_req; - assign router_3_13_req_in[3] = router_2_13_to_router_3_13_req; - assign router_3_13_req_in[4] = magia_tile_ni_3_13_to_router_3_13_req; - - assign router_3_13_to_router_3_14_rsp = router_3_13_rsp_out[0]; - assign router_3_13_to_router_4_13_rsp = router_3_13_rsp_out[1]; - assign router_3_13_to_router_3_12_rsp = router_3_13_rsp_out[2]; - assign router_3_13_to_router_2_13_rsp = router_3_13_rsp_out[3]; - assign router_3_13_to_magia_tile_ni_3_13_rsp = router_3_13_rsp_out[4]; - - assign router_3_13_to_router_3_14_req = router_3_13_req_out[0]; - assign router_3_13_to_router_4_13_req = router_3_13_req_out[1]; - assign router_3_13_to_router_3_12_req = router_3_13_req_out[2]; - assign router_3_13_to_router_2_13_req = router_3_13_req_out[3]; - assign router_3_13_to_magia_tile_ni_3_13_req = router_3_13_req_out[4]; - - assign router_3_13_rsp_in[0] = router_3_14_to_router_3_13_rsp; - assign router_3_13_rsp_in[1] = router_4_13_to_router_3_13_rsp; - assign router_3_13_rsp_in[2] = router_3_12_to_router_3_13_rsp; - assign router_3_13_rsp_in[3] = router_2_13_to_router_3_13_rsp; - assign router_3_13_rsp_in[4] = magia_tile_ni_3_13_to_router_3_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_13_req_in), - .floo_rsp_o (router_3_13_rsp_out), - .floo_req_o (router_3_13_req_out), - .floo_rsp_i (router_3_13_rsp_in) -); - - -floo_req_t [4:0] router_3_14_req_in; -floo_rsp_t [4:0] router_3_14_rsp_out; -floo_req_t [4:0] router_3_14_req_out; -floo_rsp_t [4:0] router_3_14_rsp_in; - - assign router_3_14_req_in[0] = router_3_15_to_router_3_14_req; - assign router_3_14_req_in[1] = router_4_14_to_router_3_14_req; - assign router_3_14_req_in[2] = router_3_13_to_router_3_14_req; - assign router_3_14_req_in[3] = router_2_14_to_router_3_14_req; - assign router_3_14_req_in[4] = magia_tile_ni_3_14_to_router_3_14_req; - - assign router_3_14_to_router_3_15_rsp = router_3_14_rsp_out[0]; - assign router_3_14_to_router_4_14_rsp = router_3_14_rsp_out[1]; - assign router_3_14_to_router_3_13_rsp = router_3_14_rsp_out[2]; - assign router_3_14_to_router_2_14_rsp = router_3_14_rsp_out[3]; - assign router_3_14_to_magia_tile_ni_3_14_rsp = router_3_14_rsp_out[4]; - - assign router_3_14_to_router_3_15_req = router_3_14_req_out[0]; - assign router_3_14_to_router_4_14_req = router_3_14_req_out[1]; - assign router_3_14_to_router_3_13_req = router_3_14_req_out[2]; - assign router_3_14_to_router_2_14_req = router_3_14_req_out[3]; - assign router_3_14_to_magia_tile_ni_3_14_req = router_3_14_req_out[4]; - - assign router_3_14_rsp_in[0] = router_3_15_to_router_3_14_rsp; - assign router_3_14_rsp_in[1] = router_4_14_to_router_3_14_rsp; - assign router_3_14_rsp_in[2] = router_3_13_to_router_3_14_rsp; - assign router_3_14_rsp_in[3] = router_2_14_to_router_3_14_rsp; - assign router_3_14_rsp_in[4] = magia_tile_ni_3_14_to_router_3_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_14_req_in), - .floo_rsp_o (router_3_14_rsp_out), - .floo_req_o (router_3_14_req_out), - .floo_rsp_i (router_3_14_rsp_in) -); - - -floo_req_t [4:0] router_3_15_req_in; -floo_rsp_t [4:0] router_3_15_rsp_out; -floo_req_t [4:0] router_3_15_req_out; -floo_rsp_t [4:0] router_3_15_rsp_in; - - assign router_3_15_req_in[0] = '0; - assign router_3_15_req_in[1] = router_4_15_to_router_3_15_req; - assign router_3_15_req_in[2] = router_3_14_to_router_3_15_req; - assign router_3_15_req_in[3] = router_2_15_to_router_3_15_req; - assign router_3_15_req_in[4] = magia_tile_ni_3_15_to_router_3_15_req; - - assign router_3_15_to_router_4_15_rsp = router_3_15_rsp_out[1]; - assign router_3_15_to_router_3_14_rsp = router_3_15_rsp_out[2]; - assign router_3_15_to_router_2_15_rsp = router_3_15_rsp_out[3]; - assign router_3_15_to_magia_tile_ni_3_15_rsp = router_3_15_rsp_out[4]; - - assign router_3_15_to_router_4_15_req = router_3_15_req_out[1]; - assign router_3_15_to_router_3_14_req = router_3_15_req_out[2]; - assign router_3_15_to_router_2_15_req = router_3_15_req_out[3]; - assign router_3_15_to_magia_tile_ni_3_15_req = router_3_15_req_out[4]; - - assign router_3_15_rsp_in[0] = '0; - assign router_3_15_rsp_in[1] = router_4_15_to_router_3_15_rsp; - assign router_3_15_rsp_in[2] = router_3_14_to_router_3_15_rsp; - assign router_3_15_rsp_in[3] = router_2_15_to_router_3_15_rsp; - assign router_3_15_rsp_in[4] = magia_tile_ni_3_15_to_router_3_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_15_req_in), - .floo_rsp_o (router_3_15_rsp_out), - .floo_req_o (router_3_15_req_out), - .floo_rsp_i (router_3_15_rsp_in) -); - - -floo_req_t [4:0] router_4_0_req_in; -floo_rsp_t [4:0] router_4_0_rsp_out; -floo_req_t [4:0] router_4_0_req_out; -floo_rsp_t [4:0] router_4_0_rsp_in; - - assign router_4_0_req_in[0] = router_4_1_to_router_4_0_req; - assign router_4_0_req_in[1] = router_5_0_to_router_4_0_req; - assign router_4_0_req_in[2] = '0; - assign router_4_0_req_in[3] = router_3_0_to_router_4_0_req; - assign router_4_0_req_in[4] = magia_tile_ni_4_0_to_router_4_0_req; - - assign router_4_0_to_router_4_1_rsp = router_4_0_rsp_out[0]; - assign router_4_0_to_router_5_0_rsp = router_4_0_rsp_out[1]; - assign router_4_0_to_router_3_0_rsp = router_4_0_rsp_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_rsp = router_4_0_rsp_out[4]; - - assign router_4_0_to_router_4_1_req = router_4_0_req_out[0]; - assign router_4_0_to_router_5_0_req = router_4_0_req_out[1]; - assign router_4_0_to_router_3_0_req = router_4_0_req_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_req = router_4_0_req_out[4]; - - assign router_4_0_rsp_in[0] = router_4_1_to_router_4_0_rsp; - assign router_4_0_rsp_in[1] = router_5_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[2] = '0; - assign router_4_0_rsp_in[3] = router_3_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[4] = magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_0_req_in), - .floo_rsp_o (router_4_0_rsp_out), - .floo_req_o (router_4_0_req_out), - .floo_rsp_i (router_4_0_rsp_in) -); - - -floo_req_t [4:0] router_4_1_req_in; -floo_rsp_t [4:0] router_4_1_rsp_out; -floo_req_t [4:0] router_4_1_req_out; -floo_rsp_t [4:0] router_4_1_rsp_in; - - assign router_4_1_req_in[0] = router_4_2_to_router_4_1_req; - assign router_4_1_req_in[1] = router_5_1_to_router_4_1_req; - assign router_4_1_req_in[2] = router_4_0_to_router_4_1_req; - assign router_4_1_req_in[3] = router_3_1_to_router_4_1_req; - assign router_4_1_req_in[4] = magia_tile_ni_4_1_to_router_4_1_req; - - assign router_4_1_to_router_4_2_rsp = router_4_1_rsp_out[0]; - assign router_4_1_to_router_5_1_rsp = router_4_1_rsp_out[1]; - assign router_4_1_to_router_4_0_rsp = router_4_1_rsp_out[2]; - assign router_4_1_to_router_3_1_rsp = router_4_1_rsp_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_rsp = router_4_1_rsp_out[4]; - - assign router_4_1_to_router_4_2_req = router_4_1_req_out[0]; - assign router_4_1_to_router_5_1_req = router_4_1_req_out[1]; - assign router_4_1_to_router_4_0_req = router_4_1_req_out[2]; - assign router_4_1_to_router_3_1_req = router_4_1_req_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_req = router_4_1_req_out[4]; - - assign router_4_1_rsp_in[0] = router_4_2_to_router_4_1_rsp; - assign router_4_1_rsp_in[1] = router_5_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[2] = router_4_0_to_router_4_1_rsp; - assign router_4_1_rsp_in[3] = router_3_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[4] = magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_1_req_in), - .floo_rsp_o (router_4_1_rsp_out), - .floo_req_o (router_4_1_req_out), - .floo_rsp_i (router_4_1_rsp_in) -); - - -floo_req_t [4:0] router_4_2_req_in; -floo_rsp_t [4:0] router_4_2_rsp_out; -floo_req_t [4:0] router_4_2_req_out; -floo_rsp_t [4:0] router_4_2_rsp_in; - - assign router_4_2_req_in[0] = router_4_3_to_router_4_2_req; - assign router_4_2_req_in[1] = router_5_2_to_router_4_2_req; - assign router_4_2_req_in[2] = router_4_1_to_router_4_2_req; - assign router_4_2_req_in[3] = router_3_2_to_router_4_2_req; - assign router_4_2_req_in[4] = magia_tile_ni_4_2_to_router_4_2_req; - - assign router_4_2_to_router_4_3_rsp = router_4_2_rsp_out[0]; - assign router_4_2_to_router_5_2_rsp = router_4_2_rsp_out[1]; - assign router_4_2_to_router_4_1_rsp = router_4_2_rsp_out[2]; - assign router_4_2_to_router_3_2_rsp = router_4_2_rsp_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_rsp = router_4_2_rsp_out[4]; - - assign router_4_2_to_router_4_3_req = router_4_2_req_out[0]; - assign router_4_2_to_router_5_2_req = router_4_2_req_out[1]; - assign router_4_2_to_router_4_1_req = router_4_2_req_out[2]; - assign router_4_2_to_router_3_2_req = router_4_2_req_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_req = router_4_2_req_out[4]; - - assign router_4_2_rsp_in[0] = router_4_3_to_router_4_2_rsp; - assign router_4_2_rsp_in[1] = router_5_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[2] = router_4_1_to_router_4_2_rsp; - assign router_4_2_rsp_in[3] = router_3_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[4] = magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_2_req_in), - .floo_rsp_o (router_4_2_rsp_out), - .floo_req_o (router_4_2_req_out), - .floo_rsp_i (router_4_2_rsp_in) -); - - -floo_req_t [4:0] router_4_3_req_in; -floo_rsp_t [4:0] router_4_3_rsp_out; -floo_req_t [4:0] router_4_3_req_out; -floo_rsp_t [4:0] router_4_3_rsp_in; - - assign router_4_3_req_in[0] = router_4_4_to_router_4_3_req; - assign router_4_3_req_in[1] = router_5_3_to_router_4_3_req; - assign router_4_3_req_in[2] = router_4_2_to_router_4_3_req; - assign router_4_3_req_in[3] = router_3_3_to_router_4_3_req; - assign router_4_3_req_in[4] = magia_tile_ni_4_3_to_router_4_3_req; - - assign router_4_3_to_router_4_4_rsp = router_4_3_rsp_out[0]; - assign router_4_3_to_router_5_3_rsp = router_4_3_rsp_out[1]; - assign router_4_3_to_router_4_2_rsp = router_4_3_rsp_out[2]; - assign router_4_3_to_router_3_3_rsp = router_4_3_rsp_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_rsp = router_4_3_rsp_out[4]; - - assign router_4_3_to_router_4_4_req = router_4_3_req_out[0]; - assign router_4_3_to_router_5_3_req = router_4_3_req_out[1]; - assign router_4_3_to_router_4_2_req = router_4_3_req_out[2]; - assign router_4_3_to_router_3_3_req = router_4_3_req_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_req = router_4_3_req_out[4]; - - assign router_4_3_rsp_in[0] = router_4_4_to_router_4_3_rsp; - assign router_4_3_rsp_in[1] = router_5_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[2] = router_4_2_to_router_4_3_rsp; - assign router_4_3_rsp_in[3] = router_3_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[4] = magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_3_req_in), - .floo_rsp_o (router_4_3_rsp_out), - .floo_req_o (router_4_3_req_out), - .floo_rsp_i (router_4_3_rsp_in) -); - - -floo_req_t [4:0] router_4_4_req_in; -floo_rsp_t [4:0] router_4_4_rsp_out; -floo_req_t [4:0] router_4_4_req_out; -floo_rsp_t [4:0] router_4_4_rsp_in; - - assign router_4_4_req_in[0] = router_4_5_to_router_4_4_req; - assign router_4_4_req_in[1] = router_5_4_to_router_4_4_req; - assign router_4_4_req_in[2] = router_4_3_to_router_4_4_req; - assign router_4_4_req_in[3] = router_3_4_to_router_4_4_req; - assign router_4_4_req_in[4] = magia_tile_ni_4_4_to_router_4_4_req; - - assign router_4_4_to_router_4_5_rsp = router_4_4_rsp_out[0]; - assign router_4_4_to_router_5_4_rsp = router_4_4_rsp_out[1]; - assign router_4_4_to_router_4_3_rsp = router_4_4_rsp_out[2]; - assign router_4_4_to_router_3_4_rsp = router_4_4_rsp_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_rsp = router_4_4_rsp_out[4]; - - assign router_4_4_to_router_4_5_req = router_4_4_req_out[0]; - assign router_4_4_to_router_5_4_req = router_4_4_req_out[1]; - assign router_4_4_to_router_4_3_req = router_4_4_req_out[2]; - assign router_4_4_to_router_3_4_req = router_4_4_req_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_req = router_4_4_req_out[4]; - - assign router_4_4_rsp_in[0] = router_4_5_to_router_4_4_rsp; - assign router_4_4_rsp_in[1] = router_5_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[2] = router_4_3_to_router_4_4_rsp; - assign router_4_4_rsp_in[3] = router_3_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[4] = magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_4_req_in), - .floo_rsp_o (router_4_4_rsp_out), - .floo_req_o (router_4_4_req_out), - .floo_rsp_i (router_4_4_rsp_in) -); - - -floo_req_t [4:0] router_4_5_req_in; -floo_rsp_t [4:0] router_4_5_rsp_out; -floo_req_t [4:0] router_4_5_req_out; -floo_rsp_t [4:0] router_4_5_rsp_in; - - assign router_4_5_req_in[0] = router_4_6_to_router_4_5_req; - assign router_4_5_req_in[1] = router_5_5_to_router_4_5_req; - assign router_4_5_req_in[2] = router_4_4_to_router_4_5_req; - assign router_4_5_req_in[3] = router_3_5_to_router_4_5_req; - assign router_4_5_req_in[4] = magia_tile_ni_4_5_to_router_4_5_req; - - assign router_4_5_to_router_4_6_rsp = router_4_5_rsp_out[0]; - assign router_4_5_to_router_5_5_rsp = router_4_5_rsp_out[1]; - assign router_4_5_to_router_4_4_rsp = router_4_5_rsp_out[2]; - assign router_4_5_to_router_3_5_rsp = router_4_5_rsp_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_rsp = router_4_5_rsp_out[4]; - - assign router_4_5_to_router_4_6_req = router_4_5_req_out[0]; - assign router_4_5_to_router_5_5_req = router_4_5_req_out[1]; - assign router_4_5_to_router_4_4_req = router_4_5_req_out[2]; - assign router_4_5_to_router_3_5_req = router_4_5_req_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_req = router_4_5_req_out[4]; - - assign router_4_5_rsp_in[0] = router_4_6_to_router_4_5_rsp; - assign router_4_5_rsp_in[1] = router_5_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[2] = router_4_4_to_router_4_5_rsp; - assign router_4_5_rsp_in[3] = router_3_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[4] = magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_5_req_in), - .floo_rsp_o (router_4_5_rsp_out), - .floo_req_o (router_4_5_req_out), - .floo_rsp_i (router_4_5_rsp_in) -); - - -floo_req_t [4:0] router_4_6_req_in; -floo_rsp_t [4:0] router_4_6_rsp_out; -floo_req_t [4:0] router_4_6_req_out; -floo_rsp_t [4:0] router_4_6_rsp_in; - - assign router_4_6_req_in[0] = router_4_7_to_router_4_6_req; - assign router_4_6_req_in[1] = router_5_6_to_router_4_6_req; - assign router_4_6_req_in[2] = router_4_5_to_router_4_6_req; - assign router_4_6_req_in[3] = router_3_6_to_router_4_6_req; - assign router_4_6_req_in[4] = magia_tile_ni_4_6_to_router_4_6_req; - - assign router_4_6_to_router_4_7_rsp = router_4_6_rsp_out[0]; - assign router_4_6_to_router_5_6_rsp = router_4_6_rsp_out[1]; - assign router_4_6_to_router_4_5_rsp = router_4_6_rsp_out[2]; - assign router_4_6_to_router_3_6_rsp = router_4_6_rsp_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_rsp = router_4_6_rsp_out[4]; - - assign router_4_6_to_router_4_7_req = router_4_6_req_out[0]; - assign router_4_6_to_router_5_6_req = router_4_6_req_out[1]; - assign router_4_6_to_router_4_5_req = router_4_6_req_out[2]; - assign router_4_6_to_router_3_6_req = router_4_6_req_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_req = router_4_6_req_out[4]; - - assign router_4_6_rsp_in[0] = router_4_7_to_router_4_6_rsp; - assign router_4_6_rsp_in[1] = router_5_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[2] = router_4_5_to_router_4_6_rsp; - assign router_4_6_rsp_in[3] = router_3_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[4] = magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_6_req_in), - .floo_rsp_o (router_4_6_rsp_out), - .floo_req_o (router_4_6_req_out), - .floo_rsp_i (router_4_6_rsp_in) -); - - -floo_req_t [4:0] router_4_7_req_in; -floo_rsp_t [4:0] router_4_7_rsp_out; -floo_req_t [4:0] router_4_7_req_out; -floo_rsp_t [4:0] router_4_7_rsp_in; - - assign router_4_7_req_in[0] = router_4_8_to_router_4_7_req; - assign router_4_7_req_in[1] = router_5_7_to_router_4_7_req; - assign router_4_7_req_in[2] = router_4_6_to_router_4_7_req; - assign router_4_7_req_in[3] = router_3_7_to_router_4_7_req; - assign router_4_7_req_in[4] = magia_tile_ni_4_7_to_router_4_7_req; - - assign router_4_7_to_router_4_8_rsp = router_4_7_rsp_out[0]; - assign router_4_7_to_router_5_7_rsp = router_4_7_rsp_out[1]; - assign router_4_7_to_router_4_6_rsp = router_4_7_rsp_out[2]; - assign router_4_7_to_router_3_7_rsp = router_4_7_rsp_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_rsp = router_4_7_rsp_out[4]; - - assign router_4_7_to_router_4_8_req = router_4_7_req_out[0]; - assign router_4_7_to_router_5_7_req = router_4_7_req_out[1]; - assign router_4_7_to_router_4_6_req = router_4_7_req_out[2]; - assign router_4_7_to_router_3_7_req = router_4_7_req_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_req = router_4_7_req_out[4]; - - assign router_4_7_rsp_in[0] = router_4_8_to_router_4_7_rsp; - assign router_4_7_rsp_in[1] = router_5_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[2] = router_4_6_to_router_4_7_rsp; - assign router_4_7_rsp_in[3] = router_3_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[4] = magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_7_req_in), - .floo_rsp_o (router_4_7_rsp_out), - .floo_req_o (router_4_7_req_out), - .floo_rsp_i (router_4_7_rsp_in) -); - - -floo_req_t [4:0] router_4_8_req_in; -floo_rsp_t [4:0] router_4_8_rsp_out; -floo_req_t [4:0] router_4_8_req_out; -floo_rsp_t [4:0] router_4_8_rsp_in; - - assign router_4_8_req_in[0] = router_4_9_to_router_4_8_req; - assign router_4_8_req_in[1] = router_5_8_to_router_4_8_req; - assign router_4_8_req_in[2] = router_4_7_to_router_4_8_req; - assign router_4_8_req_in[3] = router_3_8_to_router_4_8_req; - assign router_4_8_req_in[4] = magia_tile_ni_4_8_to_router_4_8_req; - - assign router_4_8_to_router_4_9_rsp = router_4_8_rsp_out[0]; - assign router_4_8_to_router_5_8_rsp = router_4_8_rsp_out[1]; - assign router_4_8_to_router_4_7_rsp = router_4_8_rsp_out[2]; - assign router_4_8_to_router_3_8_rsp = router_4_8_rsp_out[3]; - assign router_4_8_to_magia_tile_ni_4_8_rsp = router_4_8_rsp_out[4]; - - assign router_4_8_to_router_4_9_req = router_4_8_req_out[0]; - assign router_4_8_to_router_5_8_req = router_4_8_req_out[1]; - assign router_4_8_to_router_4_7_req = router_4_8_req_out[2]; - assign router_4_8_to_router_3_8_req = router_4_8_req_out[3]; - assign router_4_8_to_magia_tile_ni_4_8_req = router_4_8_req_out[4]; - - assign router_4_8_rsp_in[0] = router_4_9_to_router_4_8_rsp; - assign router_4_8_rsp_in[1] = router_5_8_to_router_4_8_rsp; - assign router_4_8_rsp_in[2] = router_4_7_to_router_4_8_rsp; - assign router_4_8_rsp_in[3] = router_3_8_to_router_4_8_rsp; - assign router_4_8_rsp_in[4] = magia_tile_ni_4_8_to_router_4_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_8_req_in), - .floo_rsp_o (router_4_8_rsp_out), - .floo_req_o (router_4_8_req_out), - .floo_rsp_i (router_4_8_rsp_in) -); - - -floo_req_t [4:0] router_4_9_req_in; -floo_rsp_t [4:0] router_4_9_rsp_out; -floo_req_t [4:0] router_4_9_req_out; -floo_rsp_t [4:0] router_4_9_rsp_in; - - assign router_4_9_req_in[0] = router_4_10_to_router_4_9_req; - assign router_4_9_req_in[1] = router_5_9_to_router_4_9_req; - assign router_4_9_req_in[2] = router_4_8_to_router_4_9_req; - assign router_4_9_req_in[3] = router_3_9_to_router_4_9_req; - assign router_4_9_req_in[4] = magia_tile_ni_4_9_to_router_4_9_req; - - assign router_4_9_to_router_4_10_rsp = router_4_9_rsp_out[0]; - assign router_4_9_to_router_5_9_rsp = router_4_9_rsp_out[1]; - assign router_4_9_to_router_4_8_rsp = router_4_9_rsp_out[2]; - assign router_4_9_to_router_3_9_rsp = router_4_9_rsp_out[3]; - assign router_4_9_to_magia_tile_ni_4_9_rsp = router_4_9_rsp_out[4]; - - assign router_4_9_to_router_4_10_req = router_4_9_req_out[0]; - assign router_4_9_to_router_5_9_req = router_4_9_req_out[1]; - assign router_4_9_to_router_4_8_req = router_4_9_req_out[2]; - assign router_4_9_to_router_3_9_req = router_4_9_req_out[3]; - assign router_4_9_to_magia_tile_ni_4_9_req = router_4_9_req_out[4]; - - assign router_4_9_rsp_in[0] = router_4_10_to_router_4_9_rsp; - assign router_4_9_rsp_in[1] = router_5_9_to_router_4_9_rsp; - assign router_4_9_rsp_in[2] = router_4_8_to_router_4_9_rsp; - assign router_4_9_rsp_in[3] = router_3_9_to_router_4_9_rsp; - assign router_4_9_rsp_in[4] = magia_tile_ni_4_9_to_router_4_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_9_req_in), - .floo_rsp_o (router_4_9_rsp_out), - .floo_req_o (router_4_9_req_out), - .floo_rsp_i (router_4_9_rsp_in) -); - - -floo_req_t [4:0] router_4_10_req_in; -floo_rsp_t [4:0] router_4_10_rsp_out; -floo_req_t [4:0] router_4_10_req_out; -floo_rsp_t [4:0] router_4_10_rsp_in; - - assign router_4_10_req_in[0] = router_4_11_to_router_4_10_req; - assign router_4_10_req_in[1] = router_5_10_to_router_4_10_req; - assign router_4_10_req_in[2] = router_4_9_to_router_4_10_req; - assign router_4_10_req_in[3] = router_3_10_to_router_4_10_req; - assign router_4_10_req_in[4] = magia_tile_ni_4_10_to_router_4_10_req; - - assign router_4_10_to_router_4_11_rsp = router_4_10_rsp_out[0]; - assign router_4_10_to_router_5_10_rsp = router_4_10_rsp_out[1]; - assign router_4_10_to_router_4_9_rsp = router_4_10_rsp_out[2]; - assign router_4_10_to_router_3_10_rsp = router_4_10_rsp_out[3]; - assign router_4_10_to_magia_tile_ni_4_10_rsp = router_4_10_rsp_out[4]; - - assign router_4_10_to_router_4_11_req = router_4_10_req_out[0]; - assign router_4_10_to_router_5_10_req = router_4_10_req_out[1]; - assign router_4_10_to_router_4_9_req = router_4_10_req_out[2]; - assign router_4_10_to_router_3_10_req = router_4_10_req_out[3]; - assign router_4_10_to_magia_tile_ni_4_10_req = router_4_10_req_out[4]; - - assign router_4_10_rsp_in[0] = router_4_11_to_router_4_10_rsp; - assign router_4_10_rsp_in[1] = router_5_10_to_router_4_10_rsp; - assign router_4_10_rsp_in[2] = router_4_9_to_router_4_10_rsp; - assign router_4_10_rsp_in[3] = router_3_10_to_router_4_10_rsp; - assign router_4_10_rsp_in[4] = magia_tile_ni_4_10_to_router_4_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_10_req_in), - .floo_rsp_o (router_4_10_rsp_out), - .floo_req_o (router_4_10_req_out), - .floo_rsp_i (router_4_10_rsp_in) -); - - -floo_req_t [4:0] router_4_11_req_in; -floo_rsp_t [4:0] router_4_11_rsp_out; -floo_req_t [4:0] router_4_11_req_out; -floo_rsp_t [4:0] router_4_11_rsp_in; - - assign router_4_11_req_in[0] = router_4_12_to_router_4_11_req; - assign router_4_11_req_in[1] = router_5_11_to_router_4_11_req; - assign router_4_11_req_in[2] = router_4_10_to_router_4_11_req; - assign router_4_11_req_in[3] = router_3_11_to_router_4_11_req; - assign router_4_11_req_in[4] = magia_tile_ni_4_11_to_router_4_11_req; - - assign router_4_11_to_router_4_12_rsp = router_4_11_rsp_out[0]; - assign router_4_11_to_router_5_11_rsp = router_4_11_rsp_out[1]; - assign router_4_11_to_router_4_10_rsp = router_4_11_rsp_out[2]; - assign router_4_11_to_router_3_11_rsp = router_4_11_rsp_out[3]; - assign router_4_11_to_magia_tile_ni_4_11_rsp = router_4_11_rsp_out[4]; - - assign router_4_11_to_router_4_12_req = router_4_11_req_out[0]; - assign router_4_11_to_router_5_11_req = router_4_11_req_out[1]; - assign router_4_11_to_router_4_10_req = router_4_11_req_out[2]; - assign router_4_11_to_router_3_11_req = router_4_11_req_out[3]; - assign router_4_11_to_magia_tile_ni_4_11_req = router_4_11_req_out[4]; - - assign router_4_11_rsp_in[0] = router_4_12_to_router_4_11_rsp; - assign router_4_11_rsp_in[1] = router_5_11_to_router_4_11_rsp; - assign router_4_11_rsp_in[2] = router_4_10_to_router_4_11_rsp; - assign router_4_11_rsp_in[3] = router_3_11_to_router_4_11_rsp; - assign router_4_11_rsp_in[4] = magia_tile_ni_4_11_to_router_4_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_11_req_in), - .floo_rsp_o (router_4_11_rsp_out), - .floo_req_o (router_4_11_req_out), - .floo_rsp_i (router_4_11_rsp_in) -); - - -floo_req_t [4:0] router_4_12_req_in; -floo_rsp_t [4:0] router_4_12_rsp_out; -floo_req_t [4:0] router_4_12_req_out; -floo_rsp_t [4:0] router_4_12_rsp_in; - - assign router_4_12_req_in[0] = router_4_13_to_router_4_12_req; - assign router_4_12_req_in[1] = router_5_12_to_router_4_12_req; - assign router_4_12_req_in[2] = router_4_11_to_router_4_12_req; - assign router_4_12_req_in[3] = router_3_12_to_router_4_12_req; - assign router_4_12_req_in[4] = magia_tile_ni_4_12_to_router_4_12_req; - - assign router_4_12_to_router_4_13_rsp = router_4_12_rsp_out[0]; - assign router_4_12_to_router_5_12_rsp = router_4_12_rsp_out[1]; - assign router_4_12_to_router_4_11_rsp = router_4_12_rsp_out[2]; - assign router_4_12_to_router_3_12_rsp = router_4_12_rsp_out[3]; - assign router_4_12_to_magia_tile_ni_4_12_rsp = router_4_12_rsp_out[4]; - - assign router_4_12_to_router_4_13_req = router_4_12_req_out[0]; - assign router_4_12_to_router_5_12_req = router_4_12_req_out[1]; - assign router_4_12_to_router_4_11_req = router_4_12_req_out[2]; - assign router_4_12_to_router_3_12_req = router_4_12_req_out[3]; - assign router_4_12_to_magia_tile_ni_4_12_req = router_4_12_req_out[4]; - - assign router_4_12_rsp_in[0] = router_4_13_to_router_4_12_rsp; - assign router_4_12_rsp_in[1] = router_5_12_to_router_4_12_rsp; - assign router_4_12_rsp_in[2] = router_4_11_to_router_4_12_rsp; - assign router_4_12_rsp_in[3] = router_3_12_to_router_4_12_rsp; - assign router_4_12_rsp_in[4] = magia_tile_ni_4_12_to_router_4_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_12_req_in), - .floo_rsp_o (router_4_12_rsp_out), - .floo_req_o (router_4_12_req_out), - .floo_rsp_i (router_4_12_rsp_in) -); - - -floo_req_t [4:0] router_4_13_req_in; -floo_rsp_t [4:0] router_4_13_rsp_out; -floo_req_t [4:0] router_4_13_req_out; -floo_rsp_t [4:0] router_4_13_rsp_in; - - assign router_4_13_req_in[0] = router_4_14_to_router_4_13_req; - assign router_4_13_req_in[1] = router_5_13_to_router_4_13_req; - assign router_4_13_req_in[2] = router_4_12_to_router_4_13_req; - assign router_4_13_req_in[3] = router_3_13_to_router_4_13_req; - assign router_4_13_req_in[4] = magia_tile_ni_4_13_to_router_4_13_req; - - assign router_4_13_to_router_4_14_rsp = router_4_13_rsp_out[0]; - assign router_4_13_to_router_5_13_rsp = router_4_13_rsp_out[1]; - assign router_4_13_to_router_4_12_rsp = router_4_13_rsp_out[2]; - assign router_4_13_to_router_3_13_rsp = router_4_13_rsp_out[3]; - assign router_4_13_to_magia_tile_ni_4_13_rsp = router_4_13_rsp_out[4]; - - assign router_4_13_to_router_4_14_req = router_4_13_req_out[0]; - assign router_4_13_to_router_5_13_req = router_4_13_req_out[1]; - assign router_4_13_to_router_4_12_req = router_4_13_req_out[2]; - assign router_4_13_to_router_3_13_req = router_4_13_req_out[3]; - assign router_4_13_to_magia_tile_ni_4_13_req = router_4_13_req_out[4]; - - assign router_4_13_rsp_in[0] = router_4_14_to_router_4_13_rsp; - assign router_4_13_rsp_in[1] = router_5_13_to_router_4_13_rsp; - assign router_4_13_rsp_in[2] = router_4_12_to_router_4_13_rsp; - assign router_4_13_rsp_in[3] = router_3_13_to_router_4_13_rsp; - assign router_4_13_rsp_in[4] = magia_tile_ni_4_13_to_router_4_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_13_req_in), - .floo_rsp_o (router_4_13_rsp_out), - .floo_req_o (router_4_13_req_out), - .floo_rsp_i (router_4_13_rsp_in) -); - - -floo_req_t [4:0] router_4_14_req_in; -floo_rsp_t [4:0] router_4_14_rsp_out; -floo_req_t [4:0] router_4_14_req_out; -floo_rsp_t [4:0] router_4_14_rsp_in; - - assign router_4_14_req_in[0] = router_4_15_to_router_4_14_req; - assign router_4_14_req_in[1] = router_5_14_to_router_4_14_req; - assign router_4_14_req_in[2] = router_4_13_to_router_4_14_req; - assign router_4_14_req_in[3] = router_3_14_to_router_4_14_req; - assign router_4_14_req_in[4] = magia_tile_ni_4_14_to_router_4_14_req; - - assign router_4_14_to_router_4_15_rsp = router_4_14_rsp_out[0]; - assign router_4_14_to_router_5_14_rsp = router_4_14_rsp_out[1]; - assign router_4_14_to_router_4_13_rsp = router_4_14_rsp_out[2]; - assign router_4_14_to_router_3_14_rsp = router_4_14_rsp_out[3]; - assign router_4_14_to_magia_tile_ni_4_14_rsp = router_4_14_rsp_out[4]; - - assign router_4_14_to_router_4_15_req = router_4_14_req_out[0]; - assign router_4_14_to_router_5_14_req = router_4_14_req_out[1]; - assign router_4_14_to_router_4_13_req = router_4_14_req_out[2]; - assign router_4_14_to_router_3_14_req = router_4_14_req_out[3]; - assign router_4_14_to_magia_tile_ni_4_14_req = router_4_14_req_out[4]; - - assign router_4_14_rsp_in[0] = router_4_15_to_router_4_14_rsp; - assign router_4_14_rsp_in[1] = router_5_14_to_router_4_14_rsp; - assign router_4_14_rsp_in[2] = router_4_13_to_router_4_14_rsp; - assign router_4_14_rsp_in[3] = router_3_14_to_router_4_14_rsp; - assign router_4_14_rsp_in[4] = magia_tile_ni_4_14_to_router_4_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_14_req_in), - .floo_rsp_o (router_4_14_rsp_out), - .floo_req_o (router_4_14_req_out), - .floo_rsp_i (router_4_14_rsp_in) -); - - -floo_req_t [4:0] router_4_15_req_in; -floo_rsp_t [4:0] router_4_15_rsp_out; -floo_req_t [4:0] router_4_15_req_out; -floo_rsp_t [4:0] router_4_15_rsp_in; - - assign router_4_15_req_in[0] = '0; - assign router_4_15_req_in[1] = router_5_15_to_router_4_15_req; - assign router_4_15_req_in[2] = router_4_14_to_router_4_15_req; - assign router_4_15_req_in[3] = router_3_15_to_router_4_15_req; - assign router_4_15_req_in[4] = magia_tile_ni_4_15_to_router_4_15_req; - - assign router_4_15_to_router_5_15_rsp = router_4_15_rsp_out[1]; - assign router_4_15_to_router_4_14_rsp = router_4_15_rsp_out[2]; - assign router_4_15_to_router_3_15_rsp = router_4_15_rsp_out[3]; - assign router_4_15_to_magia_tile_ni_4_15_rsp = router_4_15_rsp_out[4]; - - assign router_4_15_to_router_5_15_req = router_4_15_req_out[1]; - assign router_4_15_to_router_4_14_req = router_4_15_req_out[2]; - assign router_4_15_to_router_3_15_req = router_4_15_req_out[3]; - assign router_4_15_to_magia_tile_ni_4_15_req = router_4_15_req_out[4]; - - assign router_4_15_rsp_in[0] = '0; - assign router_4_15_rsp_in[1] = router_5_15_to_router_4_15_rsp; - assign router_4_15_rsp_in[2] = router_4_14_to_router_4_15_rsp; - assign router_4_15_rsp_in[3] = router_3_15_to_router_4_15_rsp; - assign router_4_15_rsp_in[4] = magia_tile_ni_4_15_to_router_4_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_15_req_in), - .floo_rsp_o (router_4_15_rsp_out), - .floo_req_o (router_4_15_req_out), - .floo_rsp_i (router_4_15_rsp_in) -); - - -floo_req_t [4:0] router_5_0_req_in; -floo_rsp_t [4:0] router_5_0_rsp_out; -floo_req_t [4:0] router_5_0_req_out; -floo_rsp_t [4:0] router_5_0_rsp_in; - - assign router_5_0_req_in[0] = router_5_1_to_router_5_0_req; - assign router_5_0_req_in[1] = router_6_0_to_router_5_0_req; - assign router_5_0_req_in[2] = '0; - assign router_5_0_req_in[3] = router_4_0_to_router_5_0_req; - assign router_5_0_req_in[4] = magia_tile_ni_5_0_to_router_5_0_req; - - assign router_5_0_to_router_5_1_rsp = router_5_0_rsp_out[0]; - assign router_5_0_to_router_6_0_rsp = router_5_0_rsp_out[1]; - assign router_5_0_to_router_4_0_rsp = router_5_0_rsp_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_rsp = router_5_0_rsp_out[4]; - - assign router_5_0_to_router_5_1_req = router_5_0_req_out[0]; - assign router_5_0_to_router_6_0_req = router_5_0_req_out[1]; - assign router_5_0_to_router_4_0_req = router_5_0_req_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_req = router_5_0_req_out[4]; - - assign router_5_0_rsp_in[0] = router_5_1_to_router_5_0_rsp; - assign router_5_0_rsp_in[1] = router_6_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[2] = '0; - assign router_5_0_rsp_in[3] = router_4_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[4] = magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_0_req_in), - .floo_rsp_o (router_5_0_rsp_out), - .floo_req_o (router_5_0_req_out), - .floo_rsp_i (router_5_0_rsp_in) -); - - -floo_req_t [4:0] router_5_1_req_in; -floo_rsp_t [4:0] router_5_1_rsp_out; -floo_req_t [4:0] router_5_1_req_out; -floo_rsp_t [4:0] router_5_1_rsp_in; - - assign router_5_1_req_in[0] = router_5_2_to_router_5_1_req; - assign router_5_1_req_in[1] = router_6_1_to_router_5_1_req; - assign router_5_1_req_in[2] = router_5_0_to_router_5_1_req; - assign router_5_1_req_in[3] = router_4_1_to_router_5_1_req; - assign router_5_1_req_in[4] = magia_tile_ni_5_1_to_router_5_1_req; - - assign router_5_1_to_router_5_2_rsp = router_5_1_rsp_out[0]; - assign router_5_1_to_router_6_1_rsp = router_5_1_rsp_out[1]; - assign router_5_1_to_router_5_0_rsp = router_5_1_rsp_out[2]; - assign router_5_1_to_router_4_1_rsp = router_5_1_rsp_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_rsp = router_5_1_rsp_out[4]; - - assign router_5_1_to_router_5_2_req = router_5_1_req_out[0]; - assign router_5_1_to_router_6_1_req = router_5_1_req_out[1]; - assign router_5_1_to_router_5_0_req = router_5_1_req_out[2]; - assign router_5_1_to_router_4_1_req = router_5_1_req_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_req = router_5_1_req_out[4]; - - assign router_5_1_rsp_in[0] = router_5_2_to_router_5_1_rsp; - assign router_5_1_rsp_in[1] = router_6_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[2] = router_5_0_to_router_5_1_rsp; - assign router_5_1_rsp_in[3] = router_4_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[4] = magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_1_req_in), - .floo_rsp_o (router_5_1_rsp_out), - .floo_req_o (router_5_1_req_out), - .floo_rsp_i (router_5_1_rsp_in) -); - - -floo_req_t [4:0] router_5_2_req_in; -floo_rsp_t [4:0] router_5_2_rsp_out; -floo_req_t [4:0] router_5_2_req_out; -floo_rsp_t [4:0] router_5_2_rsp_in; - - assign router_5_2_req_in[0] = router_5_3_to_router_5_2_req; - assign router_5_2_req_in[1] = router_6_2_to_router_5_2_req; - assign router_5_2_req_in[2] = router_5_1_to_router_5_2_req; - assign router_5_2_req_in[3] = router_4_2_to_router_5_2_req; - assign router_5_2_req_in[4] = magia_tile_ni_5_2_to_router_5_2_req; - - assign router_5_2_to_router_5_3_rsp = router_5_2_rsp_out[0]; - assign router_5_2_to_router_6_2_rsp = router_5_2_rsp_out[1]; - assign router_5_2_to_router_5_1_rsp = router_5_2_rsp_out[2]; - assign router_5_2_to_router_4_2_rsp = router_5_2_rsp_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_rsp = router_5_2_rsp_out[4]; - - assign router_5_2_to_router_5_3_req = router_5_2_req_out[0]; - assign router_5_2_to_router_6_2_req = router_5_2_req_out[1]; - assign router_5_2_to_router_5_1_req = router_5_2_req_out[2]; - assign router_5_2_to_router_4_2_req = router_5_2_req_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_req = router_5_2_req_out[4]; - - assign router_5_2_rsp_in[0] = router_5_3_to_router_5_2_rsp; - assign router_5_2_rsp_in[1] = router_6_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[2] = router_5_1_to_router_5_2_rsp; - assign router_5_2_rsp_in[3] = router_4_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[4] = magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_2_req_in), - .floo_rsp_o (router_5_2_rsp_out), - .floo_req_o (router_5_2_req_out), - .floo_rsp_i (router_5_2_rsp_in) -); - - -floo_req_t [4:0] router_5_3_req_in; -floo_rsp_t [4:0] router_5_3_rsp_out; -floo_req_t [4:0] router_5_3_req_out; -floo_rsp_t [4:0] router_5_3_rsp_in; - - assign router_5_3_req_in[0] = router_5_4_to_router_5_3_req; - assign router_5_3_req_in[1] = router_6_3_to_router_5_3_req; - assign router_5_3_req_in[2] = router_5_2_to_router_5_3_req; - assign router_5_3_req_in[3] = router_4_3_to_router_5_3_req; - assign router_5_3_req_in[4] = magia_tile_ni_5_3_to_router_5_3_req; - - assign router_5_3_to_router_5_4_rsp = router_5_3_rsp_out[0]; - assign router_5_3_to_router_6_3_rsp = router_5_3_rsp_out[1]; - assign router_5_3_to_router_5_2_rsp = router_5_3_rsp_out[2]; - assign router_5_3_to_router_4_3_rsp = router_5_3_rsp_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_rsp = router_5_3_rsp_out[4]; - - assign router_5_3_to_router_5_4_req = router_5_3_req_out[0]; - assign router_5_3_to_router_6_3_req = router_5_3_req_out[1]; - assign router_5_3_to_router_5_2_req = router_5_3_req_out[2]; - assign router_5_3_to_router_4_3_req = router_5_3_req_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_req = router_5_3_req_out[4]; - - assign router_5_3_rsp_in[0] = router_5_4_to_router_5_3_rsp; - assign router_5_3_rsp_in[1] = router_6_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[2] = router_5_2_to_router_5_3_rsp; - assign router_5_3_rsp_in[3] = router_4_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[4] = magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_3_req_in), - .floo_rsp_o (router_5_3_rsp_out), - .floo_req_o (router_5_3_req_out), - .floo_rsp_i (router_5_3_rsp_in) -); - - -floo_req_t [4:0] router_5_4_req_in; -floo_rsp_t [4:0] router_5_4_rsp_out; -floo_req_t [4:0] router_5_4_req_out; -floo_rsp_t [4:0] router_5_4_rsp_in; - - assign router_5_4_req_in[0] = router_5_5_to_router_5_4_req; - assign router_5_4_req_in[1] = router_6_4_to_router_5_4_req; - assign router_5_4_req_in[2] = router_5_3_to_router_5_4_req; - assign router_5_4_req_in[3] = router_4_4_to_router_5_4_req; - assign router_5_4_req_in[4] = magia_tile_ni_5_4_to_router_5_4_req; - - assign router_5_4_to_router_5_5_rsp = router_5_4_rsp_out[0]; - assign router_5_4_to_router_6_4_rsp = router_5_4_rsp_out[1]; - assign router_5_4_to_router_5_3_rsp = router_5_4_rsp_out[2]; - assign router_5_4_to_router_4_4_rsp = router_5_4_rsp_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_rsp = router_5_4_rsp_out[4]; - - assign router_5_4_to_router_5_5_req = router_5_4_req_out[0]; - assign router_5_4_to_router_6_4_req = router_5_4_req_out[1]; - assign router_5_4_to_router_5_3_req = router_5_4_req_out[2]; - assign router_5_4_to_router_4_4_req = router_5_4_req_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_req = router_5_4_req_out[4]; - - assign router_5_4_rsp_in[0] = router_5_5_to_router_5_4_rsp; - assign router_5_4_rsp_in[1] = router_6_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[2] = router_5_3_to_router_5_4_rsp; - assign router_5_4_rsp_in[3] = router_4_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[4] = magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_4_req_in), - .floo_rsp_o (router_5_4_rsp_out), - .floo_req_o (router_5_4_req_out), - .floo_rsp_i (router_5_4_rsp_in) -); - - -floo_req_t [4:0] router_5_5_req_in; -floo_rsp_t [4:0] router_5_5_rsp_out; -floo_req_t [4:0] router_5_5_req_out; -floo_rsp_t [4:0] router_5_5_rsp_in; - - assign router_5_5_req_in[0] = router_5_6_to_router_5_5_req; - assign router_5_5_req_in[1] = router_6_5_to_router_5_5_req; - assign router_5_5_req_in[2] = router_5_4_to_router_5_5_req; - assign router_5_5_req_in[3] = router_4_5_to_router_5_5_req; - assign router_5_5_req_in[4] = magia_tile_ni_5_5_to_router_5_5_req; - - assign router_5_5_to_router_5_6_rsp = router_5_5_rsp_out[0]; - assign router_5_5_to_router_6_5_rsp = router_5_5_rsp_out[1]; - assign router_5_5_to_router_5_4_rsp = router_5_5_rsp_out[2]; - assign router_5_5_to_router_4_5_rsp = router_5_5_rsp_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_rsp = router_5_5_rsp_out[4]; - - assign router_5_5_to_router_5_6_req = router_5_5_req_out[0]; - assign router_5_5_to_router_6_5_req = router_5_5_req_out[1]; - assign router_5_5_to_router_5_4_req = router_5_5_req_out[2]; - assign router_5_5_to_router_4_5_req = router_5_5_req_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_req = router_5_5_req_out[4]; - - assign router_5_5_rsp_in[0] = router_5_6_to_router_5_5_rsp; - assign router_5_5_rsp_in[1] = router_6_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[2] = router_5_4_to_router_5_5_rsp; - assign router_5_5_rsp_in[3] = router_4_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[4] = magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_5_req_in), - .floo_rsp_o (router_5_5_rsp_out), - .floo_req_o (router_5_5_req_out), - .floo_rsp_i (router_5_5_rsp_in) -); - - -floo_req_t [4:0] router_5_6_req_in; -floo_rsp_t [4:0] router_5_6_rsp_out; -floo_req_t [4:0] router_5_6_req_out; -floo_rsp_t [4:0] router_5_6_rsp_in; - - assign router_5_6_req_in[0] = router_5_7_to_router_5_6_req; - assign router_5_6_req_in[1] = router_6_6_to_router_5_6_req; - assign router_5_6_req_in[2] = router_5_5_to_router_5_6_req; - assign router_5_6_req_in[3] = router_4_6_to_router_5_6_req; - assign router_5_6_req_in[4] = magia_tile_ni_5_6_to_router_5_6_req; - - assign router_5_6_to_router_5_7_rsp = router_5_6_rsp_out[0]; - assign router_5_6_to_router_6_6_rsp = router_5_6_rsp_out[1]; - assign router_5_6_to_router_5_5_rsp = router_5_6_rsp_out[2]; - assign router_5_6_to_router_4_6_rsp = router_5_6_rsp_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_rsp = router_5_6_rsp_out[4]; - - assign router_5_6_to_router_5_7_req = router_5_6_req_out[0]; - assign router_5_6_to_router_6_6_req = router_5_6_req_out[1]; - assign router_5_6_to_router_5_5_req = router_5_6_req_out[2]; - assign router_5_6_to_router_4_6_req = router_5_6_req_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_req = router_5_6_req_out[4]; - - assign router_5_6_rsp_in[0] = router_5_7_to_router_5_6_rsp; - assign router_5_6_rsp_in[1] = router_6_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[2] = router_5_5_to_router_5_6_rsp; - assign router_5_6_rsp_in[3] = router_4_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[4] = magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_6_req_in), - .floo_rsp_o (router_5_6_rsp_out), - .floo_req_o (router_5_6_req_out), - .floo_rsp_i (router_5_6_rsp_in) -); - - -floo_req_t [4:0] router_5_7_req_in; -floo_rsp_t [4:0] router_5_7_rsp_out; -floo_req_t [4:0] router_5_7_req_out; -floo_rsp_t [4:0] router_5_7_rsp_in; - - assign router_5_7_req_in[0] = router_5_8_to_router_5_7_req; - assign router_5_7_req_in[1] = router_6_7_to_router_5_7_req; - assign router_5_7_req_in[2] = router_5_6_to_router_5_7_req; - assign router_5_7_req_in[3] = router_4_7_to_router_5_7_req; - assign router_5_7_req_in[4] = magia_tile_ni_5_7_to_router_5_7_req; - - assign router_5_7_to_router_5_8_rsp = router_5_7_rsp_out[0]; - assign router_5_7_to_router_6_7_rsp = router_5_7_rsp_out[1]; - assign router_5_7_to_router_5_6_rsp = router_5_7_rsp_out[2]; - assign router_5_7_to_router_4_7_rsp = router_5_7_rsp_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_rsp = router_5_7_rsp_out[4]; - - assign router_5_7_to_router_5_8_req = router_5_7_req_out[0]; - assign router_5_7_to_router_6_7_req = router_5_7_req_out[1]; - assign router_5_7_to_router_5_6_req = router_5_7_req_out[2]; - assign router_5_7_to_router_4_7_req = router_5_7_req_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_req = router_5_7_req_out[4]; - - assign router_5_7_rsp_in[0] = router_5_8_to_router_5_7_rsp; - assign router_5_7_rsp_in[1] = router_6_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[2] = router_5_6_to_router_5_7_rsp; - assign router_5_7_rsp_in[3] = router_4_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[4] = magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_7_req_in), - .floo_rsp_o (router_5_7_rsp_out), - .floo_req_o (router_5_7_req_out), - .floo_rsp_i (router_5_7_rsp_in) -); - - -floo_req_t [4:0] router_5_8_req_in; -floo_rsp_t [4:0] router_5_8_rsp_out; -floo_req_t [4:0] router_5_8_req_out; -floo_rsp_t [4:0] router_5_8_rsp_in; - - assign router_5_8_req_in[0] = router_5_9_to_router_5_8_req; - assign router_5_8_req_in[1] = router_6_8_to_router_5_8_req; - assign router_5_8_req_in[2] = router_5_7_to_router_5_8_req; - assign router_5_8_req_in[3] = router_4_8_to_router_5_8_req; - assign router_5_8_req_in[4] = magia_tile_ni_5_8_to_router_5_8_req; - - assign router_5_8_to_router_5_9_rsp = router_5_8_rsp_out[0]; - assign router_5_8_to_router_6_8_rsp = router_5_8_rsp_out[1]; - assign router_5_8_to_router_5_7_rsp = router_5_8_rsp_out[2]; - assign router_5_8_to_router_4_8_rsp = router_5_8_rsp_out[3]; - assign router_5_8_to_magia_tile_ni_5_8_rsp = router_5_8_rsp_out[4]; - - assign router_5_8_to_router_5_9_req = router_5_8_req_out[0]; - assign router_5_8_to_router_6_8_req = router_5_8_req_out[1]; - assign router_5_8_to_router_5_7_req = router_5_8_req_out[2]; - assign router_5_8_to_router_4_8_req = router_5_8_req_out[3]; - assign router_5_8_to_magia_tile_ni_5_8_req = router_5_8_req_out[4]; - - assign router_5_8_rsp_in[0] = router_5_9_to_router_5_8_rsp; - assign router_5_8_rsp_in[1] = router_6_8_to_router_5_8_rsp; - assign router_5_8_rsp_in[2] = router_5_7_to_router_5_8_rsp; - assign router_5_8_rsp_in[3] = router_4_8_to_router_5_8_rsp; - assign router_5_8_rsp_in[4] = magia_tile_ni_5_8_to_router_5_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_8_req_in), - .floo_rsp_o (router_5_8_rsp_out), - .floo_req_o (router_5_8_req_out), - .floo_rsp_i (router_5_8_rsp_in) -); - - -floo_req_t [4:0] router_5_9_req_in; -floo_rsp_t [4:0] router_5_9_rsp_out; -floo_req_t [4:0] router_5_9_req_out; -floo_rsp_t [4:0] router_5_9_rsp_in; - - assign router_5_9_req_in[0] = router_5_10_to_router_5_9_req; - assign router_5_9_req_in[1] = router_6_9_to_router_5_9_req; - assign router_5_9_req_in[2] = router_5_8_to_router_5_9_req; - assign router_5_9_req_in[3] = router_4_9_to_router_5_9_req; - assign router_5_9_req_in[4] = magia_tile_ni_5_9_to_router_5_9_req; - - assign router_5_9_to_router_5_10_rsp = router_5_9_rsp_out[0]; - assign router_5_9_to_router_6_9_rsp = router_5_9_rsp_out[1]; - assign router_5_9_to_router_5_8_rsp = router_5_9_rsp_out[2]; - assign router_5_9_to_router_4_9_rsp = router_5_9_rsp_out[3]; - assign router_5_9_to_magia_tile_ni_5_9_rsp = router_5_9_rsp_out[4]; - - assign router_5_9_to_router_5_10_req = router_5_9_req_out[0]; - assign router_5_9_to_router_6_9_req = router_5_9_req_out[1]; - assign router_5_9_to_router_5_8_req = router_5_9_req_out[2]; - assign router_5_9_to_router_4_9_req = router_5_9_req_out[3]; - assign router_5_9_to_magia_tile_ni_5_9_req = router_5_9_req_out[4]; - - assign router_5_9_rsp_in[0] = router_5_10_to_router_5_9_rsp; - assign router_5_9_rsp_in[1] = router_6_9_to_router_5_9_rsp; - assign router_5_9_rsp_in[2] = router_5_8_to_router_5_9_rsp; - assign router_5_9_rsp_in[3] = router_4_9_to_router_5_9_rsp; - assign router_5_9_rsp_in[4] = magia_tile_ni_5_9_to_router_5_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_9_req_in), - .floo_rsp_o (router_5_9_rsp_out), - .floo_req_o (router_5_9_req_out), - .floo_rsp_i (router_5_9_rsp_in) -); - - -floo_req_t [4:0] router_5_10_req_in; -floo_rsp_t [4:0] router_5_10_rsp_out; -floo_req_t [4:0] router_5_10_req_out; -floo_rsp_t [4:0] router_5_10_rsp_in; - - assign router_5_10_req_in[0] = router_5_11_to_router_5_10_req; - assign router_5_10_req_in[1] = router_6_10_to_router_5_10_req; - assign router_5_10_req_in[2] = router_5_9_to_router_5_10_req; - assign router_5_10_req_in[3] = router_4_10_to_router_5_10_req; - assign router_5_10_req_in[4] = magia_tile_ni_5_10_to_router_5_10_req; - - assign router_5_10_to_router_5_11_rsp = router_5_10_rsp_out[0]; - assign router_5_10_to_router_6_10_rsp = router_5_10_rsp_out[1]; - assign router_5_10_to_router_5_9_rsp = router_5_10_rsp_out[2]; - assign router_5_10_to_router_4_10_rsp = router_5_10_rsp_out[3]; - assign router_5_10_to_magia_tile_ni_5_10_rsp = router_5_10_rsp_out[4]; - - assign router_5_10_to_router_5_11_req = router_5_10_req_out[0]; - assign router_5_10_to_router_6_10_req = router_5_10_req_out[1]; - assign router_5_10_to_router_5_9_req = router_5_10_req_out[2]; - assign router_5_10_to_router_4_10_req = router_5_10_req_out[3]; - assign router_5_10_to_magia_tile_ni_5_10_req = router_5_10_req_out[4]; - - assign router_5_10_rsp_in[0] = router_5_11_to_router_5_10_rsp; - assign router_5_10_rsp_in[1] = router_6_10_to_router_5_10_rsp; - assign router_5_10_rsp_in[2] = router_5_9_to_router_5_10_rsp; - assign router_5_10_rsp_in[3] = router_4_10_to_router_5_10_rsp; - assign router_5_10_rsp_in[4] = magia_tile_ni_5_10_to_router_5_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_10_req_in), - .floo_rsp_o (router_5_10_rsp_out), - .floo_req_o (router_5_10_req_out), - .floo_rsp_i (router_5_10_rsp_in) -); - - -floo_req_t [4:0] router_5_11_req_in; -floo_rsp_t [4:0] router_5_11_rsp_out; -floo_req_t [4:0] router_5_11_req_out; -floo_rsp_t [4:0] router_5_11_rsp_in; - - assign router_5_11_req_in[0] = router_5_12_to_router_5_11_req; - assign router_5_11_req_in[1] = router_6_11_to_router_5_11_req; - assign router_5_11_req_in[2] = router_5_10_to_router_5_11_req; - assign router_5_11_req_in[3] = router_4_11_to_router_5_11_req; - assign router_5_11_req_in[4] = magia_tile_ni_5_11_to_router_5_11_req; - - assign router_5_11_to_router_5_12_rsp = router_5_11_rsp_out[0]; - assign router_5_11_to_router_6_11_rsp = router_5_11_rsp_out[1]; - assign router_5_11_to_router_5_10_rsp = router_5_11_rsp_out[2]; - assign router_5_11_to_router_4_11_rsp = router_5_11_rsp_out[3]; - assign router_5_11_to_magia_tile_ni_5_11_rsp = router_5_11_rsp_out[4]; - - assign router_5_11_to_router_5_12_req = router_5_11_req_out[0]; - assign router_5_11_to_router_6_11_req = router_5_11_req_out[1]; - assign router_5_11_to_router_5_10_req = router_5_11_req_out[2]; - assign router_5_11_to_router_4_11_req = router_5_11_req_out[3]; - assign router_5_11_to_magia_tile_ni_5_11_req = router_5_11_req_out[4]; - - assign router_5_11_rsp_in[0] = router_5_12_to_router_5_11_rsp; - assign router_5_11_rsp_in[1] = router_6_11_to_router_5_11_rsp; - assign router_5_11_rsp_in[2] = router_5_10_to_router_5_11_rsp; - assign router_5_11_rsp_in[3] = router_4_11_to_router_5_11_rsp; - assign router_5_11_rsp_in[4] = magia_tile_ni_5_11_to_router_5_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_11_req_in), - .floo_rsp_o (router_5_11_rsp_out), - .floo_req_o (router_5_11_req_out), - .floo_rsp_i (router_5_11_rsp_in) -); - - -floo_req_t [4:0] router_5_12_req_in; -floo_rsp_t [4:0] router_5_12_rsp_out; -floo_req_t [4:0] router_5_12_req_out; -floo_rsp_t [4:0] router_5_12_rsp_in; - - assign router_5_12_req_in[0] = router_5_13_to_router_5_12_req; - assign router_5_12_req_in[1] = router_6_12_to_router_5_12_req; - assign router_5_12_req_in[2] = router_5_11_to_router_5_12_req; - assign router_5_12_req_in[3] = router_4_12_to_router_5_12_req; - assign router_5_12_req_in[4] = magia_tile_ni_5_12_to_router_5_12_req; - - assign router_5_12_to_router_5_13_rsp = router_5_12_rsp_out[0]; - assign router_5_12_to_router_6_12_rsp = router_5_12_rsp_out[1]; - assign router_5_12_to_router_5_11_rsp = router_5_12_rsp_out[2]; - assign router_5_12_to_router_4_12_rsp = router_5_12_rsp_out[3]; - assign router_5_12_to_magia_tile_ni_5_12_rsp = router_5_12_rsp_out[4]; - - assign router_5_12_to_router_5_13_req = router_5_12_req_out[0]; - assign router_5_12_to_router_6_12_req = router_5_12_req_out[1]; - assign router_5_12_to_router_5_11_req = router_5_12_req_out[2]; - assign router_5_12_to_router_4_12_req = router_5_12_req_out[3]; - assign router_5_12_to_magia_tile_ni_5_12_req = router_5_12_req_out[4]; - - assign router_5_12_rsp_in[0] = router_5_13_to_router_5_12_rsp; - assign router_5_12_rsp_in[1] = router_6_12_to_router_5_12_rsp; - assign router_5_12_rsp_in[2] = router_5_11_to_router_5_12_rsp; - assign router_5_12_rsp_in[3] = router_4_12_to_router_5_12_rsp; - assign router_5_12_rsp_in[4] = magia_tile_ni_5_12_to_router_5_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_12_req_in), - .floo_rsp_o (router_5_12_rsp_out), - .floo_req_o (router_5_12_req_out), - .floo_rsp_i (router_5_12_rsp_in) -); - - -floo_req_t [4:0] router_5_13_req_in; -floo_rsp_t [4:0] router_5_13_rsp_out; -floo_req_t [4:0] router_5_13_req_out; -floo_rsp_t [4:0] router_5_13_rsp_in; - - assign router_5_13_req_in[0] = router_5_14_to_router_5_13_req; - assign router_5_13_req_in[1] = router_6_13_to_router_5_13_req; - assign router_5_13_req_in[2] = router_5_12_to_router_5_13_req; - assign router_5_13_req_in[3] = router_4_13_to_router_5_13_req; - assign router_5_13_req_in[4] = magia_tile_ni_5_13_to_router_5_13_req; - - assign router_5_13_to_router_5_14_rsp = router_5_13_rsp_out[0]; - assign router_5_13_to_router_6_13_rsp = router_5_13_rsp_out[1]; - assign router_5_13_to_router_5_12_rsp = router_5_13_rsp_out[2]; - assign router_5_13_to_router_4_13_rsp = router_5_13_rsp_out[3]; - assign router_5_13_to_magia_tile_ni_5_13_rsp = router_5_13_rsp_out[4]; - - assign router_5_13_to_router_5_14_req = router_5_13_req_out[0]; - assign router_5_13_to_router_6_13_req = router_5_13_req_out[1]; - assign router_5_13_to_router_5_12_req = router_5_13_req_out[2]; - assign router_5_13_to_router_4_13_req = router_5_13_req_out[3]; - assign router_5_13_to_magia_tile_ni_5_13_req = router_5_13_req_out[4]; - - assign router_5_13_rsp_in[0] = router_5_14_to_router_5_13_rsp; - assign router_5_13_rsp_in[1] = router_6_13_to_router_5_13_rsp; - assign router_5_13_rsp_in[2] = router_5_12_to_router_5_13_rsp; - assign router_5_13_rsp_in[3] = router_4_13_to_router_5_13_rsp; - assign router_5_13_rsp_in[4] = magia_tile_ni_5_13_to_router_5_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_13_req_in), - .floo_rsp_o (router_5_13_rsp_out), - .floo_req_o (router_5_13_req_out), - .floo_rsp_i (router_5_13_rsp_in) -); - - -floo_req_t [4:0] router_5_14_req_in; -floo_rsp_t [4:0] router_5_14_rsp_out; -floo_req_t [4:0] router_5_14_req_out; -floo_rsp_t [4:0] router_5_14_rsp_in; - - assign router_5_14_req_in[0] = router_5_15_to_router_5_14_req; - assign router_5_14_req_in[1] = router_6_14_to_router_5_14_req; - assign router_5_14_req_in[2] = router_5_13_to_router_5_14_req; - assign router_5_14_req_in[3] = router_4_14_to_router_5_14_req; - assign router_5_14_req_in[4] = magia_tile_ni_5_14_to_router_5_14_req; - - assign router_5_14_to_router_5_15_rsp = router_5_14_rsp_out[0]; - assign router_5_14_to_router_6_14_rsp = router_5_14_rsp_out[1]; - assign router_5_14_to_router_5_13_rsp = router_5_14_rsp_out[2]; - assign router_5_14_to_router_4_14_rsp = router_5_14_rsp_out[3]; - assign router_5_14_to_magia_tile_ni_5_14_rsp = router_5_14_rsp_out[4]; - - assign router_5_14_to_router_5_15_req = router_5_14_req_out[0]; - assign router_5_14_to_router_6_14_req = router_5_14_req_out[1]; - assign router_5_14_to_router_5_13_req = router_5_14_req_out[2]; - assign router_5_14_to_router_4_14_req = router_5_14_req_out[3]; - assign router_5_14_to_magia_tile_ni_5_14_req = router_5_14_req_out[4]; - - assign router_5_14_rsp_in[0] = router_5_15_to_router_5_14_rsp; - assign router_5_14_rsp_in[1] = router_6_14_to_router_5_14_rsp; - assign router_5_14_rsp_in[2] = router_5_13_to_router_5_14_rsp; - assign router_5_14_rsp_in[3] = router_4_14_to_router_5_14_rsp; - assign router_5_14_rsp_in[4] = magia_tile_ni_5_14_to_router_5_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_14_req_in), - .floo_rsp_o (router_5_14_rsp_out), - .floo_req_o (router_5_14_req_out), - .floo_rsp_i (router_5_14_rsp_in) -); - - -floo_req_t [4:0] router_5_15_req_in; -floo_rsp_t [4:0] router_5_15_rsp_out; -floo_req_t [4:0] router_5_15_req_out; -floo_rsp_t [4:0] router_5_15_rsp_in; - - assign router_5_15_req_in[0] = '0; - assign router_5_15_req_in[1] = router_6_15_to_router_5_15_req; - assign router_5_15_req_in[2] = router_5_14_to_router_5_15_req; - assign router_5_15_req_in[3] = router_4_15_to_router_5_15_req; - assign router_5_15_req_in[4] = magia_tile_ni_5_15_to_router_5_15_req; - - assign router_5_15_to_router_6_15_rsp = router_5_15_rsp_out[1]; - assign router_5_15_to_router_5_14_rsp = router_5_15_rsp_out[2]; - assign router_5_15_to_router_4_15_rsp = router_5_15_rsp_out[3]; - assign router_5_15_to_magia_tile_ni_5_15_rsp = router_5_15_rsp_out[4]; - - assign router_5_15_to_router_6_15_req = router_5_15_req_out[1]; - assign router_5_15_to_router_5_14_req = router_5_15_req_out[2]; - assign router_5_15_to_router_4_15_req = router_5_15_req_out[3]; - assign router_5_15_to_magia_tile_ni_5_15_req = router_5_15_req_out[4]; - - assign router_5_15_rsp_in[0] = '0; - assign router_5_15_rsp_in[1] = router_6_15_to_router_5_15_rsp; - assign router_5_15_rsp_in[2] = router_5_14_to_router_5_15_rsp; - assign router_5_15_rsp_in[3] = router_4_15_to_router_5_15_rsp; - assign router_5_15_rsp_in[4] = magia_tile_ni_5_15_to_router_5_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_15_req_in), - .floo_rsp_o (router_5_15_rsp_out), - .floo_req_o (router_5_15_req_out), - .floo_rsp_i (router_5_15_rsp_in) -); - - -floo_req_t [4:0] router_6_0_req_in; -floo_rsp_t [4:0] router_6_0_rsp_out; -floo_req_t [4:0] router_6_0_req_out; -floo_rsp_t [4:0] router_6_0_rsp_in; - - assign router_6_0_req_in[0] = router_6_1_to_router_6_0_req; - assign router_6_0_req_in[1] = router_7_0_to_router_6_0_req; - assign router_6_0_req_in[2] = '0; - assign router_6_0_req_in[3] = router_5_0_to_router_6_0_req; - assign router_6_0_req_in[4] = magia_tile_ni_6_0_to_router_6_0_req; - - assign router_6_0_to_router_6_1_rsp = router_6_0_rsp_out[0]; - assign router_6_0_to_router_7_0_rsp = router_6_0_rsp_out[1]; - assign router_6_0_to_router_5_0_rsp = router_6_0_rsp_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_rsp = router_6_0_rsp_out[4]; - - assign router_6_0_to_router_6_1_req = router_6_0_req_out[0]; - assign router_6_0_to_router_7_0_req = router_6_0_req_out[1]; - assign router_6_0_to_router_5_0_req = router_6_0_req_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_req = router_6_0_req_out[4]; - - assign router_6_0_rsp_in[0] = router_6_1_to_router_6_0_rsp; - assign router_6_0_rsp_in[1] = router_7_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[2] = '0; - assign router_6_0_rsp_in[3] = router_5_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[4] = magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_0_req_in), - .floo_rsp_o (router_6_0_rsp_out), - .floo_req_o (router_6_0_req_out), - .floo_rsp_i (router_6_0_rsp_in) -); - - -floo_req_t [4:0] router_6_1_req_in; -floo_rsp_t [4:0] router_6_1_rsp_out; -floo_req_t [4:0] router_6_1_req_out; -floo_rsp_t [4:0] router_6_1_rsp_in; - - assign router_6_1_req_in[0] = router_6_2_to_router_6_1_req; - assign router_6_1_req_in[1] = router_7_1_to_router_6_1_req; - assign router_6_1_req_in[2] = router_6_0_to_router_6_1_req; - assign router_6_1_req_in[3] = router_5_1_to_router_6_1_req; - assign router_6_1_req_in[4] = magia_tile_ni_6_1_to_router_6_1_req; - - assign router_6_1_to_router_6_2_rsp = router_6_1_rsp_out[0]; - assign router_6_1_to_router_7_1_rsp = router_6_1_rsp_out[1]; - assign router_6_1_to_router_6_0_rsp = router_6_1_rsp_out[2]; - assign router_6_1_to_router_5_1_rsp = router_6_1_rsp_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_rsp = router_6_1_rsp_out[4]; - - assign router_6_1_to_router_6_2_req = router_6_1_req_out[0]; - assign router_6_1_to_router_7_1_req = router_6_1_req_out[1]; - assign router_6_1_to_router_6_0_req = router_6_1_req_out[2]; - assign router_6_1_to_router_5_1_req = router_6_1_req_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_req = router_6_1_req_out[4]; - - assign router_6_1_rsp_in[0] = router_6_2_to_router_6_1_rsp; - assign router_6_1_rsp_in[1] = router_7_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[2] = router_6_0_to_router_6_1_rsp; - assign router_6_1_rsp_in[3] = router_5_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[4] = magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_1_req_in), - .floo_rsp_o (router_6_1_rsp_out), - .floo_req_o (router_6_1_req_out), - .floo_rsp_i (router_6_1_rsp_in) -); - - -floo_req_t [4:0] router_6_2_req_in; -floo_rsp_t [4:0] router_6_2_rsp_out; -floo_req_t [4:0] router_6_2_req_out; -floo_rsp_t [4:0] router_6_2_rsp_in; - - assign router_6_2_req_in[0] = router_6_3_to_router_6_2_req; - assign router_6_2_req_in[1] = router_7_2_to_router_6_2_req; - assign router_6_2_req_in[2] = router_6_1_to_router_6_2_req; - assign router_6_2_req_in[3] = router_5_2_to_router_6_2_req; - assign router_6_2_req_in[4] = magia_tile_ni_6_2_to_router_6_2_req; - - assign router_6_2_to_router_6_3_rsp = router_6_2_rsp_out[0]; - assign router_6_2_to_router_7_2_rsp = router_6_2_rsp_out[1]; - assign router_6_2_to_router_6_1_rsp = router_6_2_rsp_out[2]; - assign router_6_2_to_router_5_2_rsp = router_6_2_rsp_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_rsp = router_6_2_rsp_out[4]; - - assign router_6_2_to_router_6_3_req = router_6_2_req_out[0]; - assign router_6_2_to_router_7_2_req = router_6_2_req_out[1]; - assign router_6_2_to_router_6_1_req = router_6_2_req_out[2]; - assign router_6_2_to_router_5_2_req = router_6_2_req_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_req = router_6_2_req_out[4]; - - assign router_6_2_rsp_in[0] = router_6_3_to_router_6_2_rsp; - assign router_6_2_rsp_in[1] = router_7_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[2] = router_6_1_to_router_6_2_rsp; - assign router_6_2_rsp_in[3] = router_5_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[4] = magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_2_req_in), - .floo_rsp_o (router_6_2_rsp_out), - .floo_req_o (router_6_2_req_out), - .floo_rsp_i (router_6_2_rsp_in) -); - - -floo_req_t [4:0] router_6_3_req_in; -floo_rsp_t [4:0] router_6_3_rsp_out; -floo_req_t [4:0] router_6_3_req_out; -floo_rsp_t [4:0] router_6_3_rsp_in; - - assign router_6_3_req_in[0] = router_6_4_to_router_6_3_req; - assign router_6_3_req_in[1] = router_7_3_to_router_6_3_req; - assign router_6_3_req_in[2] = router_6_2_to_router_6_3_req; - assign router_6_3_req_in[3] = router_5_3_to_router_6_3_req; - assign router_6_3_req_in[4] = magia_tile_ni_6_3_to_router_6_3_req; - - assign router_6_3_to_router_6_4_rsp = router_6_3_rsp_out[0]; - assign router_6_3_to_router_7_3_rsp = router_6_3_rsp_out[1]; - assign router_6_3_to_router_6_2_rsp = router_6_3_rsp_out[2]; - assign router_6_3_to_router_5_3_rsp = router_6_3_rsp_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_rsp = router_6_3_rsp_out[4]; - - assign router_6_3_to_router_6_4_req = router_6_3_req_out[0]; - assign router_6_3_to_router_7_3_req = router_6_3_req_out[1]; - assign router_6_3_to_router_6_2_req = router_6_3_req_out[2]; - assign router_6_3_to_router_5_3_req = router_6_3_req_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_req = router_6_3_req_out[4]; - - assign router_6_3_rsp_in[0] = router_6_4_to_router_6_3_rsp; - assign router_6_3_rsp_in[1] = router_7_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[2] = router_6_2_to_router_6_3_rsp; - assign router_6_3_rsp_in[3] = router_5_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[4] = magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_3_req_in), - .floo_rsp_o (router_6_3_rsp_out), - .floo_req_o (router_6_3_req_out), - .floo_rsp_i (router_6_3_rsp_in) -); - - -floo_req_t [4:0] router_6_4_req_in; -floo_rsp_t [4:0] router_6_4_rsp_out; -floo_req_t [4:0] router_6_4_req_out; -floo_rsp_t [4:0] router_6_4_rsp_in; - - assign router_6_4_req_in[0] = router_6_5_to_router_6_4_req; - assign router_6_4_req_in[1] = router_7_4_to_router_6_4_req; - assign router_6_4_req_in[2] = router_6_3_to_router_6_4_req; - assign router_6_4_req_in[3] = router_5_4_to_router_6_4_req; - assign router_6_4_req_in[4] = magia_tile_ni_6_4_to_router_6_4_req; - - assign router_6_4_to_router_6_5_rsp = router_6_4_rsp_out[0]; - assign router_6_4_to_router_7_4_rsp = router_6_4_rsp_out[1]; - assign router_6_4_to_router_6_3_rsp = router_6_4_rsp_out[2]; - assign router_6_4_to_router_5_4_rsp = router_6_4_rsp_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_rsp = router_6_4_rsp_out[4]; - - assign router_6_4_to_router_6_5_req = router_6_4_req_out[0]; - assign router_6_4_to_router_7_4_req = router_6_4_req_out[1]; - assign router_6_4_to_router_6_3_req = router_6_4_req_out[2]; - assign router_6_4_to_router_5_4_req = router_6_4_req_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_req = router_6_4_req_out[4]; - - assign router_6_4_rsp_in[0] = router_6_5_to_router_6_4_rsp; - assign router_6_4_rsp_in[1] = router_7_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[2] = router_6_3_to_router_6_4_rsp; - assign router_6_4_rsp_in[3] = router_5_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[4] = magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_4_req_in), - .floo_rsp_o (router_6_4_rsp_out), - .floo_req_o (router_6_4_req_out), - .floo_rsp_i (router_6_4_rsp_in) -); - - -floo_req_t [4:0] router_6_5_req_in; -floo_rsp_t [4:0] router_6_5_rsp_out; -floo_req_t [4:0] router_6_5_req_out; -floo_rsp_t [4:0] router_6_5_rsp_in; - - assign router_6_5_req_in[0] = router_6_6_to_router_6_5_req; - assign router_6_5_req_in[1] = router_7_5_to_router_6_5_req; - assign router_6_5_req_in[2] = router_6_4_to_router_6_5_req; - assign router_6_5_req_in[3] = router_5_5_to_router_6_5_req; - assign router_6_5_req_in[4] = magia_tile_ni_6_5_to_router_6_5_req; - - assign router_6_5_to_router_6_6_rsp = router_6_5_rsp_out[0]; - assign router_6_5_to_router_7_5_rsp = router_6_5_rsp_out[1]; - assign router_6_5_to_router_6_4_rsp = router_6_5_rsp_out[2]; - assign router_6_5_to_router_5_5_rsp = router_6_5_rsp_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_rsp = router_6_5_rsp_out[4]; - - assign router_6_5_to_router_6_6_req = router_6_5_req_out[0]; - assign router_6_5_to_router_7_5_req = router_6_5_req_out[1]; - assign router_6_5_to_router_6_4_req = router_6_5_req_out[2]; - assign router_6_5_to_router_5_5_req = router_6_5_req_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_req = router_6_5_req_out[4]; - - assign router_6_5_rsp_in[0] = router_6_6_to_router_6_5_rsp; - assign router_6_5_rsp_in[1] = router_7_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[2] = router_6_4_to_router_6_5_rsp; - assign router_6_5_rsp_in[3] = router_5_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[4] = magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_5_req_in), - .floo_rsp_o (router_6_5_rsp_out), - .floo_req_o (router_6_5_req_out), - .floo_rsp_i (router_6_5_rsp_in) -); - - -floo_req_t [4:0] router_6_6_req_in; -floo_rsp_t [4:0] router_6_6_rsp_out; -floo_req_t [4:0] router_6_6_req_out; -floo_rsp_t [4:0] router_6_6_rsp_in; - - assign router_6_6_req_in[0] = router_6_7_to_router_6_6_req; - assign router_6_6_req_in[1] = router_7_6_to_router_6_6_req; - assign router_6_6_req_in[2] = router_6_5_to_router_6_6_req; - assign router_6_6_req_in[3] = router_5_6_to_router_6_6_req; - assign router_6_6_req_in[4] = magia_tile_ni_6_6_to_router_6_6_req; - - assign router_6_6_to_router_6_7_rsp = router_6_6_rsp_out[0]; - assign router_6_6_to_router_7_6_rsp = router_6_6_rsp_out[1]; - assign router_6_6_to_router_6_5_rsp = router_6_6_rsp_out[2]; - assign router_6_6_to_router_5_6_rsp = router_6_6_rsp_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_rsp = router_6_6_rsp_out[4]; - - assign router_6_6_to_router_6_7_req = router_6_6_req_out[0]; - assign router_6_6_to_router_7_6_req = router_6_6_req_out[1]; - assign router_6_6_to_router_6_5_req = router_6_6_req_out[2]; - assign router_6_6_to_router_5_6_req = router_6_6_req_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_req = router_6_6_req_out[4]; - - assign router_6_6_rsp_in[0] = router_6_7_to_router_6_6_rsp; - assign router_6_6_rsp_in[1] = router_7_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[2] = router_6_5_to_router_6_6_rsp; - assign router_6_6_rsp_in[3] = router_5_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[4] = magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_6_req_in), - .floo_rsp_o (router_6_6_rsp_out), - .floo_req_o (router_6_6_req_out), - .floo_rsp_i (router_6_6_rsp_in) -); - - -floo_req_t [4:0] router_6_7_req_in; -floo_rsp_t [4:0] router_6_7_rsp_out; -floo_req_t [4:0] router_6_7_req_out; -floo_rsp_t [4:0] router_6_7_rsp_in; - - assign router_6_7_req_in[0] = router_6_8_to_router_6_7_req; - assign router_6_7_req_in[1] = router_7_7_to_router_6_7_req; - assign router_6_7_req_in[2] = router_6_6_to_router_6_7_req; - assign router_6_7_req_in[3] = router_5_7_to_router_6_7_req; - assign router_6_7_req_in[4] = magia_tile_ni_6_7_to_router_6_7_req; - - assign router_6_7_to_router_6_8_rsp = router_6_7_rsp_out[0]; - assign router_6_7_to_router_7_7_rsp = router_6_7_rsp_out[1]; - assign router_6_7_to_router_6_6_rsp = router_6_7_rsp_out[2]; - assign router_6_7_to_router_5_7_rsp = router_6_7_rsp_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_rsp = router_6_7_rsp_out[4]; - - assign router_6_7_to_router_6_8_req = router_6_7_req_out[0]; - assign router_6_7_to_router_7_7_req = router_6_7_req_out[1]; - assign router_6_7_to_router_6_6_req = router_6_7_req_out[2]; - assign router_6_7_to_router_5_7_req = router_6_7_req_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_req = router_6_7_req_out[4]; - - assign router_6_7_rsp_in[0] = router_6_8_to_router_6_7_rsp; - assign router_6_7_rsp_in[1] = router_7_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[2] = router_6_6_to_router_6_7_rsp; - assign router_6_7_rsp_in[3] = router_5_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[4] = magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_7_req_in), - .floo_rsp_o (router_6_7_rsp_out), - .floo_req_o (router_6_7_req_out), - .floo_rsp_i (router_6_7_rsp_in) -); - - -floo_req_t [4:0] router_6_8_req_in; -floo_rsp_t [4:0] router_6_8_rsp_out; -floo_req_t [4:0] router_6_8_req_out; -floo_rsp_t [4:0] router_6_8_rsp_in; - - assign router_6_8_req_in[0] = router_6_9_to_router_6_8_req; - assign router_6_8_req_in[1] = router_7_8_to_router_6_8_req; - assign router_6_8_req_in[2] = router_6_7_to_router_6_8_req; - assign router_6_8_req_in[3] = router_5_8_to_router_6_8_req; - assign router_6_8_req_in[4] = magia_tile_ni_6_8_to_router_6_8_req; - - assign router_6_8_to_router_6_9_rsp = router_6_8_rsp_out[0]; - assign router_6_8_to_router_7_8_rsp = router_6_8_rsp_out[1]; - assign router_6_8_to_router_6_7_rsp = router_6_8_rsp_out[2]; - assign router_6_8_to_router_5_8_rsp = router_6_8_rsp_out[3]; - assign router_6_8_to_magia_tile_ni_6_8_rsp = router_6_8_rsp_out[4]; - - assign router_6_8_to_router_6_9_req = router_6_8_req_out[0]; - assign router_6_8_to_router_7_8_req = router_6_8_req_out[1]; - assign router_6_8_to_router_6_7_req = router_6_8_req_out[2]; - assign router_6_8_to_router_5_8_req = router_6_8_req_out[3]; - assign router_6_8_to_magia_tile_ni_6_8_req = router_6_8_req_out[4]; - - assign router_6_8_rsp_in[0] = router_6_9_to_router_6_8_rsp; - assign router_6_8_rsp_in[1] = router_7_8_to_router_6_8_rsp; - assign router_6_8_rsp_in[2] = router_6_7_to_router_6_8_rsp; - assign router_6_8_rsp_in[3] = router_5_8_to_router_6_8_rsp; - assign router_6_8_rsp_in[4] = magia_tile_ni_6_8_to_router_6_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_8_req_in), - .floo_rsp_o (router_6_8_rsp_out), - .floo_req_o (router_6_8_req_out), - .floo_rsp_i (router_6_8_rsp_in) -); - - -floo_req_t [4:0] router_6_9_req_in; -floo_rsp_t [4:0] router_6_9_rsp_out; -floo_req_t [4:0] router_6_9_req_out; -floo_rsp_t [4:0] router_6_9_rsp_in; - - assign router_6_9_req_in[0] = router_6_10_to_router_6_9_req; - assign router_6_9_req_in[1] = router_7_9_to_router_6_9_req; - assign router_6_9_req_in[2] = router_6_8_to_router_6_9_req; - assign router_6_9_req_in[3] = router_5_9_to_router_6_9_req; - assign router_6_9_req_in[4] = magia_tile_ni_6_9_to_router_6_9_req; - - assign router_6_9_to_router_6_10_rsp = router_6_9_rsp_out[0]; - assign router_6_9_to_router_7_9_rsp = router_6_9_rsp_out[1]; - assign router_6_9_to_router_6_8_rsp = router_6_9_rsp_out[2]; - assign router_6_9_to_router_5_9_rsp = router_6_9_rsp_out[3]; - assign router_6_9_to_magia_tile_ni_6_9_rsp = router_6_9_rsp_out[4]; - - assign router_6_9_to_router_6_10_req = router_6_9_req_out[0]; - assign router_6_9_to_router_7_9_req = router_6_9_req_out[1]; - assign router_6_9_to_router_6_8_req = router_6_9_req_out[2]; - assign router_6_9_to_router_5_9_req = router_6_9_req_out[3]; - assign router_6_9_to_magia_tile_ni_6_9_req = router_6_9_req_out[4]; - - assign router_6_9_rsp_in[0] = router_6_10_to_router_6_9_rsp; - assign router_6_9_rsp_in[1] = router_7_9_to_router_6_9_rsp; - assign router_6_9_rsp_in[2] = router_6_8_to_router_6_9_rsp; - assign router_6_9_rsp_in[3] = router_5_9_to_router_6_9_rsp; - assign router_6_9_rsp_in[4] = magia_tile_ni_6_9_to_router_6_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_9_req_in), - .floo_rsp_o (router_6_9_rsp_out), - .floo_req_o (router_6_9_req_out), - .floo_rsp_i (router_6_9_rsp_in) -); - - -floo_req_t [4:0] router_6_10_req_in; -floo_rsp_t [4:0] router_6_10_rsp_out; -floo_req_t [4:0] router_6_10_req_out; -floo_rsp_t [4:0] router_6_10_rsp_in; - - assign router_6_10_req_in[0] = router_6_11_to_router_6_10_req; - assign router_6_10_req_in[1] = router_7_10_to_router_6_10_req; - assign router_6_10_req_in[2] = router_6_9_to_router_6_10_req; - assign router_6_10_req_in[3] = router_5_10_to_router_6_10_req; - assign router_6_10_req_in[4] = magia_tile_ni_6_10_to_router_6_10_req; - - assign router_6_10_to_router_6_11_rsp = router_6_10_rsp_out[0]; - assign router_6_10_to_router_7_10_rsp = router_6_10_rsp_out[1]; - assign router_6_10_to_router_6_9_rsp = router_6_10_rsp_out[2]; - assign router_6_10_to_router_5_10_rsp = router_6_10_rsp_out[3]; - assign router_6_10_to_magia_tile_ni_6_10_rsp = router_6_10_rsp_out[4]; - - assign router_6_10_to_router_6_11_req = router_6_10_req_out[0]; - assign router_6_10_to_router_7_10_req = router_6_10_req_out[1]; - assign router_6_10_to_router_6_9_req = router_6_10_req_out[2]; - assign router_6_10_to_router_5_10_req = router_6_10_req_out[3]; - assign router_6_10_to_magia_tile_ni_6_10_req = router_6_10_req_out[4]; - - assign router_6_10_rsp_in[0] = router_6_11_to_router_6_10_rsp; - assign router_6_10_rsp_in[1] = router_7_10_to_router_6_10_rsp; - assign router_6_10_rsp_in[2] = router_6_9_to_router_6_10_rsp; - assign router_6_10_rsp_in[3] = router_5_10_to_router_6_10_rsp; - assign router_6_10_rsp_in[4] = magia_tile_ni_6_10_to_router_6_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_10_req_in), - .floo_rsp_o (router_6_10_rsp_out), - .floo_req_o (router_6_10_req_out), - .floo_rsp_i (router_6_10_rsp_in) -); - - -floo_req_t [4:0] router_6_11_req_in; -floo_rsp_t [4:0] router_6_11_rsp_out; -floo_req_t [4:0] router_6_11_req_out; -floo_rsp_t [4:0] router_6_11_rsp_in; - - assign router_6_11_req_in[0] = router_6_12_to_router_6_11_req; - assign router_6_11_req_in[1] = router_7_11_to_router_6_11_req; - assign router_6_11_req_in[2] = router_6_10_to_router_6_11_req; - assign router_6_11_req_in[3] = router_5_11_to_router_6_11_req; - assign router_6_11_req_in[4] = magia_tile_ni_6_11_to_router_6_11_req; - - assign router_6_11_to_router_6_12_rsp = router_6_11_rsp_out[0]; - assign router_6_11_to_router_7_11_rsp = router_6_11_rsp_out[1]; - assign router_6_11_to_router_6_10_rsp = router_6_11_rsp_out[2]; - assign router_6_11_to_router_5_11_rsp = router_6_11_rsp_out[3]; - assign router_6_11_to_magia_tile_ni_6_11_rsp = router_6_11_rsp_out[4]; - - assign router_6_11_to_router_6_12_req = router_6_11_req_out[0]; - assign router_6_11_to_router_7_11_req = router_6_11_req_out[1]; - assign router_6_11_to_router_6_10_req = router_6_11_req_out[2]; - assign router_6_11_to_router_5_11_req = router_6_11_req_out[3]; - assign router_6_11_to_magia_tile_ni_6_11_req = router_6_11_req_out[4]; - - assign router_6_11_rsp_in[0] = router_6_12_to_router_6_11_rsp; - assign router_6_11_rsp_in[1] = router_7_11_to_router_6_11_rsp; - assign router_6_11_rsp_in[2] = router_6_10_to_router_6_11_rsp; - assign router_6_11_rsp_in[3] = router_5_11_to_router_6_11_rsp; - assign router_6_11_rsp_in[4] = magia_tile_ni_6_11_to_router_6_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_11_req_in), - .floo_rsp_o (router_6_11_rsp_out), - .floo_req_o (router_6_11_req_out), - .floo_rsp_i (router_6_11_rsp_in) -); - - -floo_req_t [4:0] router_6_12_req_in; -floo_rsp_t [4:0] router_6_12_rsp_out; -floo_req_t [4:0] router_6_12_req_out; -floo_rsp_t [4:0] router_6_12_rsp_in; - - assign router_6_12_req_in[0] = router_6_13_to_router_6_12_req; - assign router_6_12_req_in[1] = router_7_12_to_router_6_12_req; - assign router_6_12_req_in[2] = router_6_11_to_router_6_12_req; - assign router_6_12_req_in[3] = router_5_12_to_router_6_12_req; - assign router_6_12_req_in[4] = magia_tile_ni_6_12_to_router_6_12_req; - - assign router_6_12_to_router_6_13_rsp = router_6_12_rsp_out[0]; - assign router_6_12_to_router_7_12_rsp = router_6_12_rsp_out[1]; - assign router_6_12_to_router_6_11_rsp = router_6_12_rsp_out[2]; - assign router_6_12_to_router_5_12_rsp = router_6_12_rsp_out[3]; - assign router_6_12_to_magia_tile_ni_6_12_rsp = router_6_12_rsp_out[4]; - - assign router_6_12_to_router_6_13_req = router_6_12_req_out[0]; - assign router_6_12_to_router_7_12_req = router_6_12_req_out[1]; - assign router_6_12_to_router_6_11_req = router_6_12_req_out[2]; - assign router_6_12_to_router_5_12_req = router_6_12_req_out[3]; - assign router_6_12_to_magia_tile_ni_6_12_req = router_6_12_req_out[4]; - - assign router_6_12_rsp_in[0] = router_6_13_to_router_6_12_rsp; - assign router_6_12_rsp_in[1] = router_7_12_to_router_6_12_rsp; - assign router_6_12_rsp_in[2] = router_6_11_to_router_6_12_rsp; - assign router_6_12_rsp_in[3] = router_5_12_to_router_6_12_rsp; - assign router_6_12_rsp_in[4] = magia_tile_ni_6_12_to_router_6_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_12_req_in), - .floo_rsp_o (router_6_12_rsp_out), - .floo_req_o (router_6_12_req_out), - .floo_rsp_i (router_6_12_rsp_in) -); - - -floo_req_t [4:0] router_6_13_req_in; -floo_rsp_t [4:0] router_6_13_rsp_out; -floo_req_t [4:0] router_6_13_req_out; -floo_rsp_t [4:0] router_6_13_rsp_in; - - assign router_6_13_req_in[0] = router_6_14_to_router_6_13_req; - assign router_6_13_req_in[1] = router_7_13_to_router_6_13_req; - assign router_6_13_req_in[2] = router_6_12_to_router_6_13_req; - assign router_6_13_req_in[3] = router_5_13_to_router_6_13_req; - assign router_6_13_req_in[4] = magia_tile_ni_6_13_to_router_6_13_req; - - assign router_6_13_to_router_6_14_rsp = router_6_13_rsp_out[0]; - assign router_6_13_to_router_7_13_rsp = router_6_13_rsp_out[1]; - assign router_6_13_to_router_6_12_rsp = router_6_13_rsp_out[2]; - assign router_6_13_to_router_5_13_rsp = router_6_13_rsp_out[3]; - assign router_6_13_to_magia_tile_ni_6_13_rsp = router_6_13_rsp_out[4]; - - assign router_6_13_to_router_6_14_req = router_6_13_req_out[0]; - assign router_6_13_to_router_7_13_req = router_6_13_req_out[1]; - assign router_6_13_to_router_6_12_req = router_6_13_req_out[2]; - assign router_6_13_to_router_5_13_req = router_6_13_req_out[3]; - assign router_6_13_to_magia_tile_ni_6_13_req = router_6_13_req_out[4]; - - assign router_6_13_rsp_in[0] = router_6_14_to_router_6_13_rsp; - assign router_6_13_rsp_in[1] = router_7_13_to_router_6_13_rsp; - assign router_6_13_rsp_in[2] = router_6_12_to_router_6_13_rsp; - assign router_6_13_rsp_in[3] = router_5_13_to_router_6_13_rsp; - assign router_6_13_rsp_in[4] = magia_tile_ni_6_13_to_router_6_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_13_req_in), - .floo_rsp_o (router_6_13_rsp_out), - .floo_req_o (router_6_13_req_out), - .floo_rsp_i (router_6_13_rsp_in) -); - - -floo_req_t [4:0] router_6_14_req_in; -floo_rsp_t [4:0] router_6_14_rsp_out; -floo_req_t [4:0] router_6_14_req_out; -floo_rsp_t [4:0] router_6_14_rsp_in; - - assign router_6_14_req_in[0] = router_6_15_to_router_6_14_req; - assign router_6_14_req_in[1] = router_7_14_to_router_6_14_req; - assign router_6_14_req_in[2] = router_6_13_to_router_6_14_req; - assign router_6_14_req_in[3] = router_5_14_to_router_6_14_req; - assign router_6_14_req_in[4] = magia_tile_ni_6_14_to_router_6_14_req; - - assign router_6_14_to_router_6_15_rsp = router_6_14_rsp_out[0]; - assign router_6_14_to_router_7_14_rsp = router_6_14_rsp_out[1]; - assign router_6_14_to_router_6_13_rsp = router_6_14_rsp_out[2]; - assign router_6_14_to_router_5_14_rsp = router_6_14_rsp_out[3]; - assign router_6_14_to_magia_tile_ni_6_14_rsp = router_6_14_rsp_out[4]; - - assign router_6_14_to_router_6_15_req = router_6_14_req_out[0]; - assign router_6_14_to_router_7_14_req = router_6_14_req_out[1]; - assign router_6_14_to_router_6_13_req = router_6_14_req_out[2]; - assign router_6_14_to_router_5_14_req = router_6_14_req_out[3]; - assign router_6_14_to_magia_tile_ni_6_14_req = router_6_14_req_out[4]; - - assign router_6_14_rsp_in[0] = router_6_15_to_router_6_14_rsp; - assign router_6_14_rsp_in[1] = router_7_14_to_router_6_14_rsp; - assign router_6_14_rsp_in[2] = router_6_13_to_router_6_14_rsp; - assign router_6_14_rsp_in[3] = router_5_14_to_router_6_14_rsp; - assign router_6_14_rsp_in[4] = magia_tile_ni_6_14_to_router_6_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_14_req_in), - .floo_rsp_o (router_6_14_rsp_out), - .floo_req_o (router_6_14_req_out), - .floo_rsp_i (router_6_14_rsp_in) -); - - -floo_req_t [4:0] router_6_15_req_in; -floo_rsp_t [4:0] router_6_15_rsp_out; -floo_req_t [4:0] router_6_15_req_out; -floo_rsp_t [4:0] router_6_15_rsp_in; - - assign router_6_15_req_in[0] = '0; - assign router_6_15_req_in[1] = router_7_15_to_router_6_15_req; - assign router_6_15_req_in[2] = router_6_14_to_router_6_15_req; - assign router_6_15_req_in[3] = router_5_15_to_router_6_15_req; - assign router_6_15_req_in[4] = magia_tile_ni_6_15_to_router_6_15_req; - - assign router_6_15_to_router_7_15_rsp = router_6_15_rsp_out[1]; - assign router_6_15_to_router_6_14_rsp = router_6_15_rsp_out[2]; - assign router_6_15_to_router_5_15_rsp = router_6_15_rsp_out[3]; - assign router_6_15_to_magia_tile_ni_6_15_rsp = router_6_15_rsp_out[4]; - - assign router_6_15_to_router_7_15_req = router_6_15_req_out[1]; - assign router_6_15_to_router_6_14_req = router_6_15_req_out[2]; - assign router_6_15_to_router_5_15_req = router_6_15_req_out[3]; - assign router_6_15_to_magia_tile_ni_6_15_req = router_6_15_req_out[4]; - - assign router_6_15_rsp_in[0] = '0; - assign router_6_15_rsp_in[1] = router_7_15_to_router_6_15_rsp; - assign router_6_15_rsp_in[2] = router_6_14_to_router_6_15_rsp; - assign router_6_15_rsp_in[3] = router_5_15_to_router_6_15_rsp; - assign router_6_15_rsp_in[4] = magia_tile_ni_6_15_to_router_6_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_15_req_in), - .floo_rsp_o (router_6_15_rsp_out), - .floo_req_o (router_6_15_req_out), - .floo_rsp_i (router_6_15_rsp_in) -); - - -floo_req_t [4:0] router_7_0_req_in; -floo_rsp_t [4:0] router_7_0_rsp_out; -floo_req_t [4:0] router_7_0_req_out; -floo_rsp_t [4:0] router_7_0_rsp_in; - - assign router_7_0_req_in[0] = router_7_1_to_router_7_0_req; - assign router_7_0_req_in[1] = router_8_0_to_router_7_0_req; - assign router_7_0_req_in[2] = '0; - assign router_7_0_req_in[3] = router_6_0_to_router_7_0_req; - assign router_7_0_req_in[4] = magia_tile_ni_7_0_to_router_7_0_req; - - assign router_7_0_to_router_7_1_rsp = router_7_0_rsp_out[0]; - assign router_7_0_to_router_8_0_rsp = router_7_0_rsp_out[1]; - assign router_7_0_to_router_6_0_rsp = router_7_0_rsp_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_rsp = router_7_0_rsp_out[4]; - - assign router_7_0_to_router_7_1_req = router_7_0_req_out[0]; - assign router_7_0_to_router_8_0_req = router_7_0_req_out[1]; - assign router_7_0_to_router_6_0_req = router_7_0_req_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_req = router_7_0_req_out[4]; - - assign router_7_0_rsp_in[0] = router_7_1_to_router_7_0_rsp; - assign router_7_0_rsp_in[1] = router_8_0_to_router_7_0_rsp; - assign router_7_0_rsp_in[2] = '0; - assign router_7_0_rsp_in[3] = router_6_0_to_router_7_0_rsp; - assign router_7_0_rsp_in[4] = magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_0_req_in), - .floo_rsp_o (router_7_0_rsp_out), - .floo_req_o (router_7_0_req_out), - .floo_rsp_i (router_7_0_rsp_in) -); - - -floo_req_t [4:0] router_7_1_req_in; -floo_rsp_t [4:0] router_7_1_rsp_out; -floo_req_t [4:0] router_7_1_req_out; -floo_rsp_t [4:0] router_7_1_rsp_in; - - assign router_7_1_req_in[0] = router_7_2_to_router_7_1_req; - assign router_7_1_req_in[1] = router_8_1_to_router_7_1_req; - assign router_7_1_req_in[2] = router_7_0_to_router_7_1_req; - assign router_7_1_req_in[3] = router_6_1_to_router_7_1_req; - assign router_7_1_req_in[4] = magia_tile_ni_7_1_to_router_7_1_req; - - assign router_7_1_to_router_7_2_rsp = router_7_1_rsp_out[0]; - assign router_7_1_to_router_8_1_rsp = router_7_1_rsp_out[1]; - assign router_7_1_to_router_7_0_rsp = router_7_1_rsp_out[2]; - assign router_7_1_to_router_6_1_rsp = router_7_1_rsp_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_rsp = router_7_1_rsp_out[4]; - - assign router_7_1_to_router_7_2_req = router_7_1_req_out[0]; - assign router_7_1_to_router_8_1_req = router_7_1_req_out[1]; - assign router_7_1_to_router_7_0_req = router_7_1_req_out[2]; - assign router_7_1_to_router_6_1_req = router_7_1_req_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_req = router_7_1_req_out[4]; - - assign router_7_1_rsp_in[0] = router_7_2_to_router_7_1_rsp; - assign router_7_1_rsp_in[1] = router_8_1_to_router_7_1_rsp; - assign router_7_1_rsp_in[2] = router_7_0_to_router_7_1_rsp; - assign router_7_1_rsp_in[3] = router_6_1_to_router_7_1_rsp; - assign router_7_1_rsp_in[4] = magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_1_req_in), - .floo_rsp_o (router_7_1_rsp_out), - .floo_req_o (router_7_1_req_out), - .floo_rsp_i (router_7_1_rsp_in) -); - - -floo_req_t [4:0] router_7_2_req_in; -floo_rsp_t [4:0] router_7_2_rsp_out; -floo_req_t [4:0] router_7_2_req_out; -floo_rsp_t [4:0] router_7_2_rsp_in; - - assign router_7_2_req_in[0] = router_7_3_to_router_7_2_req; - assign router_7_2_req_in[1] = router_8_2_to_router_7_2_req; - assign router_7_2_req_in[2] = router_7_1_to_router_7_2_req; - assign router_7_2_req_in[3] = router_6_2_to_router_7_2_req; - assign router_7_2_req_in[4] = magia_tile_ni_7_2_to_router_7_2_req; - - assign router_7_2_to_router_7_3_rsp = router_7_2_rsp_out[0]; - assign router_7_2_to_router_8_2_rsp = router_7_2_rsp_out[1]; - assign router_7_2_to_router_7_1_rsp = router_7_2_rsp_out[2]; - assign router_7_2_to_router_6_2_rsp = router_7_2_rsp_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_rsp = router_7_2_rsp_out[4]; - - assign router_7_2_to_router_7_3_req = router_7_2_req_out[0]; - assign router_7_2_to_router_8_2_req = router_7_2_req_out[1]; - assign router_7_2_to_router_7_1_req = router_7_2_req_out[2]; - assign router_7_2_to_router_6_2_req = router_7_2_req_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_req = router_7_2_req_out[4]; - - assign router_7_2_rsp_in[0] = router_7_3_to_router_7_2_rsp; - assign router_7_2_rsp_in[1] = router_8_2_to_router_7_2_rsp; - assign router_7_2_rsp_in[2] = router_7_1_to_router_7_2_rsp; - assign router_7_2_rsp_in[3] = router_6_2_to_router_7_2_rsp; - assign router_7_2_rsp_in[4] = magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_2_req_in), - .floo_rsp_o (router_7_2_rsp_out), - .floo_req_o (router_7_2_req_out), - .floo_rsp_i (router_7_2_rsp_in) -); - - -floo_req_t [4:0] router_7_3_req_in; -floo_rsp_t [4:0] router_7_3_rsp_out; -floo_req_t [4:0] router_7_3_req_out; -floo_rsp_t [4:0] router_7_3_rsp_in; - - assign router_7_3_req_in[0] = router_7_4_to_router_7_3_req; - assign router_7_3_req_in[1] = router_8_3_to_router_7_3_req; - assign router_7_3_req_in[2] = router_7_2_to_router_7_3_req; - assign router_7_3_req_in[3] = router_6_3_to_router_7_3_req; - assign router_7_3_req_in[4] = magia_tile_ni_7_3_to_router_7_3_req; - - assign router_7_3_to_router_7_4_rsp = router_7_3_rsp_out[0]; - assign router_7_3_to_router_8_3_rsp = router_7_3_rsp_out[1]; - assign router_7_3_to_router_7_2_rsp = router_7_3_rsp_out[2]; - assign router_7_3_to_router_6_3_rsp = router_7_3_rsp_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_rsp = router_7_3_rsp_out[4]; - - assign router_7_3_to_router_7_4_req = router_7_3_req_out[0]; - assign router_7_3_to_router_8_3_req = router_7_3_req_out[1]; - assign router_7_3_to_router_7_2_req = router_7_3_req_out[2]; - assign router_7_3_to_router_6_3_req = router_7_3_req_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_req = router_7_3_req_out[4]; - - assign router_7_3_rsp_in[0] = router_7_4_to_router_7_3_rsp; - assign router_7_3_rsp_in[1] = router_8_3_to_router_7_3_rsp; - assign router_7_3_rsp_in[2] = router_7_2_to_router_7_3_rsp; - assign router_7_3_rsp_in[3] = router_6_3_to_router_7_3_rsp; - assign router_7_3_rsp_in[4] = magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_3_req_in), - .floo_rsp_o (router_7_3_rsp_out), - .floo_req_o (router_7_3_req_out), - .floo_rsp_i (router_7_3_rsp_in) -); - - -floo_req_t [4:0] router_7_4_req_in; -floo_rsp_t [4:0] router_7_4_rsp_out; -floo_req_t [4:0] router_7_4_req_out; -floo_rsp_t [4:0] router_7_4_rsp_in; - - assign router_7_4_req_in[0] = router_7_5_to_router_7_4_req; - assign router_7_4_req_in[1] = router_8_4_to_router_7_4_req; - assign router_7_4_req_in[2] = router_7_3_to_router_7_4_req; - assign router_7_4_req_in[3] = router_6_4_to_router_7_4_req; - assign router_7_4_req_in[4] = magia_tile_ni_7_4_to_router_7_4_req; - - assign router_7_4_to_router_7_5_rsp = router_7_4_rsp_out[0]; - assign router_7_4_to_router_8_4_rsp = router_7_4_rsp_out[1]; - assign router_7_4_to_router_7_3_rsp = router_7_4_rsp_out[2]; - assign router_7_4_to_router_6_4_rsp = router_7_4_rsp_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_rsp = router_7_4_rsp_out[4]; - - assign router_7_4_to_router_7_5_req = router_7_4_req_out[0]; - assign router_7_4_to_router_8_4_req = router_7_4_req_out[1]; - assign router_7_4_to_router_7_3_req = router_7_4_req_out[2]; - assign router_7_4_to_router_6_4_req = router_7_4_req_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_req = router_7_4_req_out[4]; - - assign router_7_4_rsp_in[0] = router_7_5_to_router_7_4_rsp; - assign router_7_4_rsp_in[1] = router_8_4_to_router_7_4_rsp; - assign router_7_4_rsp_in[2] = router_7_3_to_router_7_4_rsp; - assign router_7_4_rsp_in[3] = router_6_4_to_router_7_4_rsp; - assign router_7_4_rsp_in[4] = magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_4_req_in), - .floo_rsp_o (router_7_4_rsp_out), - .floo_req_o (router_7_4_req_out), - .floo_rsp_i (router_7_4_rsp_in) -); - - -floo_req_t [4:0] router_7_5_req_in; -floo_rsp_t [4:0] router_7_5_rsp_out; -floo_req_t [4:0] router_7_5_req_out; -floo_rsp_t [4:0] router_7_5_rsp_in; - - assign router_7_5_req_in[0] = router_7_6_to_router_7_5_req; - assign router_7_5_req_in[1] = router_8_5_to_router_7_5_req; - assign router_7_5_req_in[2] = router_7_4_to_router_7_5_req; - assign router_7_5_req_in[3] = router_6_5_to_router_7_5_req; - assign router_7_5_req_in[4] = magia_tile_ni_7_5_to_router_7_5_req; - - assign router_7_5_to_router_7_6_rsp = router_7_5_rsp_out[0]; - assign router_7_5_to_router_8_5_rsp = router_7_5_rsp_out[1]; - assign router_7_5_to_router_7_4_rsp = router_7_5_rsp_out[2]; - assign router_7_5_to_router_6_5_rsp = router_7_5_rsp_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_rsp = router_7_5_rsp_out[4]; - - assign router_7_5_to_router_7_6_req = router_7_5_req_out[0]; - assign router_7_5_to_router_8_5_req = router_7_5_req_out[1]; - assign router_7_5_to_router_7_4_req = router_7_5_req_out[2]; - assign router_7_5_to_router_6_5_req = router_7_5_req_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_req = router_7_5_req_out[4]; - - assign router_7_5_rsp_in[0] = router_7_6_to_router_7_5_rsp; - assign router_7_5_rsp_in[1] = router_8_5_to_router_7_5_rsp; - assign router_7_5_rsp_in[2] = router_7_4_to_router_7_5_rsp; - assign router_7_5_rsp_in[3] = router_6_5_to_router_7_5_rsp; - assign router_7_5_rsp_in[4] = magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_5_req_in), - .floo_rsp_o (router_7_5_rsp_out), - .floo_req_o (router_7_5_req_out), - .floo_rsp_i (router_7_5_rsp_in) -); - - -floo_req_t [4:0] router_7_6_req_in; -floo_rsp_t [4:0] router_7_6_rsp_out; -floo_req_t [4:0] router_7_6_req_out; -floo_rsp_t [4:0] router_7_6_rsp_in; - - assign router_7_6_req_in[0] = router_7_7_to_router_7_6_req; - assign router_7_6_req_in[1] = router_8_6_to_router_7_6_req; - assign router_7_6_req_in[2] = router_7_5_to_router_7_6_req; - assign router_7_6_req_in[3] = router_6_6_to_router_7_6_req; - assign router_7_6_req_in[4] = magia_tile_ni_7_6_to_router_7_6_req; - - assign router_7_6_to_router_7_7_rsp = router_7_6_rsp_out[0]; - assign router_7_6_to_router_8_6_rsp = router_7_6_rsp_out[1]; - assign router_7_6_to_router_7_5_rsp = router_7_6_rsp_out[2]; - assign router_7_6_to_router_6_6_rsp = router_7_6_rsp_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_rsp = router_7_6_rsp_out[4]; - - assign router_7_6_to_router_7_7_req = router_7_6_req_out[0]; - assign router_7_6_to_router_8_6_req = router_7_6_req_out[1]; - assign router_7_6_to_router_7_5_req = router_7_6_req_out[2]; - assign router_7_6_to_router_6_6_req = router_7_6_req_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_req = router_7_6_req_out[4]; - - assign router_7_6_rsp_in[0] = router_7_7_to_router_7_6_rsp; - assign router_7_6_rsp_in[1] = router_8_6_to_router_7_6_rsp; - assign router_7_6_rsp_in[2] = router_7_5_to_router_7_6_rsp; - assign router_7_6_rsp_in[3] = router_6_6_to_router_7_6_rsp; - assign router_7_6_rsp_in[4] = magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_6_req_in), - .floo_rsp_o (router_7_6_rsp_out), - .floo_req_o (router_7_6_req_out), - .floo_rsp_i (router_7_6_rsp_in) -); - - -floo_req_t [4:0] router_7_7_req_in; -floo_rsp_t [4:0] router_7_7_rsp_out; -floo_req_t [4:0] router_7_7_req_out; -floo_rsp_t [4:0] router_7_7_rsp_in; - - assign router_7_7_req_in[0] = router_7_8_to_router_7_7_req; - assign router_7_7_req_in[1] = router_8_7_to_router_7_7_req; - assign router_7_7_req_in[2] = router_7_6_to_router_7_7_req; - assign router_7_7_req_in[3] = router_6_7_to_router_7_7_req; - assign router_7_7_req_in[4] = magia_tile_ni_7_7_to_router_7_7_req; - - assign router_7_7_to_router_7_8_rsp = router_7_7_rsp_out[0]; - assign router_7_7_to_router_8_7_rsp = router_7_7_rsp_out[1]; - assign router_7_7_to_router_7_6_rsp = router_7_7_rsp_out[2]; - assign router_7_7_to_router_6_7_rsp = router_7_7_rsp_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_rsp = router_7_7_rsp_out[4]; - - assign router_7_7_to_router_7_8_req = router_7_7_req_out[0]; - assign router_7_7_to_router_8_7_req = router_7_7_req_out[1]; - assign router_7_7_to_router_7_6_req = router_7_7_req_out[2]; - assign router_7_7_to_router_6_7_req = router_7_7_req_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_req = router_7_7_req_out[4]; - - assign router_7_7_rsp_in[0] = router_7_8_to_router_7_7_rsp; - assign router_7_7_rsp_in[1] = router_8_7_to_router_7_7_rsp; - assign router_7_7_rsp_in[2] = router_7_6_to_router_7_7_rsp; - assign router_7_7_rsp_in[3] = router_6_7_to_router_7_7_rsp; - assign router_7_7_rsp_in[4] = magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_7_req_in), - .floo_rsp_o (router_7_7_rsp_out), - .floo_req_o (router_7_7_req_out), - .floo_rsp_i (router_7_7_rsp_in) -); - - -floo_req_t [4:0] router_7_8_req_in; -floo_rsp_t [4:0] router_7_8_rsp_out; -floo_req_t [4:0] router_7_8_req_out; -floo_rsp_t [4:0] router_7_8_rsp_in; - - assign router_7_8_req_in[0] = router_7_9_to_router_7_8_req; - assign router_7_8_req_in[1] = router_8_8_to_router_7_8_req; - assign router_7_8_req_in[2] = router_7_7_to_router_7_8_req; - assign router_7_8_req_in[3] = router_6_8_to_router_7_8_req; - assign router_7_8_req_in[4] = magia_tile_ni_7_8_to_router_7_8_req; - - assign router_7_8_to_router_7_9_rsp = router_7_8_rsp_out[0]; - assign router_7_8_to_router_8_8_rsp = router_7_8_rsp_out[1]; - assign router_7_8_to_router_7_7_rsp = router_7_8_rsp_out[2]; - assign router_7_8_to_router_6_8_rsp = router_7_8_rsp_out[3]; - assign router_7_8_to_magia_tile_ni_7_8_rsp = router_7_8_rsp_out[4]; - - assign router_7_8_to_router_7_9_req = router_7_8_req_out[0]; - assign router_7_8_to_router_8_8_req = router_7_8_req_out[1]; - assign router_7_8_to_router_7_7_req = router_7_8_req_out[2]; - assign router_7_8_to_router_6_8_req = router_7_8_req_out[3]; - assign router_7_8_to_magia_tile_ni_7_8_req = router_7_8_req_out[4]; - - assign router_7_8_rsp_in[0] = router_7_9_to_router_7_8_rsp; - assign router_7_8_rsp_in[1] = router_8_8_to_router_7_8_rsp; - assign router_7_8_rsp_in[2] = router_7_7_to_router_7_8_rsp; - assign router_7_8_rsp_in[3] = router_6_8_to_router_7_8_rsp; - assign router_7_8_rsp_in[4] = magia_tile_ni_7_8_to_router_7_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_8_req_in), - .floo_rsp_o (router_7_8_rsp_out), - .floo_req_o (router_7_8_req_out), - .floo_rsp_i (router_7_8_rsp_in) -); - - -floo_req_t [4:0] router_7_9_req_in; -floo_rsp_t [4:0] router_7_9_rsp_out; -floo_req_t [4:0] router_7_9_req_out; -floo_rsp_t [4:0] router_7_9_rsp_in; - - assign router_7_9_req_in[0] = router_7_10_to_router_7_9_req; - assign router_7_9_req_in[1] = router_8_9_to_router_7_9_req; - assign router_7_9_req_in[2] = router_7_8_to_router_7_9_req; - assign router_7_9_req_in[3] = router_6_9_to_router_7_9_req; - assign router_7_9_req_in[4] = magia_tile_ni_7_9_to_router_7_9_req; - - assign router_7_9_to_router_7_10_rsp = router_7_9_rsp_out[0]; - assign router_7_9_to_router_8_9_rsp = router_7_9_rsp_out[1]; - assign router_7_9_to_router_7_8_rsp = router_7_9_rsp_out[2]; - assign router_7_9_to_router_6_9_rsp = router_7_9_rsp_out[3]; - assign router_7_9_to_magia_tile_ni_7_9_rsp = router_7_9_rsp_out[4]; - - assign router_7_9_to_router_7_10_req = router_7_9_req_out[0]; - assign router_7_9_to_router_8_9_req = router_7_9_req_out[1]; - assign router_7_9_to_router_7_8_req = router_7_9_req_out[2]; - assign router_7_9_to_router_6_9_req = router_7_9_req_out[3]; - assign router_7_9_to_magia_tile_ni_7_9_req = router_7_9_req_out[4]; - - assign router_7_9_rsp_in[0] = router_7_10_to_router_7_9_rsp; - assign router_7_9_rsp_in[1] = router_8_9_to_router_7_9_rsp; - assign router_7_9_rsp_in[2] = router_7_8_to_router_7_9_rsp; - assign router_7_9_rsp_in[3] = router_6_9_to_router_7_9_rsp; - assign router_7_9_rsp_in[4] = magia_tile_ni_7_9_to_router_7_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_9_req_in), - .floo_rsp_o (router_7_9_rsp_out), - .floo_req_o (router_7_9_req_out), - .floo_rsp_i (router_7_9_rsp_in) -); - - -floo_req_t [4:0] router_7_10_req_in; -floo_rsp_t [4:0] router_7_10_rsp_out; -floo_req_t [4:0] router_7_10_req_out; -floo_rsp_t [4:0] router_7_10_rsp_in; - - assign router_7_10_req_in[0] = router_7_11_to_router_7_10_req; - assign router_7_10_req_in[1] = router_8_10_to_router_7_10_req; - assign router_7_10_req_in[2] = router_7_9_to_router_7_10_req; - assign router_7_10_req_in[3] = router_6_10_to_router_7_10_req; - assign router_7_10_req_in[4] = magia_tile_ni_7_10_to_router_7_10_req; - - assign router_7_10_to_router_7_11_rsp = router_7_10_rsp_out[0]; - assign router_7_10_to_router_8_10_rsp = router_7_10_rsp_out[1]; - assign router_7_10_to_router_7_9_rsp = router_7_10_rsp_out[2]; - assign router_7_10_to_router_6_10_rsp = router_7_10_rsp_out[3]; - assign router_7_10_to_magia_tile_ni_7_10_rsp = router_7_10_rsp_out[4]; - - assign router_7_10_to_router_7_11_req = router_7_10_req_out[0]; - assign router_7_10_to_router_8_10_req = router_7_10_req_out[1]; - assign router_7_10_to_router_7_9_req = router_7_10_req_out[2]; - assign router_7_10_to_router_6_10_req = router_7_10_req_out[3]; - assign router_7_10_to_magia_tile_ni_7_10_req = router_7_10_req_out[4]; - - assign router_7_10_rsp_in[0] = router_7_11_to_router_7_10_rsp; - assign router_7_10_rsp_in[1] = router_8_10_to_router_7_10_rsp; - assign router_7_10_rsp_in[2] = router_7_9_to_router_7_10_rsp; - assign router_7_10_rsp_in[3] = router_6_10_to_router_7_10_rsp; - assign router_7_10_rsp_in[4] = magia_tile_ni_7_10_to_router_7_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_10_req_in), - .floo_rsp_o (router_7_10_rsp_out), - .floo_req_o (router_7_10_req_out), - .floo_rsp_i (router_7_10_rsp_in) -); - - -floo_req_t [4:0] router_7_11_req_in; -floo_rsp_t [4:0] router_7_11_rsp_out; -floo_req_t [4:0] router_7_11_req_out; -floo_rsp_t [4:0] router_7_11_rsp_in; - - assign router_7_11_req_in[0] = router_7_12_to_router_7_11_req; - assign router_7_11_req_in[1] = router_8_11_to_router_7_11_req; - assign router_7_11_req_in[2] = router_7_10_to_router_7_11_req; - assign router_7_11_req_in[3] = router_6_11_to_router_7_11_req; - assign router_7_11_req_in[4] = magia_tile_ni_7_11_to_router_7_11_req; - - assign router_7_11_to_router_7_12_rsp = router_7_11_rsp_out[0]; - assign router_7_11_to_router_8_11_rsp = router_7_11_rsp_out[1]; - assign router_7_11_to_router_7_10_rsp = router_7_11_rsp_out[2]; - assign router_7_11_to_router_6_11_rsp = router_7_11_rsp_out[3]; - assign router_7_11_to_magia_tile_ni_7_11_rsp = router_7_11_rsp_out[4]; - - assign router_7_11_to_router_7_12_req = router_7_11_req_out[0]; - assign router_7_11_to_router_8_11_req = router_7_11_req_out[1]; - assign router_7_11_to_router_7_10_req = router_7_11_req_out[2]; - assign router_7_11_to_router_6_11_req = router_7_11_req_out[3]; - assign router_7_11_to_magia_tile_ni_7_11_req = router_7_11_req_out[4]; - - assign router_7_11_rsp_in[0] = router_7_12_to_router_7_11_rsp; - assign router_7_11_rsp_in[1] = router_8_11_to_router_7_11_rsp; - assign router_7_11_rsp_in[2] = router_7_10_to_router_7_11_rsp; - assign router_7_11_rsp_in[3] = router_6_11_to_router_7_11_rsp; - assign router_7_11_rsp_in[4] = magia_tile_ni_7_11_to_router_7_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_11_req_in), - .floo_rsp_o (router_7_11_rsp_out), - .floo_req_o (router_7_11_req_out), - .floo_rsp_i (router_7_11_rsp_in) -); - - -floo_req_t [4:0] router_7_12_req_in; -floo_rsp_t [4:0] router_7_12_rsp_out; -floo_req_t [4:0] router_7_12_req_out; -floo_rsp_t [4:0] router_7_12_rsp_in; - - assign router_7_12_req_in[0] = router_7_13_to_router_7_12_req; - assign router_7_12_req_in[1] = router_8_12_to_router_7_12_req; - assign router_7_12_req_in[2] = router_7_11_to_router_7_12_req; - assign router_7_12_req_in[3] = router_6_12_to_router_7_12_req; - assign router_7_12_req_in[4] = magia_tile_ni_7_12_to_router_7_12_req; - - assign router_7_12_to_router_7_13_rsp = router_7_12_rsp_out[0]; - assign router_7_12_to_router_8_12_rsp = router_7_12_rsp_out[1]; - assign router_7_12_to_router_7_11_rsp = router_7_12_rsp_out[2]; - assign router_7_12_to_router_6_12_rsp = router_7_12_rsp_out[3]; - assign router_7_12_to_magia_tile_ni_7_12_rsp = router_7_12_rsp_out[4]; - - assign router_7_12_to_router_7_13_req = router_7_12_req_out[0]; - assign router_7_12_to_router_8_12_req = router_7_12_req_out[1]; - assign router_7_12_to_router_7_11_req = router_7_12_req_out[2]; - assign router_7_12_to_router_6_12_req = router_7_12_req_out[3]; - assign router_7_12_to_magia_tile_ni_7_12_req = router_7_12_req_out[4]; - - assign router_7_12_rsp_in[0] = router_7_13_to_router_7_12_rsp; - assign router_7_12_rsp_in[1] = router_8_12_to_router_7_12_rsp; - assign router_7_12_rsp_in[2] = router_7_11_to_router_7_12_rsp; - assign router_7_12_rsp_in[3] = router_6_12_to_router_7_12_rsp; - assign router_7_12_rsp_in[4] = magia_tile_ni_7_12_to_router_7_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_12_req_in), - .floo_rsp_o (router_7_12_rsp_out), - .floo_req_o (router_7_12_req_out), - .floo_rsp_i (router_7_12_rsp_in) -); - - -floo_req_t [4:0] router_7_13_req_in; -floo_rsp_t [4:0] router_7_13_rsp_out; -floo_req_t [4:0] router_7_13_req_out; -floo_rsp_t [4:0] router_7_13_rsp_in; - - assign router_7_13_req_in[0] = router_7_14_to_router_7_13_req; - assign router_7_13_req_in[1] = router_8_13_to_router_7_13_req; - assign router_7_13_req_in[2] = router_7_12_to_router_7_13_req; - assign router_7_13_req_in[3] = router_6_13_to_router_7_13_req; - assign router_7_13_req_in[4] = magia_tile_ni_7_13_to_router_7_13_req; - - assign router_7_13_to_router_7_14_rsp = router_7_13_rsp_out[0]; - assign router_7_13_to_router_8_13_rsp = router_7_13_rsp_out[1]; - assign router_7_13_to_router_7_12_rsp = router_7_13_rsp_out[2]; - assign router_7_13_to_router_6_13_rsp = router_7_13_rsp_out[3]; - assign router_7_13_to_magia_tile_ni_7_13_rsp = router_7_13_rsp_out[4]; - - assign router_7_13_to_router_7_14_req = router_7_13_req_out[0]; - assign router_7_13_to_router_8_13_req = router_7_13_req_out[1]; - assign router_7_13_to_router_7_12_req = router_7_13_req_out[2]; - assign router_7_13_to_router_6_13_req = router_7_13_req_out[3]; - assign router_7_13_to_magia_tile_ni_7_13_req = router_7_13_req_out[4]; - - assign router_7_13_rsp_in[0] = router_7_14_to_router_7_13_rsp; - assign router_7_13_rsp_in[1] = router_8_13_to_router_7_13_rsp; - assign router_7_13_rsp_in[2] = router_7_12_to_router_7_13_rsp; - assign router_7_13_rsp_in[3] = router_6_13_to_router_7_13_rsp; - assign router_7_13_rsp_in[4] = magia_tile_ni_7_13_to_router_7_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_13_req_in), - .floo_rsp_o (router_7_13_rsp_out), - .floo_req_o (router_7_13_req_out), - .floo_rsp_i (router_7_13_rsp_in) -); - - -floo_req_t [4:0] router_7_14_req_in; -floo_rsp_t [4:0] router_7_14_rsp_out; -floo_req_t [4:0] router_7_14_req_out; -floo_rsp_t [4:0] router_7_14_rsp_in; - - assign router_7_14_req_in[0] = router_7_15_to_router_7_14_req; - assign router_7_14_req_in[1] = router_8_14_to_router_7_14_req; - assign router_7_14_req_in[2] = router_7_13_to_router_7_14_req; - assign router_7_14_req_in[3] = router_6_14_to_router_7_14_req; - assign router_7_14_req_in[4] = magia_tile_ni_7_14_to_router_7_14_req; - - assign router_7_14_to_router_7_15_rsp = router_7_14_rsp_out[0]; - assign router_7_14_to_router_8_14_rsp = router_7_14_rsp_out[1]; - assign router_7_14_to_router_7_13_rsp = router_7_14_rsp_out[2]; - assign router_7_14_to_router_6_14_rsp = router_7_14_rsp_out[3]; - assign router_7_14_to_magia_tile_ni_7_14_rsp = router_7_14_rsp_out[4]; - - assign router_7_14_to_router_7_15_req = router_7_14_req_out[0]; - assign router_7_14_to_router_8_14_req = router_7_14_req_out[1]; - assign router_7_14_to_router_7_13_req = router_7_14_req_out[2]; - assign router_7_14_to_router_6_14_req = router_7_14_req_out[3]; - assign router_7_14_to_magia_tile_ni_7_14_req = router_7_14_req_out[4]; - - assign router_7_14_rsp_in[0] = router_7_15_to_router_7_14_rsp; - assign router_7_14_rsp_in[1] = router_8_14_to_router_7_14_rsp; - assign router_7_14_rsp_in[2] = router_7_13_to_router_7_14_rsp; - assign router_7_14_rsp_in[3] = router_6_14_to_router_7_14_rsp; - assign router_7_14_rsp_in[4] = magia_tile_ni_7_14_to_router_7_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_14_req_in), - .floo_rsp_o (router_7_14_rsp_out), - .floo_req_o (router_7_14_req_out), - .floo_rsp_i (router_7_14_rsp_in) -); - - -floo_req_t [4:0] router_7_15_req_in; -floo_rsp_t [4:0] router_7_15_rsp_out; -floo_req_t [4:0] router_7_15_req_out; -floo_rsp_t [4:0] router_7_15_rsp_in; - - assign router_7_15_req_in[0] = '0; - assign router_7_15_req_in[1] = router_8_15_to_router_7_15_req; - assign router_7_15_req_in[2] = router_7_14_to_router_7_15_req; - assign router_7_15_req_in[3] = router_6_15_to_router_7_15_req; - assign router_7_15_req_in[4] = magia_tile_ni_7_15_to_router_7_15_req; - - assign router_7_15_to_router_8_15_rsp = router_7_15_rsp_out[1]; - assign router_7_15_to_router_7_14_rsp = router_7_15_rsp_out[2]; - assign router_7_15_to_router_6_15_rsp = router_7_15_rsp_out[3]; - assign router_7_15_to_magia_tile_ni_7_15_rsp = router_7_15_rsp_out[4]; - - assign router_7_15_to_router_8_15_req = router_7_15_req_out[1]; - assign router_7_15_to_router_7_14_req = router_7_15_req_out[2]; - assign router_7_15_to_router_6_15_req = router_7_15_req_out[3]; - assign router_7_15_to_magia_tile_ni_7_15_req = router_7_15_req_out[4]; - - assign router_7_15_rsp_in[0] = '0; - assign router_7_15_rsp_in[1] = router_8_15_to_router_7_15_rsp; - assign router_7_15_rsp_in[2] = router_7_14_to_router_7_15_rsp; - assign router_7_15_rsp_in[3] = router_6_15_to_router_7_15_rsp; - assign router_7_15_rsp_in[4] = magia_tile_ni_7_15_to_router_7_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_15_req_in), - .floo_rsp_o (router_7_15_rsp_out), - .floo_req_o (router_7_15_req_out), - .floo_rsp_i (router_7_15_rsp_in) -); - - -floo_req_t [4:0] router_8_0_req_in; -floo_rsp_t [4:0] router_8_0_rsp_out; -floo_req_t [4:0] router_8_0_req_out; -floo_rsp_t [4:0] router_8_0_rsp_in; - - assign router_8_0_req_in[0] = router_8_1_to_router_8_0_req; - assign router_8_0_req_in[1] = router_9_0_to_router_8_0_req; - assign router_8_0_req_in[2] = '0; - assign router_8_0_req_in[3] = router_7_0_to_router_8_0_req; - assign router_8_0_req_in[4] = magia_tile_ni_8_0_to_router_8_0_req; - - assign router_8_0_to_router_8_1_rsp = router_8_0_rsp_out[0]; - assign router_8_0_to_router_9_0_rsp = router_8_0_rsp_out[1]; - assign router_8_0_to_router_7_0_rsp = router_8_0_rsp_out[3]; - assign router_8_0_to_magia_tile_ni_8_0_rsp = router_8_0_rsp_out[4]; - - assign router_8_0_to_router_8_1_req = router_8_0_req_out[0]; - assign router_8_0_to_router_9_0_req = router_8_0_req_out[1]; - assign router_8_0_to_router_7_0_req = router_8_0_req_out[3]; - assign router_8_0_to_magia_tile_ni_8_0_req = router_8_0_req_out[4]; - - assign router_8_0_rsp_in[0] = router_8_1_to_router_8_0_rsp; - assign router_8_0_rsp_in[1] = router_9_0_to_router_8_0_rsp; - assign router_8_0_rsp_in[2] = '0; - assign router_8_0_rsp_in[3] = router_7_0_to_router_8_0_rsp; - assign router_8_0_rsp_in[4] = magia_tile_ni_8_0_to_router_8_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_0_req_in), - .floo_rsp_o (router_8_0_rsp_out), - .floo_req_o (router_8_0_req_out), - .floo_rsp_i (router_8_0_rsp_in) -); - - -floo_req_t [4:0] router_8_1_req_in; -floo_rsp_t [4:0] router_8_1_rsp_out; -floo_req_t [4:0] router_8_1_req_out; -floo_rsp_t [4:0] router_8_1_rsp_in; - - assign router_8_1_req_in[0] = router_8_2_to_router_8_1_req; - assign router_8_1_req_in[1] = router_9_1_to_router_8_1_req; - assign router_8_1_req_in[2] = router_8_0_to_router_8_1_req; - assign router_8_1_req_in[3] = router_7_1_to_router_8_1_req; - assign router_8_1_req_in[4] = magia_tile_ni_8_1_to_router_8_1_req; - - assign router_8_1_to_router_8_2_rsp = router_8_1_rsp_out[0]; - assign router_8_1_to_router_9_1_rsp = router_8_1_rsp_out[1]; - assign router_8_1_to_router_8_0_rsp = router_8_1_rsp_out[2]; - assign router_8_1_to_router_7_1_rsp = router_8_1_rsp_out[3]; - assign router_8_1_to_magia_tile_ni_8_1_rsp = router_8_1_rsp_out[4]; - - assign router_8_1_to_router_8_2_req = router_8_1_req_out[0]; - assign router_8_1_to_router_9_1_req = router_8_1_req_out[1]; - assign router_8_1_to_router_8_0_req = router_8_1_req_out[2]; - assign router_8_1_to_router_7_1_req = router_8_1_req_out[3]; - assign router_8_1_to_magia_tile_ni_8_1_req = router_8_1_req_out[4]; - - assign router_8_1_rsp_in[0] = router_8_2_to_router_8_1_rsp; - assign router_8_1_rsp_in[1] = router_9_1_to_router_8_1_rsp; - assign router_8_1_rsp_in[2] = router_8_0_to_router_8_1_rsp; - assign router_8_1_rsp_in[3] = router_7_1_to_router_8_1_rsp; - assign router_8_1_rsp_in[4] = magia_tile_ni_8_1_to_router_8_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_1_req_in), - .floo_rsp_o (router_8_1_rsp_out), - .floo_req_o (router_8_1_req_out), - .floo_rsp_i (router_8_1_rsp_in) -); - - -floo_req_t [4:0] router_8_2_req_in; -floo_rsp_t [4:0] router_8_2_rsp_out; -floo_req_t [4:0] router_8_2_req_out; -floo_rsp_t [4:0] router_8_2_rsp_in; - - assign router_8_2_req_in[0] = router_8_3_to_router_8_2_req; - assign router_8_2_req_in[1] = router_9_2_to_router_8_2_req; - assign router_8_2_req_in[2] = router_8_1_to_router_8_2_req; - assign router_8_2_req_in[3] = router_7_2_to_router_8_2_req; - assign router_8_2_req_in[4] = magia_tile_ni_8_2_to_router_8_2_req; - - assign router_8_2_to_router_8_3_rsp = router_8_2_rsp_out[0]; - assign router_8_2_to_router_9_2_rsp = router_8_2_rsp_out[1]; - assign router_8_2_to_router_8_1_rsp = router_8_2_rsp_out[2]; - assign router_8_2_to_router_7_2_rsp = router_8_2_rsp_out[3]; - assign router_8_2_to_magia_tile_ni_8_2_rsp = router_8_2_rsp_out[4]; - - assign router_8_2_to_router_8_3_req = router_8_2_req_out[0]; - assign router_8_2_to_router_9_2_req = router_8_2_req_out[1]; - assign router_8_2_to_router_8_1_req = router_8_2_req_out[2]; - assign router_8_2_to_router_7_2_req = router_8_2_req_out[3]; - assign router_8_2_to_magia_tile_ni_8_2_req = router_8_2_req_out[4]; - - assign router_8_2_rsp_in[0] = router_8_3_to_router_8_2_rsp; - assign router_8_2_rsp_in[1] = router_9_2_to_router_8_2_rsp; - assign router_8_2_rsp_in[2] = router_8_1_to_router_8_2_rsp; - assign router_8_2_rsp_in[3] = router_7_2_to_router_8_2_rsp; - assign router_8_2_rsp_in[4] = magia_tile_ni_8_2_to_router_8_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_2_req_in), - .floo_rsp_o (router_8_2_rsp_out), - .floo_req_o (router_8_2_req_out), - .floo_rsp_i (router_8_2_rsp_in) -); - - -floo_req_t [4:0] router_8_3_req_in; -floo_rsp_t [4:0] router_8_3_rsp_out; -floo_req_t [4:0] router_8_3_req_out; -floo_rsp_t [4:0] router_8_3_rsp_in; - - assign router_8_3_req_in[0] = router_8_4_to_router_8_3_req; - assign router_8_3_req_in[1] = router_9_3_to_router_8_3_req; - assign router_8_3_req_in[2] = router_8_2_to_router_8_3_req; - assign router_8_3_req_in[3] = router_7_3_to_router_8_3_req; - assign router_8_3_req_in[4] = magia_tile_ni_8_3_to_router_8_3_req; - - assign router_8_3_to_router_8_4_rsp = router_8_3_rsp_out[0]; - assign router_8_3_to_router_9_3_rsp = router_8_3_rsp_out[1]; - assign router_8_3_to_router_8_2_rsp = router_8_3_rsp_out[2]; - assign router_8_3_to_router_7_3_rsp = router_8_3_rsp_out[3]; - assign router_8_3_to_magia_tile_ni_8_3_rsp = router_8_3_rsp_out[4]; - - assign router_8_3_to_router_8_4_req = router_8_3_req_out[0]; - assign router_8_3_to_router_9_3_req = router_8_3_req_out[1]; - assign router_8_3_to_router_8_2_req = router_8_3_req_out[2]; - assign router_8_3_to_router_7_3_req = router_8_3_req_out[3]; - assign router_8_3_to_magia_tile_ni_8_3_req = router_8_3_req_out[4]; - - assign router_8_3_rsp_in[0] = router_8_4_to_router_8_3_rsp; - assign router_8_3_rsp_in[1] = router_9_3_to_router_8_3_rsp; - assign router_8_3_rsp_in[2] = router_8_2_to_router_8_3_rsp; - assign router_8_3_rsp_in[3] = router_7_3_to_router_8_3_rsp; - assign router_8_3_rsp_in[4] = magia_tile_ni_8_3_to_router_8_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_3_req_in), - .floo_rsp_o (router_8_3_rsp_out), - .floo_req_o (router_8_3_req_out), - .floo_rsp_i (router_8_3_rsp_in) -); - - -floo_req_t [4:0] router_8_4_req_in; -floo_rsp_t [4:0] router_8_4_rsp_out; -floo_req_t [4:0] router_8_4_req_out; -floo_rsp_t [4:0] router_8_4_rsp_in; - - assign router_8_4_req_in[0] = router_8_5_to_router_8_4_req; - assign router_8_4_req_in[1] = router_9_4_to_router_8_4_req; - assign router_8_4_req_in[2] = router_8_3_to_router_8_4_req; - assign router_8_4_req_in[3] = router_7_4_to_router_8_4_req; - assign router_8_4_req_in[4] = magia_tile_ni_8_4_to_router_8_4_req; - - assign router_8_4_to_router_8_5_rsp = router_8_4_rsp_out[0]; - assign router_8_4_to_router_9_4_rsp = router_8_4_rsp_out[1]; - assign router_8_4_to_router_8_3_rsp = router_8_4_rsp_out[2]; - assign router_8_4_to_router_7_4_rsp = router_8_4_rsp_out[3]; - assign router_8_4_to_magia_tile_ni_8_4_rsp = router_8_4_rsp_out[4]; - - assign router_8_4_to_router_8_5_req = router_8_4_req_out[0]; - assign router_8_4_to_router_9_4_req = router_8_4_req_out[1]; - assign router_8_4_to_router_8_3_req = router_8_4_req_out[2]; - assign router_8_4_to_router_7_4_req = router_8_4_req_out[3]; - assign router_8_4_to_magia_tile_ni_8_4_req = router_8_4_req_out[4]; - - assign router_8_4_rsp_in[0] = router_8_5_to_router_8_4_rsp; - assign router_8_4_rsp_in[1] = router_9_4_to_router_8_4_rsp; - assign router_8_4_rsp_in[2] = router_8_3_to_router_8_4_rsp; - assign router_8_4_rsp_in[3] = router_7_4_to_router_8_4_rsp; - assign router_8_4_rsp_in[4] = magia_tile_ni_8_4_to_router_8_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_4_req_in), - .floo_rsp_o (router_8_4_rsp_out), - .floo_req_o (router_8_4_req_out), - .floo_rsp_i (router_8_4_rsp_in) -); - - -floo_req_t [4:0] router_8_5_req_in; -floo_rsp_t [4:0] router_8_5_rsp_out; -floo_req_t [4:0] router_8_5_req_out; -floo_rsp_t [4:0] router_8_5_rsp_in; - - assign router_8_5_req_in[0] = router_8_6_to_router_8_5_req; - assign router_8_5_req_in[1] = router_9_5_to_router_8_5_req; - assign router_8_5_req_in[2] = router_8_4_to_router_8_5_req; - assign router_8_5_req_in[3] = router_7_5_to_router_8_5_req; - assign router_8_5_req_in[4] = magia_tile_ni_8_5_to_router_8_5_req; - - assign router_8_5_to_router_8_6_rsp = router_8_5_rsp_out[0]; - assign router_8_5_to_router_9_5_rsp = router_8_5_rsp_out[1]; - assign router_8_5_to_router_8_4_rsp = router_8_5_rsp_out[2]; - assign router_8_5_to_router_7_5_rsp = router_8_5_rsp_out[3]; - assign router_8_5_to_magia_tile_ni_8_5_rsp = router_8_5_rsp_out[4]; - - assign router_8_5_to_router_8_6_req = router_8_5_req_out[0]; - assign router_8_5_to_router_9_5_req = router_8_5_req_out[1]; - assign router_8_5_to_router_8_4_req = router_8_5_req_out[2]; - assign router_8_5_to_router_7_5_req = router_8_5_req_out[3]; - assign router_8_5_to_magia_tile_ni_8_5_req = router_8_5_req_out[4]; - - assign router_8_5_rsp_in[0] = router_8_6_to_router_8_5_rsp; - assign router_8_5_rsp_in[1] = router_9_5_to_router_8_5_rsp; - assign router_8_5_rsp_in[2] = router_8_4_to_router_8_5_rsp; - assign router_8_5_rsp_in[3] = router_7_5_to_router_8_5_rsp; - assign router_8_5_rsp_in[4] = magia_tile_ni_8_5_to_router_8_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_5_req_in), - .floo_rsp_o (router_8_5_rsp_out), - .floo_req_o (router_8_5_req_out), - .floo_rsp_i (router_8_5_rsp_in) -); - - -floo_req_t [4:0] router_8_6_req_in; -floo_rsp_t [4:0] router_8_6_rsp_out; -floo_req_t [4:0] router_8_6_req_out; -floo_rsp_t [4:0] router_8_6_rsp_in; - - assign router_8_6_req_in[0] = router_8_7_to_router_8_6_req; - assign router_8_6_req_in[1] = router_9_6_to_router_8_6_req; - assign router_8_6_req_in[2] = router_8_5_to_router_8_6_req; - assign router_8_6_req_in[3] = router_7_6_to_router_8_6_req; - assign router_8_6_req_in[4] = magia_tile_ni_8_6_to_router_8_6_req; - - assign router_8_6_to_router_8_7_rsp = router_8_6_rsp_out[0]; - assign router_8_6_to_router_9_6_rsp = router_8_6_rsp_out[1]; - assign router_8_6_to_router_8_5_rsp = router_8_6_rsp_out[2]; - assign router_8_6_to_router_7_6_rsp = router_8_6_rsp_out[3]; - assign router_8_6_to_magia_tile_ni_8_6_rsp = router_8_6_rsp_out[4]; - - assign router_8_6_to_router_8_7_req = router_8_6_req_out[0]; - assign router_8_6_to_router_9_6_req = router_8_6_req_out[1]; - assign router_8_6_to_router_8_5_req = router_8_6_req_out[2]; - assign router_8_6_to_router_7_6_req = router_8_6_req_out[3]; - assign router_8_6_to_magia_tile_ni_8_6_req = router_8_6_req_out[4]; - - assign router_8_6_rsp_in[0] = router_8_7_to_router_8_6_rsp; - assign router_8_6_rsp_in[1] = router_9_6_to_router_8_6_rsp; - assign router_8_6_rsp_in[2] = router_8_5_to_router_8_6_rsp; - assign router_8_6_rsp_in[3] = router_7_6_to_router_8_6_rsp; - assign router_8_6_rsp_in[4] = magia_tile_ni_8_6_to_router_8_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_6_req_in), - .floo_rsp_o (router_8_6_rsp_out), - .floo_req_o (router_8_6_req_out), - .floo_rsp_i (router_8_6_rsp_in) -); - - -floo_req_t [4:0] router_8_7_req_in; -floo_rsp_t [4:0] router_8_7_rsp_out; -floo_req_t [4:0] router_8_7_req_out; -floo_rsp_t [4:0] router_8_7_rsp_in; - - assign router_8_7_req_in[0] = router_8_8_to_router_8_7_req; - assign router_8_7_req_in[1] = router_9_7_to_router_8_7_req; - assign router_8_7_req_in[2] = router_8_6_to_router_8_7_req; - assign router_8_7_req_in[3] = router_7_7_to_router_8_7_req; - assign router_8_7_req_in[4] = magia_tile_ni_8_7_to_router_8_7_req; - - assign router_8_7_to_router_8_8_rsp = router_8_7_rsp_out[0]; - assign router_8_7_to_router_9_7_rsp = router_8_7_rsp_out[1]; - assign router_8_7_to_router_8_6_rsp = router_8_7_rsp_out[2]; - assign router_8_7_to_router_7_7_rsp = router_8_7_rsp_out[3]; - assign router_8_7_to_magia_tile_ni_8_7_rsp = router_8_7_rsp_out[4]; - - assign router_8_7_to_router_8_8_req = router_8_7_req_out[0]; - assign router_8_7_to_router_9_7_req = router_8_7_req_out[1]; - assign router_8_7_to_router_8_6_req = router_8_7_req_out[2]; - assign router_8_7_to_router_7_7_req = router_8_7_req_out[3]; - assign router_8_7_to_magia_tile_ni_8_7_req = router_8_7_req_out[4]; - - assign router_8_7_rsp_in[0] = router_8_8_to_router_8_7_rsp; - assign router_8_7_rsp_in[1] = router_9_7_to_router_8_7_rsp; - assign router_8_7_rsp_in[2] = router_8_6_to_router_8_7_rsp; - assign router_8_7_rsp_in[3] = router_7_7_to_router_8_7_rsp; - assign router_8_7_rsp_in[4] = magia_tile_ni_8_7_to_router_8_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_7_req_in), - .floo_rsp_o (router_8_7_rsp_out), - .floo_req_o (router_8_7_req_out), - .floo_rsp_i (router_8_7_rsp_in) -); - - -floo_req_t [4:0] router_8_8_req_in; -floo_rsp_t [4:0] router_8_8_rsp_out; -floo_req_t [4:0] router_8_8_req_out; -floo_rsp_t [4:0] router_8_8_rsp_in; - - assign router_8_8_req_in[0] = router_8_9_to_router_8_8_req; - assign router_8_8_req_in[1] = router_9_8_to_router_8_8_req; - assign router_8_8_req_in[2] = router_8_7_to_router_8_8_req; - assign router_8_8_req_in[3] = router_7_8_to_router_8_8_req; - assign router_8_8_req_in[4] = magia_tile_ni_8_8_to_router_8_8_req; - - assign router_8_8_to_router_8_9_rsp = router_8_8_rsp_out[0]; - assign router_8_8_to_router_9_8_rsp = router_8_8_rsp_out[1]; - assign router_8_8_to_router_8_7_rsp = router_8_8_rsp_out[2]; - assign router_8_8_to_router_7_8_rsp = router_8_8_rsp_out[3]; - assign router_8_8_to_magia_tile_ni_8_8_rsp = router_8_8_rsp_out[4]; - - assign router_8_8_to_router_8_9_req = router_8_8_req_out[0]; - assign router_8_8_to_router_9_8_req = router_8_8_req_out[1]; - assign router_8_8_to_router_8_7_req = router_8_8_req_out[2]; - assign router_8_8_to_router_7_8_req = router_8_8_req_out[3]; - assign router_8_8_to_magia_tile_ni_8_8_req = router_8_8_req_out[4]; - - assign router_8_8_rsp_in[0] = router_8_9_to_router_8_8_rsp; - assign router_8_8_rsp_in[1] = router_9_8_to_router_8_8_rsp; - assign router_8_8_rsp_in[2] = router_8_7_to_router_8_8_rsp; - assign router_8_8_rsp_in[3] = router_7_8_to_router_8_8_rsp; - assign router_8_8_rsp_in[4] = magia_tile_ni_8_8_to_router_8_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_8_req_in), - .floo_rsp_o (router_8_8_rsp_out), - .floo_req_o (router_8_8_req_out), - .floo_rsp_i (router_8_8_rsp_in) -); - - -floo_req_t [4:0] router_8_9_req_in; -floo_rsp_t [4:0] router_8_9_rsp_out; -floo_req_t [4:0] router_8_9_req_out; -floo_rsp_t [4:0] router_8_9_rsp_in; - - assign router_8_9_req_in[0] = router_8_10_to_router_8_9_req; - assign router_8_9_req_in[1] = router_9_9_to_router_8_9_req; - assign router_8_9_req_in[2] = router_8_8_to_router_8_9_req; - assign router_8_9_req_in[3] = router_7_9_to_router_8_9_req; - assign router_8_9_req_in[4] = magia_tile_ni_8_9_to_router_8_9_req; - - assign router_8_9_to_router_8_10_rsp = router_8_9_rsp_out[0]; - assign router_8_9_to_router_9_9_rsp = router_8_9_rsp_out[1]; - assign router_8_9_to_router_8_8_rsp = router_8_9_rsp_out[2]; - assign router_8_9_to_router_7_9_rsp = router_8_9_rsp_out[3]; - assign router_8_9_to_magia_tile_ni_8_9_rsp = router_8_9_rsp_out[4]; - - assign router_8_9_to_router_8_10_req = router_8_9_req_out[0]; - assign router_8_9_to_router_9_9_req = router_8_9_req_out[1]; - assign router_8_9_to_router_8_8_req = router_8_9_req_out[2]; - assign router_8_9_to_router_7_9_req = router_8_9_req_out[3]; - assign router_8_9_to_magia_tile_ni_8_9_req = router_8_9_req_out[4]; - - assign router_8_9_rsp_in[0] = router_8_10_to_router_8_9_rsp; - assign router_8_9_rsp_in[1] = router_9_9_to_router_8_9_rsp; - assign router_8_9_rsp_in[2] = router_8_8_to_router_8_9_rsp; - assign router_8_9_rsp_in[3] = router_7_9_to_router_8_9_rsp; - assign router_8_9_rsp_in[4] = magia_tile_ni_8_9_to_router_8_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_9_req_in), - .floo_rsp_o (router_8_9_rsp_out), - .floo_req_o (router_8_9_req_out), - .floo_rsp_i (router_8_9_rsp_in) -); - - -floo_req_t [4:0] router_8_10_req_in; -floo_rsp_t [4:0] router_8_10_rsp_out; -floo_req_t [4:0] router_8_10_req_out; -floo_rsp_t [4:0] router_8_10_rsp_in; - - assign router_8_10_req_in[0] = router_8_11_to_router_8_10_req; - assign router_8_10_req_in[1] = router_9_10_to_router_8_10_req; - assign router_8_10_req_in[2] = router_8_9_to_router_8_10_req; - assign router_8_10_req_in[3] = router_7_10_to_router_8_10_req; - assign router_8_10_req_in[4] = magia_tile_ni_8_10_to_router_8_10_req; - - assign router_8_10_to_router_8_11_rsp = router_8_10_rsp_out[0]; - assign router_8_10_to_router_9_10_rsp = router_8_10_rsp_out[1]; - assign router_8_10_to_router_8_9_rsp = router_8_10_rsp_out[2]; - assign router_8_10_to_router_7_10_rsp = router_8_10_rsp_out[3]; - assign router_8_10_to_magia_tile_ni_8_10_rsp = router_8_10_rsp_out[4]; - - assign router_8_10_to_router_8_11_req = router_8_10_req_out[0]; - assign router_8_10_to_router_9_10_req = router_8_10_req_out[1]; - assign router_8_10_to_router_8_9_req = router_8_10_req_out[2]; - assign router_8_10_to_router_7_10_req = router_8_10_req_out[3]; - assign router_8_10_to_magia_tile_ni_8_10_req = router_8_10_req_out[4]; - - assign router_8_10_rsp_in[0] = router_8_11_to_router_8_10_rsp; - assign router_8_10_rsp_in[1] = router_9_10_to_router_8_10_rsp; - assign router_8_10_rsp_in[2] = router_8_9_to_router_8_10_rsp; - assign router_8_10_rsp_in[3] = router_7_10_to_router_8_10_rsp; - assign router_8_10_rsp_in[4] = magia_tile_ni_8_10_to_router_8_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_10_req_in), - .floo_rsp_o (router_8_10_rsp_out), - .floo_req_o (router_8_10_req_out), - .floo_rsp_i (router_8_10_rsp_in) -); - - -floo_req_t [4:0] router_8_11_req_in; -floo_rsp_t [4:0] router_8_11_rsp_out; -floo_req_t [4:0] router_8_11_req_out; -floo_rsp_t [4:0] router_8_11_rsp_in; - - assign router_8_11_req_in[0] = router_8_12_to_router_8_11_req; - assign router_8_11_req_in[1] = router_9_11_to_router_8_11_req; - assign router_8_11_req_in[2] = router_8_10_to_router_8_11_req; - assign router_8_11_req_in[3] = router_7_11_to_router_8_11_req; - assign router_8_11_req_in[4] = magia_tile_ni_8_11_to_router_8_11_req; - - assign router_8_11_to_router_8_12_rsp = router_8_11_rsp_out[0]; - assign router_8_11_to_router_9_11_rsp = router_8_11_rsp_out[1]; - assign router_8_11_to_router_8_10_rsp = router_8_11_rsp_out[2]; - assign router_8_11_to_router_7_11_rsp = router_8_11_rsp_out[3]; - assign router_8_11_to_magia_tile_ni_8_11_rsp = router_8_11_rsp_out[4]; - - assign router_8_11_to_router_8_12_req = router_8_11_req_out[0]; - assign router_8_11_to_router_9_11_req = router_8_11_req_out[1]; - assign router_8_11_to_router_8_10_req = router_8_11_req_out[2]; - assign router_8_11_to_router_7_11_req = router_8_11_req_out[3]; - assign router_8_11_to_magia_tile_ni_8_11_req = router_8_11_req_out[4]; - - assign router_8_11_rsp_in[0] = router_8_12_to_router_8_11_rsp; - assign router_8_11_rsp_in[1] = router_9_11_to_router_8_11_rsp; - assign router_8_11_rsp_in[2] = router_8_10_to_router_8_11_rsp; - assign router_8_11_rsp_in[3] = router_7_11_to_router_8_11_rsp; - assign router_8_11_rsp_in[4] = magia_tile_ni_8_11_to_router_8_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_11_req_in), - .floo_rsp_o (router_8_11_rsp_out), - .floo_req_o (router_8_11_req_out), - .floo_rsp_i (router_8_11_rsp_in) -); - - -floo_req_t [4:0] router_8_12_req_in; -floo_rsp_t [4:0] router_8_12_rsp_out; -floo_req_t [4:0] router_8_12_req_out; -floo_rsp_t [4:0] router_8_12_rsp_in; - - assign router_8_12_req_in[0] = router_8_13_to_router_8_12_req; - assign router_8_12_req_in[1] = router_9_12_to_router_8_12_req; - assign router_8_12_req_in[2] = router_8_11_to_router_8_12_req; - assign router_8_12_req_in[3] = router_7_12_to_router_8_12_req; - assign router_8_12_req_in[4] = magia_tile_ni_8_12_to_router_8_12_req; - - assign router_8_12_to_router_8_13_rsp = router_8_12_rsp_out[0]; - assign router_8_12_to_router_9_12_rsp = router_8_12_rsp_out[1]; - assign router_8_12_to_router_8_11_rsp = router_8_12_rsp_out[2]; - assign router_8_12_to_router_7_12_rsp = router_8_12_rsp_out[3]; - assign router_8_12_to_magia_tile_ni_8_12_rsp = router_8_12_rsp_out[4]; - - assign router_8_12_to_router_8_13_req = router_8_12_req_out[0]; - assign router_8_12_to_router_9_12_req = router_8_12_req_out[1]; - assign router_8_12_to_router_8_11_req = router_8_12_req_out[2]; - assign router_8_12_to_router_7_12_req = router_8_12_req_out[3]; - assign router_8_12_to_magia_tile_ni_8_12_req = router_8_12_req_out[4]; - - assign router_8_12_rsp_in[0] = router_8_13_to_router_8_12_rsp; - assign router_8_12_rsp_in[1] = router_9_12_to_router_8_12_rsp; - assign router_8_12_rsp_in[2] = router_8_11_to_router_8_12_rsp; - assign router_8_12_rsp_in[3] = router_7_12_to_router_8_12_rsp; - assign router_8_12_rsp_in[4] = magia_tile_ni_8_12_to_router_8_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_12_req_in), - .floo_rsp_o (router_8_12_rsp_out), - .floo_req_o (router_8_12_req_out), - .floo_rsp_i (router_8_12_rsp_in) -); - - -floo_req_t [4:0] router_8_13_req_in; -floo_rsp_t [4:0] router_8_13_rsp_out; -floo_req_t [4:0] router_8_13_req_out; -floo_rsp_t [4:0] router_8_13_rsp_in; - - assign router_8_13_req_in[0] = router_8_14_to_router_8_13_req; - assign router_8_13_req_in[1] = router_9_13_to_router_8_13_req; - assign router_8_13_req_in[2] = router_8_12_to_router_8_13_req; - assign router_8_13_req_in[3] = router_7_13_to_router_8_13_req; - assign router_8_13_req_in[4] = magia_tile_ni_8_13_to_router_8_13_req; - - assign router_8_13_to_router_8_14_rsp = router_8_13_rsp_out[0]; - assign router_8_13_to_router_9_13_rsp = router_8_13_rsp_out[1]; - assign router_8_13_to_router_8_12_rsp = router_8_13_rsp_out[2]; - assign router_8_13_to_router_7_13_rsp = router_8_13_rsp_out[3]; - assign router_8_13_to_magia_tile_ni_8_13_rsp = router_8_13_rsp_out[4]; - - assign router_8_13_to_router_8_14_req = router_8_13_req_out[0]; - assign router_8_13_to_router_9_13_req = router_8_13_req_out[1]; - assign router_8_13_to_router_8_12_req = router_8_13_req_out[2]; - assign router_8_13_to_router_7_13_req = router_8_13_req_out[3]; - assign router_8_13_to_magia_tile_ni_8_13_req = router_8_13_req_out[4]; - - assign router_8_13_rsp_in[0] = router_8_14_to_router_8_13_rsp; - assign router_8_13_rsp_in[1] = router_9_13_to_router_8_13_rsp; - assign router_8_13_rsp_in[2] = router_8_12_to_router_8_13_rsp; - assign router_8_13_rsp_in[3] = router_7_13_to_router_8_13_rsp; - assign router_8_13_rsp_in[4] = magia_tile_ni_8_13_to_router_8_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_13_req_in), - .floo_rsp_o (router_8_13_rsp_out), - .floo_req_o (router_8_13_req_out), - .floo_rsp_i (router_8_13_rsp_in) -); - - -floo_req_t [4:0] router_8_14_req_in; -floo_rsp_t [4:0] router_8_14_rsp_out; -floo_req_t [4:0] router_8_14_req_out; -floo_rsp_t [4:0] router_8_14_rsp_in; - - assign router_8_14_req_in[0] = router_8_15_to_router_8_14_req; - assign router_8_14_req_in[1] = router_9_14_to_router_8_14_req; - assign router_8_14_req_in[2] = router_8_13_to_router_8_14_req; - assign router_8_14_req_in[3] = router_7_14_to_router_8_14_req; - assign router_8_14_req_in[4] = magia_tile_ni_8_14_to_router_8_14_req; - - assign router_8_14_to_router_8_15_rsp = router_8_14_rsp_out[0]; - assign router_8_14_to_router_9_14_rsp = router_8_14_rsp_out[1]; - assign router_8_14_to_router_8_13_rsp = router_8_14_rsp_out[2]; - assign router_8_14_to_router_7_14_rsp = router_8_14_rsp_out[3]; - assign router_8_14_to_magia_tile_ni_8_14_rsp = router_8_14_rsp_out[4]; - - assign router_8_14_to_router_8_15_req = router_8_14_req_out[0]; - assign router_8_14_to_router_9_14_req = router_8_14_req_out[1]; - assign router_8_14_to_router_8_13_req = router_8_14_req_out[2]; - assign router_8_14_to_router_7_14_req = router_8_14_req_out[3]; - assign router_8_14_to_magia_tile_ni_8_14_req = router_8_14_req_out[4]; - - assign router_8_14_rsp_in[0] = router_8_15_to_router_8_14_rsp; - assign router_8_14_rsp_in[1] = router_9_14_to_router_8_14_rsp; - assign router_8_14_rsp_in[2] = router_8_13_to_router_8_14_rsp; - assign router_8_14_rsp_in[3] = router_7_14_to_router_8_14_rsp; - assign router_8_14_rsp_in[4] = magia_tile_ni_8_14_to_router_8_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_14_req_in), - .floo_rsp_o (router_8_14_rsp_out), - .floo_req_o (router_8_14_req_out), - .floo_rsp_i (router_8_14_rsp_in) -); - - -floo_req_t [4:0] router_8_15_req_in; -floo_rsp_t [4:0] router_8_15_rsp_out; -floo_req_t [4:0] router_8_15_req_out; -floo_rsp_t [4:0] router_8_15_rsp_in; - - assign router_8_15_req_in[0] = '0; - assign router_8_15_req_in[1] = router_9_15_to_router_8_15_req; - assign router_8_15_req_in[2] = router_8_14_to_router_8_15_req; - assign router_8_15_req_in[3] = router_7_15_to_router_8_15_req; - assign router_8_15_req_in[4] = magia_tile_ni_8_15_to_router_8_15_req; - - assign router_8_15_to_router_9_15_rsp = router_8_15_rsp_out[1]; - assign router_8_15_to_router_8_14_rsp = router_8_15_rsp_out[2]; - assign router_8_15_to_router_7_15_rsp = router_8_15_rsp_out[3]; - assign router_8_15_to_magia_tile_ni_8_15_rsp = router_8_15_rsp_out[4]; - - assign router_8_15_to_router_9_15_req = router_8_15_req_out[1]; - assign router_8_15_to_router_8_14_req = router_8_15_req_out[2]; - assign router_8_15_to_router_7_15_req = router_8_15_req_out[3]; - assign router_8_15_to_magia_tile_ni_8_15_req = router_8_15_req_out[4]; - - assign router_8_15_rsp_in[0] = '0; - assign router_8_15_rsp_in[1] = router_9_15_to_router_8_15_rsp; - assign router_8_15_rsp_in[2] = router_8_14_to_router_8_15_rsp; - assign router_8_15_rsp_in[3] = router_7_15_to_router_8_15_rsp; - assign router_8_15_rsp_in[4] = magia_tile_ni_8_15_to_router_8_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_15_req_in), - .floo_rsp_o (router_8_15_rsp_out), - .floo_req_o (router_8_15_req_out), - .floo_rsp_i (router_8_15_rsp_in) -); - - -floo_req_t [4:0] router_9_0_req_in; -floo_rsp_t [4:0] router_9_0_rsp_out; -floo_req_t [4:0] router_9_0_req_out; -floo_rsp_t [4:0] router_9_0_rsp_in; - - assign router_9_0_req_in[0] = router_9_1_to_router_9_0_req; - assign router_9_0_req_in[1] = router_10_0_to_router_9_0_req; - assign router_9_0_req_in[2] = '0; - assign router_9_0_req_in[3] = router_8_0_to_router_9_0_req; - assign router_9_0_req_in[4] = magia_tile_ni_9_0_to_router_9_0_req; - - assign router_9_0_to_router_9_1_rsp = router_9_0_rsp_out[0]; - assign router_9_0_to_router_10_0_rsp = router_9_0_rsp_out[1]; - assign router_9_0_to_router_8_0_rsp = router_9_0_rsp_out[3]; - assign router_9_0_to_magia_tile_ni_9_0_rsp = router_9_0_rsp_out[4]; - - assign router_9_0_to_router_9_1_req = router_9_0_req_out[0]; - assign router_9_0_to_router_10_0_req = router_9_0_req_out[1]; - assign router_9_0_to_router_8_0_req = router_9_0_req_out[3]; - assign router_9_0_to_magia_tile_ni_9_0_req = router_9_0_req_out[4]; - - assign router_9_0_rsp_in[0] = router_9_1_to_router_9_0_rsp; - assign router_9_0_rsp_in[1] = router_10_0_to_router_9_0_rsp; - assign router_9_0_rsp_in[2] = '0; - assign router_9_0_rsp_in[3] = router_8_0_to_router_9_0_rsp; - assign router_9_0_rsp_in[4] = magia_tile_ni_9_0_to_router_9_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_0_req_in), - .floo_rsp_o (router_9_0_rsp_out), - .floo_req_o (router_9_0_req_out), - .floo_rsp_i (router_9_0_rsp_in) -); - - -floo_req_t [4:0] router_9_1_req_in; -floo_rsp_t [4:0] router_9_1_rsp_out; -floo_req_t [4:0] router_9_1_req_out; -floo_rsp_t [4:0] router_9_1_rsp_in; - - assign router_9_1_req_in[0] = router_9_2_to_router_9_1_req; - assign router_9_1_req_in[1] = router_10_1_to_router_9_1_req; - assign router_9_1_req_in[2] = router_9_0_to_router_9_1_req; - assign router_9_1_req_in[3] = router_8_1_to_router_9_1_req; - assign router_9_1_req_in[4] = magia_tile_ni_9_1_to_router_9_1_req; - - assign router_9_1_to_router_9_2_rsp = router_9_1_rsp_out[0]; - assign router_9_1_to_router_10_1_rsp = router_9_1_rsp_out[1]; - assign router_9_1_to_router_9_0_rsp = router_9_1_rsp_out[2]; - assign router_9_1_to_router_8_1_rsp = router_9_1_rsp_out[3]; - assign router_9_1_to_magia_tile_ni_9_1_rsp = router_9_1_rsp_out[4]; - - assign router_9_1_to_router_9_2_req = router_9_1_req_out[0]; - assign router_9_1_to_router_10_1_req = router_9_1_req_out[1]; - assign router_9_1_to_router_9_0_req = router_9_1_req_out[2]; - assign router_9_1_to_router_8_1_req = router_9_1_req_out[3]; - assign router_9_1_to_magia_tile_ni_9_1_req = router_9_1_req_out[4]; - - assign router_9_1_rsp_in[0] = router_9_2_to_router_9_1_rsp; - assign router_9_1_rsp_in[1] = router_10_1_to_router_9_1_rsp; - assign router_9_1_rsp_in[2] = router_9_0_to_router_9_1_rsp; - assign router_9_1_rsp_in[3] = router_8_1_to_router_9_1_rsp; - assign router_9_1_rsp_in[4] = magia_tile_ni_9_1_to_router_9_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_1_req_in), - .floo_rsp_o (router_9_1_rsp_out), - .floo_req_o (router_9_1_req_out), - .floo_rsp_i (router_9_1_rsp_in) -); - - -floo_req_t [4:0] router_9_2_req_in; -floo_rsp_t [4:0] router_9_2_rsp_out; -floo_req_t [4:0] router_9_2_req_out; -floo_rsp_t [4:0] router_9_2_rsp_in; - - assign router_9_2_req_in[0] = router_9_3_to_router_9_2_req; - assign router_9_2_req_in[1] = router_10_2_to_router_9_2_req; - assign router_9_2_req_in[2] = router_9_1_to_router_9_2_req; - assign router_9_2_req_in[3] = router_8_2_to_router_9_2_req; - assign router_9_2_req_in[4] = magia_tile_ni_9_2_to_router_9_2_req; - - assign router_9_2_to_router_9_3_rsp = router_9_2_rsp_out[0]; - assign router_9_2_to_router_10_2_rsp = router_9_2_rsp_out[1]; - assign router_9_2_to_router_9_1_rsp = router_9_2_rsp_out[2]; - assign router_9_2_to_router_8_2_rsp = router_9_2_rsp_out[3]; - assign router_9_2_to_magia_tile_ni_9_2_rsp = router_9_2_rsp_out[4]; - - assign router_9_2_to_router_9_3_req = router_9_2_req_out[0]; - assign router_9_2_to_router_10_2_req = router_9_2_req_out[1]; - assign router_9_2_to_router_9_1_req = router_9_2_req_out[2]; - assign router_9_2_to_router_8_2_req = router_9_2_req_out[3]; - assign router_9_2_to_magia_tile_ni_9_2_req = router_9_2_req_out[4]; - - assign router_9_2_rsp_in[0] = router_9_3_to_router_9_2_rsp; - assign router_9_2_rsp_in[1] = router_10_2_to_router_9_2_rsp; - assign router_9_2_rsp_in[2] = router_9_1_to_router_9_2_rsp; - assign router_9_2_rsp_in[3] = router_8_2_to_router_9_2_rsp; - assign router_9_2_rsp_in[4] = magia_tile_ni_9_2_to_router_9_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_2_req_in), - .floo_rsp_o (router_9_2_rsp_out), - .floo_req_o (router_9_2_req_out), - .floo_rsp_i (router_9_2_rsp_in) -); - - -floo_req_t [4:0] router_9_3_req_in; -floo_rsp_t [4:0] router_9_3_rsp_out; -floo_req_t [4:0] router_9_3_req_out; -floo_rsp_t [4:0] router_9_3_rsp_in; - - assign router_9_3_req_in[0] = router_9_4_to_router_9_3_req; - assign router_9_3_req_in[1] = router_10_3_to_router_9_3_req; - assign router_9_3_req_in[2] = router_9_2_to_router_9_3_req; - assign router_9_3_req_in[3] = router_8_3_to_router_9_3_req; - assign router_9_3_req_in[4] = magia_tile_ni_9_3_to_router_9_3_req; - - assign router_9_3_to_router_9_4_rsp = router_9_3_rsp_out[0]; - assign router_9_3_to_router_10_3_rsp = router_9_3_rsp_out[1]; - assign router_9_3_to_router_9_2_rsp = router_9_3_rsp_out[2]; - assign router_9_3_to_router_8_3_rsp = router_9_3_rsp_out[3]; - assign router_9_3_to_magia_tile_ni_9_3_rsp = router_9_3_rsp_out[4]; - - assign router_9_3_to_router_9_4_req = router_9_3_req_out[0]; - assign router_9_3_to_router_10_3_req = router_9_3_req_out[1]; - assign router_9_3_to_router_9_2_req = router_9_3_req_out[2]; - assign router_9_3_to_router_8_3_req = router_9_3_req_out[3]; - assign router_9_3_to_magia_tile_ni_9_3_req = router_9_3_req_out[4]; - - assign router_9_3_rsp_in[0] = router_9_4_to_router_9_3_rsp; - assign router_9_3_rsp_in[1] = router_10_3_to_router_9_3_rsp; - assign router_9_3_rsp_in[2] = router_9_2_to_router_9_3_rsp; - assign router_9_3_rsp_in[3] = router_8_3_to_router_9_3_rsp; - assign router_9_3_rsp_in[4] = magia_tile_ni_9_3_to_router_9_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_3_req_in), - .floo_rsp_o (router_9_3_rsp_out), - .floo_req_o (router_9_3_req_out), - .floo_rsp_i (router_9_3_rsp_in) -); - - -floo_req_t [4:0] router_9_4_req_in; -floo_rsp_t [4:0] router_9_4_rsp_out; -floo_req_t [4:0] router_9_4_req_out; -floo_rsp_t [4:0] router_9_4_rsp_in; - - assign router_9_4_req_in[0] = router_9_5_to_router_9_4_req; - assign router_9_4_req_in[1] = router_10_4_to_router_9_4_req; - assign router_9_4_req_in[2] = router_9_3_to_router_9_4_req; - assign router_9_4_req_in[3] = router_8_4_to_router_9_4_req; - assign router_9_4_req_in[4] = magia_tile_ni_9_4_to_router_9_4_req; - - assign router_9_4_to_router_9_5_rsp = router_9_4_rsp_out[0]; - assign router_9_4_to_router_10_4_rsp = router_9_4_rsp_out[1]; - assign router_9_4_to_router_9_3_rsp = router_9_4_rsp_out[2]; - assign router_9_4_to_router_8_4_rsp = router_9_4_rsp_out[3]; - assign router_9_4_to_magia_tile_ni_9_4_rsp = router_9_4_rsp_out[4]; - - assign router_9_4_to_router_9_5_req = router_9_4_req_out[0]; - assign router_9_4_to_router_10_4_req = router_9_4_req_out[1]; - assign router_9_4_to_router_9_3_req = router_9_4_req_out[2]; - assign router_9_4_to_router_8_4_req = router_9_4_req_out[3]; - assign router_9_4_to_magia_tile_ni_9_4_req = router_9_4_req_out[4]; - - assign router_9_4_rsp_in[0] = router_9_5_to_router_9_4_rsp; - assign router_9_4_rsp_in[1] = router_10_4_to_router_9_4_rsp; - assign router_9_4_rsp_in[2] = router_9_3_to_router_9_4_rsp; - assign router_9_4_rsp_in[3] = router_8_4_to_router_9_4_rsp; - assign router_9_4_rsp_in[4] = magia_tile_ni_9_4_to_router_9_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_4_req_in), - .floo_rsp_o (router_9_4_rsp_out), - .floo_req_o (router_9_4_req_out), - .floo_rsp_i (router_9_4_rsp_in) -); - - -floo_req_t [4:0] router_9_5_req_in; -floo_rsp_t [4:0] router_9_5_rsp_out; -floo_req_t [4:0] router_9_5_req_out; -floo_rsp_t [4:0] router_9_5_rsp_in; - - assign router_9_5_req_in[0] = router_9_6_to_router_9_5_req; - assign router_9_5_req_in[1] = router_10_5_to_router_9_5_req; - assign router_9_5_req_in[2] = router_9_4_to_router_9_5_req; - assign router_9_5_req_in[3] = router_8_5_to_router_9_5_req; - assign router_9_5_req_in[4] = magia_tile_ni_9_5_to_router_9_5_req; - - assign router_9_5_to_router_9_6_rsp = router_9_5_rsp_out[0]; - assign router_9_5_to_router_10_5_rsp = router_9_5_rsp_out[1]; - assign router_9_5_to_router_9_4_rsp = router_9_5_rsp_out[2]; - assign router_9_5_to_router_8_5_rsp = router_9_5_rsp_out[3]; - assign router_9_5_to_magia_tile_ni_9_5_rsp = router_9_5_rsp_out[4]; - - assign router_9_5_to_router_9_6_req = router_9_5_req_out[0]; - assign router_9_5_to_router_10_5_req = router_9_5_req_out[1]; - assign router_9_5_to_router_9_4_req = router_9_5_req_out[2]; - assign router_9_5_to_router_8_5_req = router_9_5_req_out[3]; - assign router_9_5_to_magia_tile_ni_9_5_req = router_9_5_req_out[4]; - - assign router_9_5_rsp_in[0] = router_9_6_to_router_9_5_rsp; - assign router_9_5_rsp_in[1] = router_10_5_to_router_9_5_rsp; - assign router_9_5_rsp_in[2] = router_9_4_to_router_9_5_rsp; - assign router_9_5_rsp_in[3] = router_8_5_to_router_9_5_rsp; - assign router_9_5_rsp_in[4] = magia_tile_ni_9_5_to_router_9_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_5_req_in), - .floo_rsp_o (router_9_5_rsp_out), - .floo_req_o (router_9_5_req_out), - .floo_rsp_i (router_9_5_rsp_in) -); - - -floo_req_t [4:0] router_9_6_req_in; -floo_rsp_t [4:0] router_9_6_rsp_out; -floo_req_t [4:0] router_9_6_req_out; -floo_rsp_t [4:0] router_9_6_rsp_in; - - assign router_9_6_req_in[0] = router_9_7_to_router_9_6_req; - assign router_9_6_req_in[1] = router_10_6_to_router_9_6_req; - assign router_9_6_req_in[2] = router_9_5_to_router_9_6_req; - assign router_9_6_req_in[3] = router_8_6_to_router_9_6_req; - assign router_9_6_req_in[4] = magia_tile_ni_9_6_to_router_9_6_req; - - assign router_9_6_to_router_9_7_rsp = router_9_6_rsp_out[0]; - assign router_9_6_to_router_10_6_rsp = router_9_6_rsp_out[1]; - assign router_9_6_to_router_9_5_rsp = router_9_6_rsp_out[2]; - assign router_9_6_to_router_8_6_rsp = router_9_6_rsp_out[3]; - assign router_9_6_to_magia_tile_ni_9_6_rsp = router_9_6_rsp_out[4]; - - assign router_9_6_to_router_9_7_req = router_9_6_req_out[0]; - assign router_9_6_to_router_10_6_req = router_9_6_req_out[1]; - assign router_9_6_to_router_9_5_req = router_9_6_req_out[2]; - assign router_9_6_to_router_8_6_req = router_9_6_req_out[3]; - assign router_9_6_to_magia_tile_ni_9_6_req = router_9_6_req_out[4]; - - assign router_9_6_rsp_in[0] = router_9_7_to_router_9_6_rsp; - assign router_9_6_rsp_in[1] = router_10_6_to_router_9_6_rsp; - assign router_9_6_rsp_in[2] = router_9_5_to_router_9_6_rsp; - assign router_9_6_rsp_in[3] = router_8_6_to_router_9_6_rsp; - assign router_9_6_rsp_in[4] = magia_tile_ni_9_6_to_router_9_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_6_req_in), - .floo_rsp_o (router_9_6_rsp_out), - .floo_req_o (router_9_6_req_out), - .floo_rsp_i (router_9_6_rsp_in) -); - - -floo_req_t [4:0] router_9_7_req_in; -floo_rsp_t [4:0] router_9_7_rsp_out; -floo_req_t [4:0] router_9_7_req_out; -floo_rsp_t [4:0] router_9_7_rsp_in; - - assign router_9_7_req_in[0] = router_9_8_to_router_9_7_req; - assign router_9_7_req_in[1] = router_10_7_to_router_9_7_req; - assign router_9_7_req_in[2] = router_9_6_to_router_9_7_req; - assign router_9_7_req_in[3] = router_8_7_to_router_9_7_req; - assign router_9_7_req_in[4] = magia_tile_ni_9_7_to_router_9_7_req; - - assign router_9_7_to_router_9_8_rsp = router_9_7_rsp_out[0]; - assign router_9_7_to_router_10_7_rsp = router_9_7_rsp_out[1]; - assign router_9_7_to_router_9_6_rsp = router_9_7_rsp_out[2]; - assign router_9_7_to_router_8_7_rsp = router_9_7_rsp_out[3]; - assign router_9_7_to_magia_tile_ni_9_7_rsp = router_9_7_rsp_out[4]; - - assign router_9_7_to_router_9_8_req = router_9_7_req_out[0]; - assign router_9_7_to_router_10_7_req = router_9_7_req_out[1]; - assign router_9_7_to_router_9_6_req = router_9_7_req_out[2]; - assign router_9_7_to_router_8_7_req = router_9_7_req_out[3]; - assign router_9_7_to_magia_tile_ni_9_7_req = router_9_7_req_out[4]; - - assign router_9_7_rsp_in[0] = router_9_8_to_router_9_7_rsp; - assign router_9_7_rsp_in[1] = router_10_7_to_router_9_7_rsp; - assign router_9_7_rsp_in[2] = router_9_6_to_router_9_7_rsp; - assign router_9_7_rsp_in[3] = router_8_7_to_router_9_7_rsp; - assign router_9_7_rsp_in[4] = magia_tile_ni_9_7_to_router_9_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_7_req_in), - .floo_rsp_o (router_9_7_rsp_out), - .floo_req_o (router_9_7_req_out), - .floo_rsp_i (router_9_7_rsp_in) -); - - -floo_req_t [4:0] router_9_8_req_in; -floo_rsp_t [4:0] router_9_8_rsp_out; -floo_req_t [4:0] router_9_8_req_out; -floo_rsp_t [4:0] router_9_8_rsp_in; - - assign router_9_8_req_in[0] = router_9_9_to_router_9_8_req; - assign router_9_8_req_in[1] = router_10_8_to_router_9_8_req; - assign router_9_8_req_in[2] = router_9_7_to_router_9_8_req; - assign router_9_8_req_in[3] = router_8_8_to_router_9_8_req; - assign router_9_8_req_in[4] = magia_tile_ni_9_8_to_router_9_8_req; - - assign router_9_8_to_router_9_9_rsp = router_9_8_rsp_out[0]; - assign router_9_8_to_router_10_8_rsp = router_9_8_rsp_out[1]; - assign router_9_8_to_router_9_7_rsp = router_9_8_rsp_out[2]; - assign router_9_8_to_router_8_8_rsp = router_9_8_rsp_out[3]; - assign router_9_8_to_magia_tile_ni_9_8_rsp = router_9_8_rsp_out[4]; - - assign router_9_8_to_router_9_9_req = router_9_8_req_out[0]; - assign router_9_8_to_router_10_8_req = router_9_8_req_out[1]; - assign router_9_8_to_router_9_7_req = router_9_8_req_out[2]; - assign router_9_8_to_router_8_8_req = router_9_8_req_out[3]; - assign router_9_8_to_magia_tile_ni_9_8_req = router_9_8_req_out[4]; - - assign router_9_8_rsp_in[0] = router_9_9_to_router_9_8_rsp; - assign router_9_8_rsp_in[1] = router_10_8_to_router_9_8_rsp; - assign router_9_8_rsp_in[2] = router_9_7_to_router_9_8_rsp; - assign router_9_8_rsp_in[3] = router_8_8_to_router_9_8_rsp; - assign router_9_8_rsp_in[4] = magia_tile_ni_9_8_to_router_9_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_8_req_in), - .floo_rsp_o (router_9_8_rsp_out), - .floo_req_o (router_9_8_req_out), - .floo_rsp_i (router_9_8_rsp_in) -); - - -floo_req_t [4:0] router_9_9_req_in; -floo_rsp_t [4:0] router_9_9_rsp_out; -floo_req_t [4:0] router_9_9_req_out; -floo_rsp_t [4:0] router_9_9_rsp_in; - - assign router_9_9_req_in[0] = router_9_10_to_router_9_9_req; - assign router_9_9_req_in[1] = router_10_9_to_router_9_9_req; - assign router_9_9_req_in[2] = router_9_8_to_router_9_9_req; - assign router_9_9_req_in[3] = router_8_9_to_router_9_9_req; - assign router_9_9_req_in[4] = magia_tile_ni_9_9_to_router_9_9_req; - - assign router_9_9_to_router_9_10_rsp = router_9_9_rsp_out[0]; - assign router_9_9_to_router_10_9_rsp = router_9_9_rsp_out[1]; - assign router_9_9_to_router_9_8_rsp = router_9_9_rsp_out[2]; - assign router_9_9_to_router_8_9_rsp = router_9_9_rsp_out[3]; - assign router_9_9_to_magia_tile_ni_9_9_rsp = router_9_9_rsp_out[4]; - - assign router_9_9_to_router_9_10_req = router_9_9_req_out[0]; - assign router_9_9_to_router_10_9_req = router_9_9_req_out[1]; - assign router_9_9_to_router_9_8_req = router_9_9_req_out[2]; - assign router_9_9_to_router_8_9_req = router_9_9_req_out[3]; - assign router_9_9_to_magia_tile_ni_9_9_req = router_9_9_req_out[4]; - - assign router_9_9_rsp_in[0] = router_9_10_to_router_9_9_rsp; - assign router_9_9_rsp_in[1] = router_10_9_to_router_9_9_rsp; - assign router_9_9_rsp_in[2] = router_9_8_to_router_9_9_rsp; - assign router_9_9_rsp_in[3] = router_8_9_to_router_9_9_rsp; - assign router_9_9_rsp_in[4] = magia_tile_ni_9_9_to_router_9_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_9_req_in), - .floo_rsp_o (router_9_9_rsp_out), - .floo_req_o (router_9_9_req_out), - .floo_rsp_i (router_9_9_rsp_in) -); - - -floo_req_t [4:0] router_9_10_req_in; -floo_rsp_t [4:0] router_9_10_rsp_out; -floo_req_t [4:0] router_9_10_req_out; -floo_rsp_t [4:0] router_9_10_rsp_in; - - assign router_9_10_req_in[0] = router_9_11_to_router_9_10_req; - assign router_9_10_req_in[1] = router_10_10_to_router_9_10_req; - assign router_9_10_req_in[2] = router_9_9_to_router_9_10_req; - assign router_9_10_req_in[3] = router_8_10_to_router_9_10_req; - assign router_9_10_req_in[4] = magia_tile_ni_9_10_to_router_9_10_req; - - assign router_9_10_to_router_9_11_rsp = router_9_10_rsp_out[0]; - assign router_9_10_to_router_10_10_rsp = router_9_10_rsp_out[1]; - assign router_9_10_to_router_9_9_rsp = router_9_10_rsp_out[2]; - assign router_9_10_to_router_8_10_rsp = router_9_10_rsp_out[3]; - assign router_9_10_to_magia_tile_ni_9_10_rsp = router_9_10_rsp_out[4]; - - assign router_9_10_to_router_9_11_req = router_9_10_req_out[0]; - assign router_9_10_to_router_10_10_req = router_9_10_req_out[1]; - assign router_9_10_to_router_9_9_req = router_9_10_req_out[2]; - assign router_9_10_to_router_8_10_req = router_9_10_req_out[3]; - assign router_9_10_to_magia_tile_ni_9_10_req = router_9_10_req_out[4]; - - assign router_9_10_rsp_in[0] = router_9_11_to_router_9_10_rsp; - assign router_9_10_rsp_in[1] = router_10_10_to_router_9_10_rsp; - assign router_9_10_rsp_in[2] = router_9_9_to_router_9_10_rsp; - assign router_9_10_rsp_in[3] = router_8_10_to_router_9_10_rsp; - assign router_9_10_rsp_in[4] = magia_tile_ni_9_10_to_router_9_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_10_req_in), - .floo_rsp_o (router_9_10_rsp_out), - .floo_req_o (router_9_10_req_out), - .floo_rsp_i (router_9_10_rsp_in) -); - - -floo_req_t [4:0] router_9_11_req_in; -floo_rsp_t [4:0] router_9_11_rsp_out; -floo_req_t [4:0] router_9_11_req_out; -floo_rsp_t [4:0] router_9_11_rsp_in; - - assign router_9_11_req_in[0] = router_9_12_to_router_9_11_req; - assign router_9_11_req_in[1] = router_10_11_to_router_9_11_req; - assign router_9_11_req_in[2] = router_9_10_to_router_9_11_req; - assign router_9_11_req_in[3] = router_8_11_to_router_9_11_req; - assign router_9_11_req_in[4] = magia_tile_ni_9_11_to_router_9_11_req; - - assign router_9_11_to_router_9_12_rsp = router_9_11_rsp_out[0]; - assign router_9_11_to_router_10_11_rsp = router_9_11_rsp_out[1]; - assign router_9_11_to_router_9_10_rsp = router_9_11_rsp_out[2]; - assign router_9_11_to_router_8_11_rsp = router_9_11_rsp_out[3]; - assign router_9_11_to_magia_tile_ni_9_11_rsp = router_9_11_rsp_out[4]; - - assign router_9_11_to_router_9_12_req = router_9_11_req_out[0]; - assign router_9_11_to_router_10_11_req = router_9_11_req_out[1]; - assign router_9_11_to_router_9_10_req = router_9_11_req_out[2]; - assign router_9_11_to_router_8_11_req = router_9_11_req_out[3]; - assign router_9_11_to_magia_tile_ni_9_11_req = router_9_11_req_out[4]; - - assign router_9_11_rsp_in[0] = router_9_12_to_router_9_11_rsp; - assign router_9_11_rsp_in[1] = router_10_11_to_router_9_11_rsp; - assign router_9_11_rsp_in[2] = router_9_10_to_router_9_11_rsp; - assign router_9_11_rsp_in[3] = router_8_11_to_router_9_11_rsp; - assign router_9_11_rsp_in[4] = magia_tile_ni_9_11_to_router_9_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_11_req_in), - .floo_rsp_o (router_9_11_rsp_out), - .floo_req_o (router_9_11_req_out), - .floo_rsp_i (router_9_11_rsp_in) -); - - -floo_req_t [4:0] router_9_12_req_in; -floo_rsp_t [4:0] router_9_12_rsp_out; -floo_req_t [4:0] router_9_12_req_out; -floo_rsp_t [4:0] router_9_12_rsp_in; - - assign router_9_12_req_in[0] = router_9_13_to_router_9_12_req; - assign router_9_12_req_in[1] = router_10_12_to_router_9_12_req; - assign router_9_12_req_in[2] = router_9_11_to_router_9_12_req; - assign router_9_12_req_in[3] = router_8_12_to_router_9_12_req; - assign router_9_12_req_in[4] = magia_tile_ni_9_12_to_router_9_12_req; - - assign router_9_12_to_router_9_13_rsp = router_9_12_rsp_out[0]; - assign router_9_12_to_router_10_12_rsp = router_9_12_rsp_out[1]; - assign router_9_12_to_router_9_11_rsp = router_9_12_rsp_out[2]; - assign router_9_12_to_router_8_12_rsp = router_9_12_rsp_out[3]; - assign router_9_12_to_magia_tile_ni_9_12_rsp = router_9_12_rsp_out[4]; - - assign router_9_12_to_router_9_13_req = router_9_12_req_out[0]; - assign router_9_12_to_router_10_12_req = router_9_12_req_out[1]; - assign router_9_12_to_router_9_11_req = router_9_12_req_out[2]; - assign router_9_12_to_router_8_12_req = router_9_12_req_out[3]; - assign router_9_12_to_magia_tile_ni_9_12_req = router_9_12_req_out[4]; - - assign router_9_12_rsp_in[0] = router_9_13_to_router_9_12_rsp; - assign router_9_12_rsp_in[1] = router_10_12_to_router_9_12_rsp; - assign router_9_12_rsp_in[2] = router_9_11_to_router_9_12_rsp; - assign router_9_12_rsp_in[3] = router_8_12_to_router_9_12_rsp; - assign router_9_12_rsp_in[4] = magia_tile_ni_9_12_to_router_9_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_12_req_in), - .floo_rsp_o (router_9_12_rsp_out), - .floo_req_o (router_9_12_req_out), - .floo_rsp_i (router_9_12_rsp_in) -); - - -floo_req_t [4:0] router_9_13_req_in; -floo_rsp_t [4:0] router_9_13_rsp_out; -floo_req_t [4:0] router_9_13_req_out; -floo_rsp_t [4:0] router_9_13_rsp_in; - - assign router_9_13_req_in[0] = router_9_14_to_router_9_13_req; - assign router_9_13_req_in[1] = router_10_13_to_router_9_13_req; - assign router_9_13_req_in[2] = router_9_12_to_router_9_13_req; - assign router_9_13_req_in[3] = router_8_13_to_router_9_13_req; - assign router_9_13_req_in[4] = magia_tile_ni_9_13_to_router_9_13_req; - - assign router_9_13_to_router_9_14_rsp = router_9_13_rsp_out[0]; - assign router_9_13_to_router_10_13_rsp = router_9_13_rsp_out[1]; - assign router_9_13_to_router_9_12_rsp = router_9_13_rsp_out[2]; - assign router_9_13_to_router_8_13_rsp = router_9_13_rsp_out[3]; - assign router_9_13_to_magia_tile_ni_9_13_rsp = router_9_13_rsp_out[4]; - - assign router_9_13_to_router_9_14_req = router_9_13_req_out[0]; - assign router_9_13_to_router_10_13_req = router_9_13_req_out[1]; - assign router_9_13_to_router_9_12_req = router_9_13_req_out[2]; - assign router_9_13_to_router_8_13_req = router_9_13_req_out[3]; - assign router_9_13_to_magia_tile_ni_9_13_req = router_9_13_req_out[4]; - - assign router_9_13_rsp_in[0] = router_9_14_to_router_9_13_rsp; - assign router_9_13_rsp_in[1] = router_10_13_to_router_9_13_rsp; - assign router_9_13_rsp_in[2] = router_9_12_to_router_9_13_rsp; - assign router_9_13_rsp_in[3] = router_8_13_to_router_9_13_rsp; - assign router_9_13_rsp_in[4] = magia_tile_ni_9_13_to_router_9_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_13_req_in), - .floo_rsp_o (router_9_13_rsp_out), - .floo_req_o (router_9_13_req_out), - .floo_rsp_i (router_9_13_rsp_in) -); - - -floo_req_t [4:0] router_9_14_req_in; -floo_rsp_t [4:0] router_9_14_rsp_out; -floo_req_t [4:0] router_9_14_req_out; -floo_rsp_t [4:0] router_9_14_rsp_in; - - assign router_9_14_req_in[0] = router_9_15_to_router_9_14_req; - assign router_9_14_req_in[1] = router_10_14_to_router_9_14_req; - assign router_9_14_req_in[2] = router_9_13_to_router_9_14_req; - assign router_9_14_req_in[3] = router_8_14_to_router_9_14_req; - assign router_9_14_req_in[4] = magia_tile_ni_9_14_to_router_9_14_req; - - assign router_9_14_to_router_9_15_rsp = router_9_14_rsp_out[0]; - assign router_9_14_to_router_10_14_rsp = router_9_14_rsp_out[1]; - assign router_9_14_to_router_9_13_rsp = router_9_14_rsp_out[2]; - assign router_9_14_to_router_8_14_rsp = router_9_14_rsp_out[3]; - assign router_9_14_to_magia_tile_ni_9_14_rsp = router_9_14_rsp_out[4]; - - assign router_9_14_to_router_9_15_req = router_9_14_req_out[0]; - assign router_9_14_to_router_10_14_req = router_9_14_req_out[1]; - assign router_9_14_to_router_9_13_req = router_9_14_req_out[2]; - assign router_9_14_to_router_8_14_req = router_9_14_req_out[3]; - assign router_9_14_to_magia_tile_ni_9_14_req = router_9_14_req_out[4]; - - assign router_9_14_rsp_in[0] = router_9_15_to_router_9_14_rsp; - assign router_9_14_rsp_in[1] = router_10_14_to_router_9_14_rsp; - assign router_9_14_rsp_in[2] = router_9_13_to_router_9_14_rsp; - assign router_9_14_rsp_in[3] = router_8_14_to_router_9_14_rsp; - assign router_9_14_rsp_in[4] = magia_tile_ni_9_14_to_router_9_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_14_req_in), - .floo_rsp_o (router_9_14_rsp_out), - .floo_req_o (router_9_14_req_out), - .floo_rsp_i (router_9_14_rsp_in) -); - - -floo_req_t [4:0] router_9_15_req_in; -floo_rsp_t [4:0] router_9_15_rsp_out; -floo_req_t [4:0] router_9_15_req_out; -floo_rsp_t [4:0] router_9_15_rsp_in; - - assign router_9_15_req_in[0] = '0; - assign router_9_15_req_in[1] = router_10_15_to_router_9_15_req; - assign router_9_15_req_in[2] = router_9_14_to_router_9_15_req; - assign router_9_15_req_in[3] = router_8_15_to_router_9_15_req; - assign router_9_15_req_in[4] = magia_tile_ni_9_15_to_router_9_15_req; - - assign router_9_15_to_router_10_15_rsp = router_9_15_rsp_out[1]; - assign router_9_15_to_router_9_14_rsp = router_9_15_rsp_out[2]; - assign router_9_15_to_router_8_15_rsp = router_9_15_rsp_out[3]; - assign router_9_15_to_magia_tile_ni_9_15_rsp = router_9_15_rsp_out[4]; - - assign router_9_15_to_router_10_15_req = router_9_15_req_out[1]; - assign router_9_15_to_router_9_14_req = router_9_15_req_out[2]; - assign router_9_15_to_router_8_15_req = router_9_15_req_out[3]; - assign router_9_15_to_magia_tile_ni_9_15_req = router_9_15_req_out[4]; - - assign router_9_15_rsp_in[0] = '0; - assign router_9_15_rsp_in[1] = router_10_15_to_router_9_15_rsp; - assign router_9_15_rsp_in[2] = router_9_14_to_router_9_15_rsp; - assign router_9_15_rsp_in[3] = router_8_15_to_router_9_15_rsp; - assign router_9_15_rsp_in[4] = magia_tile_ni_9_15_to_router_9_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_15_req_in), - .floo_rsp_o (router_9_15_rsp_out), - .floo_req_o (router_9_15_req_out), - .floo_rsp_i (router_9_15_rsp_in) -); - - -floo_req_t [4:0] router_10_0_req_in; -floo_rsp_t [4:0] router_10_0_rsp_out; -floo_req_t [4:0] router_10_0_req_out; -floo_rsp_t [4:0] router_10_0_rsp_in; - - assign router_10_0_req_in[0] = router_10_1_to_router_10_0_req; - assign router_10_0_req_in[1] = router_11_0_to_router_10_0_req; - assign router_10_0_req_in[2] = '0; - assign router_10_0_req_in[3] = router_9_0_to_router_10_0_req; - assign router_10_0_req_in[4] = magia_tile_ni_10_0_to_router_10_0_req; - - assign router_10_0_to_router_10_1_rsp = router_10_0_rsp_out[0]; - assign router_10_0_to_router_11_0_rsp = router_10_0_rsp_out[1]; - assign router_10_0_to_router_9_0_rsp = router_10_0_rsp_out[3]; - assign router_10_0_to_magia_tile_ni_10_0_rsp = router_10_0_rsp_out[4]; - - assign router_10_0_to_router_10_1_req = router_10_0_req_out[0]; - assign router_10_0_to_router_11_0_req = router_10_0_req_out[1]; - assign router_10_0_to_router_9_0_req = router_10_0_req_out[3]; - assign router_10_0_to_magia_tile_ni_10_0_req = router_10_0_req_out[4]; - - assign router_10_0_rsp_in[0] = router_10_1_to_router_10_0_rsp; - assign router_10_0_rsp_in[1] = router_11_0_to_router_10_0_rsp; - assign router_10_0_rsp_in[2] = '0; - assign router_10_0_rsp_in[3] = router_9_0_to_router_10_0_rsp; - assign router_10_0_rsp_in[4] = magia_tile_ni_10_0_to_router_10_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_0_req_in), - .floo_rsp_o (router_10_0_rsp_out), - .floo_req_o (router_10_0_req_out), - .floo_rsp_i (router_10_0_rsp_in) -); - - -floo_req_t [4:0] router_10_1_req_in; -floo_rsp_t [4:0] router_10_1_rsp_out; -floo_req_t [4:0] router_10_1_req_out; -floo_rsp_t [4:0] router_10_1_rsp_in; - - assign router_10_1_req_in[0] = router_10_2_to_router_10_1_req; - assign router_10_1_req_in[1] = router_11_1_to_router_10_1_req; - assign router_10_1_req_in[2] = router_10_0_to_router_10_1_req; - assign router_10_1_req_in[3] = router_9_1_to_router_10_1_req; - assign router_10_1_req_in[4] = magia_tile_ni_10_1_to_router_10_1_req; - - assign router_10_1_to_router_10_2_rsp = router_10_1_rsp_out[0]; - assign router_10_1_to_router_11_1_rsp = router_10_1_rsp_out[1]; - assign router_10_1_to_router_10_0_rsp = router_10_1_rsp_out[2]; - assign router_10_1_to_router_9_1_rsp = router_10_1_rsp_out[3]; - assign router_10_1_to_magia_tile_ni_10_1_rsp = router_10_1_rsp_out[4]; - - assign router_10_1_to_router_10_2_req = router_10_1_req_out[0]; - assign router_10_1_to_router_11_1_req = router_10_1_req_out[1]; - assign router_10_1_to_router_10_0_req = router_10_1_req_out[2]; - assign router_10_1_to_router_9_1_req = router_10_1_req_out[3]; - assign router_10_1_to_magia_tile_ni_10_1_req = router_10_1_req_out[4]; - - assign router_10_1_rsp_in[0] = router_10_2_to_router_10_1_rsp; - assign router_10_1_rsp_in[1] = router_11_1_to_router_10_1_rsp; - assign router_10_1_rsp_in[2] = router_10_0_to_router_10_1_rsp; - assign router_10_1_rsp_in[3] = router_9_1_to_router_10_1_rsp; - assign router_10_1_rsp_in[4] = magia_tile_ni_10_1_to_router_10_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_1_req_in), - .floo_rsp_o (router_10_1_rsp_out), - .floo_req_o (router_10_1_req_out), - .floo_rsp_i (router_10_1_rsp_in) -); - - -floo_req_t [4:0] router_10_2_req_in; -floo_rsp_t [4:0] router_10_2_rsp_out; -floo_req_t [4:0] router_10_2_req_out; -floo_rsp_t [4:0] router_10_2_rsp_in; - - assign router_10_2_req_in[0] = router_10_3_to_router_10_2_req; - assign router_10_2_req_in[1] = router_11_2_to_router_10_2_req; - assign router_10_2_req_in[2] = router_10_1_to_router_10_2_req; - assign router_10_2_req_in[3] = router_9_2_to_router_10_2_req; - assign router_10_2_req_in[4] = magia_tile_ni_10_2_to_router_10_2_req; - - assign router_10_2_to_router_10_3_rsp = router_10_2_rsp_out[0]; - assign router_10_2_to_router_11_2_rsp = router_10_2_rsp_out[1]; - assign router_10_2_to_router_10_1_rsp = router_10_2_rsp_out[2]; - assign router_10_2_to_router_9_2_rsp = router_10_2_rsp_out[3]; - assign router_10_2_to_magia_tile_ni_10_2_rsp = router_10_2_rsp_out[4]; - - assign router_10_2_to_router_10_3_req = router_10_2_req_out[0]; - assign router_10_2_to_router_11_2_req = router_10_2_req_out[1]; - assign router_10_2_to_router_10_1_req = router_10_2_req_out[2]; - assign router_10_2_to_router_9_2_req = router_10_2_req_out[3]; - assign router_10_2_to_magia_tile_ni_10_2_req = router_10_2_req_out[4]; - - assign router_10_2_rsp_in[0] = router_10_3_to_router_10_2_rsp; - assign router_10_2_rsp_in[1] = router_11_2_to_router_10_2_rsp; - assign router_10_2_rsp_in[2] = router_10_1_to_router_10_2_rsp; - assign router_10_2_rsp_in[3] = router_9_2_to_router_10_2_rsp; - assign router_10_2_rsp_in[4] = magia_tile_ni_10_2_to_router_10_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_2_req_in), - .floo_rsp_o (router_10_2_rsp_out), - .floo_req_o (router_10_2_req_out), - .floo_rsp_i (router_10_2_rsp_in) -); - - -floo_req_t [4:0] router_10_3_req_in; -floo_rsp_t [4:0] router_10_3_rsp_out; -floo_req_t [4:0] router_10_3_req_out; -floo_rsp_t [4:0] router_10_3_rsp_in; - - assign router_10_3_req_in[0] = router_10_4_to_router_10_3_req; - assign router_10_3_req_in[1] = router_11_3_to_router_10_3_req; - assign router_10_3_req_in[2] = router_10_2_to_router_10_3_req; - assign router_10_3_req_in[3] = router_9_3_to_router_10_3_req; - assign router_10_3_req_in[4] = magia_tile_ni_10_3_to_router_10_3_req; - - assign router_10_3_to_router_10_4_rsp = router_10_3_rsp_out[0]; - assign router_10_3_to_router_11_3_rsp = router_10_3_rsp_out[1]; - assign router_10_3_to_router_10_2_rsp = router_10_3_rsp_out[2]; - assign router_10_3_to_router_9_3_rsp = router_10_3_rsp_out[3]; - assign router_10_3_to_magia_tile_ni_10_3_rsp = router_10_3_rsp_out[4]; - - assign router_10_3_to_router_10_4_req = router_10_3_req_out[0]; - assign router_10_3_to_router_11_3_req = router_10_3_req_out[1]; - assign router_10_3_to_router_10_2_req = router_10_3_req_out[2]; - assign router_10_3_to_router_9_3_req = router_10_3_req_out[3]; - assign router_10_3_to_magia_tile_ni_10_3_req = router_10_3_req_out[4]; - - assign router_10_3_rsp_in[0] = router_10_4_to_router_10_3_rsp; - assign router_10_3_rsp_in[1] = router_11_3_to_router_10_3_rsp; - assign router_10_3_rsp_in[2] = router_10_2_to_router_10_3_rsp; - assign router_10_3_rsp_in[3] = router_9_3_to_router_10_3_rsp; - assign router_10_3_rsp_in[4] = magia_tile_ni_10_3_to_router_10_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_3_req_in), - .floo_rsp_o (router_10_3_rsp_out), - .floo_req_o (router_10_3_req_out), - .floo_rsp_i (router_10_3_rsp_in) -); - - -floo_req_t [4:0] router_10_4_req_in; -floo_rsp_t [4:0] router_10_4_rsp_out; -floo_req_t [4:0] router_10_4_req_out; -floo_rsp_t [4:0] router_10_4_rsp_in; - - assign router_10_4_req_in[0] = router_10_5_to_router_10_4_req; - assign router_10_4_req_in[1] = router_11_4_to_router_10_4_req; - assign router_10_4_req_in[2] = router_10_3_to_router_10_4_req; - assign router_10_4_req_in[3] = router_9_4_to_router_10_4_req; - assign router_10_4_req_in[4] = magia_tile_ni_10_4_to_router_10_4_req; - - assign router_10_4_to_router_10_5_rsp = router_10_4_rsp_out[0]; - assign router_10_4_to_router_11_4_rsp = router_10_4_rsp_out[1]; - assign router_10_4_to_router_10_3_rsp = router_10_4_rsp_out[2]; - assign router_10_4_to_router_9_4_rsp = router_10_4_rsp_out[3]; - assign router_10_4_to_magia_tile_ni_10_4_rsp = router_10_4_rsp_out[4]; - - assign router_10_4_to_router_10_5_req = router_10_4_req_out[0]; - assign router_10_4_to_router_11_4_req = router_10_4_req_out[1]; - assign router_10_4_to_router_10_3_req = router_10_4_req_out[2]; - assign router_10_4_to_router_9_4_req = router_10_4_req_out[3]; - assign router_10_4_to_magia_tile_ni_10_4_req = router_10_4_req_out[4]; - - assign router_10_4_rsp_in[0] = router_10_5_to_router_10_4_rsp; - assign router_10_4_rsp_in[1] = router_11_4_to_router_10_4_rsp; - assign router_10_4_rsp_in[2] = router_10_3_to_router_10_4_rsp; - assign router_10_4_rsp_in[3] = router_9_4_to_router_10_4_rsp; - assign router_10_4_rsp_in[4] = magia_tile_ni_10_4_to_router_10_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_4_req_in), - .floo_rsp_o (router_10_4_rsp_out), - .floo_req_o (router_10_4_req_out), - .floo_rsp_i (router_10_4_rsp_in) -); - - -floo_req_t [4:0] router_10_5_req_in; -floo_rsp_t [4:0] router_10_5_rsp_out; -floo_req_t [4:0] router_10_5_req_out; -floo_rsp_t [4:0] router_10_5_rsp_in; - - assign router_10_5_req_in[0] = router_10_6_to_router_10_5_req; - assign router_10_5_req_in[1] = router_11_5_to_router_10_5_req; - assign router_10_5_req_in[2] = router_10_4_to_router_10_5_req; - assign router_10_5_req_in[3] = router_9_5_to_router_10_5_req; - assign router_10_5_req_in[4] = magia_tile_ni_10_5_to_router_10_5_req; - - assign router_10_5_to_router_10_6_rsp = router_10_5_rsp_out[0]; - assign router_10_5_to_router_11_5_rsp = router_10_5_rsp_out[1]; - assign router_10_5_to_router_10_4_rsp = router_10_5_rsp_out[2]; - assign router_10_5_to_router_9_5_rsp = router_10_5_rsp_out[3]; - assign router_10_5_to_magia_tile_ni_10_5_rsp = router_10_5_rsp_out[4]; - - assign router_10_5_to_router_10_6_req = router_10_5_req_out[0]; - assign router_10_5_to_router_11_5_req = router_10_5_req_out[1]; - assign router_10_5_to_router_10_4_req = router_10_5_req_out[2]; - assign router_10_5_to_router_9_5_req = router_10_5_req_out[3]; - assign router_10_5_to_magia_tile_ni_10_5_req = router_10_5_req_out[4]; - - assign router_10_5_rsp_in[0] = router_10_6_to_router_10_5_rsp; - assign router_10_5_rsp_in[1] = router_11_5_to_router_10_5_rsp; - assign router_10_5_rsp_in[2] = router_10_4_to_router_10_5_rsp; - assign router_10_5_rsp_in[3] = router_9_5_to_router_10_5_rsp; - assign router_10_5_rsp_in[4] = magia_tile_ni_10_5_to_router_10_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_5_req_in), - .floo_rsp_o (router_10_5_rsp_out), - .floo_req_o (router_10_5_req_out), - .floo_rsp_i (router_10_5_rsp_in) -); - - -floo_req_t [4:0] router_10_6_req_in; -floo_rsp_t [4:0] router_10_6_rsp_out; -floo_req_t [4:0] router_10_6_req_out; -floo_rsp_t [4:0] router_10_6_rsp_in; - - assign router_10_6_req_in[0] = router_10_7_to_router_10_6_req; - assign router_10_6_req_in[1] = router_11_6_to_router_10_6_req; - assign router_10_6_req_in[2] = router_10_5_to_router_10_6_req; - assign router_10_6_req_in[3] = router_9_6_to_router_10_6_req; - assign router_10_6_req_in[4] = magia_tile_ni_10_6_to_router_10_6_req; - - assign router_10_6_to_router_10_7_rsp = router_10_6_rsp_out[0]; - assign router_10_6_to_router_11_6_rsp = router_10_6_rsp_out[1]; - assign router_10_6_to_router_10_5_rsp = router_10_6_rsp_out[2]; - assign router_10_6_to_router_9_6_rsp = router_10_6_rsp_out[3]; - assign router_10_6_to_magia_tile_ni_10_6_rsp = router_10_6_rsp_out[4]; - - assign router_10_6_to_router_10_7_req = router_10_6_req_out[0]; - assign router_10_6_to_router_11_6_req = router_10_6_req_out[1]; - assign router_10_6_to_router_10_5_req = router_10_6_req_out[2]; - assign router_10_6_to_router_9_6_req = router_10_6_req_out[3]; - assign router_10_6_to_magia_tile_ni_10_6_req = router_10_6_req_out[4]; - - assign router_10_6_rsp_in[0] = router_10_7_to_router_10_6_rsp; - assign router_10_6_rsp_in[1] = router_11_6_to_router_10_6_rsp; - assign router_10_6_rsp_in[2] = router_10_5_to_router_10_6_rsp; - assign router_10_6_rsp_in[3] = router_9_6_to_router_10_6_rsp; - assign router_10_6_rsp_in[4] = magia_tile_ni_10_6_to_router_10_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_6_req_in), - .floo_rsp_o (router_10_6_rsp_out), - .floo_req_o (router_10_6_req_out), - .floo_rsp_i (router_10_6_rsp_in) -); - - -floo_req_t [4:0] router_10_7_req_in; -floo_rsp_t [4:0] router_10_7_rsp_out; -floo_req_t [4:0] router_10_7_req_out; -floo_rsp_t [4:0] router_10_7_rsp_in; - - assign router_10_7_req_in[0] = router_10_8_to_router_10_7_req; - assign router_10_7_req_in[1] = router_11_7_to_router_10_7_req; - assign router_10_7_req_in[2] = router_10_6_to_router_10_7_req; - assign router_10_7_req_in[3] = router_9_7_to_router_10_7_req; - assign router_10_7_req_in[4] = magia_tile_ni_10_7_to_router_10_7_req; - - assign router_10_7_to_router_10_8_rsp = router_10_7_rsp_out[0]; - assign router_10_7_to_router_11_7_rsp = router_10_7_rsp_out[1]; - assign router_10_7_to_router_10_6_rsp = router_10_7_rsp_out[2]; - assign router_10_7_to_router_9_7_rsp = router_10_7_rsp_out[3]; - assign router_10_7_to_magia_tile_ni_10_7_rsp = router_10_7_rsp_out[4]; - - assign router_10_7_to_router_10_8_req = router_10_7_req_out[0]; - assign router_10_7_to_router_11_7_req = router_10_7_req_out[1]; - assign router_10_7_to_router_10_6_req = router_10_7_req_out[2]; - assign router_10_7_to_router_9_7_req = router_10_7_req_out[3]; - assign router_10_7_to_magia_tile_ni_10_7_req = router_10_7_req_out[4]; - - assign router_10_7_rsp_in[0] = router_10_8_to_router_10_7_rsp; - assign router_10_7_rsp_in[1] = router_11_7_to_router_10_7_rsp; - assign router_10_7_rsp_in[2] = router_10_6_to_router_10_7_rsp; - assign router_10_7_rsp_in[3] = router_9_7_to_router_10_7_rsp; - assign router_10_7_rsp_in[4] = magia_tile_ni_10_7_to_router_10_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_7_req_in), - .floo_rsp_o (router_10_7_rsp_out), - .floo_req_o (router_10_7_req_out), - .floo_rsp_i (router_10_7_rsp_in) -); - - -floo_req_t [4:0] router_10_8_req_in; -floo_rsp_t [4:0] router_10_8_rsp_out; -floo_req_t [4:0] router_10_8_req_out; -floo_rsp_t [4:0] router_10_8_rsp_in; - - assign router_10_8_req_in[0] = router_10_9_to_router_10_8_req; - assign router_10_8_req_in[1] = router_11_8_to_router_10_8_req; - assign router_10_8_req_in[2] = router_10_7_to_router_10_8_req; - assign router_10_8_req_in[3] = router_9_8_to_router_10_8_req; - assign router_10_8_req_in[4] = magia_tile_ni_10_8_to_router_10_8_req; - - assign router_10_8_to_router_10_9_rsp = router_10_8_rsp_out[0]; - assign router_10_8_to_router_11_8_rsp = router_10_8_rsp_out[1]; - assign router_10_8_to_router_10_7_rsp = router_10_8_rsp_out[2]; - assign router_10_8_to_router_9_8_rsp = router_10_8_rsp_out[3]; - assign router_10_8_to_magia_tile_ni_10_8_rsp = router_10_8_rsp_out[4]; - - assign router_10_8_to_router_10_9_req = router_10_8_req_out[0]; - assign router_10_8_to_router_11_8_req = router_10_8_req_out[1]; - assign router_10_8_to_router_10_7_req = router_10_8_req_out[2]; - assign router_10_8_to_router_9_8_req = router_10_8_req_out[3]; - assign router_10_8_to_magia_tile_ni_10_8_req = router_10_8_req_out[4]; - - assign router_10_8_rsp_in[0] = router_10_9_to_router_10_8_rsp; - assign router_10_8_rsp_in[1] = router_11_8_to_router_10_8_rsp; - assign router_10_8_rsp_in[2] = router_10_7_to_router_10_8_rsp; - assign router_10_8_rsp_in[3] = router_9_8_to_router_10_8_rsp; - assign router_10_8_rsp_in[4] = magia_tile_ni_10_8_to_router_10_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_8_req_in), - .floo_rsp_o (router_10_8_rsp_out), - .floo_req_o (router_10_8_req_out), - .floo_rsp_i (router_10_8_rsp_in) -); - - -floo_req_t [4:0] router_10_9_req_in; -floo_rsp_t [4:0] router_10_9_rsp_out; -floo_req_t [4:0] router_10_9_req_out; -floo_rsp_t [4:0] router_10_9_rsp_in; - - assign router_10_9_req_in[0] = router_10_10_to_router_10_9_req; - assign router_10_9_req_in[1] = router_11_9_to_router_10_9_req; - assign router_10_9_req_in[2] = router_10_8_to_router_10_9_req; - assign router_10_9_req_in[3] = router_9_9_to_router_10_9_req; - assign router_10_9_req_in[4] = magia_tile_ni_10_9_to_router_10_9_req; - - assign router_10_9_to_router_10_10_rsp = router_10_9_rsp_out[0]; - assign router_10_9_to_router_11_9_rsp = router_10_9_rsp_out[1]; - assign router_10_9_to_router_10_8_rsp = router_10_9_rsp_out[2]; - assign router_10_9_to_router_9_9_rsp = router_10_9_rsp_out[3]; - assign router_10_9_to_magia_tile_ni_10_9_rsp = router_10_9_rsp_out[4]; - - assign router_10_9_to_router_10_10_req = router_10_9_req_out[0]; - assign router_10_9_to_router_11_9_req = router_10_9_req_out[1]; - assign router_10_9_to_router_10_8_req = router_10_9_req_out[2]; - assign router_10_9_to_router_9_9_req = router_10_9_req_out[3]; - assign router_10_9_to_magia_tile_ni_10_9_req = router_10_9_req_out[4]; - - assign router_10_9_rsp_in[0] = router_10_10_to_router_10_9_rsp; - assign router_10_9_rsp_in[1] = router_11_9_to_router_10_9_rsp; - assign router_10_9_rsp_in[2] = router_10_8_to_router_10_9_rsp; - assign router_10_9_rsp_in[3] = router_9_9_to_router_10_9_rsp; - assign router_10_9_rsp_in[4] = magia_tile_ni_10_9_to_router_10_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_9_req_in), - .floo_rsp_o (router_10_9_rsp_out), - .floo_req_o (router_10_9_req_out), - .floo_rsp_i (router_10_9_rsp_in) -); - - -floo_req_t [4:0] router_10_10_req_in; -floo_rsp_t [4:0] router_10_10_rsp_out; -floo_req_t [4:0] router_10_10_req_out; -floo_rsp_t [4:0] router_10_10_rsp_in; - - assign router_10_10_req_in[0] = router_10_11_to_router_10_10_req; - assign router_10_10_req_in[1] = router_11_10_to_router_10_10_req; - assign router_10_10_req_in[2] = router_10_9_to_router_10_10_req; - assign router_10_10_req_in[3] = router_9_10_to_router_10_10_req; - assign router_10_10_req_in[4] = magia_tile_ni_10_10_to_router_10_10_req; - - assign router_10_10_to_router_10_11_rsp = router_10_10_rsp_out[0]; - assign router_10_10_to_router_11_10_rsp = router_10_10_rsp_out[1]; - assign router_10_10_to_router_10_9_rsp = router_10_10_rsp_out[2]; - assign router_10_10_to_router_9_10_rsp = router_10_10_rsp_out[3]; - assign router_10_10_to_magia_tile_ni_10_10_rsp = router_10_10_rsp_out[4]; - - assign router_10_10_to_router_10_11_req = router_10_10_req_out[0]; - assign router_10_10_to_router_11_10_req = router_10_10_req_out[1]; - assign router_10_10_to_router_10_9_req = router_10_10_req_out[2]; - assign router_10_10_to_router_9_10_req = router_10_10_req_out[3]; - assign router_10_10_to_magia_tile_ni_10_10_req = router_10_10_req_out[4]; - - assign router_10_10_rsp_in[0] = router_10_11_to_router_10_10_rsp; - assign router_10_10_rsp_in[1] = router_11_10_to_router_10_10_rsp; - assign router_10_10_rsp_in[2] = router_10_9_to_router_10_10_rsp; - assign router_10_10_rsp_in[3] = router_9_10_to_router_10_10_rsp; - assign router_10_10_rsp_in[4] = magia_tile_ni_10_10_to_router_10_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_10_req_in), - .floo_rsp_o (router_10_10_rsp_out), - .floo_req_o (router_10_10_req_out), - .floo_rsp_i (router_10_10_rsp_in) -); - - -floo_req_t [4:0] router_10_11_req_in; -floo_rsp_t [4:0] router_10_11_rsp_out; -floo_req_t [4:0] router_10_11_req_out; -floo_rsp_t [4:0] router_10_11_rsp_in; - - assign router_10_11_req_in[0] = router_10_12_to_router_10_11_req; - assign router_10_11_req_in[1] = router_11_11_to_router_10_11_req; - assign router_10_11_req_in[2] = router_10_10_to_router_10_11_req; - assign router_10_11_req_in[3] = router_9_11_to_router_10_11_req; - assign router_10_11_req_in[4] = magia_tile_ni_10_11_to_router_10_11_req; - - assign router_10_11_to_router_10_12_rsp = router_10_11_rsp_out[0]; - assign router_10_11_to_router_11_11_rsp = router_10_11_rsp_out[1]; - assign router_10_11_to_router_10_10_rsp = router_10_11_rsp_out[2]; - assign router_10_11_to_router_9_11_rsp = router_10_11_rsp_out[3]; - assign router_10_11_to_magia_tile_ni_10_11_rsp = router_10_11_rsp_out[4]; - - assign router_10_11_to_router_10_12_req = router_10_11_req_out[0]; - assign router_10_11_to_router_11_11_req = router_10_11_req_out[1]; - assign router_10_11_to_router_10_10_req = router_10_11_req_out[2]; - assign router_10_11_to_router_9_11_req = router_10_11_req_out[3]; - assign router_10_11_to_magia_tile_ni_10_11_req = router_10_11_req_out[4]; - - assign router_10_11_rsp_in[0] = router_10_12_to_router_10_11_rsp; - assign router_10_11_rsp_in[1] = router_11_11_to_router_10_11_rsp; - assign router_10_11_rsp_in[2] = router_10_10_to_router_10_11_rsp; - assign router_10_11_rsp_in[3] = router_9_11_to_router_10_11_rsp; - assign router_10_11_rsp_in[4] = magia_tile_ni_10_11_to_router_10_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_11_req_in), - .floo_rsp_o (router_10_11_rsp_out), - .floo_req_o (router_10_11_req_out), - .floo_rsp_i (router_10_11_rsp_in) -); - - -floo_req_t [4:0] router_10_12_req_in; -floo_rsp_t [4:0] router_10_12_rsp_out; -floo_req_t [4:0] router_10_12_req_out; -floo_rsp_t [4:0] router_10_12_rsp_in; - - assign router_10_12_req_in[0] = router_10_13_to_router_10_12_req; - assign router_10_12_req_in[1] = router_11_12_to_router_10_12_req; - assign router_10_12_req_in[2] = router_10_11_to_router_10_12_req; - assign router_10_12_req_in[3] = router_9_12_to_router_10_12_req; - assign router_10_12_req_in[4] = magia_tile_ni_10_12_to_router_10_12_req; - - assign router_10_12_to_router_10_13_rsp = router_10_12_rsp_out[0]; - assign router_10_12_to_router_11_12_rsp = router_10_12_rsp_out[1]; - assign router_10_12_to_router_10_11_rsp = router_10_12_rsp_out[2]; - assign router_10_12_to_router_9_12_rsp = router_10_12_rsp_out[3]; - assign router_10_12_to_magia_tile_ni_10_12_rsp = router_10_12_rsp_out[4]; - - assign router_10_12_to_router_10_13_req = router_10_12_req_out[0]; - assign router_10_12_to_router_11_12_req = router_10_12_req_out[1]; - assign router_10_12_to_router_10_11_req = router_10_12_req_out[2]; - assign router_10_12_to_router_9_12_req = router_10_12_req_out[3]; - assign router_10_12_to_magia_tile_ni_10_12_req = router_10_12_req_out[4]; - - assign router_10_12_rsp_in[0] = router_10_13_to_router_10_12_rsp; - assign router_10_12_rsp_in[1] = router_11_12_to_router_10_12_rsp; - assign router_10_12_rsp_in[2] = router_10_11_to_router_10_12_rsp; - assign router_10_12_rsp_in[3] = router_9_12_to_router_10_12_rsp; - assign router_10_12_rsp_in[4] = magia_tile_ni_10_12_to_router_10_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_12_req_in), - .floo_rsp_o (router_10_12_rsp_out), - .floo_req_o (router_10_12_req_out), - .floo_rsp_i (router_10_12_rsp_in) -); - - -floo_req_t [4:0] router_10_13_req_in; -floo_rsp_t [4:0] router_10_13_rsp_out; -floo_req_t [4:0] router_10_13_req_out; -floo_rsp_t [4:0] router_10_13_rsp_in; - - assign router_10_13_req_in[0] = router_10_14_to_router_10_13_req; - assign router_10_13_req_in[1] = router_11_13_to_router_10_13_req; - assign router_10_13_req_in[2] = router_10_12_to_router_10_13_req; - assign router_10_13_req_in[3] = router_9_13_to_router_10_13_req; - assign router_10_13_req_in[4] = magia_tile_ni_10_13_to_router_10_13_req; - - assign router_10_13_to_router_10_14_rsp = router_10_13_rsp_out[0]; - assign router_10_13_to_router_11_13_rsp = router_10_13_rsp_out[1]; - assign router_10_13_to_router_10_12_rsp = router_10_13_rsp_out[2]; - assign router_10_13_to_router_9_13_rsp = router_10_13_rsp_out[3]; - assign router_10_13_to_magia_tile_ni_10_13_rsp = router_10_13_rsp_out[4]; - - assign router_10_13_to_router_10_14_req = router_10_13_req_out[0]; - assign router_10_13_to_router_11_13_req = router_10_13_req_out[1]; - assign router_10_13_to_router_10_12_req = router_10_13_req_out[2]; - assign router_10_13_to_router_9_13_req = router_10_13_req_out[3]; - assign router_10_13_to_magia_tile_ni_10_13_req = router_10_13_req_out[4]; - - assign router_10_13_rsp_in[0] = router_10_14_to_router_10_13_rsp; - assign router_10_13_rsp_in[1] = router_11_13_to_router_10_13_rsp; - assign router_10_13_rsp_in[2] = router_10_12_to_router_10_13_rsp; - assign router_10_13_rsp_in[3] = router_9_13_to_router_10_13_rsp; - assign router_10_13_rsp_in[4] = magia_tile_ni_10_13_to_router_10_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_13_req_in), - .floo_rsp_o (router_10_13_rsp_out), - .floo_req_o (router_10_13_req_out), - .floo_rsp_i (router_10_13_rsp_in) -); - - -floo_req_t [4:0] router_10_14_req_in; -floo_rsp_t [4:0] router_10_14_rsp_out; -floo_req_t [4:0] router_10_14_req_out; -floo_rsp_t [4:0] router_10_14_rsp_in; - - assign router_10_14_req_in[0] = router_10_15_to_router_10_14_req; - assign router_10_14_req_in[1] = router_11_14_to_router_10_14_req; - assign router_10_14_req_in[2] = router_10_13_to_router_10_14_req; - assign router_10_14_req_in[3] = router_9_14_to_router_10_14_req; - assign router_10_14_req_in[4] = magia_tile_ni_10_14_to_router_10_14_req; - - assign router_10_14_to_router_10_15_rsp = router_10_14_rsp_out[0]; - assign router_10_14_to_router_11_14_rsp = router_10_14_rsp_out[1]; - assign router_10_14_to_router_10_13_rsp = router_10_14_rsp_out[2]; - assign router_10_14_to_router_9_14_rsp = router_10_14_rsp_out[3]; - assign router_10_14_to_magia_tile_ni_10_14_rsp = router_10_14_rsp_out[4]; - - assign router_10_14_to_router_10_15_req = router_10_14_req_out[0]; - assign router_10_14_to_router_11_14_req = router_10_14_req_out[1]; - assign router_10_14_to_router_10_13_req = router_10_14_req_out[2]; - assign router_10_14_to_router_9_14_req = router_10_14_req_out[3]; - assign router_10_14_to_magia_tile_ni_10_14_req = router_10_14_req_out[4]; - - assign router_10_14_rsp_in[0] = router_10_15_to_router_10_14_rsp; - assign router_10_14_rsp_in[1] = router_11_14_to_router_10_14_rsp; - assign router_10_14_rsp_in[2] = router_10_13_to_router_10_14_rsp; - assign router_10_14_rsp_in[3] = router_9_14_to_router_10_14_rsp; - assign router_10_14_rsp_in[4] = magia_tile_ni_10_14_to_router_10_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_14_req_in), - .floo_rsp_o (router_10_14_rsp_out), - .floo_req_o (router_10_14_req_out), - .floo_rsp_i (router_10_14_rsp_in) -); - - -floo_req_t [4:0] router_10_15_req_in; -floo_rsp_t [4:0] router_10_15_rsp_out; -floo_req_t [4:0] router_10_15_req_out; -floo_rsp_t [4:0] router_10_15_rsp_in; - - assign router_10_15_req_in[0] = '0; - assign router_10_15_req_in[1] = router_11_15_to_router_10_15_req; - assign router_10_15_req_in[2] = router_10_14_to_router_10_15_req; - assign router_10_15_req_in[3] = router_9_15_to_router_10_15_req; - assign router_10_15_req_in[4] = magia_tile_ni_10_15_to_router_10_15_req; - - assign router_10_15_to_router_11_15_rsp = router_10_15_rsp_out[1]; - assign router_10_15_to_router_10_14_rsp = router_10_15_rsp_out[2]; - assign router_10_15_to_router_9_15_rsp = router_10_15_rsp_out[3]; - assign router_10_15_to_magia_tile_ni_10_15_rsp = router_10_15_rsp_out[4]; - - assign router_10_15_to_router_11_15_req = router_10_15_req_out[1]; - assign router_10_15_to_router_10_14_req = router_10_15_req_out[2]; - assign router_10_15_to_router_9_15_req = router_10_15_req_out[3]; - assign router_10_15_to_magia_tile_ni_10_15_req = router_10_15_req_out[4]; - - assign router_10_15_rsp_in[0] = '0; - assign router_10_15_rsp_in[1] = router_11_15_to_router_10_15_rsp; - assign router_10_15_rsp_in[2] = router_10_14_to_router_10_15_rsp; - assign router_10_15_rsp_in[3] = router_9_15_to_router_10_15_rsp; - assign router_10_15_rsp_in[4] = magia_tile_ni_10_15_to_router_10_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_15_req_in), - .floo_rsp_o (router_10_15_rsp_out), - .floo_req_o (router_10_15_req_out), - .floo_rsp_i (router_10_15_rsp_in) -); - - -floo_req_t [4:0] router_11_0_req_in; -floo_rsp_t [4:0] router_11_0_rsp_out; -floo_req_t [4:0] router_11_0_req_out; -floo_rsp_t [4:0] router_11_0_rsp_in; - - assign router_11_0_req_in[0] = router_11_1_to_router_11_0_req; - assign router_11_0_req_in[1] = router_12_0_to_router_11_0_req; - assign router_11_0_req_in[2] = '0; - assign router_11_0_req_in[3] = router_10_0_to_router_11_0_req; - assign router_11_0_req_in[4] = magia_tile_ni_11_0_to_router_11_0_req; - - assign router_11_0_to_router_11_1_rsp = router_11_0_rsp_out[0]; - assign router_11_0_to_router_12_0_rsp = router_11_0_rsp_out[1]; - assign router_11_0_to_router_10_0_rsp = router_11_0_rsp_out[3]; - assign router_11_0_to_magia_tile_ni_11_0_rsp = router_11_0_rsp_out[4]; - - assign router_11_0_to_router_11_1_req = router_11_0_req_out[0]; - assign router_11_0_to_router_12_0_req = router_11_0_req_out[1]; - assign router_11_0_to_router_10_0_req = router_11_0_req_out[3]; - assign router_11_0_to_magia_tile_ni_11_0_req = router_11_0_req_out[4]; - - assign router_11_0_rsp_in[0] = router_11_1_to_router_11_0_rsp; - assign router_11_0_rsp_in[1] = router_12_0_to_router_11_0_rsp; - assign router_11_0_rsp_in[2] = '0; - assign router_11_0_rsp_in[3] = router_10_0_to_router_11_0_rsp; - assign router_11_0_rsp_in[4] = magia_tile_ni_11_0_to_router_11_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_0_req_in), - .floo_rsp_o (router_11_0_rsp_out), - .floo_req_o (router_11_0_req_out), - .floo_rsp_i (router_11_0_rsp_in) -); - - -floo_req_t [4:0] router_11_1_req_in; -floo_rsp_t [4:0] router_11_1_rsp_out; -floo_req_t [4:0] router_11_1_req_out; -floo_rsp_t [4:0] router_11_1_rsp_in; - - assign router_11_1_req_in[0] = router_11_2_to_router_11_1_req; - assign router_11_1_req_in[1] = router_12_1_to_router_11_1_req; - assign router_11_1_req_in[2] = router_11_0_to_router_11_1_req; - assign router_11_1_req_in[3] = router_10_1_to_router_11_1_req; - assign router_11_1_req_in[4] = magia_tile_ni_11_1_to_router_11_1_req; - - assign router_11_1_to_router_11_2_rsp = router_11_1_rsp_out[0]; - assign router_11_1_to_router_12_1_rsp = router_11_1_rsp_out[1]; - assign router_11_1_to_router_11_0_rsp = router_11_1_rsp_out[2]; - assign router_11_1_to_router_10_1_rsp = router_11_1_rsp_out[3]; - assign router_11_1_to_magia_tile_ni_11_1_rsp = router_11_1_rsp_out[4]; - - assign router_11_1_to_router_11_2_req = router_11_1_req_out[0]; - assign router_11_1_to_router_12_1_req = router_11_1_req_out[1]; - assign router_11_1_to_router_11_0_req = router_11_1_req_out[2]; - assign router_11_1_to_router_10_1_req = router_11_1_req_out[3]; - assign router_11_1_to_magia_tile_ni_11_1_req = router_11_1_req_out[4]; - - assign router_11_1_rsp_in[0] = router_11_2_to_router_11_1_rsp; - assign router_11_1_rsp_in[1] = router_12_1_to_router_11_1_rsp; - assign router_11_1_rsp_in[2] = router_11_0_to_router_11_1_rsp; - assign router_11_1_rsp_in[3] = router_10_1_to_router_11_1_rsp; - assign router_11_1_rsp_in[4] = magia_tile_ni_11_1_to_router_11_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_1_req_in), - .floo_rsp_o (router_11_1_rsp_out), - .floo_req_o (router_11_1_req_out), - .floo_rsp_i (router_11_1_rsp_in) -); - - -floo_req_t [4:0] router_11_2_req_in; -floo_rsp_t [4:0] router_11_2_rsp_out; -floo_req_t [4:0] router_11_2_req_out; -floo_rsp_t [4:0] router_11_2_rsp_in; - - assign router_11_2_req_in[0] = router_11_3_to_router_11_2_req; - assign router_11_2_req_in[1] = router_12_2_to_router_11_2_req; - assign router_11_2_req_in[2] = router_11_1_to_router_11_2_req; - assign router_11_2_req_in[3] = router_10_2_to_router_11_2_req; - assign router_11_2_req_in[4] = magia_tile_ni_11_2_to_router_11_2_req; - - assign router_11_2_to_router_11_3_rsp = router_11_2_rsp_out[0]; - assign router_11_2_to_router_12_2_rsp = router_11_2_rsp_out[1]; - assign router_11_2_to_router_11_1_rsp = router_11_2_rsp_out[2]; - assign router_11_2_to_router_10_2_rsp = router_11_2_rsp_out[3]; - assign router_11_2_to_magia_tile_ni_11_2_rsp = router_11_2_rsp_out[4]; - - assign router_11_2_to_router_11_3_req = router_11_2_req_out[0]; - assign router_11_2_to_router_12_2_req = router_11_2_req_out[1]; - assign router_11_2_to_router_11_1_req = router_11_2_req_out[2]; - assign router_11_2_to_router_10_2_req = router_11_2_req_out[3]; - assign router_11_2_to_magia_tile_ni_11_2_req = router_11_2_req_out[4]; - - assign router_11_2_rsp_in[0] = router_11_3_to_router_11_2_rsp; - assign router_11_2_rsp_in[1] = router_12_2_to_router_11_2_rsp; - assign router_11_2_rsp_in[2] = router_11_1_to_router_11_2_rsp; - assign router_11_2_rsp_in[3] = router_10_2_to_router_11_2_rsp; - assign router_11_2_rsp_in[4] = magia_tile_ni_11_2_to_router_11_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_2_req_in), - .floo_rsp_o (router_11_2_rsp_out), - .floo_req_o (router_11_2_req_out), - .floo_rsp_i (router_11_2_rsp_in) -); - - -floo_req_t [4:0] router_11_3_req_in; -floo_rsp_t [4:0] router_11_3_rsp_out; -floo_req_t [4:0] router_11_3_req_out; -floo_rsp_t [4:0] router_11_3_rsp_in; - - assign router_11_3_req_in[0] = router_11_4_to_router_11_3_req; - assign router_11_3_req_in[1] = router_12_3_to_router_11_3_req; - assign router_11_3_req_in[2] = router_11_2_to_router_11_3_req; - assign router_11_3_req_in[3] = router_10_3_to_router_11_3_req; - assign router_11_3_req_in[4] = magia_tile_ni_11_3_to_router_11_3_req; - - assign router_11_3_to_router_11_4_rsp = router_11_3_rsp_out[0]; - assign router_11_3_to_router_12_3_rsp = router_11_3_rsp_out[1]; - assign router_11_3_to_router_11_2_rsp = router_11_3_rsp_out[2]; - assign router_11_3_to_router_10_3_rsp = router_11_3_rsp_out[3]; - assign router_11_3_to_magia_tile_ni_11_3_rsp = router_11_3_rsp_out[4]; - - assign router_11_3_to_router_11_4_req = router_11_3_req_out[0]; - assign router_11_3_to_router_12_3_req = router_11_3_req_out[1]; - assign router_11_3_to_router_11_2_req = router_11_3_req_out[2]; - assign router_11_3_to_router_10_3_req = router_11_3_req_out[3]; - assign router_11_3_to_magia_tile_ni_11_3_req = router_11_3_req_out[4]; - - assign router_11_3_rsp_in[0] = router_11_4_to_router_11_3_rsp; - assign router_11_3_rsp_in[1] = router_12_3_to_router_11_3_rsp; - assign router_11_3_rsp_in[2] = router_11_2_to_router_11_3_rsp; - assign router_11_3_rsp_in[3] = router_10_3_to_router_11_3_rsp; - assign router_11_3_rsp_in[4] = magia_tile_ni_11_3_to_router_11_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_3_req_in), - .floo_rsp_o (router_11_3_rsp_out), - .floo_req_o (router_11_3_req_out), - .floo_rsp_i (router_11_3_rsp_in) -); - - -floo_req_t [4:0] router_11_4_req_in; -floo_rsp_t [4:0] router_11_4_rsp_out; -floo_req_t [4:0] router_11_4_req_out; -floo_rsp_t [4:0] router_11_4_rsp_in; - - assign router_11_4_req_in[0] = router_11_5_to_router_11_4_req; - assign router_11_4_req_in[1] = router_12_4_to_router_11_4_req; - assign router_11_4_req_in[2] = router_11_3_to_router_11_4_req; - assign router_11_4_req_in[3] = router_10_4_to_router_11_4_req; - assign router_11_4_req_in[4] = magia_tile_ni_11_4_to_router_11_4_req; - - assign router_11_4_to_router_11_5_rsp = router_11_4_rsp_out[0]; - assign router_11_4_to_router_12_4_rsp = router_11_4_rsp_out[1]; - assign router_11_4_to_router_11_3_rsp = router_11_4_rsp_out[2]; - assign router_11_4_to_router_10_4_rsp = router_11_4_rsp_out[3]; - assign router_11_4_to_magia_tile_ni_11_4_rsp = router_11_4_rsp_out[4]; - - assign router_11_4_to_router_11_5_req = router_11_4_req_out[0]; - assign router_11_4_to_router_12_4_req = router_11_4_req_out[1]; - assign router_11_4_to_router_11_3_req = router_11_4_req_out[2]; - assign router_11_4_to_router_10_4_req = router_11_4_req_out[3]; - assign router_11_4_to_magia_tile_ni_11_4_req = router_11_4_req_out[4]; - - assign router_11_4_rsp_in[0] = router_11_5_to_router_11_4_rsp; - assign router_11_4_rsp_in[1] = router_12_4_to_router_11_4_rsp; - assign router_11_4_rsp_in[2] = router_11_3_to_router_11_4_rsp; - assign router_11_4_rsp_in[3] = router_10_4_to_router_11_4_rsp; - assign router_11_4_rsp_in[4] = magia_tile_ni_11_4_to_router_11_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_4_req_in), - .floo_rsp_o (router_11_4_rsp_out), - .floo_req_o (router_11_4_req_out), - .floo_rsp_i (router_11_4_rsp_in) -); - - -floo_req_t [4:0] router_11_5_req_in; -floo_rsp_t [4:0] router_11_5_rsp_out; -floo_req_t [4:0] router_11_5_req_out; -floo_rsp_t [4:0] router_11_5_rsp_in; - - assign router_11_5_req_in[0] = router_11_6_to_router_11_5_req; - assign router_11_5_req_in[1] = router_12_5_to_router_11_5_req; - assign router_11_5_req_in[2] = router_11_4_to_router_11_5_req; - assign router_11_5_req_in[3] = router_10_5_to_router_11_5_req; - assign router_11_5_req_in[4] = magia_tile_ni_11_5_to_router_11_5_req; - - assign router_11_5_to_router_11_6_rsp = router_11_5_rsp_out[0]; - assign router_11_5_to_router_12_5_rsp = router_11_5_rsp_out[1]; - assign router_11_5_to_router_11_4_rsp = router_11_5_rsp_out[2]; - assign router_11_5_to_router_10_5_rsp = router_11_5_rsp_out[3]; - assign router_11_5_to_magia_tile_ni_11_5_rsp = router_11_5_rsp_out[4]; - - assign router_11_5_to_router_11_6_req = router_11_5_req_out[0]; - assign router_11_5_to_router_12_5_req = router_11_5_req_out[1]; - assign router_11_5_to_router_11_4_req = router_11_5_req_out[2]; - assign router_11_5_to_router_10_5_req = router_11_5_req_out[3]; - assign router_11_5_to_magia_tile_ni_11_5_req = router_11_5_req_out[4]; - - assign router_11_5_rsp_in[0] = router_11_6_to_router_11_5_rsp; - assign router_11_5_rsp_in[1] = router_12_5_to_router_11_5_rsp; - assign router_11_5_rsp_in[2] = router_11_4_to_router_11_5_rsp; - assign router_11_5_rsp_in[3] = router_10_5_to_router_11_5_rsp; - assign router_11_5_rsp_in[4] = magia_tile_ni_11_5_to_router_11_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_5_req_in), - .floo_rsp_o (router_11_5_rsp_out), - .floo_req_o (router_11_5_req_out), - .floo_rsp_i (router_11_5_rsp_in) -); - - -floo_req_t [4:0] router_11_6_req_in; -floo_rsp_t [4:0] router_11_6_rsp_out; -floo_req_t [4:0] router_11_6_req_out; -floo_rsp_t [4:0] router_11_6_rsp_in; - - assign router_11_6_req_in[0] = router_11_7_to_router_11_6_req; - assign router_11_6_req_in[1] = router_12_6_to_router_11_6_req; - assign router_11_6_req_in[2] = router_11_5_to_router_11_6_req; - assign router_11_6_req_in[3] = router_10_6_to_router_11_6_req; - assign router_11_6_req_in[4] = magia_tile_ni_11_6_to_router_11_6_req; - - assign router_11_6_to_router_11_7_rsp = router_11_6_rsp_out[0]; - assign router_11_6_to_router_12_6_rsp = router_11_6_rsp_out[1]; - assign router_11_6_to_router_11_5_rsp = router_11_6_rsp_out[2]; - assign router_11_6_to_router_10_6_rsp = router_11_6_rsp_out[3]; - assign router_11_6_to_magia_tile_ni_11_6_rsp = router_11_6_rsp_out[4]; - - assign router_11_6_to_router_11_7_req = router_11_6_req_out[0]; - assign router_11_6_to_router_12_6_req = router_11_6_req_out[1]; - assign router_11_6_to_router_11_5_req = router_11_6_req_out[2]; - assign router_11_6_to_router_10_6_req = router_11_6_req_out[3]; - assign router_11_6_to_magia_tile_ni_11_6_req = router_11_6_req_out[4]; - - assign router_11_6_rsp_in[0] = router_11_7_to_router_11_6_rsp; - assign router_11_6_rsp_in[1] = router_12_6_to_router_11_6_rsp; - assign router_11_6_rsp_in[2] = router_11_5_to_router_11_6_rsp; - assign router_11_6_rsp_in[3] = router_10_6_to_router_11_6_rsp; - assign router_11_6_rsp_in[4] = magia_tile_ni_11_6_to_router_11_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_6_req_in), - .floo_rsp_o (router_11_6_rsp_out), - .floo_req_o (router_11_6_req_out), - .floo_rsp_i (router_11_6_rsp_in) -); - - -floo_req_t [4:0] router_11_7_req_in; -floo_rsp_t [4:0] router_11_7_rsp_out; -floo_req_t [4:0] router_11_7_req_out; -floo_rsp_t [4:0] router_11_7_rsp_in; - - assign router_11_7_req_in[0] = router_11_8_to_router_11_7_req; - assign router_11_7_req_in[1] = router_12_7_to_router_11_7_req; - assign router_11_7_req_in[2] = router_11_6_to_router_11_7_req; - assign router_11_7_req_in[3] = router_10_7_to_router_11_7_req; - assign router_11_7_req_in[4] = magia_tile_ni_11_7_to_router_11_7_req; - - assign router_11_7_to_router_11_8_rsp = router_11_7_rsp_out[0]; - assign router_11_7_to_router_12_7_rsp = router_11_7_rsp_out[1]; - assign router_11_7_to_router_11_6_rsp = router_11_7_rsp_out[2]; - assign router_11_7_to_router_10_7_rsp = router_11_7_rsp_out[3]; - assign router_11_7_to_magia_tile_ni_11_7_rsp = router_11_7_rsp_out[4]; - - assign router_11_7_to_router_11_8_req = router_11_7_req_out[0]; - assign router_11_7_to_router_12_7_req = router_11_7_req_out[1]; - assign router_11_7_to_router_11_6_req = router_11_7_req_out[2]; - assign router_11_7_to_router_10_7_req = router_11_7_req_out[3]; - assign router_11_7_to_magia_tile_ni_11_7_req = router_11_7_req_out[4]; - - assign router_11_7_rsp_in[0] = router_11_8_to_router_11_7_rsp; - assign router_11_7_rsp_in[1] = router_12_7_to_router_11_7_rsp; - assign router_11_7_rsp_in[2] = router_11_6_to_router_11_7_rsp; - assign router_11_7_rsp_in[3] = router_10_7_to_router_11_7_rsp; - assign router_11_7_rsp_in[4] = magia_tile_ni_11_7_to_router_11_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_7_req_in), - .floo_rsp_o (router_11_7_rsp_out), - .floo_req_o (router_11_7_req_out), - .floo_rsp_i (router_11_7_rsp_in) -); - - -floo_req_t [4:0] router_11_8_req_in; -floo_rsp_t [4:0] router_11_8_rsp_out; -floo_req_t [4:0] router_11_8_req_out; -floo_rsp_t [4:0] router_11_8_rsp_in; - - assign router_11_8_req_in[0] = router_11_9_to_router_11_8_req; - assign router_11_8_req_in[1] = router_12_8_to_router_11_8_req; - assign router_11_8_req_in[2] = router_11_7_to_router_11_8_req; - assign router_11_8_req_in[3] = router_10_8_to_router_11_8_req; - assign router_11_8_req_in[4] = magia_tile_ni_11_8_to_router_11_8_req; - - assign router_11_8_to_router_11_9_rsp = router_11_8_rsp_out[0]; - assign router_11_8_to_router_12_8_rsp = router_11_8_rsp_out[1]; - assign router_11_8_to_router_11_7_rsp = router_11_8_rsp_out[2]; - assign router_11_8_to_router_10_8_rsp = router_11_8_rsp_out[3]; - assign router_11_8_to_magia_tile_ni_11_8_rsp = router_11_8_rsp_out[4]; - - assign router_11_8_to_router_11_9_req = router_11_8_req_out[0]; - assign router_11_8_to_router_12_8_req = router_11_8_req_out[1]; - assign router_11_8_to_router_11_7_req = router_11_8_req_out[2]; - assign router_11_8_to_router_10_8_req = router_11_8_req_out[3]; - assign router_11_8_to_magia_tile_ni_11_8_req = router_11_8_req_out[4]; - - assign router_11_8_rsp_in[0] = router_11_9_to_router_11_8_rsp; - assign router_11_8_rsp_in[1] = router_12_8_to_router_11_8_rsp; - assign router_11_8_rsp_in[2] = router_11_7_to_router_11_8_rsp; - assign router_11_8_rsp_in[3] = router_10_8_to_router_11_8_rsp; - assign router_11_8_rsp_in[4] = magia_tile_ni_11_8_to_router_11_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_8_req_in), - .floo_rsp_o (router_11_8_rsp_out), - .floo_req_o (router_11_8_req_out), - .floo_rsp_i (router_11_8_rsp_in) -); - - -floo_req_t [4:0] router_11_9_req_in; -floo_rsp_t [4:0] router_11_9_rsp_out; -floo_req_t [4:0] router_11_9_req_out; -floo_rsp_t [4:0] router_11_9_rsp_in; - - assign router_11_9_req_in[0] = router_11_10_to_router_11_9_req; - assign router_11_9_req_in[1] = router_12_9_to_router_11_9_req; - assign router_11_9_req_in[2] = router_11_8_to_router_11_9_req; - assign router_11_9_req_in[3] = router_10_9_to_router_11_9_req; - assign router_11_9_req_in[4] = magia_tile_ni_11_9_to_router_11_9_req; - - assign router_11_9_to_router_11_10_rsp = router_11_9_rsp_out[0]; - assign router_11_9_to_router_12_9_rsp = router_11_9_rsp_out[1]; - assign router_11_9_to_router_11_8_rsp = router_11_9_rsp_out[2]; - assign router_11_9_to_router_10_9_rsp = router_11_9_rsp_out[3]; - assign router_11_9_to_magia_tile_ni_11_9_rsp = router_11_9_rsp_out[4]; - - assign router_11_9_to_router_11_10_req = router_11_9_req_out[0]; - assign router_11_9_to_router_12_9_req = router_11_9_req_out[1]; - assign router_11_9_to_router_11_8_req = router_11_9_req_out[2]; - assign router_11_9_to_router_10_9_req = router_11_9_req_out[3]; - assign router_11_9_to_magia_tile_ni_11_9_req = router_11_9_req_out[4]; - - assign router_11_9_rsp_in[0] = router_11_10_to_router_11_9_rsp; - assign router_11_9_rsp_in[1] = router_12_9_to_router_11_9_rsp; - assign router_11_9_rsp_in[2] = router_11_8_to_router_11_9_rsp; - assign router_11_9_rsp_in[3] = router_10_9_to_router_11_9_rsp; - assign router_11_9_rsp_in[4] = magia_tile_ni_11_9_to_router_11_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_9_req_in), - .floo_rsp_o (router_11_9_rsp_out), - .floo_req_o (router_11_9_req_out), - .floo_rsp_i (router_11_9_rsp_in) -); - - -floo_req_t [4:0] router_11_10_req_in; -floo_rsp_t [4:0] router_11_10_rsp_out; -floo_req_t [4:0] router_11_10_req_out; -floo_rsp_t [4:0] router_11_10_rsp_in; - - assign router_11_10_req_in[0] = router_11_11_to_router_11_10_req; - assign router_11_10_req_in[1] = router_12_10_to_router_11_10_req; - assign router_11_10_req_in[2] = router_11_9_to_router_11_10_req; - assign router_11_10_req_in[3] = router_10_10_to_router_11_10_req; - assign router_11_10_req_in[4] = magia_tile_ni_11_10_to_router_11_10_req; - - assign router_11_10_to_router_11_11_rsp = router_11_10_rsp_out[0]; - assign router_11_10_to_router_12_10_rsp = router_11_10_rsp_out[1]; - assign router_11_10_to_router_11_9_rsp = router_11_10_rsp_out[2]; - assign router_11_10_to_router_10_10_rsp = router_11_10_rsp_out[3]; - assign router_11_10_to_magia_tile_ni_11_10_rsp = router_11_10_rsp_out[4]; - - assign router_11_10_to_router_11_11_req = router_11_10_req_out[0]; - assign router_11_10_to_router_12_10_req = router_11_10_req_out[1]; - assign router_11_10_to_router_11_9_req = router_11_10_req_out[2]; - assign router_11_10_to_router_10_10_req = router_11_10_req_out[3]; - assign router_11_10_to_magia_tile_ni_11_10_req = router_11_10_req_out[4]; - - assign router_11_10_rsp_in[0] = router_11_11_to_router_11_10_rsp; - assign router_11_10_rsp_in[1] = router_12_10_to_router_11_10_rsp; - assign router_11_10_rsp_in[2] = router_11_9_to_router_11_10_rsp; - assign router_11_10_rsp_in[3] = router_10_10_to_router_11_10_rsp; - assign router_11_10_rsp_in[4] = magia_tile_ni_11_10_to_router_11_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_10_req_in), - .floo_rsp_o (router_11_10_rsp_out), - .floo_req_o (router_11_10_req_out), - .floo_rsp_i (router_11_10_rsp_in) -); - - -floo_req_t [4:0] router_11_11_req_in; -floo_rsp_t [4:0] router_11_11_rsp_out; -floo_req_t [4:0] router_11_11_req_out; -floo_rsp_t [4:0] router_11_11_rsp_in; - - assign router_11_11_req_in[0] = router_11_12_to_router_11_11_req; - assign router_11_11_req_in[1] = router_12_11_to_router_11_11_req; - assign router_11_11_req_in[2] = router_11_10_to_router_11_11_req; - assign router_11_11_req_in[3] = router_10_11_to_router_11_11_req; - assign router_11_11_req_in[4] = magia_tile_ni_11_11_to_router_11_11_req; - - assign router_11_11_to_router_11_12_rsp = router_11_11_rsp_out[0]; - assign router_11_11_to_router_12_11_rsp = router_11_11_rsp_out[1]; - assign router_11_11_to_router_11_10_rsp = router_11_11_rsp_out[2]; - assign router_11_11_to_router_10_11_rsp = router_11_11_rsp_out[3]; - assign router_11_11_to_magia_tile_ni_11_11_rsp = router_11_11_rsp_out[4]; - - assign router_11_11_to_router_11_12_req = router_11_11_req_out[0]; - assign router_11_11_to_router_12_11_req = router_11_11_req_out[1]; - assign router_11_11_to_router_11_10_req = router_11_11_req_out[2]; - assign router_11_11_to_router_10_11_req = router_11_11_req_out[3]; - assign router_11_11_to_magia_tile_ni_11_11_req = router_11_11_req_out[4]; - - assign router_11_11_rsp_in[0] = router_11_12_to_router_11_11_rsp; - assign router_11_11_rsp_in[1] = router_12_11_to_router_11_11_rsp; - assign router_11_11_rsp_in[2] = router_11_10_to_router_11_11_rsp; - assign router_11_11_rsp_in[3] = router_10_11_to_router_11_11_rsp; - assign router_11_11_rsp_in[4] = magia_tile_ni_11_11_to_router_11_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_11_req_in), - .floo_rsp_o (router_11_11_rsp_out), - .floo_req_o (router_11_11_req_out), - .floo_rsp_i (router_11_11_rsp_in) -); - - -floo_req_t [4:0] router_11_12_req_in; -floo_rsp_t [4:0] router_11_12_rsp_out; -floo_req_t [4:0] router_11_12_req_out; -floo_rsp_t [4:0] router_11_12_rsp_in; - - assign router_11_12_req_in[0] = router_11_13_to_router_11_12_req; - assign router_11_12_req_in[1] = router_12_12_to_router_11_12_req; - assign router_11_12_req_in[2] = router_11_11_to_router_11_12_req; - assign router_11_12_req_in[3] = router_10_12_to_router_11_12_req; - assign router_11_12_req_in[4] = magia_tile_ni_11_12_to_router_11_12_req; - - assign router_11_12_to_router_11_13_rsp = router_11_12_rsp_out[0]; - assign router_11_12_to_router_12_12_rsp = router_11_12_rsp_out[1]; - assign router_11_12_to_router_11_11_rsp = router_11_12_rsp_out[2]; - assign router_11_12_to_router_10_12_rsp = router_11_12_rsp_out[3]; - assign router_11_12_to_magia_tile_ni_11_12_rsp = router_11_12_rsp_out[4]; - - assign router_11_12_to_router_11_13_req = router_11_12_req_out[0]; - assign router_11_12_to_router_12_12_req = router_11_12_req_out[1]; - assign router_11_12_to_router_11_11_req = router_11_12_req_out[2]; - assign router_11_12_to_router_10_12_req = router_11_12_req_out[3]; - assign router_11_12_to_magia_tile_ni_11_12_req = router_11_12_req_out[4]; - - assign router_11_12_rsp_in[0] = router_11_13_to_router_11_12_rsp; - assign router_11_12_rsp_in[1] = router_12_12_to_router_11_12_rsp; - assign router_11_12_rsp_in[2] = router_11_11_to_router_11_12_rsp; - assign router_11_12_rsp_in[3] = router_10_12_to_router_11_12_rsp; - assign router_11_12_rsp_in[4] = magia_tile_ni_11_12_to_router_11_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_12_req_in), - .floo_rsp_o (router_11_12_rsp_out), - .floo_req_o (router_11_12_req_out), - .floo_rsp_i (router_11_12_rsp_in) -); - - -floo_req_t [4:0] router_11_13_req_in; -floo_rsp_t [4:0] router_11_13_rsp_out; -floo_req_t [4:0] router_11_13_req_out; -floo_rsp_t [4:0] router_11_13_rsp_in; - - assign router_11_13_req_in[0] = router_11_14_to_router_11_13_req; - assign router_11_13_req_in[1] = router_12_13_to_router_11_13_req; - assign router_11_13_req_in[2] = router_11_12_to_router_11_13_req; - assign router_11_13_req_in[3] = router_10_13_to_router_11_13_req; - assign router_11_13_req_in[4] = magia_tile_ni_11_13_to_router_11_13_req; - - assign router_11_13_to_router_11_14_rsp = router_11_13_rsp_out[0]; - assign router_11_13_to_router_12_13_rsp = router_11_13_rsp_out[1]; - assign router_11_13_to_router_11_12_rsp = router_11_13_rsp_out[2]; - assign router_11_13_to_router_10_13_rsp = router_11_13_rsp_out[3]; - assign router_11_13_to_magia_tile_ni_11_13_rsp = router_11_13_rsp_out[4]; - - assign router_11_13_to_router_11_14_req = router_11_13_req_out[0]; - assign router_11_13_to_router_12_13_req = router_11_13_req_out[1]; - assign router_11_13_to_router_11_12_req = router_11_13_req_out[2]; - assign router_11_13_to_router_10_13_req = router_11_13_req_out[3]; - assign router_11_13_to_magia_tile_ni_11_13_req = router_11_13_req_out[4]; - - assign router_11_13_rsp_in[0] = router_11_14_to_router_11_13_rsp; - assign router_11_13_rsp_in[1] = router_12_13_to_router_11_13_rsp; - assign router_11_13_rsp_in[2] = router_11_12_to_router_11_13_rsp; - assign router_11_13_rsp_in[3] = router_10_13_to_router_11_13_rsp; - assign router_11_13_rsp_in[4] = magia_tile_ni_11_13_to_router_11_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_13_req_in), - .floo_rsp_o (router_11_13_rsp_out), - .floo_req_o (router_11_13_req_out), - .floo_rsp_i (router_11_13_rsp_in) -); - - -floo_req_t [4:0] router_11_14_req_in; -floo_rsp_t [4:0] router_11_14_rsp_out; -floo_req_t [4:0] router_11_14_req_out; -floo_rsp_t [4:0] router_11_14_rsp_in; - - assign router_11_14_req_in[0] = router_11_15_to_router_11_14_req; - assign router_11_14_req_in[1] = router_12_14_to_router_11_14_req; - assign router_11_14_req_in[2] = router_11_13_to_router_11_14_req; - assign router_11_14_req_in[3] = router_10_14_to_router_11_14_req; - assign router_11_14_req_in[4] = magia_tile_ni_11_14_to_router_11_14_req; - - assign router_11_14_to_router_11_15_rsp = router_11_14_rsp_out[0]; - assign router_11_14_to_router_12_14_rsp = router_11_14_rsp_out[1]; - assign router_11_14_to_router_11_13_rsp = router_11_14_rsp_out[2]; - assign router_11_14_to_router_10_14_rsp = router_11_14_rsp_out[3]; - assign router_11_14_to_magia_tile_ni_11_14_rsp = router_11_14_rsp_out[4]; - - assign router_11_14_to_router_11_15_req = router_11_14_req_out[0]; - assign router_11_14_to_router_12_14_req = router_11_14_req_out[1]; - assign router_11_14_to_router_11_13_req = router_11_14_req_out[2]; - assign router_11_14_to_router_10_14_req = router_11_14_req_out[3]; - assign router_11_14_to_magia_tile_ni_11_14_req = router_11_14_req_out[4]; - - assign router_11_14_rsp_in[0] = router_11_15_to_router_11_14_rsp; - assign router_11_14_rsp_in[1] = router_12_14_to_router_11_14_rsp; - assign router_11_14_rsp_in[2] = router_11_13_to_router_11_14_rsp; - assign router_11_14_rsp_in[3] = router_10_14_to_router_11_14_rsp; - assign router_11_14_rsp_in[4] = magia_tile_ni_11_14_to_router_11_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_14_req_in), - .floo_rsp_o (router_11_14_rsp_out), - .floo_req_o (router_11_14_req_out), - .floo_rsp_i (router_11_14_rsp_in) -); - - -floo_req_t [4:0] router_11_15_req_in; -floo_rsp_t [4:0] router_11_15_rsp_out; -floo_req_t [4:0] router_11_15_req_out; -floo_rsp_t [4:0] router_11_15_rsp_in; - - assign router_11_15_req_in[0] = '0; - assign router_11_15_req_in[1] = router_12_15_to_router_11_15_req; - assign router_11_15_req_in[2] = router_11_14_to_router_11_15_req; - assign router_11_15_req_in[3] = router_10_15_to_router_11_15_req; - assign router_11_15_req_in[4] = magia_tile_ni_11_15_to_router_11_15_req; - - assign router_11_15_to_router_12_15_rsp = router_11_15_rsp_out[1]; - assign router_11_15_to_router_11_14_rsp = router_11_15_rsp_out[2]; - assign router_11_15_to_router_10_15_rsp = router_11_15_rsp_out[3]; - assign router_11_15_to_magia_tile_ni_11_15_rsp = router_11_15_rsp_out[4]; - - assign router_11_15_to_router_12_15_req = router_11_15_req_out[1]; - assign router_11_15_to_router_11_14_req = router_11_15_req_out[2]; - assign router_11_15_to_router_10_15_req = router_11_15_req_out[3]; - assign router_11_15_to_magia_tile_ni_11_15_req = router_11_15_req_out[4]; - - assign router_11_15_rsp_in[0] = '0; - assign router_11_15_rsp_in[1] = router_12_15_to_router_11_15_rsp; - assign router_11_15_rsp_in[2] = router_11_14_to_router_11_15_rsp; - assign router_11_15_rsp_in[3] = router_10_15_to_router_11_15_rsp; - assign router_11_15_rsp_in[4] = magia_tile_ni_11_15_to_router_11_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_15_req_in), - .floo_rsp_o (router_11_15_rsp_out), - .floo_req_o (router_11_15_req_out), - .floo_rsp_i (router_11_15_rsp_in) -); - - -floo_req_t [4:0] router_12_0_req_in; -floo_rsp_t [4:0] router_12_0_rsp_out; -floo_req_t [4:0] router_12_0_req_out; -floo_rsp_t [4:0] router_12_0_rsp_in; - - assign router_12_0_req_in[0] = router_12_1_to_router_12_0_req; - assign router_12_0_req_in[1] = router_13_0_to_router_12_0_req; - assign router_12_0_req_in[2] = '0; - assign router_12_0_req_in[3] = router_11_0_to_router_12_0_req; - assign router_12_0_req_in[4] = magia_tile_ni_12_0_to_router_12_0_req; - - assign router_12_0_to_router_12_1_rsp = router_12_0_rsp_out[0]; - assign router_12_0_to_router_13_0_rsp = router_12_0_rsp_out[1]; - assign router_12_0_to_router_11_0_rsp = router_12_0_rsp_out[3]; - assign router_12_0_to_magia_tile_ni_12_0_rsp = router_12_0_rsp_out[4]; - - assign router_12_0_to_router_12_1_req = router_12_0_req_out[0]; - assign router_12_0_to_router_13_0_req = router_12_0_req_out[1]; - assign router_12_0_to_router_11_0_req = router_12_0_req_out[3]; - assign router_12_0_to_magia_tile_ni_12_0_req = router_12_0_req_out[4]; - - assign router_12_0_rsp_in[0] = router_12_1_to_router_12_0_rsp; - assign router_12_0_rsp_in[1] = router_13_0_to_router_12_0_rsp; - assign router_12_0_rsp_in[2] = '0; - assign router_12_0_rsp_in[3] = router_11_0_to_router_12_0_rsp; - assign router_12_0_rsp_in[4] = magia_tile_ni_12_0_to_router_12_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_0_req_in), - .floo_rsp_o (router_12_0_rsp_out), - .floo_req_o (router_12_0_req_out), - .floo_rsp_i (router_12_0_rsp_in) -); - - -floo_req_t [4:0] router_12_1_req_in; -floo_rsp_t [4:0] router_12_1_rsp_out; -floo_req_t [4:0] router_12_1_req_out; -floo_rsp_t [4:0] router_12_1_rsp_in; - - assign router_12_1_req_in[0] = router_12_2_to_router_12_1_req; - assign router_12_1_req_in[1] = router_13_1_to_router_12_1_req; - assign router_12_1_req_in[2] = router_12_0_to_router_12_1_req; - assign router_12_1_req_in[3] = router_11_1_to_router_12_1_req; - assign router_12_1_req_in[4] = magia_tile_ni_12_1_to_router_12_1_req; - - assign router_12_1_to_router_12_2_rsp = router_12_1_rsp_out[0]; - assign router_12_1_to_router_13_1_rsp = router_12_1_rsp_out[1]; - assign router_12_1_to_router_12_0_rsp = router_12_1_rsp_out[2]; - assign router_12_1_to_router_11_1_rsp = router_12_1_rsp_out[3]; - assign router_12_1_to_magia_tile_ni_12_1_rsp = router_12_1_rsp_out[4]; - - assign router_12_1_to_router_12_2_req = router_12_1_req_out[0]; - assign router_12_1_to_router_13_1_req = router_12_1_req_out[1]; - assign router_12_1_to_router_12_0_req = router_12_1_req_out[2]; - assign router_12_1_to_router_11_1_req = router_12_1_req_out[3]; - assign router_12_1_to_magia_tile_ni_12_1_req = router_12_1_req_out[4]; - - assign router_12_1_rsp_in[0] = router_12_2_to_router_12_1_rsp; - assign router_12_1_rsp_in[1] = router_13_1_to_router_12_1_rsp; - assign router_12_1_rsp_in[2] = router_12_0_to_router_12_1_rsp; - assign router_12_1_rsp_in[3] = router_11_1_to_router_12_1_rsp; - assign router_12_1_rsp_in[4] = magia_tile_ni_12_1_to_router_12_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_1_req_in), - .floo_rsp_o (router_12_1_rsp_out), - .floo_req_o (router_12_1_req_out), - .floo_rsp_i (router_12_1_rsp_in) -); - - -floo_req_t [4:0] router_12_2_req_in; -floo_rsp_t [4:0] router_12_2_rsp_out; -floo_req_t [4:0] router_12_2_req_out; -floo_rsp_t [4:0] router_12_2_rsp_in; - - assign router_12_2_req_in[0] = router_12_3_to_router_12_2_req; - assign router_12_2_req_in[1] = router_13_2_to_router_12_2_req; - assign router_12_2_req_in[2] = router_12_1_to_router_12_2_req; - assign router_12_2_req_in[3] = router_11_2_to_router_12_2_req; - assign router_12_2_req_in[4] = magia_tile_ni_12_2_to_router_12_2_req; - - assign router_12_2_to_router_12_3_rsp = router_12_2_rsp_out[0]; - assign router_12_2_to_router_13_2_rsp = router_12_2_rsp_out[1]; - assign router_12_2_to_router_12_1_rsp = router_12_2_rsp_out[2]; - assign router_12_2_to_router_11_2_rsp = router_12_2_rsp_out[3]; - assign router_12_2_to_magia_tile_ni_12_2_rsp = router_12_2_rsp_out[4]; - - assign router_12_2_to_router_12_3_req = router_12_2_req_out[0]; - assign router_12_2_to_router_13_2_req = router_12_2_req_out[1]; - assign router_12_2_to_router_12_1_req = router_12_2_req_out[2]; - assign router_12_2_to_router_11_2_req = router_12_2_req_out[3]; - assign router_12_2_to_magia_tile_ni_12_2_req = router_12_2_req_out[4]; - - assign router_12_2_rsp_in[0] = router_12_3_to_router_12_2_rsp; - assign router_12_2_rsp_in[1] = router_13_2_to_router_12_2_rsp; - assign router_12_2_rsp_in[2] = router_12_1_to_router_12_2_rsp; - assign router_12_2_rsp_in[3] = router_11_2_to_router_12_2_rsp; - assign router_12_2_rsp_in[4] = magia_tile_ni_12_2_to_router_12_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_2_req_in), - .floo_rsp_o (router_12_2_rsp_out), - .floo_req_o (router_12_2_req_out), - .floo_rsp_i (router_12_2_rsp_in) -); - - -floo_req_t [4:0] router_12_3_req_in; -floo_rsp_t [4:0] router_12_3_rsp_out; -floo_req_t [4:0] router_12_3_req_out; -floo_rsp_t [4:0] router_12_3_rsp_in; - - assign router_12_3_req_in[0] = router_12_4_to_router_12_3_req; - assign router_12_3_req_in[1] = router_13_3_to_router_12_3_req; - assign router_12_3_req_in[2] = router_12_2_to_router_12_3_req; - assign router_12_3_req_in[3] = router_11_3_to_router_12_3_req; - assign router_12_3_req_in[4] = magia_tile_ni_12_3_to_router_12_3_req; - - assign router_12_3_to_router_12_4_rsp = router_12_3_rsp_out[0]; - assign router_12_3_to_router_13_3_rsp = router_12_3_rsp_out[1]; - assign router_12_3_to_router_12_2_rsp = router_12_3_rsp_out[2]; - assign router_12_3_to_router_11_3_rsp = router_12_3_rsp_out[3]; - assign router_12_3_to_magia_tile_ni_12_3_rsp = router_12_3_rsp_out[4]; - - assign router_12_3_to_router_12_4_req = router_12_3_req_out[0]; - assign router_12_3_to_router_13_3_req = router_12_3_req_out[1]; - assign router_12_3_to_router_12_2_req = router_12_3_req_out[2]; - assign router_12_3_to_router_11_3_req = router_12_3_req_out[3]; - assign router_12_3_to_magia_tile_ni_12_3_req = router_12_3_req_out[4]; - - assign router_12_3_rsp_in[0] = router_12_4_to_router_12_3_rsp; - assign router_12_3_rsp_in[1] = router_13_3_to_router_12_3_rsp; - assign router_12_3_rsp_in[2] = router_12_2_to_router_12_3_rsp; - assign router_12_3_rsp_in[3] = router_11_3_to_router_12_3_rsp; - assign router_12_3_rsp_in[4] = magia_tile_ni_12_3_to_router_12_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_3_req_in), - .floo_rsp_o (router_12_3_rsp_out), - .floo_req_o (router_12_3_req_out), - .floo_rsp_i (router_12_3_rsp_in) -); - - -floo_req_t [4:0] router_12_4_req_in; -floo_rsp_t [4:0] router_12_4_rsp_out; -floo_req_t [4:0] router_12_4_req_out; -floo_rsp_t [4:0] router_12_4_rsp_in; - - assign router_12_4_req_in[0] = router_12_5_to_router_12_4_req; - assign router_12_4_req_in[1] = router_13_4_to_router_12_4_req; - assign router_12_4_req_in[2] = router_12_3_to_router_12_4_req; - assign router_12_4_req_in[3] = router_11_4_to_router_12_4_req; - assign router_12_4_req_in[4] = magia_tile_ni_12_4_to_router_12_4_req; - - assign router_12_4_to_router_12_5_rsp = router_12_4_rsp_out[0]; - assign router_12_4_to_router_13_4_rsp = router_12_4_rsp_out[1]; - assign router_12_4_to_router_12_3_rsp = router_12_4_rsp_out[2]; - assign router_12_4_to_router_11_4_rsp = router_12_4_rsp_out[3]; - assign router_12_4_to_magia_tile_ni_12_4_rsp = router_12_4_rsp_out[4]; - - assign router_12_4_to_router_12_5_req = router_12_4_req_out[0]; - assign router_12_4_to_router_13_4_req = router_12_4_req_out[1]; - assign router_12_4_to_router_12_3_req = router_12_4_req_out[2]; - assign router_12_4_to_router_11_4_req = router_12_4_req_out[3]; - assign router_12_4_to_magia_tile_ni_12_4_req = router_12_4_req_out[4]; - - assign router_12_4_rsp_in[0] = router_12_5_to_router_12_4_rsp; - assign router_12_4_rsp_in[1] = router_13_4_to_router_12_4_rsp; - assign router_12_4_rsp_in[2] = router_12_3_to_router_12_4_rsp; - assign router_12_4_rsp_in[3] = router_11_4_to_router_12_4_rsp; - assign router_12_4_rsp_in[4] = magia_tile_ni_12_4_to_router_12_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_4_req_in), - .floo_rsp_o (router_12_4_rsp_out), - .floo_req_o (router_12_4_req_out), - .floo_rsp_i (router_12_4_rsp_in) -); - - -floo_req_t [4:0] router_12_5_req_in; -floo_rsp_t [4:0] router_12_5_rsp_out; -floo_req_t [4:0] router_12_5_req_out; -floo_rsp_t [4:0] router_12_5_rsp_in; - - assign router_12_5_req_in[0] = router_12_6_to_router_12_5_req; - assign router_12_5_req_in[1] = router_13_5_to_router_12_5_req; - assign router_12_5_req_in[2] = router_12_4_to_router_12_5_req; - assign router_12_5_req_in[3] = router_11_5_to_router_12_5_req; - assign router_12_5_req_in[4] = magia_tile_ni_12_5_to_router_12_5_req; - - assign router_12_5_to_router_12_6_rsp = router_12_5_rsp_out[0]; - assign router_12_5_to_router_13_5_rsp = router_12_5_rsp_out[1]; - assign router_12_5_to_router_12_4_rsp = router_12_5_rsp_out[2]; - assign router_12_5_to_router_11_5_rsp = router_12_5_rsp_out[3]; - assign router_12_5_to_magia_tile_ni_12_5_rsp = router_12_5_rsp_out[4]; - - assign router_12_5_to_router_12_6_req = router_12_5_req_out[0]; - assign router_12_5_to_router_13_5_req = router_12_5_req_out[1]; - assign router_12_5_to_router_12_4_req = router_12_5_req_out[2]; - assign router_12_5_to_router_11_5_req = router_12_5_req_out[3]; - assign router_12_5_to_magia_tile_ni_12_5_req = router_12_5_req_out[4]; - - assign router_12_5_rsp_in[0] = router_12_6_to_router_12_5_rsp; - assign router_12_5_rsp_in[1] = router_13_5_to_router_12_5_rsp; - assign router_12_5_rsp_in[2] = router_12_4_to_router_12_5_rsp; - assign router_12_5_rsp_in[3] = router_11_5_to_router_12_5_rsp; - assign router_12_5_rsp_in[4] = magia_tile_ni_12_5_to_router_12_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_5_req_in), - .floo_rsp_o (router_12_5_rsp_out), - .floo_req_o (router_12_5_req_out), - .floo_rsp_i (router_12_5_rsp_in) -); - - -floo_req_t [4:0] router_12_6_req_in; -floo_rsp_t [4:0] router_12_6_rsp_out; -floo_req_t [4:0] router_12_6_req_out; -floo_rsp_t [4:0] router_12_6_rsp_in; - - assign router_12_6_req_in[0] = router_12_7_to_router_12_6_req; - assign router_12_6_req_in[1] = router_13_6_to_router_12_6_req; - assign router_12_6_req_in[2] = router_12_5_to_router_12_6_req; - assign router_12_6_req_in[3] = router_11_6_to_router_12_6_req; - assign router_12_6_req_in[4] = magia_tile_ni_12_6_to_router_12_6_req; - - assign router_12_6_to_router_12_7_rsp = router_12_6_rsp_out[0]; - assign router_12_6_to_router_13_6_rsp = router_12_6_rsp_out[1]; - assign router_12_6_to_router_12_5_rsp = router_12_6_rsp_out[2]; - assign router_12_6_to_router_11_6_rsp = router_12_6_rsp_out[3]; - assign router_12_6_to_magia_tile_ni_12_6_rsp = router_12_6_rsp_out[4]; - - assign router_12_6_to_router_12_7_req = router_12_6_req_out[0]; - assign router_12_6_to_router_13_6_req = router_12_6_req_out[1]; - assign router_12_6_to_router_12_5_req = router_12_6_req_out[2]; - assign router_12_6_to_router_11_6_req = router_12_6_req_out[3]; - assign router_12_6_to_magia_tile_ni_12_6_req = router_12_6_req_out[4]; - - assign router_12_6_rsp_in[0] = router_12_7_to_router_12_6_rsp; - assign router_12_6_rsp_in[1] = router_13_6_to_router_12_6_rsp; - assign router_12_6_rsp_in[2] = router_12_5_to_router_12_6_rsp; - assign router_12_6_rsp_in[3] = router_11_6_to_router_12_6_rsp; - assign router_12_6_rsp_in[4] = magia_tile_ni_12_6_to_router_12_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_6_req_in), - .floo_rsp_o (router_12_6_rsp_out), - .floo_req_o (router_12_6_req_out), - .floo_rsp_i (router_12_6_rsp_in) -); - - -floo_req_t [4:0] router_12_7_req_in; -floo_rsp_t [4:0] router_12_7_rsp_out; -floo_req_t [4:0] router_12_7_req_out; -floo_rsp_t [4:0] router_12_7_rsp_in; - - assign router_12_7_req_in[0] = router_12_8_to_router_12_7_req; - assign router_12_7_req_in[1] = router_13_7_to_router_12_7_req; - assign router_12_7_req_in[2] = router_12_6_to_router_12_7_req; - assign router_12_7_req_in[3] = router_11_7_to_router_12_7_req; - assign router_12_7_req_in[4] = magia_tile_ni_12_7_to_router_12_7_req; - - assign router_12_7_to_router_12_8_rsp = router_12_7_rsp_out[0]; - assign router_12_7_to_router_13_7_rsp = router_12_7_rsp_out[1]; - assign router_12_7_to_router_12_6_rsp = router_12_7_rsp_out[2]; - assign router_12_7_to_router_11_7_rsp = router_12_7_rsp_out[3]; - assign router_12_7_to_magia_tile_ni_12_7_rsp = router_12_7_rsp_out[4]; - - assign router_12_7_to_router_12_8_req = router_12_7_req_out[0]; - assign router_12_7_to_router_13_7_req = router_12_7_req_out[1]; - assign router_12_7_to_router_12_6_req = router_12_7_req_out[2]; - assign router_12_7_to_router_11_7_req = router_12_7_req_out[3]; - assign router_12_7_to_magia_tile_ni_12_7_req = router_12_7_req_out[4]; - - assign router_12_7_rsp_in[0] = router_12_8_to_router_12_7_rsp; - assign router_12_7_rsp_in[1] = router_13_7_to_router_12_7_rsp; - assign router_12_7_rsp_in[2] = router_12_6_to_router_12_7_rsp; - assign router_12_7_rsp_in[3] = router_11_7_to_router_12_7_rsp; - assign router_12_7_rsp_in[4] = magia_tile_ni_12_7_to_router_12_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_7_req_in), - .floo_rsp_o (router_12_7_rsp_out), - .floo_req_o (router_12_7_req_out), - .floo_rsp_i (router_12_7_rsp_in) -); - - -floo_req_t [4:0] router_12_8_req_in; -floo_rsp_t [4:0] router_12_8_rsp_out; -floo_req_t [4:0] router_12_8_req_out; -floo_rsp_t [4:0] router_12_8_rsp_in; - - assign router_12_8_req_in[0] = router_12_9_to_router_12_8_req; - assign router_12_8_req_in[1] = router_13_8_to_router_12_8_req; - assign router_12_8_req_in[2] = router_12_7_to_router_12_8_req; - assign router_12_8_req_in[3] = router_11_8_to_router_12_8_req; - assign router_12_8_req_in[4] = magia_tile_ni_12_8_to_router_12_8_req; - - assign router_12_8_to_router_12_9_rsp = router_12_8_rsp_out[0]; - assign router_12_8_to_router_13_8_rsp = router_12_8_rsp_out[1]; - assign router_12_8_to_router_12_7_rsp = router_12_8_rsp_out[2]; - assign router_12_8_to_router_11_8_rsp = router_12_8_rsp_out[3]; - assign router_12_8_to_magia_tile_ni_12_8_rsp = router_12_8_rsp_out[4]; - - assign router_12_8_to_router_12_9_req = router_12_8_req_out[0]; - assign router_12_8_to_router_13_8_req = router_12_8_req_out[1]; - assign router_12_8_to_router_12_7_req = router_12_8_req_out[2]; - assign router_12_8_to_router_11_8_req = router_12_8_req_out[3]; - assign router_12_8_to_magia_tile_ni_12_8_req = router_12_8_req_out[4]; - - assign router_12_8_rsp_in[0] = router_12_9_to_router_12_8_rsp; - assign router_12_8_rsp_in[1] = router_13_8_to_router_12_8_rsp; - assign router_12_8_rsp_in[2] = router_12_7_to_router_12_8_rsp; - assign router_12_8_rsp_in[3] = router_11_8_to_router_12_8_rsp; - assign router_12_8_rsp_in[4] = magia_tile_ni_12_8_to_router_12_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_8_req_in), - .floo_rsp_o (router_12_8_rsp_out), - .floo_req_o (router_12_8_req_out), - .floo_rsp_i (router_12_8_rsp_in) -); - - -floo_req_t [4:0] router_12_9_req_in; -floo_rsp_t [4:0] router_12_9_rsp_out; -floo_req_t [4:0] router_12_9_req_out; -floo_rsp_t [4:0] router_12_9_rsp_in; - - assign router_12_9_req_in[0] = router_12_10_to_router_12_9_req; - assign router_12_9_req_in[1] = router_13_9_to_router_12_9_req; - assign router_12_9_req_in[2] = router_12_8_to_router_12_9_req; - assign router_12_9_req_in[3] = router_11_9_to_router_12_9_req; - assign router_12_9_req_in[4] = magia_tile_ni_12_9_to_router_12_9_req; - - assign router_12_9_to_router_12_10_rsp = router_12_9_rsp_out[0]; - assign router_12_9_to_router_13_9_rsp = router_12_9_rsp_out[1]; - assign router_12_9_to_router_12_8_rsp = router_12_9_rsp_out[2]; - assign router_12_9_to_router_11_9_rsp = router_12_9_rsp_out[3]; - assign router_12_9_to_magia_tile_ni_12_9_rsp = router_12_9_rsp_out[4]; - - assign router_12_9_to_router_12_10_req = router_12_9_req_out[0]; - assign router_12_9_to_router_13_9_req = router_12_9_req_out[1]; - assign router_12_9_to_router_12_8_req = router_12_9_req_out[2]; - assign router_12_9_to_router_11_9_req = router_12_9_req_out[3]; - assign router_12_9_to_magia_tile_ni_12_9_req = router_12_9_req_out[4]; - - assign router_12_9_rsp_in[0] = router_12_10_to_router_12_9_rsp; - assign router_12_9_rsp_in[1] = router_13_9_to_router_12_9_rsp; - assign router_12_9_rsp_in[2] = router_12_8_to_router_12_9_rsp; - assign router_12_9_rsp_in[3] = router_11_9_to_router_12_9_rsp; - assign router_12_9_rsp_in[4] = magia_tile_ni_12_9_to_router_12_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_9_req_in), - .floo_rsp_o (router_12_9_rsp_out), - .floo_req_o (router_12_9_req_out), - .floo_rsp_i (router_12_9_rsp_in) -); - - -floo_req_t [4:0] router_12_10_req_in; -floo_rsp_t [4:0] router_12_10_rsp_out; -floo_req_t [4:0] router_12_10_req_out; -floo_rsp_t [4:0] router_12_10_rsp_in; - - assign router_12_10_req_in[0] = router_12_11_to_router_12_10_req; - assign router_12_10_req_in[1] = router_13_10_to_router_12_10_req; - assign router_12_10_req_in[2] = router_12_9_to_router_12_10_req; - assign router_12_10_req_in[3] = router_11_10_to_router_12_10_req; - assign router_12_10_req_in[4] = magia_tile_ni_12_10_to_router_12_10_req; - - assign router_12_10_to_router_12_11_rsp = router_12_10_rsp_out[0]; - assign router_12_10_to_router_13_10_rsp = router_12_10_rsp_out[1]; - assign router_12_10_to_router_12_9_rsp = router_12_10_rsp_out[2]; - assign router_12_10_to_router_11_10_rsp = router_12_10_rsp_out[3]; - assign router_12_10_to_magia_tile_ni_12_10_rsp = router_12_10_rsp_out[4]; - - assign router_12_10_to_router_12_11_req = router_12_10_req_out[0]; - assign router_12_10_to_router_13_10_req = router_12_10_req_out[1]; - assign router_12_10_to_router_12_9_req = router_12_10_req_out[2]; - assign router_12_10_to_router_11_10_req = router_12_10_req_out[3]; - assign router_12_10_to_magia_tile_ni_12_10_req = router_12_10_req_out[4]; - - assign router_12_10_rsp_in[0] = router_12_11_to_router_12_10_rsp; - assign router_12_10_rsp_in[1] = router_13_10_to_router_12_10_rsp; - assign router_12_10_rsp_in[2] = router_12_9_to_router_12_10_rsp; - assign router_12_10_rsp_in[3] = router_11_10_to_router_12_10_rsp; - assign router_12_10_rsp_in[4] = magia_tile_ni_12_10_to_router_12_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_10_req_in), - .floo_rsp_o (router_12_10_rsp_out), - .floo_req_o (router_12_10_req_out), - .floo_rsp_i (router_12_10_rsp_in) -); - - -floo_req_t [4:0] router_12_11_req_in; -floo_rsp_t [4:0] router_12_11_rsp_out; -floo_req_t [4:0] router_12_11_req_out; -floo_rsp_t [4:0] router_12_11_rsp_in; - - assign router_12_11_req_in[0] = router_12_12_to_router_12_11_req; - assign router_12_11_req_in[1] = router_13_11_to_router_12_11_req; - assign router_12_11_req_in[2] = router_12_10_to_router_12_11_req; - assign router_12_11_req_in[3] = router_11_11_to_router_12_11_req; - assign router_12_11_req_in[4] = magia_tile_ni_12_11_to_router_12_11_req; - - assign router_12_11_to_router_12_12_rsp = router_12_11_rsp_out[0]; - assign router_12_11_to_router_13_11_rsp = router_12_11_rsp_out[1]; - assign router_12_11_to_router_12_10_rsp = router_12_11_rsp_out[2]; - assign router_12_11_to_router_11_11_rsp = router_12_11_rsp_out[3]; - assign router_12_11_to_magia_tile_ni_12_11_rsp = router_12_11_rsp_out[4]; - - assign router_12_11_to_router_12_12_req = router_12_11_req_out[0]; - assign router_12_11_to_router_13_11_req = router_12_11_req_out[1]; - assign router_12_11_to_router_12_10_req = router_12_11_req_out[2]; - assign router_12_11_to_router_11_11_req = router_12_11_req_out[3]; - assign router_12_11_to_magia_tile_ni_12_11_req = router_12_11_req_out[4]; - - assign router_12_11_rsp_in[0] = router_12_12_to_router_12_11_rsp; - assign router_12_11_rsp_in[1] = router_13_11_to_router_12_11_rsp; - assign router_12_11_rsp_in[2] = router_12_10_to_router_12_11_rsp; - assign router_12_11_rsp_in[3] = router_11_11_to_router_12_11_rsp; - assign router_12_11_rsp_in[4] = magia_tile_ni_12_11_to_router_12_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_11_req_in), - .floo_rsp_o (router_12_11_rsp_out), - .floo_req_o (router_12_11_req_out), - .floo_rsp_i (router_12_11_rsp_in) -); - - -floo_req_t [4:0] router_12_12_req_in; -floo_rsp_t [4:0] router_12_12_rsp_out; -floo_req_t [4:0] router_12_12_req_out; -floo_rsp_t [4:0] router_12_12_rsp_in; - - assign router_12_12_req_in[0] = router_12_13_to_router_12_12_req; - assign router_12_12_req_in[1] = router_13_12_to_router_12_12_req; - assign router_12_12_req_in[2] = router_12_11_to_router_12_12_req; - assign router_12_12_req_in[3] = router_11_12_to_router_12_12_req; - assign router_12_12_req_in[4] = magia_tile_ni_12_12_to_router_12_12_req; - - assign router_12_12_to_router_12_13_rsp = router_12_12_rsp_out[0]; - assign router_12_12_to_router_13_12_rsp = router_12_12_rsp_out[1]; - assign router_12_12_to_router_12_11_rsp = router_12_12_rsp_out[2]; - assign router_12_12_to_router_11_12_rsp = router_12_12_rsp_out[3]; - assign router_12_12_to_magia_tile_ni_12_12_rsp = router_12_12_rsp_out[4]; - - assign router_12_12_to_router_12_13_req = router_12_12_req_out[0]; - assign router_12_12_to_router_13_12_req = router_12_12_req_out[1]; - assign router_12_12_to_router_12_11_req = router_12_12_req_out[2]; - assign router_12_12_to_router_11_12_req = router_12_12_req_out[3]; - assign router_12_12_to_magia_tile_ni_12_12_req = router_12_12_req_out[4]; - - assign router_12_12_rsp_in[0] = router_12_13_to_router_12_12_rsp; - assign router_12_12_rsp_in[1] = router_13_12_to_router_12_12_rsp; - assign router_12_12_rsp_in[2] = router_12_11_to_router_12_12_rsp; - assign router_12_12_rsp_in[3] = router_11_12_to_router_12_12_rsp; - assign router_12_12_rsp_in[4] = magia_tile_ni_12_12_to_router_12_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_12_req_in), - .floo_rsp_o (router_12_12_rsp_out), - .floo_req_o (router_12_12_req_out), - .floo_rsp_i (router_12_12_rsp_in) -); - - -floo_req_t [4:0] router_12_13_req_in; -floo_rsp_t [4:0] router_12_13_rsp_out; -floo_req_t [4:0] router_12_13_req_out; -floo_rsp_t [4:0] router_12_13_rsp_in; - - assign router_12_13_req_in[0] = router_12_14_to_router_12_13_req; - assign router_12_13_req_in[1] = router_13_13_to_router_12_13_req; - assign router_12_13_req_in[2] = router_12_12_to_router_12_13_req; - assign router_12_13_req_in[3] = router_11_13_to_router_12_13_req; - assign router_12_13_req_in[4] = magia_tile_ni_12_13_to_router_12_13_req; - - assign router_12_13_to_router_12_14_rsp = router_12_13_rsp_out[0]; - assign router_12_13_to_router_13_13_rsp = router_12_13_rsp_out[1]; - assign router_12_13_to_router_12_12_rsp = router_12_13_rsp_out[2]; - assign router_12_13_to_router_11_13_rsp = router_12_13_rsp_out[3]; - assign router_12_13_to_magia_tile_ni_12_13_rsp = router_12_13_rsp_out[4]; - - assign router_12_13_to_router_12_14_req = router_12_13_req_out[0]; - assign router_12_13_to_router_13_13_req = router_12_13_req_out[1]; - assign router_12_13_to_router_12_12_req = router_12_13_req_out[2]; - assign router_12_13_to_router_11_13_req = router_12_13_req_out[3]; - assign router_12_13_to_magia_tile_ni_12_13_req = router_12_13_req_out[4]; - - assign router_12_13_rsp_in[0] = router_12_14_to_router_12_13_rsp; - assign router_12_13_rsp_in[1] = router_13_13_to_router_12_13_rsp; - assign router_12_13_rsp_in[2] = router_12_12_to_router_12_13_rsp; - assign router_12_13_rsp_in[3] = router_11_13_to_router_12_13_rsp; - assign router_12_13_rsp_in[4] = magia_tile_ni_12_13_to_router_12_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_13_req_in), - .floo_rsp_o (router_12_13_rsp_out), - .floo_req_o (router_12_13_req_out), - .floo_rsp_i (router_12_13_rsp_in) -); - - -floo_req_t [4:0] router_12_14_req_in; -floo_rsp_t [4:0] router_12_14_rsp_out; -floo_req_t [4:0] router_12_14_req_out; -floo_rsp_t [4:0] router_12_14_rsp_in; - - assign router_12_14_req_in[0] = router_12_15_to_router_12_14_req; - assign router_12_14_req_in[1] = router_13_14_to_router_12_14_req; - assign router_12_14_req_in[2] = router_12_13_to_router_12_14_req; - assign router_12_14_req_in[3] = router_11_14_to_router_12_14_req; - assign router_12_14_req_in[4] = magia_tile_ni_12_14_to_router_12_14_req; - - assign router_12_14_to_router_12_15_rsp = router_12_14_rsp_out[0]; - assign router_12_14_to_router_13_14_rsp = router_12_14_rsp_out[1]; - assign router_12_14_to_router_12_13_rsp = router_12_14_rsp_out[2]; - assign router_12_14_to_router_11_14_rsp = router_12_14_rsp_out[3]; - assign router_12_14_to_magia_tile_ni_12_14_rsp = router_12_14_rsp_out[4]; - - assign router_12_14_to_router_12_15_req = router_12_14_req_out[0]; - assign router_12_14_to_router_13_14_req = router_12_14_req_out[1]; - assign router_12_14_to_router_12_13_req = router_12_14_req_out[2]; - assign router_12_14_to_router_11_14_req = router_12_14_req_out[3]; - assign router_12_14_to_magia_tile_ni_12_14_req = router_12_14_req_out[4]; - - assign router_12_14_rsp_in[0] = router_12_15_to_router_12_14_rsp; - assign router_12_14_rsp_in[1] = router_13_14_to_router_12_14_rsp; - assign router_12_14_rsp_in[2] = router_12_13_to_router_12_14_rsp; - assign router_12_14_rsp_in[3] = router_11_14_to_router_12_14_rsp; - assign router_12_14_rsp_in[4] = magia_tile_ni_12_14_to_router_12_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_14_req_in), - .floo_rsp_o (router_12_14_rsp_out), - .floo_req_o (router_12_14_req_out), - .floo_rsp_i (router_12_14_rsp_in) -); - - -floo_req_t [4:0] router_12_15_req_in; -floo_rsp_t [4:0] router_12_15_rsp_out; -floo_req_t [4:0] router_12_15_req_out; -floo_rsp_t [4:0] router_12_15_rsp_in; - - assign router_12_15_req_in[0] = '0; - assign router_12_15_req_in[1] = router_13_15_to_router_12_15_req; - assign router_12_15_req_in[2] = router_12_14_to_router_12_15_req; - assign router_12_15_req_in[3] = router_11_15_to_router_12_15_req; - assign router_12_15_req_in[4] = magia_tile_ni_12_15_to_router_12_15_req; - - assign router_12_15_to_router_13_15_rsp = router_12_15_rsp_out[1]; - assign router_12_15_to_router_12_14_rsp = router_12_15_rsp_out[2]; - assign router_12_15_to_router_11_15_rsp = router_12_15_rsp_out[3]; - assign router_12_15_to_magia_tile_ni_12_15_rsp = router_12_15_rsp_out[4]; - - assign router_12_15_to_router_13_15_req = router_12_15_req_out[1]; - assign router_12_15_to_router_12_14_req = router_12_15_req_out[2]; - assign router_12_15_to_router_11_15_req = router_12_15_req_out[3]; - assign router_12_15_to_magia_tile_ni_12_15_req = router_12_15_req_out[4]; - - assign router_12_15_rsp_in[0] = '0; - assign router_12_15_rsp_in[1] = router_13_15_to_router_12_15_rsp; - assign router_12_15_rsp_in[2] = router_12_14_to_router_12_15_rsp; - assign router_12_15_rsp_in[3] = router_11_15_to_router_12_15_rsp; - assign router_12_15_rsp_in[4] = magia_tile_ni_12_15_to_router_12_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_15_req_in), - .floo_rsp_o (router_12_15_rsp_out), - .floo_req_o (router_12_15_req_out), - .floo_rsp_i (router_12_15_rsp_in) -); - - -floo_req_t [4:0] router_13_0_req_in; -floo_rsp_t [4:0] router_13_0_rsp_out; -floo_req_t [4:0] router_13_0_req_out; -floo_rsp_t [4:0] router_13_0_rsp_in; - - assign router_13_0_req_in[0] = router_13_1_to_router_13_0_req; - assign router_13_0_req_in[1] = router_14_0_to_router_13_0_req; - assign router_13_0_req_in[2] = '0; - assign router_13_0_req_in[3] = router_12_0_to_router_13_0_req; - assign router_13_0_req_in[4] = magia_tile_ni_13_0_to_router_13_0_req; - - assign router_13_0_to_router_13_1_rsp = router_13_0_rsp_out[0]; - assign router_13_0_to_router_14_0_rsp = router_13_0_rsp_out[1]; - assign router_13_0_to_router_12_0_rsp = router_13_0_rsp_out[3]; - assign router_13_0_to_magia_tile_ni_13_0_rsp = router_13_0_rsp_out[4]; - - assign router_13_0_to_router_13_1_req = router_13_0_req_out[0]; - assign router_13_0_to_router_14_0_req = router_13_0_req_out[1]; - assign router_13_0_to_router_12_0_req = router_13_0_req_out[3]; - assign router_13_0_to_magia_tile_ni_13_0_req = router_13_0_req_out[4]; - - assign router_13_0_rsp_in[0] = router_13_1_to_router_13_0_rsp; - assign router_13_0_rsp_in[1] = router_14_0_to_router_13_0_rsp; - assign router_13_0_rsp_in[2] = '0; - assign router_13_0_rsp_in[3] = router_12_0_to_router_13_0_rsp; - assign router_13_0_rsp_in[4] = magia_tile_ni_13_0_to_router_13_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_0_req_in), - .floo_rsp_o (router_13_0_rsp_out), - .floo_req_o (router_13_0_req_out), - .floo_rsp_i (router_13_0_rsp_in) -); - - -floo_req_t [4:0] router_13_1_req_in; -floo_rsp_t [4:0] router_13_1_rsp_out; -floo_req_t [4:0] router_13_1_req_out; -floo_rsp_t [4:0] router_13_1_rsp_in; - - assign router_13_1_req_in[0] = router_13_2_to_router_13_1_req; - assign router_13_1_req_in[1] = router_14_1_to_router_13_1_req; - assign router_13_1_req_in[2] = router_13_0_to_router_13_1_req; - assign router_13_1_req_in[3] = router_12_1_to_router_13_1_req; - assign router_13_1_req_in[4] = magia_tile_ni_13_1_to_router_13_1_req; - - assign router_13_1_to_router_13_2_rsp = router_13_1_rsp_out[0]; - assign router_13_1_to_router_14_1_rsp = router_13_1_rsp_out[1]; - assign router_13_1_to_router_13_0_rsp = router_13_1_rsp_out[2]; - assign router_13_1_to_router_12_1_rsp = router_13_1_rsp_out[3]; - assign router_13_1_to_magia_tile_ni_13_1_rsp = router_13_1_rsp_out[4]; - - assign router_13_1_to_router_13_2_req = router_13_1_req_out[0]; - assign router_13_1_to_router_14_1_req = router_13_1_req_out[1]; - assign router_13_1_to_router_13_0_req = router_13_1_req_out[2]; - assign router_13_1_to_router_12_1_req = router_13_1_req_out[3]; - assign router_13_1_to_magia_tile_ni_13_1_req = router_13_1_req_out[4]; - - assign router_13_1_rsp_in[0] = router_13_2_to_router_13_1_rsp; - assign router_13_1_rsp_in[1] = router_14_1_to_router_13_1_rsp; - assign router_13_1_rsp_in[2] = router_13_0_to_router_13_1_rsp; - assign router_13_1_rsp_in[3] = router_12_1_to_router_13_1_rsp; - assign router_13_1_rsp_in[4] = magia_tile_ni_13_1_to_router_13_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_1_req_in), - .floo_rsp_o (router_13_1_rsp_out), - .floo_req_o (router_13_1_req_out), - .floo_rsp_i (router_13_1_rsp_in) -); - - -floo_req_t [4:0] router_13_2_req_in; -floo_rsp_t [4:0] router_13_2_rsp_out; -floo_req_t [4:0] router_13_2_req_out; -floo_rsp_t [4:0] router_13_2_rsp_in; - - assign router_13_2_req_in[0] = router_13_3_to_router_13_2_req; - assign router_13_2_req_in[1] = router_14_2_to_router_13_2_req; - assign router_13_2_req_in[2] = router_13_1_to_router_13_2_req; - assign router_13_2_req_in[3] = router_12_2_to_router_13_2_req; - assign router_13_2_req_in[4] = magia_tile_ni_13_2_to_router_13_2_req; - - assign router_13_2_to_router_13_3_rsp = router_13_2_rsp_out[0]; - assign router_13_2_to_router_14_2_rsp = router_13_2_rsp_out[1]; - assign router_13_2_to_router_13_1_rsp = router_13_2_rsp_out[2]; - assign router_13_2_to_router_12_2_rsp = router_13_2_rsp_out[3]; - assign router_13_2_to_magia_tile_ni_13_2_rsp = router_13_2_rsp_out[4]; - - assign router_13_2_to_router_13_3_req = router_13_2_req_out[0]; - assign router_13_2_to_router_14_2_req = router_13_2_req_out[1]; - assign router_13_2_to_router_13_1_req = router_13_2_req_out[2]; - assign router_13_2_to_router_12_2_req = router_13_2_req_out[3]; - assign router_13_2_to_magia_tile_ni_13_2_req = router_13_2_req_out[4]; - - assign router_13_2_rsp_in[0] = router_13_3_to_router_13_2_rsp; - assign router_13_2_rsp_in[1] = router_14_2_to_router_13_2_rsp; - assign router_13_2_rsp_in[2] = router_13_1_to_router_13_2_rsp; - assign router_13_2_rsp_in[3] = router_12_2_to_router_13_2_rsp; - assign router_13_2_rsp_in[4] = magia_tile_ni_13_2_to_router_13_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_2_req_in), - .floo_rsp_o (router_13_2_rsp_out), - .floo_req_o (router_13_2_req_out), - .floo_rsp_i (router_13_2_rsp_in) -); - - -floo_req_t [4:0] router_13_3_req_in; -floo_rsp_t [4:0] router_13_3_rsp_out; -floo_req_t [4:0] router_13_3_req_out; -floo_rsp_t [4:0] router_13_3_rsp_in; - - assign router_13_3_req_in[0] = router_13_4_to_router_13_3_req; - assign router_13_3_req_in[1] = router_14_3_to_router_13_3_req; - assign router_13_3_req_in[2] = router_13_2_to_router_13_3_req; - assign router_13_3_req_in[3] = router_12_3_to_router_13_3_req; - assign router_13_3_req_in[4] = magia_tile_ni_13_3_to_router_13_3_req; - - assign router_13_3_to_router_13_4_rsp = router_13_3_rsp_out[0]; - assign router_13_3_to_router_14_3_rsp = router_13_3_rsp_out[1]; - assign router_13_3_to_router_13_2_rsp = router_13_3_rsp_out[2]; - assign router_13_3_to_router_12_3_rsp = router_13_3_rsp_out[3]; - assign router_13_3_to_magia_tile_ni_13_3_rsp = router_13_3_rsp_out[4]; - - assign router_13_3_to_router_13_4_req = router_13_3_req_out[0]; - assign router_13_3_to_router_14_3_req = router_13_3_req_out[1]; - assign router_13_3_to_router_13_2_req = router_13_3_req_out[2]; - assign router_13_3_to_router_12_3_req = router_13_3_req_out[3]; - assign router_13_3_to_magia_tile_ni_13_3_req = router_13_3_req_out[4]; - - assign router_13_3_rsp_in[0] = router_13_4_to_router_13_3_rsp; - assign router_13_3_rsp_in[1] = router_14_3_to_router_13_3_rsp; - assign router_13_3_rsp_in[2] = router_13_2_to_router_13_3_rsp; - assign router_13_3_rsp_in[3] = router_12_3_to_router_13_3_rsp; - assign router_13_3_rsp_in[4] = magia_tile_ni_13_3_to_router_13_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_3_req_in), - .floo_rsp_o (router_13_3_rsp_out), - .floo_req_o (router_13_3_req_out), - .floo_rsp_i (router_13_3_rsp_in) -); - - -floo_req_t [4:0] router_13_4_req_in; -floo_rsp_t [4:0] router_13_4_rsp_out; -floo_req_t [4:0] router_13_4_req_out; -floo_rsp_t [4:0] router_13_4_rsp_in; - - assign router_13_4_req_in[0] = router_13_5_to_router_13_4_req; - assign router_13_4_req_in[1] = router_14_4_to_router_13_4_req; - assign router_13_4_req_in[2] = router_13_3_to_router_13_4_req; - assign router_13_4_req_in[3] = router_12_4_to_router_13_4_req; - assign router_13_4_req_in[4] = magia_tile_ni_13_4_to_router_13_4_req; - - assign router_13_4_to_router_13_5_rsp = router_13_4_rsp_out[0]; - assign router_13_4_to_router_14_4_rsp = router_13_4_rsp_out[1]; - assign router_13_4_to_router_13_3_rsp = router_13_4_rsp_out[2]; - assign router_13_4_to_router_12_4_rsp = router_13_4_rsp_out[3]; - assign router_13_4_to_magia_tile_ni_13_4_rsp = router_13_4_rsp_out[4]; - - assign router_13_4_to_router_13_5_req = router_13_4_req_out[0]; - assign router_13_4_to_router_14_4_req = router_13_4_req_out[1]; - assign router_13_4_to_router_13_3_req = router_13_4_req_out[2]; - assign router_13_4_to_router_12_4_req = router_13_4_req_out[3]; - assign router_13_4_to_magia_tile_ni_13_4_req = router_13_4_req_out[4]; - - assign router_13_4_rsp_in[0] = router_13_5_to_router_13_4_rsp; - assign router_13_4_rsp_in[1] = router_14_4_to_router_13_4_rsp; - assign router_13_4_rsp_in[2] = router_13_3_to_router_13_4_rsp; - assign router_13_4_rsp_in[3] = router_12_4_to_router_13_4_rsp; - assign router_13_4_rsp_in[4] = magia_tile_ni_13_4_to_router_13_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_4_req_in), - .floo_rsp_o (router_13_4_rsp_out), - .floo_req_o (router_13_4_req_out), - .floo_rsp_i (router_13_4_rsp_in) -); - - -floo_req_t [4:0] router_13_5_req_in; -floo_rsp_t [4:0] router_13_5_rsp_out; -floo_req_t [4:0] router_13_5_req_out; -floo_rsp_t [4:0] router_13_5_rsp_in; - - assign router_13_5_req_in[0] = router_13_6_to_router_13_5_req; - assign router_13_5_req_in[1] = router_14_5_to_router_13_5_req; - assign router_13_5_req_in[2] = router_13_4_to_router_13_5_req; - assign router_13_5_req_in[3] = router_12_5_to_router_13_5_req; - assign router_13_5_req_in[4] = magia_tile_ni_13_5_to_router_13_5_req; - - assign router_13_5_to_router_13_6_rsp = router_13_5_rsp_out[0]; - assign router_13_5_to_router_14_5_rsp = router_13_5_rsp_out[1]; - assign router_13_5_to_router_13_4_rsp = router_13_5_rsp_out[2]; - assign router_13_5_to_router_12_5_rsp = router_13_5_rsp_out[3]; - assign router_13_5_to_magia_tile_ni_13_5_rsp = router_13_5_rsp_out[4]; - - assign router_13_5_to_router_13_6_req = router_13_5_req_out[0]; - assign router_13_5_to_router_14_5_req = router_13_5_req_out[1]; - assign router_13_5_to_router_13_4_req = router_13_5_req_out[2]; - assign router_13_5_to_router_12_5_req = router_13_5_req_out[3]; - assign router_13_5_to_magia_tile_ni_13_5_req = router_13_5_req_out[4]; - - assign router_13_5_rsp_in[0] = router_13_6_to_router_13_5_rsp; - assign router_13_5_rsp_in[1] = router_14_5_to_router_13_5_rsp; - assign router_13_5_rsp_in[2] = router_13_4_to_router_13_5_rsp; - assign router_13_5_rsp_in[3] = router_12_5_to_router_13_5_rsp; - assign router_13_5_rsp_in[4] = magia_tile_ni_13_5_to_router_13_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_5_req_in), - .floo_rsp_o (router_13_5_rsp_out), - .floo_req_o (router_13_5_req_out), - .floo_rsp_i (router_13_5_rsp_in) -); - - -floo_req_t [4:0] router_13_6_req_in; -floo_rsp_t [4:0] router_13_6_rsp_out; -floo_req_t [4:0] router_13_6_req_out; -floo_rsp_t [4:0] router_13_6_rsp_in; - - assign router_13_6_req_in[0] = router_13_7_to_router_13_6_req; - assign router_13_6_req_in[1] = router_14_6_to_router_13_6_req; - assign router_13_6_req_in[2] = router_13_5_to_router_13_6_req; - assign router_13_6_req_in[3] = router_12_6_to_router_13_6_req; - assign router_13_6_req_in[4] = magia_tile_ni_13_6_to_router_13_6_req; - - assign router_13_6_to_router_13_7_rsp = router_13_6_rsp_out[0]; - assign router_13_6_to_router_14_6_rsp = router_13_6_rsp_out[1]; - assign router_13_6_to_router_13_5_rsp = router_13_6_rsp_out[2]; - assign router_13_6_to_router_12_6_rsp = router_13_6_rsp_out[3]; - assign router_13_6_to_magia_tile_ni_13_6_rsp = router_13_6_rsp_out[4]; - - assign router_13_6_to_router_13_7_req = router_13_6_req_out[0]; - assign router_13_6_to_router_14_6_req = router_13_6_req_out[1]; - assign router_13_6_to_router_13_5_req = router_13_6_req_out[2]; - assign router_13_6_to_router_12_6_req = router_13_6_req_out[3]; - assign router_13_6_to_magia_tile_ni_13_6_req = router_13_6_req_out[4]; - - assign router_13_6_rsp_in[0] = router_13_7_to_router_13_6_rsp; - assign router_13_6_rsp_in[1] = router_14_6_to_router_13_6_rsp; - assign router_13_6_rsp_in[2] = router_13_5_to_router_13_6_rsp; - assign router_13_6_rsp_in[3] = router_12_6_to_router_13_6_rsp; - assign router_13_6_rsp_in[4] = magia_tile_ni_13_6_to_router_13_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_6_req_in), - .floo_rsp_o (router_13_6_rsp_out), - .floo_req_o (router_13_6_req_out), - .floo_rsp_i (router_13_6_rsp_in) -); - - -floo_req_t [4:0] router_13_7_req_in; -floo_rsp_t [4:0] router_13_7_rsp_out; -floo_req_t [4:0] router_13_7_req_out; -floo_rsp_t [4:0] router_13_7_rsp_in; - - assign router_13_7_req_in[0] = router_13_8_to_router_13_7_req; - assign router_13_7_req_in[1] = router_14_7_to_router_13_7_req; - assign router_13_7_req_in[2] = router_13_6_to_router_13_7_req; - assign router_13_7_req_in[3] = router_12_7_to_router_13_7_req; - assign router_13_7_req_in[4] = magia_tile_ni_13_7_to_router_13_7_req; - - assign router_13_7_to_router_13_8_rsp = router_13_7_rsp_out[0]; - assign router_13_7_to_router_14_7_rsp = router_13_7_rsp_out[1]; - assign router_13_7_to_router_13_6_rsp = router_13_7_rsp_out[2]; - assign router_13_7_to_router_12_7_rsp = router_13_7_rsp_out[3]; - assign router_13_7_to_magia_tile_ni_13_7_rsp = router_13_7_rsp_out[4]; - - assign router_13_7_to_router_13_8_req = router_13_7_req_out[0]; - assign router_13_7_to_router_14_7_req = router_13_7_req_out[1]; - assign router_13_7_to_router_13_6_req = router_13_7_req_out[2]; - assign router_13_7_to_router_12_7_req = router_13_7_req_out[3]; - assign router_13_7_to_magia_tile_ni_13_7_req = router_13_7_req_out[4]; - - assign router_13_7_rsp_in[0] = router_13_8_to_router_13_7_rsp; - assign router_13_7_rsp_in[1] = router_14_7_to_router_13_7_rsp; - assign router_13_7_rsp_in[2] = router_13_6_to_router_13_7_rsp; - assign router_13_7_rsp_in[3] = router_12_7_to_router_13_7_rsp; - assign router_13_7_rsp_in[4] = magia_tile_ni_13_7_to_router_13_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_7_req_in), - .floo_rsp_o (router_13_7_rsp_out), - .floo_req_o (router_13_7_req_out), - .floo_rsp_i (router_13_7_rsp_in) -); - - -floo_req_t [4:0] router_13_8_req_in; -floo_rsp_t [4:0] router_13_8_rsp_out; -floo_req_t [4:0] router_13_8_req_out; -floo_rsp_t [4:0] router_13_8_rsp_in; - - assign router_13_8_req_in[0] = router_13_9_to_router_13_8_req; - assign router_13_8_req_in[1] = router_14_8_to_router_13_8_req; - assign router_13_8_req_in[2] = router_13_7_to_router_13_8_req; - assign router_13_8_req_in[3] = router_12_8_to_router_13_8_req; - assign router_13_8_req_in[4] = magia_tile_ni_13_8_to_router_13_8_req; - - assign router_13_8_to_router_13_9_rsp = router_13_8_rsp_out[0]; - assign router_13_8_to_router_14_8_rsp = router_13_8_rsp_out[1]; - assign router_13_8_to_router_13_7_rsp = router_13_8_rsp_out[2]; - assign router_13_8_to_router_12_8_rsp = router_13_8_rsp_out[3]; - assign router_13_8_to_magia_tile_ni_13_8_rsp = router_13_8_rsp_out[4]; - - assign router_13_8_to_router_13_9_req = router_13_8_req_out[0]; - assign router_13_8_to_router_14_8_req = router_13_8_req_out[1]; - assign router_13_8_to_router_13_7_req = router_13_8_req_out[2]; - assign router_13_8_to_router_12_8_req = router_13_8_req_out[3]; - assign router_13_8_to_magia_tile_ni_13_8_req = router_13_8_req_out[4]; - - assign router_13_8_rsp_in[0] = router_13_9_to_router_13_8_rsp; - assign router_13_8_rsp_in[1] = router_14_8_to_router_13_8_rsp; - assign router_13_8_rsp_in[2] = router_13_7_to_router_13_8_rsp; - assign router_13_8_rsp_in[3] = router_12_8_to_router_13_8_rsp; - assign router_13_8_rsp_in[4] = magia_tile_ni_13_8_to_router_13_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_8_req_in), - .floo_rsp_o (router_13_8_rsp_out), - .floo_req_o (router_13_8_req_out), - .floo_rsp_i (router_13_8_rsp_in) -); - - -floo_req_t [4:0] router_13_9_req_in; -floo_rsp_t [4:0] router_13_9_rsp_out; -floo_req_t [4:0] router_13_9_req_out; -floo_rsp_t [4:0] router_13_9_rsp_in; - - assign router_13_9_req_in[0] = router_13_10_to_router_13_9_req; - assign router_13_9_req_in[1] = router_14_9_to_router_13_9_req; - assign router_13_9_req_in[2] = router_13_8_to_router_13_9_req; - assign router_13_9_req_in[3] = router_12_9_to_router_13_9_req; - assign router_13_9_req_in[4] = magia_tile_ni_13_9_to_router_13_9_req; - - assign router_13_9_to_router_13_10_rsp = router_13_9_rsp_out[0]; - assign router_13_9_to_router_14_9_rsp = router_13_9_rsp_out[1]; - assign router_13_9_to_router_13_8_rsp = router_13_9_rsp_out[2]; - assign router_13_9_to_router_12_9_rsp = router_13_9_rsp_out[3]; - assign router_13_9_to_magia_tile_ni_13_9_rsp = router_13_9_rsp_out[4]; - - assign router_13_9_to_router_13_10_req = router_13_9_req_out[0]; - assign router_13_9_to_router_14_9_req = router_13_9_req_out[1]; - assign router_13_9_to_router_13_8_req = router_13_9_req_out[2]; - assign router_13_9_to_router_12_9_req = router_13_9_req_out[3]; - assign router_13_9_to_magia_tile_ni_13_9_req = router_13_9_req_out[4]; - - assign router_13_9_rsp_in[0] = router_13_10_to_router_13_9_rsp; - assign router_13_9_rsp_in[1] = router_14_9_to_router_13_9_rsp; - assign router_13_9_rsp_in[2] = router_13_8_to_router_13_9_rsp; - assign router_13_9_rsp_in[3] = router_12_9_to_router_13_9_rsp; - assign router_13_9_rsp_in[4] = magia_tile_ni_13_9_to_router_13_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_9_req_in), - .floo_rsp_o (router_13_9_rsp_out), - .floo_req_o (router_13_9_req_out), - .floo_rsp_i (router_13_9_rsp_in) -); - - -floo_req_t [4:0] router_13_10_req_in; -floo_rsp_t [4:0] router_13_10_rsp_out; -floo_req_t [4:0] router_13_10_req_out; -floo_rsp_t [4:0] router_13_10_rsp_in; - - assign router_13_10_req_in[0] = router_13_11_to_router_13_10_req; - assign router_13_10_req_in[1] = router_14_10_to_router_13_10_req; - assign router_13_10_req_in[2] = router_13_9_to_router_13_10_req; - assign router_13_10_req_in[3] = router_12_10_to_router_13_10_req; - assign router_13_10_req_in[4] = magia_tile_ni_13_10_to_router_13_10_req; - - assign router_13_10_to_router_13_11_rsp = router_13_10_rsp_out[0]; - assign router_13_10_to_router_14_10_rsp = router_13_10_rsp_out[1]; - assign router_13_10_to_router_13_9_rsp = router_13_10_rsp_out[2]; - assign router_13_10_to_router_12_10_rsp = router_13_10_rsp_out[3]; - assign router_13_10_to_magia_tile_ni_13_10_rsp = router_13_10_rsp_out[4]; - - assign router_13_10_to_router_13_11_req = router_13_10_req_out[0]; - assign router_13_10_to_router_14_10_req = router_13_10_req_out[1]; - assign router_13_10_to_router_13_9_req = router_13_10_req_out[2]; - assign router_13_10_to_router_12_10_req = router_13_10_req_out[3]; - assign router_13_10_to_magia_tile_ni_13_10_req = router_13_10_req_out[4]; - - assign router_13_10_rsp_in[0] = router_13_11_to_router_13_10_rsp; - assign router_13_10_rsp_in[1] = router_14_10_to_router_13_10_rsp; - assign router_13_10_rsp_in[2] = router_13_9_to_router_13_10_rsp; - assign router_13_10_rsp_in[3] = router_12_10_to_router_13_10_rsp; - assign router_13_10_rsp_in[4] = magia_tile_ni_13_10_to_router_13_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_10_req_in), - .floo_rsp_o (router_13_10_rsp_out), - .floo_req_o (router_13_10_req_out), - .floo_rsp_i (router_13_10_rsp_in) -); - - -floo_req_t [4:0] router_13_11_req_in; -floo_rsp_t [4:0] router_13_11_rsp_out; -floo_req_t [4:0] router_13_11_req_out; -floo_rsp_t [4:0] router_13_11_rsp_in; - - assign router_13_11_req_in[0] = router_13_12_to_router_13_11_req; - assign router_13_11_req_in[1] = router_14_11_to_router_13_11_req; - assign router_13_11_req_in[2] = router_13_10_to_router_13_11_req; - assign router_13_11_req_in[3] = router_12_11_to_router_13_11_req; - assign router_13_11_req_in[4] = magia_tile_ni_13_11_to_router_13_11_req; - - assign router_13_11_to_router_13_12_rsp = router_13_11_rsp_out[0]; - assign router_13_11_to_router_14_11_rsp = router_13_11_rsp_out[1]; - assign router_13_11_to_router_13_10_rsp = router_13_11_rsp_out[2]; - assign router_13_11_to_router_12_11_rsp = router_13_11_rsp_out[3]; - assign router_13_11_to_magia_tile_ni_13_11_rsp = router_13_11_rsp_out[4]; - - assign router_13_11_to_router_13_12_req = router_13_11_req_out[0]; - assign router_13_11_to_router_14_11_req = router_13_11_req_out[1]; - assign router_13_11_to_router_13_10_req = router_13_11_req_out[2]; - assign router_13_11_to_router_12_11_req = router_13_11_req_out[3]; - assign router_13_11_to_magia_tile_ni_13_11_req = router_13_11_req_out[4]; - - assign router_13_11_rsp_in[0] = router_13_12_to_router_13_11_rsp; - assign router_13_11_rsp_in[1] = router_14_11_to_router_13_11_rsp; - assign router_13_11_rsp_in[2] = router_13_10_to_router_13_11_rsp; - assign router_13_11_rsp_in[3] = router_12_11_to_router_13_11_rsp; - assign router_13_11_rsp_in[4] = magia_tile_ni_13_11_to_router_13_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_11_req_in), - .floo_rsp_o (router_13_11_rsp_out), - .floo_req_o (router_13_11_req_out), - .floo_rsp_i (router_13_11_rsp_in) -); - - -floo_req_t [4:0] router_13_12_req_in; -floo_rsp_t [4:0] router_13_12_rsp_out; -floo_req_t [4:0] router_13_12_req_out; -floo_rsp_t [4:0] router_13_12_rsp_in; - - assign router_13_12_req_in[0] = router_13_13_to_router_13_12_req; - assign router_13_12_req_in[1] = router_14_12_to_router_13_12_req; - assign router_13_12_req_in[2] = router_13_11_to_router_13_12_req; - assign router_13_12_req_in[3] = router_12_12_to_router_13_12_req; - assign router_13_12_req_in[4] = magia_tile_ni_13_12_to_router_13_12_req; - - assign router_13_12_to_router_13_13_rsp = router_13_12_rsp_out[0]; - assign router_13_12_to_router_14_12_rsp = router_13_12_rsp_out[1]; - assign router_13_12_to_router_13_11_rsp = router_13_12_rsp_out[2]; - assign router_13_12_to_router_12_12_rsp = router_13_12_rsp_out[3]; - assign router_13_12_to_magia_tile_ni_13_12_rsp = router_13_12_rsp_out[4]; - - assign router_13_12_to_router_13_13_req = router_13_12_req_out[0]; - assign router_13_12_to_router_14_12_req = router_13_12_req_out[1]; - assign router_13_12_to_router_13_11_req = router_13_12_req_out[2]; - assign router_13_12_to_router_12_12_req = router_13_12_req_out[3]; - assign router_13_12_to_magia_tile_ni_13_12_req = router_13_12_req_out[4]; - - assign router_13_12_rsp_in[0] = router_13_13_to_router_13_12_rsp; - assign router_13_12_rsp_in[1] = router_14_12_to_router_13_12_rsp; - assign router_13_12_rsp_in[2] = router_13_11_to_router_13_12_rsp; - assign router_13_12_rsp_in[3] = router_12_12_to_router_13_12_rsp; - assign router_13_12_rsp_in[4] = magia_tile_ni_13_12_to_router_13_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_12_req_in), - .floo_rsp_o (router_13_12_rsp_out), - .floo_req_o (router_13_12_req_out), - .floo_rsp_i (router_13_12_rsp_in) -); - - -floo_req_t [4:0] router_13_13_req_in; -floo_rsp_t [4:0] router_13_13_rsp_out; -floo_req_t [4:0] router_13_13_req_out; -floo_rsp_t [4:0] router_13_13_rsp_in; - - assign router_13_13_req_in[0] = router_13_14_to_router_13_13_req; - assign router_13_13_req_in[1] = router_14_13_to_router_13_13_req; - assign router_13_13_req_in[2] = router_13_12_to_router_13_13_req; - assign router_13_13_req_in[3] = router_12_13_to_router_13_13_req; - assign router_13_13_req_in[4] = magia_tile_ni_13_13_to_router_13_13_req; - - assign router_13_13_to_router_13_14_rsp = router_13_13_rsp_out[0]; - assign router_13_13_to_router_14_13_rsp = router_13_13_rsp_out[1]; - assign router_13_13_to_router_13_12_rsp = router_13_13_rsp_out[2]; - assign router_13_13_to_router_12_13_rsp = router_13_13_rsp_out[3]; - assign router_13_13_to_magia_tile_ni_13_13_rsp = router_13_13_rsp_out[4]; - - assign router_13_13_to_router_13_14_req = router_13_13_req_out[0]; - assign router_13_13_to_router_14_13_req = router_13_13_req_out[1]; - assign router_13_13_to_router_13_12_req = router_13_13_req_out[2]; - assign router_13_13_to_router_12_13_req = router_13_13_req_out[3]; - assign router_13_13_to_magia_tile_ni_13_13_req = router_13_13_req_out[4]; - - assign router_13_13_rsp_in[0] = router_13_14_to_router_13_13_rsp; - assign router_13_13_rsp_in[1] = router_14_13_to_router_13_13_rsp; - assign router_13_13_rsp_in[2] = router_13_12_to_router_13_13_rsp; - assign router_13_13_rsp_in[3] = router_12_13_to_router_13_13_rsp; - assign router_13_13_rsp_in[4] = magia_tile_ni_13_13_to_router_13_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_13_req_in), - .floo_rsp_o (router_13_13_rsp_out), - .floo_req_o (router_13_13_req_out), - .floo_rsp_i (router_13_13_rsp_in) -); - - -floo_req_t [4:0] router_13_14_req_in; -floo_rsp_t [4:0] router_13_14_rsp_out; -floo_req_t [4:0] router_13_14_req_out; -floo_rsp_t [4:0] router_13_14_rsp_in; - - assign router_13_14_req_in[0] = router_13_15_to_router_13_14_req; - assign router_13_14_req_in[1] = router_14_14_to_router_13_14_req; - assign router_13_14_req_in[2] = router_13_13_to_router_13_14_req; - assign router_13_14_req_in[3] = router_12_14_to_router_13_14_req; - assign router_13_14_req_in[4] = magia_tile_ni_13_14_to_router_13_14_req; - - assign router_13_14_to_router_13_15_rsp = router_13_14_rsp_out[0]; - assign router_13_14_to_router_14_14_rsp = router_13_14_rsp_out[1]; - assign router_13_14_to_router_13_13_rsp = router_13_14_rsp_out[2]; - assign router_13_14_to_router_12_14_rsp = router_13_14_rsp_out[3]; - assign router_13_14_to_magia_tile_ni_13_14_rsp = router_13_14_rsp_out[4]; - - assign router_13_14_to_router_13_15_req = router_13_14_req_out[0]; - assign router_13_14_to_router_14_14_req = router_13_14_req_out[1]; - assign router_13_14_to_router_13_13_req = router_13_14_req_out[2]; - assign router_13_14_to_router_12_14_req = router_13_14_req_out[3]; - assign router_13_14_to_magia_tile_ni_13_14_req = router_13_14_req_out[4]; - - assign router_13_14_rsp_in[0] = router_13_15_to_router_13_14_rsp; - assign router_13_14_rsp_in[1] = router_14_14_to_router_13_14_rsp; - assign router_13_14_rsp_in[2] = router_13_13_to_router_13_14_rsp; - assign router_13_14_rsp_in[3] = router_12_14_to_router_13_14_rsp; - assign router_13_14_rsp_in[4] = magia_tile_ni_13_14_to_router_13_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_14_req_in), - .floo_rsp_o (router_13_14_rsp_out), - .floo_req_o (router_13_14_req_out), - .floo_rsp_i (router_13_14_rsp_in) -); - - -floo_req_t [4:0] router_13_15_req_in; -floo_rsp_t [4:0] router_13_15_rsp_out; -floo_req_t [4:0] router_13_15_req_out; -floo_rsp_t [4:0] router_13_15_rsp_in; - - assign router_13_15_req_in[0] = '0; - assign router_13_15_req_in[1] = router_14_15_to_router_13_15_req; - assign router_13_15_req_in[2] = router_13_14_to_router_13_15_req; - assign router_13_15_req_in[3] = router_12_15_to_router_13_15_req; - assign router_13_15_req_in[4] = magia_tile_ni_13_15_to_router_13_15_req; - - assign router_13_15_to_router_14_15_rsp = router_13_15_rsp_out[1]; - assign router_13_15_to_router_13_14_rsp = router_13_15_rsp_out[2]; - assign router_13_15_to_router_12_15_rsp = router_13_15_rsp_out[3]; - assign router_13_15_to_magia_tile_ni_13_15_rsp = router_13_15_rsp_out[4]; - - assign router_13_15_to_router_14_15_req = router_13_15_req_out[1]; - assign router_13_15_to_router_13_14_req = router_13_15_req_out[2]; - assign router_13_15_to_router_12_15_req = router_13_15_req_out[3]; - assign router_13_15_to_magia_tile_ni_13_15_req = router_13_15_req_out[4]; - - assign router_13_15_rsp_in[0] = '0; - assign router_13_15_rsp_in[1] = router_14_15_to_router_13_15_rsp; - assign router_13_15_rsp_in[2] = router_13_14_to_router_13_15_rsp; - assign router_13_15_rsp_in[3] = router_12_15_to_router_13_15_rsp; - assign router_13_15_rsp_in[4] = magia_tile_ni_13_15_to_router_13_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_15_req_in), - .floo_rsp_o (router_13_15_rsp_out), - .floo_req_o (router_13_15_req_out), - .floo_rsp_i (router_13_15_rsp_in) -); - - -floo_req_t [4:0] router_14_0_req_in; -floo_rsp_t [4:0] router_14_0_rsp_out; -floo_req_t [4:0] router_14_0_req_out; -floo_rsp_t [4:0] router_14_0_rsp_in; - - assign router_14_0_req_in[0] = router_14_1_to_router_14_0_req; - assign router_14_0_req_in[1] = router_15_0_to_router_14_0_req; - assign router_14_0_req_in[2] = '0; - assign router_14_0_req_in[3] = router_13_0_to_router_14_0_req; - assign router_14_0_req_in[4] = magia_tile_ni_14_0_to_router_14_0_req; - - assign router_14_0_to_router_14_1_rsp = router_14_0_rsp_out[0]; - assign router_14_0_to_router_15_0_rsp = router_14_0_rsp_out[1]; - assign router_14_0_to_router_13_0_rsp = router_14_0_rsp_out[3]; - assign router_14_0_to_magia_tile_ni_14_0_rsp = router_14_0_rsp_out[4]; - - assign router_14_0_to_router_14_1_req = router_14_0_req_out[0]; - assign router_14_0_to_router_15_0_req = router_14_0_req_out[1]; - assign router_14_0_to_router_13_0_req = router_14_0_req_out[3]; - assign router_14_0_to_magia_tile_ni_14_0_req = router_14_0_req_out[4]; - - assign router_14_0_rsp_in[0] = router_14_1_to_router_14_0_rsp; - assign router_14_0_rsp_in[1] = router_15_0_to_router_14_0_rsp; - assign router_14_0_rsp_in[2] = '0; - assign router_14_0_rsp_in[3] = router_13_0_to_router_14_0_rsp; - assign router_14_0_rsp_in[4] = magia_tile_ni_14_0_to_router_14_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_0_req_in), - .floo_rsp_o (router_14_0_rsp_out), - .floo_req_o (router_14_0_req_out), - .floo_rsp_i (router_14_0_rsp_in) -); - - -floo_req_t [4:0] router_14_1_req_in; -floo_rsp_t [4:0] router_14_1_rsp_out; -floo_req_t [4:0] router_14_1_req_out; -floo_rsp_t [4:0] router_14_1_rsp_in; - - assign router_14_1_req_in[0] = router_14_2_to_router_14_1_req; - assign router_14_1_req_in[1] = router_15_1_to_router_14_1_req; - assign router_14_1_req_in[2] = router_14_0_to_router_14_1_req; - assign router_14_1_req_in[3] = router_13_1_to_router_14_1_req; - assign router_14_1_req_in[4] = magia_tile_ni_14_1_to_router_14_1_req; - - assign router_14_1_to_router_14_2_rsp = router_14_1_rsp_out[0]; - assign router_14_1_to_router_15_1_rsp = router_14_1_rsp_out[1]; - assign router_14_1_to_router_14_0_rsp = router_14_1_rsp_out[2]; - assign router_14_1_to_router_13_1_rsp = router_14_1_rsp_out[3]; - assign router_14_1_to_magia_tile_ni_14_1_rsp = router_14_1_rsp_out[4]; - - assign router_14_1_to_router_14_2_req = router_14_1_req_out[0]; - assign router_14_1_to_router_15_1_req = router_14_1_req_out[1]; - assign router_14_1_to_router_14_0_req = router_14_1_req_out[2]; - assign router_14_1_to_router_13_1_req = router_14_1_req_out[3]; - assign router_14_1_to_magia_tile_ni_14_1_req = router_14_1_req_out[4]; - - assign router_14_1_rsp_in[0] = router_14_2_to_router_14_1_rsp; - assign router_14_1_rsp_in[1] = router_15_1_to_router_14_1_rsp; - assign router_14_1_rsp_in[2] = router_14_0_to_router_14_1_rsp; - assign router_14_1_rsp_in[3] = router_13_1_to_router_14_1_rsp; - assign router_14_1_rsp_in[4] = magia_tile_ni_14_1_to_router_14_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_1_req_in), - .floo_rsp_o (router_14_1_rsp_out), - .floo_req_o (router_14_1_req_out), - .floo_rsp_i (router_14_1_rsp_in) -); - - -floo_req_t [4:0] router_14_2_req_in; -floo_rsp_t [4:0] router_14_2_rsp_out; -floo_req_t [4:0] router_14_2_req_out; -floo_rsp_t [4:0] router_14_2_rsp_in; - - assign router_14_2_req_in[0] = router_14_3_to_router_14_2_req; - assign router_14_2_req_in[1] = router_15_2_to_router_14_2_req; - assign router_14_2_req_in[2] = router_14_1_to_router_14_2_req; - assign router_14_2_req_in[3] = router_13_2_to_router_14_2_req; - assign router_14_2_req_in[4] = magia_tile_ni_14_2_to_router_14_2_req; - - assign router_14_2_to_router_14_3_rsp = router_14_2_rsp_out[0]; - assign router_14_2_to_router_15_2_rsp = router_14_2_rsp_out[1]; - assign router_14_2_to_router_14_1_rsp = router_14_2_rsp_out[2]; - assign router_14_2_to_router_13_2_rsp = router_14_2_rsp_out[3]; - assign router_14_2_to_magia_tile_ni_14_2_rsp = router_14_2_rsp_out[4]; - - assign router_14_2_to_router_14_3_req = router_14_2_req_out[0]; - assign router_14_2_to_router_15_2_req = router_14_2_req_out[1]; - assign router_14_2_to_router_14_1_req = router_14_2_req_out[2]; - assign router_14_2_to_router_13_2_req = router_14_2_req_out[3]; - assign router_14_2_to_magia_tile_ni_14_2_req = router_14_2_req_out[4]; - - assign router_14_2_rsp_in[0] = router_14_3_to_router_14_2_rsp; - assign router_14_2_rsp_in[1] = router_15_2_to_router_14_2_rsp; - assign router_14_2_rsp_in[2] = router_14_1_to_router_14_2_rsp; - assign router_14_2_rsp_in[3] = router_13_2_to_router_14_2_rsp; - assign router_14_2_rsp_in[4] = magia_tile_ni_14_2_to_router_14_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_2_req_in), - .floo_rsp_o (router_14_2_rsp_out), - .floo_req_o (router_14_2_req_out), - .floo_rsp_i (router_14_2_rsp_in) -); - - -floo_req_t [4:0] router_14_3_req_in; -floo_rsp_t [4:0] router_14_3_rsp_out; -floo_req_t [4:0] router_14_3_req_out; -floo_rsp_t [4:0] router_14_3_rsp_in; - - assign router_14_3_req_in[0] = router_14_4_to_router_14_3_req; - assign router_14_3_req_in[1] = router_15_3_to_router_14_3_req; - assign router_14_3_req_in[2] = router_14_2_to_router_14_3_req; - assign router_14_3_req_in[3] = router_13_3_to_router_14_3_req; - assign router_14_3_req_in[4] = magia_tile_ni_14_3_to_router_14_3_req; - - assign router_14_3_to_router_14_4_rsp = router_14_3_rsp_out[0]; - assign router_14_3_to_router_15_3_rsp = router_14_3_rsp_out[1]; - assign router_14_3_to_router_14_2_rsp = router_14_3_rsp_out[2]; - assign router_14_3_to_router_13_3_rsp = router_14_3_rsp_out[3]; - assign router_14_3_to_magia_tile_ni_14_3_rsp = router_14_3_rsp_out[4]; - - assign router_14_3_to_router_14_4_req = router_14_3_req_out[0]; - assign router_14_3_to_router_15_3_req = router_14_3_req_out[1]; - assign router_14_3_to_router_14_2_req = router_14_3_req_out[2]; - assign router_14_3_to_router_13_3_req = router_14_3_req_out[3]; - assign router_14_3_to_magia_tile_ni_14_3_req = router_14_3_req_out[4]; - - assign router_14_3_rsp_in[0] = router_14_4_to_router_14_3_rsp; - assign router_14_3_rsp_in[1] = router_15_3_to_router_14_3_rsp; - assign router_14_3_rsp_in[2] = router_14_2_to_router_14_3_rsp; - assign router_14_3_rsp_in[3] = router_13_3_to_router_14_3_rsp; - assign router_14_3_rsp_in[4] = magia_tile_ni_14_3_to_router_14_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_3_req_in), - .floo_rsp_o (router_14_3_rsp_out), - .floo_req_o (router_14_3_req_out), - .floo_rsp_i (router_14_3_rsp_in) -); - - -floo_req_t [4:0] router_14_4_req_in; -floo_rsp_t [4:0] router_14_4_rsp_out; -floo_req_t [4:0] router_14_4_req_out; -floo_rsp_t [4:0] router_14_4_rsp_in; - - assign router_14_4_req_in[0] = router_14_5_to_router_14_4_req; - assign router_14_4_req_in[1] = router_15_4_to_router_14_4_req; - assign router_14_4_req_in[2] = router_14_3_to_router_14_4_req; - assign router_14_4_req_in[3] = router_13_4_to_router_14_4_req; - assign router_14_4_req_in[4] = magia_tile_ni_14_4_to_router_14_4_req; - - assign router_14_4_to_router_14_5_rsp = router_14_4_rsp_out[0]; - assign router_14_4_to_router_15_4_rsp = router_14_4_rsp_out[1]; - assign router_14_4_to_router_14_3_rsp = router_14_4_rsp_out[2]; - assign router_14_4_to_router_13_4_rsp = router_14_4_rsp_out[3]; - assign router_14_4_to_magia_tile_ni_14_4_rsp = router_14_4_rsp_out[4]; - - assign router_14_4_to_router_14_5_req = router_14_4_req_out[0]; - assign router_14_4_to_router_15_4_req = router_14_4_req_out[1]; - assign router_14_4_to_router_14_3_req = router_14_4_req_out[2]; - assign router_14_4_to_router_13_4_req = router_14_4_req_out[3]; - assign router_14_4_to_magia_tile_ni_14_4_req = router_14_4_req_out[4]; - - assign router_14_4_rsp_in[0] = router_14_5_to_router_14_4_rsp; - assign router_14_4_rsp_in[1] = router_15_4_to_router_14_4_rsp; - assign router_14_4_rsp_in[2] = router_14_3_to_router_14_4_rsp; - assign router_14_4_rsp_in[3] = router_13_4_to_router_14_4_rsp; - assign router_14_4_rsp_in[4] = magia_tile_ni_14_4_to_router_14_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_4_req_in), - .floo_rsp_o (router_14_4_rsp_out), - .floo_req_o (router_14_4_req_out), - .floo_rsp_i (router_14_4_rsp_in) -); - - -floo_req_t [4:0] router_14_5_req_in; -floo_rsp_t [4:0] router_14_5_rsp_out; -floo_req_t [4:0] router_14_5_req_out; -floo_rsp_t [4:0] router_14_5_rsp_in; - - assign router_14_5_req_in[0] = router_14_6_to_router_14_5_req; - assign router_14_5_req_in[1] = router_15_5_to_router_14_5_req; - assign router_14_5_req_in[2] = router_14_4_to_router_14_5_req; - assign router_14_5_req_in[3] = router_13_5_to_router_14_5_req; - assign router_14_5_req_in[4] = magia_tile_ni_14_5_to_router_14_5_req; - - assign router_14_5_to_router_14_6_rsp = router_14_5_rsp_out[0]; - assign router_14_5_to_router_15_5_rsp = router_14_5_rsp_out[1]; - assign router_14_5_to_router_14_4_rsp = router_14_5_rsp_out[2]; - assign router_14_5_to_router_13_5_rsp = router_14_5_rsp_out[3]; - assign router_14_5_to_magia_tile_ni_14_5_rsp = router_14_5_rsp_out[4]; - - assign router_14_5_to_router_14_6_req = router_14_5_req_out[0]; - assign router_14_5_to_router_15_5_req = router_14_5_req_out[1]; - assign router_14_5_to_router_14_4_req = router_14_5_req_out[2]; - assign router_14_5_to_router_13_5_req = router_14_5_req_out[3]; - assign router_14_5_to_magia_tile_ni_14_5_req = router_14_5_req_out[4]; - - assign router_14_5_rsp_in[0] = router_14_6_to_router_14_5_rsp; - assign router_14_5_rsp_in[1] = router_15_5_to_router_14_5_rsp; - assign router_14_5_rsp_in[2] = router_14_4_to_router_14_5_rsp; - assign router_14_5_rsp_in[3] = router_13_5_to_router_14_5_rsp; - assign router_14_5_rsp_in[4] = magia_tile_ni_14_5_to_router_14_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_5_req_in), - .floo_rsp_o (router_14_5_rsp_out), - .floo_req_o (router_14_5_req_out), - .floo_rsp_i (router_14_5_rsp_in) -); - - -floo_req_t [4:0] router_14_6_req_in; -floo_rsp_t [4:0] router_14_6_rsp_out; -floo_req_t [4:0] router_14_6_req_out; -floo_rsp_t [4:0] router_14_6_rsp_in; - - assign router_14_6_req_in[0] = router_14_7_to_router_14_6_req; - assign router_14_6_req_in[1] = router_15_6_to_router_14_6_req; - assign router_14_6_req_in[2] = router_14_5_to_router_14_6_req; - assign router_14_6_req_in[3] = router_13_6_to_router_14_6_req; - assign router_14_6_req_in[4] = magia_tile_ni_14_6_to_router_14_6_req; - - assign router_14_6_to_router_14_7_rsp = router_14_6_rsp_out[0]; - assign router_14_6_to_router_15_6_rsp = router_14_6_rsp_out[1]; - assign router_14_6_to_router_14_5_rsp = router_14_6_rsp_out[2]; - assign router_14_6_to_router_13_6_rsp = router_14_6_rsp_out[3]; - assign router_14_6_to_magia_tile_ni_14_6_rsp = router_14_6_rsp_out[4]; - - assign router_14_6_to_router_14_7_req = router_14_6_req_out[0]; - assign router_14_6_to_router_15_6_req = router_14_6_req_out[1]; - assign router_14_6_to_router_14_5_req = router_14_6_req_out[2]; - assign router_14_6_to_router_13_6_req = router_14_6_req_out[3]; - assign router_14_6_to_magia_tile_ni_14_6_req = router_14_6_req_out[4]; - - assign router_14_6_rsp_in[0] = router_14_7_to_router_14_6_rsp; - assign router_14_6_rsp_in[1] = router_15_6_to_router_14_6_rsp; - assign router_14_6_rsp_in[2] = router_14_5_to_router_14_6_rsp; - assign router_14_6_rsp_in[3] = router_13_6_to_router_14_6_rsp; - assign router_14_6_rsp_in[4] = magia_tile_ni_14_6_to_router_14_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_6_req_in), - .floo_rsp_o (router_14_6_rsp_out), - .floo_req_o (router_14_6_req_out), - .floo_rsp_i (router_14_6_rsp_in) -); - - -floo_req_t [4:0] router_14_7_req_in; -floo_rsp_t [4:0] router_14_7_rsp_out; -floo_req_t [4:0] router_14_7_req_out; -floo_rsp_t [4:0] router_14_7_rsp_in; - - assign router_14_7_req_in[0] = router_14_8_to_router_14_7_req; - assign router_14_7_req_in[1] = router_15_7_to_router_14_7_req; - assign router_14_7_req_in[2] = router_14_6_to_router_14_7_req; - assign router_14_7_req_in[3] = router_13_7_to_router_14_7_req; - assign router_14_7_req_in[4] = magia_tile_ni_14_7_to_router_14_7_req; - - assign router_14_7_to_router_14_8_rsp = router_14_7_rsp_out[0]; - assign router_14_7_to_router_15_7_rsp = router_14_7_rsp_out[1]; - assign router_14_7_to_router_14_6_rsp = router_14_7_rsp_out[2]; - assign router_14_7_to_router_13_7_rsp = router_14_7_rsp_out[3]; - assign router_14_7_to_magia_tile_ni_14_7_rsp = router_14_7_rsp_out[4]; - - assign router_14_7_to_router_14_8_req = router_14_7_req_out[0]; - assign router_14_7_to_router_15_7_req = router_14_7_req_out[1]; - assign router_14_7_to_router_14_6_req = router_14_7_req_out[2]; - assign router_14_7_to_router_13_7_req = router_14_7_req_out[3]; - assign router_14_7_to_magia_tile_ni_14_7_req = router_14_7_req_out[4]; - - assign router_14_7_rsp_in[0] = router_14_8_to_router_14_7_rsp; - assign router_14_7_rsp_in[1] = router_15_7_to_router_14_7_rsp; - assign router_14_7_rsp_in[2] = router_14_6_to_router_14_7_rsp; - assign router_14_7_rsp_in[3] = router_13_7_to_router_14_7_rsp; - assign router_14_7_rsp_in[4] = magia_tile_ni_14_7_to_router_14_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_7_req_in), - .floo_rsp_o (router_14_7_rsp_out), - .floo_req_o (router_14_7_req_out), - .floo_rsp_i (router_14_7_rsp_in) -); - - -floo_req_t [4:0] router_14_8_req_in; -floo_rsp_t [4:0] router_14_8_rsp_out; -floo_req_t [4:0] router_14_8_req_out; -floo_rsp_t [4:0] router_14_8_rsp_in; - - assign router_14_8_req_in[0] = router_14_9_to_router_14_8_req; - assign router_14_8_req_in[1] = router_15_8_to_router_14_8_req; - assign router_14_8_req_in[2] = router_14_7_to_router_14_8_req; - assign router_14_8_req_in[3] = router_13_8_to_router_14_8_req; - assign router_14_8_req_in[4] = magia_tile_ni_14_8_to_router_14_8_req; - - assign router_14_8_to_router_14_9_rsp = router_14_8_rsp_out[0]; - assign router_14_8_to_router_15_8_rsp = router_14_8_rsp_out[1]; - assign router_14_8_to_router_14_7_rsp = router_14_8_rsp_out[2]; - assign router_14_8_to_router_13_8_rsp = router_14_8_rsp_out[3]; - assign router_14_8_to_magia_tile_ni_14_8_rsp = router_14_8_rsp_out[4]; - - assign router_14_8_to_router_14_9_req = router_14_8_req_out[0]; - assign router_14_8_to_router_15_8_req = router_14_8_req_out[1]; - assign router_14_8_to_router_14_7_req = router_14_8_req_out[2]; - assign router_14_8_to_router_13_8_req = router_14_8_req_out[3]; - assign router_14_8_to_magia_tile_ni_14_8_req = router_14_8_req_out[4]; - - assign router_14_8_rsp_in[0] = router_14_9_to_router_14_8_rsp; - assign router_14_8_rsp_in[1] = router_15_8_to_router_14_8_rsp; - assign router_14_8_rsp_in[2] = router_14_7_to_router_14_8_rsp; - assign router_14_8_rsp_in[3] = router_13_8_to_router_14_8_rsp; - assign router_14_8_rsp_in[4] = magia_tile_ni_14_8_to_router_14_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_8_req_in), - .floo_rsp_o (router_14_8_rsp_out), - .floo_req_o (router_14_8_req_out), - .floo_rsp_i (router_14_8_rsp_in) -); - - -floo_req_t [4:0] router_14_9_req_in; -floo_rsp_t [4:0] router_14_9_rsp_out; -floo_req_t [4:0] router_14_9_req_out; -floo_rsp_t [4:0] router_14_9_rsp_in; - - assign router_14_9_req_in[0] = router_14_10_to_router_14_9_req; - assign router_14_9_req_in[1] = router_15_9_to_router_14_9_req; - assign router_14_9_req_in[2] = router_14_8_to_router_14_9_req; - assign router_14_9_req_in[3] = router_13_9_to_router_14_9_req; - assign router_14_9_req_in[4] = magia_tile_ni_14_9_to_router_14_9_req; - - assign router_14_9_to_router_14_10_rsp = router_14_9_rsp_out[0]; - assign router_14_9_to_router_15_9_rsp = router_14_9_rsp_out[1]; - assign router_14_9_to_router_14_8_rsp = router_14_9_rsp_out[2]; - assign router_14_9_to_router_13_9_rsp = router_14_9_rsp_out[3]; - assign router_14_9_to_magia_tile_ni_14_9_rsp = router_14_9_rsp_out[4]; - - assign router_14_9_to_router_14_10_req = router_14_9_req_out[0]; - assign router_14_9_to_router_15_9_req = router_14_9_req_out[1]; - assign router_14_9_to_router_14_8_req = router_14_9_req_out[2]; - assign router_14_9_to_router_13_9_req = router_14_9_req_out[3]; - assign router_14_9_to_magia_tile_ni_14_9_req = router_14_9_req_out[4]; - - assign router_14_9_rsp_in[0] = router_14_10_to_router_14_9_rsp; - assign router_14_9_rsp_in[1] = router_15_9_to_router_14_9_rsp; - assign router_14_9_rsp_in[2] = router_14_8_to_router_14_9_rsp; - assign router_14_9_rsp_in[3] = router_13_9_to_router_14_9_rsp; - assign router_14_9_rsp_in[4] = magia_tile_ni_14_9_to_router_14_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_9_req_in), - .floo_rsp_o (router_14_9_rsp_out), - .floo_req_o (router_14_9_req_out), - .floo_rsp_i (router_14_9_rsp_in) -); - - -floo_req_t [4:0] router_14_10_req_in; -floo_rsp_t [4:0] router_14_10_rsp_out; -floo_req_t [4:0] router_14_10_req_out; -floo_rsp_t [4:0] router_14_10_rsp_in; - - assign router_14_10_req_in[0] = router_14_11_to_router_14_10_req; - assign router_14_10_req_in[1] = router_15_10_to_router_14_10_req; - assign router_14_10_req_in[2] = router_14_9_to_router_14_10_req; - assign router_14_10_req_in[3] = router_13_10_to_router_14_10_req; - assign router_14_10_req_in[4] = magia_tile_ni_14_10_to_router_14_10_req; - - assign router_14_10_to_router_14_11_rsp = router_14_10_rsp_out[0]; - assign router_14_10_to_router_15_10_rsp = router_14_10_rsp_out[1]; - assign router_14_10_to_router_14_9_rsp = router_14_10_rsp_out[2]; - assign router_14_10_to_router_13_10_rsp = router_14_10_rsp_out[3]; - assign router_14_10_to_magia_tile_ni_14_10_rsp = router_14_10_rsp_out[4]; - - assign router_14_10_to_router_14_11_req = router_14_10_req_out[0]; - assign router_14_10_to_router_15_10_req = router_14_10_req_out[1]; - assign router_14_10_to_router_14_9_req = router_14_10_req_out[2]; - assign router_14_10_to_router_13_10_req = router_14_10_req_out[3]; - assign router_14_10_to_magia_tile_ni_14_10_req = router_14_10_req_out[4]; - - assign router_14_10_rsp_in[0] = router_14_11_to_router_14_10_rsp; - assign router_14_10_rsp_in[1] = router_15_10_to_router_14_10_rsp; - assign router_14_10_rsp_in[2] = router_14_9_to_router_14_10_rsp; - assign router_14_10_rsp_in[3] = router_13_10_to_router_14_10_rsp; - assign router_14_10_rsp_in[4] = magia_tile_ni_14_10_to_router_14_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_10_req_in), - .floo_rsp_o (router_14_10_rsp_out), - .floo_req_o (router_14_10_req_out), - .floo_rsp_i (router_14_10_rsp_in) -); - - -floo_req_t [4:0] router_14_11_req_in; -floo_rsp_t [4:0] router_14_11_rsp_out; -floo_req_t [4:0] router_14_11_req_out; -floo_rsp_t [4:0] router_14_11_rsp_in; - - assign router_14_11_req_in[0] = router_14_12_to_router_14_11_req; - assign router_14_11_req_in[1] = router_15_11_to_router_14_11_req; - assign router_14_11_req_in[2] = router_14_10_to_router_14_11_req; - assign router_14_11_req_in[3] = router_13_11_to_router_14_11_req; - assign router_14_11_req_in[4] = magia_tile_ni_14_11_to_router_14_11_req; - - assign router_14_11_to_router_14_12_rsp = router_14_11_rsp_out[0]; - assign router_14_11_to_router_15_11_rsp = router_14_11_rsp_out[1]; - assign router_14_11_to_router_14_10_rsp = router_14_11_rsp_out[2]; - assign router_14_11_to_router_13_11_rsp = router_14_11_rsp_out[3]; - assign router_14_11_to_magia_tile_ni_14_11_rsp = router_14_11_rsp_out[4]; - - assign router_14_11_to_router_14_12_req = router_14_11_req_out[0]; - assign router_14_11_to_router_15_11_req = router_14_11_req_out[1]; - assign router_14_11_to_router_14_10_req = router_14_11_req_out[2]; - assign router_14_11_to_router_13_11_req = router_14_11_req_out[3]; - assign router_14_11_to_magia_tile_ni_14_11_req = router_14_11_req_out[4]; - - assign router_14_11_rsp_in[0] = router_14_12_to_router_14_11_rsp; - assign router_14_11_rsp_in[1] = router_15_11_to_router_14_11_rsp; - assign router_14_11_rsp_in[2] = router_14_10_to_router_14_11_rsp; - assign router_14_11_rsp_in[3] = router_13_11_to_router_14_11_rsp; - assign router_14_11_rsp_in[4] = magia_tile_ni_14_11_to_router_14_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_11_req_in), - .floo_rsp_o (router_14_11_rsp_out), - .floo_req_o (router_14_11_req_out), - .floo_rsp_i (router_14_11_rsp_in) -); - - -floo_req_t [4:0] router_14_12_req_in; -floo_rsp_t [4:0] router_14_12_rsp_out; -floo_req_t [4:0] router_14_12_req_out; -floo_rsp_t [4:0] router_14_12_rsp_in; - - assign router_14_12_req_in[0] = router_14_13_to_router_14_12_req; - assign router_14_12_req_in[1] = router_15_12_to_router_14_12_req; - assign router_14_12_req_in[2] = router_14_11_to_router_14_12_req; - assign router_14_12_req_in[3] = router_13_12_to_router_14_12_req; - assign router_14_12_req_in[4] = magia_tile_ni_14_12_to_router_14_12_req; - - assign router_14_12_to_router_14_13_rsp = router_14_12_rsp_out[0]; - assign router_14_12_to_router_15_12_rsp = router_14_12_rsp_out[1]; - assign router_14_12_to_router_14_11_rsp = router_14_12_rsp_out[2]; - assign router_14_12_to_router_13_12_rsp = router_14_12_rsp_out[3]; - assign router_14_12_to_magia_tile_ni_14_12_rsp = router_14_12_rsp_out[4]; - - assign router_14_12_to_router_14_13_req = router_14_12_req_out[0]; - assign router_14_12_to_router_15_12_req = router_14_12_req_out[1]; - assign router_14_12_to_router_14_11_req = router_14_12_req_out[2]; - assign router_14_12_to_router_13_12_req = router_14_12_req_out[3]; - assign router_14_12_to_magia_tile_ni_14_12_req = router_14_12_req_out[4]; - - assign router_14_12_rsp_in[0] = router_14_13_to_router_14_12_rsp; - assign router_14_12_rsp_in[1] = router_15_12_to_router_14_12_rsp; - assign router_14_12_rsp_in[2] = router_14_11_to_router_14_12_rsp; - assign router_14_12_rsp_in[3] = router_13_12_to_router_14_12_rsp; - assign router_14_12_rsp_in[4] = magia_tile_ni_14_12_to_router_14_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_12_req_in), - .floo_rsp_o (router_14_12_rsp_out), - .floo_req_o (router_14_12_req_out), - .floo_rsp_i (router_14_12_rsp_in) -); - - -floo_req_t [4:0] router_14_13_req_in; -floo_rsp_t [4:0] router_14_13_rsp_out; -floo_req_t [4:0] router_14_13_req_out; -floo_rsp_t [4:0] router_14_13_rsp_in; - - assign router_14_13_req_in[0] = router_14_14_to_router_14_13_req; - assign router_14_13_req_in[1] = router_15_13_to_router_14_13_req; - assign router_14_13_req_in[2] = router_14_12_to_router_14_13_req; - assign router_14_13_req_in[3] = router_13_13_to_router_14_13_req; - assign router_14_13_req_in[4] = magia_tile_ni_14_13_to_router_14_13_req; - - assign router_14_13_to_router_14_14_rsp = router_14_13_rsp_out[0]; - assign router_14_13_to_router_15_13_rsp = router_14_13_rsp_out[1]; - assign router_14_13_to_router_14_12_rsp = router_14_13_rsp_out[2]; - assign router_14_13_to_router_13_13_rsp = router_14_13_rsp_out[3]; - assign router_14_13_to_magia_tile_ni_14_13_rsp = router_14_13_rsp_out[4]; - - assign router_14_13_to_router_14_14_req = router_14_13_req_out[0]; - assign router_14_13_to_router_15_13_req = router_14_13_req_out[1]; - assign router_14_13_to_router_14_12_req = router_14_13_req_out[2]; - assign router_14_13_to_router_13_13_req = router_14_13_req_out[3]; - assign router_14_13_to_magia_tile_ni_14_13_req = router_14_13_req_out[4]; - - assign router_14_13_rsp_in[0] = router_14_14_to_router_14_13_rsp; - assign router_14_13_rsp_in[1] = router_15_13_to_router_14_13_rsp; - assign router_14_13_rsp_in[2] = router_14_12_to_router_14_13_rsp; - assign router_14_13_rsp_in[3] = router_13_13_to_router_14_13_rsp; - assign router_14_13_rsp_in[4] = magia_tile_ni_14_13_to_router_14_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_13_req_in), - .floo_rsp_o (router_14_13_rsp_out), - .floo_req_o (router_14_13_req_out), - .floo_rsp_i (router_14_13_rsp_in) -); - - -floo_req_t [4:0] router_14_14_req_in; -floo_rsp_t [4:0] router_14_14_rsp_out; -floo_req_t [4:0] router_14_14_req_out; -floo_rsp_t [4:0] router_14_14_rsp_in; - - assign router_14_14_req_in[0] = router_14_15_to_router_14_14_req; - assign router_14_14_req_in[1] = router_15_14_to_router_14_14_req; - assign router_14_14_req_in[2] = router_14_13_to_router_14_14_req; - assign router_14_14_req_in[3] = router_13_14_to_router_14_14_req; - assign router_14_14_req_in[4] = magia_tile_ni_14_14_to_router_14_14_req; - - assign router_14_14_to_router_14_15_rsp = router_14_14_rsp_out[0]; - assign router_14_14_to_router_15_14_rsp = router_14_14_rsp_out[1]; - assign router_14_14_to_router_14_13_rsp = router_14_14_rsp_out[2]; - assign router_14_14_to_router_13_14_rsp = router_14_14_rsp_out[3]; - assign router_14_14_to_magia_tile_ni_14_14_rsp = router_14_14_rsp_out[4]; - - assign router_14_14_to_router_14_15_req = router_14_14_req_out[0]; - assign router_14_14_to_router_15_14_req = router_14_14_req_out[1]; - assign router_14_14_to_router_14_13_req = router_14_14_req_out[2]; - assign router_14_14_to_router_13_14_req = router_14_14_req_out[3]; - assign router_14_14_to_magia_tile_ni_14_14_req = router_14_14_req_out[4]; - - assign router_14_14_rsp_in[0] = router_14_15_to_router_14_14_rsp; - assign router_14_14_rsp_in[1] = router_15_14_to_router_14_14_rsp; - assign router_14_14_rsp_in[2] = router_14_13_to_router_14_14_rsp; - assign router_14_14_rsp_in[3] = router_13_14_to_router_14_14_rsp; - assign router_14_14_rsp_in[4] = magia_tile_ni_14_14_to_router_14_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_14_req_in), - .floo_rsp_o (router_14_14_rsp_out), - .floo_req_o (router_14_14_req_out), - .floo_rsp_i (router_14_14_rsp_in) -); - - -floo_req_t [4:0] router_14_15_req_in; -floo_rsp_t [4:0] router_14_15_rsp_out; -floo_req_t [4:0] router_14_15_req_out; -floo_rsp_t [4:0] router_14_15_rsp_in; - - assign router_14_15_req_in[0] = '0; - assign router_14_15_req_in[1] = router_15_15_to_router_14_15_req; - assign router_14_15_req_in[2] = router_14_14_to_router_14_15_req; - assign router_14_15_req_in[3] = router_13_15_to_router_14_15_req; - assign router_14_15_req_in[4] = magia_tile_ni_14_15_to_router_14_15_req; - - assign router_14_15_to_router_15_15_rsp = router_14_15_rsp_out[1]; - assign router_14_15_to_router_14_14_rsp = router_14_15_rsp_out[2]; - assign router_14_15_to_router_13_15_rsp = router_14_15_rsp_out[3]; - assign router_14_15_to_magia_tile_ni_14_15_rsp = router_14_15_rsp_out[4]; - - assign router_14_15_to_router_15_15_req = router_14_15_req_out[1]; - assign router_14_15_to_router_14_14_req = router_14_15_req_out[2]; - assign router_14_15_to_router_13_15_req = router_14_15_req_out[3]; - assign router_14_15_to_magia_tile_ni_14_15_req = router_14_15_req_out[4]; - - assign router_14_15_rsp_in[0] = '0; - assign router_14_15_rsp_in[1] = router_15_15_to_router_14_15_rsp; - assign router_14_15_rsp_in[2] = router_14_14_to_router_14_15_rsp; - assign router_14_15_rsp_in[3] = router_13_15_to_router_14_15_rsp; - assign router_14_15_rsp_in[4] = magia_tile_ni_14_15_to_router_14_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_15_req_in), - .floo_rsp_o (router_14_15_rsp_out), - .floo_req_o (router_14_15_req_out), - .floo_rsp_i (router_14_15_rsp_in) -); - - -floo_req_t [4:0] router_15_0_req_in; -floo_rsp_t [4:0] router_15_0_rsp_out; -floo_req_t [4:0] router_15_0_req_out; -floo_rsp_t [4:0] router_15_0_rsp_in; - - assign router_15_0_req_in[0] = router_15_1_to_router_15_0_req; - assign router_15_0_req_in[1] = '0; - assign router_15_0_req_in[2] = '0; - assign router_15_0_req_in[3] = router_14_0_to_router_15_0_req; - assign router_15_0_req_in[4] = magia_tile_ni_15_0_to_router_15_0_req; - - assign router_15_0_to_router_15_1_rsp = router_15_0_rsp_out[0]; - assign router_15_0_to_router_14_0_rsp = router_15_0_rsp_out[3]; - assign router_15_0_to_magia_tile_ni_15_0_rsp = router_15_0_rsp_out[4]; - - assign router_15_0_to_router_15_1_req = router_15_0_req_out[0]; - assign router_15_0_to_router_14_0_req = router_15_0_req_out[3]; - assign router_15_0_to_magia_tile_ni_15_0_req = router_15_0_req_out[4]; - - assign router_15_0_rsp_in[0] = router_15_1_to_router_15_0_rsp; - assign router_15_0_rsp_in[1] = '0; - assign router_15_0_rsp_in[2] = '0; - assign router_15_0_rsp_in[3] = router_14_0_to_router_15_0_rsp; - assign router_15_0_rsp_in[4] = magia_tile_ni_15_0_to_router_15_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_0_req_in), - .floo_rsp_o (router_15_0_rsp_out), - .floo_req_o (router_15_0_req_out), - .floo_rsp_i (router_15_0_rsp_in) -); - - -floo_req_t [4:0] router_15_1_req_in; -floo_rsp_t [4:0] router_15_1_rsp_out; -floo_req_t [4:0] router_15_1_req_out; -floo_rsp_t [4:0] router_15_1_rsp_in; - - assign router_15_1_req_in[0] = router_15_2_to_router_15_1_req; - assign router_15_1_req_in[1] = '0; - assign router_15_1_req_in[2] = router_15_0_to_router_15_1_req; - assign router_15_1_req_in[3] = router_14_1_to_router_15_1_req; - assign router_15_1_req_in[4] = magia_tile_ni_15_1_to_router_15_1_req; - - assign router_15_1_to_router_15_2_rsp = router_15_1_rsp_out[0]; - assign router_15_1_to_router_15_0_rsp = router_15_1_rsp_out[2]; - assign router_15_1_to_router_14_1_rsp = router_15_1_rsp_out[3]; - assign router_15_1_to_magia_tile_ni_15_1_rsp = router_15_1_rsp_out[4]; - - assign router_15_1_to_router_15_2_req = router_15_1_req_out[0]; - assign router_15_1_to_router_15_0_req = router_15_1_req_out[2]; - assign router_15_1_to_router_14_1_req = router_15_1_req_out[3]; - assign router_15_1_to_magia_tile_ni_15_1_req = router_15_1_req_out[4]; - - assign router_15_1_rsp_in[0] = router_15_2_to_router_15_1_rsp; - assign router_15_1_rsp_in[1] = '0; - assign router_15_1_rsp_in[2] = router_15_0_to_router_15_1_rsp; - assign router_15_1_rsp_in[3] = router_14_1_to_router_15_1_rsp; - assign router_15_1_rsp_in[4] = magia_tile_ni_15_1_to_router_15_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_1_req_in), - .floo_rsp_o (router_15_1_rsp_out), - .floo_req_o (router_15_1_req_out), - .floo_rsp_i (router_15_1_rsp_in) -); - - -floo_req_t [4:0] router_15_2_req_in; -floo_rsp_t [4:0] router_15_2_rsp_out; -floo_req_t [4:0] router_15_2_req_out; -floo_rsp_t [4:0] router_15_2_rsp_in; - - assign router_15_2_req_in[0] = router_15_3_to_router_15_2_req; - assign router_15_2_req_in[1] = '0; - assign router_15_2_req_in[2] = router_15_1_to_router_15_2_req; - assign router_15_2_req_in[3] = router_14_2_to_router_15_2_req; - assign router_15_2_req_in[4] = magia_tile_ni_15_2_to_router_15_2_req; - - assign router_15_2_to_router_15_3_rsp = router_15_2_rsp_out[0]; - assign router_15_2_to_router_15_1_rsp = router_15_2_rsp_out[2]; - assign router_15_2_to_router_14_2_rsp = router_15_2_rsp_out[3]; - assign router_15_2_to_magia_tile_ni_15_2_rsp = router_15_2_rsp_out[4]; - - assign router_15_2_to_router_15_3_req = router_15_2_req_out[0]; - assign router_15_2_to_router_15_1_req = router_15_2_req_out[2]; - assign router_15_2_to_router_14_2_req = router_15_2_req_out[3]; - assign router_15_2_to_magia_tile_ni_15_2_req = router_15_2_req_out[4]; - - assign router_15_2_rsp_in[0] = router_15_3_to_router_15_2_rsp; - assign router_15_2_rsp_in[1] = '0; - assign router_15_2_rsp_in[2] = router_15_1_to_router_15_2_rsp; - assign router_15_2_rsp_in[3] = router_14_2_to_router_15_2_rsp; - assign router_15_2_rsp_in[4] = magia_tile_ni_15_2_to_router_15_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_2_req_in), - .floo_rsp_o (router_15_2_rsp_out), - .floo_req_o (router_15_2_req_out), - .floo_rsp_i (router_15_2_rsp_in) -); - - -floo_req_t [4:0] router_15_3_req_in; -floo_rsp_t [4:0] router_15_3_rsp_out; -floo_req_t [4:0] router_15_3_req_out; -floo_rsp_t [4:0] router_15_3_rsp_in; - - assign router_15_3_req_in[0] = router_15_4_to_router_15_3_req; - assign router_15_3_req_in[1] = '0; - assign router_15_3_req_in[2] = router_15_2_to_router_15_3_req; - assign router_15_3_req_in[3] = router_14_3_to_router_15_3_req; - assign router_15_3_req_in[4] = magia_tile_ni_15_3_to_router_15_3_req; - - assign router_15_3_to_router_15_4_rsp = router_15_3_rsp_out[0]; - assign router_15_3_to_router_15_2_rsp = router_15_3_rsp_out[2]; - assign router_15_3_to_router_14_3_rsp = router_15_3_rsp_out[3]; - assign router_15_3_to_magia_tile_ni_15_3_rsp = router_15_3_rsp_out[4]; - - assign router_15_3_to_router_15_4_req = router_15_3_req_out[0]; - assign router_15_3_to_router_15_2_req = router_15_3_req_out[2]; - assign router_15_3_to_router_14_3_req = router_15_3_req_out[3]; - assign router_15_3_to_magia_tile_ni_15_3_req = router_15_3_req_out[4]; - - assign router_15_3_rsp_in[0] = router_15_4_to_router_15_3_rsp; - assign router_15_3_rsp_in[1] = '0; - assign router_15_3_rsp_in[2] = router_15_2_to_router_15_3_rsp; - assign router_15_3_rsp_in[3] = router_14_3_to_router_15_3_rsp; - assign router_15_3_rsp_in[4] = magia_tile_ni_15_3_to_router_15_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_3_req_in), - .floo_rsp_o (router_15_3_rsp_out), - .floo_req_o (router_15_3_req_out), - .floo_rsp_i (router_15_3_rsp_in) -); - - -floo_req_t [4:0] router_15_4_req_in; -floo_rsp_t [4:0] router_15_4_rsp_out; -floo_req_t [4:0] router_15_4_req_out; -floo_rsp_t [4:0] router_15_4_rsp_in; - - assign router_15_4_req_in[0] = router_15_5_to_router_15_4_req; - assign router_15_4_req_in[1] = '0; - assign router_15_4_req_in[2] = router_15_3_to_router_15_4_req; - assign router_15_4_req_in[3] = router_14_4_to_router_15_4_req; - assign router_15_4_req_in[4] = magia_tile_ni_15_4_to_router_15_4_req; - - assign router_15_4_to_router_15_5_rsp = router_15_4_rsp_out[0]; - assign router_15_4_to_router_15_3_rsp = router_15_4_rsp_out[2]; - assign router_15_4_to_router_14_4_rsp = router_15_4_rsp_out[3]; - assign router_15_4_to_magia_tile_ni_15_4_rsp = router_15_4_rsp_out[4]; - - assign router_15_4_to_router_15_5_req = router_15_4_req_out[0]; - assign router_15_4_to_router_15_3_req = router_15_4_req_out[2]; - assign router_15_4_to_router_14_4_req = router_15_4_req_out[3]; - assign router_15_4_to_magia_tile_ni_15_4_req = router_15_4_req_out[4]; - - assign router_15_4_rsp_in[0] = router_15_5_to_router_15_4_rsp; - assign router_15_4_rsp_in[1] = '0; - assign router_15_4_rsp_in[2] = router_15_3_to_router_15_4_rsp; - assign router_15_4_rsp_in[3] = router_14_4_to_router_15_4_rsp; - assign router_15_4_rsp_in[4] = magia_tile_ni_15_4_to_router_15_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_4_req_in), - .floo_rsp_o (router_15_4_rsp_out), - .floo_req_o (router_15_4_req_out), - .floo_rsp_i (router_15_4_rsp_in) -); - - -floo_req_t [4:0] router_15_5_req_in; -floo_rsp_t [4:0] router_15_5_rsp_out; -floo_req_t [4:0] router_15_5_req_out; -floo_rsp_t [4:0] router_15_5_rsp_in; - - assign router_15_5_req_in[0] = router_15_6_to_router_15_5_req; - assign router_15_5_req_in[1] = '0; - assign router_15_5_req_in[2] = router_15_4_to_router_15_5_req; - assign router_15_5_req_in[3] = router_14_5_to_router_15_5_req; - assign router_15_5_req_in[4] = magia_tile_ni_15_5_to_router_15_5_req; - - assign router_15_5_to_router_15_6_rsp = router_15_5_rsp_out[0]; - assign router_15_5_to_router_15_4_rsp = router_15_5_rsp_out[2]; - assign router_15_5_to_router_14_5_rsp = router_15_5_rsp_out[3]; - assign router_15_5_to_magia_tile_ni_15_5_rsp = router_15_5_rsp_out[4]; - - assign router_15_5_to_router_15_6_req = router_15_5_req_out[0]; - assign router_15_5_to_router_15_4_req = router_15_5_req_out[2]; - assign router_15_5_to_router_14_5_req = router_15_5_req_out[3]; - assign router_15_5_to_magia_tile_ni_15_5_req = router_15_5_req_out[4]; - - assign router_15_5_rsp_in[0] = router_15_6_to_router_15_5_rsp; - assign router_15_5_rsp_in[1] = '0; - assign router_15_5_rsp_in[2] = router_15_4_to_router_15_5_rsp; - assign router_15_5_rsp_in[3] = router_14_5_to_router_15_5_rsp; - assign router_15_5_rsp_in[4] = magia_tile_ni_15_5_to_router_15_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_5_req_in), - .floo_rsp_o (router_15_5_rsp_out), - .floo_req_o (router_15_5_req_out), - .floo_rsp_i (router_15_5_rsp_in) -); - - -floo_req_t [4:0] router_15_6_req_in; -floo_rsp_t [4:0] router_15_6_rsp_out; -floo_req_t [4:0] router_15_6_req_out; -floo_rsp_t [4:0] router_15_6_rsp_in; - - assign router_15_6_req_in[0] = router_15_7_to_router_15_6_req; - assign router_15_6_req_in[1] = '0; - assign router_15_6_req_in[2] = router_15_5_to_router_15_6_req; - assign router_15_6_req_in[3] = router_14_6_to_router_15_6_req; - assign router_15_6_req_in[4] = magia_tile_ni_15_6_to_router_15_6_req; - - assign router_15_6_to_router_15_7_rsp = router_15_6_rsp_out[0]; - assign router_15_6_to_router_15_5_rsp = router_15_6_rsp_out[2]; - assign router_15_6_to_router_14_6_rsp = router_15_6_rsp_out[3]; - assign router_15_6_to_magia_tile_ni_15_6_rsp = router_15_6_rsp_out[4]; - - assign router_15_6_to_router_15_7_req = router_15_6_req_out[0]; - assign router_15_6_to_router_15_5_req = router_15_6_req_out[2]; - assign router_15_6_to_router_14_6_req = router_15_6_req_out[3]; - assign router_15_6_to_magia_tile_ni_15_6_req = router_15_6_req_out[4]; - - assign router_15_6_rsp_in[0] = router_15_7_to_router_15_6_rsp; - assign router_15_6_rsp_in[1] = '0; - assign router_15_6_rsp_in[2] = router_15_5_to_router_15_6_rsp; - assign router_15_6_rsp_in[3] = router_14_6_to_router_15_6_rsp; - assign router_15_6_rsp_in[4] = magia_tile_ni_15_6_to_router_15_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_6_req_in), - .floo_rsp_o (router_15_6_rsp_out), - .floo_req_o (router_15_6_req_out), - .floo_rsp_i (router_15_6_rsp_in) -); - - -floo_req_t [4:0] router_15_7_req_in; -floo_rsp_t [4:0] router_15_7_rsp_out; -floo_req_t [4:0] router_15_7_req_out; -floo_rsp_t [4:0] router_15_7_rsp_in; - - assign router_15_7_req_in[0] = router_15_8_to_router_15_7_req; - assign router_15_7_req_in[1] = '0; - assign router_15_7_req_in[2] = router_15_6_to_router_15_7_req; - assign router_15_7_req_in[3] = router_14_7_to_router_15_7_req; - assign router_15_7_req_in[4] = magia_tile_ni_15_7_to_router_15_7_req; - - assign router_15_7_to_router_15_8_rsp = router_15_7_rsp_out[0]; - assign router_15_7_to_router_15_6_rsp = router_15_7_rsp_out[2]; - assign router_15_7_to_router_14_7_rsp = router_15_7_rsp_out[3]; - assign router_15_7_to_magia_tile_ni_15_7_rsp = router_15_7_rsp_out[4]; - - assign router_15_7_to_router_15_8_req = router_15_7_req_out[0]; - assign router_15_7_to_router_15_6_req = router_15_7_req_out[2]; - assign router_15_7_to_router_14_7_req = router_15_7_req_out[3]; - assign router_15_7_to_magia_tile_ni_15_7_req = router_15_7_req_out[4]; - - assign router_15_7_rsp_in[0] = router_15_8_to_router_15_7_rsp; - assign router_15_7_rsp_in[1] = '0; - assign router_15_7_rsp_in[2] = router_15_6_to_router_15_7_rsp; - assign router_15_7_rsp_in[3] = router_14_7_to_router_15_7_rsp; - assign router_15_7_rsp_in[4] = magia_tile_ni_15_7_to_router_15_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_7_req_in), - .floo_rsp_o (router_15_7_rsp_out), - .floo_req_o (router_15_7_req_out), - .floo_rsp_i (router_15_7_rsp_in) -); - - -floo_req_t [4:0] router_15_8_req_in; -floo_rsp_t [4:0] router_15_8_rsp_out; -floo_req_t [4:0] router_15_8_req_out; -floo_rsp_t [4:0] router_15_8_rsp_in; - - assign router_15_8_req_in[0] = router_15_9_to_router_15_8_req; - assign router_15_8_req_in[1] = '0; - assign router_15_8_req_in[2] = router_15_7_to_router_15_8_req; - assign router_15_8_req_in[3] = router_14_8_to_router_15_8_req; - assign router_15_8_req_in[4] = magia_tile_ni_15_8_to_router_15_8_req; - - assign router_15_8_to_router_15_9_rsp = router_15_8_rsp_out[0]; - assign router_15_8_to_router_15_7_rsp = router_15_8_rsp_out[2]; - assign router_15_8_to_router_14_8_rsp = router_15_8_rsp_out[3]; - assign router_15_8_to_magia_tile_ni_15_8_rsp = router_15_8_rsp_out[4]; - - assign router_15_8_to_router_15_9_req = router_15_8_req_out[0]; - assign router_15_8_to_router_15_7_req = router_15_8_req_out[2]; - assign router_15_8_to_router_14_8_req = router_15_8_req_out[3]; - assign router_15_8_to_magia_tile_ni_15_8_req = router_15_8_req_out[4]; - - assign router_15_8_rsp_in[0] = router_15_9_to_router_15_8_rsp; - assign router_15_8_rsp_in[1] = '0; - assign router_15_8_rsp_in[2] = router_15_7_to_router_15_8_rsp; - assign router_15_8_rsp_in[3] = router_14_8_to_router_15_8_rsp; - assign router_15_8_rsp_in[4] = magia_tile_ni_15_8_to_router_15_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_8_req_in), - .floo_rsp_o (router_15_8_rsp_out), - .floo_req_o (router_15_8_req_out), - .floo_rsp_i (router_15_8_rsp_in) -); - - -floo_req_t [4:0] router_15_9_req_in; -floo_rsp_t [4:0] router_15_9_rsp_out; -floo_req_t [4:0] router_15_9_req_out; -floo_rsp_t [4:0] router_15_9_rsp_in; - - assign router_15_9_req_in[0] = router_15_10_to_router_15_9_req; - assign router_15_9_req_in[1] = '0; - assign router_15_9_req_in[2] = router_15_8_to_router_15_9_req; - assign router_15_9_req_in[3] = router_14_9_to_router_15_9_req; - assign router_15_9_req_in[4] = magia_tile_ni_15_9_to_router_15_9_req; - - assign router_15_9_to_router_15_10_rsp = router_15_9_rsp_out[0]; - assign router_15_9_to_router_15_8_rsp = router_15_9_rsp_out[2]; - assign router_15_9_to_router_14_9_rsp = router_15_9_rsp_out[3]; - assign router_15_9_to_magia_tile_ni_15_9_rsp = router_15_9_rsp_out[4]; - - assign router_15_9_to_router_15_10_req = router_15_9_req_out[0]; - assign router_15_9_to_router_15_8_req = router_15_9_req_out[2]; - assign router_15_9_to_router_14_9_req = router_15_9_req_out[3]; - assign router_15_9_to_magia_tile_ni_15_9_req = router_15_9_req_out[4]; - - assign router_15_9_rsp_in[0] = router_15_10_to_router_15_9_rsp; - assign router_15_9_rsp_in[1] = '0; - assign router_15_9_rsp_in[2] = router_15_8_to_router_15_9_rsp; - assign router_15_9_rsp_in[3] = router_14_9_to_router_15_9_rsp; - assign router_15_9_rsp_in[4] = magia_tile_ni_15_9_to_router_15_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_9_req_in), - .floo_rsp_o (router_15_9_rsp_out), - .floo_req_o (router_15_9_req_out), - .floo_rsp_i (router_15_9_rsp_in) -); - - -floo_req_t [4:0] router_15_10_req_in; -floo_rsp_t [4:0] router_15_10_rsp_out; -floo_req_t [4:0] router_15_10_req_out; -floo_rsp_t [4:0] router_15_10_rsp_in; - - assign router_15_10_req_in[0] = router_15_11_to_router_15_10_req; - assign router_15_10_req_in[1] = '0; - assign router_15_10_req_in[2] = router_15_9_to_router_15_10_req; - assign router_15_10_req_in[3] = router_14_10_to_router_15_10_req; - assign router_15_10_req_in[4] = magia_tile_ni_15_10_to_router_15_10_req; - - assign router_15_10_to_router_15_11_rsp = router_15_10_rsp_out[0]; - assign router_15_10_to_router_15_9_rsp = router_15_10_rsp_out[2]; - assign router_15_10_to_router_14_10_rsp = router_15_10_rsp_out[3]; - assign router_15_10_to_magia_tile_ni_15_10_rsp = router_15_10_rsp_out[4]; - - assign router_15_10_to_router_15_11_req = router_15_10_req_out[0]; - assign router_15_10_to_router_15_9_req = router_15_10_req_out[2]; - assign router_15_10_to_router_14_10_req = router_15_10_req_out[3]; - assign router_15_10_to_magia_tile_ni_15_10_req = router_15_10_req_out[4]; - - assign router_15_10_rsp_in[0] = router_15_11_to_router_15_10_rsp; - assign router_15_10_rsp_in[1] = '0; - assign router_15_10_rsp_in[2] = router_15_9_to_router_15_10_rsp; - assign router_15_10_rsp_in[3] = router_14_10_to_router_15_10_rsp; - assign router_15_10_rsp_in[4] = magia_tile_ni_15_10_to_router_15_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_10_req_in), - .floo_rsp_o (router_15_10_rsp_out), - .floo_req_o (router_15_10_req_out), - .floo_rsp_i (router_15_10_rsp_in) -); - - -floo_req_t [4:0] router_15_11_req_in; -floo_rsp_t [4:0] router_15_11_rsp_out; -floo_req_t [4:0] router_15_11_req_out; -floo_rsp_t [4:0] router_15_11_rsp_in; - - assign router_15_11_req_in[0] = router_15_12_to_router_15_11_req; - assign router_15_11_req_in[1] = '0; - assign router_15_11_req_in[2] = router_15_10_to_router_15_11_req; - assign router_15_11_req_in[3] = router_14_11_to_router_15_11_req; - assign router_15_11_req_in[4] = magia_tile_ni_15_11_to_router_15_11_req; - - assign router_15_11_to_router_15_12_rsp = router_15_11_rsp_out[0]; - assign router_15_11_to_router_15_10_rsp = router_15_11_rsp_out[2]; - assign router_15_11_to_router_14_11_rsp = router_15_11_rsp_out[3]; - assign router_15_11_to_magia_tile_ni_15_11_rsp = router_15_11_rsp_out[4]; - - assign router_15_11_to_router_15_12_req = router_15_11_req_out[0]; - assign router_15_11_to_router_15_10_req = router_15_11_req_out[2]; - assign router_15_11_to_router_14_11_req = router_15_11_req_out[3]; - assign router_15_11_to_magia_tile_ni_15_11_req = router_15_11_req_out[4]; - - assign router_15_11_rsp_in[0] = router_15_12_to_router_15_11_rsp; - assign router_15_11_rsp_in[1] = '0; - assign router_15_11_rsp_in[2] = router_15_10_to_router_15_11_rsp; - assign router_15_11_rsp_in[3] = router_14_11_to_router_15_11_rsp; - assign router_15_11_rsp_in[4] = magia_tile_ni_15_11_to_router_15_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_11_req_in), - .floo_rsp_o (router_15_11_rsp_out), - .floo_req_o (router_15_11_req_out), - .floo_rsp_i (router_15_11_rsp_in) -); - - -floo_req_t [4:0] router_15_12_req_in; -floo_rsp_t [4:0] router_15_12_rsp_out; -floo_req_t [4:0] router_15_12_req_out; -floo_rsp_t [4:0] router_15_12_rsp_in; - - assign router_15_12_req_in[0] = router_15_13_to_router_15_12_req; - assign router_15_12_req_in[1] = '0; - assign router_15_12_req_in[2] = router_15_11_to_router_15_12_req; - assign router_15_12_req_in[3] = router_14_12_to_router_15_12_req; - assign router_15_12_req_in[4] = magia_tile_ni_15_12_to_router_15_12_req; - - assign router_15_12_to_router_15_13_rsp = router_15_12_rsp_out[0]; - assign router_15_12_to_router_15_11_rsp = router_15_12_rsp_out[2]; - assign router_15_12_to_router_14_12_rsp = router_15_12_rsp_out[3]; - assign router_15_12_to_magia_tile_ni_15_12_rsp = router_15_12_rsp_out[4]; - - assign router_15_12_to_router_15_13_req = router_15_12_req_out[0]; - assign router_15_12_to_router_15_11_req = router_15_12_req_out[2]; - assign router_15_12_to_router_14_12_req = router_15_12_req_out[3]; - assign router_15_12_to_magia_tile_ni_15_12_req = router_15_12_req_out[4]; - - assign router_15_12_rsp_in[0] = router_15_13_to_router_15_12_rsp; - assign router_15_12_rsp_in[1] = '0; - assign router_15_12_rsp_in[2] = router_15_11_to_router_15_12_rsp; - assign router_15_12_rsp_in[3] = router_14_12_to_router_15_12_rsp; - assign router_15_12_rsp_in[4] = magia_tile_ni_15_12_to_router_15_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_12_req_in), - .floo_rsp_o (router_15_12_rsp_out), - .floo_req_o (router_15_12_req_out), - .floo_rsp_i (router_15_12_rsp_in) -); - - -floo_req_t [4:0] router_15_13_req_in; -floo_rsp_t [4:0] router_15_13_rsp_out; -floo_req_t [4:0] router_15_13_req_out; -floo_rsp_t [4:0] router_15_13_rsp_in; - - assign router_15_13_req_in[0] = router_15_14_to_router_15_13_req; - assign router_15_13_req_in[1] = '0; - assign router_15_13_req_in[2] = router_15_12_to_router_15_13_req; - assign router_15_13_req_in[3] = router_14_13_to_router_15_13_req; - assign router_15_13_req_in[4] = magia_tile_ni_15_13_to_router_15_13_req; - - assign router_15_13_to_router_15_14_rsp = router_15_13_rsp_out[0]; - assign router_15_13_to_router_15_12_rsp = router_15_13_rsp_out[2]; - assign router_15_13_to_router_14_13_rsp = router_15_13_rsp_out[3]; - assign router_15_13_to_magia_tile_ni_15_13_rsp = router_15_13_rsp_out[4]; - - assign router_15_13_to_router_15_14_req = router_15_13_req_out[0]; - assign router_15_13_to_router_15_12_req = router_15_13_req_out[2]; - assign router_15_13_to_router_14_13_req = router_15_13_req_out[3]; - assign router_15_13_to_magia_tile_ni_15_13_req = router_15_13_req_out[4]; - - assign router_15_13_rsp_in[0] = router_15_14_to_router_15_13_rsp; - assign router_15_13_rsp_in[1] = '0; - assign router_15_13_rsp_in[2] = router_15_12_to_router_15_13_rsp; - assign router_15_13_rsp_in[3] = router_14_13_to_router_15_13_rsp; - assign router_15_13_rsp_in[4] = magia_tile_ni_15_13_to_router_15_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_13_req_in), - .floo_rsp_o (router_15_13_rsp_out), - .floo_req_o (router_15_13_req_out), - .floo_rsp_i (router_15_13_rsp_in) -); - - -floo_req_t [4:0] router_15_14_req_in; -floo_rsp_t [4:0] router_15_14_rsp_out; -floo_req_t [4:0] router_15_14_req_out; -floo_rsp_t [4:0] router_15_14_rsp_in; - - assign router_15_14_req_in[0] = router_15_15_to_router_15_14_req; - assign router_15_14_req_in[1] = '0; - assign router_15_14_req_in[2] = router_15_13_to_router_15_14_req; - assign router_15_14_req_in[3] = router_14_14_to_router_15_14_req; - assign router_15_14_req_in[4] = magia_tile_ni_15_14_to_router_15_14_req; - - assign router_15_14_to_router_15_15_rsp = router_15_14_rsp_out[0]; - assign router_15_14_to_router_15_13_rsp = router_15_14_rsp_out[2]; - assign router_15_14_to_router_14_14_rsp = router_15_14_rsp_out[3]; - assign router_15_14_to_magia_tile_ni_15_14_rsp = router_15_14_rsp_out[4]; - - assign router_15_14_to_router_15_15_req = router_15_14_req_out[0]; - assign router_15_14_to_router_15_13_req = router_15_14_req_out[2]; - assign router_15_14_to_router_14_14_req = router_15_14_req_out[3]; - assign router_15_14_to_magia_tile_ni_15_14_req = router_15_14_req_out[4]; - - assign router_15_14_rsp_in[0] = router_15_15_to_router_15_14_rsp; - assign router_15_14_rsp_in[1] = '0; - assign router_15_14_rsp_in[2] = router_15_13_to_router_15_14_rsp; - assign router_15_14_rsp_in[3] = router_14_14_to_router_15_14_rsp; - assign router_15_14_rsp_in[4] = magia_tile_ni_15_14_to_router_15_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_14_req_in), - .floo_rsp_o (router_15_14_rsp_out), - .floo_req_o (router_15_14_req_out), - .floo_rsp_i (router_15_14_rsp_in) -); - - -floo_req_t [4:0] router_15_15_req_in; -floo_rsp_t [4:0] router_15_15_rsp_out; -floo_req_t [4:0] router_15_15_req_out; -floo_rsp_t [4:0] router_15_15_rsp_in; - - assign router_15_15_req_in[0] = '0; - assign router_15_15_req_in[1] = '0; - assign router_15_15_req_in[2] = router_15_14_to_router_15_15_req; - assign router_15_15_req_in[3] = router_14_15_to_router_15_15_req; - assign router_15_15_req_in[4] = magia_tile_ni_15_15_to_router_15_15_req; - - assign router_15_15_to_router_15_14_rsp = router_15_15_rsp_out[2]; - assign router_15_15_to_router_14_15_rsp = router_15_15_rsp_out[3]; - assign router_15_15_to_magia_tile_ni_15_15_rsp = router_15_15_rsp_out[4]; - - assign router_15_15_to_router_15_14_req = router_15_15_req_out[2]; - assign router_15_15_to_router_14_15_req = router_15_15_req_out[3]; - assign router_15_15_to_magia_tile_ni_15_15_req = router_15_15_req_out[4]; - - assign router_15_15_rsp_in[0] = '0; - assign router_15_15_rsp_in[1] = '0; - assign router_15_15_rsp_in[2] = router_15_14_to_router_15_15_rsp; - assign router_15_15_rsp_in[3] = router_14_15_to_router_15_15_rsp; - assign router_15_15_rsp_in[4] = magia_tile_ni_15_15_to_router_15_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_15_req_in), - .floo_rsp_o (router_15_15_rsp_out), - .floo_req_o (router_15_15_req_out), - .floo_rsp_i (router_15_15_rsp_in) -); - - - -endmodule diff --git a/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv b/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv index aee373c..a1a73f3 100644 --- a/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv +++ b/hw/mesh/noc/floo_axi_mesh_2x2_noc.sv @@ -97,481 +97,3 @@ typedef logic[0:0] axi_data_slv_user_t; endpackage - -module floo_axi_mesh_2x2_noc - import floo_pkg::*; - import floo_axi_mesh_2x2_noc_pkg::*; -( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input axi_data_slv_req_t [1:0][1:0] magia_tile_data_slv_req_i, - output axi_data_slv_rsp_t [1:0][1:0] magia_tile_data_slv_rsp_o, - output axi_data_mst_req_t [1:0][1:0] magia_tile_data_mst_req_o, - input axi_data_mst_rsp_t [1:0][1:0] magia_tile_data_mst_rsp_i, - output axi_data_mst_req_t [1:0] L2_data_mst_req_o, - input axi_data_mst_rsp_t [1:0] L2_data_mst_rsp_i - -); - -floo_req_t router_0_0_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_0_rsp; - -floo_req_t router_0_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_magia_tile_ni_0_0_req; -floo_rsp_t magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_L2_ni_0_req; -floo_rsp_t L2_ni_0_to_router_0_0_rsp; - -floo_req_t router_0_1_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_magia_tile_ni_0_1_req; -floo_rsp_t magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_L2_ni_1_req; -floo_rsp_t L2_ni_1_to_router_0_1_rsp; - -floo_req_t router_1_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_0_rsp; - -floo_req_t router_1_0_to_magia_tile_ni_1_0_req; -floo_rsp_t magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_req_t router_1_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_1_1_rsp; - -floo_req_t router_1_1_to_magia_tile_ni_1_1_req; -floo_rsp_t magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_req_t magia_tile_ni_0_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_magia_tile_ni_0_0_rsp; - -floo_req_t magia_tile_ni_0_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_magia_tile_ni_0_1_rsp; - -floo_req_t magia_tile_ni_1_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_magia_tile_ni_1_0_rsp; - -floo_req_t magia_tile_ni_1_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_magia_tile_ni_1_1_rsp; - -floo_req_t L2_ni_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_L2_ni_0_rsp; - -floo_req_t L2_ni_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_L2_ni_1_rsp; - - - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][0] ), - .id_i ( '{x: 1, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_magia_tile_ni_0_0_rsp ), - .floo_req_i ( router_0_0_to_magia_tile_ni_0_0_req ), - .floo_rsp_o ( magia_tile_ni_0_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][1] ), - .id_i ( '{x: 1, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_magia_tile_ni_0_1_rsp ), - .floo_req_i ( router_0_1_to_magia_tile_ni_0_1_req ), - .floo_rsp_o ( magia_tile_ni_0_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][0] ), - .id_i ( '{x: 2, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_0_to_router_1_0_req ), - .floo_rsp_i ( router_1_0_to_magia_tile_ni_1_0_rsp ), - .floo_req_i ( router_1_0_to_magia_tile_ni_1_0_req ), - .floo_rsp_o ( magia_tile_ni_1_0_to_router_1_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][1] ), - .id_i ( '{x: 2, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_1_to_router_1_1_req ), - .floo_rsp_i ( router_1_1_to_magia_tile_ni_1_1_rsp ), - .floo_req_i ( router_1_1_to_magia_tile_ni_1_1_req ), - .floo_rsp_o ( magia_tile_ni_1_1_to_router_1_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[0] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[0] ), - .id_i ( '{x: 0, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_L2_ni_0_rsp ), - .floo_req_i ( router_0_0_to_L2_ni_0_req ), - .floo_rsp_o ( L2_ni_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[1] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[1] ), - .id_i ( '{x: 0, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_L2_ni_1_rsp ), - .floo_req_i ( router_0_1_to_L2_ni_1_req ), - .floo_rsp_o ( L2_ni_1_to_router_0_1_rsp ) -); - - -floo_req_t [4:0] router_0_0_req_in; -floo_rsp_t [4:0] router_0_0_rsp_out; -floo_req_t [4:0] router_0_0_req_out; -floo_rsp_t [4:0] router_0_0_rsp_in; - - assign router_0_0_req_in[0] = router_0_1_to_router_0_0_req; - assign router_0_0_req_in[1] = router_1_0_to_router_0_0_req; - assign router_0_0_req_in[2] = '0; - assign router_0_0_req_in[3] = L2_ni_0_to_router_0_0_req; - assign router_0_0_req_in[4] = magia_tile_ni_0_0_to_router_0_0_req; - - assign router_0_0_to_router_0_1_rsp = router_0_0_rsp_out[0]; - assign router_0_0_to_router_1_0_rsp = router_0_0_rsp_out[1]; - assign router_0_0_to_L2_ni_0_rsp = router_0_0_rsp_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_rsp = router_0_0_rsp_out[4]; - - assign router_0_0_to_router_0_1_req = router_0_0_req_out[0]; - assign router_0_0_to_router_1_0_req = router_0_0_req_out[1]; - assign router_0_0_to_L2_ni_0_req = router_0_0_req_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_req = router_0_0_req_out[4]; - - assign router_0_0_rsp_in[0] = router_0_1_to_router_0_0_rsp; - assign router_0_0_rsp_in[1] = router_1_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[2] = '0; - assign router_0_0_rsp_in[3] = L2_ni_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[4] = magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_0_req_in), - .floo_rsp_o (router_0_0_rsp_out), - .floo_req_o (router_0_0_req_out), - .floo_rsp_i (router_0_0_rsp_in) -); - - -floo_req_t [4:0] router_0_1_req_in; -floo_rsp_t [4:0] router_0_1_rsp_out; -floo_req_t [4:0] router_0_1_req_out; -floo_rsp_t [4:0] router_0_1_rsp_in; - - assign router_0_1_req_in[0] = '0; - assign router_0_1_req_in[1] = router_1_1_to_router_0_1_req; - assign router_0_1_req_in[2] = router_0_0_to_router_0_1_req; - assign router_0_1_req_in[3] = L2_ni_1_to_router_0_1_req; - assign router_0_1_req_in[4] = magia_tile_ni_0_1_to_router_0_1_req; - - assign router_0_1_to_router_1_1_rsp = router_0_1_rsp_out[1]; - assign router_0_1_to_router_0_0_rsp = router_0_1_rsp_out[2]; - assign router_0_1_to_L2_ni_1_rsp = router_0_1_rsp_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_rsp = router_0_1_rsp_out[4]; - - assign router_0_1_to_router_1_1_req = router_0_1_req_out[1]; - assign router_0_1_to_router_0_0_req = router_0_1_req_out[2]; - assign router_0_1_to_L2_ni_1_req = router_0_1_req_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_req = router_0_1_req_out[4]; - - assign router_0_1_rsp_in[0] = '0; - assign router_0_1_rsp_in[1] = router_1_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[2] = router_0_0_to_router_0_1_rsp; - assign router_0_1_rsp_in[3] = L2_ni_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[4] = magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_1_req_in), - .floo_rsp_o (router_0_1_rsp_out), - .floo_req_o (router_0_1_req_out), - .floo_rsp_i (router_0_1_rsp_in) -); - - -floo_req_t [4:0] router_1_0_req_in; -floo_rsp_t [4:0] router_1_0_rsp_out; -floo_req_t [4:0] router_1_0_req_out; -floo_rsp_t [4:0] router_1_0_rsp_in; - - assign router_1_0_req_in[0] = router_1_1_to_router_1_0_req; - assign router_1_0_req_in[1] = '0; - assign router_1_0_req_in[2] = '0; - assign router_1_0_req_in[3] = router_0_0_to_router_1_0_req; - assign router_1_0_req_in[4] = magia_tile_ni_1_0_to_router_1_0_req; - - assign router_1_0_to_router_1_1_rsp = router_1_0_rsp_out[0]; - assign router_1_0_to_router_0_0_rsp = router_1_0_rsp_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_rsp = router_1_0_rsp_out[4]; - - assign router_1_0_to_router_1_1_req = router_1_0_req_out[0]; - assign router_1_0_to_router_0_0_req = router_1_0_req_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_req = router_1_0_req_out[4]; - - assign router_1_0_rsp_in[0] = router_1_1_to_router_1_0_rsp; - assign router_1_0_rsp_in[1] = '0; - assign router_1_0_rsp_in[2] = '0; - assign router_1_0_rsp_in[3] = router_0_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[4] = magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_0_req_in), - .floo_rsp_o (router_1_0_rsp_out), - .floo_req_o (router_1_0_req_out), - .floo_rsp_i (router_1_0_rsp_in) -); - - -floo_req_t [4:0] router_1_1_req_in; -floo_rsp_t [4:0] router_1_1_rsp_out; -floo_req_t [4:0] router_1_1_req_out; -floo_rsp_t [4:0] router_1_1_rsp_in; - - assign router_1_1_req_in[0] = '0; - assign router_1_1_req_in[1] = '0; - assign router_1_1_req_in[2] = router_1_0_to_router_1_1_req; - assign router_1_1_req_in[3] = router_0_1_to_router_1_1_req; - assign router_1_1_req_in[4] = magia_tile_ni_1_1_to_router_1_1_req; - - assign router_1_1_to_router_1_0_rsp = router_1_1_rsp_out[2]; - assign router_1_1_to_router_0_1_rsp = router_1_1_rsp_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_rsp = router_1_1_rsp_out[4]; - - assign router_1_1_to_router_1_0_req = router_1_1_req_out[2]; - assign router_1_1_to_router_0_1_req = router_1_1_req_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_req = router_1_1_req_out[4]; - - assign router_1_1_rsp_in[0] = '0; - assign router_1_1_rsp_in[1] = '0; - assign router_1_1_rsp_in[2] = router_1_0_to_router_1_1_rsp; - assign router_1_1_rsp_in[3] = router_0_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[4] = magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_1_req_in), - .floo_rsp_o (router_1_1_rsp_out), - .floo_req_o (router_1_1_req_out), - .floo_rsp_i (router_1_1_rsp_in) -); - - - -endmodule diff --git a/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv b/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv index 66305f8..05e14d1 100644 --- a/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv +++ b/hw/mesh/noc/floo_axi_mesh_32x32_noc.sv @@ -2197,107161 +2197,3 @@ typedef logic[0:0] axi_data_slv_user_t; endpackage - -module floo_axi_mesh_32x32_noc - import floo_pkg::*; - import floo_axi_mesh_32x32_noc_pkg::*; -( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input axi_data_slv_req_t [31:0][31:0] magia_tile_data_slv_req_i, - output axi_data_slv_rsp_t [31:0][31:0] magia_tile_data_slv_rsp_o, - output axi_data_mst_req_t [31:0][31:0] magia_tile_data_mst_req_o, - input axi_data_mst_rsp_t [31:0][31:0] magia_tile_data_mst_rsp_i, - output axi_data_mst_req_t [31:0] L2_data_mst_req_o, - input axi_data_mst_rsp_t [31:0] L2_data_mst_rsp_i - -); - -floo_req_t router_0_0_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_0_rsp; - -floo_req_t router_0_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_magia_tile_ni_0_0_req; -floo_rsp_t magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_L2_ni_0_req; -floo_rsp_t L2_ni_0_to_router_0_0_rsp; - -floo_req_t router_0_1_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_magia_tile_ni_0_1_req; -floo_rsp_t magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_L2_ni_1_req; -floo_rsp_t L2_ni_1_to_router_0_1_rsp; - -floo_req_t router_0_2_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_magia_tile_ni_0_2_req; -floo_rsp_t magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_L2_ni_2_req; -floo_rsp_t L2_ni_2_to_router_0_2_rsp; - -floo_req_t router_0_3_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_magia_tile_ni_0_3_req; -floo_rsp_t magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_L2_ni_3_req; -floo_rsp_t L2_ni_3_to_router_0_3_rsp; - -floo_req_t router_0_4_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_magia_tile_ni_0_4_req; -floo_rsp_t magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_L2_ni_4_req; -floo_rsp_t L2_ni_4_to_router_0_4_rsp; - -floo_req_t router_0_5_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_magia_tile_ni_0_5_req; -floo_rsp_t magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_L2_ni_5_req; -floo_rsp_t L2_ni_5_to_router_0_5_rsp; - -floo_req_t router_0_6_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_magia_tile_ni_0_6_req; -floo_rsp_t magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_L2_ni_6_req; -floo_rsp_t L2_ni_6_to_router_0_6_rsp; - -floo_req_t router_0_7_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_7_rsp; - -floo_req_t router_0_7_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_0_7_rsp; - -floo_req_t router_0_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_magia_tile_ni_0_7_req; -floo_rsp_t magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_L2_ni_7_req; -floo_rsp_t L2_ni_7_to_router_0_7_rsp; - -floo_req_t router_0_8_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_0_8_rsp; - -floo_req_t router_0_8_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_0_8_rsp; - -floo_req_t router_0_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_0_8_rsp; - -floo_req_t router_0_8_to_magia_tile_ni_0_8_req; -floo_rsp_t magia_tile_ni_0_8_to_router_0_8_rsp; - -floo_req_t router_0_8_to_L2_ni_8_req; -floo_rsp_t L2_ni_8_to_router_0_8_rsp; - -floo_req_t router_0_9_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_0_9_rsp; - -floo_req_t router_0_9_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_0_9_rsp; - -floo_req_t router_0_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_0_9_rsp; - -floo_req_t router_0_9_to_magia_tile_ni_0_9_req; -floo_rsp_t magia_tile_ni_0_9_to_router_0_9_rsp; - -floo_req_t router_0_9_to_L2_ni_9_req; -floo_rsp_t L2_ni_9_to_router_0_9_rsp; - -floo_req_t router_0_10_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_0_10_rsp; - -floo_req_t router_0_10_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_0_10_rsp; - -floo_req_t router_0_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_0_10_rsp; - -floo_req_t router_0_10_to_magia_tile_ni_0_10_req; -floo_rsp_t magia_tile_ni_0_10_to_router_0_10_rsp; - -floo_req_t router_0_10_to_L2_ni_10_req; -floo_rsp_t L2_ni_10_to_router_0_10_rsp; - -floo_req_t router_0_11_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_0_11_rsp; - -floo_req_t router_0_11_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_0_11_rsp; - -floo_req_t router_0_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_0_11_rsp; - -floo_req_t router_0_11_to_magia_tile_ni_0_11_req; -floo_rsp_t magia_tile_ni_0_11_to_router_0_11_rsp; - -floo_req_t router_0_11_to_L2_ni_11_req; -floo_rsp_t L2_ni_11_to_router_0_11_rsp; - -floo_req_t router_0_12_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_0_12_rsp; - -floo_req_t router_0_12_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_0_12_rsp; - -floo_req_t router_0_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_0_12_rsp; - -floo_req_t router_0_12_to_magia_tile_ni_0_12_req; -floo_rsp_t magia_tile_ni_0_12_to_router_0_12_rsp; - -floo_req_t router_0_12_to_L2_ni_12_req; -floo_rsp_t L2_ni_12_to_router_0_12_rsp; - -floo_req_t router_0_13_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_0_13_rsp; - -floo_req_t router_0_13_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_0_13_rsp; - -floo_req_t router_0_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_0_13_rsp; - -floo_req_t router_0_13_to_magia_tile_ni_0_13_req; -floo_rsp_t magia_tile_ni_0_13_to_router_0_13_rsp; - -floo_req_t router_0_13_to_L2_ni_13_req; -floo_rsp_t L2_ni_13_to_router_0_13_rsp; - -floo_req_t router_0_14_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_0_14_rsp; - -floo_req_t router_0_14_to_router_0_15_req; -floo_rsp_t router_0_15_to_router_0_14_rsp; - -floo_req_t router_0_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_0_14_rsp; - -floo_req_t router_0_14_to_magia_tile_ni_0_14_req; -floo_rsp_t magia_tile_ni_0_14_to_router_0_14_rsp; - -floo_req_t router_0_14_to_L2_ni_14_req; -floo_rsp_t L2_ni_14_to_router_0_14_rsp; - -floo_req_t router_0_15_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_0_15_rsp; - -floo_req_t router_0_15_to_router_0_16_req; -floo_rsp_t router_0_16_to_router_0_15_rsp; - -floo_req_t router_0_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_0_15_rsp; - -floo_req_t router_0_15_to_magia_tile_ni_0_15_req; -floo_rsp_t magia_tile_ni_0_15_to_router_0_15_rsp; - -floo_req_t router_0_15_to_L2_ni_15_req; -floo_rsp_t L2_ni_15_to_router_0_15_rsp; - -floo_req_t router_0_16_to_router_0_15_req; -floo_rsp_t router_0_15_to_router_0_16_rsp; - -floo_req_t router_0_16_to_router_0_17_req; -floo_rsp_t router_0_17_to_router_0_16_rsp; - -floo_req_t router_0_16_to_router_1_16_req; -floo_rsp_t router_1_16_to_router_0_16_rsp; - -floo_req_t router_0_16_to_magia_tile_ni_0_16_req; -floo_rsp_t magia_tile_ni_0_16_to_router_0_16_rsp; - -floo_req_t router_0_16_to_L2_ni_16_req; -floo_rsp_t L2_ni_16_to_router_0_16_rsp; - -floo_req_t router_0_17_to_router_0_16_req; -floo_rsp_t router_0_16_to_router_0_17_rsp; - -floo_req_t router_0_17_to_router_0_18_req; -floo_rsp_t router_0_18_to_router_0_17_rsp; - -floo_req_t router_0_17_to_router_1_17_req; -floo_rsp_t router_1_17_to_router_0_17_rsp; - -floo_req_t router_0_17_to_magia_tile_ni_0_17_req; -floo_rsp_t magia_tile_ni_0_17_to_router_0_17_rsp; - -floo_req_t router_0_17_to_L2_ni_17_req; -floo_rsp_t L2_ni_17_to_router_0_17_rsp; - -floo_req_t router_0_18_to_router_0_17_req; -floo_rsp_t router_0_17_to_router_0_18_rsp; - -floo_req_t router_0_18_to_router_0_19_req; -floo_rsp_t router_0_19_to_router_0_18_rsp; - -floo_req_t router_0_18_to_router_1_18_req; -floo_rsp_t router_1_18_to_router_0_18_rsp; - -floo_req_t router_0_18_to_magia_tile_ni_0_18_req; -floo_rsp_t magia_tile_ni_0_18_to_router_0_18_rsp; - -floo_req_t router_0_18_to_L2_ni_18_req; -floo_rsp_t L2_ni_18_to_router_0_18_rsp; - -floo_req_t router_0_19_to_router_0_18_req; -floo_rsp_t router_0_18_to_router_0_19_rsp; - -floo_req_t router_0_19_to_router_0_20_req; -floo_rsp_t router_0_20_to_router_0_19_rsp; - -floo_req_t router_0_19_to_router_1_19_req; -floo_rsp_t router_1_19_to_router_0_19_rsp; - -floo_req_t router_0_19_to_magia_tile_ni_0_19_req; -floo_rsp_t magia_tile_ni_0_19_to_router_0_19_rsp; - -floo_req_t router_0_19_to_L2_ni_19_req; -floo_rsp_t L2_ni_19_to_router_0_19_rsp; - -floo_req_t router_0_20_to_router_0_19_req; -floo_rsp_t router_0_19_to_router_0_20_rsp; - -floo_req_t router_0_20_to_router_0_21_req; -floo_rsp_t router_0_21_to_router_0_20_rsp; - -floo_req_t router_0_20_to_router_1_20_req; -floo_rsp_t router_1_20_to_router_0_20_rsp; - -floo_req_t router_0_20_to_magia_tile_ni_0_20_req; -floo_rsp_t magia_tile_ni_0_20_to_router_0_20_rsp; - -floo_req_t router_0_20_to_L2_ni_20_req; -floo_rsp_t L2_ni_20_to_router_0_20_rsp; - -floo_req_t router_0_21_to_router_0_20_req; -floo_rsp_t router_0_20_to_router_0_21_rsp; - -floo_req_t router_0_21_to_router_0_22_req; -floo_rsp_t router_0_22_to_router_0_21_rsp; - -floo_req_t router_0_21_to_router_1_21_req; -floo_rsp_t router_1_21_to_router_0_21_rsp; - -floo_req_t router_0_21_to_magia_tile_ni_0_21_req; -floo_rsp_t magia_tile_ni_0_21_to_router_0_21_rsp; - -floo_req_t router_0_21_to_L2_ni_21_req; -floo_rsp_t L2_ni_21_to_router_0_21_rsp; - -floo_req_t router_0_22_to_router_0_21_req; -floo_rsp_t router_0_21_to_router_0_22_rsp; - -floo_req_t router_0_22_to_router_0_23_req; -floo_rsp_t router_0_23_to_router_0_22_rsp; - -floo_req_t router_0_22_to_router_1_22_req; -floo_rsp_t router_1_22_to_router_0_22_rsp; - -floo_req_t router_0_22_to_magia_tile_ni_0_22_req; -floo_rsp_t magia_tile_ni_0_22_to_router_0_22_rsp; - -floo_req_t router_0_22_to_L2_ni_22_req; -floo_rsp_t L2_ni_22_to_router_0_22_rsp; - -floo_req_t router_0_23_to_router_0_22_req; -floo_rsp_t router_0_22_to_router_0_23_rsp; - -floo_req_t router_0_23_to_router_0_24_req; -floo_rsp_t router_0_24_to_router_0_23_rsp; - -floo_req_t router_0_23_to_router_1_23_req; -floo_rsp_t router_1_23_to_router_0_23_rsp; - -floo_req_t router_0_23_to_magia_tile_ni_0_23_req; -floo_rsp_t magia_tile_ni_0_23_to_router_0_23_rsp; - -floo_req_t router_0_23_to_L2_ni_23_req; -floo_rsp_t L2_ni_23_to_router_0_23_rsp; - -floo_req_t router_0_24_to_router_0_23_req; -floo_rsp_t router_0_23_to_router_0_24_rsp; - -floo_req_t router_0_24_to_router_0_25_req; -floo_rsp_t router_0_25_to_router_0_24_rsp; - -floo_req_t router_0_24_to_router_1_24_req; -floo_rsp_t router_1_24_to_router_0_24_rsp; - -floo_req_t router_0_24_to_magia_tile_ni_0_24_req; -floo_rsp_t magia_tile_ni_0_24_to_router_0_24_rsp; - -floo_req_t router_0_24_to_L2_ni_24_req; -floo_rsp_t L2_ni_24_to_router_0_24_rsp; - -floo_req_t router_0_25_to_router_0_24_req; -floo_rsp_t router_0_24_to_router_0_25_rsp; - -floo_req_t router_0_25_to_router_0_26_req; -floo_rsp_t router_0_26_to_router_0_25_rsp; - -floo_req_t router_0_25_to_router_1_25_req; -floo_rsp_t router_1_25_to_router_0_25_rsp; - -floo_req_t router_0_25_to_magia_tile_ni_0_25_req; -floo_rsp_t magia_tile_ni_0_25_to_router_0_25_rsp; - -floo_req_t router_0_25_to_L2_ni_25_req; -floo_rsp_t L2_ni_25_to_router_0_25_rsp; - -floo_req_t router_0_26_to_router_0_25_req; -floo_rsp_t router_0_25_to_router_0_26_rsp; - -floo_req_t router_0_26_to_router_0_27_req; -floo_rsp_t router_0_27_to_router_0_26_rsp; - -floo_req_t router_0_26_to_router_1_26_req; -floo_rsp_t router_1_26_to_router_0_26_rsp; - -floo_req_t router_0_26_to_magia_tile_ni_0_26_req; -floo_rsp_t magia_tile_ni_0_26_to_router_0_26_rsp; - -floo_req_t router_0_26_to_L2_ni_26_req; -floo_rsp_t L2_ni_26_to_router_0_26_rsp; - -floo_req_t router_0_27_to_router_0_26_req; -floo_rsp_t router_0_26_to_router_0_27_rsp; - -floo_req_t router_0_27_to_router_0_28_req; -floo_rsp_t router_0_28_to_router_0_27_rsp; - -floo_req_t router_0_27_to_router_1_27_req; -floo_rsp_t router_1_27_to_router_0_27_rsp; - -floo_req_t router_0_27_to_magia_tile_ni_0_27_req; -floo_rsp_t magia_tile_ni_0_27_to_router_0_27_rsp; - -floo_req_t router_0_27_to_L2_ni_27_req; -floo_rsp_t L2_ni_27_to_router_0_27_rsp; - -floo_req_t router_0_28_to_router_0_27_req; -floo_rsp_t router_0_27_to_router_0_28_rsp; - -floo_req_t router_0_28_to_router_0_29_req; -floo_rsp_t router_0_29_to_router_0_28_rsp; - -floo_req_t router_0_28_to_router_1_28_req; -floo_rsp_t router_1_28_to_router_0_28_rsp; - -floo_req_t router_0_28_to_magia_tile_ni_0_28_req; -floo_rsp_t magia_tile_ni_0_28_to_router_0_28_rsp; - -floo_req_t router_0_28_to_L2_ni_28_req; -floo_rsp_t L2_ni_28_to_router_0_28_rsp; - -floo_req_t router_0_29_to_router_0_28_req; -floo_rsp_t router_0_28_to_router_0_29_rsp; - -floo_req_t router_0_29_to_router_0_30_req; -floo_rsp_t router_0_30_to_router_0_29_rsp; - -floo_req_t router_0_29_to_router_1_29_req; -floo_rsp_t router_1_29_to_router_0_29_rsp; - -floo_req_t router_0_29_to_magia_tile_ni_0_29_req; -floo_rsp_t magia_tile_ni_0_29_to_router_0_29_rsp; - -floo_req_t router_0_29_to_L2_ni_29_req; -floo_rsp_t L2_ni_29_to_router_0_29_rsp; - -floo_req_t router_0_30_to_router_0_29_req; -floo_rsp_t router_0_29_to_router_0_30_rsp; - -floo_req_t router_0_30_to_router_0_31_req; -floo_rsp_t router_0_31_to_router_0_30_rsp; - -floo_req_t router_0_30_to_router_1_30_req; -floo_rsp_t router_1_30_to_router_0_30_rsp; - -floo_req_t router_0_30_to_magia_tile_ni_0_30_req; -floo_rsp_t magia_tile_ni_0_30_to_router_0_30_rsp; - -floo_req_t router_0_30_to_L2_ni_30_req; -floo_rsp_t L2_ni_30_to_router_0_30_rsp; - -floo_req_t router_0_31_to_router_0_30_req; -floo_rsp_t router_0_30_to_router_0_31_rsp; - -floo_req_t router_0_31_to_router_1_31_req; -floo_rsp_t router_1_31_to_router_0_31_rsp; - -floo_req_t router_0_31_to_magia_tile_ni_0_31_req; -floo_rsp_t magia_tile_ni_0_31_to_router_0_31_rsp; - -floo_req_t router_0_31_to_L2_ni_31_req; -floo_rsp_t L2_ni_31_to_router_0_31_rsp; - -floo_req_t router_1_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_magia_tile_ni_1_0_req; -floo_rsp_t magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_req_t router_1_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_magia_tile_ni_1_1_req; -floo_rsp_t magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_req_t router_1_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_magia_tile_ni_1_2_req; -floo_rsp_t magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_req_t router_1_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_magia_tile_ni_1_3_req; -floo_rsp_t magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_req_t router_1_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_magia_tile_ni_1_4_req; -floo_rsp_t magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_req_t router_1_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_magia_tile_ni_1_5_req; -floo_rsp_t magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_req_t router_1_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_magia_tile_ni_1_6_req; -floo_rsp_t magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_req_t router_1_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_magia_tile_ni_1_7_req; -floo_rsp_t magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_req_t router_1_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_1_8_rsp; - -floo_req_t router_1_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_1_8_rsp; - -floo_req_t router_1_8_to_magia_tile_ni_1_8_req; -floo_rsp_t magia_tile_ni_1_8_to_router_1_8_rsp; - -floo_req_t router_1_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_1_9_rsp; - -floo_req_t router_1_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_1_9_rsp; - -floo_req_t router_1_9_to_magia_tile_ni_1_9_req; -floo_rsp_t magia_tile_ni_1_9_to_router_1_9_rsp; - -floo_req_t router_1_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_1_10_rsp; - -floo_req_t router_1_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_1_10_rsp; - -floo_req_t router_1_10_to_magia_tile_ni_1_10_req; -floo_rsp_t magia_tile_ni_1_10_to_router_1_10_rsp; - -floo_req_t router_1_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_1_11_rsp; - -floo_req_t router_1_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_1_11_rsp; - -floo_req_t router_1_11_to_magia_tile_ni_1_11_req; -floo_rsp_t magia_tile_ni_1_11_to_router_1_11_rsp; - -floo_req_t router_1_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_1_12_rsp; - -floo_req_t router_1_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_1_12_rsp; - -floo_req_t router_1_12_to_magia_tile_ni_1_12_req; -floo_rsp_t magia_tile_ni_1_12_to_router_1_12_rsp; - -floo_req_t router_1_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_1_13_rsp; - -floo_req_t router_1_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_1_13_rsp; - -floo_req_t router_1_13_to_magia_tile_ni_1_13_req; -floo_rsp_t magia_tile_ni_1_13_to_router_1_13_rsp; - -floo_req_t router_1_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_1_14_rsp; - -floo_req_t router_1_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_1_14_rsp; - -floo_req_t router_1_14_to_magia_tile_ni_1_14_req; -floo_rsp_t magia_tile_ni_1_14_to_router_1_14_rsp; - -floo_req_t router_1_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_router_1_15_rsp; - -floo_req_t router_1_15_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_1_15_rsp; - -floo_req_t router_1_15_to_router_1_16_req; -floo_rsp_t router_1_16_to_router_1_15_rsp; - -floo_req_t router_1_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_1_15_rsp; - -floo_req_t router_1_15_to_magia_tile_ni_1_15_req; -floo_rsp_t magia_tile_ni_1_15_to_router_1_15_rsp; - -floo_req_t router_1_16_to_router_0_16_req; -floo_rsp_t router_0_16_to_router_1_16_rsp; - -floo_req_t router_1_16_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_1_16_rsp; - -floo_req_t router_1_16_to_router_1_17_req; -floo_rsp_t router_1_17_to_router_1_16_rsp; - -floo_req_t router_1_16_to_router_2_16_req; -floo_rsp_t router_2_16_to_router_1_16_rsp; - -floo_req_t router_1_16_to_magia_tile_ni_1_16_req; -floo_rsp_t magia_tile_ni_1_16_to_router_1_16_rsp; - -floo_req_t router_1_17_to_router_0_17_req; -floo_rsp_t router_0_17_to_router_1_17_rsp; - -floo_req_t router_1_17_to_router_1_16_req; -floo_rsp_t router_1_16_to_router_1_17_rsp; - -floo_req_t router_1_17_to_router_1_18_req; -floo_rsp_t router_1_18_to_router_1_17_rsp; - -floo_req_t router_1_17_to_router_2_17_req; -floo_rsp_t router_2_17_to_router_1_17_rsp; - -floo_req_t router_1_17_to_magia_tile_ni_1_17_req; -floo_rsp_t magia_tile_ni_1_17_to_router_1_17_rsp; - -floo_req_t router_1_18_to_router_0_18_req; -floo_rsp_t router_0_18_to_router_1_18_rsp; - -floo_req_t router_1_18_to_router_1_17_req; -floo_rsp_t router_1_17_to_router_1_18_rsp; - -floo_req_t router_1_18_to_router_1_19_req; -floo_rsp_t router_1_19_to_router_1_18_rsp; - -floo_req_t router_1_18_to_router_2_18_req; -floo_rsp_t router_2_18_to_router_1_18_rsp; - -floo_req_t router_1_18_to_magia_tile_ni_1_18_req; -floo_rsp_t magia_tile_ni_1_18_to_router_1_18_rsp; - -floo_req_t router_1_19_to_router_0_19_req; -floo_rsp_t router_0_19_to_router_1_19_rsp; - -floo_req_t router_1_19_to_router_1_18_req; -floo_rsp_t router_1_18_to_router_1_19_rsp; - -floo_req_t router_1_19_to_router_1_20_req; -floo_rsp_t router_1_20_to_router_1_19_rsp; - -floo_req_t router_1_19_to_router_2_19_req; -floo_rsp_t router_2_19_to_router_1_19_rsp; - -floo_req_t router_1_19_to_magia_tile_ni_1_19_req; -floo_rsp_t magia_tile_ni_1_19_to_router_1_19_rsp; - -floo_req_t router_1_20_to_router_0_20_req; -floo_rsp_t router_0_20_to_router_1_20_rsp; - -floo_req_t router_1_20_to_router_1_19_req; -floo_rsp_t router_1_19_to_router_1_20_rsp; - -floo_req_t router_1_20_to_router_1_21_req; -floo_rsp_t router_1_21_to_router_1_20_rsp; - -floo_req_t router_1_20_to_router_2_20_req; -floo_rsp_t router_2_20_to_router_1_20_rsp; - -floo_req_t router_1_20_to_magia_tile_ni_1_20_req; -floo_rsp_t magia_tile_ni_1_20_to_router_1_20_rsp; - -floo_req_t router_1_21_to_router_0_21_req; -floo_rsp_t router_0_21_to_router_1_21_rsp; - -floo_req_t router_1_21_to_router_1_20_req; -floo_rsp_t router_1_20_to_router_1_21_rsp; - -floo_req_t router_1_21_to_router_1_22_req; -floo_rsp_t router_1_22_to_router_1_21_rsp; - -floo_req_t router_1_21_to_router_2_21_req; -floo_rsp_t router_2_21_to_router_1_21_rsp; - -floo_req_t router_1_21_to_magia_tile_ni_1_21_req; -floo_rsp_t magia_tile_ni_1_21_to_router_1_21_rsp; - -floo_req_t router_1_22_to_router_0_22_req; -floo_rsp_t router_0_22_to_router_1_22_rsp; - -floo_req_t router_1_22_to_router_1_21_req; -floo_rsp_t router_1_21_to_router_1_22_rsp; - -floo_req_t router_1_22_to_router_1_23_req; -floo_rsp_t router_1_23_to_router_1_22_rsp; - -floo_req_t router_1_22_to_router_2_22_req; -floo_rsp_t router_2_22_to_router_1_22_rsp; - -floo_req_t router_1_22_to_magia_tile_ni_1_22_req; -floo_rsp_t magia_tile_ni_1_22_to_router_1_22_rsp; - -floo_req_t router_1_23_to_router_0_23_req; -floo_rsp_t router_0_23_to_router_1_23_rsp; - -floo_req_t router_1_23_to_router_1_22_req; -floo_rsp_t router_1_22_to_router_1_23_rsp; - -floo_req_t router_1_23_to_router_1_24_req; -floo_rsp_t router_1_24_to_router_1_23_rsp; - -floo_req_t router_1_23_to_router_2_23_req; -floo_rsp_t router_2_23_to_router_1_23_rsp; - -floo_req_t router_1_23_to_magia_tile_ni_1_23_req; -floo_rsp_t magia_tile_ni_1_23_to_router_1_23_rsp; - -floo_req_t router_1_24_to_router_0_24_req; -floo_rsp_t router_0_24_to_router_1_24_rsp; - -floo_req_t router_1_24_to_router_1_23_req; -floo_rsp_t router_1_23_to_router_1_24_rsp; - -floo_req_t router_1_24_to_router_1_25_req; -floo_rsp_t router_1_25_to_router_1_24_rsp; - -floo_req_t router_1_24_to_router_2_24_req; -floo_rsp_t router_2_24_to_router_1_24_rsp; - -floo_req_t router_1_24_to_magia_tile_ni_1_24_req; -floo_rsp_t magia_tile_ni_1_24_to_router_1_24_rsp; - -floo_req_t router_1_25_to_router_0_25_req; -floo_rsp_t router_0_25_to_router_1_25_rsp; - -floo_req_t router_1_25_to_router_1_24_req; -floo_rsp_t router_1_24_to_router_1_25_rsp; - -floo_req_t router_1_25_to_router_1_26_req; -floo_rsp_t router_1_26_to_router_1_25_rsp; - -floo_req_t router_1_25_to_router_2_25_req; -floo_rsp_t router_2_25_to_router_1_25_rsp; - -floo_req_t router_1_25_to_magia_tile_ni_1_25_req; -floo_rsp_t magia_tile_ni_1_25_to_router_1_25_rsp; - -floo_req_t router_1_26_to_router_0_26_req; -floo_rsp_t router_0_26_to_router_1_26_rsp; - -floo_req_t router_1_26_to_router_1_25_req; -floo_rsp_t router_1_25_to_router_1_26_rsp; - -floo_req_t router_1_26_to_router_1_27_req; -floo_rsp_t router_1_27_to_router_1_26_rsp; - -floo_req_t router_1_26_to_router_2_26_req; -floo_rsp_t router_2_26_to_router_1_26_rsp; - -floo_req_t router_1_26_to_magia_tile_ni_1_26_req; -floo_rsp_t magia_tile_ni_1_26_to_router_1_26_rsp; - -floo_req_t router_1_27_to_router_0_27_req; -floo_rsp_t router_0_27_to_router_1_27_rsp; - -floo_req_t router_1_27_to_router_1_26_req; -floo_rsp_t router_1_26_to_router_1_27_rsp; - -floo_req_t router_1_27_to_router_1_28_req; -floo_rsp_t router_1_28_to_router_1_27_rsp; - -floo_req_t router_1_27_to_router_2_27_req; -floo_rsp_t router_2_27_to_router_1_27_rsp; - -floo_req_t router_1_27_to_magia_tile_ni_1_27_req; -floo_rsp_t magia_tile_ni_1_27_to_router_1_27_rsp; - -floo_req_t router_1_28_to_router_0_28_req; -floo_rsp_t router_0_28_to_router_1_28_rsp; - -floo_req_t router_1_28_to_router_1_27_req; -floo_rsp_t router_1_27_to_router_1_28_rsp; - -floo_req_t router_1_28_to_router_1_29_req; -floo_rsp_t router_1_29_to_router_1_28_rsp; - -floo_req_t router_1_28_to_router_2_28_req; -floo_rsp_t router_2_28_to_router_1_28_rsp; - -floo_req_t router_1_28_to_magia_tile_ni_1_28_req; -floo_rsp_t magia_tile_ni_1_28_to_router_1_28_rsp; - -floo_req_t router_1_29_to_router_0_29_req; -floo_rsp_t router_0_29_to_router_1_29_rsp; - -floo_req_t router_1_29_to_router_1_28_req; -floo_rsp_t router_1_28_to_router_1_29_rsp; - -floo_req_t router_1_29_to_router_1_30_req; -floo_rsp_t router_1_30_to_router_1_29_rsp; - -floo_req_t router_1_29_to_router_2_29_req; -floo_rsp_t router_2_29_to_router_1_29_rsp; - -floo_req_t router_1_29_to_magia_tile_ni_1_29_req; -floo_rsp_t magia_tile_ni_1_29_to_router_1_29_rsp; - -floo_req_t router_1_30_to_router_0_30_req; -floo_rsp_t router_0_30_to_router_1_30_rsp; - -floo_req_t router_1_30_to_router_1_29_req; -floo_rsp_t router_1_29_to_router_1_30_rsp; - -floo_req_t router_1_30_to_router_1_31_req; -floo_rsp_t router_1_31_to_router_1_30_rsp; - -floo_req_t router_1_30_to_router_2_30_req; -floo_rsp_t router_2_30_to_router_1_30_rsp; - -floo_req_t router_1_30_to_magia_tile_ni_1_30_req; -floo_rsp_t magia_tile_ni_1_30_to_router_1_30_rsp; - -floo_req_t router_1_31_to_router_0_31_req; -floo_rsp_t router_0_31_to_router_1_31_rsp; - -floo_req_t router_1_31_to_router_1_30_req; -floo_rsp_t router_1_30_to_router_1_31_rsp; - -floo_req_t router_1_31_to_router_2_31_req; -floo_rsp_t router_2_31_to_router_1_31_rsp; - -floo_req_t router_1_31_to_magia_tile_ni_1_31_req; -floo_rsp_t magia_tile_ni_1_31_to_router_1_31_rsp; - -floo_req_t router_2_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_magia_tile_ni_2_0_req; -floo_rsp_t magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_req_t router_2_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_magia_tile_ni_2_1_req; -floo_rsp_t magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_req_t router_2_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_magia_tile_ni_2_2_req; -floo_rsp_t magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_req_t router_2_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_magia_tile_ni_2_3_req; -floo_rsp_t magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_req_t router_2_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_magia_tile_ni_2_4_req; -floo_rsp_t magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_req_t router_2_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_magia_tile_ni_2_5_req; -floo_rsp_t magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_req_t router_2_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_magia_tile_ni_2_6_req; -floo_rsp_t magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_req_t router_2_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_magia_tile_ni_2_7_req; -floo_rsp_t magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_req_t router_2_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_2_8_rsp; - -floo_req_t router_2_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_2_8_rsp; - -floo_req_t router_2_8_to_magia_tile_ni_2_8_req; -floo_rsp_t magia_tile_ni_2_8_to_router_2_8_rsp; - -floo_req_t router_2_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_2_9_rsp; - -floo_req_t router_2_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_2_9_rsp; - -floo_req_t router_2_9_to_magia_tile_ni_2_9_req; -floo_rsp_t magia_tile_ni_2_9_to_router_2_9_rsp; - -floo_req_t router_2_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_2_10_rsp; - -floo_req_t router_2_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_2_10_rsp; - -floo_req_t router_2_10_to_magia_tile_ni_2_10_req; -floo_rsp_t magia_tile_ni_2_10_to_router_2_10_rsp; - -floo_req_t router_2_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_2_11_rsp; - -floo_req_t router_2_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_2_11_rsp; - -floo_req_t router_2_11_to_magia_tile_ni_2_11_req; -floo_rsp_t magia_tile_ni_2_11_to_router_2_11_rsp; - -floo_req_t router_2_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_2_12_rsp; - -floo_req_t router_2_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_2_12_rsp; - -floo_req_t router_2_12_to_magia_tile_ni_2_12_req; -floo_rsp_t magia_tile_ni_2_12_to_router_2_12_rsp; - -floo_req_t router_2_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_2_13_rsp; - -floo_req_t router_2_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_2_13_rsp; - -floo_req_t router_2_13_to_magia_tile_ni_2_13_req; -floo_rsp_t magia_tile_ni_2_13_to_router_2_13_rsp; - -floo_req_t router_2_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_2_14_rsp; - -floo_req_t router_2_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_2_14_rsp; - -floo_req_t router_2_14_to_magia_tile_ni_2_14_req; -floo_rsp_t magia_tile_ni_2_14_to_router_2_14_rsp; - -floo_req_t router_2_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_router_2_15_rsp; - -floo_req_t router_2_15_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_2_15_rsp; - -floo_req_t router_2_15_to_router_2_16_req; -floo_rsp_t router_2_16_to_router_2_15_rsp; - -floo_req_t router_2_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_2_15_rsp; - -floo_req_t router_2_15_to_magia_tile_ni_2_15_req; -floo_rsp_t magia_tile_ni_2_15_to_router_2_15_rsp; - -floo_req_t router_2_16_to_router_1_16_req; -floo_rsp_t router_1_16_to_router_2_16_rsp; - -floo_req_t router_2_16_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_2_16_rsp; - -floo_req_t router_2_16_to_router_2_17_req; -floo_rsp_t router_2_17_to_router_2_16_rsp; - -floo_req_t router_2_16_to_router_3_16_req; -floo_rsp_t router_3_16_to_router_2_16_rsp; - -floo_req_t router_2_16_to_magia_tile_ni_2_16_req; -floo_rsp_t magia_tile_ni_2_16_to_router_2_16_rsp; - -floo_req_t router_2_17_to_router_1_17_req; -floo_rsp_t router_1_17_to_router_2_17_rsp; - -floo_req_t router_2_17_to_router_2_16_req; -floo_rsp_t router_2_16_to_router_2_17_rsp; - -floo_req_t router_2_17_to_router_2_18_req; -floo_rsp_t router_2_18_to_router_2_17_rsp; - -floo_req_t router_2_17_to_router_3_17_req; -floo_rsp_t router_3_17_to_router_2_17_rsp; - -floo_req_t router_2_17_to_magia_tile_ni_2_17_req; -floo_rsp_t magia_tile_ni_2_17_to_router_2_17_rsp; - -floo_req_t router_2_18_to_router_1_18_req; -floo_rsp_t router_1_18_to_router_2_18_rsp; - -floo_req_t router_2_18_to_router_2_17_req; -floo_rsp_t router_2_17_to_router_2_18_rsp; - -floo_req_t router_2_18_to_router_2_19_req; -floo_rsp_t router_2_19_to_router_2_18_rsp; - -floo_req_t router_2_18_to_router_3_18_req; -floo_rsp_t router_3_18_to_router_2_18_rsp; - -floo_req_t router_2_18_to_magia_tile_ni_2_18_req; -floo_rsp_t magia_tile_ni_2_18_to_router_2_18_rsp; - -floo_req_t router_2_19_to_router_1_19_req; -floo_rsp_t router_1_19_to_router_2_19_rsp; - -floo_req_t router_2_19_to_router_2_18_req; -floo_rsp_t router_2_18_to_router_2_19_rsp; - -floo_req_t router_2_19_to_router_2_20_req; -floo_rsp_t router_2_20_to_router_2_19_rsp; - -floo_req_t router_2_19_to_router_3_19_req; -floo_rsp_t router_3_19_to_router_2_19_rsp; - -floo_req_t router_2_19_to_magia_tile_ni_2_19_req; -floo_rsp_t magia_tile_ni_2_19_to_router_2_19_rsp; - -floo_req_t router_2_20_to_router_1_20_req; -floo_rsp_t router_1_20_to_router_2_20_rsp; - -floo_req_t router_2_20_to_router_2_19_req; -floo_rsp_t router_2_19_to_router_2_20_rsp; - -floo_req_t router_2_20_to_router_2_21_req; -floo_rsp_t router_2_21_to_router_2_20_rsp; - -floo_req_t router_2_20_to_router_3_20_req; -floo_rsp_t router_3_20_to_router_2_20_rsp; - -floo_req_t router_2_20_to_magia_tile_ni_2_20_req; -floo_rsp_t magia_tile_ni_2_20_to_router_2_20_rsp; - -floo_req_t router_2_21_to_router_1_21_req; -floo_rsp_t router_1_21_to_router_2_21_rsp; - -floo_req_t router_2_21_to_router_2_20_req; -floo_rsp_t router_2_20_to_router_2_21_rsp; - -floo_req_t router_2_21_to_router_2_22_req; -floo_rsp_t router_2_22_to_router_2_21_rsp; - -floo_req_t router_2_21_to_router_3_21_req; -floo_rsp_t router_3_21_to_router_2_21_rsp; - -floo_req_t router_2_21_to_magia_tile_ni_2_21_req; -floo_rsp_t magia_tile_ni_2_21_to_router_2_21_rsp; - -floo_req_t router_2_22_to_router_1_22_req; -floo_rsp_t router_1_22_to_router_2_22_rsp; - -floo_req_t router_2_22_to_router_2_21_req; -floo_rsp_t router_2_21_to_router_2_22_rsp; - -floo_req_t router_2_22_to_router_2_23_req; -floo_rsp_t router_2_23_to_router_2_22_rsp; - -floo_req_t router_2_22_to_router_3_22_req; -floo_rsp_t router_3_22_to_router_2_22_rsp; - -floo_req_t router_2_22_to_magia_tile_ni_2_22_req; -floo_rsp_t magia_tile_ni_2_22_to_router_2_22_rsp; - -floo_req_t router_2_23_to_router_1_23_req; -floo_rsp_t router_1_23_to_router_2_23_rsp; - -floo_req_t router_2_23_to_router_2_22_req; -floo_rsp_t router_2_22_to_router_2_23_rsp; - -floo_req_t router_2_23_to_router_2_24_req; -floo_rsp_t router_2_24_to_router_2_23_rsp; - -floo_req_t router_2_23_to_router_3_23_req; -floo_rsp_t router_3_23_to_router_2_23_rsp; - -floo_req_t router_2_23_to_magia_tile_ni_2_23_req; -floo_rsp_t magia_tile_ni_2_23_to_router_2_23_rsp; - -floo_req_t router_2_24_to_router_1_24_req; -floo_rsp_t router_1_24_to_router_2_24_rsp; - -floo_req_t router_2_24_to_router_2_23_req; -floo_rsp_t router_2_23_to_router_2_24_rsp; - -floo_req_t router_2_24_to_router_2_25_req; -floo_rsp_t router_2_25_to_router_2_24_rsp; - -floo_req_t router_2_24_to_router_3_24_req; -floo_rsp_t router_3_24_to_router_2_24_rsp; - -floo_req_t router_2_24_to_magia_tile_ni_2_24_req; -floo_rsp_t magia_tile_ni_2_24_to_router_2_24_rsp; - -floo_req_t router_2_25_to_router_1_25_req; -floo_rsp_t router_1_25_to_router_2_25_rsp; - -floo_req_t router_2_25_to_router_2_24_req; -floo_rsp_t router_2_24_to_router_2_25_rsp; - -floo_req_t router_2_25_to_router_2_26_req; -floo_rsp_t router_2_26_to_router_2_25_rsp; - -floo_req_t router_2_25_to_router_3_25_req; -floo_rsp_t router_3_25_to_router_2_25_rsp; - -floo_req_t router_2_25_to_magia_tile_ni_2_25_req; -floo_rsp_t magia_tile_ni_2_25_to_router_2_25_rsp; - -floo_req_t router_2_26_to_router_1_26_req; -floo_rsp_t router_1_26_to_router_2_26_rsp; - -floo_req_t router_2_26_to_router_2_25_req; -floo_rsp_t router_2_25_to_router_2_26_rsp; - -floo_req_t router_2_26_to_router_2_27_req; -floo_rsp_t router_2_27_to_router_2_26_rsp; - -floo_req_t router_2_26_to_router_3_26_req; -floo_rsp_t router_3_26_to_router_2_26_rsp; - -floo_req_t router_2_26_to_magia_tile_ni_2_26_req; -floo_rsp_t magia_tile_ni_2_26_to_router_2_26_rsp; - -floo_req_t router_2_27_to_router_1_27_req; -floo_rsp_t router_1_27_to_router_2_27_rsp; - -floo_req_t router_2_27_to_router_2_26_req; -floo_rsp_t router_2_26_to_router_2_27_rsp; - -floo_req_t router_2_27_to_router_2_28_req; -floo_rsp_t router_2_28_to_router_2_27_rsp; - -floo_req_t router_2_27_to_router_3_27_req; -floo_rsp_t router_3_27_to_router_2_27_rsp; - -floo_req_t router_2_27_to_magia_tile_ni_2_27_req; -floo_rsp_t magia_tile_ni_2_27_to_router_2_27_rsp; - -floo_req_t router_2_28_to_router_1_28_req; -floo_rsp_t router_1_28_to_router_2_28_rsp; - -floo_req_t router_2_28_to_router_2_27_req; -floo_rsp_t router_2_27_to_router_2_28_rsp; - -floo_req_t router_2_28_to_router_2_29_req; -floo_rsp_t router_2_29_to_router_2_28_rsp; - -floo_req_t router_2_28_to_router_3_28_req; -floo_rsp_t router_3_28_to_router_2_28_rsp; - -floo_req_t router_2_28_to_magia_tile_ni_2_28_req; -floo_rsp_t magia_tile_ni_2_28_to_router_2_28_rsp; - -floo_req_t router_2_29_to_router_1_29_req; -floo_rsp_t router_1_29_to_router_2_29_rsp; - -floo_req_t router_2_29_to_router_2_28_req; -floo_rsp_t router_2_28_to_router_2_29_rsp; - -floo_req_t router_2_29_to_router_2_30_req; -floo_rsp_t router_2_30_to_router_2_29_rsp; - -floo_req_t router_2_29_to_router_3_29_req; -floo_rsp_t router_3_29_to_router_2_29_rsp; - -floo_req_t router_2_29_to_magia_tile_ni_2_29_req; -floo_rsp_t magia_tile_ni_2_29_to_router_2_29_rsp; - -floo_req_t router_2_30_to_router_1_30_req; -floo_rsp_t router_1_30_to_router_2_30_rsp; - -floo_req_t router_2_30_to_router_2_29_req; -floo_rsp_t router_2_29_to_router_2_30_rsp; - -floo_req_t router_2_30_to_router_2_31_req; -floo_rsp_t router_2_31_to_router_2_30_rsp; - -floo_req_t router_2_30_to_router_3_30_req; -floo_rsp_t router_3_30_to_router_2_30_rsp; - -floo_req_t router_2_30_to_magia_tile_ni_2_30_req; -floo_rsp_t magia_tile_ni_2_30_to_router_2_30_rsp; - -floo_req_t router_2_31_to_router_1_31_req; -floo_rsp_t router_1_31_to_router_2_31_rsp; - -floo_req_t router_2_31_to_router_2_30_req; -floo_rsp_t router_2_30_to_router_2_31_rsp; - -floo_req_t router_2_31_to_router_3_31_req; -floo_rsp_t router_3_31_to_router_2_31_rsp; - -floo_req_t router_2_31_to_magia_tile_ni_2_31_req; -floo_rsp_t magia_tile_ni_2_31_to_router_2_31_rsp; - -floo_req_t router_3_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_magia_tile_ni_3_0_req; -floo_rsp_t magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_req_t router_3_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_magia_tile_ni_3_1_req; -floo_rsp_t magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_req_t router_3_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_magia_tile_ni_3_2_req; -floo_rsp_t magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_req_t router_3_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_magia_tile_ni_3_3_req; -floo_rsp_t magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_req_t router_3_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_magia_tile_ni_3_4_req; -floo_rsp_t magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_req_t router_3_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_magia_tile_ni_3_5_req; -floo_rsp_t magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_req_t router_3_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_magia_tile_ni_3_6_req; -floo_rsp_t magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_req_t router_3_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_magia_tile_ni_3_7_req; -floo_rsp_t magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_req_t router_3_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_3_8_rsp; - -floo_req_t router_3_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_3_8_rsp; - -floo_req_t router_3_8_to_magia_tile_ni_3_8_req; -floo_rsp_t magia_tile_ni_3_8_to_router_3_8_rsp; - -floo_req_t router_3_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_3_9_rsp; - -floo_req_t router_3_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_3_9_rsp; - -floo_req_t router_3_9_to_magia_tile_ni_3_9_req; -floo_rsp_t magia_tile_ni_3_9_to_router_3_9_rsp; - -floo_req_t router_3_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_3_10_rsp; - -floo_req_t router_3_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_3_10_rsp; - -floo_req_t router_3_10_to_magia_tile_ni_3_10_req; -floo_rsp_t magia_tile_ni_3_10_to_router_3_10_rsp; - -floo_req_t router_3_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_3_11_rsp; - -floo_req_t router_3_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_3_11_rsp; - -floo_req_t router_3_11_to_magia_tile_ni_3_11_req; -floo_rsp_t magia_tile_ni_3_11_to_router_3_11_rsp; - -floo_req_t router_3_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_3_12_rsp; - -floo_req_t router_3_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_3_12_rsp; - -floo_req_t router_3_12_to_magia_tile_ni_3_12_req; -floo_rsp_t magia_tile_ni_3_12_to_router_3_12_rsp; - -floo_req_t router_3_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_3_13_rsp; - -floo_req_t router_3_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_3_13_rsp; - -floo_req_t router_3_13_to_magia_tile_ni_3_13_req; -floo_rsp_t magia_tile_ni_3_13_to_router_3_13_rsp; - -floo_req_t router_3_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_3_14_rsp; - -floo_req_t router_3_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_3_14_rsp; - -floo_req_t router_3_14_to_magia_tile_ni_3_14_req; -floo_rsp_t magia_tile_ni_3_14_to_router_3_14_rsp; - -floo_req_t router_3_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_router_3_15_rsp; - -floo_req_t router_3_15_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_3_15_rsp; - -floo_req_t router_3_15_to_router_3_16_req; -floo_rsp_t router_3_16_to_router_3_15_rsp; - -floo_req_t router_3_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_3_15_rsp; - -floo_req_t router_3_15_to_magia_tile_ni_3_15_req; -floo_rsp_t magia_tile_ni_3_15_to_router_3_15_rsp; - -floo_req_t router_3_16_to_router_2_16_req; -floo_rsp_t router_2_16_to_router_3_16_rsp; - -floo_req_t router_3_16_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_3_16_rsp; - -floo_req_t router_3_16_to_router_3_17_req; -floo_rsp_t router_3_17_to_router_3_16_rsp; - -floo_req_t router_3_16_to_router_4_16_req; -floo_rsp_t router_4_16_to_router_3_16_rsp; - -floo_req_t router_3_16_to_magia_tile_ni_3_16_req; -floo_rsp_t magia_tile_ni_3_16_to_router_3_16_rsp; - -floo_req_t router_3_17_to_router_2_17_req; -floo_rsp_t router_2_17_to_router_3_17_rsp; - -floo_req_t router_3_17_to_router_3_16_req; -floo_rsp_t router_3_16_to_router_3_17_rsp; - -floo_req_t router_3_17_to_router_3_18_req; -floo_rsp_t router_3_18_to_router_3_17_rsp; - -floo_req_t router_3_17_to_router_4_17_req; -floo_rsp_t router_4_17_to_router_3_17_rsp; - -floo_req_t router_3_17_to_magia_tile_ni_3_17_req; -floo_rsp_t magia_tile_ni_3_17_to_router_3_17_rsp; - -floo_req_t router_3_18_to_router_2_18_req; -floo_rsp_t router_2_18_to_router_3_18_rsp; - -floo_req_t router_3_18_to_router_3_17_req; -floo_rsp_t router_3_17_to_router_3_18_rsp; - -floo_req_t router_3_18_to_router_3_19_req; -floo_rsp_t router_3_19_to_router_3_18_rsp; - -floo_req_t router_3_18_to_router_4_18_req; -floo_rsp_t router_4_18_to_router_3_18_rsp; - -floo_req_t router_3_18_to_magia_tile_ni_3_18_req; -floo_rsp_t magia_tile_ni_3_18_to_router_3_18_rsp; - -floo_req_t router_3_19_to_router_2_19_req; -floo_rsp_t router_2_19_to_router_3_19_rsp; - -floo_req_t router_3_19_to_router_3_18_req; -floo_rsp_t router_3_18_to_router_3_19_rsp; - -floo_req_t router_3_19_to_router_3_20_req; -floo_rsp_t router_3_20_to_router_3_19_rsp; - -floo_req_t router_3_19_to_router_4_19_req; -floo_rsp_t router_4_19_to_router_3_19_rsp; - -floo_req_t router_3_19_to_magia_tile_ni_3_19_req; -floo_rsp_t magia_tile_ni_3_19_to_router_3_19_rsp; - -floo_req_t router_3_20_to_router_2_20_req; -floo_rsp_t router_2_20_to_router_3_20_rsp; - -floo_req_t router_3_20_to_router_3_19_req; -floo_rsp_t router_3_19_to_router_3_20_rsp; - -floo_req_t router_3_20_to_router_3_21_req; -floo_rsp_t router_3_21_to_router_3_20_rsp; - -floo_req_t router_3_20_to_router_4_20_req; -floo_rsp_t router_4_20_to_router_3_20_rsp; - -floo_req_t router_3_20_to_magia_tile_ni_3_20_req; -floo_rsp_t magia_tile_ni_3_20_to_router_3_20_rsp; - -floo_req_t router_3_21_to_router_2_21_req; -floo_rsp_t router_2_21_to_router_3_21_rsp; - -floo_req_t router_3_21_to_router_3_20_req; -floo_rsp_t router_3_20_to_router_3_21_rsp; - -floo_req_t router_3_21_to_router_3_22_req; -floo_rsp_t router_3_22_to_router_3_21_rsp; - -floo_req_t router_3_21_to_router_4_21_req; -floo_rsp_t router_4_21_to_router_3_21_rsp; - -floo_req_t router_3_21_to_magia_tile_ni_3_21_req; -floo_rsp_t magia_tile_ni_3_21_to_router_3_21_rsp; - -floo_req_t router_3_22_to_router_2_22_req; -floo_rsp_t router_2_22_to_router_3_22_rsp; - -floo_req_t router_3_22_to_router_3_21_req; -floo_rsp_t router_3_21_to_router_3_22_rsp; - -floo_req_t router_3_22_to_router_3_23_req; -floo_rsp_t router_3_23_to_router_3_22_rsp; - -floo_req_t router_3_22_to_router_4_22_req; -floo_rsp_t router_4_22_to_router_3_22_rsp; - -floo_req_t router_3_22_to_magia_tile_ni_3_22_req; -floo_rsp_t magia_tile_ni_3_22_to_router_3_22_rsp; - -floo_req_t router_3_23_to_router_2_23_req; -floo_rsp_t router_2_23_to_router_3_23_rsp; - -floo_req_t router_3_23_to_router_3_22_req; -floo_rsp_t router_3_22_to_router_3_23_rsp; - -floo_req_t router_3_23_to_router_3_24_req; -floo_rsp_t router_3_24_to_router_3_23_rsp; - -floo_req_t router_3_23_to_router_4_23_req; -floo_rsp_t router_4_23_to_router_3_23_rsp; - -floo_req_t router_3_23_to_magia_tile_ni_3_23_req; -floo_rsp_t magia_tile_ni_3_23_to_router_3_23_rsp; - -floo_req_t router_3_24_to_router_2_24_req; -floo_rsp_t router_2_24_to_router_3_24_rsp; - -floo_req_t router_3_24_to_router_3_23_req; -floo_rsp_t router_3_23_to_router_3_24_rsp; - -floo_req_t router_3_24_to_router_3_25_req; -floo_rsp_t router_3_25_to_router_3_24_rsp; - -floo_req_t router_3_24_to_router_4_24_req; -floo_rsp_t router_4_24_to_router_3_24_rsp; - -floo_req_t router_3_24_to_magia_tile_ni_3_24_req; -floo_rsp_t magia_tile_ni_3_24_to_router_3_24_rsp; - -floo_req_t router_3_25_to_router_2_25_req; -floo_rsp_t router_2_25_to_router_3_25_rsp; - -floo_req_t router_3_25_to_router_3_24_req; -floo_rsp_t router_3_24_to_router_3_25_rsp; - -floo_req_t router_3_25_to_router_3_26_req; -floo_rsp_t router_3_26_to_router_3_25_rsp; - -floo_req_t router_3_25_to_router_4_25_req; -floo_rsp_t router_4_25_to_router_3_25_rsp; - -floo_req_t router_3_25_to_magia_tile_ni_3_25_req; -floo_rsp_t magia_tile_ni_3_25_to_router_3_25_rsp; - -floo_req_t router_3_26_to_router_2_26_req; -floo_rsp_t router_2_26_to_router_3_26_rsp; - -floo_req_t router_3_26_to_router_3_25_req; -floo_rsp_t router_3_25_to_router_3_26_rsp; - -floo_req_t router_3_26_to_router_3_27_req; -floo_rsp_t router_3_27_to_router_3_26_rsp; - -floo_req_t router_3_26_to_router_4_26_req; -floo_rsp_t router_4_26_to_router_3_26_rsp; - -floo_req_t router_3_26_to_magia_tile_ni_3_26_req; -floo_rsp_t magia_tile_ni_3_26_to_router_3_26_rsp; - -floo_req_t router_3_27_to_router_2_27_req; -floo_rsp_t router_2_27_to_router_3_27_rsp; - -floo_req_t router_3_27_to_router_3_26_req; -floo_rsp_t router_3_26_to_router_3_27_rsp; - -floo_req_t router_3_27_to_router_3_28_req; -floo_rsp_t router_3_28_to_router_3_27_rsp; - -floo_req_t router_3_27_to_router_4_27_req; -floo_rsp_t router_4_27_to_router_3_27_rsp; - -floo_req_t router_3_27_to_magia_tile_ni_3_27_req; -floo_rsp_t magia_tile_ni_3_27_to_router_3_27_rsp; - -floo_req_t router_3_28_to_router_2_28_req; -floo_rsp_t router_2_28_to_router_3_28_rsp; - -floo_req_t router_3_28_to_router_3_27_req; -floo_rsp_t router_3_27_to_router_3_28_rsp; - -floo_req_t router_3_28_to_router_3_29_req; -floo_rsp_t router_3_29_to_router_3_28_rsp; - -floo_req_t router_3_28_to_router_4_28_req; -floo_rsp_t router_4_28_to_router_3_28_rsp; - -floo_req_t router_3_28_to_magia_tile_ni_3_28_req; -floo_rsp_t magia_tile_ni_3_28_to_router_3_28_rsp; - -floo_req_t router_3_29_to_router_2_29_req; -floo_rsp_t router_2_29_to_router_3_29_rsp; - -floo_req_t router_3_29_to_router_3_28_req; -floo_rsp_t router_3_28_to_router_3_29_rsp; - -floo_req_t router_3_29_to_router_3_30_req; -floo_rsp_t router_3_30_to_router_3_29_rsp; - -floo_req_t router_3_29_to_router_4_29_req; -floo_rsp_t router_4_29_to_router_3_29_rsp; - -floo_req_t router_3_29_to_magia_tile_ni_3_29_req; -floo_rsp_t magia_tile_ni_3_29_to_router_3_29_rsp; - -floo_req_t router_3_30_to_router_2_30_req; -floo_rsp_t router_2_30_to_router_3_30_rsp; - -floo_req_t router_3_30_to_router_3_29_req; -floo_rsp_t router_3_29_to_router_3_30_rsp; - -floo_req_t router_3_30_to_router_3_31_req; -floo_rsp_t router_3_31_to_router_3_30_rsp; - -floo_req_t router_3_30_to_router_4_30_req; -floo_rsp_t router_4_30_to_router_3_30_rsp; - -floo_req_t router_3_30_to_magia_tile_ni_3_30_req; -floo_rsp_t magia_tile_ni_3_30_to_router_3_30_rsp; - -floo_req_t router_3_31_to_router_2_31_req; -floo_rsp_t router_2_31_to_router_3_31_rsp; - -floo_req_t router_3_31_to_router_3_30_req; -floo_rsp_t router_3_30_to_router_3_31_rsp; - -floo_req_t router_3_31_to_router_4_31_req; -floo_rsp_t router_4_31_to_router_3_31_rsp; - -floo_req_t router_3_31_to_magia_tile_ni_3_31_req; -floo_rsp_t magia_tile_ni_3_31_to_router_3_31_rsp; - -floo_req_t router_4_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_magia_tile_ni_4_0_req; -floo_rsp_t magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_req_t router_4_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_magia_tile_ni_4_1_req; -floo_rsp_t magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_req_t router_4_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_magia_tile_ni_4_2_req; -floo_rsp_t magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_req_t router_4_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_magia_tile_ni_4_3_req; -floo_rsp_t magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_req_t router_4_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_magia_tile_ni_4_4_req; -floo_rsp_t magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_req_t router_4_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_magia_tile_ni_4_5_req; -floo_rsp_t magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_req_t router_4_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_magia_tile_ni_4_6_req; -floo_rsp_t magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_req_t router_4_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_magia_tile_ni_4_7_req; -floo_rsp_t magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_req_t router_4_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_4_8_rsp; - -floo_req_t router_4_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_4_8_rsp; - -floo_req_t router_4_8_to_magia_tile_ni_4_8_req; -floo_rsp_t magia_tile_ni_4_8_to_router_4_8_rsp; - -floo_req_t router_4_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_4_9_rsp; - -floo_req_t router_4_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_4_9_rsp; - -floo_req_t router_4_9_to_magia_tile_ni_4_9_req; -floo_rsp_t magia_tile_ni_4_9_to_router_4_9_rsp; - -floo_req_t router_4_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_4_10_rsp; - -floo_req_t router_4_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_4_10_rsp; - -floo_req_t router_4_10_to_magia_tile_ni_4_10_req; -floo_rsp_t magia_tile_ni_4_10_to_router_4_10_rsp; - -floo_req_t router_4_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_4_11_rsp; - -floo_req_t router_4_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_4_11_rsp; - -floo_req_t router_4_11_to_magia_tile_ni_4_11_req; -floo_rsp_t magia_tile_ni_4_11_to_router_4_11_rsp; - -floo_req_t router_4_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_4_12_rsp; - -floo_req_t router_4_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_4_12_rsp; - -floo_req_t router_4_12_to_magia_tile_ni_4_12_req; -floo_rsp_t magia_tile_ni_4_12_to_router_4_12_rsp; - -floo_req_t router_4_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_4_13_rsp; - -floo_req_t router_4_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_4_13_rsp; - -floo_req_t router_4_13_to_magia_tile_ni_4_13_req; -floo_rsp_t magia_tile_ni_4_13_to_router_4_13_rsp; - -floo_req_t router_4_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_4_14_rsp; - -floo_req_t router_4_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_4_14_rsp; - -floo_req_t router_4_14_to_magia_tile_ni_4_14_req; -floo_rsp_t magia_tile_ni_4_14_to_router_4_14_rsp; - -floo_req_t router_4_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_router_4_15_rsp; - -floo_req_t router_4_15_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_4_15_rsp; - -floo_req_t router_4_15_to_router_4_16_req; -floo_rsp_t router_4_16_to_router_4_15_rsp; - -floo_req_t router_4_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_4_15_rsp; - -floo_req_t router_4_15_to_magia_tile_ni_4_15_req; -floo_rsp_t magia_tile_ni_4_15_to_router_4_15_rsp; - -floo_req_t router_4_16_to_router_3_16_req; -floo_rsp_t router_3_16_to_router_4_16_rsp; - -floo_req_t router_4_16_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_4_16_rsp; - -floo_req_t router_4_16_to_router_4_17_req; -floo_rsp_t router_4_17_to_router_4_16_rsp; - -floo_req_t router_4_16_to_router_5_16_req; -floo_rsp_t router_5_16_to_router_4_16_rsp; - -floo_req_t router_4_16_to_magia_tile_ni_4_16_req; -floo_rsp_t magia_tile_ni_4_16_to_router_4_16_rsp; - -floo_req_t router_4_17_to_router_3_17_req; -floo_rsp_t router_3_17_to_router_4_17_rsp; - -floo_req_t router_4_17_to_router_4_16_req; -floo_rsp_t router_4_16_to_router_4_17_rsp; - -floo_req_t router_4_17_to_router_4_18_req; -floo_rsp_t router_4_18_to_router_4_17_rsp; - -floo_req_t router_4_17_to_router_5_17_req; -floo_rsp_t router_5_17_to_router_4_17_rsp; - -floo_req_t router_4_17_to_magia_tile_ni_4_17_req; -floo_rsp_t magia_tile_ni_4_17_to_router_4_17_rsp; - -floo_req_t router_4_18_to_router_3_18_req; -floo_rsp_t router_3_18_to_router_4_18_rsp; - -floo_req_t router_4_18_to_router_4_17_req; -floo_rsp_t router_4_17_to_router_4_18_rsp; - -floo_req_t router_4_18_to_router_4_19_req; -floo_rsp_t router_4_19_to_router_4_18_rsp; - -floo_req_t router_4_18_to_router_5_18_req; -floo_rsp_t router_5_18_to_router_4_18_rsp; - -floo_req_t router_4_18_to_magia_tile_ni_4_18_req; -floo_rsp_t magia_tile_ni_4_18_to_router_4_18_rsp; - -floo_req_t router_4_19_to_router_3_19_req; -floo_rsp_t router_3_19_to_router_4_19_rsp; - -floo_req_t router_4_19_to_router_4_18_req; -floo_rsp_t router_4_18_to_router_4_19_rsp; - -floo_req_t router_4_19_to_router_4_20_req; -floo_rsp_t router_4_20_to_router_4_19_rsp; - -floo_req_t router_4_19_to_router_5_19_req; -floo_rsp_t router_5_19_to_router_4_19_rsp; - -floo_req_t router_4_19_to_magia_tile_ni_4_19_req; -floo_rsp_t magia_tile_ni_4_19_to_router_4_19_rsp; - -floo_req_t router_4_20_to_router_3_20_req; -floo_rsp_t router_3_20_to_router_4_20_rsp; - -floo_req_t router_4_20_to_router_4_19_req; -floo_rsp_t router_4_19_to_router_4_20_rsp; - -floo_req_t router_4_20_to_router_4_21_req; -floo_rsp_t router_4_21_to_router_4_20_rsp; - -floo_req_t router_4_20_to_router_5_20_req; -floo_rsp_t router_5_20_to_router_4_20_rsp; - -floo_req_t router_4_20_to_magia_tile_ni_4_20_req; -floo_rsp_t magia_tile_ni_4_20_to_router_4_20_rsp; - -floo_req_t router_4_21_to_router_3_21_req; -floo_rsp_t router_3_21_to_router_4_21_rsp; - -floo_req_t router_4_21_to_router_4_20_req; -floo_rsp_t router_4_20_to_router_4_21_rsp; - -floo_req_t router_4_21_to_router_4_22_req; -floo_rsp_t router_4_22_to_router_4_21_rsp; - -floo_req_t router_4_21_to_router_5_21_req; -floo_rsp_t router_5_21_to_router_4_21_rsp; - -floo_req_t router_4_21_to_magia_tile_ni_4_21_req; -floo_rsp_t magia_tile_ni_4_21_to_router_4_21_rsp; - -floo_req_t router_4_22_to_router_3_22_req; -floo_rsp_t router_3_22_to_router_4_22_rsp; - -floo_req_t router_4_22_to_router_4_21_req; -floo_rsp_t router_4_21_to_router_4_22_rsp; - -floo_req_t router_4_22_to_router_4_23_req; -floo_rsp_t router_4_23_to_router_4_22_rsp; - -floo_req_t router_4_22_to_router_5_22_req; -floo_rsp_t router_5_22_to_router_4_22_rsp; - -floo_req_t router_4_22_to_magia_tile_ni_4_22_req; -floo_rsp_t magia_tile_ni_4_22_to_router_4_22_rsp; - -floo_req_t router_4_23_to_router_3_23_req; -floo_rsp_t router_3_23_to_router_4_23_rsp; - -floo_req_t router_4_23_to_router_4_22_req; -floo_rsp_t router_4_22_to_router_4_23_rsp; - -floo_req_t router_4_23_to_router_4_24_req; -floo_rsp_t router_4_24_to_router_4_23_rsp; - -floo_req_t router_4_23_to_router_5_23_req; -floo_rsp_t router_5_23_to_router_4_23_rsp; - -floo_req_t router_4_23_to_magia_tile_ni_4_23_req; -floo_rsp_t magia_tile_ni_4_23_to_router_4_23_rsp; - -floo_req_t router_4_24_to_router_3_24_req; -floo_rsp_t router_3_24_to_router_4_24_rsp; - -floo_req_t router_4_24_to_router_4_23_req; -floo_rsp_t router_4_23_to_router_4_24_rsp; - -floo_req_t router_4_24_to_router_4_25_req; -floo_rsp_t router_4_25_to_router_4_24_rsp; - -floo_req_t router_4_24_to_router_5_24_req; -floo_rsp_t router_5_24_to_router_4_24_rsp; - -floo_req_t router_4_24_to_magia_tile_ni_4_24_req; -floo_rsp_t magia_tile_ni_4_24_to_router_4_24_rsp; - -floo_req_t router_4_25_to_router_3_25_req; -floo_rsp_t router_3_25_to_router_4_25_rsp; - -floo_req_t router_4_25_to_router_4_24_req; -floo_rsp_t router_4_24_to_router_4_25_rsp; - -floo_req_t router_4_25_to_router_4_26_req; -floo_rsp_t router_4_26_to_router_4_25_rsp; - -floo_req_t router_4_25_to_router_5_25_req; -floo_rsp_t router_5_25_to_router_4_25_rsp; - -floo_req_t router_4_25_to_magia_tile_ni_4_25_req; -floo_rsp_t magia_tile_ni_4_25_to_router_4_25_rsp; - -floo_req_t router_4_26_to_router_3_26_req; -floo_rsp_t router_3_26_to_router_4_26_rsp; - -floo_req_t router_4_26_to_router_4_25_req; -floo_rsp_t router_4_25_to_router_4_26_rsp; - -floo_req_t router_4_26_to_router_4_27_req; -floo_rsp_t router_4_27_to_router_4_26_rsp; - -floo_req_t router_4_26_to_router_5_26_req; -floo_rsp_t router_5_26_to_router_4_26_rsp; - -floo_req_t router_4_26_to_magia_tile_ni_4_26_req; -floo_rsp_t magia_tile_ni_4_26_to_router_4_26_rsp; - -floo_req_t router_4_27_to_router_3_27_req; -floo_rsp_t router_3_27_to_router_4_27_rsp; - -floo_req_t router_4_27_to_router_4_26_req; -floo_rsp_t router_4_26_to_router_4_27_rsp; - -floo_req_t router_4_27_to_router_4_28_req; -floo_rsp_t router_4_28_to_router_4_27_rsp; - -floo_req_t router_4_27_to_router_5_27_req; -floo_rsp_t router_5_27_to_router_4_27_rsp; - -floo_req_t router_4_27_to_magia_tile_ni_4_27_req; -floo_rsp_t magia_tile_ni_4_27_to_router_4_27_rsp; - -floo_req_t router_4_28_to_router_3_28_req; -floo_rsp_t router_3_28_to_router_4_28_rsp; - -floo_req_t router_4_28_to_router_4_27_req; -floo_rsp_t router_4_27_to_router_4_28_rsp; - -floo_req_t router_4_28_to_router_4_29_req; -floo_rsp_t router_4_29_to_router_4_28_rsp; - -floo_req_t router_4_28_to_router_5_28_req; -floo_rsp_t router_5_28_to_router_4_28_rsp; - -floo_req_t router_4_28_to_magia_tile_ni_4_28_req; -floo_rsp_t magia_tile_ni_4_28_to_router_4_28_rsp; - -floo_req_t router_4_29_to_router_3_29_req; -floo_rsp_t router_3_29_to_router_4_29_rsp; - -floo_req_t router_4_29_to_router_4_28_req; -floo_rsp_t router_4_28_to_router_4_29_rsp; - -floo_req_t router_4_29_to_router_4_30_req; -floo_rsp_t router_4_30_to_router_4_29_rsp; - -floo_req_t router_4_29_to_router_5_29_req; -floo_rsp_t router_5_29_to_router_4_29_rsp; - -floo_req_t router_4_29_to_magia_tile_ni_4_29_req; -floo_rsp_t magia_tile_ni_4_29_to_router_4_29_rsp; - -floo_req_t router_4_30_to_router_3_30_req; -floo_rsp_t router_3_30_to_router_4_30_rsp; - -floo_req_t router_4_30_to_router_4_29_req; -floo_rsp_t router_4_29_to_router_4_30_rsp; - -floo_req_t router_4_30_to_router_4_31_req; -floo_rsp_t router_4_31_to_router_4_30_rsp; - -floo_req_t router_4_30_to_router_5_30_req; -floo_rsp_t router_5_30_to_router_4_30_rsp; - -floo_req_t router_4_30_to_magia_tile_ni_4_30_req; -floo_rsp_t magia_tile_ni_4_30_to_router_4_30_rsp; - -floo_req_t router_4_31_to_router_3_31_req; -floo_rsp_t router_3_31_to_router_4_31_rsp; - -floo_req_t router_4_31_to_router_4_30_req; -floo_rsp_t router_4_30_to_router_4_31_rsp; - -floo_req_t router_4_31_to_router_5_31_req; -floo_rsp_t router_5_31_to_router_4_31_rsp; - -floo_req_t router_4_31_to_magia_tile_ni_4_31_req; -floo_rsp_t magia_tile_ni_4_31_to_router_4_31_rsp; - -floo_req_t router_5_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_magia_tile_ni_5_0_req; -floo_rsp_t magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_req_t router_5_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_magia_tile_ni_5_1_req; -floo_rsp_t magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_req_t router_5_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_magia_tile_ni_5_2_req; -floo_rsp_t magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_req_t router_5_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_magia_tile_ni_5_3_req; -floo_rsp_t magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_req_t router_5_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_magia_tile_ni_5_4_req; -floo_rsp_t magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_req_t router_5_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_magia_tile_ni_5_5_req; -floo_rsp_t magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_req_t router_5_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_magia_tile_ni_5_6_req; -floo_rsp_t magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_req_t router_5_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_magia_tile_ni_5_7_req; -floo_rsp_t magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_req_t router_5_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_5_8_rsp; - -floo_req_t router_5_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_5_8_rsp; - -floo_req_t router_5_8_to_magia_tile_ni_5_8_req; -floo_rsp_t magia_tile_ni_5_8_to_router_5_8_rsp; - -floo_req_t router_5_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_5_9_rsp; - -floo_req_t router_5_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_5_9_rsp; - -floo_req_t router_5_9_to_magia_tile_ni_5_9_req; -floo_rsp_t magia_tile_ni_5_9_to_router_5_9_rsp; - -floo_req_t router_5_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_5_10_rsp; - -floo_req_t router_5_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_5_10_rsp; - -floo_req_t router_5_10_to_magia_tile_ni_5_10_req; -floo_rsp_t magia_tile_ni_5_10_to_router_5_10_rsp; - -floo_req_t router_5_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_5_11_rsp; - -floo_req_t router_5_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_5_11_rsp; - -floo_req_t router_5_11_to_magia_tile_ni_5_11_req; -floo_rsp_t magia_tile_ni_5_11_to_router_5_11_rsp; - -floo_req_t router_5_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_5_12_rsp; - -floo_req_t router_5_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_5_12_rsp; - -floo_req_t router_5_12_to_magia_tile_ni_5_12_req; -floo_rsp_t magia_tile_ni_5_12_to_router_5_12_rsp; - -floo_req_t router_5_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_5_13_rsp; - -floo_req_t router_5_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_5_13_rsp; - -floo_req_t router_5_13_to_magia_tile_ni_5_13_req; -floo_rsp_t magia_tile_ni_5_13_to_router_5_13_rsp; - -floo_req_t router_5_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_5_14_rsp; - -floo_req_t router_5_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_5_14_rsp; - -floo_req_t router_5_14_to_magia_tile_ni_5_14_req; -floo_rsp_t magia_tile_ni_5_14_to_router_5_14_rsp; - -floo_req_t router_5_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_router_5_15_rsp; - -floo_req_t router_5_15_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_5_15_rsp; - -floo_req_t router_5_15_to_router_5_16_req; -floo_rsp_t router_5_16_to_router_5_15_rsp; - -floo_req_t router_5_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_5_15_rsp; - -floo_req_t router_5_15_to_magia_tile_ni_5_15_req; -floo_rsp_t magia_tile_ni_5_15_to_router_5_15_rsp; - -floo_req_t router_5_16_to_router_4_16_req; -floo_rsp_t router_4_16_to_router_5_16_rsp; - -floo_req_t router_5_16_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_5_16_rsp; - -floo_req_t router_5_16_to_router_5_17_req; -floo_rsp_t router_5_17_to_router_5_16_rsp; - -floo_req_t router_5_16_to_router_6_16_req; -floo_rsp_t router_6_16_to_router_5_16_rsp; - -floo_req_t router_5_16_to_magia_tile_ni_5_16_req; -floo_rsp_t magia_tile_ni_5_16_to_router_5_16_rsp; - -floo_req_t router_5_17_to_router_4_17_req; -floo_rsp_t router_4_17_to_router_5_17_rsp; - -floo_req_t router_5_17_to_router_5_16_req; -floo_rsp_t router_5_16_to_router_5_17_rsp; - -floo_req_t router_5_17_to_router_5_18_req; -floo_rsp_t router_5_18_to_router_5_17_rsp; - -floo_req_t router_5_17_to_router_6_17_req; -floo_rsp_t router_6_17_to_router_5_17_rsp; - -floo_req_t router_5_17_to_magia_tile_ni_5_17_req; -floo_rsp_t magia_tile_ni_5_17_to_router_5_17_rsp; - -floo_req_t router_5_18_to_router_4_18_req; -floo_rsp_t router_4_18_to_router_5_18_rsp; - -floo_req_t router_5_18_to_router_5_17_req; -floo_rsp_t router_5_17_to_router_5_18_rsp; - -floo_req_t router_5_18_to_router_5_19_req; -floo_rsp_t router_5_19_to_router_5_18_rsp; - -floo_req_t router_5_18_to_router_6_18_req; -floo_rsp_t router_6_18_to_router_5_18_rsp; - -floo_req_t router_5_18_to_magia_tile_ni_5_18_req; -floo_rsp_t magia_tile_ni_5_18_to_router_5_18_rsp; - -floo_req_t router_5_19_to_router_4_19_req; -floo_rsp_t router_4_19_to_router_5_19_rsp; - -floo_req_t router_5_19_to_router_5_18_req; -floo_rsp_t router_5_18_to_router_5_19_rsp; - -floo_req_t router_5_19_to_router_5_20_req; -floo_rsp_t router_5_20_to_router_5_19_rsp; - -floo_req_t router_5_19_to_router_6_19_req; -floo_rsp_t router_6_19_to_router_5_19_rsp; - -floo_req_t router_5_19_to_magia_tile_ni_5_19_req; -floo_rsp_t magia_tile_ni_5_19_to_router_5_19_rsp; - -floo_req_t router_5_20_to_router_4_20_req; -floo_rsp_t router_4_20_to_router_5_20_rsp; - -floo_req_t router_5_20_to_router_5_19_req; -floo_rsp_t router_5_19_to_router_5_20_rsp; - -floo_req_t router_5_20_to_router_5_21_req; -floo_rsp_t router_5_21_to_router_5_20_rsp; - -floo_req_t router_5_20_to_router_6_20_req; -floo_rsp_t router_6_20_to_router_5_20_rsp; - -floo_req_t router_5_20_to_magia_tile_ni_5_20_req; -floo_rsp_t magia_tile_ni_5_20_to_router_5_20_rsp; - -floo_req_t router_5_21_to_router_4_21_req; -floo_rsp_t router_4_21_to_router_5_21_rsp; - -floo_req_t router_5_21_to_router_5_20_req; -floo_rsp_t router_5_20_to_router_5_21_rsp; - -floo_req_t router_5_21_to_router_5_22_req; -floo_rsp_t router_5_22_to_router_5_21_rsp; - -floo_req_t router_5_21_to_router_6_21_req; -floo_rsp_t router_6_21_to_router_5_21_rsp; - -floo_req_t router_5_21_to_magia_tile_ni_5_21_req; -floo_rsp_t magia_tile_ni_5_21_to_router_5_21_rsp; - -floo_req_t router_5_22_to_router_4_22_req; -floo_rsp_t router_4_22_to_router_5_22_rsp; - -floo_req_t router_5_22_to_router_5_21_req; -floo_rsp_t router_5_21_to_router_5_22_rsp; - -floo_req_t router_5_22_to_router_5_23_req; -floo_rsp_t router_5_23_to_router_5_22_rsp; - -floo_req_t router_5_22_to_router_6_22_req; -floo_rsp_t router_6_22_to_router_5_22_rsp; - -floo_req_t router_5_22_to_magia_tile_ni_5_22_req; -floo_rsp_t magia_tile_ni_5_22_to_router_5_22_rsp; - -floo_req_t router_5_23_to_router_4_23_req; -floo_rsp_t router_4_23_to_router_5_23_rsp; - -floo_req_t router_5_23_to_router_5_22_req; -floo_rsp_t router_5_22_to_router_5_23_rsp; - -floo_req_t router_5_23_to_router_5_24_req; -floo_rsp_t router_5_24_to_router_5_23_rsp; - -floo_req_t router_5_23_to_router_6_23_req; -floo_rsp_t router_6_23_to_router_5_23_rsp; - -floo_req_t router_5_23_to_magia_tile_ni_5_23_req; -floo_rsp_t magia_tile_ni_5_23_to_router_5_23_rsp; - -floo_req_t router_5_24_to_router_4_24_req; -floo_rsp_t router_4_24_to_router_5_24_rsp; - -floo_req_t router_5_24_to_router_5_23_req; -floo_rsp_t router_5_23_to_router_5_24_rsp; - -floo_req_t router_5_24_to_router_5_25_req; -floo_rsp_t router_5_25_to_router_5_24_rsp; - -floo_req_t router_5_24_to_router_6_24_req; -floo_rsp_t router_6_24_to_router_5_24_rsp; - -floo_req_t router_5_24_to_magia_tile_ni_5_24_req; -floo_rsp_t magia_tile_ni_5_24_to_router_5_24_rsp; - -floo_req_t router_5_25_to_router_4_25_req; -floo_rsp_t router_4_25_to_router_5_25_rsp; - -floo_req_t router_5_25_to_router_5_24_req; -floo_rsp_t router_5_24_to_router_5_25_rsp; - -floo_req_t router_5_25_to_router_5_26_req; -floo_rsp_t router_5_26_to_router_5_25_rsp; - -floo_req_t router_5_25_to_router_6_25_req; -floo_rsp_t router_6_25_to_router_5_25_rsp; - -floo_req_t router_5_25_to_magia_tile_ni_5_25_req; -floo_rsp_t magia_tile_ni_5_25_to_router_5_25_rsp; - -floo_req_t router_5_26_to_router_4_26_req; -floo_rsp_t router_4_26_to_router_5_26_rsp; - -floo_req_t router_5_26_to_router_5_25_req; -floo_rsp_t router_5_25_to_router_5_26_rsp; - -floo_req_t router_5_26_to_router_5_27_req; -floo_rsp_t router_5_27_to_router_5_26_rsp; - -floo_req_t router_5_26_to_router_6_26_req; -floo_rsp_t router_6_26_to_router_5_26_rsp; - -floo_req_t router_5_26_to_magia_tile_ni_5_26_req; -floo_rsp_t magia_tile_ni_5_26_to_router_5_26_rsp; - -floo_req_t router_5_27_to_router_4_27_req; -floo_rsp_t router_4_27_to_router_5_27_rsp; - -floo_req_t router_5_27_to_router_5_26_req; -floo_rsp_t router_5_26_to_router_5_27_rsp; - -floo_req_t router_5_27_to_router_5_28_req; -floo_rsp_t router_5_28_to_router_5_27_rsp; - -floo_req_t router_5_27_to_router_6_27_req; -floo_rsp_t router_6_27_to_router_5_27_rsp; - -floo_req_t router_5_27_to_magia_tile_ni_5_27_req; -floo_rsp_t magia_tile_ni_5_27_to_router_5_27_rsp; - -floo_req_t router_5_28_to_router_4_28_req; -floo_rsp_t router_4_28_to_router_5_28_rsp; - -floo_req_t router_5_28_to_router_5_27_req; -floo_rsp_t router_5_27_to_router_5_28_rsp; - -floo_req_t router_5_28_to_router_5_29_req; -floo_rsp_t router_5_29_to_router_5_28_rsp; - -floo_req_t router_5_28_to_router_6_28_req; -floo_rsp_t router_6_28_to_router_5_28_rsp; - -floo_req_t router_5_28_to_magia_tile_ni_5_28_req; -floo_rsp_t magia_tile_ni_5_28_to_router_5_28_rsp; - -floo_req_t router_5_29_to_router_4_29_req; -floo_rsp_t router_4_29_to_router_5_29_rsp; - -floo_req_t router_5_29_to_router_5_28_req; -floo_rsp_t router_5_28_to_router_5_29_rsp; - -floo_req_t router_5_29_to_router_5_30_req; -floo_rsp_t router_5_30_to_router_5_29_rsp; - -floo_req_t router_5_29_to_router_6_29_req; -floo_rsp_t router_6_29_to_router_5_29_rsp; - -floo_req_t router_5_29_to_magia_tile_ni_5_29_req; -floo_rsp_t magia_tile_ni_5_29_to_router_5_29_rsp; - -floo_req_t router_5_30_to_router_4_30_req; -floo_rsp_t router_4_30_to_router_5_30_rsp; - -floo_req_t router_5_30_to_router_5_29_req; -floo_rsp_t router_5_29_to_router_5_30_rsp; - -floo_req_t router_5_30_to_router_5_31_req; -floo_rsp_t router_5_31_to_router_5_30_rsp; - -floo_req_t router_5_30_to_router_6_30_req; -floo_rsp_t router_6_30_to_router_5_30_rsp; - -floo_req_t router_5_30_to_magia_tile_ni_5_30_req; -floo_rsp_t magia_tile_ni_5_30_to_router_5_30_rsp; - -floo_req_t router_5_31_to_router_4_31_req; -floo_rsp_t router_4_31_to_router_5_31_rsp; - -floo_req_t router_5_31_to_router_5_30_req; -floo_rsp_t router_5_30_to_router_5_31_rsp; - -floo_req_t router_5_31_to_router_6_31_req; -floo_rsp_t router_6_31_to_router_5_31_rsp; - -floo_req_t router_5_31_to_magia_tile_ni_5_31_req; -floo_rsp_t magia_tile_ni_5_31_to_router_5_31_rsp; - -floo_req_t router_6_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_magia_tile_ni_6_0_req; -floo_rsp_t magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_req_t router_6_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_magia_tile_ni_6_1_req; -floo_rsp_t magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_req_t router_6_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_magia_tile_ni_6_2_req; -floo_rsp_t magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_req_t router_6_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_magia_tile_ni_6_3_req; -floo_rsp_t magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_req_t router_6_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_magia_tile_ni_6_4_req; -floo_rsp_t magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_req_t router_6_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_magia_tile_ni_6_5_req; -floo_rsp_t magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_req_t router_6_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_magia_tile_ni_6_6_req; -floo_rsp_t magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_req_t router_6_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_magia_tile_ni_6_7_req; -floo_rsp_t magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_req_t router_6_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_6_8_rsp; - -floo_req_t router_6_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_6_8_rsp; - -floo_req_t router_6_8_to_magia_tile_ni_6_8_req; -floo_rsp_t magia_tile_ni_6_8_to_router_6_8_rsp; - -floo_req_t router_6_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_6_9_rsp; - -floo_req_t router_6_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_6_9_rsp; - -floo_req_t router_6_9_to_magia_tile_ni_6_9_req; -floo_rsp_t magia_tile_ni_6_9_to_router_6_9_rsp; - -floo_req_t router_6_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_6_10_rsp; - -floo_req_t router_6_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_6_10_rsp; - -floo_req_t router_6_10_to_magia_tile_ni_6_10_req; -floo_rsp_t magia_tile_ni_6_10_to_router_6_10_rsp; - -floo_req_t router_6_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_6_11_rsp; - -floo_req_t router_6_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_6_11_rsp; - -floo_req_t router_6_11_to_magia_tile_ni_6_11_req; -floo_rsp_t magia_tile_ni_6_11_to_router_6_11_rsp; - -floo_req_t router_6_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_6_12_rsp; - -floo_req_t router_6_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_6_12_rsp; - -floo_req_t router_6_12_to_magia_tile_ni_6_12_req; -floo_rsp_t magia_tile_ni_6_12_to_router_6_12_rsp; - -floo_req_t router_6_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_6_13_rsp; - -floo_req_t router_6_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_6_13_rsp; - -floo_req_t router_6_13_to_magia_tile_ni_6_13_req; -floo_rsp_t magia_tile_ni_6_13_to_router_6_13_rsp; - -floo_req_t router_6_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_6_14_rsp; - -floo_req_t router_6_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_6_14_rsp; - -floo_req_t router_6_14_to_magia_tile_ni_6_14_req; -floo_rsp_t magia_tile_ni_6_14_to_router_6_14_rsp; - -floo_req_t router_6_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_router_6_15_rsp; - -floo_req_t router_6_15_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_6_15_rsp; - -floo_req_t router_6_15_to_router_6_16_req; -floo_rsp_t router_6_16_to_router_6_15_rsp; - -floo_req_t router_6_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_6_15_rsp; - -floo_req_t router_6_15_to_magia_tile_ni_6_15_req; -floo_rsp_t magia_tile_ni_6_15_to_router_6_15_rsp; - -floo_req_t router_6_16_to_router_5_16_req; -floo_rsp_t router_5_16_to_router_6_16_rsp; - -floo_req_t router_6_16_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_6_16_rsp; - -floo_req_t router_6_16_to_router_6_17_req; -floo_rsp_t router_6_17_to_router_6_16_rsp; - -floo_req_t router_6_16_to_router_7_16_req; -floo_rsp_t router_7_16_to_router_6_16_rsp; - -floo_req_t router_6_16_to_magia_tile_ni_6_16_req; -floo_rsp_t magia_tile_ni_6_16_to_router_6_16_rsp; - -floo_req_t router_6_17_to_router_5_17_req; -floo_rsp_t router_5_17_to_router_6_17_rsp; - -floo_req_t router_6_17_to_router_6_16_req; -floo_rsp_t router_6_16_to_router_6_17_rsp; - -floo_req_t router_6_17_to_router_6_18_req; -floo_rsp_t router_6_18_to_router_6_17_rsp; - -floo_req_t router_6_17_to_router_7_17_req; -floo_rsp_t router_7_17_to_router_6_17_rsp; - -floo_req_t router_6_17_to_magia_tile_ni_6_17_req; -floo_rsp_t magia_tile_ni_6_17_to_router_6_17_rsp; - -floo_req_t router_6_18_to_router_5_18_req; -floo_rsp_t router_5_18_to_router_6_18_rsp; - -floo_req_t router_6_18_to_router_6_17_req; -floo_rsp_t router_6_17_to_router_6_18_rsp; - -floo_req_t router_6_18_to_router_6_19_req; -floo_rsp_t router_6_19_to_router_6_18_rsp; - -floo_req_t router_6_18_to_router_7_18_req; -floo_rsp_t router_7_18_to_router_6_18_rsp; - -floo_req_t router_6_18_to_magia_tile_ni_6_18_req; -floo_rsp_t magia_tile_ni_6_18_to_router_6_18_rsp; - -floo_req_t router_6_19_to_router_5_19_req; -floo_rsp_t router_5_19_to_router_6_19_rsp; - -floo_req_t router_6_19_to_router_6_18_req; -floo_rsp_t router_6_18_to_router_6_19_rsp; - -floo_req_t router_6_19_to_router_6_20_req; -floo_rsp_t router_6_20_to_router_6_19_rsp; - -floo_req_t router_6_19_to_router_7_19_req; -floo_rsp_t router_7_19_to_router_6_19_rsp; - -floo_req_t router_6_19_to_magia_tile_ni_6_19_req; -floo_rsp_t magia_tile_ni_6_19_to_router_6_19_rsp; - -floo_req_t router_6_20_to_router_5_20_req; -floo_rsp_t router_5_20_to_router_6_20_rsp; - -floo_req_t router_6_20_to_router_6_19_req; -floo_rsp_t router_6_19_to_router_6_20_rsp; - -floo_req_t router_6_20_to_router_6_21_req; -floo_rsp_t router_6_21_to_router_6_20_rsp; - -floo_req_t router_6_20_to_router_7_20_req; -floo_rsp_t router_7_20_to_router_6_20_rsp; - -floo_req_t router_6_20_to_magia_tile_ni_6_20_req; -floo_rsp_t magia_tile_ni_6_20_to_router_6_20_rsp; - -floo_req_t router_6_21_to_router_5_21_req; -floo_rsp_t router_5_21_to_router_6_21_rsp; - -floo_req_t router_6_21_to_router_6_20_req; -floo_rsp_t router_6_20_to_router_6_21_rsp; - -floo_req_t router_6_21_to_router_6_22_req; -floo_rsp_t router_6_22_to_router_6_21_rsp; - -floo_req_t router_6_21_to_router_7_21_req; -floo_rsp_t router_7_21_to_router_6_21_rsp; - -floo_req_t router_6_21_to_magia_tile_ni_6_21_req; -floo_rsp_t magia_tile_ni_6_21_to_router_6_21_rsp; - -floo_req_t router_6_22_to_router_5_22_req; -floo_rsp_t router_5_22_to_router_6_22_rsp; - -floo_req_t router_6_22_to_router_6_21_req; -floo_rsp_t router_6_21_to_router_6_22_rsp; - -floo_req_t router_6_22_to_router_6_23_req; -floo_rsp_t router_6_23_to_router_6_22_rsp; - -floo_req_t router_6_22_to_router_7_22_req; -floo_rsp_t router_7_22_to_router_6_22_rsp; - -floo_req_t router_6_22_to_magia_tile_ni_6_22_req; -floo_rsp_t magia_tile_ni_6_22_to_router_6_22_rsp; - -floo_req_t router_6_23_to_router_5_23_req; -floo_rsp_t router_5_23_to_router_6_23_rsp; - -floo_req_t router_6_23_to_router_6_22_req; -floo_rsp_t router_6_22_to_router_6_23_rsp; - -floo_req_t router_6_23_to_router_6_24_req; -floo_rsp_t router_6_24_to_router_6_23_rsp; - -floo_req_t router_6_23_to_router_7_23_req; -floo_rsp_t router_7_23_to_router_6_23_rsp; - -floo_req_t router_6_23_to_magia_tile_ni_6_23_req; -floo_rsp_t magia_tile_ni_6_23_to_router_6_23_rsp; - -floo_req_t router_6_24_to_router_5_24_req; -floo_rsp_t router_5_24_to_router_6_24_rsp; - -floo_req_t router_6_24_to_router_6_23_req; -floo_rsp_t router_6_23_to_router_6_24_rsp; - -floo_req_t router_6_24_to_router_6_25_req; -floo_rsp_t router_6_25_to_router_6_24_rsp; - -floo_req_t router_6_24_to_router_7_24_req; -floo_rsp_t router_7_24_to_router_6_24_rsp; - -floo_req_t router_6_24_to_magia_tile_ni_6_24_req; -floo_rsp_t magia_tile_ni_6_24_to_router_6_24_rsp; - -floo_req_t router_6_25_to_router_5_25_req; -floo_rsp_t router_5_25_to_router_6_25_rsp; - -floo_req_t router_6_25_to_router_6_24_req; -floo_rsp_t router_6_24_to_router_6_25_rsp; - -floo_req_t router_6_25_to_router_6_26_req; -floo_rsp_t router_6_26_to_router_6_25_rsp; - -floo_req_t router_6_25_to_router_7_25_req; -floo_rsp_t router_7_25_to_router_6_25_rsp; - -floo_req_t router_6_25_to_magia_tile_ni_6_25_req; -floo_rsp_t magia_tile_ni_6_25_to_router_6_25_rsp; - -floo_req_t router_6_26_to_router_5_26_req; -floo_rsp_t router_5_26_to_router_6_26_rsp; - -floo_req_t router_6_26_to_router_6_25_req; -floo_rsp_t router_6_25_to_router_6_26_rsp; - -floo_req_t router_6_26_to_router_6_27_req; -floo_rsp_t router_6_27_to_router_6_26_rsp; - -floo_req_t router_6_26_to_router_7_26_req; -floo_rsp_t router_7_26_to_router_6_26_rsp; - -floo_req_t router_6_26_to_magia_tile_ni_6_26_req; -floo_rsp_t magia_tile_ni_6_26_to_router_6_26_rsp; - -floo_req_t router_6_27_to_router_5_27_req; -floo_rsp_t router_5_27_to_router_6_27_rsp; - -floo_req_t router_6_27_to_router_6_26_req; -floo_rsp_t router_6_26_to_router_6_27_rsp; - -floo_req_t router_6_27_to_router_6_28_req; -floo_rsp_t router_6_28_to_router_6_27_rsp; - -floo_req_t router_6_27_to_router_7_27_req; -floo_rsp_t router_7_27_to_router_6_27_rsp; - -floo_req_t router_6_27_to_magia_tile_ni_6_27_req; -floo_rsp_t magia_tile_ni_6_27_to_router_6_27_rsp; - -floo_req_t router_6_28_to_router_5_28_req; -floo_rsp_t router_5_28_to_router_6_28_rsp; - -floo_req_t router_6_28_to_router_6_27_req; -floo_rsp_t router_6_27_to_router_6_28_rsp; - -floo_req_t router_6_28_to_router_6_29_req; -floo_rsp_t router_6_29_to_router_6_28_rsp; - -floo_req_t router_6_28_to_router_7_28_req; -floo_rsp_t router_7_28_to_router_6_28_rsp; - -floo_req_t router_6_28_to_magia_tile_ni_6_28_req; -floo_rsp_t magia_tile_ni_6_28_to_router_6_28_rsp; - -floo_req_t router_6_29_to_router_5_29_req; -floo_rsp_t router_5_29_to_router_6_29_rsp; - -floo_req_t router_6_29_to_router_6_28_req; -floo_rsp_t router_6_28_to_router_6_29_rsp; - -floo_req_t router_6_29_to_router_6_30_req; -floo_rsp_t router_6_30_to_router_6_29_rsp; - -floo_req_t router_6_29_to_router_7_29_req; -floo_rsp_t router_7_29_to_router_6_29_rsp; - -floo_req_t router_6_29_to_magia_tile_ni_6_29_req; -floo_rsp_t magia_tile_ni_6_29_to_router_6_29_rsp; - -floo_req_t router_6_30_to_router_5_30_req; -floo_rsp_t router_5_30_to_router_6_30_rsp; - -floo_req_t router_6_30_to_router_6_29_req; -floo_rsp_t router_6_29_to_router_6_30_rsp; - -floo_req_t router_6_30_to_router_6_31_req; -floo_rsp_t router_6_31_to_router_6_30_rsp; - -floo_req_t router_6_30_to_router_7_30_req; -floo_rsp_t router_7_30_to_router_6_30_rsp; - -floo_req_t router_6_30_to_magia_tile_ni_6_30_req; -floo_rsp_t magia_tile_ni_6_30_to_router_6_30_rsp; - -floo_req_t router_6_31_to_router_5_31_req; -floo_rsp_t router_5_31_to_router_6_31_rsp; - -floo_req_t router_6_31_to_router_6_30_req; -floo_rsp_t router_6_30_to_router_6_31_rsp; - -floo_req_t router_6_31_to_router_7_31_req; -floo_rsp_t router_7_31_to_router_6_31_rsp; - -floo_req_t router_6_31_to_magia_tile_ni_6_31_req; -floo_rsp_t magia_tile_ni_6_31_to_router_6_31_rsp; - -floo_req_t router_7_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_7_0_rsp; - -floo_req_t router_7_0_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_0_rsp; - -floo_req_t router_7_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_7_0_rsp; - -floo_req_t router_7_0_to_magia_tile_ni_7_0_req; -floo_rsp_t magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_req_t router_7_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_7_1_rsp; - -floo_req_t router_7_1_to_magia_tile_ni_7_1_req; -floo_rsp_t magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_req_t router_7_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_7_2_rsp; - -floo_req_t router_7_2_to_magia_tile_ni_7_2_req; -floo_rsp_t magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_req_t router_7_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_7_3_rsp; - -floo_req_t router_7_3_to_magia_tile_ni_7_3_req; -floo_rsp_t magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_req_t router_7_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_7_4_rsp; - -floo_req_t router_7_4_to_magia_tile_ni_7_4_req; -floo_rsp_t magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_req_t router_7_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_7_5_rsp; - -floo_req_t router_7_5_to_magia_tile_ni_7_5_req; -floo_rsp_t magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_req_t router_7_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_7_6_rsp; - -floo_req_t router_7_6_to_magia_tile_ni_7_6_req; -floo_rsp_t magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_req_t router_7_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_7_7_rsp; - -floo_req_t router_7_7_to_magia_tile_ni_7_7_req; -floo_rsp_t magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_req_t router_7_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_7_8_rsp; - -floo_req_t router_7_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_7_8_rsp; - -floo_req_t router_7_8_to_magia_tile_ni_7_8_req; -floo_rsp_t magia_tile_ni_7_8_to_router_7_8_rsp; - -floo_req_t router_7_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_7_9_rsp; - -floo_req_t router_7_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_7_9_rsp; - -floo_req_t router_7_9_to_magia_tile_ni_7_9_req; -floo_rsp_t magia_tile_ni_7_9_to_router_7_9_rsp; - -floo_req_t router_7_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_7_10_rsp; - -floo_req_t router_7_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_7_10_rsp; - -floo_req_t router_7_10_to_magia_tile_ni_7_10_req; -floo_rsp_t magia_tile_ni_7_10_to_router_7_10_rsp; - -floo_req_t router_7_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_7_11_rsp; - -floo_req_t router_7_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_7_11_rsp; - -floo_req_t router_7_11_to_magia_tile_ni_7_11_req; -floo_rsp_t magia_tile_ni_7_11_to_router_7_11_rsp; - -floo_req_t router_7_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_7_12_rsp; - -floo_req_t router_7_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_7_12_rsp; - -floo_req_t router_7_12_to_magia_tile_ni_7_12_req; -floo_rsp_t magia_tile_ni_7_12_to_router_7_12_rsp; - -floo_req_t router_7_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_7_13_rsp; - -floo_req_t router_7_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_7_13_rsp; - -floo_req_t router_7_13_to_magia_tile_ni_7_13_req; -floo_rsp_t magia_tile_ni_7_13_to_router_7_13_rsp; - -floo_req_t router_7_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_7_14_rsp; - -floo_req_t router_7_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_7_14_rsp; - -floo_req_t router_7_14_to_magia_tile_ni_7_14_req; -floo_rsp_t magia_tile_ni_7_14_to_router_7_14_rsp; - -floo_req_t router_7_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_router_7_15_rsp; - -floo_req_t router_7_15_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_7_15_rsp; - -floo_req_t router_7_15_to_router_7_16_req; -floo_rsp_t router_7_16_to_router_7_15_rsp; - -floo_req_t router_7_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_7_15_rsp; - -floo_req_t router_7_15_to_magia_tile_ni_7_15_req; -floo_rsp_t magia_tile_ni_7_15_to_router_7_15_rsp; - -floo_req_t router_7_16_to_router_6_16_req; -floo_rsp_t router_6_16_to_router_7_16_rsp; - -floo_req_t router_7_16_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_7_16_rsp; - -floo_req_t router_7_16_to_router_7_17_req; -floo_rsp_t router_7_17_to_router_7_16_rsp; - -floo_req_t router_7_16_to_router_8_16_req; -floo_rsp_t router_8_16_to_router_7_16_rsp; - -floo_req_t router_7_16_to_magia_tile_ni_7_16_req; -floo_rsp_t magia_tile_ni_7_16_to_router_7_16_rsp; - -floo_req_t router_7_17_to_router_6_17_req; -floo_rsp_t router_6_17_to_router_7_17_rsp; - -floo_req_t router_7_17_to_router_7_16_req; -floo_rsp_t router_7_16_to_router_7_17_rsp; - -floo_req_t router_7_17_to_router_7_18_req; -floo_rsp_t router_7_18_to_router_7_17_rsp; - -floo_req_t router_7_17_to_router_8_17_req; -floo_rsp_t router_8_17_to_router_7_17_rsp; - -floo_req_t router_7_17_to_magia_tile_ni_7_17_req; -floo_rsp_t magia_tile_ni_7_17_to_router_7_17_rsp; - -floo_req_t router_7_18_to_router_6_18_req; -floo_rsp_t router_6_18_to_router_7_18_rsp; - -floo_req_t router_7_18_to_router_7_17_req; -floo_rsp_t router_7_17_to_router_7_18_rsp; - -floo_req_t router_7_18_to_router_7_19_req; -floo_rsp_t router_7_19_to_router_7_18_rsp; - -floo_req_t router_7_18_to_router_8_18_req; -floo_rsp_t router_8_18_to_router_7_18_rsp; - -floo_req_t router_7_18_to_magia_tile_ni_7_18_req; -floo_rsp_t magia_tile_ni_7_18_to_router_7_18_rsp; - -floo_req_t router_7_19_to_router_6_19_req; -floo_rsp_t router_6_19_to_router_7_19_rsp; - -floo_req_t router_7_19_to_router_7_18_req; -floo_rsp_t router_7_18_to_router_7_19_rsp; - -floo_req_t router_7_19_to_router_7_20_req; -floo_rsp_t router_7_20_to_router_7_19_rsp; - -floo_req_t router_7_19_to_router_8_19_req; -floo_rsp_t router_8_19_to_router_7_19_rsp; - -floo_req_t router_7_19_to_magia_tile_ni_7_19_req; -floo_rsp_t magia_tile_ni_7_19_to_router_7_19_rsp; - -floo_req_t router_7_20_to_router_6_20_req; -floo_rsp_t router_6_20_to_router_7_20_rsp; - -floo_req_t router_7_20_to_router_7_19_req; -floo_rsp_t router_7_19_to_router_7_20_rsp; - -floo_req_t router_7_20_to_router_7_21_req; -floo_rsp_t router_7_21_to_router_7_20_rsp; - -floo_req_t router_7_20_to_router_8_20_req; -floo_rsp_t router_8_20_to_router_7_20_rsp; - -floo_req_t router_7_20_to_magia_tile_ni_7_20_req; -floo_rsp_t magia_tile_ni_7_20_to_router_7_20_rsp; - -floo_req_t router_7_21_to_router_6_21_req; -floo_rsp_t router_6_21_to_router_7_21_rsp; - -floo_req_t router_7_21_to_router_7_20_req; -floo_rsp_t router_7_20_to_router_7_21_rsp; - -floo_req_t router_7_21_to_router_7_22_req; -floo_rsp_t router_7_22_to_router_7_21_rsp; - -floo_req_t router_7_21_to_router_8_21_req; -floo_rsp_t router_8_21_to_router_7_21_rsp; - -floo_req_t router_7_21_to_magia_tile_ni_7_21_req; -floo_rsp_t magia_tile_ni_7_21_to_router_7_21_rsp; - -floo_req_t router_7_22_to_router_6_22_req; -floo_rsp_t router_6_22_to_router_7_22_rsp; - -floo_req_t router_7_22_to_router_7_21_req; -floo_rsp_t router_7_21_to_router_7_22_rsp; - -floo_req_t router_7_22_to_router_7_23_req; -floo_rsp_t router_7_23_to_router_7_22_rsp; - -floo_req_t router_7_22_to_router_8_22_req; -floo_rsp_t router_8_22_to_router_7_22_rsp; - -floo_req_t router_7_22_to_magia_tile_ni_7_22_req; -floo_rsp_t magia_tile_ni_7_22_to_router_7_22_rsp; - -floo_req_t router_7_23_to_router_6_23_req; -floo_rsp_t router_6_23_to_router_7_23_rsp; - -floo_req_t router_7_23_to_router_7_22_req; -floo_rsp_t router_7_22_to_router_7_23_rsp; - -floo_req_t router_7_23_to_router_7_24_req; -floo_rsp_t router_7_24_to_router_7_23_rsp; - -floo_req_t router_7_23_to_router_8_23_req; -floo_rsp_t router_8_23_to_router_7_23_rsp; - -floo_req_t router_7_23_to_magia_tile_ni_7_23_req; -floo_rsp_t magia_tile_ni_7_23_to_router_7_23_rsp; - -floo_req_t router_7_24_to_router_6_24_req; -floo_rsp_t router_6_24_to_router_7_24_rsp; - -floo_req_t router_7_24_to_router_7_23_req; -floo_rsp_t router_7_23_to_router_7_24_rsp; - -floo_req_t router_7_24_to_router_7_25_req; -floo_rsp_t router_7_25_to_router_7_24_rsp; - -floo_req_t router_7_24_to_router_8_24_req; -floo_rsp_t router_8_24_to_router_7_24_rsp; - -floo_req_t router_7_24_to_magia_tile_ni_7_24_req; -floo_rsp_t magia_tile_ni_7_24_to_router_7_24_rsp; - -floo_req_t router_7_25_to_router_6_25_req; -floo_rsp_t router_6_25_to_router_7_25_rsp; - -floo_req_t router_7_25_to_router_7_24_req; -floo_rsp_t router_7_24_to_router_7_25_rsp; - -floo_req_t router_7_25_to_router_7_26_req; -floo_rsp_t router_7_26_to_router_7_25_rsp; - -floo_req_t router_7_25_to_router_8_25_req; -floo_rsp_t router_8_25_to_router_7_25_rsp; - -floo_req_t router_7_25_to_magia_tile_ni_7_25_req; -floo_rsp_t magia_tile_ni_7_25_to_router_7_25_rsp; - -floo_req_t router_7_26_to_router_6_26_req; -floo_rsp_t router_6_26_to_router_7_26_rsp; - -floo_req_t router_7_26_to_router_7_25_req; -floo_rsp_t router_7_25_to_router_7_26_rsp; - -floo_req_t router_7_26_to_router_7_27_req; -floo_rsp_t router_7_27_to_router_7_26_rsp; - -floo_req_t router_7_26_to_router_8_26_req; -floo_rsp_t router_8_26_to_router_7_26_rsp; - -floo_req_t router_7_26_to_magia_tile_ni_7_26_req; -floo_rsp_t magia_tile_ni_7_26_to_router_7_26_rsp; - -floo_req_t router_7_27_to_router_6_27_req; -floo_rsp_t router_6_27_to_router_7_27_rsp; - -floo_req_t router_7_27_to_router_7_26_req; -floo_rsp_t router_7_26_to_router_7_27_rsp; - -floo_req_t router_7_27_to_router_7_28_req; -floo_rsp_t router_7_28_to_router_7_27_rsp; - -floo_req_t router_7_27_to_router_8_27_req; -floo_rsp_t router_8_27_to_router_7_27_rsp; - -floo_req_t router_7_27_to_magia_tile_ni_7_27_req; -floo_rsp_t magia_tile_ni_7_27_to_router_7_27_rsp; - -floo_req_t router_7_28_to_router_6_28_req; -floo_rsp_t router_6_28_to_router_7_28_rsp; - -floo_req_t router_7_28_to_router_7_27_req; -floo_rsp_t router_7_27_to_router_7_28_rsp; - -floo_req_t router_7_28_to_router_7_29_req; -floo_rsp_t router_7_29_to_router_7_28_rsp; - -floo_req_t router_7_28_to_router_8_28_req; -floo_rsp_t router_8_28_to_router_7_28_rsp; - -floo_req_t router_7_28_to_magia_tile_ni_7_28_req; -floo_rsp_t magia_tile_ni_7_28_to_router_7_28_rsp; - -floo_req_t router_7_29_to_router_6_29_req; -floo_rsp_t router_6_29_to_router_7_29_rsp; - -floo_req_t router_7_29_to_router_7_28_req; -floo_rsp_t router_7_28_to_router_7_29_rsp; - -floo_req_t router_7_29_to_router_7_30_req; -floo_rsp_t router_7_30_to_router_7_29_rsp; - -floo_req_t router_7_29_to_router_8_29_req; -floo_rsp_t router_8_29_to_router_7_29_rsp; - -floo_req_t router_7_29_to_magia_tile_ni_7_29_req; -floo_rsp_t magia_tile_ni_7_29_to_router_7_29_rsp; - -floo_req_t router_7_30_to_router_6_30_req; -floo_rsp_t router_6_30_to_router_7_30_rsp; - -floo_req_t router_7_30_to_router_7_29_req; -floo_rsp_t router_7_29_to_router_7_30_rsp; - -floo_req_t router_7_30_to_router_7_31_req; -floo_rsp_t router_7_31_to_router_7_30_rsp; - -floo_req_t router_7_30_to_router_8_30_req; -floo_rsp_t router_8_30_to_router_7_30_rsp; - -floo_req_t router_7_30_to_magia_tile_ni_7_30_req; -floo_rsp_t magia_tile_ni_7_30_to_router_7_30_rsp; - -floo_req_t router_7_31_to_router_6_31_req; -floo_rsp_t router_6_31_to_router_7_31_rsp; - -floo_req_t router_7_31_to_router_7_30_req; -floo_rsp_t router_7_30_to_router_7_31_rsp; - -floo_req_t router_7_31_to_router_8_31_req; -floo_rsp_t router_8_31_to_router_7_31_rsp; - -floo_req_t router_7_31_to_magia_tile_ni_7_31_req; -floo_rsp_t magia_tile_ni_7_31_to_router_7_31_rsp; - -floo_req_t router_8_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_8_0_rsp; - -floo_req_t router_8_0_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_8_0_rsp; - -floo_req_t router_8_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_8_0_rsp; - -floo_req_t router_8_0_to_magia_tile_ni_8_0_req; -floo_rsp_t magia_tile_ni_8_0_to_router_8_0_rsp; - -floo_req_t router_8_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_8_1_rsp; - -floo_req_t router_8_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_8_1_rsp; - -floo_req_t router_8_1_to_magia_tile_ni_8_1_req; -floo_rsp_t magia_tile_ni_8_1_to_router_8_1_rsp; - -floo_req_t router_8_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_8_2_rsp; - -floo_req_t router_8_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_8_2_rsp; - -floo_req_t router_8_2_to_magia_tile_ni_8_2_req; -floo_rsp_t magia_tile_ni_8_2_to_router_8_2_rsp; - -floo_req_t router_8_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_8_3_rsp; - -floo_req_t router_8_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_8_3_rsp; - -floo_req_t router_8_3_to_magia_tile_ni_8_3_req; -floo_rsp_t magia_tile_ni_8_3_to_router_8_3_rsp; - -floo_req_t router_8_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_8_4_rsp; - -floo_req_t router_8_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_8_4_rsp; - -floo_req_t router_8_4_to_magia_tile_ni_8_4_req; -floo_rsp_t magia_tile_ni_8_4_to_router_8_4_rsp; - -floo_req_t router_8_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_8_5_rsp; - -floo_req_t router_8_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_8_5_rsp; - -floo_req_t router_8_5_to_magia_tile_ni_8_5_req; -floo_rsp_t magia_tile_ni_8_5_to_router_8_5_rsp; - -floo_req_t router_8_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_8_6_rsp; - -floo_req_t router_8_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_8_6_rsp; - -floo_req_t router_8_6_to_magia_tile_ni_8_6_req; -floo_rsp_t magia_tile_ni_8_6_to_router_8_6_rsp; - -floo_req_t router_8_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_8_7_rsp; - -floo_req_t router_8_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_8_7_rsp; - -floo_req_t router_8_7_to_magia_tile_ni_8_7_req; -floo_rsp_t magia_tile_ni_8_7_to_router_8_7_rsp; - -floo_req_t router_8_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_8_8_rsp; - -floo_req_t router_8_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_8_8_rsp; - -floo_req_t router_8_8_to_magia_tile_ni_8_8_req; -floo_rsp_t magia_tile_ni_8_8_to_router_8_8_rsp; - -floo_req_t router_8_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_8_9_rsp; - -floo_req_t router_8_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_8_9_rsp; - -floo_req_t router_8_9_to_magia_tile_ni_8_9_req; -floo_rsp_t magia_tile_ni_8_9_to_router_8_9_rsp; - -floo_req_t router_8_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_8_10_rsp; - -floo_req_t router_8_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_8_10_rsp; - -floo_req_t router_8_10_to_magia_tile_ni_8_10_req; -floo_rsp_t magia_tile_ni_8_10_to_router_8_10_rsp; - -floo_req_t router_8_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_8_11_rsp; - -floo_req_t router_8_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_8_11_rsp; - -floo_req_t router_8_11_to_magia_tile_ni_8_11_req; -floo_rsp_t magia_tile_ni_8_11_to_router_8_11_rsp; - -floo_req_t router_8_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_8_12_rsp; - -floo_req_t router_8_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_8_12_rsp; - -floo_req_t router_8_12_to_magia_tile_ni_8_12_req; -floo_rsp_t magia_tile_ni_8_12_to_router_8_12_rsp; - -floo_req_t router_8_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_8_13_rsp; - -floo_req_t router_8_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_8_13_rsp; - -floo_req_t router_8_13_to_magia_tile_ni_8_13_req; -floo_rsp_t magia_tile_ni_8_13_to_router_8_13_rsp; - -floo_req_t router_8_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_8_14_rsp; - -floo_req_t router_8_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_8_14_rsp; - -floo_req_t router_8_14_to_magia_tile_ni_8_14_req; -floo_rsp_t magia_tile_ni_8_14_to_router_8_14_rsp; - -floo_req_t router_8_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_router_8_15_rsp; - -floo_req_t router_8_15_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_8_15_rsp; - -floo_req_t router_8_15_to_router_8_16_req; -floo_rsp_t router_8_16_to_router_8_15_rsp; - -floo_req_t router_8_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_8_15_rsp; - -floo_req_t router_8_15_to_magia_tile_ni_8_15_req; -floo_rsp_t magia_tile_ni_8_15_to_router_8_15_rsp; - -floo_req_t router_8_16_to_router_7_16_req; -floo_rsp_t router_7_16_to_router_8_16_rsp; - -floo_req_t router_8_16_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_8_16_rsp; - -floo_req_t router_8_16_to_router_8_17_req; -floo_rsp_t router_8_17_to_router_8_16_rsp; - -floo_req_t router_8_16_to_router_9_16_req; -floo_rsp_t router_9_16_to_router_8_16_rsp; - -floo_req_t router_8_16_to_magia_tile_ni_8_16_req; -floo_rsp_t magia_tile_ni_8_16_to_router_8_16_rsp; - -floo_req_t router_8_17_to_router_7_17_req; -floo_rsp_t router_7_17_to_router_8_17_rsp; - -floo_req_t router_8_17_to_router_8_16_req; -floo_rsp_t router_8_16_to_router_8_17_rsp; - -floo_req_t router_8_17_to_router_8_18_req; -floo_rsp_t router_8_18_to_router_8_17_rsp; - -floo_req_t router_8_17_to_router_9_17_req; -floo_rsp_t router_9_17_to_router_8_17_rsp; - -floo_req_t router_8_17_to_magia_tile_ni_8_17_req; -floo_rsp_t magia_tile_ni_8_17_to_router_8_17_rsp; - -floo_req_t router_8_18_to_router_7_18_req; -floo_rsp_t router_7_18_to_router_8_18_rsp; - -floo_req_t router_8_18_to_router_8_17_req; -floo_rsp_t router_8_17_to_router_8_18_rsp; - -floo_req_t router_8_18_to_router_8_19_req; -floo_rsp_t router_8_19_to_router_8_18_rsp; - -floo_req_t router_8_18_to_router_9_18_req; -floo_rsp_t router_9_18_to_router_8_18_rsp; - -floo_req_t router_8_18_to_magia_tile_ni_8_18_req; -floo_rsp_t magia_tile_ni_8_18_to_router_8_18_rsp; - -floo_req_t router_8_19_to_router_7_19_req; -floo_rsp_t router_7_19_to_router_8_19_rsp; - -floo_req_t router_8_19_to_router_8_18_req; -floo_rsp_t router_8_18_to_router_8_19_rsp; - -floo_req_t router_8_19_to_router_8_20_req; -floo_rsp_t router_8_20_to_router_8_19_rsp; - -floo_req_t router_8_19_to_router_9_19_req; -floo_rsp_t router_9_19_to_router_8_19_rsp; - -floo_req_t router_8_19_to_magia_tile_ni_8_19_req; -floo_rsp_t magia_tile_ni_8_19_to_router_8_19_rsp; - -floo_req_t router_8_20_to_router_7_20_req; -floo_rsp_t router_7_20_to_router_8_20_rsp; - -floo_req_t router_8_20_to_router_8_19_req; -floo_rsp_t router_8_19_to_router_8_20_rsp; - -floo_req_t router_8_20_to_router_8_21_req; -floo_rsp_t router_8_21_to_router_8_20_rsp; - -floo_req_t router_8_20_to_router_9_20_req; -floo_rsp_t router_9_20_to_router_8_20_rsp; - -floo_req_t router_8_20_to_magia_tile_ni_8_20_req; -floo_rsp_t magia_tile_ni_8_20_to_router_8_20_rsp; - -floo_req_t router_8_21_to_router_7_21_req; -floo_rsp_t router_7_21_to_router_8_21_rsp; - -floo_req_t router_8_21_to_router_8_20_req; -floo_rsp_t router_8_20_to_router_8_21_rsp; - -floo_req_t router_8_21_to_router_8_22_req; -floo_rsp_t router_8_22_to_router_8_21_rsp; - -floo_req_t router_8_21_to_router_9_21_req; -floo_rsp_t router_9_21_to_router_8_21_rsp; - -floo_req_t router_8_21_to_magia_tile_ni_8_21_req; -floo_rsp_t magia_tile_ni_8_21_to_router_8_21_rsp; - -floo_req_t router_8_22_to_router_7_22_req; -floo_rsp_t router_7_22_to_router_8_22_rsp; - -floo_req_t router_8_22_to_router_8_21_req; -floo_rsp_t router_8_21_to_router_8_22_rsp; - -floo_req_t router_8_22_to_router_8_23_req; -floo_rsp_t router_8_23_to_router_8_22_rsp; - -floo_req_t router_8_22_to_router_9_22_req; -floo_rsp_t router_9_22_to_router_8_22_rsp; - -floo_req_t router_8_22_to_magia_tile_ni_8_22_req; -floo_rsp_t magia_tile_ni_8_22_to_router_8_22_rsp; - -floo_req_t router_8_23_to_router_7_23_req; -floo_rsp_t router_7_23_to_router_8_23_rsp; - -floo_req_t router_8_23_to_router_8_22_req; -floo_rsp_t router_8_22_to_router_8_23_rsp; - -floo_req_t router_8_23_to_router_8_24_req; -floo_rsp_t router_8_24_to_router_8_23_rsp; - -floo_req_t router_8_23_to_router_9_23_req; -floo_rsp_t router_9_23_to_router_8_23_rsp; - -floo_req_t router_8_23_to_magia_tile_ni_8_23_req; -floo_rsp_t magia_tile_ni_8_23_to_router_8_23_rsp; - -floo_req_t router_8_24_to_router_7_24_req; -floo_rsp_t router_7_24_to_router_8_24_rsp; - -floo_req_t router_8_24_to_router_8_23_req; -floo_rsp_t router_8_23_to_router_8_24_rsp; - -floo_req_t router_8_24_to_router_8_25_req; -floo_rsp_t router_8_25_to_router_8_24_rsp; - -floo_req_t router_8_24_to_router_9_24_req; -floo_rsp_t router_9_24_to_router_8_24_rsp; - -floo_req_t router_8_24_to_magia_tile_ni_8_24_req; -floo_rsp_t magia_tile_ni_8_24_to_router_8_24_rsp; - -floo_req_t router_8_25_to_router_7_25_req; -floo_rsp_t router_7_25_to_router_8_25_rsp; - -floo_req_t router_8_25_to_router_8_24_req; -floo_rsp_t router_8_24_to_router_8_25_rsp; - -floo_req_t router_8_25_to_router_8_26_req; -floo_rsp_t router_8_26_to_router_8_25_rsp; - -floo_req_t router_8_25_to_router_9_25_req; -floo_rsp_t router_9_25_to_router_8_25_rsp; - -floo_req_t router_8_25_to_magia_tile_ni_8_25_req; -floo_rsp_t magia_tile_ni_8_25_to_router_8_25_rsp; - -floo_req_t router_8_26_to_router_7_26_req; -floo_rsp_t router_7_26_to_router_8_26_rsp; - -floo_req_t router_8_26_to_router_8_25_req; -floo_rsp_t router_8_25_to_router_8_26_rsp; - -floo_req_t router_8_26_to_router_8_27_req; -floo_rsp_t router_8_27_to_router_8_26_rsp; - -floo_req_t router_8_26_to_router_9_26_req; -floo_rsp_t router_9_26_to_router_8_26_rsp; - -floo_req_t router_8_26_to_magia_tile_ni_8_26_req; -floo_rsp_t magia_tile_ni_8_26_to_router_8_26_rsp; - -floo_req_t router_8_27_to_router_7_27_req; -floo_rsp_t router_7_27_to_router_8_27_rsp; - -floo_req_t router_8_27_to_router_8_26_req; -floo_rsp_t router_8_26_to_router_8_27_rsp; - -floo_req_t router_8_27_to_router_8_28_req; -floo_rsp_t router_8_28_to_router_8_27_rsp; - -floo_req_t router_8_27_to_router_9_27_req; -floo_rsp_t router_9_27_to_router_8_27_rsp; - -floo_req_t router_8_27_to_magia_tile_ni_8_27_req; -floo_rsp_t magia_tile_ni_8_27_to_router_8_27_rsp; - -floo_req_t router_8_28_to_router_7_28_req; -floo_rsp_t router_7_28_to_router_8_28_rsp; - -floo_req_t router_8_28_to_router_8_27_req; -floo_rsp_t router_8_27_to_router_8_28_rsp; - -floo_req_t router_8_28_to_router_8_29_req; -floo_rsp_t router_8_29_to_router_8_28_rsp; - -floo_req_t router_8_28_to_router_9_28_req; -floo_rsp_t router_9_28_to_router_8_28_rsp; - -floo_req_t router_8_28_to_magia_tile_ni_8_28_req; -floo_rsp_t magia_tile_ni_8_28_to_router_8_28_rsp; - -floo_req_t router_8_29_to_router_7_29_req; -floo_rsp_t router_7_29_to_router_8_29_rsp; - -floo_req_t router_8_29_to_router_8_28_req; -floo_rsp_t router_8_28_to_router_8_29_rsp; - -floo_req_t router_8_29_to_router_8_30_req; -floo_rsp_t router_8_30_to_router_8_29_rsp; - -floo_req_t router_8_29_to_router_9_29_req; -floo_rsp_t router_9_29_to_router_8_29_rsp; - -floo_req_t router_8_29_to_magia_tile_ni_8_29_req; -floo_rsp_t magia_tile_ni_8_29_to_router_8_29_rsp; - -floo_req_t router_8_30_to_router_7_30_req; -floo_rsp_t router_7_30_to_router_8_30_rsp; - -floo_req_t router_8_30_to_router_8_29_req; -floo_rsp_t router_8_29_to_router_8_30_rsp; - -floo_req_t router_8_30_to_router_8_31_req; -floo_rsp_t router_8_31_to_router_8_30_rsp; - -floo_req_t router_8_30_to_router_9_30_req; -floo_rsp_t router_9_30_to_router_8_30_rsp; - -floo_req_t router_8_30_to_magia_tile_ni_8_30_req; -floo_rsp_t magia_tile_ni_8_30_to_router_8_30_rsp; - -floo_req_t router_8_31_to_router_7_31_req; -floo_rsp_t router_7_31_to_router_8_31_rsp; - -floo_req_t router_8_31_to_router_8_30_req; -floo_rsp_t router_8_30_to_router_8_31_rsp; - -floo_req_t router_8_31_to_router_9_31_req; -floo_rsp_t router_9_31_to_router_8_31_rsp; - -floo_req_t router_8_31_to_magia_tile_ni_8_31_req; -floo_rsp_t magia_tile_ni_8_31_to_router_8_31_rsp; - -floo_req_t router_9_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_router_9_0_rsp; - -floo_req_t router_9_0_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_9_0_rsp; - -floo_req_t router_9_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_9_0_rsp; - -floo_req_t router_9_0_to_magia_tile_ni_9_0_req; -floo_rsp_t magia_tile_ni_9_0_to_router_9_0_rsp; - -floo_req_t router_9_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_9_1_rsp; - -floo_req_t router_9_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_9_1_rsp; - -floo_req_t router_9_1_to_magia_tile_ni_9_1_req; -floo_rsp_t magia_tile_ni_9_1_to_router_9_1_rsp; - -floo_req_t router_9_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_9_2_rsp; - -floo_req_t router_9_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_9_2_rsp; - -floo_req_t router_9_2_to_magia_tile_ni_9_2_req; -floo_rsp_t magia_tile_ni_9_2_to_router_9_2_rsp; - -floo_req_t router_9_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_9_3_rsp; - -floo_req_t router_9_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_9_3_rsp; - -floo_req_t router_9_3_to_magia_tile_ni_9_3_req; -floo_rsp_t magia_tile_ni_9_3_to_router_9_3_rsp; - -floo_req_t router_9_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_9_4_rsp; - -floo_req_t router_9_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_9_4_rsp; - -floo_req_t router_9_4_to_magia_tile_ni_9_4_req; -floo_rsp_t magia_tile_ni_9_4_to_router_9_4_rsp; - -floo_req_t router_9_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_9_5_rsp; - -floo_req_t router_9_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_9_5_rsp; - -floo_req_t router_9_5_to_magia_tile_ni_9_5_req; -floo_rsp_t magia_tile_ni_9_5_to_router_9_5_rsp; - -floo_req_t router_9_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_9_6_rsp; - -floo_req_t router_9_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_9_6_rsp; - -floo_req_t router_9_6_to_magia_tile_ni_9_6_req; -floo_rsp_t magia_tile_ni_9_6_to_router_9_6_rsp; - -floo_req_t router_9_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_9_7_rsp; - -floo_req_t router_9_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_9_7_rsp; - -floo_req_t router_9_7_to_magia_tile_ni_9_7_req; -floo_rsp_t magia_tile_ni_9_7_to_router_9_7_rsp; - -floo_req_t router_9_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_9_8_rsp; - -floo_req_t router_9_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_9_8_rsp; - -floo_req_t router_9_8_to_magia_tile_ni_9_8_req; -floo_rsp_t magia_tile_ni_9_8_to_router_9_8_rsp; - -floo_req_t router_9_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_9_9_rsp; - -floo_req_t router_9_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_9_9_rsp; - -floo_req_t router_9_9_to_magia_tile_ni_9_9_req; -floo_rsp_t magia_tile_ni_9_9_to_router_9_9_rsp; - -floo_req_t router_9_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_9_10_rsp; - -floo_req_t router_9_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_9_10_rsp; - -floo_req_t router_9_10_to_magia_tile_ni_9_10_req; -floo_rsp_t magia_tile_ni_9_10_to_router_9_10_rsp; - -floo_req_t router_9_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_9_11_rsp; - -floo_req_t router_9_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_9_11_rsp; - -floo_req_t router_9_11_to_magia_tile_ni_9_11_req; -floo_rsp_t magia_tile_ni_9_11_to_router_9_11_rsp; - -floo_req_t router_9_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_9_12_rsp; - -floo_req_t router_9_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_9_12_rsp; - -floo_req_t router_9_12_to_magia_tile_ni_9_12_req; -floo_rsp_t magia_tile_ni_9_12_to_router_9_12_rsp; - -floo_req_t router_9_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_9_13_rsp; - -floo_req_t router_9_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_9_13_rsp; - -floo_req_t router_9_13_to_magia_tile_ni_9_13_req; -floo_rsp_t magia_tile_ni_9_13_to_router_9_13_rsp; - -floo_req_t router_9_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_9_14_rsp; - -floo_req_t router_9_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_9_14_rsp; - -floo_req_t router_9_14_to_magia_tile_ni_9_14_req; -floo_rsp_t magia_tile_ni_9_14_to_router_9_14_rsp; - -floo_req_t router_9_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_router_9_15_rsp; - -floo_req_t router_9_15_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_9_15_rsp; - -floo_req_t router_9_15_to_router_9_16_req; -floo_rsp_t router_9_16_to_router_9_15_rsp; - -floo_req_t router_9_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_9_15_rsp; - -floo_req_t router_9_15_to_magia_tile_ni_9_15_req; -floo_rsp_t magia_tile_ni_9_15_to_router_9_15_rsp; - -floo_req_t router_9_16_to_router_8_16_req; -floo_rsp_t router_8_16_to_router_9_16_rsp; - -floo_req_t router_9_16_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_9_16_rsp; - -floo_req_t router_9_16_to_router_9_17_req; -floo_rsp_t router_9_17_to_router_9_16_rsp; - -floo_req_t router_9_16_to_router_10_16_req; -floo_rsp_t router_10_16_to_router_9_16_rsp; - -floo_req_t router_9_16_to_magia_tile_ni_9_16_req; -floo_rsp_t magia_tile_ni_9_16_to_router_9_16_rsp; - -floo_req_t router_9_17_to_router_8_17_req; -floo_rsp_t router_8_17_to_router_9_17_rsp; - -floo_req_t router_9_17_to_router_9_16_req; -floo_rsp_t router_9_16_to_router_9_17_rsp; - -floo_req_t router_9_17_to_router_9_18_req; -floo_rsp_t router_9_18_to_router_9_17_rsp; - -floo_req_t router_9_17_to_router_10_17_req; -floo_rsp_t router_10_17_to_router_9_17_rsp; - -floo_req_t router_9_17_to_magia_tile_ni_9_17_req; -floo_rsp_t magia_tile_ni_9_17_to_router_9_17_rsp; - -floo_req_t router_9_18_to_router_8_18_req; -floo_rsp_t router_8_18_to_router_9_18_rsp; - -floo_req_t router_9_18_to_router_9_17_req; -floo_rsp_t router_9_17_to_router_9_18_rsp; - -floo_req_t router_9_18_to_router_9_19_req; -floo_rsp_t router_9_19_to_router_9_18_rsp; - -floo_req_t router_9_18_to_router_10_18_req; -floo_rsp_t router_10_18_to_router_9_18_rsp; - -floo_req_t router_9_18_to_magia_tile_ni_9_18_req; -floo_rsp_t magia_tile_ni_9_18_to_router_9_18_rsp; - -floo_req_t router_9_19_to_router_8_19_req; -floo_rsp_t router_8_19_to_router_9_19_rsp; - -floo_req_t router_9_19_to_router_9_18_req; -floo_rsp_t router_9_18_to_router_9_19_rsp; - -floo_req_t router_9_19_to_router_9_20_req; -floo_rsp_t router_9_20_to_router_9_19_rsp; - -floo_req_t router_9_19_to_router_10_19_req; -floo_rsp_t router_10_19_to_router_9_19_rsp; - -floo_req_t router_9_19_to_magia_tile_ni_9_19_req; -floo_rsp_t magia_tile_ni_9_19_to_router_9_19_rsp; - -floo_req_t router_9_20_to_router_8_20_req; -floo_rsp_t router_8_20_to_router_9_20_rsp; - -floo_req_t router_9_20_to_router_9_19_req; -floo_rsp_t router_9_19_to_router_9_20_rsp; - -floo_req_t router_9_20_to_router_9_21_req; -floo_rsp_t router_9_21_to_router_9_20_rsp; - -floo_req_t router_9_20_to_router_10_20_req; -floo_rsp_t router_10_20_to_router_9_20_rsp; - -floo_req_t router_9_20_to_magia_tile_ni_9_20_req; -floo_rsp_t magia_tile_ni_9_20_to_router_9_20_rsp; - -floo_req_t router_9_21_to_router_8_21_req; -floo_rsp_t router_8_21_to_router_9_21_rsp; - -floo_req_t router_9_21_to_router_9_20_req; -floo_rsp_t router_9_20_to_router_9_21_rsp; - -floo_req_t router_9_21_to_router_9_22_req; -floo_rsp_t router_9_22_to_router_9_21_rsp; - -floo_req_t router_9_21_to_router_10_21_req; -floo_rsp_t router_10_21_to_router_9_21_rsp; - -floo_req_t router_9_21_to_magia_tile_ni_9_21_req; -floo_rsp_t magia_tile_ni_9_21_to_router_9_21_rsp; - -floo_req_t router_9_22_to_router_8_22_req; -floo_rsp_t router_8_22_to_router_9_22_rsp; - -floo_req_t router_9_22_to_router_9_21_req; -floo_rsp_t router_9_21_to_router_9_22_rsp; - -floo_req_t router_9_22_to_router_9_23_req; -floo_rsp_t router_9_23_to_router_9_22_rsp; - -floo_req_t router_9_22_to_router_10_22_req; -floo_rsp_t router_10_22_to_router_9_22_rsp; - -floo_req_t router_9_22_to_magia_tile_ni_9_22_req; -floo_rsp_t magia_tile_ni_9_22_to_router_9_22_rsp; - -floo_req_t router_9_23_to_router_8_23_req; -floo_rsp_t router_8_23_to_router_9_23_rsp; - -floo_req_t router_9_23_to_router_9_22_req; -floo_rsp_t router_9_22_to_router_9_23_rsp; - -floo_req_t router_9_23_to_router_9_24_req; -floo_rsp_t router_9_24_to_router_9_23_rsp; - -floo_req_t router_9_23_to_router_10_23_req; -floo_rsp_t router_10_23_to_router_9_23_rsp; - -floo_req_t router_9_23_to_magia_tile_ni_9_23_req; -floo_rsp_t magia_tile_ni_9_23_to_router_9_23_rsp; - -floo_req_t router_9_24_to_router_8_24_req; -floo_rsp_t router_8_24_to_router_9_24_rsp; - -floo_req_t router_9_24_to_router_9_23_req; -floo_rsp_t router_9_23_to_router_9_24_rsp; - -floo_req_t router_9_24_to_router_9_25_req; -floo_rsp_t router_9_25_to_router_9_24_rsp; - -floo_req_t router_9_24_to_router_10_24_req; -floo_rsp_t router_10_24_to_router_9_24_rsp; - -floo_req_t router_9_24_to_magia_tile_ni_9_24_req; -floo_rsp_t magia_tile_ni_9_24_to_router_9_24_rsp; - -floo_req_t router_9_25_to_router_8_25_req; -floo_rsp_t router_8_25_to_router_9_25_rsp; - -floo_req_t router_9_25_to_router_9_24_req; -floo_rsp_t router_9_24_to_router_9_25_rsp; - -floo_req_t router_9_25_to_router_9_26_req; -floo_rsp_t router_9_26_to_router_9_25_rsp; - -floo_req_t router_9_25_to_router_10_25_req; -floo_rsp_t router_10_25_to_router_9_25_rsp; - -floo_req_t router_9_25_to_magia_tile_ni_9_25_req; -floo_rsp_t magia_tile_ni_9_25_to_router_9_25_rsp; - -floo_req_t router_9_26_to_router_8_26_req; -floo_rsp_t router_8_26_to_router_9_26_rsp; - -floo_req_t router_9_26_to_router_9_25_req; -floo_rsp_t router_9_25_to_router_9_26_rsp; - -floo_req_t router_9_26_to_router_9_27_req; -floo_rsp_t router_9_27_to_router_9_26_rsp; - -floo_req_t router_9_26_to_router_10_26_req; -floo_rsp_t router_10_26_to_router_9_26_rsp; - -floo_req_t router_9_26_to_magia_tile_ni_9_26_req; -floo_rsp_t magia_tile_ni_9_26_to_router_9_26_rsp; - -floo_req_t router_9_27_to_router_8_27_req; -floo_rsp_t router_8_27_to_router_9_27_rsp; - -floo_req_t router_9_27_to_router_9_26_req; -floo_rsp_t router_9_26_to_router_9_27_rsp; - -floo_req_t router_9_27_to_router_9_28_req; -floo_rsp_t router_9_28_to_router_9_27_rsp; - -floo_req_t router_9_27_to_router_10_27_req; -floo_rsp_t router_10_27_to_router_9_27_rsp; - -floo_req_t router_9_27_to_magia_tile_ni_9_27_req; -floo_rsp_t magia_tile_ni_9_27_to_router_9_27_rsp; - -floo_req_t router_9_28_to_router_8_28_req; -floo_rsp_t router_8_28_to_router_9_28_rsp; - -floo_req_t router_9_28_to_router_9_27_req; -floo_rsp_t router_9_27_to_router_9_28_rsp; - -floo_req_t router_9_28_to_router_9_29_req; -floo_rsp_t router_9_29_to_router_9_28_rsp; - -floo_req_t router_9_28_to_router_10_28_req; -floo_rsp_t router_10_28_to_router_9_28_rsp; - -floo_req_t router_9_28_to_magia_tile_ni_9_28_req; -floo_rsp_t magia_tile_ni_9_28_to_router_9_28_rsp; - -floo_req_t router_9_29_to_router_8_29_req; -floo_rsp_t router_8_29_to_router_9_29_rsp; - -floo_req_t router_9_29_to_router_9_28_req; -floo_rsp_t router_9_28_to_router_9_29_rsp; - -floo_req_t router_9_29_to_router_9_30_req; -floo_rsp_t router_9_30_to_router_9_29_rsp; - -floo_req_t router_9_29_to_router_10_29_req; -floo_rsp_t router_10_29_to_router_9_29_rsp; - -floo_req_t router_9_29_to_magia_tile_ni_9_29_req; -floo_rsp_t magia_tile_ni_9_29_to_router_9_29_rsp; - -floo_req_t router_9_30_to_router_8_30_req; -floo_rsp_t router_8_30_to_router_9_30_rsp; - -floo_req_t router_9_30_to_router_9_29_req; -floo_rsp_t router_9_29_to_router_9_30_rsp; - -floo_req_t router_9_30_to_router_9_31_req; -floo_rsp_t router_9_31_to_router_9_30_rsp; - -floo_req_t router_9_30_to_router_10_30_req; -floo_rsp_t router_10_30_to_router_9_30_rsp; - -floo_req_t router_9_30_to_magia_tile_ni_9_30_req; -floo_rsp_t magia_tile_ni_9_30_to_router_9_30_rsp; - -floo_req_t router_9_31_to_router_8_31_req; -floo_rsp_t router_8_31_to_router_9_31_rsp; - -floo_req_t router_9_31_to_router_9_30_req; -floo_rsp_t router_9_30_to_router_9_31_rsp; - -floo_req_t router_9_31_to_router_10_31_req; -floo_rsp_t router_10_31_to_router_9_31_rsp; - -floo_req_t router_9_31_to_magia_tile_ni_9_31_req; -floo_rsp_t magia_tile_ni_9_31_to_router_9_31_rsp; - -floo_req_t router_10_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_router_10_0_rsp; - -floo_req_t router_10_0_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_10_0_rsp; - -floo_req_t router_10_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_10_0_rsp; - -floo_req_t router_10_0_to_magia_tile_ni_10_0_req; -floo_rsp_t magia_tile_ni_10_0_to_router_10_0_rsp; - -floo_req_t router_10_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_10_1_rsp; - -floo_req_t router_10_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_10_1_rsp; - -floo_req_t router_10_1_to_magia_tile_ni_10_1_req; -floo_rsp_t magia_tile_ni_10_1_to_router_10_1_rsp; - -floo_req_t router_10_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_10_2_rsp; - -floo_req_t router_10_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_10_2_rsp; - -floo_req_t router_10_2_to_magia_tile_ni_10_2_req; -floo_rsp_t magia_tile_ni_10_2_to_router_10_2_rsp; - -floo_req_t router_10_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_10_3_rsp; - -floo_req_t router_10_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_10_3_rsp; - -floo_req_t router_10_3_to_magia_tile_ni_10_3_req; -floo_rsp_t magia_tile_ni_10_3_to_router_10_3_rsp; - -floo_req_t router_10_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_10_4_rsp; - -floo_req_t router_10_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_10_4_rsp; - -floo_req_t router_10_4_to_magia_tile_ni_10_4_req; -floo_rsp_t magia_tile_ni_10_4_to_router_10_4_rsp; - -floo_req_t router_10_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_10_5_rsp; - -floo_req_t router_10_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_10_5_rsp; - -floo_req_t router_10_5_to_magia_tile_ni_10_5_req; -floo_rsp_t magia_tile_ni_10_5_to_router_10_5_rsp; - -floo_req_t router_10_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_10_6_rsp; - -floo_req_t router_10_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_10_6_rsp; - -floo_req_t router_10_6_to_magia_tile_ni_10_6_req; -floo_rsp_t magia_tile_ni_10_6_to_router_10_6_rsp; - -floo_req_t router_10_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_10_7_rsp; - -floo_req_t router_10_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_10_7_rsp; - -floo_req_t router_10_7_to_magia_tile_ni_10_7_req; -floo_rsp_t magia_tile_ni_10_7_to_router_10_7_rsp; - -floo_req_t router_10_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_10_8_rsp; - -floo_req_t router_10_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_10_8_rsp; - -floo_req_t router_10_8_to_magia_tile_ni_10_8_req; -floo_rsp_t magia_tile_ni_10_8_to_router_10_8_rsp; - -floo_req_t router_10_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_10_9_rsp; - -floo_req_t router_10_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_10_9_rsp; - -floo_req_t router_10_9_to_magia_tile_ni_10_9_req; -floo_rsp_t magia_tile_ni_10_9_to_router_10_9_rsp; - -floo_req_t router_10_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_10_10_rsp; - -floo_req_t router_10_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_10_10_rsp; - -floo_req_t router_10_10_to_magia_tile_ni_10_10_req; -floo_rsp_t magia_tile_ni_10_10_to_router_10_10_rsp; - -floo_req_t router_10_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_10_11_rsp; - -floo_req_t router_10_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_10_11_rsp; - -floo_req_t router_10_11_to_magia_tile_ni_10_11_req; -floo_rsp_t magia_tile_ni_10_11_to_router_10_11_rsp; - -floo_req_t router_10_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_10_12_rsp; - -floo_req_t router_10_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_10_12_rsp; - -floo_req_t router_10_12_to_magia_tile_ni_10_12_req; -floo_rsp_t magia_tile_ni_10_12_to_router_10_12_rsp; - -floo_req_t router_10_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_10_13_rsp; - -floo_req_t router_10_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_10_13_rsp; - -floo_req_t router_10_13_to_magia_tile_ni_10_13_req; -floo_rsp_t magia_tile_ni_10_13_to_router_10_13_rsp; - -floo_req_t router_10_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_10_14_rsp; - -floo_req_t router_10_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_10_14_rsp; - -floo_req_t router_10_14_to_magia_tile_ni_10_14_req; -floo_rsp_t magia_tile_ni_10_14_to_router_10_14_rsp; - -floo_req_t router_10_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_router_10_15_rsp; - -floo_req_t router_10_15_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_10_15_rsp; - -floo_req_t router_10_15_to_router_10_16_req; -floo_rsp_t router_10_16_to_router_10_15_rsp; - -floo_req_t router_10_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_10_15_rsp; - -floo_req_t router_10_15_to_magia_tile_ni_10_15_req; -floo_rsp_t magia_tile_ni_10_15_to_router_10_15_rsp; - -floo_req_t router_10_16_to_router_9_16_req; -floo_rsp_t router_9_16_to_router_10_16_rsp; - -floo_req_t router_10_16_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_10_16_rsp; - -floo_req_t router_10_16_to_router_10_17_req; -floo_rsp_t router_10_17_to_router_10_16_rsp; - -floo_req_t router_10_16_to_router_11_16_req; -floo_rsp_t router_11_16_to_router_10_16_rsp; - -floo_req_t router_10_16_to_magia_tile_ni_10_16_req; -floo_rsp_t magia_tile_ni_10_16_to_router_10_16_rsp; - -floo_req_t router_10_17_to_router_9_17_req; -floo_rsp_t router_9_17_to_router_10_17_rsp; - -floo_req_t router_10_17_to_router_10_16_req; -floo_rsp_t router_10_16_to_router_10_17_rsp; - -floo_req_t router_10_17_to_router_10_18_req; -floo_rsp_t router_10_18_to_router_10_17_rsp; - -floo_req_t router_10_17_to_router_11_17_req; -floo_rsp_t router_11_17_to_router_10_17_rsp; - -floo_req_t router_10_17_to_magia_tile_ni_10_17_req; -floo_rsp_t magia_tile_ni_10_17_to_router_10_17_rsp; - -floo_req_t router_10_18_to_router_9_18_req; -floo_rsp_t router_9_18_to_router_10_18_rsp; - -floo_req_t router_10_18_to_router_10_17_req; -floo_rsp_t router_10_17_to_router_10_18_rsp; - -floo_req_t router_10_18_to_router_10_19_req; -floo_rsp_t router_10_19_to_router_10_18_rsp; - -floo_req_t router_10_18_to_router_11_18_req; -floo_rsp_t router_11_18_to_router_10_18_rsp; - -floo_req_t router_10_18_to_magia_tile_ni_10_18_req; -floo_rsp_t magia_tile_ni_10_18_to_router_10_18_rsp; - -floo_req_t router_10_19_to_router_9_19_req; -floo_rsp_t router_9_19_to_router_10_19_rsp; - -floo_req_t router_10_19_to_router_10_18_req; -floo_rsp_t router_10_18_to_router_10_19_rsp; - -floo_req_t router_10_19_to_router_10_20_req; -floo_rsp_t router_10_20_to_router_10_19_rsp; - -floo_req_t router_10_19_to_router_11_19_req; -floo_rsp_t router_11_19_to_router_10_19_rsp; - -floo_req_t router_10_19_to_magia_tile_ni_10_19_req; -floo_rsp_t magia_tile_ni_10_19_to_router_10_19_rsp; - -floo_req_t router_10_20_to_router_9_20_req; -floo_rsp_t router_9_20_to_router_10_20_rsp; - -floo_req_t router_10_20_to_router_10_19_req; -floo_rsp_t router_10_19_to_router_10_20_rsp; - -floo_req_t router_10_20_to_router_10_21_req; -floo_rsp_t router_10_21_to_router_10_20_rsp; - -floo_req_t router_10_20_to_router_11_20_req; -floo_rsp_t router_11_20_to_router_10_20_rsp; - -floo_req_t router_10_20_to_magia_tile_ni_10_20_req; -floo_rsp_t magia_tile_ni_10_20_to_router_10_20_rsp; - -floo_req_t router_10_21_to_router_9_21_req; -floo_rsp_t router_9_21_to_router_10_21_rsp; - -floo_req_t router_10_21_to_router_10_20_req; -floo_rsp_t router_10_20_to_router_10_21_rsp; - -floo_req_t router_10_21_to_router_10_22_req; -floo_rsp_t router_10_22_to_router_10_21_rsp; - -floo_req_t router_10_21_to_router_11_21_req; -floo_rsp_t router_11_21_to_router_10_21_rsp; - -floo_req_t router_10_21_to_magia_tile_ni_10_21_req; -floo_rsp_t magia_tile_ni_10_21_to_router_10_21_rsp; - -floo_req_t router_10_22_to_router_9_22_req; -floo_rsp_t router_9_22_to_router_10_22_rsp; - -floo_req_t router_10_22_to_router_10_21_req; -floo_rsp_t router_10_21_to_router_10_22_rsp; - -floo_req_t router_10_22_to_router_10_23_req; -floo_rsp_t router_10_23_to_router_10_22_rsp; - -floo_req_t router_10_22_to_router_11_22_req; -floo_rsp_t router_11_22_to_router_10_22_rsp; - -floo_req_t router_10_22_to_magia_tile_ni_10_22_req; -floo_rsp_t magia_tile_ni_10_22_to_router_10_22_rsp; - -floo_req_t router_10_23_to_router_9_23_req; -floo_rsp_t router_9_23_to_router_10_23_rsp; - -floo_req_t router_10_23_to_router_10_22_req; -floo_rsp_t router_10_22_to_router_10_23_rsp; - -floo_req_t router_10_23_to_router_10_24_req; -floo_rsp_t router_10_24_to_router_10_23_rsp; - -floo_req_t router_10_23_to_router_11_23_req; -floo_rsp_t router_11_23_to_router_10_23_rsp; - -floo_req_t router_10_23_to_magia_tile_ni_10_23_req; -floo_rsp_t magia_tile_ni_10_23_to_router_10_23_rsp; - -floo_req_t router_10_24_to_router_9_24_req; -floo_rsp_t router_9_24_to_router_10_24_rsp; - -floo_req_t router_10_24_to_router_10_23_req; -floo_rsp_t router_10_23_to_router_10_24_rsp; - -floo_req_t router_10_24_to_router_10_25_req; -floo_rsp_t router_10_25_to_router_10_24_rsp; - -floo_req_t router_10_24_to_router_11_24_req; -floo_rsp_t router_11_24_to_router_10_24_rsp; - -floo_req_t router_10_24_to_magia_tile_ni_10_24_req; -floo_rsp_t magia_tile_ni_10_24_to_router_10_24_rsp; - -floo_req_t router_10_25_to_router_9_25_req; -floo_rsp_t router_9_25_to_router_10_25_rsp; - -floo_req_t router_10_25_to_router_10_24_req; -floo_rsp_t router_10_24_to_router_10_25_rsp; - -floo_req_t router_10_25_to_router_10_26_req; -floo_rsp_t router_10_26_to_router_10_25_rsp; - -floo_req_t router_10_25_to_router_11_25_req; -floo_rsp_t router_11_25_to_router_10_25_rsp; - -floo_req_t router_10_25_to_magia_tile_ni_10_25_req; -floo_rsp_t magia_tile_ni_10_25_to_router_10_25_rsp; - -floo_req_t router_10_26_to_router_9_26_req; -floo_rsp_t router_9_26_to_router_10_26_rsp; - -floo_req_t router_10_26_to_router_10_25_req; -floo_rsp_t router_10_25_to_router_10_26_rsp; - -floo_req_t router_10_26_to_router_10_27_req; -floo_rsp_t router_10_27_to_router_10_26_rsp; - -floo_req_t router_10_26_to_router_11_26_req; -floo_rsp_t router_11_26_to_router_10_26_rsp; - -floo_req_t router_10_26_to_magia_tile_ni_10_26_req; -floo_rsp_t magia_tile_ni_10_26_to_router_10_26_rsp; - -floo_req_t router_10_27_to_router_9_27_req; -floo_rsp_t router_9_27_to_router_10_27_rsp; - -floo_req_t router_10_27_to_router_10_26_req; -floo_rsp_t router_10_26_to_router_10_27_rsp; - -floo_req_t router_10_27_to_router_10_28_req; -floo_rsp_t router_10_28_to_router_10_27_rsp; - -floo_req_t router_10_27_to_router_11_27_req; -floo_rsp_t router_11_27_to_router_10_27_rsp; - -floo_req_t router_10_27_to_magia_tile_ni_10_27_req; -floo_rsp_t magia_tile_ni_10_27_to_router_10_27_rsp; - -floo_req_t router_10_28_to_router_9_28_req; -floo_rsp_t router_9_28_to_router_10_28_rsp; - -floo_req_t router_10_28_to_router_10_27_req; -floo_rsp_t router_10_27_to_router_10_28_rsp; - -floo_req_t router_10_28_to_router_10_29_req; -floo_rsp_t router_10_29_to_router_10_28_rsp; - -floo_req_t router_10_28_to_router_11_28_req; -floo_rsp_t router_11_28_to_router_10_28_rsp; - -floo_req_t router_10_28_to_magia_tile_ni_10_28_req; -floo_rsp_t magia_tile_ni_10_28_to_router_10_28_rsp; - -floo_req_t router_10_29_to_router_9_29_req; -floo_rsp_t router_9_29_to_router_10_29_rsp; - -floo_req_t router_10_29_to_router_10_28_req; -floo_rsp_t router_10_28_to_router_10_29_rsp; - -floo_req_t router_10_29_to_router_10_30_req; -floo_rsp_t router_10_30_to_router_10_29_rsp; - -floo_req_t router_10_29_to_router_11_29_req; -floo_rsp_t router_11_29_to_router_10_29_rsp; - -floo_req_t router_10_29_to_magia_tile_ni_10_29_req; -floo_rsp_t magia_tile_ni_10_29_to_router_10_29_rsp; - -floo_req_t router_10_30_to_router_9_30_req; -floo_rsp_t router_9_30_to_router_10_30_rsp; - -floo_req_t router_10_30_to_router_10_29_req; -floo_rsp_t router_10_29_to_router_10_30_rsp; - -floo_req_t router_10_30_to_router_10_31_req; -floo_rsp_t router_10_31_to_router_10_30_rsp; - -floo_req_t router_10_30_to_router_11_30_req; -floo_rsp_t router_11_30_to_router_10_30_rsp; - -floo_req_t router_10_30_to_magia_tile_ni_10_30_req; -floo_rsp_t magia_tile_ni_10_30_to_router_10_30_rsp; - -floo_req_t router_10_31_to_router_9_31_req; -floo_rsp_t router_9_31_to_router_10_31_rsp; - -floo_req_t router_10_31_to_router_10_30_req; -floo_rsp_t router_10_30_to_router_10_31_rsp; - -floo_req_t router_10_31_to_router_11_31_req; -floo_rsp_t router_11_31_to_router_10_31_rsp; - -floo_req_t router_10_31_to_magia_tile_ni_10_31_req; -floo_rsp_t magia_tile_ni_10_31_to_router_10_31_rsp; - -floo_req_t router_11_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_router_11_0_rsp; - -floo_req_t router_11_0_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_11_0_rsp; - -floo_req_t router_11_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_11_0_rsp; - -floo_req_t router_11_0_to_magia_tile_ni_11_0_req; -floo_rsp_t magia_tile_ni_11_0_to_router_11_0_rsp; - -floo_req_t router_11_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_11_1_rsp; - -floo_req_t router_11_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_11_1_rsp; - -floo_req_t router_11_1_to_magia_tile_ni_11_1_req; -floo_rsp_t magia_tile_ni_11_1_to_router_11_1_rsp; - -floo_req_t router_11_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_11_2_rsp; - -floo_req_t router_11_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_11_2_rsp; - -floo_req_t router_11_2_to_magia_tile_ni_11_2_req; -floo_rsp_t magia_tile_ni_11_2_to_router_11_2_rsp; - -floo_req_t router_11_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_11_3_rsp; - -floo_req_t router_11_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_11_3_rsp; - -floo_req_t router_11_3_to_magia_tile_ni_11_3_req; -floo_rsp_t magia_tile_ni_11_3_to_router_11_3_rsp; - -floo_req_t router_11_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_11_4_rsp; - -floo_req_t router_11_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_11_4_rsp; - -floo_req_t router_11_4_to_magia_tile_ni_11_4_req; -floo_rsp_t magia_tile_ni_11_4_to_router_11_4_rsp; - -floo_req_t router_11_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_11_5_rsp; - -floo_req_t router_11_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_11_5_rsp; - -floo_req_t router_11_5_to_magia_tile_ni_11_5_req; -floo_rsp_t magia_tile_ni_11_5_to_router_11_5_rsp; - -floo_req_t router_11_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_11_6_rsp; - -floo_req_t router_11_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_11_6_rsp; - -floo_req_t router_11_6_to_magia_tile_ni_11_6_req; -floo_rsp_t magia_tile_ni_11_6_to_router_11_6_rsp; - -floo_req_t router_11_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_11_7_rsp; - -floo_req_t router_11_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_11_7_rsp; - -floo_req_t router_11_7_to_magia_tile_ni_11_7_req; -floo_rsp_t magia_tile_ni_11_7_to_router_11_7_rsp; - -floo_req_t router_11_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_11_8_rsp; - -floo_req_t router_11_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_11_8_rsp; - -floo_req_t router_11_8_to_magia_tile_ni_11_8_req; -floo_rsp_t magia_tile_ni_11_8_to_router_11_8_rsp; - -floo_req_t router_11_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_11_9_rsp; - -floo_req_t router_11_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_11_9_rsp; - -floo_req_t router_11_9_to_magia_tile_ni_11_9_req; -floo_rsp_t magia_tile_ni_11_9_to_router_11_9_rsp; - -floo_req_t router_11_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_11_10_rsp; - -floo_req_t router_11_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_11_10_rsp; - -floo_req_t router_11_10_to_magia_tile_ni_11_10_req; -floo_rsp_t magia_tile_ni_11_10_to_router_11_10_rsp; - -floo_req_t router_11_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_11_11_rsp; - -floo_req_t router_11_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_11_11_rsp; - -floo_req_t router_11_11_to_magia_tile_ni_11_11_req; -floo_rsp_t magia_tile_ni_11_11_to_router_11_11_rsp; - -floo_req_t router_11_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_11_12_rsp; - -floo_req_t router_11_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_11_12_rsp; - -floo_req_t router_11_12_to_magia_tile_ni_11_12_req; -floo_rsp_t magia_tile_ni_11_12_to_router_11_12_rsp; - -floo_req_t router_11_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_11_13_rsp; - -floo_req_t router_11_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_11_13_rsp; - -floo_req_t router_11_13_to_magia_tile_ni_11_13_req; -floo_rsp_t magia_tile_ni_11_13_to_router_11_13_rsp; - -floo_req_t router_11_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_11_14_rsp; - -floo_req_t router_11_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_11_14_rsp; - -floo_req_t router_11_14_to_magia_tile_ni_11_14_req; -floo_rsp_t magia_tile_ni_11_14_to_router_11_14_rsp; - -floo_req_t router_11_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_router_11_15_rsp; - -floo_req_t router_11_15_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_11_15_rsp; - -floo_req_t router_11_15_to_router_11_16_req; -floo_rsp_t router_11_16_to_router_11_15_rsp; - -floo_req_t router_11_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_11_15_rsp; - -floo_req_t router_11_15_to_magia_tile_ni_11_15_req; -floo_rsp_t magia_tile_ni_11_15_to_router_11_15_rsp; - -floo_req_t router_11_16_to_router_10_16_req; -floo_rsp_t router_10_16_to_router_11_16_rsp; - -floo_req_t router_11_16_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_11_16_rsp; - -floo_req_t router_11_16_to_router_11_17_req; -floo_rsp_t router_11_17_to_router_11_16_rsp; - -floo_req_t router_11_16_to_router_12_16_req; -floo_rsp_t router_12_16_to_router_11_16_rsp; - -floo_req_t router_11_16_to_magia_tile_ni_11_16_req; -floo_rsp_t magia_tile_ni_11_16_to_router_11_16_rsp; - -floo_req_t router_11_17_to_router_10_17_req; -floo_rsp_t router_10_17_to_router_11_17_rsp; - -floo_req_t router_11_17_to_router_11_16_req; -floo_rsp_t router_11_16_to_router_11_17_rsp; - -floo_req_t router_11_17_to_router_11_18_req; -floo_rsp_t router_11_18_to_router_11_17_rsp; - -floo_req_t router_11_17_to_router_12_17_req; -floo_rsp_t router_12_17_to_router_11_17_rsp; - -floo_req_t router_11_17_to_magia_tile_ni_11_17_req; -floo_rsp_t magia_tile_ni_11_17_to_router_11_17_rsp; - -floo_req_t router_11_18_to_router_10_18_req; -floo_rsp_t router_10_18_to_router_11_18_rsp; - -floo_req_t router_11_18_to_router_11_17_req; -floo_rsp_t router_11_17_to_router_11_18_rsp; - -floo_req_t router_11_18_to_router_11_19_req; -floo_rsp_t router_11_19_to_router_11_18_rsp; - -floo_req_t router_11_18_to_router_12_18_req; -floo_rsp_t router_12_18_to_router_11_18_rsp; - -floo_req_t router_11_18_to_magia_tile_ni_11_18_req; -floo_rsp_t magia_tile_ni_11_18_to_router_11_18_rsp; - -floo_req_t router_11_19_to_router_10_19_req; -floo_rsp_t router_10_19_to_router_11_19_rsp; - -floo_req_t router_11_19_to_router_11_18_req; -floo_rsp_t router_11_18_to_router_11_19_rsp; - -floo_req_t router_11_19_to_router_11_20_req; -floo_rsp_t router_11_20_to_router_11_19_rsp; - -floo_req_t router_11_19_to_router_12_19_req; -floo_rsp_t router_12_19_to_router_11_19_rsp; - -floo_req_t router_11_19_to_magia_tile_ni_11_19_req; -floo_rsp_t magia_tile_ni_11_19_to_router_11_19_rsp; - -floo_req_t router_11_20_to_router_10_20_req; -floo_rsp_t router_10_20_to_router_11_20_rsp; - -floo_req_t router_11_20_to_router_11_19_req; -floo_rsp_t router_11_19_to_router_11_20_rsp; - -floo_req_t router_11_20_to_router_11_21_req; -floo_rsp_t router_11_21_to_router_11_20_rsp; - -floo_req_t router_11_20_to_router_12_20_req; -floo_rsp_t router_12_20_to_router_11_20_rsp; - -floo_req_t router_11_20_to_magia_tile_ni_11_20_req; -floo_rsp_t magia_tile_ni_11_20_to_router_11_20_rsp; - -floo_req_t router_11_21_to_router_10_21_req; -floo_rsp_t router_10_21_to_router_11_21_rsp; - -floo_req_t router_11_21_to_router_11_20_req; -floo_rsp_t router_11_20_to_router_11_21_rsp; - -floo_req_t router_11_21_to_router_11_22_req; -floo_rsp_t router_11_22_to_router_11_21_rsp; - -floo_req_t router_11_21_to_router_12_21_req; -floo_rsp_t router_12_21_to_router_11_21_rsp; - -floo_req_t router_11_21_to_magia_tile_ni_11_21_req; -floo_rsp_t magia_tile_ni_11_21_to_router_11_21_rsp; - -floo_req_t router_11_22_to_router_10_22_req; -floo_rsp_t router_10_22_to_router_11_22_rsp; - -floo_req_t router_11_22_to_router_11_21_req; -floo_rsp_t router_11_21_to_router_11_22_rsp; - -floo_req_t router_11_22_to_router_11_23_req; -floo_rsp_t router_11_23_to_router_11_22_rsp; - -floo_req_t router_11_22_to_router_12_22_req; -floo_rsp_t router_12_22_to_router_11_22_rsp; - -floo_req_t router_11_22_to_magia_tile_ni_11_22_req; -floo_rsp_t magia_tile_ni_11_22_to_router_11_22_rsp; - -floo_req_t router_11_23_to_router_10_23_req; -floo_rsp_t router_10_23_to_router_11_23_rsp; - -floo_req_t router_11_23_to_router_11_22_req; -floo_rsp_t router_11_22_to_router_11_23_rsp; - -floo_req_t router_11_23_to_router_11_24_req; -floo_rsp_t router_11_24_to_router_11_23_rsp; - -floo_req_t router_11_23_to_router_12_23_req; -floo_rsp_t router_12_23_to_router_11_23_rsp; - -floo_req_t router_11_23_to_magia_tile_ni_11_23_req; -floo_rsp_t magia_tile_ni_11_23_to_router_11_23_rsp; - -floo_req_t router_11_24_to_router_10_24_req; -floo_rsp_t router_10_24_to_router_11_24_rsp; - -floo_req_t router_11_24_to_router_11_23_req; -floo_rsp_t router_11_23_to_router_11_24_rsp; - -floo_req_t router_11_24_to_router_11_25_req; -floo_rsp_t router_11_25_to_router_11_24_rsp; - -floo_req_t router_11_24_to_router_12_24_req; -floo_rsp_t router_12_24_to_router_11_24_rsp; - -floo_req_t router_11_24_to_magia_tile_ni_11_24_req; -floo_rsp_t magia_tile_ni_11_24_to_router_11_24_rsp; - -floo_req_t router_11_25_to_router_10_25_req; -floo_rsp_t router_10_25_to_router_11_25_rsp; - -floo_req_t router_11_25_to_router_11_24_req; -floo_rsp_t router_11_24_to_router_11_25_rsp; - -floo_req_t router_11_25_to_router_11_26_req; -floo_rsp_t router_11_26_to_router_11_25_rsp; - -floo_req_t router_11_25_to_router_12_25_req; -floo_rsp_t router_12_25_to_router_11_25_rsp; - -floo_req_t router_11_25_to_magia_tile_ni_11_25_req; -floo_rsp_t magia_tile_ni_11_25_to_router_11_25_rsp; - -floo_req_t router_11_26_to_router_10_26_req; -floo_rsp_t router_10_26_to_router_11_26_rsp; - -floo_req_t router_11_26_to_router_11_25_req; -floo_rsp_t router_11_25_to_router_11_26_rsp; - -floo_req_t router_11_26_to_router_11_27_req; -floo_rsp_t router_11_27_to_router_11_26_rsp; - -floo_req_t router_11_26_to_router_12_26_req; -floo_rsp_t router_12_26_to_router_11_26_rsp; - -floo_req_t router_11_26_to_magia_tile_ni_11_26_req; -floo_rsp_t magia_tile_ni_11_26_to_router_11_26_rsp; - -floo_req_t router_11_27_to_router_10_27_req; -floo_rsp_t router_10_27_to_router_11_27_rsp; - -floo_req_t router_11_27_to_router_11_26_req; -floo_rsp_t router_11_26_to_router_11_27_rsp; - -floo_req_t router_11_27_to_router_11_28_req; -floo_rsp_t router_11_28_to_router_11_27_rsp; - -floo_req_t router_11_27_to_router_12_27_req; -floo_rsp_t router_12_27_to_router_11_27_rsp; - -floo_req_t router_11_27_to_magia_tile_ni_11_27_req; -floo_rsp_t magia_tile_ni_11_27_to_router_11_27_rsp; - -floo_req_t router_11_28_to_router_10_28_req; -floo_rsp_t router_10_28_to_router_11_28_rsp; - -floo_req_t router_11_28_to_router_11_27_req; -floo_rsp_t router_11_27_to_router_11_28_rsp; - -floo_req_t router_11_28_to_router_11_29_req; -floo_rsp_t router_11_29_to_router_11_28_rsp; - -floo_req_t router_11_28_to_router_12_28_req; -floo_rsp_t router_12_28_to_router_11_28_rsp; - -floo_req_t router_11_28_to_magia_tile_ni_11_28_req; -floo_rsp_t magia_tile_ni_11_28_to_router_11_28_rsp; - -floo_req_t router_11_29_to_router_10_29_req; -floo_rsp_t router_10_29_to_router_11_29_rsp; - -floo_req_t router_11_29_to_router_11_28_req; -floo_rsp_t router_11_28_to_router_11_29_rsp; - -floo_req_t router_11_29_to_router_11_30_req; -floo_rsp_t router_11_30_to_router_11_29_rsp; - -floo_req_t router_11_29_to_router_12_29_req; -floo_rsp_t router_12_29_to_router_11_29_rsp; - -floo_req_t router_11_29_to_magia_tile_ni_11_29_req; -floo_rsp_t magia_tile_ni_11_29_to_router_11_29_rsp; - -floo_req_t router_11_30_to_router_10_30_req; -floo_rsp_t router_10_30_to_router_11_30_rsp; - -floo_req_t router_11_30_to_router_11_29_req; -floo_rsp_t router_11_29_to_router_11_30_rsp; - -floo_req_t router_11_30_to_router_11_31_req; -floo_rsp_t router_11_31_to_router_11_30_rsp; - -floo_req_t router_11_30_to_router_12_30_req; -floo_rsp_t router_12_30_to_router_11_30_rsp; - -floo_req_t router_11_30_to_magia_tile_ni_11_30_req; -floo_rsp_t magia_tile_ni_11_30_to_router_11_30_rsp; - -floo_req_t router_11_31_to_router_10_31_req; -floo_rsp_t router_10_31_to_router_11_31_rsp; - -floo_req_t router_11_31_to_router_11_30_req; -floo_rsp_t router_11_30_to_router_11_31_rsp; - -floo_req_t router_11_31_to_router_12_31_req; -floo_rsp_t router_12_31_to_router_11_31_rsp; - -floo_req_t router_11_31_to_magia_tile_ni_11_31_req; -floo_rsp_t magia_tile_ni_11_31_to_router_11_31_rsp; - -floo_req_t router_12_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_router_12_0_rsp; - -floo_req_t router_12_0_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_12_0_rsp; - -floo_req_t router_12_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_12_0_rsp; - -floo_req_t router_12_0_to_magia_tile_ni_12_0_req; -floo_rsp_t magia_tile_ni_12_0_to_router_12_0_rsp; - -floo_req_t router_12_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_12_1_rsp; - -floo_req_t router_12_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_12_1_rsp; - -floo_req_t router_12_1_to_magia_tile_ni_12_1_req; -floo_rsp_t magia_tile_ni_12_1_to_router_12_1_rsp; - -floo_req_t router_12_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_12_2_rsp; - -floo_req_t router_12_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_12_2_rsp; - -floo_req_t router_12_2_to_magia_tile_ni_12_2_req; -floo_rsp_t magia_tile_ni_12_2_to_router_12_2_rsp; - -floo_req_t router_12_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_12_3_rsp; - -floo_req_t router_12_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_12_3_rsp; - -floo_req_t router_12_3_to_magia_tile_ni_12_3_req; -floo_rsp_t magia_tile_ni_12_3_to_router_12_3_rsp; - -floo_req_t router_12_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_12_4_rsp; - -floo_req_t router_12_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_12_4_rsp; - -floo_req_t router_12_4_to_magia_tile_ni_12_4_req; -floo_rsp_t magia_tile_ni_12_4_to_router_12_4_rsp; - -floo_req_t router_12_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_12_5_rsp; - -floo_req_t router_12_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_12_5_rsp; - -floo_req_t router_12_5_to_magia_tile_ni_12_5_req; -floo_rsp_t magia_tile_ni_12_5_to_router_12_5_rsp; - -floo_req_t router_12_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_12_6_rsp; - -floo_req_t router_12_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_12_6_rsp; - -floo_req_t router_12_6_to_magia_tile_ni_12_6_req; -floo_rsp_t magia_tile_ni_12_6_to_router_12_6_rsp; - -floo_req_t router_12_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_12_7_rsp; - -floo_req_t router_12_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_12_7_rsp; - -floo_req_t router_12_7_to_magia_tile_ni_12_7_req; -floo_rsp_t magia_tile_ni_12_7_to_router_12_7_rsp; - -floo_req_t router_12_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_12_8_rsp; - -floo_req_t router_12_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_12_8_rsp; - -floo_req_t router_12_8_to_magia_tile_ni_12_8_req; -floo_rsp_t magia_tile_ni_12_8_to_router_12_8_rsp; - -floo_req_t router_12_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_12_9_rsp; - -floo_req_t router_12_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_12_9_rsp; - -floo_req_t router_12_9_to_magia_tile_ni_12_9_req; -floo_rsp_t magia_tile_ni_12_9_to_router_12_9_rsp; - -floo_req_t router_12_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_12_10_rsp; - -floo_req_t router_12_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_12_10_rsp; - -floo_req_t router_12_10_to_magia_tile_ni_12_10_req; -floo_rsp_t magia_tile_ni_12_10_to_router_12_10_rsp; - -floo_req_t router_12_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_12_11_rsp; - -floo_req_t router_12_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_12_11_rsp; - -floo_req_t router_12_11_to_magia_tile_ni_12_11_req; -floo_rsp_t magia_tile_ni_12_11_to_router_12_11_rsp; - -floo_req_t router_12_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_12_12_rsp; - -floo_req_t router_12_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_12_12_rsp; - -floo_req_t router_12_12_to_magia_tile_ni_12_12_req; -floo_rsp_t magia_tile_ni_12_12_to_router_12_12_rsp; - -floo_req_t router_12_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_12_13_rsp; - -floo_req_t router_12_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_12_13_rsp; - -floo_req_t router_12_13_to_magia_tile_ni_12_13_req; -floo_rsp_t magia_tile_ni_12_13_to_router_12_13_rsp; - -floo_req_t router_12_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_12_14_rsp; - -floo_req_t router_12_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_12_14_rsp; - -floo_req_t router_12_14_to_magia_tile_ni_12_14_req; -floo_rsp_t magia_tile_ni_12_14_to_router_12_14_rsp; - -floo_req_t router_12_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_router_12_15_rsp; - -floo_req_t router_12_15_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_12_15_rsp; - -floo_req_t router_12_15_to_router_12_16_req; -floo_rsp_t router_12_16_to_router_12_15_rsp; - -floo_req_t router_12_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_12_15_rsp; - -floo_req_t router_12_15_to_magia_tile_ni_12_15_req; -floo_rsp_t magia_tile_ni_12_15_to_router_12_15_rsp; - -floo_req_t router_12_16_to_router_11_16_req; -floo_rsp_t router_11_16_to_router_12_16_rsp; - -floo_req_t router_12_16_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_12_16_rsp; - -floo_req_t router_12_16_to_router_12_17_req; -floo_rsp_t router_12_17_to_router_12_16_rsp; - -floo_req_t router_12_16_to_router_13_16_req; -floo_rsp_t router_13_16_to_router_12_16_rsp; - -floo_req_t router_12_16_to_magia_tile_ni_12_16_req; -floo_rsp_t magia_tile_ni_12_16_to_router_12_16_rsp; - -floo_req_t router_12_17_to_router_11_17_req; -floo_rsp_t router_11_17_to_router_12_17_rsp; - -floo_req_t router_12_17_to_router_12_16_req; -floo_rsp_t router_12_16_to_router_12_17_rsp; - -floo_req_t router_12_17_to_router_12_18_req; -floo_rsp_t router_12_18_to_router_12_17_rsp; - -floo_req_t router_12_17_to_router_13_17_req; -floo_rsp_t router_13_17_to_router_12_17_rsp; - -floo_req_t router_12_17_to_magia_tile_ni_12_17_req; -floo_rsp_t magia_tile_ni_12_17_to_router_12_17_rsp; - -floo_req_t router_12_18_to_router_11_18_req; -floo_rsp_t router_11_18_to_router_12_18_rsp; - -floo_req_t router_12_18_to_router_12_17_req; -floo_rsp_t router_12_17_to_router_12_18_rsp; - -floo_req_t router_12_18_to_router_12_19_req; -floo_rsp_t router_12_19_to_router_12_18_rsp; - -floo_req_t router_12_18_to_router_13_18_req; -floo_rsp_t router_13_18_to_router_12_18_rsp; - -floo_req_t router_12_18_to_magia_tile_ni_12_18_req; -floo_rsp_t magia_tile_ni_12_18_to_router_12_18_rsp; - -floo_req_t router_12_19_to_router_11_19_req; -floo_rsp_t router_11_19_to_router_12_19_rsp; - -floo_req_t router_12_19_to_router_12_18_req; -floo_rsp_t router_12_18_to_router_12_19_rsp; - -floo_req_t router_12_19_to_router_12_20_req; -floo_rsp_t router_12_20_to_router_12_19_rsp; - -floo_req_t router_12_19_to_router_13_19_req; -floo_rsp_t router_13_19_to_router_12_19_rsp; - -floo_req_t router_12_19_to_magia_tile_ni_12_19_req; -floo_rsp_t magia_tile_ni_12_19_to_router_12_19_rsp; - -floo_req_t router_12_20_to_router_11_20_req; -floo_rsp_t router_11_20_to_router_12_20_rsp; - -floo_req_t router_12_20_to_router_12_19_req; -floo_rsp_t router_12_19_to_router_12_20_rsp; - -floo_req_t router_12_20_to_router_12_21_req; -floo_rsp_t router_12_21_to_router_12_20_rsp; - -floo_req_t router_12_20_to_router_13_20_req; -floo_rsp_t router_13_20_to_router_12_20_rsp; - -floo_req_t router_12_20_to_magia_tile_ni_12_20_req; -floo_rsp_t magia_tile_ni_12_20_to_router_12_20_rsp; - -floo_req_t router_12_21_to_router_11_21_req; -floo_rsp_t router_11_21_to_router_12_21_rsp; - -floo_req_t router_12_21_to_router_12_20_req; -floo_rsp_t router_12_20_to_router_12_21_rsp; - -floo_req_t router_12_21_to_router_12_22_req; -floo_rsp_t router_12_22_to_router_12_21_rsp; - -floo_req_t router_12_21_to_router_13_21_req; -floo_rsp_t router_13_21_to_router_12_21_rsp; - -floo_req_t router_12_21_to_magia_tile_ni_12_21_req; -floo_rsp_t magia_tile_ni_12_21_to_router_12_21_rsp; - -floo_req_t router_12_22_to_router_11_22_req; -floo_rsp_t router_11_22_to_router_12_22_rsp; - -floo_req_t router_12_22_to_router_12_21_req; -floo_rsp_t router_12_21_to_router_12_22_rsp; - -floo_req_t router_12_22_to_router_12_23_req; -floo_rsp_t router_12_23_to_router_12_22_rsp; - -floo_req_t router_12_22_to_router_13_22_req; -floo_rsp_t router_13_22_to_router_12_22_rsp; - -floo_req_t router_12_22_to_magia_tile_ni_12_22_req; -floo_rsp_t magia_tile_ni_12_22_to_router_12_22_rsp; - -floo_req_t router_12_23_to_router_11_23_req; -floo_rsp_t router_11_23_to_router_12_23_rsp; - -floo_req_t router_12_23_to_router_12_22_req; -floo_rsp_t router_12_22_to_router_12_23_rsp; - -floo_req_t router_12_23_to_router_12_24_req; -floo_rsp_t router_12_24_to_router_12_23_rsp; - -floo_req_t router_12_23_to_router_13_23_req; -floo_rsp_t router_13_23_to_router_12_23_rsp; - -floo_req_t router_12_23_to_magia_tile_ni_12_23_req; -floo_rsp_t magia_tile_ni_12_23_to_router_12_23_rsp; - -floo_req_t router_12_24_to_router_11_24_req; -floo_rsp_t router_11_24_to_router_12_24_rsp; - -floo_req_t router_12_24_to_router_12_23_req; -floo_rsp_t router_12_23_to_router_12_24_rsp; - -floo_req_t router_12_24_to_router_12_25_req; -floo_rsp_t router_12_25_to_router_12_24_rsp; - -floo_req_t router_12_24_to_router_13_24_req; -floo_rsp_t router_13_24_to_router_12_24_rsp; - -floo_req_t router_12_24_to_magia_tile_ni_12_24_req; -floo_rsp_t magia_tile_ni_12_24_to_router_12_24_rsp; - -floo_req_t router_12_25_to_router_11_25_req; -floo_rsp_t router_11_25_to_router_12_25_rsp; - -floo_req_t router_12_25_to_router_12_24_req; -floo_rsp_t router_12_24_to_router_12_25_rsp; - -floo_req_t router_12_25_to_router_12_26_req; -floo_rsp_t router_12_26_to_router_12_25_rsp; - -floo_req_t router_12_25_to_router_13_25_req; -floo_rsp_t router_13_25_to_router_12_25_rsp; - -floo_req_t router_12_25_to_magia_tile_ni_12_25_req; -floo_rsp_t magia_tile_ni_12_25_to_router_12_25_rsp; - -floo_req_t router_12_26_to_router_11_26_req; -floo_rsp_t router_11_26_to_router_12_26_rsp; - -floo_req_t router_12_26_to_router_12_25_req; -floo_rsp_t router_12_25_to_router_12_26_rsp; - -floo_req_t router_12_26_to_router_12_27_req; -floo_rsp_t router_12_27_to_router_12_26_rsp; - -floo_req_t router_12_26_to_router_13_26_req; -floo_rsp_t router_13_26_to_router_12_26_rsp; - -floo_req_t router_12_26_to_magia_tile_ni_12_26_req; -floo_rsp_t magia_tile_ni_12_26_to_router_12_26_rsp; - -floo_req_t router_12_27_to_router_11_27_req; -floo_rsp_t router_11_27_to_router_12_27_rsp; - -floo_req_t router_12_27_to_router_12_26_req; -floo_rsp_t router_12_26_to_router_12_27_rsp; - -floo_req_t router_12_27_to_router_12_28_req; -floo_rsp_t router_12_28_to_router_12_27_rsp; - -floo_req_t router_12_27_to_router_13_27_req; -floo_rsp_t router_13_27_to_router_12_27_rsp; - -floo_req_t router_12_27_to_magia_tile_ni_12_27_req; -floo_rsp_t magia_tile_ni_12_27_to_router_12_27_rsp; - -floo_req_t router_12_28_to_router_11_28_req; -floo_rsp_t router_11_28_to_router_12_28_rsp; - -floo_req_t router_12_28_to_router_12_27_req; -floo_rsp_t router_12_27_to_router_12_28_rsp; - -floo_req_t router_12_28_to_router_12_29_req; -floo_rsp_t router_12_29_to_router_12_28_rsp; - -floo_req_t router_12_28_to_router_13_28_req; -floo_rsp_t router_13_28_to_router_12_28_rsp; - -floo_req_t router_12_28_to_magia_tile_ni_12_28_req; -floo_rsp_t magia_tile_ni_12_28_to_router_12_28_rsp; - -floo_req_t router_12_29_to_router_11_29_req; -floo_rsp_t router_11_29_to_router_12_29_rsp; - -floo_req_t router_12_29_to_router_12_28_req; -floo_rsp_t router_12_28_to_router_12_29_rsp; - -floo_req_t router_12_29_to_router_12_30_req; -floo_rsp_t router_12_30_to_router_12_29_rsp; - -floo_req_t router_12_29_to_router_13_29_req; -floo_rsp_t router_13_29_to_router_12_29_rsp; - -floo_req_t router_12_29_to_magia_tile_ni_12_29_req; -floo_rsp_t magia_tile_ni_12_29_to_router_12_29_rsp; - -floo_req_t router_12_30_to_router_11_30_req; -floo_rsp_t router_11_30_to_router_12_30_rsp; - -floo_req_t router_12_30_to_router_12_29_req; -floo_rsp_t router_12_29_to_router_12_30_rsp; - -floo_req_t router_12_30_to_router_12_31_req; -floo_rsp_t router_12_31_to_router_12_30_rsp; - -floo_req_t router_12_30_to_router_13_30_req; -floo_rsp_t router_13_30_to_router_12_30_rsp; - -floo_req_t router_12_30_to_magia_tile_ni_12_30_req; -floo_rsp_t magia_tile_ni_12_30_to_router_12_30_rsp; - -floo_req_t router_12_31_to_router_11_31_req; -floo_rsp_t router_11_31_to_router_12_31_rsp; - -floo_req_t router_12_31_to_router_12_30_req; -floo_rsp_t router_12_30_to_router_12_31_rsp; - -floo_req_t router_12_31_to_router_13_31_req; -floo_rsp_t router_13_31_to_router_12_31_rsp; - -floo_req_t router_12_31_to_magia_tile_ni_12_31_req; -floo_rsp_t magia_tile_ni_12_31_to_router_12_31_rsp; - -floo_req_t router_13_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_router_13_0_rsp; - -floo_req_t router_13_0_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_13_0_rsp; - -floo_req_t router_13_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_13_0_rsp; - -floo_req_t router_13_0_to_magia_tile_ni_13_0_req; -floo_rsp_t magia_tile_ni_13_0_to_router_13_0_rsp; - -floo_req_t router_13_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_13_1_rsp; - -floo_req_t router_13_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_13_1_rsp; - -floo_req_t router_13_1_to_magia_tile_ni_13_1_req; -floo_rsp_t magia_tile_ni_13_1_to_router_13_1_rsp; - -floo_req_t router_13_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_13_2_rsp; - -floo_req_t router_13_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_13_2_rsp; - -floo_req_t router_13_2_to_magia_tile_ni_13_2_req; -floo_rsp_t magia_tile_ni_13_2_to_router_13_2_rsp; - -floo_req_t router_13_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_13_3_rsp; - -floo_req_t router_13_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_13_3_rsp; - -floo_req_t router_13_3_to_magia_tile_ni_13_3_req; -floo_rsp_t magia_tile_ni_13_3_to_router_13_3_rsp; - -floo_req_t router_13_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_13_4_rsp; - -floo_req_t router_13_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_13_4_rsp; - -floo_req_t router_13_4_to_magia_tile_ni_13_4_req; -floo_rsp_t magia_tile_ni_13_4_to_router_13_4_rsp; - -floo_req_t router_13_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_13_5_rsp; - -floo_req_t router_13_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_13_5_rsp; - -floo_req_t router_13_5_to_magia_tile_ni_13_5_req; -floo_rsp_t magia_tile_ni_13_5_to_router_13_5_rsp; - -floo_req_t router_13_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_13_6_rsp; - -floo_req_t router_13_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_13_6_rsp; - -floo_req_t router_13_6_to_magia_tile_ni_13_6_req; -floo_rsp_t magia_tile_ni_13_6_to_router_13_6_rsp; - -floo_req_t router_13_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_13_7_rsp; - -floo_req_t router_13_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_13_7_rsp; - -floo_req_t router_13_7_to_magia_tile_ni_13_7_req; -floo_rsp_t magia_tile_ni_13_7_to_router_13_7_rsp; - -floo_req_t router_13_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_13_8_rsp; - -floo_req_t router_13_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_13_8_rsp; - -floo_req_t router_13_8_to_magia_tile_ni_13_8_req; -floo_rsp_t magia_tile_ni_13_8_to_router_13_8_rsp; - -floo_req_t router_13_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_13_9_rsp; - -floo_req_t router_13_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_13_9_rsp; - -floo_req_t router_13_9_to_magia_tile_ni_13_9_req; -floo_rsp_t magia_tile_ni_13_9_to_router_13_9_rsp; - -floo_req_t router_13_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_13_10_rsp; - -floo_req_t router_13_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_13_10_rsp; - -floo_req_t router_13_10_to_magia_tile_ni_13_10_req; -floo_rsp_t magia_tile_ni_13_10_to_router_13_10_rsp; - -floo_req_t router_13_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_13_11_rsp; - -floo_req_t router_13_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_13_11_rsp; - -floo_req_t router_13_11_to_magia_tile_ni_13_11_req; -floo_rsp_t magia_tile_ni_13_11_to_router_13_11_rsp; - -floo_req_t router_13_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_13_12_rsp; - -floo_req_t router_13_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_13_12_rsp; - -floo_req_t router_13_12_to_magia_tile_ni_13_12_req; -floo_rsp_t magia_tile_ni_13_12_to_router_13_12_rsp; - -floo_req_t router_13_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_13_13_rsp; - -floo_req_t router_13_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_13_13_rsp; - -floo_req_t router_13_13_to_magia_tile_ni_13_13_req; -floo_rsp_t magia_tile_ni_13_13_to_router_13_13_rsp; - -floo_req_t router_13_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_13_14_rsp; - -floo_req_t router_13_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_13_14_rsp; - -floo_req_t router_13_14_to_magia_tile_ni_13_14_req; -floo_rsp_t magia_tile_ni_13_14_to_router_13_14_rsp; - -floo_req_t router_13_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_router_13_15_rsp; - -floo_req_t router_13_15_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_13_15_rsp; - -floo_req_t router_13_15_to_router_13_16_req; -floo_rsp_t router_13_16_to_router_13_15_rsp; - -floo_req_t router_13_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_13_15_rsp; - -floo_req_t router_13_15_to_magia_tile_ni_13_15_req; -floo_rsp_t magia_tile_ni_13_15_to_router_13_15_rsp; - -floo_req_t router_13_16_to_router_12_16_req; -floo_rsp_t router_12_16_to_router_13_16_rsp; - -floo_req_t router_13_16_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_13_16_rsp; - -floo_req_t router_13_16_to_router_13_17_req; -floo_rsp_t router_13_17_to_router_13_16_rsp; - -floo_req_t router_13_16_to_router_14_16_req; -floo_rsp_t router_14_16_to_router_13_16_rsp; - -floo_req_t router_13_16_to_magia_tile_ni_13_16_req; -floo_rsp_t magia_tile_ni_13_16_to_router_13_16_rsp; - -floo_req_t router_13_17_to_router_12_17_req; -floo_rsp_t router_12_17_to_router_13_17_rsp; - -floo_req_t router_13_17_to_router_13_16_req; -floo_rsp_t router_13_16_to_router_13_17_rsp; - -floo_req_t router_13_17_to_router_13_18_req; -floo_rsp_t router_13_18_to_router_13_17_rsp; - -floo_req_t router_13_17_to_router_14_17_req; -floo_rsp_t router_14_17_to_router_13_17_rsp; - -floo_req_t router_13_17_to_magia_tile_ni_13_17_req; -floo_rsp_t magia_tile_ni_13_17_to_router_13_17_rsp; - -floo_req_t router_13_18_to_router_12_18_req; -floo_rsp_t router_12_18_to_router_13_18_rsp; - -floo_req_t router_13_18_to_router_13_17_req; -floo_rsp_t router_13_17_to_router_13_18_rsp; - -floo_req_t router_13_18_to_router_13_19_req; -floo_rsp_t router_13_19_to_router_13_18_rsp; - -floo_req_t router_13_18_to_router_14_18_req; -floo_rsp_t router_14_18_to_router_13_18_rsp; - -floo_req_t router_13_18_to_magia_tile_ni_13_18_req; -floo_rsp_t magia_tile_ni_13_18_to_router_13_18_rsp; - -floo_req_t router_13_19_to_router_12_19_req; -floo_rsp_t router_12_19_to_router_13_19_rsp; - -floo_req_t router_13_19_to_router_13_18_req; -floo_rsp_t router_13_18_to_router_13_19_rsp; - -floo_req_t router_13_19_to_router_13_20_req; -floo_rsp_t router_13_20_to_router_13_19_rsp; - -floo_req_t router_13_19_to_router_14_19_req; -floo_rsp_t router_14_19_to_router_13_19_rsp; - -floo_req_t router_13_19_to_magia_tile_ni_13_19_req; -floo_rsp_t magia_tile_ni_13_19_to_router_13_19_rsp; - -floo_req_t router_13_20_to_router_12_20_req; -floo_rsp_t router_12_20_to_router_13_20_rsp; - -floo_req_t router_13_20_to_router_13_19_req; -floo_rsp_t router_13_19_to_router_13_20_rsp; - -floo_req_t router_13_20_to_router_13_21_req; -floo_rsp_t router_13_21_to_router_13_20_rsp; - -floo_req_t router_13_20_to_router_14_20_req; -floo_rsp_t router_14_20_to_router_13_20_rsp; - -floo_req_t router_13_20_to_magia_tile_ni_13_20_req; -floo_rsp_t magia_tile_ni_13_20_to_router_13_20_rsp; - -floo_req_t router_13_21_to_router_12_21_req; -floo_rsp_t router_12_21_to_router_13_21_rsp; - -floo_req_t router_13_21_to_router_13_20_req; -floo_rsp_t router_13_20_to_router_13_21_rsp; - -floo_req_t router_13_21_to_router_13_22_req; -floo_rsp_t router_13_22_to_router_13_21_rsp; - -floo_req_t router_13_21_to_router_14_21_req; -floo_rsp_t router_14_21_to_router_13_21_rsp; - -floo_req_t router_13_21_to_magia_tile_ni_13_21_req; -floo_rsp_t magia_tile_ni_13_21_to_router_13_21_rsp; - -floo_req_t router_13_22_to_router_12_22_req; -floo_rsp_t router_12_22_to_router_13_22_rsp; - -floo_req_t router_13_22_to_router_13_21_req; -floo_rsp_t router_13_21_to_router_13_22_rsp; - -floo_req_t router_13_22_to_router_13_23_req; -floo_rsp_t router_13_23_to_router_13_22_rsp; - -floo_req_t router_13_22_to_router_14_22_req; -floo_rsp_t router_14_22_to_router_13_22_rsp; - -floo_req_t router_13_22_to_magia_tile_ni_13_22_req; -floo_rsp_t magia_tile_ni_13_22_to_router_13_22_rsp; - -floo_req_t router_13_23_to_router_12_23_req; -floo_rsp_t router_12_23_to_router_13_23_rsp; - -floo_req_t router_13_23_to_router_13_22_req; -floo_rsp_t router_13_22_to_router_13_23_rsp; - -floo_req_t router_13_23_to_router_13_24_req; -floo_rsp_t router_13_24_to_router_13_23_rsp; - -floo_req_t router_13_23_to_router_14_23_req; -floo_rsp_t router_14_23_to_router_13_23_rsp; - -floo_req_t router_13_23_to_magia_tile_ni_13_23_req; -floo_rsp_t magia_tile_ni_13_23_to_router_13_23_rsp; - -floo_req_t router_13_24_to_router_12_24_req; -floo_rsp_t router_12_24_to_router_13_24_rsp; - -floo_req_t router_13_24_to_router_13_23_req; -floo_rsp_t router_13_23_to_router_13_24_rsp; - -floo_req_t router_13_24_to_router_13_25_req; -floo_rsp_t router_13_25_to_router_13_24_rsp; - -floo_req_t router_13_24_to_router_14_24_req; -floo_rsp_t router_14_24_to_router_13_24_rsp; - -floo_req_t router_13_24_to_magia_tile_ni_13_24_req; -floo_rsp_t magia_tile_ni_13_24_to_router_13_24_rsp; - -floo_req_t router_13_25_to_router_12_25_req; -floo_rsp_t router_12_25_to_router_13_25_rsp; - -floo_req_t router_13_25_to_router_13_24_req; -floo_rsp_t router_13_24_to_router_13_25_rsp; - -floo_req_t router_13_25_to_router_13_26_req; -floo_rsp_t router_13_26_to_router_13_25_rsp; - -floo_req_t router_13_25_to_router_14_25_req; -floo_rsp_t router_14_25_to_router_13_25_rsp; - -floo_req_t router_13_25_to_magia_tile_ni_13_25_req; -floo_rsp_t magia_tile_ni_13_25_to_router_13_25_rsp; - -floo_req_t router_13_26_to_router_12_26_req; -floo_rsp_t router_12_26_to_router_13_26_rsp; - -floo_req_t router_13_26_to_router_13_25_req; -floo_rsp_t router_13_25_to_router_13_26_rsp; - -floo_req_t router_13_26_to_router_13_27_req; -floo_rsp_t router_13_27_to_router_13_26_rsp; - -floo_req_t router_13_26_to_router_14_26_req; -floo_rsp_t router_14_26_to_router_13_26_rsp; - -floo_req_t router_13_26_to_magia_tile_ni_13_26_req; -floo_rsp_t magia_tile_ni_13_26_to_router_13_26_rsp; - -floo_req_t router_13_27_to_router_12_27_req; -floo_rsp_t router_12_27_to_router_13_27_rsp; - -floo_req_t router_13_27_to_router_13_26_req; -floo_rsp_t router_13_26_to_router_13_27_rsp; - -floo_req_t router_13_27_to_router_13_28_req; -floo_rsp_t router_13_28_to_router_13_27_rsp; - -floo_req_t router_13_27_to_router_14_27_req; -floo_rsp_t router_14_27_to_router_13_27_rsp; - -floo_req_t router_13_27_to_magia_tile_ni_13_27_req; -floo_rsp_t magia_tile_ni_13_27_to_router_13_27_rsp; - -floo_req_t router_13_28_to_router_12_28_req; -floo_rsp_t router_12_28_to_router_13_28_rsp; - -floo_req_t router_13_28_to_router_13_27_req; -floo_rsp_t router_13_27_to_router_13_28_rsp; - -floo_req_t router_13_28_to_router_13_29_req; -floo_rsp_t router_13_29_to_router_13_28_rsp; - -floo_req_t router_13_28_to_router_14_28_req; -floo_rsp_t router_14_28_to_router_13_28_rsp; - -floo_req_t router_13_28_to_magia_tile_ni_13_28_req; -floo_rsp_t magia_tile_ni_13_28_to_router_13_28_rsp; - -floo_req_t router_13_29_to_router_12_29_req; -floo_rsp_t router_12_29_to_router_13_29_rsp; - -floo_req_t router_13_29_to_router_13_28_req; -floo_rsp_t router_13_28_to_router_13_29_rsp; - -floo_req_t router_13_29_to_router_13_30_req; -floo_rsp_t router_13_30_to_router_13_29_rsp; - -floo_req_t router_13_29_to_router_14_29_req; -floo_rsp_t router_14_29_to_router_13_29_rsp; - -floo_req_t router_13_29_to_magia_tile_ni_13_29_req; -floo_rsp_t magia_tile_ni_13_29_to_router_13_29_rsp; - -floo_req_t router_13_30_to_router_12_30_req; -floo_rsp_t router_12_30_to_router_13_30_rsp; - -floo_req_t router_13_30_to_router_13_29_req; -floo_rsp_t router_13_29_to_router_13_30_rsp; - -floo_req_t router_13_30_to_router_13_31_req; -floo_rsp_t router_13_31_to_router_13_30_rsp; - -floo_req_t router_13_30_to_router_14_30_req; -floo_rsp_t router_14_30_to_router_13_30_rsp; - -floo_req_t router_13_30_to_magia_tile_ni_13_30_req; -floo_rsp_t magia_tile_ni_13_30_to_router_13_30_rsp; - -floo_req_t router_13_31_to_router_12_31_req; -floo_rsp_t router_12_31_to_router_13_31_rsp; - -floo_req_t router_13_31_to_router_13_30_req; -floo_rsp_t router_13_30_to_router_13_31_rsp; - -floo_req_t router_13_31_to_router_14_31_req; -floo_rsp_t router_14_31_to_router_13_31_rsp; - -floo_req_t router_13_31_to_magia_tile_ni_13_31_req; -floo_rsp_t magia_tile_ni_13_31_to_router_13_31_rsp; - -floo_req_t router_14_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_router_14_0_rsp; - -floo_req_t router_14_0_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_14_0_rsp; - -floo_req_t router_14_0_to_router_15_0_req; -floo_rsp_t router_15_0_to_router_14_0_rsp; - -floo_req_t router_14_0_to_magia_tile_ni_14_0_req; -floo_rsp_t magia_tile_ni_14_0_to_router_14_0_rsp; - -floo_req_t router_14_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_14_1_rsp; - -floo_req_t router_14_1_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_14_1_rsp; - -floo_req_t router_14_1_to_magia_tile_ni_14_1_req; -floo_rsp_t magia_tile_ni_14_1_to_router_14_1_rsp; - -floo_req_t router_14_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_14_2_rsp; - -floo_req_t router_14_2_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_14_2_rsp; - -floo_req_t router_14_2_to_magia_tile_ni_14_2_req; -floo_rsp_t magia_tile_ni_14_2_to_router_14_2_rsp; - -floo_req_t router_14_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_14_3_rsp; - -floo_req_t router_14_3_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_14_3_rsp; - -floo_req_t router_14_3_to_magia_tile_ni_14_3_req; -floo_rsp_t magia_tile_ni_14_3_to_router_14_3_rsp; - -floo_req_t router_14_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_14_4_rsp; - -floo_req_t router_14_4_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_14_4_rsp; - -floo_req_t router_14_4_to_magia_tile_ni_14_4_req; -floo_rsp_t magia_tile_ni_14_4_to_router_14_4_rsp; - -floo_req_t router_14_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_14_5_rsp; - -floo_req_t router_14_5_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_14_5_rsp; - -floo_req_t router_14_5_to_magia_tile_ni_14_5_req; -floo_rsp_t magia_tile_ni_14_5_to_router_14_5_rsp; - -floo_req_t router_14_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_14_6_rsp; - -floo_req_t router_14_6_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_14_6_rsp; - -floo_req_t router_14_6_to_magia_tile_ni_14_6_req; -floo_rsp_t magia_tile_ni_14_6_to_router_14_6_rsp; - -floo_req_t router_14_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_14_7_rsp; - -floo_req_t router_14_7_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_14_7_rsp; - -floo_req_t router_14_7_to_magia_tile_ni_14_7_req; -floo_rsp_t magia_tile_ni_14_7_to_router_14_7_rsp; - -floo_req_t router_14_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_14_8_rsp; - -floo_req_t router_14_8_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_14_8_rsp; - -floo_req_t router_14_8_to_magia_tile_ni_14_8_req; -floo_rsp_t magia_tile_ni_14_8_to_router_14_8_rsp; - -floo_req_t router_14_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_14_9_rsp; - -floo_req_t router_14_9_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_14_9_rsp; - -floo_req_t router_14_9_to_magia_tile_ni_14_9_req; -floo_rsp_t magia_tile_ni_14_9_to_router_14_9_rsp; - -floo_req_t router_14_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_14_10_rsp; - -floo_req_t router_14_10_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_14_10_rsp; - -floo_req_t router_14_10_to_magia_tile_ni_14_10_req; -floo_rsp_t magia_tile_ni_14_10_to_router_14_10_rsp; - -floo_req_t router_14_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_14_11_rsp; - -floo_req_t router_14_11_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_14_11_rsp; - -floo_req_t router_14_11_to_magia_tile_ni_14_11_req; -floo_rsp_t magia_tile_ni_14_11_to_router_14_11_rsp; - -floo_req_t router_14_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_14_12_rsp; - -floo_req_t router_14_12_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_14_12_rsp; - -floo_req_t router_14_12_to_magia_tile_ni_14_12_req; -floo_rsp_t magia_tile_ni_14_12_to_router_14_12_rsp; - -floo_req_t router_14_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_14_13_rsp; - -floo_req_t router_14_13_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_14_13_rsp; - -floo_req_t router_14_13_to_magia_tile_ni_14_13_req; -floo_rsp_t magia_tile_ni_14_13_to_router_14_13_rsp; - -floo_req_t router_14_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_14_14_rsp; - -floo_req_t router_14_14_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_14_14_rsp; - -floo_req_t router_14_14_to_magia_tile_ni_14_14_req; -floo_rsp_t magia_tile_ni_14_14_to_router_14_14_rsp; - -floo_req_t router_14_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_router_14_15_rsp; - -floo_req_t router_14_15_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_14_15_rsp; - -floo_req_t router_14_15_to_router_14_16_req; -floo_rsp_t router_14_16_to_router_14_15_rsp; - -floo_req_t router_14_15_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_14_15_rsp; - -floo_req_t router_14_15_to_magia_tile_ni_14_15_req; -floo_rsp_t magia_tile_ni_14_15_to_router_14_15_rsp; - -floo_req_t router_14_16_to_router_13_16_req; -floo_rsp_t router_13_16_to_router_14_16_rsp; - -floo_req_t router_14_16_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_14_16_rsp; - -floo_req_t router_14_16_to_router_14_17_req; -floo_rsp_t router_14_17_to_router_14_16_rsp; - -floo_req_t router_14_16_to_router_15_16_req; -floo_rsp_t router_15_16_to_router_14_16_rsp; - -floo_req_t router_14_16_to_magia_tile_ni_14_16_req; -floo_rsp_t magia_tile_ni_14_16_to_router_14_16_rsp; - -floo_req_t router_14_17_to_router_13_17_req; -floo_rsp_t router_13_17_to_router_14_17_rsp; - -floo_req_t router_14_17_to_router_14_16_req; -floo_rsp_t router_14_16_to_router_14_17_rsp; - -floo_req_t router_14_17_to_router_14_18_req; -floo_rsp_t router_14_18_to_router_14_17_rsp; - -floo_req_t router_14_17_to_router_15_17_req; -floo_rsp_t router_15_17_to_router_14_17_rsp; - -floo_req_t router_14_17_to_magia_tile_ni_14_17_req; -floo_rsp_t magia_tile_ni_14_17_to_router_14_17_rsp; - -floo_req_t router_14_18_to_router_13_18_req; -floo_rsp_t router_13_18_to_router_14_18_rsp; - -floo_req_t router_14_18_to_router_14_17_req; -floo_rsp_t router_14_17_to_router_14_18_rsp; - -floo_req_t router_14_18_to_router_14_19_req; -floo_rsp_t router_14_19_to_router_14_18_rsp; - -floo_req_t router_14_18_to_router_15_18_req; -floo_rsp_t router_15_18_to_router_14_18_rsp; - -floo_req_t router_14_18_to_magia_tile_ni_14_18_req; -floo_rsp_t magia_tile_ni_14_18_to_router_14_18_rsp; - -floo_req_t router_14_19_to_router_13_19_req; -floo_rsp_t router_13_19_to_router_14_19_rsp; - -floo_req_t router_14_19_to_router_14_18_req; -floo_rsp_t router_14_18_to_router_14_19_rsp; - -floo_req_t router_14_19_to_router_14_20_req; -floo_rsp_t router_14_20_to_router_14_19_rsp; - -floo_req_t router_14_19_to_router_15_19_req; -floo_rsp_t router_15_19_to_router_14_19_rsp; - -floo_req_t router_14_19_to_magia_tile_ni_14_19_req; -floo_rsp_t magia_tile_ni_14_19_to_router_14_19_rsp; - -floo_req_t router_14_20_to_router_13_20_req; -floo_rsp_t router_13_20_to_router_14_20_rsp; - -floo_req_t router_14_20_to_router_14_19_req; -floo_rsp_t router_14_19_to_router_14_20_rsp; - -floo_req_t router_14_20_to_router_14_21_req; -floo_rsp_t router_14_21_to_router_14_20_rsp; - -floo_req_t router_14_20_to_router_15_20_req; -floo_rsp_t router_15_20_to_router_14_20_rsp; - -floo_req_t router_14_20_to_magia_tile_ni_14_20_req; -floo_rsp_t magia_tile_ni_14_20_to_router_14_20_rsp; - -floo_req_t router_14_21_to_router_13_21_req; -floo_rsp_t router_13_21_to_router_14_21_rsp; - -floo_req_t router_14_21_to_router_14_20_req; -floo_rsp_t router_14_20_to_router_14_21_rsp; - -floo_req_t router_14_21_to_router_14_22_req; -floo_rsp_t router_14_22_to_router_14_21_rsp; - -floo_req_t router_14_21_to_router_15_21_req; -floo_rsp_t router_15_21_to_router_14_21_rsp; - -floo_req_t router_14_21_to_magia_tile_ni_14_21_req; -floo_rsp_t magia_tile_ni_14_21_to_router_14_21_rsp; - -floo_req_t router_14_22_to_router_13_22_req; -floo_rsp_t router_13_22_to_router_14_22_rsp; - -floo_req_t router_14_22_to_router_14_21_req; -floo_rsp_t router_14_21_to_router_14_22_rsp; - -floo_req_t router_14_22_to_router_14_23_req; -floo_rsp_t router_14_23_to_router_14_22_rsp; - -floo_req_t router_14_22_to_router_15_22_req; -floo_rsp_t router_15_22_to_router_14_22_rsp; - -floo_req_t router_14_22_to_magia_tile_ni_14_22_req; -floo_rsp_t magia_tile_ni_14_22_to_router_14_22_rsp; - -floo_req_t router_14_23_to_router_13_23_req; -floo_rsp_t router_13_23_to_router_14_23_rsp; - -floo_req_t router_14_23_to_router_14_22_req; -floo_rsp_t router_14_22_to_router_14_23_rsp; - -floo_req_t router_14_23_to_router_14_24_req; -floo_rsp_t router_14_24_to_router_14_23_rsp; - -floo_req_t router_14_23_to_router_15_23_req; -floo_rsp_t router_15_23_to_router_14_23_rsp; - -floo_req_t router_14_23_to_magia_tile_ni_14_23_req; -floo_rsp_t magia_tile_ni_14_23_to_router_14_23_rsp; - -floo_req_t router_14_24_to_router_13_24_req; -floo_rsp_t router_13_24_to_router_14_24_rsp; - -floo_req_t router_14_24_to_router_14_23_req; -floo_rsp_t router_14_23_to_router_14_24_rsp; - -floo_req_t router_14_24_to_router_14_25_req; -floo_rsp_t router_14_25_to_router_14_24_rsp; - -floo_req_t router_14_24_to_router_15_24_req; -floo_rsp_t router_15_24_to_router_14_24_rsp; - -floo_req_t router_14_24_to_magia_tile_ni_14_24_req; -floo_rsp_t magia_tile_ni_14_24_to_router_14_24_rsp; - -floo_req_t router_14_25_to_router_13_25_req; -floo_rsp_t router_13_25_to_router_14_25_rsp; - -floo_req_t router_14_25_to_router_14_24_req; -floo_rsp_t router_14_24_to_router_14_25_rsp; - -floo_req_t router_14_25_to_router_14_26_req; -floo_rsp_t router_14_26_to_router_14_25_rsp; - -floo_req_t router_14_25_to_router_15_25_req; -floo_rsp_t router_15_25_to_router_14_25_rsp; - -floo_req_t router_14_25_to_magia_tile_ni_14_25_req; -floo_rsp_t magia_tile_ni_14_25_to_router_14_25_rsp; - -floo_req_t router_14_26_to_router_13_26_req; -floo_rsp_t router_13_26_to_router_14_26_rsp; - -floo_req_t router_14_26_to_router_14_25_req; -floo_rsp_t router_14_25_to_router_14_26_rsp; - -floo_req_t router_14_26_to_router_14_27_req; -floo_rsp_t router_14_27_to_router_14_26_rsp; - -floo_req_t router_14_26_to_router_15_26_req; -floo_rsp_t router_15_26_to_router_14_26_rsp; - -floo_req_t router_14_26_to_magia_tile_ni_14_26_req; -floo_rsp_t magia_tile_ni_14_26_to_router_14_26_rsp; - -floo_req_t router_14_27_to_router_13_27_req; -floo_rsp_t router_13_27_to_router_14_27_rsp; - -floo_req_t router_14_27_to_router_14_26_req; -floo_rsp_t router_14_26_to_router_14_27_rsp; - -floo_req_t router_14_27_to_router_14_28_req; -floo_rsp_t router_14_28_to_router_14_27_rsp; - -floo_req_t router_14_27_to_router_15_27_req; -floo_rsp_t router_15_27_to_router_14_27_rsp; - -floo_req_t router_14_27_to_magia_tile_ni_14_27_req; -floo_rsp_t magia_tile_ni_14_27_to_router_14_27_rsp; - -floo_req_t router_14_28_to_router_13_28_req; -floo_rsp_t router_13_28_to_router_14_28_rsp; - -floo_req_t router_14_28_to_router_14_27_req; -floo_rsp_t router_14_27_to_router_14_28_rsp; - -floo_req_t router_14_28_to_router_14_29_req; -floo_rsp_t router_14_29_to_router_14_28_rsp; - -floo_req_t router_14_28_to_router_15_28_req; -floo_rsp_t router_15_28_to_router_14_28_rsp; - -floo_req_t router_14_28_to_magia_tile_ni_14_28_req; -floo_rsp_t magia_tile_ni_14_28_to_router_14_28_rsp; - -floo_req_t router_14_29_to_router_13_29_req; -floo_rsp_t router_13_29_to_router_14_29_rsp; - -floo_req_t router_14_29_to_router_14_28_req; -floo_rsp_t router_14_28_to_router_14_29_rsp; - -floo_req_t router_14_29_to_router_14_30_req; -floo_rsp_t router_14_30_to_router_14_29_rsp; - -floo_req_t router_14_29_to_router_15_29_req; -floo_rsp_t router_15_29_to_router_14_29_rsp; - -floo_req_t router_14_29_to_magia_tile_ni_14_29_req; -floo_rsp_t magia_tile_ni_14_29_to_router_14_29_rsp; - -floo_req_t router_14_30_to_router_13_30_req; -floo_rsp_t router_13_30_to_router_14_30_rsp; - -floo_req_t router_14_30_to_router_14_29_req; -floo_rsp_t router_14_29_to_router_14_30_rsp; - -floo_req_t router_14_30_to_router_14_31_req; -floo_rsp_t router_14_31_to_router_14_30_rsp; - -floo_req_t router_14_30_to_router_15_30_req; -floo_rsp_t router_15_30_to_router_14_30_rsp; - -floo_req_t router_14_30_to_magia_tile_ni_14_30_req; -floo_rsp_t magia_tile_ni_14_30_to_router_14_30_rsp; - -floo_req_t router_14_31_to_router_13_31_req; -floo_rsp_t router_13_31_to_router_14_31_rsp; - -floo_req_t router_14_31_to_router_14_30_req; -floo_rsp_t router_14_30_to_router_14_31_rsp; - -floo_req_t router_14_31_to_router_15_31_req; -floo_rsp_t router_15_31_to_router_14_31_rsp; - -floo_req_t router_14_31_to_magia_tile_ni_14_31_req; -floo_rsp_t magia_tile_ni_14_31_to_router_14_31_rsp; - -floo_req_t router_15_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_router_15_0_rsp; - -floo_req_t router_15_0_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_15_0_rsp; - -floo_req_t router_15_0_to_router_16_0_req; -floo_rsp_t router_16_0_to_router_15_0_rsp; - -floo_req_t router_15_0_to_magia_tile_ni_15_0_req; -floo_rsp_t magia_tile_ni_15_0_to_router_15_0_rsp; - -floo_req_t router_15_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_router_15_1_rsp; - -floo_req_t router_15_1_to_router_15_0_req; -floo_rsp_t router_15_0_to_router_15_1_rsp; - -floo_req_t router_15_1_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_15_1_rsp; - -floo_req_t router_15_1_to_router_16_1_req; -floo_rsp_t router_16_1_to_router_15_1_rsp; - -floo_req_t router_15_1_to_magia_tile_ni_15_1_req; -floo_rsp_t magia_tile_ni_15_1_to_router_15_1_rsp; - -floo_req_t router_15_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_router_15_2_rsp; - -floo_req_t router_15_2_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_15_2_rsp; - -floo_req_t router_15_2_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_15_2_rsp; - -floo_req_t router_15_2_to_router_16_2_req; -floo_rsp_t router_16_2_to_router_15_2_rsp; - -floo_req_t router_15_2_to_magia_tile_ni_15_2_req; -floo_rsp_t magia_tile_ni_15_2_to_router_15_2_rsp; - -floo_req_t router_15_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_router_15_3_rsp; - -floo_req_t router_15_3_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_15_3_rsp; - -floo_req_t router_15_3_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_15_3_rsp; - -floo_req_t router_15_3_to_router_16_3_req; -floo_rsp_t router_16_3_to_router_15_3_rsp; - -floo_req_t router_15_3_to_magia_tile_ni_15_3_req; -floo_rsp_t magia_tile_ni_15_3_to_router_15_3_rsp; - -floo_req_t router_15_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_router_15_4_rsp; - -floo_req_t router_15_4_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_15_4_rsp; - -floo_req_t router_15_4_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_15_4_rsp; - -floo_req_t router_15_4_to_router_16_4_req; -floo_rsp_t router_16_4_to_router_15_4_rsp; - -floo_req_t router_15_4_to_magia_tile_ni_15_4_req; -floo_rsp_t magia_tile_ni_15_4_to_router_15_4_rsp; - -floo_req_t router_15_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_router_15_5_rsp; - -floo_req_t router_15_5_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_15_5_rsp; - -floo_req_t router_15_5_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_15_5_rsp; - -floo_req_t router_15_5_to_router_16_5_req; -floo_rsp_t router_16_5_to_router_15_5_rsp; - -floo_req_t router_15_5_to_magia_tile_ni_15_5_req; -floo_rsp_t magia_tile_ni_15_5_to_router_15_5_rsp; - -floo_req_t router_15_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_router_15_6_rsp; - -floo_req_t router_15_6_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_15_6_rsp; - -floo_req_t router_15_6_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_15_6_rsp; - -floo_req_t router_15_6_to_router_16_6_req; -floo_rsp_t router_16_6_to_router_15_6_rsp; - -floo_req_t router_15_6_to_magia_tile_ni_15_6_req; -floo_rsp_t magia_tile_ni_15_6_to_router_15_6_rsp; - -floo_req_t router_15_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_router_15_7_rsp; - -floo_req_t router_15_7_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_15_7_rsp; - -floo_req_t router_15_7_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_15_7_rsp; - -floo_req_t router_15_7_to_router_16_7_req; -floo_rsp_t router_16_7_to_router_15_7_rsp; - -floo_req_t router_15_7_to_magia_tile_ni_15_7_req; -floo_rsp_t magia_tile_ni_15_7_to_router_15_7_rsp; - -floo_req_t router_15_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_router_15_8_rsp; - -floo_req_t router_15_8_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_15_8_rsp; - -floo_req_t router_15_8_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_15_8_rsp; - -floo_req_t router_15_8_to_router_16_8_req; -floo_rsp_t router_16_8_to_router_15_8_rsp; - -floo_req_t router_15_8_to_magia_tile_ni_15_8_req; -floo_rsp_t magia_tile_ni_15_8_to_router_15_8_rsp; - -floo_req_t router_15_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_router_15_9_rsp; - -floo_req_t router_15_9_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_15_9_rsp; - -floo_req_t router_15_9_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_15_9_rsp; - -floo_req_t router_15_9_to_router_16_9_req; -floo_rsp_t router_16_9_to_router_15_9_rsp; - -floo_req_t router_15_9_to_magia_tile_ni_15_9_req; -floo_rsp_t magia_tile_ni_15_9_to_router_15_9_rsp; - -floo_req_t router_15_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_router_15_10_rsp; - -floo_req_t router_15_10_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_15_10_rsp; - -floo_req_t router_15_10_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_15_10_rsp; - -floo_req_t router_15_10_to_router_16_10_req; -floo_rsp_t router_16_10_to_router_15_10_rsp; - -floo_req_t router_15_10_to_magia_tile_ni_15_10_req; -floo_rsp_t magia_tile_ni_15_10_to_router_15_10_rsp; - -floo_req_t router_15_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_router_15_11_rsp; - -floo_req_t router_15_11_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_15_11_rsp; - -floo_req_t router_15_11_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_15_11_rsp; - -floo_req_t router_15_11_to_router_16_11_req; -floo_rsp_t router_16_11_to_router_15_11_rsp; - -floo_req_t router_15_11_to_magia_tile_ni_15_11_req; -floo_rsp_t magia_tile_ni_15_11_to_router_15_11_rsp; - -floo_req_t router_15_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_router_15_12_rsp; - -floo_req_t router_15_12_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_15_12_rsp; - -floo_req_t router_15_12_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_15_12_rsp; - -floo_req_t router_15_12_to_router_16_12_req; -floo_rsp_t router_16_12_to_router_15_12_rsp; - -floo_req_t router_15_12_to_magia_tile_ni_15_12_req; -floo_rsp_t magia_tile_ni_15_12_to_router_15_12_rsp; - -floo_req_t router_15_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_router_15_13_rsp; - -floo_req_t router_15_13_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_15_13_rsp; - -floo_req_t router_15_13_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_15_13_rsp; - -floo_req_t router_15_13_to_router_16_13_req; -floo_rsp_t router_16_13_to_router_15_13_rsp; - -floo_req_t router_15_13_to_magia_tile_ni_15_13_req; -floo_rsp_t magia_tile_ni_15_13_to_router_15_13_rsp; - -floo_req_t router_15_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_router_15_14_rsp; - -floo_req_t router_15_14_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_15_14_rsp; - -floo_req_t router_15_14_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_15_14_rsp; - -floo_req_t router_15_14_to_router_16_14_req; -floo_rsp_t router_16_14_to_router_15_14_rsp; - -floo_req_t router_15_14_to_magia_tile_ni_15_14_req; -floo_rsp_t magia_tile_ni_15_14_to_router_15_14_rsp; - -floo_req_t router_15_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_router_15_15_rsp; - -floo_req_t router_15_15_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_15_15_rsp; - -floo_req_t router_15_15_to_router_15_16_req; -floo_rsp_t router_15_16_to_router_15_15_rsp; - -floo_req_t router_15_15_to_router_16_15_req; -floo_rsp_t router_16_15_to_router_15_15_rsp; - -floo_req_t router_15_15_to_magia_tile_ni_15_15_req; -floo_rsp_t magia_tile_ni_15_15_to_router_15_15_rsp; - -floo_req_t router_15_16_to_router_14_16_req; -floo_rsp_t router_14_16_to_router_15_16_rsp; - -floo_req_t router_15_16_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_15_16_rsp; - -floo_req_t router_15_16_to_router_15_17_req; -floo_rsp_t router_15_17_to_router_15_16_rsp; - -floo_req_t router_15_16_to_router_16_16_req; -floo_rsp_t router_16_16_to_router_15_16_rsp; - -floo_req_t router_15_16_to_magia_tile_ni_15_16_req; -floo_rsp_t magia_tile_ni_15_16_to_router_15_16_rsp; - -floo_req_t router_15_17_to_router_14_17_req; -floo_rsp_t router_14_17_to_router_15_17_rsp; - -floo_req_t router_15_17_to_router_15_16_req; -floo_rsp_t router_15_16_to_router_15_17_rsp; - -floo_req_t router_15_17_to_router_15_18_req; -floo_rsp_t router_15_18_to_router_15_17_rsp; - -floo_req_t router_15_17_to_router_16_17_req; -floo_rsp_t router_16_17_to_router_15_17_rsp; - -floo_req_t router_15_17_to_magia_tile_ni_15_17_req; -floo_rsp_t magia_tile_ni_15_17_to_router_15_17_rsp; - -floo_req_t router_15_18_to_router_14_18_req; -floo_rsp_t router_14_18_to_router_15_18_rsp; - -floo_req_t router_15_18_to_router_15_17_req; -floo_rsp_t router_15_17_to_router_15_18_rsp; - -floo_req_t router_15_18_to_router_15_19_req; -floo_rsp_t router_15_19_to_router_15_18_rsp; - -floo_req_t router_15_18_to_router_16_18_req; -floo_rsp_t router_16_18_to_router_15_18_rsp; - -floo_req_t router_15_18_to_magia_tile_ni_15_18_req; -floo_rsp_t magia_tile_ni_15_18_to_router_15_18_rsp; - -floo_req_t router_15_19_to_router_14_19_req; -floo_rsp_t router_14_19_to_router_15_19_rsp; - -floo_req_t router_15_19_to_router_15_18_req; -floo_rsp_t router_15_18_to_router_15_19_rsp; - -floo_req_t router_15_19_to_router_15_20_req; -floo_rsp_t router_15_20_to_router_15_19_rsp; - -floo_req_t router_15_19_to_router_16_19_req; -floo_rsp_t router_16_19_to_router_15_19_rsp; - -floo_req_t router_15_19_to_magia_tile_ni_15_19_req; -floo_rsp_t magia_tile_ni_15_19_to_router_15_19_rsp; - -floo_req_t router_15_20_to_router_14_20_req; -floo_rsp_t router_14_20_to_router_15_20_rsp; - -floo_req_t router_15_20_to_router_15_19_req; -floo_rsp_t router_15_19_to_router_15_20_rsp; - -floo_req_t router_15_20_to_router_15_21_req; -floo_rsp_t router_15_21_to_router_15_20_rsp; - -floo_req_t router_15_20_to_router_16_20_req; -floo_rsp_t router_16_20_to_router_15_20_rsp; - -floo_req_t router_15_20_to_magia_tile_ni_15_20_req; -floo_rsp_t magia_tile_ni_15_20_to_router_15_20_rsp; - -floo_req_t router_15_21_to_router_14_21_req; -floo_rsp_t router_14_21_to_router_15_21_rsp; - -floo_req_t router_15_21_to_router_15_20_req; -floo_rsp_t router_15_20_to_router_15_21_rsp; - -floo_req_t router_15_21_to_router_15_22_req; -floo_rsp_t router_15_22_to_router_15_21_rsp; - -floo_req_t router_15_21_to_router_16_21_req; -floo_rsp_t router_16_21_to_router_15_21_rsp; - -floo_req_t router_15_21_to_magia_tile_ni_15_21_req; -floo_rsp_t magia_tile_ni_15_21_to_router_15_21_rsp; - -floo_req_t router_15_22_to_router_14_22_req; -floo_rsp_t router_14_22_to_router_15_22_rsp; - -floo_req_t router_15_22_to_router_15_21_req; -floo_rsp_t router_15_21_to_router_15_22_rsp; - -floo_req_t router_15_22_to_router_15_23_req; -floo_rsp_t router_15_23_to_router_15_22_rsp; - -floo_req_t router_15_22_to_router_16_22_req; -floo_rsp_t router_16_22_to_router_15_22_rsp; - -floo_req_t router_15_22_to_magia_tile_ni_15_22_req; -floo_rsp_t magia_tile_ni_15_22_to_router_15_22_rsp; - -floo_req_t router_15_23_to_router_14_23_req; -floo_rsp_t router_14_23_to_router_15_23_rsp; - -floo_req_t router_15_23_to_router_15_22_req; -floo_rsp_t router_15_22_to_router_15_23_rsp; - -floo_req_t router_15_23_to_router_15_24_req; -floo_rsp_t router_15_24_to_router_15_23_rsp; - -floo_req_t router_15_23_to_router_16_23_req; -floo_rsp_t router_16_23_to_router_15_23_rsp; - -floo_req_t router_15_23_to_magia_tile_ni_15_23_req; -floo_rsp_t magia_tile_ni_15_23_to_router_15_23_rsp; - -floo_req_t router_15_24_to_router_14_24_req; -floo_rsp_t router_14_24_to_router_15_24_rsp; - -floo_req_t router_15_24_to_router_15_23_req; -floo_rsp_t router_15_23_to_router_15_24_rsp; - -floo_req_t router_15_24_to_router_15_25_req; -floo_rsp_t router_15_25_to_router_15_24_rsp; - -floo_req_t router_15_24_to_router_16_24_req; -floo_rsp_t router_16_24_to_router_15_24_rsp; - -floo_req_t router_15_24_to_magia_tile_ni_15_24_req; -floo_rsp_t magia_tile_ni_15_24_to_router_15_24_rsp; - -floo_req_t router_15_25_to_router_14_25_req; -floo_rsp_t router_14_25_to_router_15_25_rsp; - -floo_req_t router_15_25_to_router_15_24_req; -floo_rsp_t router_15_24_to_router_15_25_rsp; - -floo_req_t router_15_25_to_router_15_26_req; -floo_rsp_t router_15_26_to_router_15_25_rsp; - -floo_req_t router_15_25_to_router_16_25_req; -floo_rsp_t router_16_25_to_router_15_25_rsp; - -floo_req_t router_15_25_to_magia_tile_ni_15_25_req; -floo_rsp_t magia_tile_ni_15_25_to_router_15_25_rsp; - -floo_req_t router_15_26_to_router_14_26_req; -floo_rsp_t router_14_26_to_router_15_26_rsp; - -floo_req_t router_15_26_to_router_15_25_req; -floo_rsp_t router_15_25_to_router_15_26_rsp; - -floo_req_t router_15_26_to_router_15_27_req; -floo_rsp_t router_15_27_to_router_15_26_rsp; - -floo_req_t router_15_26_to_router_16_26_req; -floo_rsp_t router_16_26_to_router_15_26_rsp; - -floo_req_t router_15_26_to_magia_tile_ni_15_26_req; -floo_rsp_t magia_tile_ni_15_26_to_router_15_26_rsp; - -floo_req_t router_15_27_to_router_14_27_req; -floo_rsp_t router_14_27_to_router_15_27_rsp; - -floo_req_t router_15_27_to_router_15_26_req; -floo_rsp_t router_15_26_to_router_15_27_rsp; - -floo_req_t router_15_27_to_router_15_28_req; -floo_rsp_t router_15_28_to_router_15_27_rsp; - -floo_req_t router_15_27_to_router_16_27_req; -floo_rsp_t router_16_27_to_router_15_27_rsp; - -floo_req_t router_15_27_to_magia_tile_ni_15_27_req; -floo_rsp_t magia_tile_ni_15_27_to_router_15_27_rsp; - -floo_req_t router_15_28_to_router_14_28_req; -floo_rsp_t router_14_28_to_router_15_28_rsp; - -floo_req_t router_15_28_to_router_15_27_req; -floo_rsp_t router_15_27_to_router_15_28_rsp; - -floo_req_t router_15_28_to_router_15_29_req; -floo_rsp_t router_15_29_to_router_15_28_rsp; - -floo_req_t router_15_28_to_router_16_28_req; -floo_rsp_t router_16_28_to_router_15_28_rsp; - -floo_req_t router_15_28_to_magia_tile_ni_15_28_req; -floo_rsp_t magia_tile_ni_15_28_to_router_15_28_rsp; - -floo_req_t router_15_29_to_router_14_29_req; -floo_rsp_t router_14_29_to_router_15_29_rsp; - -floo_req_t router_15_29_to_router_15_28_req; -floo_rsp_t router_15_28_to_router_15_29_rsp; - -floo_req_t router_15_29_to_router_15_30_req; -floo_rsp_t router_15_30_to_router_15_29_rsp; - -floo_req_t router_15_29_to_router_16_29_req; -floo_rsp_t router_16_29_to_router_15_29_rsp; - -floo_req_t router_15_29_to_magia_tile_ni_15_29_req; -floo_rsp_t magia_tile_ni_15_29_to_router_15_29_rsp; - -floo_req_t router_15_30_to_router_14_30_req; -floo_rsp_t router_14_30_to_router_15_30_rsp; - -floo_req_t router_15_30_to_router_15_29_req; -floo_rsp_t router_15_29_to_router_15_30_rsp; - -floo_req_t router_15_30_to_router_15_31_req; -floo_rsp_t router_15_31_to_router_15_30_rsp; - -floo_req_t router_15_30_to_router_16_30_req; -floo_rsp_t router_16_30_to_router_15_30_rsp; - -floo_req_t router_15_30_to_magia_tile_ni_15_30_req; -floo_rsp_t magia_tile_ni_15_30_to_router_15_30_rsp; - -floo_req_t router_15_31_to_router_14_31_req; -floo_rsp_t router_14_31_to_router_15_31_rsp; - -floo_req_t router_15_31_to_router_15_30_req; -floo_rsp_t router_15_30_to_router_15_31_rsp; - -floo_req_t router_15_31_to_router_16_31_req; -floo_rsp_t router_16_31_to_router_15_31_rsp; - -floo_req_t router_15_31_to_magia_tile_ni_15_31_req; -floo_rsp_t magia_tile_ni_15_31_to_router_15_31_rsp; - -floo_req_t router_16_0_to_router_15_0_req; -floo_rsp_t router_15_0_to_router_16_0_rsp; - -floo_req_t router_16_0_to_router_16_1_req; -floo_rsp_t router_16_1_to_router_16_0_rsp; - -floo_req_t router_16_0_to_router_17_0_req; -floo_rsp_t router_17_0_to_router_16_0_rsp; - -floo_req_t router_16_0_to_magia_tile_ni_16_0_req; -floo_rsp_t magia_tile_ni_16_0_to_router_16_0_rsp; - -floo_req_t router_16_1_to_router_15_1_req; -floo_rsp_t router_15_1_to_router_16_1_rsp; - -floo_req_t router_16_1_to_router_16_0_req; -floo_rsp_t router_16_0_to_router_16_1_rsp; - -floo_req_t router_16_1_to_router_16_2_req; -floo_rsp_t router_16_2_to_router_16_1_rsp; - -floo_req_t router_16_1_to_router_17_1_req; -floo_rsp_t router_17_1_to_router_16_1_rsp; - -floo_req_t router_16_1_to_magia_tile_ni_16_1_req; -floo_rsp_t magia_tile_ni_16_1_to_router_16_1_rsp; - -floo_req_t router_16_2_to_router_15_2_req; -floo_rsp_t router_15_2_to_router_16_2_rsp; - -floo_req_t router_16_2_to_router_16_1_req; -floo_rsp_t router_16_1_to_router_16_2_rsp; - -floo_req_t router_16_2_to_router_16_3_req; -floo_rsp_t router_16_3_to_router_16_2_rsp; - -floo_req_t router_16_2_to_router_17_2_req; -floo_rsp_t router_17_2_to_router_16_2_rsp; - -floo_req_t router_16_2_to_magia_tile_ni_16_2_req; -floo_rsp_t magia_tile_ni_16_2_to_router_16_2_rsp; - -floo_req_t router_16_3_to_router_15_3_req; -floo_rsp_t router_15_3_to_router_16_3_rsp; - -floo_req_t router_16_3_to_router_16_2_req; -floo_rsp_t router_16_2_to_router_16_3_rsp; - -floo_req_t router_16_3_to_router_16_4_req; -floo_rsp_t router_16_4_to_router_16_3_rsp; - -floo_req_t router_16_3_to_router_17_3_req; -floo_rsp_t router_17_3_to_router_16_3_rsp; - -floo_req_t router_16_3_to_magia_tile_ni_16_3_req; -floo_rsp_t magia_tile_ni_16_3_to_router_16_3_rsp; - -floo_req_t router_16_4_to_router_15_4_req; -floo_rsp_t router_15_4_to_router_16_4_rsp; - -floo_req_t router_16_4_to_router_16_3_req; -floo_rsp_t router_16_3_to_router_16_4_rsp; - -floo_req_t router_16_4_to_router_16_5_req; -floo_rsp_t router_16_5_to_router_16_4_rsp; - -floo_req_t router_16_4_to_router_17_4_req; -floo_rsp_t router_17_4_to_router_16_4_rsp; - -floo_req_t router_16_4_to_magia_tile_ni_16_4_req; -floo_rsp_t magia_tile_ni_16_4_to_router_16_4_rsp; - -floo_req_t router_16_5_to_router_15_5_req; -floo_rsp_t router_15_5_to_router_16_5_rsp; - -floo_req_t router_16_5_to_router_16_4_req; -floo_rsp_t router_16_4_to_router_16_5_rsp; - -floo_req_t router_16_5_to_router_16_6_req; -floo_rsp_t router_16_6_to_router_16_5_rsp; - -floo_req_t router_16_5_to_router_17_5_req; -floo_rsp_t router_17_5_to_router_16_5_rsp; - -floo_req_t router_16_5_to_magia_tile_ni_16_5_req; -floo_rsp_t magia_tile_ni_16_5_to_router_16_5_rsp; - -floo_req_t router_16_6_to_router_15_6_req; -floo_rsp_t router_15_6_to_router_16_6_rsp; - -floo_req_t router_16_6_to_router_16_5_req; -floo_rsp_t router_16_5_to_router_16_6_rsp; - -floo_req_t router_16_6_to_router_16_7_req; -floo_rsp_t router_16_7_to_router_16_6_rsp; - -floo_req_t router_16_6_to_router_17_6_req; -floo_rsp_t router_17_6_to_router_16_6_rsp; - -floo_req_t router_16_6_to_magia_tile_ni_16_6_req; -floo_rsp_t magia_tile_ni_16_6_to_router_16_6_rsp; - -floo_req_t router_16_7_to_router_15_7_req; -floo_rsp_t router_15_7_to_router_16_7_rsp; - -floo_req_t router_16_7_to_router_16_6_req; -floo_rsp_t router_16_6_to_router_16_7_rsp; - -floo_req_t router_16_7_to_router_16_8_req; -floo_rsp_t router_16_8_to_router_16_7_rsp; - -floo_req_t router_16_7_to_router_17_7_req; -floo_rsp_t router_17_7_to_router_16_7_rsp; - -floo_req_t router_16_7_to_magia_tile_ni_16_7_req; -floo_rsp_t magia_tile_ni_16_7_to_router_16_7_rsp; - -floo_req_t router_16_8_to_router_15_8_req; -floo_rsp_t router_15_8_to_router_16_8_rsp; - -floo_req_t router_16_8_to_router_16_7_req; -floo_rsp_t router_16_7_to_router_16_8_rsp; - -floo_req_t router_16_8_to_router_16_9_req; -floo_rsp_t router_16_9_to_router_16_8_rsp; - -floo_req_t router_16_8_to_router_17_8_req; -floo_rsp_t router_17_8_to_router_16_8_rsp; - -floo_req_t router_16_8_to_magia_tile_ni_16_8_req; -floo_rsp_t magia_tile_ni_16_8_to_router_16_8_rsp; - -floo_req_t router_16_9_to_router_15_9_req; -floo_rsp_t router_15_9_to_router_16_9_rsp; - -floo_req_t router_16_9_to_router_16_8_req; -floo_rsp_t router_16_8_to_router_16_9_rsp; - -floo_req_t router_16_9_to_router_16_10_req; -floo_rsp_t router_16_10_to_router_16_9_rsp; - -floo_req_t router_16_9_to_router_17_9_req; -floo_rsp_t router_17_9_to_router_16_9_rsp; - -floo_req_t router_16_9_to_magia_tile_ni_16_9_req; -floo_rsp_t magia_tile_ni_16_9_to_router_16_9_rsp; - -floo_req_t router_16_10_to_router_15_10_req; -floo_rsp_t router_15_10_to_router_16_10_rsp; - -floo_req_t router_16_10_to_router_16_9_req; -floo_rsp_t router_16_9_to_router_16_10_rsp; - -floo_req_t router_16_10_to_router_16_11_req; -floo_rsp_t router_16_11_to_router_16_10_rsp; - -floo_req_t router_16_10_to_router_17_10_req; -floo_rsp_t router_17_10_to_router_16_10_rsp; - -floo_req_t router_16_10_to_magia_tile_ni_16_10_req; -floo_rsp_t magia_tile_ni_16_10_to_router_16_10_rsp; - -floo_req_t router_16_11_to_router_15_11_req; -floo_rsp_t router_15_11_to_router_16_11_rsp; - -floo_req_t router_16_11_to_router_16_10_req; -floo_rsp_t router_16_10_to_router_16_11_rsp; - -floo_req_t router_16_11_to_router_16_12_req; -floo_rsp_t router_16_12_to_router_16_11_rsp; - -floo_req_t router_16_11_to_router_17_11_req; -floo_rsp_t router_17_11_to_router_16_11_rsp; - -floo_req_t router_16_11_to_magia_tile_ni_16_11_req; -floo_rsp_t magia_tile_ni_16_11_to_router_16_11_rsp; - -floo_req_t router_16_12_to_router_15_12_req; -floo_rsp_t router_15_12_to_router_16_12_rsp; - -floo_req_t router_16_12_to_router_16_11_req; -floo_rsp_t router_16_11_to_router_16_12_rsp; - -floo_req_t router_16_12_to_router_16_13_req; -floo_rsp_t router_16_13_to_router_16_12_rsp; - -floo_req_t router_16_12_to_router_17_12_req; -floo_rsp_t router_17_12_to_router_16_12_rsp; - -floo_req_t router_16_12_to_magia_tile_ni_16_12_req; -floo_rsp_t magia_tile_ni_16_12_to_router_16_12_rsp; - -floo_req_t router_16_13_to_router_15_13_req; -floo_rsp_t router_15_13_to_router_16_13_rsp; - -floo_req_t router_16_13_to_router_16_12_req; -floo_rsp_t router_16_12_to_router_16_13_rsp; - -floo_req_t router_16_13_to_router_16_14_req; -floo_rsp_t router_16_14_to_router_16_13_rsp; - -floo_req_t router_16_13_to_router_17_13_req; -floo_rsp_t router_17_13_to_router_16_13_rsp; - -floo_req_t router_16_13_to_magia_tile_ni_16_13_req; -floo_rsp_t magia_tile_ni_16_13_to_router_16_13_rsp; - -floo_req_t router_16_14_to_router_15_14_req; -floo_rsp_t router_15_14_to_router_16_14_rsp; - -floo_req_t router_16_14_to_router_16_13_req; -floo_rsp_t router_16_13_to_router_16_14_rsp; - -floo_req_t router_16_14_to_router_16_15_req; -floo_rsp_t router_16_15_to_router_16_14_rsp; - -floo_req_t router_16_14_to_router_17_14_req; -floo_rsp_t router_17_14_to_router_16_14_rsp; - -floo_req_t router_16_14_to_magia_tile_ni_16_14_req; -floo_rsp_t magia_tile_ni_16_14_to_router_16_14_rsp; - -floo_req_t router_16_15_to_router_15_15_req; -floo_rsp_t router_15_15_to_router_16_15_rsp; - -floo_req_t router_16_15_to_router_16_14_req; -floo_rsp_t router_16_14_to_router_16_15_rsp; - -floo_req_t router_16_15_to_router_16_16_req; -floo_rsp_t router_16_16_to_router_16_15_rsp; - -floo_req_t router_16_15_to_router_17_15_req; -floo_rsp_t router_17_15_to_router_16_15_rsp; - -floo_req_t router_16_15_to_magia_tile_ni_16_15_req; -floo_rsp_t magia_tile_ni_16_15_to_router_16_15_rsp; - -floo_req_t router_16_16_to_router_15_16_req; -floo_rsp_t router_15_16_to_router_16_16_rsp; - -floo_req_t router_16_16_to_router_16_15_req; -floo_rsp_t router_16_15_to_router_16_16_rsp; - -floo_req_t router_16_16_to_router_16_17_req; -floo_rsp_t router_16_17_to_router_16_16_rsp; - -floo_req_t router_16_16_to_router_17_16_req; -floo_rsp_t router_17_16_to_router_16_16_rsp; - -floo_req_t router_16_16_to_magia_tile_ni_16_16_req; -floo_rsp_t magia_tile_ni_16_16_to_router_16_16_rsp; - -floo_req_t router_16_17_to_router_15_17_req; -floo_rsp_t router_15_17_to_router_16_17_rsp; - -floo_req_t router_16_17_to_router_16_16_req; -floo_rsp_t router_16_16_to_router_16_17_rsp; - -floo_req_t router_16_17_to_router_16_18_req; -floo_rsp_t router_16_18_to_router_16_17_rsp; - -floo_req_t router_16_17_to_router_17_17_req; -floo_rsp_t router_17_17_to_router_16_17_rsp; - -floo_req_t router_16_17_to_magia_tile_ni_16_17_req; -floo_rsp_t magia_tile_ni_16_17_to_router_16_17_rsp; - -floo_req_t router_16_18_to_router_15_18_req; -floo_rsp_t router_15_18_to_router_16_18_rsp; - -floo_req_t router_16_18_to_router_16_17_req; -floo_rsp_t router_16_17_to_router_16_18_rsp; - -floo_req_t router_16_18_to_router_16_19_req; -floo_rsp_t router_16_19_to_router_16_18_rsp; - -floo_req_t router_16_18_to_router_17_18_req; -floo_rsp_t router_17_18_to_router_16_18_rsp; - -floo_req_t router_16_18_to_magia_tile_ni_16_18_req; -floo_rsp_t magia_tile_ni_16_18_to_router_16_18_rsp; - -floo_req_t router_16_19_to_router_15_19_req; -floo_rsp_t router_15_19_to_router_16_19_rsp; - -floo_req_t router_16_19_to_router_16_18_req; -floo_rsp_t router_16_18_to_router_16_19_rsp; - -floo_req_t router_16_19_to_router_16_20_req; -floo_rsp_t router_16_20_to_router_16_19_rsp; - -floo_req_t router_16_19_to_router_17_19_req; -floo_rsp_t router_17_19_to_router_16_19_rsp; - -floo_req_t router_16_19_to_magia_tile_ni_16_19_req; -floo_rsp_t magia_tile_ni_16_19_to_router_16_19_rsp; - -floo_req_t router_16_20_to_router_15_20_req; -floo_rsp_t router_15_20_to_router_16_20_rsp; - -floo_req_t router_16_20_to_router_16_19_req; -floo_rsp_t router_16_19_to_router_16_20_rsp; - -floo_req_t router_16_20_to_router_16_21_req; -floo_rsp_t router_16_21_to_router_16_20_rsp; - -floo_req_t router_16_20_to_router_17_20_req; -floo_rsp_t router_17_20_to_router_16_20_rsp; - -floo_req_t router_16_20_to_magia_tile_ni_16_20_req; -floo_rsp_t magia_tile_ni_16_20_to_router_16_20_rsp; - -floo_req_t router_16_21_to_router_15_21_req; -floo_rsp_t router_15_21_to_router_16_21_rsp; - -floo_req_t router_16_21_to_router_16_20_req; -floo_rsp_t router_16_20_to_router_16_21_rsp; - -floo_req_t router_16_21_to_router_16_22_req; -floo_rsp_t router_16_22_to_router_16_21_rsp; - -floo_req_t router_16_21_to_router_17_21_req; -floo_rsp_t router_17_21_to_router_16_21_rsp; - -floo_req_t router_16_21_to_magia_tile_ni_16_21_req; -floo_rsp_t magia_tile_ni_16_21_to_router_16_21_rsp; - -floo_req_t router_16_22_to_router_15_22_req; -floo_rsp_t router_15_22_to_router_16_22_rsp; - -floo_req_t router_16_22_to_router_16_21_req; -floo_rsp_t router_16_21_to_router_16_22_rsp; - -floo_req_t router_16_22_to_router_16_23_req; -floo_rsp_t router_16_23_to_router_16_22_rsp; - -floo_req_t router_16_22_to_router_17_22_req; -floo_rsp_t router_17_22_to_router_16_22_rsp; - -floo_req_t router_16_22_to_magia_tile_ni_16_22_req; -floo_rsp_t magia_tile_ni_16_22_to_router_16_22_rsp; - -floo_req_t router_16_23_to_router_15_23_req; -floo_rsp_t router_15_23_to_router_16_23_rsp; - -floo_req_t router_16_23_to_router_16_22_req; -floo_rsp_t router_16_22_to_router_16_23_rsp; - -floo_req_t router_16_23_to_router_16_24_req; -floo_rsp_t router_16_24_to_router_16_23_rsp; - -floo_req_t router_16_23_to_router_17_23_req; -floo_rsp_t router_17_23_to_router_16_23_rsp; - -floo_req_t router_16_23_to_magia_tile_ni_16_23_req; -floo_rsp_t magia_tile_ni_16_23_to_router_16_23_rsp; - -floo_req_t router_16_24_to_router_15_24_req; -floo_rsp_t router_15_24_to_router_16_24_rsp; - -floo_req_t router_16_24_to_router_16_23_req; -floo_rsp_t router_16_23_to_router_16_24_rsp; - -floo_req_t router_16_24_to_router_16_25_req; -floo_rsp_t router_16_25_to_router_16_24_rsp; - -floo_req_t router_16_24_to_router_17_24_req; -floo_rsp_t router_17_24_to_router_16_24_rsp; - -floo_req_t router_16_24_to_magia_tile_ni_16_24_req; -floo_rsp_t magia_tile_ni_16_24_to_router_16_24_rsp; - -floo_req_t router_16_25_to_router_15_25_req; -floo_rsp_t router_15_25_to_router_16_25_rsp; - -floo_req_t router_16_25_to_router_16_24_req; -floo_rsp_t router_16_24_to_router_16_25_rsp; - -floo_req_t router_16_25_to_router_16_26_req; -floo_rsp_t router_16_26_to_router_16_25_rsp; - -floo_req_t router_16_25_to_router_17_25_req; -floo_rsp_t router_17_25_to_router_16_25_rsp; - -floo_req_t router_16_25_to_magia_tile_ni_16_25_req; -floo_rsp_t magia_tile_ni_16_25_to_router_16_25_rsp; - -floo_req_t router_16_26_to_router_15_26_req; -floo_rsp_t router_15_26_to_router_16_26_rsp; - -floo_req_t router_16_26_to_router_16_25_req; -floo_rsp_t router_16_25_to_router_16_26_rsp; - -floo_req_t router_16_26_to_router_16_27_req; -floo_rsp_t router_16_27_to_router_16_26_rsp; - -floo_req_t router_16_26_to_router_17_26_req; -floo_rsp_t router_17_26_to_router_16_26_rsp; - -floo_req_t router_16_26_to_magia_tile_ni_16_26_req; -floo_rsp_t magia_tile_ni_16_26_to_router_16_26_rsp; - -floo_req_t router_16_27_to_router_15_27_req; -floo_rsp_t router_15_27_to_router_16_27_rsp; - -floo_req_t router_16_27_to_router_16_26_req; -floo_rsp_t router_16_26_to_router_16_27_rsp; - -floo_req_t router_16_27_to_router_16_28_req; -floo_rsp_t router_16_28_to_router_16_27_rsp; - -floo_req_t router_16_27_to_router_17_27_req; -floo_rsp_t router_17_27_to_router_16_27_rsp; - -floo_req_t router_16_27_to_magia_tile_ni_16_27_req; -floo_rsp_t magia_tile_ni_16_27_to_router_16_27_rsp; - -floo_req_t router_16_28_to_router_15_28_req; -floo_rsp_t router_15_28_to_router_16_28_rsp; - -floo_req_t router_16_28_to_router_16_27_req; -floo_rsp_t router_16_27_to_router_16_28_rsp; - -floo_req_t router_16_28_to_router_16_29_req; -floo_rsp_t router_16_29_to_router_16_28_rsp; - -floo_req_t router_16_28_to_router_17_28_req; -floo_rsp_t router_17_28_to_router_16_28_rsp; - -floo_req_t router_16_28_to_magia_tile_ni_16_28_req; -floo_rsp_t magia_tile_ni_16_28_to_router_16_28_rsp; - -floo_req_t router_16_29_to_router_15_29_req; -floo_rsp_t router_15_29_to_router_16_29_rsp; - -floo_req_t router_16_29_to_router_16_28_req; -floo_rsp_t router_16_28_to_router_16_29_rsp; - -floo_req_t router_16_29_to_router_16_30_req; -floo_rsp_t router_16_30_to_router_16_29_rsp; - -floo_req_t router_16_29_to_router_17_29_req; -floo_rsp_t router_17_29_to_router_16_29_rsp; - -floo_req_t router_16_29_to_magia_tile_ni_16_29_req; -floo_rsp_t magia_tile_ni_16_29_to_router_16_29_rsp; - -floo_req_t router_16_30_to_router_15_30_req; -floo_rsp_t router_15_30_to_router_16_30_rsp; - -floo_req_t router_16_30_to_router_16_29_req; -floo_rsp_t router_16_29_to_router_16_30_rsp; - -floo_req_t router_16_30_to_router_16_31_req; -floo_rsp_t router_16_31_to_router_16_30_rsp; - -floo_req_t router_16_30_to_router_17_30_req; -floo_rsp_t router_17_30_to_router_16_30_rsp; - -floo_req_t router_16_30_to_magia_tile_ni_16_30_req; -floo_rsp_t magia_tile_ni_16_30_to_router_16_30_rsp; - -floo_req_t router_16_31_to_router_15_31_req; -floo_rsp_t router_15_31_to_router_16_31_rsp; - -floo_req_t router_16_31_to_router_16_30_req; -floo_rsp_t router_16_30_to_router_16_31_rsp; - -floo_req_t router_16_31_to_router_17_31_req; -floo_rsp_t router_17_31_to_router_16_31_rsp; - -floo_req_t router_16_31_to_magia_tile_ni_16_31_req; -floo_rsp_t magia_tile_ni_16_31_to_router_16_31_rsp; - -floo_req_t router_17_0_to_router_16_0_req; -floo_rsp_t router_16_0_to_router_17_0_rsp; - -floo_req_t router_17_0_to_router_17_1_req; -floo_rsp_t router_17_1_to_router_17_0_rsp; - -floo_req_t router_17_0_to_router_18_0_req; -floo_rsp_t router_18_0_to_router_17_0_rsp; - -floo_req_t router_17_0_to_magia_tile_ni_17_0_req; -floo_rsp_t magia_tile_ni_17_0_to_router_17_0_rsp; - -floo_req_t router_17_1_to_router_16_1_req; -floo_rsp_t router_16_1_to_router_17_1_rsp; - -floo_req_t router_17_1_to_router_17_0_req; -floo_rsp_t router_17_0_to_router_17_1_rsp; - -floo_req_t router_17_1_to_router_17_2_req; -floo_rsp_t router_17_2_to_router_17_1_rsp; - -floo_req_t router_17_1_to_router_18_1_req; -floo_rsp_t router_18_1_to_router_17_1_rsp; - -floo_req_t router_17_1_to_magia_tile_ni_17_1_req; -floo_rsp_t magia_tile_ni_17_1_to_router_17_1_rsp; - -floo_req_t router_17_2_to_router_16_2_req; -floo_rsp_t router_16_2_to_router_17_2_rsp; - -floo_req_t router_17_2_to_router_17_1_req; -floo_rsp_t router_17_1_to_router_17_2_rsp; - -floo_req_t router_17_2_to_router_17_3_req; -floo_rsp_t router_17_3_to_router_17_2_rsp; - -floo_req_t router_17_2_to_router_18_2_req; -floo_rsp_t router_18_2_to_router_17_2_rsp; - -floo_req_t router_17_2_to_magia_tile_ni_17_2_req; -floo_rsp_t magia_tile_ni_17_2_to_router_17_2_rsp; - -floo_req_t router_17_3_to_router_16_3_req; -floo_rsp_t router_16_3_to_router_17_3_rsp; - -floo_req_t router_17_3_to_router_17_2_req; -floo_rsp_t router_17_2_to_router_17_3_rsp; - -floo_req_t router_17_3_to_router_17_4_req; -floo_rsp_t router_17_4_to_router_17_3_rsp; - -floo_req_t router_17_3_to_router_18_3_req; -floo_rsp_t router_18_3_to_router_17_3_rsp; - -floo_req_t router_17_3_to_magia_tile_ni_17_3_req; -floo_rsp_t magia_tile_ni_17_3_to_router_17_3_rsp; - -floo_req_t router_17_4_to_router_16_4_req; -floo_rsp_t router_16_4_to_router_17_4_rsp; - -floo_req_t router_17_4_to_router_17_3_req; -floo_rsp_t router_17_3_to_router_17_4_rsp; - -floo_req_t router_17_4_to_router_17_5_req; -floo_rsp_t router_17_5_to_router_17_4_rsp; - -floo_req_t router_17_4_to_router_18_4_req; -floo_rsp_t router_18_4_to_router_17_4_rsp; - -floo_req_t router_17_4_to_magia_tile_ni_17_4_req; -floo_rsp_t magia_tile_ni_17_4_to_router_17_4_rsp; - -floo_req_t router_17_5_to_router_16_5_req; -floo_rsp_t router_16_5_to_router_17_5_rsp; - -floo_req_t router_17_5_to_router_17_4_req; -floo_rsp_t router_17_4_to_router_17_5_rsp; - -floo_req_t router_17_5_to_router_17_6_req; -floo_rsp_t router_17_6_to_router_17_5_rsp; - -floo_req_t router_17_5_to_router_18_5_req; -floo_rsp_t router_18_5_to_router_17_5_rsp; - -floo_req_t router_17_5_to_magia_tile_ni_17_5_req; -floo_rsp_t magia_tile_ni_17_5_to_router_17_5_rsp; - -floo_req_t router_17_6_to_router_16_6_req; -floo_rsp_t router_16_6_to_router_17_6_rsp; - -floo_req_t router_17_6_to_router_17_5_req; -floo_rsp_t router_17_5_to_router_17_6_rsp; - -floo_req_t router_17_6_to_router_17_7_req; -floo_rsp_t router_17_7_to_router_17_6_rsp; - -floo_req_t router_17_6_to_router_18_6_req; -floo_rsp_t router_18_6_to_router_17_6_rsp; - -floo_req_t router_17_6_to_magia_tile_ni_17_6_req; -floo_rsp_t magia_tile_ni_17_6_to_router_17_6_rsp; - -floo_req_t router_17_7_to_router_16_7_req; -floo_rsp_t router_16_7_to_router_17_7_rsp; - -floo_req_t router_17_7_to_router_17_6_req; -floo_rsp_t router_17_6_to_router_17_7_rsp; - -floo_req_t router_17_7_to_router_17_8_req; -floo_rsp_t router_17_8_to_router_17_7_rsp; - -floo_req_t router_17_7_to_router_18_7_req; -floo_rsp_t router_18_7_to_router_17_7_rsp; - -floo_req_t router_17_7_to_magia_tile_ni_17_7_req; -floo_rsp_t magia_tile_ni_17_7_to_router_17_7_rsp; - -floo_req_t router_17_8_to_router_16_8_req; -floo_rsp_t router_16_8_to_router_17_8_rsp; - -floo_req_t router_17_8_to_router_17_7_req; -floo_rsp_t router_17_7_to_router_17_8_rsp; - -floo_req_t router_17_8_to_router_17_9_req; -floo_rsp_t router_17_9_to_router_17_8_rsp; - -floo_req_t router_17_8_to_router_18_8_req; -floo_rsp_t router_18_8_to_router_17_8_rsp; - -floo_req_t router_17_8_to_magia_tile_ni_17_8_req; -floo_rsp_t magia_tile_ni_17_8_to_router_17_8_rsp; - -floo_req_t router_17_9_to_router_16_9_req; -floo_rsp_t router_16_9_to_router_17_9_rsp; - -floo_req_t router_17_9_to_router_17_8_req; -floo_rsp_t router_17_8_to_router_17_9_rsp; - -floo_req_t router_17_9_to_router_17_10_req; -floo_rsp_t router_17_10_to_router_17_9_rsp; - -floo_req_t router_17_9_to_router_18_9_req; -floo_rsp_t router_18_9_to_router_17_9_rsp; - -floo_req_t router_17_9_to_magia_tile_ni_17_9_req; -floo_rsp_t magia_tile_ni_17_9_to_router_17_9_rsp; - -floo_req_t router_17_10_to_router_16_10_req; -floo_rsp_t router_16_10_to_router_17_10_rsp; - -floo_req_t router_17_10_to_router_17_9_req; -floo_rsp_t router_17_9_to_router_17_10_rsp; - -floo_req_t router_17_10_to_router_17_11_req; -floo_rsp_t router_17_11_to_router_17_10_rsp; - -floo_req_t router_17_10_to_router_18_10_req; -floo_rsp_t router_18_10_to_router_17_10_rsp; - -floo_req_t router_17_10_to_magia_tile_ni_17_10_req; -floo_rsp_t magia_tile_ni_17_10_to_router_17_10_rsp; - -floo_req_t router_17_11_to_router_16_11_req; -floo_rsp_t router_16_11_to_router_17_11_rsp; - -floo_req_t router_17_11_to_router_17_10_req; -floo_rsp_t router_17_10_to_router_17_11_rsp; - -floo_req_t router_17_11_to_router_17_12_req; -floo_rsp_t router_17_12_to_router_17_11_rsp; - -floo_req_t router_17_11_to_router_18_11_req; -floo_rsp_t router_18_11_to_router_17_11_rsp; - -floo_req_t router_17_11_to_magia_tile_ni_17_11_req; -floo_rsp_t magia_tile_ni_17_11_to_router_17_11_rsp; - -floo_req_t router_17_12_to_router_16_12_req; -floo_rsp_t router_16_12_to_router_17_12_rsp; - -floo_req_t router_17_12_to_router_17_11_req; -floo_rsp_t router_17_11_to_router_17_12_rsp; - -floo_req_t router_17_12_to_router_17_13_req; -floo_rsp_t router_17_13_to_router_17_12_rsp; - -floo_req_t router_17_12_to_router_18_12_req; -floo_rsp_t router_18_12_to_router_17_12_rsp; - -floo_req_t router_17_12_to_magia_tile_ni_17_12_req; -floo_rsp_t magia_tile_ni_17_12_to_router_17_12_rsp; - -floo_req_t router_17_13_to_router_16_13_req; -floo_rsp_t router_16_13_to_router_17_13_rsp; - -floo_req_t router_17_13_to_router_17_12_req; -floo_rsp_t router_17_12_to_router_17_13_rsp; - -floo_req_t router_17_13_to_router_17_14_req; -floo_rsp_t router_17_14_to_router_17_13_rsp; - -floo_req_t router_17_13_to_router_18_13_req; -floo_rsp_t router_18_13_to_router_17_13_rsp; - -floo_req_t router_17_13_to_magia_tile_ni_17_13_req; -floo_rsp_t magia_tile_ni_17_13_to_router_17_13_rsp; - -floo_req_t router_17_14_to_router_16_14_req; -floo_rsp_t router_16_14_to_router_17_14_rsp; - -floo_req_t router_17_14_to_router_17_13_req; -floo_rsp_t router_17_13_to_router_17_14_rsp; - -floo_req_t router_17_14_to_router_17_15_req; -floo_rsp_t router_17_15_to_router_17_14_rsp; - -floo_req_t router_17_14_to_router_18_14_req; -floo_rsp_t router_18_14_to_router_17_14_rsp; - -floo_req_t router_17_14_to_magia_tile_ni_17_14_req; -floo_rsp_t magia_tile_ni_17_14_to_router_17_14_rsp; - -floo_req_t router_17_15_to_router_16_15_req; -floo_rsp_t router_16_15_to_router_17_15_rsp; - -floo_req_t router_17_15_to_router_17_14_req; -floo_rsp_t router_17_14_to_router_17_15_rsp; - -floo_req_t router_17_15_to_router_17_16_req; -floo_rsp_t router_17_16_to_router_17_15_rsp; - -floo_req_t router_17_15_to_router_18_15_req; -floo_rsp_t router_18_15_to_router_17_15_rsp; - -floo_req_t router_17_15_to_magia_tile_ni_17_15_req; -floo_rsp_t magia_tile_ni_17_15_to_router_17_15_rsp; - -floo_req_t router_17_16_to_router_16_16_req; -floo_rsp_t router_16_16_to_router_17_16_rsp; - -floo_req_t router_17_16_to_router_17_15_req; -floo_rsp_t router_17_15_to_router_17_16_rsp; - -floo_req_t router_17_16_to_router_17_17_req; -floo_rsp_t router_17_17_to_router_17_16_rsp; - -floo_req_t router_17_16_to_router_18_16_req; -floo_rsp_t router_18_16_to_router_17_16_rsp; - -floo_req_t router_17_16_to_magia_tile_ni_17_16_req; -floo_rsp_t magia_tile_ni_17_16_to_router_17_16_rsp; - -floo_req_t router_17_17_to_router_16_17_req; -floo_rsp_t router_16_17_to_router_17_17_rsp; - -floo_req_t router_17_17_to_router_17_16_req; -floo_rsp_t router_17_16_to_router_17_17_rsp; - -floo_req_t router_17_17_to_router_17_18_req; -floo_rsp_t router_17_18_to_router_17_17_rsp; - -floo_req_t router_17_17_to_router_18_17_req; -floo_rsp_t router_18_17_to_router_17_17_rsp; - -floo_req_t router_17_17_to_magia_tile_ni_17_17_req; -floo_rsp_t magia_tile_ni_17_17_to_router_17_17_rsp; - -floo_req_t router_17_18_to_router_16_18_req; -floo_rsp_t router_16_18_to_router_17_18_rsp; - -floo_req_t router_17_18_to_router_17_17_req; -floo_rsp_t router_17_17_to_router_17_18_rsp; - -floo_req_t router_17_18_to_router_17_19_req; -floo_rsp_t router_17_19_to_router_17_18_rsp; - -floo_req_t router_17_18_to_router_18_18_req; -floo_rsp_t router_18_18_to_router_17_18_rsp; - -floo_req_t router_17_18_to_magia_tile_ni_17_18_req; -floo_rsp_t magia_tile_ni_17_18_to_router_17_18_rsp; - -floo_req_t router_17_19_to_router_16_19_req; -floo_rsp_t router_16_19_to_router_17_19_rsp; - -floo_req_t router_17_19_to_router_17_18_req; -floo_rsp_t router_17_18_to_router_17_19_rsp; - -floo_req_t router_17_19_to_router_17_20_req; -floo_rsp_t router_17_20_to_router_17_19_rsp; - -floo_req_t router_17_19_to_router_18_19_req; -floo_rsp_t router_18_19_to_router_17_19_rsp; - -floo_req_t router_17_19_to_magia_tile_ni_17_19_req; -floo_rsp_t magia_tile_ni_17_19_to_router_17_19_rsp; - -floo_req_t router_17_20_to_router_16_20_req; -floo_rsp_t router_16_20_to_router_17_20_rsp; - -floo_req_t router_17_20_to_router_17_19_req; -floo_rsp_t router_17_19_to_router_17_20_rsp; - -floo_req_t router_17_20_to_router_17_21_req; -floo_rsp_t router_17_21_to_router_17_20_rsp; - -floo_req_t router_17_20_to_router_18_20_req; -floo_rsp_t router_18_20_to_router_17_20_rsp; - -floo_req_t router_17_20_to_magia_tile_ni_17_20_req; -floo_rsp_t magia_tile_ni_17_20_to_router_17_20_rsp; - -floo_req_t router_17_21_to_router_16_21_req; -floo_rsp_t router_16_21_to_router_17_21_rsp; - -floo_req_t router_17_21_to_router_17_20_req; -floo_rsp_t router_17_20_to_router_17_21_rsp; - -floo_req_t router_17_21_to_router_17_22_req; -floo_rsp_t router_17_22_to_router_17_21_rsp; - -floo_req_t router_17_21_to_router_18_21_req; -floo_rsp_t router_18_21_to_router_17_21_rsp; - -floo_req_t router_17_21_to_magia_tile_ni_17_21_req; -floo_rsp_t magia_tile_ni_17_21_to_router_17_21_rsp; - -floo_req_t router_17_22_to_router_16_22_req; -floo_rsp_t router_16_22_to_router_17_22_rsp; - -floo_req_t router_17_22_to_router_17_21_req; -floo_rsp_t router_17_21_to_router_17_22_rsp; - -floo_req_t router_17_22_to_router_17_23_req; -floo_rsp_t router_17_23_to_router_17_22_rsp; - -floo_req_t router_17_22_to_router_18_22_req; -floo_rsp_t router_18_22_to_router_17_22_rsp; - -floo_req_t router_17_22_to_magia_tile_ni_17_22_req; -floo_rsp_t magia_tile_ni_17_22_to_router_17_22_rsp; - -floo_req_t router_17_23_to_router_16_23_req; -floo_rsp_t router_16_23_to_router_17_23_rsp; - -floo_req_t router_17_23_to_router_17_22_req; -floo_rsp_t router_17_22_to_router_17_23_rsp; - -floo_req_t router_17_23_to_router_17_24_req; -floo_rsp_t router_17_24_to_router_17_23_rsp; - -floo_req_t router_17_23_to_router_18_23_req; -floo_rsp_t router_18_23_to_router_17_23_rsp; - -floo_req_t router_17_23_to_magia_tile_ni_17_23_req; -floo_rsp_t magia_tile_ni_17_23_to_router_17_23_rsp; - -floo_req_t router_17_24_to_router_16_24_req; -floo_rsp_t router_16_24_to_router_17_24_rsp; - -floo_req_t router_17_24_to_router_17_23_req; -floo_rsp_t router_17_23_to_router_17_24_rsp; - -floo_req_t router_17_24_to_router_17_25_req; -floo_rsp_t router_17_25_to_router_17_24_rsp; - -floo_req_t router_17_24_to_router_18_24_req; -floo_rsp_t router_18_24_to_router_17_24_rsp; - -floo_req_t router_17_24_to_magia_tile_ni_17_24_req; -floo_rsp_t magia_tile_ni_17_24_to_router_17_24_rsp; - -floo_req_t router_17_25_to_router_16_25_req; -floo_rsp_t router_16_25_to_router_17_25_rsp; - -floo_req_t router_17_25_to_router_17_24_req; -floo_rsp_t router_17_24_to_router_17_25_rsp; - -floo_req_t router_17_25_to_router_17_26_req; -floo_rsp_t router_17_26_to_router_17_25_rsp; - -floo_req_t router_17_25_to_router_18_25_req; -floo_rsp_t router_18_25_to_router_17_25_rsp; - -floo_req_t router_17_25_to_magia_tile_ni_17_25_req; -floo_rsp_t magia_tile_ni_17_25_to_router_17_25_rsp; - -floo_req_t router_17_26_to_router_16_26_req; -floo_rsp_t router_16_26_to_router_17_26_rsp; - -floo_req_t router_17_26_to_router_17_25_req; -floo_rsp_t router_17_25_to_router_17_26_rsp; - -floo_req_t router_17_26_to_router_17_27_req; -floo_rsp_t router_17_27_to_router_17_26_rsp; - -floo_req_t router_17_26_to_router_18_26_req; -floo_rsp_t router_18_26_to_router_17_26_rsp; - -floo_req_t router_17_26_to_magia_tile_ni_17_26_req; -floo_rsp_t magia_tile_ni_17_26_to_router_17_26_rsp; - -floo_req_t router_17_27_to_router_16_27_req; -floo_rsp_t router_16_27_to_router_17_27_rsp; - -floo_req_t router_17_27_to_router_17_26_req; -floo_rsp_t router_17_26_to_router_17_27_rsp; - -floo_req_t router_17_27_to_router_17_28_req; -floo_rsp_t router_17_28_to_router_17_27_rsp; - -floo_req_t router_17_27_to_router_18_27_req; -floo_rsp_t router_18_27_to_router_17_27_rsp; - -floo_req_t router_17_27_to_magia_tile_ni_17_27_req; -floo_rsp_t magia_tile_ni_17_27_to_router_17_27_rsp; - -floo_req_t router_17_28_to_router_16_28_req; -floo_rsp_t router_16_28_to_router_17_28_rsp; - -floo_req_t router_17_28_to_router_17_27_req; -floo_rsp_t router_17_27_to_router_17_28_rsp; - -floo_req_t router_17_28_to_router_17_29_req; -floo_rsp_t router_17_29_to_router_17_28_rsp; - -floo_req_t router_17_28_to_router_18_28_req; -floo_rsp_t router_18_28_to_router_17_28_rsp; - -floo_req_t router_17_28_to_magia_tile_ni_17_28_req; -floo_rsp_t magia_tile_ni_17_28_to_router_17_28_rsp; - -floo_req_t router_17_29_to_router_16_29_req; -floo_rsp_t router_16_29_to_router_17_29_rsp; - -floo_req_t router_17_29_to_router_17_28_req; -floo_rsp_t router_17_28_to_router_17_29_rsp; - -floo_req_t router_17_29_to_router_17_30_req; -floo_rsp_t router_17_30_to_router_17_29_rsp; - -floo_req_t router_17_29_to_router_18_29_req; -floo_rsp_t router_18_29_to_router_17_29_rsp; - -floo_req_t router_17_29_to_magia_tile_ni_17_29_req; -floo_rsp_t magia_tile_ni_17_29_to_router_17_29_rsp; - -floo_req_t router_17_30_to_router_16_30_req; -floo_rsp_t router_16_30_to_router_17_30_rsp; - -floo_req_t router_17_30_to_router_17_29_req; -floo_rsp_t router_17_29_to_router_17_30_rsp; - -floo_req_t router_17_30_to_router_17_31_req; -floo_rsp_t router_17_31_to_router_17_30_rsp; - -floo_req_t router_17_30_to_router_18_30_req; -floo_rsp_t router_18_30_to_router_17_30_rsp; - -floo_req_t router_17_30_to_magia_tile_ni_17_30_req; -floo_rsp_t magia_tile_ni_17_30_to_router_17_30_rsp; - -floo_req_t router_17_31_to_router_16_31_req; -floo_rsp_t router_16_31_to_router_17_31_rsp; - -floo_req_t router_17_31_to_router_17_30_req; -floo_rsp_t router_17_30_to_router_17_31_rsp; - -floo_req_t router_17_31_to_router_18_31_req; -floo_rsp_t router_18_31_to_router_17_31_rsp; - -floo_req_t router_17_31_to_magia_tile_ni_17_31_req; -floo_rsp_t magia_tile_ni_17_31_to_router_17_31_rsp; - -floo_req_t router_18_0_to_router_17_0_req; -floo_rsp_t router_17_0_to_router_18_0_rsp; - -floo_req_t router_18_0_to_router_18_1_req; -floo_rsp_t router_18_1_to_router_18_0_rsp; - -floo_req_t router_18_0_to_router_19_0_req; -floo_rsp_t router_19_0_to_router_18_0_rsp; - -floo_req_t router_18_0_to_magia_tile_ni_18_0_req; -floo_rsp_t magia_tile_ni_18_0_to_router_18_0_rsp; - -floo_req_t router_18_1_to_router_17_1_req; -floo_rsp_t router_17_1_to_router_18_1_rsp; - -floo_req_t router_18_1_to_router_18_0_req; -floo_rsp_t router_18_0_to_router_18_1_rsp; - -floo_req_t router_18_1_to_router_18_2_req; -floo_rsp_t router_18_2_to_router_18_1_rsp; - -floo_req_t router_18_1_to_router_19_1_req; -floo_rsp_t router_19_1_to_router_18_1_rsp; - -floo_req_t router_18_1_to_magia_tile_ni_18_1_req; -floo_rsp_t magia_tile_ni_18_1_to_router_18_1_rsp; - -floo_req_t router_18_2_to_router_17_2_req; -floo_rsp_t router_17_2_to_router_18_2_rsp; - -floo_req_t router_18_2_to_router_18_1_req; -floo_rsp_t router_18_1_to_router_18_2_rsp; - -floo_req_t router_18_2_to_router_18_3_req; -floo_rsp_t router_18_3_to_router_18_2_rsp; - -floo_req_t router_18_2_to_router_19_2_req; -floo_rsp_t router_19_2_to_router_18_2_rsp; - -floo_req_t router_18_2_to_magia_tile_ni_18_2_req; -floo_rsp_t magia_tile_ni_18_2_to_router_18_2_rsp; - -floo_req_t router_18_3_to_router_17_3_req; -floo_rsp_t router_17_3_to_router_18_3_rsp; - -floo_req_t router_18_3_to_router_18_2_req; -floo_rsp_t router_18_2_to_router_18_3_rsp; - -floo_req_t router_18_3_to_router_18_4_req; -floo_rsp_t router_18_4_to_router_18_3_rsp; - -floo_req_t router_18_3_to_router_19_3_req; -floo_rsp_t router_19_3_to_router_18_3_rsp; - -floo_req_t router_18_3_to_magia_tile_ni_18_3_req; -floo_rsp_t magia_tile_ni_18_3_to_router_18_3_rsp; - -floo_req_t router_18_4_to_router_17_4_req; -floo_rsp_t router_17_4_to_router_18_4_rsp; - -floo_req_t router_18_4_to_router_18_3_req; -floo_rsp_t router_18_3_to_router_18_4_rsp; - -floo_req_t router_18_4_to_router_18_5_req; -floo_rsp_t router_18_5_to_router_18_4_rsp; - -floo_req_t router_18_4_to_router_19_4_req; -floo_rsp_t router_19_4_to_router_18_4_rsp; - -floo_req_t router_18_4_to_magia_tile_ni_18_4_req; -floo_rsp_t magia_tile_ni_18_4_to_router_18_4_rsp; - -floo_req_t router_18_5_to_router_17_5_req; -floo_rsp_t router_17_5_to_router_18_5_rsp; - -floo_req_t router_18_5_to_router_18_4_req; -floo_rsp_t router_18_4_to_router_18_5_rsp; - -floo_req_t router_18_5_to_router_18_6_req; -floo_rsp_t router_18_6_to_router_18_5_rsp; - -floo_req_t router_18_5_to_router_19_5_req; -floo_rsp_t router_19_5_to_router_18_5_rsp; - -floo_req_t router_18_5_to_magia_tile_ni_18_5_req; -floo_rsp_t magia_tile_ni_18_5_to_router_18_5_rsp; - -floo_req_t router_18_6_to_router_17_6_req; -floo_rsp_t router_17_6_to_router_18_6_rsp; - -floo_req_t router_18_6_to_router_18_5_req; -floo_rsp_t router_18_5_to_router_18_6_rsp; - -floo_req_t router_18_6_to_router_18_7_req; -floo_rsp_t router_18_7_to_router_18_6_rsp; - -floo_req_t router_18_6_to_router_19_6_req; -floo_rsp_t router_19_6_to_router_18_6_rsp; - -floo_req_t router_18_6_to_magia_tile_ni_18_6_req; -floo_rsp_t magia_tile_ni_18_6_to_router_18_6_rsp; - -floo_req_t router_18_7_to_router_17_7_req; -floo_rsp_t router_17_7_to_router_18_7_rsp; - -floo_req_t router_18_7_to_router_18_6_req; -floo_rsp_t router_18_6_to_router_18_7_rsp; - -floo_req_t router_18_7_to_router_18_8_req; -floo_rsp_t router_18_8_to_router_18_7_rsp; - -floo_req_t router_18_7_to_router_19_7_req; -floo_rsp_t router_19_7_to_router_18_7_rsp; - -floo_req_t router_18_7_to_magia_tile_ni_18_7_req; -floo_rsp_t magia_tile_ni_18_7_to_router_18_7_rsp; - -floo_req_t router_18_8_to_router_17_8_req; -floo_rsp_t router_17_8_to_router_18_8_rsp; - -floo_req_t router_18_8_to_router_18_7_req; -floo_rsp_t router_18_7_to_router_18_8_rsp; - -floo_req_t router_18_8_to_router_18_9_req; -floo_rsp_t router_18_9_to_router_18_8_rsp; - -floo_req_t router_18_8_to_router_19_8_req; -floo_rsp_t router_19_8_to_router_18_8_rsp; - -floo_req_t router_18_8_to_magia_tile_ni_18_8_req; -floo_rsp_t magia_tile_ni_18_8_to_router_18_8_rsp; - -floo_req_t router_18_9_to_router_17_9_req; -floo_rsp_t router_17_9_to_router_18_9_rsp; - -floo_req_t router_18_9_to_router_18_8_req; -floo_rsp_t router_18_8_to_router_18_9_rsp; - -floo_req_t router_18_9_to_router_18_10_req; -floo_rsp_t router_18_10_to_router_18_9_rsp; - -floo_req_t router_18_9_to_router_19_9_req; -floo_rsp_t router_19_9_to_router_18_9_rsp; - -floo_req_t router_18_9_to_magia_tile_ni_18_9_req; -floo_rsp_t magia_tile_ni_18_9_to_router_18_9_rsp; - -floo_req_t router_18_10_to_router_17_10_req; -floo_rsp_t router_17_10_to_router_18_10_rsp; - -floo_req_t router_18_10_to_router_18_9_req; -floo_rsp_t router_18_9_to_router_18_10_rsp; - -floo_req_t router_18_10_to_router_18_11_req; -floo_rsp_t router_18_11_to_router_18_10_rsp; - -floo_req_t router_18_10_to_router_19_10_req; -floo_rsp_t router_19_10_to_router_18_10_rsp; - -floo_req_t router_18_10_to_magia_tile_ni_18_10_req; -floo_rsp_t magia_tile_ni_18_10_to_router_18_10_rsp; - -floo_req_t router_18_11_to_router_17_11_req; -floo_rsp_t router_17_11_to_router_18_11_rsp; - -floo_req_t router_18_11_to_router_18_10_req; -floo_rsp_t router_18_10_to_router_18_11_rsp; - -floo_req_t router_18_11_to_router_18_12_req; -floo_rsp_t router_18_12_to_router_18_11_rsp; - -floo_req_t router_18_11_to_router_19_11_req; -floo_rsp_t router_19_11_to_router_18_11_rsp; - -floo_req_t router_18_11_to_magia_tile_ni_18_11_req; -floo_rsp_t magia_tile_ni_18_11_to_router_18_11_rsp; - -floo_req_t router_18_12_to_router_17_12_req; -floo_rsp_t router_17_12_to_router_18_12_rsp; - -floo_req_t router_18_12_to_router_18_11_req; -floo_rsp_t router_18_11_to_router_18_12_rsp; - -floo_req_t router_18_12_to_router_18_13_req; -floo_rsp_t router_18_13_to_router_18_12_rsp; - -floo_req_t router_18_12_to_router_19_12_req; -floo_rsp_t router_19_12_to_router_18_12_rsp; - -floo_req_t router_18_12_to_magia_tile_ni_18_12_req; -floo_rsp_t magia_tile_ni_18_12_to_router_18_12_rsp; - -floo_req_t router_18_13_to_router_17_13_req; -floo_rsp_t router_17_13_to_router_18_13_rsp; - -floo_req_t router_18_13_to_router_18_12_req; -floo_rsp_t router_18_12_to_router_18_13_rsp; - -floo_req_t router_18_13_to_router_18_14_req; -floo_rsp_t router_18_14_to_router_18_13_rsp; - -floo_req_t router_18_13_to_router_19_13_req; -floo_rsp_t router_19_13_to_router_18_13_rsp; - -floo_req_t router_18_13_to_magia_tile_ni_18_13_req; -floo_rsp_t magia_tile_ni_18_13_to_router_18_13_rsp; - -floo_req_t router_18_14_to_router_17_14_req; -floo_rsp_t router_17_14_to_router_18_14_rsp; - -floo_req_t router_18_14_to_router_18_13_req; -floo_rsp_t router_18_13_to_router_18_14_rsp; - -floo_req_t router_18_14_to_router_18_15_req; -floo_rsp_t router_18_15_to_router_18_14_rsp; - -floo_req_t router_18_14_to_router_19_14_req; -floo_rsp_t router_19_14_to_router_18_14_rsp; - -floo_req_t router_18_14_to_magia_tile_ni_18_14_req; -floo_rsp_t magia_tile_ni_18_14_to_router_18_14_rsp; - -floo_req_t router_18_15_to_router_17_15_req; -floo_rsp_t router_17_15_to_router_18_15_rsp; - -floo_req_t router_18_15_to_router_18_14_req; -floo_rsp_t router_18_14_to_router_18_15_rsp; - -floo_req_t router_18_15_to_router_18_16_req; -floo_rsp_t router_18_16_to_router_18_15_rsp; - -floo_req_t router_18_15_to_router_19_15_req; -floo_rsp_t router_19_15_to_router_18_15_rsp; - -floo_req_t router_18_15_to_magia_tile_ni_18_15_req; -floo_rsp_t magia_tile_ni_18_15_to_router_18_15_rsp; - -floo_req_t router_18_16_to_router_17_16_req; -floo_rsp_t router_17_16_to_router_18_16_rsp; - -floo_req_t router_18_16_to_router_18_15_req; -floo_rsp_t router_18_15_to_router_18_16_rsp; - -floo_req_t router_18_16_to_router_18_17_req; -floo_rsp_t router_18_17_to_router_18_16_rsp; - -floo_req_t router_18_16_to_router_19_16_req; -floo_rsp_t router_19_16_to_router_18_16_rsp; - -floo_req_t router_18_16_to_magia_tile_ni_18_16_req; -floo_rsp_t magia_tile_ni_18_16_to_router_18_16_rsp; - -floo_req_t router_18_17_to_router_17_17_req; -floo_rsp_t router_17_17_to_router_18_17_rsp; - -floo_req_t router_18_17_to_router_18_16_req; -floo_rsp_t router_18_16_to_router_18_17_rsp; - -floo_req_t router_18_17_to_router_18_18_req; -floo_rsp_t router_18_18_to_router_18_17_rsp; - -floo_req_t router_18_17_to_router_19_17_req; -floo_rsp_t router_19_17_to_router_18_17_rsp; - -floo_req_t router_18_17_to_magia_tile_ni_18_17_req; -floo_rsp_t magia_tile_ni_18_17_to_router_18_17_rsp; - -floo_req_t router_18_18_to_router_17_18_req; -floo_rsp_t router_17_18_to_router_18_18_rsp; - -floo_req_t router_18_18_to_router_18_17_req; -floo_rsp_t router_18_17_to_router_18_18_rsp; - -floo_req_t router_18_18_to_router_18_19_req; -floo_rsp_t router_18_19_to_router_18_18_rsp; - -floo_req_t router_18_18_to_router_19_18_req; -floo_rsp_t router_19_18_to_router_18_18_rsp; - -floo_req_t router_18_18_to_magia_tile_ni_18_18_req; -floo_rsp_t magia_tile_ni_18_18_to_router_18_18_rsp; - -floo_req_t router_18_19_to_router_17_19_req; -floo_rsp_t router_17_19_to_router_18_19_rsp; - -floo_req_t router_18_19_to_router_18_18_req; -floo_rsp_t router_18_18_to_router_18_19_rsp; - -floo_req_t router_18_19_to_router_18_20_req; -floo_rsp_t router_18_20_to_router_18_19_rsp; - -floo_req_t router_18_19_to_router_19_19_req; -floo_rsp_t router_19_19_to_router_18_19_rsp; - -floo_req_t router_18_19_to_magia_tile_ni_18_19_req; -floo_rsp_t magia_tile_ni_18_19_to_router_18_19_rsp; - -floo_req_t router_18_20_to_router_17_20_req; -floo_rsp_t router_17_20_to_router_18_20_rsp; - -floo_req_t router_18_20_to_router_18_19_req; -floo_rsp_t router_18_19_to_router_18_20_rsp; - -floo_req_t router_18_20_to_router_18_21_req; -floo_rsp_t router_18_21_to_router_18_20_rsp; - -floo_req_t router_18_20_to_router_19_20_req; -floo_rsp_t router_19_20_to_router_18_20_rsp; - -floo_req_t router_18_20_to_magia_tile_ni_18_20_req; -floo_rsp_t magia_tile_ni_18_20_to_router_18_20_rsp; - -floo_req_t router_18_21_to_router_17_21_req; -floo_rsp_t router_17_21_to_router_18_21_rsp; - -floo_req_t router_18_21_to_router_18_20_req; -floo_rsp_t router_18_20_to_router_18_21_rsp; - -floo_req_t router_18_21_to_router_18_22_req; -floo_rsp_t router_18_22_to_router_18_21_rsp; - -floo_req_t router_18_21_to_router_19_21_req; -floo_rsp_t router_19_21_to_router_18_21_rsp; - -floo_req_t router_18_21_to_magia_tile_ni_18_21_req; -floo_rsp_t magia_tile_ni_18_21_to_router_18_21_rsp; - -floo_req_t router_18_22_to_router_17_22_req; -floo_rsp_t router_17_22_to_router_18_22_rsp; - -floo_req_t router_18_22_to_router_18_21_req; -floo_rsp_t router_18_21_to_router_18_22_rsp; - -floo_req_t router_18_22_to_router_18_23_req; -floo_rsp_t router_18_23_to_router_18_22_rsp; - -floo_req_t router_18_22_to_router_19_22_req; -floo_rsp_t router_19_22_to_router_18_22_rsp; - -floo_req_t router_18_22_to_magia_tile_ni_18_22_req; -floo_rsp_t magia_tile_ni_18_22_to_router_18_22_rsp; - -floo_req_t router_18_23_to_router_17_23_req; -floo_rsp_t router_17_23_to_router_18_23_rsp; - -floo_req_t router_18_23_to_router_18_22_req; -floo_rsp_t router_18_22_to_router_18_23_rsp; - -floo_req_t router_18_23_to_router_18_24_req; -floo_rsp_t router_18_24_to_router_18_23_rsp; - -floo_req_t router_18_23_to_router_19_23_req; -floo_rsp_t router_19_23_to_router_18_23_rsp; - -floo_req_t router_18_23_to_magia_tile_ni_18_23_req; -floo_rsp_t magia_tile_ni_18_23_to_router_18_23_rsp; - -floo_req_t router_18_24_to_router_17_24_req; -floo_rsp_t router_17_24_to_router_18_24_rsp; - -floo_req_t router_18_24_to_router_18_23_req; -floo_rsp_t router_18_23_to_router_18_24_rsp; - -floo_req_t router_18_24_to_router_18_25_req; -floo_rsp_t router_18_25_to_router_18_24_rsp; - -floo_req_t router_18_24_to_router_19_24_req; -floo_rsp_t router_19_24_to_router_18_24_rsp; - -floo_req_t router_18_24_to_magia_tile_ni_18_24_req; -floo_rsp_t magia_tile_ni_18_24_to_router_18_24_rsp; - -floo_req_t router_18_25_to_router_17_25_req; -floo_rsp_t router_17_25_to_router_18_25_rsp; - -floo_req_t router_18_25_to_router_18_24_req; -floo_rsp_t router_18_24_to_router_18_25_rsp; - -floo_req_t router_18_25_to_router_18_26_req; -floo_rsp_t router_18_26_to_router_18_25_rsp; - -floo_req_t router_18_25_to_router_19_25_req; -floo_rsp_t router_19_25_to_router_18_25_rsp; - -floo_req_t router_18_25_to_magia_tile_ni_18_25_req; -floo_rsp_t magia_tile_ni_18_25_to_router_18_25_rsp; - -floo_req_t router_18_26_to_router_17_26_req; -floo_rsp_t router_17_26_to_router_18_26_rsp; - -floo_req_t router_18_26_to_router_18_25_req; -floo_rsp_t router_18_25_to_router_18_26_rsp; - -floo_req_t router_18_26_to_router_18_27_req; -floo_rsp_t router_18_27_to_router_18_26_rsp; - -floo_req_t router_18_26_to_router_19_26_req; -floo_rsp_t router_19_26_to_router_18_26_rsp; - -floo_req_t router_18_26_to_magia_tile_ni_18_26_req; -floo_rsp_t magia_tile_ni_18_26_to_router_18_26_rsp; - -floo_req_t router_18_27_to_router_17_27_req; -floo_rsp_t router_17_27_to_router_18_27_rsp; - -floo_req_t router_18_27_to_router_18_26_req; -floo_rsp_t router_18_26_to_router_18_27_rsp; - -floo_req_t router_18_27_to_router_18_28_req; -floo_rsp_t router_18_28_to_router_18_27_rsp; - -floo_req_t router_18_27_to_router_19_27_req; -floo_rsp_t router_19_27_to_router_18_27_rsp; - -floo_req_t router_18_27_to_magia_tile_ni_18_27_req; -floo_rsp_t magia_tile_ni_18_27_to_router_18_27_rsp; - -floo_req_t router_18_28_to_router_17_28_req; -floo_rsp_t router_17_28_to_router_18_28_rsp; - -floo_req_t router_18_28_to_router_18_27_req; -floo_rsp_t router_18_27_to_router_18_28_rsp; - -floo_req_t router_18_28_to_router_18_29_req; -floo_rsp_t router_18_29_to_router_18_28_rsp; - -floo_req_t router_18_28_to_router_19_28_req; -floo_rsp_t router_19_28_to_router_18_28_rsp; - -floo_req_t router_18_28_to_magia_tile_ni_18_28_req; -floo_rsp_t magia_tile_ni_18_28_to_router_18_28_rsp; - -floo_req_t router_18_29_to_router_17_29_req; -floo_rsp_t router_17_29_to_router_18_29_rsp; - -floo_req_t router_18_29_to_router_18_28_req; -floo_rsp_t router_18_28_to_router_18_29_rsp; - -floo_req_t router_18_29_to_router_18_30_req; -floo_rsp_t router_18_30_to_router_18_29_rsp; - -floo_req_t router_18_29_to_router_19_29_req; -floo_rsp_t router_19_29_to_router_18_29_rsp; - -floo_req_t router_18_29_to_magia_tile_ni_18_29_req; -floo_rsp_t magia_tile_ni_18_29_to_router_18_29_rsp; - -floo_req_t router_18_30_to_router_17_30_req; -floo_rsp_t router_17_30_to_router_18_30_rsp; - -floo_req_t router_18_30_to_router_18_29_req; -floo_rsp_t router_18_29_to_router_18_30_rsp; - -floo_req_t router_18_30_to_router_18_31_req; -floo_rsp_t router_18_31_to_router_18_30_rsp; - -floo_req_t router_18_30_to_router_19_30_req; -floo_rsp_t router_19_30_to_router_18_30_rsp; - -floo_req_t router_18_30_to_magia_tile_ni_18_30_req; -floo_rsp_t magia_tile_ni_18_30_to_router_18_30_rsp; - -floo_req_t router_18_31_to_router_17_31_req; -floo_rsp_t router_17_31_to_router_18_31_rsp; - -floo_req_t router_18_31_to_router_18_30_req; -floo_rsp_t router_18_30_to_router_18_31_rsp; - -floo_req_t router_18_31_to_router_19_31_req; -floo_rsp_t router_19_31_to_router_18_31_rsp; - -floo_req_t router_18_31_to_magia_tile_ni_18_31_req; -floo_rsp_t magia_tile_ni_18_31_to_router_18_31_rsp; - -floo_req_t router_19_0_to_router_18_0_req; -floo_rsp_t router_18_0_to_router_19_0_rsp; - -floo_req_t router_19_0_to_router_19_1_req; -floo_rsp_t router_19_1_to_router_19_0_rsp; - -floo_req_t router_19_0_to_router_20_0_req; -floo_rsp_t router_20_0_to_router_19_0_rsp; - -floo_req_t router_19_0_to_magia_tile_ni_19_0_req; -floo_rsp_t magia_tile_ni_19_0_to_router_19_0_rsp; - -floo_req_t router_19_1_to_router_18_1_req; -floo_rsp_t router_18_1_to_router_19_1_rsp; - -floo_req_t router_19_1_to_router_19_0_req; -floo_rsp_t router_19_0_to_router_19_1_rsp; - -floo_req_t router_19_1_to_router_19_2_req; -floo_rsp_t router_19_2_to_router_19_1_rsp; - -floo_req_t router_19_1_to_router_20_1_req; -floo_rsp_t router_20_1_to_router_19_1_rsp; - -floo_req_t router_19_1_to_magia_tile_ni_19_1_req; -floo_rsp_t magia_tile_ni_19_1_to_router_19_1_rsp; - -floo_req_t router_19_2_to_router_18_2_req; -floo_rsp_t router_18_2_to_router_19_2_rsp; - -floo_req_t router_19_2_to_router_19_1_req; -floo_rsp_t router_19_1_to_router_19_2_rsp; - -floo_req_t router_19_2_to_router_19_3_req; -floo_rsp_t router_19_3_to_router_19_2_rsp; - -floo_req_t router_19_2_to_router_20_2_req; -floo_rsp_t router_20_2_to_router_19_2_rsp; - -floo_req_t router_19_2_to_magia_tile_ni_19_2_req; -floo_rsp_t magia_tile_ni_19_2_to_router_19_2_rsp; - -floo_req_t router_19_3_to_router_18_3_req; -floo_rsp_t router_18_3_to_router_19_3_rsp; - -floo_req_t router_19_3_to_router_19_2_req; -floo_rsp_t router_19_2_to_router_19_3_rsp; - -floo_req_t router_19_3_to_router_19_4_req; -floo_rsp_t router_19_4_to_router_19_3_rsp; - -floo_req_t router_19_3_to_router_20_3_req; -floo_rsp_t router_20_3_to_router_19_3_rsp; - -floo_req_t router_19_3_to_magia_tile_ni_19_3_req; -floo_rsp_t magia_tile_ni_19_3_to_router_19_3_rsp; - -floo_req_t router_19_4_to_router_18_4_req; -floo_rsp_t router_18_4_to_router_19_4_rsp; - -floo_req_t router_19_4_to_router_19_3_req; -floo_rsp_t router_19_3_to_router_19_4_rsp; - -floo_req_t router_19_4_to_router_19_5_req; -floo_rsp_t router_19_5_to_router_19_4_rsp; - -floo_req_t router_19_4_to_router_20_4_req; -floo_rsp_t router_20_4_to_router_19_4_rsp; - -floo_req_t router_19_4_to_magia_tile_ni_19_4_req; -floo_rsp_t magia_tile_ni_19_4_to_router_19_4_rsp; - -floo_req_t router_19_5_to_router_18_5_req; -floo_rsp_t router_18_5_to_router_19_5_rsp; - -floo_req_t router_19_5_to_router_19_4_req; -floo_rsp_t router_19_4_to_router_19_5_rsp; - -floo_req_t router_19_5_to_router_19_6_req; -floo_rsp_t router_19_6_to_router_19_5_rsp; - -floo_req_t router_19_5_to_router_20_5_req; -floo_rsp_t router_20_5_to_router_19_5_rsp; - -floo_req_t router_19_5_to_magia_tile_ni_19_5_req; -floo_rsp_t magia_tile_ni_19_5_to_router_19_5_rsp; - -floo_req_t router_19_6_to_router_18_6_req; -floo_rsp_t router_18_6_to_router_19_6_rsp; - -floo_req_t router_19_6_to_router_19_5_req; -floo_rsp_t router_19_5_to_router_19_6_rsp; - -floo_req_t router_19_6_to_router_19_7_req; -floo_rsp_t router_19_7_to_router_19_6_rsp; - -floo_req_t router_19_6_to_router_20_6_req; -floo_rsp_t router_20_6_to_router_19_6_rsp; - -floo_req_t router_19_6_to_magia_tile_ni_19_6_req; -floo_rsp_t magia_tile_ni_19_6_to_router_19_6_rsp; - -floo_req_t router_19_7_to_router_18_7_req; -floo_rsp_t router_18_7_to_router_19_7_rsp; - -floo_req_t router_19_7_to_router_19_6_req; -floo_rsp_t router_19_6_to_router_19_7_rsp; - -floo_req_t router_19_7_to_router_19_8_req; -floo_rsp_t router_19_8_to_router_19_7_rsp; - -floo_req_t router_19_7_to_router_20_7_req; -floo_rsp_t router_20_7_to_router_19_7_rsp; - -floo_req_t router_19_7_to_magia_tile_ni_19_7_req; -floo_rsp_t magia_tile_ni_19_7_to_router_19_7_rsp; - -floo_req_t router_19_8_to_router_18_8_req; -floo_rsp_t router_18_8_to_router_19_8_rsp; - -floo_req_t router_19_8_to_router_19_7_req; -floo_rsp_t router_19_7_to_router_19_8_rsp; - -floo_req_t router_19_8_to_router_19_9_req; -floo_rsp_t router_19_9_to_router_19_8_rsp; - -floo_req_t router_19_8_to_router_20_8_req; -floo_rsp_t router_20_8_to_router_19_8_rsp; - -floo_req_t router_19_8_to_magia_tile_ni_19_8_req; -floo_rsp_t magia_tile_ni_19_8_to_router_19_8_rsp; - -floo_req_t router_19_9_to_router_18_9_req; -floo_rsp_t router_18_9_to_router_19_9_rsp; - -floo_req_t router_19_9_to_router_19_8_req; -floo_rsp_t router_19_8_to_router_19_9_rsp; - -floo_req_t router_19_9_to_router_19_10_req; -floo_rsp_t router_19_10_to_router_19_9_rsp; - -floo_req_t router_19_9_to_router_20_9_req; -floo_rsp_t router_20_9_to_router_19_9_rsp; - -floo_req_t router_19_9_to_magia_tile_ni_19_9_req; -floo_rsp_t magia_tile_ni_19_9_to_router_19_9_rsp; - -floo_req_t router_19_10_to_router_18_10_req; -floo_rsp_t router_18_10_to_router_19_10_rsp; - -floo_req_t router_19_10_to_router_19_9_req; -floo_rsp_t router_19_9_to_router_19_10_rsp; - -floo_req_t router_19_10_to_router_19_11_req; -floo_rsp_t router_19_11_to_router_19_10_rsp; - -floo_req_t router_19_10_to_router_20_10_req; -floo_rsp_t router_20_10_to_router_19_10_rsp; - -floo_req_t router_19_10_to_magia_tile_ni_19_10_req; -floo_rsp_t magia_tile_ni_19_10_to_router_19_10_rsp; - -floo_req_t router_19_11_to_router_18_11_req; -floo_rsp_t router_18_11_to_router_19_11_rsp; - -floo_req_t router_19_11_to_router_19_10_req; -floo_rsp_t router_19_10_to_router_19_11_rsp; - -floo_req_t router_19_11_to_router_19_12_req; -floo_rsp_t router_19_12_to_router_19_11_rsp; - -floo_req_t router_19_11_to_router_20_11_req; -floo_rsp_t router_20_11_to_router_19_11_rsp; - -floo_req_t router_19_11_to_magia_tile_ni_19_11_req; -floo_rsp_t magia_tile_ni_19_11_to_router_19_11_rsp; - -floo_req_t router_19_12_to_router_18_12_req; -floo_rsp_t router_18_12_to_router_19_12_rsp; - -floo_req_t router_19_12_to_router_19_11_req; -floo_rsp_t router_19_11_to_router_19_12_rsp; - -floo_req_t router_19_12_to_router_19_13_req; -floo_rsp_t router_19_13_to_router_19_12_rsp; - -floo_req_t router_19_12_to_router_20_12_req; -floo_rsp_t router_20_12_to_router_19_12_rsp; - -floo_req_t router_19_12_to_magia_tile_ni_19_12_req; -floo_rsp_t magia_tile_ni_19_12_to_router_19_12_rsp; - -floo_req_t router_19_13_to_router_18_13_req; -floo_rsp_t router_18_13_to_router_19_13_rsp; - -floo_req_t router_19_13_to_router_19_12_req; -floo_rsp_t router_19_12_to_router_19_13_rsp; - -floo_req_t router_19_13_to_router_19_14_req; -floo_rsp_t router_19_14_to_router_19_13_rsp; - -floo_req_t router_19_13_to_router_20_13_req; -floo_rsp_t router_20_13_to_router_19_13_rsp; - -floo_req_t router_19_13_to_magia_tile_ni_19_13_req; -floo_rsp_t magia_tile_ni_19_13_to_router_19_13_rsp; - -floo_req_t router_19_14_to_router_18_14_req; -floo_rsp_t router_18_14_to_router_19_14_rsp; - -floo_req_t router_19_14_to_router_19_13_req; -floo_rsp_t router_19_13_to_router_19_14_rsp; - -floo_req_t router_19_14_to_router_19_15_req; -floo_rsp_t router_19_15_to_router_19_14_rsp; - -floo_req_t router_19_14_to_router_20_14_req; -floo_rsp_t router_20_14_to_router_19_14_rsp; - -floo_req_t router_19_14_to_magia_tile_ni_19_14_req; -floo_rsp_t magia_tile_ni_19_14_to_router_19_14_rsp; - -floo_req_t router_19_15_to_router_18_15_req; -floo_rsp_t router_18_15_to_router_19_15_rsp; - -floo_req_t router_19_15_to_router_19_14_req; -floo_rsp_t router_19_14_to_router_19_15_rsp; - -floo_req_t router_19_15_to_router_19_16_req; -floo_rsp_t router_19_16_to_router_19_15_rsp; - -floo_req_t router_19_15_to_router_20_15_req; -floo_rsp_t router_20_15_to_router_19_15_rsp; - -floo_req_t router_19_15_to_magia_tile_ni_19_15_req; -floo_rsp_t magia_tile_ni_19_15_to_router_19_15_rsp; - -floo_req_t router_19_16_to_router_18_16_req; -floo_rsp_t router_18_16_to_router_19_16_rsp; - -floo_req_t router_19_16_to_router_19_15_req; -floo_rsp_t router_19_15_to_router_19_16_rsp; - -floo_req_t router_19_16_to_router_19_17_req; -floo_rsp_t router_19_17_to_router_19_16_rsp; - -floo_req_t router_19_16_to_router_20_16_req; -floo_rsp_t router_20_16_to_router_19_16_rsp; - -floo_req_t router_19_16_to_magia_tile_ni_19_16_req; -floo_rsp_t magia_tile_ni_19_16_to_router_19_16_rsp; - -floo_req_t router_19_17_to_router_18_17_req; -floo_rsp_t router_18_17_to_router_19_17_rsp; - -floo_req_t router_19_17_to_router_19_16_req; -floo_rsp_t router_19_16_to_router_19_17_rsp; - -floo_req_t router_19_17_to_router_19_18_req; -floo_rsp_t router_19_18_to_router_19_17_rsp; - -floo_req_t router_19_17_to_router_20_17_req; -floo_rsp_t router_20_17_to_router_19_17_rsp; - -floo_req_t router_19_17_to_magia_tile_ni_19_17_req; -floo_rsp_t magia_tile_ni_19_17_to_router_19_17_rsp; - -floo_req_t router_19_18_to_router_18_18_req; -floo_rsp_t router_18_18_to_router_19_18_rsp; - -floo_req_t router_19_18_to_router_19_17_req; -floo_rsp_t router_19_17_to_router_19_18_rsp; - -floo_req_t router_19_18_to_router_19_19_req; -floo_rsp_t router_19_19_to_router_19_18_rsp; - -floo_req_t router_19_18_to_router_20_18_req; -floo_rsp_t router_20_18_to_router_19_18_rsp; - -floo_req_t router_19_18_to_magia_tile_ni_19_18_req; -floo_rsp_t magia_tile_ni_19_18_to_router_19_18_rsp; - -floo_req_t router_19_19_to_router_18_19_req; -floo_rsp_t router_18_19_to_router_19_19_rsp; - -floo_req_t router_19_19_to_router_19_18_req; -floo_rsp_t router_19_18_to_router_19_19_rsp; - -floo_req_t router_19_19_to_router_19_20_req; -floo_rsp_t router_19_20_to_router_19_19_rsp; - -floo_req_t router_19_19_to_router_20_19_req; -floo_rsp_t router_20_19_to_router_19_19_rsp; - -floo_req_t router_19_19_to_magia_tile_ni_19_19_req; -floo_rsp_t magia_tile_ni_19_19_to_router_19_19_rsp; - -floo_req_t router_19_20_to_router_18_20_req; -floo_rsp_t router_18_20_to_router_19_20_rsp; - -floo_req_t router_19_20_to_router_19_19_req; -floo_rsp_t router_19_19_to_router_19_20_rsp; - -floo_req_t router_19_20_to_router_19_21_req; -floo_rsp_t router_19_21_to_router_19_20_rsp; - -floo_req_t router_19_20_to_router_20_20_req; -floo_rsp_t router_20_20_to_router_19_20_rsp; - -floo_req_t router_19_20_to_magia_tile_ni_19_20_req; -floo_rsp_t magia_tile_ni_19_20_to_router_19_20_rsp; - -floo_req_t router_19_21_to_router_18_21_req; -floo_rsp_t router_18_21_to_router_19_21_rsp; - -floo_req_t router_19_21_to_router_19_20_req; -floo_rsp_t router_19_20_to_router_19_21_rsp; - -floo_req_t router_19_21_to_router_19_22_req; -floo_rsp_t router_19_22_to_router_19_21_rsp; - -floo_req_t router_19_21_to_router_20_21_req; -floo_rsp_t router_20_21_to_router_19_21_rsp; - -floo_req_t router_19_21_to_magia_tile_ni_19_21_req; -floo_rsp_t magia_tile_ni_19_21_to_router_19_21_rsp; - -floo_req_t router_19_22_to_router_18_22_req; -floo_rsp_t router_18_22_to_router_19_22_rsp; - -floo_req_t router_19_22_to_router_19_21_req; -floo_rsp_t router_19_21_to_router_19_22_rsp; - -floo_req_t router_19_22_to_router_19_23_req; -floo_rsp_t router_19_23_to_router_19_22_rsp; - -floo_req_t router_19_22_to_router_20_22_req; -floo_rsp_t router_20_22_to_router_19_22_rsp; - -floo_req_t router_19_22_to_magia_tile_ni_19_22_req; -floo_rsp_t magia_tile_ni_19_22_to_router_19_22_rsp; - -floo_req_t router_19_23_to_router_18_23_req; -floo_rsp_t router_18_23_to_router_19_23_rsp; - -floo_req_t router_19_23_to_router_19_22_req; -floo_rsp_t router_19_22_to_router_19_23_rsp; - -floo_req_t router_19_23_to_router_19_24_req; -floo_rsp_t router_19_24_to_router_19_23_rsp; - -floo_req_t router_19_23_to_router_20_23_req; -floo_rsp_t router_20_23_to_router_19_23_rsp; - -floo_req_t router_19_23_to_magia_tile_ni_19_23_req; -floo_rsp_t magia_tile_ni_19_23_to_router_19_23_rsp; - -floo_req_t router_19_24_to_router_18_24_req; -floo_rsp_t router_18_24_to_router_19_24_rsp; - -floo_req_t router_19_24_to_router_19_23_req; -floo_rsp_t router_19_23_to_router_19_24_rsp; - -floo_req_t router_19_24_to_router_19_25_req; -floo_rsp_t router_19_25_to_router_19_24_rsp; - -floo_req_t router_19_24_to_router_20_24_req; -floo_rsp_t router_20_24_to_router_19_24_rsp; - -floo_req_t router_19_24_to_magia_tile_ni_19_24_req; -floo_rsp_t magia_tile_ni_19_24_to_router_19_24_rsp; - -floo_req_t router_19_25_to_router_18_25_req; -floo_rsp_t router_18_25_to_router_19_25_rsp; - -floo_req_t router_19_25_to_router_19_24_req; -floo_rsp_t router_19_24_to_router_19_25_rsp; - -floo_req_t router_19_25_to_router_19_26_req; -floo_rsp_t router_19_26_to_router_19_25_rsp; - -floo_req_t router_19_25_to_router_20_25_req; -floo_rsp_t router_20_25_to_router_19_25_rsp; - -floo_req_t router_19_25_to_magia_tile_ni_19_25_req; -floo_rsp_t magia_tile_ni_19_25_to_router_19_25_rsp; - -floo_req_t router_19_26_to_router_18_26_req; -floo_rsp_t router_18_26_to_router_19_26_rsp; - -floo_req_t router_19_26_to_router_19_25_req; -floo_rsp_t router_19_25_to_router_19_26_rsp; - -floo_req_t router_19_26_to_router_19_27_req; -floo_rsp_t router_19_27_to_router_19_26_rsp; - -floo_req_t router_19_26_to_router_20_26_req; -floo_rsp_t router_20_26_to_router_19_26_rsp; - -floo_req_t router_19_26_to_magia_tile_ni_19_26_req; -floo_rsp_t magia_tile_ni_19_26_to_router_19_26_rsp; - -floo_req_t router_19_27_to_router_18_27_req; -floo_rsp_t router_18_27_to_router_19_27_rsp; - -floo_req_t router_19_27_to_router_19_26_req; -floo_rsp_t router_19_26_to_router_19_27_rsp; - -floo_req_t router_19_27_to_router_19_28_req; -floo_rsp_t router_19_28_to_router_19_27_rsp; - -floo_req_t router_19_27_to_router_20_27_req; -floo_rsp_t router_20_27_to_router_19_27_rsp; - -floo_req_t router_19_27_to_magia_tile_ni_19_27_req; -floo_rsp_t magia_tile_ni_19_27_to_router_19_27_rsp; - -floo_req_t router_19_28_to_router_18_28_req; -floo_rsp_t router_18_28_to_router_19_28_rsp; - -floo_req_t router_19_28_to_router_19_27_req; -floo_rsp_t router_19_27_to_router_19_28_rsp; - -floo_req_t router_19_28_to_router_19_29_req; -floo_rsp_t router_19_29_to_router_19_28_rsp; - -floo_req_t router_19_28_to_router_20_28_req; -floo_rsp_t router_20_28_to_router_19_28_rsp; - -floo_req_t router_19_28_to_magia_tile_ni_19_28_req; -floo_rsp_t magia_tile_ni_19_28_to_router_19_28_rsp; - -floo_req_t router_19_29_to_router_18_29_req; -floo_rsp_t router_18_29_to_router_19_29_rsp; - -floo_req_t router_19_29_to_router_19_28_req; -floo_rsp_t router_19_28_to_router_19_29_rsp; - -floo_req_t router_19_29_to_router_19_30_req; -floo_rsp_t router_19_30_to_router_19_29_rsp; - -floo_req_t router_19_29_to_router_20_29_req; -floo_rsp_t router_20_29_to_router_19_29_rsp; - -floo_req_t router_19_29_to_magia_tile_ni_19_29_req; -floo_rsp_t magia_tile_ni_19_29_to_router_19_29_rsp; - -floo_req_t router_19_30_to_router_18_30_req; -floo_rsp_t router_18_30_to_router_19_30_rsp; - -floo_req_t router_19_30_to_router_19_29_req; -floo_rsp_t router_19_29_to_router_19_30_rsp; - -floo_req_t router_19_30_to_router_19_31_req; -floo_rsp_t router_19_31_to_router_19_30_rsp; - -floo_req_t router_19_30_to_router_20_30_req; -floo_rsp_t router_20_30_to_router_19_30_rsp; - -floo_req_t router_19_30_to_magia_tile_ni_19_30_req; -floo_rsp_t magia_tile_ni_19_30_to_router_19_30_rsp; - -floo_req_t router_19_31_to_router_18_31_req; -floo_rsp_t router_18_31_to_router_19_31_rsp; - -floo_req_t router_19_31_to_router_19_30_req; -floo_rsp_t router_19_30_to_router_19_31_rsp; - -floo_req_t router_19_31_to_router_20_31_req; -floo_rsp_t router_20_31_to_router_19_31_rsp; - -floo_req_t router_19_31_to_magia_tile_ni_19_31_req; -floo_rsp_t magia_tile_ni_19_31_to_router_19_31_rsp; - -floo_req_t router_20_0_to_router_19_0_req; -floo_rsp_t router_19_0_to_router_20_0_rsp; - -floo_req_t router_20_0_to_router_20_1_req; -floo_rsp_t router_20_1_to_router_20_0_rsp; - -floo_req_t router_20_0_to_router_21_0_req; -floo_rsp_t router_21_0_to_router_20_0_rsp; - -floo_req_t router_20_0_to_magia_tile_ni_20_0_req; -floo_rsp_t magia_tile_ni_20_0_to_router_20_0_rsp; - -floo_req_t router_20_1_to_router_19_1_req; -floo_rsp_t router_19_1_to_router_20_1_rsp; - -floo_req_t router_20_1_to_router_20_0_req; -floo_rsp_t router_20_0_to_router_20_1_rsp; - -floo_req_t router_20_1_to_router_20_2_req; -floo_rsp_t router_20_2_to_router_20_1_rsp; - -floo_req_t router_20_1_to_router_21_1_req; -floo_rsp_t router_21_1_to_router_20_1_rsp; - -floo_req_t router_20_1_to_magia_tile_ni_20_1_req; -floo_rsp_t magia_tile_ni_20_1_to_router_20_1_rsp; - -floo_req_t router_20_2_to_router_19_2_req; -floo_rsp_t router_19_2_to_router_20_2_rsp; - -floo_req_t router_20_2_to_router_20_1_req; -floo_rsp_t router_20_1_to_router_20_2_rsp; - -floo_req_t router_20_2_to_router_20_3_req; -floo_rsp_t router_20_3_to_router_20_2_rsp; - -floo_req_t router_20_2_to_router_21_2_req; -floo_rsp_t router_21_2_to_router_20_2_rsp; - -floo_req_t router_20_2_to_magia_tile_ni_20_2_req; -floo_rsp_t magia_tile_ni_20_2_to_router_20_2_rsp; - -floo_req_t router_20_3_to_router_19_3_req; -floo_rsp_t router_19_3_to_router_20_3_rsp; - -floo_req_t router_20_3_to_router_20_2_req; -floo_rsp_t router_20_2_to_router_20_3_rsp; - -floo_req_t router_20_3_to_router_20_4_req; -floo_rsp_t router_20_4_to_router_20_3_rsp; - -floo_req_t router_20_3_to_router_21_3_req; -floo_rsp_t router_21_3_to_router_20_3_rsp; - -floo_req_t router_20_3_to_magia_tile_ni_20_3_req; -floo_rsp_t magia_tile_ni_20_3_to_router_20_3_rsp; - -floo_req_t router_20_4_to_router_19_4_req; -floo_rsp_t router_19_4_to_router_20_4_rsp; - -floo_req_t router_20_4_to_router_20_3_req; -floo_rsp_t router_20_3_to_router_20_4_rsp; - -floo_req_t router_20_4_to_router_20_5_req; -floo_rsp_t router_20_5_to_router_20_4_rsp; - -floo_req_t router_20_4_to_router_21_4_req; -floo_rsp_t router_21_4_to_router_20_4_rsp; - -floo_req_t router_20_4_to_magia_tile_ni_20_4_req; -floo_rsp_t magia_tile_ni_20_4_to_router_20_4_rsp; - -floo_req_t router_20_5_to_router_19_5_req; -floo_rsp_t router_19_5_to_router_20_5_rsp; - -floo_req_t router_20_5_to_router_20_4_req; -floo_rsp_t router_20_4_to_router_20_5_rsp; - -floo_req_t router_20_5_to_router_20_6_req; -floo_rsp_t router_20_6_to_router_20_5_rsp; - -floo_req_t router_20_5_to_router_21_5_req; -floo_rsp_t router_21_5_to_router_20_5_rsp; - -floo_req_t router_20_5_to_magia_tile_ni_20_5_req; -floo_rsp_t magia_tile_ni_20_5_to_router_20_5_rsp; - -floo_req_t router_20_6_to_router_19_6_req; -floo_rsp_t router_19_6_to_router_20_6_rsp; - -floo_req_t router_20_6_to_router_20_5_req; -floo_rsp_t router_20_5_to_router_20_6_rsp; - -floo_req_t router_20_6_to_router_20_7_req; -floo_rsp_t router_20_7_to_router_20_6_rsp; - -floo_req_t router_20_6_to_router_21_6_req; -floo_rsp_t router_21_6_to_router_20_6_rsp; - -floo_req_t router_20_6_to_magia_tile_ni_20_6_req; -floo_rsp_t magia_tile_ni_20_6_to_router_20_6_rsp; - -floo_req_t router_20_7_to_router_19_7_req; -floo_rsp_t router_19_7_to_router_20_7_rsp; - -floo_req_t router_20_7_to_router_20_6_req; -floo_rsp_t router_20_6_to_router_20_7_rsp; - -floo_req_t router_20_7_to_router_20_8_req; -floo_rsp_t router_20_8_to_router_20_7_rsp; - -floo_req_t router_20_7_to_router_21_7_req; -floo_rsp_t router_21_7_to_router_20_7_rsp; - -floo_req_t router_20_7_to_magia_tile_ni_20_7_req; -floo_rsp_t magia_tile_ni_20_7_to_router_20_7_rsp; - -floo_req_t router_20_8_to_router_19_8_req; -floo_rsp_t router_19_8_to_router_20_8_rsp; - -floo_req_t router_20_8_to_router_20_7_req; -floo_rsp_t router_20_7_to_router_20_8_rsp; - -floo_req_t router_20_8_to_router_20_9_req; -floo_rsp_t router_20_9_to_router_20_8_rsp; - -floo_req_t router_20_8_to_router_21_8_req; -floo_rsp_t router_21_8_to_router_20_8_rsp; - -floo_req_t router_20_8_to_magia_tile_ni_20_8_req; -floo_rsp_t magia_tile_ni_20_8_to_router_20_8_rsp; - -floo_req_t router_20_9_to_router_19_9_req; -floo_rsp_t router_19_9_to_router_20_9_rsp; - -floo_req_t router_20_9_to_router_20_8_req; -floo_rsp_t router_20_8_to_router_20_9_rsp; - -floo_req_t router_20_9_to_router_20_10_req; -floo_rsp_t router_20_10_to_router_20_9_rsp; - -floo_req_t router_20_9_to_router_21_9_req; -floo_rsp_t router_21_9_to_router_20_9_rsp; - -floo_req_t router_20_9_to_magia_tile_ni_20_9_req; -floo_rsp_t magia_tile_ni_20_9_to_router_20_9_rsp; - -floo_req_t router_20_10_to_router_19_10_req; -floo_rsp_t router_19_10_to_router_20_10_rsp; - -floo_req_t router_20_10_to_router_20_9_req; -floo_rsp_t router_20_9_to_router_20_10_rsp; - -floo_req_t router_20_10_to_router_20_11_req; -floo_rsp_t router_20_11_to_router_20_10_rsp; - -floo_req_t router_20_10_to_router_21_10_req; -floo_rsp_t router_21_10_to_router_20_10_rsp; - -floo_req_t router_20_10_to_magia_tile_ni_20_10_req; -floo_rsp_t magia_tile_ni_20_10_to_router_20_10_rsp; - -floo_req_t router_20_11_to_router_19_11_req; -floo_rsp_t router_19_11_to_router_20_11_rsp; - -floo_req_t router_20_11_to_router_20_10_req; -floo_rsp_t router_20_10_to_router_20_11_rsp; - -floo_req_t router_20_11_to_router_20_12_req; -floo_rsp_t router_20_12_to_router_20_11_rsp; - -floo_req_t router_20_11_to_router_21_11_req; -floo_rsp_t router_21_11_to_router_20_11_rsp; - -floo_req_t router_20_11_to_magia_tile_ni_20_11_req; -floo_rsp_t magia_tile_ni_20_11_to_router_20_11_rsp; - -floo_req_t router_20_12_to_router_19_12_req; -floo_rsp_t router_19_12_to_router_20_12_rsp; - -floo_req_t router_20_12_to_router_20_11_req; -floo_rsp_t router_20_11_to_router_20_12_rsp; - -floo_req_t router_20_12_to_router_20_13_req; -floo_rsp_t router_20_13_to_router_20_12_rsp; - -floo_req_t router_20_12_to_router_21_12_req; -floo_rsp_t router_21_12_to_router_20_12_rsp; - -floo_req_t router_20_12_to_magia_tile_ni_20_12_req; -floo_rsp_t magia_tile_ni_20_12_to_router_20_12_rsp; - -floo_req_t router_20_13_to_router_19_13_req; -floo_rsp_t router_19_13_to_router_20_13_rsp; - -floo_req_t router_20_13_to_router_20_12_req; -floo_rsp_t router_20_12_to_router_20_13_rsp; - -floo_req_t router_20_13_to_router_20_14_req; -floo_rsp_t router_20_14_to_router_20_13_rsp; - -floo_req_t router_20_13_to_router_21_13_req; -floo_rsp_t router_21_13_to_router_20_13_rsp; - -floo_req_t router_20_13_to_magia_tile_ni_20_13_req; -floo_rsp_t magia_tile_ni_20_13_to_router_20_13_rsp; - -floo_req_t router_20_14_to_router_19_14_req; -floo_rsp_t router_19_14_to_router_20_14_rsp; - -floo_req_t router_20_14_to_router_20_13_req; -floo_rsp_t router_20_13_to_router_20_14_rsp; - -floo_req_t router_20_14_to_router_20_15_req; -floo_rsp_t router_20_15_to_router_20_14_rsp; - -floo_req_t router_20_14_to_router_21_14_req; -floo_rsp_t router_21_14_to_router_20_14_rsp; - -floo_req_t router_20_14_to_magia_tile_ni_20_14_req; -floo_rsp_t magia_tile_ni_20_14_to_router_20_14_rsp; - -floo_req_t router_20_15_to_router_19_15_req; -floo_rsp_t router_19_15_to_router_20_15_rsp; - -floo_req_t router_20_15_to_router_20_14_req; -floo_rsp_t router_20_14_to_router_20_15_rsp; - -floo_req_t router_20_15_to_router_20_16_req; -floo_rsp_t router_20_16_to_router_20_15_rsp; - -floo_req_t router_20_15_to_router_21_15_req; -floo_rsp_t router_21_15_to_router_20_15_rsp; - -floo_req_t router_20_15_to_magia_tile_ni_20_15_req; -floo_rsp_t magia_tile_ni_20_15_to_router_20_15_rsp; - -floo_req_t router_20_16_to_router_19_16_req; -floo_rsp_t router_19_16_to_router_20_16_rsp; - -floo_req_t router_20_16_to_router_20_15_req; -floo_rsp_t router_20_15_to_router_20_16_rsp; - -floo_req_t router_20_16_to_router_20_17_req; -floo_rsp_t router_20_17_to_router_20_16_rsp; - -floo_req_t router_20_16_to_router_21_16_req; -floo_rsp_t router_21_16_to_router_20_16_rsp; - -floo_req_t router_20_16_to_magia_tile_ni_20_16_req; -floo_rsp_t magia_tile_ni_20_16_to_router_20_16_rsp; - -floo_req_t router_20_17_to_router_19_17_req; -floo_rsp_t router_19_17_to_router_20_17_rsp; - -floo_req_t router_20_17_to_router_20_16_req; -floo_rsp_t router_20_16_to_router_20_17_rsp; - -floo_req_t router_20_17_to_router_20_18_req; -floo_rsp_t router_20_18_to_router_20_17_rsp; - -floo_req_t router_20_17_to_router_21_17_req; -floo_rsp_t router_21_17_to_router_20_17_rsp; - -floo_req_t router_20_17_to_magia_tile_ni_20_17_req; -floo_rsp_t magia_tile_ni_20_17_to_router_20_17_rsp; - -floo_req_t router_20_18_to_router_19_18_req; -floo_rsp_t router_19_18_to_router_20_18_rsp; - -floo_req_t router_20_18_to_router_20_17_req; -floo_rsp_t router_20_17_to_router_20_18_rsp; - -floo_req_t router_20_18_to_router_20_19_req; -floo_rsp_t router_20_19_to_router_20_18_rsp; - -floo_req_t router_20_18_to_router_21_18_req; -floo_rsp_t router_21_18_to_router_20_18_rsp; - -floo_req_t router_20_18_to_magia_tile_ni_20_18_req; -floo_rsp_t magia_tile_ni_20_18_to_router_20_18_rsp; - -floo_req_t router_20_19_to_router_19_19_req; -floo_rsp_t router_19_19_to_router_20_19_rsp; - -floo_req_t router_20_19_to_router_20_18_req; -floo_rsp_t router_20_18_to_router_20_19_rsp; - -floo_req_t router_20_19_to_router_20_20_req; -floo_rsp_t router_20_20_to_router_20_19_rsp; - -floo_req_t router_20_19_to_router_21_19_req; -floo_rsp_t router_21_19_to_router_20_19_rsp; - -floo_req_t router_20_19_to_magia_tile_ni_20_19_req; -floo_rsp_t magia_tile_ni_20_19_to_router_20_19_rsp; - -floo_req_t router_20_20_to_router_19_20_req; -floo_rsp_t router_19_20_to_router_20_20_rsp; - -floo_req_t router_20_20_to_router_20_19_req; -floo_rsp_t router_20_19_to_router_20_20_rsp; - -floo_req_t router_20_20_to_router_20_21_req; -floo_rsp_t router_20_21_to_router_20_20_rsp; - -floo_req_t router_20_20_to_router_21_20_req; -floo_rsp_t router_21_20_to_router_20_20_rsp; - -floo_req_t router_20_20_to_magia_tile_ni_20_20_req; -floo_rsp_t magia_tile_ni_20_20_to_router_20_20_rsp; - -floo_req_t router_20_21_to_router_19_21_req; -floo_rsp_t router_19_21_to_router_20_21_rsp; - -floo_req_t router_20_21_to_router_20_20_req; -floo_rsp_t router_20_20_to_router_20_21_rsp; - -floo_req_t router_20_21_to_router_20_22_req; -floo_rsp_t router_20_22_to_router_20_21_rsp; - -floo_req_t router_20_21_to_router_21_21_req; -floo_rsp_t router_21_21_to_router_20_21_rsp; - -floo_req_t router_20_21_to_magia_tile_ni_20_21_req; -floo_rsp_t magia_tile_ni_20_21_to_router_20_21_rsp; - -floo_req_t router_20_22_to_router_19_22_req; -floo_rsp_t router_19_22_to_router_20_22_rsp; - -floo_req_t router_20_22_to_router_20_21_req; -floo_rsp_t router_20_21_to_router_20_22_rsp; - -floo_req_t router_20_22_to_router_20_23_req; -floo_rsp_t router_20_23_to_router_20_22_rsp; - -floo_req_t router_20_22_to_router_21_22_req; -floo_rsp_t router_21_22_to_router_20_22_rsp; - -floo_req_t router_20_22_to_magia_tile_ni_20_22_req; -floo_rsp_t magia_tile_ni_20_22_to_router_20_22_rsp; - -floo_req_t router_20_23_to_router_19_23_req; -floo_rsp_t router_19_23_to_router_20_23_rsp; - -floo_req_t router_20_23_to_router_20_22_req; -floo_rsp_t router_20_22_to_router_20_23_rsp; - -floo_req_t router_20_23_to_router_20_24_req; -floo_rsp_t router_20_24_to_router_20_23_rsp; - -floo_req_t router_20_23_to_router_21_23_req; -floo_rsp_t router_21_23_to_router_20_23_rsp; - -floo_req_t router_20_23_to_magia_tile_ni_20_23_req; -floo_rsp_t magia_tile_ni_20_23_to_router_20_23_rsp; - -floo_req_t router_20_24_to_router_19_24_req; -floo_rsp_t router_19_24_to_router_20_24_rsp; - -floo_req_t router_20_24_to_router_20_23_req; -floo_rsp_t router_20_23_to_router_20_24_rsp; - -floo_req_t router_20_24_to_router_20_25_req; -floo_rsp_t router_20_25_to_router_20_24_rsp; - -floo_req_t router_20_24_to_router_21_24_req; -floo_rsp_t router_21_24_to_router_20_24_rsp; - -floo_req_t router_20_24_to_magia_tile_ni_20_24_req; -floo_rsp_t magia_tile_ni_20_24_to_router_20_24_rsp; - -floo_req_t router_20_25_to_router_19_25_req; -floo_rsp_t router_19_25_to_router_20_25_rsp; - -floo_req_t router_20_25_to_router_20_24_req; -floo_rsp_t router_20_24_to_router_20_25_rsp; - -floo_req_t router_20_25_to_router_20_26_req; -floo_rsp_t router_20_26_to_router_20_25_rsp; - -floo_req_t router_20_25_to_router_21_25_req; -floo_rsp_t router_21_25_to_router_20_25_rsp; - -floo_req_t router_20_25_to_magia_tile_ni_20_25_req; -floo_rsp_t magia_tile_ni_20_25_to_router_20_25_rsp; - -floo_req_t router_20_26_to_router_19_26_req; -floo_rsp_t router_19_26_to_router_20_26_rsp; - -floo_req_t router_20_26_to_router_20_25_req; -floo_rsp_t router_20_25_to_router_20_26_rsp; - -floo_req_t router_20_26_to_router_20_27_req; -floo_rsp_t router_20_27_to_router_20_26_rsp; - -floo_req_t router_20_26_to_router_21_26_req; -floo_rsp_t router_21_26_to_router_20_26_rsp; - -floo_req_t router_20_26_to_magia_tile_ni_20_26_req; -floo_rsp_t magia_tile_ni_20_26_to_router_20_26_rsp; - -floo_req_t router_20_27_to_router_19_27_req; -floo_rsp_t router_19_27_to_router_20_27_rsp; - -floo_req_t router_20_27_to_router_20_26_req; -floo_rsp_t router_20_26_to_router_20_27_rsp; - -floo_req_t router_20_27_to_router_20_28_req; -floo_rsp_t router_20_28_to_router_20_27_rsp; - -floo_req_t router_20_27_to_router_21_27_req; -floo_rsp_t router_21_27_to_router_20_27_rsp; - -floo_req_t router_20_27_to_magia_tile_ni_20_27_req; -floo_rsp_t magia_tile_ni_20_27_to_router_20_27_rsp; - -floo_req_t router_20_28_to_router_19_28_req; -floo_rsp_t router_19_28_to_router_20_28_rsp; - -floo_req_t router_20_28_to_router_20_27_req; -floo_rsp_t router_20_27_to_router_20_28_rsp; - -floo_req_t router_20_28_to_router_20_29_req; -floo_rsp_t router_20_29_to_router_20_28_rsp; - -floo_req_t router_20_28_to_router_21_28_req; -floo_rsp_t router_21_28_to_router_20_28_rsp; - -floo_req_t router_20_28_to_magia_tile_ni_20_28_req; -floo_rsp_t magia_tile_ni_20_28_to_router_20_28_rsp; - -floo_req_t router_20_29_to_router_19_29_req; -floo_rsp_t router_19_29_to_router_20_29_rsp; - -floo_req_t router_20_29_to_router_20_28_req; -floo_rsp_t router_20_28_to_router_20_29_rsp; - -floo_req_t router_20_29_to_router_20_30_req; -floo_rsp_t router_20_30_to_router_20_29_rsp; - -floo_req_t router_20_29_to_router_21_29_req; -floo_rsp_t router_21_29_to_router_20_29_rsp; - -floo_req_t router_20_29_to_magia_tile_ni_20_29_req; -floo_rsp_t magia_tile_ni_20_29_to_router_20_29_rsp; - -floo_req_t router_20_30_to_router_19_30_req; -floo_rsp_t router_19_30_to_router_20_30_rsp; - -floo_req_t router_20_30_to_router_20_29_req; -floo_rsp_t router_20_29_to_router_20_30_rsp; - -floo_req_t router_20_30_to_router_20_31_req; -floo_rsp_t router_20_31_to_router_20_30_rsp; - -floo_req_t router_20_30_to_router_21_30_req; -floo_rsp_t router_21_30_to_router_20_30_rsp; - -floo_req_t router_20_30_to_magia_tile_ni_20_30_req; -floo_rsp_t magia_tile_ni_20_30_to_router_20_30_rsp; - -floo_req_t router_20_31_to_router_19_31_req; -floo_rsp_t router_19_31_to_router_20_31_rsp; - -floo_req_t router_20_31_to_router_20_30_req; -floo_rsp_t router_20_30_to_router_20_31_rsp; - -floo_req_t router_20_31_to_router_21_31_req; -floo_rsp_t router_21_31_to_router_20_31_rsp; - -floo_req_t router_20_31_to_magia_tile_ni_20_31_req; -floo_rsp_t magia_tile_ni_20_31_to_router_20_31_rsp; - -floo_req_t router_21_0_to_router_20_0_req; -floo_rsp_t router_20_0_to_router_21_0_rsp; - -floo_req_t router_21_0_to_router_21_1_req; -floo_rsp_t router_21_1_to_router_21_0_rsp; - -floo_req_t router_21_0_to_router_22_0_req; -floo_rsp_t router_22_0_to_router_21_0_rsp; - -floo_req_t router_21_0_to_magia_tile_ni_21_0_req; -floo_rsp_t magia_tile_ni_21_0_to_router_21_0_rsp; - -floo_req_t router_21_1_to_router_20_1_req; -floo_rsp_t router_20_1_to_router_21_1_rsp; - -floo_req_t router_21_1_to_router_21_0_req; -floo_rsp_t router_21_0_to_router_21_1_rsp; - -floo_req_t router_21_1_to_router_21_2_req; -floo_rsp_t router_21_2_to_router_21_1_rsp; - -floo_req_t router_21_1_to_router_22_1_req; -floo_rsp_t router_22_1_to_router_21_1_rsp; - -floo_req_t router_21_1_to_magia_tile_ni_21_1_req; -floo_rsp_t magia_tile_ni_21_1_to_router_21_1_rsp; - -floo_req_t router_21_2_to_router_20_2_req; -floo_rsp_t router_20_2_to_router_21_2_rsp; - -floo_req_t router_21_2_to_router_21_1_req; -floo_rsp_t router_21_1_to_router_21_2_rsp; - -floo_req_t router_21_2_to_router_21_3_req; -floo_rsp_t router_21_3_to_router_21_2_rsp; - -floo_req_t router_21_2_to_router_22_2_req; -floo_rsp_t router_22_2_to_router_21_2_rsp; - -floo_req_t router_21_2_to_magia_tile_ni_21_2_req; -floo_rsp_t magia_tile_ni_21_2_to_router_21_2_rsp; - -floo_req_t router_21_3_to_router_20_3_req; -floo_rsp_t router_20_3_to_router_21_3_rsp; - -floo_req_t router_21_3_to_router_21_2_req; -floo_rsp_t router_21_2_to_router_21_3_rsp; - -floo_req_t router_21_3_to_router_21_4_req; -floo_rsp_t router_21_4_to_router_21_3_rsp; - -floo_req_t router_21_3_to_router_22_3_req; -floo_rsp_t router_22_3_to_router_21_3_rsp; - -floo_req_t router_21_3_to_magia_tile_ni_21_3_req; -floo_rsp_t magia_tile_ni_21_3_to_router_21_3_rsp; - -floo_req_t router_21_4_to_router_20_4_req; -floo_rsp_t router_20_4_to_router_21_4_rsp; - -floo_req_t router_21_4_to_router_21_3_req; -floo_rsp_t router_21_3_to_router_21_4_rsp; - -floo_req_t router_21_4_to_router_21_5_req; -floo_rsp_t router_21_5_to_router_21_4_rsp; - -floo_req_t router_21_4_to_router_22_4_req; -floo_rsp_t router_22_4_to_router_21_4_rsp; - -floo_req_t router_21_4_to_magia_tile_ni_21_4_req; -floo_rsp_t magia_tile_ni_21_4_to_router_21_4_rsp; - -floo_req_t router_21_5_to_router_20_5_req; -floo_rsp_t router_20_5_to_router_21_5_rsp; - -floo_req_t router_21_5_to_router_21_4_req; -floo_rsp_t router_21_4_to_router_21_5_rsp; - -floo_req_t router_21_5_to_router_21_6_req; -floo_rsp_t router_21_6_to_router_21_5_rsp; - -floo_req_t router_21_5_to_router_22_5_req; -floo_rsp_t router_22_5_to_router_21_5_rsp; - -floo_req_t router_21_5_to_magia_tile_ni_21_5_req; -floo_rsp_t magia_tile_ni_21_5_to_router_21_5_rsp; - -floo_req_t router_21_6_to_router_20_6_req; -floo_rsp_t router_20_6_to_router_21_6_rsp; - -floo_req_t router_21_6_to_router_21_5_req; -floo_rsp_t router_21_5_to_router_21_6_rsp; - -floo_req_t router_21_6_to_router_21_7_req; -floo_rsp_t router_21_7_to_router_21_6_rsp; - -floo_req_t router_21_6_to_router_22_6_req; -floo_rsp_t router_22_6_to_router_21_6_rsp; - -floo_req_t router_21_6_to_magia_tile_ni_21_6_req; -floo_rsp_t magia_tile_ni_21_6_to_router_21_6_rsp; - -floo_req_t router_21_7_to_router_20_7_req; -floo_rsp_t router_20_7_to_router_21_7_rsp; - -floo_req_t router_21_7_to_router_21_6_req; -floo_rsp_t router_21_6_to_router_21_7_rsp; - -floo_req_t router_21_7_to_router_21_8_req; -floo_rsp_t router_21_8_to_router_21_7_rsp; - -floo_req_t router_21_7_to_router_22_7_req; -floo_rsp_t router_22_7_to_router_21_7_rsp; - -floo_req_t router_21_7_to_magia_tile_ni_21_7_req; -floo_rsp_t magia_tile_ni_21_7_to_router_21_7_rsp; - -floo_req_t router_21_8_to_router_20_8_req; -floo_rsp_t router_20_8_to_router_21_8_rsp; - -floo_req_t router_21_8_to_router_21_7_req; -floo_rsp_t router_21_7_to_router_21_8_rsp; - -floo_req_t router_21_8_to_router_21_9_req; -floo_rsp_t router_21_9_to_router_21_8_rsp; - -floo_req_t router_21_8_to_router_22_8_req; -floo_rsp_t router_22_8_to_router_21_8_rsp; - -floo_req_t router_21_8_to_magia_tile_ni_21_8_req; -floo_rsp_t magia_tile_ni_21_8_to_router_21_8_rsp; - -floo_req_t router_21_9_to_router_20_9_req; -floo_rsp_t router_20_9_to_router_21_9_rsp; - -floo_req_t router_21_9_to_router_21_8_req; -floo_rsp_t router_21_8_to_router_21_9_rsp; - -floo_req_t router_21_9_to_router_21_10_req; -floo_rsp_t router_21_10_to_router_21_9_rsp; - -floo_req_t router_21_9_to_router_22_9_req; -floo_rsp_t router_22_9_to_router_21_9_rsp; - -floo_req_t router_21_9_to_magia_tile_ni_21_9_req; -floo_rsp_t magia_tile_ni_21_9_to_router_21_9_rsp; - -floo_req_t router_21_10_to_router_20_10_req; -floo_rsp_t router_20_10_to_router_21_10_rsp; - -floo_req_t router_21_10_to_router_21_9_req; -floo_rsp_t router_21_9_to_router_21_10_rsp; - -floo_req_t router_21_10_to_router_21_11_req; -floo_rsp_t router_21_11_to_router_21_10_rsp; - -floo_req_t router_21_10_to_router_22_10_req; -floo_rsp_t router_22_10_to_router_21_10_rsp; - -floo_req_t router_21_10_to_magia_tile_ni_21_10_req; -floo_rsp_t magia_tile_ni_21_10_to_router_21_10_rsp; - -floo_req_t router_21_11_to_router_20_11_req; -floo_rsp_t router_20_11_to_router_21_11_rsp; - -floo_req_t router_21_11_to_router_21_10_req; -floo_rsp_t router_21_10_to_router_21_11_rsp; - -floo_req_t router_21_11_to_router_21_12_req; -floo_rsp_t router_21_12_to_router_21_11_rsp; - -floo_req_t router_21_11_to_router_22_11_req; -floo_rsp_t router_22_11_to_router_21_11_rsp; - -floo_req_t router_21_11_to_magia_tile_ni_21_11_req; -floo_rsp_t magia_tile_ni_21_11_to_router_21_11_rsp; - -floo_req_t router_21_12_to_router_20_12_req; -floo_rsp_t router_20_12_to_router_21_12_rsp; - -floo_req_t router_21_12_to_router_21_11_req; -floo_rsp_t router_21_11_to_router_21_12_rsp; - -floo_req_t router_21_12_to_router_21_13_req; -floo_rsp_t router_21_13_to_router_21_12_rsp; - -floo_req_t router_21_12_to_router_22_12_req; -floo_rsp_t router_22_12_to_router_21_12_rsp; - -floo_req_t router_21_12_to_magia_tile_ni_21_12_req; -floo_rsp_t magia_tile_ni_21_12_to_router_21_12_rsp; - -floo_req_t router_21_13_to_router_20_13_req; -floo_rsp_t router_20_13_to_router_21_13_rsp; - -floo_req_t router_21_13_to_router_21_12_req; -floo_rsp_t router_21_12_to_router_21_13_rsp; - -floo_req_t router_21_13_to_router_21_14_req; -floo_rsp_t router_21_14_to_router_21_13_rsp; - -floo_req_t router_21_13_to_router_22_13_req; -floo_rsp_t router_22_13_to_router_21_13_rsp; - -floo_req_t router_21_13_to_magia_tile_ni_21_13_req; -floo_rsp_t magia_tile_ni_21_13_to_router_21_13_rsp; - -floo_req_t router_21_14_to_router_20_14_req; -floo_rsp_t router_20_14_to_router_21_14_rsp; - -floo_req_t router_21_14_to_router_21_13_req; -floo_rsp_t router_21_13_to_router_21_14_rsp; - -floo_req_t router_21_14_to_router_21_15_req; -floo_rsp_t router_21_15_to_router_21_14_rsp; - -floo_req_t router_21_14_to_router_22_14_req; -floo_rsp_t router_22_14_to_router_21_14_rsp; - -floo_req_t router_21_14_to_magia_tile_ni_21_14_req; -floo_rsp_t magia_tile_ni_21_14_to_router_21_14_rsp; - -floo_req_t router_21_15_to_router_20_15_req; -floo_rsp_t router_20_15_to_router_21_15_rsp; - -floo_req_t router_21_15_to_router_21_14_req; -floo_rsp_t router_21_14_to_router_21_15_rsp; - -floo_req_t router_21_15_to_router_21_16_req; -floo_rsp_t router_21_16_to_router_21_15_rsp; - -floo_req_t router_21_15_to_router_22_15_req; -floo_rsp_t router_22_15_to_router_21_15_rsp; - -floo_req_t router_21_15_to_magia_tile_ni_21_15_req; -floo_rsp_t magia_tile_ni_21_15_to_router_21_15_rsp; - -floo_req_t router_21_16_to_router_20_16_req; -floo_rsp_t router_20_16_to_router_21_16_rsp; - -floo_req_t router_21_16_to_router_21_15_req; -floo_rsp_t router_21_15_to_router_21_16_rsp; - -floo_req_t router_21_16_to_router_21_17_req; -floo_rsp_t router_21_17_to_router_21_16_rsp; - -floo_req_t router_21_16_to_router_22_16_req; -floo_rsp_t router_22_16_to_router_21_16_rsp; - -floo_req_t router_21_16_to_magia_tile_ni_21_16_req; -floo_rsp_t magia_tile_ni_21_16_to_router_21_16_rsp; - -floo_req_t router_21_17_to_router_20_17_req; -floo_rsp_t router_20_17_to_router_21_17_rsp; - -floo_req_t router_21_17_to_router_21_16_req; -floo_rsp_t router_21_16_to_router_21_17_rsp; - -floo_req_t router_21_17_to_router_21_18_req; -floo_rsp_t router_21_18_to_router_21_17_rsp; - -floo_req_t router_21_17_to_router_22_17_req; -floo_rsp_t router_22_17_to_router_21_17_rsp; - -floo_req_t router_21_17_to_magia_tile_ni_21_17_req; -floo_rsp_t magia_tile_ni_21_17_to_router_21_17_rsp; - -floo_req_t router_21_18_to_router_20_18_req; -floo_rsp_t router_20_18_to_router_21_18_rsp; - -floo_req_t router_21_18_to_router_21_17_req; -floo_rsp_t router_21_17_to_router_21_18_rsp; - -floo_req_t router_21_18_to_router_21_19_req; -floo_rsp_t router_21_19_to_router_21_18_rsp; - -floo_req_t router_21_18_to_router_22_18_req; -floo_rsp_t router_22_18_to_router_21_18_rsp; - -floo_req_t router_21_18_to_magia_tile_ni_21_18_req; -floo_rsp_t magia_tile_ni_21_18_to_router_21_18_rsp; - -floo_req_t router_21_19_to_router_20_19_req; -floo_rsp_t router_20_19_to_router_21_19_rsp; - -floo_req_t router_21_19_to_router_21_18_req; -floo_rsp_t router_21_18_to_router_21_19_rsp; - -floo_req_t router_21_19_to_router_21_20_req; -floo_rsp_t router_21_20_to_router_21_19_rsp; - -floo_req_t router_21_19_to_router_22_19_req; -floo_rsp_t router_22_19_to_router_21_19_rsp; - -floo_req_t router_21_19_to_magia_tile_ni_21_19_req; -floo_rsp_t magia_tile_ni_21_19_to_router_21_19_rsp; - -floo_req_t router_21_20_to_router_20_20_req; -floo_rsp_t router_20_20_to_router_21_20_rsp; - -floo_req_t router_21_20_to_router_21_19_req; -floo_rsp_t router_21_19_to_router_21_20_rsp; - -floo_req_t router_21_20_to_router_21_21_req; -floo_rsp_t router_21_21_to_router_21_20_rsp; - -floo_req_t router_21_20_to_router_22_20_req; -floo_rsp_t router_22_20_to_router_21_20_rsp; - -floo_req_t router_21_20_to_magia_tile_ni_21_20_req; -floo_rsp_t magia_tile_ni_21_20_to_router_21_20_rsp; - -floo_req_t router_21_21_to_router_20_21_req; -floo_rsp_t router_20_21_to_router_21_21_rsp; - -floo_req_t router_21_21_to_router_21_20_req; -floo_rsp_t router_21_20_to_router_21_21_rsp; - -floo_req_t router_21_21_to_router_21_22_req; -floo_rsp_t router_21_22_to_router_21_21_rsp; - -floo_req_t router_21_21_to_router_22_21_req; -floo_rsp_t router_22_21_to_router_21_21_rsp; - -floo_req_t router_21_21_to_magia_tile_ni_21_21_req; -floo_rsp_t magia_tile_ni_21_21_to_router_21_21_rsp; - -floo_req_t router_21_22_to_router_20_22_req; -floo_rsp_t router_20_22_to_router_21_22_rsp; - -floo_req_t router_21_22_to_router_21_21_req; -floo_rsp_t router_21_21_to_router_21_22_rsp; - -floo_req_t router_21_22_to_router_21_23_req; -floo_rsp_t router_21_23_to_router_21_22_rsp; - -floo_req_t router_21_22_to_router_22_22_req; -floo_rsp_t router_22_22_to_router_21_22_rsp; - -floo_req_t router_21_22_to_magia_tile_ni_21_22_req; -floo_rsp_t magia_tile_ni_21_22_to_router_21_22_rsp; - -floo_req_t router_21_23_to_router_20_23_req; -floo_rsp_t router_20_23_to_router_21_23_rsp; - -floo_req_t router_21_23_to_router_21_22_req; -floo_rsp_t router_21_22_to_router_21_23_rsp; - -floo_req_t router_21_23_to_router_21_24_req; -floo_rsp_t router_21_24_to_router_21_23_rsp; - -floo_req_t router_21_23_to_router_22_23_req; -floo_rsp_t router_22_23_to_router_21_23_rsp; - -floo_req_t router_21_23_to_magia_tile_ni_21_23_req; -floo_rsp_t magia_tile_ni_21_23_to_router_21_23_rsp; - -floo_req_t router_21_24_to_router_20_24_req; -floo_rsp_t router_20_24_to_router_21_24_rsp; - -floo_req_t router_21_24_to_router_21_23_req; -floo_rsp_t router_21_23_to_router_21_24_rsp; - -floo_req_t router_21_24_to_router_21_25_req; -floo_rsp_t router_21_25_to_router_21_24_rsp; - -floo_req_t router_21_24_to_router_22_24_req; -floo_rsp_t router_22_24_to_router_21_24_rsp; - -floo_req_t router_21_24_to_magia_tile_ni_21_24_req; -floo_rsp_t magia_tile_ni_21_24_to_router_21_24_rsp; - -floo_req_t router_21_25_to_router_20_25_req; -floo_rsp_t router_20_25_to_router_21_25_rsp; - -floo_req_t router_21_25_to_router_21_24_req; -floo_rsp_t router_21_24_to_router_21_25_rsp; - -floo_req_t router_21_25_to_router_21_26_req; -floo_rsp_t router_21_26_to_router_21_25_rsp; - -floo_req_t router_21_25_to_router_22_25_req; -floo_rsp_t router_22_25_to_router_21_25_rsp; - -floo_req_t router_21_25_to_magia_tile_ni_21_25_req; -floo_rsp_t magia_tile_ni_21_25_to_router_21_25_rsp; - -floo_req_t router_21_26_to_router_20_26_req; -floo_rsp_t router_20_26_to_router_21_26_rsp; - -floo_req_t router_21_26_to_router_21_25_req; -floo_rsp_t router_21_25_to_router_21_26_rsp; - -floo_req_t router_21_26_to_router_21_27_req; -floo_rsp_t router_21_27_to_router_21_26_rsp; - -floo_req_t router_21_26_to_router_22_26_req; -floo_rsp_t router_22_26_to_router_21_26_rsp; - -floo_req_t router_21_26_to_magia_tile_ni_21_26_req; -floo_rsp_t magia_tile_ni_21_26_to_router_21_26_rsp; - -floo_req_t router_21_27_to_router_20_27_req; -floo_rsp_t router_20_27_to_router_21_27_rsp; - -floo_req_t router_21_27_to_router_21_26_req; -floo_rsp_t router_21_26_to_router_21_27_rsp; - -floo_req_t router_21_27_to_router_21_28_req; -floo_rsp_t router_21_28_to_router_21_27_rsp; - -floo_req_t router_21_27_to_router_22_27_req; -floo_rsp_t router_22_27_to_router_21_27_rsp; - -floo_req_t router_21_27_to_magia_tile_ni_21_27_req; -floo_rsp_t magia_tile_ni_21_27_to_router_21_27_rsp; - -floo_req_t router_21_28_to_router_20_28_req; -floo_rsp_t router_20_28_to_router_21_28_rsp; - -floo_req_t router_21_28_to_router_21_27_req; -floo_rsp_t router_21_27_to_router_21_28_rsp; - -floo_req_t router_21_28_to_router_21_29_req; -floo_rsp_t router_21_29_to_router_21_28_rsp; - -floo_req_t router_21_28_to_router_22_28_req; -floo_rsp_t router_22_28_to_router_21_28_rsp; - -floo_req_t router_21_28_to_magia_tile_ni_21_28_req; -floo_rsp_t magia_tile_ni_21_28_to_router_21_28_rsp; - -floo_req_t router_21_29_to_router_20_29_req; -floo_rsp_t router_20_29_to_router_21_29_rsp; - -floo_req_t router_21_29_to_router_21_28_req; -floo_rsp_t router_21_28_to_router_21_29_rsp; - -floo_req_t router_21_29_to_router_21_30_req; -floo_rsp_t router_21_30_to_router_21_29_rsp; - -floo_req_t router_21_29_to_router_22_29_req; -floo_rsp_t router_22_29_to_router_21_29_rsp; - -floo_req_t router_21_29_to_magia_tile_ni_21_29_req; -floo_rsp_t magia_tile_ni_21_29_to_router_21_29_rsp; - -floo_req_t router_21_30_to_router_20_30_req; -floo_rsp_t router_20_30_to_router_21_30_rsp; - -floo_req_t router_21_30_to_router_21_29_req; -floo_rsp_t router_21_29_to_router_21_30_rsp; - -floo_req_t router_21_30_to_router_21_31_req; -floo_rsp_t router_21_31_to_router_21_30_rsp; - -floo_req_t router_21_30_to_router_22_30_req; -floo_rsp_t router_22_30_to_router_21_30_rsp; - -floo_req_t router_21_30_to_magia_tile_ni_21_30_req; -floo_rsp_t magia_tile_ni_21_30_to_router_21_30_rsp; - -floo_req_t router_21_31_to_router_20_31_req; -floo_rsp_t router_20_31_to_router_21_31_rsp; - -floo_req_t router_21_31_to_router_21_30_req; -floo_rsp_t router_21_30_to_router_21_31_rsp; - -floo_req_t router_21_31_to_router_22_31_req; -floo_rsp_t router_22_31_to_router_21_31_rsp; - -floo_req_t router_21_31_to_magia_tile_ni_21_31_req; -floo_rsp_t magia_tile_ni_21_31_to_router_21_31_rsp; - -floo_req_t router_22_0_to_router_21_0_req; -floo_rsp_t router_21_0_to_router_22_0_rsp; - -floo_req_t router_22_0_to_router_22_1_req; -floo_rsp_t router_22_1_to_router_22_0_rsp; - -floo_req_t router_22_0_to_router_23_0_req; -floo_rsp_t router_23_0_to_router_22_0_rsp; - -floo_req_t router_22_0_to_magia_tile_ni_22_0_req; -floo_rsp_t magia_tile_ni_22_0_to_router_22_0_rsp; - -floo_req_t router_22_1_to_router_21_1_req; -floo_rsp_t router_21_1_to_router_22_1_rsp; - -floo_req_t router_22_1_to_router_22_0_req; -floo_rsp_t router_22_0_to_router_22_1_rsp; - -floo_req_t router_22_1_to_router_22_2_req; -floo_rsp_t router_22_2_to_router_22_1_rsp; - -floo_req_t router_22_1_to_router_23_1_req; -floo_rsp_t router_23_1_to_router_22_1_rsp; - -floo_req_t router_22_1_to_magia_tile_ni_22_1_req; -floo_rsp_t magia_tile_ni_22_1_to_router_22_1_rsp; - -floo_req_t router_22_2_to_router_21_2_req; -floo_rsp_t router_21_2_to_router_22_2_rsp; - -floo_req_t router_22_2_to_router_22_1_req; -floo_rsp_t router_22_1_to_router_22_2_rsp; - -floo_req_t router_22_2_to_router_22_3_req; -floo_rsp_t router_22_3_to_router_22_2_rsp; - -floo_req_t router_22_2_to_router_23_2_req; -floo_rsp_t router_23_2_to_router_22_2_rsp; - -floo_req_t router_22_2_to_magia_tile_ni_22_2_req; -floo_rsp_t magia_tile_ni_22_2_to_router_22_2_rsp; - -floo_req_t router_22_3_to_router_21_3_req; -floo_rsp_t router_21_3_to_router_22_3_rsp; - -floo_req_t router_22_3_to_router_22_2_req; -floo_rsp_t router_22_2_to_router_22_3_rsp; - -floo_req_t router_22_3_to_router_22_4_req; -floo_rsp_t router_22_4_to_router_22_3_rsp; - -floo_req_t router_22_3_to_router_23_3_req; -floo_rsp_t router_23_3_to_router_22_3_rsp; - -floo_req_t router_22_3_to_magia_tile_ni_22_3_req; -floo_rsp_t magia_tile_ni_22_3_to_router_22_3_rsp; - -floo_req_t router_22_4_to_router_21_4_req; -floo_rsp_t router_21_4_to_router_22_4_rsp; - -floo_req_t router_22_4_to_router_22_3_req; -floo_rsp_t router_22_3_to_router_22_4_rsp; - -floo_req_t router_22_4_to_router_22_5_req; -floo_rsp_t router_22_5_to_router_22_4_rsp; - -floo_req_t router_22_4_to_router_23_4_req; -floo_rsp_t router_23_4_to_router_22_4_rsp; - -floo_req_t router_22_4_to_magia_tile_ni_22_4_req; -floo_rsp_t magia_tile_ni_22_4_to_router_22_4_rsp; - -floo_req_t router_22_5_to_router_21_5_req; -floo_rsp_t router_21_5_to_router_22_5_rsp; - -floo_req_t router_22_5_to_router_22_4_req; -floo_rsp_t router_22_4_to_router_22_5_rsp; - -floo_req_t router_22_5_to_router_22_6_req; -floo_rsp_t router_22_6_to_router_22_5_rsp; - -floo_req_t router_22_5_to_router_23_5_req; -floo_rsp_t router_23_5_to_router_22_5_rsp; - -floo_req_t router_22_5_to_magia_tile_ni_22_5_req; -floo_rsp_t magia_tile_ni_22_5_to_router_22_5_rsp; - -floo_req_t router_22_6_to_router_21_6_req; -floo_rsp_t router_21_6_to_router_22_6_rsp; - -floo_req_t router_22_6_to_router_22_5_req; -floo_rsp_t router_22_5_to_router_22_6_rsp; - -floo_req_t router_22_6_to_router_22_7_req; -floo_rsp_t router_22_7_to_router_22_6_rsp; - -floo_req_t router_22_6_to_router_23_6_req; -floo_rsp_t router_23_6_to_router_22_6_rsp; - -floo_req_t router_22_6_to_magia_tile_ni_22_6_req; -floo_rsp_t magia_tile_ni_22_6_to_router_22_6_rsp; - -floo_req_t router_22_7_to_router_21_7_req; -floo_rsp_t router_21_7_to_router_22_7_rsp; - -floo_req_t router_22_7_to_router_22_6_req; -floo_rsp_t router_22_6_to_router_22_7_rsp; - -floo_req_t router_22_7_to_router_22_8_req; -floo_rsp_t router_22_8_to_router_22_7_rsp; - -floo_req_t router_22_7_to_router_23_7_req; -floo_rsp_t router_23_7_to_router_22_7_rsp; - -floo_req_t router_22_7_to_magia_tile_ni_22_7_req; -floo_rsp_t magia_tile_ni_22_7_to_router_22_7_rsp; - -floo_req_t router_22_8_to_router_21_8_req; -floo_rsp_t router_21_8_to_router_22_8_rsp; - -floo_req_t router_22_8_to_router_22_7_req; -floo_rsp_t router_22_7_to_router_22_8_rsp; - -floo_req_t router_22_8_to_router_22_9_req; -floo_rsp_t router_22_9_to_router_22_8_rsp; - -floo_req_t router_22_8_to_router_23_8_req; -floo_rsp_t router_23_8_to_router_22_8_rsp; - -floo_req_t router_22_8_to_magia_tile_ni_22_8_req; -floo_rsp_t magia_tile_ni_22_8_to_router_22_8_rsp; - -floo_req_t router_22_9_to_router_21_9_req; -floo_rsp_t router_21_9_to_router_22_9_rsp; - -floo_req_t router_22_9_to_router_22_8_req; -floo_rsp_t router_22_8_to_router_22_9_rsp; - -floo_req_t router_22_9_to_router_22_10_req; -floo_rsp_t router_22_10_to_router_22_9_rsp; - -floo_req_t router_22_9_to_router_23_9_req; -floo_rsp_t router_23_9_to_router_22_9_rsp; - -floo_req_t router_22_9_to_magia_tile_ni_22_9_req; -floo_rsp_t magia_tile_ni_22_9_to_router_22_9_rsp; - -floo_req_t router_22_10_to_router_21_10_req; -floo_rsp_t router_21_10_to_router_22_10_rsp; - -floo_req_t router_22_10_to_router_22_9_req; -floo_rsp_t router_22_9_to_router_22_10_rsp; - -floo_req_t router_22_10_to_router_22_11_req; -floo_rsp_t router_22_11_to_router_22_10_rsp; - -floo_req_t router_22_10_to_router_23_10_req; -floo_rsp_t router_23_10_to_router_22_10_rsp; - -floo_req_t router_22_10_to_magia_tile_ni_22_10_req; -floo_rsp_t magia_tile_ni_22_10_to_router_22_10_rsp; - -floo_req_t router_22_11_to_router_21_11_req; -floo_rsp_t router_21_11_to_router_22_11_rsp; - -floo_req_t router_22_11_to_router_22_10_req; -floo_rsp_t router_22_10_to_router_22_11_rsp; - -floo_req_t router_22_11_to_router_22_12_req; -floo_rsp_t router_22_12_to_router_22_11_rsp; - -floo_req_t router_22_11_to_router_23_11_req; -floo_rsp_t router_23_11_to_router_22_11_rsp; - -floo_req_t router_22_11_to_magia_tile_ni_22_11_req; -floo_rsp_t magia_tile_ni_22_11_to_router_22_11_rsp; - -floo_req_t router_22_12_to_router_21_12_req; -floo_rsp_t router_21_12_to_router_22_12_rsp; - -floo_req_t router_22_12_to_router_22_11_req; -floo_rsp_t router_22_11_to_router_22_12_rsp; - -floo_req_t router_22_12_to_router_22_13_req; -floo_rsp_t router_22_13_to_router_22_12_rsp; - -floo_req_t router_22_12_to_router_23_12_req; -floo_rsp_t router_23_12_to_router_22_12_rsp; - -floo_req_t router_22_12_to_magia_tile_ni_22_12_req; -floo_rsp_t magia_tile_ni_22_12_to_router_22_12_rsp; - -floo_req_t router_22_13_to_router_21_13_req; -floo_rsp_t router_21_13_to_router_22_13_rsp; - -floo_req_t router_22_13_to_router_22_12_req; -floo_rsp_t router_22_12_to_router_22_13_rsp; - -floo_req_t router_22_13_to_router_22_14_req; -floo_rsp_t router_22_14_to_router_22_13_rsp; - -floo_req_t router_22_13_to_router_23_13_req; -floo_rsp_t router_23_13_to_router_22_13_rsp; - -floo_req_t router_22_13_to_magia_tile_ni_22_13_req; -floo_rsp_t magia_tile_ni_22_13_to_router_22_13_rsp; - -floo_req_t router_22_14_to_router_21_14_req; -floo_rsp_t router_21_14_to_router_22_14_rsp; - -floo_req_t router_22_14_to_router_22_13_req; -floo_rsp_t router_22_13_to_router_22_14_rsp; - -floo_req_t router_22_14_to_router_22_15_req; -floo_rsp_t router_22_15_to_router_22_14_rsp; - -floo_req_t router_22_14_to_router_23_14_req; -floo_rsp_t router_23_14_to_router_22_14_rsp; - -floo_req_t router_22_14_to_magia_tile_ni_22_14_req; -floo_rsp_t magia_tile_ni_22_14_to_router_22_14_rsp; - -floo_req_t router_22_15_to_router_21_15_req; -floo_rsp_t router_21_15_to_router_22_15_rsp; - -floo_req_t router_22_15_to_router_22_14_req; -floo_rsp_t router_22_14_to_router_22_15_rsp; - -floo_req_t router_22_15_to_router_22_16_req; -floo_rsp_t router_22_16_to_router_22_15_rsp; - -floo_req_t router_22_15_to_router_23_15_req; -floo_rsp_t router_23_15_to_router_22_15_rsp; - -floo_req_t router_22_15_to_magia_tile_ni_22_15_req; -floo_rsp_t magia_tile_ni_22_15_to_router_22_15_rsp; - -floo_req_t router_22_16_to_router_21_16_req; -floo_rsp_t router_21_16_to_router_22_16_rsp; - -floo_req_t router_22_16_to_router_22_15_req; -floo_rsp_t router_22_15_to_router_22_16_rsp; - -floo_req_t router_22_16_to_router_22_17_req; -floo_rsp_t router_22_17_to_router_22_16_rsp; - -floo_req_t router_22_16_to_router_23_16_req; -floo_rsp_t router_23_16_to_router_22_16_rsp; - -floo_req_t router_22_16_to_magia_tile_ni_22_16_req; -floo_rsp_t magia_tile_ni_22_16_to_router_22_16_rsp; - -floo_req_t router_22_17_to_router_21_17_req; -floo_rsp_t router_21_17_to_router_22_17_rsp; - -floo_req_t router_22_17_to_router_22_16_req; -floo_rsp_t router_22_16_to_router_22_17_rsp; - -floo_req_t router_22_17_to_router_22_18_req; -floo_rsp_t router_22_18_to_router_22_17_rsp; - -floo_req_t router_22_17_to_router_23_17_req; -floo_rsp_t router_23_17_to_router_22_17_rsp; - -floo_req_t router_22_17_to_magia_tile_ni_22_17_req; -floo_rsp_t magia_tile_ni_22_17_to_router_22_17_rsp; - -floo_req_t router_22_18_to_router_21_18_req; -floo_rsp_t router_21_18_to_router_22_18_rsp; - -floo_req_t router_22_18_to_router_22_17_req; -floo_rsp_t router_22_17_to_router_22_18_rsp; - -floo_req_t router_22_18_to_router_22_19_req; -floo_rsp_t router_22_19_to_router_22_18_rsp; - -floo_req_t router_22_18_to_router_23_18_req; -floo_rsp_t router_23_18_to_router_22_18_rsp; - -floo_req_t router_22_18_to_magia_tile_ni_22_18_req; -floo_rsp_t magia_tile_ni_22_18_to_router_22_18_rsp; - -floo_req_t router_22_19_to_router_21_19_req; -floo_rsp_t router_21_19_to_router_22_19_rsp; - -floo_req_t router_22_19_to_router_22_18_req; -floo_rsp_t router_22_18_to_router_22_19_rsp; - -floo_req_t router_22_19_to_router_22_20_req; -floo_rsp_t router_22_20_to_router_22_19_rsp; - -floo_req_t router_22_19_to_router_23_19_req; -floo_rsp_t router_23_19_to_router_22_19_rsp; - -floo_req_t router_22_19_to_magia_tile_ni_22_19_req; -floo_rsp_t magia_tile_ni_22_19_to_router_22_19_rsp; - -floo_req_t router_22_20_to_router_21_20_req; -floo_rsp_t router_21_20_to_router_22_20_rsp; - -floo_req_t router_22_20_to_router_22_19_req; -floo_rsp_t router_22_19_to_router_22_20_rsp; - -floo_req_t router_22_20_to_router_22_21_req; -floo_rsp_t router_22_21_to_router_22_20_rsp; - -floo_req_t router_22_20_to_router_23_20_req; -floo_rsp_t router_23_20_to_router_22_20_rsp; - -floo_req_t router_22_20_to_magia_tile_ni_22_20_req; -floo_rsp_t magia_tile_ni_22_20_to_router_22_20_rsp; - -floo_req_t router_22_21_to_router_21_21_req; -floo_rsp_t router_21_21_to_router_22_21_rsp; - -floo_req_t router_22_21_to_router_22_20_req; -floo_rsp_t router_22_20_to_router_22_21_rsp; - -floo_req_t router_22_21_to_router_22_22_req; -floo_rsp_t router_22_22_to_router_22_21_rsp; - -floo_req_t router_22_21_to_router_23_21_req; -floo_rsp_t router_23_21_to_router_22_21_rsp; - -floo_req_t router_22_21_to_magia_tile_ni_22_21_req; -floo_rsp_t magia_tile_ni_22_21_to_router_22_21_rsp; - -floo_req_t router_22_22_to_router_21_22_req; -floo_rsp_t router_21_22_to_router_22_22_rsp; - -floo_req_t router_22_22_to_router_22_21_req; -floo_rsp_t router_22_21_to_router_22_22_rsp; - -floo_req_t router_22_22_to_router_22_23_req; -floo_rsp_t router_22_23_to_router_22_22_rsp; - -floo_req_t router_22_22_to_router_23_22_req; -floo_rsp_t router_23_22_to_router_22_22_rsp; - -floo_req_t router_22_22_to_magia_tile_ni_22_22_req; -floo_rsp_t magia_tile_ni_22_22_to_router_22_22_rsp; - -floo_req_t router_22_23_to_router_21_23_req; -floo_rsp_t router_21_23_to_router_22_23_rsp; - -floo_req_t router_22_23_to_router_22_22_req; -floo_rsp_t router_22_22_to_router_22_23_rsp; - -floo_req_t router_22_23_to_router_22_24_req; -floo_rsp_t router_22_24_to_router_22_23_rsp; - -floo_req_t router_22_23_to_router_23_23_req; -floo_rsp_t router_23_23_to_router_22_23_rsp; - -floo_req_t router_22_23_to_magia_tile_ni_22_23_req; -floo_rsp_t magia_tile_ni_22_23_to_router_22_23_rsp; - -floo_req_t router_22_24_to_router_21_24_req; -floo_rsp_t router_21_24_to_router_22_24_rsp; - -floo_req_t router_22_24_to_router_22_23_req; -floo_rsp_t router_22_23_to_router_22_24_rsp; - -floo_req_t router_22_24_to_router_22_25_req; -floo_rsp_t router_22_25_to_router_22_24_rsp; - -floo_req_t router_22_24_to_router_23_24_req; -floo_rsp_t router_23_24_to_router_22_24_rsp; - -floo_req_t router_22_24_to_magia_tile_ni_22_24_req; -floo_rsp_t magia_tile_ni_22_24_to_router_22_24_rsp; - -floo_req_t router_22_25_to_router_21_25_req; -floo_rsp_t router_21_25_to_router_22_25_rsp; - -floo_req_t router_22_25_to_router_22_24_req; -floo_rsp_t router_22_24_to_router_22_25_rsp; - -floo_req_t router_22_25_to_router_22_26_req; -floo_rsp_t router_22_26_to_router_22_25_rsp; - -floo_req_t router_22_25_to_router_23_25_req; -floo_rsp_t router_23_25_to_router_22_25_rsp; - -floo_req_t router_22_25_to_magia_tile_ni_22_25_req; -floo_rsp_t magia_tile_ni_22_25_to_router_22_25_rsp; - -floo_req_t router_22_26_to_router_21_26_req; -floo_rsp_t router_21_26_to_router_22_26_rsp; - -floo_req_t router_22_26_to_router_22_25_req; -floo_rsp_t router_22_25_to_router_22_26_rsp; - -floo_req_t router_22_26_to_router_22_27_req; -floo_rsp_t router_22_27_to_router_22_26_rsp; - -floo_req_t router_22_26_to_router_23_26_req; -floo_rsp_t router_23_26_to_router_22_26_rsp; - -floo_req_t router_22_26_to_magia_tile_ni_22_26_req; -floo_rsp_t magia_tile_ni_22_26_to_router_22_26_rsp; - -floo_req_t router_22_27_to_router_21_27_req; -floo_rsp_t router_21_27_to_router_22_27_rsp; - -floo_req_t router_22_27_to_router_22_26_req; -floo_rsp_t router_22_26_to_router_22_27_rsp; - -floo_req_t router_22_27_to_router_22_28_req; -floo_rsp_t router_22_28_to_router_22_27_rsp; - -floo_req_t router_22_27_to_router_23_27_req; -floo_rsp_t router_23_27_to_router_22_27_rsp; - -floo_req_t router_22_27_to_magia_tile_ni_22_27_req; -floo_rsp_t magia_tile_ni_22_27_to_router_22_27_rsp; - -floo_req_t router_22_28_to_router_21_28_req; -floo_rsp_t router_21_28_to_router_22_28_rsp; - -floo_req_t router_22_28_to_router_22_27_req; -floo_rsp_t router_22_27_to_router_22_28_rsp; - -floo_req_t router_22_28_to_router_22_29_req; -floo_rsp_t router_22_29_to_router_22_28_rsp; - -floo_req_t router_22_28_to_router_23_28_req; -floo_rsp_t router_23_28_to_router_22_28_rsp; - -floo_req_t router_22_28_to_magia_tile_ni_22_28_req; -floo_rsp_t magia_tile_ni_22_28_to_router_22_28_rsp; - -floo_req_t router_22_29_to_router_21_29_req; -floo_rsp_t router_21_29_to_router_22_29_rsp; - -floo_req_t router_22_29_to_router_22_28_req; -floo_rsp_t router_22_28_to_router_22_29_rsp; - -floo_req_t router_22_29_to_router_22_30_req; -floo_rsp_t router_22_30_to_router_22_29_rsp; - -floo_req_t router_22_29_to_router_23_29_req; -floo_rsp_t router_23_29_to_router_22_29_rsp; - -floo_req_t router_22_29_to_magia_tile_ni_22_29_req; -floo_rsp_t magia_tile_ni_22_29_to_router_22_29_rsp; - -floo_req_t router_22_30_to_router_21_30_req; -floo_rsp_t router_21_30_to_router_22_30_rsp; - -floo_req_t router_22_30_to_router_22_29_req; -floo_rsp_t router_22_29_to_router_22_30_rsp; - -floo_req_t router_22_30_to_router_22_31_req; -floo_rsp_t router_22_31_to_router_22_30_rsp; - -floo_req_t router_22_30_to_router_23_30_req; -floo_rsp_t router_23_30_to_router_22_30_rsp; - -floo_req_t router_22_30_to_magia_tile_ni_22_30_req; -floo_rsp_t magia_tile_ni_22_30_to_router_22_30_rsp; - -floo_req_t router_22_31_to_router_21_31_req; -floo_rsp_t router_21_31_to_router_22_31_rsp; - -floo_req_t router_22_31_to_router_22_30_req; -floo_rsp_t router_22_30_to_router_22_31_rsp; - -floo_req_t router_22_31_to_router_23_31_req; -floo_rsp_t router_23_31_to_router_22_31_rsp; - -floo_req_t router_22_31_to_magia_tile_ni_22_31_req; -floo_rsp_t magia_tile_ni_22_31_to_router_22_31_rsp; - -floo_req_t router_23_0_to_router_22_0_req; -floo_rsp_t router_22_0_to_router_23_0_rsp; - -floo_req_t router_23_0_to_router_23_1_req; -floo_rsp_t router_23_1_to_router_23_0_rsp; - -floo_req_t router_23_0_to_router_24_0_req; -floo_rsp_t router_24_0_to_router_23_0_rsp; - -floo_req_t router_23_0_to_magia_tile_ni_23_0_req; -floo_rsp_t magia_tile_ni_23_0_to_router_23_0_rsp; - -floo_req_t router_23_1_to_router_22_1_req; -floo_rsp_t router_22_1_to_router_23_1_rsp; - -floo_req_t router_23_1_to_router_23_0_req; -floo_rsp_t router_23_0_to_router_23_1_rsp; - -floo_req_t router_23_1_to_router_23_2_req; -floo_rsp_t router_23_2_to_router_23_1_rsp; - -floo_req_t router_23_1_to_router_24_1_req; -floo_rsp_t router_24_1_to_router_23_1_rsp; - -floo_req_t router_23_1_to_magia_tile_ni_23_1_req; -floo_rsp_t magia_tile_ni_23_1_to_router_23_1_rsp; - -floo_req_t router_23_2_to_router_22_2_req; -floo_rsp_t router_22_2_to_router_23_2_rsp; - -floo_req_t router_23_2_to_router_23_1_req; -floo_rsp_t router_23_1_to_router_23_2_rsp; - -floo_req_t router_23_2_to_router_23_3_req; -floo_rsp_t router_23_3_to_router_23_2_rsp; - -floo_req_t router_23_2_to_router_24_2_req; -floo_rsp_t router_24_2_to_router_23_2_rsp; - -floo_req_t router_23_2_to_magia_tile_ni_23_2_req; -floo_rsp_t magia_tile_ni_23_2_to_router_23_2_rsp; - -floo_req_t router_23_3_to_router_22_3_req; -floo_rsp_t router_22_3_to_router_23_3_rsp; - -floo_req_t router_23_3_to_router_23_2_req; -floo_rsp_t router_23_2_to_router_23_3_rsp; - -floo_req_t router_23_3_to_router_23_4_req; -floo_rsp_t router_23_4_to_router_23_3_rsp; - -floo_req_t router_23_3_to_router_24_3_req; -floo_rsp_t router_24_3_to_router_23_3_rsp; - -floo_req_t router_23_3_to_magia_tile_ni_23_3_req; -floo_rsp_t magia_tile_ni_23_3_to_router_23_3_rsp; - -floo_req_t router_23_4_to_router_22_4_req; -floo_rsp_t router_22_4_to_router_23_4_rsp; - -floo_req_t router_23_4_to_router_23_3_req; -floo_rsp_t router_23_3_to_router_23_4_rsp; - -floo_req_t router_23_4_to_router_23_5_req; -floo_rsp_t router_23_5_to_router_23_4_rsp; - -floo_req_t router_23_4_to_router_24_4_req; -floo_rsp_t router_24_4_to_router_23_4_rsp; - -floo_req_t router_23_4_to_magia_tile_ni_23_4_req; -floo_rsp_t magia_tile_ni_23_4_to_router_23_4_rsp; - -floo_req_t router_23_5_to_router_22_5_req; -floo_rsp_t router_22_5_to_router_23_5_rsp; - -floo_req_t router_23_5_to_router_23_4_req; -floo_rsp_t router_23_4_to_router_23_5_rsp; - -floo_req_t router_23_5_to_router_23_6_req; -floo_rsp_t router_23_6_to_router_23_5_rsp; - -floo_req_t router_23_5_to_router_24_5_req; -floo_rsp_t router_24_5_to_router_23_5_rsp; - -floo_req_t router_23_5_to_magia_tile_ni_23_5_req; -floo_rsp_t magia_tile_ni_23_5_to_router_23_5_rsp; - -floo_req_t router_23_6_to_router_22_6_req; -floo_rsp_t router_22_6_to_router_23_6_rsp; - -floo_req_t router_23_6_to_router_23_5_req; -floo_rsp_t router_23_5_to_router_23_6_rsp; - -floo_req_t router_23_6_to_router_23_7_req; -floo_rsp_t router_23_7_to_router_23_6_rsp; - -floo_req_t router_23_6_to_router_24_6_req; -floo_rsp_t router_24_6_to_router_23_6_rsp; - -floo_req_t router_23_6_to_magia_tile_ni_23_6_req; -floo_rsp_t magia_tile_ni_23_6_to_router_23_6_rsp; - -floo_req_t router_23_7_to_router_22_7_req; -floo_rsp_t router_22_7_to_router_23_7_rsp; - -floo_req_t router_23_7_to_router_23_6_req; -floo_rsp_t router_23_6_to_router_23_7_rsp; - -floo_req_t router_23_7_to_router_23_8_req; -floo_rsp_t router_23_8_to_router_23_7_rsp; - -floo_req_t router_23_7_to_router_24_7_req; -floo_rsp_t router_24_7_to_router_23_7_rsp; - -floo_req_t router_23_7_to_magia_tile_ni_23_7_req; -floo_rsp_t magia_tile_ni_23_7_to_router_23_7_rsp; - -floo_req_t router_23_8_to_router_22_8_req; -floo_rsp_t router_22_8_to_router_23_8_rsp; - -floo_req_t router_23_8_to_router_23_7_req; -floo_rsp_t router_23_7_to_router_23_8_rsp; - -floo_req_t router_23_8_to_router_23_9_req; -floo_rsp_t router_23_9_to_router_23_8_rsp; - -floo_req_t router_23_8_to_router_24_8_req; -floo_rsp_t router_24_8_to_router_23_8_rsp; - -floo_req_t router_23_8_to_magia_tile_ni_23_8_req; -floo_rsp_t magia_tile_ni_23_8_to_router_23_8_rsp; - -floo_req_t router_23_9_to_router_22_9_req; -floo_rsp_t router_22_9_to_router_23_9_rsp; - -floo_req_t router_23_9_to_router_23_8_req; -floo_rsp_t router_23_8_to_router_23_9_rsp; - -floo_req_t router_23_9_to_router_23_10_req; -floo_rsp_t router_23_10_to_router_23_9_rsp; - -floo_req_t router_23_9_to_router_24_9_req; -floo_rsp_t router_24_9_to_router_23_9_rsp; - -floo_req_t router_23_9_to_magia_tile_ni_23_9_req; -floo_rsp_t magia_tile_ni_23_9_to_router_23_9_rsp; - -floo_req_t router_23_10_to_router_22_10_req; -floo_rsp_t router_22_10_to_router_23_10_rsp; - -floo_req_t router_23_10_to_router_23_9_req; -floo_rsp_t router_23_9_to_router_23_10_rsp; - -floo_req_t router_23_10_to_router_23_11_req; -floo_rsp_t router_23_11_to_router_23_10_rsp; - -floo_req_t router_23_10_to_router_24_10_req; -floo_rsp_t router_24_10_to_router_23_10_rsp; - -floo_req_t router_23_10_to_magia_tile_ni_23_10_req; -floo_rsp_t magia_tile_ni_23_10_to_router_23_10_rsp; - -floo_req_t router_23_11_to_router_22_11_req; -floo_rsp_t router_22_11_to_router_23_11_rsp; - -floo_req_t router_23_11_to_router_23_10_req; -floo_rsp_t router_23_10_to_router_23_11_rsp; - -floo_req_t router_23_11_to_router_23_12_req; -floo_rsp_t router_23_12_to_router_23_11_rsp; - -floo_req_t router_23_11_to_router_24_11_req; -floo_rsp_t router_24_11_to_router_23_11_rsp; - -floo_req_t router_23_11_to_magia_tile_ni_23_11_req; -floo_rsp_t magia_tile_ni_23_11_to_router_23_11_rsp; - -floo_req_t router_23_12_to_router_22_12_req; -floo_rsp_t router_22_12_to_router_23_12_rsp; - -floo_req_t router_23_12_to_router_23_11_req; -floo_rsp_t router_23_11_to_router_23_12_rsp; - -floo_req_t router_23_12_to_router_23_13_req; -floo_rsp_t router_23_13_to_router_23_12_rsp; - -floo_req_t router_23_12_to_router_24_12_req; -floo_rsp_t router_24_12_to_router_23_12_rsp; - -floo_req_t router_23_12_to_magia_tile_ni_23_12_req; -floo_rsp_t magia_tile_ni_23_12_to_router_23_12_rsp; - -floo_req_t router_23_13_to_router_22_13_req; -floo_rsp_t router_22_13_to_router_23_13_rsp; - -floo_req_t router_23_13_to_router_23_12_req; -floo_rsp_t router_23_12_to_router_23_13_rsp; - -floo_req_t router_23_13_to_router_23_14_req; -floo_rsp_t router_23_14_to_router_23_13_rsp; - -floo_req_t router_23_13_to_router_24_13_req; -floo_rsp_t router_24_13_to_router_23_13_rsp; - -floo_req_t router_23_13_to_magia_tile_ni_23_13_req; -floo_rsp_t magia_tile_ni_23_13_to_router_23_13_rsp; - -floo_req_t router_23_14_to_router_22_14_req; -floo_rsp_t router_22_14_to_router_23_14_rsp; - -floo_req_t router_23_14_to_router_23_13_req; -floo_rsp_t router_23_13_to_router_23_14_rsp; - -floo_req_t router_23_14_to_router_23_15_req; -floo_rsp_t router_23_15_to_router_23_14_rsp; - -floo_req_t router_23_14_to_router_24_14_req; -floo_rsp_t router_24_14_to_router_23_14_rsp; - -floo_req_t router_23_14_to_magia_tile_ni_23_14_req; -floo_rsp_t magia_tile_ni_23_14_to_router_23_14_rsp; - -floo_req_t router_23_15_to_router_22_15_req; -floo_rsp_t router_22_15_to_router_23_15_rsp; - -floo_req_t router_23_15_to_router_23_14_req; -floo_rsp_t router_23_14_to_router_23_15_rsp; - -floo_req_t router_23_15_to_router_23_16_req; -floo_rsp_t router_23_16_to_router_23_15_rsp; - -floo_req_t router_23_15_to_router_24_15_req; -floo_rsp_t router_24_15_to_router_23_15_rsp; - -floo_req_t router_23_15_to_magia_tile_ni_23_15_req; -floo_rsp_t magia_tile_ni_23_15_to_router_23_15_rsp; - -floo_req_t router_23_16_to_router_22_16_req; -floo_rsp_t router_22_16_to_router_23_16_rsp; - -floo_req_t router_23_16_to_router_23_15_req; -floo_rsp_t router_23_15_to_router_23_16_rsp; - -floo_req_t router_23_16_to_router_23_17_req; -floo_rsp_t router_23_17_to_router_23_16_rsp; - -floo_req_t router_23_16_to_router_24_16_req; -floo_rsp_t router_24_16_to_router_23_16_rsp; - -floo_req_t router_23_16_to_magia_tile_ni_23_16_req; -floo_rsp_t magia_tile_ni_23_16_to_router_23_16_rsp; - -floo_req_t router_23_17_to_router_22_17_req; -floo_rsp_t router_22_17_to_router_23_17_rsp; - -floo_req_t router_23_17_to_router_23_16_req; -floo_rsp_t router_23_16_to_router_23_17_rsp; - -floo_req_t router_23_17_to_router_23_18_req; -floo_rsp_t router_23_18_to_router_23_17_rsp; - -floo_req_t router_23_17_to_router_24_17_req; -floo_rsp_t router_24_17_to_router_23_17_rsp; - -floo_req_t router_23_17_to_magia_tile_ni_23_17_req; -floo_rsp_t magia_tile_ni_23_17_to_router_23_17_rsp; - -floo_req_t router_23_18_to_router_22_18_req; -floo_rsp_t router_22_18_to_router_23_18_rsp; - -floo_req_t router_23_18_to_router_23_17_req; -floo_rsp_t router_23_17_to_router_23_18_rsp; - -floo_req_t router_23_18_to_router_23_19_req; -floo_rsp_t router_23_19_to_router_23_18_rsp; - -floo_req_t router_23_18_to_router_24_18_req; -floo_rsp_t router_24_18_to_router_23_18_rsp; - -floo_req_t router_23_18_to_magia_tile_ni_23_18_req; -floo_rsp_t magia_tile_ni_23_18_to_router_23_18_rsp; - -floo_req_t router_23_19_to_router_22_19_req; -floo_rsp_t router_22_19_to_router_23_19_rsp; - -floo_req_t router_23_19_to_router_23_18_req; -floo_rsp_t router_23_18_to_router_23_19_rsp; - -floo_req_t router_23_19_to_router_23_20_req; -floo_rsp_t router_23_20_to_router_23_19_rsp; - -floo_req_t router_23_19_to_router_24_19_req; -floo_rsp_t router_24_19_to_router_23_19_rsp; - -floo_req_t router_23_19_to_magia_tile_ni_23_19_req; -floo_rsp_t magia_tile_ni_23_19_to_router_23_19_rsp; - -floo_req_t router_23_20_to_router_22_20_req; -floo_rsp_t router_22_20_to_router_23_20_rsp; - -floo_req_t router_23_20_to_router_23_19_req; -floo_rsp_t router_23_19_to_router_23_20_rsp; - -floo_req_t router_23_20_to_router_23_21_req; -floo_rsp_t router_23_21_to_router_23_20_rsp; - -floo_req_t router_23_20_to_router_24_20_req; -floo_rsp_t router_24_20_to_router_23_20_rsp; - -floo_req_t router_23_20_to_magia_tile_ni_23_20_req; -floo_rsp_t magia_tile_ni_23_20_to_router_23_20_rsp; - -floo_req_t router_23_21_to_router_22_21_req; -floo_rsp_t router_22_21_to_router_23_21_rsp; - -floo_req_t router_23_21_to_router_23_20_req; -floo_rsp_t router_23_20_to_router_23_21_rsp; - -floo_req_t router_23_21_to_router_23_22_req; -floo_rsp_t router_23_22_to_router_23_21_rsp; - -floo_req_t router_23_21_to_router_24_21_req; -floo_rsp_t router_24_21_to_router_23_21_rsp; - -floo_req_t router_23_21_to_magia_tile_ni_23_21_req; -floo_rsp_t magia_tile_ni_23_21_to_router_23_21_rsp; - -floo_req_t router_23_22_to_router_22_22_req; -floo_rsp_t router_22_22_to_router_23_22_rsp; - -floo_req_t router_23_22_to_router_23_21_req; -floo_rsp_t router_23_21_to_router_23_22_rsp; - -floo_req_t router_23_22_to_router_23_23_req; -floo_rsp_t router_23_23_to_router_23_22_rsp; - -floo_req_t router_23_22_to_router_24_22_req; -floo_rsp_t router_24_22_to_router_23_22_rsp; - -floo_req_t router_23_22_to_magia_tile_ni_23_22_req; -floo_rsp_t magia_tile_ni_23_22_to_router_23_22_rsp; - -floo_req_t router_23_23_to_router_22_23_req; -floo_rsp_t router_22_23_to_router_23_23_rsp; - -floo_req_t router_23_23_to_router_23_22_req; -floo_rsp_t router_23_22_to_router_23_23_rsp; - -floo_req_t router_23_23_to_router_23_24_req; -floo_rsp_t router_23_24_to_router_23_23_rsp; - -floo_req_t router_23_23_to_router_24_23_req; -floo_rsp_t router_24_23_to_router_23_23_rsp; - -floo_req_t router_23_23_to_magia_tile_ni_23_23_req; -floo_rsp_t magia_tile_ni_23_23_to_router_23_23_rsp; - -floo_req_t router_23_24_to_router_22_24_req; -floo_rsp_t router_22_24_to_router_23_24_rsp; - -floo_req_t router_23_24_to_router_23_23_req; -floo_rsp_t router_23_23_to_router_23_24_rsp; - -floo_req_t router_23_24_to_router_23_25_req; -floo_rsp_t router_23_25_to_router_23_24_rsp; - -floo_req_t router_23_24_to_router_24_24_req; -floo_rsp_t router_24_24_to_router_23_24_rsp; - -floo_req_t router_23_24_to_magia_tile_ni_23_24_req; -floo_rsp_t magia_tile_ni_23_24_to_router_23_24_rsp; - -floo_req_t router_23_25_to_router_22_25_req; -floo_rsp_t router_22_25_to_router_23_25_rsp; - -floo_req_t router_23_25_to_router_23_24_req; -floo_rsp_t router_23_24_to_router_23_25_rsp; - -floo_req_t router_23_25_to_router_23_26_req; -floo_rsp_t router_23_26_to_router_23_25_rsp; - -floo_req_t router_23_25_to_router_24_25_req; -floo_rsp_t router_24_25_to_router_23_25_rsp; - -floo_req_t router_23_25_to_magia_tile_ni_23_25_req; -floo_rsp_t magia_tile_ni_23_25_to_router_23_25_rsp; - -floo_req_t router_23_26_to_router_22_26_req; -floo_rsp_t router_22_26_to_router_23_26_rsp; - -floo_req_t router_23_26_to_router_23_25_req; -floo_rsp_t router_23_25_to_router_23_26_rsp; - -floo_req_t router_23_26_to_router_23_27_req; -floo_rsp_t router_23_27_to_router_23_26_rsp; - -floo_req_t router_23_26_to_router_24_26_req; -floo_rsp_t router_24_26_to_router_23_26_rsp; - -floo_req_t router_23_26_to_magia_tile_ni_23_26_req; -floo_rsp_t magia_tile_ni_23_26_to_router_23_26_rsp; - -floo_req_t router_23_27_to_router_22_27_req; -floo_rsp_t router_22_27_to_router_23_27_rsp; - -floo_req_t router_23_27_to_router_23_26_req; -floo_rsp_t router_23_26_to_router_23_27_rsp; - -floo_req_t router_23_27_to_router_23_28_req; -floo_rsp_t router_23_28_to_router_23_27_rsp; - -floo_req_t router_23_27_to_router_24_27_req; -floo_rsp_t router_24_27_to_router_23_27_rsp; - -floo_req_t router_23_27_to_magia_tile_ni_23_27_req; -floo_rsp_t magia_tile_ni_23_27_to_router_23_27_rsp; - -floo_req_t router_23_28_to_router_22_28_req; -floo_rsp_t router_22_28_to_router_23_28_rsp; - -floo_req_t router_23_28_to_router_23_27_req; -floo_rsp_t router_23_27_to_router_23_28_rsp; - -floo_req_t router_23_28_to_router_23_29_req; -floo_rsp_t router_23_29_to_router_23_28_rsp; - -floo_req_t router_23_28_to_router_24_28_req; -floo_rsp_t router_24_28_to_router_23_28_rsp; - -floo_req_t router_23_28_to_magia_tile_ni_23_28_req; -floo_rsp_t magia_tile_ni_23_28_to_router_23_28_rsp; - -floo_req_t router_23_29_to_router_22_29_req; -floo_rsp_t router_22_29_to_router_23_29_rsp; - -floo_req_t router_23_29_to_router_23_28_req; -floo_rsp_t router_23_28_to_router_23_29_rsp; - -floo_req_t router_23_29_to_router_23_30_req; -floo_rsp_t router_23_30_to_router_23_29_rsp; - -floo_req_t router_23_29_to_router_24_29_req; -floo_rsp_t router_24_29_to_router_23_29_rsp; - -floo_req_t router_23_29_to_magia_tile_ni_23_29_req; -floo_rsp_t magia_tile_ni_23_29_to_router_23_29_rsp; - -floo_req_t router_23_30_to_router_22_30_req; -floo_rsp_t router_22_30_to_router_23_30_rsp; - -floo_req_t router_23_30_to_router_23_29_req; -floo_rsp_t router_23_29_to_router_23_30_rsp; - -floo_req_t router_23_30_to_router_23_31_req; -floo_rsp_t router_23_31_to_router_23_30_rsp; - -floo_req_t router_23_30_to_router_24_30_req; -floo_rsp_t router_24_30_to_router_23_30_rsp; - -floo_req_t router_23_30_to_magia_tile_ni_23_30_req; -floo_rsp_t magia_tile_ni_23_30_to_router_23_30_rsp; - -floo_req_t router_23_31_to_router_22_31_req; -floo_rsp_t router_22_31_to_router_23_31_rsp; - -floo_req_t router_23_31_to_router_23_30_req; -floo_rsp_t router_23_30_to_router_23_31_rsp; - -floo_req_t router_23_31_to_router_24_31_req; -floo_rsp_t router_24_31_to_router_23_31_rsp; - -floo_req_t router_23_31_to_magia_tile_ni_23_31_req; -floo_rsp_t magia_tile_ni_23_31_to_router_23_31_rsp; - -floo_req_t router_24_0_to_router_23_0_req; -floo_rsp_t router_23_0_to_router_24_0_rsp; - -floo_req_t router_24_0_to_router_24_1_req; -floo_rsp_t router_24_1_to_router_24_0_rsp; - -floo_req_t router_24_0_to_router_25_0_req; -floo_rsp_t router_25_0_to_router_24_0_rsp; - -floo_req_t router_24_0_to_magia_tile_ni_24_0_req; -floo_rsp_t magia_tile_ni_24_0_to_router_24_0_rsp; - -floo_req_t router_24_1_to_router_23_1_req; -floo_rsp_t router_23_1_to_router_24_1_rsp; - -floo_req_t router_24_1_to_router_24_0_req; -floo_rsp_t router_24_0_to_router_24_1_rsp; - -floo_req_t router_24_1_to_router_24_2_req; -floo_rsp_t router_24_2_to_router_24_1_rsp; - -floo_req_t router_24_1_to_router_25_1_req; -floo_rsp_t router_25_1_to_router_24_1_rsp; - -floo_req_t router_24_1_to_magia_tile_ni_24_1_req; -floo_rsp_t magia_tile_ni_24_1_to_router_24_1_rsp; - -floo_req_t router_24_2_to_router_23_2_req; -floo_rsp_t router_23_2_to_router_24_2_rsp; - -floo_req_t router_24_2_to_router_24_1_req; -floo_rsp_t router_24_1_to_router_24_2_rsp; - -floo_req_t router_24_2_to_router_24_3_req; -floo_rsp_t router_24_3_to_router_24_2_rsp; - -floo_req_t router_24_2_to_router_25_2_req; -floo_rsp_t router_25_2_to_router_24_2_rsp; - -floo_req_t router_24_2_to_magia_tile_ni_24_2_req; -floo_rsp_t magia_tile_ni_24_2_to_router_24_2_rsp; - -floo_req_t router_24_3_to_router_23_3_req; -floo_rsp_t router_23_3_to_router_24_3_rsp; - -floo_req_t router_24_3_to_router_24_2_req; -floo_rsp_t router_24_2_to_router_24_3_rsp; - -floo_req_t router_24_3_to_router_24_4_req; -floo_rsp_t router_24_4_to_router_24_3_rsp; - -floo_req_t router_24_3_to_router_25_3_req; -floo_rsp_t router_25_3_to_router_24_3_rsp; - -floo_req_t router_24_3_to_magia_tile_ni_24_3_req; -floo_rsp_t magia_tile_ni_24_3_to_router_24_3_rsp; - -floo_req_t router_24_4_to_router_23_4_req; -floo_rsp_t router_23_4_to_router_24_4_rsp; - -floo_req_t router_24_4_to_router_24_3_req; -floo_rsp_t router_24_3_to_router_24_4_rsp; - -floo_req_t router_24_4_to_router_24_5_req; -floo_rsp_t router_24_5_to_router_24_4_rsp; - -floo_req_t router_24_4_to_router_25_4_req; -floo_rsp_t router_25_4_to_router_24_4_rsp; - -floo_req_t router_24_4_to_magia_tile_ni_24_4_req; -floo_rsp_t magia_tile_ni_24_4_to_router_24_4_rsp; - -floo_req_t router_24_5_to_router_23_5_req; -floo_rsp_t router_23_5_to_router_24_5_rsp; - -floo_req_t router_24_5_to_router_24_4_req; -floo_rsp_t router_24_4_to_router_24_5_rsp; - -floo_req_t router_24_5_to_router_24_6_req; -floo_rsp_t router_24_6_to_router_24_5_rsp; - -floo_req_t router_24_5_to_router_25_5_req; -floo_rsp_t router_25_5_to_router_24_5_rsp; - -floo_req_t router_24_5_to_magia_tile_ni_24_5_req; -floo_rsp_t magia_tile_ni_24_5_to_router_24_5_rsp; - -floo_req_t router_24_6_to_router_23_6_req; -floo_rsp_t router_23_6_to_router_24_6_rsp; - -floo_req_t router_24_6_to_router_24_5_req; -floo_rsp_t router_24_5_to_router_24_6_rsp; - -floo_req_t router_24_6_to_router_24_7_req; -floo_rsp_t router_24_7_to_router_24_6_rsp; - -floo_req_t router_24_6_to_router_25_6_req; -floo_rsp_t router_25_6_to_router_24_6_rsp; - -floo_req_t router_24_6_to_magia_tile_ni_24_6_req; -floo_rsp_t magia_tile_ni_24_6_to_router_24_6_rsp; - -floo_req_t router_24_7_to_router_23_7_req; -floo_rsp_t router_23_7_to_router_24_7_rsp; - -floo_req_t router_24_7_to_router_24_6_req; -floo_rsp_t router_24_6_to_router_24_7_rsp; - -floo_req_t router_24_7_to_router_24_8_req; -floo_rsp_t router_24_8_to_router_24_7_rsp; - -floo_req_t router_24_7_to_router_25_7_req; -floo_rsp_t router_25_7_to_router_24_7_rsp; - -floo_req_t router_24_7_to_magia_tile_ni_24_7_req; -floo_rsp_t magia_tile_ni_24_7_to_router_24_7_rsp; - -floo_req_t router_24_8_to_router_23_8_req; -floo_rsp_t router_23_8_to_router_24_8_rsp; - -floo_req_t router_24_8_to_router_24_7_req; -floo_rsp_t router_24_7_to_router_24_8_rsp; - -floo_req_t router_24_8_to_router_24_9_req; -floo_rsp_t router_24_9_to_router_24_8_rsp; - -floo_req_t router_24_8_to_router_25_8_req; -floo_rsp_t router_25_8_to_router_24_8_rsp; - -floo_req_t router_24_8_to_magia_tile_ni_24_8_req; -floo_rsp_t magia_tile_ni_24_8_to_router_24_8_rsp; - -floo_req_t router_24_9_to_router_23_9_req; -floo_rsp_t router_23_9_to_router_24_9_rsp; - -floo_req_t router_24_9_to_router_24_8_req; -floo_rsp_t router_24_8_to_router_24_9_rsp; - -floo_req_t router_24_9_to_router_24_10_req; -floo_rsp_t router_24_10_to_router_24_9_rsp; - -floo_req_t router_24_9_to_router_25_9_req; -floo_rsp_t router_25_9_to_router_24_9_rsp; - -floo_req_t router_24_9_to_magia_tile_ni_24_9_req; -floo_rsp_t magia_tile_ni_24_9_to_router_24_9_rsp; - -floo_req_t router_24_10_to_router_23_10_req; -floo_rsp_t router_23_10_to_router_24_10_rsp; - -floo_req_t router_24_10_to_router_24_9_req; -floo_rsp_t router_24_9_to_router_24_10_rsp; - -floo_req_t router_24_10_to_router_24_11_req; -floo_rsp_t router_24_11_to_router_24_10_rsp; - -floo_req_t router_24_10_to_router_25_10_req; -floo_rsp_t router_25_10_to_router_24_10_rsp; - -floo_req_t router_24_10_to_magia_tile_ni_24_10_req; -floo_rsp_t magia_tile_ni_24_10_to_router_24_10_rsp; - -floo_req_t router_24_11_to_router_23_11_req; -floo_rsp_t router_23_11_to_router_24_11_rsp; - -floo_req_t router_24_11_to_router_24_10_req; -floo_rsp_t router_24_10_to_router_24_11_rsp; - -floo_req_t router_24_11_to_router_24_12_req; -floo_rsp_t router_24_12_to_router_24_11_rsp; - -floo_req_t router_24_11_to_router_25_11_req; -floo_rsp_t router_25_11_to_router_24_11_rsp; - -floo_req_t router_24_11_to_magia_tile_ni_24_11_req; -floo_rsp_t magia_tile_ni_24_11_to_router_24_11_rsp; - -floo_req_t router_24_12_to_router_23_12_req; -floo_rsp_t router_23_12_to_router_24_12_rsp; - -floo_req_t router_24_12_to_router_24_11_req; -floo_rsp_t router_24_11_to_router_24_12_rsp; - -floo_req_t router_24_12_to_router_24_13_req; -floo_rsp_t router_24_13_to_router_24_12_rsp; - -floo_req_t router_24_12_to_router_25_12_req; -floo_rsp_t router_25_12_to_router_24_12_rsp; - -floo_req_t router_24_12_to_magia_tile_ni_24_12_req; -floo_rsp_t magia_tile_ni_24_12_to_router_24_12_rsp; - -floo_req_t router_24_13_to_router_23_13_req; -floo_rsp_t router_23_13_to_router_24_13_rsp; - -floo_req_t router_24_13_to_router_24_12_req; -floo_rsp_t router_24_12_to_router_24_13_rsp; - -floo_req_t router_24_13_to_router_24_14_req; -floo_rsp_t router_24_14_to_router_24_13_rsp; - -floo_req_t router_24_13_to_router_25_13_req; -floo_rsp_t router_25_13_to_router_24_13_rsp; - -floo_req_t router_24_13_to_magia_tile_ni_24_13_req; -floo_rsp_t magia_tile_ni_24_13_to_router_24_13_rsp; - -floo_req_t router_24_14_to_router_23_14_req; -floo_rsp_t router_23_14_to_router_24_14_rsp; - -floo_req_t router_24_14_to_router_24_13_req; -floo_rsp_t router_24_13_to_router_24_14_rsp; - -floo_req_t router_24_14_to_router_24_15_req; -floo_rsp_t router_24_15_to_router_24_14_rsp; - -floo_req_t router_24_14_to_router_25_14_req; -floo_rsp_t router_25_14_to_router_24_14_rsp; - -floo_req_t router_24_14_to_magia_tile_ni_24_14_req; -floo_rsp_t magia_tile_ni_24_14_to_router_24_14_rsp; - -floo_req_t router_24_15_to_router_23_15_req; -floo_rsp_t router_23_15_to_router_24_15_rsp; - -floo_req_t router_24_15_to_router_24_14_req; -floo_rsp_t router_24_14_to_router_24_15_rsp; - -floo_req_t router_24_15_to_router_24_16_req; -floo_rsp_t router_24_16_to_router_24_15_rsp; - -floo_req_t router_24_15_to_router_25_15_req; -floo_rsp_t router_25_15_to_router_24_15_rsp; - -floo_req_t router_24_15_to_magia_tile_ni_24_15_req; -floo_rsp_t magia_tile_ni_24_15_to_router_24_15_rsp; - -floo_req_t router_24_16_to_router_23_16_req; -floo_rsp_t router_23_16_to_router_24_16_rsp; - -floo_req_t router_24_16_to_router_24_15_req; -floo_rsp_t router_24_15_to_router_24_16_rsp; - -floo_req_t router_24_16_to_router_24_17_req; -floo_rsp_t router_24_17_to_router_24_16_rsp; - -floo_req_t router_24_16_to_router_25_16_req; -floo_rsp_t router_25_16_to_router_24_16_rsp; - -floo_req_t router_24_16_to_magia_tile_ni_24_16_req; -floo_rsp_t magia_tile_ni_24_16_to_router_24_16_rsp; - -floo_req_t router_24_17_to_router_23_17_req; -floo_rsp_t router_23_17_to_router_24_17_rsp; - -floo_req_t router_24_17_to_router_24_16_req; -floo_rsp_t router_24_16_to_router_24_17_rsp; - -floo_req_t router_24_17_to_router_24_18_req; -floo_rsp_t router_24_18_to_router_24_17_rsp; - -floo_req_t router_24_17_to_router_25_17_req; -floo_rsp_t router_25_17_to_router_24_17_rsp; - -floo_req_t router_24_17_to_magia_tile_ni_24_17_req; -floo_rsp_t magia_tile_ni_24_17_to_router_24_17_rsp; - -floo_req_t router_24_18_to_router_23_18_req; -floo_rsp_t router_23_18_to_router_24_18_rsp; - -floo_req_t router_24_18_to_router_24_17_req; -floo_rsp_t router_24_17_to_router_24_18_rsp; - -floo_req_t router_24_18_to_router_24_19_req; -floo_rsp_t router_24_19_to_router_24_18_rsp; - -floo_req_t router_24_18_to_router_25_18_req; -floo_rsp_t router_25_18_to_router_24_18_rsp; - -floo_req_t router_24_18_to_magia_tile_ni_24_18_req; -floo_rsp_t magia_tile_ni_24_18_to_router_24_18_rsp; - -floo_req_t router_24_19_to_router_23_19_req; -floo_rsp_t router_23_19_to_router_24_19_rsp; - -floo_req_t router_24_19_to_router_24_18_req; -floo_rsp_t router_24_18_to_router_24_19_rsp; - -floo_req_t router_24_19_to_router_24_20_req; -floo_rsp_t router_24_20_to_router_24_19_rsp; - -floo_req_t router_24_19_to_router_25_19_req; -floo_rsp_t router_25_19_to_router_24_19_rsp; - -floo_req_t router_24_19_to_magia_tile_ni_24_19_req; -floo_rsp_t magia_tile_ni_24_19_to_router_24_19_rsp; - -floo_req_t router_24_20_to_router_23_20_req; -floo_rsp_t router_23_20_to_router_24_20_rsp; - -floo_req_t router_24_20_to_router_24_19_req; -floo_rsp_t router_24_19_to_router_24_20_rsp; - -floo_req_t router_24_20_to_router_24_21_req; -floo_rsp_t router_24_21_to_router_24_20_rsp; - -floo_req_t router_24_20_to_router_25_20_req; -floo_rsp_t router_25_20_to_router_24_20_rsp; - -floo_req_t router_24_20_to_magia_tile_ni_24_20_req; -floo_rsp_t magia_tile_ni_24_20_to_router_24_20_rsp; - -floo_req_t router_24_21_to_router_23_21_req; -floo_rsp_t router_23_21_to_router_24_21_rsp; - -floo_req_t router_24_21_to_router_24_20_req; -floo_rsp_t router_24_20_to_router_24_21_rsp; - -floo_req_t router_24_21_to_router_24_22_req; -floo_rsp_t router_24_22_to_router_24_21_rsp; - -floo_req_t router_24_21_to_router_25_21_req; -floo_rsp_t router_25_21_to_router_24_21_rsp; - -floo_req_t router_24_21_to_magia_tile_ni_24_21_req; -floo_rsp_t magia_tile_ni_24_21_to_router_24_21_rsp; - -floo_req_t router_24_22_to_router_23_22_req; -floo_rsp_t router_23_22_to_router_24_22_rsp; - -floo_req_t router_24_22_to_router_24_21_req; -floo_rsp_t router_24_21_to_router_24_22_rsp; - -floo_req_t router_24_22_to_router_24_23_req; -floo_rsp_t router_24_23_to_router_24_22_rsp; - -floo_req_t router_24_22_to_router_25_22_req; -floo_rsp_t router_25_22_to_router_24_22_rsp; - -floo_req_t router_24_22_to_magia_tile_ni_24_22_req; -floo_rsp_t magia_tile_ni_24_22_to_router_24_22_rsp; - -floo_req_t router_24_23_to_router_23_23_req; -floo_rsp_t router_23_23_to_router_24_23_rsp; - -floo_req_t router_24_23_to_router_24_22_req; -floo_rsp_t router_24_22_to_router_24_23_rsp; - -floo_req_t router_24_23_to_router_24_24_req; -floo_rsp_t router_24_24_to_router_24_23_rsp; - -floo_req_t router_24_23_to_router_25_23_req; -floo_rsp_t router_25_23_to_router_24_23_rsp; - -floo_req_t router_24_23_to_magia_tile_ni_24_23_req; -floo_rsp_t magia_tile_ni_24_23_to_router_24_23_rsp; - -floo_req_t router_24_24_to_router_23_24_req; -floo_rsp_t router_23_24_to_router_24_24_rsp; - -floo_req_t router_24_24_to_router_24_23_req; -floo_rsp_t router_24_23_to_router_24_24_rsp; - -floo_req_t router_24_24_to_router_24_25_req; -floo_rsp_t router_24_25_to_router_24_24_rsp; - -floo_req_t router_24_24_to_router_25_24_req; -floo_rsp_t router_25_24_to_router_24_24_rsp; - -floo_req_t router_24_24_to_magia_tile_ni_24_24_req; -floo_rsp_t magia_tile_ni_24_24_to_router_24_24_rsp; - -floo_req_t router_24_25_to_router_23_25_req; -floo_rsp_t router_23_25_to_router_24_25_rsp; - -floo_req_t router_24_25_to_router_24_24_req; -floo_rsp_t router_24_24_to_router_24_25_rsp; - -floo_req_t router_24_25_to_router_24_26_req; -floo_rsp_t router_24_26_to_router_24_25_rsp; - -floo_req_t router_24_25_to_router_25_25_req; -floo_rsp_t router_25_25_to_router_24_25_rsp; - -floo_req_t router_24_25_to_magia_tile_ni_24_25_req; -floo_rsp_t magia_tile_ni_24_25_to_router_24_25_rsp; - -floo_req_t router_24_26_to_router_23_26_req; -floo_rsp_t router_23_26_to_router_24_26_rsp; - -floo_req_t router_24_26_to_router_24_25_req; -floo_rsp_t router_24_25_to_router_24_26_rsp; - -floo_req_t router_24_26_to_router_24_27_req; -floo_rsp_t router_24_27_to_router_24_26_rsp; - -floo_req_t router_24_26_to_router_25_26_req; -floo_rsp_t router_25_26_to_router_24_26_rsp; - -floo_req_t router_24_26_to_magia_tile_ni_24_26_req; -floo_rsp_t magia_tile_ni_24_26_to_router_24_26_rsp; - -floo_req_t router_24_27_to_router_23_27_req; -floo_rsp_t router_23_27_to_router_24_27_rsp; - -floo_req_t router_24_27_to_router_24_26_req; -floo_rsp_t router_24_26_to_router_24_27_rsp; - -floo_req_t router_24_27_to_router_24_28_req; -floo_rsp_t router_24_28_to_router_24_27_rsp; - -floo_req_t router_24_27_to_router_25_27_req; -floo_rsp_t router_25_27_to_router_24_27_rsp; - -floo_req_t router_24_27_to_magia_tile_ni_24_27_req; -floo_rsp_t magia_tile_ni_24_27_to_router_24_27_rsp; - -floo_req_t router_24_28_to_router_23_28_req; -floo_rsp_t router_23_28_to_router_24_28_rsp; - -floo_req_t router_24_28_to_router_24_27_req; -floo_rsp_t router_24_27_to_router_24_28_rsp; - -floo_req_t router_24_28_to_router_24_29_req; -floo_rsp_t router_24_29_to_router_24_28_rsp; - -floo_req_t router_24_28_to_router_25_28_req; -floo_rsp_t router_25_28_to_router_24_28_rsp; - -floo_req_t router_24_28_to_magia_tile_ni_24_28_req; -floo_rsp_t magia_tile_ni_24_28_to_router_24_28_rsp; - -floo_req_t router_24_29_to_router_23_29_req; -floo_rsp_t router_23_29_to_router_24_29_rsp; - -floo_req_t router_24_29_to_router_24_28_req; -floo_rsp_t router_24_28_to_router_24_29_rsp; - -floo_req_t router_24_29_to_router_24_30_req; -floo_rsp_t router_24_30_to_router_24_29_rsp; - -floo_req_t router_24_29_to_router_25_29_req; -floo_rsp_t router_25_29_to_router_24_29_rsp; - -floo_req_t router_24_29_to_magia_tile_ni_24_29_req; -floo_rsp_t magia_tile_ni_24_29_to_router_24_29_rsp; - -floo_req_t router_24_30_to_router_23_30_req; -floo_rsp_t router_23_30_to_router_24_30_rsp; - -floo_req_t router_24_30_to_router_24_29_req; -floo_rsp_t router_24_29_to_router_24_30_rsp; - -floo_req_t router_24_30_to_router_24_31_req; -floo_rsp_t router_24_31_to_router_24_30_rsp; - -floo_req_t router_24_30_to_router_25_30_req; -floo_rsp_t router_25_30_to_router_24_30_rsp; - -floo_req_t router_24_30_to_magia_tile_ni_24_30_req; -floo_rsp_t magia_tile_ni_24_30_to_router_24_30_rsp; - -floo_req_t router_24_31_to_router_23_31_req; -floo_rsp_t router_23_31_to_router_24_31_rsp; - -floo_req_t router_24_31_to_router_24_30_req; -floo_rsp_t router_24_30_to_router_24_31_rsp; - -floo_req_t router_24_31_to_router_25_31_req; -floo_rsp_t router_25_31_to_router_24_31_rsp; - -floo_req_t router_24_31_to_magia_tile_ni_24_31_req; -floo_rsp_t magia_tile_ni_24_31_to_router_24_31_rsp; - -floo_req_t router_25_0_to_router_24_0_req; -floo_rsp_t router_24_0_to_router_25_0_rsp; - -floo_req_t router_25_0_to_router_25_1_req; -floo_rsp_t router_25_1_to_router_25_0_rsp; - -floo_req_t router_25_0_to_router_26_0_req; -floo_rsp_t router_26_0_to_router_25_0_rsp; - -floo_req_t router_25_0_to_magia_tile_ni_25_0_req; -floo_rsp_t magia_tile_ni_25_0_to_router_25_0_rsp; - -floo_req_t router_25_1_to_router_24_1_req; -floo_rsp_t router_24_1_to_router_25_1_rsp; - -floo_req_t router_25_1_to_router_25_0_req; -floo_rsp_t router_25_0_to_router_25_1_rsp; - -floo_req_t router_25_1_to_router_25_2_req; -floo_rsp_t router_25_2_to_router_25_1_rsp; - -floo_req_t router_25_1_to_router_26_1_req; -floo_rsp_t router_26_1_to_router_25_1_rsp; - -floo_req_t router_25_1_to_magia_tile_ni_25_1_req; -floo_rsp_t magia_tile_ni_25_1_to_router_25_1_rsp; - -floo_req_t router_25_2_to_router_24_2_req; -floo_rsp_t router_24_2_to_router_25_2_rsp; - -floo_req_t router_25_2_to_router_25_1_req; -floo_rsp_t router_25_1_to_router_25_2_rsp; - -floo_req_t router_25_2_to_router_25_3_req; -floo_rsp_t router_25_3_to_router_25_2_rsp; - -floo_req_t router_25_2_to_router_26_2_req; -floo_rsp_t router_26_2_to_router_25_2_rsp; - -floo_req_t router_25_2_to_magia_tile_ni_25_2_req; -floo_rsp_t magia_tile_ni_25_2_to_router_25_2_rsp; - -floo_req_t router_25_3_to_router_24_3_req; -floo_rsp_t router_24_3_to_router_25_3_rsp; - -floo_req_t router_25_3_to_router_25_2_req; -floo_rsp_t router_25_2_to_router_25_3_rsp; - -floo_req_t router_25_3_to_router_25_4_req; -floo_rsp_t router_25_4_to_router_25_3_rsp; - -floo_req_t router_25_3_to_router_26_3_req; -floo_rsp_t router_26_3_to_router_25_3_rsp; - -floo_req_t router_25_3_to_magia_tile_ni_25_3_req; -floo_rsp_t magia_tile_ni_25_3_to_router_25_3_rsp; - -floo_req_t router_25_4_to_router_24_4_req; -floo_rsp_t router_24_4_to_router_25_4_rsp; - -floo_req_t router_25_4_to_router_25_3_req; -floo_rsp_t router_25_3_to_router_25_4_rsp; - -floo_req_t router_25_4_to_router_25_5_req; -floo_rsp_t router_25_5_to_router_25_4_rsp; - -floo_req_t router_25_4_to_router_26_4_req; -floo_rsp_t router_26_4_to_router_25_4_rsp; - -floo_req_t router_25_4_to_magia_tile_ni_25_4_req; -floo_rsp_t magia_tile_ni_25_4_to_router_25_4_rsp; - -floo_req_t router_25_5_to_router_24_5_req; -floo_rsp_t router_24_5_to_router_25_5_rsp; - -floo_req_t router_25_5_to_router_25_4_req; -floo_rsp_t router_25_4_to_router_25_5_rsp; - -floo_req_t router_25_5_to_router_25_6_req; -floo_rsp_t router_25_6_to_router_25_5_rsp; - -floo_req_t router_25_5_to_router_26_5_req; -floo_rsp_t router_26_5_to_router_25_5_rsp; - -floo_req_t router_25_5_to_magia_tile_ni_25_5_req; -floo_rsp_t magia_tile_ni_25_5_to_router_25_5_rsp; - -floo_req_t router_25_6_to_router_24_6_req; -floo_rsp_t router_24_6_to_router_25_6_rsp; - -floo_req_t router_25_6_to_router_25_5_req; -floo_rsp_t router_25_5_to_router_25_6_rsp; - -floo_req_t router_25_6_to_router_25_7_req; -floo_rsp_t router_25_7_to_router_25_6_rsp; - -floo_req_t router_25_6_to_router_26_6_req; -floo_rsp_t router_26_6_to_router_25_6_rsp; - -floo_req_t router_25_6_to_magia_tile_ni_25_6_req; -floo_rsp_t magia_tile_ni_25_6_to_router_25_6_rsp; - -floo_req_t router_25_7_to_router_24_7_req; -floo_rsp_t router_24_7_to_router_25_7_rsp; - -floo_req_t router_25_7_to_router_25_6_req; -floo_rsp_t router_25_6_to_router_25_7_rsp; - -floo_req_t router_25_7_to_router_25_8_req; -floo_rsp_t router_25_8_to_router_25_7_rsp; - -floo_req_t router_25_7_to_router_26_7_req; -floo_rsp_t router_26_7_to_router_25_7_rsp; - -floo_req_t router_25_7_to_magia_tile_ni_25_7_req; -floo_rsp_t magia_tile_ni_25_7_to_router_25_7_rsp; - -floo_req_t router_25_8_to_router_24_8_req; -floo_rsp_t router_24_8_to_router_25_8_rsp; - -floo_req_t router_25_8_to_router_25_7_req; -floo_rsp_t router_25_7_to_router_25_8_rsp; - -floo_req_t router_25_8_to_router_25_9_req; -floo_rsp_t router_25_9_to_router_25_8_rsp; - -floo_req_t router_25_8_to_router_26_8_req; -floo_rsp_t router_26_8_to_router_25_8_rsp; - -floo_req_t router_25_8_to_magia_tile_ni_25_8_req; -floo_rsp_t magia_tile_ni_25_8_to_router_25_8_rsp; - -floo_req_t router_25_9_to_router_24_9_req; -floo_rsp_t router_24_9_to_router_25_9_rsp; - -floo_req_t router_25_9_to_router_25_8_req; -floo_rsp_t router_25_8_to_router_25_9_rsp; - -floo_req_t router_25_9_to_router_25_10_req; -floo_rsp_t router_25_10_to_router_25_9_rsp; - -floo_req_t router_25_9_to_router_26_9_req; -floo_rsp_t router_26_9_to_router_25_9_rsp; - -floo_req_t router_25_9_to_magia_tile_ni_25_9_req; -floo_rsp_t magia_tile_ni_25_9_to_router_25_9_rsp; - -floo_req_t router_25_10_to_router_24_10_req; -floo_rsp_t router_24_10_to_router_25_10_rsp; - -floo_req_t router_25_10_to_router_25_9_req; -floo_rsp_t router_25_9_to_router_25_10_rsp; - -floo_req_t router_25_10_to_router_25_11_req; -floo_rsp_t router_25_11_to_router_25_10_rsp; - -floo_req_t router_25_10_to_router_26_10_req; -floo_rsp_t router_26_10_to_router_25_10_rsp; - -floo_req_t router_25_10_to_magia_tile_ni_25_10_req; -floo_rsp_t magia_tile_ni_25_10_to_router_25_10_rsp; - -floo_req_t router_25_11_to_router_24_11_req; -floo_rsp_t router_24_11_to_router_25_11_rsp; - -floo_req_t router_25_11_to_router_25_10_req; -floo_rsp_t router_25_10_to_router_25_11_rsp; - -floo_req_t router_25_11_to_router_25_12_req; -floo_rsp_t router_25_12_to_router_25_11_rsp; - -floo_req_t router_25_11_to_router_26_11_req; -floo_rsp_t router_26_11_to_router_25_11_rsp; - -floo_req_t router_25_11_to_magia_tile_ni_25_11_req; -floo_rsp_t magia_tile_ni_25_11_to_router_25_11_rsp; - -floo_req_t router_25_12_to_router_24_12_req; -floo_rsp_t router_24_12_to_router_25_12_rsp; - -floo_req_t router_25_12_to_router_25_11_req; -floo_rsp_t router_25_11_to_router_25_12_rsp; - -floo_req_t router_25_12_to_router_25_13_req; -floo_rsp_t router_25_13_to_router_25_12_rsp; - -floo_req_t router_25_12_to_router_26_12_req; -floo_rsp_t router_26_12_to_router_25_12_rsp; - -floo_req_t router_25_12_to_magia_tile_ni_25_12_req; -floo_rsp_t magia_tile_ni_25_12_to_router_25_12_rsp; - -floo_req_t router_25_13_to_router_24_13_req; -floo_rsp_t router_24_13_to_router_25_13_rsp; - -floo_req_t router_25_13_to_router_25_12_req; -floo_rsp_t router_25_12_to_router_25_13_rsp; - -floo_req_t router_25_13_to_router_25_14_req; -floo_rsp_t router_25_14_to_router_25_13_rsp; - -floo_req_t router_25_13_to_router_26_13_req; -floo_rsp_t router_26_13_to_router_25_13_rsp; - -floo_req_t router_25_13_to_magia_tile_ni_25_13_req; -floo_rsp_t magia_tile_ni_25_13_to_router_25_13_rsp; - -floo_req_t router_25_14_to_router_24_14_req; -floo_rsp_t router_24_14_to_router_25_14_rsp; - -floo_req_t router_25_14_to_router_25_13_req; -floo_rsp_t router_25_13_to_router_25_14_rsp; - -floo_req_t router_25_14_to_router_25_15_req; -floo_rsp_t router_25_15_to_router_25_14_rsp; - -floo_req_t router_25_14_to_router_26_14_req; -floo_rsp_t router_26_14_to_router_25_14_rsp; - -floo_req_t router_25_14_to_magia_tile_ni_25_14_req; -floo_rsp_t magia_tile_ni_25_14_to_router_25_14_rsp; - -floo_req_t router_25_15_to_router_24_15_req; -floo_rsp_t router_24_15_to_router_25_15_rsp; - -floo_req_t router_25_15_to_router_25_14_req; -floo_rsp_t router_25_14_to_router_25_15_rsp; - -floo_req_t router_25_15_to_router_25_16_req; -floo_rsp_t router_25_16_to_router_25_15_rsp; - -floo_req_t router_25_15_to_router_26_15_req; -floo_rsp_t router_26_15_to_router_25_15_rsp; - -floo_req_t router_25_15_to_magia_tile_ni_25_15_req; -floo_rsp_t magia_tile_ni_25_15_to_router_25_15_rsp; - -floo_req_t router_25_16_to_router_24_16_req; -floo_rsp_t router_24_16_to_router_25_16_rsp; - -floo_req_t router_25_16_to_router_25_15_req; -floo_rsp_t router_25_15_to_router_25_16_rsp; - -floo_req_t router_25_16_to_router_25_17_req; -floo_rsp_t router_25_17_to_router_25_16_rsp; - -floo_req_t router_25_16_to_router_26_16_req; -floo_rsp_t router_26_16_to_router_25_16_rsp; - -floo_req_t router_25_16_to_magia_tile_ni_25_16_req; -floo_rsp_t magia_tile_ni_25_16_to_router_25_16_rsp; - -floo_req_t router_25_17_to_router_24_17_req; -floo_rsp_t router_24_17_to_router_25_17_rsp; - -floo_req_t router_25_17_to_router_25_16_req; -floo_rsp_t router_25_16_to_router_25_17_rsp; - -floo_req_t router_25_17_to_router_25_18_req; -floo_rsp_t router_25_18_to_router_25_17_rsp; - -floo_req_t router_25_17_to_router_26_17_req; -floo_rsp_t router_26_17_to_router_25_17_rsp; - -floo_req_t router_25_17_to_magia_tile_ni_25_17_req; -floo_rsp_t magia_tile_ni_25_17_to_router_25_17_rsp; - -floo_req_t router_25_18_to_router_24_18_req; -floo_rsp_t router_24_18_to_router_25_18_rsp; - -floo_req_t router_25_18_to_router_25_17_req; -floo_rsp_t router_25_17_to_router_25_18_rsp; - -floo_req_t router_25_18_to_router_25_19_req; -floo_rsp_t router_25_19_to_router_25_18_rsp; - -floo_req_t router_25_18_to_router_26_18_req; -floo_rsp_t router_26_18_to_router_25_18_rsp; - -floo_req_t router_25_18_to_magia_tile_ni_25_18_req; -floo_rsp_t magia_tile_ni_25_18_to_router_25_18_rsp; - -floo_req_t router_25_19_to_router_24_19_req; -floo_rsp_t router_24_19_to_router_25_19_rsp; - -floo_req_t router_25_19_to_router_25_18_req; -floo_rsp_t router_25_18_to_router_25_19_rsp; - -floo_req_t router_25_19_to_router_25_20_req; -floo_rsp_t router_25_20_to_router_25_19_rsp; - -floo_req_t router_25_19_to_router_26_19_req; -floo_rsp_t router_26_19_to_router_25_19_rsp; - -floo_req_t router_25_19_to_magia_tile_ni_25_19_req; -floo_rsp_t magia_tile_ni_25_19_to_router_25_19_rsp; - -floo_req_t router_25_20_to_router_24_20_req; -floo_rsp_t router_24_20_to_router_25_20_rsp; - -floo_req_t router_25_20_to_router_25_19_req; -floo_rsp_t router_25_19_to_router_25_20_rsp; - -floo_req_t router_25_20_to_router_25_21_req; -floo_rsp_t router_25_21_to_router_25_20_rsp; - -floo_req_t router_25_20_to_router_26_20_req; -floo_rsp_t router_26_20_to_router_25_20_rsp; - -floo_req_t router_25_20_to_magia_tile_ni_25_20_req; -floo_rsp_t magia_tile_ni_25_20_to_router_25_20_rsp; - -floo_req_t router_25_21_to_router_24_21_req; -floo_rsp_t router_24_21_to_router_25_21_rsp; - -floo_req_t router_25_21_to_router_25_20_req; -floo_rsp_t router_25_20_to_router_25_21_rsp; - -floo_req_t router_25_21_to_router_25_22_req; -floo_rsp_t router_25_22_to_router_25_21_rsp; - -floo_req_t router_25_21_to_router_26_21_req; -floo_rsp_t router_26_21_to_router_25_21_rsp; - -floo_req_t router_25_21_to_magia_tile_ni_25_21_req; -floo_rsp_t magia_tile_ni_25_21_to_router_25_21_rsp; - -floo_req_t router_25_22_to_router_24_22_req; -floo_rsp_t router_24_22_to_router_25_22_rsp; - -floo_req_t router_25_22_to_router_25_21_req; -floo_rsp_t router_25_21_to_router_25_22_rsp; - -floo_req_t router_25_22_to_router_25_23_req; -floo_rsp_t router_25_23_to_router_25_22_rsp; - -floo_req_t router_25_22_to_router_26_22_req; -floo_rsp_t router_26_22_to_router_25_22_rsp; - -floo_req_t router_25_22_to_magia_tile_ni_25_22_req; -floo_rsp_t magia_tile_ni_25_22_to_router_25_22_rsp; - -floo_req_t router_25_23_to_router_24_23_req; -floo_rsp_t router_24_23_to_router_25_23_rsp; - -floo_req_t router_25_23_to_router_25_22_req; -floo_rsp_t router_25_22_to_router_25_23_rsp; - -floo_req_t router_25_23_to_router_25_24_req; -floo_rsp_t router_25_24_to_router_25_23_rsp; - -floo_req_t router_25_23_to_router_26_23_req; -floo_rsp_t router_26_23_to_router_25_23_rsp; - -floo_req_t router_25_23_to_magia_tile_ni_25_23_req; -floo_rsp_t magia_tile_ni_25_23_to_router_25_23_rsp; - -floo_req_t router_25_24_to_router_24_24_req; -floo_rsp_t router_24_24_to_router_25_24_rsp; - -floo_req_t router_25_24_to_router_25_23_req; -floo_rsp_t router_25_23_to_router_25_24_rsp; - -floo_req_t router_25_24_to_router_25_25_req; -floo_rsp_t router_25_25_to_router_25_24_rsp; - -floo_req_t router_25_24_to_router_26_24_req; -floo_rsp_t router_26_24_to_router_25_24_rsp; - -floo_req_t router_25_24_to_magia_tile_ni_25_24_req; -floo_rsp_t magia_tile_ni_25_24_to_router_25_24_rsp; - -floo_req_t router_25_25_to_router_24_25_req; -floo_rsp_t router_24_25_to_router_25_25_rsp; - -floo_req_t router_25_25_to_router_25_24_req; -floo_rsp_t router_25_24_to_router_25_25_rsp; - -floo_req_t router_25_25_to_router_25_26_req; -floo_rsp_t router_25_26_to_router_25_25_rsp; - -floo_req_t router_25_25_to_router_26_25_req; -floo_rsp_t router_26_25_to_router_25_25_rsp; - -floo_req_t router_25_25_to_magia_tile_ni_25_25_req; -floo_rsp_t magia_tile_ni_25_25_to_router_25_25_rsp; - -floo_req_t router_25_26_to_router_24_26_req; -floo_rsp_t router_24_26_to_router_25_26_rsp; - -floo_req_t router_25_26_to_router_25_25_req; -floo_rsp_t router_25_25_to_router_25_26_rsp; - -floo_req_t router_25_26_to_router_25_27_req; -floo_rsp_t router_25_27_to_router_25_26_rsp; - -floo_req_t router_25_26_to_router_26_26_req; -floo_rsp_t router_26_26_to_router_25_26_rsp; - -floo_req_t router_25_26_to_magia_tile_ni_25_26_req; -floo_rsp_t magia_tile_ni_25_26_to_router_25_26_rsp; - -floo_req_t router_25_27_to_router_24_27_req; -floo_rsp_t router_24_27_to_router_25_27_rsp; - -floo_req_t router_25_27_to_router_25_26_req; -floo_rsp_t router_25_26_to_router_25_27_rsp; - -floo_req_t router_25_27_to_router_25_28_req; -floo_rsp_t router_25_28_to_router_25_27_rsp; - -floo_req_t router_25_27_to_router_26_27_req; -floo_rsp_t router_26_27_to_router_25_27_rsp; - -floo_req_t router_25_27_to_magia_tile_ni_25_27_req; -floo_rsp_t magia_tile_ni_25_27_to_router_25_27_rsp; - -floo_req_t router_25_28_to_router_24_28_req; -floo_rsp_t router_24_28_to_router_25_28_rsp; - -floo_req_t router_25_28_to_router_25_27_req; -floo_rsp_t router_25_27_to_router_25_28_rsp; - -floo_req_t router_25_28_to_router_25_29_req; -floo_rsp_t router_25_29_to_router_25_28_rsp; - -floo_req_t router_25_28_to_router_26_28_req; -floo_rsp_t router_26_28_to_router_25_28_rsp; - -floo_req_t router_25_28_to_magia_tile_ni_25_28_req; -floo_rsp_t magia_tile_ni_25_28_to_router_25_28_rsp; - -floo_req_t router_25_29_to_router_24_29_req; -floo_rsp_t router_24_29_to_router_25_29_rsp; - -floo_req_t router_25_29_to_router_25_28_req; -floo_rsp_t router_25_28_to_router_25_29_rsp; - -floo_req_t router_25_29_to_router_25_30_req; -floo_rsp_t router_25_30_to_router_25_29_rsp; - -floo_req_t router_25_29_to_router_26_29_req; -floo_rsp_t router_26_29_to_router_25_29_rsp; - -floo_req_t router_25_29_to_magia_tile_ni_25_29_req; -floo_rsp_t magia_tile_ni_25_29_to_router_25_29_rsp; - -floo_req_t router_25_30_to_router_24_30_req; -floo_rsp_t router_24_30_to_router_25_30_rsp; - -floo_req_t router_25_30_to_router_25_29_req; -floo_rsp_t router_25_29_to_router_25_30_rsp; - -floo_req_t router_25_30_to_router_25_31_req; -floo_rsp_t router_25_31_to_router_25_30_rsp; - -floo_req_t router_25_30_to_router_26_30_req; -floo_rsp_t router_26_30_to_router_25_30_rsp; - -floo_req_t router_25_30_to_magia_tile_ni_25_30_req; -floo_rsp_t magia_tile_ni_25_30_to_router_25_30_rsp; - -floo_req_t router_25_31_to_router_24_31_req; -floo_rsp_t router_24_31_to_router_25_31_rsp; - -floo_req_t router_25_31_to_router_25_30_req; -floo_rsp_t router_25_30_to_router_25_31_rsp; - -floo_req_t router_25_31_to_router_26_31_req; -floo_rsp_t router_26_31_to_router_25_31_rsp; - -floo_req_t router_25_31_to_magia_tile_ni_25_31_req; -floo_rsp_t magia_tile_ni_25_31_to_router_25_31_rsp; - -floo_req_t router_26_0_to_router_25_0_req; -floo_rsp_t router_25_0_to_router_26_0_rsp; - -floo_req_t router_26_0_to_router_26_1_req; -floo_rsp_t router_26_1_to_router_26_0_rsp; - -floo_req_t router_26_0_to_router_27_0_req; -floo_rsp_t router_27_0_to_router_26_0_rsp; - -floo_req_t router_26_0_to_magia_tile_ni_26_0_req; -floo_rsp_t magia_tile_ni_26_0_to_router_26_0_rsp; - -floo_req_t router_26_1_to_router_25_1_req; -floo_rsp_t router_25_1_to_router_26_1_rsp; - -floo_req_t router_26_1_to_router_26_0_req; -floo_rsp_t router_26_0_to_router_26_1_rsp; - -floo_req_t router_26_1_to_router_26_2_req; -floo_rsp_t router_26_2_to_router_26_1_rsp; - -floo_req_t router_26_1_to_router_27_1_req; -floo_rsp_t router_27_1_to_router_26_1_rsp; - -floo_req_t router_26_1_to_magia_tile_ni_26_1_req; -floo_rsp_t magia_tile_ni_26_1_to_router_26_1_rsp; - -floo_req_t router_26_2_to_router_25_2_req; -floo_rsp_t router_25_2_to_router_26_2_rsp; - -floo_req_t router_26_2_to_router_26_1_req; -floo_rsp_t router_26_1_to_router_26_2_rsp; - -floo_req_t router_26_2_to_router_26_3_req; -floo_rsp_t router_26_3_to_router_26_2_rsp; - -floo_req_t router_26_2_to_router_27_2_req; -floo_rsp_t router_27_2_to_router_26_2_rsp; - -floo_req_t router_26_2_to_magia_tile_ni_26_2_req; -floo_rsp_t magia_tile_ni_26_2_to_router_26_2_rsp; - -floo_req_t router_26_3_to_router_25_3_req; -floo_rsp_t router_25_3_to_router_26_3_rsp; - -floo_req_t router_26_3_to_router_26_2_req; -floo_rsp_t router_26_2_to_router_26_3_rsp; - -floo_req_t router_26_3_to_router_26_4_req; -floo_rsp_t router_26_4_to_router_26_3_rsp; - -floo_req_t router_26_3_to_router_27_3_req; -floo_rsp_t router_27_3_to_router_26_3_rsp; - -floo_req_t router_26_3_to_magia_tile_ni_26_3_req; -floo_rsp_t magia_tile_ni_26_3_to_router_26_3_rsp; - -floo_req_t router_26_4_to_router_25_4_req; -floo_rsp_t router_25_4_to_router_26_4_rsp; - -floo_req_t router_26_4_to_router_26_3_req; -floo_rsp_t router_26_3_to_router_26_4_rsp; - -floo_req_t router_26_4_to_router_26_5_req; -floo_rsp_t router_26_5_to_router_26_4_rsp; - -floo_req_t router_26_4_to_router_27_4_req; -floo_rsp_t router_27_4_to_router_26_4_rsp; - -floo_req_t router_26_4_to_magia_tile_ni_26_4_req; -floo_rsp_t magia_tile_ni_26_4_to_router_26_4_rsp; - -floo_req_t router_26_5_to_router_25_5_req; -floo_rsp_t router_25_5_to_router_26_5_rsp; - -floo_req_t router_26_5_to_router_26_4_req; -floo_rsp_t router_26_4_to_router_26_5_rsp; - -floo_req_t router_26_5_to_router_26_6_req; -floo_rsp_t router_26_6_to_router_26_5_rsp; - -floo_req_t router_26_5_to_router_27_5_req; -floo_rsp_t router_27_5_to_router_26_5_rsp; - -floo_req_t router_26_5_to_magia_tile_ni_26_5_req; -floo_rsp_t magia_tile_ni_26_5_to_router_26_5_rsp; - -floo_req_t router_26_6_to_router_25_6_req; -floo_rsp_t router_25_6_to_router_26_6_rsp; - -floo_req_t router_26_6_to_router_26_5_req; -floo_rsp_t router_26_5_to_router_26_6_rsp; - -floo_req_t router_26_6_to_router_26_7_req; -floo_rsp_t router_26_7_to_router_26_6_rsp; - -floo_req_t router_26_6_to_router_27_6_req; -floo_rsp_t router_27_6_to_router_26_6_rsp; - -floo_req_t router_26_6_to_magia_tile_ni_26_6_req; -floo_rsp_t magia_tile_ni_26_6_to_router_26_6_rsp; - -floo_req_t router_26_7_to_router_25_7_req; -floo_rsp_t router_25_7_to_router_26_7_rsp; - -floo_req_t router_26_7_to_router_26_6_req; -floo_rsp_t router_26_6_to_router_26_7_rsp; - -floo_req_t router_26_7_to_router_26_8_req; -floo_rsp_t router_26_8_to_router_26_7_rsp; - -floo_req_t router_26_7_to_router_27_7_req; -floo_rsp_t router_27_7_to_router_26_7_rsp; - -floo_req_t router_26_7_to_magia_tile_ni_26_7_req; -floo_rsp_t magia_tile_ni_26_7_to_router_26_7_rsp; - -floo_req_t router_26_8_to_router_25_8_req; -floo_rsp_t router_25_8_to_router_26_8_rsp; - -floo_req_t router_26_8_to_router_26_7_req; -floo_rsp_t router_26_7_to_router_26_8_rsp; - -floo_req_t router_26_8_to_router_26_9_req; -floo_rsp_t router_26_9_to_router_26_8_rsp; - -floo_req_t router_26_8_to_router_27_8_req; -floo_rsp_t router_27_8_to_router_26_8_rsp; - -floo_req_t router_26_8_to_magia_tile_ni_26_8_req; -floo_rsp_t magia_tile_ni_26_8_to_router_26_8_rsp; - -floo_req_t router_26_9_to_router_25_9_req; -floo_rsp_t router_25_9_to_router_26_9_rsp; - -floo_req_t router_26_9_to_router_26_8_req; -floo_rsp_t router_26_8_to_router_26_9_rsp; - -floo_req_t router_26_9_to_router_26_10_req; -floo_rsp_t router_26_10_to_router_26_9_rsp; - -floo_req_t router_26_9_to_router_27_9_req; -floo_rsp_t router_27_9_to_router_26_9_rsp; - -floo_req_t router_26_9_to_magia_tile_ni_26_9_req; -floo_rsp_t magia_tile_ni_26_9_to_router_26_9_rsp; - -floo_req_t router_26_10_to_router_25_10_req; -floo_rsp_t router_25_10_to_router_26_10_rsp; - -floo_req_t router_26_10_to_router_26_9_req; -floo_rsp_t router_26_9_to_router_26_10_rsp; - -floo_req_t router_26_10_to_router_26_11_req; -floo_rsp_t router_26_11_to_router_26_10_rsp; - -floo_req_t router_26_10_to_router_27_10_req; -floo_rsp_t router_27_10_to_router_26_10_rsp; - -floo_req_t router_26_10_to_magia_tile_ni_26_10_req; -floo_rsp_t magia_tile_ni_26_10_to_router_26_10_rsp; - -floo_req_t router_26_11_to_router_25_11_req; -floo_rsp_t router_25_11_to_router_26_11_rsp; - -floo_req_t router_26_11_to_router_26_10_req; -floo_rsp_t router_26_10_to_router_26_11_rsp; - -floo_req_t router_26_11_to_router_26_12_req; -floo_rsp_t router_26_12_to_router_26_11_rsp; - -floo_req_t router_26_11_to_router_27_11_req; -floo_rsp_t router_27_11_to_router_26_11_rsp; - -floo_req_t router_26_11_to_magia_tile_ni_26_11_req; -floo_rsp_t magia_tile_ni_26_11_to_router_26_11_rsp; - -floo_req_t router_26_12_to_router_25_12_req; -floo_rsp_t router_25_12_to_router_26_12_rsp; - -floo_req_t router_26_12_to_router_26_11_req; -floo_rsp_t router_26_11_to_router_26_12_rsp; - -floo_req_t router_26_12_to_router_26_13_req; -floo_rsp_t router_26_13_to_router_26_12_rsp; - -floo_req_t router_26_12_to_router_27_12_req; -floo_rsp_t router_27_12_to_router_26_12_rsp; - -floo_req_t router_26_12_to_magia_tile_ni_26_12_req; -floo_rsp_t magia_tile_ni_26_12_to_router_26_12_rsp; - -floo_req_t router_26_13_to_router_25_13_req; -floo_rsp_t router_25_13_to_router_26_13_rsp; - -floo_req_t router_26_13_to_router_26_12_req; -floo_rsp_t router_26_12_to_router_26_13_rsp; - -floo_req_t router_26_13_to_router_26_14_req; -floo_rsp_t router_26_14_to_router_26_13_rsp; - -floo_req_t router_26_13_to_router_27_13_req; -floo_rsp_t router_27_13_to_router_26_13_rsp; - -floo_req_t router_26_13_to_magia_tile_ni_26_13_req; -floo_rsp_t magia_tile_ni_26_13_to_router_26_13_rsp; - -floo_req_t router_26_14_to_router_25_14_req; -floo_rsp_t router_25_14_to_router_26_14_rsp; - -floo_req_t router_26_14_to_router_26_13_req; -floo_rsp_t router_26_13_to_router_26_14_rsp; - -floo_req_t router_26_14_to_router_26_15_req; -floo_rsp_t router_26_15_to_router_26_14_rsp; - -floo_req_t router_26_14_to_router_27_14_req; -floo_rsp_t router_27_14_to_router_26_14_rsp; - -floo_req_t router_26_14_to_magia_tile_ni_26_14_req; -floo_rsp_t magia_tile_ni_26_14_to_router_26_14_rsp; - -floo_req_t router_26_15_to_router_25_15_req; -floo_rsp_t router_25_15_to_router_26_15_rsp; - -floo_req_t router_26_15_to_router_26_14_req; -floo_rsp_t router_26_14_to_router_26_15_rsp; - -floo_req_t router_26_15_to_router_26_16_req; -floo_rsp_t router_26_16_to_router_26_15_rsp; - -floo_req_t router_26_15_to_router_27_15_req; -floo_rsp_t router_27_15_to_router_26_15_rsp; - -floo_req_t router_26_15_to_magia_tile_ni_26_15_req; -floo_rsp_t magia_tile_ni_26_15_to_router_26_15_rsp; - -floo_req_t router_26_16_to_router_25_16_req; -floo_rsp_t router_25_16_to_router_26_16_rsp; - -floo_req_t router_26_16_to_router_26_15_req; -floo_rsp_t router_26_15_to_router_26_16_rsp; - -floo_req_t router_26_16_to_router_26_17_req; -floo_rsp_t router_26_17_to_router_26_16_rsp; - -floo_req_t router_26_16_to_router_27_16_req; -floo_rsp_t router_27_16_to_router_26_16_rsp; - -floo_req_t router_26_16_to_magia_tile_ni_26_16_req; -floo_rsp_t magia_tile_ni_26_16_to_router_26_16_rsp; - -floo_req_t router_26_17_to_router_25_17_req; -floo_rsp_t router_25_17_to_router_26_17_rsp; - -floo_req_t router_26_17_to_router_26_16_req; -floo_rsp_t router_26_16_to_router_26_17_rsp; - -floo_req_t router_26_17_to_router_26_18_req; -floo_rsp_t router_26_18_to_router_26_17_rsp; - -floo_req_t router_26_17_to_router_27_17_req; -floo_rsp_t router_27_17_to_router_26_17_rsp; - -floo_req_t router_26_17_to_magia_tile_ni_26_17_req; -floo_rsp_t magia_tile_ni_26_17_to_router_26_17_rsp; - -floo_req_t router_26_18_to_router_25_18_req; -floo_rsp_t router_25_18_to_router_26_18_rsp; - -floo_req_t router_26_18_to_router_26_17_req; -floo_rsp_t router_26_17_to_router_26_18_rsp; - -floo_req_t router_26_18_to_router_26_19_req; -floo_rsp_t router_26_19_to_router_26_18_rsp; - -floo_req_t router_26_18_to_router_27_18_req; -floo_rsp_t router_27_18_to_router_26_18_rsp; - -floo_req_t router_26_18_to_magia_tile_ni_26_18_req; -floo_rsp_t magia_tile_ni_26_18_to_router_26_18_rsp; - -floo_req_t router_26_19_to_router_25_19_req; -floo_rsp_t router_25_19_to_router_26_19_rsp; - -floo_req_t router_26_19_to_router_26_18_req; -floo_rsp_t router_26_18_to_router_26_19_rsp; - -floo_req_t router_26_19_to_router_26_20_req; -floo_rsp_t router_26_20_to_router_26_19_rsp; - -floo_req_t router_26_19_to_router_27_19_req; -floo_rsp_t router_27_19_to_router_26_19_rsp; - -floo_req_t router_26_19_to_magia_tile_ni_26_19_req; -floo_rsp_t magia_tile_ni_26_19_to_router_26_19_rsp; - -floo_req_t router_26_20_to_router_25_20_req; -floo_rsp_t router_25_20_to_router_26_20_rsp; - -floo_req_t router_26_20_to_router_26_19_req; -floo_rsp_t router_26_19_to_router_26_20_rsp; - -floo_req_t router_26_20_to_router_26_21_req; -floo_rsp_t router_26_21_to_router_26_20_rsp; - -floo_req_t router_26_20_to_router_27_20_req; -floo_rsp_t router_27_20_to_router_26_20_rsp; - -floo_req_t router_26_20_to_magia_tile_ni_26_20_req; -floo_rsp_t magia_tile_ni_26_20_to_router_26_20_rsp; - -floo_req_t router_26_21_to_router_25_21_req; -floo_rsp_t router_25_21_to_router_26_21_rsp; - -floo_req_t router_26_21_to_router_26_20_req; -floo_rsp_t router_26_20_to_router_26_21_rsp; - -floo_req_t router_26_21_to_router_26_22_req; -floo_rsp_t router_26_22_to_router_26_21_rsp; - -floo_req_t router_26_21_to_router_27_21_req; -floo_rsp_t router_27_21_to_router_26_21_rsp; - -floo_req_t router_26_21_to_magia_tile_ni_26_21_req; -floo_rsp_t magia_tile_ni_26_21_to_router_26_21_rsp; - -floo_req_t router_26_22_to_router_25_22_req; -floo_rsp_t router_25_22_to_router_26_22_rsp; - -floo_req_t router_26_22_to_router_26_21_req; -floo_rsp_t router_26_21_to_router_26_22_rsp; - -floo_req_t router_26_22_to_router_26_23_req; -floo_rsp_t router_26_23_to_router_26_22_rsp; - -floo_req_t router_26_22_to_router_27_22_req; -floo_rsp_t router_27_22_to_router_26_22_rsp; - -floo_req_t router_26_22_to_magia_tile_ni_26_22_req; -floo_rsp_t magia_tile_ni_26_22_to_router_26_22_rsp; - -floo_req_t router_26_23_to_router_25_23_req; -floo_rsp_t router_25_23_to_router_26_23_rsp; - -floo_req_t router_26_23_to_router_26_22_req; -floo_rsp_t router_26_22_to_router_26_23_rsp; - -floo_req_t router_26_23_to_router_26_24_req; -floo_rsp_t router_26_24_to_router_26_23_rsp; - -floo_req_t router_26_23_to_router_27_23_req; -floo_rsp_t router_27_23_to_router_26_23_rsp; - -floo_req_t router_26_23_to_magia_tile_ni_26_23_req; -floo_rsp_t magia_tile_ni_26_23_to_router_26_23_rsp; - -floo_req_t router_26_24_to_router_25_24_req; -floo_rsp_t router_25_24_to_router_26_24_rsp; - -floo_req_t router_26_24_to_router_26_23_req; -floo_rsp_t router_26_23_to_router_26_24_rsp; - -floo_req_t router_26_24_to_router_26_25_req; -floo_rsp_t router_26_25_to_router_26_24_rsp; - -floo_req_t router_26_24_to_router_27_24_req; -floo_rsp_t router_27_24_to_router_26_24_rsp; - -floo_req_t router_26_24_to_magia_tile_ni_26_24_req; -floo_rsp_t magia_tile_ni_26_24_to_router_26_24_rsp; - -floo_req_t router_26_25_to_router_25_25_req; -floo_rsp_t router_25_25_to_router_26_25_rsp; - -floo_req_t router_26_25_to_router_26_24_req; -floo_rsp_t router_26_24_to_router_26_25_rsp; - -floo_req_t router_26_25_to_router_26_26_req; -floo_rsp_t router_26_26_to_router_26_25_rsp; - -floo_req_t router_26_25_to_router_27_25_req; -floo_rsp_t router_27_25_to_router_26_25_rsp; - -floo_req_t router_26_25_to_magia_tile_ni_26_25_req; -floo_rsp_t magia_tile_ni_26_25_to_router_26_25_rsp; - -floo_req_t router_26_26_to_router_25_26_req; -floo_rsp_t router_25_26_to_router_26_26_rsp; - -floo_req_t router_26_26_to_router_26_25_req; -floo_rsp_t router_26_25_to_router_26_26_rsp; - -floo_req_t router_26_26_to_router_26_27_req; -floo_rsp_t router_26_27_to_router_26_26_rsp; - -floo_req_t router_26_26_to_router_27_26_req; -floo_rsp_t router_27_26_to_router_26_26_rsp; - -floo_req_t router_26_26_to_magia_tile_ni_26_26_req; -floo_rsp_t magia_tile_ni_26_26_to_router_26_26_rsp; - -floo_req_t router_26_27_to_router_25_27_req; -floo_rsp_t router_25_27_to_router_26_27_rsp; - -floo_req_t router_26_27_to_router_26_26_req; -floo_rsp_t router_26_26_to_router_26_27_rsp; - -floo_req_t router_26_27_to_router_26_28_req; -floo_rsp_t router_26_28_to_router_26_27_rsp; - -floo_req_t router_26_27_to_router_27_27_req; -floo_rsp_t router_27_27_to_router_26_27_rsp; - -floo_req_t router_26_27_to_magia_tile_ni_26_27_req; -floo_rsp_t magia_tile_ni_26_27_to_router_26_27_rsp; - -floo_req_t router_26_28_to_router_25_28_req; -floo_rsp_t router_25_28_to_router_26_28_rsp; - -floo_req_t router_26_28_to_router_26_27_req; -floo_rsp_t router_26_27_to_router_26_28_rsp; - -floo_req_t router_26_28_to_router_26_29_req; -floo_rsp_t router_26_29_to_router_26_28_rsp; - -floo_req_t router_26_28_to_router_27_28_req; -floo_rsp_t router_27_28_to_router_26_28_rsp; - -floo_req_t router_26_28_to_magia_tile_ni_26_28_req; -floo_rsp_t magia_tile_ni_26_28_to_router_26_28_rsp; - -floo_req_t router_26_29_to_router_25_29_req; -floo_rsp_t router_25_29_to_router_26_29_rsp; - -floo_req_t router_26_29_to_router_26_28_req; -floo_rsp_t router_26_28_to_router_26_29_rsp; - -floo_req_t router_26_29_to_router_26_30_req; -floo_rsp_t router_26_30_to_router_26_29_rsp; - -floo_req_t router_26_29_to_router_27_29_req; -floo_rsp_t router_27_29_to_router_26_29_rsp; - -floo_req_t router_26_29_to_magia_tile_ni_26_29_req; -floo_rsp_t magia_tile_ni_26_29_to_router_26_29_rsp; - -floo_req_t router_26_30_to_router_25_30_req; -floo_rsp_t router_25_30_to_router_26_30_rsp; - -floo_req_t router_26_30_to_router_26_29_req; -floo_rsp_t router_26_29_to_router_26_30_rsp; - -floo_req_t router_26_30_to_router_26_31_req; -floo_rsp_t router_26_31_to_router_26_30_rsp; - -floo_req_t router_26_30_to_router_27_30_req; -floo_rsp_t router_27_30_to_router_26_30_rsp; - -floo_req_t router_26_30_to_magia_tile_ni_26_30_req; -floo_rsp_t magia_tile_ni_26_30_to_router_26_30_rsp; - -floo_req_t router_26_31_to_router_25_31_req; -floo_rsp_t router_25_31_to_router_26_31_rsp; - -floo_req_t router_26_31_to_router_26_30_req; -floo_rsp_t router_26_30_to_router_26_31_rsp; - -floo_req_t router_26_31_to_router_27_31_req; -floo_rsp_t router_27_31_to_router_26_31_rsp; - -floo_req_t router_26_31_to_magia_tile_ni_26_31_req; -floo_rsp_t magia_tile_ni_26_31_to_router_26_31_rsp; - -floo_req_t router_27_0_to_router_26_0_req; -floo_rsp_t router_26_0_to_router_27_0_rsp; - -floo_req_t router_27_0_to_router_27_1_req; -floo_rsp_t router_27_1_to_router_27_0_rsp; - -floo_req_t router_27_0_to_router_28_0_req; -floo_rsp_t router_28_0_to_router_27_0_rsp; - -floo_req_t router_27_0_to_magia_tile_ni_27_0_req; -floo_rsp_t magia_tile_ni_27_0_to_router_27_0_rsp; - -floo_req_t router_27_1_to_router_26_1_req; -floo_rsp_t router_26_1_to_router_27_1_rsp; - -floo_req_t router_27_1_to_router_27_0_req; -floo_rsp_t router_27_0_to_router_27_1_rsp; - -floo_req_t router_27_1_to_router_27_2_req; -floo_rsp_t router_27_2_to_router_27_1_rsp; - -floo_req_t router_27_1_to_router_28_1_req; -floo_rsp_t router_28_1_to_router_27_1_rsp; - -floo_req_t router_27_1_to_magia_tile_ni_27_1_req; -floo_rsp_t magia_tile_ni_27_1_to_router_27_1_rsp; - -floo_req_t router_27_2_to_router_26_2_req; -floo_rsp_t router_26_2_to_router_27_2_rsp; - -floo_req_t router_27_2_to_router_27_1_req; -floo_rsp_t router_27_1_to_router_27_2_rsp; - -floo_req_t router_27_2_to_router_27_3_req; -floo_rsp_t router_27_3_to_router_27_2_rsp; - -floo_req_t router_27_2_to_router_28_2_req; -floo_rsp_t router_28_2_to_router_27_2_rsp; - -floo_req_t router_27_2_to_magia_tile_ni_27_2_req; -floo_rsp_t magia_tile_ni_27_2_to_router_27_2_rsp; - -floo_req_t router_27_3_to_router_26_3_req; -floo_rsp_t router_26_3_to_router_27_3_rsp; - -floo_req_t router_27_3_to_router_27_2_req; -floo_rsp_t router_27_2_to_router_27_3_rsp; - -floo_req_t router_27_3_to_router_27_4_req; -floo_rsp_t router_27_4_to_router_27_3_rsp; - -floo_req_t router_27_3_to_router_28_3_req; -floo_rsp_t router_28_3_to_router_27_3_rsp; - -floo_req_t router_27_3_to_magia_tile_ni_27_3_req; -floo_rsp_t magia_tile_ni_27_3_to_router_27_3_rsp; - -floo_req_t router_27_4_to_router_26_4_req; -floo_rsp_t router_26_4_to_router_27_4_rsp; - -floo_req_t router_27_4_to_router_27_3_req; -floo_rsp_t router_27_3_to_router_27_4_rsp; - -floo_req_t router_27_4_to_router_27_5_req; -floo_rsp_t router_27_5_to_router_27_4_rsp; - -floo_req_t router_27_4_to_router_28_4_req; -floo_rsp_t router_28_4_to_router_27_4_rsp; - -floo_req_t router_27_4_to_magia_tile_ni_27_4_req; -floo_rsp_t magia_tile_ni_27_4_to_router_27_4_rsp; - -floo_req_t router_27_5_to_router_26_5_req; -floo_rsp_t router_26_5_to_router_27_5_rsp; - -floo_req_t router_27_5_to_router_27_4_req; -floo_rsp_t router_27_4_to_router_27_5_rsp; - -floo_req_t router_27_5_to_router_27_6_req; -floo_rsp_t router_27_6_to_router_27_5_rsp; - -floo_req_t router_27_5_to_router_28_5_req; -floo_rsp_t router_28_5_to_router_27_5_rsp; - -floo_req_t router_27_5_to_magia_tile_ni_27_5_req; -floo_rsp_t magia_tile_ni_27_5_to_router_27_5_rsp; - -floo_req_t router_27_6_to_router_26_6_req; -floo_rsp_t router_26_6_to_router_27_6_rsp; - -floo_req_t router_27_6_to_router_27_5_req; -floo_rsp_t router_27_5_to_router_27_6_rsp; - -floo_req_t router_27_6_to_router_27_7_req; -floo_rsp_t router_27_7_to_router_27_6_rsp; - -floo_req_t router_27_6_to_router_28_6_req; -floo_rsp_t router_28_6_to_router_27_6_rsp; - -floo_req_t router_27_6_to_magia_tile_ni_27_6_req; -floo_rsp_t magia_tile_ni_27_6_to_router_27_6_rsp; - -floo_req_t router_27_7_to_router_26_7_req; -floo_rsp_t router_26_7_to_router_27_7_rsp; - -floo_req_t router_27_7_to_router_27_6_req; -floo_rsp_t router_27_6_to_router_27_7_rsp; - -floo_req_t router_27_7_to_router_27_8_req; -floo_rsp_t router_27_8_to_router_27_7_rsp; - -floo_req_t router_27_7_to_router_28_7_req; -floo_rsp_t router_28_7_to_router_27_7_rsp; - -floo_req_t router_27_7_to_magia_tile_ni_27_7_req; -floo_rsp_t magia_tile_ni_27_7_to_router_27_7_rsp; - -floo_req_t router_27_8_to_router_26_8_req; -floo_rsp_t router_26_8_to_router_27_8_rsp; - -floo_req_t router_27_8_to_router_27_7_req; -floo_rsp_t router_27_7_to_router_27_8_rsp; - -floo_req_t router_27_8_to_router_27_9_req; -floo_rsp_t router_27_9_to_router_27_8_rsp; - -floo_req_t router_27_8_to_router_28_8_req; -floo_rsp_t router_28_8_to_router_27_8_rsp; - -floo_req_t router_27_8_to_magia_tile_ni_27_8_req; -floo_rsp_t magia_tile_ni_27_8_to_router_27_8_rsp; - -floo_req_t router_27_9_to_router_26_9_req; -floo_rsp_t router_26_9_to_router_27_9_rsp; - -floo_req_t router_27_9_to_router_27_8_req; -floo_rsp_t router_27_8_to_router_27_9_rsp; - -floo_req_t router_27_9_to_router_27_10_req; -floo_rsp_t router_27_10_to_router_27_9_rsp; - -floo_req_t router_27_9_to_router_28_9_req; -floo_rsp_t router_28_9_to_router_27_9_rsp; - -floo_req_t router_27_9_to_magia_tile_ni_27_9_req; -floo_rsp_t magia_tile_ni_27_9_to_router_27_9_rsp; - -floo_req_t router_27_10_to_router_26_10_req; -floo_rsp_t router_26_10_to_router_27_10_rsp; - -floo_req_t router_27_10_to_router_27_9_req; -floo_rsp_t router_27_9_to_router_27_10_rsp; - -floo_req_t router_27_10_to_router_27_11_req; -floo_rsp_t router_27_11_to_router_27_10_rsp; - -floo_req_t router_27_10_to_router_28_10_req; -floo_rsp_t router_28_10_to_router_27_10_rsp; - -floo_req_t router_27_10_to_magia_tile_ni_27_10_req; -floo_rsp_t magia_tile_ni_27_10_to_router_27_10_rsp; - -floo_req_t router_27_11_to_router_26_11_req; -floo_rsp_t router_26_11_to_router_27_11_rsp; - -floo_req_t router_27_11_to_router_27_10_req; -floo_rsp_t router_27_10_to_router_27_11_rsp; - -floo_req_t router_27_11_to_router_27_12_req; -floo_rsp_t router_27_12_to_router_27_11_rsp; - -floo_req_t router_27_11_to_router_28_11_req; -floo_rsp_t router_28_11_to_router_27_11_rsp; - -floo_req_t router_27_11_to_magia_tile_ni_27_11_req; -floo_rsp_t magia_tile_ni_27_11_to_router_27_11_rsp; - -floo_req_t router_27_12_to_router_26_12_req; -floo_rsp_t router_26_12_to_router_27_12_rsp; - -floo_req_t router_27_12_to_router_27_11_req; -floo_rsp_t router_27_11_to_router_27_12_rsp; - -floo_req_t router_27_12_to_router_27_13_req; -floo_rsp_t router_27_13_to_router_27_12_rsp; - -floo_req_t router_27_12_to_router_28_12_req; -floo_rsp_t router_28_12_to_router_27_12_rsp; - -floo_req_t router_27_12_to_magia_tile_ni_27_12_req; -floo_rsp_t magia_tile_ni_27_12_to_router_27_12_rsp; - -floo_req_t router_27_13_to_router_26_13_req; -floo_rsp_t router_26_13_to_router_27_13_rsp; - -floo_req_t router_27_13_to_router_27_12_req; -floo_rsp_t router_27_12_to_router_27_13_rsp; - -floo_req_t router_27_13_to_router_27_14_req; -floo_rsp_t router_27_14_to_router_27_13_rsp; - -floo_req_t router_27_13_to_router_28_13_req; -floo_rsp_t router_28_13_to_router_27_13_rsp; - -floo_req_t router_27_13_to_magia_tile_ni_27_13_req; -floo_rsp_t magia_tile_ni_27_13_to_router_27_13_rsp; - -floo_req_t router_27_14_to_router_26_14_req; -floo_rsp_t router_26_14_to_router_27_14_rsp; - -floo_req_t router_27_14_to_router_27_13_req; -floo_rsp_t router_27_13_to_router_27_14_rsp; - -floo_req_t router_27_14_to_router_27_15_req; -floo_rsp_t router_27_15_to_router_27_14_rsp; - -floo_req_t router_27_14_to_router_28_14_req; -floo_rsp_t router_28_14_to_router_27_14_rsp; - -floo_req_t router_27_14_to_magia_tile_ni_27_14_req; -floo_rsp_t magia_tile_ni_27_14_to_router_27_14_rsp; - -floo_req_t router_27_15_to_router_26_15_req; -floo_rsp_t router_26_15_to_router_27_15_rsp; - -floo_req_t router_27_15_to_router_27_14_req; -floo_rsp_t router_27_14_to_router_27_15_rsp; - -floo_req_t router_27_15_to_router_27_16_req; -floo_rsp_t router_27_16_to_router_27_15_rsp; - -floo_req_t router_27_15_to_router_28_15_req; -floo_rsp_t router_28_15_to_router_27_15_rsp; - -floo_req_t router_27_15_to_magia_tile_ni_27_15_req; -floo_rsp_t magia_tile_ni_27_15_to_router_27_15_rsp; - -floo_req_t router_27_16_to_router_26_16_req; -floo_rsp_t router_26_16_to_router_27_16_rsp; - -floo_req_t router_27_16_to_router_27_15_req; -floo_rsp_t router_27_15_to_router_27_16_rsp; - -floo_req_t router_27_16_to_router_27_17_req; -floo_rsp_t router_27_17_to_router_27_16_rsp; - -floo_req_t router_27_16_to_router_28_16_req; -floo_rsp_t router_28_16_to_router_27_16_rsp; - -floo_req_t router_27_16_to_magia_tile_ni_27_16_req; -floo_rsp_t magia_tile_ni_27_16_to_router_27_16_rsp; - -floo_req_t router_27_17_to_router_26_17_req; -floo_rsp_t router_26_17_to_router_27_17_rsp; - -floo_req_t router_27_17_to_router_27_16_req; -floo_rsp_t router_27_16_to_router_27_17_rsp; - -floo_req_t router_27_17_to_router_27_18_req; -floo_rsp_t router_27_18_to_router_27_17_rsp; - -floo_req_t router_27_17_to_router_28_17_req; -floo_rsp_t router_28_17_to_router_27_17_rsp; - -floo_req_t router_27_17_to_magia_tile_ni_27_17_req; -floo_rsp_t magia_tile_ni_27_17_to_router_27_17_rsp; - -floo_req_t router_27_18_to_router_26_18_req; -floo_rsp_t router_26_18_to_router_27_18_rsp; - -floo_req_t router_27_18_to_router_27_17_req; -floo_rsp_t router_27_17_to_router_27_18_rsp; - -floo_req_t router_27_18_to_router_27_19_req; -floo_rsp_t router_27_19_to_router_27_18_rsp; - -floo_req_t router_27_18_to_router_28_18_req; -floo_rsp_t router_28_18_to_router_27_18_rsp; - -floo_req_t router_27_18_to_magia_tile_ni_27_18_req; -floo_rsp_t magia_tile_ni_27_18_to_router_27_18_rsp; - -floo_req_t router_27_19_to_router_26_19_req; -floo_rsp_t router_26_19_to_router_27_19_rsp; - -floo_req_t router_27_19_to_router_27_18_req; -floo_rsp_t router_27_18_to_router_27_19_rsp; - -floo_req_t router_27_19_to_router_27_20_req; -floo_rsp_t router_27_20_to_router_27_19_rsp; - -floo_req_t router_27_19_to_router_28_19_req; -floo_rsp_t router_28_19_to_router_27_19_rsp; - -floo_req_t router_27_19_to_magia_tile_ni_27_19_req; -floo_rsp_t magia_tile_ni_27_19_to_router_27_19_rsp; - -floo_req_t router_27_20_to_router_26_20_req; -floo_rsp_t router_26_20_to_router_27_20_rsp; - -floo_req_t router_27_20_to_router_27_19_req; -floo_rsp_t router_27_19_to_router_27_20_rsp; - -floo_req_t router_27_20_to_router_27_21_req; -floo_rsp_t router_27_21_to_router_27_20_rsp; - -floo_req_t router_27_20_to_router_28_20_req; -floo_rsp_t router_28_20_to_router_27_20_rsp; - -floo_req_t router_27_20_to_magia_tile_ni_27_20_req; -floo_rsp_t magia_tile_ni_27_20_to_router_27_20_rsp; - -floo_req_t router_27_21_to_router_26_21_req; -floo_rsp_t router_26_21_to_router_27_21_rsp; - -floo_req_t router_27_21_to_router_27_20_req; -floo_rsp_t router_27_20_to_router_27_21_rsp; - -floo_req_t router_27_21_to_router_27_22_req; -floo_rsp_t router_27_22_to_router_27_21_rsp; - -floo_req_t router_27_21_to_router_28_21_req; -floo_rsp_t router_28_21_to_router_27_21_rsp; - -floo_req_t router_27_21_to_magia_tile_ni_27_21_req; -floo_rsp_t magia_tile_ni_27_21_to_router_27_21_rsp; - -floo_req_t router_27_22_to_router_26_22_req; -floo_rsp_t router_26_22_to_router_27_22_rsp; - -floo_req_t router_27_22_to_router_27_21_req; -floo_rsp_t router_27_21_to_router_27_22_rsp; - -floo_req_t router_27_22_to_router_27_23_req; -floo_rsp_t router_27_23_to_router_27_22_rsp; - -floo_req_t router_27_22_to_router_28_22_req; -floo_rsp_t router_28_22_to_router_27_22_rsp; - -floo_req_t router_27_22_to_magia_tile_ni_27_22_req; -floo_rsp_t magia_tile_ni_27_22_to_router_27_22_rsp; - -floo_req_t router_27_23_to_router_26_23_req; -floo_rsp_t router_26_23_to_router_27_23_rsp; - -floo_req_t router_27_23_to_router_27_22_req; -floo_rsp_t router_27_22_to_router_27_23_rsp; - -floo_req_t router_27_23_to_router_27_24_req; -floo_rsp_t router_27_24_to_router_27_23_rsp; - -floo_req_t router_27_23_to_router_28_23_req; -floo_rsp_t router_28_23_to_router_27_23_rsp; - -floo_req_t router_27_23_to_magia_tile_ni_27_23_req; -floo_rsp_t magia_tile_ni_27_23_to_router_27_23_rsp; - -floo_req_t router_27_24_to_router_26_24_req; -floo_rsp_t router_26_24_to_router_27_24_rsp; - -floo_req_t router_27_24_to_router_27_23_req; -floo_rsp_t router_27_23_to_router_27_24_rsp; - -floo_req_t router_27_24_to_router_27_25_req; -floo_rsp_t router_27_25_to_router_27_24_rsp; - -floo_req_t router_27_24_to_router_28_24_req; -floo_rsp_t router_28_24_to_router_27_24_rsp; - -floo_req_t router_27_24_to_magia_tile_ni_27_24_req; -floo_rsp_t magia_tile_ni_27_24_to_router_27_24_rsp; - -floo_req_t router_27_25_to_router_26_25_req; -floo_rsp_t router_26_25_to_router_27_25_rsp; - -floo_req_t router_27_25_to_router_27_24_req; -floo_rsp_t router_27_24_to_router_27_25_rsp; - -floo_req_t router_27_25_to_router_27_26_req; -floo_rsp_t router_27_26_to_router_27_25_rsp; - -floo_req_t router_27_25_to_router_28_25_req; -floo_rsp_t router_28_25_to_router_27_25_rsp; - -floo_req_t router_27_25_to_magia_tile_ni_27_25_req; -floo_rsp_t magia_tile_ni_27_25_to_router_27_25_rsp; - -floo_req_t router_27_26_to_router_26_26_req; -floo_rsp_t router_26_26_to_router_27_26_rsp; - -floo_req_t router_27_26_to_router_27_25_req; -floo_rsp_t router_27_25_to_router_27_26_rsp; - -floo_req_t router_27_26_to_router_27_27_req; -floo_rsp_t router_27_27_to_router_27_26_rsp; - -floo_req_t router_27_26_to_router_28_26_req; -floo_rsp_t router_28_26_to_router_27_26_rsp; - -floo_req_t router_27_26_to_magia_tile_ni_27_26_req; -floo_rsp_t magia_tile_ni_27_26_to_router_27_26_rsp; - -floo_req_t router_27_27_to_router_26_27_req; -floo_rsp_t router_26_27_to_router_27_27_rsp; - -floo_req_t router_27_27_to_router_27_26_req; -floo_rsp_t router_27_26_to_router_27_27_rsp; - -floo_req_t router_27_27_to_router_27_28_req; -floo_rsp_t router_27_28_to_router_27_27_rsp; - -floo_req_t router_27_27_to_router_28_27_req; -floo_rsp_t router_28_27_to_router_27_27_rsp; - -floo_req_t router_27_27_to_magia_tile_ni_27_27_req; -floo_rsp_t magia_tile_ni_27_27_to_router_27_27_rsp; - -floo_req_t router_27_28_to_router_26_28_req; -floo_rsp_t router_26_28_to_router_27_28_rsp; - -floo_req_t router_27_28_to_router_27_27_req; -floo_rsp_t router_27_27_to_router_27_28_rsp; - -floo_req_t router_27_28_to_router_27_29_req; -floo_rsp_t router_27_29_to_router_27_28_rsp; - -floo_req_t router_27_28_to_router_28_28_req; -floo_rsp_t router_28_28_to_router_27_28_rsp; - -floo_req_t router_27_28_to_magia_tile_ni_27_28_req; -floo_rsp_t magia_tile_ni_27_28_to_router_27_28_rsp; - -floo_req_t router_27_29_to_router_26_29_req; -floo_rsp_t router_26_29_to_router_27_29_rsp; - -floo_req_t router_27_29_to_router_27_28_req; -floo_rsp_t router_27_28_to_router_27_29_rsp; - -floo_req_t router_27_29_to_router_27_30_req; -floo_rsp_t router_27_30_to_router_27_29_rsp; - -floo_req_t router_27_29_to_router_28_29_req; -floo_rsp_t router_28_29_to_router_27_29_rsp; - -floo_req_t router_27_29_to_magia_tile_ni_27_29_req; -floo_rsp_t magia_tile_ni_27_29_to_router_27_29_rsp; - -floo_req_t router_27_30_to_router_26_30_req; -floo_rsp_t router_26_30_to_router_27_30_rsp; - -floo_req_t router_27_30_to_router_27_29_req; -floo_rsp_t router_27_29_to_router_27_30_rsp; - -floo_req_t router_27_30_to_router_27_31_req; -floo_rsp_t router_27_31_to_router_27_30_rsp; - -floo_req_t router_27_30_to_router_28_30_req; -floo_rsp_t router_28_30_to_router_27_30_rsp; - -floo_req_t router_27_30_to_magia_tile_ni_27_30_req; -floo_rsp_t magia_tile_ni_27_30_to_router_27_30_rsp; - -floo_req_t router_27_31_to_router_26_31_req; -floo_rsp_t router_26_31_to_router_27_31_rsp; - -floo_req_t router_27_31_to_router_27_30_req; -floo_rsp_t router_27_30_to_router_27_31_rsp; - -floo_req_t router_27_31_to_router_28_31_req; -floo_rsp_t router_28_31_to_router_27_31_rsp; - -floo_req_t router_27_31_to_magia_tile_ni_27_31_req; -floo_rsp_t magia_tile_ni_27_31_to_router_27_31_rsp; - -floo_req_t router_28_0_to_router_27_0_req; -floo_rsp_t router_27_0_to_router_28_0_rsp; - -floo_req_t router_28_0_to_router_28_1_req; -floo_rsp_t router_28_1_to_router_28_0_rsp; - -floo_req_t router_28_0_to_router_29_0_req; -floo_rsp_t router_29_0_to_router_28_0_rsp; - -floo_req_t router_28_0_to_magia_tile_ni_28_0_req; -floo_rsp_t magia_tile_ni_28_0_to_router_28_0_rsp; - -floo_req_t router_28_1_to_router_27_1_req; -floo_rsp_t router_27_1_to_router_28_1_rsp; - -floo_req_t router_28_1_to_router_28_0_req; -floo_rsp_t router_28_0_to_router_28_1_rsp; - -floo_req_t router_28_1_to_router_28_2_req; -floo_rsp_t router_28_2_to_router_28_1_rsp; - -floo_req_t router_28_1_to_router_29_1_req; -floo_rsp_t router_29_1_to_router_28_1_rsp; - -floo_req_t router_28_1_to_magia_tile_ni_28_1_req; -floo_rsp_t magia_tile_ni_28_1_to_router_28_1_rsp; - -floo_req_t router_28_2_to_router_27_2_req; -floo_rsp_t router_27_2_to_router_28_2_rsp; - -floo_req_t router_28_2_to_router_28_1_req; -floo_rsp_t router_28_1_to_router_28_2_rsp; - -floo_req_t router_28_2_to_router_28_3_req; -floo_rsp_t router_28_3_to_router_28_2_rsp; - -floo_req_t router_28_2_to_router_29_2_req; -floo_rsp_t router_29_2_to_router_28_2_rsp; - -floo_req_t router_28_2_to_magia_tile_ni_28_2_req; -floo_rsp_t magia_tile_ni_28_2_to_router_28_2_rsp; - -floo_req_t router_28_3_to_router_27_3_req; -floo_rsp_t router_27_3_to_router_28_3_rsp; - -floo_req_t router_28_3_to_router_28_2_req; -floo_rsp_t router_28_2_to_router_28_3_rsp; - -floo_req_t router_28_3_to_router_28_4_req; -floo_rsp_t router_28_4_to_router_28_3_rsp; - -floo_req_t router_28_3_to_router_29_3_req; -floo_rsp_t router_29_3_to_router_28_3_rsp; - -floo_req_t router_28_3_to_magia_tile_ni_28_3_req; -floo_rsp_t magia_tile_ni_28_3_to_router_28_3_rsp; - -floo_req_t router_28_4_to_router_27_4_req; -floo_rsp_t router_27_4_to_router_28_4_rsp; - -floo_req_t router_28_4_to_router_28_3_req; -floo_rsp_t router_28_3_to_router_28_4_rsp; - -floo_req_t router_28_4_to_router_28_5_req; -floo_rsp_t router_28_5_to_router_28_4_rsp; - -floo_req_t router_28_4_to_router_29_4_req; -floo_rsp_t router_29_4_to_router_28_4_rsp; - -floo_req_t router_28_4_to_magia_tile_ni_28_4_req; -floo_rsp_t magia_tile_ni_28_4_to_router_28_4_rsp; - -floo_req_t router_28_5_to_router_27_5_req; -floo_rsp_t router_27_5_to_router_28_5_rsp; - -floo_req_t router_28_5_to_router_28_4_req; -floo_rsp_t router_28_4_to_router_28_5_rsp; - -floo_req_t router_28_5_to_router_28_6_req; -floo_rsp_t router_28_6_to_router_28_5_rsp; - -floo_req_t router_28_5_to_router_29_5_req; -floo_rsp_t router_29_5_to_router_28_5_rsp; - -floo_req_t router_28_5_to_magia_tile_ni_28_5_req; -floo_rsp_t magia_tile_ni_28_5_to_router_28_5_rsp; - -floo_req_t router_28_6_to_router_27_6_req; -floo_rsp_t router_27_6_to_router_28_6_rsp; - -floo_req_t router_28_6_to_router_28_5_req; -floo_rsp_t router_28_5_to_router_28_6_rsp; - -floo_req_t router_28_6_to_router_28_7_req; -floo_rsp_t router_28_7_to_router_28_6_rsp; - -floo_req_t router_28_6_to_router_29_6_req; -floo_rsp_t router_29_6_to_router_28_6_rsp; - -floo_req_t router_28_6_to_magia_tile_ni_28_6_req; -floo_rsp_t magia_tile_ni_28_6_to_router_28_6_rsp; - -floo_req_t router_28_7_to_router_27_7_req; -floo_rsp_t router_27_7_to_router_28_7_rsp; - -floo_req_t router_28_7_to_router_28_6_req; -floo_rsp_t router_28_6_to_router_28_7_rsp; - -floo_req_t router_28_7_to_router_28_8_req; -floo_rsp_t router_28_8_to_router_28_7_rsp; - -floo_req_t router_28_7_to_router_29_7_req; -floo_rsp_t router_29_7_to_router_28_7_rsp; - -floo_req_t router_28_7_to_magia_tile_ni_28_7_req; -floo_rsp_t magia_tile_ni_28_7_to_router_28_7_rsp; - -floo_req_t router_28_8_to_router_27_8_req; -floo_rsp_t router_27_8_to_router_28_8_rsp; - -floo_req_t router_28_8_to_router_28_7_req; -floo_rsp_t router_28_7_to_router_28_8_rsp; - -floo_req_t router_28_8_to_router_28_9_req; -floo_rsp_t router_28_9_to_router_28_8_rsp; - -floo_req_t router_28_8_to_router_29_8_req; -floo_rsp_t router_29_8_to_router_28_8_rsp; - -floo_req_t router_28_8_to_magia_tile_ni_28_8_req; -floo_rsp_t magia_tile_ni_28_8_to_router_28_8_rsp; - -floo_req_t router_28_9_to_router_27_9_req; -floo_rsp_t router_27_9_to_router_28_9_rsp; - -floo_req_t router_28_9_to_router_28_8_req; -floo_rsp_t router_28_8_to_router_28_9_rsp; - -floo_req_t router_28_9_to_router_28_10_req; -floo_rsp_t router_28_10_to_router_28_9_rsp; - -floo_req_t router_28_9_to_router_29_9_req; -floo_rsp_t router_29_9_to_router_28_9_rsp; - -floo_req_t router_28_9_to_magia_tile_ni_28_9_req; -floo_rsp_t magia_tile_ni_28_9_to_router_28_9_rsp; - -floo_req_t router_28_10_to_router_27_10_req; -floo_rsp_t router_27_10_to_router_28_10_rsp; - -floo_req_t router_28_10_to_router_28_9_req; -floo_rsp_t router_28_9_to_router_28_10_rsp; - -floo_req_t router_28_10_to_router_28_11_req; -floo_rsp_t router_28_11_to_router_28_10_rsp; - -floo_req_t router_28_10_to_router_29_10_req; -floo_rsp_t router_29_10_to_router_28_10_rsp; - -floo_req_t router_28_10_to_magia_tile_ni_28_10_req; -floo_rsp_t magia_tile_ni_28_10_to_router_28_10_rsp; - -floo_req_t router_28_11_to_router_27_11_req; -floo_rsp_t router_27_11_to_router_28_11_rsp; - -floo_req_t router_28_11_to_router_28_10_req; -floo_rsp_t router_28_10_to_router_28_11_rsp; - -floo_req_t router_28_11_to_router_28_12_req; -floo_rsp_t router_28_12_to_router_28_11_rsp; - -floo_req_t router_28_11_to_router_29_11_req; -floo_rsp_t router_29_11_to_router_28_11_rsp; - -floo_req_t router_28_11_to_magia_tile_ni_28_11_req; -floo_rsp_t magia_tile_ni_28_11_to_router_28_11_rsp; - -floo_req_t router_28_12_to_router_27_12_req; -floo_rsp_t router_27_12_to_router_28_12_rsp; - -floo_req_t router_28_12_to_router_28_11_req; -floo_rsp_t router_28_11_to_router_28_12_rsp; - -floo_req_t router_28_12_to_router_28_13_req; -floo_rsp_t router_28_13_to_router_28_12_rsp; - -floo_req_t router_28_12_to_router_29_12_req; -floo_rsp_t router_29_12_to_router_28_12_rsp; - -floo_req_t router_28_12_to_magia_tile_ni_28_12_req; -floo_rsp_t magia_tile_ni_28_12_to_router_28_12_rsp; - -floo_req_t router_28_13_to_router_27_13_req; -floo_rsp_t router_27_13_to_router_28_13_rsp; - -floo_req_t router_28_13_to_router_28_12_req; -floo_rsp_t router_28_12_to_router_28_13_rsp; - -floo_req_t router_28_13_to_router_28_14_req; -floo_rsp_t router_28_14_to_router_28_13_rsp; - -floo_req_t router_28_13_to_router_29_13_req; -floo_rsp_t router_29_13_to_router_28_13_rsp; - -floo_req_t router_28_13_to_magia_tile_ni_28_13_req; -floo_rsp_t magia_tile_ni_28_13_to_router_28_13_rsp; - -floo_req_t router_28_14_to_router_27_14_req; -floo_rsp_t router_27_14_to_router_28_14_rsp; - -floo_req_t router_28_14_to_router_28_13_req; -floo_rsp_t router_28_13_to_router_28_14_rsp; - -floo_req_t router_28_14_to_router_28_15_req; -floo_rsp_t router_28_15_to_router_28_14_rsp; - -floo_req_t router_28_14_to_router_29_14_req; -floo_rsp_t router_29_14_to_router_28_14_rsp; - -floo_req_t router_28_14_to_magia_tile_ni_28_14_req; -floo_rsp_t magia_tile_ni_28_14_to_router_28_14_rsp; - -floo_req_t router_28_15_to_router_27_15_req; -floo_rsp_t router_27_15_to_router_28_15_rsp; - -floo_req_t router_28_15_to_router_28_14_req; -floo_rsp_t router_28_14_to_router_28_15_rsp; - -floo_req_t router_28_15_to_router_28_16_req; -floo_rsp_t router_28_16_to_router_28_15_rsp; - -floo_req_t router_28_15_to_router_29_15_req; -floo_rsp_t router_29_15_to_router_28_15_rsp; - -floo_req_t router_28_15_to_magia_tile_ni_28_15_req; -floo_rsp_t magia_tile_ni_28_15_to_router_28_15_rsp; - -floo_req_t router_28_16_to_router_27_16_req; -floo_rsp_t router_27_16_to_router_28_16_rsp; - -floo_req_t router_28_16_to_router_28_15_req; -floo_rsp_t router_28_15_to_router_28_16_rsp; - -floo_req_t router_28_16_to_router_28_17_req; -floo_rsp_t router_28_17_to_router_28_16_rsp; - -floo_req_t router_28_16_to_router_29_16_req; -floo_rsp_t router_29_16_to_router_28_16_rsp; - -floo_req_t router_28_16_to_magia_tile_ni_28_16_req; -floo_rsp_t magia_tile_ni_28_16_to_router_28_16_rsp; - -floo_req_t router_28_17_to_router_27_17_req; -floo_rsp_t router_27_17_to_router_28_17_rsp; - -floo_req_t router_28_17_to_router_28_16_req; -floo_rsp_t router_28_16_to_router_28_17_rsp; - -floo_req_t router_28_17_to_router_28_18_req; -floo_rsp_t router_28_18_to_router_28_17_rsp; - -floo_req_t router_28_17_to_router_29_17_req; -floo_rsp_t router_29_17_to_router_28_17_rsp; - -floo_req_t router_28_17_to_magia_tile_ni_28_17_req; -floo_rsp_t magia_tile_ni_28_17_to_router_28_17_rsp; - -floo_req_t router_28_18_to_router_27_18_req; -floo_rsp_t router_27_18_to_router_28_18_rsp; - -floo_req_t router_28_18_to_router_28_17_req; -floo_rsp_t router_28_17_to_router_28_18_rsp; - -floo_req_t router_28_18_to_router_28_19_req; -floo_rsp_t router_28_19_to_router_28_18_rsp; - -floo_req_t router_28_18_to_router_29_18_req; -floo_rsp_t router_29_18_to_router_28_18_rsp; - -floo_req_t router_28_18_to_magia_tile_ni_28_18_req; -floo_rsp_t magia_tile_ni_28_18_to_router_28_18_rsp; - -floo_req_t router_28_19_to_router_27_19_req; -floo_rsp_t router_27_19_to_router_28_19_rsp; - -floo_req_t router_28_19_to_router_28_18_req; -floo_rsp_t router_28_18_to_router_28_19_rsp; - -floo_req_t router_28_19_to_router_28_20_req; -floo_rsp_t router_28_20_to_router_28_19_rsp; - -floo_req_t router_28_19_to_router_29_19_req; -floo_rsp_t router_29_19_to_router_28_19_rsp; - -floo_req_t router_28_19_to_magia_tile_ni_28_19_req; -floo_rsp_t magia_tile_ni_28_19_to_router_28_19_rsp; - -floo_req_t router_28_20_to_router_27_20_req; -floo_rsp_t router_27_20_to_router_28_20_rsp; - -floo_req_t router_28_20_to_router_28_19_req; -floo_rsp_t router_28_19_to_router_28_20_rsp; - -floo_req_t router_28_20_to_router_28_21_req; -floo_rsp_t router_28_21_to_router_28_20_rsp; - -floo_req_t router_28_20_to_router_29_20_req; -floo_rsp_t router_29_20_to_router_28_20_rsp; - -floo_req_t router_28_20_to_magia_tile_ni_28_20_req; -floo_rsp_t magia_tile_ni_28_20_to_router_28_20_rsp; - -floo_req_t router_28_21_to_router_27_21_req; -floo_rsp_t router_27_21_to_router_28_21_rsp; - -floo_req_t router_28_21_to_router_28_20_req; -floo_rsp_t router_28_20_to_router_28_21_rsp; - -floo_req_t router_28_21_to_router_28_22_req; -floo_rsp_t router_28_22_to_router_28_21_rsp; - -floo_req_t router_28_21_to_router_29_21_req; -floo_rsp_t router_29_21_to_router_28_21_rsp; - -floo_req_t router_28_21_to_magia_tile_ni_28_21_req; -floo_rsp_t magia_tile_ni_28_21_to_router_28_21_rsp; - -floo_req_t router_28_22_to_router_27_22_req; -floo_rsp_t router_27_22_to_router_28_22_rsp; - -floo_req_t router_28_22_to_router_28_21_req; -floo_rsp_t router_28_21_to_router_28_22_rsp; - -floo_req_t router_28_22_to_router_28_23_req; -floo_rsp_t router_28_23_to_router_28_22_rsp; - -floo_req_t router_28_22_to_router_29_22_req; -floo_rsp_t router_29_22_to_router_28_22_rsp; - -floo_req_t router_28_22_to_magia_tile_ni_28_22_req; -floo_rsp_t magia_tile_ni_28_22_to_router_28_22_rsp; - -floo_req_t router_28_23_to_router_27_23_req; -floo_rsp_t router_27_23_to_router_28_23_rsp; - -floo_req_t router_28_23_to_router_28_22_req; -floo_rsp_t router_28_22_to_router_28_23_rsp; - -floo_req_t router_28_23_to_router_28_24_req; -floo_rsp_t router_28_24_to_router_28_23_rsp; - -floo_req_t router_28_23_to_router_29_23_req; -floo_rsp_t router_29_23_to_router_28_23_rsp; - -floo_req_t router_28_23_to_magia_tile_ni_28_23_req; -floo_rsp_t magia_tile_ni_28_23_to_router_28_23_rsp; - -floo_req_t router_28_24_to_router_27_24_req; -floo_rsp_t router_27_24_to_router_28_24_rsp; - -floo_req_t router_28_24_to_router_28_23_req; -floo_rsp_t router_28_23_to_router_28_24_rsp; - -floo_req_t router_28_24_to_router_28_25_req; -floo_rsp_t router_28_25_to_router_28_24_rsp; - -floo_req_t router_28_24_to_router_29_24_req; -floo_rsp_t router_29_24_to_router_28_24_rsp; - -floo_req_t router_28_24_to_magia_tile_ni_28_24_req; -floo_rsp_t magia_tile_ni_28_24_to_router_28_24_rsp; - -floo_req_t router_28_25_to_router_27_25_req; -floo_rsp_t router_27_25_to_router_28_25_rsp; - -floo_req_t router_28_25_to_router_28_24_req; -floo_rsp_t router_28_24_to_router_28_25_rsp; - -floo_req_t router_28_25_to_router_28_26_req; -floo_rsp_t router_28_26_to_router_28_25_rsp; - -floo_req_t router_28_25_to_router_29_25_req; -floo_rsp_t router_29_25_to_router_28_25_rsp; - -floo_req_t router_28_25_to_magia_tile_ni_28_25_req; -floo_rsp_t magia_tile_ni_28_25_to_router_28_25_rsp; - -floo_req_t router_28_26_to_router_27_26_req; -floo_rsp_t router_27_26_to_router_28_26_rsp; - -floo_req_t router_28_26_to_router_28_25_req; -floo_rsp_t router_28_25_to_router_28_26_rsp; - -floo_req_t router_28_26_to_router_28_27_req; -floo_rsp_t router_28_27_to_router_28_26_rsp; - -floo_req_t router_28_26_to_router_29_26_req; -floo_rsp_t router_29_26_to_router_28_26_rsp; - -floo_req_t router_28_26_to_magia_tile_ni_28_26_req; -floo_rsp_t magia_tile_ni_28_26_to_router_28_26_rsp; - -floo_req_t router_28_27_to_router_27_27_req; -floo_rsp_t router_27_27_to_router_28_27_rsp; - -floo_req_t router_28_27_to_router_28_26_req; -floo_rsp_t router_28_26_to_router_28_27_rsp; - -floo_req_t router_28_27_to_router_28_28_req; -floo_rsp_t router_28_28_to_router_28_27_rsp; - -floo_req_t router_28_27_to_router_29_27_req; -floo_rsp_t router_29_27_to_router_28_27_rsp; - -floo_req_t router_28_27_to_magia_tile_ni_28_27_req; -floo_rsp_t magia_tile_ni_28_27_to_router_28_27_rsp; - -floo_req_t router_28_28_to_router_27_28_req; -floo_rsp_t router_27_28_to_router_28_28_rsp; - -floo_req_t router_28_28_to_router_28_27_req; -floo_rsp_t router_28_27_to_router_28_28_rsp; - -floo_req_t router_28_28_to_router_28_29_req; -floo_rsp_t router_28_29_to_router_28_28_rsp; - -floo_req_t router_28_28_to_router_29_28_req; -floo_rsp_t router_29_28_to_router_28_28_rsp; - -floo_req_t router_28_28_to_magia_tile_ni_28_28_req; -floo_rsp_t magia_tile_ni_28_28_to_router_28_28_rsp; - -floo_req_t router_28_29_to_router_27_29_req; -floo_rsp_t router_27_29_to_router_28_29_rsp; - -floo_req_t router_28_29_to_router_28_28_req; -floo_rsp_t router_28_28_to_router_28_29_rsp; - -floo_req_t router_28_29_to_router_28_30_req; -floo_rsp_t router_28_30_to_router_28_29_rsp; - -floo_req_t router_28_29_to_router_29_29_req; -floo_rsp_t router_29_29_to_router_28_29_rsp; - -floo_req_t router_28_29_to_magia_tile_ni_28_29_req; -floo_rsp_t magia_tile_ni_28_29_to_router_28_29_rsp; - -floo_req_t router_28_30_to_router_27_30_req; -floo_rsp_t router_27_30_to_router_28_30_rsp; - -floo_req_t router_28_30_to_router_28_29_req; -floo_rsp_t router_28_29_to_router_28_30_rsp; - -floo_req_t router_28_30_to_router_28_31_req; -floo_rsp_t router_28_31_to_router_28_30_rsp; - -floo_req_t router_28_30_to_router_29_30_req; -floo_rsp_t router_29_30_to_router_28_30_rsp; - -floo_req_t router_28_30_to_magia_tile_ni_28_30_req; -floo_rsp_t magia_tile_ni_28_30_to_router_28_30_rsp; - -floo_req_t router_28_31_to_router_27_31_req; -floo_rsp_t router_27_31_to_router_28_31_rsp; - -floo_req_t router_28_31_to_router_28_30_req; -floo_rsp_t router_28_30_to_router_28_31_rsp; - -floo_req_t router_28_31_to_router_29_31_req; -floo_rsp_t router_29_31_to_router_28_31_rsp; - -floo_req_t router_28_31_to_magia_tile_ni_28_31_req; -floo_rsp_t magia_tile_ni_28_31_to_router_28_31_rsp; - -floo_req_t router_29_0_to_router_28_0_req; -floo_rsp_t router_28_0_to_router_29_0_rsp; - -floo_req_t router_29_0_to_router_29_1_req; -floo_rsp_t router_29_1_to_router_29_0_rsp; - -floo_req_t router_29_0_to_router_30_0_req; -floo_rsp_t router_30_0_to_router_29_0_rsp; - -floo_req_t router_29_0_to_magia_tile_ni_29_0_req; -floo_rsp_t magia_tile_ni_29_0_to_router_29_0_rsp; - -floo_req_t router_29_1_to_router_28_1_req; -floo_rsp_t router_28_1_to_router_29_1_rsp; - -floo_req_t router_29_1_to_router_29_0_req; -floo_rsp_t router_29_0_to_router_29_1_rsp; - -floo_req_t router_29_1_to_router_29_2_req; -floo_rsp_t router_29_2_to_router_29_1_rsp; - -floo_req_t router_29_1_to_router_30_1_req; -floo_rsp_t router_30_1_to_router_29_1_rsp; - -floo_req_t router_29_1_to_magia_tile_ni_29_1_req; -floo_rsp_t magia_tile_ni_29_1_to_router_29_1_rsp; - -floo_req_t router_29_2_to_router_28_2_req; -floo_rsp_t router_28_2_to_router_29_2_rsp; - -floo_req_t router_29_2_to_router_29_1_req; -floo_rsp_t router_29_1_to_router_29_2_rsp; - -floo_req_t router_29_2_to_router_29_3_req; -floo_rsp_t router_29_3_to_router_29_2_rsp; - -floo_req_t router_29_2_to_router_30_2_req; -floo_rsp_t router_30_2_to_router_29_2_rsp; - -floo_req_t router_29_2_to_magia_tile_ni_29_2_req; -floo_rsp_t magia_tile_ni_29_2_to_router_29_2_rsp; - -floo_req_t router_29_3_to_router_28_3_req; -floo_rsp_t router_28_3_to_router_29_3_rsp; - -floo_req_t router_29_3_to_router_29_2_req; -floo_rsp_t router_29_2_to_router_29_3_rsp; - -floo_req_t router_29_3_to_router_29_4_req; -floo_rsp_t router_29_4_to_router_29_3_rsp; - -floo_req_t router_29_3_to_router_30_3_req; -floo_rsp_t router_30_3_to_router_29_3_rsp; - -floo_req_t router_29_3_to_magia_tile_ni_29_3_req; -floo_rsp_t magia_tile_ni_29_3_to_router_29_3_rsp; - -floo_req_t router_29_4_to_router_28_4_req; -floo_rsp_t router_28_4_to_router_29_4_rsp; - -floo_req_t router_29_4_to_router_29_3_req; -floo_rsp_t router_29_3_to_router_29_4_rsp; - -floo_req_t router_29_4_to_router_29_5_req; -floo_rsp_t router_29_5_to_router_29_4_rsp; - -floo_req_t router_29_4_to_router_30_4_req; -floo_rsp_t router_30_4_to_router_29_4_rsp; - -floo_req_t router_29_4_to_magia_tile_ni_29_4_req; -floo_rsp_t magia_tile_ni_29_4_to_router_29_4_rsp; - -floo_req_t router_29_5_to_router_28_5_req; -floo_rsp_t router_28_5_to_router_29_5_rsp; - -floo_req_t router_29_5_to_router_29_4_req; -floo_rsp_t router_29_4_to_router_29_5_rsp; - -floo_req_t router_29_5_to_router_29_6_req; -floo_rsp_t router_29_6_to_router_29_5_rsp; - -floo_req_t router_29_5_to_router_30_5_req; -floo_rsp_t router_30_5_to_router_29_5_rsp; - -floo_req_t router_29_5_to_magia_tile_ni_29_5_req; -floo_rsp_t magia_tile_ni_29_5_to_router_29_5_rsp; - -floo_req_t router_29_6_to_router_28_6_req; -floo_rsp_t router_28_6_to_router_29_6_rsp; - -floo_req_t router_29_6_to_router_29_5_req; -floo_rsp_t router_29_5_to_router_29_6_rsp; - -floo_req_t router_29_6_to_router_29_7_req; -floo_rsp_t router_29_7_to_router_29_6_rsp; - -floo_req_t router_29_6_to_router_30_6_req; -floo_rsp_t router_30_6_to_router_29_6_rsp; - -floo_req_t router_29_6_to_magia_tile_ni_29_6_req; -floo_rsp_t magia_tile_ni_29_6_to_router_29_6_rsp; - -floo_req_t router_29_7_to_router_28_7_req; -floo_rsp_t router_28_7_to_router_29_7_rsp; - -floo_req_t router_29_7_to_router_29_6_req; -floo_rsp_t router_29_6_to_router_29_7_rsp; - -floo_req_t router_29_7_to_router_29_8_req; -floo_rsp_t router_29_8_to_router_29_7_rsp; - -floo_req_t router_29_7_to_router_30_7_req; -floo_rsp_t router_30_7_to_router_29_7_rsp; - -floo_req_t router_29_7_to_magia_tile_ni_29_7_req; -floo_rsp_t magia_tile_ni_29_7_to_router_29_7_rsp; - -floo_req_t router_29_8_to_router_28_8_req; -floo_rsp_t router_28_8_to_router_29_8_rsp; - -floo_req_t router_29_8_to_router_29_7_req; -floo_rsp_t router_29_7_to_router_29_8_rsp; - -floo_req_t router_29_8_to_router_29_9_req; -floo_rsp_t router_29_9_to_router_29_8_rsp; - -floo_req_t router_29_8_to_router_30_8_req; -floo_rsp_t router_30_8_to_router_29_8_rsp; - -floo_req_t router_29_8_to_magia_tile_ni_29_8_req; -floo_rsp_t magia_tile_ni_29_8_to_router_29_8_rsp; - -floo_req_t router_29_9_to_router_28_9_req; -floo_rsp_t router_28_9_to_router_29_9_rsp; - -floo_req_t router_29_9_to_router_29_8_req; -floo_rsp_t router_29_8_to_router_29_9_rsp; - -floo_req_t router_29_9_to_router_29_10_req; -floo_rsp_t router_29_10_to_router_29_9_rsp; - -floo_req_t router_29_9_to_router_30_9_req; -floo_rsp_t router_30_9_to_router_29_9_rsp; - -floo_req_t router_29_9_to_magia_tile_ni_29_9_req; -floo_rsp_t magia_tile_ni_29_9_to_router_29_9_rsp; - -floo_req_t router_29_10_to_router_28_10_req; -floo_rsp_t router_28_10_to_router_29_10_rsp; - -floo_req_t router_29_10_to_router_29_9_req; -floo_rsp_t router_29_9_to_router_29_10_rsp; - -floo_req_t router_29_10_to_router_29_11_req; -floo_rsp_t router_29_11_to_router_29_10_rsp; - -floo_req_t router_29_10_to_router_30_10_req; -floo_rsp_t router_30_10_to_router_29_10_rsp; - -floo_req_t router_29_10_to_magia_tile_ni_29_10_req; -floo_rsp_t magia_tile_ni_29_10_to_router_29_10_rsp; - -floo_req_t router_29_11_to_router_28_11_req; -floo_rsp_t router_28_11_to_router_29_11_rsp; - -floo_req_t router_29_11_to_router_29_10_req; -floo_rsp_t router_29_10_to_router_29_11_rsp; - -floo_req_t router_29_11_to_router_29_12_req; -floo_rsp_t router_29_12_to_router_29_11_rsp; - -floo_req_t router_29_11_to_router_30_11_req; -floo_rsp_t router_30_11_to_router_29_11_rsp; - -floo_req_t router_29_11_to_magia_tile_ni_29_11_req; -floo_rsp_t magia_tile_ni_29_11_to_router_29_11_rsp; - -floo_req_t router_29_12_to_router_28_12_req; -floo_rsp_t router_28_12_to_router_29_12_rsp; - -floo_req_t router_29_12_to_router_29_11_req; -floo_rsp_t router_29_11_to_router_29_12_rsp; - -floo_req_t router_29_12_to_router_29_13_req; -floo_rsp_t router_29_13_to_router_29_12_rsp; - -floo_req_t router_29_12_to_router_30_12_req; -floo_rsp_t router_30_12_to_router_29_12_rsp; - -floo_req_t router_29_12_to_magia_tile_ni_29_12_req; -floo_rsp_t magia_tile_ni_29_12_to_router_29_12_rsp; - -floo_req_t router_29_13_to_router_28_13_req; -floo_rsp_t router_28_13_to_router_29_13_rsp; - -floo_req_t router_29_13_to_router_29_12_req; -floo_rsp_t router_29_12_to_router_29_13_rsp; - -floo_req_t router_29_13_to_router_29_14_req; -floo_rsp_t router_29_14_to_router_29_13_rsp; - -floo_req_t router_29_13_to_router_30_13_req; -floo_rsp_t router_30_13_to_router_29_13_rsp; - -floo_req_t router_29_13_to_magia_tile_ni_29_13_req; -floo_rsp_t magia_tile_ni_29_13_to_router_29_13_rsp; - -floo_req_t router_29_14_to_router_28_14_req; -floo_rsp_t router_28_14_to_router_29_14_rsp; - -floo_req_t router_29_14_to_router_29_13_req; -floo_rsp_t router_29_13_to_router_29_14_rsp; - -floo_req_t router_29_14_to_router_29_15_req; -floo_rsp_t router_29_15_to_router_29_14_rsp; - -floo_req_t router_29_14_to_router_30_14_req; -floo_rsp_t router_30_14_to_router_29_14_rsp; - -floo_req_t router_29_14_to_magia_tile_ni_29_14_req; -floo_rsp_t magia_tile_ni_29_14_to_router_29_14_rsp; - -floo_req_t router_29_15_to_router_28_15_req; -floo_rsp_t router_28_15_to_router_29_15_rsp; - -floo_req_t router_29_15_to_router_29_14_req; -floo_rsp_t router_29_14_to_router_29_15_rsp; - -floo_req_t router_29_15_to_router_29_16_req; -floo_rsp_t router_29_16_to_router_29_15_rsp; - -floo_req_t router_29_15_to_router_30_15_req; -floo_rsp_t router_30_15_to_router_29_15_rsp; - -floo_req_t router_29_15_to_magia_tile_ni_29_15_req; -floo_rsp_t magia_tile_ni_29_15_to_router_29_15_rsp; - -floo_req_t router_29_16_to_router_28_16_req; -floo_rsp_t router_28_16_to_router_29_16_rsp; - -floo_req_t router_29_16_to_router_29_15_req; -floo_rsp_t router_29_15_to_router_29_16_rsp; - -floo_req_t router_29_16_to_router_29_17_req; -floo_rsp_t router_29_17_to_router_29_16_rsp; - -floo_req_t router_29_16_to_router_30_16_req; -floo_rsp_t router_30_16_to_router_29_16_rsp; - -floo_req_t router_29_16_to_magia_tile_ni_29_16_req; -floo_rsp_t magia_tile_ni_29_16_to_router_29_16_rsp; - -floo_req_t router_29_17_to_router_28_17_req; -floo_rsp_t router_28_17_to_router_29_17_rsp; - -floo_req_t router_29_17_to_router_29_16_req; -floo_rsp_t router_29_16_to_router_29_17_rsp; - -floo_req_t router_29_17_to_router_29_18_req; -floo_rsp_t router_29_18_to_router_29_17_rsp; - -floo_req_t router_29_17_to_router_30_17_req; -floo_rsp_t router_30_17_to_router_29_17_rsp; - -floo_req_t router_29_17_to_magia_tile_ni_29_17_req; -floo_rsp_t magia_tile_ni_29_17_to_router_29_17_rsp; - -floo_req_t router_29_18_to_router_28_18_req; -floo_rsp_t router_28_18_to_router_29_18_rsp; - -floo_req_t router_29_18_to_router_29_17_req; -floo_rsp_t router_29_17_to_router_29_18_rsp; - -floo_req_t router_29_18_to_router_29_19_req; -floo_rsp_t router_29_19_to_router_29_18_rsp; - -floo_req_t router_29_18_to_router_30_18_req; -floo_rsp_t router_30_18_to_router_29_18_rsp; - -floo_req_t router_29_18_to_magia_tile_ni_29_18_req; -floo_rsp_t magia_tile_ni_29_18_to_router_29_18_rsp; - -floo_req_t router_29_19_to_router_28_19_req; -floo_rsp_t router_28_19_to_router_29_19_rsp; - -floo_req_t router_29_19_to_router_29_18_req; -floo_rsp_t router_29_18_to_router_29_19_rsp; - -floo_req_t router_29_19_to_router_29_20_req; -floo_rsp_t router_29_20_to_router_29_19_rsp; - -floo_req_t router_29_19_to_router_30_19_req; -floo_rsp_t router_30_19_to_router_29_19_rsp; - -floo_req_t router_29_19_to_magia_tile_ni_29_19_req; -floo_rsp_t magia_tile_ni_29_19_to_router_29_19_rsp; - -floo_req_t router_29_20_to_router_28_20_req; -floo_rsp_t router_28_20_to_router_29_20_rsp; - -floo_req_t router_29_20_to_router_29_19_req; -floo_rsp_t router_29_19_to_router_29_20_rsp; - -floo_req_t router_29_20_to_router_29_21_req; -floo_rsp_t router_29_21_to_router_29_20_rsp; - -floo_req_t router_29_20_to_router_30_20_req; -floo_rsp_t router_30_20_to_router_29_20_rsp; - -floo_req_t router_29_20_to_magia_tile_ni_29_20_req; -floo_rsp_t magia_tile_ni_29_20_to_router_29_20_rsp; - -floo_req_t router_29_21_to_router_28_21_req; -floo_rsp_t router_28_21_to_router_29_21_rsp; - -floo_req_t router_29_21_to_router_29_20_req; -floo_rsp_t router_29_20_to_router_29_21_rsp; - -floo_req_t router_29_21_to_router_29_22_req; -floo_rsp_t router_29_22_to_router_29_21_rsp; - -floo_req_t router_29_21_to_router_30_21_req; -floo_rsp_t router_30_21_to_router_29_21_rsp; - -floo_req_t router_29_21_to_magia_tile_ni_29_21_req; -floo_rsp_t magia_tile_ni_29_21_to_router_29_21_rsp; - -floo_req_t router_29_22_to_router_28_22_req; -floo_rsp_t router_28_22_to_router_29_22_rsp; - -floo_req_t router_29_22_to_router_29_21_req; -floo_rsp_t router_29_21_to_router_29_22_rsp; - -floo_req_t router_29_22_to_router_29_23_req; -floo_rsp_t router_29_23_to_router_29_22_rsp; - -floo_req_t router_29_22_to_router_30_22_req; -floo_rsp_t router_30_22_to_router_29_22_rsp; - -floo_req_t router_29_22_to_magia_tile_ni_29_22_req; -floo_rsp_t magia_tile_ni_29_22_to_router_29_22_rsp; - -floo_req_t router_29_23_to_router_28_23_req; -floo_rsp_t router_28_23_to_router_29_23_rsp; - -floo_req_t router_29_23_to_router_29_22_req; -floo_rsp_t router_29_22_to_router_29_23_rsp; - -floo_req_t router_29_23_to_router_29_24_req; -floo_rsp_t router_29_24_to_router_29_23_rsp; - -floo_req_t router_29_23_to_router_30_23_req; -floo_rsp_t router_30_23_to_router_29_23_rsp; - -floo_req_t router_29_23_to_magia_tile_ni_29_23_req; -floo_rsp_t magia_tile_ni_29_23_to_router_29_23_rsp; - -floo_req_t router_29_24_to_router_28_24_req; -floo_rsp_t router_28_24_to_router_29_24_rsp; - -floo_req_t router_29_24_to_router_29_23_req; -floo_rsp_t router_29_23_to_router_29_24_rsp; - -floo_req_t router_29_24_to_router_29_25_req; -floo_rsp_t router_29_25_to_router_29_24_rsp; - -floo_req_t router_29_24_to_router_30_24_req; -floo_rsp_t router_30_24_to_router_29_24_rsp; - -floo_req_t router_29_24_to_magia_tile_ni_29_24_req; -floo_rsp_t magia_tile_ni_29_24_to_router_29_24_rsp; - -floo_req_t router_29_25_to_router_28_25_req; -floo_rsp_t router_28_25_to_router_29_25_rsp; - -floo_req_t router_29_25_to_router_29_24_req; -floo_rsp_t router_29_24_to_router_29_25_rsp; - -floo_req_t router_29_25_to_router_29_26_req; -floo_rsp_t router_29_26_to_router_29_25_rsp; - -floo_req_t router_29_25_to_router_30_25_req; -floo_rsp_t router_30_25_to_router_29_25_rsp; - -floo_req_t router_29_25_to_magia_tile_ni_29_25_req; -floo_rsp_t magia_tile_ni_29_25_to_router_29_25_rsp; - -floo_req_t router_29_26_to_router_28_26_req; -floo_rsp_t router_28_26_to_router_29_26_rsp; - -floo_req_t router_29_26_to_router_29_25_req; -floo_rsp_t router_29_25_to_router_29_26_rsp; - -floo_req_t router_29_26_to_router_29_27_req; -floo_rsp_t router_29_27_to_router_29_26_rsp; - -floo_req_t router_29_26_to_router_30_26_req; -floo_rsp_t router_30_26_to_router_29_26_rsp; - -floo_req_t router_29_26_to_magia_tile_ni_29_26_req; -floo_rsp_t magia_tile_ni_29_26_to_router_29_26_rsp; - -floo_req_t router_29_27_to_router_28_27_req; -floo_rsp_t router_28_27_to_router_29_27_rsp; - -floo_req_t router_29_27_to_router_29_26_req; -floo_rsp_t router_29_26_to_router_29_27_rsp; - -floo_req_t router_29_27_to_router_29_28_req; -floo_rsp_t router_29_28_to_router_29_27_rsp; - -floo_req_t router_29_27_to_router_30_27_req; -floo_rsp_t router_30_27_to_router_29_27_rsp; - -floo_req_t router_29_27_to_magia_tile_ni_29_27_req; -floo_rsp_t magia_tile_ni_29_27_to_router_29_27_rsp; - -floo_req_t router_29_28_to_router_28_28_req; -floo_rsp_t router_28_28_to_router_29_28_rsp; - -floo_req_t router_29_28_to_router_29_27_req; -floo_rsp_t router_29_27_to_router_29_28_rsp; - -floo_req_t router_29_28_to_router_29_29_req; -floo_rsp_t router_29_29_to_router_29_28_rsp; - -floo_req_t router_29_28_to_router_30_28_req; -floo_rsp_t router_30_28_to_router_29_28_rsp; - -floo_req_t router_29_28_to_magia_tile_ni_29_28_req; -floo_rsp_t magia_tile_ni_29_28_to_router_29_28_rsp; - -floo_req_t router_29_29_to_router_28_29_req; -floo_rsp_t router_28_29_to_router_29_29_rsp; - -floo_req_t router_29_29_to_router_29_28_req; -floo_rsp_t router_29_28_to_router_29_29_rsp; - -floo_req_t router_29_29_to_router_29_30_req; -floo_rsp_t router_29_30_to_router_29_29_rsp; - -floo_req_t router_29_29_to_router_30_29_req; -floo_rsp_t router_30_29_to_router_29_29_rsp; - -floo_req_t router_29_29_to_magia_tile_ni_29_29_req; -floo_rsp_t magia_tile_ni_29_29_to_router_29_29_rsp; - -floo_req_t router_29_30_to_router_28_30_req; -floo_rsp_t router_28_30_to_router_29_30_rsp; - -floo_req_t router_29_30_to_router_29_29_req; -floo_rsp_t router_29_29_to_router_29_30_rsp; - -floo_req_t router_29_30_to_router_29_31_req; -floo_rsp_t router_29_31_to_router_29_30_rsp; - -floo_req_t router_29_30_to_router_30_30_req; -floo_rsp_t router_30_30_to_router_29_30_rsp; - -floo_req_t router_29_30_to_magia_tile_ni_29_30_req; -floo_rsp_t magia_tile_ni_29_30_to_router_29_30_rsp; - -floo_req_t router_29_31_to_router_28_31_req; -floo_rsp_t router_28_31_to_router_29_31_rsp; - -floo_req_t router_29_31_to_router_29_30_req; -floo_rsp_t router_29_30_to_router_29_31_rsp; - -floo_req_t router_29_31_to_router_30_31_req; -floo_rsp_t router_30_31_to_router_29_31_rsp; - -floo_req_t router_29_31_to_magia_tile_ni_29_31_req; -floo_rsp_t magia_tile_ni_29_31_to_router_29_31_rsp; - -floo_req_t router_30_0_to_router_29_0_req; -floo_rsp_t router_29_0_to_router_30_0_rsp; - -floo_req_t router_30_0_to_router_30_1_req; -floo_rsp_t router_30_1_to_router_30_0_rsp; - -floo_req_t router_30_0_to_router_31_0_req; -floo_rsp_t router_31_0_to_router_30_0_rsp; - -floo_req_t router_30_0_to_magia_tile_ni_30_0_req; -floo_rsp_t magia_tile_ni_30_0_to_router_30_0_rsp; - -floo_req_t router_30_1_to_router_29_1_req; -floo_rsp_t router_29_1_to_router_30_1_rsp; - -floo_req_t router_30_1_to_router_30_0_req; -floo_rsp_t router_30_0_to_router_30_1_rsp; - -floo_req_t router_30_1_to_router_30_2_req; -floo_rsp_t router_30_2_to_router_30_1_rsp; - -floo_req_t router_30_1_to_router_31_1_req; -floo_rsp_t router_31_1_to_router_30_1_rsp; - -floo_req_t router_30_1_to_magia_tile_ni_30_1_req; -floo_rsp_t magia_tile_ni_30_1_to_router_30_1_rsp; - -floo_req_t router_30_2_to_router_29_2_req; -floo_rsp_t router_29_2_to_router_30_2_rsp; - -floo_req_t router_30_2_to_router_30_1_req; -floo_rsp_t router_30_1_to_router_30_2_rsp; - -floo_req_t router_30_2_to_router_30_3_req; -floo_rsp_t router_30_3_to_router_30_2_rsp; - -floo_req_t router_30_2_to_router_31_2_req; -floo_rsp_t router_31_2_to_router_30_2_rsp; - -floo_req_t router_30_2_to_magia_tile_ni_30_2_req; -floo_rsp_t magia_tile_ni_30_2_to_router_30_2_rsp; - -floo_req_t router_30_3_to_router_29_3_req; -floo_rsp_t router_29_3_to_router_30_3_rsp; - -floo_req_t router_30_3_to_router_30_2_req; -floo_rsp_t router_30_2_to_router_30_3_rsp; - -floo_req_t router_30_3_to_router_30_4_req; -floo_rsp_t router_30_4_to_router_30_3_rsp; - -floo_req_t router_30_3_to_router_31_3_req; -floo_rsp_t router_31_3_to_router_30_3_rsp; - -floo_req_t router_30_3_to_magia_tile_ni_30_3_req; -floo_rsp_t magia_tile_ni_30_3_to_router_30_3_rsp; - -floo_req_t router_30_4_to_router_29_4_req; -floo_rsp_t router_29_4_to_router_30_4_rsp; - -floo_req_t router_30_4_to_router_30_3_req; -floo_rsp_t router_30_3_to_router_30_4_rsp; - -floo_req_t router_30_4_to_router_30_5_req; -floo_rsp_t router_30_5_to_router_30_4_rsp; - -floo_req_t router_30_4_to_router_31_4_req; -floo_rsp_t router_31_4_to_router_30_4_rsp; - -floo_req_t router_30_4_to_magia_tile_ni_30_4_req; -floo_rsp_t magia_tile_ni_30_4_to_router_30_4_rsp; - -floo_req_t router_30_5_to_router_29_5_req; -floo_rsp_t router_29_5_to_router_30_5_rsp; - -floo_req_t router_30_5_to_router_30_4_req; -floo_rsp_t router_30_4_to_router_30_5_rsp; - -floo_req_t router_30_5_to_router_30_6_req; -floo_rsp_t router_30_6_to_router_30_5_rsp; - -floo_req_t router_30_5_to_router_31_5_req; -floo_rsp_t router_31_5_to_router_30_5_rsp; - -floo_req_t router_30_5_to_magia_tile_ni_30_5_req; -floo_rsp_t magia_tile_ni_30_5_to_router_30_5_rsp; - -floo_req_t router_30_6_to_router_29_6_req; -floo_rsp_t router_29_6_to_router_30_6_rsp; - -floo_req_t router_30_6_to_router_30_5_req; -floo_rsp_t router_30_5_to_router_30_6_rsp; - -floo_req_t router_30_6_to_router_30_7_req; -floo_rsp_t router_30_7_to_router_30_6_rsp; - -floo_req_t router_30_6_to_router_31_6_req; -floo_rsp_t router_31_6_to_router_30_6_rsp; - -floo_req_t router_30_6_to_magia_tile_ni_30_6_req; -floo_rsp_t magia_tile_ni_30_6_to_router_30_6_rsp; - -floo_req_t router_30_7_to_router_29_7_req; -floo_rsp_t router_29_7_to_router_30_7_rsp; - -floo_req_t router_30_7_to_router_30_6_req; -floo_rsp_t router_30_6_to_router_30_7_rsp; - -floo_req_t router_30_7_to_router_30_8_req; -floo_rsp_t router_30_8_to_router_30_7_rsp; - -floo_req_t router_30_7_to_router_31_7_req; -floo_rsp_t router_31_7_to_router_30_7_rsp; - -floo_req_t router_30_7_to_magia_tile_ni_30_7_req; -floo_rsp_t magia_tile_ni_30_7_to_router_30_7_rsp; - -floo_req_t router_30_8_to_router_29_8_req; -floo_rsp_t router_29_8_to_router_30_8_rsp; - -floo_req_t router_30_8_to_router_30_7_req; -floo_rsp_t router_30_7_to_router_30_8_rsp; - -floo_req_t router_30_8_to_router_30_9_req; -floo_rsp_t router_30_9_to_router_30_8_rsp; - -floo_req_t router_30_8_to_router_31_8_req; -floo_rsp_t router_31_8_to_router_30_8_rsp; - -floo_req_t router_30_8_to_magia_tile_ni_30_8_req; -floo_rsp_t magia_tile_ni_30_8_to_router_30_8_rsp; - -floo_req_t router_30_9_to_router_29_9_req; -floo_rsp_t router_29_9_to_router_30_9_rsp; - -floo_req_t router_30_9_to_router_30_8_req; -floo_rsp_t router_30_8_to_router_30_9_rsp; - -floo_req_t router_30_9_to_router_30_10_req; -floo_rsp_t router_30_10_to_router_30_9_rsp; - -floo_req_t router_30_9_to_router_31_9_req; -floo_rsp_t router_31_9_to_router_30_9_rsp; - -floo_req_t router_30_9_to_magia_tile_ni_30_9_req; -floo_rsp_t magia_tile_ni_30_9_to_router_30_9_rsp; - -floo_req_t router_30_10_to_router_29_10_req; -floo_rsp_t router_29_10_to_router_30_10_rsp; - -floo_req_t router_30_10_to_router_30_9_req; -floo_rsp_t router_30_9_to_router_30_10_rsp; - -floo_req_t router_30_10_to_router_30_11_req; -floo_rsp_t router_30_11_to_router_30_10_rsp; - -floo_req_t router_30_10_to_router_31_10_req; -floo_rsp_t router_31_10_to_router_30_10_rsp; - -floo_req_t router_30_10_to_magia_tile_ni_30_10_req; -floo_rsp_t magia_tile_ni_30_10_to_router_30_10_rsp; - -floo_req_t router_30_11_to_router_29_11_req; -floo_rsp_t router_29_11_to_router_30_11_rsp; - -floo_req_t router_30_11_to_router_30_10_req; -floo_rsp_t router_30_10_to_router_30_11_rsp; - -floo_req_t router_30_11_to_router_30_12_req; -floo_rsp_t router_30_12_to_router_30_11_rsp; - -floo_req_t router_30_11_to_router_31_11_req; -floo_rsp_t router_31_11_to_router_30_11_rsp; - -floo_req_t router_30_11_to_magia_tile_ni_30_11_req; -floo_rsp_t magia_tile_ni_30_11_to_router_30_11_rsp; - -floo_req_t router_30_12_to_router_29_12_req; -floo_rsp_t router_29_12_to_router_30_12_rsp; - -floo_req_t router_30_12_to_router_30_11_req; -floo_rsp_t router_30_11_to_router_30_12_rsp; - -floo_req_t router_30_12_to_router_30_13_req; -floo_rsp_t router_30_13_to_router_30_12_rsp; - -floo_req_t router_30_12_to_router_31_12_req; -floo_rsp_t router_31_12_to_router_30_12_rsp; - -floo_req_t router_30_12_to_magia_tile_ni_30_12_req; -floo_rsp_t magia_tile_ni_30_12_to_router_30_12_rsp; - -floo_req_t router_30_13_to_router_29_13_req; -floo_rsp_t router_29_13_to_router_30_13_rsp; - -floo_req_t router_30_13_to_router_30_12_req; -floo_rsp_t router_30_12_to_router_30_13_rsp; - -floo_req_t router_30_13_to_router_30_14_req; -floo_rsp_t router_30_14_to_router_30_13_rsp; - -floo_req_t router_30_13_to_router_31_13_req; -floo_rsp_t router_31_13_to_router_30_13_rsp; - -floo_req_t router_30_13_to_magia_tile_ni_30_13_req; -floo_rsp_t magia_tile_ni_30_13_to_router_30_13_rsp; - -floo_req_t router_30_14_to_router_29_14_req; -floo_rsp_t router_29_14_to_router_30_14_rsp; - -floo_req_t router_30_14_to_router_30_13_req; -floo_rsp_t router_30_13_to_router_30_14_rsp; - -floo_req_t router_30_14_to_router_30_15_req; -floo_rsp_t router_30_15_to_router_30_14_rsp; - -floo_req_t router_30_14_to_router_31_14_req; -floo_rsp_t router_31_14_to_router_30_14_rsp; - -floo_req_t router_30_14_to_magia_tile_ni_30_14_req; -floo_rsp_t magia_tile_ni_30_14_to_router_30_14_rsp; - -floo_req_t router_30_15_to_router_29_15_req; -floo_rsp_t router_29_15_to_router_30_15_rsp; - -floo_req_t router_30_15_to_router_30_14_req; -floo_rsp_t router_30_14_to_router_30_15_rsp; - -floo_req_t router_30_15_to_router_30_16_req; -floo_rsp_t router_30_16_to_router_30_15_rsp; - -floo_req_t router_30_15_to_router_31_15_req; -floo_rsp_t router_31_15_to_router_30_15_rsp; - -floo_req_t router_30_15_to_magia_tile_ni_30_15_req; -floo_rsp_t magia_tile_ni_30_15_to_router_30_15_rsp; - -floo_req_t router_30_16_to_router_29_16_req; -floo_rsp_t router_29_16_to_router_30_16_rsp; - -floo_req_t router_30_16_to_router_30_15_req; -floo_rsp_t router_30_15_to_router_30_16_rsp; - -floo_req_t router_30_16_to_router_30_17_req; -floo_rsp_t router_30_17_to_router_30_16_rsp; - -floo_req_t router_30_16_to_router_31_16_req; -floo_rsp_t router_31_16_to_router_30_16_rsp; - -floo_req_t router_30_16_to_magia_tile_ni_30_16_req; -floo_rsp_t magia_tile_ni_30_16_to_router_30_16_rsp; - -floo_req_t router_30_17_to_router_29_17_req; -floo_rsp_t router_29_17_to_router_30_17_rsp; - -floo_req_t router_30_17_to_router_30_16_req; -floo_rsp_t router_30_16_to_router_30_17_rsp; - -floo_req_t router_30_17_to_router_30_18_req; -floo_rsp_t router_30_18_to_router_30_17_rsp; - -floo_req_t router_30_17_to_router_31_17_req; -floo_rsp_t router_31_17_to_router_30_17_rsp; - -floo_req_t router_30_17_to_magia_tile_ni_30_17_req; -floo_rsp_t magia_tile_ni_30_17_to_router_30_17_rsp; - -floo_req_t router_30_18_to_router_29_18_req; -floo_rsp_t router_29_18_to_router_30_18_rsp; - -floo_req_t router_30_18_to_router_30_17_req; -floo_rsp_t router_30_17_to_router_30_18_rsp; - -floo_req_t router_30_18_to_router_30_19_req; -floo_rsp_t router_30_19_to_router_30_18_rsp; - -floo_req_t router_30_18_to_router_31_18_req; -floo_rsp_t router_31_18_to_router_30_18_rsp; - -floo_req_t router_30_18_to_magia_tile_ni_30_18_req; -floo_rsp_t magia_tile_ni_30_18_to_router_30_18_rsp; - -floo_req_t router_30_19_to_router_29_19_req; -floo_rsp_t router_29_19_to_router_30_19_rsp; - -floo_req_t router_30_19_to_router_30_18_req; -floo_rsp_t router_30_18_to_router_30_19_rsp; - -floo_req_t router_30_19_to_router_30_20_req; -floo_rsp_t router_30_20_to_router_30_19_rsp; - -floo_req_t router_30_19_to_router_31_19_req; -floo_rsp_t router_31_19_to_router_30_19_rsp; - -floo_req_t router_30_19_to_magia_tile_ni_30_19_req; -floo_rsp_t magia_tile_ni_30_19_to_router_30_19_rsp; - -floo_req_t router_30_20_to_router_29_20_req; -floo_rsp_t router_29_20_to_router_30_20_rsp; - -floo_req_t router_30_20_to_router_30_19_req; -floo_rsp_t router_30_19_to_router_30_20_rsp; - -floo_req_t router_30_20_to_router_30_21_req; -floo_rsp_t router_30_21_to_router_30_20_rsp; - -floo_req_t router_30_20_to_router_31_20_req; -floo_rsp_t router_31_20_to_router_30_20_rsp; - -floo_req_t router_30_20_to_magia_tile_ni_30_20_req; -floo_rsp_t magia_tile_ni_30_20_to_router_30_20_rsp; - -floo_req_t router_30_21_to_router_29_21_req; -floo_rsp_t router_29_21_to_router_30_21_rsp; - -floo_req_t router_30_21_to_router_30_20_req; -floo_rsp_t router_30_20_to_router_30_21_rsp; - -floo_req_t router_30_21_to_router_30_22_req; -floo_rsp_t router_30_22_to_router_30_21_rsp; - -floo_req_t router_30_21_to_router_31_21_req; -floo_rsp_t router_31_21_to_router_30_21_rsp; - -floo_req_t router_30_21_to_magia_tile_ni_30_21_req; -floo_rsp_t magia_tile_ni_30_21_to_router_30_21_rsp; - -floo_req_t router_30_22_to_router_29_22_req; -floo_rsp_t router_29_22_to_router_30_22_rsp; - -floo_req_t router_30_22_to_router_30_21_req; -floo_rsp_t router_30_21_to_router_30_22_rsp; - -floo_req_t router_30_22_to_router_30_23_req; -floo_rsp_t router_30_23_to_router_30_22_rsp; - -floo_req_t router_30_22_to_router_31_22_req; -floo_rsp_t router_31_22_to_router_30_22_rsp; - -floo_req_t router_30_22_to_magia_tile_ni_30_22_req; -floo_rsp_t magia_tile_ni_30_22_to_router_30_22_rsp; - -floo_req_t router_30_23_to_router_29_23_req; -floo_rsp_t router_29_23_to_router_30_23_rsp; - -floo_req_t router_30_23_to_router_30_22_req; -floo_rsp_t router_30_22_to_router_30_23_rsp; - -floo_req_t router_30_23_to_router_30_24_req; -floo_rsp_t router_30_24_to_router_30_23_rsp; - -floo_req_t router_30_23_to_router_31_23_req; -floo_rsp_t router_31_23_to_router_30_23_rsp; - -floo_req_t router_30_23_to_magia_tile_ni_30_23_req; -floo_rsp_t magia_tile_ni_30_23_to_router_30_23_rsp; - -floo_req_t router_30_24_to_router_29_24_req; -floo_rsp_t router_29_24_to_router_30_24_rsp; - -floo_req_t router_30_24_to_router_30_23_req; -floo_rsp_t router_30_23_to_router_30_24_rsp; - -floo_req_t router_30_24_to_router_30_25_req; -floo_rsp_t router_30_25_to_router_30_24_rsp; - -floo_req_t router_30_24_to_router_31_24_req; -floo_rsp_t router_31_24_to_router_30_24_rsp; - -floo_req_t router_30_24_to_magia_tile_ni_30_24_req; -floo_rsp_t magia_tile_ni_30_24_to_router_30_24_rsp; - -floo_req_t router_30_25_to_router_29_25_req; -floo_rsp_t router_29_25_to_router_30_25_rsp; - -floo_req_t router_30_25_to_router_30_24_req; -floo_rsp_t router_30_24_to_router_30_25_rsp; - -floo_req_t router_30_25_to_router_30_26_req; -floo_rsp_t router_30_26_to_router_30_25_rsp; - -floo_req_t router_30_25_to_router_31_25_req; -floo_rsp_t router_31_25_to_router_30_25_rsp; - -floo_req_t router_30_25_to_magia_tile_ni_30_25_req; -floo_rsp_t magia_tile_ni_30_25_to_router_30_25_rsp; - -floo_req_t router_30_26_to_router_29_26_req; -floo_rsp_t router_29_26_to_router_30_26_rsp; - -floo_req_t router_30_26_to_router_30_25_req; -floo_rsp_t router_30_25_to_router_30_26_rsp; - -floo_req_t router_30_26_to_router_30_27_req; -floo_rsp_t router_30_27_to_router_30_26_rsp; - -floo_req_t router_30_26_to_router_31_26_req; -floo_rsp_t router_31_26_to_router_30_26_rsp; - -floo_req_t router_30_26_to_magia_tile_ni_30_26_req; -floo_rsp_t magia_tile_ni_30_26_to_router_30_26_rsp; - -floo_req_t router_30_27_to_router_29_27_req; -floo_rsp_t router_29_27_to_router_30_27_rsp; - -floo_req_t router_30_27_to_router_30_26_req; -floo_rsp_t router_30_26_to_router_30_27_rsp; - -floo_req_t router_30_27_to_router_30_28_req; -floo_rsp_t router_30_28_to_router_30_27_rsp; - -floo_req_t router_30_27_to_router_31_27_req; -floo_rsp_t router_31_27_to_router_30_27_rsp; - -floo_req_t router_30_27_to_magia_tile_ni_30_27_req; -floo_rsp_t magia_tile_ni_30_27_to_router_30_27_rsp; - -floo_req_t router_30_28_to_router_29_28_req; -floo_rsp_t router_29_28_to_router_30_28_rsp; - -floo_req_t router_30_28_to_router_30_27_req; -floo_rsp_t router_30_27_to_router_30_28_rsp; - -floo_req_t router_30_28_to_router_30_29_req; -floo_rsp_t router_30_29_to_router_30_28_rsp; - -floo_req_t router_30_28_to_router_31_28_req; -floo_rsp_t router_31_28_to_router_30_28_rsp; - -floo_req_t router_30_28_to_magia_tile_ni_30_28_req; -floo_rsp_t magia_tile_ni_30_28_to_router_30_28_rsp; - -floo_req_t router_30_29_to_router_29_29_req; -floo_rsp_t router_29_29_to_router_30_29_rsp; - -floo_req_t router_30_29_to_router_30_28_req; -floo_rsp_t router_30_28_to_router_30_29_rsp; - -floo_req_t router_30_29_to_router_30_30_req; -floo_rsp_t router_30_30_to_router_30_29_rsp; - -floo_req_t router_30_29_to_router_31_29_req; -floo_rsp_t router_31_29_to_router_30_29_rsp; - -floo_req_t router_30_29_to_magia_tile_ni_30_29_req; -floo_rsp_t magia_tile_ni_30_29_to_router_30_29_rsp; - -floo_req_t router_30_30_to_router_29_30_req; -floo_rsp_t router_29_30_to_router_30_30_rsp; - -floo_req_t router_30_30_to_router_30_29_req; -floo_rsp_t router_30_29_to_router_30_30_rsp; - -floo_req_t router_30_30_to_router_30_31_req; -floo_rsp_t router_30_31_to_router_30_30_rsp; - -floo_req_t router_30_30_to_router_31_30_req; -floo_rsp_t router_31_30_to_router_30_30_rsp; - -floo_req_t router_30_30_to_magia_tile_ni_30_30_req; -floo_rsp_t magia_tile_ni_30_30_to_router_30_30_rsp; - -floo_req_t router_30_31_to_router_29_31_req; -floo_rsp_t router_29_31_to_router_30_31_rsp; - -floo_req_t router_30_31_to_router_30_30_req; -floo_rsp_t router_30_30_to_router_30_31_rsp; - -floo_req_t router_30_31_to_router_31_31_req; -floo_rsp_t router_31_31_to_router_30_31_rsp; - -floo_req_t router_30_31_to_magia_tile_ni_30_31_req; -floo_rsp_t magia_tile_ni_30_31_to_router_30_31_rsp; - -floo_req_t router_31_0_to_router_30_0_req; -floo_rsp_t router_30_0_to_router_31_0_rsp; - -floo_req_t router_31_0_to_router_31_1_req; -floo_rsp_t router_31_1_to_router_31_0_rsp; - -floo_req_t router_31_0_to_magia_tile_ni_31_0_req; -floo_rsp_t magia_tile_ni_31_0_to_router_31_0_rsp; - -floo_req_t router_31_1_to_router_30_1_req; -floo_rsp_t router_30_1_to_router_31_1_rsp; - -floo_req_t router_31_1_to_router_31_0_req; -floo_rsp_t router_31_0_to_router_31_1_rsp; - -floo_req_t router_31_1_to_router_31_2_req; -floo_rsp_t router_31_2_to_router_31_1_rsp; - -floo_req_t router_31_1_to_magia_tile_ni_31_1_req; -floo_rsp_t magia_tile_ni_31_1_to_router_31_1_rsp; - -floo_req_t router_31_2_to_router_30_2_req; -floo_rsp_t router_30_2_to_router_31_2_rsp; - -floo_req_t router_31_2_to_router_31_1_req; -floo_rsp_t router_31_1_to_router_31_2_rsp; - -floo_req_t router_31_2_to_router_31_3_req; -floo_rsp_t router_31_3_to_router_31_2_rsp; - -floo_req_t router_31_2_to_magia_tile_ni_31_2_req; -floo_rsp_t magia_tile_ni_31_2_to_router_31_2_rsp; - -floo_req_t router_31_3_to_router_30_3_req; -floo_rsp_t router_30_3_to_router_31_3_rsp; - -floo_req_t router_31_3_to_router_31_2_req; -floo_rsp_t router_31_2_to_router_31_3_rsp; - -floo_req_t router_31_3_to_router_31_4_req; -floo_rsp_t router_31_4_to_router_31_3_rsp; - -floo_req_t router_31_3_to_magia_tile_ni_31_3_req; -floo_rsp_t magia_tile_ni_31_3_to_router_31_3_rsp; - -floo_req_t router_31_4_to_router_30_4_req; -floo_rsp_t router_30_4_to_router_31_4_rsp; - -floo_req_t router_31_4_to_router_31_3_req; -floo_rsp_t router_31_3_to_router_31_4_rsp; - -floo_req_t router_31_4_to_router_31_5_req; -floo_rsp_t router_31_5_to_router_31_4_rsp; - -floo_req_t router_31_4_to_magia_tile_ni_31_4_req; -floo_rsp_t magia_tile_ni_31_4_to_router_31_4_rsp; - -floo_req_t router_31_5_to_router_30_5_req; -floo_rsp_t router_30_5_to_router_31_5_rsp; - -floo_req_t router_31_5_to_router_31_4_req; -floo_rsp_t router_31_4_to_router_31_5_rsp; - -floo_req_t router_31_5_to_router_31_6_req; -floo_rsp_t router_31_6_to_router_31_5_rsp; - -floo_req_t router_31_5_to_magia_tile_ni_31_5_req; -floo_rsp_t magia_tile_ni_31_5_to_router_31_5_rsp; - -floo_req_t router_31_6_to_router_30_6_req; -floo_rsp_t router_30_6_to_router_31_6_rsp; - -floo_req_t router_31_6_to_router_31_5_req; -floo_rsp_t router_31_5_to_router_31_6_rsp; - -floo_req_t router_31_6_to_router_31_7_req; -floo_rsp_t router_31_7_to_router_31_6_rsp; - -floo_req_t router_31_6_to_magia_tile_ni_31_6_req; -floo_rsp_t magia_tile_ni_31_6_to_router_31_6_rsp; - -floo_req_t router_31_7_to_router_30_7_req; -floo_rsp_t router_30_7_to_router_31_7_rsp; - -floo_req_t router_31_7_to_router_31_6_req; -floo_rsp_t router_31_6_to_router_31_7_rsp; - -floo_req_t router_31_7_to_router_31_8_req; -floo_rsp_t router_31_8_to_router_31_7_rsp; - -floo_req_t router_31_7_to_magia_tile_ni_31_7_req; -floo_rsp_t magia_tile_ni_31_7_to_router_31_7_rsp; - -floo_req_t router_31_8_to_router_30_8_req; -floo_rsp_t router_30_8_to_router_31_8_rsp; - -floo_req_t router_31_8_to_router_31_7_req; -floo_rsp_t router_31_7_to_router_31_8_rsp; - -floo_req_t router_31_8_to_router_31_9_req; -floo_rsp_t router_31_9_to_router_31_8_rsp; - -floo_req_t router_31_8_to_magia_tile_ni_31_8_req; -floo_rsp_t magia_tile_ni_31_8_to_router_31_8_rsp; - -floo_req_t router_31_9_to_router_30_9_req; -floo_rsp_t router_30_9_to_router_31_9_rsp; - -floo_req_t router_31_9_to_router_31_8_req; -floo_rsp_t router_31_8_to_router_31_9_rsp; - -floo_req_t router_31_9_to_router_31_10_req; -floo_rsp_t router_31_10_to_router_31_9_rsp; - -floo_req_t router_31_9_to_magia_tile_ni_31_9_req; -floo_rsp_t magia_tile_ni_31_9_to_router_31_9_rsp; - -floo_req_t router_31_10_to_router_30_10_req; -floo_rsp_t router_30_10_to_router_31_10_rsp; - -floo_req_t router_31_10_to_router_31_9_req; -floo_rsp_t router_31_9_to_router_31_10_rsp; - -floo_req_t router_31_10_to_router_31_11_req; -floo_rsp_t router_31_11_to_router_31_10_rsp; - -floo_req_t router_31_10_to_magia_tile_ni_31_10_req; -floo_rsp_t magia_tile_ni_31_10_to_router_31_10_rsp; - -floo_req_t router_31_11_to_router_30_11_req; -floo_rsp_t router_30_11_to_router_31_11_rsp; - -floo_req_t router_31_11_to_router_31_10_req; -floo_rsp_t router_31_10_to_router_31_11_rsp; - -floo_req_t router_31_11_to_router_31_12_req; -floo_rsp_t router_31_12_to_router_31_11_rsp; - -floo_req_t router_31_11_to_magia_tile_ni_31_11_req; -floo_rsp_t magia_tile_ni_31_11_to_router_31_11_rsp; - -floo_req_t router_31_12_to_router_30_12_req; -floo_rsp_t router_30_12_to_router_31_12_rsp; - -floo_req_t router_31_12_to_router_31_11_req; -floo_rsp_t router_31_11_to_router_31_12_rsp; - -floo_req_t router_31_12_to_router_31_13_req; -floo_rsp_t router_31_13_to_router_31_12_rsp; - -floo_req_t router_31_12_to_magia_tile_ni_31_12_req; -floo_rsp_t magia_tile_ni_31_12_to_router_31_12_rsp; - -floo_req_t router_31_13_to_router_30_13_req; -floo_rsp_t router_30_13_to_router_31_13_rsp; - -floo_req_t router_31_13_to_router_31_12_req; -floo_rsp_t router_31_12_to_router_31_13_rsp; - -floo_req_t router_31_13_to_router_31_14_req; -floo_rsp_t router_31_14_to_router_31_13_rsp; - -floo_req_t router_31_13_to_magia_tile_ni_31_13_req; -floo_rsp_t magia_tile_ni_31_13_to_router_31_13_rsp; - -floo_req_t router_31_14_to_router_30_14_req; -floo_rsp_t router_30_14_to_router_31_14_rsp; - -floo_req_t router_31_14_to_router_31_13_req; -floo_rsp_t router_31_13_to_router_31_14_rsp; - -floo_req_t router_31_14_to_router_31_15_req; -floo_rsp_t router_31_15_to_router_31_14_rsp; - -floo_req_t router_31_14_to_magia_tile_ni_31_14_req; -floo_rsp_t magia_tile_ni_31_14_to_router_31_14_rsp; - -floo_req_t router_31_15_to_router_30_15_req; -floo_rsp_t router_30_15_to_router_31_15_rsp; - -floo_req_t router_31_15_to_router_31_14_req; -floo_rsp_t router_31_14_to_router_31_15_rsp; - -floo_req_t router_31_15_to_router_31_16_req; -floo_rsp_t router_31_16_to_router_31_15_rsp; - -floo_req_t router_31_15_to_magia_tile_ni_31_15_req; -floo_rsp_t magia_tile_ni_31_15_to_router_31_15_rsp; - -floo_req_t router_31_16_to_router_30_16_req; -floo_rsp_t router_30_16_to_router_31_16_rsp; - -floo_req_t router_31_16_to_router_31_15_req; -floo_rsp_t router_31_15_to_router_31_16_rsp; - -floo_req_t router_31_16_to_router_31_17_req; -floo_rsp_t router_31_17_to_router_31_16_rsp; - -floo_req_t router_31_16_to_magia_tile_ni_31_16_req; -floo_rsp_t magia_tile_ni_31_16_to_router_31_16_rsp; - -floo_req_t router_31_17_to_router_30_17_req; -floo_rsp_t router_30_17_to_router_31_17_rsp; - -floo_req_t router_31_17_to_router_31_16_req; -floo_rsp_t router_31_16_to_router_31_17_rsp; - -floo_req_t router_31_17_to_router_31_18_req; -floo_rsp_t router_31_18_to_router_31_17_rsp; - -floo_req_t router_31_17_to_magia_tile_ni_31_17_req; -floo_rsp_t magia_tile_ni_31_17_to_router_31_17_rsp; - -floo_req_t router_31_18_to_router_30_18_req; -floo_rsp_t router_30_18_to_router_31_18_rsp; - -floo_req_t router_31_18_to_router_31_17_req; -floo_rsp_t router_31_17_to_router_31_18_rsp; - -floo_req_t router_31_18_to_router_31_19_req; -floo_rsp_t router_31_19_to_router_31_18_rsp; - -floo_req_t router_31_18_to_magia_tile_ni_31_18_req; -floo_rsp_t magia_tile_ni_31_18_to_router_31_18_rsp; - -floo_req_t router_31_19_to_router_30_19_req; -floo_rsp_t router_30_19_to_router_31_19_rsp; - -floo_req_t router_31_19_to_router_31_18_req; -floo_rsp_t router_31_18_to_router_31_19_rsp; - -floo_req_t router_31_19_to_router_31_20_req; -floo_rsp_t router_31_20_to_router_31_19_rsp; - -floo_req_t router_31_19_to_magia_tile_ni_31_19_req; -floo_rsp_t magia_tile_ni_31_19_to_router_31_19_rsp; - -floo_req_t router_31_20_to_router_30_20_req; -floo_rsp_t router_30_20_to_router_31_20_rsp; - -floo_req_t router_31_20_to_router_31_19_req; -floo_rsp_t router_31_19_to_router_31_20_rsp; - -floo_req_t router_31_20_to_router_31_21_req; -floo_rsp_t router_31_21_to_router_31_20_rsp; - -floo_req_t router_31_20_to_magia_tile_ni_31_20_req; -floo_rsp_t magia_tile_ni_31_20_to_router_31_20_rsp; - -floo_req_t router_31_21_to_router_30_21_req; -floo_rsp_t router_30_21_to_router_31_21_rsp; - -floo_req_t router_31_21_to_router_31_20_req; -floo_rsp_t router_31_20_to_router_31_21_rsp; - -floo_req_t router_31_21_to_router_31_22_req; -floo_rsp_t router_31_22_to_router_31_21_rsp; - -floo_req_t router_31_21_to_magia_tile_ni_31_21_req; -floo_rsp_t magia_tile_ni_31_21_to_router_31_21_rsp; - -floo_req_t router_31_22_to_router_30_22_req; -floo_rsp_t router_30_22_to_router_31_22_rsp; - -floo_req_t router_31_22_to_router_31_21_req; -floo_rsp_t router_31_21_to_router_31_22_rsp; - -floo_req_t router_31_22_to_router_31_23_req; -floo_rsp_t router_31_23_to_router_31_22_rsp; - -floo_req_t router_31_22_to_magia_tile_ni_31_22_req; -floo_rsp_t magia_tile_ni_31_22_to_router_31_22_rsp; - -floo_req_t router_31_23_to_router_30_23_req; -floo_rsp_t router_30_23_to_router_31_23_rsp; - -floo_req_t router_31_23_to_router_31_22_req; -floo_rsp_t router_31_22_to_router_31_23_rsp; - -floo_req_t router_31_23_to_router_31_24_req; -floo_rsp_t router_31_24_to_router_31_23_rsp; - -floo_req_t router_31_23_to_magia_tile_ni_31_23_req; -floo_rsp_t magia_tile_ni_31_23_to_router_31_23_rsp; - -floo_req_t router_31_24_to_router_30_24_req; -floo_rsp_t router_30_24_to_router_31_24_rsp; - -floo_req_t router_31_24_to_router_31_23_req; -floo_rsp_t router_31_23_to_router_31_24_rsp; - -floo_req_t router_31_24_to_router_31_25_req; -floo_rsp_t router_31_25_to_router_31_24_rsp; - -floo_req_t router_31_24_to_magia_tile_ni_31_24_req; -floo_rsp_t magia_tile_ni_31_24_to_router_31_24_rsp; - -floo_req_t router_31_25_to_router_30_25_req; -floo_rsp_t router_30_25_to_router_31_25_rsp; - -floo_req_t router_31_25_to_router_31_24_req; -floo_rsp_t router_31_24_to_router_31_25_rsp; - -floo_req_t router_31_25_to_router_31_26_req; -floo_rsp_t router_31_26_to_router_31_25_rsp; - -floo_req_t router_31_25_to_magia_tile_ni_31_25_req; -floo_rsp_t magia_tile_ni_31_25_to_router_31_25_rsp; - -floo_req_t router_31_26_to_router_30_26_req; -floo_rsp_t router_30_26_to_router_31_26_rsp; - -floo_req_t router_31_26_to_router_31_25_req; -floo_rsp_t router_31_25_to_router_31_26_rsp; - -floo_req_t router_31_26_to_router_31_27_req; -floo_rsp_t router_31_27_to_router_31_26_rsp; - -floo_req_t router_31_26_to_magia_tile_ni_31_26_req; -floo_rsp_t magia_tile_ni_31_26_to_router_31_26_rsp; - -floo_req_t router_31_27_to_router_30_27_req; -floo_rsp_t router_30_27_to_router_31_27_rsp; - -floo_req_t router_31_27_to_router_31_26_req; -floo_rsp_t router_31_26_to_router_31_27_rsp; - -floo_req_t router_31_27_to_router_31_28_req; -floo_rsp_t router_31_28_to_router_31_27_rsp; - -floo_req_t router_31_27_to_magia_tile_ni_31_27_req; -floo_rsp_t magia_tile_ni_31_27_to_router_31_27_rsp; - -floo_req_t router_31_28_to_router_30_28_req; -floo_rsp_t router_30_28_to_router_31_28_rsp; - -floo_req_t router_31_28_to_router_31_27_req; -floo_rsp_t router_31_27_to_router_31_28_rsp; - -floo_req_t router_31_28_to_router_31_29_req; -floo_rsp_t router_31_29_to_router_31_28_rsp; - -floo_req_t router_31_28_to_magia_tile_ni_31_28_req; -floo_rsp_t magia_tile_ni_31_28_to_router_31_28_rsp; - -floo_req_t router_31_29_to_router_30_29_req; -floo_rsp_t router_30_29_to_router_31_29_rsp; - -floo_req_t router_31_29_to_router_31_28_req; -floo_rsp_t router_31_28_to_router_31_29_rsp; - -floo_req_t router_31_29_to_router_31_30_req; -floo_rsp_t router_31_30_to_router_31_29_rsp; - -floo_req_t router_31_29_to_magia_tile_ni_31_29_req; -floo_rsp_t magia_tile_ni_31_29_to_router_31_29_rsp; - -floo_req_t router_31_30_to_router_30_30_req; -floo_rsp_t router_30_30_to_router_31_30_rsp; - -floo_req_t router_31_30_to_router_31_29_req; -floo_rsp_t router_31_29_to_router_31_30_rsp; - -floo_req_t router_31_30_to_router_31_31_req; -floo_rsp_t router_31_31_to_router_31_30_rsp; - -floo_req_t router_31_30_to_magia_tile_ni_31_30_req; -floo_rsp_t magia_tile_ni_31_30_to_router_31_30_rsp; - -floo_req_t router_31_31_to_router_30_31_req; -floo_rsp_t router_30_31_to_router_31_31_rsp; - -floo_req_t router_31_31_to_router_31_30_req; -floo_rsp_t router_31_30_to_router_31_31_rsp; - -floo_req_t router_31_31_to_magia_tile_ni_31_31_req; -floo_rsp_t magia_tile_ni_31_31_to_router_31_31_rsp; - -floo_req_t magia_tile_ni_0_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_magia_tile_ni_0_0_rsp; - -floo_req_t magia_tile_ni_0_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_magia_tile_ni_0_1_rsp; - -floo_req_t magia_tile_ni_0_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_magia_tile_ni_0_2_rsp; - -floo_req_t magia_tile_ni_0_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_magia_tile_ni_0_3_rsp; - -floo_req_t magia_tile_ni_0_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_magia_tile_ni_0_4_rsp; - -floo_req_t magia_tile_ni_0_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_magia_tile_ni_0_5_rsp; - -floo_req_t magia_tile_ni_0_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_magia_tile_ni_0_6_rsp; - -floo_req_t magia_tile_ni_0_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_magia_tile_ni_0_7_rsp; - -floo_req_t magia_tile_ni_0_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_magia_tile_ni_0_8_rsp; - -floo_req_t magia_tile_ni_0_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_magia_tile_ni_0_9_rsp; - -floo_req_t magia_tile_ni_0_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_magia_tile_ni_0_10_rsp; - -floo_req_t magia_tile_ni_0_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_magia_tile_ni_0_11_rsp; - -floo_req_t magia_tile_ni_0_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_magia_tile_ni_0_12_rsp; - -floo_req_t magia_tile_ni_0_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_magia_tile_ni_0_13_rsp; - -floo_req_t magia_tile_ni_0_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_magia_tile_ni_0_14_rsp; - -floo_req_t magia_tile_ni_0_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_magia_tile_ni_0_15_rsp; - -floo_req_t magia_tile_ni_0_16_to_router_0_16_req; -floo_rsp_t router_0_16_to_magia_tile_ni_0_16_rsp; - -floo_req_t magia_tile_ni_0_17_to_router_0_17_req; -floo_rsp_t router_0_17_to_magia_tile_ni_0_17_rsp; - -floo_req_t magia_tile_ni_0_18_to_router_0_18_req; -floo_rsp_t router_0_18_to_magia_tile_ni_0_18_rsp; - -floo_req_t magia_tile_ni_0_19_to_router_0_19_req; -floo_rsp_t router_0_19_to_magia_tile_ni_0_19_rsp; - -floo_req_t magia_tile_ni_0_20_to_router_0_20_req; -floo_rsp_t router_0_20_to_magia_tile_ni_0_20_rsp; - -floo_req_t magia_tile_ni_0_21_to_router_0_21_req; -floo_rsp_t router_0_21_to_magia_tile_ni_0_21_rsp; - -floo_req_t magia_tile_ni_0_22_to_router_0_22_req; -floo_rsp_t router_0_22_to_magia_tile_ni_0_22_rsp; - -floo_req_t magia_tile_ni_0_23_to_router_0_23_req; -floo_rsp_t router_0_23_to_magia_tile_ni_0_23_rsp; - -floo_req_t magia_tile_ni_0_24_to_router_0_24_req; -floo_rsp_t router_0_24_to_magia_tile_ni_0_24_rsp; - -floo_req_t magia_tile_ni_0_25_to_router_0_25_req; -floo_rsp_t router_0_25_to_magia_tile_ni_0_25_rsp; - -floo_req_t magia_tile_ni_0_26_to_router_0_26_req; -floo_rsp_t router_0_26_to_magia_tile_ni_0_26_rsp; - -floo_req_t magia_tile_ni_0_27_to_router_0_27_req; -floo_rsp_t router_0_27_to_magia_tile_ni_0_27_rsp; - -floo_req_t magia_tile_ni_0_28_to_router_0_28_req; -floo_rsp_t router_0_28_to_magia_tile_ni_0_28_rsp; - -floo_req_t magia_tile_ni_0_29_to_router_0_29_req; -floo_rsp_t router_0_29_to_magia_tile_ni_0_29_rsp; - -floo_req_t magia_tile_ni_0_30_to_router_0_30_req; -floo_rsp_t router_0_30_to_magia_tile_ni_0_30_rsp; - -floo_req_t magia_tile_ni_0_31_to_router_0_31_req; -floo_rsp_t router_0_31_to_magia_tile_ni_0_31_rsp; - -floo_req_t magia_tile_ni_1_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_magia_tile_ni_1_0_rsp; - -floo_req_t magia_tile_ni_1_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_magia_tile_ni_1_1_rsp; - -floo_req_t magia_tile_ni_1_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_magia_tile_ni_1_2_rsp; - -floo_req_t magia_tile_ni_1_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_magia_tile_ni_1_3_rsp; - -floo_req_t magia_tile_ni_1_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_magia_tile_ni_1_4_rsp; - -floo_req_t magia_tile_ni_1_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_magia_tile_ni_1_5_rsp; - -floo_req_t magia_tile_ni_1_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_magia_tile_ni_1_6_rsp; - -floo_req_t magia_tile_ni_1_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_magia_tile_ni_1_7_rsp; - -floo_req_t magia_tile_ni_1_8_to_router_1_8_req; -floo_rsp_t router_1_8_to_magia_tile_ni_1_8_rsp; - -floo_req_t magia_tile_ni_1_9_to_router_1_9_req; -floo_rsp_t router_1_9_to_magia_tile_ni_1_9_rsp; - -floo_req_t magia_tile_ni_1_10_to_router_1_10_req; -floo_rsp_t router_1_10_to_magia_tile_ni_1_10_rsp; - -floo_req_t magia_tile_ni_1_11_to_router_1_11_req; -floo_rsp_t router_1_11_to_magia_tile_ni_1_11_rsp; - -floo_req_t magia_tile_ni_1_12_to_router_1_12_req; -floo_rsp_t router_1_12_to_magia_tile_ni_1_12_rsp; - -floo_req_t magia_tile_ni_1_13_to_router_1_13_req; -floo_rsp_t router_1_13_to_magia_tile_ni_1_13_rsp; - -floo_req_t magia_tile_ni_1_14_to_router_1_14_req; -floo_rsp_t router_1_14_to_magia_tile_ni_1_14_rsp; - -floo_req_t magia_tile_ni_1_15_to_router_1_15_req; -floo_rsp_t router_1_15_to_magia_tile_ni_1_15_rsp; - -floo_req_t magia_tile_ni_1_16_to_router_1_16_req; -floo_rsp_t router_1_16_to_magia_tile_ni_1_16_rsp; - -floo_req_t magia_tile_ni_1_17_to_router_1_17_req; -floo_rsp_t router_1_17_to_magia_tile_ni_1_17_rsp; - -floo_req_t magia_tile_ni_1_18_to_router_1_18_req; -floo_rsp_t router_1_18_to_magia_tile_ni_1_18_rsp; - -floo_req_t magia_tile_ni_1_19_to_router_1_19_req; -floo_rsp_t router_1_19_to_magia_tile_ni_1_19_rsp; - -floo_req_t magia_tile_ni_1_20_to_router_1_20_req; -floo_rsp_t router_1_20_to_magia_tile_ni_1_20_rsp; - -floo_req_t magia_tile_ni_1_21_to_router_1_21_req; -floo_rsp_t router_1_21_to_magia_tile_ni_1_21_rsp; - -floo_req_t magia_tile_ni_1_22_to_router_1_22_req; -floo_rsp_t router_1_22_to_magia_tile_ni_1_22_rsp; - -floo_req_t magia_tile_ni_1_23_to_router_1_23_req; -floo_rsp_t router_1_23_to_magia_tile_ni_1_23_rsp; - -floo_req_t magia_tile_ni_1_24_to_router_1_24_req; -floo_rsp_t router_1_24_to_magia_tile_ni_1_24_rsp; - -floo_req_t magia_tile_ni_1_25_to_router_1_25_req; -floo_rsp_t router_1_25_to_magia_tile_ni_1_25_rsp; - -floo_req_t magia_tile_ni_1_26_to_router_1_26_req; -floo_rsp_t router_1_26_to_magia_tile_ni_1_26_rsp; - -floo_req_t magia_tile_ni_1_27_to_router_1_27_req; -floo_rsp_t router_1_27_to_magia_tile_ni_1_27_rsp; - -floo_req_t magia_tile_ni_1_28_to_router_1_28_req; -floo_rsp_t router_1_28_to_magia_tile_ni_1_28_rsp; - -floo_req_t magia_tile_ni_1_29_to_router_1_29_req; -floo_rsp_t router_1_29_to_magia_tile_ni_1_29_rsp; - -floo_req_t magia_tile_ni_1_30_to_router_1_30_req; -floo_rsp_t router_1_30_to_magia_tile_ni_1_30_rsp; - -floo_req_t magia_tile_ni_1_31_to_router_1_31_req; -floo_rsp_t router_1_31_to_magia_tile_ni_1_31_rsp; - -floo_req_t magia_tile_ni_2_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_magia_tile_ni_2_0_rsp; - -floo_req_t magia_tile_ni_2_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_magia_tile_ni_2_1_rsp; - -floo_req_t magia_tile_ni_2_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_magia_tile_ni_2_2_rsp; - -floo_req_t magia_tile_ni_2_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_magia_tile_ni_2_3_rsp; - -floo_req_t magia_tile_ni_2_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_magia_tile_ni_2_4_rsp; - -floo_req_t magia_tile_ni_2_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_magia_tile_ni_2_5_rsp; - -floo_req_t magia_tile_ni_2_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_magia_tile_ni_2_6_rsp; - -floo_req_t magia_tile_ni_2_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_magia_tile_ni_2_7_rsp; - -floo_req_t magia_tile_ni_2_8_to_router_2_8_req; -floo_rsp_t router_2_8_to_magia_tile_ni_2_8_rsp; - -floo_req_t magia_tile_ni_2_9_to_router_2_9_req; -floo_rsp_t router_2_9_to_magia_tile_ni_2_9_rsp; - -floo_req_t magia_tile_ni_2_10_to_router_2_10_req; -floo_rsp_t router_2_10_to_magia_tile_ni_2_10_rsp; - -floo_req_t magia_tile_ni_2_11_to_router_2_11_req; -floo_rsp_t router_2_11_to_magia_tile_ni_2_11_rsp; - -floo_req_t magia_tile_ni_2_12_to_router_2_12_req; -floo_rsp_t router_2_12_to_magia_tile_ni_2_12_rsp; - -floo_req_t magia_tile_ni_2_13_to_router_2_13_req; -floo_rsp_t router_2_13_to_magia_tile_ni_2_13_rsp; - -floo_req_t magia_tile_ni_2_14_to_router_2_14_req; -floo_rsp_t router_2_14_to_magia_tile_ni_2_14_rsp; - -floo_req_t magia_tile_ni_2_15_to_router_2_15_req; -floo_rsp_t router_2_15_to_magia_tile_ni_2_15_rsp; - -floo_req_t magia_tile_ni_2_16_to_router_2_16_req; -floo_rsp_t router_2_16_to_magia_tile_ni_2_16_rsp; - -floo_req_t magia_tile_ni_2_17_to_router_2_17_req; -floo_rsp_t router_2_17_to_magia_tile_ni_2_17_rsp; - -floo_req_t magia_tile_ni_2_18_to_router_2_18_req; -floo_rsp_t router_2_18_to_magia_tile_ni_2_18_rsp; - -floo_req_t magia_tile_ni_2_19_to_router_2_19_req; -floo_rsp_t router_2_19_to_magia_tile_ni_2_19_rsp; - -floo_req_t magia_tile_ni_2_20_to_router_2_20_req; -floo_rsp_t router_2_20_to_magia_tile_ni_2_20_rsp; - -floo_req_t magia_tile_ni_2_21_to_router_2_21_req; -floo_rsp_t router_2_21_to_magia_tile_ni_2_21_rsp; - -floo_req_t magia_tile_ni_2_22_to_router_2_22_req; -floo_rsp_t router_2_22_to_magia_tile_ni_2_22_rsp; - -floo_req_t magia_tile_ni_2_23_to_router_2_23_req; -floo_rsp_t router_2_23_to_magia_tile_ni_2_23_rsp; - -floo_req_t magia_tile_ni_2_24_to_router_2_24_req; -floo_rsp_t router_2_24_to_magia_tile_ni_2_24_rsp; - -floo_req_t magia_tile_ni_2_25_to_router_2_25_req; -floo_rsp_t router_2_25_to_magia_tile_ni_2_25_rsp; - -floo_req_t magia_tile_ni_2_26_to_router_2_26_req; -floo_rsp_t router_2_26_to_magia_tile_ni_2_26_rsp; - -floo_req_t magia_tile_ni_2_27_to_router_2_27_req; -floo_rsp_t router_2_27_to_magia_tile_ni_2_27_rsp; - -floo_req_t magia_tile_ni_2_28_to_router_2_28_req; -floo_rsp_t router_2_28_to_magia_tile_ni_2_28_rsp; - -floo_req_t magia_tile_ni_2_29_to_router_2_29_req; -floo_rsp_t router_2_29_to_magia_tile_ni_2_29_rsp; - -floo_req_t magia_tile_ni_2_30_to_router_2_30_req; -floo_rsp_t router_2_30_to_magia_tile_ni_2_30_rsp; - -floo_req_t magia_tile_ni_2_31_to_router_2_31_req; -floo_rsp_t router_2_31_to_magia_tile_ni_2_31_rsp; - -floo_req_t magia_tile_ni_3_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_magia_tile_ni_3_0_rsp; - -floo_req_t magia_tile_ni_3_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_magia_tile_ni_3_1_rsp; - -floo_req_t magia_tile_ni_3_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_magia_tile_ni_3_2_rsp; - -floo_req_t magia_tile_ni_3_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_magia_tile_ni_3_3_rsp; - -floo_req_t magia_tile_ni_3_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_magia_tile_ni_3_4_rsp; - -floo_req_t magia_tile_ni_3_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_magia_tile_ni_3_5_rsp; - -floo_req_t magia_tile_ni_3_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_magia_tile_ni_3_6_rsp; - -floo_req_t magia_tile_ni_3_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_magia_tile_ni_3_7_rsp; - -floo_req_t magia_tile_ni_3_8_to_router_3_8_req; -floo_rsp_t router_3_8_to_magia_tile_ni_3_8_rsp; - -floo_req_t magia_tile_ni_3_9_to_router_3_9_req; -floo_rsp_t router_3_9_to_magia_tile_ni_3_9_rsp; - -floo_req_t magia_tile_ni_3_10_to_router_3_10_req; -floo_rsp_t router_3_10_to_magia_tile_ni_3_10_rsp; - -floo_req_t magia_tile_ni_3_11_to_router_3_11_req; -floo_rsp_t router_3_11_to_magia_tile_ni_3_11_rsp; - -floo_req_t magia_tile_ni_3_12_to_router_3_12_req; -floo_rsp_t router_3_12_to_magia_tile_ni_3_12_rsp; - -floo_req_t magia_tile_ni_3_13_to_router_3_13_req; -floo_rsp_t router_3_13_to_magia_tile_ni_3_13_rsp; - -floo_req_t magia_tile_ni_3_14_to_router_3_14_req; -floo_rsp_t router_3_14_to_magia_tile_ni_3_14_rsp; - -floo_req_t magia_tile_ni_3_15_to_router_3_15_req; -floo_rsp_t router_3_15_to_magia_tile_ni_3_15_rsp; - -floo_req_t magia_tile_ni_3_16_to_router_3_16_req; -floo_rsp_t router_3_16_to_magia_tile_ni_3_16_rsp; - -floo_req_t magia_tile_ni_3_17_to_router_3_17_req; -floo_rsp_t router_3_17_to_magia_tile_ni_3_17_rsp; - -floo_req_t magia_tile_ni_3_18_to_router_3_18_req; -floo_rsp_t router_3_18_to_magia_tile_ni_3_18_rsp; - -floo_req_t magia_tile_ni_3_19_to_router_3_19_req; -floo_rsp_t router_3_19_to_magia_tile_ni_3_19_rsp; - -floo_req_t magia_tile_ni_3_20_to_router_3_20_req; -floo_rsp_t router_3_20_to_magia_tile_ni_3_20_rsp; - -floo_req_t magia_tile_ni_3_21_to_router_3_21_req; -floo_rsp_t router_3_21_to_magia_tile_ni_3_21_rsp; - -floo_req_t magia_tile_ni_3_22_to_router_3_22_req; -floo_rsp_t router_3_22_to_magia_tile_ni_3_22_rsp; - -floo_req_t magia_tile_ni_3_23_to_router_3_23_req; -floo_rsp_t router_3_23_to_magia_tile_ni_3_23_rsp; - -floo_req_t magia_tile_ni_3_24_to_router_3_24_req; -floo_rsp_t router_3_24_to_magia_tile_ni_3_24_rsp; - -floo_req_t magia_tile_ni_3_25_to_router_3_25_req; -floo_rsp_t router_3_25_to_magia_tile_ni_3_25_rsp; - -floo_req_t magia_tile_ni_3_26_to_router_3_26_req; -floo_rsp_t router_3_26_to_magia_tile_ni_3_26_rsp; - -floo_req_t magia_tile_ni_3_27_to_router_3_27_req; -floo_rsp_t router_3_27_to_magia_tile_ni_3_27_rsp; - -floo_req_t magia_tile_ni_3_28_to_router_3_28_req; -floo_rsp_t router_3_28_to_magia_tile_ni_3_28_rsp; - -floo_req_t magia_tile_ni_3_29_to_router_3_29_req; -floo_rsp_t router_3_29_to_magia_tile_ni_3_29_rsp; - -floo_req_t magia_tile_ni_3_30_to_router_3_30_req; -floo_rsp_t router_3_30_to_magia_tile_ni_3_30_rsp; - -floo_req_t magia_tile_ni_3_31_to_router_3_31_req; -floo_rsp_t router_3_31_to_magia_tile_ni_3_31_rsp; - -floo_req_t magia_tile_ni_4_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_magia_tile_ni_4_0_rsp; - -floo_req_t magia_tile_ni_4_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_magia_tile_ni_4_1_rsp; - -floo_req_t magia_tile_ni_4_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_magia_tile_ni_4_2_rsp; - -floo_req_t magia_tile_ni_4_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_magia_tile_ni_4_3_rsp; - -floo_req_t magia_tile_ni_4_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_magia_tile_ni_4_4_rsp; - -floo_req_t magia_tile_ni_4_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_magia_tile_ni_4_5_rsp; - -floo_req_t magia_tile_ni_4_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_magia_tile_ni_4_6_rsp; - -floo_req_t magia_tile_ni_4_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_magia_tile_ni_4_7_rsp; - -floo_req_t magia_tile_ni_4_8_to_router_4_8_req; -floo_rsp_t router_4_8_to_magia_tile_ni_4_8_rsp; - -floo_req_t magia_tile_ni_4_9_to_router_4_9_req; -floo_rsp_t router_4_9_to_magia_tile_ni_4_9_rsp; - -floo_req_t magia_tile_ni_4_10_to_router_4_10_req; -floo_rsp_t router_4_10_to_magia_tile_ni_4_10_rsp; - -floo_req_t magia_tile_ni_4_11_to_router_4_11_req; -floo_rsp_t router_4_11_to_magia_tile_ni_4_11_rsp; - -floo_req_t magia_tile_ni_4_12_to_router_4_12_req; -floo_rsp_t router_4_12_to_magia_tile_ni_4_12_rsp; - -floo_req_t magia_tile_ni_4_13_to_router_4_13_req; -floo_rsp_t router_4_13_to_magia_tile_ni_4_13_rsp; - -floo_req_t magia_tile_ni_4_14_to_router_4_14_req; -floo_rsp_t router_4_14_to_magia_tile_ni_4_14_rsp; - -floo_req_t magia_tile_ni_4_15_to_router_4_15_req; -floo_rsp_t router_4_15_to_magia_tile_ni_4_15_rsp; - -floo_req_t magia_tile_ni_4_16_to_router_4_16_req; -floo_rsp_t router_4_16_to_magia_tile_ni_4_16_rsp; - -floo_req_t magia_tile_ni_4_17_to_router_4_17_req; -floo_rsp_t router_4_17_to_magia_tile_ni_4_17_rsp; - -floo_req_t magia_tile_ni_4_18_to_router_4_18_req; -floo_rsp_t router_4_18_to_magia_tile_ni_4_18_rsp; - -floo_req_t magia_tile_ni_4_19_to_router_4_19_req; -floo_rsp_t router_4_19_to_magia_tile_ni_4_19_rsp; - -floo_req_t magia_tile_ni_4_20_to_router_4_20_req; -floo_rsp_t router_4_20_to_magia_tile_ni_4_20_rsp; - -floo_req_t magia_tile_ni_4_21_to_router_4_21_req; -floo_rsp_t router_4_21_to_magia_tile_ni_4_21_rsp; - -floo_req_t magia_tile_ni_4_22_to_router_4_22_req; -floo_rsp_t router_4_22_to_magia_tile_ni_4_22_rsp; - -floo_req_t magia_tile_ni_4_23_to_router_4_23_req; -floo_rsp_t router_4_23_to_magia_tile_ni_4_23_rsp; - -floo_req_t magia_tile_ni_4_24_to_router_4_24_req; -floo_rsp_t router_4_24_to_magia_tile_ni_4_24_rsp; - -floo_req_t magia_tile_ni_4_25_to_router_4_25_req; -floo_rsp_t router_4_25_to_magia_tile_ni_4_25_rsp; - -floo_req_t magia_tile_ni_4_26_to_router_4_26_req; -floo_rsp_t router_4_26_to_magia_tile_ni_4_26_rsp; - -floo_req_t magia_tile_ni_4_27_to_router_4_27_req; -floo_rsp_t router_4_27_to_magia_tile_ni_4_27_rsp; - -floo_req_t magia_tile_ni_4_28_to_router_4_28_req; -floo_rsp_t router_4_28_to_magia_tile_ni_4_28_rsp; - -floo_req_t magia_tile_ni_4_29_to_router_4_29_req; -floo_rsp_t router_4_29_to_magia_tile_ni_4_29_rsp; - -floo_req_t magia_tile_ni_4_30_to_router_4_30_req; -floo_rsp_t router_4_30_to_magia_tile_ni_4_30_rsp; - -floo_req_t magia_tile_ni_4_31_to_router_4_31_req; -floo_rsp_t router_4_31_to_magia_tile_ni_4_31_rsp; - -floo_req_t magia_tile_ni_5_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_magia_tile_ni_5_0_rsp; - -floo_req_t magia_tile_ni_5_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_magia_tile_ni_5_1_rsp; - -floo_req_t magia_tile_ni_5_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_magia_tile_ni_5_2_rsp; - -floo_req_t magia_tile_ni_5_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_magia_tile_ni_5_3_rsp; - -floo_req_t magia_tile_ni_5_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_magia_tile_ni_5_4_rsp; - -floo_req_t magia_tile_ni_5_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_magia_tile_ni_5_5_rsp; - -floo_req_t magia_tile_ni_5_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_magia_tile_ni_5_6_rsp; - -floo_req_t magia_tile_ni_5_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_magia_tile_ni_5_7_rsp; - -floo_req_t magia_tile_ni_5_8_to_router_5_8_req; -floo_rsp_t router_5_8_to_magia_tile_ni_5_8_rsp; - -floo_req_t magia_tile_ni_5_9_to_router_5_9_req; -floo_rsp_t router_5_9_to_magia_tile_ni_5_9_rsp; - -floo_req_t magia_tile_ni_5_10_to_router_5_10_req; -floo_rsp_t router_5_10_to_magia_tile_ni_5_10_rsp; - -floo_req_t magia_tile_ni_5_11_to_router_5_11_req; -floo_rsp_t router_5_11_to_magia_tile_ni_5_11_rsp; - -floo_req_t magia_tile_ni_5_12_to_router_5_12_req; -floo_rsp_t router_5_12_to_magia_tile_ni_5_12_rsp; - -floo_req_t magia_tile_ni_5_13_to_router_5_13_req; -floo_rsp_t router_5_13_to_magia_tile_ni_5_13_rsp; - -floo_req_t magia_tile_ni_5_14_to_router_5_14_req; -floo_rsp_t router_5_14_to_magia_tile_ni_5_14_rsp; - -floo_req_t magia_tile_ni_5_15_to_router_5_15_req; -floo_rsp_t router_5_15_to_magia_tile_ni_5_15_rsp; - -floo_req_t magia_tile_ni_5_16_to_router_5_16_req; -floo_rsp_t router_5_16_to_magia_tile_ni_5_16_rsp; - -floo_req_t magia_tile_ni_5_17_to_router_5_17_req; -floo_rsp_t router_5_17_to_magia_tile_ni_5_17_rsp; - -floo_req_t magia_tile_ni_5_18_to_router_5_18_req; -floo_rsp_t router_5_18_to_magia_tile_ni_5_18_rsp; - -floo_req_t magia_tile_ni_5_19_to_router_5_19_req; -floo_rsp_t router_5_19_to_magia_tile_ni_5_19_rsp; - -floo_req_t magia_tile_ni_5_20_to_router_5_20_req; -floo_rsp_t router_5_20_to_magia_tile_ni_5_20_rsp; - -floo_req_t magia_tile_ni_5_21_to_router_5_21_req; -floo_rsp_t router_5_21_to_magia_tile_ni_5_21_rsp; - -floo_req_t magia_tile_ni_5_22_to_router_5_22_req; -floo_rsp_t router_5_22_to_magia_tile_ni_5_22_rsp; - -floo_req_t magia_tile_ni_5_23_to_router_5_23_req; -floo_rsp_t router_5_23_to_magia_tile_ni_5_23_rsp; - -floo_req_t magia_tile_ni_5_24_to_router_5_24_req; -floo_rsp_t router_5_24_to_magia_tile_ni_5_24_rsp; - -floo_req_t magia_tile_ni_5_25_to_router_5_25_req; -floo_rsp_t router_5_25_to_magia_tile_ni_5_25_rsp; - -floo_req_t magia_tile_ni_5_26_to_router_5_26_req; -floo_rsp_t router_5_26_to_magia_tile_ni_5_26_rsp; - -floo_req_t magia_tile_ni_5_27_to_router_5_27_req; -floo_rsp_t router_5_27_to_magia_tile_ni_5_27_rsp; - -floo_req_t magia_tile_ni_5_28_to_router_5_28_req; -floo_rsp_t router_5_28_to_magia_tile_ni_5_28_rsp; - -floo_req_t magia_tile_ni_5_29_to_router_5_29_req; -floo_rsp_t router_5_29_to_magia_tile_ni_5_29_rsp; - -floo_req_t magia_tile_ni_5_30_to_router_5_30_req; -floo_rsp_t router_5_30_to_magia_tile_ni_5_30_rsp; - -floo_req_t magia_tile_ni_5_31_to_router_5_31_req; -floo_rsp_t router_5_31_to_magia_tile_ni_5_31_rsp; - -floo_req_t magia_tile_ni_6_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_magia_tile_ni_6_0_rsp; - -floo_req_t magia_tile_ni_6_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_magia_tile_ni_6_1_rsp; - -floo_req_t magia_tile_ni_6_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_magia_tile_ni_6_2_rsp; - -floo_req_t magia_tile_ni_6_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_magia_tile_ni_6_3_rsp; - -floo_req_t magia_tile_ni_6_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_magia_tile_ni_6_4_rsp; - -floo_req_t magia_tile_ni_6_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_magia_tile_ni_6_5_rsp; - -floo_req_t magia_tile_ni_6_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_magia_tile_ni_6_6_rsp; - -floo_req_t magia_tile_ni_6_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_magia_tile_ni_6_7_rsp; - -floo_req_t magia_tile_ni_6_8_to_router_6_8_req; -floo_rsp_t router_6_8_to_magia_tile_ni_6_8_rsp; - -floo_req_t magia_tile_ni_6_9_to_router_6_9_req; -floo_rsp_t router_6_9_to_magia_tile_ni_6_9_rsp; - -floo_req_t magia_tile_ni_6_10_to_router_6_10_req; -floo_rsp_t router_6_10_to_magia_tile_ni_6_10_rsp; - -floo_req_t magia_tile_ni_6_11_to_router_6_11_req; -floo_rsp_t router_6_11_to_magia_tile_ni_6_11_rsp; - -floo_req_t magia_tile_ni_6_12_to_router_6_12_req; -floo_rsp_t router_6_12_to_magia_tile_ni_6_12_rsp; - -floo_req_t magia_tile_ni_6_13_to_router_6_13_req; -floo_rsp_t router_6_13_to_magia_tile_ni_6_13_rsp; - -floo_req_t magia_tile_ni_6_14_to_router_6_14_req; -floo_rsp_t router_6_14_to_magia_tile_ni_6_14_rsp; - -floo_req_t magia_tile_ni_6_15_to_router_6_15_req; -floo_rsp_t router_6_15_to_magia_tile_ni_6_15_rsp; - -floo_req_t magia_tile_ni_6_16_to_router_6_16_req; -floo_rsp_t router_6_16_to_magia_tile_ni_6_16_rsp; - -floo_req_t magia_tile_ni_6_17_to_router_6_17_req; -floo_rsp_t router_6_17_to_magia_tile_ni_6_17_rsp; - -floo_req_t magia_tile_ni_6_18_to_router_6_18_req; -floo_rsp_t router_6_18_to_magia_tile_ni_6_18_rsp; - -floo_req_t magia_tile_ni_6_19_to_router_6_19_req; -floo_rsp_t router_6_19_to_magia_tile_ni_6_19_rsp; - -floo_req_t magia_tile_ni_6_20_to_router_6_20_req; -floo_rsp_t router_6_20_to_magia_tile_ni_6_20_rsp; - -floo_req_t magia_tile_ni_6_21_to_router_6_21_req; -floo_rsp_t router_6_21_to_magia_tile_ni_6_21_rsp; - -floo_req_t magia_tile_ni_6_22_to_router_6_22_req; -floo_rsp_t router_6_22_to_magia_tile_ni_6_22_rsp; - -floo_req_t magia_tile_ni_6_23_to_router_6_23_req; -floo_rsp_t router_6_23_to_magia_tile_ni_6_23_rsp; - -floo_req_t magia_tile_ni_6_24_to_router_6_24_req; -floo_rsp_t router_6_24_to_magia_tile_ni_6_24_rsp; - -floo_req_t magia_tile_ni_6_25_to_router_6_25_req; -floo_rsp_t router_6_25_to_magia_tile_ni_6_25_rsp; - -floo_req_t magia_tile_ni_6_26_to_router_6_26_req; -floo_rsp_t router_6_26_to_magia_tile_ni_6_26_rsp; - -floo_req_t magia_tile_ni_6_27_to_router_6_27_req; -floo_rsp_t router_6_27_to_magia_tile_ni_6_27_rsp; - -floo_req_t magia_tile_ni_6_28_to_router_6_28_req; -floo_rsp_t router_6_28_to_magia_tile_ni_6_28_rsp; - -floo_req_t magia_tile_ni_6_29_to_router_6_29_req; -floo_rsp_t router_6_29_to_magia_tile_ni_6_29_rsp; - -floo_req_t magia_tile_ni_6_30_to_router_6_30_req; -floo_rsp_t router_6_30_to_magia_tile_ni_6_30_rsp; - -floo_req_t magia_tile_ni_6_31_to_router_6_31_req; -floo_rsp_t router_6_31_to_magia_tile_ni_6_31_rsp; - -floo_req_t magia_tile_ni_7_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_magia_tile_ni_7_0_rsp; - -floo_req_t magia_tile_ni_7_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_magia_tile_ni_7_1_rsp; - -floo_req_t magia_tile_ni_7_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_magia_tile_ni_7_2_rsp; - -floo_req_t magia_tile_ni_7_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_magia_tile_ni_7_3_rsp; - -floo_req_t magia_tile_ni_7_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_magia_tile_ni_7_4_rsp; - -floo_req_t magia_tile_ni_7_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_magia_tile_ni_7_5_rsp; - -floo_req_t magia_tile_ni_7_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_magia_tile_ni_7_6_rsp; - -floo_req_t magia_tile_ni_7_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_magia_tile_ni_7_7_rsp; - -floo_req_t magia_tile_ni_7_8_to_router_7_8_req; -floo_rsp_t router_7_8_to_magia_tile_ni_7_8_rsp; - -floo_req_t magia_tile_ni_7_9_to_router_7_9_req; -floo_rsp_t router_7_9_to_magia_tile_ni_7_9_rsp; - -floo_req_t magia_tile_ni_7_10_to_router_7_10_req; -floo_rsp_t router_7_10_to_magia_tile_ni_7_10_rsp; - -floo_req_t magia_tile_ni_7_11_to_router_7_11_req; -floo_rsp_t router_7_11_to_magia_tile_ni_7_11_rsp; - -floo_req_t magia_tile_ni_7_12_to_router_7_12_req; -floo_rsp_t router_7_12_to_magia_tile_ni_7_12_rsp; - -floo_req_t magia_tile_ni_7_13_to_router_7_13_req; -floo_rsp_t router_7_13_to_magia_tile_ni_7_13_rsp; - -floo_req_t magia_tile_ni_7_14_to_router_7_14_req; -floo_rsp_t router_7_14_to_magia_tile_ni_7_14_rsp; - -floo_req_t magia_tile_ni_7_15_to_router_7_15_req; -floo_rsp_t router_7_15_to_magia_tile_ni_7_15_rsp; - -floo_req_t magia_tile_ni_7_16_to_router_7_16_req; -floo_rsp_t router_7_16_to_magia_tile_ni_7_16_rsp; - -floo_req_t magia_tile_ni_7_17_to_router_7_17_req; -floo_rsp_t router_7_17_to_magia_tile_ni_7_17_rsp; - -floo_req_t magia_tile_ni_7_18_to_router_7_18_req; -floo_rsp_t router_7_18_to_magia_tile_ni_7_18_rsp; - -floo_req_t magia_tile_ni_7_19_to_router_7_19_req; -floo_rsp_t router_7_19_to_magia_tile_ni_7_19_rsp; - -floo_req_t magia_tile_ni_7_20_to_router_7_20_req; -floo_rsp_t router_7_20_to_magia_tile_ni_7_20_rsp; - -floo_req_t magia_tile_ni_7_21_to_router_7_21_req; -floo_rsp_t router_7_21_to_magia_tile_ni_7_21_rsp; - -floo_req_t magia_tile_ni_7_22_to_router_7_22_req; -floo_rsp_t router_7_22_to_magia_tile_ni_7_22_rsp; - -floo_req_t magia_tile_ni_7_23_to_router_7_23_req; -floo_rsp_t router_7_23_to_magia_tile_ni_7_23_rsp; - -floo_req_t magia_tile_ni_7_24_to_router_7_24_req; -floo_rsp_t router_7_24_to_magia_tile_ni_7_24_rsp; - -floo_req_t magia_tile_ni_7_25_to_router_7_25_req; -floo_rsp_t router_7_25_to_magia_tile_ni_7_25_rsp; - -floo_req_t magia_tile_ni_7_26_to_router_7_26_req; -floo_rsp_t router_7_26_to_magia_tile_ni_7_26_rsp; - -floo_req_t magia_tile_ni_7_27_to_router_7_27_req; -floo_rsp_t router_7_27_to_magia_tile_ni_7_27_rsp; - -floo_req_t magia_tile_ni_7_28_to_router_7_28_req; -floo_rsp_t router_7_28_to_magia_tile_ni_7_28_rsp; - -floo_req_t magia_tile_ni_7_29_to_router_7_29_req; -floo_rsp_t router_7_29_to_magia_tile_ni_7_29_rsp; - -floo_req_t magia_tile_ni_7_30_to_router_7_30_req; -floo_rsp_t router_7_30_to_magia_tile_ni_7_30_rsp; - -floo_req_t magia_tile_ni_7_31_to_router_7_31_req; -floo_rsp_t router_7_31_to_magia_tile_ni_7_31_rsp; - -floo_req_t magia_tile_ni_8_0_to_router_8_0_req; -floo_rsp_t router_8_0_to_magia_tile_ni_8_0_rsp; - -floo_req_t magia_tile_ni_8_1_to_router_8_1_req; -floo_rsp_t router_8_1_to_magia_tile_ni_8_1_rsp; - -floo_req_t magia_tile_ni_8_2_to_router_8_2_req; -floo_rsp_t router_8_2_to_magia_tile_ni_8_2_rsp; - -floo_req_t magia_tile_ni_8_3_to_router_8_3_req; -floo_rsp_t router_8_3_to_magia_tile_ni_8_3_rsp; - -floo_req_t magia_tile_ni_8_4_to_router_8_4_req; -floo_rsp_t router_8_4_to_magia_tile_ni_8_4_rsp; - -floo_req_t magia_tile_ni_8_5_to_router_8_5_req; -floo_rsp_t router_8_5_to_magia_tile_ni_8_5_rsp; - -floo_req_t magia_tile_ni_8_6_to_router_8_6_req; -floo_rsp_t router_8_6_to_magia_tile_ni_8_6_rsp; - -floo_req_t magia_tile_ni_8_7_to_router_8_7_req; -floo_rsp_t router_8_7_to_magia_tile_ni_8_7_rsp; - -floo_req_t magia_tile_ni_8_8_to_router_8_8_req; -floo_rsp_t router_8_8_to_magia_tile_ni_8_8_rsp; - -floo_req_t magia_tile_ni_8_9_to_router_8_9_req; -floo_rsp_t router_8_9_to_magia_tile_ni_8_9_rsp; - -floo_req_t magia_tile_ni_8_10_to_router_8_10_req; -floo_rsp_t router_8_10_to_magia_tile_ni_8_10_rsp; - -floo_req_t magia_tile_ni_8_11_to_router_8_11_req; -floo_rsp_t router_8_11_to_magia_tile_ni_8_11_rsp; - -floo_req_t magia_tile_ni_8_12_to_router_8_12_req; -floo_rsp_t router_8_12_to_magia_tile_ni_8_12_rsp; - -floo_req_t magia_tile_ni_8_13_to_router_8_13_req; -floo_rsp_t router_8_13_to_magia_tile_ni_8_13_rsp; - -floo_req_t magia_tile_ni_8_14_to_router_8_14_req; -floo_rsp_t router_8_14_to_magia_tile_ni_8_14_rsp; - -floo_req_t magia_tile_ni_8_15_to_router_8_15_req; -floo_rsp_t router_8_15_to_magia_tile_ni_8_15_rsp; - -floo_req_t magia_tile_ni_8_16_to_router_8_16_req; -floo_rsp_t router_8_16_to_magia_tile_ni_8_16_rsp; - -floo_req_t magia_tile_ni_8_17_to_router_8_17_req; -floo_rsp_t router_8_17_to_magia_tile_ni_8_17_rsp; - -floo_req_t magia_tile_ni_8_18_to_router_8_18_req; -floo_rsp_t router_8_18_to_magia_tile_ni_8_18_rsp; - -floo_req_t magia_tile_ni_8_19_to_router_8_19_req; -floo_rsp_t router_8_19_to_magia_tile_ni_8_19_rsp; - -floo_req_t magia_tile_ni_8_20_to_router_8_20_req; -floo_rsp_t router_8_20_to_magia_tile_ni_8_20_rsp; - -floo_req_t magia_tile_ni_8_21_to_router_8_21_req; -floo_rsp_t router_8_21_to_magia_tile_ni_8_21_rsp; - -floo_req_t magia_tile_ni_8_22_to_router_8_22_req; -floo_rsp_t router_8_22_to_magia_tile_ni_8_22_rsp; - -floo_req_t magia_tile_ni_8_23_to_router_8_23_req; -floo_rsp_t router_8_23_to_magia_tile_ni_8_23_rsp; - -floo_req_t magia_tile_ni_8_24_to_router_8_24_req; -floo_rsp_t router_8_24_to_magia_tile_ni_8_24_rsp; - -floo_req_t magia_tile_ni_8_25_to_router_8_25_req; -floo_rsp_t router_8_25_to_magia_tile_ni_8_25_rsp; - -floo_req_t magia_tile_ni_8_26_to_router_8_26_req; -floo_rsp_t router_8_26_to_magia_tile_ni_8_26_rsp; - -floo_req_t magia_tile_ni_8_27_to_router_8_27_req; -floo_rsp_t router_8_27_to_magia_tile_ni_8_27_rsp; - -floo_req_t magia_tile_ni_8_28_to_router_8_28_req; -floo_rsp_t router_8_28_to_magia_tile_ni_8_28_rsp; - -floo_req_t magia_tile_ni_8_29_to_router_8_29_req; -floo_rsp_t router_8_29_to_magia_tile_ni_8_29_rsp; - -floo_req_t magia_tile_ni_8_30_to_router_8_30_req; -floo_rsp_t router_8_30_to_magia_tile_ni_8_30_rsp; - -floo_req_t magia_tile_ni_8_31_to_router_8_31_req; -floo_rsp_t router_8_31_to_magia_tile_ni_8_31_rsp; - -floo_req_t magia_tile_ni_9_0_to_router_9_0_req; -floo_rsp_t router_9_0_to_magia_tile_ni_9_0_rsp; - -floo_req_t magia_tile_ni_9_1_to_router_9_1_req; -floo_rsp_t router_9_1_to_magia_tile_ni_9_1_rsp; - -floo_req_t magia_tile_ni_9_2_to_router_9_2_req; -floo_rsp_t router_9_2_to_magia_tile_ni_9_2_rsp; - -floo_req_t magia_tile_ni_9_3_to_router_9_3_req; -floo_rsp_t router_9_3_to_magia_tile_ni_9_3_rsp; - -floo_req_t magia_tile_ni_9_4_to_router_9_4_req; -floo_rsp_t router_9_4_to_magia_tile_ni_9_4_rsp; - -floo_req_t magia_tile_ni_9_5_to_router_9_5_req; -floo_rsp_t router_9_5_to_magia_tile_ni_9_5_rsp; - -floo_req_t magia_tile_ni_9_6_to_router_9_6_req; -floo_rsp_t router_9_6_to_magia_tile_ni_9_6_rsp; - -floo_req_t magia_tile_ni_9_7_to_router_9_7_req; -floo_rsp_t router_9_7_to_magia_tile_ni_9_7_rsp; - -floo_req_t magia_tile_ni_9_8_to_router_9_8_req; -floo_rsp_t router_9_8_to_magia_tile_ni_9_8_rsp; - -floo_req_t magia_tile_ni_9_9_to_router_9_9_req; -floo_rsp_t router_9_9_to_magia_tile_ni_9_9_rsp; - -floo_req_t magia_tile_ni_9_10_to_router_9_10_req; -floo_rsp_t router_9_10_to_magia_tile_ni_9_10_rsp; - -floo_req_t magia_tile_ni_9_11_to_router_9_11_req; -floo_rsp_t router_9_11_to_magia_tile_ni_9_11_rsp; - -floo_req_t magia_tile_ni_9_12_to_router_9_12_req; -floo_rsp_t router_9_12_to_magia_tile_ni_9_12_rsp; - -floo_req_t magia_tile_ni_9_13_to_router_9_13_req; -floo_rsp_t router_9_13_to_magia_tile_ni_9_13_rsp; - -floo_req_t magia_tile_ni_9_14_to_router_9_14_req; -floo_rsp_t router_9_14_to_magia_tile_ni_9_14_rsp; - -floo_req_t magia_tile_ni_9_15_to_router_9_15_req; -floo_rsp_t router_9_15_to_magia_tile_ni_9_15_rsp; - -floo_req_t magia_tile_ni_9_16_to_router_9_16_req; -floo_rsp_t router_9_16_to_magia_tile_ni_9_16_rsp; - -floo_req_t magia_tile_ni_9_17_to_router_9_17_req; -floo_rsp_t router_9_17_to_magia_tile_ni_9_17_rsp; - -floo_req_t magia_tile_ni_9_18_to_router_9_18_req; -floo_rsp_t router_9_18_to_magia_tile_ni_9_18_rsp; - -floo_req_t magia_tile_ni_9_19_to_router_9_19_req; -floo_rsp_t router_9_19_to_magia_tile_ni_9_19_rsp; - -floo_req_t magia_tile_ni_9_20_to_router_9_20_req; -floo_rsp_t router_9_20_to_magia_tile_ni_9_20_rsp; - -floo_req_t magia_tile_ni_9_21_to_router_9_21_req; -floo_rsp_t router_9_21_to_magia_tile_ni_9_21_rsp; - -floo_req_t magia_tile_ni_9_22_to_router_9_22_req; -floo_rsp_t router_9_22_to_magia_tile_ni_9_22_rsp; - -floo_req_t magia_tile_ni_9_23_to_router_9_23_req; -floo_rsp_t router_9_23_to_magia_tile_ni_9_23_rsp; - -floo_req_t magia_tile_ni_9_24_to_router_9_24_req; -floo_rsp_t router_9_24_to_magia_tile_ni_9_24_rsp; - -floo_req_t magia_tile_ni_9_25_to_router_9_25_req; -floo_rsp_t router_9_25_to_magia_tile_ni_9_25_rsp; - -floo_req_t magia_tile_ni_9_26_to_router_9_26_req; -floo_rsp_t router_9_26_to_magia_tile_ni_9_26_rsp; - -floo_req_t magia_tile_ni_9_27_to_router_9_27_req; -floo_rsp_t router_9_27_to_magia_tile_ni_9_27_rsp; - -floo_req_t magia_tile_ni_9_28_to_router_9_28_req; -floo_rsp_t router_9_28_to_magia_tile_ni_9_28_rsp; - -floo_req_t magia_tile_ni_9_29_to_router_9_29_req; -floo_rsp_t router_9_29_to_magia_tile_ni_9_29_rsp; - -floo_req_t magia_tile_ni_9_30_to_router_9_30_req; -floo_rsp_t router_9_30_to_magia_tile_ni_9_30_rsp; - -floo_req_t magia_tile_ni_9_31_to_router_9_31_req; -floo_rsp_t router_9_31_to_magia_tile_ni_9_31_rsp; - -floo_req_t magia_tile_ni_10_0_to_router_10_0_req; -floo_rsp_t router_10_0_to_magia_tile_ni_10_0_rsp; - -floo_req_t magia_tile_ni_10_1_to_router_10_1_req; -floo_rsp_t router_10_1_to_magia_tile_ni_10_1_rsp; - -floo_req_t magia_tile_ni_10_2_to_router_10_2_req; -floo_rsp_t router_10_2_to_magia_tile_ni_10_2_rsp; - -floo_req_t magia_tile_ni_10_3_to_router_10_3_req; -floo_rsp_t router_10_3_to_magia_tile_ni_10_3_rsp; - -floo_req_t magia_tile_ni_10_4_to_router_10_4_req; -floo_rsp_t router_10_4_to_magia_tile_ni_10_4_rsp; - -floo_req_t magia_tile_ni_10_5_to_router_10_5_req; -floo_rsp_t router_10_5_to_magia_tile_ni_10_5_rsp; - -floo_req_t magia_tile_ni_10_6_to_router_10_6_req; -floo_rsp_t router_10_6_to_magia_tile_ni_10_6_rsp; - -floo_req_t magia_tile_ni_10_7_to_router_10_7_req; -floo_rsp_t router_10_7_to_magia_tile_ni_10_7_rsp; - -floo_req_t magia_tile_ni_10_8_to_router_10_8_req; -floo_rsp_t router_10_8_to_magia_tile_ni_10_8_rsp; - -floo_req_t magia_tile_ni_10_9_to_router_10_9_req; -floo_rsp_t router_10_9_to_magia_tile_ni_10_9_rsp; - -floo_req_t magia_tile_ni_10_10_to_router_10_10_req; -floo_rsp_t router_10_10_to_magia_tile_ni_10_10_rsp; - -floo_req_t magia_tile_ni_10_11_to_router_10_11_req; -floo_rsp_t router_10_11_to_magia_tile_ni_10_11_rsp; - -floo_req_t magia_tile_ni_10_12_to_router_10_12_req; -floo_rsp_t router_10_12_to_magia_tile_ni_10_12_rsp; - -floo_req_t magia_tile_ni_10_13_to_router_10_13_req; -floo_rsp_t router_10_13_to_magia_tile_ni_10_13_rsp; - -floo_req_t magia_tile_ni_10_14_to_router_10_14_req; -floo_rsp_t router_10_14_to_magia_tile_ni_10_14_rsp; - -floo_req_t magia_tile_ni_10_15_to_router_10_15_req; -floo_rsp_t router_10_15_to_magia_tile_ni_10_15_rsp; - -floo_req_t magia_tile_ni_10_16_to_router_10_16_req; -floo_rsp_t router_10_16_to_magia_tile_ni_10_16_rsp; - -floo_req_t magia_tile_ni_10_17_to_router_10_17_req; -floo_rsp_t router_10_17_to_magia_tile_ni_10_17_rsp; - -floo_req_t magia_tile_ni_10_18_to_router_10_18_req; -floo_rsp_t router_10_18_to_magia_tile_ni_10_18_rsp; - -floo_req_t magia_tile_ni_10_19_to_router_10_19_req; -floo_rsp_t router_10_19_to_magia_tile_ni_10_19_rsp; - -floo_req_t magia_tile_ni_10_20_to_router_10_20_req; -floo_rsp_t router_10_20_to_magia_tile_ni_10_20_rsp; - -floo_req_t magia_tile_ni_10_21_to_router_10_21_req; -floo_rsp_t router_10_21_to_magia_tile_ni_10_21_rsp; - -floo_req_t magia_tile_ni_10_22_to_router_10_22_req; -floo_rsp_t router_10_22_to_magia_tile_ni_10_22_rsp; - -floo_req_t magia_tile_ni_10_23_to_router_10_23_req; -floo_rsp_t router_10_23_to_magia_tile_ni_10_23_rsp; - -floo_req_t magia_tile_ni_10_24_to_router_10_24_req; -floo_rsp_t router_10_24_to_magia_tile_ni_10_24_rsp; - -floo_req_t magia_tile_ni_10_25_to_router_10_25_req; -floo_rsp_t router_10_25_to_magia_tile_ni_10_25_rsp; - -floo_req_t magia_tile_ni_10_26_to_router_10_26_req; -floo_rsp_t router_10_26_to_magia_tile_ni_10_26_rsp; - -floo_req_t magia_tile_ni_10_27_to_router_10_27_req; -floo_rsp_t router_10_27_to_magia_tile_ni_10_27_rsp; - -floo_req_t magia_tile_ni_10_28_to_router_10_28_req; -floo_rsp_t router_10_28_to_magia_tile_ni_10_28_rsp; - -floo_req_t magia_tile_ni_10_29_to_router_10_29_req; -floo_rsp_t router_10_29_to_magia_tile_ni_10_29_rsp; - -floo_req_t magia_tile_ni_10_30_to_router_10_30_req; -floo_rsp_t router_10_30_to_magia_tile_ni_10_30_rsp; - -floo_req_t magia_tile_ni_10_31_to_router_10_31_req; -floo_rsp_t router_10_31_to_magia_tile_ni_10_31_rsp; - -floo_req_t magia_tile_ni_11_0_to_router_11_0_req; -floo_rsp_t router_11_0_to_magia_tile_ni_11_0_rsp; - -floo_req_t magia_tile_ni_11_1_to_router_11_1_req; -floo_rsp_t router_11_1_to_magia_tile_ni_11_1_rsp; - -floo_req_t magia_tile_ni_11_2_to_router_11_2_req; -floo_rsp_t router_11_2_to_magia_tile_ni_11_2_rsp; - -floo_req_t magia_tile_ni_11_3_to_router_11_3_req; -floo_rsp_t router_11_3_to_magia_tile_ni_11_3_rsp; - -floo_req_t magia_tile_ni_11_4_to_router_11_4_req; -floo_rsp_t router_11_4_to_magia_tile_ni_11_4_rsp; - -floo_req_t magia_tile_ni_11_5_to_router_11_5_req; -floo_rsp_t router_11_5_to_magia_tile_ni_11_5_rsp; - -floo_req_t magia_tile_ni_11_6_to_router_11_6_req; -floo_rsp_t router_11_6_to_magia_tile_ni_11_6_rsp; - -floo_req_t magia_tile_ni_11_7_to_router_11_7_req; -floo_rsp_t router_11_7_to_magia_tile_ni_11_7_rsp; - -floo_req_t magia_tile_ni_11_8_to_router_11_8_req; -floo_rsp_t router_11_8_to_magia_tile_ni_11_8_rsp; - -floo_req_t magia_tile_ni_11_9_to_router_11_9_req; -floo_rsp_t router_11_9_to_magia_tile_ni_11_9_rsp; - -floo_req_t magia_tile_ni_11_10_to_router_11_10_req; -floo_rsp_t router_11_10_to_magia_tile_ni_11_10_rsp; - -floo_req_t magia_tile_ni_11_11_to_router_11_11_req; -floo_rsp_t router_11_11_to_magia_tile_ni_11_11_rsp; - -floo_req_t magia_tile_ni_11_12_to_router_11_12_req; -floo_rsp_t router_11_12_to_magia_tile_ni_11_12_rsp; - -floo_req_t magia_tile_ni_11_13_to_router_11_13_req; -floo_rsp_t router_11_13_to_magia_tile_ni_11_13_rsp; - -floo_req_t magia_tile_ni_11_14_to_router_11_14_req; -floo_rsp_t router_11_14_to_magia_tile_ni_11_14_rsp; - -floo_req_t magia_tile_ni_11_15_to_router_11_15_req; -floo_rsp_t router_11_15_to_magia_tile_ni_11_15_rsp; - -floo_req_t magia_tile_ni_11_16_to_router_11_16_req; -floo_rsp_t router_11_16_to_magia_tile_ni_11_16_rsp; - -floo_req_t magia_tile_ni_11_17_to_router_11_17_req; -floo_rsp_t router_11_17_to_magia_tile_ni_11_17_rsp; - -floo_req_t magia_tile_ni_11_18_to_router_11_18_req; -floo_rsp_t router_11_18_to_magia_tile_ni_11_18_rsp; - -floo_req_t magia_tile_ni_11_19_to_router_11_19_req; -floo_rsp_t router_11_19_to_magia_tile_ni_11_19_rsp; - -floo_req_t magia_tile_ni_11_20_to_router_11_20_req; -floo_rsp_t router_11_20_to_magia_tile_ni_11_20_rsp; - -floo_req_t magia_tile_ni_11_21_to_router_11_21_req; -floo_rsp_t router_11_21_to_magia_tile_ni_11_21_rsp; - -floo_req_t magia_tile_ni_11_22_to_router_11_22_req; -floo_rsp_t router_11_22_to_magia_tile_ni_11_22_rsp; - -floo_req_t magia_tile_ni_11_23_to_router_11_23_req; -floo_rsp_t router_11_23_to_magia_tile_ni_11_23_rsp; - -floo_req_t magia_tile_ni_11_24_to_router_11_24_req; -floo_rsp_t router_11_24_to_magia_tile_ni_11_24_rsp; - -floo_req_t magia_tile_ni_11_25_to_router_11_25_req; -floo_rsp_t router_11_25_to_magia_tile_ni_11_25_rsp; - -floo_req_t magia_tile_ni_11_26_to_router_11_26_req; -floo_rsp_t router_11_26_to_magia_tile_ni_11_26_rsp; - -floo_req_t magia_tile_ni_11_27_to_router_11_27_req; -floo_rsp_t router_11_27_to_magia_tile_ni_11_27_rsp; - -floo_req_t magia_tile_ni_11_28_to_router_11_28_req; -floo_rsp_t router_11_28_to_magia_tile_ni_11_28_rsp; - -floo_req_t magia_tile_ni_11_29_to_router_11_29_req; -floo_rsp_t router_11_29_to_magia_tile_ni_11_29_rsp; - -floo_req_t magia_tile_ni_11_30_to_router_11_30_req; -floo_rsp_t router_11_30_to_magia_tile_ni_11_30_rsp; - -floo_req_t magia_tile_ni_11_31_to_router_11_31_req; -floo_rsp_t router_11_31_to_magia_tile_ni_11_31_rsp; - -floo_req_t magia_tile_ni_12_0_to_router_12_0_req; -floo_rsp_t router_12_0_to_magia_tile_ni_12_0_rsp; - -floo_req_t magia_tile_ni_12_1_to_router_12_1_req; -floo_rsp_t router_12_1_to_magia_tile_ni_12_1_rsp; - -floo_req_t magia_tile_ni_12_2_to_router_12_2_req; -floo_rsp_t router_12_2_to_magia_tile_ni_12_2_rsp; - -floo_req_t magia_tile_ni_12_3_to_router_12_3_req; -floo_rsp_t router_12_3_to_magia_tile_ni_12_3_rsp; - -floo_req_t magia_tile_ni_12_4_to_router_12_4_req; -floo_rsp_t router_12_4_to_magia_tile_ni_12_4_rsp; - -floo_req_t magia_tile_ni_12_5_to_router_12_5_req; -floo_rsp_t router_12_5_to_magia_tile_ni_12_5_rsp; - -floo_req_t magia_tile_ni_12_6_to_router_12_6_req; -floo_rsp_t router_12_6_to_magia_tile_ni_12_6_rsp; - -floo_req_t magia_tile_ni_12_7_to_router_12_7_req; -floo_rsp_t router_12_7_to_magia_tile_ni_12_7_rsp; - -floo_req_t magia_tile_ni_12_8_to_router_12_8_req; -floo_rsp_t router_12_8_to_magia_tile_ni_12_8_rsp; - -floo_req_t magia_tile_ni_12_9_to_router_12_9_req; -floo_rsp_t router_12_9_to_magia_tile_ni_12_9_rsp; - -floo_req_t magia_tile_ni_12_10_to_router_12_10_req; -floo_rsp_t router_12_10_to_magia_tile_ni_12_10_rsp; - -floo_req_t magia_tile_ni_12_11_to_router_12_11_req; -floo_rsp_t router_12_11_to_magia_tile_ni_12_11_rsp; - -floo_req_t magia_tile_ni_12_12_to_router_12_12_req; -floo_rsp_t router_12_12_to_magia_tile_ni_12_12_rsp; - -floo_req_t magia_tile_ni_12_13_to_router_12_13_req; -floo_rsp_t router_12_13_to_magia_tile_ni_12_13_rsp; - -floo_req_t magia_tile_ni_12_14_to_router_12_14_req; -floo_rsp_t router_12_14_to_magia_tile_ni_12_14_rsp; - -floo_req_t magia_tile_ni_12_15_to_router_12_15_req; -floo_rsp_t router_12_15_to_magia_tile_ni_12_15_rsp; - -floo_req_t magia_tile_ni_12_16_to_router_12_16_req; -floo_rsp_t router_12_16_to_magia_tile_ni_12_16_rsp; - -floo_req_t magia_tile_ni_12_17_to_router_12_17_req; -floo_rsp_t router_12_17_to_magia_tile_ni_12_17_rsp; - -floo_req_t magia_tile_ni_12_18_to_router_12_18_req; -floo_rsp_t router_12_18_to_magia_tile_ni_12_18_rsp; - -floo_req_t magia_tile_ni_12_19_to_router_12_19_req; -floo_rsp_t router_12_19_to_magia_tile_ni_12_19_rsp; - -floo_req_t magia_tile_ni_12_20_to_router_12_20_req; -floo_rsp_t router_12_20_to_magia_tile_ni_12_20_rsp; - -floo_req_t magia_tile_ni_12_21_to_router_12_21_req; -floo_rsp_t router_12_21_to_magia_tile_ni_12_21_rsp; - -floo_req_t magia_tile_ni_12_22_to_router_12_22_req; -floo_rsp_t router_12_22_to_magia_tile_ni_12_22_rsp; - -floo_req_t magia_tile_ni_12_23_to_router_12_23_req; -floo_rsp_t router_12_23_to_magia_tile_ni_12_23_rsp; - -floo_req_t magia_tile_ni_12_24_to_router_12_24_req; -floo_rsp_t router_12_24_to_magia_tile_ni_12_24_rsp; - -floo_req_t magia_tile_ni_12_25_to_router_12_25_req; -floo_rsp_t router_12_25_to_magia_tile_ni_12_25_rsp; - -floo_req_t magia_tile_ni_12_26_to_router_12_26_req; -floo_rsp_t router_12_26_to_magia_tile_ni_12_26_rsp; - -floo_req_t magia_tile_ni_12_27_to_router_12_27_req; -floo_rsp_t router_12_27_to_magia_tile_ni_12_27_rsp; - -floo_req_t magia_tile_ni_12_28_to_router_12_28_req; -floo_rsp_t router_12_28_to_magia_tile_ni_12_28_rsp; - -floo_req_t magia_tile_ni_12_29_to_router_12_29_req; -floo_rsp_t router_12_29_to_magia_tile_ni_12_29_rsp; - -floo_req_t magia_tile_ni_12_30_to_router_12_30_req; -floo_rsp_t router_12_30_to_magia_tile_ni_12_30_rsp; - -floo_req_t magia_tile_ni_12_31_to_router_12_31_req; -floo_rsp_t router_12_31_to_magia_tile_ni_12_31_rsp; - -floo_req_t magia_tile_ni_13_0_to_router_13_0_req; -floo_rsp_t router_13_0_to_magia_tile_ni_13_0_rsp; - -floo_req_t magia_tile_ni_13_1_to_router_13_1_req; -floo_rsp_t router_13_1_to_magia_tile_ni_13_1_rsp; - -floo_req_t magia_tile_ni_13_2_to_router_13_2_req; -floo_rsp_t router_13_2_to_magia_tile_ni_13_2_rsp; - -floo_req_t magia_tile_ni_13_3_to_router_13_3_req; -floo_rsp_t router_13_3_to_magia_tile_ni_13_3_rsp; - -floo_req_t magia_tile_ni_13_4_to_router_13_4_req; -floo_rsp_t router_13_4_to_magia_tile_ni_13_4_rsp; - -floo_req_t magia_tile_ni_13_5_to_router_13_5_req; -floo_rsp_t router_13_5_to_magia_tile_ni_13_5_rsp; - -floo_req_t magia_tile_ni_13_6_to_router_13_6_req; -floo_rsp_t router_13_6_to_magia_tile_ni_13_6_rsp; - -floo_req_t magia_tile_ni_13_7_to_router_13_7_req; -floo_rsp_t router_13_7_to_magia_tile_ni_13_7_rsp; - -floo_req_t magia_tile_ni_13_8_to_router_13_8_req; -floo_rsp_t router_13_8_to_magia_tile_ni_13_8_rsp; - -floo_req_t magia_tile_ni_13_9_to_router_13_9_req; -floo_rsp_t router_13_9_to_magia_tile_ni_13_9_rsp; - -floo_req_t magia_tile_ni_13_10_to_router_13_10_req; -floo_rsp_t router_13_10_to_magia_tile_ni_13_10_rsp; - -floo_req_t magia_tile_ni_13_11_to_router_13_11_req; -floo_rsp_t router_13_11_to_magia_tile_ni_13_11_rsp; - -floo_req_t magia_tile_ni_13_12_to_router_13_12_req; -floo_rsp_t router_13_12_to_magia_tile_ni_13_12_rsp; - -floo_req_t magia_tile_ni_13_13_to_router_13_13_req; -floo_rsp_t router_13_13_to_magia_tile_ni_13_13_rsp; - -floo_req_t magia_tile_ni_13_14_to_router_13_14_req; -floo_rsp_t router_13_14_to_magia_tile_ni_13_14_rsp; - -floo_req_t magia_tile_ni_13_15_to_router_13_15_req; -floo_rsp_t router_13_15_to_magia_tile_ni_13_15_rsp; - -floo_req_t magia_tile_ni_13_16_to_router_13_16_req; -floo_rsp_t router_13_16_to_magia_tile_ni_13_16_rsp; - -floo_req_t magia_tile_ni_13_17_to_router_13_17_req; -floo_rsp_t router_13_17_to_magia_tile_ni_13_17_rsp; - -floo_req_t magia_tile_ni_13_18_to_router_13_18_req; -floo_rsp_t router_13_18_to_magia_tile_ni_13_18_rsp; - -floo_req_t magia_tile_ni_13_19_to_router_13_19_req; -floo_rsp_t router_13_19_to_magia_tile_ni_13_19_rsp; - -floo_req_t magia_tile_ni_13_20_to_router_13_20_req; -floo_rsp_t router_13_20_to_magia_tile_ni_13_20_rsp; - -floo_req_t magia_tile_ni_13_21_to_router_13_21_req; -floo_rsp_t router_13_21_to_magia_tile_ni_13_21_rsp; - -floo_req_t magia_tile_ni_13_22_to_router_13_22_req; -floo_rsp_t router_13_22_to_magia_tile_ni_13_22_rsp; - -floo_req_t magia_tile_ni_13_23_to_router_13_23_req; -floo_rsp_t router_13_23_to_magia_tile_ni_13_23_rsp; - -floo_req_t magia_tile_ni_13_24_to_router_13_24_req; -floo_rsp_t router_13_24_to_magia_tile_ni_13_24_rsp; - -floo_req_t magia_tile_ni_13_25_to_router_13_25_req; -floo_rsp_t router_13_25_to_magia_tile_ni_13_25_rsp; - -floo_req_t magia_tile_ni_13_26_to_router_13_26_req; -floo_rsp_t router_13_26_to_magia_tile_ni_13_26_rsp; - -floo_req_t magia_tile_ni_13_27_to_router_13_27_req; -floo_rsp_t router_13_27_to_magia_tile_ni_13_27_rsp; - -floo_req_t magia_tile_ni_13_28_to_router_13_28_req; -floo_rsp_t router_13_28_to_magia_tile_ni_13_28_rsp; - -floo_req_t magia_tile_ni_13_29_to_router_13_29_req; -floo_rsp_t router_13_29_to_magia_tile_ni_13_29_rsp; - -floo_req_t magia_tile_ni_13_30_to_router_13_30_req; -floo_rsp_t router_13_30_to_magia_tile_ni_13_30_rsp; - -floo_req_t magia_tile_ni_13_31_to_router_13_31_req; -floo_rsp_t router_13_31_to_magia_tile_ni_13_31_rsp; - -floo_req_t magia_tile_ni_14_0_to_router_14_0_req; -floo_rsp_t router_14_0_to_magia_tile_ni_14_0_rsp; - -floo_req_t magia_tile_ni_14_1_to_router_14_1_req; -floo_rsp_t router_14_1_to_magia_tile_ni_14_1_rsp; - -floo_req_t magia_tile_ni_14_2_to_router_14_2_req; -floo_rsp_t router_14_2_to_magia_tile_ni_14_2_rsp; - -floo_req_t magia_tile_ni_14_3_to_router_14_3_req; -floo_rsp_t router_14_3_to_magia_tile_ni_14_3_rsp; - -floo_req_t magia_tile_ni_14_4_to_router_14_4_req; -floo_rsp_t router_14_4_to_magia_tile_ni_14_4_rsp; - -floo_req_t magia_tile_ni_14_5_to_router_14_5_req; -floo_rsp_t router_14_5_to_magia_tile_ni_14_5_rsp; - -floo_req_t magia_tile_ni_14_6_to_router_14_6_req; -floo_rsp_t router_14_6_to_magia_tile_ni_14_6_rsp; - -floo_req_t magia_tile_ni_14_7_to_router_14_7_req; -floo_rsp_t router_14_7_to_magia_tile_ni_14_7_rsp; - -floo_req_t magia_tile_ni_14_8_to_router_14_8_req; -floo_rsp_t router_14_8_to_magia_tile_ni_14_8_rsp; - -floo_req_t magia_tile_ni_14_9_to_router_14_9_req; -floo_rsp_t router_14_9_to_magia_tile_ni_14_9_rsp; - -floo_req_t magia_tile_ni_14_10_to_router_14_10_req; -floo_rsp_t router_14_10_to_magia_tile_ni_14_10_rsp; - -floo_req_t magia_tile_ni_14_11_to_router_14_11_req; -floo_rsp_t router_14_11_to_magia_tile_ni_14_11_rsp; - -floo_req_t magia_tile_ni_14_12_to_router_14_12_req; -floo_rsp_t router_14_12_to_magia_tile_ni_14_12_rsp; - -floo_req_t magia_tile_ni_14_13_to_router_14_13_req; -floo_rsp_t router_14_13_to_magia_tile_ni_14_13_rsp; - -floo_req_t magia_tile_ni_14_14_to_router_14_14_req; -floo_rsp_t router_14_14_to_magia_tile_ni_14_14_rsp; - -floo_req_t magia_tile_ni_14_15_to_router_14_15_req; -floo_rsp_t router_14_15_to_magia_tile_ni_14_15_rsp; - -floo_req_t magia_tile_ni_14_16_to_router_14_16_req; -floo_rsp_t router_14_16_to_magia_tile_ni_14_16_rsp; - -floo_req_t magia_tile_ni_14_17_to_router_14_17_req; -floo_rsp_t router_14_17_to_magia_tile_ni_14_17_rsp; - -floo_req_t magia_tile_ni_14_18_to_router_14_18_req; -floo_rsp_t router_14_18_to_magia_tile_ni_14_18_rsp; - -floo_req_t magia_tile_ni_14_19_to_router_14_19_req; -floo_rsp_t router_14_19_to_magia_tile_ni_14_19_rsp; - -floo_req_t magia_tile_ni_14_20_to_router_14_20_req; -floo_rsp_t router_14_20_to_magia_tile_ni_14_20_rsp; - -floo_req_t magia_tile_ni_14_21_to_router_14_21_req; -floo_rsp_t router_14_21_to_magia_tile_ni_14_21_rsp; - -floo_req_t magia_tile_ni_14_22_to_router_14_22_req; -floo_rsp_t router_14_22_to_magia_tile_ni_14_22_rsp; - -floo_req_t magia_tile_ni_14_23_to_router_14_23_req; -floo_rsp_t router_14_23_to_magia_tile_ni_14_23_rsp; - -floo_req_t magia_tile_ni_14_24_to_router_14_24_req; -floo_rsp_t router_14_24_to_magia_tile_ni_14_24_rsp; - -floo_req_t magia_tile_ni_14_25_to_router_14_25_req; -floo_rsp_t router_14_25_to_magia_tile_ni_14_25_rsp; - -floo_req_t magia_tile_ni_14_26_to_router_14_26_req; -floo_rsp_t router_14_26_to_magia_tile_ni_14_26_rsp; - -floo_req_t magia_tile_ni_14_27_to_router_14_27_req; -floo_rsp_t router_14_27_to_magia_tile_ni_14_27_rsp; - -floo_req_t magia_tile_ni_14_28_to_router_14_28_req; -floo_rsp_t router_14_28_to_magia_tile_ni_14_28_rsp; - -floo_req_t magia_tile_ni_14_29_to_router_14_29_req; -floo_rsp_t router_14_29_to_magia_tile_ni_14_29_rsp; - -floo_req_t magia_tile_ni_14_30_to_router_14_30_req; -floo_rsp_t router_14_30_to_magia_tile_ni_14_30_rsp; - -floo_req_t magia_tile_ni_14_31_to_router_14_31_req; -floo_rsp_t router_14_31_to_magia_tile_ni_14_31_rsp; - -floo_req_t magia_tile_ni_15_0_to_router_15_0_req; -floo_rsp_t router_15_0_to_magia_tile_ni_15_0_rsp; - -floo_req_t magia_tile_ni_15_1_to_router_15_1_req; -floo_rsp_t router_15_1_to_magia_tile_ni_15_1_rsp; - -floo_req_t magia_tile_ni_15_2_to_router_15_2_req; -floo_rsp_t router_15_2_to_magia_tile_ni_15_2_rsp; - -floo_req_t magia_tile_ni_15_3_to_router_15_3_req; -floo_rsp_t router_15_3_to_magia_tile_ni_15_3_rsp; - -floo_req_t magia_tile_ni_15_4_to_router_15_4_req; -floo_rsp_t router_15_4_to_magia_tile_ni_15_4_rsp; - -floo_req_t magia_tile_ni_15_5_to_router_15_5_req; -floo_rsp_t router_15_5_to_magia_tile_ni_15_5_rsp; - -floo_req_t magia_tile_ni_15_6_to_router_15_6_req; -floo_rsp_t router_15_6_to_magia_tile_ni_15_6_rsp; - -floo_req_t magia_tile_ni_15_7_to_router_15_7_req; -floo_rsp_t router_15_7_to_magia_tile_ni_15_7_rsp; - -floo_req_t magia_tile_ni_15_8_to_router_15_8_req; -floo_rsp_t router_15_8_to_magia_tile_ni_15_8_rsp; - -floo_req_t magia_tile_ni_15_9_to_router_15_9_req; -floo_rsp_t router_15_9_to_magia_tile_ni_15_9_rsp; - -floo_req_t magia_tile_ni_15_10_to_router_15_10_req; -floo_rsp_t router_15_10_to_magia_tile_ni_15_10_rsp; - -floo_req_t magia_tile_ni_15_11_to_router_15_11_req; -floo_rsp_t router_15_11_to_magia_tile_ni_15_11_rsp; - -floo_req_t magia_tile_ni_15_12_to_router_15_12_req; -floo_rsp_t router_15_12_to_magia_tile_ni_15_12_rsp; - -floo_req_t magia_tile_ni_15_13_to_router_15_13_req; -floo_rsp_t router_15_13_to_magia_tile_ni_15_13_rsp; - -floo_req_t magia_tile_ni_15_14_to_router_15_14_req; -floo_rsp_t router_15_14_to_magia_tile_ni_15_14_rsp; - -floo_req_t magia_tile_ni_15_15_to_router_15_15_req; -floo_rsp_t router_15_15_to_magia_tile_ni_15_15_rsp; - -floo_req_t magia_tile_ni_15_16_to_router_15_16_req; -floo_rsp_t router_15_16_to_magia_tile_ni_15_16_rsp; - -floo_req_t magia_tile_ni_15_17_to_router_15_17_req; -floo_rsp_t router_15_17_to_magia_tile_ni_15_17_rsp; - -floo_req_t magia_tile_ni_15_18_to_router_15_18_req; -floo_rsp_t router_15_18_to_magia_tile_ni_15_18_rsp; - -floo_req_t magia_tile_ni_15_19_to_router_15_19_req; -floo_rsp_t router_15_19_to_magia_tile_ni_15_19_rsp; - -floo_req_t magia_tile_ni_15_20_to_router_15_20_req; -floo_rsp_t router_15_20_to_magia_tile_ni_15_20_rsp; - -floo_req_t magia_tile_ni_15_21_to_router_15_21_req; -floo_rsp_t router_15_21_to_magia_tile_ni_15_21_rsp; - -floo_req_t magia_tile_ni_15_22_to_router_15_22_req; -floo_rsp_t router_15_22_to_magia_tile_ni_15_22_rsp; - -floo_req_t magia_tile_ni_15_23_to_router_15_23_req; -floo_rsp_t router_15_23_to_magia_tile_ni_15_23_rsp; - -floo_req_t magia_tile_ni_15_24_to_router_15_24_req; -floo_rsp_t router_15_24_to_magia_tile_ni_15_24_rsp; - -floo_req_t magia_tile_ni_15_25_to_router_15_25_req; -floo_rsp_t router_15_25_to_magia_tile_ni_15_25_rsp; - -floo_req_t magia_tile_ni_15_26_to_router_15_26_req; -floo_rsp_t router_15_26_to_magia_tile_ni_15_26_rsp; - -floo_req_t magia_tile_ni_15_27_to_router_15_27_req; -floo_rsp_t router_15_27_to_magia_tile_ni_15_27_rsp; - -floo_req_t magia_tile_ni_15_28_to_router_15_28_req; -floo_rsp_t router_15_28_to_magia_tile_ni_15_28_rsp; - -floo_req_t magia_tile_ni_15_29_to_router_15_29_req; -floo_rsp_t router_15_29_to_magia_tile_ni_15_29_rsp; - -floo_req_t magia_tile_ni_15_30_to_router_15_30_req; -floo_rsp_t router_15_30_to_magia_tile_ni_15_30_rsp; - -floo_req_t magia_tile_ni_15_31_to_router_15_31_req; -floo_rsp_t router_15_31_to_magia_tile_ni_15_31_rsp; - -floo_req_t magia_tile_ni_16_0_to_router_16_0_req; -floo_rsp_t router_16_0_to_magia_tile_ni_16_0_rsp; - -floo_req_t magia_tile_ni_16_1_to_router_16_1_req; -floo_rsp_t router_16_1_to_magia_tile_ni_16_1_rsp; - -floo_req_t magia_tile_ni_16_2_to_router_16_2_req; -floo_rsp_t router_16_2_to_magia_tile_ni_16_2_rsp; - -floo_req_t magia_tile_ni_16_3_to_router_16_3_req; -floo_rsp_t router_16_3_to_magia_tile_ni_16_3_rsp; - -floo_req_t magia_tile_ni_16_4_to_router_16_4_req; -floo_rsp_t router_16_4_to_magia_tile_ni_16_4_rsp; - -floo_req_t magia_tile_ni_16_5_to_router_16_5_req; -floo_rsp_t router_16_5_to_magia_tile_ni_16_5_rsp; - -floo_req_t magia_tile_ni_16_6_to_router_16_6_req; -floo_rsp_t router_16_6_to_magia_tile_ni_16_6_rsp; - -floo_req_t magia_tile_ni_16_7_to_router_16_7_req; -floo_rsp_t router_16_7_to_magia_tile_ni_16_7_rsp; - -floo_req_t magia_tile_ni_16_8_to_router_16_8_req; -floo_rsp_t router_16_8_to_magia_tile_ni_16_8_rsp; - -floo_req_t magia_tile_ni_16_9_to_router_16_9_req; -floo_rsp_t router_16_9_to_magia_tile_ni_16_9_rsp; - -floo_req_t magia_tile_ni_16_10_to_router_16_10_req; -floo_rsp_t router_16_10_to_magia_tile_ni_16_10_rsp; - -floo_req_t magia_tile_ni_16_11_to_router_16_11_req; -floo_rsp_t router_16_11_to_magia_tile_ni_16_11_rsp; - -floo_req_t magia_tile_ni_16_12_to_router_16_12_req; -floo_rsp_t router_16_12_to_magia_tile_ni_16_12_rsp; - -floo_req_t magia_tile_ni_16_13_to_router_16_13_req; -floo_rsp_t router_16_13_to_magia_tile_ni_16_13_rsp; - -floo_req_t magia_tile_ni_16_14_to_router_16_14_req; -floo_rsp_t router_16_14_to_magia_tile_ni_16_14_rsp; - -floo_req_t magia_tile_ni_16_15_to_router_16_15_req; -floo_rsp_t router_16_15_to_magia_tile_ni_16_15_rsp; - -floo_req_t magia_tile_ni_16_16_to_router_16_16_req; -floo_rsp_t router_16_16_to_magia_tile_ni_16_16_rsp; - -floo_req_t magia_tile_ni_16_17_to_router_16_17_req; -floo_rsp_t router_16_17_to_magia_tile_ni_16_17_rsp; - -floo_req_t magia_tile_ni_16_18_to_router_16_18_req; -floo_rsp_t router_16_18_to_magia_tile_ni_16_18_rsp; - -floo_req_t magia_tile_ni_16_19_to_router_16_19_req; -floo_rsp_t router_16_19_to_magia_tile_ni_16_19_rsp; - -floo_req_t magia_tile_ni_16_20_to_router_16_20_req; -floo_rsp_t router_16_20_to_magia_tile_ni_16_20_rsp; - -floo_req_t magia_tile_ni_16_21_to_router_16_21_req; -floo_rsp_t router_16_21_to_magia_tile_ni_16_21_rsp; - -floo_req_t magia_tile_ni_16_22_to_router_16_22_req; -floo_rsp_t router_16_22_to_magia_tile_ni_16_22_rsp; - -floo_req_t magia_tile_ni_16_23_to_router_16_23_req; -floo_rsp_t router_16_23_to_magia_tile_ni_16_23_rsp; - -floo_req_t magia_tile_ni_16_24_to_router_16_24_req; -floo_rsp_t router_16_24_to_magia_tile_ni_16_24_rsp; - -floo_req_t magia_tile_ni_16_25_to_router_16_25_req; -floo_rsp_t router_16_25_to_magia_tile_ni_16_25_rsp; - -floo_req_t magia_tile_ni_16_26_to_router_16_26_req; -floo_rsp_t router_16_26_to_magia_tile_ni_16_26_rsp; - -floo_req_t magia_tile_ni_16_27_to_router_16_27_req; -floo_rsp_t router_16_27_to_magia_tile_ni_16_27_rsp; - -floo_req_t magia_tile_ni_16_28_to_router_16_28_req; -floo_rsp_t router_16_28_to_magia_tile_ni_16_28_rsp; - -floo_req_t magia_tile_ni_16_29_to_router_16_29_req; -floo_rsp_t router_16_29_to_magia_tile_ni_16_29_rsp; - -floo_req_t magia_tile_ni_16_30_to_router_16_30_req; -floo_rsp_t router_16_30_to_magia_tile_ni_16_30_rsp; - -floo_req_t magia_tile_ni_16_31_to_router_16_31_req; -floo_rsp_t router_16_31_to_magia_tile_ni_16_31_rsp; - -floo_req_t magia_tile_ni_17_0_to_router_17_0_req; -floo_rsp_t router_17_0_to_magia_tile_ni_17_0_rsp; - -floo_req_t magia_tile_ni_17_1_to_router_17_1_req; -floo_rsp_t router_17_1_to_magia_tile_ni_17_1_rsp; - -floo_req_t magia_tile_ni_17_2_to_router_17_2_req; -floo_rsp_t router_17_2_to_magia_tile_ni_17_2_rsp; - -floo_req_t magia_tile_ni_17_3_to_router_17_3_req; -floo_rsp_t router_17_3_to_magia_tile_ni_17_3_rsp; - -floo_req_t magia_tile_ni_17_4_to_router_17_4_req; -floo_rsp_t router_17_4_to_magia_tile_ni_17_4_rsp; - -floo_req_t magia_tile_ni_17_5_to_router_17_5_req; -floo_rsp_t router_17_5_to_magia_tile_ni_17_5_rsp; - -floo_req_t magia_tile_ni_17_6_to_router_17_6_req; -floo_rsp_t router_17_6_to_magia_tile_ni_17_6_rsp; - -floo_req_t magia_tile_ni_17_7_to_router_17_7_req; -floo_rsp_t router_17_7_to_magia_tile_ni_17_7_rsp; - -floo_req_t magia_tile_ni_17_8_to_router_17_8_req; -floo_rsp_t router_17_8_to_magia_tile_ni_17_8_rsp; - -floo_req_t magia_tile_ni_17_9_to_router_17_9_req; -floo_rsp_t router_17_9_to_magia_tile_ni_17_9_rsp; - -floo_req_t magia_tile_ni_17_10_to_router_17_10_req; -floo_rsp_t router_17_10_to_magia_tile_ni_17_10_rsp; - -floo_req_t magia_tile_ni_17_11_to_router_17_11_req; -floo_rsp_t router_17_11_to_magia_tile_ni_17_11_rsp; - -floo_req_t magia_tile_ni_17_12_to_router_17_12_req; -floo_rsp_t router_17_12_to_magia_tile_ni_17_12_rsp; - -floo_req_t magia_tile_ni_17_13_to_router_17_13_req; -floo_rsp_t router_17_13_to_magia_tile_ni_17_13_rsp; - -floo_req_t magia_tile_ni_17_14_to_router_17_14_req; -floo_rsp_t router_17_14_to_magia_tile_ni_17_14_rsp; - -floo_req_t magia_tile_ni_17_15_to_router_17_15_req; -floo_rsp_t router_17_15_to_magia_tile_ni_17_15_rsp; - -floo_req_t magia_tile_ni_17_16_to_router_17_16_req; -floo_rsp_t router_17_16_to_magia_tile_ni_17_16_rsp; - -floo_req_t magia_tile_ni_17_17_to_router_17_17_req; -floo_rsp_t router_17_17_to_magia_tile_ni_17_17_rsp; - -floo_req_t magia_tile_ni_17_18_to_router_17_18_req; -floo_rsp_t router_17_18_to_magia_tile_ni_17_18_rsp; - -floo_req_t magia_tile_ni_17_19_to_router_17_19_req; -floo_rsp_t router_17_19_to_magia_tile_ni_17_19_rsp; - -floo_req_t magia_tile_ni_17_20_to_router_17_20_req; -floo_rsp_t router_17_20_to_magia_tile_ni_17_20_rsp; - -floo_req_t magia_tile_ni_17_21_to_router_17_21_req; -floo_rsp_t router_17_21_to_magia_tile_ni_17_21_rsp; - -floo_req_t magia_tile_ni_17_22_to_router_17_22_req; -floo_rsp_t router_17_22_to_magia_tile_ni_17_22_rsp; - -floo_req_t magia_tile_ni_17_23_to_router_17_23_req; -floo_rsp_t router_17_23_to_magia_tile_ni_17_23_rsp; - -floo_req_t magia_tile_ni_17_24_to_router_17_24_req; -floo_rsp_t router_17_24_to_magia_tile_ni_17_24_rsp; - -floo_req_t magia_tile_ni_17_25_to_router_17_25_req; -floo_rsp_t router_17_25_to_magia_tile_ni_17_25_rsp; - -floo_req_t magia_tile_ni_17_26_to_router_17_26_req; -floo_rsp_t router_17_26_to_magia_tile_ni_17_26_rsp; - -floo_req_t magia_tile_ni_17_27_to_router_17_27_req; -floo_rsp_t router_17_27_to_magia_tile_ni_17_27_rsp; - -floo_req_t magia_tile_ni_17_28_to_router_17_28_req; -floo_rsp_t router_17_28_to_magia_tile_ni_17_28_rsp; - -floo_req_t magia_tile_ni_17_29_to_router_17_29_req; -floo_rsp_t router_17_29_to_magia_tile_ni_17_29_rsp; - -floo_req_t magia_tile_ni_17_30_to_router_17_30_req; -floo_rsp_t router_17_30_to_magia_tile_ni_17_30_rsp; - -floo_req_t magia_tile_ni_17_31_to_router_17_31_req; -floo_rsp_t router_17_31_to_magia_tile_ni_17_31_rsp; - -floo_req_t magia_tile_ni_18_0_to_router_18_0_req; -floo_rsp_t router_18_0_to_magia_tile_ni_18_0_rsp; - -floo_req_t magia_tile_ni_18_1_to_router_18_1_req; -floo_rsp_t router_18_1_to_magia_tile_ni_18_1_rsp; - -floo_req_t magia_tile_ni_18_2_to_router_18_2_req; -floo_rsp_t router_18_2_to_magia_tile_ni_18_2_rsp; - -floo_req_t magia_tile_ni_18_3_to_router_18_3_req; -floo_rsp_t router_18_3_to_magia_tile_ni_18_3_rsp; - -floo_req_t magia_tile_ni_18_4_to_router_18_4_req; -floo_rsp_t router_18_4_to_magia_tile_ni_18_4_rsp; - -floo_req_t magia_tile_ni_18_5_to_router_18_5_req; -floo_rsp_t router_18_5_to_magia_tile_ni_18_5_rsp; - -floo_req_t magia_tile_ni_18_6_to_router_18_6_req; -floo_rsp_t router_18_6_to_magia_tile_ni_18_6_rsp; - -floo_req_t magia_tile_ni_18_7_to_router_18_7_req; -floo_rsp_t router_18_7_to_magia_tile_ni_18_7_rsp; - -floo_req_t magia_tile_ni_18_8_to_router_18_8_req; -floo_rsp_t router_18_8_to_magia_tile_ni_18_8_rsp; - -floo_req_t magia_tile_ni_18_9_to_router_18_9_req; -floo_rsp_t router_18_9_to_magia_tile_ni_18_9_rsp; - -floo_req_t magia_tile_ni_18_10_to_router_18_10_req; -floo_rsp_t router_18_10_to_magia_tile_ni_18_10_rsp; - -floo_req_t magia_tile_ni_18_11_to_router_18_11_req; -floo_rsp_t router_18_11_to_magia_tile_ni_18_11_rsp; - -floo_req_t magia_tile_ni_18_12_to_router_18_12_req; -floo_rsp_t router_18_12_to_magia_tile_ni_18_12_rsp; - -floo_req_t magia_tile_ni_18_13_to_router_18_13_req; -floo_rsp_t router_18_13_to_magia_tile_ni_18_13_rsp; - -floo_req_t magia_tile_ni_18_14_to_router_18_14_req; -floo_rsp_t router_18_14_to_magia_tile_ni_18_14_rsp; - -floo_req_t magia_tile_ni_18_15_to_router_18_15_req; -floo_rsp_t router_18_15_to_magia_tile_ni_18_15_rsp; - -floo_req_t magia_tile_ni_18_16_to_router_18_16_req; -floo_rsp_t router_18_16_to_magia_tile_ni_18_16_rsp; - -floo_req_t magia_tile_ni_18_17_to_router_18_17_req; -floo_rsp_t router_18_17_to_magia_tile_ni_18_17_rsp; - -floo_req_t magia_tile_ni_18_18_to_router_18_18_req; -floo_rsp_t router_18_18_to_magia_tile_ni_18_18_rsp; - -floo_req_t magia_tile_ni_18_19_to_router_18_19_req; -floo_rsp_t router_18_19_to_magia_tile_ni_18_19_rsp; - -floo_req_t magia_tile_ni_18_20_to_router_18_20_req; -floo_rsp_t router_18_20_to_magia_tile_ni_18_20_rsp; - -floo_req_t magia_tile_ni_18_21_to_router_18_21_req; -floo_rsp_t router_18_21_to_magia_tile_ni_18_21_rsp; - -floo_req_t magia_tile_ni_18_22_to_router_18_22_req; -floo_rsp_t router_18_22_to_magia_tile_ni_18_22_rsp; - -floo_req_t magia_tile_ni_18_23_to_router_18_23_req; -floo_rsp_t router_18_23_to_magia_tile_ni_18_23_rsp; - -floo_req_t magia_tile_ni_18_24_to_router_18_24_req; -floo_rsp_t router_18_24_to_magia_tile_ni_18_24_rsp; - -floo_req_t magia_tile_ni_18_25_to_router_18_25_req; -floo_rsp_t router_18_25_to_magia_tile_ni_18_25_rsp; - -floo_req_t magia_tile_ni_18_26_to_router_18_26_req; -floo_rsp_t router_18_26_to_magia_tile_ni_18_26_rsp; - -floo_req_t magia_tile_ni_18_27_to_router_18_27_req; -floo_rsp_t router_18_27_to_magia_tile_ni_18_27_rsp; - -floo_req_t magia_tile_ni_18_28_to_router_18_28_req; -floo_rsp_t router_18_28_to_magia_tile_ni_18_28_rsp; - -floo_req_t magia_tile_ni_18_29_to_router_18_29_req; -floo_rsp_t router_18_29_to_magia_tile_ni_18_29_rsp; - -floo_req_t magia_tile_ni_18_30_to_router_18_30_req; -floo_rsp_t router_18_30_to_magia_tile_ni_18_30_rsp; - -floo_req_t magia_tile_ni_18_31_to_router_18_31_req; -floo_rsp_t router_18_31_to_magia_tile_ni_18_31_rsp; - -floo_req_t magia_tile_ni_19_0_to_router_19_0_req; -floo_rsp_t router_19_0_to_magia_tile_ni_19_0_rsp; - -floo_req_t magia_tile_ni_19_1_to_router_19_1_req; -floo_rsp_t router_19_1_to_magia_tile_ni_19_1_rsp; - -floo_req_t magia_tile_ni_19_2_to_router_19_2_req; -floo_rsp_t router_19_2_to_magia_tile_ni_19_2_rsp; - -floo_req_t magia_tile_ni_19_3_to_router_19_3_req; -floo_rsp_t router_19_3_to_magia_tile_ni_19_3_rsp; - -floo_req_t magia_tile_ni_19_4_to_router_19_4_req; -floo_rsp_t router_19_4_to_magia_tile_ni_19_4_rsp; - -floo_req_t magia_tile_ni_19_5_to_router_19_5_req; -floo_rsp_t router_19_5_to_magia_tile_ni_19_5_rsp; - -floo_req_t magia_tile_ni_19_6_to_router_19_6_req; -floo_rsp_t router_19_6_to_magia_tile_ni_19_6_rsp; - -floo_req_t magia_tile_ni_19_7_to_router_19_7_req; -floo_rsp_t router_19_7_to_magia_tile_ni_19_7_rsp; - -floo_req_t magia_tile_ni_19_8_to_router_19_8_req; -floo_rsp_t router_19_8_to_magia_tile_ni_19_8_rsp; - -floo_req_t magia_tile_ni_19_9_to_router_19_9_req; -floo_rsp_t router_19_9_to_magia_tile_ni_19_9_rsp; - -floo_req_t magia_tile_ni_19_10_to_router_19_10_req; -floo_rsp_t router_19_10_to_magia_tile_ni_19_10_rsp; - -floo_req_t magia_tile_ni_19_11_to_router_19_11_req; -floo_rsp_t router_19_11_to_magia_tile_ni_19_11_rsp; - -floo_req_t magia_tile_ni_19_12_to_router_19_12_req; -floo_rsp_t router_19_12_to_magia_tile_ni_19_12_rsp; - -floo_req_t magia_tile_ni_19_13_to_router_19_13_req; -floo_rsp_t router_19_13_to_magia_tile_ni_19_13_rsp; - -floo_req_t magia_tile_ni_19_14_to_router_19_14_req; -floo_rsp_t router_19_14_to_magia_tile_ni_19_14_rsp; - -floo_req_t magia_tile_ni_19_15_to_router_19_15_req; -floo_rsp_t router_19_15_to_magia_tile_ni_19_15_rsp; - -floo_req_t magia_tile_ni_19_16_to_router_19_16_req; -floo_rsp_t router_19_16_to_magia_tile_ni_19_16_rsp; - -floo_req_t magia_tile_ni_19_17_to_router_19_17_req; -floo_rsp_t router_19_17_to_magia_tile_ni_19_17_rsp; - -floo_req_t magia_tile_ni_19_18_to_router_19_18_req; -floo_rsp_t router_19_18_to_magia_tile_ni_19_18_rsp; - -floo_req_t magia_tile_ni_19_19_to_router_19_19_req; -floo_rsp_t router_19_19_to_magia_tile_ni_19_19_rsp; - -floo_req_t magia_tile_ni_19_20_to_router_19_20_req; -floo_rsp_t router_19_20_to_magia_tile_ni_19_20_rsp; - -floo_req_t magia_tile_ni_19_21_to_router_19_21_req; -floo_rsp_t router_19_21_to_magia_tile_ni_19_21_rsp; - -floo_req_t magia_tile_ni_19_22_to_router_19_22_req; -floo_rsp_t router_19_22_to_magia_tile_ni_19_22_rsp; - -floo_req_t magia_tile_ni_19_23_to_router_19_23_req; -floo_rsp_t router_19_23_to_magia_tile_ni_19_23_rsp; - -floo_req_t magia_tile_ni_19_24_to_router_19_24_req; -floo_rsp_t router_19_24_to_magia_tile_ni_19_24_rsp; - -floo_req_t magia_tile_ni_19_25_to_router_19_25_req; -floo_rsp_t router_19_25_to_magia_tile_ni_19_25_rsp; - -floo_req_t magia_tile_ni_19_26_to_router_19_26_req; -floo_rsp_t router_19_26_to_magia_tile_ni_19_26_rsp; - -floo_req_t magia_tile_ni_19_27_to_router_19_27_req; -floo_rsp_t router_19_27_to_magia_tile_ni_19_27_rsp; - -floo_req_t magia_tile_ni_19_28_to_router_19_28_req; -floo_rsp_t router_19_28_to_magia_tile_ni_19_28_rsp; - -floo_req_t magia_tile_ni_19_29_to_router_19_29_req; -floo_rsp_t router_19_29_to_magia_tile_ni_19_29_rsp; - -floo_req_t magia_tile_ni_19_30_to_router_19_30_req; -floo_rsp_t router_19_30_to_magia_tile_ni_19_30_rsp; - -floo_req_t magia_tile_ni_19_31_to_router_19_31_req; -floo_rsp_t router_19_31_to_magia_tile_ni_19_31_rsp; - -floo_req_t magia_tile_ni_20_0_to_router_20_0_req; -floo_rsp_t router_20_0_to_magia_tile_ni_20_0_rsp; - -floo_req_t magia_tile_ni_20_1_to_router_20_1_req; -floo_rsp_t router_20_1_to_magia_tile_ni_20_1_rsp; - -floo_req_t magia_tile_ni_20_2_to_router_20_2_req; -floo_rsp_t router_20_2_to_magia_tile_ni_20_2_rsp; - -floo_req_t magia_tile_ni_20_3_to_router_20_3_req; -floo_rsp_t router_20_3_to_magia_tile_ni_20_3_rsp; - -floo_req_t magia_tile_ni_20_4_to_router_20_4_req; -floo_rsp_t router_20_4_to_magia_tile_ni_20_4_rsp; - -floo_req_t magia_tile_ni_20_5_to_router_20_5_req; -floo_rsp_t router_20_5_to_magia_tile_ni_20_5_rsp; - -floo_req_t magia_tile_ni_20_6_to_router_20_6_req; -floo_rsp_t router_20_6_to_magia_tile_ni_20_6_rsp; - -floo_req_t magia_tile_ni_20_7_to_router_20_7_req; -floo_rsp_t router_20_7_to_magia_tile_ni_20_7_rsp; - -floo_req_t magia_tile_ni_20_8_to_router_20_8_req; -floo_rsp_t router_20_8_to_magia_tile_ni_20_8_rsp; - -floo_req_t magia_tile_ni_20_9_to_router_20_9_req; -floo_rsp_t router_20_9_to_magia_tile_ni_20_9_rsp; - -floo_req_t magia_tile_ni_20_10_to_router_20_10_req; -floo_rsp_t router_20_10_to_magia_tile_ni_20_10_rsp; - -floo_req_t magia_tile_ni_20_11_to_router_20_11_req; -floo_rsp_t router_20_11_to_magia_tile_ni_20_11_rsp; - -floo_req_t magia_tile_ni_20_12_to_router_20_12_req; -floo_rsp_t router_20_12_to_magia_tile_ni_20_12_rsp; - -floo_req_t magia_tile_ni_20_13_to_router_20_13_req; -floo_rsp_t router_20_13_to_magia_tile_ni_20_13_rsp; - -floo_req_t magia_tile_ni_20_14_to_router_20_14_req; -floo_rsp_t router_20_14_to_magia_tile_ni_20_14_rsp; - -floo_req_t magia_tile_ni_20_15_to_router_20_15_req; -floo_rsp_t router_20_15_to_magia_tile_ni_20_15_rsp; - -floo_req_t magia_tile_ni_20_16_to_router_20_16_req; -floo_rsp_t router_20_16_to_magia_tile_ni_20_16_rsp; - -floo_req_t magia_tile_ni_20_17_to_router_20_17_req; -floo_rsp_t router_20_17_to_magia_tile_ni_20_17_rsp; - -floo_req_t magia_tile_ni_20_18_to_router_20_18_req; -floo_rsp_t router_20_18_to_magia_tile_ni_20_18_rsp; - -floo_req_t magia_tile_ni_20_19_to_router_20_19_req; -floo_rsp_t router_20_19_to_magia_tile_ni_20_19_rsp; - -floo_req_t magia_tile_ni_20_20_to_router_20_20_req; -floo_rsp_t router_20_20_to_magia_tile_ni_20_20_rsp; - -floo_req_t magia_tile_ni_20_21_to_router_20_21_req; -floo_rsp_t router_20_21_to_magia_tile_ni_20_21_rsp; - -floo_req_t magia_tile_ni_20_22_to_router_20_22_req; -floo_rsp_t router_20_22_to_magia_tile_ni_20_22_rsp; - -floo_req_t magia_tile_ni_20_23_to_router_20_23_req; -floo_rsp_t router_20_23_to_magia_tile_ni_20_23_rsp; - -floo_req_t magia_tile_ni_20_24_to_router_20_24_req; -floo_rsp_t router_20_24_to_magia_tile_ni_20_24_rsp; - -floo_req_t magia_tile_ni_20_25_to_router_20_25_req; -floo_rsp_t router_20_25_to_magia_tile_ni_20_25_rsp; - -floo_req_t magia_tile_ni_20_26_to_router_20_26_req; -floo_rsp_t router_20_26_to_magia_tile_ni_20_26_rsp; - -floo_req_t magia_tile_ni_20_27_to_router_20_27_req; -floo_rsp_t router_20_27_to_magia_tile_ni_20_27_rsp; - -floo_req_t magia_tile_ni_20_28_to_router_20_28_req; -floo_rsp_t router_20_28_to_magia_tile_ni_20_28_rsp; - -floo_req_t magia_tile_ni_20_29_to_router_20_29_req; -floo_rsp_t router_20_29_to_magia_tile_ni_20_29_rsp; - -floo_req_t magia_tile_ni_20_30_to_router_20_30_req; -floo_rsp_t router_20_30_to_magia_tile_ni_20_30_rsp; - -floo_req_t magia_tile_ni_20_31_to_router_20_31_req; -floo_rsp_t router_20_31_to_magia_tile_ni_20_31_rsp; - -floo_req_t magia_tile_ni_21_0_to_router_21_0_req; -floo_rsp_t router_21_0_to_magia_tile_ni_21_0_rsp; - -floo_req_t magia_tile_ni_21_1_to_router_21_1_req; -floo_rsp_t router_21_1_to_magia_tile_ni_21_1_rsp; - -floo_req_t magia_tile_ni_21_2_to_router_21_2_req; -floo_rsp_t router_21_2_to_magia_tile_ni_21_2_rsp; - -floo_req_t magia_tile_ni_21_3_to_router_21_3_req; -floo_rsp_t router_21_3_to_magia_tile_ni_21_3_rsp; - -floo_req_t magia_tile_ni_21_4_to_router_21_4_req; -floo_rsp_t router_21_4_to_magia_tile_ni_21_4_rsp; - -floo_req_t magia_tile_ni_21_5_to_router_21_5_req; -floo_rsp_t router_21_5_to_magia_tile_ni_21_5_rsp; - -floo_req_t magia_tile_ni_21_6_to_router_21_6_req; -floo_rsp_t router_21_6_to_magia_tile_ni_21_6_rsp; - -floo_req_t magia_tile_ni_21_7_to_router_21_7_req; -floo_rsp_t router_21_7_to_magia_tile_ni_21_7_rsp; - -floo_req_t magia_tile_ni_21_8_to_router_21_8_req; -floo_rsp_t router_21_8_to_magia_tile_ni_21_8_rsp; - -floo_req_t magia_tile_ni_21_9_to_router_21_9_req; -floo_rsp_t router_21_9_to_magia_tile_ni_21_9_rsp; - -floo_req_t magia_tile_ni_21_10_to_router_21_10_req; -floo_rsp_t router_21_10_to_magia_tile_ni_21_10_rsp; - -floo_req_t magia_tile_ni_21_11_to_router_21_11_req; -floo_rsp_t router_21_11_to_magia_tile_ni_21_11_rsp; - -floo_req_t magia_tile_ni_21_12_to_router_21_12_req; -floo_rsp_t router_21_12_to_magia_tile_ni_21_12_rsp; - -floo_req_t magia_tile_ni_21_13_to_router_21_13_req; -floo_rsp_t router_21_13_to_magia_tile_ni_21_13_rsp; - -floo_req_t magia_tile_ni_21_14_to_router_21_14_req; -floo_rsp_t router_21_14_to_magia_tile_ni_21_14_rsp; - -floo_req_t magia_tile_ni_21_15_to_router_21_15_req; -floo_rsp_t router_21_15_to_magia_tile_ni_21_15_rsp; - -floo_req_t magia_tile_ni_21_16_to_router_21_16_req; -floo_rsp_t router_21_16_to_magia_tile_ni_21_16_rsp; - -floo_req_t magia_tile_ni_21_17_to_router_21_17_req; -floo_rsp_t router_21_17_to_magia_tile_ni_21_17_rsp; - -floo_req_t magia_tile_ni_21_18_to_router_21_18_req; -floo_rsp_t router_21_18_to_magia_tile_ni_21_18_rsp; - -floo_req_t magia_tile_ni_21_19_to_router_21_19_req; -floo_rsp_t router_21_19_to_magia_tile_ni_21_19_rsp; - -floo_req_t magia_tile_ni_21_20_to_router_21_20_req; -floo_rsp_t router_21_20_to_magia_tile_ni_21_20_rsp; - -floo_req_t magia_tile_ni_21_21_to_router_21_21_req; -floo_rsp_t router_21_21_to_magia_tile_ni_21_21_rsp; - -floo_req_t magia_tile_ni_21_22_to_router_21_22_req; -floo_rsp_t router_21_22_to_magia_tile_ni_21_22_rsp; - -floo_req_t magia_tile_ni_21_23_to_router_21_23_req; -floo_rsp_t router_21_23_to_magia_tile_ni_21_23_rsp; - -floo_req_t magia_tile_ni_21_24_to_router_21_24_req; -floo_rsp_t router_21_24_to_magia_tile_ni_21_24_rsp; - -floo_req_t magia_tile_ni_21_25_to_router_21_25_req; -floo_rsp_t router_21_25_to_magia_tile_ni_21_25_rsp; - -floo_req_t magia_tile_ni_21_26_to_router_21_26_req; -floo_rsp_t router_21_26_to_magia_tile_ni_21_26_rsp; - -floo_req_t magia_tile_ni_21_27_to_router_21_27_req; -floo_rsp_t router_21_27_to_magia_tile_ni_21_27_rsp; - -floo_req_t magia_tile_ni_21_28_to_router_21_28_req; -floo_rsp_t router_21_28_to_magia_tile_ni_21_28_rsp; - -floo_req_t magia_tile_ni_21_29_to_router_21_29_req; -floo_rsp_t router_21_29_to_magia_tile_ni_21_29_rsp; - -floo_req_t magia_tile_ni_21_30_to_router_21_30_req; -floo_rsp_t router_21_30_to_magia_tile_ni_21_30_rsp; - -floo_req_t magia_tile_ni_21_31_to_router_21_31_req; -floo_rsp_t router_21_31_to_magia_tile_ni_21_31_rsp; - -floo_req_t magia_tile_ni_22_0_to_router_22_0_req; -floo_rsp_t router_22_0_to_magia_tile_ni_22_0_rsp; - -floo_req_t magia_tile_ni_22_1_to_router_22_1_req; -floo_rsp_t router_22_1_to_magia_tile_ni_22_1_rsp; - -floo_req_t magia_tile_ni_22_2_to_router_22_2_req; -floo_rsp_t router_22_2_to_magia_tile_ni_22_2_rsp; - -floo_req_t magia_tile_ni_22_3_to_router_22_3_req; -floo_rsp_t router_22_3_to_magia_tile_ni_22_3_rsp; - -floo_req_t magia_tile_ni_22_4_to_router_22_4_req; -floo_rsp_t router_22_4_to_magia_tile_ni_22_4_rsp; - -floo_req_t magia_tile_ni_22_5_to_router_22_5_req; -floo_rsp_t router_22_5_to_magia_tile_ni_22_5_rsp; - -floo_req_t magia_tile_ni_22_6_to_router_22_6_req; -floo_rsp_t router_22_6_to_magia_tile_ni_22_6_rsp; - -floo_req_t magia_tile_ni_22_7_to_router_22_7_req; -floo_rsp_t router_22_7_to_magia_tile_ni_22_7_rsp; - -floo_req_t magia_tile_ni_22_8_to_router_22_8_req; -floo_rsp_t router_22_8_to_magia_tile_ni_22_8_rsp; - -floo_req_t magia_tile_ni_22_9_to_router_22_9_req; -floo_rsp_t router_22_9_to_magia_tile_ni_22_9_rsp; - -floo_req_t magia_tile_ni_22_10_to_router_22_10_req; -floo_rsp_t router_22_10_to_magia_tile_ni_22_10_rsp; - -floo_req_t magia_tile_ni_22_11_to_router_22_11_req; -floo_rsp_t router_22_11_to_magia_tile_ni_22_11_rsp; - -floo_req_t magia_tile_ni_22_12_to_router_22_12_req; -floo_rsp_t router_22_12_to_magia_tile_ni_22_12_rsp; - -floo_req_t magia_tile_ni_22_13_to_router_22_13_req; -floo_rsp_t router_22_13_to_magia_tile_ni_22_13_rsp; - -floo_req_t magia_tile_ni_22_14_to_router_22_14_req; -floo_rsp_t router_22_14_to_magia_tile_ni_22_14_rsp; - -floo_req_t magia_tile_ni_22_15_to_router_22_15_req; -floo_rsp_t router_22_15_to_magia_tile_ni_22_15_rsp; - -floo_req_t magia_tile_ni_22_16_to_router_22_16_req; -floo_rsp_t router_22_16_to_magia_tile_ni_22_16_rsp; - -floo_req_t magia_tile_ni_22_17_to_router_22_17_req; -floo_rsp_t router_22_17_to_magia_tile_ni_22_17_rsp; - -floo_req_t magia_tile_ni_22_18_to_router_22_18_req; -floo_rsp_t router_22_18_to_magia_tile_ni_22_18_rsp; - -floo_req_t magia_tile_ni_22_19_to_router_22_19_req; -floo_rsp_t router_22_19_to_magia_tile_ni_22_19_rsp; - -floo_req_t magia_tile_ni_22_20_to_router_22_20_req; -floo_rsp_t router_22_20_to_magia_tile_ni_22_20_rsp; - -floo_req_t magia_tile_ni_22_21_to_router_22_21_req; -floo_rsp_t router_22_21_to_magia_tile_ni_22_21_rsp; - -floo_req_t magia_tile_ni_22_22_to_router_22_22_req; -floo_rsp_t router_22_22_to_magia_tile_ni_22_22_rsp; - -floo_req_t magia_tile_ni_22_23_to_router_22_23_req; -floo_rsp_t router_22_23_to_magia_tile_ni_22_23_rsp; - -floo_req_t magia_tile_ni_22_24_to_router_22_24_req; -floo_rsp_t router_22_24_to_magia_tile_ni_22_24_rsp; - -floo_req_t magia_tile_ni_22_25_to_router_22_25_req; -floo_rsp_t router_22_25_to_magia_tile_ni_22_25_rsp; - -floo_req_t magia_tile_ni_22_26_to_router_22_26_req; -floo_rsp_t router_22_26_to_magia_tile_ni_22_26_rsp; - -floo_req_t magia_tile_ni_22_27_to_router_22_27_req; -floo_rsp_t router_22_27_to_magia_tile_ni_22_27_rsp; - -floo_req_t magia_tile_ni_22_28_to_router_22_28_req; -floo_rsp_t router_22_28_to_magia_tile_ni_22_28_rsp; - -floo_req_t magia_tile_ni_22_29_to_router_22_29_req; -floo_rsp_t router_22_29_to_magia_tile_ni_22_29_rsp; - -floo_req_t magia_tile_ni_22_30_to_router_22_30_req; -floo_rsp_t router_22_30_to_magia_tile_ni_22_30_rsp; - -floo_req_t magia_tile_ni_22_31_to_router_22_31_req; -floo_rsp_t router_22_31_to_magia_tile_ni_22_31_rsp; - -floo_req_t magia_tile_ni_23_0_to_router_23_0_req; -floo_rsp_t router_23_0_to_magia_tile_ni_23_0_rsp; - -floo_req_t magia_tile_ni_23_1_to_router_23_1_req; -floo_rsp_t router_23_1_to_magia_tile_ni_23_1_rsp; - -floo_req_t magia_tile_ni_23_2_to_router_23_2_req; -floo_rsp_t router_23_2_to_magia_tile_ni_23_2_rsp; - -floo_req_t magia_tile_ni_23_3_to_router_23_3_req; -floo_rsp_t router_23_3_to_magia_tile_ni_23_3_rsp; - -floo_req_t magia_tile_ni_23_4_to_router_23_4_req; -floo_rsp_t router_23_4_to_magia_tile_ni_23_4_rsp; - -floo_req_t magia_tile_ni_23_5_to_router_23_5_req; -floo_rsp_t router_23_5_to_magia_tile_ni_23_5_rsp; - -floo_req_t magia_tile_ni_23_6_to_router_23_6_req; -floo_rsp_t router_23_6_to_magia_tile_ni_23_6_rsp; - -floo_req_t magia_tile_ni_23_7_to_router_23_7_req; -floo_rsp_t router_23_7_to_magia_tile_ni_23_7_rsp; - -floo_req_t magia_tile_ni_23_8_to_router_23_8_req; -floo_rsp_t router_23_8_to_magia_tile_ni_23_8_rsp; - -floo_req_t magia_tile_ni_23_9_to_router_23_9_req; -floo_rsp_t router_23_9_to_magia_tile_ni_23_9_rsp; - -floo_req_t magia_tile_ni_23_10_to_router_23_10_req; -floo_rsp_t router_23_10_to_magia_tile_ni_23_10_rsp; - -floo_req_t magia_tile_ni_23_11_to_router_23_11_req; -floo_rsp_t router_23_11_to_magia_tile_ni_23_11_rsp; - -floo_req_t magia_tile_ni_23_12_to_router_23_12_req; -floo_rsp_t router_23_12_to_magia_tile_ni_23_12_rsp; - -floo_req_t magia_tile_ni_23_13_to_router_23_13_req; -floo_rsp_t router_23_13_to_magia_tile_ni_23_13_rsp; - -floo_req_t magia_tile_ni_23_14_to_router_23_14_req; -floo_rsp_t router_23_14_to_magia_tile_ni_23_14_rsp; - -floo_req_t magia_tile_ni_23_15_to_router_23_15_req; -floo_rsp_t router_23_15_to_magia_tile_ni_23_15_rsp; - -floo_req_t magia_tile_ni_23_16_to_router_23_16_req; -floo_rsp_t router_23_16_to_magia_tile_ni_23_16_rsp; - -floo_req_t magia_tile_ni_23_17_to_router_23_17_req; -floo_rsp_t router_23_17_to_magia_tile_ni_23_17_rsp; - -floo_req_t magia_tile_ni_23_18_to_router_23_18_req; -floo_rsp_t router_23_18_to_magia_tile_ni_23_18_rsp; - -floo_req_t magia_tile_ni_23_19_to_router_23_19_req; -floo_rsp_t router_23_19_to_magia_tile_ni_23_19_rsp; - -floo_req_t magia_tile_ni_23_20_to_router_23_20_req; -floo_rsp_t router_23_20_to_magia_tile_ni_23_20_rsp; - -floo_req_t magia_tile_ni_23_21_to_router_23_21_req; -floo_rsp_t router_23_21_to_magia_tile_ni_23_21_rsp; - -floo_req_t magia_tile_ni_23_22_to_router_23_22_req; -floo_rsp_t router_23_22_to_magia_tile_ni_23_22_rsp; - -floo_req_t magia_tile_ni_23_23_to_router_23_23_req; -floo_rsp_t router_23_23_to_magia_tile_ni_23_23_rsp; - -floo_req_t magia_tile_ni_23_24_to_router_23_24_req; -floo_rsp_t router_23_24_to_magia_tile_ni_23_24_rsp; - -floo_req_t magia_tile_ni_23_25_to_router_23_25_req; -floo_rsp_t router_23_25_to_magia_tile_ni_23_25_rsp; - -floo_req_t magia_tile_ni_23_26_to_router_23_26_req; -floo_rsp_t router_23_26_to_magia_tile_ni_23_26_rsp; - -floo_req_t magia_tile_ni_23_27_to_router_23_27_req; -floo_rsp_t router_23_27_to_magia_tile_ni_23_27_rsp; - -floo_req_t magia_tile_ni_23_28_to_router_23_28_req; -floo_rsp_t router_23_28_to_magia_tile_ni_23_28_rsp; - -floo_req_t magia_tile_ni_23_29_to_router_23_29_req; -floo_rsp_t router_23_29_to_magia_tile_ni_23_29_rsp; - -floo_req_t magia_tile_ni_23_30_to_router_23_30_req; -floo_rsp_t router_23_30_to_magia_tile_ni_23_30_rsp; - -floo_req_t magia_tile_ni_23_31_to_router_23_31_req; -floo_rsp_t router_23_31_to_magia_tile_ni_23_31_rsp; - -floo_req_t magia_tile_ni_24_0_to_router_24_0_req; -floo_rsp_t router_24_0_to_magia_tile_ni_24_0_rsp; - -floo_req_t magia_tile_ni_24_1_to_router_24_1_req; -floo_rsp_t router_24_1_to_magia_tile_ni_24_1_rsp; - -floo_req_t magia_tile_ni_24_2_to_router_24_2_req; -floo_rsp_t router_24_2_to_magia_tile_ni_24_2_rsp; - -floo_req_t magia_tile_ni_24_3_to_router_24_3_req; -floo_rsp_t router_24_3_to_magia_tile_ni_24_3_rsp; - -floo_req_t magia_tile_ni_24_4_to_router_24_4_req; -floo_rsp_t router_24_4_to_magia_tile_ni_24_4_rsp; - -floo_req_t magia_tile_ni_24_5_to_router_24_5_req; -floo_rsp_t router_24_5_to_magia_tile_ni_24_5_rsp; - -floo_req_t magia_tile_ni_24_6_to_router_24_6_req; -floo_rsp_t router_24_6_to_magia_tile_ni_24_6_rsp; - -floo_req_t magia_tile_ni_24_7_to_router_24_7_req; -floo_rsp_t router_24_7_to_magia_tile_ni_24_7_rsp; - -floo_req_t magia_tile_ni_24_8_to_router_24_8_req; -floo_rsp_t router_24_8_to_magia_tile_ni_24_8_rsp; - -floo_req_t magia_tile_ni_24_9_to_router_24_9_req; -floo_rsp_t router_24_9_to_magia_tile_ni_24_9_rsp; - -floo_req_t magia_tile_ni_24_10_to_router_24_10_req; -floo_rsp_t router_24_10_to_magia_tile_ni_24_10_rsp; - -floo_req_t magia_tile_ni_24_11_to_router_24_11_req; -floo_rsp_t router_24_11_to_magia_tile_ni_24_11_rsp; - -floo_req_t magia_tile_ni_24_12_to_router_24_12_req; -floo_rsp_t router_24_12_to_magia_tile_ni_24_12_rsp; - -floo_req_t magia_tile_ni_24_13_to_router_24_13_req; -floo_rsp_t router_24_13_to_magia_tile_ni_24_13_rsp; - -floo_req_t magia_tile_ni_24_14_to_router_24_14_req; -floo_rsp_t router_24_14_to_magia_tile_ni_24_14_rsp; - -floo_req_t magia_tile_ni_24_15_to_router_24_15_req; -floo_rsp_t router_24_15_to_magia_tile_ni_24_15_rsp; - -floo_req_t magia_tile_ni_24_16_to_router_24_16_req; -floo_rsp_t router_24_16_to_magia_tile_ni_24_16_rsp; - -floo_req_t magia_tile_ni_24_17_to_router_24_17_req; -floo_rsp_t router_24_17_to_magia_tile_ni_24_17_rsp; - -floo_req_t magia_tile_ni_24_18_to_router_24_18_req; -floo_rsp_t router_24_18_to_magia_tile_ni_24_18_rsp; - -floo_req_t magia_tile_ni_24_19_to_router_24_19_req; -floo_rsp_t router_24_19_to_magia_tile_ni_24_19_rsp; - -floo_req_t magia_tile_ni_24_20_to_router_24_20_req; -floo_rsp_t router_24_20_to_magia_tile_ni_24_20_rsp; - -floo_req_t magia_tile_ni_24_21_to_router_24_21_req; -floo_rsp_t router_24_21_to_magia_tile_ni_24_21_rsp; - -floo_req_t magia_tile_ni_24_22_to_router_24_22_req; -floo_rsp_t router_24_22_to_magia_tile_ni_24_22_rsp; - -floo_req_t magia_tile_ni_24_23_to_router_24_23_req; -floo_rsp_t router_24_23_to_magia_tile_ni_24_23_rsp; - -floo_req_t magia_tile_ni_24_24_to_router_24_24_req; -floo_rsp_t router_24_24_to_magia_tile_ni_24_24_rsp; - -floo_req_t magia_tile_ni_24_25_to_router_24_25_req; -floo_rsp_t router_24_25_to_magia_tile_ni_24_25_rsp; - -floo_req_t magia_tile_ni_24_26_to_router_24_26_req; -floo_rsp_t router_24_26_to_magia_tile_ni_24_26_rsp; - -floo_req_t magia_tile_ni_24_27_to_router_24_27_req; -floo_rsp_t router_24_27_to_magia_tile_ni_24_27_rsp; - -floo_req_t magia_tile_ni_24_28_to_router_24_28_req; -floo_rsp_t router_24_28_to_magia_tile_ni_24_28_rsp; - -floo_req_t magia_tile_ni_24_29_to_router_24_29_req; -floo_rsp_t router_24_29_to_magia_tile_ni_24_29_rsp; - -floo_req_t magia_tile_ni_24_30_to_router_24_30_req; -floo_rsp_t router_24_30_to_magia_tile_ni_24_30_rsp; - -floo_req_t magia_tile_ni_24_31_to_router_24_31_req; -floo_rsp_t router_24_31_to_magia_tile_ni_24_31_rsp; - -floo_req_t magia_tile_ni_25_0_to_router_25_0_req; -floo_rsp_t router_25_0_to_magia_tile_ni_25_0_rsp; - -floo_req_t magia_tile_ni_25_1_to_router_25_1_req; -floo_rsp_t router_25_1_to_magia_tile_ni_25_1_rsp; - -floo_req_t magia_tile_ni_25_2_to_router_25_2_req; -floo_rsp_t router_25_2_to_magia_tile_ni_25_2_rsp; - -floo_req_t magia_tile_ni_25_3_to_router_25_3_req; -floo_rsp_t router_25_3_to_magia_tile_ni_25_3_rsp; - -floo_req_t magia_tile_ni_25_4_to_router_25_4_req; -floo_rsp_t router_25_4_to_magia_tile_ni_25_4_rsp; - -floo_req_t magia_tile_ni_25_5_to_router_25_5_req; -floo_rsp_t router_25_5_to_magia_tile_ni_25_5_rsp; - -floo_req_t magia_tile_ni_25_6_to_router_25_6_req; -floo_rsp_t router_25_6_to_magia_tile_ni_25_6_rsp; - -floo_req_t magia_tile_ni_25_7_to_router_25_7_req; -floo_rsp_t router_25_7_to_magia_tile_ni_25_7_rsp; - -floo_req_t magia_tile_ni_25_8_to_router_25_8_req; -floo_rsp_t router_25_8_to_magia_tile_ni_25_8_rsp; - -floo_req_t magia_tile_ni_25_9_to_router_25_9_req; -floo_rsp_t router_25_9_to_magia_tile_ni_25_9_rsp; - -floo_req_t magia_tile_ni_25_10_to_router_25_10_req; -floo_rsp_t router_25_10_to_magia_tile_ni_25_10_rsp; - -floo_req_t magia_tile_ni_25_11_to_router_25_11_req; -floo_rsp_t router_25_11_to_magia_tile_ni_25_11_rsp; - -floo_req_t magia_tile_ni_25_12_to_router_25_12_req; -floo_rsp_t router_25_12_to_magia_tile_ni_25_12_rsp; - -floo_req_t magia_tile_ni_25_13_to_router_25_13_req; -floo_rsp_t router_25_13_to_magia_tile_ni_25_13_rsp; - -floo_req_t magia_tile_ni_25_14_to_router_25_14_req; -floo_rsp_t router_25_14_to_magia_tile_ni_25_14_rsp; - -floo_req_t magia_tile_ni_25_15_to_router_25_15_req; -floo_rsp_t router_25_15_to_magia_tile_ni_25_15_rsp; - -floo_req_t magia_tile_ni_25_16_to_router_25_16_req; -floo_rsp_t router_25_16_to_magia_tile_ni_25_16_rsp; - -floo_req_t magia_tile_ni_25_17_to_router_25_17_req; -floo_rsp_t router_25_17_to_magia_tile_ni_25_17_rsp; - -floo_req_t magia_tile_ni_25_18_to_router_25_18_req; -floo_rsp_t router_25_18_to_magia_tile_ni_25_18_rsp; - -floo_req_t magia_tile_ni_25_19_to_router_25_19_req; -floo_rsp_t router_25_19_to_magia_tile_ni_25_19_rsp; - -floo_req_t magia_tile_ni_25_20_to_router_25_20_req; -floo_rsp_t router_25_20_to_magia_tile_ni_25_20_rsp; - -floo_req_t magia_tile_ni_25_21_to_router_25_21_req; -floo_rsp_t router_25_21_to_magia_tile_ni_25_21_rsp; - -floo_req_t magia_tile_ni_25_22_to_router_25_22_req; -floo_rsp_t router_25_22_to_magia_tile_ni_25_22_rsp; - -floo_req_t magia_tile_ni_25_23_to_router_25_23_req; -floo_rsp_t router_25_23_to_magia_tile_ni_25_23_rsp; - -floo_req_t magia_tile_ni_25_24_to_router_25_24_req; -floo_rsp_t router_25_24_to_magia_tile_ni_25_24_rsp; - -floo_req_t magia_tile_ni_25_25_to_router_25_25_req; -floo_rsp_t router_25_25_to_magia_tile_ni_25_25_rsp; - -floo_req_t magia_tile_ni_25_26_to_router_25_26_req; -floo_rsp_t router_25_26_to_magia_tile_ni_25_26_rsp; - -floo_req_t magia_tile_ni_25_27_to_router_25_27_req; -floo_rsp_t router_25_27_to_magia_tile_ni_25_27_rsp; - -floo_req_t magia_tile_ni_25_28_to_router_25_28_req; -floo_rsp_t router_25_28_to_magia_tile_ni_25_28_rsp; - -floo_req_t magia_tile_ni_25_29_to_router_25_29_req; -floo_rsp_t router_25_29_to_magia_tile_ni_25_29_rsp; - -floo_req_t magia_tile_ni_25_30_to_router_25_30_req; -floo_rsp_t router_25_30_to_magia_tile_ni_25_30_rsp; - -floo_req_t magia_tile_ni_25_31_to_router_25_31_req; -floo_rsp_t router_25_31_to_magia_tile_ni_25_31_rsp; - -floo_req_t magia_tile_ni_26_0_to_router_26_0_req; -floo_rsp_t router_26_0_to_magia_tile_ni_26_0_rsp; - -floo_req_t magia_tile_ni_26_1_to_router_26_1_req; -floo_rsp_t router_26_1_to_magia_tile_ni_26_1_rsp; - -floo_req_t magia_tile_ni_26_2_to_router_26_2_req; -floo_rsp_t router_26_2_to_magia_tile_ni_26_2_rsp; - -floo_req_t magia_tile_ni_26_3_to_router_26_3_req; -floo_rsp_t router_26_3_to_magia_tile_ni_26_3_rsp; - -floo_req_t magia_tile_ni_26_4_to_router_26_4_req; -floo_rsp_t router_26_4_to_magia_tile_ni_26_4_rsp; - -floo_req_t magia_tile_ni_26_5_to_router_26_5_req; -floo_rsp_t router_26_5_to_magia_tile_ni_26_5_rsp; - -floo_req_t magia_tile_ni_26_6_to_router_26_6_req; -floo_rsp_t router_26_6_to_magia_tile_ni_26_6_rsp; - -floo_req_t magia_tile_ni_26_7_to_router_26_7_req; -floo_rsp_t router_26_7_to_magia_tile_ni_26_7_rsp; - -floo_req_t magia_tile_ni_26_8_to_router_26_8_req; -floo_rsp_t router_26_8_to_magia_tile_ni_26_8_rsp; - -floo_req_t magia_tile_ni_26_9_to_router_26_9_req; -floo_rsp_t router_26_9_to_magia_tile_ni_26_9_rsp; - -floo_req_t magia_tile_ni_26_10_to_router_26_10_req; -floo_rsp_t router_26_10_to_magia_tile_ni_26_10_rsp; - -floo_req_t magia_tile_ni_26_11_to_router_26_11_req; -floo_rsp_t router_26_11_to_magia_tile_ni_26_11_rsp; - -floo_req_t magia_tile_ni_26_12_to_router_26_12_req; -floo_rsp_t router_26_12_to_magia_tile_ni_26_12_rsp; - -floo_req_t magia_tile_ni_26_13_to_router_26_13_req; -floo_rsp_t router_26_13_to_magia_tile_ni_26_13_rsp; - -floo_req_t magia_tile_ni_26_14_to_router_26_14_req; -floo_rsp_t router_26_14_to_magia_tile_ni_26_14_rsp; - -floo_req_t magia_tile_ni_26_15_to_router_26_15_req; -floo_rsp_t router_26_15_to_magia_tile_ni_26_15_rsp; - -floo_req_t magia_tile_ni_26_16_to_router_26_16_req; -floo_rsp_t router_26_16_to_magia_tile_ni_26_16_rsp; - -floo_req_t magia_tile_ni_26_17_to_router_26_17_req; -floo_rsp_t router_26_17_to_magia_tile_ni_26_17_rsp; - -floo_req_t magia_tile_ni_26_18_to_router_26_18_req; -floo_rsp_t router_26_18_to_magia_tile_ni_26_18_rsp; - -floo_req_t magia_tile_ni_26_19_to_router_26_19_req; -floo_rsp_t router_26_19_to_magia_tile_ni_26_19_rsp; - -floo_req_t magia_tile_ni_26_20_to_router_26_20_req; -floo_rsp_t router_26_20_to_magia_tile_ni_26_20_rsp; - -floo_req_t magia_tile_ni_26_21_to_router_26_21_req; -floo_rsp_t router_26_21_to_magia_tile_ni_26_21_rsp; - -floo_req_t magia_tile_ni_26_22_to_router_26_22_req; -floo_rsp_t router_26_22_to_magia_tile_ni_26_22_rsp; - -floo_req_t magia_tile_ni_26_23_to_router_26_23_req; -floo_rsp_t router_26_23_to_magia_tile_ni_26_23_rsp; - -floo_req_t magia_tile_ni_26_24_to_router_26_24_req; -floo_rsp_t router_26_24_to_magia_tile_ni_26_24_rsp; - -floo_req_t magia_tile_ni_26_25_to_router_26_25_req; -floo_rsp_t router_26_25_to_magia_tile_ni_26_25_rsp; - -floo_req_t magia_tile_ni_26_26_to_router_26_26_req; -floo_rsp_t router_26_26_to_magia_tile_ni_26_26_rsp; - -floo_req_t magia_tile_ni_26_27_to_router_26_27_req; -floo_rsp_t router_26_27_to_magia_tile_ni_26_27_rsp; - -floo_req_t magia_tile_ni_26_28_to_router_26_28_req; -floo_rsp_t router_26_28_to_magia_tile_ni_26_28_rsp; - -floo_req_t magia_tile_ni_26_29_to_router_26_29_req; -floo_rsp_t router_26_29_to_magia_tile_ni_26_29_rsp; - -floo_req_t magia_tile_ni_26_30_to_router_26_30_req; -floo_rsp_t router_26_30_to_magia_tile_ni_26_30_rsp; - -floo_req_t magia_tile_ni_26_31_to_router_26_31_req; -floo_rsp_t router_26_31_to_magia_tile_ni_26_31_rsp; - -floo_req_t magia_tile_ni_27_0_to_router_27_0_req; -floo_rsp_t router_27_0_to_magia_tile_ni_27_0_rsp; - -floo_req_t magia_tile_ni_27_1_to_router_27_1_req; -floo_rsp_t router_27_1_to_magia_tile_ni_27_1_rsp; - -floo_req_t magia_tile_ni_27_2_to_router_27_2_req; -floo_rsp_t router_27_2_to_magia_tile_ni_27_2_rsp; - -floo_req_t magia_tile_ni_27_3_to_router_27_3_req; -floo_rsp_t router_27_3_to_magia_tile_ni_27_3_rsp; - -floo_req_t magia_tile_ni_27_4_to_router_27_4_req; -floo_rsp_t router_27_4_to_magia_tile_ni_27_4_rsp; - -floo_req_t magia_tile_ni_27_5_to_router_27_5_req; -floo_rsp_t router_27_5_to_magia_tile_ni_27_5_rsp; - -floo_req_t magia_tile_ni_27_6_to_router_27_6_req; -floo_rsp_t router_27_6_to_magia_tile_ni_27_6_rsp; - -floo_req_t magia_tile_ni_27_7_to_router_27_7_req; -floo_rsp_t router_27_7_to_magia_tile_ni_27_7_rsp; - -floo_req_t magia_tile_ni_27_8_to_router_27_8_req; -floo_rsp_t router_27_8_to_magia_tile_ni_27_8_rsp; - -floo_req_t magia_tile_ni_27_9_to_router_27_9_req; -floo_rsp_t router_27_9_to_magia_tile_ni_27_9_rsp; - -floo_req_t magia_tile_ni_27_10_to_router_27_10_req; -floo_rsp_t router_27_10_to_magia_tile_ni_27_10_rsp; - -floo_req_t magia_tile_ni_27_11_to_router_27_11_req; -floo_rsp_t router_27_11_to_magia_tile_ni_27_11_rsp; - -floo_req_t magia_tile_ni_27_12_to_router_27_12_req; -floo_rsp_t router_27_12_to_magia_tile_ni_27_12_rsp; - -floo_req_t magia_tile_ni_27_13_to_router_27_13_req; -floo_rsp_t router_27_13_to_magia_tile_ni_27_13_rsp; - -floo_req_t magia_tile_ni_27_14_to_router_27_14_req; -floo_rsp_t router_27_14_to_magia_tile_ni_27_14_rsp; - -floo_req_t magia_tile_ni_27_15_to_router_27_15_req; -floo_rsp_t router_27_15_to_magia_tile_ni_27_15_rsp; - -floo_req_t magia_tile_ni_27_16_to_router_27_16_req; -floo_rsp_t router_27_16_to_magia_tile_ni_27_16_rsp; - -floo_req_t magia_tile_ni_27_17_to_router_27_17_req; -floo_rsp_t router_27_17_to_magia_tile_ni_27_17_rsp; - -floo_req_t magia_tile_ni_27_18_to_router_27_18_req; -floo_rsp_t router_27_18_to_magia_tile_ni_27_18_rsp; - -floo_req_t magia_tile_ni_27_19_to_router_27_19_req; -floo_rsp_t router_27_19_to_magia_tile_ni_27_19_rsp; - -floo_req_t magia_tile_ni_27_20_to_router_27_20_req; -floo_rsp_t router_27_20_to_magia_tile_ni_27_20_rsp; - -floo_req_t magia_tile_ni_27_21_to_router_27_21_req; -floo_rsp_t router_27_21_to_magia_tile_ni_27_21_rsp; - -floo_req_t magia_tile_ni_27_22_to_router_27_22_req; -floo_rsp_t router_27_22_to_magia_tile_ni_27_22_rsp; - -floo_req_t magia_tile_ni_27_23_to_router_27_23_req; -floo_rsp_t router_27_23_to_magia_tile_ni_27_23_rsp; - -floo_req_t magia_tile_ni_27_24_to_router_27_24_req; -floo_rsp_t router_27_24_to_magia_tile_ni_27_24_rsp; - -floo_req_t magia_tile_ni_27_25_to_router_27_25_req; -floo_rsp_t router_27_25_to_magia_tile_ni_27_25_rsp; - -floo_req_t magia_tile_ni_27_26_to_router_27_26_req; -floo_rsp_t router_27_26_to_magia_tile_ni_27_26_rsp; - -floo_req_t magia_tile_ni_27_27_to_router_27_27_req; -floo_rsp_t router_27_27_to_magia_tile_ni_27_27_rsp; - -floo_req_t magia_tile_ni_27_28_to_router_27_28_req; -floo_rsp_t router_27_28_to_magia_tile_ni_27_28_rsp; - -floo_req_t magia_tile_ni_27_29_to_router_27_29_req; -floo_rsp_t router_27_29_to_magia_tile_ni_27_29_rsp; - -floo_req_t magia_tile_ni_27_30_to_router_27_30_req; -floo_rsp_t router_27_30_to_magia_tile_ni_27_30_rsp; - -floo_req_t magia_tile_ni_27_31_to_router_27_31_req; -floo_rsp_t router_27_31_to_magia_tile_ni_27_31_rsp; - -floo_req_t magia_tile_ni_28_0_to_router_28_0_req; -floo_rsp_t router_28_0_to_magia_tile_ni_28_0_rsp; - -floo_req_t magia_tile_ni_28_1_to_router_28_1_req; -floo_rsp_t router_28_1_to_magia_tile_ni_28_1_rsp; - -floo_req_t magia_tile_ni_28_2_to_router_28_2_req; -floo_rsp_t router_28_2_to_magia_tile_ni_28_2_rsp; - -floo_req_t magia_tile_ni_28_3_to_router_28_3_req; -floo_rsp_t router_28_3_to_magia_tile_ni_28_3_rsp; - -floo_req_t magia_tile_ni_28_4_to_router_28_4_req; -floo_rsp_t router_28_4_to_magia_tile_ni_28_4_rsp; - -floo_req_t magia_tile_ni_28_5_to_router_28_5_req; -floo_rsp_t router_28_5_to_magia_tile_ni_28_5_rsp; - -floo_req_t magia_tile_ni_28_6_to_router_28_6_req; -floo_rsp_t router_28_6_to_magia_tile_ni_28_6_rsp; - -floo_req_t magia_tile_ni_28_7_to_router_28_7_req; -floo_rsp_t router_28_7_to_magia_tile_ni_28_7_rsp; - -floo_req_t magia_tile_ni_28_8_to_router_28_8_req; -floo_rsp_t router_28_8_to_magia_tile_ni_28_8_rsp; - -floo_req_t magia_tile_ni_28_9_to_router_28_9_req; -floo_rsp_t router_28_9_to_magia_tile_ni_28_9_rsp; - -floo_req_t magia_tile_ni_28_10_to_router_28_10_req; -floo_rsp_t router_28_10_to_magia_tile_ni_28_10_rsp; - -floo_req_t magia_tile_ni_28_11_to_router_28_11_req; -floo_rsp_t router_28_11_to_magia_tile_ni_28_11_rsp; - -floo_req_t magia_tile_ni_28_12_to_router_28_12_req; -floo_rsp_t router_28_12_to_magia_tile_ni_28_12_rsp; - -floo_req_t magia_tile_ni_28_13_to_router_28_13_req; -floo_rsp_t router_28_13_to_magia_tile_ni_28_13_rsp; - -floo_req_t magia_tile_ni_28_14_to_router_28_14_req; -floo_rsp_t router_28_14_to_magia_tile_ni_28_14_rsp; - -floo_req_t magia_tile_ni_28_15_to_router_28_15_req; -floo_rsp_t router_28_15_to_magia_tile_ni_28_15_rsp; - -floo_req_t magia_tile_ni_28_16_to_router_28_16_req; -floo_rsp_t router_28_16_to_magia_tile_ni_28_16_rsp; - -floo_req_t magia_tile_ni_28_17_to_router_28_17_req; -floo_rsp_t router_28_17_to_magia_tile_ni_28_17_rsp; - -floo_req_t magia_tile_ni_28_18_to_router_28_18_req; -floo_rsp_t router_28_18_to_magia_tile_ni_28_18_rsp; - -floo_req_t magia_tile_ni_28_19_to_router_28_19_req; -floo_rsp_t router_28_19_to_magia_tile_ni_28_19_rsp; - -floo_req_t magia_tile_ni_28_20_to_router_28_20_req; -floo_rsp_t router_28_20_to_magia_tile_ni_28_20_rsp; - -floo_req_t magia_tile_ni_28_21_to_router_28_21_req; -floo_rsp_t router_28_21_to_magia_tile_ni_28_21_rsp; - -floo_req_t magia_tile_ni_28_22_to_router_28_22_req; -floo_rsp_t router_28_22_to_magia_tile_ni_28_22_rsp; - -floo_req_t magia_tile_ni_28_23_to_router_28_23_req; -floo_rsp_t router_28_23_to_magia_tile_ni_28_23_rsp; - -floo_req_t magia_tile_ni_28_24_to_router_28_24_req; -floo_rsp_t router_28_24_to_magia_tile_ni_28_24_rsp; - -floo_req_t magia_tile_ni_28_25_to_router_28_25_req; -floo_rsp_t router_28_25_to_magia_tile_ni_28_25_rsp; - -floo_req_t magia_tile_ni_28_26_to_router_28_26_req; -floo_rsp_t router_28_26_to_magia_tile_ni_28_26_rsp; - -floo_req_t magia_tile_ni_28_27_to_router_28_27_req; -floo_rsp_t router_28_27_to_magia_tile_ni_28_27_rsp; - -floo_req_t magia_tile_ni_28_28_to_router_28_28_req; -floo_rsp_t router_28_28_to_magia_tile_ni_28_28_rsp; - -floo_req_t magia_tile_ni_28_29_to_router_28_29_req; -floo_rsp_t router_28_29_to_magia_tile_ni_28_29_rsp; - -floo_req_t magia_tile_ni_28_30_to_router_28_30_req; -floo_rsp_t router_28_30_to_magia_tile_ni_28_30_rsp; - -floo_req_t magia_tile_ni_28_31_to_router_28_31_req; -floo_rsp_t router_28_31_to_magia_tile_ni_28_31_rsp; - -floo_req_t magia_tile_ni_29_0_to_router_29_0_req; -floo_rsp_t router_29_0_to_magia_tile_ni_29_0_rsp; - -floo_req_t magia_tile_ni_29_1_to_router_29_1_req; -floo_rsp_t router_29_1_to_magia_tile_ni_29_1_rsp; - -floo_req_t magia_tile_ni_29_2_to_router_29_2_req; -floo_rsp_t router_29_2_to_magia_tile_ni_29_2_rsp; - -floo_req_t magia_tile_ni_29_3_to_router_29_3_req; -floo_rsp_t router_29_3_to_magia_tile_ni_29_3_rsp; - -floo_req_t magia_tile_ni_29_4_to_router_29_4_req; -floo_rsp_t router_29_4_to_magia_tile_ni_29_4_rsp; - -floo_req_t magia_tile_ni_29_5_to_router_29_5_req; -floo_rsp_t router_29_5_to_magia_tile_ni_29_5_rsp; - -floo_req_t magia_tile_ni_29_6_to_router_29_6_req; -floo_rsp_t router_29_6_to_magia_tile_ni_29_6_rsp; - -floo_req_t magia_tile_ni_29_7_to_router_29_7_req; -floo_rsp_t router_29_7_to_magia_tile_ni_29_7_rsp; - -floo_req_t magia_tile_ni_29_8_to_router_29_8_req; -floo_rsp_t router_29_8_to_magia_tile_ni_29_8_rsp; - -floo_req_t magia_tile_ni_29_9_to_router_29_9_req; -floo_rsp_t router_29_9_to_magia_tile_ni_29_9_rsp; - -floo_req_t magia_tile_ni_29_10_to_router_29_10_req; -floo_rsp_t router_29_10_to_magia_tile_ni_29_10_rsp; - -floo_req_t magia_tile_ni_29_11_to_router_29_11_req; -floo_rsp_t router_29_11_to_magia_tile_ni_29_11_rsp; - -floo_req_t magia_tile_ni_29_12_to_router_29_12_req; -floo_rsp_t router_29_12_to_magia_tile_ni_29_12_rsp; - -floo_req_t magia_tile_ni_29_13_to_router_29_13_req; -floo_rsp_t router_29_13_to_magia_tile_ni_29_13_rsp; - -floo_req_t magia_tile_ni_29_14_to_router_29_14_req; -floo_rsp_t router_29_14_to_magia_tile_ni_29_14_rsp; - -floo_req_t magia_tile_ni_29_15_to_router_29_15_req; -floo_rsp_t router_29_15_to_magia_tile_ni_29_15_rsp; - -floo_req_t magia_tile_ni_29_16_to_router_29_16_req; -floo_rsp_t router_29_16_to_magia_tile_ni_29_16_rsp; - -floo_req_t magia_tile_ni_29_17_to_router_29_17_req; -floo_rsp_t router_29_17_to_magia_tile_ni_29_17_rsp; - -floo_req_t magia_tile_ni_29_18_to_router_29_18_req; -floo_rsp_t router_29_18_to_magia_tile_ni_29_18_rsp; - -floo_req_t magia_tile_ni_29_19_to_router_29_19_req; -floo_rsp_t router_29_19_to_magia_tile_ni_29_19_rsp; - -floo_req_t magia_tile_ni_29_20_to_router_29_20_req; -floo_rsp_t router_29_20_to_magia_tile_ni_29_20_rsp; - -floo_req_t magia_tile_ni_29_21_to_router_29_21_req; -floo_rsp_t router_29_21_to_magia_tile_ni_29_21_rsp; - -floo_req_t magia_tile_ni_29_22_to_router_29_22_req; -floo_rsp_t router_29_22_to_magia_tile_ni_29_22_rsp; - -floo_req_t magia_tile_ni_29_23_to_router_29_23_req; -floo_rsp_t router_29_23_to_magia_tile_ni_29_23_rsp; - -floo_req_t magia_tile_ni_29_24_to_router_29_24_req; -floo_rsp_t router_29_24_to_magia_tile_ni_29_24_rsp; - -floo_req_t magia_tile_ni_29_25_to_router_29_25_req; -floo_rsp_t router_29_25_to_magia_tile_ni_29_25_rsp; - -floo_req_t magia_tile_ni_29_26_to_router_29_26_req; -floo_rsp_t router_29_26_to_magia_tile_ni_29_26_rsp; - -floo_req_t magia_tile_ni_29_27_to_router_29_27_req; -floo_rsp_t router_29_27_to_magia_tile_ni_29_27_rsp; - -floo_req_t magia_tile_ni_29_28_to_router_29_28_req; -floo_rsp_t router_29_28_to_magia_tile_ni_29_28_rsp; - -floo_req_t magia_tile_ni_29_29_to_router_29_29_req; -floo_rsp_t router_29_29_to_magia_tile_ni_29_29_rsp; - -floo_req_t magia_tile_ni_29_30_to_router_29_30_req; -floo_rsp_t router_29_30_to_magia_tile_ni_29_30_rsp; - -floo_req_t magia_tile_ni_29_31_to_router_29_31_req; -floo_rsp_t router_29_31_to_magia_tile_ni_29_31_rsp; - -floo_req_t magia_tile_ni_30_0_to_router_30_0_req; -floo_rsp_t router_30_0_to_magia_tile_ni_30_0_rsp; - -floo_req_t magia_tile_ni_30_1_to_router_30_1_req; -floo_rsp_t router_30_1_to_magia_tile_ni_30_1_rsp; - -floo_req_t magia_tile_ni_30_2_to_router_30_2_req; -floo_rsp_t router_30_2_to_magia_tile_ni_30_2_rsp; - -floo_req_t magia_tile_ni_30_3_to_router_30_3_req; -floo_rsp_t router_30_3_to_magia_tile_ni_30_3_rsp; - -floo_req_t magia_tile_ni_30_4_to_router_30_4_req; -floo_rsp_t router_30_4_to_magia_tile_ni_30_4_rsp; - -floo_req_t magia_tile_ni_30_5_to_router_30_5_req; -floo_rsp_t router_30_5_to_magia_tile_ni_30_5_rsp; - -floo_req_t magia_tile_ni_30_6_to_router_30_6_req; -floo_rsp_t router_30_6_to_magia_tile_ni_30_6_rsp; - -floo_req_t magia_tile_ni_30_7_to_router_30_7_req; -floo_rsp_t router_30_7_to_magia_tile_ni_30_7_rsp; - -floo_req_t magia_tile_ni_30_8_to_router_30_8_req; -floo_rsp_t router_30_8_to_magia_tile_ni_30_8_rsp; - -floo_req_t magia_tile_ni_30_9_to_router_30_9_req; -floo_rsp_t router_30_9_to_magia_tile_ni_30_9_rsp; - -floo_req_t magia_tile_ni_30_10_to_router_30_10_req; -floo_rsp_t router_30_10_to_magia_tile_ni_30_10_rsp; - -floo_req_t magia_tile_ni_30_11_to_router_30_11_req; -floo_rsp_t router_30_11_to_magia_tile_ni_30_11_rsp; - -floo_req_t magia_tile_ni_30_12_to_router_30_12_req; -floo_rsp_t router_30_12_to_magia_tile_ni_30_12_rsp; - -floo_req_t magia_tile_ni_30_13_to_router_30_13_req; -floo_rsp_t router_30_13_to_magia_tile_ni_30_13_rsp; - -floo_req_t magia_tile_ni_30_14_to_router_30_14_req; -floo_rsp_t router_30_14_to_magia_tile_ni_30_14_rsp; - -floo_req_t magia_tile_ni_30_15_to_router_30_15_req; -floo_rsp_t router_30_15_to_magia_tile_ni_30_15_rsp; - -floo_req_t magia_tile_ni_30_16_to_router_30_16_req; -floo_rsp_t router_30_16_to_magia_tile_ni_30_16_rsp; - -floo_req_t magia_tile_ni_30_17_to_router_30_17_req; -floo_rsp_t router_30_17_to_magia_tile_ni_30_17_rsp; - -floo_req_t magia_tile_ni_30_18_to_router_30_18_req; -floo_rsp_t router_30_18_to_magia_tile_ni_30_18_rsp; - -floo_req_t magia_tile_ni_30_19_to_router_30_19_req; -floo_rsp_t router_30_19_to_magia_tile_ni_30_19_rsp; - -floo_req_t magia_tile_ni_30_20_to_router_30_20_req; -floo_rsp_t router_30_20_to_magia_tile_ni_30_20_rsp; - -floo_req_t magia_tile_ni_30_21_to_router_30_21_req; -floo_rsp_t router_30_21_to_magia_tile_ni_30_21_rsp; - -floo_req_t magia_tile_ni_30_22_to_router_30_22_req; -floo_rsp_t router_30_22_to_magia_tile_ni_30_22_rsp; - -floo_req_t magia_tile_ni_30_23_to_router_30_23_req; -floo_rsp_t router_30_23_to_magia_tile_ni_30_23_rsp; - -floo_req_t magia_tile_ni_30_24_to_router_30_24_req; -floo_rsp_t router_30_24_to_magia_tile_ni_30_24_rsp; - -floo_req_t magia_tile_ni_30_25_to_router_30_25_req; -floo_rsp_t router_30_25_to_magia_tile_ni_30_25_rsp; - -floo_req_t magia_tile_ni_30_26_to_router_30_26_req; -floo_rsp_t router_30_26_to_magia_tile_ni_30_26_rsp; - -floo_req_t magia_tile_ni_30_27_to_router_30_27_req; -floo_rsp_t router_30_27_to_magia_tile_ni_30_27_rsp; - -floo_req_t magia_tile_ni_30_28_to_router_30_28_req; -floo_rsp_t router_30_28_to_magia_tile_ni_30_28_rsp; - -floo_req_t magia_tile_ni_30_29_to_router_30_29_req; -floo_rsp_t router_30_29_to_magia_tile_ni_30_29_rsp; - -floo_req_t magia_tile_ni_30_30_to_router_30_30_req; -floo_rsp_t router_30_30_to_magia_tile_ni_30_30_rsp; - -floo_req_t magia_tile_ni_30_31_to_router_30_31_req; -floo_rsp_t router_30_31_to_magia_tile_ni_30_31_rsp; - -floo_req_t magia_tile_ni_31_0_to_router_31_0_req; -floo_rsp_t router_31_0_to_magia_tile_ni_31_0_rsp; - -floo_req_t magia_tile_ni_31_1_to_router_31_1_req; -floo_rsp_t router_31_1_to_magia_tile_ni_31_1_rsp; - -floo_req_t magia_tile_ni_31_2_to_router_31_2_req; -floo_rsp_t router_31_2_to_magia_tile_ni_31_2_rsp; - -floo_req_t magia_tile_ni_31_3_to_router_31_3_req; -floo_rsp_t router_31_3_to_magia_tile_ni_31_3_rsp; - -floo_req_t magia_tile_ni_31_4_to_router_31_4_req; -floo_rsp_t router_31_4_to_magia_tile_ni_31_4_rsp; - -floo_req_t magia_tile_ni_31_5_to_router_31_5_req; -floo_rsp_t router_31_5_to_magia_tile_ni_31_5_rsp; - -floo_req_t magia_tile_ni_31_6_to_router_31_6_req; -floo_rsp_t router_31_6_to_magia_tile_ni_31_6_rsp; - -floo_req_t magia_tile_ni_31_7_to_router_31_7_req; -floo_rsp_t router_31_7_to_magia_tile_ni_31_7_rsp; - -floo_req_t magia_tile_ni_31_8_to_router_31_8_req; -floo_rsp_t router_31_8_to_magia_tile_ni_31_8_rsp; - -floo_req_t magia_tile_ni_31_9_to_router_31_9_req; -floo_rsp_t router_31_9_to_magia_tile_ni_31_9_rsp; - -floo_req_t magia_tile_ni_31_10_to_router_31_10_req; -floo_rsp_t router_31_10_to_magia_tile_ni_31_10_rsp; - -floo_req_t magia_tile_ni_31_11_to_router_31_11_req; -floo_rsp_t router_31_11_to_magia_tile_ni_31_11_rsp; - -floo_req_t magia_tile_ni_31_12_to_router_31_12_req; -floo_rsp_t router_31_12_to_magia_tile_ni_31_12_rsp; - -floo_req_t magia_tile_ni_31_13_to_router_31_13_req; -floo_rsp_t router_31_13_to_magia_tile_ni_31_13_rsp; - -floo_req_t magia_tile_ni_31_14_to_router_31_14_req; -floo_rsp_t router_31_14_to_magia_tile_ni_31_14_rsp; - -floo_req_t magia_tile_ni_31_15_to_router_31_15_req; -floo_rsp_t router_31_15_to_magia_tile_ni_31_15_rsp; - -floo_req_t magia_tile_ni_31_16_to_router_31_16_req; -floo_rsp_t router_31_16_to_magia_tile_ni_31_16_rsp; - -floo_req_t magia_tile_ni_31_17_to_router_31_17_req; -floo_rsp_t router_31_17_to_magia_tile_ni_31_17_rsp; - -floo_req_t magia_tile_ni_31_18_to_router_31_18_req; -floo_rsp_t router_31_18_to_magia_tile_ni_31_18_rsp; - -floo_req_t magia_tile_ni_31_19_to_router_31_19_req; -floo_rsp_t router_31_19_to_magia_tile_ni_31_19_rsp; - -floo_req_t magia_tile_ni_31_20_to_router_31_20_req; -floo_rsp_t router_31_20_to_magia_tile_ni_31_20_rsp; - -floo_req_t magia_tile_ni_31_21_to_router_31_21_req; -floo_rsp_t router_31_21_to_magia_tile_ni_31_21_rsp; - -floo_req_t magia_tile_ni_31_22_to_router_31_22_req; -floo_rsp_t router_31_22_to_magia_tile_ni_31_22_rsp; - -floo_req_t magia_tile_ni_31_23_to_router_31_23_req; -floo_rsp_t router_31_23_to_magia_tile_ni_31_23_rsp; - -floo_req_t magia_tile_ni_31_24_to_router_31_24_req; -floo_rsp_t router_31_24_to_magia_tile_ni_31_24_rsp; - -floo_req_t magia_tile_ni_31_25_to_router_31_25_req; -floo_rsp_t router_31_25_to_magia_tile_ni_31_25_rsp; - -floo_req_t magia_tile_ni_31_26_to_router_31_26_req; -floo_rsp_t router_31_26_to_magia_tile_ni_31_26_rsp; - -floo_req_t magia_tile_ni_31_27_to_router_31_27_req; -floo_rsp_t router_31_27_to_magia_tile_ni_31_27_rsp; - -floo_req_t magia_tile_ni_31_28_to_router_31_28_req; -floo_rsp_t router_31_28_to_magia_tile_ni_31_28_rsp; - -floo_req_t magia_tile_ni_31_29_to_router_31_29_req; -floo_rsp_t router_31_29_to_magia_tile_ni_31_29_rsp; - -floo_req_t magia_tile_ni_31_30_to_router_31_30_req; -floo_rsp_t router_31_30_to_magia_tile_ni_31_30_rsp; - -floo_req_t magia_tile_ni_31_31_to_router_31_31_req; -floo_rsp_t router_31_31_to_magia_tile_ni_31_31_rsp; - -floo_req_t L2_ni_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_L2_ni_0_rsp; - -floo_req_t L2_ni_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_L2_ni_1_rsp; - -floo_req_t L2_ni_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_L2_ni_2_rsp; - -floo_req_t L2_ni_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_L2_ni_3_rsp; - -floo_req_t L2_ni_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_L2_ni_4_rsp; - -floo_req_t L2_ni_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_L2_ni_5_rsp; - -floo_req_t L2_ni_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_L2_ni_6_rsp; - -floo_req_t L2_ni_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_L2_ni_7_rsp; - -floo_req_t L2_ni_8_to_router_0_8_req; -floo_rsp_t router_0_8_to_L2_ni_8_rsp; - -floo_req_t L2_ni_9_to_router_0_9_req; -floo_rsp_t router_0_9_to_L2_ni_9_rsp; - -floo_req_t L2_ni_10_to_router_0_10_req; -floo_rsp_t router_0_10_to_L2_ni_10_rsp; - -floo_req_t L2_ni_11_to_router_0_11_req; -floo_rsp_t router_0_11_to_L2_ni_11_rsp; - -floo_req_t L2_ni_12_to_router_0_12_req; -floo_rsp_t router_0_12_to_L2_ni_12_rsp; - -floo_req_t L2_ni_13_to_router_0_13_req; -floo_rsp_t router_0_13_to_L2_ni_13_rsp; - -floo_req_t L2_ni_14_to_router_0_14_req; -floo_rsp_t router_0_14_to_L2_ni_14_rsp; - -floo_req_t L2_ni_15_to_router_0_15_req; -floo_rsp_t router_0_15_to_L2_ni_15_rsp; - -floo_req_t L2_ni_16_to_router_0_16_req; -floo_rsp_t router_0_16_to_L2_ni_16_rsp; - -floo_req_t L2_ni_17_to_router_0_17_req; -floo_rsp_t router_0_17_to_L2_ni_17_rsp; - -floo_req_t L2_ni_18_to_router_0_18_req; -floo_rsp_t router_0_18_to_L2_ni_18_rsp; - -floo_req_t L2_ni_19_to_router_0_19_req; -floo_rsp_t router_0_19_to_L2_ni_19_rsp; - -floo_req_t L2_ni_20_to_router_0_20_req; -floo_rsp_t router_0_20_to_L2_ni_20_rsp; - -floo_req_t L2_ni_21_to_router_0_21_req; -floo_rsp_t router_0_21_to_L2_ni_21_rsp; - -floo_req_t L2_ni_22_to_router_0_22_req; -floo_rsp_t router_0_22_to_L2_ni_22_rsp; - -floo_req_t L2_ni_23_to_router_0_23_req; -floo_rsp_t router_0_23_to_L2_ni_23_rsp; - -floo_req_t L2_ni_24_to_router_0_24_req; -floo_rsp_t router_0_24_to_L2_ni_24_rsp; - -floo_req_t L2_ni_25_to_router_0_25_req; -floo_rsp_t router_0_25_to_L2_ni_25_rsp; - -floo_req_t L2_ni_26_to_router_0_26_req; -floo_rsp_t router_0_26_to_L2_ni_26_rsp; - -floo_req_t L2_ni_27_to_router_0_27_req; -floo_rsp_t router_0_27_to_L2_ni_27_rsp; - -floo_req_t L2_ni_28_to_router_0_28_req; -floo_rsp_t router_0_28_to_L2_ni_28_rsp; - -floo_req_t L2_ni_29_to_router_0_29_req; -floo_rsp_t router_0_29_to_L2_ni_29_rsp; - -floo_req_t L2_ni_30_to_router_0_30_req; -floo_rsp_t router_0_30_to_L2_ni_30_rsp; - -floo_req_t L2_ni_31_to_router_0_31_req; -floo_rsp_t router_0_31_to_L2_ni_31_rsp; - - - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][0] ), - .id_i ( '{x: 1, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_magia_tile_ni_0_0_rsp ), - .floo_req_i ( router_0_0_to_magia_tile_ni_0_0_req ), - .floo_rsp_o ( magia_tile_ni_0_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][1] ), - .id_i ( '{x: 1, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_magia_tile_ni_0_1_rsp ), - .floo_req_i ( router_0_1_to_magia_tile_ni_0_1_req ), - .floo_rsp_o ( magia_tile_ni_0_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][2] ), - .id_i ( '{x: 1, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_magia_tile_ni_0_2_rsp ), - .floo_req_i ( router_0_2_to_magia_tile_ni_0_2_req ), - .floo_rsp_o ( magia_tile_ni_0_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][3] ), - .id_i ( '{x: 1, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_magia_tile_ni_0_3_rsp ), - .floo_req_i ( router_0_3_to_magia_tile_ni_0_3_req ), - .floo_rsp_o ( magia_tile_ni_0_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][4] ), - .id_i ( '{x: 1, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_magia_tile_ni_0_4_rsp ), - .floo_req_i ( router_0_4_to_magia_tile_ni_0_4_req ), - .floo_rsp_o ( magia_tile_ni_0_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][5] ), - .id_i ( '{x: 1, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_magia_tile_ni_0_5_rsp ), - .floo_req_i ( router_0_5_to_magia_tile_ni_0_5_req ), - .floo_rsp_o ( magia_tile_ni_0_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][6] ), - .id_i ( '{x: 1, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_magia_tile_ni_0_6_rsp ), - .floo_req_i ( router_0_6_to_magia_tile_ni_0_6_req ), - .floo_rsp_o ( magia_tile_ni_0_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][7] ), - .id_i ( '{x: 1, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_magia_tile_ni_0_7_rsp ), - .floo_req_i ( router_0_7_to_magia_tile_ni_0_7_req ), - .floo_rsp_o ( magia_tile_ni_0_7_to_router_0_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][8] ), - .id_i ( '{x: 1, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_8_to_router_0_8_req ), - .floo_rsp_i ( router_0_8_to_magia_tile_ni_0_8_rsp ), - .floo_req_i ( router_0_8_to_magia_tile_ni_0_8_req ), - .floo_rsp_o ( magia_tile_ni_0_8_to_router_0_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][9] ), - .id_i ( '{x: 1, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_9_to_router_0_9_req ), - .floo_rsp_i ( router_0_9_to_magia_tile_ni_0_9_rsp ), - .floo_req_i ( router_0_9_to_magia_tile_ni_0_9_req ), - .floo_rsp_o ( magia_tile_ni_0_9_to_router_0_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][10] ), - .id_i ( '{x: 1, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_10_to_router_0_10_req ), - .floo_rsp_i ( router_0_10_to_magia_tile_ni_0_10_rsp ), - .floo_req_i ( router_0_10_to_magia_tile_ni_0_10_req ), - .floo_rsp_o ( magia_tile_ni_0_10_to_router_0_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][11] ), - .id_i ( '{x: 1, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_11_to_router_0_11_req ), - .floo_rsp_i ( router_0_11_to_magia_tile_ni_0_11_rsp ), - .floo_req_i ( router_0_11_to_magia_tile_ni_0_11_req ), - .floo_rsp_o ( magia_tile_ni_0_11_to_router_0_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][12] ), - .id_i ( '{x: 1, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_12_to_router_0_12_req ), - .floo_rsp_i ( router_0_12_to_magia_tile_ni_0_12_rsp ), - .floo_req_i ( router_0_12_to_magia_tile_ni_0_12_req ), - .floo_rsp_o ( magia_tile_ni_0_12_to_router_0_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][13] ), - .id_i ( '{x: 1, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_13_to_router_0_13_req ), - .floo_rsp_i ( router_0_13_to_magia_tile_ni_0_13_rsp ), - .floo_req_i ( router_0_13_to_magia_tile_ni_0_13_req ), - .floo_rsp_o ( magia_tile_ni_0_13_to_router_0_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][14] ), - .id_i ( '{x: 1, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_14_to_router_0_14_req ), - .floo_rsp_i ( router_0_14_to_magia_tile_ni_0_14_rsp ), - .floo_req_i ( router_0_14_to_magia_tile_ni_0_14_req ), - .floo_rsp_o ( magia_tile_ni_0_14_to_router_0_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][15] ), - .id_i ( '{x: 1, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_15_to_router_0_15_req ), - .floo_rsp_i ( router_0_15_to_magia_tile_ni_0_15_rsp ), - .floo_req_i ( router_0_15_to_magia_tile_ni_0_15_req ), - .floo_rsp_o ( magia_tile_ni_0_15_to_router_0_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][16] ), - .id_i ( '{x: 1, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_16_to_router_0_16_req ), - .floo_rsp_i ( router_0_16_to_magia_tile_ni_0_16_rsp ), - .floo_req_i ( router_0_16_to_magia_tile_ni_0_16_req ), - .floo_rsp_o ( magia_tile_ni_0_16_to_router_0_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][17] ), - .id_i ( '{x: 1, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_17_to_router_0_17_req ), - .floo_rsp_i ( router_0_17_to_magia_tile_ni_0_17_rsp ), - .floo_req_i ( router_0_17_to_magia_tile_ni_0_17_req ), - .floo_rsp_o ( magia_tile_ni_0_17_to_router_0_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][18] ), - .id_i ( '{x: 1, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_18_to_router_0_18_req ), - .floo_rsp_i ( router_0_18_to_magia_tile_ni_0_18_rsp ), - .floo_req_i ( router_0_18_to_magia_tile_ni_0_18_req ), - .floo_rsp_o ( magia_tile_ni_0_18_to_router_0_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][19] ), - .id_i ( '{x: 1, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_19_to_router_0_19_req ), - .floo_rsp_i ( router_0_19_to_magia_tile_ni_0_19_rsp ), - .floo_req_i ( router_0_19_to_magia_tile_ni_0_19_req ), - .floo_rsp_o ( magia_tile_ni_0_19_to_router_0_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][20] ), - .id_i ( '{x: 1, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_20_to_router_0_20_req ), - .floo_rsp_i ( router_0_20_to_magia_tile_ni_0_20_rsp ), - .floo_req_i ( router_0_20_to_magia_tile_ni_0_20_req ), - .floo_rsp_o ( magia_tile_ni_0_20_to_router_0_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][21] ), - .id_i ( '{x: 1, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_21_to_router_0_21_req ), - .floo_rsp_i ( router_0_21_to_magia_tile_ni_0_21_rsp ), - .floo_req_i ( router_0_21_to_magia_tile_ni_0_21_req ), - .floo_rsp_o ( magia_tile_ni_0_21_to_router_0_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][22] ), - .id_i ( '{x: 1, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_22_to_router_0_22_req ), - .floo_rsp_i ( router_0_22_to_magia_tile_ni_0_22_rsp ), - .floo_req_i ( router_0_22_to_magia_tile_ni_0_22_req ), - .floo_rsp_o ( magia_tile_ni_0_22_to_router_0_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][23] ), - .id_i ( '{x: 1, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_23_to_router_0_23_req ), - .floo_rsp_i ( router_0_23_to_magia_tile_ni_0_23_rsp ), - .floo_req_i ( router_0_23_to_magia_tile_ni_0_23_req ), - .floo_rsp_o ( magia_tile_ni_0_23_to_router_0_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][24] ), - .id_i ( '{x: 1, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_24_to_router_0_24_req ), - .floo_rsp_i ( router_0_24_to_magia_tile_ni_0_24_rsp ), - .floo_req_i ( router_0_24_to_magia_tile_ni_0_24_req ), - .floo_rsp_o ( magia_tile_ni_0_24_to_router_0_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][25] ), - .id_i ( '{x: 1, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_25_to_router_0_25_req ), - .floo_rsp_i ( router_0_25_to_magia_tile_ni_0_25_rsp ), - .floo_req_i ( router_0_25_to_magia_tile_ni_0_25_req ), - .floo_rsp_o ( magia_tile_ni_0_25_to_router_0_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][26] ), - .id_i ( '{x: 1, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_26_to_router_0_26_req ), - .floo_rsp_i ( router_0_26_to_magia_tile_ni_0_26_rsp ), - .floo_req_i ( router_0_26_to_magia_tile_ni_0_26_req ), - .floo_rsp_o ( magia_tile_ni_0_26_to_router_0_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][27] ), - .id_i ( '{x: 1, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_27_to_router_0_27_req ), - .floo_rsp_i ( router_0_27_to_magia_tile_ni_0_27_rsp ), - .floo_req_i ( router_0_27_to_magia_tile_ni_0_27_req ), - .floo_rsp_o ( magia_tile_ni_0_27_to_router_0_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][28] ), - .id_i ( '{x: 1, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_28_to_router_0_28_req ), - .floo_rsp_i ( router_0_28_to_magia_tile_ni_0_28_rsp ), - .floo_req_i ( router_0_28_to_magia_tile_ni_0_28_req ), - .floo_rsp_o ( magia_tile_ni_0_28_to_router_0_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][29] ), - .id_i ( '{x: 1, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_29_to_router_0_29_req ), - .floo_rsp_i ( router_0_29_to_magia_tile_ni_0_29_rsp ), - .floo_req_i ( router_0_29_to_magia_tile_ni_0_29_req ), - .floo_rsp_o ( magia_tile_ni_0_29_to_router_0_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][30] ), - .id_i ( '{x: 1, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_30_to_router_0_30_req ), - .floo_rsp_i ( router_0_30_to_magia_tile_ni_0_30_rsp ), - .floo_req_i ( router_0_30_to_magia_tile_ni_0_30_req ), - .floo_rsp_o ( magia_tile_ni_0_30_to_router_0_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][31] ), - .id_i ( '{x: 1, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_31_to_router_0_31_req ), - .floo_rsp_i ( router_0_31_to_magia_tile_ni_0_31_rsp ), - .floo_req_i ( router_0_31_to_magia_tile_ni_0_31_req ), - .floo_rsp_o ( magia_tile_ni_0_31_to_router_0_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][0] ), - .id_i ( '{x: 2, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_0_to_router_1_0_req ), - .floo_rsp_i ( router_1_0_to_magia_tile_ni_1_0_rsp ), - .floo_req_i ( router_1_0_to_magia_tile_ni_1_0_req ), - .floo_rsp_o ( magia_tile_ni_1_0_to_router_1_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][1] ), - .id_i ( '{x: 2, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_1_to_router_1_1_req ), - .floo_rsp_i ( router_1_1_to_magia_tile_ni_1_1_rsp ), - .floo_req_i ( router_1_1_to_magia_tile_ni_1_1_req ), - .floo_rsp_o ( magia_tile_ni_1_1_to_router_1_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][2] ), - .id_i ( '{x: 2, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_2_to_router_1_2_req ), - .floo_rsp_i ( router_1_2_to_magia_tile_ni_1_2_rsp ), - .floo_req_i ( router_1_2_to_magia_tile_ni_1_2_req ), - .floo_rsp_o ( magia_tile_ni_1_2_to_router_1_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][3] ), - .id_i ( '{x: 2, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_3_to_router_1_3_req ), - .floo_rsp_i ( router_1_3_to_magia_tile_ni_1_3_rsp ), - .floo_req_i ( router_1_3_to_magia_tile_ni_1_3_req ), - .floo_rsp_o ( magia_tile_ni_1_3_to_router_1_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][4] ), - .id_i ( '{x: 2, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_4_to_router_1_4_req ), - .floo_rsp_i ( router_1_4_to_magia_tile_ni_1_4_rsp ), - .floo_req_i ( router_1_4_to_magia_tile_ni_1_4_req ), - .floo_rsp_o ( magia_tile_ni_1_4_to_router_1_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][5] ), - .id_i ( '{x: 2, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_5_to_router_1_5_req ), - .floo_rsp_i ( router_1_5_to_magia_tile_ni_1_5_rsp ), - .floo_req_i ( router_1_5_to_magia_tile_ni_1_5_req ), - .floo_rsp_o ( magia_tile_ni_1_5_to_router_1_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][6] ), - .id_i ( '{x: 2, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_6_to_router_1_6_req ), - .floo_rsp_i ( router_1_6_to_magia_tile_ni_1_6_rsp ), - .floo_req_i ( router_1_6_to_magia_tile_ni_1_6_req ), - .floo_rsp_o ( magia_tile_ni_1_6_to_router_1_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][7] ), - .id_i ( '{x: 2, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_7_to_router_1_7_req ), - .floo_rsp_i ( router_1_7_to_magia_tile_ni_1_7_rsp ), - .floo_req_i ( router_1_7_to_magia_tile_ni_1_7_req ), - .floo_rsp_o ( magia_tile_ni_1_7_to_router_1_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][8] ), - .id_i ( '{x: 2, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_8_to_router_1_8_req ), - .floo_rsp_i ( router_1_8_to_magia_tile_ni_1_8_rsp ), - .floo_req_i ( router_1_8_to_magia_tile_ni_1_8_req ), - .floo_rsp_o ( magia_tile_ni_1_8_to_router_1_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][9] ), - .id_i ( '{x: 2, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_9_to_router_1_9_req ), - .floo_rsp_i ( router_1_9_to_magia_tile_ni_1_9_rsp ), - .floo_req_i ( router_1_9_to_magia_tile_ni_1_9_req ), - .floo_rsp_o ( magia_tile_ni_1_9_to_router_1_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][10] ), - .id_i ( '{x: 2, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_10_to_router_1_10_req ), - .floo_rsp_i ( router_1_10_to_magia_tile_ni_1_10_rsp ), - .floo_req_i ( router_1_10_to_magia_tile_ni_1_10_req ), - .floo_rsp_o ( magia_tile_ni_1_10_to_router_1_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][11] ), - .id_i ( '{x: 2, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_11_to_router_1_11_req ), - .floo_rsp_i ( router_1_11_to_magia_tile_ni_1_11_rsp ), - .floo_req_i ( router_1_11_to_magia_tile_ni_1_11_req ), - .floo_rsp_o ( magia_tile_ni_1_11_to_router_1_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][12] ), - .id_i ( '{x: 2, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_12_to_router_1_12_req ), - .floo_rsp_i ( router_1_12_to_magia_tile_ni_1_12_rsp ), - .floo_req_i ( router_1_12_to_magia_tile_ni_1_12_req ), - .floo_rsp_o ( magia_tile_ni_1_12_to_router_1_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][13] ), - .id_i ( '{x: 2, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_13_to_router_1_13_req ), - .floo_rsp_i ( router_1_13_to_magia_tile_ni_1_13_rsp ), - .floo_req_i ( router_1_13_to_magia_tile_ni_1_13_req ), - .floo_rsp_o ( magia_tile_ni_1_13_to_router_1_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][14] ), - .id_i ( '{x: 2, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_14_to_router_1_14_req ), - .floo_rsp_i ( router_1_14_to_magia_tile_ni_1_14_rsp ), - .floo_req_i ( router_1_14_to_magia_tile_ni_1_14_req ), - .floo_rsp_o ( magia_tile_ni_1_14_to_router_1_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][15] ), - .id_i ( '{x: 2, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_15_to_router_1_15_req ), - .floo_rsp_i ( router_1_15_to_magia_tile_ni_1_15_rsp ), - .floo_req_i ( router_1_15_to_magia_tile_ni_1_15_req ), - .floo_rsp_o ( magia_tile_ni_1_15_to_router_1_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][16] ), - .id_i ( '{x: 2, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_16_to_router_1_16_req ), - .floo_rsp_i ( router_1_16_to_magia_tile_ni_1_16_rsp ), - .floo_req_i ( router_1_16_to_magia_tile_ni_1_16_req ), - .floo_rsp_o ( magia_tile_ni_1_16_to_router_1_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][17] ), - .id_i ( '{x: 2, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_17_to_router_1_17_req ), - .floo_rsp_i ( router_1_17_to_magia_tile_ni_1_17_rsp ), - .floo_req_i ( router_1_17_to_magia_tile_ni_1_17_req ), - .floo_rsp_o ( magia_tile_ni_1_17_to_router_1_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][18] ), - .id_i ( '{x: 2, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_18_to_router_1_18_req ), - .floo_rsp_i ( router_1_18_to_magia_tile_ni_1_18_rsp ), - .floo_req_i ( router_1_18_to_magia_tile_ni_1_18_req ), - .floo_rsp_o ( magia_tile_ni_1_18_to_router_1_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][19] ), - .id_i ( '{x: 2, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_19_to_router_1_19_req ), - .floo_rsp_i ( router_1_19_to_magia_tile_ni_1_19_rsp ), - .floo_req_i ( router_1_19_to_magia_tile_ni_1_19_req ), - .floo_rsp_o ( magia_tile_ni_1_19_to_router_1_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][20] ), - .id_i ( '{x: 2, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_20_to_router_1_20_req ), - .floo_rsp_i ( router_1_20_to_magia_tile_ni_1_20_rsp ), - .floo_req_i ( router_1_20_to_magia_tile_ni_1_20_req ), - .floo_rsp_o ( magia_tile_ni_1_20_to_router_1_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][21] ), - .id_i ( '{x: 2, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_21_to_router_1_21_req ), - .floo_rsp_i ( router_1_21_to_magia_tile_ni_1_21_rsp ), - .floo_req_i ( router_1_21_to_magia_tile_ni_1_21_req ), - .floo_rsp_o ( magia_tile_ni_1_21_to_router_1_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][22] ), - .id_i ( '{x: 2, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_22_to_router_1_22_req ), - .floo_rsp_i ( router_1_22_to_magia_tile_ni_1_22_rsp ), - .floo_req_i ( router_1_22_to_magia_tile_ni_1_22_req ), - .floo_rsp_o ( magia_tile_ni_1_22_to_router_1_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][23] ), - .id_i ( '{x: 2, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_23_to_router_1_23_req ), - .floo_rsp_i ( router_1_23_to_magia_tile_ni_1_23_rsp ), - .floo_req_i ( router_1_23_to_magia_tile_ni_1_23_req ), - .floo_rsp_o ( magia_tile_ni_1_23_to_router_1_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][24] ), - .id_i ( '{x: 2, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_24_to_router_1_24_req ), - .floo_rsp_i ( router_1_24_to_magia_tile_ni_1_24_rsp ), - .floo_req_i ( router_1_24_to_magia_tile_ni_1_24_req ), - .floo_rsp_o ( magia_tile_ni_1_24_to_router_1_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][25] ), - .id_i ( '{x: 2, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_25_to_router_1_25_req ), - .floo_rsp_i ( router_1_25_to_magia_tile_ni_1_25_rsp ), - .floo_req_i ( router_1_25_to_magia_tile_ni_1_25_req ), - .floo_rsp_o ( magia_tile_ni_1_25_to_router_1_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][26] ), - .id_i ( '{x: 2, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_26_to_router_1_26_req ), - .floo_rsp_i ( router_1_26_to_magia_tile_ni_1_26_rsp ), - .floo_req_i ( router_1_26_to_magia_tile_ni_1_26_req ), - .floo_rsp_o ( magia_tile_ni_1_26_to_router_1_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][27] ), - .id_i ( '{x: 2, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_27_to_router_1_27_req ), - .floo_rsp_i ( router_1_27_to_magia_tile_ni_1_27_rsp ), - .floo_req_i ( router_1_27_to_magia_tile_ni_1_27_req ), - .floo_rsp_o ( magia_tile_ni_1_27_to_router_1_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][28] ), - .id_i ( '{x: 2, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_28_to_router_1_28_req ), - .floo_rsp_i ( router_1_28_to_magia_tile_ni_1_28_rsp ), - .floo_req_i ( router_1_28_to_magia_tile_ni_1_28_req ), - .floo_rsp_o ( magia_tile_ni_1_28_to_router_1_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][29] ), - .id_i ( '{x: 2, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_29_to_router_1_29_req ), - .floo_rsp_i ( router_1_29_to_magia_tile_ni_1_29_rsp ), - .floo_req_i ( router_1_29_to_magia_tile_ni_1_29_req ), - .floo_rsp_o ( magia_tile_ni_1_29_to_router_1_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][30] ), - .id_i ( '{x: 2, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_30_to_router_1_30_req ), - .floo_rsp_i ( router_1_30_to_magia_tile_ni_1_30_rsp ), - .floo_req_i ( router_1_30_to_magia_tile_ni_1_30_req ), - .floo_rsp_o ( magia_tile_ni_1_30_to_router_1_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][31] ), - .id_i ( '{x: 2, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_31_to_router_1_31_req ), - .floo_rsp_i ( router_1_31_to_magia_tile_ni_1_31_rsp ), - .floo_req_i ( router_1_31_to_magia_tile_ni_1_31_req ), - .floo_rsp_o ( magia_tile_ni_1_31_to_router_1_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][0] ), - .id_i ( '{x: 3, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_0_to_router_2_0_req ), - .floo_rsp_i ( router_2_0_to_magia_tile_ni_2_0_rsp ), - .floo_req_i ( router_2_0_to_magia_tile_ni_2_0_req ), - .floo_rsp_o ( magia_tile_ni_2_0_to_router_2_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][1] ), - .id_i ( '{x: 3, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_1_to_router_2_1_req ), - .floo_rsp_i ( router_2_1_to_magia_tile_ni_2_1_rsp ), - .floo_req_i ( router_2_1_to_magia_tile_ni_2_1_req ), - .floo_rsp_o ( magia_tile_ni_2_1_to_router_2_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][2] ), - .id_i ( '{x: 3, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_2_to_router_2_2_req ), - .floo_rsp_i ( router_2_2_to_magia_tile_ni_2_2_rsp ), - .floo_req_i ( router_2_2_to_magia_tile_ni_2_2_req ), - .floo_rsp_o ( magia_tile_ni_2_2_to_router_2_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][3] ), - .id_i ( '{x: 3, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_3_to_router_2_3_req ), - .floo_rsp_i ( router_2_3_to_magia_tile_ni_2_3_rsp ), - .floo_req_i ( router_2_3_to_magia_tile_ni_2_3_req ), - .floo_rsp_o ( magia_tile_ni_2_3_to_router_2_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][4] ), - .id_i ( '{x: 3, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_4_to_router_2_4_req ), - .floo_rsp_i ( router_2_4_to_magia_tile_ni_2_4_rsp ), - .floo_req_i ( router_2_4_to_magia_tile_ni_2_4_req ), - .floo_rsp_o ( magia_tile_ni_2_4_to_router_2_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][5] ), - .id_i ( '{x: 3, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_5_to_router_2_5_req ), - .floo_rsp_i ( router_2_5_to_magia_tile_ni_2_5_rsp ), - .floo_req_i ( router_2_5_to_magia_tile_ni_2_5_req ), - .floo_rsp_o ( magia_tile_ni_2_5_to_router_2_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][6] ), - .id_i ( '{x: 3, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_6_to_router_2_6_req ), - .floo_rsp_i ( router_2_6_to_magia_tile_ni_2_6_rsp ), - .floo_req_i ( router_2_6_to_magia_tile_ni_2_6_req ), - .floo_rsp_o ( magia_tile_ni_2_6_to_router_2_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][7] ), - .id_i ( '{x: 3, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_7_to_router_2_7_req ), - .floo_rsp_i ( router_2_7_to_magia_tile_ni_2_7_rsp ), - .floo_req_i ( router_2_7_to_magia_tile_ni_2_7_req ), - .floo_rsp_o ( magia_tile_ni_2_7_to_router_2_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][8] ), - .id_i ( '{x: 3, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_8_to_router_2_8_req ), - .floo_rsp_i ( router_2_8_to_magia_tile_ni_2_8_rsp ), - .floo_req_i ( router_2_8_to_magia_tile_ni_2_8_req ), - .floo_rsp_o ( magia_tile_ni_2_8_to_router_2_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][9] ), - .id_i ( '{x: 3, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_9_to_router_2_9_req ), - .floo_rsp_i ( router_2_9_to_magia_tile_ni_2_9_rsp ), - .floo_req_i ( router_2_9_to_magia_tile_ni_2_9_req ), - .floo_rsp_o ( magia_tile_ni_2_9_to_router_2_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][10] ), - .id_i ( '{x: 3, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_10_to_router_2_10_req ), - .floo_rsp_i ( router_2_10_to_magia_tile_ni_2_10_rsp ), - .floo_req_i ( router_2_10_to_magia_tile_ni_2_10_req ), - .floo_rsp_o ( magia_tile_ni_2_10_to_router_2_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][11] ), - .id_i ( '{x: 3, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_11_to_router_2_11_req ), - .floo_rsp_i ( router_2_11_to_magia_tile_ni_2_11_rsp ), - .floo_req_i ( router_2_11_to_magia_tile_ni_2_11_req ), - .floo_rsp_o ( magia_tile_ni_2_11_to_router_2_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][12] ), - .id_i ( '{x: 3, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_12_to_router_2_12_req ), - .floo_rsp_i ( router_2_12_to_magia_tile_ni_2_12_rsp ), - .floo_req_i ( router_2_12_to_magia_tile_ni_2_12_req ), - .floo_rsp_o ( magia_tile_ni_2_12_to_router_2_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][13] ), - .id_i ( '{x: 3, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_13_to_router_2_13_req ), - .floo_rsp_i ( router_2_13_to_magia_tile_ni_2_13_rsp ), - .floo_req_i ( router_2_13_to_magia_tile_ni_2_13_req ), - .floo_rsp_o ( magia_tile_ni_2_13_to_router_2_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][14] ), - .id_i ( '{x: 3, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_14_to_router_2_14_req ), - .floo_rsp_i ( router_2_14_to_magia_tile_ni_2_14_rsp ), - .floo_req_i ( router_2_14_to_magia_tile_ni_2_14_req ), - .floo_rsp_o ( magia_tile_ni_2_14_to_router_2_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][15] ), - .id_i ( '{x: 3, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_15_to_router_2_15_req ), - .floo_rsp_i ( router_2_15_to_magia_tile_ni_2_15_rsp ), - .floo_req_i ( router_2_15_to_magia_tile_ni_2_15_req ), - .floo_rsp_o ( magia_tile_ni_2_15_to_router_2_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][16] ), - .id_i ( '{x: 3, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_16_to_router_2_16_req ), - .floo_rsp_i ( router_2_16_to_magia_tile_ni_2_16_rsp ), - .floo_req_i ( router_2_16_to_magia_tile_ni_2_16_req ), - .floo_rsp_o ( magia_tile_ni_2_16_to_router_2_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][17] ), - .id_i ( '{x: 3, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_17_to_router_2_17_req ), - .floo_rsp_i ( router_2_17_to_magia_tile_ni_2_17_rsp ), - .floo_req_i ( router_2_17_to_magia_tile_ni_2_17_req ), - .floo_rsp_o ( magia_tile_ni_2_17_to_router_2_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][18] ), - .id_i ( '{x: 3, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_18_to_router_2_18_req ), - .floo_rsp_i ( router_2_18_to_magia_tile_ni_2_18_rsp ), - .floo_req_i ( router_2_18_to_magia_tile_ni_2_18_req ), - .floo_rsp_o ( magia_tile_ni_2_18_to_router_2_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][19] ), - .id_i ( '{x: 3, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_19_to_router_2_19_req ), - .floo_rsp_i ( router_2_19_to_magia_tile_ni_2_19_rsp ), - .floo_req_i ( router_2_19_to_magia_tile_ni_2_19_req ), - .floo_rsp_o ( magia_tile_ni_2_19_to_router_2_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][20] ), - .id_i ( '{x: 3, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_20_to_router_2_20_req ), - .floo_rsp_i ( router_2_20_to_magia_tile_ni_2_20_rsp ), - .floo_req_i ( router_2_20_to_magia_tile_ni_2_20_req ), - .floo_rsp_o ( magia_tile_ni_2_20_to_router_2_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][21] ), - .id_i ( '{x: 3, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_21_to_router_2_21_req ), - .floo_rsp_i ( router_2_21_to_magia_tile_ni_2_21_rsp ), - .floo_req_i ( router_2_21_to_magia_tile_ni_2_21_req ), - .floo_rsp_o ( magia_tile_ni_2_21_to_router_2_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][22] ), - .id_i ( '{x: 3, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_22_to_router_2_22_req ), - .floo_rsp_i ( router_2_22_to_magia_tile_ni_2_22_rsp ), - .floo_req_i ( router_2_22_to_magia_tile_ni_2_22_req ), - .floo_rsp_o ( magia_tile_ni_2_22_to_router_2_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][23] ), - .id_i ( '{x: 3, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_23_to_router_2_23_req ), - .floo_rsp_i ( router_2_23_to_magia_tile_ni_2_23_rsp ), - .floo_req_i ( router_2_23_to_magia_tile_ni_2_23_req ), - .floo_rsp_o ( magia_tile_ni_2_23_to_router_2_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][24] ), - .id_i ( '{x: 3, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_24_to_router_2_24_req ), - .floo_rsp_i ( router_2_24_to_magia_tile_ni_2_24_rsp ), - .floo_req_i ( router_2_24_to_magia_tile_ni_2_24_req ), - .floo_rsp_o ( magia_tile_ni_2_24_to_router_2_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][25] ), - .id_i ( '{x: 3, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_25_to_router_2_25_req ), - .floo_rsp_i ( router_2_25_to_magia_tile_ni_2_25_rsp ), - .floo_req_i ( router_2_25_to_magia_tile_ni_2_25_req ), - .floo_rsp_o ( magia_tile_ni_2_25_to_router_2_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][26] ), - .id_i ( '{x: 3, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_26_to_router_2_26_req ), - .floo_rsp_i ( router_2_26_to_magia_tile_ni_2_26_rsp ), - .floo_req_i ( router_2_26_to_magia_tile_ni_2_26_req ), - .floo_rsp_o ( magia_tile_ni_2_26_to_router_2_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][27] ), - .id_i ( '{x: 3, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_27_to_router_2_27_req ), - .floo_rsp_i ( router_2_27_to_magia_tile_ni_2_27_rsp ), - .floo_req_i ( router_2_27_to_magia_tile_ni_2_27_req ), - .floo_rsp_o ( magia_tile_ni_2_27_to_router_2_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][28] ), - .id_i ( '{x: 3, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_28_to_router_2_28_req ), - .floo_rsp_i ( router_2_28_to_magia_tile_ni_2_28_rsp ), - .floo_req_i ( router_2_28_to_magia_tile_ni_2_28_req ), - .floo_rsp_o ( magia_tile_ni_2_28_to_router_2_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][29] ), - .id_i ( '{x: 3, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_29_to_router_2_29_req ), - .floo_rsp_i ( router_2_29_to_magia_tile_ni_2_29_rsp ), - .floo_req_i ( router_2_29_to_magia_tile_ni_2_29_req ), - .floo_rsp_o ( magia_tile_ni_2_29_to_router_2_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][30] ), - .id_i ( '{x: 3, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_30_to_router_2_30_req ), - .floo_rsp_i ( router_2_30_to_magia_tile_ni_2_30_rsp ), - .floo_req_i ( router_2_30_to_magia_tile_ni_2_30_req ), - .floo_rsp_o ( magia_tile_ni_2_30_to_router_2_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][31] ), - .id_i ( '{x: 3, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_31_to_router_2_31_req ), - .floo_rsp_i ( router_2_31_to_magia_tile_ni_2_31_rsp ), - .floo_req_i ( router_2_31_to_magia_tile_ni_2_31_req ), - .floo_rsp_o ( magia_tile_ni_2_31_to_router_2_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][0] ), - .id_i ( '{x: 4, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_0_to_router_3_0_req ), - .floo_rsp_i ( router_3_0_to_magia_tile_ni_3_0_rsp ), - .floo_req_i ( router_3_0_to_magia_tile_ni_3_0_req ), - .floo_rsp_o ( magia_tile_ni_3_0_to_router_3_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][1] ), - .id_i ( '{x: 4, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_1_to_router_3_1_req ), - .floo_rsp_i ( router_3_1_to_magia_tile_ni_3_1_rsp ), - .floo_req_i ( router_3_1_to_magia_tile_ni_3_1_req ), - .floo_rsp_o ( magia_tile_ni_3_1_to_router_3_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][2] ), - .id_i ( '{x: 4, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_2_to_router_3_2_req ), - .floo_rsp_i ( router_3_2_to_magia_tile_ni_3_2_rsp ), - .floo_req_i ( router_3_2_to_magia_tile_ni_3_2_req ), - .floo_rsp_o ( magia_tile_ni_3_2_to_router_3_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][3] ), - .id_i ( '{x: 4, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_3_to_router_3_3_req ), - .floo_rsp_i ( router_3_3_to_magia_tile_ni_3_3_rsp ), - .floo_req_i ( router_3_3_to_magia_tile_ni_3_3_req ), - .floo_rsp_o ( magia_tile_ni_3_3_to_router_3_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][4] ), - .id_i ( '{x: 4, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_4_to_router_3_4_req ), - .floo_rsp_i ( router_3_4_to_magia_tile_ni_3_4_rsp ), - .floo_req_i ( router_3_4_to_magia_tile_ni_3_4_req ), - .floo_rsp_o ( magia_tile_ni_3_4_to_router_3_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][5] ), - .id_i ( '{x: 4, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_5_to_router_3_5_req ), - .floo_rsp_i ( router_3_5_to_magia_tile_ni_3_5_rsp ), - .floo_req_i ( router_3_5_to_magia_tile_ni_3_5_req ), - .floo_rsp_o ( magia_tile_ni_3_5_to_router_3_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][6] ), - .id_i ( '{x: 4, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_6_to_router_3_6_req ), - .floo_rsp_i ( router_3_6_to_magia_tile_ni_3_6_rsp ), - .floo_req_i ( router_3_6_to_magia_tile_ni_3_6_req ), - .floo_rsp_o ( magia_tile_ni_3_6_to_router_3_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][7] ), - .id_i ( '{x: 4, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_7_to_router_3_7_req ), - .floo_rsp_i ( router_3_7_to_magia_tile_ni_3_7_rsp ), - .floo_req_i ( router_3_7_to_magia_tile_ni_3_7_req ), - .floo_rsp_o ( magia_tile_ni_3_7_to_router_3_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][8] ), - .id_i ( '{x: 4, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_8_to_router_3_8_req ), - .floo_rsp_i ( router_3_8_to_magia_tile_ni_3_8_rsp ), - .floo_req_i ( router_3_8_to_magia_tile_ni_3_8_req ), - .floo_rsp_o ( magia_tile_ni_3_8_to_router_3_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][9] ), - .id_i ( '{x: 4, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_9_to_router_3_9_req ), - .floo_rsp_i ( router_3_9_to_magia_tile_ni_3_9_rsp ), - .floo_req_i ( router_3_9_to_magia_tile_ni_3_9_req ), - .floo_rsp_o ( magia_tile_ni_3_9_to_router_3_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][10] ), - .id_i ( '{x: 4, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_10_to_router_3_10_req ), - .floo_rsp_i ( router_3_10_to_magia_tile_ni_3_10_rsp ), - .floo_req_i ( router_3_10_to_magia_tile_ni_3_10_req ), - .floo_rsp_o ( magia_tile_ni_3_10_to_router_3_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][11] ), - .id_i ( '{x: 4, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_11_to_router_3_11_req ), - .floo_rsp_i ( router_3_11_to_magia_tile_ni_3_11_rsp ), - .floo_req_i ( router_3_11_to_magia_tile_ni_3_11_req ), - .floo_rsp_o ( magia_tile_ni_3_11_to_router_3_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][12] ), - .id_i ( '{x: 4, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_12_to_router_3_12_req ), - .floo_rsp_i ( router_3_12_to_magia_tile_ni_3_12_rsp ), - .floo_req_i ( router_3_12_to_magia_tile_ni_3_12_req ), - .floo_rsp_o ( magia_tile_ni_3_12_to_router_3_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][13] ), - .id_i ( '{x: 4, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_13_to_router_3_13_req ), - .floo_rsp_i ( router_3_13_to_magia_tile_ni_3_13_rsp ), - .floo_req_i ( router_3_13_to_magia_tile_ni_3_13_req ), - .floo_rsp_o ( magia_tile_ni_3_13_to_router_3_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][14] ), - .id_i ( '{x: 4, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_14_to_router_3_14_req ), - .floo_rsp_i ( router_3_14_to_magia_tile_ni_3_14_rsp ), - .floo_req_i ( router_3_14_to_magia_tile_ni_3_14_req ), - .floo_rsp_o ( magia_tile_ni_3_14_to_router_3_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][15] ), - .id_i ( '{x: 4, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_15_to_router_3_15_req ), - .floo_rsp_i ( router_3_15_to_magia_tile_ni_3_15_rsp ), - .floo_req_i ( router_3_15_to_magia_tile_ni_3_15_req ), - .floo_rsp_o ( magia_tile_ni_3_15_to_router_3_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][16] ), - .id_i ( '{x: 4, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_16_to_router_3_16_req ), - .floo_rsp_i ( router_3_16_to_magia_tile_ni_3_16_rsp ), - .floo_req_i ( router_3_16_to_magia_tile_ni_3_16_req ), - .floo_rsp_o ( magia_tile_ni_3_16_to_router_3_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][17] ), - .id_i ( '{x: 4, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_17_to_router_3_17_req ), - .floo_rsp_i ( router_3_17_to_magia_tile_ni_3_17_rsp ), - .floo_req_i ( router_3_17_to_magia_tile_ni_3_17_req ), - .floo_rsp_o ( magia_tile_ni_3_17_to_router_3_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][18] ), - .id_i ( '{x: 4, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_18_to_router_3_18_req ), - .floo_rsp_i ( router_3_18_to_magia_tile_ni_3_18_rsp ), - .floo_req_i ( router_3_18_to_magia_tile_ni_3_18_req ), - .floo_rsp_o ( magia_tile_ni_3_18_to_router_3_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][19] ), - .id_i ( '{x: 4, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_19_to_router_3_19_req ), - .floo_rsp_i ( router_3_19_to_magia_tile_ni_3_19_rsp ), - .floo_req_i ( router_3_19_to_magia_tile_ni_3_19_req ), - .floo_rsp_o ( magia_tile_ni_3_19_to_router_3_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][20] ), - .id_i ( '{x: 4, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_20_to_router_3_20_req ), - .floo_rsp_i ( router_3_20_to_magia_tile_ni_3_20_rsp ), - .floo_req_i ( router_3_20_to_magia_tile_ni_3_20_req ), - .floo_rsp_o ( magia_tile_ni_3_20_to_router_3_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][21] ), - .id_i ( '{x: 4, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_21_to_router_3_21_req ), - .floo_rsp_i ( router_3_21_to_magia_tile_ni_3_21_rsp ), - .floo_req_i ( router_3_21_to_magia_tile_ni_3_21_req ), - .floo_rsp_o ( magia_tile_ni_3_21_to_router_3_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][22] ), - .id_i ( '{x: 4, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_22_to_router_3_22_req ), - .floo_rsp_i ( router_3_22_to_magia_tile_ni_3_22_rsp ), - .floo_req_i ( router_3_22_to_magia_tile_ni_3_22_req ), - .floo_rsp_o ( magia_tile_ni_3_22_to_router_3_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][23] ), - .id_i ( '{x: 4, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_23_to_router_3_23_req ), - .floo_rsp_i ( router_3_23_to_magia_tile_ni_3_23_rsp ), - .floo_req_i ( router_3_23_to_magia_tile_ni_3_23_req ), - .floo_rsp_o ( magia_tile_ni_3_23_to_router_3_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][24] ), - .id_i ( '{x: 4, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_24_to_router_3_24_req ), - .floo_rsp_i ( router_3_24_to_magia_tile_ni_3_24_rsp ), - .floo_req_i ( router_3_24_to_magia_tile_ni_3_24_req ), - .floo_rsp_o ( magia_tile_ni_3_24_to_router_3_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][25] ), - .id_i ( '{x: 4, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_25_to_router_3_25_req ), - .floo_rsp_i ( router_3_25_to_magia_tile_ni_3_25_rsp ), - .floo_req_i ( router_3_25_to_magia_tile_ni_3_25_req ), - .floo_rsp_o ( magia_tile_ni_3_25_to_router_3_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][26] ), - .id_i ( '{x: 4, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_26_to_router_3_26_req ), - .floo_rsp_i ( router_3_26_to_magia_tile_ni_3_26_rsp ), - .floo_req_i ( router_3_26_to_magia_tile_ni_3_26_req ), - .floo_rsp_o ( magia_tile_ni_3_26_to_router_3_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][27] ), - .id_i ( '{x: 4, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_27_to_router_3_27_req ), - .floo_rsp_i ( router_3_27_to_magia_tile_ni_3_27_rsp ), - .floo_req_i ( router_3_27_to_magia_tile_ni_3_27_req ), - .floo_rsp_o ( magia_tile_ni_3_27_to_router_3_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][28] ), - .id_i ( '{x: 4, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_28_to_router_3_28_req ), - .floo_rsp_i ( router_3_28_to_magia_tile_ni_3_28_rsp ), - .floo_req_i ( router_3_28_to_magia_tile_ni_3_28_req ), - .floo_rsp_o ( magia_tile_ni_3_28_to_router_3_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][29] ), - .id_i ( '{x: 4, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_29_to_router_3_29_req ), - .floo_rsp_i ( router_3_29_to_magia_tile_ni_3_29_rsp ), - .floo_req_i ( router_3_29_to_magia_tile_ni_3_29_req ), - .floo_rsp_o ( magia_tile_ni_3_29_to_router_3_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][30] ), - .id_i ( '{x: 4, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_30_to_router_3_30_req ), - .floo_rsp_i ( router_3_30_to_magia_tile_ni_3_30_rsp ), - .floo_req_i ( router_3_30_to_magia_tile_ni_3_30_req ), - .floo_rsp_o ( magia_tile_ni_3_30_to_router_3_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][31] ), - .id_i ( '{x: 4, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_31_to_router_3_31_req ), - .floo_rsp_i ( router_3_31_to_magia_tile_ni_3_31_rsp ), - .floo_req_i ( router_3_31_to_magia_tile_ni_3_31_req ), - .floo_rsp_o ( magia_tile_ni_3_31_to_router_3_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][0] ), - .id_i ( '{x: 5, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_0_to_router_4_0_req ), - .floo_rsp_i ( router_4_0_to_magia_tile_ni_4_0_rsp ), - .floo_req_i ( router_4_0_to_magia_tile_ni_4_0_req ), - .floo_rsp_o ( magia_tile_ni_4_0_to_router_4_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][1] ), - .id_i ( '{x: 5, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_1_to_router_4_1_req ), - .floo_rsp_i ( router_4_1_to_magia_tile_ni_4_1_rsp ), - .floo_req_i ( router_4_1_to_magia_tile_ni_4_1_req ), - .floo_rsp_o ( magia_tile_ni_4_1_to_router_4_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][2] ), - .id_i ( '{x: 5, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_2_to_router_4_2_req ), - .floo_rsp_i ( router_4_2_to_magia_tile_ni_4_2_rsp ), - .floo_req_i ( router_4_2_to_magia_tile_ni_4_2_req ), - .floo_rsp_o ( magia_tile_ni_4_2_to_router_4_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][3] ), - .id_i ( '{x: 5, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_3_to_router_4_3_req ), - .floo_rsp_i ( router_4_3_to_magia_tile_ni_4_3_rsp ), - .floo_req_i ( router_4_3_to_magia_tile_ni_4_3_req ), - .floo_rsp_o ( magia_tile_ni_4_3_to_router_4_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][4] ), - .id_i ( '{x: 5, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_4_to_router_4_4_req ), - .floo_rsp_i ( router_4_4_to_magia_tile_ni_4_4_rsp ), - .floo_req_i ( router_4_4_to_magia_tile_ni_4_4_req ), - .floo_rsp_o ( magia_tile_ni_4_4_to_router_4_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][5] ), - .id_i ( '{x: 5, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_5_to_router_4_5_req ), - .floo_rsp_i ( router_4_5_to_magia_tile_ni_4_5_rsp ), - .floo_req_i ( router_4_5_to_magia_tile_ni_4_5_req ), - .floo_rsp_o ( magia_tile_ni_4_5_to_router_4_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][6] ), - .id_i ( '{x: 5, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_6_to_router_4_6_req ), - .floo_rsp_i ( router_4_6_to_magia_tile_ni_4_6_rsp ), - .floo_req_i ( router_4_6_to_magia_tile_ni_4_6_req ), - .floo_rsp_o ( magia_tile_ni_4_6_to_router_4_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][7] ), - .id_i ( '{x: 5, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_7_to_router_4_7_req ), - .floo_rsp_i ( router_4_7_to_magia_tile_ni_4_7_rsp ), - .floo_req_i ( router_4_7_to_magia_tile_ni_4_7_req ), - .floo_rsp_o ( magia_tile_ni_4_7_to_router_4_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][8] ), - .id_i ( '{x: 5, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_8_to_router_4_8_req ), - .floo_rsp_i ( router_4_8_to_magia_tile_ni_4_8_rsp ), - .floo_req_i ( router_4_8_to_magia_tile_ni_4_8_req ), - .floo_rsp_o ( magia_tile_ni_4_8_to_router_4_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][9] ), - .id_i ( '{x: 5, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_9_to_router_4_9_req ), - .floo_rsp_i ( router_4_9_to_magia_tile_ni_4_9_rsp ), - .floo_req_i ( router_4_9_to_magia_tile_ni_4_9_req ), - .floo_rsp_o ( magia_tile_ni_4_9_to_router_4_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][10] ), - .id_i ( '{x: 5, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_10_to_router_4_10_req ), - .floo_rsp_i ( router_4_10_to_magia_tile_ni_4_10_rsp ), - .floo_req_i ( router_4_10_to_magia_tile_ni_4_10_req ), - .floo_rsp_o ( magia_tile_ni_4_10_to_router_4_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][11] ), - .id_i ( '{x: 5, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_11_to_router_4_11_req ), - .floo_rsp_i ( router_4_11_to_magia_tile_ni_4_11_rsp ), - .floo_req_i ( router_4_11_to_magia_tile_ni_4_11_req ), - .floo_rsp_o ( magia_tile_ni_4_11_to_router_4_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][12] ), - .id_i ( '{x: 5, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_12_to_router_4_12_req ), - .floo_rsp_i ( router_4_12_to_magia_tile_ni_4_12_rsp ), - .floo_req_i ( router_4_12_to_magia_tile_ni_4_12_req ), - .floo_rsp_o ( magia_tile_ni_4_12_to_router_4_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][13] ), - .id_i ( '{x: 5, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_13_to_router_4_13_req ), - .floo_rsp_i ( router_4_13_to_magia_tile_ni_4_13_rsp ), - .floo_req_i ( router_4_13_to_magia_tile_ni_4_13_req ), - .floo_rsp_o ( magia_tile_ni_4_13_to_router_4_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][14] ), - .id_i ( '{x: 5, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_14_to_router_4_14_req ), - .floo_rsp_i ( router_4_14_to_magia_tile_ni_4_14_rsp ), - .floo_req_i ( router_4_14_to_magia_tile_ni_4_14_req ), - .floo_rsp_o ( magia_tile_ni_4_14_to_router_4_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][15] ), - .id_i ( '{x: 5, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_15_to_router_4_15_req ), - .floo_rsp_i ( router_4_15_to_magia_tile_ni_4_15_rsp ), - .floo_req_i ( router_4_15_to_magia_tile_ni_4_15_req ), - .floo_rsp_o ( magia_tile_ni_4_15_to_router_4_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][16] ), - .id_i ( '{x: 5, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_16_to_router_4_16_req ), - .floo_rsp_i ( router_4_16_to_magia_tile_ni_4_16_rsp ), - .floo_req_i ( router_4_16_to_magia_tile_ni_4_16_req ), - .floo_rsp_o ( magia_tile_ni_4_16_to_router_4_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][17] ), - .id_i ( '{x: 5, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_17_to_router_4_17_req ), - .floo_rsp_i ( router_4_17_to_magia_tile_ni_4_17_rsp ), - .floo_req_i ( router_4_17_to_magia_tile_ni_4_17_req ), - .floo_rsp_o ( magia_tile_ni_4_17_to_router_4_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][18] ), - .id_i ( '{x: 5, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_18_to_router_4_18_req ), - .floo_rsp_i ( router_4_18_to_magia_tile_ni_4_18_rsp ), - .floo_req_i ( router_4_18_to_magia_tile_ni_4_18_req ), - .floo_rsp_o ( magia_tile_ni_4_18_to_router_4_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][19] ), - .id_i ( '{x: 5, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_19_to_router_4_19_req ), - .floo_rsp_i ( router_4_19_to_magia_tile_ni_4_19_rsp ), - .floo_req_i ( router_4_19_to_magia_tile_ni_4_19_req ), - .floo_rsp_o ( magia_tile_ni_4_19_to_router_4_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][20] ), - .id_i ( '{x: 5, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_20_to_router_4_20_req ), - .floo_rsp_i ( router_4_20_to_magia_tile_ni_4_20_rsp ), - .floo_req_i ( router_4_20_to_magia_tile_ni_4_20_req ), - .floo_rsp_o ( magia_tile_ni_4_20_to_router_4_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][21] ), - .id_i ( '{x: 5, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_21_to_router_4_21_req ), - .floo_rsp_i ( router_4_21_to_magia_tile_ni_4_21_rsp ), - .floo_req_i ( router_4_21_to_magia_tile_ni_4_21_req ), - .floo_rsp_o ( magia_tile_ni_4_21_to_router_4_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][22] ), - .id_i ( '{x: 5, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_22_to_router_4_22_req ), - .floo_rsp_i ( router_4_22_to_magia_tile_ni_4_22_rsp ), - .floo_req_i ( router_4_22_to_magia_tile_ni_4_22_req ), - .floo_rsp_o ( magia_tile_ni_4_22_to_router_4_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][23] ), - .id_i ( '{x: 5, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_23_to_router_4_23_req ), - .floo_rsp_i ( router_4_23_to_magia_tile_ni_4_23_rsp ), - .floo_req_i ( router_4_23_to_magia_tile_ni_4_23_req ), - .floo_rsp_o ( magia_tile_ni_4_23_to_router_4_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][24] ), - .id_i ( '{x: 5, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_24_to_router_4_24_req ), - .floo_rsp_i ( router_4_24_to_magia_tile_ni_4_24_rsp ), - .floo_req_i ( router_4_24_to_magia_tile_ni_4_24_req ), - .floo_rsp_o ( magia_tile_ni_4_24_to_router_4_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][25] ), - .id_i ( '{x: 5, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_25_to_router_4_25_req ), - .floo_rsp_i ( router_4_25_to_magia_tile_ni_4_25_rsp ), - .floo_req_i ( router_4_25_to_magia_tile_ni_4_25_req ), - .floo_rsp_o ( magia_tile_ni_4_25_to_router_4_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][26] ), - .id_i ( '{x: 5, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_26_to_router_4_26_req ), - .floo_rsp_i ( router_4_26_to_magia_tile_ni_4_26_rsp ), - .floo_req_i ( router_4_26_to_magia_tile_ni_4_26_req ), - .floo_rsp_o ( magia_tile_ni_4_26_to_router_4_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][27] ), - .id_i ( '{x: 5, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_27_to_router_4_27_req ), - .floo_rsp_i ( router_4_27_to_magia_tile_ni_4_27_rsp ), - .floo_req_i ( router_4_27_to_magia_tile_ni_4_27_req ), - .floo_rsp_o ( magia_tile_ni_4_27_to_router_4_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][28] ), - .id_i ( '{x: 5, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_28_to_router_4_28_req ), - .floo_rsp_i ( router_4_28_to_magia_tile_ni_4_28_rsp ), - .floo_req_i ( router_4_28_to_magia_tile_ni_4_28_req ), - .floo_rsp_o ( magia_tile_ni_4_28_to_router_4_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][29] ), - .id_i ( '{x: 5, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_29_to_router_4_29_req ), - .floo_rsp_i ( router_4_29_to_magia_tile_ni_4_29_rsp ), - .floo_req_i ( router_4_29_to_magia_tile_ni_4_29_req ), - .floo_rsp_o ( magia_tile_ni_4_29_to_router_4_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][30] ), - .id_i ( '{x: 5, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_30_to_router_4_30_req ), - .floo_rsp_i ( router_4_30_to_magia_tile_ni_4_30_rsp ), - .floo_req_i ( router_4_30_to_magia_tile_ni_4_30_req ), - .floo_rsp_o ( magia_tile_ni_4_30_to_router_4_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][31] ), - .id_i ( '{x: 5, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_31_to_router_4_31_req ), - .floo_rsp_i ( router_4_31_to_magia_tile_ni_4_31_rsp ), - .floo_req_i ( router_4_31_to_magia_tile_ni_4_31_req ), - .floo_rsp_o ( magia_tile_ni_4_31_to_router_4_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][0] ), - .id_i ( '{x: 6, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_0_to_router_5_0_req ), - .floo_rsp_i ( router_5_0_to_magia_tile_ni_5_0_rsp ), - .floo_req_i ( router_5_0_to_magia_tile_ni_5_0_req ), - .floo_rsp_o ( magia_tile_ni_5_0_to_router_5_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][1] ), - .id_i ( '{x: 6, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_1_to_router_5_1_req ), - .floo_rsp_i ( router_5_1_to_magia_tile_ni_5_1_rsp ), - .floo_req_i ( router_5_1_to_magia_tile_ni_5_1_req ), - .floo_rsp_o ( magia_tile_ni_5_1_to_router_5_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][2] ), - .id_i ( '{x: 6, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_2_to_router_5_2_req ), - .floo_rsp_i ( router_5_2_to_magia_tile_ni_5_2_rsp ), - .floo_req_i ( router_5_2_to_magia_tile_ni_5_2_req ), - .floo_rsp_o ( magia_tile_ni_5_2_to_router_5_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][3] ), - .id_i ( '{x: 6, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_3_to_router_5_3_req ), - .floo_rsp_i ( router_5_3_to_magia_tile_ni_5_3_rsp ), - .floo_req_i ( router_5_3_to_magia_tile_ni_5_3_req ), - .floo_rsp_o ( magia_tile_ni_5_3_to_router_5_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][4] ), - .id_i ( '{x: 6, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_4_to_router_5_4_req ), - .floo_rsp_i ( router_5_4_to_magia_tile_ni_5_4_rsp ), - .floo_req_i ( router_5_4_to_magia_tile_ni_5_4_req ), - .floo_rsp_o ( magia_tile_ni_5_4_to_router_5_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][5] ), - .id_i ( '{x: 6, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_5_to_router_5_5_req ), - .floo_rsp_i ( router_5_5_to_magia_tile_ni_5_5_rsp ), - .floo_req_i ( router_5_5_to_magia_tile_ni_5_5_req ), - .floo_rsp_o ( magia_tile_ni_5_5_to_router_5_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][6] ), - .id_i ( '{x: 6, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_6_to_router_5_6_req ), - .floo_rsp_i ( router_5_6_to_magia_tile_ni_5_6_rsp ), - .floo_req_i ( router_5_6_to_magia_tile_ni_5_6_req ), - .floo_rsp_o ( magia_tile_ni_5_6_to_router_5_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][7] ), - .id_i ( '{x: 6, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_7_to_router_5_7_req ), - .floo_rsp_i ( router_5_7_to_magia_tile_ni_5_7_rsp ), - .floo_req_i ( router_5_7_to_magia_tile_ni_5_7_req ), - .floo_rsp_o ( magia_tile_ni_5_7_to_router_5_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][8] ), - .id_i ( '{x: 6, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_8_to_router_5_8_req ), - .floo_rsp_i ( router_5_8_to_magia_tile_ni_5_8_rsp ), - .floo_req_i ( router_5_8_to_magia_tile_ni_5_8_req ), - .floo_rsp_o ( magia_tile_ni_5_8_to_router_5_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][9] ), - .id_i ( '{x: 6, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_9_to_router_5_9_req ), - .floo_rsp_i ( router_5_9_to_magia_tile_ni_5_9_rsp ), - .floo_req_i ( router_5_9_to_magia_tile_ni_5_9_req ), - .floo_rsp_o ( magia_tile_ni_5_9_to_router_5_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][10] ), - .id_i ( '{x: 6, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_10_to_router_5_10_req ), - .floo_rsp_i ( router_5_10_to_magia_tile_ni_5_10_rsp ), - .floo_req_i ( router_5_10_to_magia_tile_ni_5_10_req ), - .floo_rsp_o ( magia_tile_ni_5_10_to_router_5_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][11] ), - .id_i ( '{x: 6, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_11_to_router_5_11_req ), - .floo_rsp_i ( router_5_11_to_magia_tile_ni_5_11_rsp ), - .floo_req_i ( router_5_11_to_magia_tile_ni_5_11_req ), - .floo_rsp_o ( magia_tile_ni_5_11_to_router_5_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][12] ), - .id_i ( '{x: 6, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_12_to_router_5_12_req ), - .floo_rsp_i ( router_5_12_to_magia_tile_ni_5_12_rsp ), - .floo_req_i ( router_5_12_to_magia_tile_ni_5_12_req ), - .floo_rsp_o ( magia_tile_ni_5_12_to_router_5_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][13] ), - .id_i ( '{x: 6, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_13_to_router_5_13_req ), - .floo_rsp_i ( router_5_13_to_magia_tile_ni_5_13_rsp ), - .floo_req_i ( router_5_13_to_magia_tile_ni_5_13_req ), - .floo_rsp_o ( magia_tile_ni_5_13_to_router_5_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][14] ), - .id_i ( '{x: 6, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_14_to_router_5_14_req ), - .floo_rsp_i ( router_5_14_to_magia_tile_ni_5_14_rsp ), - .floo_req_i ( router_5_14_to_magia_tile_ni_5_14_req ), - .floo_rsp_o ( magia_tile_ni_5_14_to_router_5_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][15] ), - .id_i ( '{x: 6, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_15_to_router_5_15_req ), - .floo_rsp_i ( router_5_15_to_magia_tile_ni_5_15_rsp ), - .floo_req_i ( router_5_15_to_magia_tile_ni_5_15_req ), - .floo_rsp_o ( magia_tile_ni_5_15_to_router_5_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][16] ), - .id_i ( '{x: 6, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_16_to_router_5_16_req ), - .floo_rsp_i ( router_5_16_to_magia_tile_ni_5_16_rsp ), - .floo_req_i ( router_5_16_to_magia_tile_ni_5_16_req ), - .floo_rsp_o ( magia_tile_ni_5_16_to_router_5_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][17] ), - .id_i ( '{x: 6, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_17_to_router_5_17_req ), - .floo_rsp_i ( router_5_17_to_magia_tile_ni_5_17_rsp ), - .floo_req_i ( router_5_17_to_magia_tile_ni_5_17_req ), - .floo_rsp_o ( magia_tile_ni_5_17_to_router_5_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][18] ), - .id_i ( '{x: 6, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_18_to_router_5_18_req ), - .floo_rsp_i ( router_5_18_to_magia_tile_ni_5_18_rsp ), - .floo_req_i ( router_5_18_to_magia_tile_ni_5_18_req ), - .floo_rsp_o ( magia_tile_ni_5_18_to_router_5_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][19] ), - .id_i ( '{x: 6, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_19_to_router_5_19_req ), - .floo_rsp_i ( router_5_19_to_magia_tile_ni_5_19_rsp ), - .floo_req_i ( router_5_19_to_magia_tile_ni_5_19_req ), - .floo_rsp_o ( magia_tile_ni_5_19_to_router_5_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][20] ), - .id_i ( '{x: 6, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_20_to_router_5_20_req ), - .floo_rsp_i ( router_5_20_to_magia_tile_ni_5_20_rsp ), - .floo_req_i ( router_5_20_to_magia_tile_ni_5_20_req ), - .floo_rsp_o ( magia_tile_ni_5_20_to_router_5_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][21] ), - .id_i ( '{x: 6, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_21_to_router_5_21_req ), - .floo_rsp_i ( router_5_21_to_magia_tile_ni_5_21_rsp ), - .floo_req_i ( router_5_21_to_magia_tile_ni_5_21_req ), - .floo_rsp_o ( magia_tile_ni_5_21_to_router_5_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][22] ), - .id_i ( '{x: 6, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_22_to_router_5_22_req ), - .floo_rsp_i ( router_5_22_to_magia_tile_ni_5_22_rsp ), - .floo_req_i ( router_5_22_to_magia_tile_ni_5_22_req ), - .floo_rsp_o ( magia_tile_ni_5_22_to_router_5_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][23] ), - .id_i ( '{x: 6, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_23_to_router_5_23_req ), - .floo_rsp_i ( router_5_23_to_magia_tile_ni_5_23_rsp ), - .floo_req_i ( router_5_23_to_magia_tile_ni_5_23_req ), - .floo_rsp_o ( magia_tile_ni_5_23_to_router_5_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][24] ), - .id_i ( '{x: 6, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_24_to_router_5_24_req ), - .floo_rsp_i ( router_5_24_to_magia_tile_ni_5_24_rsp ), - .floo_req_i ( router_5_24_to_magia_tile_ni_5_24_req ), - .floo_rsp_o ( magia_tile_ni_5_24_to_router_5_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][25] ), - .id_i ( '{x: 6, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_25_to_router_5_25_req ), - .floo_rsp_i ( router_5_25_to_magia_tile_ni_5_25_rsp ), - .floo_req_i ( router_5_25_to_magia_tile_ni_5_25_req ), - .floo_rsp_o ( magia_tile_ni_5_25_to_router_5_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][26] ), - .id_i ( '{x: 6, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_26_to_router_5_26_req ), - .floo_rsp_i ( router_5_26_to_magia_tile_ni_5_26_rsp ), - .floo_req_i ( router_5_26_to_magia_tile_ni_5_26_req ), - .floo_rsp_o ( magia_tile_ni_5_26_to_router_5_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][27] ), - .id_i ( '{x: 6, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_27_to_router_5_27_req ), - .floo_rsp_i ( router_5_27_to_magia_tile_ni_5_27_rsp ), - .floo_req_i ( router_5_27_to_magia_tile_ni_5_27_req ), - .floo_rsp_o ( magia_tile_ni_5_27_to_router_5_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][28] ), - .id_i ( '{x: 6, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_28_to_router_5_28_req ), - .floo_rsp_i ( router_5_28_to_magia_tile_ni_5_28_rsp ), - .floo_req_i ( router_5_28_to_magia_tile_ni_5_28_req ), - .floo_rsp_o ( magia_tile_ni_5_28_to_router_5_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][29] ), - .id_i ( '{x: 6, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_29_to_router_5_29_req ), - .floo_rsp_i ( router_5_29_to_magia_tile_ni_5_29_rsp ), - .floo_req_i ( router_5_29_to_magia_tile_ni_5_29_req ), - .floo_rsp_o ( magia_tile_ni_5_29_to_router_5_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][30] ), - .id_i ( '{x: 6, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_30_to_router_5_30_req ), - .floo_rsp_i ( router_5_30_to_magia_tile_ni_5_30_rsp ), - .floo_req_i ( router_5_30_to_magia_tile_ni_5_30_req ), - .floo_rsp_o ( magia_tile_ni_5_30_to_router_5_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][31] ), - .id_i ( '{x: 6, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_31_to_router_5_31_req ), - .floo_rsp_i ( router_5_31_to_magia_tile_ni_5_31_rsp ), - .floo_req_i ( router_5_31_to_magia_tile_ni_5_31_req ), - .floo_rsp_o ( magia_tile_ni_5_31_to_router_5_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][0] ), - .id_i ( '{x: 7, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_0_to_router_6_0_req ), - .floo_rsp_i ( router_6_0_to_magia_tile_ni_6_0_rsp ), - .floo_req_i ( router_6_0_to_magia_tile_ni_6_0_req ), - .floo_rsp_o ( magia_tile_ni_6_0_to_router_6_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][1] ), - .id_i ( '{x: 7, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_1_to_router_6_1_req ), - .floo_rsp_i ( router_6_1_to_magia_tile_ni_6_1_rsp ), - .floo_req_i ( router_6_1_to_magia_tile_ni_6_1_req ), - .floo_rsp_o ( magia_tile_ni_6_1_to_router_6_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][2] ), - .id_i ( '{x: 7, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_2_to_router_6_2_req ), - .floo_rsp_i ( router_6_2_to_magia_tile_ni_6_2_rsp ), - .floo_req_i ( router_6_2_to_magia_tile_ni_6_2_req ), - .floo_rsp_o ( magia_tile_ni_6_2_to_router_6_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][3] ), - .id_i ( '{x: 7, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_3_to_router_6_3_req ), - .floo_rsp_i ( router_6_3_to_magia_tile_ni_6_3_rsp ), - .floo_req_i ( router_6_3_to_magia_tile_ni_6_3_req ), - .floo_rsp_o ( magia_tile_ni_6_3_to_router_6_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][4] ), - .id_i ( '{x: 7, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_4_to_router_6_4_req ), - .floo_rsp_i ( router_6_4_to_magia_tile_ni_6_4_rsp ), - .floo_req_i ( router_6_4_to_magia_tile_ni_6_4_req ), - .floo_rsp_o ( magia_tile_ni_6_4_to_router_6_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][5] ), - .id_i ( '{x: 7, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_5_to_router_6_5_req ), - .floo_rsp_i ( router_6_5_to_magia_tile_ni_6_5_rsp ), - .floo_req_i ( router_6_5_to_magia_tile_ni_6_5_req ), - .floo_rsp_o ( magia_tile_ni_6_5_to_router_6_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][6] ), - .id_i ( '{x: 7, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_6_to_router_6_6_req ), - .floo_rsp_i ( router_6_6_to_magia_tile_ni_6_6_rsp ), - .floo_req_i ( router_6_6_to_magia_tile_ni_6_6_req ), - .floo_rsp_o ( magia_tile_ni_6_6_to_router_6_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][7] ), - .id_i ( '{x: 7, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_7_to_router_6_7_req ), - .floo_rsp_i ( router_6_7_to_magia_tile_ni_6_7_rsp ), - .floo_req_i ( router_6_7_to_magia_tile_ni_6_7_req ), - .floo_rsp_o ( magia_tile_ni_6_7_to_router_6_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][8] ), - .id_i ( '{x: 7, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_8_to_router_6_8_req ), - .floo_rsp_i ( router_6_8_to_magia_tile_ni_6_8_rsp ), - .floo_req_i ( router_6_8_to_magia_tile_ni_6_8_req ), - .floo_rsp_o ( magia_tile_ni_6_8_to_router_6_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][9] ), - .id_i ( '{x: 7, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_9_to_router_6_9_req ), - .floo_rsp_i ( router_6_9_to_magia_tile_ni_6_9_rsp ), - .floo_req_i ( router_6_9_to_magia_tile_ni_6_9_req ), - .floo_rsp_o ( magia_tile_ni_6_9_to_router_6_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][10] ), - .id_i ( '{x: 7, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_10_to_router_6_10_req ), - .floo_rsp_i ( router_6_10_to_magia_tile_ni_6_10_rsp ), - .floo_req_i ( router_6_10_to_magia_tile_ni_6_10_req ), - .floo_rsp_o ( magia_tile_ni_6_10_to_router_6_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][11] ), - .id_i ( '{x: 7, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_11_to_router_6_11_req ), - .floo_rsp_i ( router_6_11_to_magia_tile_ni_6_11_rsp ), - .floo_req_i ( router_6_11_to_magia_tile_ni_6_11_req ), - .floo_rsp_o ( magia_tile_ni_6_11_to_router_6_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][12] ), - .id_i ( '{x: 7, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_12_to_router_6_12_req ), - .floo_rsp_i ( router_6_12_to_magia_tile_ni_6_12_rsp ), - .floo_req_i ( router_6_12_to_magia_tile_ni_6_12_req ), - .floo_rsp_o ( magia_tile_ni_6_12_to_router_6_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][13] ), - .id_i ( '{x: 7, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_13_to_router_6_13_req ), - .floo_rsp_i ( router_6_13_to_magia_tile_ni_6_13_rsp ), - .floo_req_i ( router_6_13_to_magia_tile_ni_6_13_req ), - .floo_rsp_o ( magia_tile_ni_6_13_to_router_6_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][14] ), - .id_i ( '{x: 7, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_14_to_router_6_14_req ), - .floo_rsp_i ( router_6_14_to_magia_tile_ni_6_14_rsp ), - .floo_req_i ( router_6_14_to_magia_tile_ni_6_14_req ), - .floo_rsp_o ( magia_tile_ni_6_14_to_router_6_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][15] ), - .id_i ( '{x: 7, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_15_to_router_6_15_req ), - .floo_rsp_i ( router_6_15_to_magia_tile_ni_6_15_rsp ), - .floo_req_i ( router_6_15_to_magia_tile_ni_6_15_req ), - .floo_rsp_o ( magia_tile_ni_6_15_to_router_6_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][16] ), - .id_i ( '{x: 7, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_16_to_router_6_16_req ), - .floo_rsp_i ( router_6_16_to_magia_tile_ni_6_16_rsp ), - .floo_req_i ( router_6_16_to_magia_tile_ni_6_16_req ), - .floo_rsp_o ( magia_tile_ni_6_16_to_router_6_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][17] ), - .id_i ( '{x: 7, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_17_to_router_6_17_req ), - .floo_rsp_i ( router_6_17_to_magia_tile_ni_6_17_rsp ), - .floo_req_i ( router_6_17_to_magia_tile_ni_6_17_req ), - .floo_rsp_o ( magia_tile_ni_6_17_to_router_6_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][18] ), - .id_i ( '{x: 7, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_18_to_router_6_18_req ), - .floo_rsp_i ( router_6_18_to_magia_tile_ni_6_18_rsp ), - .floo_req_i ( router_6_18_to_magia_tile_ni_6_18_req ), - .floo_rsp_o ( magia_tile_ni_6_18_to_router_6_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][19] ), - .id_i ( '{x: 7, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_19_to_router_6_19_req ), - .floo_rsp_i ( router_6_19_to_magia_tile_ni_6_19_rsp ), - .floo_req_i ( router_6_19_to_magia_tile_ni_6_19_req ), - .floo_rsp_o ( magia_tile_ni_6_19_to_router_6_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][20] ), - .id_i ( '{x: 7, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_20_to_router_6_20_req ), - .floo_rsp_i ( router_6_20_to_magia_tile_ni_6_20_rsp ), - .floo_req_i ( router_6_20_to_magia_tile_ni_6_20_req ), - .floo_rsp_o ( magia_tile_ni_6_20_to_router_6_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][21] ), - .id_i ( '{x: 7, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_21_to_router_6_21_req ), - .floo_rsp_i ( router_6_21_to_magia_tile_ni_6_21_rsp ), - .floo_req_i ( router_6_21_to_magia_tile_ni_6_21_req ), - .floo_rsp_o ( magia_tile_ni_6_21_to_router_6_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][22] ), - .id_i ( '{x: 7, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_22_to_router_6_22_req ), - .floo_rsp_i ( router_6_22_to_magia_tile_ni_6_22_rsp ), - .floo_req_i ( router_6_22_to_magia_tile_ni_6_22_req ), - .floo_rsp_o ( magia_tile_ni_6_22_to_router_6_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][23] ), - .id_i ( '{x: 7, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_23_to_router_6_23_req ), - .floo_rsp_i ( router_6_23_to_magia_tile_ni_6_23_rsp ), - .floo_req_i ( router_6_23_to_magia_tile_ni_6_23_req ), - .floo_rsp_o ( magia_tile_ni_6_23_to_router_6_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][24] ), - .id_i ( '{x: 7, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_24_to_router_6_24_req ), - .floo_rsp_i ( router_6_24_to_magia_tile_ni_6_24_rsp ), - .floo_req_i ( router_6_24_to_magia_tile_ni_6_24_req ), - .floo_rsp_o ( magia_tile_ni_6_24_to_router_6_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][25] ), - .id_i ( '{x: 7, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_25_to_router_6_25_req ), - .floo_rsp_i ( router_6_25_to_magia_tile_ni_6_25_rsp ), - .floo_req_i ( router_6_25_to_magia_tile_ni_6_25_req ), - .floo_rsp_o ( magia_tile_ni_6_25_to_router_6_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][26] ), - .id_i ( '{x: 7, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_26_to_router_6_26_req ), - .floo_rsp_i ( router_6_26_to_magia_tile_ni_6_26_rsp ), - .floo_req_i ( router_6_26_to_magia_tile_ni_6_26_req ), - .floo_rsp_o ( magia_tile_ni_6_26_to_router_6_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][27] ), - .id_i ( '{x: 7, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_27_to_router_6_27_req ), - .floo_rsp_i ( router_6_27_to_magia_tile_ni_6_27_rsp ), - .floo_req_i ( router_6_27_to_magia_tile_ni_6_27_req ), - .floo_rsp_o ( magia_tile_ni_6_27_to_router_6_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][28] ), - .id_i ( '{x: 7, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_28_to_router_6_28_req ), - .floo_rsp_i ( router_6_28_to_magia_tile_ni_6_28_rsp ), - .floo_req_i ( router_6_28_to_magia_tile_ni_6_28_req ), - .floo_rsp_o ( magia_tile_ni_6_28_to_router_6_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][29] ), - .id_i ( '{x: 7, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_29_to_router_6_29_req ), - .floo_rsp_i ( router_6_29_to_magia_tile_ni_6_29_rsp ), - .floo_req_i ( router_6_29_to_magia_tile_ni_6_29_req ), - .floo_rsp_o ( magia_tile_ni_6_29_to_router_6_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][30] ), - .id_i ( '{x: 7, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_30_to_router_6_30_req ), - .floo_rsp_i ( router_6_30_to_magia_tile_ni_6_30_rsp ), - .floo_req_i ( router_6_30_to_magia_tile_ni_6_30_req ), - .floo_rsp_o ( magia_tile_ni_6_30_to_router_6_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][31] ), - .id_i ( '{x: 7, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_31_to_router_6_31_req ), - .floo_rsp_i ( router_6_31_to_magia_tile_ni_6_31_rsp ), - .floo_req_i ( router_6_31_to_magia_tile_ni_6_31_req ), - .floo_rsp_o ( magia_tile_ni_6_31_to_router_6_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][0] ), - .id_i ( '{x: 8, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_0_to_router_7_0_req ), - .floo_rsp_i ( router_7_0_to_magia_tile_ni_7_0_rsp ), - .floo_req_i ( router_7_0_to_magia_tile_ni_7_0_req ), - .floo_rsp_o ( magia_tile_ni_7_0_to_router_7_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][1] ), - .id_i ( '{x: 8, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_1_to_router_7_1_req ), - .floo_rsp_i ( router_7_1_to_magia_tile_ni_7_1_rsp ), - .floo_req_i ( router_7_1_to_magia_tile_ni_7_1_req ), - .floo_rsp_o ( magia_tile_ni_7_1_to_router_7_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][2] ), - .id_i ( '{x: 8, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_2_to_router_7_2_req ), - .floo_rsp_i ( router_7_2_to_magia_tile_ni_7_2_rsp ), - .floo_req_i ( router_7_2_to_magia_tile_ni_7_2_req ), - .floo_rsp_o ( magia_tile_ni_7_2_to_router_7_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][3] ), - .id_i ( '{x: 8, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_3_to_router_7_3_req ), - .floo_rsp_i ( router_7_3_to_magia_tile_ni_7_3_rsp ), - .floo_req_i ( router_7_3_to_magia_tile_ni_7_3_req ), - .floo_rsp_o ( magia_tile_ni_7_3_to_router_7_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][4] ), - .id_i ( '{x: 8, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_4_to_router_7_4_req ), - .floo_rsp_i ( router_7_4_to_magia_tile_ni_7_4_rsp ), - .floo_req_i ( router_7_4_to_magia_tile_ni_7_4_req ), - .floo_rsp_o ( magia_tile_ni_7_4_to_router_7_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][5] ), - .id_i ( '{x: 8, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_5_to_router_7_5_req ), - .floo_rsp_i ( router_7_5_to_magia_tile_ni_7_5_rsp ), - .floo_req_i ( router_7_5_to_magia_tile_ni_7_5_req ), - .floo_rsp_o ( magia_tile_ni_7_5_to_router_7_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][6] ), - .id_i ( '{x: 8, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_6_to_router_7_6_req ), - .floo_rsp_i ( router_7_6_to_magia_tile_ni_7_6_rsp ), - .floo_req_i ( router_7_6_to_magia_tile_ni_7_6_req ), - .floo_rsp_o ( magia_tile_ni_7_6_to_router_7_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][7] ), - .id_i ( '{x: 8, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_7_to_router_7_7_req ), - .floo_rsp_i ( router_7_7_to_magia_tile_ni_7_7_rsp ), - .floo_req_i ( router_7_7_to_magia_tile_ni_7_7_req ), - .floo_rsp_o ( magia_tile_ni_7_7_to_router_7_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][8] ), - .id_i ( '{x: 8, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_8_to_router_7_8_req ), - .floo_rsp_i ( router_7_8_to_magia_tile_ni_7_8_rsp ), - .floo_req_i ( router_7_8_to_magia_tile_ni_7_8_req ), - .floo_rsp_o ( magia_tile_ni_7_8_to_router_7_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][9] ), - .id_i ( '{x: 8, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_9_to_router_7_9_req ), - .floo_rsp_i ( router_7_9_to_magia_tile_ni_7_9_rsp ), - .floo_req_i ( router_7_9_to_magia_tile_ni_7_9_req ), - .floo_rsp_o ( magia_tile_ni_7_9_to_router_7_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][10] ), - .id_i ( '{x: 8, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_10_to_router_7_10_req ), - .floo_rsp_i ( router_7_10_to_magia_tile_ni_7_10_rsp ), - .floo_req_i ( router_7_10_to_magia_tile_ni_7_10_req ), - .floo_rsp_o ( magia_tile_ni_7_10_to_router_7_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][11] ), - .id_i ( '{x: 8, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_11_to_router_7_11_req ), - .floo_rsp_i ( router_7_11_to_magia_tile_ni_7_11_rsp ), - .floo_req_i ( router_7_11_to_magia_tile_ni_7_11_req ), - .floo_rsp_o ( magia_tile_ni_7_11_to_router_7_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][12] ), - .id_i ( '{x: 8, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_12_to_router_7_12_req ), - .floo_rsp_i ( router_7_12_to_magia_tile_ni_7_12_rsp ), - .floo_req_i ( router_7_12_to_magia_tile_ni_7_12_req ), - .floo_rsp_o ( magia_tile_ni_7_12_to_router_7_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][13] ), - .id_i ( '{x: 8, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_13_to_router_7_13_req ), - .floo_rsp_i ( router_7_13_to_magia_tile_ni_7_13_rsp ), - .floo_req_i ( router_7_13_to_magia_tile_ni_7_13_req ), - .floo_rsp_o ( magia_tile_ni_7_13_to_router_7_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][14] ), - .id_i ( '{x: 8, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_14_to_router_7_14_req ), - .floo_rsp_i ( router_7_14_to_magia_tile_ni_7_14_rsp ), - .floo_req_i ( router_7_14_to_magia_tile_ni_7_14_req ), - .floo_rsp_o ( magia_tile_ni_7_14_to_router_7_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][15] ), - .id_i ( '{x: 8, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_15_to_router_7_15_req ), - .floo_rsp_i ( router_7_15_to_magia_tile_ni_7_15_rsp ), - .floo_req_i ( router_7_15_to_magia_tile_ni_7_15_req ), - .floo_rsp_o ( magia_tile_ni_7_15_to_router_7_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][16] ), - .id_i ( '{x: 8, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_16_to_router_7_16_req ), - .floo_rsp_i ( router_7_16_to_magia_tile_ni_7_16_rsp ), - .floo_req_i ( router_7_16_to_magia_tile_ni_7_16_req ), - .floo_rsp_o ( magia_tile_ni_7_16_to_router_7_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][17] ), - .id_i ( '{x: 8, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_17_to_router_7_17_req ), - .floo_rsp_i ( router_7_17_to_magia_tile_ni_7_17_rsp ), - .floo_req_i ( router_7_17_to_magia_tile_ni_7_17_req ), - .floo_rsp_o ( magia_tile_ni_7_17_to_router_7_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][18] ), - .id_i ( '{x: 8, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_18_to_router_7_18_req ), - .floo_rsp_i ( router_7_18_to_magia_tile_ni_7_18_rsp ), - .floo_req_i ( router_7_18_to_magia_tile_ni_7_18_req ), - .floo_rsp_o ( magia_tile_ni_7_18_to_router_7_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][19] ), - .id_i ( '{x: 8, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_19_to_router_7_19_req ), - .floo_rsp_i ( router_7_19_to_magia_tile_ni_7_19_rsp ), - .floo_req_i ( router_7_19_to_magia_tile_ni_7_19_req ), - .floo_rsp_o ( magia_tile_ni_7_19_to_router_7_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][20] ), - .id_i ( '{x: 8, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_20_to_router_7_20_req ), - .floo_rsp_i ( router_7_20_to_magia_tile_ni_7_20_rsp ), - .floo_req_i ( router_7_20_to_magia_tile_ni_7_20_req ), - .floo_rsp_o ( magia_tile_ni_7_20_to_router_7_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][21] ), - .id_i ( '{x: 8, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_21_to_router_7_21_req ), - .floo_rsp_i ( router_7_21_to_magia_tile_ni_7_21_rsp ), - .floo_req_i ( router_7_21_to_magia_tile_ni_7_21_req ), - .floo_rsp_o ( magia_tile_ni_7_21_to_router_7_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][22] ), - .id_i ( '{x: 8, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_22_to_router_7_22_req ), - .floo_rsp_i ( router_7_22_to_magia_tile_ni_7_22_rsp ), - .floo_req_i ( router_7_22_to_magia_tile_ni_7_22_req ), - .floo_rsp_o ( magia_tile_ni_7_22_to_router_7_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][23] ), - .id_i ( '{x: 8, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_23_to_router_7_23_req ), - .floo_rsp_i ( router_7_23_to_magia_tile_ni_7_23_rsp ), - .floo_req_i ( router_7_23_to_magia_tile_ni_7_23_req ), - .floo_rsp_o ( magia_tile_ni_7_23_to_router_7_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][24] ), - .id_i ( '{x: 8, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_24_to_router_7_24_req ), - .floo_rsp_i ( router_7_24_to_magia_tile_ni_7_24_rsp ), - .floo_req_i ( router_7_24_to_magia_tile_ni_7_24_req ), - .floo_rsp_o ( magia_tile_ni_7_24_to_router_7_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][25] ), - .id_i ( '{x: 8, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_25_to_router_7_25_req ), - .floo_rsp_i ( router_7_25_to_magia_tile_ni_7_25_rsp ), - .floo_req_i ( router_7_25_to_magia_tile_ni_7_25_req ), - .floo_rsp_o ( magia_tile_ni_7_25_to_router_7_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][26] ), - .id_i ( '{x: 8, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_26_to_router_7_26_req ), - .floo_rsp_i ( router_7_26_to_magia_tile_ni_7_26_rsp ), - .floo_req_i ( router_7_26_to_magia_tile_ni_7_26_req ), - .floo_rsp_o ( magia_tile_ni_7_26_to_router_7_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][27] ), - .id_i ( '{x: 8, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_27_to_router_7_27_req ), - .floo_rsp_i ( router_7_27_to_magia_tile_ni_7_27_rsp ), - .floo_req_i ( router_7_27_to_magia_tile_ni_7_27_req ), - .floo_rsp_o ( magia_tile_ni_7_27_to_router_7_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][28] ), - .id_i ( '{x: 8, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_28_to_router_7_28_req ), - .floo_rsp_i ( router_7_28_to_magia_tile_ni_7_28_rsp ), - .floo_req_i ( router_7_28_to_magia_tile_ni_7_28_req ), - .floo_rsp_o ( magia_tile_ni_7_28_to_router_7_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][29] ), - .id_i ( '{x: 8, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_29_to_router_7_29_req ), - .floo_rsp_i ( router_7_29_to_magia_tile_ni_7_29_rsp ), - .floo_req_i ( router_7_29_to_magia_tile_ni_7_29_req ), - .floo_rsp_o ( magia_tile_ni_7_29_to_router_7_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][30] ), - .id_i ( '{x: 8, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_30_to_router_7_30_req ), - .floo_rsp_i ( router_7_30_to_magia_tile_ni_7_30_rsp ), - .floo_req_i ( router_7_30_to_magia_tile_ni_7_30_req ), - .floo_rsp_o ( magia_tile_ni_7_30_to_router_7_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][31] ), - .id_i ( '{x: 8, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_31_to_router_7_31_req ), - .floo_rsp_i ( router_7_31_to_magia_tile_ni_7_31_rsp ), - .floo_req_i ( router_7_31_to_magia_tile_ni_7_31_req ), - .floo_rsp_o ( magia_tile_ni_7_31_to_router_7_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][0] ), - .id_i ( '{x: 9, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_0_to_router_8_0_req ), - .floo_rsp_i ( router_8_0_to_magia_tile_ni_8_0_rsp ), - .floo_req_i ( router_8_0_to_magia_tile_ni_8_0_req ), - .floo_rsp_o ( magia_tile_ni_8_0_to_router_8_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][1] ), - .id_i ( '{x: 9, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_1_to_router_8_1_req ), - .floo_rsp_i ( router_8_1_to_magia_tile_ni_8_1_rsp ), - .floo_req_i ( router_8_1_to_magia_tile_ni_8_1_req ), - .floo_rsp_o ( magia_tile_ni_8_1_to_router_8_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][2] ), - .id_i ( '{x: 9, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_2_to_router_8_2_req ), - .floo_rsp_i ( router_8_2_to_magia_tile_ni_8_2_rsp ), - .floo_req_i ( router_8_2_to_magia_tile_ni_8_2_req ), - .floo_rsp_o ( magia_tile_ni_8_2_to_router_8_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][3] ), - .id_i ( '{x: 9, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_3_to_router_8_3_req ), - .floo_rsp_i ( router_8_3_to_magia_tile_ni_8_3_rsp ), - .floo_req_i ( router_8_3_to_magia_tile_ni_8_3_req ), - .floo_rsp_o ( magia_tile_ni_8_3_to_router_8_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][4] ), - .id_i ( '{x: 9, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_4_to_router_8_4_req ), - .floo_rsp_i ( router_8_4_to_magia_tile_ni_8_4_rsp ), - .floo_req_i ( router_8_4_to_magia_tile_ni_8_4_req ), - .floo_rsp_o ( magia_tile_ni_8_4_to_router_8_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][5] ), - .id_i ( '{x: 9, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_5_to_router_8_5_req ), - .floo_rsp_i ( router_8_5_to_magia_tile_ni_8_5_rsp ), - .floo_req_i ( router_8_5_to_magia_tile_ni_8_5_req ), - .floo_rsp_o ( magia_tile_ni_8_5_to_router_8_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][6] ), - .id_i ( '{x: 9, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_6_to_router_8_6_req ), - .floo_rsp_i ( router_8_6_to_magia_tile_ni_8_6_rsp ), - .floo_req_i ( router_8_6_to_magia_tile_ni_8_6_req ), - .floo_rsp_o ( magia_tile_ni_8_6_to_router_8_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][7] ), - .id_i ( '{x: 9, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_7_to_router_8_7_req ), - .floo_rsp_i ( router_8_7_to_magia_tile_ni_8_7_rsp ), - .floo_req_i ( router_8_7_to_magia_tile_ni_8_7_req ), - .floo_rsp_o ( magia_tile_ni_8_7_to_router_8_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][8] ), - .id_i ( '{x: 9, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_8_to_router_8_8_req ), - .floo_rsp_i ( router_8_8_to_magia_tile_ni_8_8_rsp ), - .floo_req_i ( router_8_8_to_magia_tile_ni_8_8_req ), - .floo_rsp_o ( magia_tile_ni_8_8_to_router_8_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][9] ), - .id_i ( '{x: 9, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_9_to_router_8_9_req ), - .floo_rsp_i ( router_8_9_to_magia_tile_ni_8_9_rsp ), - .floo_req_i ( router_8_9_to_magia_tile_ni_8_9_req ), - .floo_rsp_o ( magia_tile_ni_8_9_to_router_8_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][10] ), - .id_i ( '{x: 9, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_10_to_router_8_10_req ), - .floo_rsp_i ( router_8_10_to_magia_tile_ni_8_10_rsp ), - .floo_req_i ( router_8_10_to_magia_tile_ni_8_10_req ), - .floo_rsp_o ( magia_tile_ni_8_10_to_router_8_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][11] ), - .id_i ( '{x: 9, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_11_to_router_8_11_req ), - .floo_rsp_i ( router_8_11_to_magia_tile_ni_8_11_rsp ), - .floo_req_i ( router_8_11_to_magia_tile_ni_8_11_req ), - .floo_rsp_o ( magia_tile_ni_8_11_to_router_8_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][12] ), - .id_i ( '{x: 9, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_12_to_router_8_12_req ), - .floo_rsp_i ( router_8_12_to_magia_tile_ni_8_12_rsp ), - .floo_req_i ( router_8_12_to_magia_tile_ni_8_12_req ), - .floo_rsp_o ( magia_tile_ni_8_12_to_router_8_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][13] ), - .id_i ( '{x: 9, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_13_to_router_8_13_req ), - .floo_rsp_i ( router_8_13_to_magia_tile_ni_8_13_rsp ), - .floo_req_i ( router_8_13_to_magia_tile_ni_8_13_req ), - .floo_rsp_o ( magia_tile_ni_8_13_to_router_8_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][14] ), - .id_i ( '{x: 9, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_14_to_router_8_14_req ), - .floo_rsp_i ( router_8_14_to_magia_tile_ni_8_14_rsp ), - .floo_req_i ( router_8_14_to_magia_tile_ni_8_14_req ), - .floo_rsp_o ( magia_tile_ni_8_14_to_router_8_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][15] ), - .id_i ( '{x: 9, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_15_to_router_8_15_req ), - .floo_rsp_i ( router_8_15_to_magia_tile_ni_8_15_rsp ), - .floo_req_i ( router_8_15_to_magia_tile_ni_8_15_req ), - .floo_rsp_o ( magia_tile_ni_8_15_to_router_8_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][16] ), - .id_i ( '{x: 9, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_16_to_router_8_16_req ), - .floo_rsp_i ( router_8_16_to_magia_tile_ni_8_16_rsp ), - .floo_req_i ( router_8_16_to_magia_tile_ni_8_16_req ), - .floo_rsp_o ( magia_tile_ni_8_16_to_router_8_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][17] ), - .id_i ( '{x: 9, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_17_to_router_8_17_req ), - .floo_rsp_i ( router_8_17_to_magia_tile_ni_8_17_rsp ), - .floo_req_i ( router_8_17_to_magia_tile_ni_8_17_req ), - .floo_rsp_o ( magia_tile_ni_8_17_to_router_8_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][18] ), - .id_i ( '{x: 9, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_18_to_router_8_18_req ), - .floo_rsp_i ( router_8_18_to_magia_tile_ni_8_18_rsp ), - .floo_req_i ( router_8_18_to_magia_tile_ni_8_18_req ), - .floo_rsp_o ( magia_tile_ni_8_18_to_router_8_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][19] ), - .id_i ( '{x: 9, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_19_to_router_8_19_req ), - .floo_rsp_i ( router_8_19_to_magia_tile_ni_8_19_rsp ), - .floo_req_i ( router_8_19_to_magia_tile_ni_8_19_req ), - .floo_rsp_o ( magia_tile_ni_8_19_to_router_8_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][20] ), - .id_i ( '{x: 9, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_20_to_router_8_20_req ), - .floo_rsp_i ( router_8_20_to_magia_tile_ni_8_20_rsp ), - .floo_req_i ( router_8_20_to_magia_tile_ni_8_20_req ), - .floo_rsp_o ( magia_tile_ni_8_20_to_router_8_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][21] ), - .id_i ( '{x: 9, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_21_to_router_8_21_req ), - .floo_rsp_i ( router_8_21_to_magia_tile_ni_8_21_rsp ), - .floo_req_i ( router_8_21_to_magia_tile_ni_8_21_req ), - .floo_rsp_o ( magia_tile_ni_8_21_to_router_8_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][22] ), - .id_i ( '{x: 9, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_22_to_router_8_22_req ), - .floo_rsp_i ( router_8_22_to_magia_tile_ni_8_22_rsp ), - .floo_req_i ( router_8_22_to_magia_tile_ni_8_22_req ), - .floo_rsp_o ( magia_tile_ni_8_22_to_router_8_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][23] ), - .id_i ( '{x: 9, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_23_to_router_8_23_req ), - .floo_rsp_i ( router_8_23_to_magia_tile_ni_8_23_rsp ), - .floo_req_i ( router_8_23_to_magia_tile_ni_8_23_req ), - .floo_rsp_o ( magia_tile_ni_8_23_to_router_8_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][24] ), - .id_i ( '{x: 9, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_24_to_router_8_24_req ), - .floo_rsp_i ( router_8_24_to_magia_tile_ni_8_24_rsp ), - .floo_req_i ( router_8_24_to_magia_tile_ni_8_24_req ), - .floo_rsp_o ( magia_tile_ni_8_24_to_router_8_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][25] ), - .id_i ( '{x: 9, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_25_to_router_8_25_req ), - .floo_rsp_i ( router_8_25_to_magia_tile_ni_8_25_rsp ), - .floo_req_i ( router_8_25_to_magia_tile_ni_8_25_req ), - .floo_rsp_o ( magia_tile_ni_8_25_to_router_8_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][26] ), - .id_i ( '{x: 9, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_26_to_router_8_26_req ), - .floo_rsp_i ( router_8_26_to_magia_tile_ni_8_26_rsp ), - .floo_req_i ( router_8_26_to_magia_tile_ni_8_26_req ), - .floo_rsp_o ( magia_tile_ni_8_26_to_router_8_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][27] ), - .id_i ( '{x: 9, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_27_to_router_8_27_req ), - .floo_rsp_i ( router_8_27_to_magia_tile_ni_8_27_rsp ), - .floo_req_i ( router_8_27_to_magia_tile_ni_8_27_req ), - .floo_rsp_o ( magia_tile_ni_8_27_to_router_8_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][28] ), - .id_i ( '{x: 9, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_28_to_router_8_28_req ), - .floo_rsp_i ( router_8_28_to_magia_tile_ni_8_28_rsp ), - .floo_req_i ( router_8_28_to_magia_tile_ni_8_28_req ), - .floo_rsp_o ( magia_tile_ni_8_28_to_router_8_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][29] ), - .id_i ( '{x: 9, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_29_to_router_8_29_req ), - .floo_rsp_i ( router_8_29_to_magia_tile_ni_8_29_rsp ), - .floo_req_i ( router_8_29_to_magia_tile_ni_8_29_req ), - .floo_rsp_o ( magia_tile_ni_8_29_to_router_8_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][30] ), - .id_i ( '{x: 9, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_30_to_router_8_30_req ), - .floo_rsp_i ( router_8_30_to_magia_tile_ni_8_30_rsp ), - .floo_req_i ( router_8_30_to_magia_tile_ni_8_30_req ), - .floo_rsp_o ( magia_tile_ni_8_30_to_router_8_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_8_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[8][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[8][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[8][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[8][31] ), - .id_i ( '{x: 9, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_8_31_to_router_8_31_req ), - .floo_rsp_i ( router_8_31_to_magia_tile_ni_8_31_rsp ), - .floo_req_i ( router_8_31_to_magia_tile_ni_8_31_req ), - .floo_rsp_o ( magia_tile_ni_8_31_to_router_8_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][0] ), - .id_i ( '{x: 10, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_0_to_router_9_0_req ), - .floo_rsp_i ( router_9_0_to_magia_tile_ni_9_0_rsp ), - .floo_req_i ( router_9_0_to_magia_tile_ni_9_0_req ), - .floo_rsp_o ( magia_tile_ni_9_0_to_router_9_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][1] ), - .id_i ( '{x: 10, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_1_to_router_9_1_req ), - .floo_rsp_i ( router_9_1_to_magia_tile_ni_9_1_rsp ), - .floo_req_i ( router_9_1_to_magia_tile_ni_9_1_req ), - .floo_rsp_o ( magia_tile_ni_9_1_to_router_9_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][2] ), - .id_i ( '{x: 10, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_2_to_router_9_2_req ), - .floo_rsp_i ( router_9_2_to_magia_tile_ni_9_2_rsp ), - .floo_req_i ( router_9_2_to_magia_tile_ni_9_2_req ), - .floo_rsp_o ( magia_tile_ni_9_2_to_router_9_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][3] ), - .id_i ( '{x: 10, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_3_to_router_9_3_req ), - .floo_rsp_i ( router_9_3_to_magia_tile_ni_9_3_rsp ), - .floo_req_i ( router_9_3_to_magia_tile_ni_9_3_req ), - .floo_rsp_o ( magia_tile_ni_9_3_to_router_9_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][4] ), - .id_i ( '{x: 10, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_4_to_router_9_4_req ), - .floo_rsp_i ( router_9_4_to_magia_tile_ni_9_4_rsp ), - .floo_req_i ( router_9_4_to_magia_tile_ni_9_4_req ), - .floo_rsp_o ( magia_tile_ni_9_4_to_router_9_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][5] ), - .id_i ( '{x: 10, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_5_to_router_9_5_req ), - .floo_rsp_i ( router_9_5_to_magia_tile_ni_9_5_rsp ), - .floo_req_i ( router_9_5_to_magia_tile_ni_9_5_req ), - .floo_rsp_o ( magia_tile_ni_9_5_to_router_9_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][6] ), - .id_i ( '{x: 10, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_6_to_router_9_6_req ), - .floo_rsp_i ( router_9_6_to_magia_tile_ni_9_6_rsp ), - .floo_req_i ( router_9_6_to_magia_tile_ni_9_6_req ), - .floo_rsp_o ( magia_tile_ni_9_6_to_router_9_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][7] ), - .id_i ( '{x: 10, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_7_to_router_9_7_req ), - .floo_rsp_i ( router_9_7_to_magia_tile_ni_9_7_rsp ), - .floo_req_i ( router_9_7_to_magia_tile_ni_9_7_req ), - .floo_rsp_o ( magia_tile_ni_9_7_to_router_9_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][8] ), - .id_i ( '{x: 10, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_8_to_router_9_8_req ), - .floo_rsp_i ( router_9_8_to_magia_tile_ni_9_8_rsp ), - .floo_req_i ( router_9_8_to_magia_tile_ni_9_8_req ), - .floo_rsp_o ( magia_tile_ni_9_8_to_router_9_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][9] ), - .id_i ( '{x: 10, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_9_to_router_9_9_req ), - .floo_rsp_i ( router_9_9_to_magia_tile_ni_9_9_rsp ), - .floo_req_i ( router_9_9_to_magia_tile_ni_9_9_req ), - .floo_rsp_o ( magia_tile_ni_9_9_to_router_9_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][10] ), - .id_i ( '{x: 10, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_10_to_router_9_10_req ), - .floo_rsp_i ( router_9_10_to_magia_tile_ni_9_10_rsp ), - .floo_req_i ( router_9_10_to_magia_tile_ni_9_10_req ), - .floo_rsp_o ( magia_tile_ni_9_10_to_router_9_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][11] ), - .id_i ( '{x: 10, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_11_to_router_9_11_req ), - .floo_rsp_i ( router_9_11_to_magia_tile_ni_9_11_rsp ), - .floo_req_i ( router_9_11_to_magia_tile_ni_9_11_req ), - .floo_rsp_o ( magia_tile_ni_9_11_to_router_9_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][12] ), - .id_i ( '{x: 10, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_12_to_router_9_12_req ), - .floo_rsp_i ( router_9_12_to_magia_tile_ni_9_12_rsp ), - .floo_req_i ( router_9_12_to_magia_tile_ni_9_12_req ), - .floo_rsp_o ( magia_tile_ni_9_12_to_router_9_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][13] ), - .id_i ( '{x: 10, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_13_to_router_9_13_req ), - .floo_rsp_i ( router_9_13_to_magia_tile_ni_9_13_rsp ), - .floo_req_i ( router_9_13_to_magia_tile_ni_9_13_req ), - .floo_rsp_o ( magia_tile_ni_9_13_to_router_9_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][14] ), - .id_i ( '{x: 10, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_14_to_router_9_14_req ), - .floo_rsp_i ( router_9_14_to_magia_tile_ni_9_14_rsp ), - .floo_req_i ( router_9_14_to_magia_tile_ni_9_14_req ), - .floo_rsp_o ( magia_tile_ni_9_14_to_router_9_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][15] ), - .id_i ( '{x: 10, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_15_to_router_9_15_req ), - .floo_rsp_i ( router_9_15_to_magia_tile_ni_9_15_rsp ), - .floo_req_i ( router_9_15_to_magia_tile_ni_9_15_req ), - .floo_rsp_o ( magia_tile_ni_9_15_to_router_9_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][16] ), - .id_i ( '{x: 10, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_16_to_router_9_16_req ), - .floo_rsp_i ( router_9_16_to_magia_tile_ni_9_16_rsp ), - .floo_req_i ( router_9_16_to_magia_tile_ni_9_16_req ), - .floo_rsp_o ( magia_tile_ni_9_16_to_router_9_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][17] ), - .id_i ( '{x: 10, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_17_to_router_9_17_req ), - .floo_rsp_i ( router_9_17_to_magia_tile_ni_9_17_rsp ), - .floo_req_i ( router_9_17_to_magia_tile_ni_9_17_req ), - .floo_rsp_o ( magia_tile_ni_9_17_to_router_9_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][18] ), - .id_i ( '{x: 10, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_18_to_router_9_18_req ), - .floo_rsp_i ( router_9_18_to_magia_tile_ni_9_18_rsp ), - .floo_req_i ( router_9_18_to_magia_tile_ni_9_18_req ), - .floo_rsp_o ( magia_tile_ni_9_18_to_router_9_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][19] ), - .id_i ( '{x: 10, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_19_to_router_9_19_req ), - .floo_rsp_i ( router_9_19_to_magia_tile_ni_9_19_rsp ), - .floo_req_i ( router_9_19_to_magia_tile_ni_9_19_req ), - .floo_rsp_o ( magia_tile_ni_9_19_to_router_9_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][20] ), - .id_i ( '{x: 10, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_20_to_router_9_20_req ), - .floo_rsp_i ( router_9_20_to_magia_tile_ni_9_20_rsp ), - .floo_req_i ( router_9_20_to_magia_tile_ni_9_20_req ), - .floo_rsp_o ( magia_tile_ni_9_20_to_router_9_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][21] ), - .id_i ( '{x: 10, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_21_to_router_9_21_req ), - .floo_rsp_i ( router_9_21_to_magia_tile_ni_9_21_rsp ), - .floo_req_i ( router_9_21_to_magia_tile_ni_9_21_req ), - .floo_rsp_o ( magia_tile_ni_9_21_to_router_9_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][22] ), - .id_i ( '{x: 10, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_22_to_router_9_22_req ), - .floo_rsp_i ( router_9_22_to_magia_tile_ni_9_22_rsp ), - .floo_req_i ( router_9_22_to_magia_tile_ni_9_22_req ), - .floo_rsp_o ( magia_tile_ni_9_22_to_router_9_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][23] ), - .id_i ( '{x: 10, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_23_to_router_9_23_req ), - .floo_rsp_i ( router_9_23_to_magia_tile_ni_9_23_rsp ), - .floo_req_i ( router_9_23_to_magia_tile_ni_9_23_req ), - .floo_rsp_o ( magia_tile_ni_9_23_to_router_9_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][24] ), - .id_i ( '{x: 10, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_24_to_router_9_24_req ), - .floo_rsp_i ( router_9_24_to_magia_tile_ni_9_24_rsp ), - .floo_req_i ( router_9_24_to_magia_tile_ni_9_24_req ), - .floo_rsp_o ( magia_tile_ni_9_24_to_router_9_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][25] ), - .id_i ( '{x: 10, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_25_to_router_9_25_req ), - .floo_rsp_i ( router_9_25_to_magia_tile_ni_9_25_rsp ), - .floo_req_i ( router_9_25_to_magia_tile_ni_9_25_req ), - .floo_rsp_o ( magia_tile_ni_9_25_to_router_9_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][26] ), - .id_i ( '{x: 10, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_26_to_router_9_26_req ), - .floo_rsp_i ( router_9_26_to_magia_tile_ni_9_26_rsp ), - .floo_req_i ( router_9_26_to_magia_tile_ni_9_26_req ), - .floo_rsp_o ( magia_tile_ni_9_26_to_router_9_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][27] ), - .id_i ( '{x: 10, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_27_to_router_9_27_req ), - .floo_rsp_i ( router_9_27_to_magia_tile_ni_9_27_rsp ), - .floo_req_i ( router_9_27_to_magia_tile_ni_9_27_req ), - .floo_rsp_o ( magia_tile_ni_9_27_to_router_9_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][28] ), - .id_i ( '{x: 10, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_28_to_router_9_28_req ), - .floo_rsp_i ( router_9_28_to_magia_tile_ni_9_28_rsp ), - .floo_req_i ( router_9_28_to_magia_tile_ni_9_28_req ), - .floo_rsp_o ( magia_tile_ni_9_28_to_router_9_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][29] ), - .id_i ( '{x: 10, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_29_to_router_9_29_req ), - .floo_rsp_i ( router_9_29_to_magia_tile_ni_9_29_rsp ), - .floo_req_i ( router_9_29_to_magia_tile_ni_9_29_req ), - .floo_rsp_o ( magia_tile_ni_9_29_to_router_9_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][30] ), - .id_i ( '{x: 10, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_30_to_router_9_30_req ), - .floo_rsp_i ( router_9_30_to_magia_tile_ni_9_30_rsp ), - .floo_req_i ( router_9_30_to_magia_tile_ni_9_30_req ), - .floo_rsp_o ( magia_tile_ni_9_30_to_router_9_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_9_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[9][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[9][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[9][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[9][31] ), - .id_i ( '{x: 10, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_9_31_to_router_9_31_req ), - .floo_rsp_i ( router_9_31_to_magia_tile_ni_9_31_rsp ), - .floo_req_i ( router_9_31_to_magia_tile_ni_9_31_req ), - .floo_rsp_o ( magia_tile_ni_9_31_to_router_9_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][0] ), - .id_i ( '{x: 11, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_0_to_router_10_0_req ), - .floo_rsp_i ( router_10_0_to_magia_tile_ni_10_0_rsp ), - .floo_req_i ( router_10_0_to_magia_tile_ni_10_0_req ), - .floo_rsp_o ( magia_tile_ni_10_0_to_router_10_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][1] ), - .id_i ( '{x: 11, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_1_to_router_10_1_req ), - .floo_rsp_i ( router_10_1_to_magia_tile_ni_10_1_rsp ), - .floo_req_i ( router_10_1_to_magia_tile_ni_10_1_req ), - .floo_rsp_o ( magia_tile_ni_10_1_to_router_10_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][2] ), - .id_i ( '{x: 11, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_2_to_router_10_2_req ), - .floo_rsp_i ( router_10_2_to_magia_tile_ni_10_2_rsp ), - .floo_req_i ( router_10_2_to_magia_tile_ni_10_2_req ), - .floo_rsp_o ( magia_tile_ni_10_2_to_router_10_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][3] ), - .id_i ( '{x: 11, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_3_to_router_10_3_req ), - .floo_rsp_i ( router_10_3_to_magia_tile_ni_10_3_rsp ), - .floo_req_i ( router_10_3_to_magia_tile_ni_10_3_req ), - .floo_rsp_o ( magia_tile_ni_10_3_to_router_10_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][4] ), - .id_i ( '{x: 11, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_4_to_router_10_4_req ), - .floo_rsp_i ( router_10_4_to_magia_tile_ni_10_4_rsp ), - .floo_req_i ( router_10_4_to_magia_tile_ni_10_4_req ), - .floo_rsp_o ( magia_tile_ni_10_4_to_router_10_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][5] ), - .id_i ( '{x: 11, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_5_to_router_10_5_req ), - .floo_rsp_i ( router_10_5_to_magia_tile_ni_10_5_rsp ), - .floo_req_i ( router_10_5_to_magia_tile_ni_10_5_req ), - .floo_rsp_o ( magia_tile_ni_10_5_to_router_10_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][6] ), - .id_i ( '{x: 11, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_6_to_router_10_6_req ), - .floo_rsp_i ( router_10_6_to_magia_tile_ni_10_6_rsp ), - .floo_req_i ( router_10_6_to_magia_tile_ni_10_6_req ), - .floo_rsp_o ( magia_tile_ni_10_6_to_router_10_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][7] ), - .id_i ( '{x: 11, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_7_to_router_10_7_req ), - .floo_rsp_i ( router_10_7_to_magia_tile_ni_10_7_rsp ), - .floo_req_i ( router_10_7_to_magia_tile_ni_10_7_req ), - .floo_rsp_o ( magia_tile_ni_10_7_to_router_10_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][8] ), - .id_i ( '{x: 11, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_8_to_router_10_8_req ), - .floo_rsp_i ( router_10_8_to_magia_tile_ni_10_8_rsp ), - .floo_req_i ( router_10_8_to_magia_tile_ni_10_8_req ), - .floo_rsp_o ( magia_tile_ni_10_8_to_router_10_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][9] ), - .id_i ( '{x: 11, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_9_to_router_10_9_req ), - .floo_rsp_i ( router_10_9_to_magia_tile_ni_10_9_rsp ), - .floo_req_i ( router_10_9_to_magia_tile_ni_10_9_req ), - .floo_rsp_o ( magia_tile_ni_10_9_to_router_10_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][10] ), - .id_i ( '{x: 11, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_10_to_router_10_10_req ), - .floo_rsp_i ( router_10_10_to_magia_tile_ni_10_10_rsp ), - .floo_req_i ( router_10_10_to_magia_tile_ni_10_10_req ), - .floo_rsp_o ( magia_tile_ni_10_10_to_router_10_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][11] ), - .id_i ( '{x: 11, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_11_to_router_10_11_req ), - .floo_rsp_i ( router_10_11_to_magia_tile_ni_10_11_rsp ), - .floo_req_i ( router_10_11_to_magia_tile_ni_10_11_req ), - .floo_rsp_o ( magia_tile_ni_10_11_to_router_10_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][12] ), - .id_i ( '{x: 11, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_12_to_router_10_12_req ), - .floo_rsp_i ( router_10_12_to_magia_tile_ni_10_12_rsp ), - .floo_req_i ( router_10_12_to_magia_tile_ni_10_12_req ), - .floo_rsp_o ( magia_tile_ni_10_12_to_router_10_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][13] ), - .id_i ( '{x: 11, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_13_to_router_10_13_req ), - .floo_rsp_i ( router_10_13_to_magia_tile_ni_10_13_rsp ), - .floo_req_i ( router_10_13_to_magia_tile_ni_10_13_req ), - .floo_rsp_o ( magia_tile_ni_10_13_to_router_10_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][14] ), - .id_i ( '{x: 11, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_14_to_router_10_14_req ), - .floo_rsp_i ( router_10_14_to_magia_tile_ni_10_14_rsp ), - .floo_req_i ( router_10_14_to_magia_tile_ni_10_14_req ), - .floo_rsp_o ( magia_tile_ni_10_14_to_router_10_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][15] ), - .id_i ( '{x: 11, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_15_to_router_10_15_req ), - .floo_rsp_i ( router_10_15_to_magia_tile_ni_10_15_rsp ), - .floo_req_i ( router_10_15_to_magia_tile_ni_10_15_req ), - .floo_rsp_o ( magia_tile_ni_10_15_to_router_10_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][16] ), - .id_i ( '{x: 11, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_16_to_router_10_16_req ), - .floo_rsp_i ( router_10_16_to_magia_tile_ni_10_16_rsp ), - .floo_req_i ( router_10_16_to_magia_tile_ni_10_16_req ), - .floo_rsp_o ( magia_tile_ni_10_16_to_router_10_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][17] ), - .id_i ( '{x: 11, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_17_to_router_10_17_req ), - .floo_rsp_i ( router_10_17_to_magia_tile_ni_10_17_rsp ), - .floo_req_i ( router_10_17_to_magia_tile_ni_10_17_req ), - .floo_rsp_o ( magia_tile_ni_10_17_to_router_10_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][18] ), - .id_i ( '{x: 11, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_18_to_router_10_18_req ), - .floo_rsp_i ( router_10_18_to_magia_tile_ni_10_18_rsp ), - .floo_req_i ( router_10_18_to_magia_tile_ni_10_18_req ), - .floo_rsp_o ( magia_tile_ni_10_18_to_router_10_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][19] ), - .id_i ( '{x: 11, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_19_to_router_10_19_req ), - .floo_rsp_i ( router_10_19_to_magia_tile_ni_10_19_rsp ), - .floo_req_i ( router_10_19_to_magia_tile_ni_10_19_req ), - .floo_rsp_o ( magia_tile_ni_10_19_to_router_10_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][20] ), - .id_i ( '{x: 11, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_20_to_router_10_20_req ), - .floo_rsp_i ( router_10_20_to_magia_tile_ni_10_20_rsp ), - .floo_req_i ( router_10_20_to_magia_tile_ni_10_20_req ), - .floo_rsp_o ( magia_tile_ni_10_20_to_router_10_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][21] ), - .id_i ( '{x: 11, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_21_to_router_10_21_req ), - .floo_rsp_i ( router_10_21_to_magia_tile_ni_10_21_rsp ), - .floo_req_i ( router_10_21_to_magia_tile_ni_10_21_req ), - .floo_rsp_o ( magia_tile_ni_10_21_to_router_10_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][22] ), - .id_i ( '{x: 11, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_22_to_router_10_22_req ), - .floo_rsp_i ( router_10_22_to_magia_tile_ni_10_22_rsp ), - .floo_req_i ( router_10_22_to_magia_tile_ni_10_22_req ), - .floo_rsp_o ( magia_tile_ni_10_22_to_router_10_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][23] ), - .id_i ( '{x: 11, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_23_to_router_10_23_req ), - .floo_rsp_i ( router_10_23_to_magia_tile_ni_10_23_rsp ), - .floo_req_i ( router_10_23_to_magia_tile_ni_10_23_req ), - .floo_rsp_o ( magia_tile_ni_10_23_to_router_10_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][24] ), - .id_i ( '{x: 11, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_24_to_router_10_24_req ), - .floo_rsp_i ( router_10_24_to_magia_tile_ni_10_24_rsp ), - .floo_req_i ( router_10_24_to_magia_tile_ni_10_24_req ), - .floo_rsp_o ( magia_tile_ni_10_24_to_router_10_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][25] ), - .id_i ( '{x: 11, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_25_to_router_10_25_req ), - .floo_rsp_i ( router_10_25_to_magia_tile_ni_10_25_rsp ), - .floo_req_i ( router_10_25_to_magia_tile_ni_10_25_req ), - .floo_rsp_o ( magia_tile_ni_10_25_to_router_10_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][26] ), - .id_i ( '{x: 11, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_26_to_router_10_26_req ), - .floo_rsp_i ( router_10_26_to_magia_tile_ni_10_26_rsp ), - .floo_req_i ( router_10_26_to_magia_tile_ni_10_26_req ), - .floo_rsp_o ( magia_tile_ni_10_26_to_router_10_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][27] ), - .id_i ( '{x: 11, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_27_to_router_10_27_req ), - .floo_rsp_i ( router_10_27_to_magia_tile_ni_10_27_rsp ), - .floo_req_i ( router_10_27_to_magia_tile_ni_10_27_req ), - .floo_rsp_o ( magia_tile_ni_10_27_to_router_10_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][28] ), - .id_i ( '{x: 11, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_28_to_router_10_28_req ), - .floo_rsp_i ( router_10_28_to_magia_tile_ni_10_28_rsp ), - .floo_req_i ( router_10_28_to_magia_tile_ni_10_28_req ), - .floo_rsp_o ( magia_tile_ni_10_28_to_router_10_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][29] ), - .id_i ( '{x: 11, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_29_to_router_10_29_req ), - .floo_rsp_i ( router_10_29_to_magia_tile_ni_10_29_rsp ), - .floo_req_i ( router_10_29_to_magia_tile_ni_10_29_req ), - .floo_rsp_o ( magia_tile_ni_10_29_to_router_10_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][30] ), - .id_i ( '{x: 11, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_30_to_router_10_30_req ), - .floo_rsp_i ( router_10_30_to_magia_tile_ni_10_30_rsp ), - .floo_req_i ( router_10_30_to_magia_tile_ni_10_30_req ), - .floo_rsp_o ( magia_tile_ni_10_30_to_router_10_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_10_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[10][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[10][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[10][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[10][31] ), - .id_i ( '{x: 11, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_10_31_to_router_10_31_req ), - .floo_rsp_i ( router_10_31_to_magia_tile_ni_10_31_rsp ), - .floo_req_i ( router_10_31_to_magia_tile_ni_10_31_req ), - .floo_rsp_o ( magia_tile_ni_10_31_to_router_10_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][0] ), - .id_i ( '{x: 12, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_0_to_router_11_0_req ), - .floo_rsp_i ( router_11_0_to_magia_tile_ni_11_0_rsp ), - .floo_req_i ( router_11_0_to_magia_tile_ni_11_0_req ), - .floo_rsp_o ( magia_tile_ni_11_0_to_router_11_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][1] ), - .id_i ( '{x: 12, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_1_to_router_11_1_req ), - .floo_rsp_i ( router_11_1_to_magia_tile_ni_11_1_rsp ), - .floo_req_i ( router_11_1_to_magia_tile_ni_11_1_req ), - .floo_rsp_o ( magia_tile_ni_11_1_to_router_11_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][2] ), - .id_i ( '{x: 12, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_2_to_router_11_2_req ), - .floo_rsp_i ( router_11_2_to_magia_tile_ni_11_2_rsp ), - .floo_req_i ( router_11_2_to_magia_tile_ni_11_2_req ), - .floo_rsp_o ( magia_tile_ni_11_2_to_router_11_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][3] ), - .id_i ( '{x: 12, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_3_to_router_11_3_req ), - .floo_rsp_i ( router_11_3_to_magia_tile_ni_11_3_rsp ), - .floo_req_i ( router_11_3_to_magia_tile_ni_11_3_req ), - .floo_rsp_o ( magia_tile_ni_11_3_to_router_11_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][4] ), - .id_i ( '{x: 12, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_4_to_router_11_4_req ), - .floo_rsp_i ( router_11_4_to_magia_tile_ni_11_4_rsp ), - .floo_req_i ( router_11_4_to_magia_tile_ni_11_4_req ), - .floo_rsp_o ( magia_tile_ni_11_4_to_router_11_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][5] ), - .id_i ( '{x: 12, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_5_to_router_11_5_req ), - .floo_rsp_i ( router_11_5_to_magia_tile_ni_11_5_rsp ), - .floo_req_i ( router_11_5_to_magia_tile_ni_11_5_req ), - .floo_rsp_o ( magia_tile_ni_11_5_to_router_11_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][6] ), - .id_i ( '{x: 12, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_6_to_router_11_6_req ), - .floo_rsp_i ( router_11_6_to_magia_tile_ni_11_6_rsp ), - .floo_req_i ( router_11_6_to_magia_tile_ni_11_6_req ), - .floo_rsp_o ( magia_tile_ni_11_6_to_router_11_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][7] ), - .id_i ( '{x: 12, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_7_to_router_11_7_req ), - .floo_rsp_i ( router_11_7_to_magia_tile_ni_11_7_rsp ), - .floo_req_i ( router_11_7_to_magia_tile_ni_11_7_req ), - .floo_rsp_o ( magia_tile_ni_11_7_to_router_11_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][8] ), - .id_i ( '{x: 12, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_8_to_router_11_8_req ), - .floo_rsp_i ( router_11_8_to_magia_tile_ni_11_8_rsp ), - .floo_req_i ( router_11_8_to_magia_tile_ni_11_8_req ), - .floo_rsp_o ( magia_tile_ni_11_8_to_router_11_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][9] ), - .id_i ( '{x: 12, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_9_to_router_11_9_req ), - .floo_rsp_i ( router_11_9_to_magia_tile_ni_11_9_rsp ), - .floo_req_i ( router_11_9_to_magia_tile_ni_11_9_req ), - .floo_rsp_o ( magia_tile_ni_11_9_to_router_11_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][10] ), - .id_i ( '{x: 12, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_10_to_router_11_10_req ), - .floo_rsp_i ( router_11_10_to_magia_tile_ni_11_10_rsp ), - .floo_req_i ( router_11_10_to_magia_tile_ni_11_10_req ), - .floo_rsp_o ( magia_tile_ni_11_10_to_router_11_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][11] ), - .id_i ( '{x: 12, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_11_to_router_11_11_req ), - .floo_rsp_i ( router_11_11_to_magia_tile_ni_11_11_rsp ), - .floo_req_i ( router_11_11_to_magia_tile_ni_11_11_req ), - .floo_rsp_o ( magia_tile_ni_11_11_to_router_11_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][12] ), - .id_i ( '{x: 12, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_12_to_router_11_12_req ), - .floo_rsp_i ( router_11_12_to_magia_tile_ni_11_12_rsp ), - .floo_req_i ( router_11_12_to_magia_tile_ni_11_12_req ), - .floo_rsp_o ( magia_tile_ni_11_12_to_router_11_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][13] ), - .id_i ( '{x: 12, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_13_to_router_11_13_req ), - .floo_rsp_i ( router_11_13_to_magia_tile_ni_11_13_rsp ), - .floo_req_i ( router_11_13_to_magia_tile_ni_11_13_req ), - .floo_rsp_o ( magia_tile_ni_11_13_to_router_11_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][14] ), - .id_i ( '{x: 12, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_14_to_router_11_14_req ), - .floo_rsp_i ( router_11_14_to_magia_tile_ni_11_14_rsp ), - .floo_req_i ( router_11_14_to_magia_tile_ni_11_14_req ), - .floo_rsp_o ( magia_tile_ni_11_14_to_router_11_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][15] ), - .id_i ( '{x: 12, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_15_to_router_11_15_req ), - .floo_rsp_i ( router_11_15_to_magia_tile_ni_11_15_rsp ), - .floo_req_i ( router_11_15_to_magia_tile_ni_11_15_req ), - .floo_rsp_o ( magia_tile_ni_11_15_to_router_11_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][16] ), - .id_i ( '{x: 12, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_16_to_router_11_16_req ), - .floo_rsp_i ( router_11_16_to_magia_tile_ni_11_16_rsp ), - .floo_req_i ( router_11_16_to_magia_tile_ni_11_16_req ), - .floo_rsp_o ( magia_tile_ni_11_16_to_router_11_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][17] ), - .id_i ( '{x: 12, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_17_to_router_11_17_req ), - .floo_rsp_i ( router_11_17_to_magia_tile_ni_11_17_rsp ), - .floo_req_i ( router_11_17_to_magia_tile_ni_11_17_req ), - .floo_rsp_o ( magia_tile_ni_11_17_to_router_11_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][18] ), - .id_i ( '{x: 12, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_18_to_router_11_18_req ), - .floo_rsp_i ( router_11_18_to_magia_tile_ni_11_18_rsp ), - .floo_req_i ( router_11_18_to_magia_tile_ni_11_18_req ), - .floo_rsp_o ( magia_tile_ni_11_18_to_router_11_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][19] ), - .id_i ( '{x: 12, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_19_to_router_11_19_req ), - .floo_rsp_i ( router_11_19_to_magia_tile_ni_11_19_rsp ), - .floo_req_i ( router_11_19_to_magia_tile_ni_11_19_req ), - .floo_rsp_o ( magia_tile_ni_11_19_to_router_11_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][20] ), - .id_i ( '{x: 12, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_20_to_router_11_20_req ), - .floo_rsp_i ( router_11_20_to_magia_tile_ni_11_20_rsp ), - .floo_req_i ( router_11_20_to_magia_tile_ni_11_20_req ), - .floo_rsp_o ( magia_tile_ni_11_20_to_router_11_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][21] ), - .id_i ( '{x: 12, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_21_to_router_11_21_req ), - .floo_rsp_i ( router_11_21_to_magia_tile_ni_11_21_rsp ), - .floo_req_i ( router_11_21_to_magia_tile_ni_11_21_req ), - .floo_rsp_o ( magia_tile_ni_11_21_to_router_11_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][22] ), - .id_i ( '{x: 12, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_22_to_router_11_22_req ), - .floo_rsp_i ( router_11_22_to_magia_tile_ni_11_22_rsp ), - .floo_req_i ( router_11_22_to_magia_tile_ni_11_22_req ), - .floo_rsp_o ( magia_tile_ni_11_22_to_router_11_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][23] ), - .id_i ( '{x: 12, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_23_to_router_11_23_req ), - .floo_rsp_i ( router_11_23_to_magia_tile_ni_11_23_rsp ), - .floo_req_i ( router_11_23_to_magia_tile_ni_11_23_req ), - .floo_rsp_o ( magia_tile_ni_11_23_to_router_11_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][24] ), - .id_i ( '{x: 12, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_24_to_router_11_24_req ), - .floo_rsp_i ( router_11_24_to_magia_tile_ni_11_24_rsp ), - .floo_req_i ( router_11_24_to_magia_tile_ni_11_24_req ), - .floo_rsp_o ( magia_tile_ni_11_24_to_router_11_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][25] ), - .id_i ( '{x: 12, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_25_to_router_11_25_req ), - .floo_rsp_i ( router_11_25_to_magia_tile_ni_11_25_rsp ), - .floo_req_i ( router_11_25_to_magia_tile_ni_11_25_req ), - .floo_rsp_o ( magia_tile_ni_11_25_to_router_11_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][26] ), - .id_i ( '{x: 12, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_26_to_router_11_26_req ), - .floo_rsp_i ( router_11_26_to_magia_tile_ni_11_26_rsp ), - .floo_req_i ( router_11_26_to_magia_tile_ni_11_26_req ), - .floo_rsp_o ( magia_tile_ni_11_26_to_router_11_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][27] ), - .id_i ( '{x: 12, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_27_to_router_11_27_req ), - .floo_rsp_i ( router_11_27_to_magia_tile_ni_11_27_rsp ), - .floo_req_i ( router_11_27_to_magia_tile_ni_11_27_req ), - .floo_rsp_o ( magia_tile_ni_11_27_to_router_11_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][28] ), - .id_i ( '{x: 12, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_28_to_router_11_28_req ), - .floo_rsp_i ( router_11_28_to_magia_tile_ni_11_28_rsp ), - .floo_req_i ( router_11_28_to_magia_tile_ni_11_28_req ), - .floo_rsp_o ( magia_tile_ni_11_28_to_router_11_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][29] ), - .id_i ( '{x: 12, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_29_to_router_11_29_req ), - .floo_rsp_i ( router_11_29_to_magia_tile_ni_11_29_rsp ), - .floo_req_i ( router_11_29_to_magia_tile_ni_11_29_req ), - .floo_rsp_o ( magia_tile_ni_11_29_to_router_11_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][30] ), - .id_i ( '{x: 12, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_30_to_router_11_30_req ), - .floo_rsp_i ( router_11_30_to_magia_tile_ni_11_30_rsp ), - .floo_req_i ( router_11_30_to_magia_tile_ni_11_30_req ), - .floo_rsp_o ( magia_tile_ni_11_30_to_router_11_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_11_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[11][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[11][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[11][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[11][31] ), - .id_i ( '{x: 12, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_11_31_to_router_11_31_req ), - .floo_rsp_i ( router_11_31_to_magia_tile_ni_11_31_rsp ), - .floo_req_i ( router_11_31_to_magia_tile_ni_11_31_req ), - .floo_rsp_o ( magia_tile_ni_11_31_to_router_11_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][0] ), - .id_i ( '{x: 13, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_0_to_router_12_0_req ), - .floo_rsp_i ( router_12_0_to_magia_tile_ni_12_0_rsp ), - .floo_req_i ( router_12_0_to_magia_tile_ni_12_0_req ), - .floo_rsp_o ( magia_tile_ni_12_0_to_router_12_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][1] ), - .id_i ( '{x: 13, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_1_to_router_12_1_req ), - .floo_rsp_i ( router_12_1_to_magia_tile_ni_12_1_rsp ), - .floo_req_i ( router_12_1_to_magia_tile_ni_12_1_req ), - .floo_rsp_o ( magia_tile_ni_12_1_to_router_12_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][2] ), - .id_i ( '{x: 13, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_2_to_router_12_2_req ), - .floo_rsp_i ( router_12_2_to_magia_tile_ni_12_2_rsp ), - .floo_req_i ( router_12_2_to_magia_tile_ni_12_2_req ), - .floo_rsp_o ( magia_tile_ni_12_2_to_router_12_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][3] ), - .id_i ( '{x: 13, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_3_to_router_12_3_req ), - .floo_rsp_i ( router_12_3_to_magia_tile_ni_12_3_rsp ), - .floo_req_i ( router_12_3_to_magia_tile_ni_12_3_req ), - .floo_rsp_o ( magia_tile_ni_12_3_to_router_12_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][4] ), - .id_i ( '{x: 13, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_4_to_router_12_4_req ), - .floo_rsp_i ( router_12_4_to_magia_tile_ni_12_4_rsp ), - .floo_req_i ( router_12_4_to_magia_tile_ni_12_4_req ), - .floo_rsp_o ( magia_tile_ni_12_4_to_router_12_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][5] ), - .id_i ( '{x: 13, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_5_to_router_12_5_req ), - .floo_rsp_i ( router_12_5_to_magia_tile_ni_12_5_rsp ), - .floo_req_i ( router_12_5_to_magia_tile_ni_12_5_req ), - .floo_rsp_o ( magia_tile_ni_12_5_to_router_12_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][6] ), - .id_i ( '{x: 13, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_6_to_router_12_6_req ), - .floo_rsp_i ( router_12_6_to_magia_tile_ni_12_6_rsp ), - .floo_req_i ( router_12_6_to_magia_tile_ni_12_6_req ), - .floo_rsp_o ( magia_tile_ni_12_6_to_router_12_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][7] ), - .id_i ( '{x: 13, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_7_to_router_12_7_req ), - .floo_rsp_i ( router_12_7_to_magia_tile_ni_12_7_rsp ), - .floo_req_i ( router_12_7_to_magia_tile_ni_12_7_req ), - .floo_rsp_o ( magia_tile_ni_12_7_to_router_12_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][8] ), - .id_i ( '{x: 13, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_8_to_router_12_8_req ), - .floo_rsp_i ( router_12_8_to_magia_tile_ni_12_8_rsp ), - .floo_req_i ( router_12_8_to_magia_tile_ni_12_8_req ), - .floo_rsp_o ( magia_tile_ni_12_8_to_router_12_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][9] ), - .id_i ( '{x: 13, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_9_to_router_12_9_req ), - .floo_rsp_i ( router_12_9_to_magia_tile_ni_12_9_rsp ), - .floo_req_i ( router_12_9_to_magia_tile_ni_12_9_req ), - .floo_rsp_o ( magia_tile_ni_12_9_to_router_12_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][10] ), - .id_i ( '{x: 13, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_10_to_router_12_10_req ), - .floo_rsp_i ( router_12_10_to_magia_tile_ni_12_10_rsp ), - .floo_req_i ( router_12_10_to_magia_tile_ni_12_10_req ), - .floo_rsp_o ( magia_tile_ni_12_10_to_router_12_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][11] ), - .id_i ( '{x: 13, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_11_to_router_12_11_req ), - .floo_rsp_i ( router_12_11_to_magia_tile_ni_12_11_rsp ), - .floo_req_i ( router_12_11_to_magia_tile_ni_12_11_req ), - .floo_rsp_o ( magia_tile_ni_12_11_to_router_12_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][12] ), - .id_i ( '{x: 13, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_12_to_router_12_12_req ), - .floo_rsp_i ( router_12_12_to_magia_tile_ni_12_12_rsp ), - .floo_req_i ( router_12_12_to_magia_tile_ni_12_12_req ), - .floo_rsp_o ( magia_tile_ni_12_12_to_router_12_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][13] ), - .id_i ( '{x: 13, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_13_to_router_12_13_req ), - .floo_rsp_i ( router_12_13_to_magia_tile_ni_12_13_rsp ), - .floo_req_i ( router_12_13_to_magia_tile_ni_12_13_req ), - .floo_rsp_o ( magia_tile_ni_12_13_to_router_12_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][14] ), - .id_i ( '{x: 13, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_14_to_router_12_14_req ), - .floo_rsp_i ( router_12_14_to_magia_tile_ni_12_14_rsp ), - .floo_req_i ( router_12_14_to_magia_tile_ni_12_14_req ), - .floo_rsp_o ( magia_tile_ni_12_14_to_router_12_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][15] ), - .id_i ( '{x: 13, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_15_to_router_12_15_req ), - .floo_rsp_i ( router_12_15_to_magia_tile_ni_12_15_rsp ), - .floo_req_i ( router_12_15_to_magia_tile_ni_12_15_req ), - .floo_rsp_o ( magia_tile_ni_12_15_to_router_12_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][16] ), - .id_i ( '{x: 13, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_16_to_router_12_16_req ), - .floo_rsp_i ( router_12_16_to_magia_tile_ni_12_16_rsp ), - .floo_req_i ( router_12_16_to_magia_tile_ni_12_16_req ), - .floo_rsp_o ( magia_tile_ni_12_16_to_router_12_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][17] ), - .id_i ( '{x: 13, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_17_to_router_12_17_req ), - .floo_rsp_i ( router_12_17_to_magia_tile_ni_12_17_rsp ), - .floo_req_i ( router_12_17_to_magia_tile_ni_12_17_req ), - .floo_rsp_o ( magia_tile_ni_12_17_to_router_12_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][18] ), - .id_i ( '{x: 13, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_18_to_router_12_18_req ), - .floo_rsp_i ( router_12_18_to_magia_tile_ni_12_18_rsp ), - .floo_req_i ( router_12_18_to_magia_tile_ni_12_18_req ), - .floo_rsp_o ( magia_tile_ni_12_18_to_router_12_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][19] ), - .id_i ( '{x: 13, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_19_to_router_12_19_req ), - .floo_rsp_i ( router_12_19_to_magia_tile_ni_12_19_rsp ), - .floo_req_i ( router_12_19_to_magia_tile_ni_12_19_req ), - .floo_rsp_o ( magia_tile_ni_12_19_to_router_12_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][20] ), - .id_i ( '{x: 13, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_20_to_router_12_20_req ), - .floo_rsp_i ( router_12_20_to_magia_tile_ni_12_20_rsp ), - .floo_req_i ( router_12_20_to_magia_tile_ni_12_20_req ), - .floo_rsp_o ( magia_tile_ni_12_20_to_router_12_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][21] ), - .id_i ( '{x: 13, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_21_to_router_12_21_req ), - .floo_rsp_i ( router_12_21_to_magia_tile_ni_12_21_rsp ), - .floo_req_i ( router_12_21_to_magia_tile_ni_12_21_req ), - .floo_rsp_o ( magia_tile_ni_12_21_to_router_12_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][22] ), - .id_i ( '{x: 13, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_22_to_router_12_22_req ), - .floo_rsp_i ( router_12_22_to_magia_tile_ni_12_22_rsp ), - .floo_req_i ( router_12_22_to_magia_tile_ni_12_22_req ), - .floo_rsp_o ( magia_tile_ni_12_22_to_router_12_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][23] ), - .id_i ( '{x: 13, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_23_to_router_12_23_req ), - .floo_rsp_i ( router_12_23_to_magia_tile_ni_12_23_rsp ), - .floo_req_i ( router_12_23_to_magia_tile_ni_12_23_req ), - .floo_rsp_o ( magia_tile_ni_12_23_to_router_12_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][24] ), - .id_i ( '{x: 13, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_24_to_router_12_24_req ), - .floo_rsp_i ( router_12_24_to_magia_tile_ni_12_24_rsp ), - .floo_req_i ( router_12_24_to_magia_tile_ni_12_24_req ), - .floo_rsp_o ( magia_tile_ni_12_24_to_router_12_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][25] ), - .id_i ( '{x: 13, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_25_to_router_12_25_req ), - .floo_rsp_i ( router_12_25_to_magia_tile_ni_12_25_rsp ), - .floo_req_i ( router_12_25_to_magia_tile_ni_12_25_req ), - .floo_rsp_o ( magia_tile_ni_12_25_to_router_12_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][26] ), - .id_i ( '{x: 13, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_26_to_router_12_26_req ), - .floo_rsp_i ( router_12_26_to_magia_tile_ni_12_26_rsp ), - .floo_req_i ( router_12_26_to_magia_tile_ni_12_26_req ), - .floo_rsp_o ( magia_tile_ni_12_26_to_router_12_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][27] ), - .id_i ( '{x: 13, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_27_to_router_12_27_req ), - .floo_rsp_i ( router_12_27_to_magia_tile_ni_12_27_rsp ), - .floo_req_i ( router_12_27_to_magia_tile_ni_12_27_req ), - .floo_rsp_o ( magia_tile_ni_12_27_to_router_12_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][28] ), - .id_i ( '{x: 13, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_28_to_router_12_28_req ), - .floo_rsp_i ( router_12_28_to_magia_tile_ni_12_28_rsp ), - .floo_req_i ( router_12_28_to_magia_tile_ni_12_28_req ), - .floo_rsp_o ( magia_tile_ni_12_28_to_router_12_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][29] ), - .id_i ( '{x: 13, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_29_to_router_12_29_req ), - .floo_rsp_i ( router_12_29_to_magia_tile_ni_12_29_rsp ), - .floo_req_i ( router_12_29_to_magia_tile_ni_12_29_req ), - .floo_rsp_o ( magia_tile_ni_12_29_to_router_12_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][30] ), - .id_i ( '{x: 13, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_30_to_router_12_30_req ), - .floo_rsp_i ( router_12_30_to_magia_tile_ni_12_30_rsp ), - .floo_req_i ( router_12_30_to_magia_tile_ni_12_30_req ), - .floo_rsp_o ( magia_tile_ni_12_30_to_router_12_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_12_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[12][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[12][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[12][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[12][31] ), - .id_i ( '{x: 13, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_12_31_to_router_12_31_req ), - .floo_rsp_i ( router_12_31_to_magia_tile_ni_12_31_rsp ), - .floo_req_i ( router_12_31_to_magia_tile_ni_12_31_req ), - .floo_rsp_o ( magia_tile_ni_12_31_to_router_12_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][0] ), - .id_i ( '{x: 14, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_0_to_router_13_0_req ), - .floo_rsp_i ( router_13_0_to_magia_tile_ni_13_0_rsp ), - .floo_req_i ( router_13_0_to_magia_tile_ni_13_0_req ), - .floo_rsp_o ( magia_tile_ni_13_0_to_router_13_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][1] ), - .id_i ( '{x: 14, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_1_to_router_13_1_req ), - .floo_rsp_i ( router_13_1_to_magia_tile_ni_13_1_rsp ), - .floo_req_i ( router_13_1_to_magia_tile_ni_13_1_req ), - .floo_rsp_o ( magia_tile_ni_13_1_to_router_13_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][2] ), - .id_i ( '{x: 14, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_2_to_router_13_2_req ), - .floo_rsp_i ( router_13_2_to_magia_tile_ni_13_2_rsp ), - .floo_req_i ( router_13_2_to_magia_tile_ni_13_2_req ), - .floo_rsp_o ( magia_tile_ni_13_2_to_router_13_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][3] ), - .id_i ( '{x: 14, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_3_to_router_13_3_req ), - .floo_rsp_i ( router_13_3_to_magia_tile_ni_13_3_rsp ), - .floo_req_i ( router_13_3_to_magia_tile_ni_13_3_req ), - .floo_rsp_o ( magia_tile_ni_13_3_to_router_13_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][4] ), - .id_i ( '{x: 14, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_4_to_router_13_4_req ), - .floo_rsp_i ( router_13_4_to_magia_tile_ni_13_4_rsp ), - .floo_req_i ( router_13_4_to_magia_tile_ni_13_4_req ), - .floo_rsp_o ( magia_tile_ni_13_4_to_router_13_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][5] ), - .id_i ( '{x: 14, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_5_to_router_13_5_req ), - .floo_rsp_i ( router_13_5_to_magia_tile_ni_13_5_rsp ), - .floo_req_i ( router_13_5_to_magia_tile_ni_13_5_req ), - .floo_rsp_o ( magia_tile_ni_13_5_to_router_13_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][6] ), - .id_i ( '{x: 14, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_6_to_router_13_6_req ), - .floo_rsp_i ( router_13_6_to_magia_tile_ni_13_6_rsp ), - .floo_req_i ( router_13_6_to_magia_tile_ni_13_6_req ), - .floo_rsp_o ( magia_tile_ni_13_6_to_router_13_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][7] ), - .id_i ( '{x: 14, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_7_to_router_13_7_req ), - .floo_rsp_i ( router_13_7_to_magia_tile_ni_13_7_rsp ), - .floo_req_i ( router_13_7_to_magia_tile_ni_13_7_req ), - .floo_rsp_o ( magia_tile_ni_13_7_to_router_13_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][8] ), - .id_i ( '{x: 14, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_8_to_router_13_8_req ), - .floo_rsp_i ( router_13_8_to_magia_tile_ni_13_8_rsp ), - .floo_req_i ( router_13_8_to_magia_tile_ni_13_8_req ), - .floo_rsp_o ( magia_tile_ni_13_8_to_router_13_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][9] ), - .id_i ( '{x: 14, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_9_to_router_13_9_req ), - .floo_rsp_i ( router_13_9_to_magia_tile_ni_13_9_rsp ), - .floo_req_i ( router_13_9_to_magia_tile_ni_13_9_req ), - .floo_rsp_o ( magia_tile_ni_13_9_to_router_13_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][10] ), - .id_i ( '{x: 14, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_10_to_router_13_10_req ), - .floo_rsp_i ( router_13_10_to_magia_tile_ni_13_10_rsp ), - .floo_req_i ( router_13_10_to_magia_tile_ni_13_10_req ), - .floo_rsp_o ( magia_tile_ni_13_10_to_router_13_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][11] ), - .id_i ( '{x: 14, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_11_to_router_13_11_req ), - .floo_rsp_i ( router_13_11_to_magia_tile_ni_13_11_rsp ), - .floo_req_i ( router_13_11_to_magia_tile_ni_13_11_req ), - .floo_rsp_o ( magia_tile_ni_13_11_to_router_13_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][12] ), - .id_i ( '{x: 14, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_12_to_router_13_12_req ), - .floo_rsp_i ( router_13_12_to_magia_tile_ni_13_12_rsp ), - .floo_req_i ( router_13_12_to_magia_tile_ni_13_12_req ), - .floo_rsp_o ( magia_tile_ni_13_12_to_router_13_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][13] ), - .id_i ( '{x: 14, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_13_to_router_13_13_req ), - .floo_rsp_i ( router_13_13_to_magia_tile_ni_13_13_rsp ), - .floo_req_i ( router_13_13_to_magia_tile_ni_13_13_req ), - .floo_rsp_o ( magia_tile_ni_13_13_to_router_13_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][14] ), - .id_i ( '{x: 14, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_14_to_router_13_14_req ), - .floo_rsp_i ( router_13_14_to_magia_tile_ni_13_14_rsp ), - .floo_req_i ( router_13_14_to_magia_tile_ni_13_14_req ), - .floo_rsp_o ( magia_tile_ni_13_14_to_router_13_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][15] ), - .id_i ( '{x: 14, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_15_to_router_13_15_req ), - .floo_rsp_i ( router_13_15_to_magia_tile_ni_13_15_rsp ), - .floo_req_i ( router_13_15_to_magia_tile_ni_13_15_req ), - .floo_rsp_o ( magia_tile_ni_13_15_to_router_13_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][16] ), - .id_i ( '{x: 14, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_16_to_router_13_16_req ), - .floo_rsp_i ( router_13_16_to_magia_tile_ni_13_16_rsp ), - .floo_req_i ( router_13_16_to_magia_tile_ni_13_16_req ), - .floo_rsp_o ( magia_tile_ni_13_16_to_router_13_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][17] ), - .id_i ( '{x: 14, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_17_to_router_13_17_req ), - .floo_rsp_i ( router_13_17_to_magia_tile_ni_13_17_rsp ), - .floo_req_i ( router_13_17_to_magia_tile_ni_13_17_req ), - .floo_rsp_o ( magia_tile_ni_13_17_to_router_13_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][18] ), - .id_i ( '{x: 14, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_18_to_router_13_18_req ), - .floo_rsp_i ( router_13_18_to_magia_tile_ni_13_18_rsp ), - .floo_req_i ( router_13_18_to_magia_tile_ni_13_18_req ), - .floo_rsp_o ( magia_tile_ni_13_18_to_router_13_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][19] ), - .id_i ( '{x: 14, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_19_to_router_13_19_req ), - .floo_rsp_i ( router_13_19_to_magia_tile_ni_13_19_rsp ), - .floo_req_i ( router_13_19_to_magia_tile_ni_13_19_req ), - .floo_rsp_o ( magia_tile_ni_13_19_to_router_13_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][20] ), - .id_i ( '{x: 14, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_20_to_router_13_20_req ), - .floo_rsp_i ( router_13_20_to_magia_tile_ni_13_20_rsp ), - .floo_req_i ( router_13_20_to_magia_tile_ni_13_20_req ), - .floo_rsp_o ( magia_tile_ni_13_20_to_router_13_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][21] ), - .id_i ( '{x: 14, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_21_to_router_13_21_req ), - .floo_rsp_i ( router_13_21_to_magia_tile_ni_13_21_rsp ), - .floo_req_i ( router_13_21_to_magia_tile_ni_13_21_req ), - .floo_rsp_o ( magia_tile_ni_13_21_to_router_13_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][22] ), - .id_i ( '{x: 14, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_22_to_router_13_22_req ), - .floo_rsp_i ( router_13_22_to_magia_tile_ni_13_22_rsp ), - .floo_req_i ( router_13_22_to_magia_tile_ni_13_22_req ), - .floo_rsp_o ( magia_tile_ni_13_22_to_router_13_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][23] ), - .id_i ( '{x: 14, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_23_to_router_13_23_req ), - .floo_rsp_i ( router_13_23_to_magia_tile_ni_13_23_rsp ), - .floo_req_i ( router_13_23_to_magia_tile_ni_13_23_req ), - .floo_rsp_o ( magia_tile_ni_13_23_to_router_13_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][24] ), - .id_i ( '{x: 14, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_24_to_router_13_24_req ), - .floo_rsp_i ( router_13_24_to_magia_tile_ni_13_24_rsp ), - .floo_req_i ( router_13_24_to_magia_tile_ni_13_24_req ), - .floo_rsp_o ( magia_tile_ni_13_24_to_router_13_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][25] ), - .id_i ( '{x: 14, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_25_to_router_13_25_req ), - .floo_rsp_i ( router_13_25_to_magia_tile_ni_13_25_rsp ), - .floo_req_i ( router_13_25_to_magia_tile_ni_13_25_req ), - .floo_rsp_o ( magia_tile_ni_13_25_to_router_13_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][26] ), - .id_i ( '{x: 14, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_26_to_router_13_26_req ), - .floo_rsp_i ( router_13_26_to_magia_tile_ni_13_26_rsp ), - .floo_req_i ( router_13_26_to_magia_tile_ni_13_26_req ), - .floo_rsp_o ( magia_tile_ni_13_26_to_router_13_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][27] ), - .id_i ( '{x: 14, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_27_to_router_13_27_req ), - .floo_rsp_i ( router_13_27_to_magia_tile_ni_13_27_rsp ), - .floo_req_i ( router_13_27_to_magia_tile_ni_13_27_req ), - .floo_rsp_o ( magia_tile_ni_13_27_to_router_13_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][28] ), - .id_i ( '{x: 14, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_28_to_router_13_28_req ), - .floo_rsp_i ( router_13_28_to_magia_tile_ni_13_28_rsp ), - .floo_req_i ( router_13_28_to_magia_tile_ni_13_28_req ), - .floo_rsp_o ( magia_tile_ni_13_28_to_router_13_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][29] ), - .id_i ( '{x: 14, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_29_to_router_13_29_req ), - .floo_rsp_i ( router_13_29_to_magia_tile_ni_13_29_rsp ), - .floo_req_i ( router_13_29_to_magia_tile_ni_13_29_req ), - .floo_rsp_o ( magia_tile_ni_13_29_to_router_13_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][30] ), - .id_i ( '{x: 14, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_30_to_router_13_30_req ), - .floo_rsp_i ( router_13_30_to_magia_tile_ni_13_30_rsp ), - .floo_req_i ( router_13_30_to_magia_tile_ni_13_30_req ), - .floo_rsp_o ( magia_tile_ni_13_30_to_router_13_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_13_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[13][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[13][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[13][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[13][31] ), - .id_i ( '{x: 14, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_13_31_to_router_13_31_req ), - .floo_rsp_i ( router_13_31_to_magia_tile_ni_13_31_rsp ), - .floo_req_i ( router_13_31_to_magia_tile_ni_13_31_req ), - .floo_rsp_o ( magia_tile_ni_13_31_to_router_13_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][0] ), - .id_i ( '{x: 15, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_0_to_router_14_0_req ), - .floo_rsp_i ( router_14_0_to_magia_tile_ni_14_0_rsp ), - .floo_req_i ( router_14_0_to_magia_tile_ni_14_0_req ), - .floo_rsp_o ( magia_tile_ni_14_0_to_router_14_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][1] ), - .id_i ( '{x: 15, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_1_to_router_14_1_req ), - .floo_rsp_i ( router_14_1_to_magia_tile_ni_14_1_rsp ), - .floo_req_i ( router_14_1_to_magia_tile_ni_14_1_req ), - .floo_rsp_o ( magia_tile_ni_14_1_to_router_14_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][2] ), - .id_i ( '{x: 15, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_2_to_router_14_2_req ), - .floo_rsp_i ( router_14_2_to_magia_tile_ni_14_2_rsp ), - .floo_req_i ( router_14_2_to_magia_tile_ni_14_2_req ), - .floo_rsp_o ( magia_tile_ni_14_2_to_router_14_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][3] ), - .id_i ( '{x: 15, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_3_to_router_14_3_req ), - .floo_rsp_i ( router_14_3_to_magia_tile_ni_14_3_rsp ), - .floo_req_i ( router_14_3_to_magia_tile_ni_14_3_req ), - .floo_rsp_o ( magia_tile_ni_14_3_to_router_14_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][4] ), - .id_i ( '{x: 15, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_4_to_router_14_4_req ), - .floo_rsp_i ( router_14_4_to_magia_tile_ni_14_4_rsp ), - .floo_req_i ( router_14_4_to_magia_tile_ni_14_4_req ), - .floo_rsp_o ( magia_tile_ni_14_4_to_router_14_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][5] ), - .id_i ( '{x: 15, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_5_to_router_14_5_req ), - .floo_rsp_i ( router_14_5_to_magia_tile_ni_14_5_rsp ), - .floo_req_i ( router_14_5_to_magia_tile_ni_14_5_req ), - .floo_rsp_o ( magia_tile_ni_14_5_to_router_14_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][6] ), - .id_i ( '{x: 15, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_6_to_router_14_6_req ), - .floo_rsp_i ( router_14_6_to_magia_tile_ni_14_6_rsp ), - .floo_req_i ( router_14_6_to_magia_tile_ni_14_6_req ), - .floo_rsp_o ( magia_tile_ni_14_6_to_router_14_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][7] ), - .id_i ( '{x: 15, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_7_to_router_14_7_req ), - .floo_rsp_i ( router_14_7_to_magia_tile_ni_14_7_rsp ), - .floo_req_i ( router_14_7_to_magia_tile_ni_14_7_req ), - .floo_rsp_o ( magia_tile_ni_14_7_to_router_14_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][8] ), - .id_i ( '{x: 15, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_8_to_router_14_8_req ), - .floo_rsp_i ( router_14_8_to_magia_tile_ni_14_8_rsp ), - .floo_req_i ( router_14_8_to_magia_tile_ni_14_8_req ), - .floo_rsp_o ( magia_tile_ni_14_8_to_router_14_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][9] ), - .id_i ( '{x: 15, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_9_to_router_14_9_req ), - .floo_rsp_i ( router_14_9_to_magia_tile_ni_14_9_rsp ), - .floo_req_i ( router_14_9_to_magia_tile_ni_14_9_req ), - .floo_rsp_o ( magia_tile_ni_14_9_to_router_14_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][10] ), - .id_i ( '{x: 15, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_10_to_router_14_10_req ), - .floo_rsp_i ( router_14_10_to_magia_tile_ni_14_10_rsp ), - .floo_req_i ( router_14_10_to_magia_tile_ni_14_10_req ), - .floo_rsp_o ( magia_tile_ni_14_10_to_router_14_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][11] ), - .id_i ( '{x: 15, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_11_to_router_14_11_req ), - .floo_rsp_i ( router_14_11_to_magia_tile_ni_14_11_rsp ), - .floo_req_i ( router_14_11_to_magia_tile_ni_14_11_req ), - .floo_rsp_o ( magia_tile_ni_14_11_to_router_14_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][12] ), - .id_i ( '{x: 15, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_12_to_router_14_12_req ), - .floo_rsp_i ( router_14_12_to_magia_tile_ni_14_12_rsp ), - .floo_req_i ( router_14_12_to_magia_tile_ni_14_12_req ), - .floo_rsp_o ( magia_tile_ni_14_12_to_router_14_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][13] ), - .id_i ( '{x: 15, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_13_to_router_14_13_req ), - .floo_rsp_i ( router_14_13_to_magia_tile_ni_14_13_rsp ), - .floo_req_i ( router_14_13_to_magia_tile_ni_14_13_req ), - .floo_rsp_o ( magia_tile_ni_14_13_to_router_14_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][14] ), - .id_i ( '{x: 15, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_14_to_router_14_14_req ), - .floo_rsp_i ( router_14_14_to_magia_tile_ni_14_14_rsp ), - .floo_req_i ( router_14_14_to_magia_tile_ni_14_14_req ), - .floo_rsp_o ( magia_tile_ni_14_14_to_router_14_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][15] ), - .id_i ( '{x: 15, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_15_to_router_14_15_req ), - .floo_rsp_i ( router_14_15_to_magia_tile_ni_14_15_rsp ), - .floo_req_i ( router_14_15_to_magia_tile_ni_14_15_req ), - .floo_rsp_o ( magia_tile_ni_14_15_to_router_14_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][16] ), - .id_i ( '{x: 15, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_16_to_router_14_16_req ), - .floo_rsp_i ( router_14_16_to_magia_tile_ni_14_16_rsp ), - .floo_req_i ( router_14_16_to_magia_tile_ni_14_16_req ), - .floo_rsp_o ( magia_tile_ni_14_16_to_router_14_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][17] ), - .id_i ( '{x: 15, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_17_to_router_14_17_req ), - .floo_rsp_i ( router_14_17_to_magia_tile_ni_14_17_rsp ), - .floo_req_i ( router_14_17_to_magia_tile_ni_14_17_req ), - .floo_rsp_o ( magia_tile_ni_14_17_to_router_14_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][18] ), - .id_i ( '{x: 15, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_18_to_router_14_18_req ), - .floo_rsp_i ( router_14_18_to_magia_tile_ni_14_18_rsp ), - .floo_req_i ( router_14_18_to_magia_tile_ni_14_18_req ), - .floo_rsp_o ( magia_tile_ni_14_18_to_router_14_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][19] ), - .id_i ( '{x: 15, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_19_to_router_14_19_req ), - .floo_rsp_i ( router_14_19_to_magia_tile_ni_14_19_rsp ), - .floo_req_i ( router_14_19_to_magia_tile_ni_14_19_req ), - .floo_rsp_o ( magia_tile_ni_14_19_to_router_14_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][20] ), - .id_i ( '{x: 15, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_20_to_router_14_20_req ), - .floo_rsp_i ( router_14_20_to_magia_tile_ni_14_20_rsp ), - .floo_req_i ( router_14_20_to_magia_tile_ni_14_20_req ), - .floo_rsp_o ( magia_tile_ni_14_20_to_router_14_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][21] ), - .id_i ( '{x: 15, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_21_to_router_14_21_req ), - .floo_rsp_i ( router_14_21_to_magia_tile_ni_14_21_rsp ), - .floo_req_i ( router_14_21_to_magia_tile_ni_14_21_req ), - .floo_rsp_o ( magia_tile_ni_14_21_to_router_14_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][22] ), - .id_i ( '{x: 15, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_22_to_router_14_22_req ), - .floo_rsp_i ( router_14_22_to_magia_tile_ni_14_22_rsp ), - .floo_req_i ( router_14_22_to_magia_tile_ni_14_22_req ), - .floo_rsp_o ( magia_tile_ni_14_22_to_router_14_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][23] ), - .id_i ( '{x: 15, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_23_to_router_14_23_req ), - .floo_rsp_i ( router_14_23_to_magia_tile_ni_14_23_rsp ), - .floo_req_i ( router_14_23_to_magia_tile_ni_14_23_req ), - .floo_rsp_o ( magia_tile_ni_14_23_to_router_14_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][24] ), - .id_i ( '{x: 15, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_24_to_router_14_24_req ), - .floo_rsp_i ( router_14_24_to_magia_tile_ni_14_24_rsp ), - .floo_req_i ( router_14_24_to_magia_tile_ni_14_24_req ), - .floo_rsp_o ( magia_tile_ni_14_24_to_router_14_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][25] ), - .id_i ( '{x: 15, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_25_to_router_14_25_req ), - .floo_rsp_i ( router_14_25_to_magia_tile_ni_14_25_rsp ), - .floo_req_i ( router_14_25_to_magia_tile_ni_14_25_req ), - .floo_rsp_o ( magia_tile_ni_14_25_to_router_14_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][26] ), - .id_i ( '{x: 15, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_26_to_router_14_26_req ), - .floo_rsp_i ( router_14_26_to_magia_tile_ni_14_26_rsp ), - .floo_req_i ( router_14_26_to_magia_tile_ni_14_26_req ), - .floo_rsp_o ( magia_tile_ni_14_26_to_router_14_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][27] ), - .id_i ( '{x: 15, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_27_to_router_14_27_req ), - .floo_rsp_i ( router_14_27_to_magia_tile_ni_14_27_rsp ), - .floo_req_i ( router_14_27_to_magia_tile_ni_14_27_req ), - .floo_rsp_o ( magia_tile_ni_14_27_to_router_14_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][28] ), - .id_i ( '{x: 15, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_28_to_router_14_28_req ), - .floo_rsp_i ( router_14_28_to_magia_tile_ni_14_28_rsp ), - .floo_req_i ( router_14_28_to_magia_tile_ni_14_28_req ), - .floo_rsp_o ( magia_tile_ni_14_28_to_router_14_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][29] ), - .id_i ( '{x: 15, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_29_to_router_14_29_req ), - .floo_rsp_i ( router_14_29_to_magia_tile_ni_14_29_rsp ), - .floo_req_i ( router_14_29_to_magia_tile_ni_14_29_req ), - .floo_rsp_o ( magia_tile_ni_14_29_to_router_14_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][30] ), - .id_i ( '{x: 15, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_30_to_router_14_30_req ), - .floo_rsp_i ( router_14_30_to_magia_tile_ni_14_30_rsp ), - .floo_req_i ( router_14_30_to_magia_tile_ni_14_30_req ), - .floo_rsp_o ( magia_tile_ni_14_30_to_router_14_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_14_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[14][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[14][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[14][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[14][31] ), - .id_i ( '{x: 15, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_14_31_to_router_14_31_req ), - .floo_rsp_i ( router_14_31_to_magia_tile_ni_14_31_rsp ), - .floo_req_i ( router_14_31_to_magia_tile_ni_14_31_req ), - .floo_rsp_o ( magia_tile_ni_14_31_to_router_14_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][0] ), - .id_i ( '{x: 16, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_0_to_router_15_0_req ), - .floo_rsp_i ( router_15_0_to_magia_tile_ni_15_0_rsp ), - .floo_req_i ( router_15_0_to_magia_tile_ni_15_0_req ), - .floo_rsp_o ( magia_tile_ni_15_0_to_router_15_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][1] ), - .id_i ( '{x: 16, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_1_to_router_15_1_req ), - .floo_rsp_i ( router_15_1_to_magia_tile_ni_15_1_rsp ), - .floo_req_i ( router_15_1_to_magia_tile_ni_15_1_req ), - .floo_rsp_o ( magia_tile_ni_15_1_to_router_15_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][2] ), - .id_i ( '{x: 16, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_2_to_router_15_2_req ), - .floo_rsp_i ( router_15_2_to_magia_tile_ni_15_2_rsp ), - .floo_req_i ( router_15_2_to_magia_tile_ni_15_2_req ), - .floo_rsp_o ( magia_tile_ni_15_2_to_router_15_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][3] ), - .id_i ( '{x: 16, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_3_to_router_15_3_req ), - .floo_rsp_i ( router_15_3_to_magia_tile_ni_15_3_rsp ), - .floo_req_i ( router_15_3_to_magia_tile_ni_15_3_req ), - .floo_rsp_o ( magia_tile_ni_15_3_to_router_15_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][4] ), - .id_i ( '{x: 16, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_4_to_router_15_4_req ), - .floo_rsp_i ( router_15_4_to_magia_tile_ni_15_4_rsp ), - .floo_req_i ( router_15_4_to_magia_tile_ni_15_4_req ), - .floo_rsp_o ( magia_tile_ni_15_4_to_router_15_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][5] ), - .id_i ( '{x: 16, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_5_to_router_15_5_req ), - .floo_rsp_i ( router_15_5_to_magia_tile_ni_15_5_rsp ), - .floo_req_i ( router_15_5_to_magia_tile_ni_15_5_req ), - .floo_rsp_o ( magia_tile_ni_15_5_to_router_15_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][6] ), - .id_i ( '{x: 16, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_6_to_router_15_6_req ), - .floo_rsp_i ( router_15_6_to_magia_tile_ni_15_6_rsp ), - .floo_req_i ( router_15_6_to_magia_tile_ni_15_6_req ), - .floo_rsp_o ( magia_tile_ni_15_6_to_router_15_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][7] ), - .id_i ( '{x: 16, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_7_to_router_15_7_req ), - .floo_rsp_i ( router_15_7_to_magia_tile_ni_15_7_rsp ), - .floo_req_i ( router_15_7_to_magia_tile_ni_15_7_req ), - .floo_rsp_o ( magia_tile_ni_15_7_to_router_15_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][8] ), - .id_i ( '{x: 16, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_8_to_router_15_8_req ), - .floo_rsp_i ( router_15_8_to_magia_tile_ni_15_8_rsp ), - .floo_req_i ( router_15_8_to_magia_tile_ni_15_8_req ), - .floo_rsp_o ( magia_tile_ni_15_8_to_router_15_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][9] ), - .id_i ( '{x: 16, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_9_to_router_15_9_req ), - .floo_rsp_i ( router_15_9_to_magia_tile_ni_15_9_rsp ), - .floo_req_i ( router_15_9_to_magia_tile_ni_15_9_req ), - .floo_rsp_o ( magia_tile_ni_15_9_to_router_15_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][10] ), - .id_i ( '{x: 16, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_10_to_router_15_10_req ), - .floo_rsp_i ( router_15_10_to_magia_tile_ni_15_10_rsp ), - .floo_req_i ( router_15_10_to_magia_tile_ni_15_10_req ), - .floo_rsp_o ( magia_tile_ni_15_10_to_router_15_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][11] ), - .id_i ( '{x: 16, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_11_to_router_15_11_req ), - .floo_rsp_i ( router_15_11_to_magia_tile_ni_15_11_rsp ), - .floo_req_i ( router_15_11_to_magia_tile_ni_15_11_req ), - .floo_rsp_o ( magia_tile_ni_15_11_to_router_15_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][12] ), - .id_i ( '{x: 16, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_12_to_router_15_12_req ), - .floo_rsp_i ( router_15_12_to_magia_tile_ni_15_12_rsp ), - .floo_req_i ( router_15_12_to_magia_tile_ni_15_12_req ), - .floo_rsp_o ( magia_tile_ni_15_12_to_router_15_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][13] ), - .id_i ( '{x: 16, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_13_to_router_15_13_req ), - .floo_rsp_i ( router_15_13_to_magia_tile_ni_15_13_rsp ), - .floo_req_i ( router_15_13_to_magia_tile_ni_15_13_req ), - .floo_rsp_o ( magia_tile_ni_15_13_to_router_15_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][14] ), - .id_i ( '{x: 16, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_14_to_router_15_14_req ), - .floo_rsp_i ( router_15_14_to_magia_tile_ni_15_14_rsp ), - .floo_req_i ( router_15_14_to_magia_tile_ni_15_14_req ), - .floo_rsp_o ( magia_tile_ni_15_14_to_router_15_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][15] ), - .id_i ( '{x: 16, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_15_to_router_15_15_req ), - .floo_rsp_i ( router_15_15_to_magia_tile_ni_15_15_rsp ), - .floo_req_i ( router_15_15_to_magia_tile_ni_15_15_req ), - .floo_rsp_o ( magia_tile_ni_15_15_to_router_15_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][16] ), - .id_i ( '{x: 16, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_16_to_router_15_16_req ), - .floo_rsp_i ( router_15_16_to_magia_tile_ni_15_16_rsp ), - .floo_req_i ( router_15_16_to_magia_tile_ni_15_16_req ), - .floo_rsp_o ( magia_tile_ni_15_16_to_router_15_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][17] ), - .id_i ( '{x: 16, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_17_to_router_15_17_req ), - .floo_rsp_i ( router_15_17_to_magia_tile_ni_15_17_rsp ), - .floo_req_i ( router_15_17_to_magia_tile_ni_15_17_req ), - .floo_rsp_o ( magia_tile_ni_15_17_to_router_15_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][18] ), - .id_i ( '{x: 16, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_18_to_router_15_18_req ), - .floo_rsp_i ( router_15_18_to_magia_tile_ni_15_18_rsp ), - .floo_req_i ( router_15_18_to_magia_tile_ni_15_18_req ), - .floo_rsp_o ( magia_tile_ni_15_18_to_router_15_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][19] ), - .id_i ( '{x: 16, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_19_to_router_15_19_req ), - .floo_rsp_i ( router_15_19_to_magia_tile_ni_15_19_rsp ), - .floo_req_i ( router_15_19_to_magia_tile_ni_15_19_req ), - .floo_rsp_o ( magia_tile_ni_15_19_to_router_15_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][20] ), - .id_i ( '{x: 16, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_20_to_router_15_20_req ), - .floo_rsp_i ( router_15_20_to_magia_tile_ni_15_20_rsp ), - .floo_req_i ( router_15_20_to_magia_tile_ni_15_20_req ), - .floo_rsp_o ( magia_tile_ni_15_20_to_router_15_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][21] ), - .id_i ( '{x: 16, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_21_to_router_15_21_req ), - .floo_rsp_i ( router_15_21_to_magia_tile_ni_15_21_rsp ), - .floo_req_i ( router_15_21_to_magia_tile_ni_15_21_req ), - .floo_rsp_o ( magia_tile_ni_15_21_to_router_15_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][22] ), - .id_i ( '{x: 16, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_22_to_router_15_22_req ), - .floo_rsp_i ( router_15_22_to_magia_tile_ni_15_22_rsp ), - .floo_req_i ( router_15_22_to_magia_tile_ni_15_22_req ), - .floo_rsp_o ( magia_tile_ni_15_22_to_router_15_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][23] ), - .id_i ( '{x: 16, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_23_to_router_15_23_req ), - .floo_rsp_i ( router_15_23_to_magia_tile_ni_15_23_rsp ), - .floo_req_i ( router_15_23_to_magia_tile_ni_15_23_req ), - .floo_rsp_o ( magia_tile_ni_15_23_to_router_15_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][24] ), - .id_i ( '{x: 16, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_24_to_router_15_24_req ), - .floo_rsp_i ( router_15_24_to_magia_tile_ni_15_24_rsp ), - .floo_req_i ( router_15_24_to_magia_tile_ni_15_24_req ), - .floo_rsp_o ( magia_tile_ni_15_24_to_router_15_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][25] ), - .id_i ( '{x: 16, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_25_to_router_15_25_req ), - .floo_rsp_i ( router_15_25_to_magia_tile_ni_15_25_rsp ), - .floo_req_i ( router_15_25_to_magia_tile_ni_15_25_req ), - .floo_rsp_o ( magia_tile_ni_15_25_to_router_15_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][26] ), - .id_i ( '{x: 16, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_26_to_router_15_26_req ), - .floo_rsp_i ( router_15_26_to_magia_tile_ni_15_26_rsp ), - .floo_req_i ( router_15_26_to_magia_tile_ni_15_26_req ), - .floo_rsp_o ( magia_tile_ni_15_26_to_router_15_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][27] ), - .id_i ( '{x: 16, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_27_to_router_15_27_req ), - .floo_rsp_i ( router_15_27_to_magia_tile_ni_15_27_rsp ), - .floo_req_i ( router_15_27_to_magia_tile_ni_15_27_req ), - .floo_rsp_o ( magia_tile_ni_15_27_to_router_15_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][28] ), - .id_i ( '{x: 16, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_28_to_router_15_28_req ), - .floo_rsp_i ( router_15_28_to_magia_tile_ni_15_28_rsp ), - .floo_req_i ( router_15_28_to_magia_tile_ni_15_28_req ), - .floo_rsp_o ( magia_tile_ni_15_28_to_router_15_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][29] ), - .id_i ( '{x: 16, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_29_to_router_15_29_req ), - .floo_rsp_i ( router_15_29_to_magia_tile_ni_15_29_rsp ), - .floo_req_i ( router_15_29_to_magia_tile_ni_15_29_req ), - .floo_rsp_o ( magia_tile_ni_15_29_to_router_15_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][30] ), - .id_i ( '{x: 16, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_30_to_router_15_30_req ), - .floo_rsp_i ( router_15_30_to_magia_tile_ni_15_30_rsp ), - .floo_req_i ( router_15_30_to_magia_tile_ni_15_30_req ), - .floo_rsp_o ( magia_tile_ni_15_30_to_router_15_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_15_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[15][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[15][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[15][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[15][31] ), - .id_i ( '{x: 16, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_15_31_to_router_15_31_req ), - .floo_rsp_i ( router_15_31_to_magia_tile_ni_15_31_rsp ), - .floo_req_i ( router_15_31_to_magia_tile_ni_15_31_req ), - .floo_rsp_o ( magia_tile_ni_15_31_to_router_15_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][0] ), - .id_i ( '{x: 17, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_0_to_router_16_0_req ), - .floo_rsp_i ( router_16_0_to_magia_tile_ni_16_0_rsp ), - .floo_req_i ( router_16_0_to_magia_tile_ni_16_0_req ), - .floo_rsp_o ( magia_tile_ni_16_0_to_router_16_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][1] ), - .id_i ( '{x: 17, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_1_to_router_16_1_req ), - .floo_rsp_i ( router_16_1_to_magia_tile_ni_16_1_rsp ), - .floo_req_i ( router_16_1_to_magia_tile_ni_16_1_req ), - .floo_rsp_o ( magia_tile_ni_16_1_to_router_16_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][2] ), - .id_i ( '{x: 17, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_2_to_router_16_2_req ), - .floo_rsp_i ( router_16_2_to_magia_tile_ni_16_2_rsp ), - .floo_req_i ( router_16_2_to_magia_tile_ni_16_2_req ), - .floo_rsp_o ( magia_tile_ni_16_2_to_router_16_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][3] ), - .id_i ( '{x: 17, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_3_to_router_16_3_req ), - .floo_rsp_i ( router_16_3_to_magia_tile_ni_16_3_rsp ), - .floo_req_i ( router_16_3_to_magia_tile_ni_16_3_req ), - .floo_rsp_o ( magia_tile_ni_16_3_to_router_16_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][4] ), - .id_i ( '{x: 17, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_4_to_router_16_4_req ), - .floo_rsp_i ( router_16_4_to_magia_tile_ni_16_4_rsp ), - .floo_req_i ( router_16_4_to_magia_tile_ni_16_4_req ), - .floo_rsp_o ( magia_tile_ni_16_4_to_router_16_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][5] ), - .id_i ( '{x: 17, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_5_to_router_16_5_req ), - .floo_rsp_i ( router_16_5_to_magia_tile_ni_16_5_rsp ), - .floo_req_i ( router_16_5_to_magia_tile_ni_16_5_req ), - .floo_rsp_o ( magia_tile_ni_16_5_to_router_16_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][6] ), - .id_i ( '{x: 17, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_6_to_router_16_6_req ), - .floo_rsp_i ( router_16_6_to_magia_tile_ni_16_6_rsp ), - .floo_req_i ( router_16_6_to_magia_tile_ni_16_6_req ), - .floo_rsp_o ( magia_tile_ni_16_6_to_router_16_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][7] ), - .id_i ( '{x: 17, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_7_to_router_16_7_req ), - .floo_rsp_i ( router_16_7_to_magia_tile_ni_16_7_rsp ), - .floo_req_i ( router_16_7_to_magia_tile_ni_16_7_req ), - .floo_rsp_o ( magia_tile_ni_16_7_to_router_16_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][8] ), - .id_i ( '{x: 17, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_8_to_router_16_8_req ), - .floo_rsp_i ( router_16_8_to_magia_tile_ni_16_8_rsp ), - .floo_req_i ( router_16_8_to_magia_tile_ni_16_8_req ), - .floo_rsp_o ( magia_tile_ni_16_8_to_router_16_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][9] ), - .id_i ( '{x: 17, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_9_to_router_16_9_req ), - .floo_rsp_i ( router_16_9_to_magia_tile_ni_16_9_rsp ), - .floo_req_i ( router_16_9_to_magia_tile_ni_16_9_req ), - .floo_rsp_o ( magia_tile_ni_16_9_to_router_16_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][10] ), - .id_i ( '{x: 17, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_10_to_router_16_10_req ), - .floo_rsp_i ( router_16_10_to_magia_tile_ni_16_10_rsp ), - .floo_req_i ( router_16_10_to_magia_tile_ni_16_10_req ), - .floo_rsp_o ( magia_tile_ni_16_10_to_router_16_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][11] ), - .id_i ( '{x: 17, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_11_to_router_16_11_req ), - .floo_rsp_i ( router_16_11_to_magia_tile_ni_16_11_rsp ), - .floo_req_i ( router_16_11_to_magia_tile_ni_16_11_req ), - .floo_rsp_o ( magia_tile_ni_16_11_to_router_16_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][12] ), - .id_i ( '{x: 17, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_12_to_router_16_12_req ), - .floo_rsp_i ( router_16_12_to_magia_tile_ni_16_12_rsp ), - .floo_req_i ( router_16_12_to_magia_tile_ni_16_12_req ), - .floo_rsp_o ( magia_tile_ni_16_12_to_router_16_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][13] ), - .id_i ( '{x: 17, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_13_to_router_16_13_req ), - .floo_rsp_i ( router_16_13_to_magia_tile_ni_16_13_rsp ), - .floo_req_i ( router_16_13_to_magia_tile_ni_16_13_req ), - .floo_rsp_o ( magia_tile_ni_16_13_to_router_16_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][14] ), - .id_i ( '{x: 17, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_14_to_router_16_14_req ), - .floo_rsp_i ( router_16_14_to_magia_tile_ni_16_14_rsp ), - .floo_req_i ( router_16_14_to_magia_tile_ni_16_14_req ), - .floo_rsp_o ( magia_tile_ni_16_14_to_router_16_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][15] ), - .id_i ( '{x: 17, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_15_to_router_16_15_req ), - .floo_rsp_i ( router_16_15_to_magia_tile_ni_16_15_rsp ), - .floo_req_i ( router_16_15_to_magia_tile_ni_16_15_req ), - .floo_rsp_o ( magia_tile_ni_16_15_to_router_16_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][16] ), - .id_i ( '{x: 17, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_16_to_router_16_16_req ), - .floo_rsp_i ( router_16_16_to_magia_tile_ni_16_16_rsp ), - .floo_req_i ( router_16_16_to_magia_tile_ni_16_16_req ), - .floo_rsp_o ( magia_tile_ni_16_16_to_router_16_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][17] ), - .id_i ( '{x: 17, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_17_to_router_16_17_req ), - .floo_rsp_i ( router_16_17_to_magia_tile_ni_16_17_rsp ), - .floo_req_i ( router_16_17_to_magia_tile_ni_16_17_req ), - .floo_rsp_o ( magia_tile_ni_16_17_to_router_16_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][18] ), - .id_i ( '{x: 17, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_18_to_router_16_18_req ), - .floo_rsp_i ( router_16_18_to_magia_tile_ni_16_18_rsp ), - .floo_req_i ( router_16_18_to_magia_tile_ni_16_18_req ), - .floo_rsp_o ( magia_tile_ni_16_18_to_router_16_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][19] ), - .id_i ( '{x: 17, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_19_to_router_16_19_req ), - .floo_rsp_i ( router_16_19_to_magia_tile_ni_16_19_rsp ), - .floo_req_i ( router_16_19_to_magia_tile_ni_16_19_req ), - .floo_rsp_o ( magia_tile_ni_16_19_to_router_16_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][20] ), - .id_i ( '{x: 17, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_20_to_router_16_20_req ), - .floo_rsp_i ( router_16_20_to_magia_tile_ni_16_20_rsp ), - .floo_req_i ( router_16_20_to_magia_tile_ni_16_20_req ), - .floo_rsp_o ( magia_tile_ni_16_20_to_router_16_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][21] ), - .id_i ( '{x: 17, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_21_to_router_16_21_req ), - .floo_rsp_i ( router_16_21_to_magia_tile_ni_16_21_rsp ), - .floo_req_i ( router_16_21_to_magia_tile_ni_16_21_req ), - .floo_rsp_o ( magia_tile_ni_16_21_to_router_16_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][22] ), - .id_i ( '{x: 17, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_22_to_router_16_22_req ), - .floo_rsp_i ( router_16_22_to_magia_tile_ni_16_22_rsp ), - .floo_req_i ( router_16_22_to_magia_tile_ni_16_22_req ), - .floo_rsp_o ( magia_tile_ni_16_22_to_router_16_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][23] ), - .id_i ( '{x: 17, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_23_to_router_16_23_req ), - .floo_rsp_i ( router_16_23_to_magia_tile_ni_16_23_rsp ), - .floo_req_i ( router_16_23_to_magia_tile_ni_16_23_req ), - .floo_rsp_o ( magia_tile_ni_16_23_to_router_16_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][24] ), - .id_i ( '{x: 17, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_24_to_router_16_24_req ), - .floo_rsp_i ( router_16_24_to_magia_tile_ni_16_24_rsp ), - .floo_req_i ( router_16_24_to_magia_tile_ni_16_24_req ), - .floo_rsp_o ( magia_tile_ni_16_24_to_router_16_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][25] ), - .id_i ( '{x: 17, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_25_to_router_16_25_req ), - .floo_rsp_i ( router_16_25_to_magia_tile_ni_16_25_rsp ), - .floo_req_i ( router_16_25_to_magia_tile_ni_16_25_req ), - .floo_rsp_o ( magia_tile_ni_16_25_to_router_16_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][26] ), - .id_i ( '{x: 17, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_26_to_router_16_26_req ), - .floo_rsp_i ( router_16_26_to_magia_tile_ni_16_26_rsp ), - .floo_req_i ( router_16_26_to_magia_tile_ni_16_26_req ), - .floo_rsp_o ( magia_tile_ni_16_26_to_router_16_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][27] ), - .id_i ( '{x: 17, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_27_to_router_16_27_req ), - .floo_rsp_i ( router_16_27_to_magia_tile_ni_16_27_rsp ), - .floo_req_i ( router_16_27_to_magia_tile_ni_16_27_req ), - .floo_rsp_o ( magia_tile_ni_16_27_to_router_16_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][28] ), - .id_i ( '{x: 17, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_28_to_router_16_28_req ), - .floo_rsp_i ( router_16_28_to_magia_tile_ni_16_28_rsp ), - .floo_req_i ( router_16_28_to_magia_tile_ni_16_28_req ), - .floo_rsp_o ( magia_tile_ni_16_28_to_router_16_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][29] ), - .id_i ( '{x: 17, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_29_to_router_16_29_req ), - .floo_rsp_i ( router_16_29_to_magia_tile_ni_16_29_rsp ), - .floo_req_i ( router_16_29_to_magia_tile_ni_16_29_req ), - .floo_rsp_o ( magia_tile_ni_16_29_to_router_16_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][30] ), - .id_i ( '{x: 17, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_30_to_router_16_30_req ), - .floo_rsp_i ( router_16_30_to_magia_tile_ni_16_30_rsp ), - .floo_req_i ( router_16_30_to_magia_tile_ni_16_30_req ), - .floo_rsp_o ( magia_tile_ni_16_30_to_router_16_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_16_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[16][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[16][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[16][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[16][31] ), - .id_i ( '{x: 17, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_16_31_to_router_16_31_req ), - .floo_rsp_i ( router_16_31_to_magia_tile_ni_16_31_rsp ), - .floo_req_i ( router_16_31_to_magia_tile_ni_16_31_req ), - .floo_rsp_o ( magia_tile_ni_16_31_to_router_16_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][0] ), - .id_i ( '{x: 18, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_0_to_router_17_0_req ), - .floo_rsp_i ( router_17_0_to_magia_tile_ni_17_0_rsp ), - .floo_req_i ( router_17_0_to_magia_tile_ni_17_0_req ), - .floo_rsp_o ( magia_tile_ni_17_0_to_router_17_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][1] ), - .id_i ( '{x: 18, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_1_to_router_17_1_req ), - .floo_rsp_i ( router_17_1_to_magia_tile_ni_17_1_rsp ), - .floo_req_i ( router_17_1_to_magia_tile_ni_17_1_req ), - .floo_rsp_o ( magia_tile_ni_17_1_to_router_17_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][2] ), - .id_i ( '{x: 18, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_2_to_router_17_2_req ), - .floo_rsp_i ( router_17_2_to_magia_tile_ni_17_2_rsp ), - .floo_req_i ( router_17_2_to_magia_tile_ni_17_2_req ), - .floo_rsp_o ( magia_tile_ni_17_2_to_router_17_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][3] ), - .id_i ( '{x: 18, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_3_to_router_17_3_req ), - .floo_rsp_i ( router_17_3_to_magia_tile_ni_17_3_rsp ), - .floo_req_i ( router_17_3_to_magia_tile_ni_17_3_req ), - .floo_rsp_o ( magia_tile_ni_17_3_to_router_17_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][4] ), - .id_i ( '{x: 18, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_4_to_router_17_4_req ), - .floo_rsp_i ( router_17_4_to_magia_tile_ni_17_4_rsp ), - .floo_req_i ( router_17_4_to_magia_tile_ni_17_4_req ), - .floo_rsp_o ( magia_tile_ni_17_4_to_router_17_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][5] ), - .id_i ( '{x: 18, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_5_to_router_17_5_req ), - .floo_rsp_i ( router_17_5_to_magia_tile_ni_17_5_rsp ), - .floo_req_i ( router_17_5_to_magia_tile_ni_17_5_req ), - .floo_rsp_o ( magia_tile_ni_17_5_to_router_17_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][6] ), - .id_i ( '{x: 18, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_6_to_router_17_6_req ), - .floo_rsp_i ( router_17_6_to_magia_tile_ni_17_6_rsp ), - .floo_req_i ( router_17_6_to_magia_tile_ni_17_6_req ), - .floo_rsp_o ( magia_tile_ni_17_6_to_router_17_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][7] ), - .id_i ( '{x: 18, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_7_to_router_17_7_req ), - .floo_rsp_i ( router_17_7_to_magia_tile_ni_17_7_rsp ), - .floo_req_i ( router_17_7_to_magia_tile_ni_17_7_req ), - .floo_rsp_o ( magia_tile_ni_17_7_to_router_17_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][8] ), - .id_i ( '{x: 18, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_8_to_router_17_8_req ), - .floo_rsp_i ( router_17_8_to_magia_tile_ni_17_8_rsp ), - .floo_req_i ( router_17_8_to_magia_tile_ni_17_8_req ), - .floo_rsp_o ( magia_tile_ni_17_8_to_router_17_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][9] ), - .id_i ( '{x: 18, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_9_to_router_17_9_req ), - .floo_rsp_i ( router_17_9_to_magia_tile_ni_17_9_rsp ), - .floo_req_i ( router_17_9_to_magia_tile_ni_17_9_req ), - .floo_rsp_o ( magia_tile_ni_17_9_to_router_17_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][10] ), - .id_i ( '{x: 18, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_10_to_router_17_10_req ), - .floo_rsp_i ( router_17_10_to_magia_tile_ni_17_10_rsp ), - .floo_req_i ( router_17_10_to_magia_tile_ni_17_10_req ), - .floo_rsp_o ( magia_tile_ni_17_10_to_router_17_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][11] ), - .id_i ( '{x: 18, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_11_to_router_17_11_req ), - .floo_rsp_i ( router_17_11_to_magia_tile_ni_17_11_rsp ), - .floo_req_i ( router_17_11_to_magia_tile_ni_17_11_req ), - .floo_rsp_o ( magia_tile_ni_17_11_to_router_17_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][12] ), - .id_i ( '{x: 18, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_12_to_router_17_12_req ), - .floo_rsp_i ( router_17_12_to_magia_tile_ni_17_12_rsp ), - .floo_req_i ( router_17_12_to_magia_tile_ni_17_12_req ), - .floo_rsp_o ( magia_tile_ni_17_12_to_router_17_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][13] ), - .id_i ( '{x: 18, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_13_to_router_17_13_req ), - .floo_rsp_i ( router_17_13_to_magia_tile_ni_17_13_rsp ), - .floo_req_i ( router_17_13_to_magia_tile_ni_17_13_req ), - .floo_rsp_o ( magia_tile_ni_17_13_to_router_17_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][14] ), - .id_i ( '{x: 18, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_14_to_router_17_14_req ), - .floo_rsp_i ( router_17_14_to_magia_tile_ni_17_14_rsp ), - .floo_req_i ( router_17_14_to_magia_tile_ni_17_14_req ), - .floo_rsp_o ( magia_tile_ni_17_14_to_router_17_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][15] ), - .id_i ( '{x: 18, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_15_to_router_17_15_req ), - .floo_rsp_i ( router_17_15_to_magia_tile_ni_17_15_rsp ), - .floo_req_i ( router_17_15_to_magia_tile_ni_17_15_req ), - .floo_rsp_o ( magia_tile_ni_17_15_to_router_17_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][16] ), - .id_i ( '{x: 18, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_16_to_router_17_16_req ), - .floo_rsp_i ( router_17_16_to_magia_tile_ni_17_16_rsp ), - .floo_req_i ( router_17_16_to_magia_tile_ni_17_16_req ), - .floo_rsp_o ( magia_tile_ni_17_16_to_router_17_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][17] ), - .id_i ( '{x: 18, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_17_to_router_17_17_req ), - .floo_rsp_i ( router_17_17_to_magia_tile_ni_17_17_rsp ), - .floo_req_i ( router_17_17_to_magia_tile_ni_17_17_req ), - .floo_rsp_o ( magia_tile_ni_17_17_to_router_17_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][18] ), - .id_i ( '{x: 18, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_18_to_router_17_18_req ), - .floo_rsp_i ( router_17_18_to_magia_tile_ni_17_18_rsp ), - .floo_req_i ( router_17_18_to_magia_tile_ni_17_18_req ), - .floo_rsp_o ( magia_tile_ni_17_18_to_router_17_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][19] ), - .id_i ( '{x: 18, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_19_to_router_17_19_req ), - .floo_rsp_i ( router_17_19_to_magia_tile_ni_17_19_rsp ), - .floo_req_i ( router_17_19_to_magia_tile_ni_17_19_req ), - .floo_rsp_o ( magia_tile_ni_17_19_to_router_17_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][20] ), - .id_i ( '{x: 18, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_20_to_router_17_20_req ), - .floo_rsp_i ( router_17_20_to_magia_tile_ni_17_20_rsp ), - .floo_req_i ( router_17_20_to_magia_tile_ni_17_20_req ), - .floo_rsp_o ( magia_tile_ni_17_20_to_router_17_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][21] ), - .id_i ( '{x: 18, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_21_to_router_17_21_req ), - .floo_rsp_i ( router_17_21_to_magia_tile_ni_17_21_rsp ), - .floo_req_i ( router_17_21_to_magia_tile_ni_17_21_req ), - .floo_rsp_o ( magia_tile_ni_17_21_to_router_17_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][22] ), - .id_i ( '{x: 18, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_22_to_router_17_22_req ), - .floo_rsp_i ( router_17_22_to_magia_tile_ni_17_22_rsp ), - .floo_req_i ( router_17_22_to_magia_tile_ni_17_22_req ), - .floo_rsp_o ( magia_tile_ni_17_22_to_router_17_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][23] ), - .id_i ( '{x: 18, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_23_to_router_17_23_req ), - .floo_rsp_i ( router_17_23_to_magia_tile_ni_17_23_rsp ), - .floo_req_i ( router_17_23_to_magia_tile_ni_17_23_req ), - .floo_rsp_o ( magia_tile_ni_17_23_to_router_17_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][24] ), - .id_i ( '{x: 18, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_24_to_router_17_24_req ), - .floo_rsp_i ( router_17_24_to_magia_tile_ni_17_24_rsp ), - .floo_req_i ( router_17_24_to_magia_tile_ni_17_24_req ), - .floo_rsp_o ( magia_tile_ni_17_24_to_router_17_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][25] ), - .id_i ( '{x: 18, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_25_to_router_17_25_req ), - .floo_rsp_i ( router_17_25_to_magia_tile_ni_17_25_rsp ), - .floo_req_i ( router_17_25_to_magia_tile_ni_17_25_req ), - .floo_rsp_o ( magia_tile_ni_17_25_to_router_17_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][26] ), - .id_i ( '{x: 18, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_26_to_router_17_26_req ), - .floo_rsp_i ( router_17_26_to_magia_tile_ni_17_26_rsp ), - .floo_req_i ( router_17_26_to_magia_tile_ni_17_26_req ), - .floo_rsp_o ( magia_tile_ni_17_26_to_router_17_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][27] ), - .id_i ( '{x: 18, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_27_to_router_17_27_req ), - .floo_rsp_i ( router_17_27_to_magia_tile_ni_17_27_rsp ), - .floo_req_i ( router_17_27_to_magia_tile_ni_17_27_req ), - .floo_rsp_o ( magia_tile_ni_17_27_to_router_17_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][28] ), - .id_i ( '{x: 18, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_28_to_router_17_28_req ), - .floo_rsp_i ( router_17_28_to_magia_tile_ni_17_28_rsp ), - .floo_req_i ( router_17_28_to_magia_tile_ni_17_28_req ), - .floo_rsp_o ( magia_tile_ni_17_28_to_router_17_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][29] ), - .id_i ( '{x: 18, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_29_to_router_17_29_req ), - .floo_rsp_i ( router_17_29_to_magia_tile_ni_17_29_rsp ), - .floo_req_i ( router_17_29_to_magia_tile_ni_17_29_req ), - .floo_rsp_o ( magia_tile_ni_17_29_to_router_17_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][30] ), - .id_i ( '{x: 18, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_30_to_router_17_30_req ), - .floo_rsp_i ( router_17_30_to_magia_tile_ni_17_30_rsp ), - .floo_req_i ( router_17_30_to_magia_tile_ni_17_30_req ), - .floo_rsp_o ( magia_tile_ni_17_30_to_router_17_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_17_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[17][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[17][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[17][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[17][31] ), - .id_i ( '{x: 18, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_17_31_to_router_17_31_req ), - .floo_rsp_i ( router_17_31_to_magia_tile_ni_17_31_rsp ), - .floo_req_i ( router_17_31_to_magia_tile_ni_17_31_req ), - .floo_rsp_o ( magia_tile_ni_17_31_to_router_17_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][0] ), - .id_i ( '{x: 19, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_0_to_router_18_0_req ), - .floo_rsp_i ( router_18_0_to_magia_tile_ni_18_0_rsp ), - .floo_req_i ( router_18_0_to_magia_tile_ni_18_0_req ), - .floo_rsp_o ( magia_tile_ni_18_0_to_router_18_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][1] ), - .id_i ( '{x: 19, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_1_to_router_18_1_req ), - .floo_rsp_i ( router_18_1_to_magia_tile_ni_18_1_rsp ), - .floo_req_i ( router_18_1_to_magia_tile_ni_18_1_req ), - .floo_rsp_o ( magia_tile_ni_18_1_to_router_18_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][2] ), - .id_i ( '{x: 19, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_2_to_router_18_2_req ), - .floo_rsp_i ( router_18_2_to_magia_tile_ni_18_2_rsp ), - .floo_req_i ( router_18_2_to_magia_tile_ni_18_2_req ), - .floo_rsp_o ( magia_tile_ni_18_2_to_router_18_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][3] ), - .id_i ( '{x: 19, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_3_to_router_18_3_req ), - .floo_rsp_i ( router_18_3_to_magia_tile_ni_18_3_rsp ), - .floo_req_i ( router_18_3_to_magia_tile_ni_18_3_req ), - .floo_rsp_o ( magia_tile_ni_18_3_to_router_18_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][4] ), - .id_i ( '{x: 19, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_4_to_router_18_4_req ), - .floo_rsp_i ( router_18_4_to_magia_tile_ni_18_4_rsp ), - .floo_req_i ( router_18_4_to_magia_tile_ni_18_4_req ), - .floo_rsp_o ( magia_tile_ni_18_4_to_router_18_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][5] ), - .id_i ( '{x: 19, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_5_to_router_18_5_req ), - .floo_rsp_i ( router_18_5_to_magia_tile_ni_18_5_rsp ), - .floo_req_i ( router_18_5_to_magia_tile_ni_18_5_req ), - .floo_rsp_o ( magia_tile_ni_18_5_to_router_18_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][6] ), - .id_i ( '{x: 19, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_6_to_router_18_6_req ), - .floo_rsp_i ( router_18_6_to_magia_tile_ni_18_6_rsp ), - .floo_req_i ( router_18_6_to_magia_tile_ni_18_6_req ), - .floo_rsp_o ( magia_tile_ni_18_6_to_router_18_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][7] ), - .id_i ( '{x: 19, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_7_to_router_18_7_req ), - .floo_rsp_i ( router_18_7_to_magia_tile_ni_18_7_rsp ), - .floo_req_i ( router_18_7_to_magia_tile_ni_18_7_req ), - .floo_rsp_o ( magia_tile_ni_18_7_to_router_18_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][8] ), - .id_i ( '{x: 19, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_8_to_router_18_8_req ), - .floo_rsp_i ( router_18_8_to_magia_tile_ni_18_8_rsp ), - .floo_req_i ( router_18_8_to_magia_tile_ni_18_8_req ), - .floo_rsp_o ( magia_tile_ni_18_8_to_router_18_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][9] ), - .id_i ( '{x: 19, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_9_to_router_18_9_req ), - .floo_rsp_i ( router_18_9_to_magia_tile_ni_18_9_rsp ), - .floo_req_i ( router_18_9_to_magia_tile_ni_18_9_req ), - .floo_rsp_o ( magia_tile_ni_18_9_to_router_18_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][10] ), - .id_i ( '{x: 19, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_10_to_router_18_10_req ), - .floo_rsp_i ( router_18_10_to_magia_tile_ni_18_10_rsp ), - .floo_req_i ( router_18_10_to_magia_tile_ni_18_10_req ), - .floo_rsp_o ( magia_tile_ni_18_10_to_router_18_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][11] ), - .id_i ( '{x: 19, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_11_to_router_18_11_req ), - .floo_rsp_i ( router_18_11_to_magia_tile_ni_18_11_rsp ), - .floo_req_i ( router_18_11_to_magia_tile_ni_18_11_req ), - .floo_rsp_o ( magia_tile_ni_18_11_to_router_18_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][12] ), - .id_i ( '{x: 19, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_12_to_router_18_12_req ), - .floo_rsp_i ( router_18_12_to_magia_tile_ni_18_12_rsp ), - .floo_req_i ( router_18_12_to_magia_tile_ni_18_12_req ), - .floo_rsp_o ( magia_tile_ni_18_12_to_router_18_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][13] ), - .id_i ( '{x: 19, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_13_to_router_18_13_req ), - .floo_rsp_i ( router_18_13_to_magia_tile_ni_18_13_rsp ), - .floo_req_i ( router_18_13_to_magia_tile_ni_18_13_req ), - .floo_rsp_o ( magia_tile_ni_18_13_to_router_18_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][14] ), - .id_i ( '{x: 19, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_14_to_router_18_14_req ), - .floo_rsp_i ( router_18_14_to_magia_tile_ni_18_14_rsp ), - .floo_req_i ( router_18_14_to_magia_tile_ni_18_14_req ), - .floo_rsp_o ( magia_tile_ni_18_14_to_router_18_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][15] ), - .id_i ( '{x: 19, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_15_to_router_18_15_req ), - .floo_rsp_i ( router_18_15_to_magia_tile_ni_18_15_rsp ), - .floo_req_i ( router_18_15_to_magia_tile_ni_18_15_req ), - .floo_rsp_o ( magia_tile_ni_18_15_to_router_18_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][16] ), - .id_i ( '{x: 19, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_16_to_router_18_16_req ), - .floo_rsp_i ( router_18_16_to_magia_tile_ni_18_16_rsp ), - .floo_req_i ( router_18_16_to_magia_tile_ni_18_16_req ), - .floo_rsp_o ( magia_tile_ni_18_16_to_router_18_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][17] ), - .id_i ( '{x: 19, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_17_to_router_18_17_req ), - .floo_rsp_i ( router_18_17_to_magia_tile_ni_18_17_rsp ), - .floo_req_i ( router_18_17_to_magia_tile_ni_18_17_req ), - .floo_rsp_o ( magia_tile_ni_18_17_to_router_18_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][18] ), - .id_i ( '{x: 19, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_18_to_router_18_18_req ), - .floo_rsp_i ( router_18_18_to_magia_tile_ni_18_18_rsp ), - .floo_req_i ( router_18_18_to_magia_tile_ni_18_18_req ), - .floo_rsp_o ( magia_tile_ni_18_18_to_router_18_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][19] ), - .id_i ( '{x: 19, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_19_to_router_18_19_req ), - .floo_rsp_i ( router_18_19_to_magia_tile_ni_18_19_rsp ), - .floo_req_i ( router_18_19_to_magia_tile_ni_18_19_req ), - .floo_rsp_o ( magia_tile_ni_18_19_to_router_18_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][20] ), - .id_i ( '{x: 19, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_20_to_router_18_20_req ), - .floo_rsp_i ( router_18_20_to_magia_tile_ni_18_20_rsp ), - .floo_req_i ( router_18_20_to_magia_tile_ni_18_20_req ), - .floo_rsp_o ( magia_tile_ni_18_20_to_router_18_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][21] ), - .id_i ( '{x: 19, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_21_to_router_18_21_req ), - .floo_rsp_i ( router_18_21_to_magia_tile_ni_18_21_rsp ), - .floo_req_i ( router_18_21_to_magia_tile_ni_18_21_req ), - .floo_rsp_o ( magia_tile_ni_18_21_to_router_18_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][22] ), - .id_i ( '{x: 19, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_22_to_router_18_22_req ), - .floo_rsp_i ( router_18_22_to_magia_tile_ni_18_22_rsp ), - .floo_req_i ( router_18_22_to_magia_tile_ni_18_22_req ), - .floo_rsp_o ( magia_tile_ni_18_22_to_router_18_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][23] ), - .id_i ( '{x: 19, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_23_to_router_18_23_req ), - .floo_rsp_i ( router_18_23_to_magia_tile_ni_18_23_rsp ), - .floo_req_i ( router_18_23_to_magia_tile_ni_18_23_req ), - .floo_rsp_o ( magia_tile_ni_18_23_to_router_18_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][24] ), - .id_i ( '{x: 19, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_24_to_router_18_24_req ), - .floo_rsp_i ( router_18_24_to_magia_tile_ni_18_24_rsp ), - .floo_req_i ( router_18_24_to_magia_tile_ni_18_24_req ), - .floo_rsp_o ( magia_tile_ni_18_24_to_router_18_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][25] ), - .id_i ( '{x: 19, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_25_to_router_18_25_req ), - .floo_rsp_i ( router_18_25_to_magia_tile_ni_18_25_rsp ), - .floo_req_i ( router_18_25_to_magia_tile_ni_18_25_req ), - .floo_rsp_o ( magia_tile_ni_18_25_to_router_18_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][26] ), - .id_i ( '{x: 19, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_26_to_router_18_26_req ), - .floo_rsp_i ( router_18_26_to_magia_tile_ni_18_26_rsp ), - .floo_req_i ( router_18_26_to_magia_tile_ni_18_26_req ), - .floo_rsp_o ( magia_tile_ni_18_26_to_router_18_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][27] ), - .id_i ( '{x: 19, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_27_to_router_18_27_req ), - .floo_rsp_i ( router_18_27_to_magia_tile_ni_18_27_rsp ), - .floo_req_i ( router_18_27_to_magia_tile_ni_18_27_req ), - .floo_rsp_o ( magia_tile_ni_18_27_to_router_18_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][28] ), - .id_i ( '{x: 19, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_28_to_router_18_28_req ), - .floo_rsp_i ( router_18_28_to_magia_tile_ni_18_28_rsp ), - .floo_req_i ( router_18_28_to_magia_tile_ni_18_28_req ), - .floo_rsp_o ( magia_tile_ni_18_28_to_router_18_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][29] ), - .id_i ( '{x: 19, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_29_to_router_18_29_req ), - .floo_rsp_i ( router_18_29_to_magia_tile_ni_18_29_rsp ), - .floo_req_i ( router_18_29_to_magia_tile_ni_18_29_req ), - .floo_rsp_o ( magia_tile_ni_18_29_to_router_18_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][30] ), - .id_i ( '{x: 19, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_30_to_router_18_30_req ), - .floo_rsp_i ( router_18_30_to_magia_tile_ni_18_30_rsp ), - .floo_req_i ( router_18_30_to_magia_tile_ni_18_30_req ), - .floo_rsp_o ( magia_tile_ni_18_30_to_router_18_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_18_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[18][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[18][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[18][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[18][31] ), - .id_i ( '{x: 19, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_18_31_to_router_18_31_req ), - .floo_rsp_i ( router_18_31_to_magia_tile_ni_18_31_rsp ), - .floo_req_i ( router_18_31_to_magia_tile_ni_18_31_req ), - .floo_rsp_o ( magia_tile_ni_18_31_to_router_18_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][0] ), - .id_i ( '{x: 20, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_0_to_router_19_0_req ), - .floo_rsp_i ( router_19_0_to_magia_tile_ni_19_0_rsp ), - .floo_req_i ( router_19_0_to_magia_tile_ni_19_0_req ), - .floo_rsp_o ( magia_tile_ni_19_0_to_router_19_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][1] ), - .id_i ( '{x: 20, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_1_to_router_19_1_req ), - .floo_rsp_i ( router_19_1_to_magia_tile_ni_19_1_rsp ), - .floo_req_i ( router_19_1_to_magia_tile_ni_19_1_req ), - .floo_rsp_o ( magia_tile_ni_19_1_to_router_19_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][2] ), - .id_i ( '{x: 20, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_2_to_router_19_2_req ), - .floo_rsp_i ( router_19_2_to_magia_tile_ni_19_2_rsp ), - .floo_req_i ( router_19_2_to_magia_tile_ni_19_2_req ), - .floo_rsp_o ( magia_tile_ni_19_2_to_router_19_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][3] ), - .id_i ( '{x: 20, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_3_to_router_19_3_req ), - .floo_rsp_i ( router_19_3_to_magia_tile_ni_19_3_rsp ), - .floo_req_i ( router_19_3_to_magia_tile_ni_19_3_req ), - .floo_rsp_o ( magia_tile_ni_19_3_to_router_19_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][4] ), - .id_i ( '{x: 20, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_4_to_router_19_4_req ), - .floo_rsp_i ( router_19_4_to_magia_tile_ni_19_4_rsp ), - .floo_req_i ( router_19_4_to_magia_tile_ni_19_4_req ), - .floo_rsp_o ( magia_tile_ni_19_4_to_router_19_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][5] ), - .id_i ( '{x: 20, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_5_to_router_19_5_req ), - .floo_rsp_i ( router_19_5_to_magia_tile_ni_19_5_rsp ), - .floo_req_i ( router_19_5_to_magia_tile_ni_19_5_req ), - .floo_rsp_o ( magia_tile_ni_19_5_to_router_19_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][6] ), - .id_i ( '{x: 20, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_6_to_router_19_6_req ), - .floo_rsp_i ( router_19_6_to_magia_tile_ni_19_6_rsp ), - .floo_req_i ( router_19_6_to_magia_tile_ni_19_6_req ), - .floo_rsp_o ( magia_tile_ni_19_6_to_router_19_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][7] ), - .id_i ( '{x: 20, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_7_to_router_19_7_req ), - .floo_rsp_i ( router_19_7_to_magia_tile_ni_19_7_rsp ), - .floo_req_i ( router_19_7_to_magia_tile_ni_19_7_req ), - .floo_rsp_o ( magia_tile_ni_19_7_to_router_19_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][8] ), - .id_i ( '{x: 20, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_8_to_router_19_8_req ), - .floo_rsp_i ( router_19_8_to_magia_tile_ni_19_8_rsp ), - .floo_req_i ( router_19_8_to_magia_tile_ni_19_8_req ), - .floo_rsp_o ( magia_tile_ni_19_8_to_router_19_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][9] ), - .id_i ( '{x: 20, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_9_to_router_19_9_req ), - .floo_rsp_i ( router_19_9_to_magia_tile_ni_19_9_rsp ), - .floo_req_i ( router_19_9_to_magia_tile_ni_19_9_req ), - .floo_rsp_o ( magia_tile_ni_19_9_to_router_19_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][10] ), - .id_i ( '{x: 20, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_10_to_router_19_10_req ), - .floo_rsp_i ( router_19_10_to_magia_tile_ni_19_10_rsp ), - .floo_req_i ( router_19_10_to_magia_tile_ni_19_10_req ), - .floo_rsp_o ( magia_tile_ni_19_10_to_router_19_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][11] ), - .id_i ( '{x: 20, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_11_to_router_19_11_req ), - .floo_rsp_i ( router_19_11_to_magia_tile_ni_19_11_rsp ), - .floo_req_i ( router_19_11_to_magia_tile_ni_19_11_req ), - .floo_rsp_o ( magia_tile_ni_19_11_to_router_19_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][12] ), - .id_i ( '{x: 20, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_12_to_router_19_12_req ), - .floo_rsp_i ( router_19_12_to_magia_tile_ni_19_12_rsp ), - .floo_req_i ( router_19_12_to_magia_tile_ni_19_12_req ), - .floo_rsp_o ( magia_tile_ni_19_12_to_router_19_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][13] ), - .id_i ( '{x: 20, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_13_to_router_19_13_req ), - .floo_rsp_i ( router_19_13_to_magia_tile_ni_19_13_rsp ), - .floo_req_i ( router_19_13_to_magia_tile_ni_19_13_req ), - .floo_rsp_o ( magia_tile_ni_19_13_to_router_19_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][14] ), - .id_i ( '{x: 20, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_14_to_router_19_14_req ), - .floo_rsp_i ( router_19_14_to_magia_tile_ni_19_14_rsp ), - .floo_req_i ( router_19_14_to_magia_tile_ni_19_14_req ), - .floo_rsp_o ( magia_tile_ni_19_14_to_router_19_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][15] ), - .id_i ( '{x: 20, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_15_to_router_19_15_req ), - .floo_rsp_i ( router_19_15_to_magia_tile_ni_19_15_rsp ), - .floo_req_i ( router_19_15_to_magia_tile_ni_19_15_req ), - .floo_rsp_o ( magia_tile_ni_19_15_to_router_19_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][16] ), - .id_i ( '{x: 20, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_16_to_router_19_16_req ), - .floo_rsp_i ( router_19_16_to_magia_tile_ni_19_16_rsp ), - .floo_req_i ( router_19_16_to_magia_tile_ni_19_16_req ), - .floo_rsp_o ( magia_tile_ni_19_16_to_router_19_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][17] ), - .id_i ( '{x: 20, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_17_to_router_19_17_req ), - .floo_rsp_i ( router_19_17_to_magia_tile_ni_19_17_rsp ), - .floo_req_i ( router_19_17_to_magia_tile_ni_19_17_req ), - .floo_rsp_o ( magia_tile_ni_19_17_to_router_19_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][18] ), - .id_i ( '{x: 20, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_18_to_router_19_18_req ), - .floo_rsp_i ( router_19_18_to_magia_tile_ni_19_18_rsp ), - .floo_req_i ( router_19_18_to_magia_tile_ni_19_18_req ), - .floo_rsp_o ( magia_tile_ni_19_18_to_router_19_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][19] ), - .id_i ( '{x: 20, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_19_to_router_19_19_req ), - .floo_rsp_i ( router_19_19_to_magia_tile_ni_19_19_rsp ), - .floo_req_i ( router_19_19_to_magia_tile_ni_19_19_req ), - .floo_rsp_o ( magia_tile_ni_19_19_to_router_19_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][20] ), - .id_i ( '{x: 20, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_20_to_router_19_20_req ), - .floo_rsp_i ( router_19_20_to_magia_tile_ni_19_20_rsp ), - .floo_req_i ( router_19_20_to_magia_tile_ni_19_20_req ), - .floo_rsp_o ( magia_tile_ni_19_20_to_router_19_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][21] ), - .id_i ( '{x: 20, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_21_to_router_19_21_req ), - .floo_rsp_i ( router_19_21_to_magia_tile_ni_19_21_rsp ), - .floo_req_i ( router_19_21_to_magia_tile_ni_19_21_req ), - .floo_rsp_o ( magia_tile_ni_19_21_to_router_19_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][22] ), - .id_i ( '{x: 20, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_22_to_router_19_22_req ), - .floo_rsp_i ( router_19_22_to_magia_tile_ni_19_22_rsp ), - .floo_req_i ( router_19_22_to_magia_tile_ni_19_22_req ), - .floo_rsp_o ( magia_tile_ni_19_22_to_router_19_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][23] ), - .id_i ( '{x: 20, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_23_to_router_19_23_req ), - .floo_rsp_i ( router_19_23_to_magia_tile_ni_19_23_rsp ), - .floo_req_i ( router_19_23_to_magia_tile_ni_19_23_req ), - .floo_rsp_o ( magia_tile_ni_19_23_to_router_19_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][24] ), - .id_i ( '{x: 20, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_24_to_router_19_24_req ), - .floo_rsp_i ( router_19_24_to_magia_tile_ni_19_24_rsp ), - .floo_req_i ( router_19_24_to_magia_tile_ni_19_24_req ), - .floo_rsp_o ( magia_tile_ni_19_24_to_router_19_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][25] ), - .id_i ( '{x: 20, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_25_to_router_19_25_req ), - .floo_rsp_i ( router_19_25_to_magia_tile_ni_19_25_rsp ), - .floo_req_i ( router_19_25_to_magia_tile_ni_19_25_req ), - .floo_rsp_o ( magia_tile_ni_19_25_to_router_19_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][26] ), - .id_i ( '{x: 20, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_26_to_router_19_26_req ), - .floo_rsp_i ( router_19_26_to_magia_tile_ni_19_26_rsp ), - .floo_req_i ( router_19_26_to_magia_tile_ni_19_26_req ), - .floo_rsp_o ( magia_tile_ni_19_26_to_router_19_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][27] ), - .id_i ( '{x: 20, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_27_to_router_19_27_req ), - .floo_rsp_i ( router_19_27_to_magia_tile_ni_19_27_rsp ), - .floo_req_i ( router_19_27_to_magia_tile_ni_19_27_req ), - .floo_rsp_o ( magia_tile_ni_19_27_to_router_19_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][28] ), - .id_i ( '{x: 20, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_28_to_router_19_28_req ), - .floo_rsp_i ( router_19_28_to_magia_tile_ni_19_28_rsp ), - .floo_req_i ( router_19_28_to_magia_tile_ni_19_28_req ), - .floo_rsp_o ( magia_tile_ni_19_28_to_router_19_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][29] ), - .id_i ( '{x: 20, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_29_to_router_19_29_req ), - .floo_rsp_i ( router_19_29_to_magia_tile_ni_19_29_rsp ), - .floo_req_i ( router_19_29_to_magia_tile_ni_19_29_req ), - .floo_rsp_o ( magia_tile_ni_19_29_to_router_19_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][30] ), - .id_i ( '{x: 20, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_30_to_router_19_30_req ), - .floo_rsp_i ( router_19_30_to_magia_tile_ni_19_30_rsp ), - .floo_req_i ( router_19_30_to_magia_tile_ni_19_30_req ), - .floo_rsp_o ( magia_tile_ni_19_30_to_router_19_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_19_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[19][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[19][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[19][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[19][31] ), - .id_i ( '{x: 20, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_19_31_to_router_19_31_req ), - .floo_rsp_i ( router_19_31_to_magia_tile_ni_19_31_rsp ), - .floo_req_i ( router_19_31_to_magia_tile_ni_19_31_req ), - .floo_rsp_o ( magia_tile_ni_19_31_to_router_19_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][0] ), - .id_i ( '{x: 21, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_0_to_router_20_0_req ), - .floo_rsp_i ( router_20_0_to_magia_tile_ni_20_0_rsp ), - .floo_req_i ( router_20_0_to_magia_tile_ni_20_0_req ), - .floo_rsp_o ( magia_tile_ni_20_0_to_router_20_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][1] ), - .id_i ( '{x: 21, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_1_to_router_20_1_req ), - .floo_rsp_i ( router_20_1_to_magia_tile_ni_20_1_rsp ), - .floo_req_i ( router_20_1_to_magia_tile_ni_20_1_req ), - .floo_rsp_o ( magia_tile_ni_20_1_to_router_20_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][2] ), - .id_i ( '{x: 21, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_2_to_router_20_2_req ), - .floo_rsp_i ( router_20_2_to_magia_tile_ni_20_2_rsp ), - .floo_req_i ( router_20_2_to_magia_tile_ni_20_2_req ), - .floo_rsp_o ( magia_tile_ni_20_2_to_router_20_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][3] ), - .id_i ( '{x: 21, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_3_to_router_20_3_req ), - .floo_rsp_i ( router_20_3_to_magia_tile_ni_20_3_rsp ), - .floo_req_i ( router_20_3_to_magia_tile_ni_20_3_req ), - .floo_rsp_o ( magia_tile_ni_20_3_to_router_20_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][4] ), - .id_i ( '{x: 21, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_4_to_router_20_4_req ), - .floo_rsp_i ( router_20_4_to_magia_tile_ni_20_4_rsp ), - .floo_req_i ( router_20_4_to_magia_tile_ni_20_4_req ), - .floo_rsp_o ( magia_tile_ni_20_4_to_router_20_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][5] ), - .id_i ( '{x: 21, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_5_to_router_20_5_req ), - .floo_rsp_i ( router_20_5_to_magia_tile_ni_20_5_rsp ), - .floo_req_i ( router_20_5_to_magia_tile_ni_20_5_req ), - .floo_rsp_o ( magia_tile_ni_20_5_to_router_20_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][6] ), - .id_i ( '{x: 21, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_6_to_router_20_6_req ), - .floo_rsp_i ( router_20_6_to_magia_tile_ni_20_6_rsp ), - .floo_req_i ( router_20_6_to_magia_tile_ni_20_6_req ), - .floo_rsp_o ( magia_tile_ni_20_6_to_router_20_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][7] ), - .id_i ( '{x: 21, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_7_to_router_20_7_req ), - .floo_rsp_i ( router_20_7_to_magia_tile_ni_20_7_rsp ), - .floo_req_i ( router_20_7_to_magia_tile_ni_20_7_req ), - .floo_rsp_o ( magia_tile_ni_20_7_to_router_20_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][8] ), - .id_i ( '{x: 21, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_8_to_router_20_8_req ), - .floo_rsp_i ( router_20_8_to_magia_tile_ni_20_8_rsp ), - .floo_req_i ( router_20_8_to_magia_tile_ni_20_8_req ), - .floo_rsp_o ( magia_tile_ni_20_8_to_router_20_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][9] ), - .id_i ( '{x: 21, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_9_to_router_20_9_req ), - .floo_rsp_i ( router_20_9_to_magia_tile_ni_20_9_rsp ), - .floo_req_i ( router_20_9_to_magia_tile_ni_20_9_req ), - .floo_rsp_o ( magia_tile_ni_20_9_to_router_20_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][10] ), - .id_i ( '{x: 21, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_10_to_router_20_10_req ), - .floo_rsp_i ( router_20_10_to_magia_tile_ni_20_10_rsp ), - .floo_req_i ( router_20_10_to_magia_tile_ni_20_10_req ), - .floo_rsp_o ( magia_tile_ni_20_10_to_router_20_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][11] ), - .id_i ( '{x: 21, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_11_to_router_20_11_req ), - .floo_rsp_i ( router_20_11_to_magia_tile_ni_20_11_rsp ), - .floo_req_i ( router_20_11_to_magia_tile_ni_20_11_req ), - .floo_rsp_o ( magia_tile_ni_20_11_to_router_20_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][12] ), - .id_i ( '{x: 21, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_12_to_router_20_12_req ), - .floo_rsp_i ( router_20_12_to_magia_tile_ni_20_12_rsp ), - .floo_req_i ( router_20_12_to_magia_tile_ni_20_12_req ), - .floo_rsp_o ( magia_tile_ni_20_12_to_router_20_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][13] ), - .id_i ( '{x: 21, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_13_to_router_20_13_req ), - .floo_rsp_i ( router_20_13_to_magia_tile_ni_20_13_rsp ), - .floo_req_i ( router_20_13_to_magia_tile_ni_20_13_req ), - .floo_rsp_o ( magia_tile_ni_20_13_to_router_20_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][14] ), - .id_i ( '{x: 21, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_14_to_router_20_14_req ), - .floo_rsp_i ( router_20_14_to_magia_tile_ni_20_14_rsp ), - .floo_req_i ( router_20_14_to_magia_tile_ni_20_14_req ), - .floo_rsp_o ( magia_tile_ni_20_14_to_router_20_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][15] ), - .id_i ( '{x: 21, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_15_to_router_20_15_req ), - .floo_rsp_i ( router_20_15_to_magia_tile_ni_20_15_rsp ), - .floo_req_i ( router_20_15_to_magia_tile_ni_20_15_req ), - .floo_rsp_o ( magia_tile_ni_20_15_to_router_20_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][16] ), - .id_i ( '{x: 21, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_16_to_router_20_16_req ), - .floo_rsp_i ( router_20_16_to_magia_tile_ni_20_16_rsp ), - .floo_req_i ( router_20_16_to_magia_tile_ni_20_16_req ), - .floo_rsp_o ( magia_tile_ni_20_16_to_router_20_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][17] ), - .id_i ( '{x: 21, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_17_to_router_20_17_req ), - .floo_rsp_i ( router_20_17_to_magia_tile_ni_20_17_rsp ), - .floo_req_i ( router_20_17_to_magia_tile_ni_20_17_req ), - .floo_rsp_o ( magia_tile_ni_20_17_to_router_20_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][18] ), - .id_i ( '{x: 21, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_18_to_router_20_18_req ), - .floo_rsp_i ( router_20_18_to_magia_tile_ni_20_18_rsp ), - .floo_req_i ( router_20_18_to_magia_tile_ni_20_18_req ), - .floo_rsp_o ( magia_tile_ni_20_18_to_router_20_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][19] ), - .id_i ( '{x: 21, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_19_to_router_20_19_req ), - .floo_rsp_i ( router_20_19_to_magia_tile_ni_20_19_rsp ), - .floo_req_i ( router_20_19_to_magia_tile_ni_20_19_req ), - .floo_rsp_o ( magia_tile_ni_20_19_to_router_20_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][20] ), - .id_i ( '{x: 21, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_20_to_router_20_20_req ), - .floo_rsp_i ( router_20_20_to_magia_tile_ni_20_20_rsp ), - .floo_req_i ( router_20_20_to_magia_tile_ni_20_20_req ), - .floo_rsp_o ( magia_tile_ni_20_20_to_router_20_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][21] ), - .id_i ( '{x: 21, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_21_to_router_20_21_req ), - .floo_rsp_i ( router_20_21_to_magia_tile_ni_20_21_rsp ), - .floo_req_i ( router_20_21_to_magia_tile_ni_20_21_req ), - .floo_rsp_o ( magia_tile_ni_20_21_to_router_20_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][22] ), - .id_i ( '{x: 21, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_22_to_router_20_22_req ), - .floo_rsp_i ( router_20_22_to_magia_tile_ni_20_22_rsp ), - .floo_req_i ( router_20_22_to_magia_tile_ni_20_22_req ), - .floo_rsp_o ( magia_tile_ni_20_22_to_router_20_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][23] ), - .id_i ( '{x: 21, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_23_to_router_20_23_req ), - .floo_rsp_i ( router_20_23_to_magia_tile_ni_20_23_rsp ), - .floo_req_i ( router_20_23_to_magia_tile_ni_20_23_req ), - .floo_rsp_o ( magia_tile_ni_20_23_to_router_20_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][24] ), - .id_i ( '{x: 21, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_24_to_router_20_24_req ), - .floo_rsp_i ( router_20_24_to_magia_tile_ni_20_24_rsp ), - .floo_req_i ( router_20_24_to_magia_tile_ni_20_24_req ), - .floo_rsp_o ( magia_tile_ni_20_24_to_router_20_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][25] ), - .id_i ( '{x: 21, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_25_to_router_20_25_req ), - .floo_rsp_i ( router_20_25_to_magia_tile_ni_20_25_rsp ), - .floo_req_i ( router_20_25_to_magia_tile_ni_20_25_req ), - .floo_rsp_o ( magia_tile_ni_20_25_to_router_20_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][26] ), - .id_i ( '{x: 21, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_26_to_router_20_26_req ), - .floo_rsp_i ( router_20_26_to_magia_tile_ni_20_26_rsp ), - .floo_req_i ( router_20_26_to_magia_tile_ni_20_26_req ), - .floo_rsp_o ( magia_tile_ni_20_26_to_router_20_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][27] ), - .id_i ( '{x: 21, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_27_to_router_20_27_req ), - .floo_rsp_i ( router_20_27_to_magia_tile_ni_20_27_rsp ), - .floo_req_i ( router_20_27_to_magia_tile_ni_20_27_req ), - .floo_rsp_o ( magia_tile_ni_20_27_to_router_20_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][28] ), - .id_i ( '{x: 21, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_28_to_router_20_28_req ), - .floo_rsp_i ( router_20_28_to_magia_tile_ni_20_28_rsp ), - .floo_req_i ( router_20_28_to_magia_tile_ni_20_28_req ), - .floo_rsp_o ( magia_tile_ni_20_28_to_router_20_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][29] ), - .id_i ( '{x: 21, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_29_to_router_20_29_req ), - .floo_rsp_i ( router_20_29_to_magia_tile_ni_20_29_rsp ), - .floo_req_i ( router_20_29_to_magia_tile_ni_20_29_req ), - .floo_rsp_o ( magia_tile_ni_20_29_to_router_20_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][30] ), - .id_i ( '{x: 21, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_30_to_router_20_30_req ), - .floo_rsp_i ( router_20_30_to_magia_tile_ni_20_30_rsp ), - .floo_req_i ( router_20_30_to_magia_tile_ni_20_30_req ), - .floo_rsp_o ( magia_tile_ni_20_30_to_router_20_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_20_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[20][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[20][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[20][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[20][31] ), - .id_i ( '{x: 21, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_20_31_to_router_20_31_req ), - .floo_rsp_i ( router_20_31_to_magia_tile_ni_20_31_rsp ), - .floo_req_i ( router_20_31_to_magia_tile_ni_20_31_req ), - .floo_rsp_o ( magia_tile_ni_20_31_to_router_20_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][0] ), - .id_i ( '{x: 22, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_0_to_router_21_0_req ), - .floo_rsp_i ( router_21_0_to_magia_tile_ni_21_0_rsp ), - .floo_req_i ( router_21_0_to_magia_tile_ni_21_0_req ), - .floo_rsp_o ( magia_tile_ni_21_0_to_router_21_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][1] ), - .id_i ( '{x: 22, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_1_to_router_21_1_req ), - .floo_rsp_i ( router_21_1_to_magia_tile_ni_21_1_rsp ), - .floo_req_i ( router_21_1_to_magia_tile_ni_21_1_req ), - .floo_rsp_o ( magia_tile_ni_21_1_to_router_21_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][2] ), - .id_i ( '{x: 22, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_2_to_router_21_2_req ), - .floo_rsp_i ( router_21_2_to_magia_tile_ni_21_2_rsp ), - .floo_req_i ( router_21_2_to_magia_tile_ni_21_2_req ), - .floo_rsp_o ( magia_tile_ni_21_2_to_router_21_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][3] ), - .id_i ( '{x: 22, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_3_to_router_21_3_req ), - .floo_rsp_i ( router_21_3_to_magia_tile_ni_21_3_rsp ), - .floo_req_i ( router_21_3_to_magia_tile_ni_21_3_req ), - .floo_rsp_o ( magia_tile_ni_21_3_to_router_21_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][4] ), - .id_i ( '{x: 22, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_4_to_router_21_4_req ), - .floo_rsp_i ( router_21_4_to_magia_tile_ni_21_4_rsp ), - .floo_req_i ( router_21_4_to_magia_tile_ni_21_4_req ), - .floo_rsp_o ( magia_tile_ni_21_4_to_router_21_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][5] ), - .id_i ( '{x: 22, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_5_to_router_21_5_req ), - .floo_rsp_i ( router_21_5_to_magia_tile_ni_21_5_rsp ), - .floo_req_i ( router_21_5_to_magia_tile_ni_21_5_req ), - .floo_rsp_o ( magia_tile_ni_21_5_to_router_21_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][6] ), - .id_i ( '{x: 22, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_6_to_router_21_6_req ), - .floo_rsp_i ( router_21_6_to_magia_tile_ni_21_6_rsp ), - .floo_req_i ( router_21_6_to_magia_tile_ni_21_6_req ), - .floo_rsp_o ( magia_tile_ni_21_6_to_router_21_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][7] ), - .id_i ( '{x: 22, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_7_to_router_21_7_req ), - .floo_rsp_i ( router_21_7_to_magia_tile_ni_21_7_rsp ), - .floo_req_i ( router_21_7_to_magia_tile_ni_21_7_req ), - .floo_rsp_o ( magia_tile_ni_21_7_to_router_21_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][8] ), - .id_i ( '{x: 22, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_8_to_router_21_8_req ), - .floo_rsp_i ( router_21_8_to_magia_tile_ni_21_8_rsp ), - .floo_req_i ( router_21_8_to_magia_tile_ni_21_8_req ), - .floo_rsp_o ( magia_tile_ni_21_8_to_router_21_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][9] ), - .id_i ( '{x: 22, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_9_to_router_21_9_req ), - .floo_rsp_i ( router_21_9_to_magia_tile_ni_21_9_rsp ), - .floo_req_i ( router_21_9_to_magia_tile_ni_21_9_req ), - .floo_rsp_o ( magia_tile_ni_21_9_to_router_21_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][10] ), - .id_i ( '{x: 22, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_10_to_router_21_10_req ), - .floo_rsp_i ( router_21_10_to_magia_tile_ni_21_10_rsp ), - .floo_req_i ( router_21_10_to_magia_tile_ni_21_10_req ), - .floo_rsp_o ( magia_tile_ni_21_10_to_router_21_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][11] ), - .id_i ( '{x: 22, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_11_to_router_21_11_req ), - .floo_rsp_i ( router_21_11_to_magia_tile_ni_21_11_rsp ), - .floo_req_i ( router_21_11_to_magia_tile_ni_21_11_req ), - .floo_rsp_o ( magia_tile_ni_21_11_to_router_21_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][12] ), - .id_i ( '{x: 22, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_12_to_router_21_12_req ), - .floo_rsp_i ( router_21_12_to_magia_tile_ni_21_12_rsp ), - .floo_req_i ( router_21_12_to_magia_tile_ni_21_12_req ), - .floo_rsp_o ( magia_tile_ni_21_12_to_router_21_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][13] ), - .id_i ( '{x: 22, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_13_to_router_21_13_req ), - .floo_rsp_i ( router_21_13_to_magia_tile_ni_21_13_rsp ), - .floo_req_i ( router_21_13_to_magia_tile_ni_21_13_req ), - .floo_rsp_o ( magia_tile_ni_21_13_to_router_21_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][14] ), - .id_i ( '{x: 22, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_14_to_router_21_14_req ), - .floo_rsp_i ( router_21_14_to_magia_tile_ni_21_14_rsp ), - .floo_req_i ( router_21_14_to_magia_tile_ni_21_14_req ), - .floo_rsp_o ( magia_tile_ni_21_14_to_router_21_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][15] ), - .id_i ( '{x: 22, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_15_to_router_21_15_req ), - .floo_rsp_i ( router_21_15_to_magia_tile_ni_21_15_rsp ), - .floo_req_i ( router_21_15_to_magia_tile_ni_21_15_req ), - .floo_rsp_o ( magia_tile_ni_21_15_to_router_21_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][16] ), - .id_i ( '{x: 22, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_16_to_router_21_16_req ), - .floo_rsp_i ( router_21_16_to_magia_tile_ni_21_16_rsp ), - .floo_req_i ( router_21_16_to_magia_tile_ni_21_16_req ), - .floo_rsp_o ( magia_tile_ni_21_16_to_router_21_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][17] ), - .id_i ( '{x: 22, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_17_to_router_21_17_req ), - .floo_rsp_i ( router_21_17_to_magia_tile_ni_21_17_rsp ), - .floo_req_i ( router_21_17_to_magia_tile_ni_21_17_req ), - .floo_rsp_o ( magia_tile_ni_21_17_to_router_21_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][18] ), - .id_i ( '{x: 22, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_18_to_router_21_18_req ), - .floo_rsp_i ( router_21_18_to_magia_tile_ni_21_18_rsp ), - .floo_req_i ( router_21_18_to_magia_tile_ni_21_18_req ), - .floo_rsp_o ( magia_tile_ni_21_18_to_router_21_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][19] ), - .id_i ( '{x: 22, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_19_to_router_21_19_req ), - .floo_rsp_i ( router_21_19_to_magia_tile_ni_21_19_rsp ), - .floo_req_i ( router_21_19_to_magia_tile_ni_21_19_req ), - .floo_rsp_o ( magia_tile_ni_21_19_to_router_21_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][20] ), - .id_i ( '{x: 22, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_20_to_router_21_20_req ), - .floo_rsp_i ( router_21_20_to_magia_tile_ni_21_20_rsp ), - .floo_req_i ( router_21_20_to_magia_tile_ni_21_20_req ), - .floo_rsp_o ( magia_tile_ni_21_20_to_router_21_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][21] ), - .id_i ( '{x: 22, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_21_to_router_21_21_req ), - .floo_rsp_i ( router_21_21_to_magia_tile_ni_21_21_rsp ), - .floo_req_i ( router_21_21_to_magia_tile_ni_21_21_req ), - .floo_rsp_o ( magia_tile_ni_21_21_to_router_21_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][22] ), - .id_i ( '{x: 22, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_22_to_router_21_22_req ), - .floo_rsp_i ( router_21_22_to_magia_tile_ni_21_22_rsp ), - .floo_req_i ( router_21_22_to_magia_tile_ni_21_22_req ), - .floo_rsp_o ( magia_tile_ni_21_22_to_router_21_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][23] ), - .id_i ( '{x: 22, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_23_to_router_21_23_req ), - .floo_rsp_i ( router_21_23_to_magia_tile_ni_21_23_rsp ), - .floo_req_i ( router_21_23_to_magia_tile_ni_21_23_req ), - .floo_rsp_o ( magia_tile_ni_21_23_to_router_21_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][24] ), - .id_i ( '{x: 22, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_24_to_router_21_24_req ), - .floo_rsp_i ( router_21_24_to_magia_tile_ni_21_24_rsp ), - .floo_req_i ( router_21_24_to_magia_tile_ni_21_24_req ), - .floo_rsp_o ( magia_tile_ni_21_24_to_router_21_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][25] ), - .id_i ( '{x: 22, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_25_to_router_21_25_req ), - .floo_rsp_i ( router_21_25_to_magia_tile_ni_21_25_rsp ), - .floo_req_i ( router_21_25_to_magia_tile_ni_21_25_req ), - .floo_rsp_o ( magia_tile_ni_21_25_to_router_21_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][26] ), - .id_i ( '{x: 22, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_26_to_router_21_26_req ), - .floo_rsp_i ( router_21_26_to_magia_tile_ni_21_26_rsp ), - .floo_req_i ( router_21_26_to_magia_tile_ni_21_26_req ), - .floo_rsp_o ( magia_tile_ni_21_26_to_router_21_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][27] ), - .id_i ( '{x: 22, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_27_to_router_21_27_req ), - .floo_rsp_i ( router_21_27_to_magia_tile_ni_21_27_rsp ), - .floo_req_i ( router_21_27_to_magia_tile_ni_21_27_req ), - .floo_rsp_o ( magia_tile_ni_21_27_to_router_21_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][28] ), - .id_i ( '{x: 22, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_28_to_router_21_28_req ), - .floo_rsp_i ( router_21_28_to_magia_tile_ni_21_28_rsp ), - .floo_req_i ( router_21_28_to_magia_tile_ni_21_28_req ), - .floo_rsp_o ( magia_tile_ni_21_28_to_router_21_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][29] ), - .id_i ( '{x: 22, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_29_to_router_21_29_req ), - .floo_rsp_i ( router_21_29_to_magia_tile_ni_21_29_rsp ), - .floo_req_i ( router_21_29_to_magia_tile_ni_21_29_req ), - .floo_rsp_o ( magia_tile_ni_21_29_to_router_21_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][30] ), - .id_i ( '{x: 22, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_30_to_router_21_30_req ), - .floo_rsp_i ( router_21_30_to_magia_tile_ni_21_30_rsp ), - .floo_req_i ( router_21_30_to_magia_tile_ni_21_30_req ), - .floo_rsp_o ( magia_tile_ni_21_30_to_router_21_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_21_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[21][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[21][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[21][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[21][31] ), - .id_i ( '{x: 22, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_21_31_to_router_21_31_req ), - .floo_rsp_i ( router_21_31_to_magia_tile_ni_21_31_rsp ), - .floo_req_i ( router_21_31_to_magia_tile_ni_21_31_req ), - .floo_rsp_o ( magia_tile_ni_21_31_to_router_21_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][0] ), - .id_i ( '{x: 23, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_0_to_router_22_0_req ), - .floo_rsp_i ( router_22_0_to_magia_tile_ni_22_0_rsp ), - .floo_req_i ( router_22_0_to_magia_tile_ni_22_0_req ), - .floo_rsp_o ( magia_tile_ni_22_0_to_router_22_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][1] ), - .id_i ( '{x: 23, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_1_to_router_22_1_req ), - .floo_rsp_i ( router_22_1_to_magia_tile_ni_22_1_rsp ), - .floo_req_i ( router_22_1_to_magia_tile_ni_22_1_req ), - .floo_rsp_o ( magia_tile_ni_22_1_to_router_22_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][2] ), - .id_i ( '{x: 23, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_2_to_router_22_2_req ), - .floo_rsp_i ( router_22_2_to_magia_tile_ni_22_2_rsp ), - .floo_req_i ( router_22_2_to_magia_tile_ni_22_2_req ), - .floo_rsp_o ( magia_tile_ni_22_2_to_router_22_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][3] ), - .id_i ( '{x: 23, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_3_to_router_22_3_req ), - .floo_rsp_i ( router_22_3_to_magia_tile_ni_22_3_rsp ), - .floo_req_i ( router_22_3_to_magia_tile_ni_22_3_req ), - .floo_rsp_o ( magia_tile_ni_22_3_to_router_22_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][4] ), - .id_i ( '{x: 23, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_4_to_router_22_4_req ), - .floo_rsp_i ( router_22_4_to_magia_tile_ni_22_4_rsp ), - .floo_req_i ( router_22_4_to_magia_tile_ni_22_4_req ), - .floo_rsp_o ( magia_tile_ni_22_4_to_router_22_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][5] ), - .id_i ( '{x: 23, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_5_to_router_22_5_req ), - .floo_rsp_i ( router_22_5_to_magia_tile_ni_22_5_rsp ), - .floo_req_i ( router_22_5_to_magia_tile_ni_22_5_req ), - .floo_rsp_o ( magia_tile_ni_22_5_to_router_22_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][6] ), - .id_i ( '{x: 23, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_6_to_router_22_6_req ), - .floo_rsp_i ( router_22_6_to_magia_tile_ni_22_6_rsp ), - .floo_req_i ( router_22_6_to_magia_tile_ni_22_6_req ), - .floo_rsp_o ( magia_tile_ni_22_6_to_router_22_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][7] ), - .id_i ( '{x: 23, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_7_to_router_22_7_req ), - .floo_rsp_i ( router_22_7_to_magia_tile_ni_22_7_rsp ), - .floo_req_i ( router_22_7_to_magia_tile_ni_22_7_req ), - .floo_rsp_o ( magia_tile_ni_22_7_to_router_22_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][8] ), - .id_i ( '{x: 23, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_8_to_router_22_8_req ), - .floo_rsp_i ( router_22_8_to_magia_tile_ni_22_8_rsp ), - .floo_req_i ( router_22_8_to_magia_tile_ni_22_8_req ), - .floo_rsp_o ( magia_tile_ni_22_8_to_router_22_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][9] ), - .id_i ( '{x: 23, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_9_to_router_22_9_req ), - .floo_rsp_i ( router_22_9_to_magia_tile_ni_22_9_rsp ), - .floo_req_i ( router_22_9_to_magia_tile_ni_22_9_req ), - .floo_rsp_o ( magia_tile_ni_22_9_to_router_22_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][10] ), - .id_i ( '{x: 23, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_10_to_router_22_10_req ), - .floo_rsp_i ( router_22_10_to_magia_tile_ni_22_10_rsp ), - .floo_req_i ( router_22_10_to_magia_tile_ni_22_10_req ), - .floo_rsp_o ( magia_tile_ni_22_10_to_router_22_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][11] ), - .id_i ( '{x: 23, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_11_to_router_22_11_req ), - .floo_rsp_i ( router_22_11_to_magia_tile_ni_22_11_rsp ), - .floo_req_i ( router_22_11_to_magia_tile_ni_22_11_req ), - .floo_rsp_o ( magia_tile_ni_22_11_to_router_22_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][12] ), - .id_i ( '{x: 23, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_12_to_router_22_12_req ), - .floo_rsp_i ( router_22_12_to_magia_tile_ni_22_12_rsp ), - .floo_req_i ( router_22_12_to_magia_tile_ni_22_12_req ), - .floo_rsp_o ( magia_tile_ni_22_12_to_router_22_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][13] ), - .id_i ( '{x: 23, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_13_to_router_22_13_req ), - .floo_rsp_i ( router_22_13_to_magia_tile_ni_22_13_rsp ), - .floo_req_i ( router_22_13_to_magia_tile_ni_22_13_req ), - .floo_rsp_o ( magia_tile_ni_22_13_to_router_22_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][14] ), - .id_i ( '{x: 23, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_14_to_router_22_14_req ), - .floo_rsp_i ( router_22_14_to_magia_tile_ni_22_14_rsp ), - .floo_req_i ( router_22_14_to_magia_tile_ni_22_14_req ), - .floo_rsp_o ( magia_tile_ni_22_14_to_router_22_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][15] ), - .id_i ( '{x: 23, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_15_to_router_22_15_req ), - .floo_rsp_i ( router_22_15_to_magia_tile_ni_22_15_rsp ), - .floo_req_i ( router_22_15_to_magia_tile_ni_22_15_req ), - .floo_rsp_o ( magia_tile_ni_22_15_to_router_22_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][16] ), - .id_i ( '{x: 23, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_16_to_router_22_16_req ), - .floo_rsp_i ( router_22_16_to_magia_tile_ni_22_16_rsp ), - .floo_req_i ( router_22_16_to_magia_tile_ni_22_16_req ), - .floo_rsp_o ( magia_tile_ni_22_16_to_router_22_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][17] ), - .id_i ( '{x: 23, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_17_to_router_22_17_req ), - .floo_rsp_i ( router_22_17_to_magia_tile_ni_22_17_rsp ), - .floo_req_i ( router_22_17_to_magia_tile_ni_22_17_req ), - .floo_rsp_o ( magia_tile_ni_22_17_to_router_22_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][18] ), - .id_i ( '{x: 23, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_18_to_router_22_18_req ), - .floo_rsp_i ( router_22_18_to_magia_tile_ni_22_18_rsp ), - .floo_req_i ( router_22_18_to_magia_tile_ni_22_18_req ), - .floo_rsp_o ( magia_tile_ni_22_18_to_router_22_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][19] ), - .id_i ( '{x: 23, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_19_to_router_22_19_req ), - .floo_rsp_i ( router_22_19_to_magia_tile_ni_22_19_rsp ), - .floo_req_i ( router_22_19_to_magia_tile_ni_22_19_req ), - .floo_rsp_o ( magia_tile_ni_22_19_to_router_22_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][20] ), - .id_i ( '{x: 23, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_20_to_router_22_20_req ), - .floo_rsp_i ( router_22_20_to_magia_tile_ni_22_20_rsp ), - .floo_req_i ( router_22_20_to_magia_tile_ni_22_20_req ), - .floo_rsp_o ( magia_tile_ni_22_20_to_router_22_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][21] ), - .id_i ( '{x: 23, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_21_to_router_22_21_req ), - .floo_rsp_i ( router_22_21_to_magia_tile_ni_22_21_rsp ), - .floo_req_i ( router_22_21_to_magia_tile_ni_22_21_req ), - .floo_rsp_o ( magia_tile_ni_22_21_to_router_22_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][22] ), - .id_i ( '{x: 23, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_22_to_router_22_22_req ), - .floo_rsp_i ( router_22_22_to_magia_tile_ni_22_22_rsp ), - .floo_req_i ( router_22_22_to_magia_tile_ni_22_22_req ), - .floo_rsp_o ( magia_tile_ni_22_22_to_router_22_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][23] ), - .id_i ( '{x: 23, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_23_to_router_22_23_req ), - .floo_rsp_i ( router_22_23_to_magia_tile_ni_22_23_rsp ), - .floo_req_i ( router_22_23_to_magia_tile_ni_22_23_req ), - .floo_rsp_o ( magia_tile_ni_22_23_to_router_22_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][24] ), - .id_i ( '{x: 23, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_24_to_router_22_24_req ), - .floo_rsp_i ( router_22_24_to_magia_tile_ni_22_24_rsp ), - .floo_req_i ( router_22_24_to_magia_tile_ni_22_24_req ), - .floo_rsp_o ( magia_tile_ni_22_24_to_router_22_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][25] ), - .id_i ( '{x: 23, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_25_to_router_22_25_req ), - .floo_rsp_i ( router_22_25_to_magia_tile_ni_22_25_rsp ), - .floo_req_i ( router_22_25_to_magia_tile_ni_22_25_req ), - .floo_rsp_o ( magia_tile_ni_22_25_to_router_22_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][26] ), - .id_i ( '{x: 23, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_26_to_router_22_26_req ), - .floo_rsp_i ( router_22_26_to_magia_tile_ni_22_26_rsp ), - .floo_req_i ( router_22_26_to_magia_tile_ni_22_26_req ), - .floo_rsp_o ( magia_tile_ni_22_26_to_router_22_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][27] ), - .id_i ( '{x: 23, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_27_to_router_22_27_req ), - .floo_rsp_i ( router_22_27_to_magia_tile_ni_22_27_rsp ), - .floo_req_i ( router_22_27_to_magia_tile_ni_22_27_req ), - .floo_rsp_o ( magia_tile_ni_22_27_to_router_22_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][28] ), - .id_i ( '{x: 23, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_28_to_router_22_28_req ), - .floo_rsp_i ( router_22_28_to_magia_tile_ni_22_28_rsp ), - .floo_req_i ( router_22_28_to_magia_tile_ni_22_28_req ), - .floo_rsp_o ( magia_tile_ni_22_28_to_router_22_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][29] ), - .id_i ( '{x: 23, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_29_to_router_22_29_req ), - .floo_rsp_i ( router_22_29_to_magia_tile_ni_22_29_rsp ), - .floo_req_i ( router_22_29_to_magia_tile_ni_22_29_req ), - .floo_rsp_o ( magia_tile_ni_22_29_to_router_22_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][30] ), - .id_i ( '{x: 23, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_30_to_router_22_30_req ), - .floo_rsp_i ( router_22_30_to_magia_tile_ni_22_30_rsp ), - .floo_req_i ( router_22_30_to_magia_tile_ni_22_30_req ), - .floo_rsp_o ( magia_tile_ni_22_30_to_router_22_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_22_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[22][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[22][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[22][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[22][31] ), - .id_i ( '{x: 23, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_22_31_to_router_22_31_req ), - .floo_rsp_i ( router_22_31_to_magia_tile_ni_22_31_rsp ), - .floo_req_i ( router_22_31_to_magia_tile_ni_22_31_req ), - .floo_rsp_o ( magia_tile_ni_22_31_to_router_22_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][0] ), - .id_i ( '{x: 24, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_0_to_router_23_0_req ), - .floo_rsp_i ( router_23_0_to_magia_tile_ni_23_0_rsp ), - .floo_req_i ( router_23_0_to_magia_tile_ni_23_0_req ), - .floo_rsp_o ( magia_tile_ni_23_0_to_router_23_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][1] ), - .id_i ( '{x: 24, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_1_to_router_23_1_req ), - .floo_rsp_i ( router_23_1_to_magia_tile_ni_23_1_rsp ), - .floo_req_i ( router_23_1_to_magia_tile_ni_23_1_req ), - .floo_rsp_o ( magia_tile_ni_23_1_to_router_23_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][2] ), - .id_i ( '{x: 24, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_2_to_router_23_2_req ), - .floo_rsp_i ( router_23_2_to_magia_tile_ni_23_2_rsp ), - .floo_req_i ( router_23_2_to_magia_tile_ni_23_2_req ), - .floo_rsp_o ( magia_tile_ni_23_2_to_router_23_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][3] ), - .id_i ( '{x: 24, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_3_to_router_23_3_req ), - .floo_rsp_i ( router_23_3_to_magia_tile_ni_23_3_rsp ), - .floo_req_i ( router_23_3_to_magia_tile_ni_23_3_req ), - .floo_rsp_o ( magia_tile_ni_23_3_to_router_23_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][4] ), - .id_i ( '{x: 24, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_4_to_router_23_4_req ), - .floo_rsp_i ( router_23_4_to_magia_tile_ni_23_4_rsp ), - .floo_req_i ( router_23_4_to_magia_tile_ni_23_4_req ), - .floo_rsp_o ( magia_tile_ni_23_4_to_router_23_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][5] ), - .id_i ( '{x: 24, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_5_to_router_23_5_req ), - .floo_rsp_i ( router_23_5_to_magia_tile_ni_23_5_rsp ), - .floo_req_i ( router_23_5_to_magia_tile_ni_23_5_req ), - .floo_rsp_o ( magia_tile_ni_23_5_to_router_23_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][6] ), - .id_i ( '{x: 24, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_6_to_router_23_6_req ), - .floo_rsp_i ( router_23_6_to_magia_tile_ni_23_6_rsp ), - .floo_req_i ( router_23_6_to_magia_tile_ni_23_6_req ), - .floo_rsp_o ( magia_tile_ni_23_6_to_router_23_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][7] ), - .id_i ( '{x: 24, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_7_to_router_23_7_req ), - .floo_rsp_i ( router_23_7_to_magia_tile_ni_23_7_rsp ), - .floo_req_i ( router_23_7_to_magia_tile_ni_23_7_req ), - .floo_rsp_o ( magia_tile_ni_23_7_to_router_23_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][8] ), - .id_i ( '{x: 24, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_8_to_router_23_8_req ), - .floo_rsp_i ( router_23_8_to_magia_tile_ni_23_8_rsp ), - .floo_req_i ( router_23_8_to_magia_tile_ni_23_8_req ), - .floo_rsp_o ( magia_tile_ni_23_8_to_router_23_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][9] ), - .id_i ( '{x: 24, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_9_to_router_23_9_req ), - .floo_rsp_i ( router_23_9_to_magia_tile_ni_23_9_rsp ), - .floo_req_i ( router_23_9_to_magia_tile_ni_23_9_req ), - .floo_rsp_o ( magia_tile_ni_23_9_to_router_23_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][10] ), - .id_i ( '{x: 24, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_10_to_router_23_10_req ), - .floo_rsp_i ( router_23_10_to_magia_tile_ni_23_10_rsp ), - .floo_req_i ( router_23_10_to_magia_tile_ni_23_10_req ), - .floo_rsp_o ( magia_tile_ni_23_10_to_router_23_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][11] ), - .id_i ( '{x: 24, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_11_to_router_23_11_req ), - .floo_rsp_i ( router_23_11_to_magia_tile_ni_23_11_rsp ), - .floo_req_i ( router_23_11_to_magia_tile_ni_23_11_req ), - .floo_rsp_o ( magia_tile_ni_23_11_to_router_23_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][12] ), - .id_i ( '{x: 24, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_12_to_router_23_12_req ), - .floo_rsp_i ( router_23_12_to_magia_tile_ni_23_12_rsp ), - .floo_req_i ( router_23_12_to_magia_tile_ni_23_12_req ), - .floo_rsp_o ( magia_tile_ni_23_12_to_router_23_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][13] ), - .id_i ( '{x: 24, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_13_to_router_23_13_req ), - .floo_rsp_i ( router_23_13_to_magia_tile_ni_23_13_rsp ), - .floo_req_i ( router_23_13_to_magia_tile_ni_23_13_req ), - .floo_rsp_o ( magia_tile_ni_23_13_to_router_23_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][14] ), - .id_i ( '{x: 24, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_14_to_router_23_14_req ), - .floo_rsp_i ( router_23_14_to_magia_tile_ni_23_14_rsp ), - .floo_req_i ( router_23_14_to_magia_tile_ni_23_14_req ), - .floo_rsp_o ( magia_tile_ni_23_14_to_router_23_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][15] ), - .id_i ( '{x: 24, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_15_to_router_23_15_req ), - .floo_rsp_i ( router_23_15_to_magia_tile_ni_23_15_rsp ), - .floo_req_i ( router_23_15_to_magia_tile_ni_23_15_req ), - .floo_rsp_o ( magia_tile_ni_23_15_to_router_23_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][16] ), - .id_i ( '{x: 24, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_16_to_router_23_16_req ), - .floo_rsp_i ( router_23_16_to_magia_tile_ni_23_16_rsp ), - .floo_req_i ( router_23_16_to_magia_tile_ni_23_16_req ), - .floo_rsp_o ( magia_tile_ni_23_16_to_router_23_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][17] ), - .id_i ( '{x: 24, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_17_to_router_23_17_req ), - .floo_rsp_i ( router_23_17_to_magia_tile_ni_23_17_rsp ), - .floo_req_i ( router_23_17_to_magia_tile_ni_23_17_req ), - .floo_rsp_o ( magia_tile_ni_23_17_to_router_23_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][18] ), - .id_i ( '{x: 24, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_18_to_router_23_18_req ), - .floo_rsp_i ( router_23_18_to_magia_tile_ni_23_18_rsp ), - .floo_req_i ( router_23_18_to_magia_tile_ni_23_18_req ), - .floo_rsp_o ( magia_tile_ni_23_18_to_router_23_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][19] ), - .id_i ( '{x: 24, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_19_to_router_23_19_req ), - .floo_rsp_i ( router_23_19_to_magia_tile_ni_23_19_rsp ), - .floo_req_i ( router_23_19_to_magia_tile_ni_23_19_req ), - .floo_rsp_o ( magia_tile_ni_23_19_to_router_23_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][20] ), - .id_i ( '{x: 24, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_20_to_router_23_20_req ), - .floo_rsp_i ( router_23_20_to_magia_tile_ni_23_20_rsp ), - .floo_req_i ( router_23_20_to_magia_tile_ni_23_20_req ), - .floo_rsp_o ( magia_tile_ni_23_20_to_router_23_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][21] ), - .id_i ( '{x: 24, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_21_to_router_23_21_req ), - .floo_rsp_i ( router_23_21_to_magia_tile_ni_23_21_rsp ), - .floo_req_i ( router_23_21_to_magia_tile_ni_23_21_req ), - .floo_rsp_o ( magia_tile_ni_23_21_to_router_23_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][22] ), - .id_i ( '{x: 24, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_22_to_router_23_22_req ), - .floo_rsp_i ( router_23_22_to_magia_tile_ni_23_22_rsp ), - .floo_req_i ( router_23_22_to_magia_tile_ni_23_22_req ), - .floo_rsp_o ( magia_tile_ni_23_22_to_router_23_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][23] ), - .id_i ( '{x: 24, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_23_to_router_23_23_req ), - .floo_rsp_i ( router_23_23_to_magia_tile_ni_23_23_rsp ), - .floo_req_i ( router_23_23_to_magia_tile_ni_23_23_req ), - .floo_rsp_o ( magia_tile_ni_23_23_to_router_23_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][24] ), - .id_i ( '{x: 24, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_24_to_router_23_24_req ), - .floo_rsp_i ( router_23_24_to_magia_tile_ni_23_24_rsp ), - .floo_req_i ( router_23_24_to_magia_tile_ni_23_24_req ), - .floo_rsp_o ( magia_tile_ni_23_24_to_router_23_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][25] ), - .id_i ( '{x: 24, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_25_to_router_23_25_req ), - .floo_rsp_i ( router_23_25_to_magia_tile_ni_23_25_rsp ), - .floo_req_i ( router_23_25_to_magia_tile_ni_23_25_req ), - .floo_rsp_o ( magia_tile_ni_23_25_to_router_23_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][26] ), - .id_i ( '{x: 24, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_26_to_router_23_26_req ), - .floo_rsp_i ( router_23_26_to_magia_tile_ni_23_26_rsp ), - .floo_req_i ( router_23_26_to_magia_tile_ni_23_26_req ), - .floo_rsp_o ( magia_tile_ni_23_26_to_router_23_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][27] ), - .id_i ( '{x: 24, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_27_to_router_23_27_req ), - .floo_rsp_i ( router_23_27_to_magia_tile_ni_23_27_rsp ), - .floo_req_i ( router_23_27_to_magia_tile_ni_23_27_req ), - .floo_rsp_o ( magia_tile_ni_23_27_to_router_23_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][28] ), - .id_i ( '{x: 24, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_28_to_router_23_28_req ), - .floo_rsp_i ( router_23_28_to_magia_tile_ni_23_28_rsp ), - .floo_req_i ( router_23_28_to_magia_tile_ni_23_28_req ), - .floo_rsp_o ( magia_tile_ni_23_28_to_router_23_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][29] ), - .id_i ( '{x: 24, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_29_to_router_23_29_req ), - .floo_rsp_i ( router_23_29_to_magia_tile_ni_23_29_rsp ), - .floo_req_i ( router_23_29_to_magia_tile_ni_23_29_req ), - .floo_rsp_o ( magia_tile_ni_23_29_to_router_23_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][30] ), - .id_i ( '{x: 24, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_30_to_router_23_30_req ), - .floo_rsp_i ( router_23_30_to_magia_tile_ni_23_30_rsp ), - .floo_req_i ( router_23_30_to_magia_tile_ni_23_30_req ), - .floo_rsp_o ( magia_tile_ni_23_30_to_router_23_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_23_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[23][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[23][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[23][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[23][31] ), - .id_i ( '{x: 24, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_23_31_to_router_23_31_req ), - .floo_rsp_i ( router_23_31_to_magia_tile_ni_23_31_rsp ), - .floo_req_i ( router_23_31_to_magia_tile_ni_23_31_req ), - .floo_rsp_o ( magia_tile_ni_23_31_to_router_23_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][0] ), - .id_i ( '{x: 25, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_0_to_router_24_0_req ), - .floo_rsp_i ( router_24_0_to_magia_tile_ni_24_0_rsp ), - .floo_req_i ( router_24_0_to_magia_tile_ni_24_0_req ), - .floo_rsp_o ( magia_tile_ni_24_0_to_router_24_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][1] ), - .id_i ( '{x: 25, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_1_to_router_24_1_req ), - .floo_rsp_i ( router_24_1_to_magia_tile_ni_24_1_rsp ), - .floo_req_i ( router_24_1_to_magia_tile_ni_24_1_req ), - .floo_rsp_o ( magia_tile_ni_24_1_to_router_24_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][2] ), - .id_i ( '{x: 25, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_2_to_router_24_2_req ), - .floo_rsp_i ( router_24_2_to_magia_tile_ni_24_2_rsp ), - .floo_req_i ( router_24_2_to_magia_tile_ni_24_2_req ), - .floo_rsp_o ( magia_tile_ni_24_2_to_router_24_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][3] ), - .id_i ( '{x: 25, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_3_to_router_24_3_req ), - .floo_rsp_i ( router_24_3_to_magia_tile_ni_24_3_rsp ), - .floo_req_i ( router_24_3_to_magia_tile_ni_24_3_req ), - .floo_rsp_o ( magia_tile_ni_24_3_to_router_24_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][4] ), - .id_i ( '{x: 25, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_4_to_router_24_4_req ), - .floo_rsp_i ( router_24_4_to_magia_tile_ni_24_4_rsp ), - .floo_req_i ( router_24_4_to_magia_tile_ni_24_4_req ), - .floo_rsp_o ( magia_tile_ni_24_4_to_router_24_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][5] ), - .id_i ( '{x: 25, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_5_to_router_24_5_req ), - .floo_rsp_i ( router_24_5_to_magia_tile_ni_24_5_rsp ), - .floo_req_i ( router_24_5_to_magia_tile_ni_24_5_req ), - .floo_rsp_o ( magia_tile_ni_24_5_to_router_24_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][6] ), - .id_i ( '{x: 25, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_6_to_router_24_6_req ), - .floo_rsp_i ( router_24_6_to_magia_tile_ni_24_6_rsp ), - .floo_req_i ( router_24_6_to_magia_tile_ni_24_6_req ), - .floo_rsp_o ( magia_tile_ni_24_6_to_router_24_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][7] ), - .id_i ( '{x: 25, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_7_to_router_24_7_req ), - .floo_rsp_i ( router_24_7_to_magia_tile_ni_24_7_rsp ), - .floo_req_i ( router_24_7_to_magia_tile_ni_24_7_req ), - .floo_rsp_o ( magia_tile_ni_24_7_to_router_24_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][8] ), - .id_i ( '{x: 25, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_8_to_router_24_8_req ), - .floo_rsp_i ( router_24_8_to_magia_tile_ni_24_8_rsp ), - .floo_req_i ( router_24_8_to_magia_tile_ni_24_8_req ), - .floo_rsp_o ( magia_tile_ni_24_8_to_router_24_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][9] ), - .id_i ( '{x: 25, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_9_to_router_24_9_req ), - .floo_rsp_i ( router_24_9_to_magia_tile_ni_24_9_rsp ), - .floo_req_i ( router_24_9_to_magia_tile_ni_24_9_req ), - .floo_rsp_o ( magia_tile_ni_24_9_to_router_24_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][10] ), - .id_i ( '{x: 25, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_10_to_router_24_10_req ), - .floo_rsp_i ( router_24_10_to_magia_tile_ni_24_10_rsp ), - .floo_req_i ( router_24_10_to_magia_tile_ni_24_10_req ), - .floo_rsp_o ( magia_tile_ni_24_10_to_router_24_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][11] ), - .id_i ( '{x: 25, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_11_to_router_24_11_req ), - .floo_rsp_i ( router_24_11_to_magia_tile_ni_24_11_rsp ), - .floo_req_i ( router_24_11_to_magia_tile_ni_24_11_req ), - .floo_rsp_o ( magia_tile_ni_24_11_to_router_24_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][12] ), - .id_i ( '{x: 25, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_12_to_router_24_12_req ), - .floo_rsp_i ( router_24_12_to_magia_tile_ni_24_12_rsp ), - .floo_req_i ( router_24_12_to_magia_tile_ni_24_12_req ), - .floo_rsp_o ( magia_tile_ni_24_12_to_router_24_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][13] ), - .id_i ( '{x: 25, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_13_to_router_24_13_req ), - .floo_rsp_i ( router_24_13_to_magia_tile_ni_24_13_rsp ), - .floo_req_i ( router_24_13_to_magia_tile_ni_24_13_req ), - .floo_rsp_o ( magia_tile_ni_24_13_to_router_24_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][14] ), - .id_i ( '{x: 25, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_14_to_router_24_14_req ), - .floo_rsp_i ( router_24_14_to_magia_tile_ni_24_14_rsp ), - .floo_req_i ( router_24_14_to_magia_tile_ni_24_14_req ), - .floo_rsp_o ( magia_tile_ni_24_14_to_router_24_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][15] ), - .id_i ( '{x: 25, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_15_to_router_24_15_req ), - .floo_rsp_i ( router_24_15_to_magia_tile_ni_24_15_rsp ), - .floo_req_i ( router_24_15_to_magia_tile_ni_24_15_req ), - .floo_rsp_o ( magia_tile_ni_24_15_to_router_24_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][16] ), - .id_i ( '{x: 25, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_16_to_router_24_16_req ), - .floo_rsp_i ( router_24_16_to_magia_tile_ni_24_16_rsp ), - .floo_req_i ( router_24_16_to_magia_tile_ni_24_16_req ), - .floo_rsp_o ( magia_tile_ni_24_16_to_router_24_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][17] ), - .id_i ( '{x: 25, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_17_to_router_24_17_req ), - .floo_rsp_i ( router_24_17_to_magia_tile_ni_24_17_rsp ), - .floo_req_i ( router_24_17_to_magia_tile_ni_24_17_req ), - .floo_rsp_o ( magia_tile_ni_24_17_to_router_24_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][18] ), - .id_i ( '{x: 25, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_18_to_router_24_18_req ), - .floo_rsp_i ( router_24_18_to_magia_tile_ni_24_18_rsp ), - .floo_req_i ( router_24_18_to_magia_tile_ni_24_18_req ), - .floo_rsp_o ( magia_tile_ni_24_18_to_router_24_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][19] ), - .id_i ( '{x: 25, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_19_to_router_24_19_req ), - .floo_rsp_i ( router_24_19_to_magia_tile_ni_24_19_rsp ), - .floo_req_i ( router_24_19_to_magia_tile_ni_24_19_req ), - .floo_rsp_o ( magia_tile_ni_24_19_to_router_24_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][20] ), - .id_i ( '{x: 25, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_20_to_router_24_20_req ), - .floo_rsp_i ( router_24_20_to_magia_tile_ni_24_20_rsp ), - .floo_req_i ( router_24_20_to_magia_tile_ni_24_20_req ), - .floo_rsp_o ( magia_tile_ni_24_20_to_router_24_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][21] ), - .id_i ( '{x: 25, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_21_to_router_24_21_req ), - .floo_rsp_i ( router_24_21_to_magia_tile_ni_24_21_rsp ), - .floo_req_i ( router_24_21_to_magia_tile_ni_24_21_req ), - .floo_rsp_o ( magia_tile_ni_24_21_to_router_24_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][22] ), - .id_i ( '{x: 25, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_22_to_router_24_22_req ), - .floo_rsp_i ( router_24_22_to_magia_tile_ni_24_22_rsp ), - .floo_req_i ( router_24_22_to_magia_tile_ni_24_22_req ), - .floo_rsp_o ( magia_tile_ni_24_22_to_router_24_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][23] ), - .id_i ( '{x: 25, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_23_to_router_24_23_req ), - .floo_rsp_i ( router_24_23_to_magia_tile_ni_24_23_rsp ), - .floo_req_i ( router_24_23_to_magia_tile_ni_24_23_req ), - .floo_rsp_o ( magia_tile_ni_24_23_to_router_24_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][24] ), - .id_i ( '{x: 25, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_24_to_router_24_24_req ), - .floo_rsp_i ( router_24_24_to_magia_tile_ni_24_24_rsp ), - .floo_req_i ( router_24_24_to_magia_tile_ni_24_24_req ), - .floo_rsp_o ( magia_tile_ni_24_24_to_router_24_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][25] ), - .id_i ( '{x: 25, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_25_to_router_24_25_req ), - .floo_rsp_i ( router_24_25_to_magia_tile_ni_24_25_rsp ), - .floo_req_i ( router_24_25_to_magia_tile_ni_24_25_req ), - .floo_rsp_o ( magia_tile_ni_24_25_to_router_24_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][26] ), - .id_i ( '{x: 25, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_26_to_router_24_26_req ), - .floo_rsp_i ( router_24_26_to_magia_tile_ni_24_26_rsp ), - .floo_req_i ( router_24_26_to_magia_tile_ni_24_26_req ), - .floo_rsp_o ( magia_tile_ni_24_26_to_router_24_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][27] ), - .id_i ( '{x: 25, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_27_to_router_24_27_req ), - .floo_rsp_i ( router_24_27_to_magia_tile_ni_24_27_rsp ), - .floo_req_i ( router_24_27_to_magia_tile_ni_24_27_req ), - .floo_rsp_o ( magia_tile_ni_24_27_to_router_24_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][28] ), - .id_i ( '{x: 25, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_28_to_router_24_28_req ), - .floo_rsp_i ( router_24_28_to_magia_tile_ni_24_28_rsp ), - .floo_req_i ( router_24_28_to_magia_tile_ni_24_28_req ), - .floo_rsp_o ( magia_tile_ni_24_28_to_router_24_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][29] ), - .id_i ( '{x: 25, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_29_to_router_24_29_req ), - .floo_rsp_i ( router_24_29_to_magia_tile_ni_24_29_rsp ), - .floo_req_i ( router_24_29_to_magia_tile_ni_24_29_req ), - .floo_rsp_o ( magia_tile_ni_24_29_to_router_24_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][30] ), - .id_i ( '{x: 25, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_30_to_router_24_30_req ), - .floo_rsp_i ( router_24_30_to_magia_tile_ni_24_30_rsp ), - .floo_req_i ( router_24_30_to_magia_tile_ni_24_30_req ), - .floo_rsp_o ( magia_tile_ni_24_30_to_router_24_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_24_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[24][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[24][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[24][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[24][31] ), - .id_i ( '{x: 25, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_24_31_to_router_24_31_req ), - .floo_rsp_i ( router_24_31_to_magia_tile_ni_24_31_rsp ), - .floo_req_i ( router_24_31_to_magia_tile_ni_24_31_req ), - .floo_rsp_o ( magia_tile_ni_24_31_to_router_24_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][0] ), - .id_i ( '{x: 26, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_0_to_router_25_0_req ), - .floo_rsp_i ( router_25_0_to_magia_tile_ni_25_0_rsp ), - .floo_req_i ( router_25_0_to_magia_tile_ni_25_0_req ), - .floo_rsp_o ( magia_tile_ni_25_0_to_router_25_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][1] ), - .id_i ( '{x: 26, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_1_to_router_25_1_req ), - .floo_rsp_i ( router_25_1_to_magia_tile_ni_25_1_rsp ), - .floo_req_i ( router_25_1_to_magia_tile_ni_25_1_req ), - .floo_rsp_o ( magia_tile_ni_25_1_to_router_25_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][2] ), - .id_i ( '{x: 26, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_2_to_router_25_2_req ), - .floo_rsp_i ( router_25_2_to_magia_tile_ni_25_2_rsp ), - .floo_req_i ( router_25_2_to_magia_tile_ni_25_2_req ), - .floo_rsp_o ( magia_tile_ni_25_2_to_router_25_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][3] ), - .id_i ( '{x: 26, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_3_to_router_25_3_req ), - .floo_rsp_i ( router_25_3_to_magia_tile_ni_25_3_rsp ), - .floo_req_i ( router_25_3_to_magia_tile_ni_25_3_req ), - .floo_rsp_o ( magia_tile_ni_25_3_to_router_25_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][4] ), - .id_i ( '{x: 26, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_4_to_router_25_4_req ), - .floo_rsp_i ( router_25_4_to_magia_tile_ni_25_4_rsp ), - .floo_req_i ( router_25_4_to_magia_tile_ni_25_4_req ), - .floo_rsp_o ( magia_tile_ni_25_4_to_router_25_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][5] ), - .id_i ( '{x: 26, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_5_to_router_25_5_req ), - .floo_rsp_i ( router_25_5_to_magia_tile_ni_25_5_rsp ), - .floo_req_i ( router_25_5_to_magia_tile_ni_25_5_req ), - .floo_rsp_o ( magia_tile_ni_25_5_to_router_25_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][6] ), - .id_i ( '{x: 26, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_6_to_router_25_6_req ), - .floo_rsp_i ( router_25_6_to_magia_tile_ni_25_6_rsp ), - .floo_req_i ( router_25_6_to_magia_tile_ni_25_6_req ), - .floo_rsp_o ( magia_tile_ni_25_6_to_router_25_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][7] ), - .id_i ( '{x: 26, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_7_to_router_25_7_req ), - .floo_rsp_i ( router_25_7_to_magia_tile_ni_25_7_rsp ), - .floo_req_i ( router_25_7_to_magia_tile_ni_25_7_req ), - .floo_rsp_o ( magia_tile_ni_25_7_to_router_25_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][8] ), - .id_i ( '{x: 26, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_8_to_router_25_8_req ), - .floo_rsp_i ( router_25_8_to_magia_tile_ni_25_8_rsp ), - .floo_req_i ( router_25_8_to_magia_tile_ni_25_8_req ), - .floo_rsp_o ( magia_tile_ni_25_8_to_router_25_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][9] ), - .id_i ( '{x: 26, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_9_to_router_25_9_req ), - .floo_rsp_i ( router_25_9_to_magia_tile_ni_25_9_rsp ), - .floo_req_i ( router_25_9_to_magia_tile_ni_25_9_req ), - .floo_rsp_o ( magia_tile_ni_25_9_to_router_25_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][10] ), - .id_i ( '{x: 26, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_10_to_router_25_10_req ), - .floo_rsp_i ( router_25_10_to_magia_tile_ni_25_10_rsp ), - .floo_req_i ( router_25_10_to_magia_tile_ni_25_10_req ), - .floo_rsp_o ( magia_tile_ni_25_10_to_router_25_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][11] ), - .id_i ( '{x: 26, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_11_to_router_25_11_req ), - .floo_rsp_i ( router_25_11_to_magia_tile_ni_25_11_rsp ), - .floo_req_i ( router_25_11_to_magia_tile_ni_25_11_req ), - .floo_rsp_o ( magia_tile_ni_25_11_to_router_25_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][12] ), - .id_i ( '{x: 26, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_12_to_router_25_12_req ), - .floo_rsp_i ( router_25_12_to_magia_tile_ni_25_12_rsp ), - .floo_req_i ( router_25_12_to_magia_tile_ni_25_12_req ), - .floo_rsp_o ( magia_tile_ni_25_12_to_router_25_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][13] ), - .id_i ( '{x: 26, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_13_to_router_25_13_req ), - .floo_rsp_i ( router_25_13_to_magia_tile_ni_25_13_rsp ), - .floo_req_i ( router_25_13_to_magia_tile_ni_25_13_req ), - .floo_rsp_o ( magia_tile_ni_25_13_to_router_25_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][14] ), - .id_i ( '{x: 26, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_14_to_router_25_14_req ), - .floo_rsp_i ( router_25_14_to_magia_tile_ni_25_14_rsp ), - .floo_req_i ( router_25_14_to_magia_tile_ni_25_14_req ), - .floo_rsp_o ( magia_tile_ni_25_14_to_router_25_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][15] ), - .id_i ( '{x: 26, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_15_to_router_25_15_req ), - .floo_rsp_i ( router_25_15_to_magia_tile_ni_25_15_rsp ), - .floo_req_i ( router_25_15_to_magia_tile_ni_25_15_req ), - .floo_rsp_o ( magia_tile_ni_25_15_to_router_25_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][16] ), - .id_i ( '{x: 26, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_16_to_router_25_16_req ), - .floo_rsp_i ( router_25_16_to_magia_tile_ni_25_16_rsp ), - .floo_req_i ( router_25_16_to_magia_tile_ni_25_16_req ), - .floo_rsp_o ( magia_tile_ni_25_16_to_router_25_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][17] ), - .id_i ( '{x: 26, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_17_to_router_25_17_req ), - .floo_rsp_i ( router_25_17_to_magia_tile_ni_25_17_rsp ), - .floo_req_i ( router_25_17_to_magia_tile_ni_25_17_req ), - .floo_rsp_o ( magia_tile_ni_25_17_to_router_25_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][18] ), - .id_i ( '{x: 26, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_18_to_router_25_18_req ), - .floo_rsp_i ( router_25_18_to_magia_tile_ni_25_18_rsp ), - .floo_req_i ( router_25_18_to_magia_tile_ni_25_18_req ), - .floo_rsp_o ( magia_tile_ni_25_18_to_router_25_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][19] ), - .id_i ( '{x: 26, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_19_to_router_25_19_req ), - .floo_rsp_i ( router_25_19_to_magia_tile_ni_25_19_rsp ), - .floo_req_i ( router_25_19_to_magia_tile_ni_25_19_req ), - .floo_rsp_o ( magia_tile_ni_25_19_to_router_25_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][20] ), - .id_i ( '{x: 26, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_20_to_router_25_20_req ), - .floo_rsp_i ( router_25_20_to_magia_tile_ni_25_20_rsp ), - .floo_req_i ( router_25_20_to_magia_tile_ni_25_20_req ), - .floo_rsp_o ( magia_tile_ni_25_20_to_router_25_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][21] ), - .id_i ( '{x: 26, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_21_to_router_25_21_req ), - .floo_rsp_i ( router_25_21_to_magia_tile_ni_25_21_rsp ), - .floo_req_i ( router_25_21_to_magia_tile_ni_25_21_req ), - .floo_rsp_o ( magia_tile_ni_25_21_to_router_25_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][22] ), - .id_i ( '{x: 26, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_22_to_router_25_22_req ), - .floo_rsp_i ( router_25_22_to_magia_tile_ni_25_22_rsp ), - .floo_req_i ( router_25_22_to_magia_tile_ni_25_22_req ), - .floo_rsp_o ( magia_tile_ni_25_22_to_router_25_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][23] ), - .id_i ( '{x: 26, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_23_to_router_25_23_req ), - .floo_rsp_i ( router_25_23_to_magia_tile_ni_25_23_rsp ), - .floo_req_i ( router_25_23_to_magia_tile_ni_25_23_req ), - .floo_rsp_o ( magia_tile_ni_25_23_to_router_25_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][24] ), - .id_i ( '{x: 26, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_24_to_router_25_24_req ), - .floo_rsp_i ( router_25_24_to_magia_tile_ni_25_24_rsp ), - .floo_req_i ( router_25_24_to_magia_tile_ni_25_24_req ), - .floo_rsp_o ( magia_tile_ni_25_24_to_router_25_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][25] ), - .id_i ( '{x: 26, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_25_to_router_25_25_req ), - .floo_rsp_i ( router_25_25_to_magia_tile_ni_25_25_rsp ), - .floo_req_i ( router_25_25_to_magia_tile_ni_25_25_req ), - .floo_rsp_o ( magia_tile_ni_25_25_to_router_25_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][26] ), - .id_i ( '{x: 26, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_26_to_router_25_26_req ), - .floo_rsp_i ( router_25_26_to_magia_tile_ni_25_26_rsp ), - .floo_req_i ( router_25_26_to_magia_tile_ni_25_26_req ), - .floo_rsp_o ( magia_tile_ni_25_26_to_router_25_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][27] ), - .id_i ( '{x: 26, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_27_to_router_25_27_req ), - .floo_rsp_i ( router_25_27_to_magia_tile_ni_25_27_rsp ), - .floo_req_i ( router_25_27_to_magia_tile_ni_25_27_req ), - .floo_rsp_o ( magia_tile_ni_25_27_to_router_25_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][28] ), - .id_i ( '{x: 26, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_28_to_router_25_28_req ), - .floo_rsp_i ( router_25_28_to_magia_tile_ni_25_28_rsp ), - .floo_req_i ( router_25_28_to_magia_tile_ni_25_28_req ), - .floo_rsp_o ( magia_tile_ni_25_28_to_router_25_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][29] ), - .id_i ( '{x: 26, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_29_to_router_25_29_req ), - .floo_rsp_i ( router_25_29_to_magia_tile_ni_25_29_rsp ), - .floo_req_i ( router_25_29_to_magia_tile_ni_25_29_req ), - .floo_rsp_o ( magia_tile_ni_25_29_to_router_25_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][30] ), - .id_i ( '{x: 26, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_30_to_router_25_30_req ), - .floo_rsp_i ( router_25_30_to_magia_tile_ni_25_30_rsp ), - .floo_req_i ( router_25_30_to_magia_tile_ni_25_30_req ), - .floo_rsp_o ( magia_tile_ni_25_30_to_router_25_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_25_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[25][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[25][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[25][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[25][31] ), - .id_i ( '{x: 26, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_25_31_to_router_25_31_req ), - .floo_rsp_i ( router_25_31_to_magia_tile_ni_25_31_rsp ), - .floo_req_i ( router_25_31_to_magia_tile_ni_25_31_req ), - .floo_rsp_o ( magia_tile_ni_25_31_to_router_25_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][0] ), - .id_i ( '{x: 27, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_0_to_router_26_0_req ), - .floo_rsp_i ( router_26_0_to_magia_tile_ni_26_0_rsp ), - .floo_req_i ( router_26_0_to_magia_tile_ni_26_0_req ), - .floo_rsp_o ( magia_tile_ni_26_0_to_router_26_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][1] ), - .id_i ( '{x: 27, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_1_to_router_26_1_req ), - .floo_rsp_i ( router_26_1_to_magia_tile_ni_26_1_rsp ), - .floo_req_i ( router_26_1_to_magia_tile_ni_26_1_req ), - .floo_rsp_o ( magia_tile_ni_26_1_to_router_26_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][2] ), - .id_i ( '{x: 27, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_2_to_router_26_2_req ), - .floo_rsp_i ( router_26_2_to_magia_tile_ni_26_2_rsp ), - .floo_req_i ( router_26_2_to_magia_tile_ni_26_2_req ), - .floo_rsp_o ( magia_tile_ni_26_2_to_router_26_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][3] ), - .id_i ( '{x: 27, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_3_to_router_26_3_req ), - .floo_rsp_i ( router_26_3_to_magia_tile_ni_26_3_rsp ), - .floo_req_i ( router_26_3_to_magia_tile_ni_26_3_req ), - .floo_rsp_o ( magia_tile_ni_26_3_to_router_26_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][4] ), - .id_i ( '{x: 27, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_4_to_router_26_4_req ), - .floo_rsp_i ( router_26_4_to_magia_tile_ni_26_4_rsp ), - .floo_req_i ( router_26_4_to_magia_tile_ni_26_4_req ), - .floo_rsp_o ( magia_tile_ni_26_4_to_router_26_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][5] ), - .id_i ( '{x: 27, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_5_to_router_26_5_req ), - .floo_rsp_i ( router_26_5_to_magia_tile_ni_26_5_rsp ), - .floo_req_i ( router_26_5_to_magia_tile_ni_26_5_req ), - .floo_rsp_o ( magia_tile_ni_26_5_to_router_26_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][6] ), - .id_i ( '{x: 27, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_6_to_router_26_6_req ), - .floo_rsp_i ( router_26_6_to_magia_tile_ni_26_6_rsp ), - .floo_req_i ( router_26_6_to_magia_tile_ni_26_6_req ), - .floo_rsp_o ( magia_tile_ni_26_6_to_router_26_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][7] ), - .id_i ( '{x: 27, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_7_to_router_26_7_req ), - .floo_rsp_i ( router_26_7_to_magia_tile_ni_26_7_rsp ), - .floo_req_i ( router_26_7_to_magia_tile_ni_26_7_req ), - .floo_rsp_o ( magia_tile_ni_26_7_to_router_26_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][8] ), - .id_i ( '{x: 27, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_8_to_router_26_8_req ), - .floo_rsp_i ( router_26_8_to_magia_tile_ni_26_8_rsp ), - .floo_req_i ( router_26_8_to_magia_tile_ni_26_8_req ), - .floo_rsp_o ( magia_tile_ni_26_8_to_router_26_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][9] ), - .id_i ( '{x: 27, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_9_to_router_26_9_req ), - .floo_rsp_i ( router_26_9_to_magia_tile_ni_26_9_rsp ), - .floo_req_i ( router_26_9_to_magia_tile_ni_26_9_req ), - .floo_rsp_o ( magia_tile_ni_26_9_to_router_26_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][10] ), - .id_i ( '{x: 27, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_10_to_router_26_10_req ), - .floo_rsp_i ( router_26_10_to_magia_tile_ni_26_10_rsp ), - .floo_req_i ( router_26_10_to_magia_tile_ni_26_10_req ), - .floo_rsp_o ( magia_tile_ni_26_10_to_router_26_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][11] ), - .id_i ( '{x: 27, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_11_to_router_26_11_req ), - .floo_rsp_i ( router_26_11_to_magia_tile_ni_26_11_rsp ), - .floo_req_i ( router_26_11_to_magia_tile_ni_26_11_req ), - .floo_rsp_o ( magia_tile_ni_26_11_to_router_26_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][12] ), - .id_i ( '{x: 27, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_12_to_router_26_12_req ), - .floo_rsp_i ( router_26_12_to_magia_tile_ni_26_12_rsp ), - .floo_req_i ( router_26_12_to_magia_tile_ni_26_12_req ), - .floo_rsp_o ( magia_tile_ni_26_12_to_router_26_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][13] ), - .id_i ( '{x: 27, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_13_to_router_26_13_req ), - .floo_rsp_i ( router_26_13_to_magia_tile_ni_26_13_rsp ), - .floo_req_i ( router_26_13_to_magia_tile_ni_26_13_req ), - .floo_rsp_o ( magia_tile_ni_26_13_to_router_26_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][14] ), - .id_i ( '{x: 27, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_14_to_router_26_14_req ), - .floo_rsp_i ( router_26_14_to_magia_tile_ni_26_14_rsp ), - .floo_req_i ( router_26_14_to_magia_tile_ni_26_14_req ), - .floo_rsp_o ( magia_tile_ni_26_14_to_router_26_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][15] ), - .id_i ( '{x: 27, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_15_to_router_26_15_req ), - .floo_rsp_i ( router_26_15_to_magia_tile_ni_26_15_rsp ), - .floo_req_i ( router_26_15_to_magia_tile_ni_26_15_req ), - .floo_rsp_o ( magia_tile_ni_26_15_to_router_26_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][16] ), - .id_i ( '{x: 27, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_16_to_router_26_16_req ), - .floo_rsp_i ( router_26_16_to_magia_tile_ni_26_16_rsp ), - .floo_req_i ( router_26_16_to_magia_tile_ni_26_16_req ), - .floo_rsp_o ( magia_tile_ni_26_16_to_router_26_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][17] ), - .id_i ( '{x: 27, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_17_to_router_26_17_req ), - .floo_rsp_i ( router_26_17_to_magia_tile_ni_26_17_rsp ), - .floo_req_i ( router_26_17_to_magia_tile_ni_26_17_req ), - .floo_rsp_o ( magia_tile_ni_26_17_to_router_26_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][18] ), - .id_i ( '{x: 27, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_18_to_router_26_18_req ), - .floo_rsp_i ( router_26_18_to_magia_tile_ni_26_18_rsp ), - .floo_req_i ( router_26_18_to_magia_tile_ni_26_18_req ), - .floo_rsp_o ( magia_tile_ni_26_18_to_router_26_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][19] ), - .id_i ( '{x: 27, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_19_to_router_26_19_req ), - .floo_rsp_i ( router_26_19_to_magia_tile_ni_26_19_rsp ), - .floo_req_i ( router_26_19_to_magia_tile_ni_26_19_req ), - .floo_rsp_o ( magia_tile_ni_26_19_to_router_26_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][20] ), - .id_i ( '{x: 27, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_20_to_router_26_20_req ), - .floo_rsp_i ( router_26_20_to_magia_tile_ni_26_20_rsp ), - .floo_req_i ( router_26_20_to_magia_tile_ni_26_20_req ), - .floo_rsp_o ( magia_tile_ni_26_20_to_router_26_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][21] ), - .id_i ( '{x: 27, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_21_to_router_26_21_req ), - .floo_rsp_i ( router_26_21_to_magia_tile_ni_26_21_rsp ), - .floo_req_i ( router_26_21_to_magia_tile_ni_26_21_req ), - .floo_rsp_o ( magia_tile_ni_26_21_to_router_26_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][22] ), - .id_i ( '{x: 27, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_22_to_router_26_22_req ), - .floo_rsp_i ( router_26_22_to_magia_tile_ni_26_22_rsp ), - .floo_req_i ( router_26_22_to_magia_tile_ni_26_22_req ), - .floo_rsp_o ( magia_tile_ni_26_22_to_router_26_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][23] ), - .id_i ( '{x: 27, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_23_to_router_26_23_req ), - .floo_rsp_i ( router_26_23_to_magia_tile_ni_26_23_rsp ), - .floo_req_i ( router_26_23_to_magia_tile_ni_26_23_req ), - .floo_rsp_o ( magia_tile_ni_26_23_to_router_26_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][24] ), - .id_i ( '{x: 27, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_24_to_router_26_24_req ), - .floo_rsp_i ( router_26_24_to_magia_tile_ni_26_24_rsp ), - .floo_req_i ( router_26_24_to_magia_tile_ni_26_24_req ), - .floo_rsp_o ( magia_tile_ni_26_24_to_router_26_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][25] ), - .id_i ( '{x: 27, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_25_to_router_26_25_req ), - .floo_rsp_i ( router_26_25_to_magia_tile_ni_26_25_rsp ), - .floo_req_i ( router_26_25_to_magia_tile_ni_26_25_req ), - .floo_rsp_o ( magia_tile_ni_26_25_to_router_26_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][26] ), - .id_i ( '{x: 27, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_26_to_router_26_26_req ), - .floo_rsp_i ( router_26_26_to_magia_tile_ni_26_26_rsp ), - .floo_req_i ( router_26_26_to_magia_tile_ni_26_26_req ), - .floo_rsp_o ( magia_tile_ni_26_26_to_router_26_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][27] ), - .id_i ( '{x: 27, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_27_to_router_26_27_req ), - .floo_rsp_i ( router_26_27_to_magia_tile_ni_26_27_rsp ), - .floo_req_i ( router_26_27_to_magia_tile_ni_26_27_req ), - .floo_rsp_o ( magia_tile_ni_26_27_to_router_26_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][28] ), - .id_i ( '{x: 27, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_28_to_router_26_28_req ), - .floo_rsp_i ( router_26_28_to_magia_tile_ni_26_28_rsp ), - .floo_req_i ( router_26_28_to_magia_tile_ni_26_28_req ), - .floo_rsp_o ( magia_tile_ni_26_28_to_router_26_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][29] ), - .id_i ( '{x: 27, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_29_to_router_26_29_req ), - .floo_rsp_i ( router_26_29_to_magia_tile_ni_26_29_rsp ), - .floo_req_i ( router_26_29_to_magia_tile_ni_26_29_req ), - .floo_rsp_o ( magia_tile_ni_26_29_to_router_26_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][30] ), - .id_i ( '{x: 27, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_30_to_router_26_30_req ), - .floo_rsp_i ( router_26_30_to_magia_tile_ni_26_30_rsp ), - .floo_req_i ( router_26_30_to_magia_tile_ni_26_30_req ), - .floo_rsp_o ( magia_tile_ni_26_30_to_router_26_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_26_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[26][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[26][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[26][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[26][31] ), - .id_i ( '{x: 27, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_26_31_to_router_26_31_req ), - .floo_rsp_i ( router_26_31_to_magia_tile_ni_26_31_rsp ), - .floo_req_i ( router_26_31_to_magia_tile_ni_26_31_req ), - .floo_rsp_o ( magia_tile_ni_26_31_to_router_26_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][0] ), - .id_i ( '{x: 28, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_0_to_router_27_0_req ), - .floo_rsp_i ( router_27_0_to_magia_tile_ni_27_0_rsp ), - .floo_req_i ( router_27_0_to_magia_tile_ni_27_0_req ), - .floo_rsp_o ( magia_tile_ni_27_0_to_router_27_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][1] ), - .id_i ( '{x: 28, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_1_to_router_27_1_req ), - .floo_rsp_i ( router_27_1_to_magia_tile_ni_27_1_rsp ), - .floo_req_i ( router_27_1_to_magia_tile_ni_27_1_req ), - .floo_rsp_o ( magia_tile_ni_27_1_to_router_27_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][2] ), - .id_i ( '{x: 28, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_2_to_router_27_2_req ), - .floo_rsp_i ( router_27_2_to_magia_tile_ni_27_2_rsp ), - .floo_req_i ( router_27_2_to_magia_tile_ni_27_2_req ), - .floo_rsp_o ( magia_tile_ni_27_2_to_router_27_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][3] ), - .id_i ( '{x: 28, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_3_to_router_27_3_req ), - .floo_rsp_i ( router_27_3_to_magia_tile_ni_27_3_rsp ), - .floo_req_i ( router_27_3_to_magia_tile_ni_27_3_req ), - .floo_rsp_o ( magia_tile_ni_27_3_to_router_27_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][4] ), - .id_i ( '{x: 28, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_4_to_router_27_4_req ), - .floo_rsp_i ( router_27_4_to_magia_tile_ni_27_4_rsp ), - .floo_req_i ( router_27_4_to_magia_tile_ni_27_4_req ), - .floo_rsp_o ( magia_tile_ni_27_4_to_router_27_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][5] ), - .id_i ( '{x: 28, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_5_to_router_27_5_req ), - .floo_rsp_i ( router_27_5_to_magia_tile_ni_27_5_rsp ), - .floo_req_i ( router_27_5_to_magia_tile_ni_27_5_req ), - .floo_rsp_o ( magia_tile_ni_27_5_to_router_27_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][6] ), - .id_i ( '{x: 28, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_6_to_router_27_6_req ), - .floo_rsp_i ( router_27_6_to_magia_tile_ni_27_6_rsp ), - .floo_req_i ( router_27_6_to_magia_tile_ni_27_6_req ), - .floo_rsp_o ( magia_tile_ni_27_6_to_router_27_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][7] ), - .id_i ( '{x: 28, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_7_to_router_27_7_req ), - .floo_rsp_i ( router_27_7_to_magia_tile_ni_27_7_rsp ), - .floo_req_i ( router_27_7_to_magia_tile_ni_27_7_req ), - .floo_rsp_o ( magia_tile_ni_27_7_to_router_27_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][8] ), - .id_i ( '{x: 28, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_8_to_router_27_8_req ), - .floo_rsp_i ( router_27_8_to_magia_tile_ni_27_8_rsp ), - .floo_req_i ( router_27_8_to_magia_tile_ni_27_8_req ), - .floo_rsp_o ( magia_tile_ni_27_8_to_router_27_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][9] ), - .id_i ( '{x: 28, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_9_to_router_27_9_req ), - .floo_rsp_i ( router_27_9_to_magia_tile_ni_27_9_rsp ), - .floo_req_i ( router_27_9_to_magia_tile_ni_27_9_req ), - .floo_rsp_o ( magia_tile_ni_27_9_to_router_27_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][10] ), - .id_i ( '{x: 28, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_10_to_router_27_10_req ), - .floo_rsp_i ( router_27_10_to_magia_tile_ni_27_10_rsp ), - .floo_req_i ( router_27_10_to_magia_tile_ni_27_10_req ), - .floo_rsp_o ( magia_tile_ni_27_10_to_router_27_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][11] ), - .id_i ( '{x: 28, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_11_to_router_27_11_req ), - .floo_rsp_i ( router_27_11_to_magia_tile_ni_27_11_rsp ), - .floo_req_i ( router_27_11_to_magia_tile_ni_27_11_req ), - .floo_rsp_o ( magia_tile_ni_27_11_to_router_27_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][12] ), - .id_i ( '{x: 28, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_12_to_router_27_12_req ), - .floo_rsp_i ( router_27_12_to_magia_tile_ni_27_12_rsp ), - .floo_req_i ( router_27_12_to_magia_tile_ni_27_12_req ), - .floo_rsp_o ( magia_tile_ni_27_12_to_router_27_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][13] ), - .id_i ( '{x: 28, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_13_to_router_27_13_req ), - .floo_rsp_i ( router_27_13_to_magia_tile_ni_27_13_rsp ), - .floo_req_i ( router_27_13_to_magia_tile_ni_27_13_req ), - .floo_rsp_o ( magia_tile_ni_27_13_to_router_27_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][14] ), - .id_i ( '{x: 28, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_14_to_router_27_14_req ), - .floo_rsp_i ( router_27_14_to_magia_tile_ni_27_14_rsp ), - .floo_req_i ( router_27_14_to_magia_tile_ni_27_14_req ), - .floo_rsp_o ( magia_tile_ni_27_14_to_router_27_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][15] ), - .id_i ( '{x: 28, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_15_to_router_27_15_req ), - .floo_rsp_i ( router_27_15_to_magia_tile_ni_27_15_rsp ), - .floo_req_i ( router_27_15_to_magia_tile_ni_27_15_req ), - .floo_rsp_o ( magia_tile_ni_27_15_to_router_27_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][16] ), - .id_i ( '{x: 28, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_16_to_router_27_16_req ), - .floo_rsp_i ( router_27_16_to_magia_tile_ni_27_16_rsp ), - .floo_req_i ( router_27_16_to_magia_tile_ni_27_16_req ), - .floo_rsp_o ( magia_tile_ni_27_16_to_router_27_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][17] ), - .id_i ( '{x: 28, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_17_to_router_27_17_req ), - .floo_rsp_i ( router_27_17_to_magia_tile_ni_27_17_rsp ), - .floo_req_i ( router_27_17_to_magia_tile_ni_27_17_req ), - .floo_rsp_o ( magia_tile_ni_27_17_to_router_27_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][18] ), - .id_i ( '{x: 28, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_18_to_router_27_18_req ), - .floo_rsp_i ( router_27_18_to_magia_tile_ni_27_18_rsp ), - .floo_req_i ( router_27_18_to_magia_tile_ni_27_18_req ), - .floo_rsp_o ( magia_tile_ni_27_18_to_router_27_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][19] ), - .id_i ( '{x: 28, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_19_to_router_27_19_req ), - .floo_rsp_i ( router_27_19_to_magia_tile_ni_27_19_rsp ), - .floo_req_i ( router_27_19_to_magia_tile_ni_27_19_req ), - .floo_rsp_o ( magia_tile_ni_27_19_to_router_27_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][20] ), - .id_i ( '{x: 28, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_20_to_router_27_20_req ), - .floo_rsp_i ( router_27_20_to_magia_tile_ni_27_20_rsp ), - .floo_req_i ( router_27_20_to_magia_tile_ni_27_20_req ), - .floo_rsp_o ( magia_tile_ni_27_20_to_router_27_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][21] ), - .id_i ( '{x: 28, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_21_to_router_27_21_req ), - .floo_rsp_i ( router_27_21_to_magia_tile_ni_27_21_rsp ), - .floo_req_i ( router_27_21_to_magia_tile_ni_27_21_req ), - .floo_rsp_o ( magia_tile_ni_27_21_to_router_27_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][22] ), - .id_i ( '{x: 28, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_22_to_router_27_22_req ), - .floo_rsp_i ( router_27_22_to_magia_tile_ni_27_22_rsp ), - .floo_req_i ( router_27_22_to_magia_tile_ni_27_22_req ), - .floo_rsp_o ( magia_tile_ni_27_22_to_router_27_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][23] ), - .id_i ( '{x: 28, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_23_to_router_27_23_req ), - .floo_rsp_i ( router_27_23_to_magia_tile_ni_27_23_rsp ), - .floo_req_i ( router_27_23_to_magia_tile_ni_27_23_req ), - .floo_rsp_o ( magia_tile_ni_27_23_to_router_27_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][24] ), - .id_i ( '{x: 28, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_24_to_router_27_24_req ), - .floo_rsp_i ( router_27_24_to_magia_tile_ni_27_24_rsp ), - .floo_req_i ( router_27_24_to_magia_tile_ni_27_24_req ), - .floo_rsp_o ( magia_tile_ni_27_24_to_router_27_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][25] ), - .id_i ( '{x: 28, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_25_to_router_27_25_req ), - .floo_rsp_i ( router_27_25_to_magia_tile_ni_27_25_rsp ), - .floo_req_i ( router_27_25_to_magia_tile_ni_27_25_req ), - .floo_rsp_o ( magia_tile_ni_27_25_to_router_27_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][26] ), - .id_i ( '{x: 28, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_26_to_router_27_26_req ), - .floo_rsp_i ( router_27_26_to_magia_tile_ni_27_26_rsp ), - .floo_req_i ( router_27_26_to_magia_tile_ni_27_26_req ), - .floo_rsp_o ( magia_tile_ni_27_26_to_router_27_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][27] ), - .id_i ( '{x: 28, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_27_to_router_27_27_req ), - .floo_rsp_i ( router_27_27_to_magia_tile_ni_27_27_rsp ), - .floo_req_i ( router_27_27_to_magia_tile_ni_27_27_req ), - .floo_rsp_o ( magia_tile_ni_27_27_to_router_27_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][28] ), - .id_i ( '{x: 28, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_28_to_router_27_28_req ), - .floo_rsp_i ( router_27_28_to_magia_tile_ni_27_28_rsp ), - .floo_req_i ( router_27_28_to_magia_tile_ni_27_28_req ), - .floo_rsp_o ( magia_tile_ni_27_28_to_router_27_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][29] ), - .id_i ( '{x: 28, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_29_to_router_27_29_req ), - .floo_rsp_i ( router_27_29_to_magia_tile_ni_27_29_rsp ), - .floo_req_i ( router_27_29_to_magia_tile_ni_27_29_req ), - .floo_rsp_o ( magia_tile_ni_27_29_to_router_27_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][30] ), - .id_i ( '{x: 28, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_30_to_router_27_30_req ), - .floo_rsp_i ( router_27_30_to_magia_tile_ni_27_30_rsp ), - .floo_req_i ( router_27_30_to_magia_tile_ni_27_30_req ), - .floo_rsp_o ( magia_tile_ni_27_30_to_router_27_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_27_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[27][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[27][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[27][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[27][31] ), - .id_i ( '{x: 28, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_27_31_to_router_27_31_req ), - .floo_rsp_i ( router_27_31_to_magia_tile_ni_27_31_rsp ), - .floo_req_i ( router_27_31_to_magia_tile_ni_27_31_req ), - .floo_rsp_o ( magia_tile_ni_27_31_to_router_27_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][0] ), - .id_i ( '{x: 29, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_0_to_router_28_0_req ), - .floo_rsp_i ( router_28_0_to_magia_tile_ni_28_0_rsp ), - .floo_req_i ( router_28_0_to_magia_tile_ni_28_0_req ), - .floo_rsp_o ( magia_tile_ni_28_0_to_router_28_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][1] ), - .id_i ( '{x: 29, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_1_to_router_28_1_req ), - .floo_rsp_i ( router_28_1_to_magia_tile_ni_28_1_rsp ), - .floo_req_i ( router_28_1_to_magia_tile_ni_28_1_req ), - .floo_rsp_o ( magia_tile_ni_28_1_to_router_28_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][2] ), - .id_i ( '{x: 29, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_2_to_router_28_2_req ), - .floo_rsp_i ( router_28_2_to_magia_tile_ni_28_2_rsp ), - .floo_req_i ( router_28_2_to_magia_tile_ni_28_2_req ), - .floo_rsp_o ( magia_tile_ni_28_2_to_router_28_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][3] ), - .id_i ( '{x: 29, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_3_to_router_28_3_req ), - .floo_rsp_i ( router_28_3_to_magia_tile_ni_28_3_rsp ), - .floo_req_i ( router_28_3_to_magia_tile_ni_28_3_req ), - .floo_rsp_o ( magia_tile_ni_28_3_to_router_28_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][4] ), - .id_i ( '{x: 29, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_4_to_router_28_4_req ), - .floo_rsp_i ( router_28_4_to_magia_tile_ni_28_4_rsp ), - .floo_req_i ( router_28_4_to_magia_tile_ni_28_4_req ), - .floo_rsp_o ( magia_tile_ni_28_4_to_router_28_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][5] ), - .id_i ( '{x: 29, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_5_to_router_28_5_req ), - .floo_rsp_i ( router_28_5_to_magia_tile_ni_28_5_rsp ), - .floo_req_i ( router_28_5_to_magia_tile_ni_28_5_req ), - .floo_rsp_o ( magia_tile_ni_28_5_to_router_28_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][6] ), - .id_i ( '{x: 29, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_6_to_router_28_6_req ), - .floo_rsp_i ( router_28_6_to_magia_tile_ni_28_6_rsp ), - .floo_req_i ( router_28_6_to_magia_tile_ni_28_6_req ), - .floo_rsp_o ( magia_tile_ni_28_6_to_router_28_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][7] ), - .id_i ( '{x: 29, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_7_to_router_28_7_req ), - .floo_rsp_i ( router_28_7_to_magia_tile_ni_28_7_rsp ), - .floo_req_i ( router_28_7_to_magia_tile_ni_28_7_req ), - .floo_rsp_o ( magia_tile_ni_28_7_to_router_28_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][8] ), - .id_i ( '{x: 29, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_8_to_router_28_8_req ), - .floo_rsp_i ( router_28_8_to_magia_tile_ni_28_8_rsp ), - .floo_req_i ( router_28_8_to_magia_tile_ni_28_8_req ), - .floo_rsp_o ( magia_tile_ni_28_8_to_router_28_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][9] ), - .id_i ( '{x: 29, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_9_to_router_28_9_req ), - .floo_rsp_i ( router_28_9_to_magia_tile_ni_28_9_rsp ), - .floo_req_i ( router_28_9_to_magia_tile_ni_28_9_req ), - .floo_rsp_o ( magia_tile_ni_28_9_to_router_28_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][10] ), - .id_i ( '{x: 29, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_10_to_router_28_10_req ), - .floo_rsp_i ( router_28_10_to_magia_tile_ni_28_10_rsp ), - .floo_req_i ( router_28_10_to_magia_tile_ni_28_10_req ), - .floo_rsp_o ( magia_tile_ni_28_10_to_router_28_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][11] ), - .id_i ( '{x: 29, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_11_to_router_28_11_req ), - .floo_rsp_i ( router_28_11_to_magia_tile_ni_28_11_rsp ), - .floo_req_i ( router_28_11_to_magia_tile_ni_28_11_req ), - .floo_rsp_o ( magia_tile_ni_28_11_to_router_28_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][12] ), - .id_i ( '{x: 29, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_12_to_router_28_12_req ), - .floo_rsp_i ( router_28_12_to_magia_tile_ni_28_12_rsp ), - .floo_req_i ( router_28_12_to_magia_tile_ni_28_12_req ), - .floo_rsp_o ( magia_tile_ni_28_12_to_router_28_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][13] ), - .id_i ( '{x: 29, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_13_to_router_28_13_req ), - .floo_rsp_i ( router_28_13_to_magia_tile_ni_28_13_rsp ), - .floo_req_i ( router_28_13_to_magia_tile_ni_28_13_req ), - .floo_rsp_o ( magia_tile_ni_28_13_to_router_28_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][14] ), - .id_i ( '{x: 29, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_14_to_router_28_14_req ), - .floo_rsp_i ( router_28_14_to_magia_tile_ni_28_14_rsp ), - .floo_req_i ( router_28_14_to_magia_tile_ni_28_14_req ), - .floo_rsp_o ( magia_tile_ni_28_14_to_router_28_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][15] ), - .id_i ( '{x: 29, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_15_to_router_28_15_req ), - .floo_rsp_i ( router_28_15_to_magia_tile_ni_28_15_rsp ), - .floo_req_i ( router_28_15_to_magia_tile_ni_28_15_req ), - .floo_rsp_o ( magia_tile_ni_28_15_to_router_28_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][16] ), - .id_i ( '{x: 29, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_16_to_router_28_16_req ), - .floo_rsp_i ( router_28_16_to_magia_tile_ni_28_16_rsp ), - .floo_req_i ( router_28_16_to_magia_tile_ni_28_16_req ), - .floo_rsp_o ( magia_tile_ni_28_16_to_router_28_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][17] ), - .id_i ( '{x: 29, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_17_to_router_28_17_req ), - .floo_rsp_i ( router_28_17_to_magia_tile_ni_28_17_rsp ), - .floo_req_i ( router_28_17_to_magia_tile_ni_28_17_req ), - .floo_rsp_o ( magia_tile_ni_28_17_to_router_28_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][18] ), - .id_i ( '{x: 29, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_18_to_router_28_18_req ), - .floo_rsp_i ( router_28_18_to_magia_tile_ni_28_18_rsp ), - .floo_req_i ( router_28_18_to_magia_tile_ni_28_18_req ), - .floo_rsp_o ( magia_tile_ni_28_18_to_router_28_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][19] ), - .id_i ( '{x: 29, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_19_to_router_28_19_req ), - .floo_rsp_i ( router_28_19_to_magia_tile_ni_28_19_rsp ), - .floo_req_i ( router_28_19_to_magia_tile_ni_28_19_req ), - .floo_rsp_o ( magia_tile_ni_28_19_to_router_28_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][20] ), - .id_i ( '{x: 29, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_20_to_router_28_20_req ), - .floo_rsp_i ( router_28_20_to_magia_tile_ni_28_20_rsp ), - .floo_req_i ( router_28_20_to_magia_tile_ni_28_20_req ), - .floo_rsp_o ( magia_tile_ni_28_20_to_router_28_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][21] ), - .id_i ( '{x: 29, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_21_to_router_28_21_req ), - .floo_rsp_i ( router_28_21_to_magia_tile_ni_28_21_rsp ), - .floo_req_i ( router_28_21_to_magia_tile_ni_28_21_req ), - .floo_rsp_o ( magia_tile_ni_28_21_to_router_28_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][22] ), - .id_i ( '{x: 29, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_22_to_router_28_22_req ), - .floo_rsp_i ( router_28_22_to_magia_tile_ni_28_22_rsp ), - .floo_req_i ( router_28_22_to_magia_tile_ni_28_22_req ), - .floo_rsp_o ( magia_tile_ni_28_22_to_router_28_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][23] ), - .id_i ( '{x: 29, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_23_to_router_28_23_req ), - .floo_rsp_i ( router_28_23_to_magia_tile_ni_28_23_rsp ), - .floo_req_i ( router_28_23_to_magia_tile_ni_28_23_req ), - .floo_rsp_o ( magia_tile_ni_28_23_to_router_28_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][24] ), - .id_i ( '{x: 29, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_24_to_router_28_24_req ), - .floo_rsp_i ( router_28_24_to_magia_tile_ni_28_24_rsp ), - .floo_req_i ( router_28_24_to_magia_tile_ni_28_24_req ), - .floo_rsp_o ( magia_tile_ni_28_24_to_router_28_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][25] ), - .id_i ( '{x: 29, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_25_to_router_28_25_req ), - .floo_rsp_i ( router_28_25_to_magia_tile_ni_28_25_rsp ), - .floo_req_i ( router_28_25_to_magia_tile_ni_28_25_req ), - .floo_rsp_o ( magia_tile_ni_28_25_to_router_28_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][26] ), - .id_i ( '{x: 29, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_26_to_router_28_26_req ), - .floo_rsp_i ( router_28_26_to_magia_tile_ni_28_26_rsp ), - .floo_req_i ( router_28_26_to_magia_tile_ni_28_26_req ), - .floo_rsp_o ( magia_tile_ni_28_26_to_router_28_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][27] ), - .id_i ( '{x: 29, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_27_to_router_28_27_req ), - .floo_rsp_i ( router_28_27_to_magia_tile_ni_28_27_rsp ), - .floo_req_i ( router_28_27_to_magia_tile_ni_28_27_req ), - .floo_rsp_o ( magia_tile_ni_28_27_to_router_28_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][28] ), - .id_i ( '{x: 29, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_28_to_router_28_28_req ), - .floo_rsp_i ( router_28_28_to_magia_tile_ni_28_28_rsp ), - .floo_req_i ( router_28_28_to_magia_tile_ni_28_28_req ), - .floo_rsp_o ( magia_tile_ni_28_28_to_router_28_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][29] ), - .id_i ( '{x: 29, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_29_to_router_28_29_req ), - .floo_rsp_i ( router_28_29_to_magia_tile_ni_28_29_rsp ), - .floo_req_i ( router_28_29_to_magia_tile_ni_28_29_req ), - .floo_rsp_o ( magia_tile_ni_28_29_to_router_28_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][30] ), - .id_i ( '{x: 29, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_30_to_router_28_30_req ), - .floo_rsp_i ( router_28_30_to_magia_tile_ni_28_30_rsp ), - .floo_req_i ( router_28_30_to_magia_tile_ni_28_30_req ), - .floo_rsp_o ( magia_tile_ni_28_30_to_router_28_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_28_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[28][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[28][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[28][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[28][31] ), - .id_i ( '{x: 29, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_28_31_to_router_28_31_req ), - .floo_rsp_i ( router_28_31_to_magia_tile_ni_28_31_rsp ), - .floo_req_i ( router_28_31_to_magia_tile_ni_28_31_req ), - .floo_rsp_o ( magia_tile_ni_28_31_to_router_28_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][0] ), - .id_i ( '{x: 30, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_0_to_router_29_0_req ), - .floo_rsp_i ( router_29_0_to_magia_tile_ni_29_0_rsp ), - .floo_req_i ( router_29_0_to_magia_tile_ni_29_0_req ), - .floo_rsp_o ( magia_tile_ni_29_0_to_router_29_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][1] ), - .id_i ( '{x: 30, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_1_to_router_29_1_req ), - .floo_rsp_i ( router_29_1_to_magia_tile_ni_29_1_rsp ), - .floo_req_i ( router_29_1_to_magia_tile_ni_29_1_req ), - .floo_rsp_o ( magia_tile_ni_29_1_to_router_29_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][2] ), - .id_i ( '{x: 30, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_2_to_router_29_2_req ), - .floo_rsp_i ( router_29_2_to_magia_tile_ni_29_2_rsp ), - .floo_req_i ( router_29_2_to_magia_tile_ni_29_2_req ), - .floo_rsp_o ( magia_tile_ni_29_2_to_router_29_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][3] ), - .id_i ( '{x: 30, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_3_to_router_29_3_req ), - .floo_rsp_i ( router_29_3_to_magia_tile_ni_29_3_rsp ), - .floo_req_i ( router_29_3_to_magia_tile_ni_29_3_req ), - .floo_rsp_o ( magia_tile_ni_29_3_to_router_29_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][4] ), - .id_i ( '{x: 30, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_4_to_router_29_4_req ), - .floo_rsp_i ( router_29_4_to_magia_tile_ni_29_4_rsp ), - .floo_req_i ( router_29_4_to_magia_tile_ni_29_4_req ), - .floo_rsp_o ( magia_tile_ni_29_4_to_router_29_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][5] ), - .id_i ( '{x: 30, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_5_to_router_29_5_req ), - .floo_rsp_i ( router_29_5_to_magia_tile_ni_29_5_rsp ), - .floo_req_i ( router_29_5_to_magia_tile_ni_29_5_req ), - .floo_rsp_o ( magia_tile_ni_29_5_to_router_29_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][6] ), - .id_i ( '{x: 30, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_6_to_router_29_6_req ), - .floo_rsp_i ( router_29_6_to_magia_tile_ni_29_6_rsp ), - .floo_req_i ( router_29_6_to_magia_tile_ni_29_6_req ), - .floo_rsp_o ( magia_tile_ni_29_6_to_router_29_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][7] ), - .id_i ( '{x: 30, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_7_to_router_29_7_req ), - .floo_rsp_i ( router_29_7_to_magia_tile_ni_29_7_rsp ), - .floo_req_i ( router_29_7_to_magia_tile_ni_29_7_req ), - .floo_rsp_o ( magia_tile_ni_29_7_to_router_29_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][8] ), - .id_i ( '{x: 30, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_8_to_router_29_8_req ), - .floo_rsp_i ( router_29_8_to_magia_tile_ni_29_8_rsp ), - .floo_req_i ( router_29_8_to_magia_tile_ni_29_8_req ), - .floo_rsp_o ( magia_tile_ni_29_8_to_router_29_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][9] ), - .id_i ( '{x: 30, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_9_to_router_29_9_req ), - .floo_rsp_i ( router_29_9_to_magia_tile_ni_29_9_rsp ), - .floo_req_i ( router_29_9_to_magia_tile_ni_29_9_req ), - .floo_rsp_o ( magia_tile_ni_29_9_to_router_29_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][10] ), - .id_i ( '{x: 30, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_10_to_router_29_10_req ), - .floo_rsp_i ( router_29_10_to_magia_tile_ni_29_10_rsp ), - .floo_req_i ( router_29_10_to_magia_tile_ni_29_10_req ), - .floo_rsp_o ( magia_tile_ni_29_10_to_router_29_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][11] ), - .id_i ( '{x: 30, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_11_to_router_29_11_req ), - .floo_rsp_i ( router_29_11_to_magia_tile_ni_29_11_rsp ), - .floo_req_i ( router_29_11_to_magia_tile_ni_29_11_req ), - .floo_rsp_o ( magia_tile_ni_29_11_to_router_29_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][12] ), - .id_i ( '{x: 30, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_12_to_router_29_12_req ), - .floo_rsp_i ( router_29_12_to_magia_tile_ni_29_12_rsp ), - .floo_req_i ( router_29_12_to_magia_tile_ni_29_12_req ), - .floo_rsp_o ( magia_tile_ni_29_12_to_router_29_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][13] ), - .id_i ( '{x: 30, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_13_to_router_29_13_req ), - .floo_rsp_i ( router_29_13_to_magia_tile_ni_29_13_rsp ), - .floo_req_i ( router_29_13_to_magia_tile_ni_29_13_req ), - .floo_rsp_o ( magia_tile_ni_29_13_to_router_29_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][14] ), - .id_i ( '{x: 30, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_14_to_router_29_14_req ), - .floo_rsp_i ( router_29_14_to_magia_tile_ni_29_14_rsp ), - .floo_req_i ( router_29_14_to_magia_tile_ni_29_14_req ), - .floo_rsp_o ( magia_tile_ni_29_14_to_router_29_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][15] ), - .id_i ( '{x: 30, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_15_to_router_29_15_req ), - .floo_rsp_i ( router_29_15_to_magia_tile_ni_29_15_rsp ), - .floo_req_i ( router_29_15_to_magia_tile_ni_29_15_req ), - .floo_rsp_o ( magia_tile_ni_29_15_to_router_29_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][16] ), - .id_i ( '{x: 30, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_16_to_router_29_16_req ), - .floo_rsp_i ( router_29_16_to_magia_tile_ni_29_16_rsp ), - .floo_req_i ( router_29_16_to_magia_tile_ni_29_16_req ), - .floo_rsp_o ( magia_tile_ni_29_16_to_router_29_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][17] ), - .id_i ( '{x: 30, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_17_to_router_29_17_req ), - .floo_rsp_i ( router_29_17_to_magia_tile_ni_29_17_rsp ), - .floo_req_i ( router_29_17_to_magia_tile_ni_29_17_req ), - .floo_rsp_o ( magia_tile_ni_29_17_to_router_29_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][18] ), - .id_i ( '{x: 30, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_18_to_router_29_18_req ), - .floo_rsp_i ( router_29_18_to_magia_tile_ni_29_18_rsp ), - .floo_req_i ( router_29_18_to_magia_tile_ni_29_18_req ), - .floo_rsp_o ( magia_tile_ni_29_18_to_router_29_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][19] ), - .id_i ( '{x: 30, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_19_to_router_29_19_req ), - .floo_rsp_i ( router_29_19_to_magia_tile_ni_29_19_rsp ), - .floo_req_i ( router_29_19_to_magia_tile_ni_29_19_req ), - .floo_rsp_o ( magia_tile_ni_29_19_to_router_29_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][20] ), - .id_i ( '{x: 30, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_20_to_router_29_20_req ), - .floo_rsp_i ( router_29_20_to_magia_tile_ni_29_20_rsp ), - .floo_req_i ( router_29_20_to_magia_tile_ni_29_20_req ), - .floo_rsp_o ( magia_tile_ni_29_20_to_router_29_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][21] ), - .id_i ( '{x: 30, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_21_to_router_29_21_req ), - .floo_rsp_i ( router_29_21_to_magia_tile_ni_29_21_rsp ), - .floo_req_i ( router_29_21_to_magia_tile_ni_29_21_req ), - .floo_rsp_o ( magia_tile_ni_29_21_to_router_29_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][22] ), - .id_i ( '{x: 30, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_22_to_router_29_22_req ), - .floo_rsp_i ( router_29_22_to_magia_tile_ni_29_22_rsp ), - .floo_req_i ( router_29_22_to_magia_tile_ni_29_22_req ), - .floo_rsp_o ( magia_tile_ni_29_22_to_router_29_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][23] ), - .id_i ( '{x: 30, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_23_to_router_29_23_req ), - .floo_rsp_i ( router_29_23_to_magia_tile_ni_29_23_rsp ), - .floo_req_i ( router_29_23_to_magia_tile_ni_29_23_req ), - .floo_rsp_o ( magia_tile_ni_29_23_to_router_29_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][24] ), - .id_i ( '{x: 30, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_24_to_router_29_24_req ), - .floo_rsp_i ( router_29_24_to_magia_tile_ni_29_24_rsp ), - .floo_req_i ( router_29_24_to_magia_tile_ni_29_24_req ), - .floo_rsp_o ( magia_tile_ni_29_24_to_router_29_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][25] ), - .id_i ( '{x: 30, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_25_to_router_29_25_req ), - .floo_rsp_i ( router_29_25_to_magia_tile_ni_29_25_rsp ), - .floo_req_i ( router_29_25_to_magia_tile_ni_29_25_req ), - .floo_rsp_o ( magia_tile_ni_29_25_to_router_29_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][26] ), - .id_i ( '{x: 30, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_26_to_router_29_26_req ), - .floo_rsp_i ( router_29_26_to_magia_tile_ni_29_26_rsp ), - .floo_req_i ( router_29_26_to_magia_tile_ni_29_26_req ), - .floo_rsp_o ( magia_tile_ni_29_26_to_router_29_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][27] ), - .id_i ( '{x: 30, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_27_to_router_29_27_req ), - .floo_rsp_i ( router_29_27_to_magia_tile_ni_29_27_rsp ), - .floo_req_i ( router_29_27_to_magia_tile_ni_29_27_req ), - .floo_rsp_o ( magia_tile_ni_29_27_to_router_29_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][28] ), - .id_i ( '{x: 30, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_28_to_router_29_28_req ), - .floo_rsp_i ( router_29_28_to_magia_tile_ni_29_28_rsp ), - .floo_req_i ( router_29_28_to_magia_tile_ni_29_28_req ), - .floo_rsp_o ( magia_tile_ni_29_28_to_router_29_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][29] ), - .id_i ( '{x: 30, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_29_to_router_29_29_req ), - .floo_rsp_i ( router_29_29_to_magia_tile_ni_29_29_rsp ), - .floo_req_i ( router_29_29_to_magia_tile_ni_29_29_req ), - .floo_rsp_o ( magia_tile_ni_29_29_to_router_29_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][30] ), - .id_i ( '{x: 30, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_30_to_router_29_30_req ), - .floo_rsp_i ( router_29_30_to_magia_tile_ni_29_30_rsp ), - .floo_req_i ( router_29_30_to_magia_tile_ni_29_30_req ), - .floo_rsp_o ( magia_tile_ni_29_30_to_router_29_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_29_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[29][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[29][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[29][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[29][31] ), - .id_i ( '{x: 30, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_29_31_to_router_29_31_req ), - .floo_rsp_i ( router_29_31_to_magia_tile_ni_29_31_rsp ), - .floo_req_i ( router_29_31_to_magia_tile_ni_29_31_req ), - .floo_rsp_o ( magia_tile_ni_29_31_to_router_29_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][0] ), - .id_i ( '{x: 31, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_0_to_router_30_0_req ), - .floo_rsp_i ( router_30_0_to_magia_tile_ni_30_0_rsp ), - .floo_req_i ( router_30_0_to_magia_tile_ni_30_0_req ), - .floo_rsp_o ( magia_tile_ni_30_0_to_router_30_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][1] ), - .id_i ( '{x: 31, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_1_to_router_30_1_req ), - .floo_rsp_i ( router_30_1_to_magia_tile_ni_30_1_rsp ), - .floo_req_i ( router_30_1_to_magia_tile_ni_30_1_req ), - .floo_rsp_o ( magia_tile_ni_30_1_to_router_30_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][2] ), - .id_i ( '{x: 31, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_2_to_router_30_2_req ), - .floo_rsp_i ( router_30_2_to_magia_tile_ni_30_2_rsp ), - .floo_req_i ( router_30_2_to_magia_tile_ni_30_2_req ), - .floo_rsp_o ( magia_tile_ni_30_2_to_router_30_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][3] ), - .id_i ( '{x: 31, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_3_to_router_30_3_req ), - .floo_rsp_i ( router_30_3_to_magia_tile_ni_30_3_rsp ), - .floo_req_i ( router_30_3_to_magia_tile_ni_30_3_req ), - .floo_rsp_o ( magia_tile_ni_30_3_to_router_30_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][4] ), - .id_i ( '{x: 31, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_4_to_router_30_4_req ), - .floo_rsp_i ( router_30_4_to_magia_tile_ni_30_4_rsp ), - .floo_req_i ( router_30_4_to_magia_tile_ni_30_4_req ), - .floo_rsp_o ( magia_tile_ni_30_4_to_router_30_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][5] ), - .id_i ( '{x: 31, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_5_to_router_30_5_req ), - .floo_rsp_i ( router_30_5_to_magia_tile_ni_30_5_rsp ), - .floo_req_i ( router_30_5_to_magia_tile_ni_30_5_req ), - .floo_rsp_o ( magia_tile_ni_30_5_to_router_30_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][6] ), - .id_i ( '{x: 31, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_6_to_router_30_6_req ), - .floo_rsp_i ( router_30_6_to_magia_tile_ni_30_6_rsp ), - .floo_req_i ( router_30_6_to_magia_tile_ni_30_6_req ), - .floo_rsp_o ( magia_tile_ni_30_6_to_router_30_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][7] ), - .id_i ( '{x: 31, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_7_to_router_30_7_req ), - .floo_rsp_i ( router_30_7_to_magia_tile_ni_30_7_rsp ), - .floo_req_i ( router_30_7_to_magia_tile_ni_30_7_req ), - .floo_rsp_o ( magia_tile_ni_30_7_to_router_30_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][8] ), - .id_i ( '{x: 31, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_8_to_router_30_8_req ), - .floo_rsp_i ( router_30_8_to_magia_tile_ni_30_8_rsp ), - .floo_req_i ( router_30_8_to_magia_tile_ni_30_8_req ), - .floo_rsp_o ( magia_tile_ni_30_8_to_router_30_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][9] ), - .id_i ( '{x: 31, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_9_to_router_30_9_req ), - .floo_rsp_i ( router_30_9_to_magia_tile_ni_30_9_rsp ), - .floo_req_i ( router_30_9_to_magia_tile_ni_30_9_req ), - .floo_rsp_o ( magia_tile_ni_30_9_to_router_30_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][10] ), - .id_i ( '{x: 31, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_10_to_router_30_10_req ), - .floo_rsp_i ( router_30_10_to_magia_tile_ni_30_10_rsp ), - .floo_req_i ( router_30_10_to_magia_tile_ni_30_10_req ), - .floo_rsp_o ( magia_tile_ni_30_10_to_router_30_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][11] ), - .id_i ( '{x: 31, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_11_to_router_30_11_req ), - .floo_rsp_i ( router_30_11_to_magia_tile_ni_30_11_rsp ), - .floo_req_i ( router_30_11_to_magia_tile_ni_30_11_req ), - .floo_rsp_o ( magia_tile_ni_30_11_to_router_30_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][12] ), - .id_i ( '{x: 31, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_12_to_router_30_12_req ), - .floo_rsp_i ( router_30_12_to_magia_tile_ni_30_12_rsp ), - .floo_req_i ( router_30_12_to_magia_tile_ni_30_12_req ), - .floo_rsp_o ( magia_tile_ni_30_12_to_router_30_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][13] ), - .id_i ( '{x: 31, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_13_to_router_30_13_req ), - .floo_rsp_i ( router_30_13_to_magia_tile_ni_30_13_rsp ), - .floo_req_i ( router_30_13_to_magia_tile_ni_30_13_req ), - .floo_rsp_o ( magia_tile_ni_30_13_to_router_30_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][14] ), - .id_i ( '{x: 31, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_14_to_router_30_14_req ), - .floo_rsp_i ( router_30_14_to_magia_tile_ni_30_14_rsp ), - .floo_req_i ( router_30_14_to_magia_tile_ni_30_14_req ), - .floo_rsp_o ( magia_tile_ni_30_14_to_router_30_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][15] ), - .id_i ( '{x: 31, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_15_to_router_30_15_req ), - .floo_rsp_i ( router_30_15_to_magia_tile_ni_30_15_rsp ), - .floo_req_i ( router_30_15_to_magia_tile_ni_30_15_req ), - .floo_rsp_o ( magia_tile_ni_30_15_to_router_30_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][16] ), - .id_i ( '{x: 31, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_16_to_router_30_16_req ), - .floo_rsp_i ( router_30_16_to_magia_tile_ni_30_16_rsp ), - .floo_req_i ( router_30_16_to_magia_tile_ni_30_16_req ), - .floo_rsp_o ( magia_tile_ni_30_16_to_router_30_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][17] ), - .id_i ( '{x: 31, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_17_to_router_30_17_req ), - .floo_rsp_i ( router_30_17_to_magia_tile_ni_30_17_rsp ), - .floo_req_i ( router_30_17_to_magia_tile_ni_30_17_req ), - .floo_rsp_o ( magia_tile_ni_30_17_to_router_30_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][18] ), - .id_i ( '{x: 31, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_18_to_router_30_18_req ), - .floo_rsp_i ( router_30_18_to_magia_tile_ni_30_18_rsp ), - .floo_req_i ( router_30_18_to_magia_tile_ni_30_18_req ), - .floo_rsp_o ( magia_tile_ni_30_18_to_router_30_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][19] ), - .id_i ( '{x: 31, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_19_to_router_30_19_req ), - .floo_rsp_i ( router_30_19_to_magia_tile_ni_30_19_rsp ), - .floo_req_i ( router_30_19_to_magia_tile_ni_30_19_req ), - .floo_rsp_o ( magia_tile_ni_30_19_to_router_30_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][20] ), - .id_i ( '{x: 31, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_20_to_router_30_20_req ), - .floo_rsp_i ( router_30_20_to_magia_tile_ni_30_20_rsp ), - .floo_req_i ( router_30_20_to_magia_tile_ni_30_20_req ), - .floo_rsp_o ( magia_tile_ni_30_20_to_router_30_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][21] ), - .id_i ( '{x: 31, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_21_to_router_30_21_req ), - .floo_rsp_i ( router_30_21_to_magia_tile_ni_30_21_rsp ), - .floo_req_i ( router_30_21_to_magia_tile_ni_30_21_req ), - .floo_rsp_o ( magia_tile_ni_30_21_to_router_30_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][22] ), - .id_i ( '{x: 31, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_22_to_router_30_22_req ), - .floo_rsp_i ( router_30_22_to_magia_tile_ni_30_22_rsp ), - .floo_req_i ( router_30_22_to_magia_tile_ni_30_22_req ), - .floo_rsp_o ( magia_tile_ni_30_22_to_router_30_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][23] ), - .id_i ( '{x: 31, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_23_to_router_30_23_req ), - .floo_rsp_i ( router_30_23_to_magia_tile_ni_30_23_rsp ), - .floo_req_i ( router_30_23_to_magia_tile_ni_30_23_req ), - .floo_rsp_o ( magia_tile_ni_30_23_to_router_30_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][24] ), - .id_i ( '{x: 31, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_24_to_router_30_24_req ), - .floo_rsp_i ( router_30_24_to_magia_tile_ni_30_24_rsp ), - .floo_req_i ( router_30_24_to_magia_tile_ni_30_24_req ), - .floo_rsp_o ( magia_tile_ni_30_24_to_router_30_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][25] ), - .id_i ( '{x: 31, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_25_to_router_30_25_req ), - .floo_rsp_i ( router_30_25_to_magia_tile_ni_30_25_rsp ), - .floo_req_i ( router_30_25_to_magia_tile_ni_30_25_req ), - .floo_rsp_o ( magia_tile_ni_30_25_to_router_30_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][26] ), - .id_i ( '{x: 31, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_26_to_router_30_26_req ), - .floo_rsp_i ( router_30_26_to_magia_tile_ni_30_26_rsp ), - .floo_req_i ( router_30_26_to_magia_tile_ni_30_26_req ), - .floo_rsp_o ( magia_tile_ni_30_26_to_router_30_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][27] ), - .id_i ( '{x: 31, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_27_to_router_30_27_req ), - .floo_rsp_i ( router_30_27_to_magia_tile_ni_30_27_rsp ), - .floo_req_i ( router_30_27_to_magia_tile_ni_30_27_req ), - .floo_rsp_o ( magia_tile_ni_30_27_to_router_30_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][28] ), - .id_i ( '{x: 31, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_28_to_router_30_28_req ), - .floo_rsp_i ( router_30_28_to_magia_tile_ni_30_28_rsp ), - .floo_req_i ( router_30_28_to_magia_tile_ni_30_28_req ), - .floo_rsp_o ( magia_tile_ni_30_28_to_router_30_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][29] ), - .id_i ( '{x: 31, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_29_to_router_30_29_req ), - .floo_rsp_i ( router_30_29_to_magia_tile_ni_30_29_rsp ), - .floo_req_i ( router_30_29_to_magia_tile_ni_30_29_req ), - .floo_rsp_o ( magia_tile_ni_30_29_to_router_30_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][30] ), - .id_i ( '{x: 31, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_30_to_router_30_30_req ), - .floo_rsp_i ( router_30_30_to_magia_tile_ni_30_30_rsp ), - .floo_req_i ( router_30_30_to_magia_tile_ni_30_30_req ), - .floo_rsp_o ( magia_tile_ni_30_30_to_router_30_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_30_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[30][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[30][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[30][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[30][31] ), - .id_i ( '{x: 31, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_30_31_to_router_30_31_req ), - .floo_rsp_i ( router_30_31_to_magia_tile_ni_30_31_rsp ), - .floo_req_i ( router_30_31_to_magia_tile_ni_30_31_req ), - .floo_rsp_o ( magia_tile_ni_30_31_to_router_30_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][0] ), - .id_i ( '{x: 32, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_0_to_router_31_0_req ), - .floo_rsp_i ( router_31_0_to_magia_tile_ni_31_0_rsp ), - .floo_req_i ( router_31_0_to_magia_tile_ni_31_0_req ), - .floo_rsp_o ( magia_tile_ni_31_0_to_router_31_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][1] ), - .id_i ( '{x: 32, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_1_to_router_31_1_req ), - .floo_rsp_i ( router_31_1_to_magia_tile_ni_31_1_rsp ), - .floo_req_i ( router_31_1_to_magia_tile_ni_31_1_req ), - .floo_rsp_o ( magia_tile_ni_31_1_to_router_31_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][2] ), - .id_i ( '{x: 32, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_2_to_router_31_2_req ), - .floo_rsp_i ( router_31_2_to_magia_tile_ni_31_2_rsp ), - .floo_req_i ( router_31_2_to_magia_tile_ni_31_2_req ), - .floo_rsp_o ( magia_tile_ni_31_2_to_router_31_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][3] ), - .id_i ( '{x: 32, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_3_to_router_31_3_req ), - .floo_rsp_i ( router_31_3_to_magia_tile_ni_31_3_rsp ), - .floo_req_i ( router_31_3_to_magia_tile_ni_31_3_req ), - .floo_rsp_o ( magia_tile_ni_31_3_to_router_31_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][4] ), - .id_i ( '{x: 32, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_4_to_router_31_4_req ), - .floo_rsp_i ( router_31_4_to_magia_tile_ni_31_4_rsp ), - .floo_req_i ( router_31_4_to_magia_tile_ni_31_4_req ), - .floo_rsp_o ( magia_tile_ni_31_4_to_router_31_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][5] ), - .id_i ( '{x: 32, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_5_to_router_31_5_req ), - .floo_rsp_i ( router_31_5_to_magia_tile_ni_31_5_rsp ), - .floo_req_i ( router_31_5_to_magia_tile_ni_31_5_req ), - .floo_rsp_o ( magia_tile_ni_31_5_to_router_31_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][6] ), - .id_i ( '{x: 32, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_6_to_router_31_6_req ), - .floo_rsp_i ( router_31_6_to_magia_tile_ni_31_6_rsp ), - .floo_req_i ( router_31_6_to_magia_tile_ni_31_6_req ), - .floo_rsp_o ( magia_tile_ni_31_6_to_router_31_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][7] ), - .id_i ( '{x: 32, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_7_to_router_31_7_req ), - .floo_rsp_i ( router_31_7_to_magia_tile_ni_31_7_rsp ), - .floo_req_i ( router_31_7_to_magia_tile_ni_31_7_req ), - .floo_rsp_o ( magia_tile_ni_31_7_to_router_31_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][8] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][8] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][8] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][8] ), - .id_i ( '{x: 32, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_8_to_router_31_8_req ), - .floo_rsp_i ( router_31_8_to_magia_tile_ni_31_8_rsp ), - .floo_req_i ( router_31_8_to_magia_tile_ni_31_8_req ), - .floo_rsp_o ( magia_tile_ni_31_8_to_router_31_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][9] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][9] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][9] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][9] ), - .id_i ( '{x: 32, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_9_to_router_31_9_req ), - .floo_rsp_i ( router_31_9_to_magia_tile_ni_31_9_rsp ), - .floo_req_i ( router_31_9_to_magia_tile_ni_31_9_req ), - .floo_rsp_o ( magia_tile_ni_31_9_to_router_31_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][10] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][10] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][10] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][10] ), - .id_i ( '{x: 32, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_10_to_router_31_10_req ), - .floo_rsp_i ( router_31_10_to_magia_tile_ni_31_10_rsp ), - .floo_req_i ( router_31_10_to_magia_tile_ni_31_10_req ), - .floo_rsp_o ( magia_tile_ni_31_10_to_router_31_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][11] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][11] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][11] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][11] ), - .id_i ( '{x: 32, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_11_to_router_31_11_req ), - .floo_rsp_i ( router_31_11_to_magia_tile_ni_31_11_rsp ), - .floo_req_i ( router_31_11_to_magia_tile_ni_31_11_req ), - .floo_rsp_o ( magia_tile_ni_31_11_to_router_31_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][12] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][12] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][12] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][12] ), - .id_i ( '{x: 32, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_12_to_router_31_12_req ), - .floo_rsp_i ( router_31_12_to_magia_tile_ni_31_12_rsp ), - .floo_req_i ( router_31_12_to_magia_tile_ni_31_12_req ), - .floo_rsp_o ( magia_tile_ni_31_12_to_router_31_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][13] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][13] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][13] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][13] ), - .id_i ( '{x: 32, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_13_to_router_31_13_req ), - .floo_rsp_i ( router_31_13_to_magia_tile_ni_31_13_rsp ), - .floo_req_i ( router_31_13_to_magia_tile_ni_31_13_req ), - .floo_rsp_o ( magia_tile_ni_31_13_to_router_31_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][14] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][14] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][14] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][14] ), - .id_i ( '{x: 32, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_14_to_router_31_14_req ), - .floo_rsp_i ( router_31_14_to_magia_tile_ni_31_14_rsp ), - .floo_req_i ( router_31_14_to_magia_tile_ni_31_14_req ), - .floo_rsp_o ( magia_tile_ni_31_14_to_router_31_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][15] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][15] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][15] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][15] ), - .id_i ( '{x: 32, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_15_to_router_31_15_req ), - .floo_rsp_i ( router_31_15_to_magia_tile_ni_31_15_rsp ), - .floo_req_i ( router_31_15_to_magia_tile_ni_31_15_req ), - .floo_rsp_o ( magia_tile_ni_31_15_to_router_31_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][16] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][16] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][16] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][16] ), - .id_i ( '{x: 32, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_16_to_router_31_16_req ), - .floo_rsp_i ( router_31_16_to_magia_tile_ni_31_16_rsp ), - .floo_req_i ( router_31_16_to_magia_tile_ni_31_16_req ), - .floo_rsp_o ( magia_tile_ni_31_16_to_router_31_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][17] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][17] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][17] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][17] ), - .id_i ( '{x: 32, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_17_to_router_31_17_req ), - .floo_rsp_i ( router_31_17_to_magia_tile_ni_31_17_rsp ), - .floo_req_i ( router_31_17_to_magia_tile_ni_31_17_req ), - .floo_rsp_o ( magia_tile_ni_31_17_to_router_31_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][18] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][18] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][18] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][18] ), - .id_i ( '{x: 32, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_18_to_router_31_18_req ), - .floo_rsp_i ( router_31_18_to_magia_tile_ni_31_18_rsp ), - .floo_req_i ( router_31_18_to_magia_tile_ni_31_18_req ), - .floo_rsp_o ( magia_tile_ni_31_18_to_router_31_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][19] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][19] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][19] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][19] ), - .id_i ( '{x: 32, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_19_to_router_31_19_req ), - .floo_rsp_i ( router_31_19_to_magia_tile_ni_31_19_rsp ), - .floo_req_i ( router_31_19_to_magia_tile_ni_31_19_req ), - .floo_rsp_o ( magia_tile_ni_31_19_to_router_31_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][20] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][20] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][20] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][20] ), - .id_i ( '{x: 32, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_20_to_router_31_20_req ), - .floo_rsp_i ( router_31_20_to_magia_tile_ni_31_20_rsp ), - .floo_req_i ( router_31_20_to_magia_tile_ni_31_20_req ), - .floo_rsp_o ( magia_tile_ni_31_20_to_router_31_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][21] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][21] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][21] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][21] ), - .id_i ( '{x: 32, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_21_to_router_31_21_req ), - .floo_rsp_i ( router_31_21_to_magia_tile_ni_31_21_rsp ), - .floo_req_i ( router_31_21_to_magia_tile_ni_31_21_req ), - .floo_rsp_o ( magia_tile_ni_31_21_to_router_31_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][22] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][22] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][22] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][22] ), - .id_i ( '{x: 32, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_22_to_router_31_22_req ), - .floo_rsp_i ( router_31_22_to_magia_tile_ni_31_22_rsp ), - .floo_req_i ( router_31_22_to_magia_tile_ni_31_22_req ), - .floo_rsp_o ( magia_tile_ni_31_22_to_router_31_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][23] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][23] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][23] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][23] ), - .id_i ( '{x: 32, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_23_to_router_31_23_req ), - .floo_rsp_i ( router_31_23_to_magia_tile_ni_31_23_rsp ), - .floo_req_i ( router_31_23_to_magia_tile_ni_31_23_req ), - .floo_rsp_o ( magia_tile_ni_31_23_to_router_31_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][24] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][24] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][24] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][24] ), - .id_i ( '{x: 32, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_24_to_router_31_24_req ), - .floo_rsp_i ( router_31_24_to_magia_tile_ni_31_24_rsp ), - .floo_req_i ( router_31_24_to_magia_tile_ni_31_24_req ), - .floo_rsp_o ( magia_tile_ni_31_24_to_router_31_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][25] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][25] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][25] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][25] ), - .id_i ( '{x: 32, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_25_to_router_31_25_req ), - .floo_rsp_i ( router_31_25_to_magia_tile_ni_31_25_rsp ), - .floo_req_i ( router_31_25_to_magia_tile_ni_31_25_req ), - .floo_rsp_o ( magia_tile_ni_31_25_to_router_31_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][26] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][26] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][26] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][26] ), - .id_i ( '{x: 32, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_26_to_router_31_26_req ), - .floo_rsp_i ( router_31_26_to_magia_tile_ni_31_26_rsp ), - .floo_req_i ( router_31_26_to_magia_tile_ni_31_26_req ), - .floo_rsp_o ( magia_tile_ni_31_26_to_router_31_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][27] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][27] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][27] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][27] ), - .id_i ( '{x: 32, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_27_to_router_31_27_req ), - .floo_rsp_i ( router_31_27_to_magia_tile_ni_31_27_rsp ), - .floo_req_i ( router_31_27_to_magia_tile_ni_31_27_req ), - .floo_rsp_o ( magia_tile_ni_31_27_to_router_31_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][28] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][28] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][28] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][28] ), - .id_i ( '{x: 32, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_28_to_router_31_28_req ), - .floo_rsp_i ( router_31_28_to_magia_tile_ni_31_28_rsp ), - .floo_req_i ( router_31_28_to_magia_tile_ni_31_28_req ), - .floo_rsp_o ( magia_tile_ni_31_28_to_router_31_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][29] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][29] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][29] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][29] ), - .id_i ( '{x: 32, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_29_to_router_31_29_req ), - .floo_rsp_i ( router_31_29_to_magia_tile_ni_31_29_rsp ), - .floo_req_i ( router_31_29_to_magia_tile_ni_31_29_req ), - .floo_rsp_o ( magia_tile_ni_31_29_to_router_31_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][30] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][30] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][30] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][30] ), - .id_i ( '{x: 32, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_30_to_router_31_30_req ), - .floo_rsp_i ( router_31_30_to_magia_tile_ni_31_30_rsp ), - .floo_req_i ( router_31_30_to_magia_tile_ni_31_30_req ), - .floo_rsp_o ( magia_tile_ni_31_30_to_router_31_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_31_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[31][31] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[31][31] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[31][31] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[31][31] ), - .id_i ( '{x: 32, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_31_31_to_router_31_31_req ), - .floo_rsp_i ( router_31_31_to_magia_tile_ni_31_31_rsp ), - .floo_req_i ( router_31_31_to_magia_tile_ni_31_31_req ), - .floo_rsp_o ( magia_tile_ni_31_31_to_router_31_31_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[0] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[0] ), - .id_i ( '{x: 0, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_L2_ni_0_rsp ), - .floo_req_i ( router_0_0_to_L2_ni_0_req ), - .floo_rsp_o ( L2_ni_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[1] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[1] ), - .id_i ( '{x: 0, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_L2_ni_1_rsp ), - .floo_req_i ( router_0_1_to_L2_ni_1_req ), - .floo_rsp_o ( L2_ni_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[2] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[2] ), - .id_i ( '{x: 0, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_L2_ni_2_rsp ), - .floo_req_i ( router_0_2_to_L2_ni_2_req ), - .floo_rsp_o ( L2_ni_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[3] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[3] ), - .id_i ( '{x: 0, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_L2_ni_3_rsp ), - .floo_req_i ( router_0_3_to_L2_ni_3_req ), - .floo_rsp_o ( L2_ni_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[4] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[4] ), - .id_i ( '{x: 0, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_L2_ni_4_rsp ), - .floo_req_i ( router_0_4_to_L2_ni_4_req ), - .floo_rsp_o ( L2_ni_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[5] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[5] ), - .id_i ( '{x: 0, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_L2_ni_5_rsp ), - .floo_req_i ( router_0_5_to_L2_ni_5_req ), - .floo_rsp_o ( L2_ni_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[6] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[6] ), - .id_i ( '{x: 0, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_L2_ni_6_rsp ), - .floo_req_i ( router_0_6_to_L2_ni_6_req ), - .floo_rsp_o ( L2_ni_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[7] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[7] ), - .id_i ( '{x: 0, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_L2_ni_7_rsp ), - .floo_req_i ( router_0_7_to_L2_ni_7_req ), - .floo_rsp_o ( L2_ni_7_to_router_0_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[8] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[8] ), - .id_i ( '{x: 0, y: 8, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_8_to_router_0_8_req ), - .floo_rsp_i ( router_0_8_to_L2_ni_8_rsp ), - .floo_req_i ( router_0_8_to_L2_ni_8_req ), - .floo_rsp_o ( L2_ni_8_to_router_0_8_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[9] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[9] ), - .id_i ( '{x: 0, y: 9, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_9_to_router_0_9_req ), - .floo_rsp_i ( router_0_9_to_L2_ni_9_rsp ), - .floo_req_i ( router_0_9_to_L2_ni_9_req ), - .floo_rsp_o ( L2_ni_9_to_router_0_9_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[10] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[10] ), - .id_i ( '{x: 0, y: 10, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_10_to_router_0_10_req ), - .floo_rsp_i ( router_0_10_to_L2_ni_10_rsp ), - .floo_req_i ( router_0_10_to_L2_ni_10_req ), - .floo_rsp_o ( L2_ni_10_to_router_0_10_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[11] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[11] ), - .id_i ( '{x: 0, y: 11, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_11_to_router_0_11_req ), - .floo_rsp_i ( router_0_11_to_L2_ni_11_rsp ), - .floo_req_i ( router_0_11_to_L2_ni_11_req ), - .floo_rsp_o ( L2_ni_11_to_router_0_11_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[12] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[12] ), - .id_i ( '{x: 0, y: 12, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_12_to_router_0_12_req ), - .floo_rsp_i ( router_0_12_to_L2_ni_12_rsp ), - .floo_req_i ( router_0_12_to_L2_ni_12_req ), - .floo_rsp_o ( L2_ni_12_to_router_0_12_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[13] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[13] ), - .id_i ( '{x: 0, y: 13, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_13_to_router_0_13_req ), - .floo_rsp_i ( router_0_13_to_L2_ni_13_rsp ), - .floo_req_i ( router_0_13_to_L2_ni_13_req ), - .floo_rsp_o ( L2_ni_13_to_router_0_13_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[14] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[14] ), - .id_i ( '{x: 0, y: 14, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_14_to_router_0_14_req ), - .floo_rsp_i ( router_0_14_to_L2_ni_14_rsp ), - .floo_req_i ( router_0_14_to_L2_ni_14_req ), - .floo_rsp_o ( L2_ni_14_to_router_0_14_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[15] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[15] ), - .id_i ( '{x: 0, y: 15, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_15_to_router_0_15_req ), - .floo_rsp_i ( router_0_15_to_L2_ni_15_rsp ), - .floo_req_i ( router_0_15_to_L2_ni_15_req ), - .floo_rsp_o ( L2_ni_15_to_router_0_15_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[16] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[16] ), - .id_i ( '{x: 0, y: 16, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_16_to_router_0_16_req ), - .floo_rsp_i ( router_0_16_to_L2_ni_16_rsp ), - .floo_req_i ( router_0_16_to_L2_ni_16_req ), - .floo_rsp_o ( L2_ni_16_to_router_0_16_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[17] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[17] ), - .id_i ( '{x: 0, y: 17, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_17_to_router_0_17_req ), - .floo_rsp_i ( router_0_17_to_L2_ni_17_rsp ), - .floo_req_i ( router_0_17_to_L2_ni_17_req ), - .floo_rsp_o ( L2_ni_17_to_router_0_17_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[18] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[18] ), - .id_i ( '{x: 0, y: 18, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_18_to_router_0_18_req ), - .floo_rsp_i ( router_0_18_to_L2_ni_18_rsp ), - .floo_req_i ( router_0_18_to_L2_ni_18_req ), - .floo_rsp_o ( L2_ni_18_to_router_0_18_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[19] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[19] ), - .id_i ( '{x: 0, y: 19, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_19_to_router_0_19_req ), - .floo_rsp_i ( router_0_19_to_L2_ni_19_rsp ), - .floo_req_i ( router_0_19_to_L2_ni_19_req ), - .floo_rsp_o ( L2_ni_19_to_router_0_19_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[20] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[20] ), - .id_i ( '{x: 0, y: 20, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_20_to_router_0_20_req ), - .floo_rsp_i ( router_0_20_to_L2_ni_20_rsp ), - .floo_req_i ( router_0_20_to_L2_ni_20_req ), - .floo_rsp_o ( L2_ni_20_to_router_0_20_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[21] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[21] ), - .id_i ( '{x: 0, y: 21, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_21_to_router_0_21_req ), - .floo_rsp_i ( router_0_21_to_L2_ni_21_rsp ), - .floo_req_i ( router_0_21_to_L2_ni_21_req ), - .floo_rsp_o ( L2_ni_21_to_router_0_21_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[22] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[22] ), - .id_i ( '{x: 0, y: 22, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_22_to_router_0_22_req ), - .floo_rsp_i ( router_0_22_to_L2_ni_22_rsp ), - .floo_req_i ( router_0_22_to_L2_ni_22_req ), - .floo_rsp_o ( L2_ni_22_to_router_0_22_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[23] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[23] ), - .id_i ( '{x: 0, y: 23, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_23_to_router_0_23_req ), - .floo_rsp_i ( router_0_23_to_L2_ni_23_rsp ), - .floo_req_i ( router_0_23_to_L2_ni_23_req ), - .floo_rsp_o ( L2_ni_23_to_router_0_23_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[24] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[24] ), - .id_i ( '{x: 0, y: 24, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_24_to_router_0_24_req ), - .floo_rsp_i ( router_0_24_to_L2_ni_24_rsp ), - .floo_req_i ( router_0_24_to_L2_ni_24_req ), - .floo_rsp_o ( L2_ni_24_to_router_0_24_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[25] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[25] ), - .id_i ( '{x: 0, y: 25, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_25_to_router_0_25_req ), - .floo_rsp_i ( router_0_25_to_L2_ni_25_rsp ), - .floo_req_i ( router_0_25_to_L2_ni_25_req ), - .floo_rsp_o ( L2_ni_25_to_router_0_25_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[26] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[26] ), - .id_i ( '{x: 0, y: 26, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_26_to_router_0_26_req ), - .floo_rsp_i ( router_0_26_to_L2_ni_26_rsp ), - .floo_req_i ( router_0_26_to_L2_ni_26_req ), - .floo_rsp_o ( L2_ni_26_to_router_0_26_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[27] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[27] ), - .id_i ( '{x: 0, y: 27, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_27_to_router_0_27_req ), - .floo_rsp_i ( router_0_27_to_L2_ni_27_rsp ), - .floo_req_i ( router_0_27_to_L2_ni_27_req ), - .floo_rsp_o ( L2_ni_27_to_router_0_27_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[28] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[28] ), - .id_i ( '{x: 0, y: 28, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_28_to_router_0_28_req ), - .floo_rsp_i ( router_0_28_to_L2_ni_28_rsp ), - .floo_req_i ( router_0_28_to_L2_ni_28_req ), - .floo_rsp_o ( L2_ni_28_to_router_0_28_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[29] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[29] ), - .id_i ( '{x: 0, y: 29, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_29_to_router_0_29_req ), - .floo_rsp_i ( router_0_29_to_L2_ni_29_rsp ), - .floo_req_i ( router_0_29_to_L2_ni_29_req ), - .floo_rsp_o ( L2_ni_29_to_router_0_29_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[30] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[30] ), - .id_i ( '{x: 0, y: 30, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_30_to_router_0_30_req ), - .floo_rsp_i ( router_0_30_to_L2_ni_30_rsp ), - .floo_req_i ( router_0_30_to_L2_ni_30_req ), - .floo_rsp_o ( L2_ni_30_to_router_0_30_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[31] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[31] ), - .id_i ( '{x: 0, y: 31, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_31_to_router_0_31_req ), - .floo_rsp_i ( router_0_31_to_L2_ni_31_rsp ), - .floo_req_i ( router_0_31_to_L2_ni_31_req ), - .floo_rsp_o ( L2_ni_31_to_router_0_31_rsp ) -); - - -floo_req_t [4:0] router_0_0_req_in; -floo_rsp_t [4:0] router_0_0_rsp_out; -floo_req_t [4:0] router_0_0_req_out; -floo_rsp_t [4:0] router_0_0_rsp_in; - - assign router_0_0_req_in[0] = router_0_1_to_router_0_0_req; - assign router_0_0_req_in[1] = router_1_0_to_router_0_0_req; - assign router_0_0_req_in[2] = '0; - assign router_0_0_req_in[3] = L2_ni_0_to_router_0_0_req; - assign router_0_0_req_in[4] = magia_tile_ni_0_0_to_router_0_0_req; - - assign router_0_0_to_router_0_1_rsp = router_0_0_rsp_out[0]; - assign router_0_0_to_router_1_0_rsp = router_0_0_rsp_out[1]; - assign router_0_0_to_L2_ni_0_rsp = router_0_0_rsp_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_rsp = router_0_0_rsp_out[4]; - - assign router_0_0_to_router_0_1_req = router_0_0_req_out[0]; - assign router_0_0_to_router_1_0_req = router_0_0_req_out[1]; - assign router_0_0_to_L2_ni_0_req = router_0_0_req_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_req = router_0_0_req_out[4]; - - assign router_0_0_rsp_in[0] = router_0_1_to_router_0_0_rsp; - assign router_0_0_rsp_in[1] = router_1_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[2] = '0; - assign router_0_0_rsp_in[3] = L2_ni_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[4] = magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_0_req_in), - .floo_rsp_o (router_0_0_rsp_out), - .floo_req_o (router_0_0_req_out), - .floo_rsp_i (router_0_0_rsp_in) -); - - -floo_req_t [4:0] router_0_1_req_in; -floo_rsp_t [4:0] router_0_1_rsp_out; -floo_req_t [4:0] router_0_1_req_out; -floo_rsp_t [4:0] router_0_1_rsp_in; - - assign router_0_1_req_in[0] = router_0_2_to_router_0_1_req; - assign router_0_1_req_in[1] = router_1_1_to_router_0_1_req; - assign router_0_1_req_in[2] = router_0_0_to_router_0_1_req; - assign router_0_1_req_in[3] = L2_ni_1_to_router_0_1_req; - assign router_0_1_req_in[4] = magia_tile_ni_0_1_to_router_0_1_req; - - assign router_0_1_to_router_0_2_rsp = router_0_1_rsp_out[0]; - assign router_0_1_to_router_1_1_rsp = router_0_1_rsp_out[1]; - assign router_0_1_to_router_0_0_rsp = router_0_1_rsp_out[2]; - assign router_0_1_to_L2_ni_1_rsp = router_0_1_rsp_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_rsp = router_0_1_rsp_out[4]; - - assign router_0_1_to_router_0_2_req = router_0_1_req_out[0]; - assign router_0_1_to_router_1_1_req = router_0_1_req_out[1]; - assign router_0_1_to_router_0_0_req = router_0_1_req_out[2]; - assign router_0_1_to_L2_ni_1_req = router_0_1_req_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_req = router_0_1_req_out[4]; - - assign router_0_1_rsp_in[0] = router_0_2_to_router_0_1_rsp; - assign router_0_1_rsp_in[1] = router_1_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[2] = router_0_0_to_router_0_1_rsp; - assign router_0_1_rsp_in[3] = L2_ni_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[4] = magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_1_req_in), - .floo_rsp_o (router_0_1_rsp_out), - .floo_req_o (router_0_1_req_out), - .floo_rsp_i (router_0_1_rsp_in) -); - - -floo_req_t [4:0] router_0_2_req_in; -floo_rsp_t [4:0] router_0_2_rsp_out; -floo_req_t [4:0] router_0_2_req_out; -floo_rsp_t [4:0] router_0_2_rsp_in; - - assign router_0_2_req_in[0] = router_0_3_to_router_0_2_req; - assign router_0_2_req_in[1] = router_1_2_to_router_0_2_req; - assign router_0_2_req_in[2] = router_0_1_to_router_0_2_req; - assign router_0_2_req_in[3] = L2_ni_2_to_router_0_2_req; - assign router_0_2_req_in[4] = magia_tile_ni_0_2_to_router_0_2_req; - - assign router_0_2_to_router_0_3_rsp = router_0_2_rsp_out[0]; - assign router_0_2_to_router_1_2_rsp = router_0_2_rsp_out[1]; - assign router_0_2_to_router_0_1_rsp = router_0_2_rsp_out[2]; - assign router_0_2_to_L2_ni_2_rsp = router_0_2_rsp_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_rsp = router_0_2_rsp_out[4]; - - assign router_0_2_to_router_0_3_req = router_0_2_req_out[0]; - assign router_0_2_to_router_1_2_req = router_0_2_req_out[1]; - assign router_0_2_to_router_0_1_req = router_0_2_req_out[2]; - assign router_0_2_to_L2_ni_2_req = router_0_2_req_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_req = router_0_2_req_out[4]; - - assign router_0_2_rsp_in[0] = router_0_3_to_router_0_2_rsp; - assign router_0_2_rsp_in[1] = router_1_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[2] = router_0_1_to_router_0_2_rsp; - assign router_0_2_rsp_in[3] = L2_ni_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[4] = magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_2_req_in), - .floo_rsp_o (router_0_2_rsp_out), - .floo_req_o (router_0_2_req_out), - .floo_rsp_i (router_0_2_rsp_in) -); - - -floo_req_t [4:0] router_0_3_req_in; -floo_rsp_t [4:0] router_0_3_rsp_out; -floo_req_t [4:0] router_0_3_req_out; -floo_rsp_t [4:0] router_0_3_rsp_in; - - assign router_0_3_req_in[0] = router_0_4_to_router_0_3_req; - assign router_0_3_req_in[1] = router_1_3_to_router_0_3_req; - assign router_0_3_req_in[2] = router_0_2_to_router_0_3_req; - assign router_0_3_req_in[3] = L2_ni_3_to_router_0_3_req; - assign router_0_3_req_in[4] = magia_tile_ni_0_3_to_router_0_3_req; - - assign router_0_3_to_router_0_4_rsp = router_0_3_rsp_out[0]; - assign router_0_3_to_router_1_3_rsp = router_0_3_rsp_out[1]; - assign router_0_3_to_router_0_2_rsp = router_0_3_rsp_out[2]; - assign router_0_3_to_L2_ni_3_rsp = router_0_3_rsp_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_rsp = router_0_3_rsp_out[4]; - - assign router_0_3_to_router_0_4_req = router_0_3_req_out[0]; - assign router_0_3_to_router_1_3_req = router_0_3_req_out[1]; - assign router_0_3_to_router_0_2_req = router_0_3_req_out[2]; - assign router_0_3_to_L2_ni_3_req = router_0_3_req_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_req = router_0_3_req_out[4]; - - assign router_0_3_rsp_in[0] = router_0_4_to_router_0_3_rsp; - assign router_0_3_rsp_in[1] = router_1_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[2] = router_0_2_to_router_0_3_rsp; - assign router_0_3_rsp_in[3] = L2_ni_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[4] = magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_3_req_in), - .floo_rsp_o (router_0_3_rsp_out), - .floo_req_o (router_0_3_req_out), - .floo_rsp_i (router_0_3_rsp_in) -); - - -floo_req_t [4:0] router_0_4_req_in; -floo_rsp_t [4:0] router_0_4_rsp_out; -floo_req_t [4:0] router_0_4_req_out; -floo_rsp_t [4:0] router_0_4_rsp_in; - - assign router_0_4_req_in[0] = router_0_5_to_router_0_4_req; - assign router_0_4_req_in[1] = router_1_4_to_router_0_4_req; - assign router_0_4_req_in[2] = router_0_3_to_router_0_4_req; - assign router_0_4_req_in[3] = L2_ni_4_to_router_0_4_req; - assign router_0_4_req_in[4] = magia_tile_ni_0_4_to_router_0_4_req; - - assign router_0_4_to_router_0_5_rsp = router_0_4_rsp_out[0]; - assign router_0_4_to_router_1_4_rsp = router_0_4_rsp_out[1]; - assign router_0_4_to_router_0_3_rsp = router_0_4_rsp_out[2]; - assign router_0_4_to_L2_ni_4_rsp = router_0_4_rsp_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_rsp = router_0_4_rsp_out[4]; - - assign router_0_4_to_router_0_5_req = router_0_4_req_out[0]; - assign router_0_4_to_router_1_4_req = router_0_4_req_out[1]; - assign router_0_4_to_router_0_3_req = router_0_4_req_out[2]; - assign router_0_4_to_L2_ni_4_req = router_0_4_req_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_req = router_0_4_req_out[4]; - - assign router_0_4_rsp_in[0] = router_0_5_to_router_0_4_rsp; - assign router_0_4_rsp_in[1] = router_1_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[2] = router_0_3_to_router_0_4_rsp; - assign router_0_4_rsp_in[3] = L2_ni_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[4] = magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_4_req_in), - .floo_rsp_o (router_0_4_rsp_out), - .floo_req_o (router_0_4_req_out), - .floo_rsp_i (router_0_4_rsp_in) -); - - -floo_req_t [4:0] router_0_5_req_in; -floo_rsp_t [4:0] router_0_5_rsp_out; -floo_req_t [4:0] router_0_5_req_out; -floo_rsp_t [4:0] router_0_5_rsp_in; - - assign router_0_5_req_in[0] = router_0_6_to_router_0_5_req; - assign router_0_5_req_in[1] = router_1_5_to_router_0_5_req; - assign router_0_5_req_in[2] = router_0_4_to_router_0_5_req; - assign router_0_5_req_in[3] = L2_ni_5_to_router_0_5_req; - assign router_0_5_req_in[4] = magia_tile_ni_0_5_to_router_0_5_req; - - assign router_0_5_to_router_0_6_rsp = router_0_5_rsp_out[0]; - assign router_0_5_to_router_1_5_rsp = router_0_5_rsp_out[1]; - assign router_0_5_to_router_0_4_rsp = router_0_5_rsp_out[2]; - assign router_0_5_to_L2_ni_5_rsp = router_0_5_rsp_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_rsp = router_0_5_rsp_out[4]; - - assign router_0_5_to_router_0_6_req = router_0_5_req_out[0]; - assign router_0_5_to_router_1_5_req = router_0_5_req_out[1]; - assign router_0_5_to_router_0_4_req = router_0_5_req_out[2]; - assign router_0_5_to_L2_ni_5_req = router_0_5_req_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_req = router_0_5_req_out[4]; - - assign router_0_5_rsp_in[0] = router_0_6_to_router_0_5_rsp; - assign router_0_5_rsp_in[1] = router_1_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[2] = router_0_4_to_router_0_5_rsp; - assign router_0_5_rsp_in[3] = L2_ni_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[4] = magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_5_req_in), - .floo_rsp_o (router_0_5_rsp_out), - .floo_req_o (router_0_5_req_out), - .floo_rsp_i (router_0_5_rsp_in) -); - - -floo_req_t [4:0] router_0_6_req_in; -floo_rsp_t [4:0] router_0_6_rsp_out; -floo_req_t [4:0] router_0_6_req_out; -floo_rsp_t [4:0] router_0_6_rsp_in; - - assign router_0_6_req_in[0] = router_0_7_to_router_0_6_req; - assign router_0_6_req_in[1] = router_1_6_to_router_0_6_req; - assign router_0_6_req_in[2] = router_0_5_to_router_0_6_req; - assign router_0_6_req_in[3] = L2_ni_6_to_router_0_6_req; - assign router_0_6_req_in[4] = magia_tile_ni_0_6_to_router_0_6_req; - - assign router_0_6_to_router_0_7_rsp = router_0_6_rsp_out[0]; - assign router_0_6_to_router_1_6_rsp = router_0_6_rsp_out[1]; - assign router_0_6_to_router_0_5_rsp = router_0_6_rsp_out[2]; - assign router_0_6_to_L2_ni_6_rsp = router_0_6_rsp_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_rsp = router_0_6_rsp_out[4]; - - assign router_0_6_to_router_0_7_req = router_0_6_req_out[0]; - assign router_0_6_to_router_1_6_req = router_0_6_req_out[1]; - assign router_0_6_to_router_0_5_req = router_0_6_req_out[2]; - assign router_0_6_to_L2_ni_6_req = router_0_6_req_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_req = router_0_6_req_out[4]; - - assign router_0_6_rsp_in[0] = router_0_7_to_router_0_6_rsp; - assign router_0_6_rsp_in[1] = router_1_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[2] = router_0_5_to_router_0_6_rsp; - assign router_0_6_rsp_in[3] = L2_ni_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[4] = magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_6_req_in), - .floo_rsp_o (router_0_6_rsp_out), - .floo_req_o (router_0_6_req_out), - .floo_rsp_i (router_0_6_rsp_in) -); - - -floo_req_t [4:0] router_0_7_req_in; -floo_rsp_t [4:0] router_0_7_rsp_out; -floo_req_t [4:0] router_0_7_req_out; -floo_rsp_t [4:0] router_0_7_rsp_in; - - assign router_0_7_req_in[0] = router_0_8_to_router_0_7_req; - assign router_0_7_req_in[1] = router_1_7_to_router_0_7_req; - assign router_0_7_req_in[2] = router_0_6_to_router_0_7_req; - assign router_0_7_req_in[3] = L2_ni_7_to_router_0_7_req; - assign router_0_7_req_in[4] = magia_tile_ni_0_7_to_router_0_7_req; - - assign router_0_7_to_router_0_8_rsp = router_0_7_rsp_out[0]; - assign router_0_7_to_router_1_7_rsp = router_0_7_rsp_out[1]; - assign router_0_7_to_router_0_6_rsp = router_0_7_rsp_out[2]; - assign router_0_7_to_L2_ni_7_rsp = router_0_7_rsp_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_rsp = router_0_7_rsp_out[4]; - - assign router_0_7_to_router_0_8_req = router_0_7_req_out[0]; - assign router_0_7_to_router_1_7_req = router_0_7_req_out[1]; - assign router_0_7_to_router_0_6_req = router_0_7_req_out[2]; - assign router_0_7_to_L2_ni_7_req = router_0_7_req_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_req = router_0_7_req_out[4]; - - assign router_0_7_rsp_in[0] = router_0_8_to_router_0_7_rsp; - assign router_0_7_rsp_in[1] = router_1_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[2] = router_0_6_to_router_0_7_rsp; - assign router_0_7_rsp_in[3] = L2_ni_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[4] = magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_7_req_in), - .floo_rsp_o (router_0_7_rsp_out), - .floo_req_o (router_0_7_req_out), - .floo_rsp_i (router_0_7_rsp_in) -); - - -floo_req_t [4:0] router_0_8_req_in; -floo_rsp_t [4:0] router_0_8_rsp_out; -floo_req_t [4:0] router_0_8_req_out; -floo_rsp_t [4:0] router_0_8_rsp_in; - - assign router_0_8_req_in[0] = router_0_9_to_router_0_8_req; - assign router_0_8_req_in[1] = router_1_8_to_router_0_8_req; - assign router_0_8_req_in[2] = router_0_7_to_router_0_8_req; - assign router_0_8_req_in[3] = L2_ni_8_to_router_0_8_req; - assign router_0_8_req_in[4] = magia_tile_ni_0_8_to_router_0_8_req; - - assign router_0_8_to_router_0_9_rsp = router_0_8_rsp_out[0]; - assign router_0_8_to_router_1_8_rsp = router_0_8_rsp_out[1]; - assign router_0_8_to_router_0_7_rsp = router_0_8_rsp_out[2]; - assign router_0_8_to_L2_ni_8_rsp = router_0_8_rsp_out[3]; - assign router_0_8_to_magia_tile_ni_0_8_rsp = router_0_8_rsp_out[4]; - - assign router_0_8_to_router_0_9_req = router_0_8_req_out[0]; - assign router_0_8_to_router_1_8_req = router_0_8_req_out[1]; - assign router_0_8_to_router_0_7_req = router_0_8_req_out[2]; - assign router_0_8_to_L2_ni_8_req = router_0_8_req_out[3]; - assign router_0_8_to_magia_tile_ni_0_8_req = router_0_8_req_out[4]; - - assign router_0_8_rsp_in[0] = router_0_9_to_router_0_8_rsp; - assign router_0_8_rsp_in[1] = router_1_8_to_router_0_8_rsp; - assign router_0_8_rsp_in[2] = router_0_7_to_router_0_8_rsp; - assign router_0_8_rsp_in[3] = L2_ni_8_to_router_0_8_rsp; - assign router_0_8_rsp_in[4] = magia_tile_ni_0_8_to_router_0_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_8_req_in), - .floo_rsp_o (router_0_8_rsp_out), - .floo_req_o (router_0_8_req_out), - .floo_rsp_i (router_0_8_rsp_in) -); - - -floo_req_t [4:0] router_0_9_req_in; -floo_rsp_t [4:0] router_0_9_rsp_out; -floo_req_t [4:0] router_0_9_req_out; -floo_rsp_t [4:0] router_0_9_rsp_in; - - assign router_0_9_req_in[0] = router_0_10_to_router_0_9_req; - assign router_0_9_req_in[1] = router_1_9_to_router_0_9_req; - assign router_0_9_req_in[2] = router_0_8_to_router_0_9_req; - assign router_0_9_req_in[3] = L2_ni_9_to_router_0_9_req; - assign router_0_9_req_in[4] = magia_tile_ni_0_9_to_router_0_9_req; - - assign router_0_9_to_router_0_10_rsp = router_0_9_rsp_out[0]; - assign router_0_9_to_router_1_9_rsp = router_0_9_rsp_out[1]; - assign router_0_9_to_router_0_8_rsp = router_0_9_rsp_out[2]; - assign router_0_9_to_L2_ni_9_rsp = router_0_9_rsp_out[3]; - assign router_0_9_to_magia_tile_ni_0_9_rsp = router_0_9_rsp_out[4]; - - assign router_0_9_to_router_0_10_req = router_0_9_req_out[0]; - assign router_0_9_to_router_1_9_req = router_0_9_req_out[1]; - assign router_0_9_to_router_0_8_req = router_0_9_req_out[2]; - assign router_0_9_to_L2_ni_9_req = router_0_9_req_out[3]; - assign router_0_9_to_magia_tile_ni_0_9_req = router_0_9_req_out[4]; - - assign router_0_9_rsp_in[0] = router_0_10_to_router_0_9_rsp; - assign router_0_9_rsp_in[1] = router_1_9_to_router_0_9_rsp; - assign router_0_9_rsp_in[2] = router_0_8_to_router_0_9_rsp; - assign router_0_9_rsp_in[3] = L2_ni_9_to_router_0_9_rsp; - assign router_0_9_rsp_in[4] = magia_tile_ni_0_9_to_router_0_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_9_req_in), - .floo_rsp_o (router_0_9_rsp_out), - .floo_req_o (router_0_9_req_out), - .floo_rsp_i (router_0_9_rsp_in) -); - - -floo_req_t [4:0] router_0_10_req_in; -floo_rsp_t [4:0] router_0_10_rsp_out; -floo_req_t [4:0] router_0_10_req_out; -floo_rsp_t [4:0] router_0_10_rsp_in; - - assign router_0_10_req_in[0] = router_0_11_to_router_0_10_req; - assign router_0_10_req_in[1] = router_1_10_to_router_0_10_req; - assign router_0_10_req_in[2] = router_0_9_to_router_0_10_req; - assign router_0_10_req_in[3] = L2_ni_10_to_router_0_10_req; - assign router_0_10_req_in[4] = magia_tile_ni_0_10_to_router_0_10_req; - - assign router_0_10_to_router_0_11_rsp = router_0_10_rsp_out[0]; - assign router_0_10_to_router_1_10_rsp = router_0_10_rsp_out[1]; - assign router_0_10_to_router_0_9_rsp = router_0_10_rsp_out[2]; - assign router_0_10_to_L2_ni_10_rsp = router_0_10_rsp_out[3]; - assign router_0_10_to_magia_tile_ni_0_10_rsp = router_0_10_rsp_out[4]; - - assign router_0_10_to_router_0_11_req = router_0_10_req_out[0]; - assign router_0_10_to_router_1_10_req = router_0_10_req_out[1]; - assign router_0_10_to_router_0_9_req = router_0_10_req_out[2]; - assign router_0_10_to_L2_ni_10_req = router_0_10_req_out[3]; - assign router_0_10_to_magia_tile_ni_0_10_req = router_0_10_req_out[4]; - - assign router_0_10_rsp_in[0] = router_0_11_to_router_0_10_rsp; - assign router_0_10_rsp_in[1] = router_1_10_to_router_0_10_rsp; - assign router_0_10_rsp_in[2] = router_0_9_to_router_0_10_rsp; - assign router_0_10_rsp_in[3] = L2_ni_10_to_router_0_10_rsp; - assign router_0_10_rsp_in[4] = magia_tile_ni_0_10_to_router_0_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_10_req_in), - .floo_rsp_o (router_0_10_rsp_out), - .floo_req_o (router_0_10_req_out), - .floo_rsp_i (router_0_10_rsp_in) -); - - -floo_req_t [4:0] router_0_11_req_in; -floo_rsp_t [4:0] router_0_11_rsp_out; -floo_req_t [4:0] router_0_11_req_out; -floo_rsp_t [4:0] router_0_11_rsp_in; - - assign router_0_11_req_in[0] = router_0_12_to_router_0_11_req; - assign router_0_11_req_in[1] = router_1_11_to_router_0_11_req; - assign router_0_11_req_in[2] = router_0_10_to_router_0_11_req; - assign router_0_11_req_in[3] = L2_ni_11_to_router_0_11_req; - assign router_0_11_req_in[4] = magia_tile_ni_0_11_to_router_0_11_req; - - assign router_0_11_to_router_0_12_rsp = router_0_11_rsp_out[0]; - assign router_0_11_to_router_1_11_rsp = router_0_11_rsp_out[1]; - assign router_0_11_to_router_0_10_rsp = router_0_11_rsp_out[2]; - assign router_0_11_to_L2_ni_11_rsp = router_0_11_rsp_out[3]; - assign router_0_11_to_magia_tile_ni_0_11_rsp = router_0_11_rsp_out[4]; - - assign router_0_11_to_router_0_12_req = router_0_11_req_out[0]; - assign router_0_11_to_router_1_11_req = router_0_11_req_out[1]; - assign router_0_11_to_router_0_10_req = router_0_11_req_out[2]; - assign router_0_11_to_L2_ni_11_req = router_0_11_req_out[3]; - assign router_0_11_to_magia_tile_ni_0_11_req = router_0_11_req_out[4]; - - assign router_0_11_rsp_in[0] = router_0_12_to_router_0_11_rsp; - assign router_0_11_rsp_in[1] = router_1_11_to_router_0_11_rsp; - assign router_0_11_rsp_in[2] = router_0_10_to_router_0_11_rsp; - assign router_0_11_rsp_in[3] = L2_ni_11_to_router_0_11_rsp; - assign router_0_11_rsp_in[4] = magia_tile_ni_0_11_to_router_0_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_11_req_in), - .floo_rsp_o (router_0_11_rsp_out), - .floo_req_o (router_0_11_req_out), - .floo_rsp_i (router_0_11_rsp_in) -); - - -floo_req_t [4:0] router_0_12_req_in; -floo_rsp_t [4:0] router_0_12_rsp_out; -floo_req_t [4:0] router_0_12_req_out; -floo_rsp_t [4:0] router_0_12_rsp_in; - - assign router_0_12_req_in[0] = router_0_13_to_router_0_12_req; - assign router_0_12_req_in[1] = router_1_12_to_router_0_12_req; - assign router_0_12_req_in[2] = router_0_11_to_router_0_12_req; - assign router_0_12_req_in[3] = L2_ni_12_to_router_0_12_req; - assign router_0_12_req_in[4] = magia_tile_ni_0_12_to_router_0_12_req; - - assign router_0_12_to_router_0_13_rsp = router_0_12_rsp_out[0]; - assign router_0_12_to_router_1_12_rsp = router_0_12_rsp_out[1]; - assign router_0_12_to_router_0_11_rsp = router_0_12_rsp_out[2]; - assign router_0_12_to_L2_ni_12_rsp = router_0_12_rsp_out[3]; - assign router_0_12_to_magia_tile_ni_0_12_rsp = router_0_12_rsp_out[4]; - - assign router_0_12_to_router_0_13_req = router_0_12_req_out[0]; - assign router_0_12_to_router_1_12_req = router_0_12_req_out[1]; - assign router_0_12_to_router_0_11_req = router_0_12_req_out[2]; - assign router_0_12_to_L2_ni_12_req = router_0_12_req_out[3]; - assign router_0_12_to_magia_tile_ni_0_12_req = router_0_12_req_out[4]; - - assign router_0_12_rsp_in[0] = router_0_13_to_router_0_12_rsp; - assign router_0_12_rsp_in[1] = router_1_12_to_router_0_12_rsp; - assign router_0_12_rsp_in[2] = router_0_11_to_router_0_12_rsp; - assign router_0_12_rsp_in[3] = L2_ni_12_to_router_0_12_rsp; - assign router_0_12_rsp_in[4] = magia_tile_ni_0_12_to_router_0_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_12_req_in), - .floo_rsp_o (router_0_12_rsp_out), - .floo_req_o (router_0_12_req_out), - .floo_rsp_i (router_0_12_rsp_in) -); - - -floo_req_t [4:0] router_0_13_req_in; -floo_rsp_t [4:0] router_0_13_rsp_out; -floo_req_t [4:0] router_0_13_req_out; -floo_rsp_t [4:0] router_0_13_rsp_in; - - assign router_0_13_req_in[0] = router_0_14_to_router_0_13_req; - assign router_0_13_req_in[1] = router_1_13_to_router_0_13_req; - assign router_0_13_req_in[2] = router_0_12_to_router_0_13_req; - assign router_0_13_req_in[3] = L2_ni_13_to_router_0_13_req; - assign router_0_13_req_in[4] = magia_tile_ni_0_13_to_router_0_13_req; - - assign router_0_13_to_router_0_14_rsp = router_0_13_rsp_out[0]; - assign router_0_13_to_router_1_13_rsp = router_0_13_rsp_out[1]; - assign router_0_13_to_router_0_12_rsp = router_0_13_rsp_out[2]; - assign router_0_13_to_L2_ni_13_rsp = router_0_13_rsp_out[3]; - assign router_0_13_to_magia_tile_ni_0_13_rsp = router_0_13_rsp_out[4]; - - assign router_0_13_to_router_0_14_req = router_0_13_req_out[0]; - assign router_0_13_to_router_1_13_req = router_0_13_req_out[1]; - assign router_0_13_to_router_0_12_req = router_0_13_req_out[2]; - assign router_0_13_to_L2_ni_13_req = router_0_13_req_out[3]; - assign router_0_13_to_magia_tile_ni_0_13_req = router_0_13_req_out[4]; - - assign router_0_13_rsp_in[0] = router_0_14_to_router_0_13_rsp; - assign router_0_13_rsp_in[1] = router_1_13_to_router_0_13_rsp; - assign router_0_13_rsp_in[2] = router_0_12_to_router_0_13_rsp; - assign router_0_13_rsp_in[3] = L2_ni_13_to_router_0_13_rsp; - assign router_0_13_rsp_in[4] = magia_tile_ni_0_13_to_router_0_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_13_req_in), - .floo_rsp_o (router_0_13_rsp_out), - .floo_req_o (router_0_13_req_out), - .floo_rsp_i (router_0_13_rsp_in) -); - - -floo_req_t [4:0] router_0_14_req_in; -floo_rsp_t [4:0] router_0_14_rsp_out; -floo_req_t [4:0] router_0_14_req_out; -floo_rsp_t [4:0] router_0_14_rsp_in; - - assign router_0_14_req_in[0] = router_0_15_to_router_0_14_req; - assign router_0_14_req_in[1] = router_1_14_to_router_0_14_req; - assign router_0_14_req_in[2] = router_0_13_to_router_0_14_req; - assign router_0_14_req_in[3] = L2_ni_14_to_router_0_14_req; - assign router_0_14_req_in[4] = magia_tile_ni_0_14_to_router_0_14_req; - - assign router_0_14_to_router_0_15_rsp = router_0_14_rsp_out[0]; - assign router_0_14_to_router_1_14_rsp = router_0_14_rsp_out[1]; - assign router_0_14_to_router_0_13_rsp = router_0_14_rsp_out[2]; - assign router_0_14_to_L2_ni_14_rsp = router_0_14_rsp_out[3]; - assign router_0_14_to_magia_tile_ni_0_14_rsp = router_0_14_rsp_out[4]; - - assign router_0_14_to_router_0_15_req = router_0_14_req_out[0]; - assign router_0_14_to_router_1_14_req = router_0_14_req_out[1]; - assign router_0_14_to_router_0_13_req = router_0_14_req_out[2]; - assign router_0_14_to_L2_ni_14_req = router_0_14_req_out[3]; - assign router_0_14_to_magia_tile_ni_0_14_req = router_0_14_req_out[4]; - - assign router_0_14_rsp_in[0] = router_0_15_to_router_0_14_rsp; - assign router_0_14_rsp_in[1] = router_1_14_to_router_0_14_rsp; - assign router_0_14_rsp_in[2] = router_0_13_to_router_0_14_rsp; - assign router_0_14_rsp_in[3] = L2_ni_14_to_router_0_14_rsp; - assign router_0_14_rsp_in[4] = magia_tile_ni_0_14_to_router_0_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_14_req_in), - .floo_rsp_o (router_0_14_rsp_out), - .floo_req_o (router_0_14_req_out), - .floo_rsp_i (router_0_14_rsp_in) -); - - -floo_req_t [4:0] router_0_15_req_in; -floo_rsp_t [4:0] router_0_15_rsp_out; -floo_req_t [4:0] router_0_15_req_out; -floo_rsp_t [4:0] router_0_15_rsp_in; - - assign router_0_15_req_in[0] = router_0_16_to_router_0_15_req; - assign router_0_15_req_in[1] = router_1_15_to_router_0_15_req; - assign router_0_15_req_in[2] = router_0_14_to_router_0_15_req; - assign router_0_15_req_in[3] = L2_ni_15_to_router_0_15_req; - assign router_0_15_req_in[4] = magia_tile_ni_0_15_to_router_0_15_req; - - assign router_0_15_to_router_0_16_rsp = router_0_15_rsp_out[0]; - assign router_0_15_to_router_1_15_rsp = router_0_15_rsp_out[1]; - assign router_0_15_to_router_0_14_rsp = router_0_15_rsp_out[2]; - assign router_0_15_to_L2_ni_15_rsp = router_0_15_rsp_out[3]; - assign router_0_15_to_magia_tile_ni_0_15_rsp = router_0_15_rsp_out[4]; - - assign router_0_15_to_router_0_16_req = router_0_15_req_out[0]; - assign router_0_15_to_router_1_15_req = router_0_15_req_out[1]; - assign router_0_15_to_router_0_14_req = router_0_15_req_out[2]; - assign router_0_15_to_L2_ni_15_req = router_0_15_req_out[3]; - assign router_0_15_to_magia_tile_ni_0_15_req = router_0_15_req_out[4]; - - assign router_0_15_rsp_in[0] = router_0_16_to_router_0_15_rsp; - assign router_0_15_rsp_in[1] = router_1_15_to_router_0_15_rsp; - assign router_0_15_rsp_in[2] = router_0_14_to_router_0_15_rsp; - assign router_0_15_rsp_in[3] = L2_ni_15_to_router_0_15_rsp; - assign router_0_15_rsp_in[4] = magia_tile_ni_0_15_to_router_0_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_15_req_in), - .floo_rsp_o (router_0_15_rsp_out), - .floo_req_o (router_0_15_req_out), - .floo_rsp_i (router_0_15_rsp_in) -); - - -floo_req_t [4:0] router_0_16_req_in; -floo_rsp_t [4:0] router_0_16_rsp_out; -floo_req_t [4:0] router_0_16_req_out; -floo_rsp_t [4:0] router_0_16_rsp_in; - - assign router_0_16_req_in[0] = router_0_17_to_router_0_16_req; - assign router_0_16_req_in[1] = router_1_16_to_router_0_16_req; - assign router_0_16_req_in[2] = router_0_15_to_router_0_16_req; - assign router_0_16_req_in[3] = L2_ni_16_to_router_0_16_req; - assign router_0_16_req_in[4] = magia_tile_ni_0_16_to_router_0_16_req; - - assign router_0_16_to_router_0_17_rsp = router_0_16_rsp_out[0]; - assign router_0_16_to_router_1_16_rsp = router_0_16_rsp_out[1]; - assign router_0_16_to_router_0_15_rsp = router_0_16_rsp_out[2]; - assign router_0_16_to_L2_ni_16_rsp = router_0_16_rsp_out[3]; - assign router_0_16_to_magia_tile_ni_0_16_rsp = router_0_16_rsp_out[4]; - - assign router_0_16_to_router_0_17_req = router_0_16_req_out[0]; - assign router_0_16_to_router_1_16_req = router_0_16_req_out[1]; - assign router_0_16_to_router_0_15_req = router_0_16_req_out[2]; - assign router_0_16_to_L2_ni_16_req = router_0_16_req_out[3]; - assign router_0_16_to_magia_tile_ni_0_16_req = router_0_16_req_out[4]; - - assign router_0_16_rsp_in[0] = router_0_17_to_router_0_16_rsp; - assign router_0_16_rsp_in[1] = router_1_16_to_router_0_16_rsp; - assign router_0_16_rsp_in[2] = router_0_15_to_router_0_16_rsp; - assign router_0_16_rsp_in[3] = L2_ni_16_to_router_0_16_rsp; - assign router_0_16_rsp_in[4] = magia_tile_ni_0_16_to_router_0_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_16_req_in), - .floo_rsp_o (router_0_16_rsp_out), - .floo_req_o (router_0_16_req_out), - .floo_rsp_i (router_0_16_rsp_in) -); - - -floo_req_t [4:0] router_0_17_req_in; -floo_rsp_t [4:0] router_0_17_rsp_out; -floo_req_t [4:0] router_0_17_req_out; -floo_rsp_t [4:0] router_0_17_rsp_in; - - assign router_0_17_req_in[0] = router_0_18_to_router_0_17_req; - assign router_0_17_req_in[1] = router_1_17_to_router_0_17_req; - assign router_0_17_req_in[2] = router_0_16_to_router_0_17_req; - assign router_0_17_req_in[3] = L2_ni_17_to_router_0_17_req; - assign router_0_17_req_in[4] = magia_tile_ni_0_17_to_router_0_17_req; - - assign router_0_17_to_router_0_18_rsp = router_0_17_rsp_out[0]; - assign router_0_17_to_router_1_17_rsp = router_0_17_rsp_out[1]; - assign router_0_17_to_router_0_16_rsp = router_0_17_rsp_out[2]; - assign router_0_17_to_L2_ni_17_rsp = router_0_17_rsp_out[3]; - assign router_0_17_to_magia_tile_ni_0_17_rsp = router_0_17_rsp_out[4]; - - assign router_0_17_to_router_0_18_req = router_0_17_req_out[0]; - assign router_0_17_to_router_1_17_req = router_0_17_req_out[1]; - assign router_0_17_to_router_0_16_req = router_0_17_req_out[2]; - assign router_0_17_to_L2_ni_17_req = router_0_17_req_out[3]; - assign router_0_17_to_magia_tile_ni_0_17_req = router_0_17_req_out[4]; - - assign router_0_17_rsp_in[0] = router_0_18_to_router_0_17_rsp; - assign router_0_17_rsp_in[1] = router_1_17_to_router_0_17_rsp; - assign router_0_17_rsp_in[2] = router_0_16_to_router_0_17_rsp; - assign router_0_17_rsp_in[3] = L2_ni_17_to_router_0_17_rsp; - assign router_0_17_rsp_in[4] = magia_tile_ni_0_17_to_router_0_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_17_req_in), - .floo_rsp_o (router_0_17_rsp_out), - .floo_req_o (router_0_17_req_out), - .floo_rsp_i (router_0_17_rsp_in) -); - - -floo_req_t [4:0] router_0_18_req_in; -floo_rsp_t [4:0] router_0_18_rsp_out; -floo_req_t [4:0] router_0_18_req_out; -floo_rsp_t [4:0] router_0_18_rsp_in; - - assign router_0_18_req_in[0] = router_0_19_to_router_0_18_req; - assign router_0_18_req_in[1] = router_1_18_to_router_0_18_req; - assign router_0_18_req_in[2] = router_0_17_to_router_0_18_req; - assign router_0_18_req_in[3] = L2_ni_18_to_router_0_18_req; - assign router_0_18_req_in[4] = magia_tile_ni_0_18_to_router_0_18_req; - - assign router_0_18_to_router_0_19_rsp = router_0_18_rsp_out[0]; - assign router_0_18_to_router_1_18_rsp = router_0_18_rsp_out[1]; - assign router_0_18_to_router_0_17_rsp = router_0_18_rsp_out[2]; - assign router_0_18_to_L2_ni_18_rsp = router_0_18_rsp_out[3]; - assign router_0_18_to_magia_tile_ni_0_18_rsp = router_0_18_rsp_out[4]; - - assign router_0_18_to_router_0_19_req = router_0_18_req_out[0]; - assign router_0_18_to_router_1_18_req = router_0_18_req_out[1]; - assign router_0_18_to_router_0_17_req = router_0_18_req_out[2]; - assign router_0_18_to_L2_ni_18_req = router_0_18_req_out[3]; - assign router_0_18_to_magia_tile_ni_0_18_req = router_0_18_req_out[4]; - - assign router_0_18_rsp_in[0] = router_0_19_to_router_0_18_rsp; - assign router_0_18_rsp_in[1] = router_1_18_to_router_0_18_rsp; - assign router_0_18_rsp_in[2] = router_0_17_to_router_0_18_rsp; - assign router_0_18_rsp_in[3] = L2_ni_18_to_router_0_18_rsp; - assign router_0_18_rsp_in[4] = magia_tile_ni_0_18_to_router_0_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_18_req_in), - .floo_rsp_o (router_0_18_rsp_out), - .floo_req_o (router_0_18_req_out), - .floo_rsp_i (router_0_18_rsp_in) -); - - -floo_req_t [4:0] router_0_19_req_in; -floo_rsp_t [4:0] router_0_19_rsp_out; -floo_req_t [4:0] router_0_19_req_out; -floo_rsp_t [4:0] router_0_19_rsp_in; - - assign router_0_19_req_in[0] = router_0_20_to_router_0_19_req; - assign router_0_19_req_in[1] = router_1_19_to_router_0_19_req; - assign router_0_19_req_in[2] = router_0_18_to_router_0_19_req; - assign router_0_19_req_in[3] = L2_ni_19_to_router_0_19_req; - assign router_0_19_req_in[4] = magia_tile_ni_0_19_to_router_0_19_req; - - assign router_0_19_to_router_0_20_rsp = router_0_19_rsp_out[0]; - assign router_0_19_to_router_1_19_rsp = router_0_19_rsp_out[1]; - assign router_0_19_to_router_0_18_rsp = router_0_19_rsp_out[2]; - assign router_0_19_to_L2_ni_19_rsp = router_0_19_rsp_out[3]; - assign router_0_19_to_magia_tile_ni_0_19_rsp = router_0_19_rsp_out[4]; - - assign router_0_19_to_router_0_20_req = router_0_19_req_out[0]; - assign router_0_19_to_router_1_19_req = router_0_19_req_out[1]; - assign router_0_19_to_router_0_18_req = router_0_19_req_out[2]; - assign router_0_19_to_L2_ni_19_req = router_0_19_req_out[3]; - assign router_0_19_to_magia_tile_ni_0_19_req = router_0_19_req_out[4]; - - assign router_0_19_rsp_in[0] = router_0_20_to_router_0_19_rsp; - assign router_0_19_rsp_in[1] = router_1_19_to_router_0_19_rsp; - assign router_0_19_rsp_in[2] = router_0_18_to_router_0_19_rsp; - assign router_0_19_rsp_in[3] = L2_ni_19_to_router_0_19_rsp; - assign router_0_19_rsp_in[4] = magia_tile_ni_0_19_to_router_0_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_19_req_in), - .floo_rsp_o (router_0_19_rsp_out), - .floo_req_o (router_0_19_req_out), - .floo_rsp_i (router_0_19_rsp_in) -); - - -floo_req_t [4:0] router_0_20_req_in; -floo_rsp_t [4:0] router_0_20_rsp_out; -floo_req_t [4:0] router_0_20_req_out; -floo_rsp_t [4:0] router_0_20_rsp_in; - - assign router_0_20_req_in[0] = router_0_21_to_router_0_20_req; - assign router_0_20_req_in[1] = router_1_20_to_router_0_20_req; - assign router_0_20_req_in[2] = router_0_19_to_router_0_20_req; - assign router_0_20_req_in[3] = L2_ni_20_to_router_0_20_req; - assign router_0_20_req_in[4] = magia_tile_ni_0_20_to_router_0_20_req; - - assign router_0_20_to_router_0_21_rsp = router_0_20_rsp_out[0]; - assign router_0_20_to_router_1_20_rsp = router_0_20_rsp_out[1]; - assign router_0_20_to_router_0_19_rsp = router_0_20_rsp_out[2]; - assign router_0_20_to_L2_ni_20_rsp = router_0_20_rsp_out[3]; - assign router_0_20_to_magia_tile_ni_0_20_rsp = router_0_20_rsp_out[4]; - - assign router_0_20_to_router_0_21_req = router_0_20_req_out[0]; - assign router_0_20_to_router_1_20_req = router_0_20_req_out[1]; - assign router_0_20_to_router_0_19_req = router_0_20_req_out[2]; - assign router_0_20_to_L2_ni_20_req = router_0_20_req_out[3]; - assign router_0_20_to_magia_tile_ni_0_20_req = router_0_20_req_out[4]; - - assign router_0_20_rsp_in[0] = router_0_21_to_router_0_20_rsp; - assign router_0_20_rsp_in[1] = router_1_20_to_router_0_20_rsp; - assign router_0_20_rsp_in[2] = router_0_19_to_router_0_20_rsp; - assign router_0_20_rsp_in[3] = L2_ni_20_to_router_0_20_rsp; - assign router_0_20_rsp_in[4] = magia_tile_ni_0_20_to_router_0_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_20_req_in), - .floo_rsp_o (router_0_20_rsp_out), - .floo_req_o (router_0_20_req_out), - .floo_rsp_i (router_0_20_rsp_in) -); - - -floo_req_t [4:0] router_0_21_req_in; -floo_rsp_t [4:0] router_0_21_rsp_out; -floo_req_t [4:0] router_0_21_req_out; -floo_rsp_t [4:0] router_0_21_rsp_in; - - assign router_0_21_req_in[0] = router_0_22_to_router_0_21_req; - assign router_0_21_req_in[1] = router_1_21_to_router_0_21_req; - assign router_0_21_req_in[2] = router_0_20_to_router_0_21_req; - assign router_0_21_req_in[3] = L2_ni_21_to_router_0_21_req; - assign router_0_21_req_in[4] = magia_tile_ni_0_21_to_router_0_21_req; - - assign router_0_21_to_router_0_22_rsp = router_0_21_rsp_out[0]; - assign router_0_21_to_router_1_21_rsp = router_0_21_rsp_out[1]; - assign router_0_21_to_router_0_20_rsp = router_0_21_rsp_out[2]; - assign router_0_21_to_L2_ni_21_rsp = router_0_21_rsp_out[3]; - assign router_0_21_to_magia_tile_ni_0_21_rsp = router_0_21_rsp_out[4]; - - assign router_0_21_to_router_0_22_req = router_0_21_req_out[0]; - assign router_0_21_to_router_1_21_req = router_0_21_req_out[1]; - assign router_0_21_to_router_0_20_req = router_0_21_req_out[2]; - assign router_0_21_to_L2_ni_21_req = router_0_21_req_out[3]; - assign router_0_21_to_magia_tile_ni_0_21_req = router_0_21_req_out[4]; - - assign router_0_21_rsp_in[0] = router_0_22_to_router_0_21_rsp; - assign router_0_21_rsp_in[1] = router_1_21_to_router_0_21_rsp; - assign router_0_21_rsp_in[2] = router_0_20_to_router_0_21_rsp; - assign router_0_21_rsp_in[3] = L2_ni_21_to_router_0_21_rsp; - assign router_0_21_rsp_in[4] = magia_tile_ni_0_21_to_router_0_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_21_req_in), - .floo_rsp_o (router_0_21_rsp_out), - .floo_req_o (router_0_21_req_out), - .floo_rsp_i (router_0_21_rsp_in) -); - - -floo_req_t [4:0] router_0_22_req_in; -floo_rsp_t [4:0] router_0_22_rsp_out; -floo_req_t [4:0] router_0_22_req_out; -floo_rsp_t [4:0] router_0_22_rsp_in; - - assign router_0_22_req_in[0] = router_0_23_to_router_0_22_req; - assign router_0_22_req_in[1] = router_1_22_to_router_0_22_req; - assign router_0_22_req_in[2] = router_0_21_to_router_0_22_req; - assign router_0_22_req_in[3] = L2_ni_22_to_router_0_22_req; - assign router_0_22_req_in[4] = magia_tile_ni_0_22_to_router_0_22_req; - - assign router_0_22_to_router_0_23_rsp = router_0_22_rsp_out[0]; - assign router_0_22_to_router_1_22_rsp = router_0_22_rsp_out[1]; - assign router_0_22_to_router_0_21_rsp = router_0_22_rsp_out[2]; - assign router_0_22_to_L2_ni_22_rsp = router_0_22_rsp_out[3]; - assign router_0_22_to_magia_tile_ni_0_22_rsp = router_0_22_rsp_out[4]; - - assign router_0_22_to_router_0_23_req = router_0_22_req_out[0]; - assign router_0_22_to_router_1_22_req = router_0_22_req_out[1]; - assign router_0_22_to_router_0_21_req = router_0_22_req_out[2]; - assign router_0_22_to_L2_ni_22_req = router_0_22_req_out[3]; - assign router_0_22_to_magia_tile_ni_0_22_req = router_0_22_req_out[4]; - - assign router_0_22_rsp_in[0] = router_0_23_to_router_0_22_rsp; - assign router_0_22_rsp_in[1] = router_1_22_to_router_0_22_rsp; - assign router_0_22_rsp_in[2] = router_0_21_to_router_0_22_rsp; - assign router_0_22_rsp_in[3] = L2_ni_22_to_router_0_22_rsp; - assign router_0_22_rsp_in[4] = magia_tile_ni_0_22_to_router_0_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_22_req_in), - .floo_rsp_o (router_0_22_rsp_out), - .floo_req_o (router_0_22_req_out), - .floo_rsp_i (router_0_22_rsp_in) -); - - -floo_req_t [4:0] router_0_23_req_in; -floo_rsp_t [4:0] router_0_23_rsp_out; -floo_req_t [4:0] router_0_23_req_out; -floo_rsp_t [4:0] router_0_23_rsp_in; - - assign router_0_23_req_in[0] = router_0_24_to_router_0_23_req; - assign router_0_23_req_in[1] = router_1_23_to_router_0_23_req; - assign router_0_23_req_in[2] = router_0_22_to_router_0_23_req; - assign router_0_23_req_in[3] = L2_ni_23_to_router_0_23_req; - assign router_0_23_req_in[4] = magia_tile_ni_0_23_to_router_0_23_req; - - assign router_0_23_to_router_0_24_rsp = router_0_23_rsp_out[0]; - assign router_0_23_to_router_1_23_rsp = router_0_23_rsp_out[1]; - assign router_0_23_to_router_0_22_rsp = router_0_23_rsp_out[2]; - assign router_0_23_to_L2_ni_23_rsp = router_0_23_rsp_out[3]; - assign router_0_23_to_magia_tile_ni_0_23_rsp = router_0_23_rsp_out[4]; - - assign router_0_23_to_router_0_24_req = router_0_23_req_out[0]; - assign router_0_23_to_router_1_23_req = router_0_23_req_out[1]; - assign router_0_23_to_router_0_22_req = router_0_23_req_out[2]; - assign router_0_23_to_L2_ni_23_req = router_0_23_req_out[3]; - assign router_0_23_to_magia_tile_ni_0_23_req = router_0_23_req_out[4]; - - assign router_0_23_rsp_in[0] = router_0_24_to_router_0_23_rsp; - assign router_0_23_rsp_in[1] = router_1_23_to_router_0_23_rsp; - assign router_0_23_rsp_in[2] = router_0_22_to_router_0_23_rsp; - assign router_0_23_rsp_in[3] = L2_ni_23_to_router_0_23_rsp; - assign router_0_23_rsp_in[4] = magia_tile_ni_0_23_to_router_0_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_23_req_in), - .floo_rsp_o (router_0_23_rsp_out), - .floo_req_o (router_0_23_req_out), - .floo_rsp_i (router_0_23_rsp_in) -); - - -floo_req_t [4:0] router_0_24_req_in; -floo_rsp_t [4:0] router_0_24_rsp_out; -floo_req_t [4:0] router_0_24_req_out; -floo_rsp_t [4:0] router_0_24_rsp_in; - - assign router_0_24_req_in[0] = router_0_25_to_router_0_24_req; - assign router_0_24_req_in[1] = router_1_24_to_router_0_24_req; - assign router_0_24_req_in[2] = router_0_23_to_router_0_24_req; - assign router_0_24_req_in[3] = L2_ni_24_to_router_0_24_req; - assign router_0_24_req_in[4] = magia_tile_ni_0_24_to_router_0_24_req; - - assign router_0_24_to_router_0_25_rsp = router_0_24_rsp_out[0]; - assign router_0_24_to_router_1_24_rsp = router_0_24_rsp_out[1]; - assign router_0_24_to_router_0_23_rsp = router_0_24_rsp_out[2]; - assign router_0_24_to_L2_ni_24_rsp = router_0_24_rsp_out[3]; - assign router_0_24_to_magia_tile_ni_0_24_rsp = router_0_24_rsp_out[4]; - - assign router_0_24_to_router_0_25_req = router_0_24_req_out[0]; - assign router_0_24_to_router_1_24_req = router_0_24_req_out[1]; - assign router_0_24_to_router_0_23_req = router_0_24_req_out[2]; - assign router_0_24_to_L2_ni_24_req = router_0_24_req_out[3]; - assign router_0_24_to_magia_tile_ni_0_24_req = router_0_24_req_out[4]; - - assign router_0_24_rsp_in[0] = router_0_25_to_router_0_24_rsp; - assign router_0_24_rsp_in[1] = router_1_24_to_router_0_24_rsp; - assign router_0_24_rsp_in[2] = router_0_23_to_router_0_24_rsp; - assign router_0_24_rsp_in[3] = L2_ni_24_to_router_0_24_rsp; - assign router_0_24_rsp_in[4] = magia_tile_ni_0_24_to_router_0_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_24_req_in), - .floo_rsp_o (router_0_24_rsp_out), - .floo_req_o (router_0_24_req_out), - .floo_rsp_i (router_0_24_rsp_in) -); - - -floo_req_t [4:0] router_0_25_req_in; -floo_rsp_t [4:0] router_0_25_rsp_out; -floo_req_t [4:0] router_0_25_req_out; -floo_rsp_t [4:0] router_0_25_rsp_in; - - assign router_0_25_req_in[0] = router_0_26_to_router_0_25_req; - assign router_0_25_req_in[1] = router_1_25_to_router_0_25_req; - assign router_0_25_req_in[2] = router_0_24_to_router_0_25_req; - assign router_0_25_req_in[3] = L2_ni_25_to_router_0_25_req; - assign router_0_25_req_in[4] = magia_tile_ni_0_25_to_router_0_25_req; - - assign router_0_25_to_router_0_26_rsp = router_0_25_rsp_out[0]; - assign router_0_25_to_router_1_25_rsp = router_0_25_rsp_out[1]; - assign router_0_25_to_router_0_24_rsp = router_0_25_rsp_out[2]; - assign router_0_25_to_L2_ni_25_rsp = router_0_25_rsp_out[3]; - assign router_0_25_to_magia_tile_ni_0_25_rsp = router_0_25_rsp_out[4]; - - assign router_0_25_to_router_0_26_req = router_0_25_req_out[0]; - assign router_0_25_to_router_1_25_req = router_0_25_req_out[1]; - assign router_0_25_to_router_0_24_req = router_0_25_req_out[2]; - assign router_0_25_to_L2_ni_25_req = router_0_25_req_out[3]; - assign router_0_25_to_magia_tile_ni_0_25_req = router_0_25_req_out[4]; - - assign router_0_25_rsp_in[0] = router_0_26_to_router_0_25_rsp; - assign router_0_25_rsp_in[1] = router_1_25_to_router_0_25_rsp; - assign router_0_25_rsp_in[2] = router_0_24_to_router_0_25_rsp; - assign router_0_25_rsp_in[3] = L2_ni_25_to_router_0_25_rsp; - assign router_0_25_rsp_in[4] = magia_tile_ni_0_25_to_router_0_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_25_req_in), - .floo_rsp_o (router_0_25_rsp_out), - .floo_req_o (router_0_25_req_out), - .floo_rsp_i (router_0_25_rsp_in) -); - - -floo_req_t [4:0] router_0_26_req_in; -floo_rsp_t [4:0] router_0_26_rsp_out; -floo_req_t [4:0] router_0_26_req_out; -floo_rsp_t [4:0] router_0_26_rsp_in; - - assign router_0_26_req_in[0] = router_0_27_to_router_0_26_req; - assign router_0_26_req_in[1] = router_1_26_to_router_0_26_req; - assign router_0_26_req_in[2] = router_0_25_to_router_0_26_req; - assign router_0_26_req_in[3] = L2_ni_26_to_router_0_26_req; - assign router_0_26_req_in[4] = magia_tile_ni_0_26_to_router_0_26_req; - - assign router_0_26_to_router_0_27_rsp = router_0_26_rsp_out[0]; - assign router_0_26_to_router_1_26_rsp = router_0_26_rsp_out[1]; - assign router_0_26_to_router_0_25_rsp = router_0_26_rsp_out[2]; - assign router_0_26_to_L2_ni_26_rsp = router_0_26_rsp_out[3]; - assign router_0_26_to_magia_tile_ni_0_26_rsp = router_0_26_rsp_out[4]; - - assign router_0_26_to_router_0_27_req = router_0_26_req_out[0]; - assign router_0_26_to_router_1_26_req = router_0_26_req_out[1]; - assign router_0_26_to_router_0_25_req = router_0_26_req_out[2]; - assign router_0_26_to_L2_ni_26_req = router_0_26_req_out[3]; - assign router_0_26_to_magia_tile_ni_0_26_req = router_0_26_req_out[4]; - - assign router_0_26_rsp_in[0] = router_0_27_to_router_0_26_rsp; - assign router_0_26_rsp_in[1] = router_1_26_to_router_0_26_rsp; - assign router_0_26_rsp_in[2] = router_0_25_to_router_0_26_rsp; - assign router_0_26_rsp_in[3] = L2_ni_26_to_router_0_26_rsp; - assign router_0_26_rsp_in[4] = magia_tile_ni_0_26_to_router_0_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_26_req_in), - .floo_rsp_o (router_0_26_rsp_out), - .floo_req_o (router_0_26_req_out), - .floo_rsp_i (router_0_26_rsp_in) -); - - -floo_req_t [4:0] router_0_27_req_in; -floo_rsp_t [4:0] router_0_27_rsp_out; -floo_req_t [4:0] router_0_27_req_out; -floo_rsp_t [4:0] router_0_27_rsp_in; - - assign router_0_27_req_in[0] = router_0_28_to_router_0_27_req; - assign router_0_27_req_in[1] = router_1_27_to_router_0_27_req; - assign router_0_27_req_in[2] = router_0_26_to_router_0_27_req; - assign router_0_27_req_in[3] = L2_ni_27_to_router_0_27_req; - assign router_0_27_req_in[4] = magia_tile_ni_0_27_to_router_0_27_req; - - assign router_0_27_to_router_0_28_rsp = router_0_27_rsp_out[0]; - assign router_0_27_to_router_1_27_rsp = router_0_27_rsp_out[1]; - assign router_0_27_to_router_0_26_rsp = router_0_27_rsp_out[2]; - assign router_0_27_to_L2_ni_27_rsp = router_0_27_rsp_out[3]; - assign router_0_27_to_magia_tile_ni_0_27_rsp = router_0_27_rsp_out[4]; - - assign router_0_27_to_router_0_28_req = router_0_27_req_out[0]; - assign router_0_27_to_router_1_27_req = router_0_27_req_out[1]; - assign router_0_27_to_router_0_26_req = router_0_27_req_out[2]; - assign router_0_27_to_L2_ni_27_req = router_0_27_req_out[3]; - assign router_0_27_to_magia_tile_ni_0_27_req = router_0_27_req_out[4]; - - assign router_0_27_rsp_in[0] = router_0_28_to_router_0_27_rsp; - assign router_0_27_rsp_in[1] = router_1_27_to_router_0_27_rsp; - assign router_0_27_rsp_in[2] = router_0_26_to_router_0_27_rsp; - assign router_0_27_rsp_in[3] = L2_ni_27_to_router_0_27_rsp; - assign router_0_27_rsp_in[4] = magia_tile_ni_0_27_to_router_0_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_27_req_in), - .floo_rsp_o (router_0_27_rsp_out), - .floo_req_o (router_0_27_req_out), - .floo_rsp_i (router_0_27_rsp_in) -); - - -floo_req_t [4:0] router_0_28_req_in; -floo_rsp_t [4:0] router_0_28_rsp_out; -floo_req_t [4:0] router_0_28_req_out; -floo_rsp_t [4:0] router_0_28_rsp_in; - - assign router_0_28_req_in[0] = router_0_29_to_router_0_28_req; - assign router_0_28_req_in[1] = router_1_28_to_router_0_28_req; - assign router_0_28_req_in[2] = router_0_27_to_router_0_28_req; - assign router_0_28_req_in[3] = L2_ni_28_to_router_0_28_req; - assign router_0_28_req_in[4] = magia_tile_ni_0_28_to_router_0_28_req; - - assign router_0_28_to_router_0_29_rsp = router_0_28_rsp_out[0]; - assign router_0_28_to_router_1_28_rsp = router_0_28_rsp_out[1]; - assign router_0_28_to_router_0_27_rsp = router_0_28_rsp_out[2]; - assign router_0_28_to_L2_ni_28_rsp = router_0_28_rsp_out[3]; - assign router_0_28_to_magia_tile_ni_0_28_rsp = router_0_28_rsp_out[4]; - - assign router_0_28_to_router_0_29_req = router_0_28_req_out[0]; - assign router_0_28_to_router_1_28_req = router_0_28_req_out[1]; - assign router_0_28_to_router_0_27_req = router_0_28_req_out[2]; - assign router_0_28_to_L2_ni_28_req = router_0_28_req_out[3]; - assign router_0_28_to_magia_tile_ni_0_28_req = router_0_28_req_out[4]; - - assign router_0_28_rsp_in[0] = router_0_29_to_router_0_28_rsp; - assign router_0_28_rsp_in[1] = router_1_28_to_router_0_28_rsp; - assign router_0_28_rsp_in[2] = router_0_27_to_router_0_28_rsp; - assign router_0_28_rsp_in[3] = L2_ni_28_to_router_0_28_rsp; - assign router_0_28_rsp_in[4] = magia_tile_ni_0_28_to_router_0_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_28_req_in), - .floo_rsp_o (router_0_28_rsp_out), - .floo_req_o (router_0_28_req_out), - .floo_rsp_i (router_0_28_rsp_in) -); - - -floo_req_t [4:0] router_0_29_req_in; -floo_rsp_t [4:0] router_0_29_rsp_out; -floo_req_t [4:0] router_0_29_req_out; -floo_rsp_t [4:0] router_0_29_rsp_in; - - assign router_0_29_req_in[0] = router_0_30_to_router_0_29_req; - assign router_0_29_req_in[1] = router_1_29_to_router_0_29_req; - assign router_0_29_req_in[2] = router_0_28_to_router_0_29_req; - assign router_0_29_req_in[3] = L2_ni_29_to_router_0_29_req; - assign router_0_29_req_in[4] = magia_tile_ni_0_29_to_router_0_29_req; - - assign router_0_29_to_router_0_30_rsp = router_0_29_rsp_out[0]; - assign router_0_29_to_router_1_29_rsp = router_0_29_rsp_out[1]; - assign router_0_29_to_router_0_28_rsp = router_0_29_rsp_out[2]; - assign router_0_29_to_L2_ni_29_rsp = router_0_29_rsp_out[3]; - assign router_0_29_to_magia_tile_ni_0_29_rsp = router_0_29_rsp_out[4]; - - assign router_0_29_to_router_0_30_req = router_0_29_req_out[0]; - assign router_0_29_to_router_1_29_req = router_0_29_req_out[1]; - assign router_0_29_to_router_0_28_req = router_0_29_req_out[2]; - assign router_0_29_to_L2_ni_29_req = router_0_29_req_out[3]; - assign router_0_29_to_magia_tile_ni_0_29_req = router_0_29_req_out[4]; - - assign router_0_29_rsp_in[0] = router_0_30_to_router_0_29_rsp; - assign router_0_29_rsp_in[1] = router_1_29_to_router_0_29_rsp; - assign router_0_29_rsp_in[2] = router_0_28_to_router_0_29_rsp; - assign router_0_29_rsp_in[3] = L2_ni_29_to_router_0_29_rsp; - assign router_0_29_rsp_in[4] = magia_tile_ni_0_29_to_router_0_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_29_req_in), - .floo_rsp_o (router_0_29_rsp_out), - .floo_req_o (router_0_29_req_out), - .floo_rsp_i (router_0_29_rsp_in) -); - - -floo_req_t [4:0] router_0_30_req_in; -floo_rsp_t [4:0] router_0_30_rsp_out; -floo_req_t [4:0] router_0_30_req_out; -floo_rsp_t [4:0] router_0_30_rsp_in; - - assign router_0_30_req_in[0] = router_0_31_to_router_0_30_req; - assign router_0_30_req_in[1] = router_1_30_to_router_0_30_req; - assign router_0_30_req_in[2] = router_0_29_to_router_0_30_req; - assign router_0_30_req_in[3] = L2_ni_30_to_router_0_30_req; - assign router_0_30_req_in[4] = magia_tile_ni_0_30_to_router_0_30_req; - - assign router_0_30_to_router_0_31_rsp = router_0_30_rsp_out[0]; - assign router_0_30_to_router_1_30_rsp = router_0_30_rsp_out[1]; - assign router_0_30_to_router_0_29_rsp = router_0_30_rsp_out[2]; - assign router_0_30_to_L2_ni_30_rsp = router_0_30_rsp_out[3]; - assign router_0_30_to_magia_tile_ni_0_30_rsp = router_0_30_rsp_out[4]; - - assign router_0_30_to_router_0_31_req = router_0_30_req_out[0]; - assign router_0_30_to_router_1_30_req = router_0_30_req_out[1]; - assign router_0_30_to_router_0_29_req = router_0_30_req_out[2]; - assign router_0_30_to_L2_ni_30_req = router_0_30_req_out[3]; - assign router_0_30_to_magia_tile_ni_0_30_req = router_0_30_req_out[4]; - - assign router_0_30_rsp_in[0] = router_0_31_to_router_0_30_rsp; - assign router_0_30_rsp_in[1] = router_1_30_to_router_0_30_rsp; - assign router_0_30_rsp_in[2] = router_0_29_to_router_0_30_rsp; - assign router_0_30_rsp_in[3] = L2_ni_30_to_router_0_30_rsp; - assign router_0_30_rsp_in[4] = magia_tile_ni_0_30_to_router_0_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_30_req_in), - .floo_rsp_o (router_0_30_rsp_out), - .floo_req_o (router_0_30_req_out), - .floo_rsp_i (router_0_30_rsp_in) -); - - -floo_req_t [4:0] router_0_31_req_in; -floo_rsp_t [4:0] router_0_31_rsp_out; -floo_req_t [4:0] router_0_31_req_out; -floo_rsp_t [4:0] router_0_31_rsp_in; - - assign router_0_31_req_in[0] = '0; - assign router_0_31_req_in[1] = router_1_31_to_router_0_31_req; - assign router_0_31_req_in[2] = router_0_30_to_router_0_31_req; - assign router_0_31_req_in[3] = L2_ni_31_to_router_0_31_req; - assign router_0_31_req_in[4] = magia_tile_ni_0_31_to_router_0_31_req; - - assign router_0_31_to_router_1_31_rsp = router_0_31_rsp_out[1]; - assign router_0_31_to_router_0_30_rsp = router_0_31_rsp_out[2]; - assign router_0_31_to_L2_ni_31_rsp = router_0_31_rsp_out[3]; - assign router_0_31_to_magia_tile_ni_0_31_rsp = router_0_31_rsp_out[4]; - - assign router_0_31_to_router_1_31_req = router_0_31_req_out[1]; - assign router_0_31_to_router_0_30_req = router_0_31_req_out[2]; - assign router_0_31_to_L2_ni_31_req = router_0_31_req_out[3]; - assign router_0_31_to_magia_tile_ni_0_31_req = router_0_31_req_out[4]; - - assign router_0_31_rsp_in[0] = '0; - assign router_0_31_rsp_in[1] = router_1_31_to_router_0_31_rsp; - assign router_0_31_rsp_in[2] = router_0_30_to_router_0_31_rsp; - assign router_0_31_rsp_in[3] = L2_ni_31_to_router_0_31_rsp; - assign router_0_31_rsp_in[4] = magia_tile_ni_0_31_to_router_0_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_31_req_in), - .floo_rsp_o (router_0_31_rsp_out), - .floo_req_o (router_0_31_req_out), - .floo_rsp_i (router_0_31_rsp_in) -); - - -floo_req_t [4:0] router_1_0_req_in; -floo_rsp_t [4:0] router_1_0_rsp_out; -floo_req_t [4:0] router_1_0_req_out; -floo_rsp_t [4:0] router_1_0_rsp_in; - - assign router_1_0_req_in[0] = router_1_1_to_router_1_0_req; - assign router_1_0_req_in[1] = router_2_0_to_router_1_0_req; - assign router_1_0_req_in[2] = '0; - assign router_1_0_req_in[3] = router_0_0_to_router_1_0_req; - assign router_1_0_req_in[4] = magia_tile_ni_1_0_to_router_1_0_req; - - assign router_1_0_to_router_1_1_rsp = router_1_0_rsp_out[0]; - assign router_1_0_to_router_2_0_rsp = router_1_0_rsp_out[1]; - assign router_1_0_to_router_0_0_rsp = router_1_0_rsp_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_rsp = router_1_0_rsp_out[4]; - - assign router_1_0_to_router_1_1_req = router_1_0_req_out[0]; - assign router_1_0_to_router_2_0_req = router_1_0_req_out[1]; - assign router_1_0_to_router_0_0_req = router_1_0_req_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_req = router_1_0_req_out[4]; - - assign router_1_0_rsp_in[0] = router_1_1_to_router_1_0_rsp; - assign router_1_0_rsp_in[1] = router_2_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[2] = '0; - assign router_1_0_rsp_in[3] = router_0_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[4] = magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_0_req_in), - .floo_rsp_o (router_1_0_rsp_out), - .floo_req_o (router_1_0_req_out), - .floo_rsp_i (router_1_0_rsp_in) -); - - -floo_req_t [4:0] router_1_1_req_in; -floo_rsp_t [4:0] router_1_1_rsp_out; -floo_req_t [4:0] router_1_1_req_out; -floo_rsp_t [4:0] router_1_1_rsp_in; - - assign router_1_1_req_in[0] = router_1_2_to_router_1_1_req; - assign router_1_1_req_in[1] = router_2_1_to_router_1_1_req; - assign router_1_1_req_in[2] = router_1_0_to_router_1_1_req; - assign router_1_1_req_in[3] = router_0_1_to_router_1_1_req; - assign router_1_1_req_in[4] = magia_tile_ni_1_1_to_router_1_1_req; - - assign router_1_1_to_router_1_2_rsp = router_1_1_rsp_out[0]; - assign router_1_1_to_router_2_1_rsp = router_1_1_rsp_out[1]; - assign router_1_1_to_router_1_0_rsp = router_1_1_rsp_out[2]; - assign router_1_1_to_router_0_1_rsp = router_1_1_rsp_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_rsp = router_1_1_rsp_out[4]; - - assign router_1_1_to_router_1_2_req = router_1_1_req_out[0]; - assign router_1_1_to_router_2_1_req = router_1_1_req_out[1]; - assign router_1_1_to_router_1_0_req = router_1_1_req_out[2]; - assign router_1_1_to_router_0_1_req = router_1_1_req_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_req = router_1_1_req_out[4]; - - assign router_1_1_rsp_in[0] = router_1_2_to_router_1_1_rsp; - assign router_1_1_rsp_in[1] = router_2_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[2] = router_1_0_to_router_1_1_rsp; - assign router_1_1_rsp_in[3] = router_0_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[4] = magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_1_req_in), - .floo_rsp_o (router_1_1_rsp_out), - .floo_req_o (router_1_1_req_out), - .floo_rsp_i (router_1_1_rsp_in) -); - - -floo_req_t [4:0] router_1_2_req_in; -floo_rsp_t [4:0] router_1_2_rsp_out; -floo_req_t [4:0] router_1_2_req_out; -floo_rsp_t [4:0] router_1_2_rsp_in; - - assign router_1_2_req_in[0] = router_1_3_to_router_1_2_req; - assign router_1_2_req_in[1] = router_2_2_to_router_1_2_req; - assign router_1_2_req_in[2] = router_1_1_to_router_1_2_req; - assign router_1_2_req_in[3] = router_0_2_to_router_1_2_req; - assign router_1_2_req_in[4] = magia_tile_ni_1_2_to_router_1_2_req; - - assign router_1_2_to_router_1_3_rsp = router_1_2_rsp_out[0]; - assign router_1_2_to_router_2_2_rsp = router_1_2_rsp_out[1]; - assign router_1_2_to_router_1_1_rsp = router_1_2_rsp_out[2]; - assign router_1_2_to_router_0_2_rsp = router_1_2_rsp_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_rsp = router_1_2_rsp_out[4]; - - assign router_1_2_to_router_1_3_req = router_1_2_req_out[0]; - assign router_1_2_to_router_2_2_req = router_1_2_req_out[1]; - assign router_1_2_to_router_1_1_req = router_1_2_req_out[2]; - assign router_1_2_to_router_0_2_req = router_1_2_req_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_req = router_1_2_req_out[4]; - - assign router_1_2_rsp_in[0] = router_1_3_to_router_1_2_rsp; - assign router_1_2_rsp_in[1] = router_2_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[2] = router_1_1_to_router_1_2_rsp; - assign router_1_2_rsp_in[3] = router_0_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[4] = magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_2_req_in), - .floo_rsp_o (router_1_2_rsp_out), - .floo_req_o (router_1_2_req_out), - .floo_rsp_i (router_1_2_rsp_in) -); - - -floo_req_t [4:0] router_1_3_req_in; -floo_rsp_t [4:0] router_1_3_rsp_out; -floo_req_t [4:0] router_1_3_req_out; -floo_rsp_t [4:0] router_1_3_rsp_in; - - assign router_1_3_req_in[0] = router_1_4_to_router_1_3_req; - assign router_1_3_req_in[1] = router_2_3_to_router_1_3_req; - assign router_1_3_req_in[2] = router_1_2_to_router_1_3_req; - assign router_1_3_req_in[3] = router_0_3_to_router_1_3_req; - assign router_1_3_req_in[4] = magia_tile_ni_1_3_to_router_1_3_req; - - assign router_1_3_to_router_1_4_rsp = router_1_3_rsp_out[0]; - assign router_1_3_to_router_2_3_rsp = router_1_3_rsp_out[1]; - assign router_1_3_to_router_1_2_rsp = router_1_3_rsp_out[2]; - assign router_1_3_to_router_0_3_rsp = router_1_3_rsp_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_rsp = router_1_3_rsp_out[4]; - - assign router_1_3_to_router_1_4_req = router_1_3_req_out[0]; - assign router_1_3_to_router_2_3_req = router_1_3_req_out[1]; - assign router_1_3_to_router_1_2_req = router_1_3_req_out[2]; - assign router_1_3_to_router_0_3_req = router_1_3_req_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_req = router_1_3_req_out[4]; - - assign router_1_3_rsp_in[0] = router_1_4_to_router_1_3_rsp; - assign router_1_3_rsp_in[1] = router_2_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[2] = router_1_2_to_router_1_3_rsp; - assign router_1_3_rsp_in[3] = router_0_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[4] = magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_3_req_in), - .floo_rsp_o (router_1_3_rsp_out), - .floo_req_o (router_1_3_req_out), - .floo_rsp_i (router_1_3_rsp_in) -); - - -floo_req_t [4:0] router_1_4_req_in; -floo_rsp_t [4:0] router_1_4_rsp_out; -floo_req_t [4:0] router_1_4_req_out; -floo_rsp_t [4:0] router_1_4_rsp_in; - - assign router_1_4_req_in[0] = router_1_5_to_router_1_4_req; - assign router_1_4_req_in[1] = router_2_4_to_router_1_4_req; - assign router_1_4_req_in[2] = router_1_3_to_router_1_4_req; - assign router_1_4_req_in[3] = router_0_4_to_router_1_4_req; - assign router_1_4_req_in[4] = magia_tile_ni_1_4_to_router_1_4_req; - - assign router_1_4_to_router_1_5_rsp = router_1_4_rsp_out[0]; - assign router_1_4_to_router_2_4_rsp = router_1_4_rsp_out[1]; - assign router_1_4_to_router_1_3_rsp = router_1_4_rsp_out[2]; - assign router_1_4_to_router_0_4_rsp = router_1_4_rsp_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_rsp = router_1_4_rsp_out[4]; - - assign router_1_4_to_router_1_5_req = router_1_4_req_out[0]; - assign router_1_4_to_router_2_4_req = router_1_4_req_out[1]; - assign router_1_4_to_router_1_3_req = router_1_4_req_out[2]; - assign router_1_4_to_router_0_4_req = router_1_4_req_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_req = router_1_4_req_out[4]; - - assign router_1_4_rsp_in[0] = router_1_5_to_router_1_4_rsp; - assign router_1_4_rsp_in[1] = router_2_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[2] = router_1_3_to_router_1_4_rsp; - assign router_1_4_rsp_in[3] = router_0_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[4] = magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_4_req_in), - .floo_rsp_o (router_1_4_rsp_out), - .floo_req_o (router_1_4_req_out), - .floo_rsp_i (router_1_4_rsp_in) -); - - -floo_req_t [4:0] router_1_5_req_in; -floo_rsp_t [4:0] router_1_5_rsp_out; -floo_req_t [4:0] router_1_5_req_out; -floo_rsp_t [4:0] router_1_5_rsp_in; - - assign router_1_5_req_in[0] = router_1_6_to_router_1_5_req; - assign router_1_5_req_in[1] = router_2_5_to_router_1_5_req; - assign router_1_5_req_in[2] = router_1_4_to_router_1_5_req; - assign router_1_5_req_in[3] = router_0_5_to_router_1_5_req; - assign router_1_5_req_in[4] = magia_tile_ni_1_5_to_router_1_5_req; - - assign router_1_5_to_router_1_6_rsp = router_1_5_rsp_out[0]; - assign router_1_5_to_router_2_5_rsp = router_1_5_rsp_out[1]; - assign router_1_5_to_router_1_4_rsp = router_1_5_rsp_out[2]; - assign router_1_5_to_router_0_5_rsp = router_1_5_rsp_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_rsp = router_1_5_rsp_out[4]; - - assign router_1_5_to_router_1_6_req = router_1_5_req_out[0]; - assign router_1_5_to_router_2_5_req = router_1_5_req_out[1]; - assign router_1_5_to_router_1_4_req = router_1_5_req_out[2]; - assign router_1_5_to_router_0_5_req = router_1_5_req_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_req = router_1_5_req_out[4]; - - assign router_1_5_rsp_in[0] = router_1_6_to_router_1_5_rsp; - assign router_1_5_rsp_in[1] = router_2_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[2] = router_1_4_to_router_1_5_rsp; - assign router_1_5_rsp_in[3] = router_0_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[4] = magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_5_req_in), - .floo_rsp_o (router_1_5_rsp_out), - .floo_req_o (router_1_5_req_out), - .floo_rsp_i (router_1_5_rsp_in) -); - - -floo_req_t [4:0] router_1_6_req_in; -floo_rsp_t [4:0] router_1_6_rsp_out; -floo_req_t [4:0] router_1_6_req_out; -floo_rsp_t [4:0] router_1_6_rsp_in; - - assign router_1_6_req_in[0] = router_1_7_to_router_1_6_req; - assign router_1_6_req_in[1] = router_2_6_to_router_1_6_req; - assign router_1_6_req_in[2] = router_1_5_to_router_1_6_req; - assign router_1_6_req_in[3] = router_0_6_to_router_1_6_req; - assign router_1_6_req_in[4] = magia_tile_ni_1_6_to_router_1_6_req; - - assign router_1_6_to_router_1_7_rsp = router_1_6_rsp_out[0]; - assign router_1_6_to_router_2_6_rsp = router_1_6_rsp_out[1]; - assign router_1_6_to_router_1_5_rsp = router_1_6_rsp_out[2]; - assign router_1_6_to_router_0_6_rsp = router_1_6_rsp_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_rsp = router_1_6_rsp_out[4]; - - assign router_1_6_to_router_1_7_req = router_1_6_req_out[0]; - assign router_1_6_to_router_2_6_req = router_1_6_req_out[1]; - assign router_1_6_to_router_1_5_req = router_1_6_req_out[2]; - assign router_1_6_to_router_0_6_req = router_1_6_req_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_req = router_1_6_req_out[4]; - - assign router_1_6_rsp_in[0] = router_1_7_to_router_1_6_rsp; - assign router_1_6_rsp_in[1] = router_2_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[2] = router_1_5_to_router_1_6_rsp; - assign router_1_6_rsp_in[3] = router_0_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[4] = magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_6_req_in), - .floo_rsp_o (router_1_6_rsp_out), - .floo_req_o (router_1_6_req_out), - .floo_rsp_i (router_1_6_rsp_in) -); - - -floo_req_t [4:0] router_1_7_req_in; -floo_rsp_t [4:0] router_1_7_rsp_out; -floo_req_t [4:0] router_1_7_req_out; -floo_rsp_t [4:0] router_1_7_rsp_in; - - assign router_1_7_req_in[0] = router_1_8_to_router_1_7_req; - assign router_1_7_req_in[1] = router_2_7_to_router_1_7_req; - assign router_1_7_req_in[2] = router_1_6_to_router_1_7_req; - assign router_1_7_req_in[3] = router_0_7_to_router_1_7_req; - assign router_1_7_req_in[4] = magia_tile_ni_1_7_to_router_1_7_req; - - assign router_1_7_to_router_1_8_rsp = router_1_7_rsp_out[0]; - assign router_1_7_to_router_2_7_rsp = router_1_7_rsp_out[1]; - assign router_1_7_to_router_1_6_rsp = router_1_7_rsp_out[2]; - assign router_1_7_to_router_0_7_rsp = router_1_7_rsp_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_rsp = router_1_7_rsp_out[4]; - - assign router_1_7_to_router_1_8_req = router_1_7_req_out[0]; - assign router_1_7_to_router_2_7_req = router_1_7_req_out[1]; - assign router_1_7_to_router_1_6_req = router_1_7_req_out[2]; - assign router_1_7_to_router_0_7_req = router_1_7_req_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_req = router_1_7_req_out[4]; - - assign router_1_7_rsp_in[0] = router_1_8_to_router_1_7_rsp; - assign router_1_7_rsp_in[1] = router_2_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[2] = router_1_6_to_router_1_7_rsp; - assign router_1_7_rsp_in[3] = router_0_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[4] = magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_7_req_in), - .floo_rsp_o (router_1_7_rsp_out), - .floo_req_o (router_1_7_req_out), - .floo_rsp_i (router_1_7_rsp_in) -); - - -floo_req_t [4:0] router_1_8_req_in; -floo_rsp_t [4:0] router_1_8_rsp_out; -floo_req_t [4:0] router_1_8_req_out; -floo_rsp_t [4:0] router_1_8_rsp_in; - - assign router_1_8_req_in[0] = router_1_9_to_router_1_8_req; - assign router_1_8_req_in[1] = router_2_8_to_router_1_8_req; - assign router_1_8_req_in[2] = router_1_7_to_router_1_8_req; - assign router_1_8_req_in[3] = router_0_8_to_router_1_8_req; - assign router_1_8_req_in[4] = magia_tile_ni_1_8_to_router_1_8_req; - - assign router_1_8_to_router_1_9_rsp = router_1_8_rsp_out[0]; - assign router_1_8_to_router_2_8_rsp = router_1_8_rsp_out[1]; - assign router_1_8_to_router_1_7_rsp = router_1_8_rsp_out[2]; - assign router_1_8_to_router_0_8_rsp = router_1_8_rsp_out[3]; - assign router_1_8_to_magia_tile_ni_1_8_rsp = router_1_8_rsp_out[4]; - - assign router_1_8_to_router_1_9_req = router_1_8_req_out[0]; - assign router_1_8_to_router_2_8_req = router_1_8_req_out[1]; - assign router_1_8_to_router_1_7_req = router_1_8_req_out[2]; - assign router_1_8_to_router_0_8_req = router_1_8_req_out[3]; - assign router_1_8_to_magia_tile_ni_1_8_req = router_1_8_req_out[4]; - - assign router_1_8_rsp_in[0] = router_1_9_to_router_1_8_rsp; - assign router_1_8_rsp_in[1] = router_2_8_to_router_1_8_rsp; - assign router_1_8_rsp_in[2] = router_1_7_to_router_1_8_rsp; - assign router_1_8_rsp_in[3] = router_0_8_to_router_1_8_rsp; - assign router_1_8_rsp_in[4] = magia_tile_ni_1_8_to_router_1_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_8_req_in), - .floo_rsp_o (router_1_8_rsp_out), - .floo_req_o (router_1_8_req_out), - .floo_rsp_i (router_1_8_rsp_in) -); - - -floo_req_t [4:0] router_1_9_req_in; -floo_rsp_t [4:0] router_1_9_rsp_out; -floo_req_t [4:0] router_1_9_req_out; -floo_rsp_t [4:0] router_1_9_rsp_in; - - assign router_1_9_req_in[0] = router_1_10_to_router_1_9_req; - assign router_1_9_req_in[1] = router_2_9_to_router_1_9_req; - assign router_1_9_req_in[2] = router_1_8_to_router_1_9_req; - assign router_1_9_req_in[3] = router_0_9_to_router_1_9_req; - assign router_1_9_req_in[4] = magia_tile_ni_1_9_to_router_1_9_req; - - assign router_1_9_to_router_1_10_rsp = router_1_9_rsp_out[0]; - assign router_1_9_to_router_2_9_rsp = router_1_9_rsp_out[1]; - assign router_1_9_to_router_1_8_rsp = router_1_9_rsp_out[2]; - assign router_1_9_to_router_0_9_rsp = router_1_9_rsp_out[3]; - assign router_1_9_to_magia_tile_ni_1_9_rsp = router_1_9_rsp_out[4]; - - assign router_1_9_to_router_1_10_req = router_1_9_req_out[0]; - assign router_1_9_to_router_2_9_req = router_1_9_req_out[1]; - assign router_1_9_to_router_1_8_req = router_1_9_req_out[2]; - assign router_1_9_to_router_0_9_req = router_1_9_req_out[3]; - assign router_1_9_to_magia_tile_ni_1_9_req = router_1_9_req_out[4]; - - assign router_1_9_rsp_in[0] = router_1_10_to_router_1_9_rsp; - assign router_1_9_rsp_in[1] = router_2_9_to_router_1_9_rsp; - assign router_1_9_rsp_in[2] = router_1_8_to_router_1_9_rsp; - assign router_1_9_rsp_in[3] = router_0_9_to_router_1_9_rsp; - assign router_1_9_rsp_in[4] = magia_tile_ni_1_9_to_router_1_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_9_req_in), - .floo_rsp_o (router_1_9_rsp_out), - .floo_req_o (router_1_9_req_out), - .floo_rsp_i (router_1_9_rsp_in) -); - - -floo_req_t [4:0] router_1_10_req_in; -floo_rsp_t [4:0] router_1_10_rsp_out; -floo_req_t [4:0] router_1_10_req_out; -floo_rsp_t [4:0] router_1_10_rsp_in; - - assign router_1_10_req_in[0] = router_1_11_to_router_1_10_req; - assign router_1_10_req_in[1] = router_2_10_to_router_1_10_req; - assign router_1_10_req_in[2] = router_1_9_to_router_1_10_req; - assign router_1_10_req_in[3] = router_0_10_to_router_1_10_req; - assign router_1_10_req_in[4] = magia_tile_ni_1_10_to_router_1_10_req; - - assign router_1_10_to_router_1_11_rsp = router_1_10_rsp_out[0]; - assign router_1_10_to_router_2_10_rsp = router_1_10_rsp_out[1]; - assign router_1_10_to_router_1_9_rsp = router_1_10_rsp_out[2]; - assign router_1_10_to_router_0_10_rsp = router_1_10_rsp_out[3]; - assign router_1_10_to_magia_tile_ni_1_10_rsp = router_1_10_rsp_out[4]; - - assign router_1_10_to_router_1_11_req = router_1_10_req_out[0]; - assign router_1_10_to_router_2_10_req = router_1_10_req_out[1]; - assign router_1_10_to_router_1_9_req = router_1_10_req_out[2]; - assign router_1_10_to_router_0_10_req = router_1_10_req_out[3]; - assign router_1_10_to_magia_tile_ni_1_10_req = router_1_10_req_out[4]; - - assign router_1_10_rsp_in[0] = router_1_11_to_router_1_10_rsp; - assign router_1_10_rsp_in[1] = router_2_10_to_router_1_10_rsp; - assign router_1_10_rsp_in[2] = router_1_9_to_router_1_10_rsp; - assign router_1_10_rsp_in[3] = router_0_10_to_router_1_10_rsp; - assign router_1_10_rsp_in[4] = magia_tile_ni_1_10_to_router_1_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_10_req_in), - .floo_rsp_o (router_1_10_rsp_out), - .floo_req_o (router_1_10_req_out), - .floo_rsp_i (router_1_10_rsp_in) -); - - -floo_req_t [4:0] router_1_11_req_in; -floo_rsp_t [4:0] router_1_11_rsp_out; -floo_req_t [4:0] router_1_11_req_out; -floo_rsp_t [4:0] router_1_11_rsp_in; - - assign router_1_11_req_in[0] = router_1_12_to_router_1_11_req; - assign router_1_11_req_in[1] = router_2_11_to_router_1_11_req; - assign router_1_11_req_in[2] = router_1_10_to_router_1_11_req; - assign router_1_11_req_in[3] = router_0_11_to_router_1_11_req; - assign router_1_11_req_in[4] = magia_tile_ni_1_11_to_router_1_11_req; - - assign router_1_11_to_router_1_12_rsp = router_1_11_rsp_out[0]; - assign router_1_11_to_router_2_11_rsp = router_1_11_rsp_out[1]; - assign router_1_11_to_router_1_10_rsp = router_1_11_rsp_out[2]; - assign router_1_11_to_router_0_11_rsp = router_1_11_rsp_out[3]; - assign router_1_11_to_magia_tile_ni_1_11_rsp = router_1_11_rsp_out[4]; - - assign router_1_11_to_router_1_12_req = router_1_11_req_out[0]; - assign router_1_11_to_router_2_11_req = router_1_11_req_out[1]; - assign router_1_11_to_router_1_10_req = router_1_11_req_out[2]; - assign router_1_11_to_router_0_11_req = router_1_11_req_out[3]; - assign router_1_11_to_magia_tile_ni_1_11_req = router_1_11_req_out[4]; - - assign router_1_11_rsp_in[0] = router_1_12_to_router_1_11_rsp; - assign router_1_11_rsp_in[1] = router_2_11_to_router_1_11_rsp; - assign router_1_11_rsp_in[2] = router_1_10_to_router_1_11_rsp; - assign router_1_11_rsp_in[3] = router_0_11_to_router_1_11_rsp; - assign router_1_11_rsp_in[4] = magia_tile_ni_1_11_to_router_1_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_11_req_in), - .floo_rsp_o (router_1_11_rsp_out), - .floo_req_o (router_1_11_req_out), - .floo_rsp_i (router_1_11_rsp_in) -); - - -floo_req_t [4:0] router_1_12_req_in; -floo_rsp_t [4:0] router_1_12_rsp_out; -floo_req_t [4:0] router_1_12_req_out; -floo_rsp_t [4:0] router_1_12_rsp_in; - - assign router_1_12_req_in[0] = router_1_13_to_router_1_12_req; - assign router_1_12_req_in[1] = router_2_12_to_router_1_12_req; - assign router_1_12_req_in[2] = router_1_11_to_router_1_12_req; - assign router_1_12_req_in[3] = router_0_12_to_router_1_12_req; - assign router_1_12_req_in[4] = magia_tile_ni_1_12_to_router_1_12_req; - - assign router_1_12_to_router_1_13_rsp = router_1_12_rsp_out[0]; - assign router_1_12_to_router_2_12_rsp = router_1_12_rsp_out[1]; - assign router_1_12_to_router_1_11_rsp = router_1_12_rsp_out[2]; - assign router_1_12_to_router_0_12_rsp = router_1_12_rsp_out[3]; - assign router_1_12_to_magia_tile_ni_1_12_rsp = router_1_12_rsp_out[4]; - - assign router_1_12_to_router_1_13_req = router_1_12_req_out[0]; - assign router_1_12_to_router_2_12_req = router_1_12_req_out[1]; - assign router_1_12_to_router_1_11_req = router_1_12_req_out[2]; - assign router_1_12_to_router_0_12_req = router_1_12_req_out[3]; - assign router_1_12_to_magia_tile_ni_1_12_req = router_1_12_req_out[4]; - - assign router_1_12_rsp_in[0] = router_1_13_to_router_1_12_rsp; - assign router_1_12_rsp_in[1] = router_2_12_to_router_1_12_rsp; - assign router_1_12_rsp_in[2] = router_1_11_to_router_1_12_rsp; - assign router_1_12_rsp_in[3] = router_0_12_to_router_1_12_rsp; - assign router_1_12_rsp_in[4] = magia_tile_ni_1_12_to_router_1_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_12_req_in), - .floo_rsp_o (router_1_12_rsp_out), - .floo_req_o (router_1_12_req_out), - .floo_rsp_i (router_1_12_rsp_in) -); - - -floo_req_t [4:0] router_1_13_req_in; -floo_rsp_t [4:0] router_1_13_rsp_out; -floo_req_t [4:0] router_1_13_req_out; -floo_rsp_t [4:0] router_1_13_rsp_in; - - assign router_1_13_req_in[0] = router_1_14_to_router_1_13_req; - assign router_1_13_req_in[1] = router_2_13_to_router_1_13_req; - assign router_1_13_req_in[2] = router_1_12_to_router_1_13_req; - assign router_1_13_req_in[3] = router_0_13_to_router_1_13_req; - assign router_1_13_req_in[4] = magia_tile_ni_1_13_to_router_1_13_req; - - assign router_1_13_to_router_1_14_rsp = router_1_13_rsp_out[0]; - assign router_1_13_to_router_2_13_rsp = router_1_13_rsp_out[1]; - assign router_1_13_to_router_1_12_rsp = router_1_13_rsp_out[2]; - assign router_1_13_to_router_0_13_rsp = router_1_13_rsp_out[3]; - assign router_1_13_to_magia_tile_ni_1_13_rsp = router_1_13_rsp_out[4]; - - assign router_1_13_to_router_1_14_req = router_1_13_req_out[0]; - assign router_1_13_to_router_2_13_req = router_1_13_req_out[1]; - assign router_1_13_to_router_1_12_req = router_1_13_req_out[2]; - assign router_1_13_to_router_0_13_req = router_1_13_req_out[3]; - assign router_1_13_to_magia_tile_ni_1_13_req = router_1_13_req_out[4]; - - assign router_1_13_rsp_in[0] = router_1_14_to_router_1_13_rsp; - assign router_1_13_rsp_in[1] = router_2_13_to_router_1_13_rsp; - assign router_1_13_rsp_in[2] = router_1_12_to_router_1_13_rsp; - assign router_1_13_rsp_in[3] = router_0_13_to_router_1_13_rsp; - assign router_1_13_rsp_in[4] = magia_tile_ni_1_13_to_router_1_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_13_req_in), - .floo_rsp_o (router_1_13_rsp_out), - .floo_req_o (router_1_13_req_out), - .floo_rsp_i (router_1_13_rsp_in) -); - - -floo_req_t [4:0] router_1_14_req_in; -floo_rsp_t [4:0] router_1_14_rsp_out; -floo_req_t [4:0] router_1_14_req_out; -floo_rsp_t [4:0] router_1_14_rsp_in; - - assign router_1_14_req_in[0] = router_1_15_to_router_1_14_req; - assign router_1_14_req_in[1] = router_2_14_to_router_1_14_req; - assign router_1_14_req_in[2] = router_1_13_to_router_1_14_req; - assign router_1_14_req_in[3] = router_0_14_to_router_1_14_req; - assign router_1_14_req_in[4] = magia_tile_ni_1_14_to_router_1_14_req; - - assign router_1_14_to_router_1_15_rsp = router_1_14_rsp_out[0]; - assign router_1_14_to_router_2_14_rsp = router_1_14_rsp_out[1]; - assign router_1_14_to_router_1_13_rsp = router_1_14_rsp_out[2]; - assign router_1_14_to_router_0_14_rsp = router_1_14_rsp_out[3]; - assign router_1_14_to_magia_tile_ni_1_14_rsp = router_1_14_rsp_out[4]; - - assign router_1_14_to_router_1_15_req = router_1_14_req_out[0]; - assign router_1_14_to_router_2_14_req = router_1_14_req_out[1]; - assign router_1_14_to_router_1_13_req = router_1_14_req_out[2]; - assign router_1_14_to_router_0_14_req = router_1_14_req_out[3]; - assign router_1_14_to_magia_tile_ni_1_14_req = router_1_14_req_out[4]; - - assign router_1_14_rsp_in[0] = router_1_15_to_router_1_14_rsp; - assign router_1_14_rsp_in[1] = router_2_14_to_router_1_14_rsp; - assign router_1_14_rsp_in[2] = router_1_13_to_router_1_14_rsp; - assign router_1_14_rsp_in[3] = router_0_14_to_router_1_14_rsp; - assign router_1_14_rsp_in[4] = magia_tile_ni_1_14_to_router_1_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_14_req_in), - .floo_rsp_o (router_1_14_rsp_out), - .floo_req_o (router_1_14_req_out), - .floo_rsp_i (router_1_14_rsp_in) -); - - -floo_req_t [4:0] router_1_15_req_in; -floo_rsp_t [4:0] router_1_15_rsp_out; -floo_req_t [4:0] router_1_15_req_out; -floo_rsp_t [4:0] router_1_15_rsp_in; - - assign router_1_15_req_in[0] = router_1_16_to_router_1_15_req; - assign router_1_15_req_in[1] = router_2_15_to_router_1_15_req; - assign router_1_15_req_in[2] = router_1_14_to_router_1_15_req; - assign router_1_15_req_in[3] = router_0_15_to_router_1_15_req; - assign router_1_15_req_in[4] = magia_tile_ni_1_15_to_router_1_15_req; - - assign router_1_15_to_router_1_16_rsp = router_1_15_rsp_out[0]; - assign router_1_15_to_router_2_15_rsp = router_1_15_rsp_out[1]; - assign router_1_15_to_router_1_14_rsp = router_1_15_rsp_out[2]; - assign router_1_15_to_router_0_15_rsp = router_1_15_rsp_out[3]; - assign router_1_15_to_magia_tile_ni_1_15_rsp = router_1_15_rsp_out[4]; - - assign router_1_15_to_router_1_16_req = router_1_15_req_out[0]; - assign router_1_15_to_router_2_15_req = router_1_15_req_out[1]; - assign router_1_15_to_router_1_14_req = router_1_15_req_out[2]; - assign router_1_15_to_router_0_15_req = router_1_15_req_out[3]; - assign router_1_15_to_magia_tile_ni_1_15_req = router_1_15_req_out[4]; - - assign router_1_15_rsp_in[0] = router_1_16_to_router_1_15_rsp; - assign router_1_15_rsp_in[1] = router_2_15_to_router_1_15_rsp; - assign router_1_15_rsp_in[2] = router_1_14_to_router_1_15_rsp; - assign router_1_15_rsp_in[3] = router_0_15_to_router_1_15_rsp; - assign router_1_15_rsp_in[4] = magia_tile_ni_1_15_to_router_1_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_15_req_in), - .floo_rsp_o (router_1_15_rsp_out), - .floo_req_o (router_1_15_req_out), - .floo_rsp_i (router_1_15_rsp_in) -); - - -floo_req_t [4:0] router_1_16_req_in; -floo_rsp_t [4:0] router_1_16_rsp_out; -floo_req_t [4:0] router_1_16_req_out; -floo_rsp_t [4:0] router_1_16_rsp_in; - - assign router_1_16_req_in[0] = router_1_17_to_router_1_16_req; - assign router_1_16_req_in[1] = router_2_16_to_router_1_16_req; - assign router_1_16_req_in[2] = router_1_15_to_router_1_16_req; - assign router_1_16_req_in[3] = router_0_16_to_router_1_16_req; - assign router_1_16_req_in[4] = magia_tile_ni_1_16_to_router_1_16_req; - - assign router_1_16_to_router_1_17_rsp = router_1_16_rsp_out[0]; - assign router_1_16_to_router_2_16_rsp = router_1_16_rsp_out[1]; - assign router_1_16_to_router_1_15_rsp = router_1_16_rsp_out[2]; - assign router_1_16_to_router_0_16_rsp = router_1_16_rsp_out[3]; - assign router_1_16_to_magia_tile_ni_1_16_rsp = router_1_16_rsp_out[4]; - - assign router_1_16_to_router_1_17_req = router_1_16_req_out[0]; - assign router_1_16_to_router_2_16_req = router_1_16_req_out[1]; - assign router_1_16_to_router_1_15_req = router_1_16_req_out[2]; - assign router_1_16_to_router_0_16_req = router_1_16_req_out[3]; - assign router_1_16_to_magia_tile_ni_1_16_req = router_1_16_req_out[4]; - - assign router_1_16_rsp_in[0] = router_1_17_to_router_1_16_rsp; - assign router_1_16_rsp_in[1] = router_2_16_to_router_1_16_rsp; - assign router_1_16_rsp_in[2] = router_1_15_to_router_1_16_rsp; - assign router_1_16_rsp_in[3] = router_0_16_to_router_1_16_rsp; - assign router_1_16_rsp_in[4] = magia_tile_ni_1_16_to_router_1_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_16_req_in), - .floo_rsp_o (router_1_16_rsp_out), - .floo_req_o (router_1_16_req_out), - .floo_rsp_i (router_1_16_rsp_in) -); - - -floo_req_t [4:0] router_1_17_req_in; -floo_rsp_t [4:0] router_1_17_rsp_out; -floo_req_t [4:0] router_1_17_req_out; -floo_rsp_t [4:0] router_1_17_rsp_in; - - assign router_1_17_req_in[0] = router_1_18_to_router_1_17_req; - assign router_1_17_req_in[1] = router_2_17_to_router_1_17_req; - assign router_1_17_req_in[2] = router_1_16_to_router_1_17_req; - assign router_1_17_req_in[3] = router_0_17_to_router_1_17_req; - assign router_1_17_req_in[4] = magia_tile_ni_1_17_to_router_1_17_req; - - assign router_1_17_to_router_1_18_rsp = router_1_17_rsp_out[0]; - assign router_1_17_to_router_2_17_rsp = router_1_17_rsp_out[1]; - assign router_1_17_to_router_1_16_rsp = router_1_17_rsp_out[2]; - assign router_1_17_to_router_0_17_rsp = router_1_17_rsp_out[3]; - assign router_1_17_to_magia_tile_ni_1_17_rsp = router_1_17_rsp_out[4]; - - assign router_1_17_to_router_1_18_req = router_1_17_req_out[0]; - assign router_1_17_to_router_2_17_req = router_1_17_req_out[1]; - assign router_1_17_to_router_1_16_req = router_1_17_req_out[2]; - assign router_1_17_to_router_0_17_req = router_1_17_req_out[3]; - assign router_1_17_to_magia_tile_ni_1_17_req = router_1_17_req_out[4]; - - assign router_1_17_rsp_in[0] = router_1_18_to_router_1_17_rsp; - assign router_1_17_rsp_in[1] = router_2_17_to_router_1_17_rsp; - assign router_1_17_rsp_in[2] = router_1_16_to_router_1_17_rsp; - assign router_1_17_rsp_in[3] = router_0_17_to_router_1_17_rsp; - assign router_1_17_rsp_in[4] = magia_tile_ni_1_17_to_router_1_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_17_req_in), - .floo_rsp_o (router_1_17_rsp_out), - .floo_req_o (router_1_17_req_out), - .floo_rsp_i (router_1_17_rsp_in) -); - - -floo_req_t [4:0] router_1_18_req_in; -floo_rsp_t [4:0] router_1_18_rsp_out; -floo_req_t [4:0] router_1_18_req_out; -floo_rsp_t [4:0] router_1_18_rsp_in; - - assign router_1_18_req_in[0] = router_1_19_to_router_1_18_req; - assign router_1_18_req_in[1] = router_2_18_to_router_1_18_req; - assign router_1_18_req_in[2] = router_1_17_to_router_1_18_req; - assign router_1_18_req_in[3] = router_0_18_to_router_1_18_req; - assign router_1_18_req_in[4] = magia_tile_ni_1_18_to_router_1_18_req; - - assign router_1_18_to_router_1_19_rsp = router_1_18_rsp_out[0]; - assign router_1_18_to_router_2_18_rsp = router_1_18_rsp_out[1]; - assign router_1_18_to_router_1_17_rsp = router_1_18_rsp_out[2]; - assign router_1_18_to_router_0_18_rsp = router_1_18_rsp_out[3]; - assign router_1_18_to_magia_tile_ni_1_18_rsp = router_1_18_rsp_out[4]; - - assign router_1_18_to_router_1_19_req = router_1_18_req_out[0]; - assign router_1_18_to_router_2_18_req = router_1_18_req_out[1]; - assign router_1_18_to_router_1_17_req = router_1_18_req_out[2]; - assign router_1_18_to_router_0_18_req = router_1_18_req_out[3]; - assign router_1_18_to_magia_tile_ni_1_18_req = router_1_18_req_out[4]; - - assign router_1_18_rsp_in[0] = router_1_19_to_router_1_18_rsp; - assign router_1_18_rsp_in[1] = router_2_18_to_router_1_18_rsp; - assign router_1_18_rsp_in[2] = router_1_17_to_router_1_18_rsp; - assign router_1_18_rsp_in[3] = router_0_18_to_router_1_18_rsp; - assign router_1_18_rsp_in[4] = magia_tile_ni_1_18_to_router_1_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_18_req_in), - .floo_rsp_o (router_1_18_rsp_out), - .floo_req_o (router_1_18_req_out), - .floo_rsp_i (router_1_18_rsp_in) -); - - -floo_req_t [4:0] router_1_19_req_in; -floo_rsp_t [4:0] router_1_19_rsp_out; -floo_req_t [4:0] router_1_19_req_out; -floo_rsp_t [4:0] router_1_19_rsp_in; - - assign router_1_19_req_in[0] = router_1_20_to_router_1_19_req; - assign router_1_19_req_in[1] = router_2_19_to_router_1_19_req; - assign router_1_19_req_in[2] = router_1_18_to_router_1_19_req; - assign router_1_19_req_in[3] = router_0_19_to_router_1_19_req; - assign router_1_19_req_in[4] = magia_tile_ni_1_19_to_router_1_19_req; - - assign router_1_19_to_router_1_20_rsp = router_1_19_rsp_out[0]; - assign router_1_19_to_router_2_19_rsp = router_1_19_rsp_out[1]; - assign router_1_19_to_router_1_18_rsp = router_1_19_rsp_out[2]; - assign router_1_19_to_router_0_19_rsp = router_1_19_rsp_out[3]; - assign router_1_19_to_magia_tile_ni_1_19_rsp = router_1_19_rsp_out[4]; - - assign router_1_19_to_router_1_20_req = router_1_19_req_out[0]; - assign router_1_19_to_router_2_19_req = router_1_19_req_out[1]; - assign router_1_19_to_router_1_18_req = router_1_19_req_out[2]; - assign router_1_19_to_router_0_19_req = router_1_19_req_out[3]; - assign router_1_19_to_magia_tile_ni_1_19_req = router_1_19_req_out[4]; - - assign router_1_19_rsp_in[0] = router_1_20_to_router_1_19_rsp; - assign router_1_19_rsp_in[1] = router_2_19_to_router_1_19_rsp; - assign router_1_19_rsp_in[2] = router_1_18_to_router_1_19_rsp; - assign router_1_19_rsp_in[3] = router_0_19_to_router_1_19_rsp; - assign router_1_19_rsp_in[4] = magia_tile_ni_1_19_to_router_1_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_19_req_in), - .floo_rsp_o (router_1_19_rsp_out), - .floo_req_o (router_1_19_req_out), - .floo_rsp_i (router_1_19_rsp_in) -); - - -floo_req_t [4:0] router_1_20_req_in; -floo_rsp_t [4:0] router_1_20_rsp_out; -floo_req_t [4:0] router_1_20_req_out; -floo_rsp_t [4:0] router_1_20_rsp_in; - - assign router_1_20_req_in[0] = router_1_21_to_router_1_20_req; - assign router_1_20_req_in[1] = router_2_20_to_router_1_20_req; - assign router_1_20_req_in[2] = router_1_19_to_router_1_20_req; - assign router_1_20_req_in[3] = router_0_20_to_router_1_20_req; - assign router_1_20_req_in[4] = magia_tile_ni_1_20_to_router_1_20_req; - - assign router_1_20_to_router_1_21_rsp = router_1_20_rsp_out[0]; - assign router_1_20_to_router_2_20_rsp = router_1_20_rsp_out[1]; - assign router_1_20_to_router_1_19_rsp = router_1_20_rsp_out[2]; - assign router_1_20_to_router_0_20_rsp = router_1_20_rsp_out[3]; - assign router_1_20_to_magia_tile_ni_1_20_rsp = router_1_20_rsp_out[4]; - - assign router_1_20_to_router_1_21_req = router_1_20_req_out[0]; - assign router_1_20_to_router_2_20_req = router_1_20_req_out[1]; - assign router_1_20_to_router_1_19_req = router_1_20_req_out[2]; - assign router_1_20_to_router_0_20_req = router_1_20_req_out[3]; - assign router_1_20_to_magia_tile_ni_1_20_req = router_1_20_req_out[4]; - - assign router_1_20_rsp_in[0] = router_1_21_to_router_1_20_rsp; - assign router_1_20_rsp_in[1] = router_2_20_to_router_1_20_rsp; - assign router_1_20_rsp_in[2] = router_1_19_to_router_1_20_rsp; - assign router_1_20_rsp_in[3] = router_0_20_to_router_1_20_rsp; - assign router_1_20_rsp_in[4] = magia_tile_ni_1_20_to_router_1_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_20_req_in), - .floo_rsp_o (router_1_20_rsp_out), - .floo_req_o (router_1_20_req_out), - .floo_rsp_i (router_1_20_rsp_in) -); - - -floo_req_t [4:0] router_1_21_req_in; -floo_rsp_t [4:0] router_1_21_rsp_out; -floo_req_t [4:0] router_1_21_req_out; -floo_rsp_t [4:0] router_1_21_rsp_in; - - assign router_1_21_req_in[0] = router_1_22_to_router_1_21_req; - assign router_1_21_req_in[1] = router_2_21_to_router_1_21_req; - assign router_1_21_req_in[2] = router_1_20_to_router_1_21_req; - assign router_1_21_req_in[3] = router_0_21_to_router_1_21_req; - assign router_1_21_req_in[4] = magia_tile_ni_1_21_to_router_1_21_req; - - assign router_1_21_to_router_1_22_rsp = router_1_21_rsp_out[0]; - assign router_1_21_to_router_2_21_rsp = router_1_21_rsp_out[1]; - assign router_1_21_to_router_1_20_rsp = router_1_21_rsp_out[2]; - assign router_1_21_to_router_0_21_rsp = router_1_21_rsp_out[3]; - assign router_1_21_to_magia_tile_ni_1_21_rsp = router_1_21_rsp_out[4]; - - assign router_1_21_to_router_1_22_req = router_1_21_req_out[0]; - assign router_1_21_to_router_2_21_req = router_1_21_req_out[1]; - assign router_1_21_to_router_1_20_req = router_1_21_req_out[2]; - assign router_1_21_to_router_0_21_req = router_1_21_req_out[3]; - assign router_1_21_to_magia_tile_ni_1_21_req = router_1_21_req_out[4]; - - assign router_1_21_rsp_in[0] = router_1_22_to_router_1_21_rsp; - assign router_1_21_rsp_in[1] = router_2_21_to_router_1_21_rsp; - assign router_1_21_rsp_in[2] = router_1_20_to_router_1_21_rsp; - assign router_1_21_rsp_in[3] = router_0_21_to_router_1_21_rsp; - assign router_1_21_rsp_in[4] = magia_tile_ni_1_21_to_router_1_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_21_req_in), - .floo_rsp_o (router_1_21_rsp_out), - .floo_req_o (router_1_21_req_out), - .floo_rsp_i (router_1_21_rsp_in) -); - - -floo_req_t [4:0] router_1_22_req_in; -floo_rsp_t [4:0] router_1_22_rsp_out; -floo_req_t [4:0] router_1_22_req_out; -floo_rsp_t [4:0] router_1_22_rsp_in; - - assign router_1_22_req_in[0] = router_1_23_to_router_1_22_req; - assign router_1_22_req_in[1] = router_2_22_to_router_1_22_req; - assign router_1_22_req_in[2] = router_1_21_to_router_1_22_req; - assign router_1_22_req_in[3] = router_0_22_to_router_1_22_req; - assign router_1_22_req_in[4] = magia_tile_ni_1_22_to_router_1_22_req; - - assign router_1_22_to_router_1_23_rsp = router_1_22_rsp_out[0]; - assign router_1_22_to_router_2_22_rsp = router_1_22_rsp_out[1]; - assign router_1_22_to_router_1_21_rsp = router_1_22_rsp_out[2]; - assign router_1_22_to_router_0_22_rsp = router_1_22_rsp_out[3]; - assign router_1_22_to_magia_tile_ni_1_22_rsp = router_1_22_rsp_out[4]; - - assign router_1_22_to_router_1_23_req = router_1_22_req_out[0]; - assign router_1_22_to_router_2_22_req = router_1_22_req_out[1]; - assign router_1_22_to_router_1_21_req = router_1_22_req_out[2]; - assign router_1_22_to_router_0_22_req = router_1_22_req_out[3]; - assign router_1_22_to_magia_tile_ni_1_22_req = router_1_22_req_out[4]; - - assign router_1_22_rsp_in[0] = router_1_23_to_router_1_22_rsp; - assign router_1_22_rsp_in[1] = router_2_22_to_router_1_22_rsp; - assign router_1_22_rsp_in[2] = router_1_21_to_router_1_22_rsp; - assign router_1_22_rsp_in[3] = router_0_22_to_router_1_22_rsp; - assign router_1_22_rsp_in[4] = magia_tile_ni_1_22_to_router_1_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_22_req_in), - .floo_rsp_o (router_1_22_rsp_out), - .floo_req_o (router_1_22_req_out), - .floo_rsp_i (router_1_22_rsp_in) -); - - -floo_req_t [4:0] router_1_23_req_in; -floo_rsp_t [4:0] router_1_23_rsp_out; -floo_req_t [4:0] router_1_23_req_out; -floo_rsp_t [4:0] router_1_23_rsp_in; - - assign router_1_23_req_in[0] = router_1_24_to_router_1_23_req; - assign router_1_23_req_in[1] = router_2_23_to_router_1_23_req; - assign router_1_23_req_in[2] = router_1_22_to_router_1_23_req; - assign router_1_23_req_in[3] = router_0_23_to_router_1_23_req; - assign router_1_23_req_in[4] = magia_tile_ni_1_23_to_router_1_23_req; - - assign router_1_23_to_router_1_24_rsp = router_1_23_rsp_out[0]; - assign router_1_23_to_router_2_23_rsp = router_1_23_rsp_out[1]; - assign router_1_23_to_router_1_22_rsp = router_1_23_rsp_out[2]; - assign router_1_23_to_router_0_23_rsp = router_1_23_rsp_out[3]; - assign router_1_23_to_magia_tile_ni_1_23_rsp = router_1_23_rsp_out[4]; - - assign router_1_23_to_router_1_24_req = router_1_23_req_out[0]; - assign router_1_23_to_router_2_23_req = router_1_23_req_out[1]; - assign router_1_23_to_router_1_22_req = router_1_23_req_out[2]; - assign router_1_23_to_router_0_23_req = router_1_23_req_out[3]; - assign router_1_23_to_magia_tile_ni_1_23_req = router_1_23_req_out[4]; - - assign router_1_23_rsp_in[0] = router_1_24_to_router_1_23_rsp; - assign router_1_23_rsp_in[1] = router_2_23_to_router_1_23_rsp; - assign router_1_23_rsp_in[2] = router_1_22_to_router_1_23_rsp; - assign router_1_23_rsp_in[3] = router_0_23_to_router_1_23_rsp; - assign router_1_23_rsp_in[4] = magia_tile_ni_1_23_to_router_1_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_23_req_in), - .floo_rsp_o (router_1_23_rsp_out), - .floo_req_o (router_1_23_req_out), - .floo_rsp_i (router_1_23_rsp_in) -); - - -floo_req_t [4:0] router_1_24_req_in; -floo_rsp_t [4:0] router_1_24_rsp_out; -floo_req_t [4:0] router_1_24_req_out; -floo_rsp_t [4:0] router_1_24_rsp_in; - - assign router_1_24_req_in[0] = router_1_25_to_router_1_24_req; - assign router_1_24_req_in[1] = router_2_24_to_router_1_24_req; - assign router_1_24_req_in[2] = router_1_23_to_router_1_24_req; - assign router_1_24_req_in[3] = router_0_24_to_router_1_24_req; - assign router_1_24_req_in[4] = magia_tile_ni_1_24_to_router_1_24_req; - - assign router_1_24_to_router_1_25_rsp = router_1_24_rsp_out[0]; - assign router_1_24_to_router_2_24_rsp = router_1_24_rsp_out[1]; - assign router_1_24_to_router_1_23_rsp = router_1_24_rsp_out[2]; - assign router_1_24_to_router_0_24_rsp = router_1_24_rsp_out[3]; - assign router_1_24_to_magia_tile_ni_1_24_rsp = router_1_24_rsp_out[4]; - - assign router_1_24_to_router_1_25_req = router_1_24_req_out[0]; - assign router_1_24_to_router_2_24_req = router_1_24_req_out[1]; - assign router_1_24_to_router_1_23_req = router_1_24_req_out[2]; - assign router_1_24_to_router_0_24_req = router_1_24_req_out[3]; - assign router_1_24_to_magia_tile_ni_1_24_req = router_1_24_req_out[4]; - - assign router_1_24_rsp_in[0] = router_1_25_to_router_1_24_rsp; - assign router_1_24_rsp_in[1] = router_2_24_to_router_1_24_rsp; - assign router_1_24_rsp_in[2] = router_1_23_to_router_1_24_rsp; - assign router_1_24_rsp_in[3] = router_0_24_to_router_1_24_rsp; - assign router_1_24_rsp_in[4] = magia_tile_ni_1_24_to_router_1_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_24_req_in), - .floo_rsp_o (router_1_24_rsp_out), - .floo_req_o (router_1_24_req_out), - .floo_rsp_i (router_1_24_rsp_in) -); - - -floo_req_t [4:0] router_1_25_req_in; -floo_rsp_t [4:0] router_1_25_rsp_out; -floo_req_t [4:0] router_1_25_req_out; -floo_rsp_t [4:0] router_1_25_rsp_in; - - assign router_1_25_req_in[0] = router_1_26_to_router_1_25_req; - assign router_1_25_req_in[1] = router_2_25_to_router_1_25_req; - assign router_1_25_req_in[2] = router_1_24_to_router_1_25_req; - assign router_1_25_req_in[3] = router_0_25_to_router_1_25_req; - assign router_1_25_req_in[4] = magia_tile_ni_1_25_to_router_1_25_req; - - assign router_1_25_to_router_1_26_rsp = router_1_25_rsp_out[0]; - assign router_1_25_to_router_2_25_rsp = router_1_25_rsp_out[1]; - assign router_1_25_to_router_1_24_rsp = router_1_25_rsp_out[2]; - assign router_1_25_to_router_0_25_rsp = router_1_25_rsp_out[3]; - assign router_1_25_to_magia_tile_ni_1_25_rsp = router_1_25_rsp_out[4]; - - assign router_1_25_to_router_1_26_req = router_1_25_req_out[0]; - assign router_1_25_to_router_2_25_req = router_1_25_req_out[1]; - assign router_1_25_to_router_1_24_req = router_1_25_req_out[2]; - assign router_1_25_to_router_0_25_req = router_1_25_req_out[3]; - assign router_1_25_to_magia_tile_ni_1_25_req = router_1_25_req_out[4]; - - assign router_1_25_rsp_in[0] = router_1_26_to_router_1_25_rsp; - assign router_1_25_rsp_in[1] = router_2_25_to_router_1_25_rsp; - assign router_1_25_rsp_in[2] = router_1_24_to_router_1_25_rsp; - assign router_1_25_rsp_in[3] = router_0_25_to_router_1_25_rsp; - assign router_1_25_rsp_in[4] = magia_tile_ni_1_25_to_router_1_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_25_req_in), - .floo_rsp_o (router_1_25_rsp_out), - .floo_req_o (router_1_25_req_out), - .floo_rsp_i (router_1_25_rsp_in) -); - - -floo_req_t [4:0] router_1_26_req_in; -floo_rsp_t [4:0] router_1_26_rsp_out; -floo_req_t [4:0] router_1_26_req_out; -floo_rsp_t [4:0] router_1_26_rsp_in; - - assign router_1_26_req_in[0] = router_1_27_to_router_1_26_req; - assign router_1_26_req_in[1] = router_2_26_to_router_1_26_req; - assign router_1_26_req_in[2] = router_1_25_to_router_1_26_req; - assign router_1_26_req_in[3] = router_0_26_to_router_1_26_req; - assign router_1_26_req_in[4] = magia_tile_ni_1_26_to_router_1_26_req; - - assign router_1_26_to_router_1_27_rsp = router_1_26_rsp_out[0]; - assign router_1_26_to_router_2_26_rsp = router_1_26_rsp_out[1]; - assign router_1_26_to_router_1_25_rsp = router_1_26_rsp_out[2]; - assign router_1_26_to_router_0_26_rsp = router_1_26_rsp_out[3]; - assign router_1_26_to_magia_tile_ni_1_26_rsp = router_1_26_rsp_out[4]; - - assign router_1_26_to_router_1_27_req = router_1_26_req_out[0]; - assign router_1_26_to_router_2_26_req = router_1_26_req_out[1]; - assign router_1_26_to_router_1_25_req = router_1_26_req_out[2]; - assign router_1_26_to_router_0_26_req = router_1_26_req_out[3]; - assign router_1_26_to_magia_tile_ni_1_26_req = router_1_26_req_out[4]; - - assign router_1_26_rsp_in[0] = router_1_27_to_router_1_26_rsp; - assign router_1_26_rsp_in[1] = router_2_26_to_router_1_26_rsp; - assign router_1_26_rsp_in[2] = router_1_25_to_router_1_26_rsp; - assign router_1_26_rsp_in[3] = router_0_26_to_router_1_26_rsp; - assign router_1_26_rsp_in[4] = magia_tile_ni_1_26_to_router_1_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_26_req_in), - .floo_rsp_o (router_1_26_rsp_out), - .floo_req_o (router_1_26_req_out), - .floo_rsp_i (router_1_26_rsp_in) -); - - -floo_req_t [4:0] router_1_27_req_in; -floo_rsp_t [4:0] router_1_27_rsp_out; -floo_req_t [4:0] router_1_27_req_out; -floo_rsp_t [4:0] router_1_27_rsp_in; - - assign router_1_27_req_in[0] = router_1_28_to_router_1_27_req; - assign router_1_27_req_in[1] = router_2_27_to_router_1_27_req; - assign router_1_27_req_in[2] = router_1_26_to_router_1_27_req; - assign router_1_27_req_in[3] = router_0_27_to_router_1_27_req; - assign router_1_27_req_in[4] = magia_tile_ni_1_27_to_router_1_27_req; - - assign router_1_27_to_router_1_28_rsp = router_1_27_rsp_out[0]; - assign router_1_27_to_router_2_27_rsp = router_1_27_rsp_out[1]; - assign router_1_27_to_router_1_26_rsp = router_1_27_rsp_out[2]; - assign router_1_27_to_router_0_27_rsp = router_1_27_rsp_out[3]; - assign router_1_27_to_magia_tile_ni_1_27_rsp = router_1_27_rsp_out[4]; - - assign router_1_27_to_router_1_28_req = router_1_27_req_out[0]; - assign router_1_27_to_router_2_27_req = router_1_27_req_out[1]; - assign router_1_27_to_router_1_26_req = router_1_27_req_out[2]; - assign router_1_27_to_router_0_27_req = router_1_27_req_out[3]; - assign router_1_27_to_magia_tile_ni_1_27_req = router_1_27_req_out[4]; - - assign router_1_27_rsp_in[0] = router_1_28_to_router_1_27_rsp; - assign router_1_27_rsp_in[1] = router_2_27_to_router_1_27_rsp; - assign router_1_27_rsp_in[2] = router_1_26_to_router_1_27_rsp; - assign router_1_27_rsp_in[3] = router_0_27_to_router_1_27_rsp; - assign router_1_27_rsp_in[4] = magia_tile_ni_1_27_to_router_1_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_27_req_in), - .floo_rsp_o (router_1_27_rsp_out), - .floo_req_o (router_1_27_req_out), - .floo_rsp_i (router_1_27_rsp_in) -); - - -floo_req_t [4:0] router_1_28_req_in; -floo_rsp_t [4:0] router_1_28_rsp_out; -floo_req_t [4:0] router_1_28_req_out; -floo_rsp_t [4:0] router_1_28_rsp_in; - - assign router_1_28_req_in[0] = router_1_29_to_router_1_28_req; - assign router_1_28_req_in[1] = router_2_28_to_router_1_28_req; - assign router_1_28_req_in[2] = router_1_27_to_router_1_28_req; - assign router_1_28_req_in[3] = router_0_28_to_router_1_28_req; - assign router_1_28_req_in[4] = magia_tile_ni_1_28_to_router_1_28_req; - - assign router_1_28_to_router_1_29_rsp = router_1_28_rsp_out[0]; - assign router_1_28_to_router_2_28_rsp = router_1_28_rsp_out[1]; - assign router_1_28_to_router_1_27_rsp = router_1_28_rsp_out[2]; - assign router_1_28_to_router_0_28_rsp = router_1_28_rsp_out[3]; - assign router_1_28_to_magia_tile_ni_1_28_rsp = router_1_28_rsp_out[4]; - - assign router_1_28_to_router_1_29_req = router_1_28_req_out[0]; - assign router_1_28_to_router_2_28_req = router_1_28_req_out[1]; - assign router_1_28_to_router_1_27_req = router_1_28_req_out[2]; - assign router_1_28_to_router_0_28_req = router_1_28_req_out[3]; - assign router_1_28_to_magia_tile_ni_1_28_req = router_1_28_req_out[4]; - - assign router_1_28_rsp_in[0] = router_1_29_to_router_1_28_rsp; - assign router_1_28_rsp_in[1] = router_2_28_to_router_1_28_rsp; - assign router_1_28_rsp_in[2] = router_1_27_to_router_1_28_rsp; - assign router_1_28_rsp_in[3] = router_0_28_to_router_1_28_rsp; - assign router_1_28_rsp_in[4] = magia_tile_ni_1_28_to_router_1_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_28_req_in), - .floo_rsp_o (router_1_28_rsp_out), - .floo_req_o (router_1_28_req_out), - .floo_rsp_i (router_1_28_rsp_in) -); - - -floo_req_t [4:0] router_1_29_req_in; -floo_rsp_t [4:0] router_1_29_rsp_out; -floo_req_t [4:0] router_1_29_req_out; -floo_rsp_t [4:0] router_1_29_rsp_in; - - assign router_1_29_req_in[0] = router_1_30_to_router_1_29_req; - assign router_1_29_req_in[1] = router_2_29_to_router_1_29_req; - assign router_1_29_req_in[2] = router_1_28_to_router_1_29_req; - assign router_1_29_req_in[3] = router_0_29_to_router_1_29_req; - assign router_1_29_req_in[4] = magia_tile_ni_1_29_to_router_1_29_req; - - assign router_1_29_to_router_1_30_rsp = router_1_29_rsp_out[0]; - assign router_1_29_to_router_2_29_rsp = router_1_29_rsp_out[1]; - assign router_1_29_to_router_1_28_rsp = router_1_29_rsp_out[2]; - assign router_1_29_to_router_0_29_rsp = router_1_29_rsp_out[3]; - assign router_1_29_to_magia_tile_ni_1_29_rsp = router_1_29_rsp_out[4]; - - assign router_1_29_to_router_1_30_req = router_1_29_req_out[0]; - assign router_1_29_to_router_2_29_req = router_1_29_req_out[1]; - assign router_1_29_to_router_1_28_req = router_1_29_req_out[2]; - assign router_1_29_to_router_0_29_req = router_1_29_req_out[3]; - assign router_1_29_to_magia_tile_ni_1_29_req = router_1_29_req_out[4]; - - assign router_1_29_rsp_in[0] = router_1_30_to_router_1_29_rsp; - assign router_1_29_rsp_in[1] = router_2_29_to_router_1_29_rsp; - assign router_1_29_rsp_in[2] = router_1_28_to_router_1_29_rsp; - assign router_1_29_rsp_in[3] = router_0_29_to_router_1_29_rsp; - assign router_1_29_rsp_in[4] = magia_tile_ni_1_29_to_router_1_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_29_req_in), - .floo_rsp_o (router_1_29_rsp_out), - .floo_req_o (router_1_29_req_out), - .floo_rsp_i (router_1_29_rsp_in) -); - - -floo_req_t [4:0] router_1_30_req_in; -floo_rsp_t [4:0] router_1_30_rsp_out; -floo_req_t [4:0] router_1_30_req_out; -floo_rsp_t [4:0] router_1_30_rsp_in; - - assign router_1_30_req_in[0] = router_1_31_to_router_1_30_req; - assign router_1_30_req_in[1] = router_2_30_to_router_1_30_req; - assign router_1_30_req_in[2] = router_1_29_to_router_1_30_req; - assign router_1_30_req_in[3] = router_0_30_to_router_1_30_req; - assign router_1_30_req_in[4] = magia_tile_ni_1_30_to_router_1_30_req; - - assign router_1_30_to_router_1_31_rsp = router_1_30_rsp_out[0]; - assign router_1_30_to_router_2_30_rsp = router_1_30_rsp_out[1]; - assign router_1_30_to_router_1_29_rsp = router_1_30_rsp_out[2]; - assign router_1_30_to_router_0_30_rsp = router_1_30_rsp_out[3]; - assign router_1_30_to_magia_tile_ni_1_30_rsp = router_1_30_rsp_out[4]; - - assign router_1_30_to_router_1_31_req = router_1_30_req_out[0]; - assign router_1_30_to_router_2_30_req = router_1_30_req_out[1]; - assign router_1_30_to_router_1_29_req = router_1_30_req_out[2]; - assign router_1_30_to_router_0_30_req = router_1_30_req_out[3]; - assign router_1_30_to_magia_tile_ni_1_30_req = router_1_30_req_out[4]; - - assign router_1_30_rsp_in[0] = router_1_31_to_router_1_30_rsp; - assign router_1_30_rsp_in[1] = router_2_30_to_router_1_30_rsp; - assign router_1_30_rsp_in[2] = router_1_29_to_router_1_30_rsp; - assign router_1_30_rsp_in[3] = router_0_30_to_router_1_30_rsp; - assign router_1_30_rsp_in[4] = magia_tile_ni_1_30_to_router_1_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_30_req_in), - .floo_rsp_o (router_1_30_rsp_out), - .floo_req_o (router_1_30_req_out), - .floo_rsp_i (router_1_30_rsp_in) -); - - -floo_req_t [4:0] router_1_31_req_in; -floo_rsp_t [4:0] router_1_31_rsp_out; -floo_req_t [4:0] router_1_31_req_out; -floo_rsp_t [4:0] router_1_31_rsp_in; - - assign router_1_31_req_in[0] = '0; - assign router_1_31_req_in[1] = router_2_31_to_router_1_31_req; - assign router_1_31_req_in[2] = router_1_30_to_router_1_31_req; - assign router_1_31_req_in[3] = router_0_31_to_router_1_31_req; - assign router_1_31_req_in[4] = magia_tile_ni_1_31_to_router_1_31_req; - - assign router_1_31_to_router_2_31_rsp = router_1_31_rsp_out[1]; - assign router_1_31_to_router_1_30_rsp = router_1_31_rsp_out[2]; - assign router_1_31_to_router_0_31_rsp = router_1_31_rsp_out[3]; - assign router_1_31_to_magia_tile_ni_1_31_rsp = router_1_31_rsp_out[4]; - - assign router_1_31_to_router_2_31_req = router_1_31_req_out[1]; - assign router_1_31_to_router_1_30_req = router_1_31_req_out[2]; - assign router_1_31_to_router_0_31_req = router_1_31_req_out[3]; - assign router_1_31_to_magia_tile_ni_1_31_req = router_1_31_req_out[4]; - - assign router_1_31_rsp_in[0] = '0; - assign router_1_31_rsp_in[1] = router_2_31_to_router_1_31_rsp; - assign router_1_31_rsp_in[2] = router_1_30_to_router_1_31_rsp; - assign router_1_31_rsp_in[3] = router_0_31_to_router_1_31_rsp; - assign router_1_31_rsp_in[4] = magia_tile_ni_1_31_to_router_1_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_31_req_in), - .floo_rsp_o (router_1_31_rsp_out), - .floo_req_o (router_1_31_req_out), - .floo_rsp_i (router_1_31_rsp_in) -); - - -floo_req_t [4:0] router_2_0_req_in; -floo_rsp_t [4:0] router_2_0_rsp_out; -floo_req_t [4:0] router_2_0_req_out; -floo_rsp_t [4:0] router_2_0_rsp_in; - - assign router_2_0_req_in[0] = router_2_1_to_router_2_0_req; - assign router_2_0_req_in[1] = router_3_0_to_router_2_0_req; - assign router_2_0_req_in[2] = '0; - assign router_2_0_req_in[3] = router_1_0_to_router_2_0_req; - assign router_2_0_req_in[4] = magia_tile_ni_2_0_to_router_2_0_req; - - assign router_2_0_to_router_2_1_rsp = router_2_0_rsp_out[0]; - assign router_2_0_to_router_3_0_rsp = router_2_0_rsp_out[1]; - assign router_2_0_to_router_1_0_rsp = router_2_0_rsp_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_rsp = router_2_0_rsp_out[4]; - - assign router_2_0_to_router_2_1_req = router_2_0_req_out[0]; - assign router_2_0_to_router_3_0_req = router_2_0_req_out[1]; - assign router_2_0_to_router_1_0_req = router_2_0_req_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_req = router_2_0_req_out[4]; - - assign router_2_0_rsp_in[0] = router_2_1_to_router_2_0_rsp; - assign router_2_0_rsp_in[1] = router_3_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[2] = '0; - assign router_2_0_rsp_in[3] = router_1_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[4] = magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_0_req_in), - .floo_rsp_o (router_2_0_rsp_out), - .floo_req_o (router_2_0_req_out), - .floo_rsp_i (router_2_0_rsp_in) -); - - -floo_req_t [4:0] router_2_1_req_in; -floo_rsp_t [4:0] router_2_1_rsp_out; -floo_req_t [4:0] router_2_1_req_out; -floo_rsp_t [4:0] router_2_1_rsp_in; - - assign router_2_1_req_in[0] = router_2_2_to_router_2_1_req; - assign router_2_1_req_in[1] = router_3_1_to_router_2_1_req; - assign router_2_1_req_in[2] = router_2_0_to_router_2_1_req; - assign router_2_1_req_in[3] = router_1_1_to_router_2_1_req; - assign router_2_1_req_in[4] = magia_tile_ni_2_1_to_router_2_1_req; - - assign router_2_1_to_router_2_2_rsp = router_2_1_rsp_out[0]; - assign router_2_1_to_router_3_1_rsp = router_2_1_rsp_out[1]; - assign router_2_1_to_router_2_0_rsp = router_2_1_rsp_out[2]; - assign router_2_1_to_router_1_1_rsp = router_2_1_rsp_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_rsp = router_2_1_rsp_out[4]; - - assign router_2_1_to_router_2_2_req = router_2_1_req_out[0]; - assign router_2_1_to_router_3_1_req = router_2_1_req_out[1]; - assign router_2_1_to_router_2_0_req = router_2_1_req_out[2]; - assign router_2_1_to_router_1_1_req = router_2_1_req_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_req = router_2_1_req_out[4]; - - assign router_2_1_rsp_in[0] = router_2_2_to_router_2_1_rsp; - assign router_2_1_rsp_in[1] = router_3_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[2] = router_2_0_to_router_2_1_rsp; - assign router_2_1_rsp_in[3] = router_1_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[4] = magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_1_req_in), - .floo_rsp_o (router_2_1_rsp_out), - .floo_req_o (router_2_1_req_out), - .floo_rsp_i (router_2_1_rsp_in) -); - - -floo_req_t [4:0] router_2_2_req_in; -floo_rsp_t [4:0] router_2_2_rsp_out; -floo_req_t [4:0] router_2_2_req_out; -floo_rsp_t [4:0] router_2_2_rsp_in; - - assign router_2_2_req_in[0] = router_2_3_to_router_2_2_req; - assign router_2_2_req_in[1] = router_3_2_to_router_2_2_req; - assign router_2_2_req_in[2] = router_2_1_to_router_2_2_req; - assign router_2_2_req_in[3] = router_1_2_to_router_2_2_req; - assign router_2_2_req_in[4] = magia_tile_ni_2_2_to_router_2_2_req; - - assign router_2_2_to_router_2_3_rsp = router_2_2_rsp_out[0]; - assign router_2_2_to_router_3_2_rsp = router_2_2_rsp_out[1]; - assign router_2_2_to_router_2_1_rsp = router_2_2_rsp_out[2]; - assign router_2_2_to_router_1_2_rsp = router_2_2_rsp_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_rsp = router_2_2_rsp_out[4]; - - assign router_2_2_to_router_2_3_req = router_2_2_req_out[0]; - assign router_2_2_to_router_3_2_req = router_2_2_req_out[1]; - assign router_2_2_to_router_2_1_req = router_2_2_req_out[2]; - assign router_2_2_to_router_1_2_req = router_2_2_req_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_req = router_2_2_req_out[4]; - - assign router_2_2_rsp_in[0] = router_2_3_to_router_2_2_rsp; - assign router_2_2_rsp_in[1] = router_3_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[2] = router_2_1_to_router_2_2_rsp; - assign router_2_2_rsp_in[3] = router_1_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[4] = magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_2_req_in), - .floo_rsp_o (router_2_2_rsp_out), - .floo_req_o (router_2_2_req_out), - .floo_rsp_i (router_2_2_rsp_in) -); - - -floo_req_t [4:0] router_2_3_req_in; -floo_rsp_t [4:0] router_2_3_rsp_out; -floo_req_t [4:0] router_2_3_req_out; -floo_rsp_t [4:0] router_2_3_rsp_in; - - assign router_2_3_req_in[0] = router_2_4_to_router_2_3_req; - assign router_2_3_req_in[1] = router_3_3_to_router_2_3_req; - assign router_2_3_req_in[2] = router_2_2_to_router_2_3_req; - assign router_2_3_req_in[3] = router_1_3_to_router_2_3_req; - assign router_2_3_req_in[4] = magia_tile_ni_2_3_to_router_2_3_req; - - assign router_2_3_to_router_2_4_rsp = router_2_3_rsp_out[0]; - assign router_2_3_to_router_3_3_rsp = router_2_3_rsp_out[1]; - assign router_2_3_to_router_2_2_rsp = router_2_3_rsp_out[2]; - assign router_2_3_to_router_1_3_rsp = router_2_3_rsp_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_rsp = router_2_3_rsp_out[4]; - - assign router_2_3_to_router_2_4_req = router_2_3_req_out[0]; - assign router_2_3_to_router_3_3_req = router_2_3_req_out[1]; - assign router_2_3_to_router_2_2_req = router_2_3_req_out[2]; - assign router_2_3_to_router_1_3_req = router_2_3_req_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_req = router_2_3_req_out[4]; - - assign router_2_3_rsp_in[0] = router_2_4_to_router_2_3_rsp; - assign router_2_3_rsp_in[1] = router_3_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[2] = router_2_2_to_router_2_3_rsp; - assign router_2_3_rsp_in[3] = router_1_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[4] = magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_3_req_in), - .floo_rsp_o (router_2_3_rsp_out), - .floo_req_o (router_2_3_req_out), - .floo_rsp_i (router_2_3_rsp_in) -); - - -floo_req_t [4:0] router_2_4_req_in; -floo_rsp_t [4:0] router_2_4_rsp_out; -floo_req_t [4:0] router_2_4_req_out; -floo_rsp_t [4:0] router_2_4_rsp_in; - - assign router_2_4_req_in[0] = router_2_5_to_router_2_4_req; - assign router_2_4_req_in[1] = router_3_4_to_router_2_4_req; - assign router_2_4_req_in[2] = router_2_3_to_router_2_4_req; - assign router_2_4_req_in[3] = router_1_4_to_router_2_4_req; - assign router_2_4_req_in[4] = magia_tile_ni_2_4_to_router_2_4_req; - - assign router_2_4_to_router_2_5_rsp = router_2_4_rsp_out[0]; - assign router_2_4_to_router_3_4_rsp = router_2_4_rsp_out[1]; - assign router_2_4_to_router_2_3_rsp = router_2_4_rsp_out[2]; - assign router_2_4_to_router_1_4_rsp = router_2_4_rsp_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_rsp = router_2_4_rsp_out[4]; - - assign router_2_4_to_router_2_5_req = router_2_4_req_out[0]; - assign router_2_4_to_router_3_4_req = router_2_4_req_out[1]; - assign router_2_4_to_router_2_3_req = router_2_4_req_out[2]; - assign router_2_4_to_router_1_4_req = router_2_4_req_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_req = router_2_4_req_out[4]; - - assign router_2_4_rsp_in[0] = router_2_5_to_router_2_4_rsp; - assign router_2_4_rsp_in[1] = router_3_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[2] = router_2_3_to_router_2_4_rsp; - assign router_2_4_rsp_in[3] = router_1_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[4] = magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_4_req_in), - .floo_rsp_o (router_2_4_rsp_out), - .floo_req_o (router_2_4_req_out), - .floo_rsp_i (router_2_4_rsp_in) -); - - -floo_req_t [4:0] router_2_5_req_in; -floo_rsp_t [4:0] router_2_5_rsp_out; -floo_req_t [4:0] router_2_5_req_out; -floo_rsp_t [4:0] router_2_5_rsp_in; - - assign router_2_5_req_in[0] = router_2_6_to_router_2_5_req; - assign router_2_5_req_in[1] = router_3_5_to_router_2_5_req; - assign router_2_5_req_in[2] = router_2_4_to_router_2_5_req; - assign router_2_5_req_in[3] = router_1_5_to_router_2_5_req; - assign router_2_5_req_in[4] = magia_tile_ni_2_5_to_router_2_5_req; - - assign router_2_5_to_router_2_6_rsp = router_2_5_rsp_out[0]; - assign router_2_5_to_router_3_5_rsp = router_2_5_rsp_out[1]; - assign router_2_5_to_router_2_4_rsp = router_2_5_rsp_out[2]; - assign router_2_5_to_router_1_5_rsp = router_2_5_rsp_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_rsp = router_2_5_rsp_out[4]; - - assign router_2_5_to_router_2_6_req = router_2_5_req_out[0]; - assign router_2_5_to_router_3_5_req = router_2_5_req_out[1]; - assign router_2_5_to_router_2_4_req = router_2_5_req_out[2]; - assign router_2_5_to_router_1_5_req = router_2_5_req_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_req = router_2_5_req_out[4]; - - assign router_2_5_rsp_in[0] = router_2_6_to_router_2_5_rsp; - assign router_2_5_rsp_in[1] = router_3_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[2] = router_2_4_to_router_2_5_rsp; - assign router_2_5_rsp_in[3] = router_1_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[4] = magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_5_req_in), - .floo_rsp_o (router_2_5_rsp_out), - .floo_req_o (router_2_5_req_out), - .floo_rsp_i (router_2_5_rsp_in) -); - - -floo_req_t [4:0] router_2_6_req_in; -floo_rsp_t [4:0] router_2_6_rsp_out; -floo_req_t [4:0] router_2_6_req_out; -floo_rsp_t [4:0] router_2_6_rsp_in; - - assign router_2_6_req_in[0] = router_2_7_to_router_2_6_req; - assign router_2_6_req_in[1] = router_3_6_to_router_2_6_req; - assign router_2_6_req_in[2] = router_2_5_to_router_2_6_req; - assign router_2_6_req_in[3] = router_1_6_to_router_2_6_req; - assign router_2_6_req_in[4] = magia_tile_ni_2_6_to_router_2_6_req; - - assign router_2_6_to_router_2_7_rsp = router_2_6_rsp_out[0]; - assign router_2_6_to_router_3_6_rsp = router_2_6_rsp_out[1]; - assign router_2_6_to_router_2_5_rsp = router_2_6_rsp_out[2]; - assign router_2_6_to_router_1_6_rsp = router_2_6_rsp_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_rsp = router_2_6_rsp_out[4]; - - assign router_2_6_to_router_2_7_req = router_2_6_req_out[0]; - assign router_2_6_to_router_3_6_req = router_2_6_req_out[1]; - assign router_2_6_to_router_2_5_req = router_2_6_req_out[2]; - assign router_2_6_to_router_1_6_req = router_2_6_req_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_req = router_2_6_req_out[4]; - - assign router_2_6_rsp_in[0] = router_2_7_to_router_2_6_rsp; - assign router_2_6_rsp_in[1] = router_3_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[2] = router_2_5_to_router_2_6_rsp; - assign router_2_6_rsp_in[3] = router_1_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[4] = magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_6_req_in), - .floo_rsp_o (router_2_6_rsp_out), - .floo_req_o (router_2_6_req_out), - .floo_rsp_i (router_2_6_rsp_in) -); - - -floo_req_t [4:0] router_2_7_req_in; -floo_rsp_t [4:0] router_2_7_rsp_out; -floo_req_t [4:0] router_2_7_req_out; -floo_rsp_t [4:0] router_2_7_rsp_in; - - assign router_2_7_req_in[0] = router_2_8_to_router_2_7_req; - assign router_2_7_req_in[1] = router_3_7_to_router_2_7_req; - assign router_2_7_req_in[2] = router_2_6_to_router_2_7_req; - assign router_2_7_req_in[3] = router_1_7_to_router_2_7_req; - assign router_2_7_req_in[4] = magia_tile_ni_2_7_to_router_2_7_req; - - assign router_2_7_to_router_2_8_rsp = router_2_7_rsp_out[0]; - assign router_2_7_to_router_3_7_rsp = router_2_7_rsp_out[1]; - assign router_2_7_to_router_2_6_rsp = router_2_7_rsp_out[2]; - assign router_2_7_to_router_1_7_rsp = router_2_7_rsp_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_rsp = router_2_7_rsp_out[4]; - - assign router_2_7_to_router_2_8_req = router_2_7_req_out[0]; - assign router_2_7_to_router_3_7_req = router_2_7_req_out[1]; - assign router_2_7_to_router_2_6_req = router_2_7_req_out[2]; - assign router_2_7_to_router_1_7_req = router_2_7_req_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_req = router_2_7_req_out[4]; - - assign router_2_7_rsp_in[0] = router_2_8_to_router_2_7_rsp; - assign router_2_7_rsp_in[1] = router_3_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[2] = router_2_6_to_router_2_7_rsp; - assign router_2_7_rsp_in[3] = router_1_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[4] = magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_7_req_in), - .floo_rsp_o (router_2_7_rsp_out), - .floo_req_o (router_2_7_req_out), - .floo_rsp_i (router_2_7_rsp_in) -); - - -floo_req_t [4:0] router_2_8_req_in; -floo_rsp_t [4:0] router_2_8_rsp_out; -floo_req_t [4:0] router_2_8_req_out; -floo_rsp_t [4:0] router_2_8_rsp_in; - - assign router_2_8_req_in[0] = router_2_9_to_router_2_8_req; - assign router_2_8_req_in[1] = router_3_8_to_router_2_8_req; - assign router_2_8_req_in[2] = router_2_7_to_router_2_8_req; - assign router_2_8_req_in[3] = router_1_8_to_router_2_8_req; - assign router_2_8_req_in[4] = magia_tile_ni_2_8_to_router_2_8_req; - - assign router_2_8_to_router_2_9_rsp = router_2_8_rsp_out[0]; - assign router_2_8_to_router_3_8_rsp = router_2_8_rsp_out[1]; - assign router_2_8_to_router_2_7_rsp = router_2_8_rsp_out[2]; - assign router_2_8_to_router_1_8_rsp = router_2_8_rsp_out[3]; - assign router_2_8_to_magia_tile_ni_2_8_rsp = router_2_8_rsp_out[4]; - - assign router_2_8_to_router_2_9_req = router_2_8_req_out[0]; - assign router_2_8_to_router_3_8_req = router_2_8_req_out[1]; - assign router_2_8_to_router_2_7_req = router_2_8_req_out[2]; - assign router_2_8_to_router_1_8_req = router_2_8_req_out[3]; - assign router_2_8_to_magia_tile_ni_2_8_req = router_2_8_req_out[4]; - - assign router_2_8_rsp_in[0] = router_2_9_to_router_2_8_rsp; - assign router_2_8_rsp_in[1] = router_3_8_to_router_2_8_rsp; - assign router_2_8_rsp_in[2] = router_2_7_to_router_2_8_rsp; - assign router_2_8_rsp_in[3] = router_1_8_to_router_2_8_rsp; - assign router_2_8_rsp_in[4] = magia_tile_ni_2_8_to_router_2_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_8_req_in), - .floo_rsp_o (router_2_8_rsp_out), - .floo_req_o (router_2_8_req_out), - .floo_rsp_i (router_2_8_rsp_in) -); - - -floo_req_t [4:0] router_2_9_req_in; -floo_rsp_t [4:0] router_2_9_rsp_out; -floo_req_t [4:0] router_2_9_req_out; -floo_rsp_t [4:0] router_2_9_rsp_in; - - assign router_2_9_req_in[0] = router_2_10_to_router_2_9_req; - assign router_2_9_req_in[1] = router_3_9_to_router_2_9_req; - assign router_2_9_req_in[2] = router_2_8_to_router_2_9_req; - assign router_2_9_req_in[3] = router_1_9_to_router_2_9_req; - assign router_2_9_req_in[4] = magia_tile_ni_2_9_to_router_2_9_req; - - assign router_2_9_to_router_2_10_rsp = router_2_9_rsp_out[0]; - assign router_2_9_to_router_3_9_rsp = router_2_9_rsp_out[1]; - assign router_2_9_to_router_2_8_rsp = router_2_9_rsp_out[2]; - assign router_2_9_to_router_1_9_rsp = router_2_9_rsp_out[3]; - assign router_2_9_to_magia_tile_ni_2_9_rsp = router_2_9_rsp_out[4]; - - assign router_2_9_to_router_2_10_req = router_2_9_req_out[0]; - assign router_2_9_to_router_3_9_req = router_2_9_req_out[1]; - assign router_2_9_to_router_2_8_req = router_2_9_req_out[2]; - assign router_2_9_to_router_1_9_req = router_2_9_req_out[3]; - assign router_2_9_to_magia_tile_ni_2_9_req = router_2_9_req_out[4]; - - assign router_2_9_rsp_in[0] = router_2_10_to_router_2_9_rsp; - assign router_2_9_rsp_in[1] = router_3_9_to_router_2_9_rsp; - assign router_2_9_rsp_in[2] = router_2_8_to_router_2_9_rsp; - assign router_2_9_rsp_in[3] = router_1_9_to_router_2_9_rsp; - assign router_2_9_rsp_in[4] = magia_tile_ni_2_9_to_router_2_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_9_req_in), - .floo_rsp_o (router_2_9_rsp_out), - .floo_req_o (router_2_9_req_out), - .floo_rsp_i (router_2_9_rsp_in) -); - - -floo_req_t [4:0] router_2_10_req_in; -floo_rsp_t [4:0] router_2_10_rsp_out; -floo_req_t [4:0] router_2_10_req_out; -floo_rsp_t [4:0] router_2_10_rsp_in; - - assign router_2_10_req_in[0] = router_2_11_to_router_2_10_req; - assign router_2_10_req_in[1] = router_3_10_to_router_2_10_req; - assign router_2_10_req_in[2] = router_2_9_to_router_2_10_req; - assign router_2_10_req_in[3] = router_1_10_to_router_2_10_req; - assign router_2_10_req_in[4] = magia_tile_ni_2_10_to_router_2_10_req; - - assign router_2_10_to_router_2_11_rsp = router_2_10_rsp_out[0]; - assign router_2_10_to_router_3_10_rsp = router_2_10_rsp_out[1]; - assign router_2_10_to_router_2_9_rsp = router_2_10_rsp_out[2]; - assign router_2_10_to_router_1_10_rsp = router_2_10_rsp_out[3]; - assign router_2_10_to_magia_tile_ni_2_10_rsp = router_2_10_rsp_out[4]; - - assign router_2_10_to_router_2_11_req = router_2_10_req_out[0]; - assign router_2_10_to_router_3_10_req = router_2_10_req_out[1]; - assign router_2_10_to_router_2_9_req = router_2_10_req_out[2]; - assign router_2_10_to_router_1_10_req = router_2_10_req_out[3]; - assign router_2_10_to_magia_tile_ni_2_10_req = router_2_10_req_out[4]; - - assign router_2_10_rsp_in[0] = router_2_11_to_router_2_10_rsp; - assign router_2_10_rsp_in[1] = router_3_10_to_router_2_10_rsp; - assign router_2_10_rsp_in[2] = router_2_9_to_router_2_10_rsp; - assign router_2_10_rsp_in[3] = router_1_10_to_router_2_10_rsp; - assign router_2_10_rsp_in[4] = magia_tile_ni_2_10_to_router_2_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_10_req_in), - .floo_rsp_o (router_2_10_rsp_out), - .floo_req_o (router_2_10_req_out), - .floo_rsp_i (router_2_10_rsp_in) -); - - -floo_req_t [4:0] router_2_11_req_in; -floo_rsp_t [4:0] router_2_11_rsp_out; -floo_req_t [4:0] router_2_11_req_out; -floo_rsp_t [4:0] router_2_11_rsp_in; - - assign router_2_11_req_in[0] = router_2_12_to_router_2_11_req; - assign router_2_11_req_in[1] = router_3_11_to_router_2_11_req; - assign router_2_11_req_in[2] = router_2_10_to_router_2_11_req; - assign router_2_11_req_in[3] = router_1_11_to_router_2_11_req; - assign router_2_11_req_in[4] = magia_tile_ni_2_11_to_router_2_11_req; - - assign router_2_11_to_router_2_12_rsp = router_2_11_rsp_out[0]; - assign router_2_11_to_router_3_11_rsp = router_2_11_rsp_out[1]; - assign router_2_11_to_router_2_10_rsp = router_2_11_rsp_out[2]; - assign router_2_11_to_router_1_11_rsp = router_2_11_rsp_out[3]; - assign router_2_11_to_magia_tile_ni_2_11_rsp = router_2_11_rsp_out[4]; - - assign router_2_11_to_router_2_12_req = router_2_11_req_out[0]; - assign router_2_11_to_router_3_11_req = router_2_11_req_out[1]; - assign router_2_11_to_router_2_10_req = router_2_11_req_out[2]; - assign router_2_11_to_router_1_11_req = router_2_11_req_out[3]; - assign router_2_11_to_magia_tile_ni_2_11_req = router_2_11_req_out[4]; - - assign router_2_11_rsp_in[0] = router_2_12_to_router_2_11_rsp; - assign router_2_11_rsp_in[1] = router_3_11_to_router_2_11_rsp; - assign router_2_11_rsp_in[2] = router_2_10_to_router_2_11_rsp; - assign router_2_11_rsp_in[3] = router_1_11_to_router_2_11_rsp; - assign router_2_11_rsp_in[4] = magia_tile_ni_2_11_to_router_2_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_11_req_in), - .floo_rsp_o (router_2_11_rsp_out), - .floo_req_o (router_2_11_req_out), - .floo_rsp_i (router_2_11_rsp_in) -); - - -floo_req_t [4:0] router_2_12_req_in; -floo_rsp_t [4:0] router_2_12_rsp_out; -floo_req_t [4:0] router_2_12_req_out; -floo_rsp_t [4:0] router_2_12_rsp_in; - - assign router_2_12_req_in[0] = router_2_13_to_router_2_12_req; - assign router_2_12_req_in[1] = router_3_12_to_router_2_12_req; - assign router_2_12_req_in[2] = router_2_11_to_router_2_12_req; - assign router_2_12_req_in[3] = router_1_12_to_router_2_12_req; - assign router_2_12_req_in[4] = magia_tile_ni_2_12_to_router_2_12_req; - - assign router_2_12_to_router_2_13_rsp = router_2_12_rsp_out[0]; - assign router_2_12_to_router_3_12_rsp = router_2_12_rsp_out[1]; - assign router_2_12_to_router_2_11_rsp = router_2_12_rsp_out[2]; - assign router_2_12_to_router_1_12_rsp = router_2_12_rsp_out[3]; - assign router_2_12_to_magia_tile_ni_2_12_rsp = router_2_12_rsp_out[4]; - - assign router_2_12_to_router_2_13_req = router_2_12_req_out[0]; - assign router_2_12_to_router_3_12_req = router_2_12_req_out[1]; - assign router_2_12_to_router_2_11_req = router_2_12_req_out[2]; - assign router_2_12_to_router_1_12_req = router_2_12_req_out[3]; - assign router_2_12_to_magia_tile_ni_2_12_req = router_2_12_req_out[4]; - - assign router_2_12_rsp_in[0] = router_2_13_to_router_2_12_rsp; - assign router_2_12_rsp_in[1] = router_3_12_to_router_2_12_rsp; - assign router_2_12_rsp_in[2] = router_2_11_to_router_2_12_rsp; - assign router_2_12_rsp_in[3] = router_1_12_to_router_2_12_rsp; - assign router_2_12_rsp_in[4] = magia_tile_ni_2_12_to_router_2_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_12_req_in), - .floo_rsp_o (router_2_12_rsp_out), - .floo_req_o (router_2_12_req_out), - .floo_rsp_i (router_2_12_rsp_in) -); - - -floo_req_t [4:0] router_2_13_req_in; -floo_rsp_t [4:0] router_2_13_rsp_out; -floo_req_t [4:0] router_2_13_req_out; -floo_rsp_t [4:0] router_2_13_rsp_in; - - assign router_2_13_req_in[0] = router_2_14_to_router_2_13_req; - assign router_2_13_req_in[1] = router_3_13_to_router_2_13_req; - assign router_2_13_req_in[2] = router_2_12_to_router_2_13_req; - assign router_2_13_req_in[3] = router_1_13_to_router_2_13_req; - assign router_2_13_req_in[4] = magia_tile_ni_2_13_to_router_2_13_req; - - assign router_2_13_to_router_2_14_rsp = router_2_13_rsp_out[0]; - assign router_2_13_to_router_3_13_rsp = router_2_13_rsp_out[1]; - assign router_2_13_to_router_2_12_rsp = router_2_13_rsp_out[2]; - assign router_2_13_to_router_1_13_rsp = router_2_13_rsp_out[3]; - assign router_2_13_to_magia_tile_ni_2_13_rsp = router_2_13_rsp_out[4]; - - assign router_2_13_to_router_2_14_req = router_2_13_req_out[0]; - assign router_2_13_to_router_3_13_req = router_2_13_req_out[1]; - assign router_2_13_to_router_2_12_req = router_2_13_req_out[2]; - assign router_2_13_to_router_1_13_req = router_2_13_req_out[3]; - assign router_2_13_to_magia_tile_ni_2_13_req = router_2_13_req_out[4]; - - assign router_2_13_rsp_in[0] = router_2_14_to_router_2_13_rsp; - assign router_2_13_rsp_in[1] = router_3_13_to_router_2_13_rsp; - assign router_2_13_rsp_in[2] = router_2_12_to_router_2_13_rsp; - assign router_2_13_rsp_in[3] = router_1_13_to_router_2_13_rsp; - assign router_2_13_rsp_in[4] = magia_tile_ni_2_13_to_router_2_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_13_req_in), - .floo_rsp_o (router_2_13_rsp_out), - .floo_req_o (router_2_13_req_out), - .floo_rsp_i (router_2_13_rsp_in) -); - - -floo_req_t [4:0] router_2_14_req_in; -floo_rsp_t [4:0] router_2_14_rsp_out; -floo_req_t [4:0] router_2_14_req_out; -floo_rsp_t [4:0] router_2_14_rsp_in; - - assign router_2_14_req_in[0] = router_2_15_to_router_2_14_req; - assign router_2_14_req_in[1] = router_3_14_to_router_2_14_req; - assign router_2_14_req_in[2] = router_2_13_to_router_2_14_req; - assign router_2_14_req_in[3] = router_1_14_to_router_2_14_req; - assign router_2_14_req_in[4] = magia_tile_ni_2_14_to_router_2_14_req; - - assign router_2_14_to_router_2_15_rsp = router_2_14_rsp_out[0]; - assign router_2_14_to_router_3_14_rsp = router_2_14_rsp_out[1]; - assign router_2_14_to_router_2_13_rsp = router_2_14_rsp_out[2]; - assign router_2_14_to_router_1_14_rsp = router_2_14_rsp_out[3]; - assign router_2_14_to_magia_tile_ni_2_14_rsp = router_2_14_rsp_out[4]; - - assign router_2_14_to_router_2_15_req = router_2_14_req_out[0]; - assign router_2_14_to_router_3_14_req = router_2_14_req_out[1]; - assign router_2_14_to_router_2_13_req = router_2_14_req_out[2]; - assign router_2_14_to_router_1_14_req = router_2_14_req_out[3]; - assign router_2_14_to_magia_tile_ni_2_14_req = router_2_14_req_out[4]; - - assign router_2_14_rsp_in[0] = router_2_15_to_router_2_14_rsp; - assign router_2_14_rsp_in[1] = router_3_14_to_router_2_14_rsp; - assign router_2_14_rsp_in[2] = router_2_13_to_router_2_14_rsp; - assign router_2_14_rsp_in[3] = router_1_14_to_router_2_14_rsp; - assign router_2_14_rsp_in[4] = magia_tile_ni_2_14_to_router_2_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_14_req_in), - .floo_rsp_o (router_2_14_rsp_out), - .floo_req_o (router_2_14_req_out), - .floo_rsp_i (router_2_14_rsp_in) -); - - -floo_req_t [4:0] router_2_15_req_in; -floo_rsp_t [4:0] router_2_15_rsp_out; -floo_req_t [4:0] router_2_15_req_out; -floo_rsp_t [4:0] router_2_15_rsp_in; - - assign router_2_15_req_in[0] = router_2_16_to_router_2_15_req; - assign router_2_15_req_in[1] = router_3_15_to_router_2_15_req; - assign router_2_15_req_in[2] = router_2_14_to_router_2_15_req; - assign router_2_15_req_in[3] = router_1_15_to_router_2_15_req; - assign router_2_15_req_in[4] = magia_tile_ni_2_15_to_router_2_15_req; - - assign router_2_15_to_router_2_16_rsp = router_2_15_rsp_out[0]; - assign router_2_15_to_router_3_15_rsp = router_2_15_rsp_out[1]; - assign router_2_15_to_router_2_14_rsp = router_2_15_rsp_out[2]; - assign router_2_15_to_router_1_15_rsp = router_2_15_rsp_out[3]; - assign router_2_15_to_magia_tile_ni_2_15_rsp = router_2_15_rsp_out[4]; - - assign router_2_15_to_router_2_16_req = router_2_15_req_out[0]; - assign router_2_15_to_router_3_15_req = router_2_15_req_out[1]; - assign router_2_15_to_router_2_14_req = router_2_15_req_out[2]; - assign router_2_15_to_router_1_15_req = router_2_15_req_out[3]; - assign router_2_15_to_magia_tile_ni_2_15_req = router_2_15_req_out[4]; - - assign router_2_15_rsp_in[0] = router_2_16_to_router_2_15_rsp; - assign router_2_15_rsp_in[1] = router_3_15_to_router_2_15_rsp; - assign router_2_15_rsp_in[2] = router_2_14_to_router_2_15_rsp; - assign router_2_15_rsp_in[3] = router_1_15_to_router_2_15_rsp; - assign router_2_15_rsp_in[4] = magia_tile_ni_2_15_to_router_2_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_15_req_in), - .floo_rsp_o (router_2_15_rsp_out), - .floo_req_o (router_2_15_req_out), - .floo_rsp_i (router_2_15_rsp_in) -); - - -floo_req_t [4:0] router_2_16_req_in; -floo_rsp_t [4:0] router_2_16_rsp_out; -floo_req_t [4:0] router_2_16_req_out; -floo_rsp_t [4:0] router_2_16_rsp_in; - - assign router_2_16_req_in[0] = router_2_17_to_router_2_16_req; - assign router_2_16_req_in[1] = router_3_16_to_router_2_16_req; - assign router_2_16_req_in[2] = router_2_15_to_router_2_16_req; - assign router_2_16_req_in[3] = router_1_16_to_router_2_16_req; - assign router_2_16_req_in[4] = magia_tile_ni_2_16_to_router_2_16_req; - - assign router_2_16_to_router_2_17_rsp = router_2_16_rsp_out[0]; - assign router_2_16_to_router_3_16_rsp = router_2_16_rsp_out[1]; - assign router_2_16_to_router_2_15_rsp = router_2_16_rsp_out[2]; - assign router_2_16_to_router_1_16_rsp = router_2_16_rsp_out[3]; - assign router_2_16_to_magia_tile_ni_2_16_rsp = router_2_16_rsp_out[4]; - - assign router_2_16_to_router_2_17_req = router_2_16_req_out[0]; - assign router_2_16_to_router_3_16_req = router_2_16_req_out[1]; - assign router_2_16_to_router_2_15_req = router_2_16_req_out[2]; - assign router_2_16_to_router_1_16_req = router_2_16_req_out[3]; - assign router_2_16_to_magia_tile_ni_2_16_req = router_2_16_req_out[4]; - - assign router_2_16_rsp_in[0] = router_2_17_to_router_2_16_rsp; - assign router_2_16_rsp_in[1] = router_3_16_to_router_2_16_rsp; - assign router_2_16_rsp_in[2] = router_2_15_to_router_2_16_rsp; - assign router_2_16_rsp_in[3] = router_1_16_to_router_2_16_rsp; - assign router_2_16_rsp_in[4] = magia_tile_ni_2_16_to_router_2_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_16_req_in), - .floo_rsp_o (router_2_16_rsp_out), - .floo_req_o (router_2_16_req_out), - .floo_rsp_i (router_2_16_rsp_in) -); - - -floo_req_t [4:0] router_2_17_req_in; -floo_rsp_t [4:0] router_2_17_rsp_out; -floo_req_t [4:0] router_2_17_req_out; -floo_rsp_t [4:0] router_2_17_rsp_in; - - assign router_2_17_req_in[0] = router_2_18_to_router_2_17_req; - assign router_2_17_req_in[1] = router_3_17_to_router_2_17_req; - assign router_2_17_req_in[2] = router_2_16_to_router_2_17_req; - assign router_2_17_req_in[3] = router_1_17_to_router_2_17_req; - assign router_2_17_req_in[4] = magia_tile_ni_2_17_to_router_2_17_req; - - assign router_2_17_to_router_2_18_rsp = router_2_17_rsp_out[0]; - assign router_2_17_to_router_3_17_rsp = router_2_17_rsp_out[1]; - assign router_2_17_to_router_2_16_rsp = router_2_17_rsp_out[2]; - assign router_2_17_to_router_1_17_rsp = router_2_17_rsp_out[3]; - assign router_2_17_to_magia_tile_ni_2_17_rsp = router_2_17_rsp_out[4]; - - assign router_2_17_to_router_2_18_req = router_2_17_req_out[0]; - assign router_2_17_to_router_3_17_req = router_2_17_req_out[1]; - assign router_2_17_to_router_2_16_req = router_2_17_req_out[2]; - assign router_2_17_to_router_1_17_req = router_2_17_req_out[3]; - assign router_2_17_to_magia_tile_ni_2_17_req = router_2_17_req_out[4]; - - assign router_2_17_rsp_in[0] = router_2_18_to_router_2_17_rsp; - assign router_2_17_rsp_in[1] = router_3_17_to_router_2_17_rsp; - assign router_2_17_rsp_in[2] = router_2_16_to_router_2_17_rsp; - assign router_2_17_rsp_in[3] = router_1_17_to_router_2_17_rsp; - assign router_2_17_rsp_in[4] = magia_tile_ni_2_17_to_router_2_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_17_req_in), - .floo_rsp_o (router_2_17_rsp_out), - .floo_req_o (router_2_17_req_out), - .floo_rsp_i (router_2_17_rsp_in) -); - - -floo_req_t [4:0] router_2_18_req_in; -floo_rsp_t [4:0] router_2_18_rsp_out; -floo_req_t [4:0] router_2_18_req_out; -floo_rsp_t [4:0] router_2_18_rsp_in; - - assign router_2_18_req_in[0] = router_2_19_to_router_2_18_req; - assign router_2_18_req_in[1] = router_3_18_to_router_2_18_req; - assign router_2_18_req_in[2] = router_2_17_to_router_2_18_req; - assign router_2_18_req_in[3] = router_1_18_to_router_2_18_req; - assign router_2_18_req_in[4] = magia_tile_ni_2_18_to_router_2_18_req; - - assign router_2_18_to_router_2_19_rsp = router_2_18_rsp_out[0]; - assign router_2_18_to_router_3_18_rsp = router_2_18_rsp_out[1]; - assign router_2_18_to_router_2_17_rsp = router_2_18_rsp_out[2]; - assign router_2_18_to_router_1_18_rsp = router_2_18_rsp_out[3]; - assign router_2_18_to_magia_tile_ni_2_18_rsp = router_2_18_rsp_out[4]; - - assign router_2_18_to_router_2_19_req = router_2_18_req_out[0]; - assign router_2_18_to_router_3_18_req = router_2_18_req_out[1]; - assign router_2_18_to_router_2_17_req = router_2_18_req_out[2]; - assign router_2_18_to_router_1_18_req = router_2_18_req_out[3]; - assign router_2_18_to_magia_tile_ni_2_18_req = router_2_18_req_out[4]; - - assign router_2_18_rsp_in[0] = router_2_19_to_router_2_18_rsp; - assign router_2_18_rsp_in[1] = router_3_18_to_router_2_18_rsp; - assign router_2_18_rsp_in[2] = router_2_17_to_router_2_18_rsp; - assign router_2_18_rsp_in[3] = router_1_18_to_router_2_18_rsp; - assign router_2_18_rsp_in[4] = magia_tile_ni_2_18_to_router_2_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_18_req_in), - .floo_rsp_o (router_2_18_rsp_out), - .floo_req_o (router_2_18_req_out), - .floo_rsp_i (router_2_18_rsp_in) -); - - -floo_req_t [4:0] router_2_19_req_in; -floo_rsp_t [4:0] router_2_19_rsp_out; -floo_req_t [4:0] router_2_19_req_out; -floo_rsp_t [4:0] router_2_19_rsp_in; - - assign router_2_19_req_in[0] = router_2_20_to_router_2_19_req; - assign router_2_19_req_in[1] = router_3_19_to_router_2_19_req; - assign router_2_19_req_in[2] = router_2_18_to_router_2_19_req; - assign router_2_19_req_in[3] = router_1_19_to_router_2_19_req; - assign router_2_19_req_in[4] = magia_tile_ni_2_19_to_router_2_19_req; - - assign router_2_19_to_router_2_20_rsp = router_2_19_rsp_out[0]; - assign router_2_19_to_router_3_19_rsp = router_2_19_rsp_out[1]; - assign router_2_19_to_router_2_18_rsp = router_2_19_rsp_out[2]; - assign router_2_19_to_router_1_19_rsp = router_2_19_rsp_out[3]; - assign router_2_19_to_magia_tile_ni_2_19_rsp = router_2_19_rsp_out[4]; - - assign router_2_19_to_router_2_20_req = router_2_19_req_out[0]; - assign router_2_19_to_router_3_19_req = router_2_19_req_out[1]; - assign router_2_19_to_router_2_18_req = router_2_19_req_out[2]; - assign router_2_19_to_router_1_19_req = router_2_19_req_out[3]; - assign router_2_19_to_magia_tile_ni_2_19_req = router_2_19_req_out[4]; - - assign router_2_19_rsp_in[0] = router_2_20_to_router_2_19_rsp; - assign router_2_19_rsp_in[1] = router_3_19_to_router_2_19_rsp; - assign router_2_19_rsp_in[2] = router_2_18_to_router_2_19_rsp; - assign router_2_19_rsp_in[3] = router_1_19_to_router_2_19_rsp; - assign router_2_19_rsp_in[4] = magia_tile_ni_2_19_to_router_2_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_19_req_in), - .floo_rsp_o (router_2_19_rsp_out), - .floo_req_o (router_2_19_req_out), - .floo_rsp_i (router_2_19_rsp_in) -); - - -floo_req_t [4:0] router_2_20_req_in; -floo_rsp_t [4:0] router_2_20_rsp_out; -floo_req_t [4:0] router_2_20_req_out; -floo_rsp_t [4:0] router_2_20_rsp_in; - - assign router_2_20_req_in[0] = router_2_21_to_router_2_20_req; - assign router_2_20_req_in[1] = router_3_20_to_router_2_20_req; - assign router_2_20_req_in[2] = router_2_19_to_router_2_20_req; - assign router_2_20_req_in[3] = router_1_20_to_router_2_20_req; - assign router_2_20_req_in[4] = magia_tile_ni_2_20_to_router_2_20_req; - - assign router_2_20_to_router_2_21_rsp = router_2_20_rsp_out[0]; - assign router_2_20_to_router_3_20_rsp = router_2_20_rsp_out[1]; - assign router_2_20_to_router_2_19_rsp = router_2_20_rsp_out[2]; - assign router_2_20_to_router_1_20_rsp = router_2_20_rsp_out[3]; - assign router_2_20_to_magia_tile_ni_2_20_rsp = router_2_20_rsp_out[4]; - - assign router_2_20_to_router_2_21_req = router_2_20_req_out[0]; - assign router_2_20_to_router_3_20_req = router_2_20_req_out[1]; - assign router_2_20_to_router_2_19_req = router_2_20_req_out[2]; - assign router_2_20_to_router_1_20_req = router_2_20_req_out[3]; - assign router_2_20_to_magia_tile_ni_2_20_req = router_2_20_req_out[4]; - - assign router_2_20_rsp_in[0] = router_2_21_to_router_2_20_rsp; - assign router_2_20_rsp_in[1] = router_3_20_to_router_2_20_rsp; - assign router_2_20_rsp_in[2] = router_2_19_to_router_2_20_rsp; - assign router_2_20_rsp_in[3] = router_1_20_to_router_2_20_rsp; - assign router_2_20_rsp_in[4] = magia_tile_ni_2_20_to_router_2_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_20_req_in), - .floo_rsp_o (router_2_20_rsp_out), - .floo_req_o (router_2_20_req_out), - .floo_rsp_i (router_2_20_rsp_in) -); - - -floo_req_t [4:0] router_2_21_req_in; -floo_rsp_t [4:0] router_2_21_rsp_out; -floo_req_t [4:0] router_2_21_req_out; -floo_rsp_t [4:0] router_2_21_rsp_in; - - assign router_2_21_req_in[0] = router_2_22_to_router_2_21_req; - assign router_2_21_req_in[1] = router_3_21_to_router_2_21_req; - assign router_2_21_req_in[2] = router_2_20_to_router_2_21_req; - assign router_2_21_req_in[3] = router_1_21_to_router_2_21_req; - assign router_2_21_req_in[4] = magia_tile_ni_2_21_to_router_2_21_req; - - assign router_2_21_to_router_2_22_rsp = router_2_21_rsp_out[0]; - assign router_2_21_to_router_3_21_rsp = router_2_21_rsp_out[1]; - assign router_2_21_to_router_2_20_rsp = router_2_21_rsp_out[2]; - assign router_2_21_to_router_1_21_rsp = router_2_21_rsp_out[3]; - assign router_2_21_to_magia_tile_ni_2_21_rsp = router_2_21_rsp_out[4]; - - assign router_2_21_to_router_2_22_req = router_2_21_req_out[0]; - assign router_2_21_to_router_3_21_req = router_2_21_req_out[1]; - assign router_2_21_to_router_2_20_req = router_2_21_req_out[2]; - assign router_2_21_to_router_1_21_req = router_2_21_req_out[3]; - assign router_2_21_to_magia_tile_ni_2_21_req = router_2_21_req_out[4]; - - assign router_2_21_rsp_in[0] = router_2_22_to_router_2_21_rsp; - assign router_2_21_rsp_in[1] = router_3_21_to_router_2_21_rsp; - assign router_2_21_rsp_in[2] = router_2_20_to_router_2_21_rsp; - assign router_2_21_rsp_in[3] = router_1_21_to_router_2_21_rsp; - assign router_2_21_rsp_in[4] = magia_tile_ni_2_21_to_router_2_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_21_req_in), - .floo_rsp_o (router_2_21_rsp_out), - .floo_req_o (router_2_21_req_out), - .floo_rsp_i (router_2_21_rsp_in) -); - - -floo_req_t [4:0] router_2_22_req_in; -floo_rsp_t [4:0] router_2_22_rsp_out; -floo_req_t [4:0] router_2_22_req_out; -floo_rsp_t [4:0] router_2_22_rsp_in; - - assign router_2_22_req_in[0] = router_2_23_to_router_2_22_req; - assign router_2_22_req_in[1] = router_3_22_to_router_2_22_req; - assign router_2_22_req_in[2] = router_2_21_to_router_2_22_req; - assign router_2_22_req_in[3] = router_1_22_to_router_2_22_req; - assign router_2_22_req_in[4] = magia_tile_ni_2_22_to_router_2_22_req; - - assign router_2_22_to_router_2_23_rsp = router_2_22_rsp_out[0]; - assign router_2_22_to_router_3_22_rsp = router_2_22_rsp_out[1]; - assign router_2_22_to_router_2_21_rsp = router_2_22_rsp_out[2]; - assign router_2_22_to_router_1_22_rsp = router_2_22_rsp_out[3]; - assign router_2_22_to_magia_tile_ni_2_22_rsp = router_2_22_rsp_out[4]; - - assign router_2_22_to_router_2_23_req = router_2_22_req_out[0]; - assign router_2_22_to_router_3_22_req = router_2_22_req_out[1]; - assign router_2_22_to_router_2_21_req = router_2_22_req_out[2]; - assign router_2_22_to_router_1_22_req = router_2_22_req_out[3]; - assign router_2_22_to_magia_tile_ni_2_22_req = router_2_22_req_out[4]; - - assign router_2_22_rsp_in[0] = router_2_23_to_router_2_22_rsp; - assign router_2_22_rsp_in[1] = router_3_22_to_router_2_22_rsp; - assign router_2_22_rsp_in[2] = router_2_21_to_router_2_22_rsp; - assign router_2_22_rsp_in[3] = router_1_22_to_router_2_22_rsp; - assign router_2_22_rsp_in[4] = magia_tile_ni_2_22_to_router_2_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_22_req_in), - .floo_rsp_o (router_2_22_rsp_out), - .floo_req_o (router_2_22_req_out), - .floo_rsp_i (router_2_22_rsp_in) -); - - -floo_req_t [4:0] router_2_23_req_in; -floo_rsp_t [4:0] router_2_23_rsp_out; -floo_req_t [4:0] router_2_23_req_out; -floo_rsp_t [4:0] router_2_23_rsp_in; - - assign router_2_23_req_in[0] = router_2_24_to_router_2_23_req; - assign router_2_23_req_in[1] = router_3_23_to_router_2_23_req; - assign router_2_23_req_in[2] = router_2_22_to_router_2_23_req; - assign router_2_23_req_in[3] = router_1_23_to_router_2_23_req; - assign router_2_23_req_in[4] = magia_tile_ni_2_23_to_router_2_23_req; - - assign router_2_23_to_router_2_24_rsp = router_2_23_rsp_out[0]; - assign router_2_23_to_router_3_23_rsp = router_2_23_rsp_out[1]; - assign router_2_23_to_router_2_22_rsp = router_2_23_rsp_out[2]; - assign router_2_23_to_router_1_23_rsp = router_2_23_rsp_out[3]; - assign router_2_23_to_magia_tile_ni_2_23_rsp = router_2_23_rsp_out[4]; - - assign router_2_23_to_router_2_24_req = router_2_23_req_out[0]; - assign router_2_23_to_router_3_23_req = router_2_23_req_out[1]; - assign router_2_23_to_router_2_22_req = router_2_23_req_out[2]; - assign router_2_23_to_router_1_23_req = router_2_23_req_out[3]; - assign router_2_23_to_magia_tile_ni_2_23_req = router_2_23_req_out[4]; - - assign router_2_23_rsp_in[0] = router_2_24_to_router_2_23_rsp; - assign router_2_23_rsp_in[1] = router_3_23_to_router_2_23_rsp; - assign router_2_23_rsp_in[2] = router_2_22_to_router_2_23_rsp; - assign router_2_23_rsp_in[3] = router_1_23_to_router_2_23_rsp; - assign router_2_23_rsp_in[4] = magia_tile_ni_2_23_to_router_2_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_23_req_in), - .floo_rsp_o (router_2_23_rsp_out), - .floo_req_o (router_2_23_req_out), - .floo_rsp_i (router_2_23_rsp_in) -); - - -floo_req_t [4:0] router_2_24_req_in; -floo_rsp_t [4:0] router_2_24_rsp_out; -floo_req_t [4:0] router_2_24_req_out; -floo_rsp_t [4:0] router_2_24_rsp_in; - - assign router_2_24_req_in[0] = router_2_25_to_router_2_24_req; - assign router_2_24_req_in[1] = router_3_24_to_router_2_24_req; - assign router_2_24_req_in[2] = router_2_23_to_router_2_24_req; - assign router_2_24_req_in[3] = router_1_24_to_router_2_24_req; - assign router_2_24_req_in[4] = magia_tile_ni_2_24_to_router_2_24_req; - - assign router_2_24_to_router_2_25_rsp = router_2_24_rsp_out[0]; - assign router_2_24_to_router_3_24_rsp = router_2_24_rsp_out[1]; - assign router_2_24_to_router_2_23_rsp = router_2_24_rsp_out[2]; - assign router_2_24_to_router_1_24_rsp = router_2_24_rsp_out[3]; - assign router_2_24_to_magia_tile_ni_2_24_rsp = router_2_24_rsp_out[4]; - - assign router_2_24_to_router_2_25_req = router_2_24_req_out[0]; - assign router_2_24_to_router_3_24_req = router_2_24_req_out[1]; - assign router_2_24_to_router_2_23_req = router_2_24_req_out[2]; - assign router_2_24_to_router_1_24_req = router_2_24_req_out[3]; - assign router_2_24_to_magia_tile_ni_2_24_req = router_2_24_req_out[4]; - - assign router_2_24_rsp_in[0] = router_2_25_to_router_2_24_rsp; - assign router_2_24_rsp_in[1] = router_3_24_to_router_2_24_rsp; - assign router_2_24_rsp_in[2] = router_2_23_to_router_2_24_rsp; - assign router_2_24_rsp_in[3] = router_1_24_to_router_2_24_rsp; - assign router_2_24_rsp_in[4] = magia_tile_ni_2_24_to_router_2_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_24_req_in), - .floo_rsp_o (router_2_24_rsp_out), - .floo_req_o (router_2_24_req_out), - .floo_rsp_i (router_2_24_rsp_in) -); - - -floo_req_t [4:0] router_2_25_req_in; -floo_rsp_t [4:0] router_2_25_rsp_out; -floo_req_t [4:0] router_2_25_req_out; -floo_rsp_t [4:0] router_2_25_rsp_in; - - assign router_2_25_req_in[0] = router_2_26_to_router_2_25_req; - assign router_2_25_req_in[1] = router_3_25_to_router_2_25_req; - assign router_2_25_req_in[2] = router_2_24_to_router_2_25_req; - assign router_2_25_req_in[3] = router_1_25_to_router_2_25_req; - assign router_2_25_req_in[4] = magia_tile_ni_2_25_to_router_2_25_req; - - assign router_2_25_to_router_2_26_rsp = router_2_25_rsp_out[0]; - assign router_2_25_to_router_3_25_rsp = router_2_25_rsp_out[1]; - assign router_2_25_to_router_2_24_rsp = router_2_25_rsp_out[2]; - assign router_2_25_to_router_1_25_rsp = router_2_25_rsp_out[3]; - assign router_2_25_to_magia_tile_ni_2_25_rsp = router_2_25_rsp_out[4]; - - assign router_2_25_to_router_2_26_req = router_2_25_req_out[0]; - assign router_2_25_to_router_3_25_req = router_2_25_req_out[1]; - assign router_2_25_to_router_2_24_req = router_2_25_req_out[2]; - assign router_2_25_to_router_1_25_req = router_2_25_req_out[3]; - assign router_2_25_to_magia_tile_ni_2_25_req = router_2_25_req_out[4]; - - assign router_2_25_rsp_in[0] = router_2_26_to_router_2_25_rsp; - assign router_2_25_rsp_in[1] = router_3_25_to_router_2_25_rsp; - assign router_2_25_rsp_in[2] = router_2_24_to_router_2_25_rsp; - assign router_2_25_rsp_in[3] = router_1_25_to_router_2_25_rsp; - assign router_2_25_rsp_in[4] = magia_tile_ni_2_25_to_router_2_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_25_req_in), - .floo_rsp_o (router_2_25_rsp_out), - .floo_req_o (router_2_25_req_out), - .floo_rsp_i (router_2_25_rsp_in) -); - - -floo_req_t [4:0] router_2_26_req_in; -floo_rsp_t [4:0] router_2_26_rsp_out; -floo_req_t [4:0] router_2_26_req_out; -floo_rsp_t [4:0] router_2_26_rsp_in; - - assign router_2_26_req_in[0] = router_2_27_to_router_2_26_req; - assign router_2_26_req_in[1] = router_3_26_to_router_2_26_req; - assign router_2_26_req_in[2] = router_2_25_to_router_2_26_req; - assign router_2_26_req_in[3] = router_1_26_to_router_2_26_req; - assign router_2_26_req_in[4] = magia_tile_ni_2_26_to_router_2_26_req; - - assign router_2_26_to_router_2_27_rsp = router_2_26_rsp_out[0]; - assign router_2_26_to_router_3_26_rsp = router_2_26_rsp_out[1]; - assign router_2_26_to_router_2_25_rsp = router_2_26_rsp_out[2]; - assign router_2_26_to_router_1_26_rsp = router_2_26_rsp_out[3]; - assign router_2_26_to_magia_tile_ni_2_26_rsp = router_2_26_rsp_out[4]; - - assign router_2_26_to_router_2_27_req = router_2_26_req_out[0]; - assign router_2_26_to_router_3_26_req = router_2_26_req_out[1]; - assign router_2_26_to_router_2_25_req = router_2_26_req_out[2]; - assign router_2_26_to_router_1_26_req = router_2_26_req_out[3]; - assign router_2_26_to_magia_tile_ni_2_26_req = router_2_26_req_out[4]; - - assign router_2_26_rsp_in[0] = router_2_27_to_router_2_26_rsp; - assign router_2_26_rsp_in[1] = router_3_26_to_router_2_26_rsp; - assign router_2_26_rsp_in[2] = router_2_25_to_router_2_26_rsp; - assign router_2_26_rsp_in[3] = router_1_26_to_router_2_26_rsp; - assign router_2_26_rsp_in[4] = magia_tile_ni_2_26_to_router_2_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_26_req_in), - .floo_rsp_o (router_2_26_rsp_out), - .floo_req_o (router_2_26_req_out), - .floo_rsp_i (router_2_26_rsp_in) -); - - -floo_req_t [4:0] router_2_27_req_in; -floo_rsp_t [4:0] router_2_27_rsp_out; -floo_req_t [4:0] router_2_27_req_out; -floo_rsp_t [4:0] router_2_27_rsp_in; - - assign router_2_27_req_in[0] = router_2_28_to_router_2_27_req; - assign router_2_27_req_in[1] = router_3_27_to_router_2_27_req; - assign router_2_27_req_in[2] = router_2_26_to_router_2_27_req; - assign router_2_27_req_in[3] = router_1_27_to_router_2_27_req; - assign router_2_27_req_in[4] = magia_tile_ni_2_27_to_router_2_27_req; - - assign router_2_27_to_router_2_28_rsp = router_2_27_rsp_out[0]; - assign router_2_27_to_router_3_27_rsp = router_2_27_rsp_out[1]; - assign router_2_27_to_router_2_26_rsp = router_2_27_rsp_out[2]; - assign router_2_27_to_router_1_27_rsp = router_2_27_rsp_out[3]; - assign router_2_27_to_magia_tile_ni_2_27_rsp = router_2_27_rsp_out[4]; - - assign router_2_27_to_router_2_28_req = router_2_27_req_out[0]; - assign router_2_27_to_router_3_27_req = router_2_27_req_out[1]; - assign router_2_27_to_router_2_26_req = router_2_27_req_out[2]; - assign router_2_27_to_router_1_27_req = router_2_27_req_out[3]; - assign router_2_27_to_magia_tile_ni_2_27_req = router_2_27_req_out[4]; - - assign router_2_27_rsp_in[0] = router_2_28_to_router_2_27_rsp; - assign router_2_27_rsp_in[1] = router_3_27_to_router_2_27_rsp; - assign router_2_27_rsp_in[2] = router_2_26_to_router_2_27_rsp; - assign router_2_27_rsp_in[3] = router_1_27_to_router_2_27_rsp; - assign router_2_27_rsp_in[4] = magia_tile_ni_2_27_to_router_2_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_27_req_in), - .floo_rsp_o (router_2_27_rsp_out), - .floo_req_o (router_2_27_req_out), - .floo_rsp_i (router_2_27_rsp_in) -); - - -floo_req_t [4:0] router_2_28_req_in; -floo_rsp_t [4:0] router_2_28_rsp_out; -floo_req_t [4:0] router_2_28_req_out; -floo_rsp_t [4:0] router_2_28_rsp_in; - - assign router_2_28_req_in[0] = router_2_29_to_router_2_28_req; - assign router_2_28_req_in[1] = router_3_28_to_router_2_28_req; - assign router_2_28_req_in[2] = router_2_27_to_router_2_28_req; - assign router_2_28_req_in[3] = router_1_28_to_router_2_28_req; - assign router_2_28_req_in[4] = magia_tile_ni_2_28_to_router_2_28_req; - - assign router_2_28_to_router_2_29_rsp = router_2_28_rsp_out[0]; - assign router_2_28_to_router_3_28_rsp = router_2_28_rsp_out[1]; - assign router_2_28_to_router_2_27_rsp = router_2_28_rsp_out[2]; - assign router_2_28_to_router_1_28_rsp = router_2_28_rsp_out[3]; - assign router_2_28_to_magia_tile_ni_2_28_rsp = router_2_28_rsp_out[4]; - - assign router_2_28_to_router_2_29_req = router_2_28_req_out[0]; - assign router_2_28_to_router_3_28_req = router_2_28_req_out[1]; - assign router_2_28_to_router_2_27_req = router_2_28_req_out[2]; - assign router_2_28_to_router_1_28_req = router_2_28_req_out[3]; - assign router_2_28_to_magia_tile_ni_2_28_req = router_2_28_req_out[4]; - - assign router_2_28_rsp_in[0] = router_2_29_to_router_2_28_rsp; - assign router_2_28_rsp_in[1] = router_3_28_to_router_2_28_rsp; - assign router_2_28_rsp_in[2] = router_2_27_to_router_2_28_rsp; - assign router_2_28_rsp_in[3] = router_1_28_to_router_2_28_rsp; - assign router_2_28_rsp_in[4] = magia_tile_ni_2_28_to_router_2_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_28_req_in), - .floo_rsp_o (router_2_28_rsp_out), - .floo_req_o (router_2_28_req_out), - .floo_rsp_i (router_2_28_rsp_in) -); - - -floo_req_t [4:0] router_2_29_req_in; -floo_rsp_t [4:0] router_2_29_rsp_out; -floo_req_t [4:0] router_2_29_req_out; -floo_rsp_t [4:0] router_2_29_rsp_in; - - assign router_2_29_req_in[0] = router_2_30_to_router_2_29_req; - assign router_2_29_req_in[1] = router_3_29_to_router_2_29_req; - assign router_2_29_req_in[2] = router_2_28_to_router_2_29_req; - assign router_2_29_req_in[3] = router_1_29_to_router_2_29_req; - assign router_2_29_req_in[4] = magia_tile_ni_2_29_to_router_2_29_req; - - assign router_2_29_to_router_2_30_rsp = router_2_29_rsp_out[0]; - assign router_2_29_to_router_3_29_rsp = router_2_29_rsp_out[1]; - assign router_2_29_to_router_2_28_rsp = router_2_29_rsp_out[2]; - assign router_2_29_to_router_1_29_rsp = router_2_29_rsp_out[3]; - assign router_2_29_to_magia_tile_ni_2_29_rsp = router_2_29_rsp_out[4]; - - assign router_2_29_to_router_2_30_req = router_2_29_req_out[0]; - assign router_2_29_to_router_3_29_req = router_2_29_req_out[1]; - assign router_2_29_to_router_2_28_req = router_2_29_req_out[2]; - assign router_2_29_to_router_1_29_req = router_2_29_req_out[3]; - assign router_2_29_to_magia_tile_ni_2_29_req = router_2_29_req_out[4]; - - assign router_2_29_rsp_in[0] = router_2_30_to_router_2_29_rsp; - assign router_2_29_rsp_in[1] = router_3_29_to_router_2_29_rsp; - assign router_2_29_rsp_in[2] = router_2_28_to_router_2_29_rsp; - assign router_2_29_rsp_in[3] = router_1_29_to_router_2_29_rsp; - assign router_2_29_rsp_in[4] = magia_tile_ni_2_29_to_router_2_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_29_req_in), - .floo_rsp_o (router_2_29_rsp_out), - .floo_req_o (router_2_29_req_out), - .floo_rsp_i (router_2_29_rsp_in) -); - - -floo_req_t [4:0] router_2_30_req_in; -floo_rsp_t [4:0] router_2_30_rsp_out; -floo_req_t [4:0] router_2_30_req_out; -floo_rsp_t [4:0] router_2_30_rsp_in; - - assign router_2_30_req_in[0] = router_2_31_to_router_2_30_req; - assign router_2_30_req_in[1] = router_3_30_to_router_2_30_req; - assign router_2_30_req_in[2] = router_2_29_to_router_2_30_req; - assign router_2_30_req_in[3] = router_1_30_to_router_2_30_req; - assign router_2_30_req_in[4] = magia_tile_ni_2_30_to_router_2_30_req; - - assign router_2_30_to_router_2_31_rsp = router_2_30_rsp_out[0]; - assign router_2_30_to_router_3_30_rsp = router_2_30_rsp_out[1]; - assign router_2_30_to_router_2_29_rsp = router_2_30_rsp_out[2]; - assign router_2_30_to_router_1_30_rsp = router_2_30_rsp_out[3]; - assign router_2_30_to_magia_tile_ni_2_30_rsp = router_2_30_rsp_out[4]; - - assign router_2_30_to_router_2_31_req = router_2_30_req_out[0]; - assign router_2_30_to_router_3_30_req = router_2_30_req_out[1]; - assign router_2_30_to_router_2_29_req = router_2_30_req_out[2]; - assign router_2_30_to_router_1_30_req = router_2_30_req_out[3]; - assign router_2_30_to_magia_tile_ni_2_30_req = router_2_30_req_out[4]; - - assign router_2_30_rsp_in[0] = router_2_31_to_router_2_30_rsp; - assign router_2_30_rsp_in[1] = router_3_30_to_router_2_30_rsp; - assign router_2_30_rsp_in[2] = router_2_29_to_router_2_30_rsp; - assign router_2_30_rsp_in[3] = router_1_30_to_router_2_30_rsp; - assign router_2_30_rsp_in[4] = magia_tile_ni_2_30_to_router_2_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_30_req_in), - .floo_rsp_o (router_2_30_rsp_out), - .floo_req_o (router_2_30_req_out), - .floo_rsp_i (router_2_30_rsp_in) -); - - -floo_req_t [4:0] router_2_31_req_in; -floo_rsp_t [4:0] router_2_31_rsp_out; -floo_req_t [4:0] router_2_31_req_out; -floo_rsp_t [4:0] router_2_31_rsp_in; - - assign router_2_31_req_in[0] = '0; - assign router_2_31_req_in[1] = router_3_31_to_router_2_31_req; - assign router_2_31_req_in[2] = router_2_30_to_router_2_31_req; - assign router_2_31_req_in[3] = router_1_31_to_router_2_31_req; - assign router_2_31_req_in[4] = magia_tile_ni_2_31_to_router_2_31_req; - - assign router_2_31_to_router_3_31_rsp = router_2_31_rsp_out[1]; - assign router_2_31_to_router_2_30_rsp = router_2_31_rsp_out[2]; - assign router_2_31_to_router_1_31_rsp = router_2_31_rsp_out[3]; - assign router_2_31_to_magia_tile_ni_2_31_rsp = router_2_31_rsp_out[4]; - - assign router_2_31_to_router_3_31_req = router_2_31_req_out[1]; - assign router_2_31_to_router_2_30_req = router_2_31_req_out[2]; - assign router_2_31_to_router_1_31_req = router_2_31_req_out[3]; - assign router_2_31_to_magia_tile_ni_2_31_req = router_2_31_req_out[4]; - - assign router_2_31_rsp_in[0] = '0; - assign router_2_31_rsp_in[1] = router_3_31_to_router_2_31_rsp; - assign router_2_31_rsp_in[2] = router_2_30_to_router_2_31_rsp; - assign router_2_31_rsp_in[3] = router_1_31_to_router_2_31_rsp; - assign router_2_31_rsp_in[4] = magia_tile_ni_2_31_to_router_2_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_31_req_in), - .floo_rsp_o (router_2_31_rsp_out), - .floo_req_o (router_2_31_req_out), - .floo_rsp_i (router_2_31_rsp_in) -); - - -floo_req_t [4:0] router_3_0_req_in; -floo_rsp_t [4:0] router_3_0_rsp_out; -floo_req_t [4:0] router_3_0_req_out; -floo_rsp_t [4:0] router_3_0_rsp_in; - - assign router_3_0_req_in[0] = router_3_1_to_router_3_0_req; - assign router_3_0_req_in[1] = router_4_0_to_router_3_0_req; - assign router_3_0_req_in[2] = '0; - assign router_3_0_req_in[3] = router_2_0_to_router_3_0_req; - assign router_3_0_req_in[4] = magia_tile_ni_3_0_to_router_3_0_req; - - assign router_3_0_to_router_3_1_rsp = router_3_0_rsp_out[0]; - assign router_3_0_to_router_4_0_rsp = router_3_0_rsp_out[1]; - assign router_3_0_to_router_2_0_rsp = router_3_0_rsp_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_rsp = router_3_0_rsp_out[4]; - - assign router_3_0_to_router_3_1_req = router_3_0_req_out[0]; - assign router_3_0_to_router_4_0_req = router_3_0_req_out[1]; - assign router_3_0_to_router_2_0_req = router_3_0_req_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_req = router_3_0_req_out[4]; - - assign router_3_0_rsp_in[0] = router_3_1_to_router_3_0_rsp; - assign router_3_0_rsp_in[1] = router_4_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[2] = '0; - assign router_3_0_rsp_in[3] = router_2_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[4] = magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_0_req_in), - .floo_rsp_o (router_3_0_rsp_out), - .floo_req_o (router_3_0_req_out), - .floo_rsp_i (router_3_0_rsp_in) -); - - -floo_req_t [4:0] router_3_1_req_in; -floo_rsp_t [4:0] router_3_1_rsp_out; -floo_req_t [4:0] router_3_1_req_out; -floo_rsp_t [4:0] router_3_1_rsp_in; - - assign router_3_1_req_in[0] = router_3_2_to_router_3_1_req; - assign router_3_1_req_in[1] = router_4_1_to_router_3_1_req; - assign router_3_1_req_in[2] = router_3_0_to_router_3_1_req; - assign router_3_1_req_in[3] = router_2_1_to_router_3_1_req; - assign router_3_1_req_in[4] = magia_tile_ni_3_1_to_router_3_1_req; - - assign router_3_1_to_router_3_2_rsp = router_3_1_rsp_out[0]; - assign router_3_1_to_router_4_1_rsp = router_3_1_rsp_out[1]; - assign router_3_1_to_router_3_0_rsp = router_3_1_rsp_out[2]; - assign router_3_1_to_router_2_1_rsp = router_3_1_rsp_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_rsp = router_3_1_rsp_out[4]; - - assign router_3_1_to_router_3_2_req = router_3_1_req_out[0]; - assign router_3_1_to_router_4_1_req = router_3_1_req_out[1]; - assign router_3_1_to_router_3_0_req = router_3_1_req_out[2]; - assign router_3_1_to_router_2_1_req = router_3_1_req_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_req = router_3_1_req_out[4]; - - assign router_3_1_rsp_in[0] = router_3_2_to_router_3_1_rsp; - assign router_3_1_rsp_in[1] = router_4_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[2] = router_3_0_to_router_3_1_rsp; - assign router_3_1_rsp_in[3] = router_2_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[4] = magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_1_req_in), - .floo_rsp_o (router_3_1_rsp_out), - .floo_req_o (router_3_1_req_out), - .floo_rsp_i (router_3_1_rsp_in) -); - - -floo_req_t [4:0] router_3_2_req_in; -floo_rsp_t [4:0] router_3_2_rsp_out; -floo_req_t [4:0] router_3_2_req_out; -floo_rsp_t [4:0] router_3_2_rsp_in; - - assign router_3_2_req_in[0] = router_3_3_to_router_3_2_req; - assign router_3_2_req_in[1] = router_4_2_to_router_3_2_req; - assign router_3_2_req_in[2] = router_3_1_to_router_3_2_req; - assign router_3_2_req_in[3] = router_2_2_to_router_3_2_req; - assign router_3_2_req_in[4] = magia_tile_ni_3_2_to_router_3_2_req; - - assign router_3_2_to_router_3_3_rsp = router_3_2_rsp_out[0]; - assign router_3_2_to_router_4_2_rsp = router_3_2_rsp_out[1]; - assign router_3_2_to_router_3_1_rsp = router_3_2_rsp_out[2]; - assign router_3_2_to_router_2_2_rsp = router_3_2_rsp_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_rsp = router_3_2_rsp_out[4]; - - assign router_3_2_to_router_3_3_req = router_3_2_req_out[0]; - assign router_3_2_to_router_4_2_req = router_3_2_req_out[1]; - assign router_3_2_to_router_3_1_req = router_3_2_req_out[2]; - assign router_3_2_to_router_2_2_req = router_3_2_req_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_req = router_3_2_req_out[4]; - - assign router_3_2_rsp_in[0] = router_3_3_to_router_3_2_rsp; - assign router_3_2_rsp_in[1] = router_4_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[2] = router_3_1_to_router_3_2_rsp; - assign router_3_2_rsp_in[3] = router_2_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[4] = magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_2_req_in), - .floo_rsp_o (router_3_2_rsp_out), - .floo_req_o (router_3_2_req_out), - .floo_rsp_i (router_3_2_rsp_in) -); - - -floo_req_t [4:0] router_3_3_req_in; -floo_rsp_t [4:0] router_3_3_rsp_out; -floo_req_t [4:0] router_3_3_req_out; -floo_rsp_t [4:0] router_3_3_rsp_in; - - assign router_3_3_req_in[0] = router_3_4_to_router_3_3_req; - assign router_3_3_req_in[1] = router_4_3_to_router_3_3_req; - assign router_3_3_req_in[2] = router_3_2_to_router_3_3_req; - assign router_3_3_req_in[3] = router_2_3_to_router_3_3_req; - assign router_3_3_req_in[4] = magia_tile_ni_3_3_to_router_3_3_req; - - assign router_3_3_to_router_3_4_rsp = router_3_3_rsp_out[0]; - assign router_3_3_to_router_4_3_rsp = router_3_3_rsp_out[1]; - assign router_3_3_to_router_3_2_rsp = router_3_3_rsp_out[2]; - assign router_3_3_to_router_2_3_rsp = router_3_3_rsp_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_rsp = router_3_3_rsp_out[4]; - - assign router_3_3_to_router_3_4_req = router_3_3_req_out[0]; - assign router_3_3_to_router_4_3_req = router_3_3_req_out[1]; - assign router_3_3_to_router_3_2_req = router_3_3_req_out[2]; - assign router_3_3_to_router_2_3_req = router_3_3_req_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_req = router_3_3_req_out[4]; - - assign router_3_3_rsp_in[0] = router_3_4_to_router_3_3_rsp; - assign router_3_3_rsp_in[1] = router_4_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[2] = router_3_2_to_router_3_3_rsp; - assign router_3_3_rsp_in[3] = router_2_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[4] = magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_3_req_in), - .floo_rsp_o (router_3_3_rsp_out), - .floo_req_o (router_3_3_req_out), - .floo_rsp_i (router_3_3_rsp_in) -); - - -floo_req_t [4:0] router_3_4_req_in; -floo_rsp_t [4:0] router_3_4_rsp_out; -floo_req_t [4:0] router_3_4_req_out; -floo_rsp_t [4:0] router_3_4_rsp_in; - - assign router_3_4_req_in[0] = router_3_5_to_router_3_4_req; - assign router_3_4_req_in[1] = router_4_4_to_router_3_4_req; - assign router_3_4_req_in[2] = router_3_3_to_router_3_4_req; - assign router_3_4_req_in[3] = router_2_4_to_router_3_4_req; - assign router_3_4_req_in[4] = magia_tile_ni_3_4_to_router_3_4_req; - - assign router_3_4_to_router_3_5_rsp = router_3_4_rsp_out[0]; - assign router_3_4_to_router_4_4_rsp = router_3_4_rsp_out[1]; - assign router_3_4_to_router_3_3_rsp = router_3_4_rsp_out[2]; - assign router_3_4_to_router_2_4_rsp = router_3_4_rsp_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_rsp = router_3_4_rsp_out[4]; - - assign router_3_4_to_router_3_5_req = router_3_4_req_out[0]; - assign router_3_4_to_router_4_4_req = router_3_4_req_out[1]; - assign router_3_4_to_router_3_3_req = router_3_4_req_out[2]; - assign router_3_4_to_router_2_4_req = router_3_4_req_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_req = router_3_4_req_out[4]; - - assign router_3_4_rsp_in[0] = router_3_5_to_router_3_4_rsp; - assign router_3_4_rsp_in[1] = router_4_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[2] = router_3_3_to_router_3_4_rsp; - assign router_3_4_rsp_in[3] = router_2_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[4] = magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_4_req_in), - .floo_rsp_o (router_3_4_rsp_out), - .floo_req_o (router_3_4_req_out), - .floo_rsp_i (router_3_4_rsp_in) -); - - -floo_req_t [4:0] router_3_5_req_in; -floo_rsp_t [4:0] router_3_5_rsp_out; -floo_req_t [4:0] router_3_5_req_out; -floo_rsp_t [4:0] router_3_5_rsp_in; - - assign router_3_5_req_in[0] = router_3_6_to_router_3_5_req; - assign router_3_5_req_in[1] = router_4_5_to_router_3_5_req; - assign router_3_5_req_in[2] = router_3_4_to_router_3_5_req; - assign router_3_5_req_in[3] = router_2_5_to_router_3_5_req; - assign router_3_5_req_in[4] = magia_tile_ni_3_5_to_router_3_5_req; - - assign router_3_5_to_router_3_6_rsp = router_3_5_rsp_out[0]; - assign router_3_5_to_router_4_5_rsp = router_3_5_rsp_out[1]; - assign router_3_5_to_router_3_4_rsp = router_3_5_rsp_out[2]; - assign router_3_5_to_router_2_5_rsp = router_3_5_rsp_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_rsp = router_3_5_rsp_out[4]; - - assign router_3_5_to_router_3_6_req = router_3_5_req_out[0]; - assign router_3_5_to_router_4_5_req = router_3_5_req_out[1]; - assign router_3_5_to_router_3_4_req = router_3_5_req_out[2]; - assign router_3_5_to_router_2_5_req = router_3_5_req_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_req = router_3_5_req_out[4]; - - assign router_3_5_rsp_in[0] = router_3_6_to_router_3_5_rsp; - assign router_3_5_rsp_in[1] = router_4_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[2] = router_3_4_to_router_3_5_rsp; - assign router_3_5_rsp_in[3] = router_2_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[4] = magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_5_req_in), - .floo_rsp_o (router_3_5_rsp_out), - .floo_req_o (router_3_5_req_out), - .floo_rsp_i (router_3_5_rsp_in) -); - - -floo_req_t [4:0] router_3_6_req_in; -floo_rsp_t [4:0] router_3_6_rsp_out; -floo_req_t [4:0] router_3_6_req_out; -floo_rsp_t [4:0] router_3_6_rsp_in; - - assign router_3_6_req_in[0] = router_3_7_to_router_3_6_req; - assign router_3_6_req_in[1] = router_4_6_to_router_3_6_req; - assign router_3_6_req_in[2] = router_3_5_to_router_3_6_req; - assign router_3_6_req_in[3] = router_2_6_to_router_3_6_req; - assign router_3_6_req_in[4] = magia_tile_ni_3_6_to_router_3_6_req; - - assign router_3_6_to_router_3_7_rsp = router_3_6_rsp_out[0]; - assign router_3_6_to_router_4_6_rsp = router_3_6_rsp_out[1]; - assign router_3_6_to_router_3_5_rsp = router_3_6_rsp_out[2]; - assign router_3_6_to_router_2_6_rsp = router_3_6_rsp_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_rsp = router_3_6_rsp_out[4]; - - assign router_3_6_to_router_3_7_req = router_3_6_req_out[0]; - assign router_3_6_to_router_4_6_req = router_3_6_req_out[1]; - assign router_3_6_to_router_3_5_req = router_3_6_req_out[2]; - assign router_3_6_to_router_2_6_req = router_3_6_req_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_req = router_3_6_req_out[4]; - - assign router_3_6_rsp_in[0] = router_3_7_to_router_3_6_rsp; - assign router_3_6_rsp_in[1] = router_4_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[2] = router_3_5_to_router_3_6_rsp; - assign router_3_6_rsp_in[3] = router_2_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[4] = magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_6_req_in), - .floo_rsp_o (router_3_6_rsp_out), - .floo_req_o (router_3_6_req_out), - .floo_rsp_i (router_3_6_rsp_in) -); - - -floo_req_t [4:0] router_3_7_req_in; -floo_rsp_t [4:0] router_3_7_rsp_out; -floo_req_t [4:0] router_3_7_req_out; -floo_rsp_t [4:0] router_3_7_rsp_in; - - assign router_3_7_req_in[0] = router_3_8_to_router_3_7_req; - assign router_3_7_req_in[1] = router_4_7_to_router_3_7_req; - assign router_3_7_req_in[2] = router_3_6_to_router_3_7_req; - assign router_3_7_req_in[3] = router_2_7_to_router_3_7_req; - assign router_3_7_req_in[4] = magia_tile_ni_3_7_to_router_3_7_req; - - assign router_3_7_to_router_3_8_rsp = router_3_7_rsp_out[0]; - assign router_3_7_to_router_4_7_rsp = router_3_7_rsp_out[1]; - assign router_3_7_to_router_3_6_rsp = router_3_7_rsp_out[2]; - assign router_3_7_to_router_2_7_rsp = router_3_7_rsp_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_rsp = router_3_7_rsp_out[4]; - - assign router_3_7_to_router_3_8_req = router_3_7_req_out[0]; - assign router_3_7_to_router_4_7_req = router_3_7_req_out[1]; - assign router_3_7_to_router_3_6_req = router_3_7_req_out[2]; - assign router_3_7_to_router_2_7_req = router_3_7_req_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_req = router_3_7_req_out[4]; - - assign router_3_7_rsp_in[0] = router_3_8_to_router_3_7_rsp; - assign router_3_7_rsp_in[1] = router_4_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[2] = router_3_6_to_router_3_7_rsp; - assign router_3_7_rsp_in[3] = router_2_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[4] = magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_7_req_in), - .floo_rsp_o (router_3_7_rsp_out), - .floo_req_o (router_3_7_req_out), - .floo_rsp_i (router_3_7_rsp_in) -); - - -floo_req_t [4:0] router_3_8_req_in; -floo_rsp_t [4:0] router_3_8_rsp_out; -floo_req_t [4:0] router_3_8_req_out; -floo_rsp_t [4:0] router_3_8_rsp_in; - - assign router_3_8_req_in[0] = router_3_9_to_router_3_8_req; - assign router_3_8_req_in[1] = router_4_8_to_router_3_8_req; - assign router_3_8_req_in[2] = router_3_7_to_router_3_8_req; - assign router_3_8_req_in[3] = router_2_8_to_router_3_8_req; - assign router_3_8_req_in[4] = magia_tile_ni_3_8_to_router_3_8_req; - - assign router_3_8_to_router_3_9_rsp = router_3_8_rsp_out[0]; - assign router_3_8_to_router_4_8_rsp = router_3_8_rsp_out[1]; - assign router_3_8_to_router_3_7_rsp = router_3_8_rsp_out[2]; - assign router_3_8_to_router_2_8_rsp = router_3_8_rsp_out[3]; - assign router_3_8_to_magia_tile_ni_3_8_rsp = router_3_8_rsp_out[4]; - - assign router_3_8_to_router_3_9_req = router_3_8_req_out[0]; - assign router_3_8_to_router_4_8_req = router_3_8_req_out[1]; - assign router_3_8_to_router_3_7_req = router_3_8_req_out[2]; - assign router_3_8_to_router_2_8_req = router_3_8_req_out[3]; - assign router_3_8_to_magia_tile_ni_3_8_req = router_3_8_req_out[4]; - - assign router_3_8_rsp_in[0] = router_3_9_to_router_3_8_rsp; - assign router_3_8_rsp_in[1] = router_4_8_to_router_3_8_rsp; - assign router_3_8_rsp_in[2] = router_3_7_to_router_3_8_rsp; - assign router_3_8_rsp_in[3] = router_2_8_to_router_3_8_rsp; - assign router_3_8_rsp_in[4] = magia_tile_ni_3_8_to_router_3_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_8_req_in), - .floo_rsp_o (router_3_8_rsp_out), - .floo_req_o (router_3_8_req_out), - .floo_rsp_i (router_3_8_rsp_in) -); - - -floo_req_t [4:0] router_3_9_req_in; -floo_rsp_t [4:0] router_3_9_rsp_out; -floo_req_t [4:0] router_3_9_req_out; -floo_rsp_t [4:0] router_3_9_rsp_in; - - assign router_3_9_req_in[0] = router_3_10_to_router_3_9_req; - assign router_3_9_req_in[1] = router_4_9_to_router_3_9_req; - assign router_3_9_req_in[2] = router_3_8_to_router_3_9_req; - assign router_3_9_req_in[3] = router_2_9_to_router_3_9_req; - assign router_3_9_req_in[4] = magia_tile_ni_3_9_to_router_3_9_req; - - assign router_3_9_to_router_3_10_rsp = router_3_9_rsp_out[0]; - assign router_3_9_to_router_4_9_rsp = router_3_9_rsp_out[1]; - assign router_3_9_to_router_3_8_rsp = router_3_9_rsp_out[2]; - assign router_3_9_to_router_2_9_rsp = router_3_9_rsp_out[3]; - assign router_3_9_to_magia_tile_ni_3_9_rsp = router_3_9_rsp_out[4]; - - assign router_3_9_to_router_3_10_req = router_3_9_req_out[0]; - assign router_3_9_to_router_4_9_req = router_3_9_req_out[1]; - assign router_3_9_to_router_3_8_req = router_3_9_req_out[2]; - assign router_3_9_to_router_2_9_req = router_3_9_req_out[3]; - assign router_3_9_to_magia_tile_ni_3_9_req = router_3_9_req_out[4]; - - assign router_3_9_rsp_in[0] = router_3_10_to_router_3_9_rsp; - assign router_3_9_rsp_in[1] = router_4_9_to_router_3_9_rsp; - assign router_3_9_rsp_in[2] = router_3_8_to_router_3_9_rsp; - assign router_3_9_rsp_in[3] = router_2_9_to_router_3_9_rsp; - assign router_3_9_rsp_in[4] = magia_tile_ni_3_9_to_router_3_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_9_req_in), - .floo_rsp_o (router_3_9_rsp_out), - .floo_req_o (router_3_9_req_out), - .floo_rsp_i (router_3_9_rsp_in) -); - - -floo_req_t [4:0] router_3_10_req_in; -floo_rsp_t [4:0] router_3_10_rsp_out; -floo_req_t [4:0] router_3_10_req_out; -floo_rsp_t [4:0] router_3_10_rsp_in; - - assign router_3_10_req_in[0] = router_3_11_to_router_3_10_req; - assign router_3_10_req_in[1] = router_4_10_to_router_3_10_req; - assign router_3_10_req_in[2] = router_3_9_to_router_3_10_req; - assign router_3_10_req_in[3] = router_2_10_to_router_3_10_req; - assign router_3_10_req_in[4] = magia_tile_ni_3_10_to_router_3_10_req; - - assign router_3_10_to_router_3_11_rsp = router_3_10_rsp_out[0]; - assign router_3_10_to_router_4_10_rsp = router_3_10_rsp_out[1]; - assign router_3_10_to_router_3_9_rsp = router_3_10_rsp_out[2]; - assign router_3_10_to_router_2_10_rsp = router_3_10_rsp_out[3]; - assign router_3_10_to_magia_tile_ni_3_10_rsp = router_3_10_rsp_out[4]; - - assign router_3_10_to_router_3_11_req = router_3_10_req_out[0]; - assign router_3_10_to_router_4_10_req = router_3_10_req_out[1]; - assign router_3_10_to_router_3_9_req = router_3_10_req_out[2]; - assign router_3_10_to_router_2_10_req = router_3_10_req_out[3]; - assign router_3_10_to_magia_tile_ni_3_10_req = router_3_10_req_out[4]; - - assign router_3_10_rsp_in[0] = router_3_11_to_router_3_10_rsp; - assign router_3_10_rsp_in[1] = router_4_10_to_router_3_10_rsp; - assign router_3_10_rsp_in[2] = router_3_9_to_router_3_10_rsp; - assign router_3_10_rsp_in[3] = router_2_10_to_router_3_10_rsp; - assign router_3_10_rsp_in[4] = magia_tile_ni_3_10_to_router_3_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_10_req_in), - .floo_rsp_o (router_3_10_rsp_out), - .floo_req_o (router_3_10_req_out), - .floo_rsp_i (router_3_10_rsp_in) -); - - -floo_req_t [4:0] router_3_11_req_in; -floo_rsp_t [4:0] router_3_11_rsp_out; -floo_req_t [4:0] router_3_11_req_out; -floo_rsp_t [4:0] router_3_11_rsp_in; - - assign router_3_11_req_in[0] = router_3_12_to_router_3_11_req; - assign router_3_11_req_in[1] = router_4_11_to_router_3_11_req; - assign router_3_11_req_in[2] = router_3_10_to_router_3_11_req; - assign router_3_11_req_in[3] = router_2_11_to_router_3_11_req; - assign router_3_11_req_in[4] = magia_tile_ni_3_11_to_router_3_11_req; - - assign router_3_11_to_router_3_12_rsp = router_3_11_rsp_out[0]; - assign router_3_11_to_router_4_11_rsp = router_3_11_rsp_out[1]; - assign router_3_11_to_router_3_10_rsp = router_3_11_rsp_out[2]; - assign router_3_11_to_router_2_11_rsp = router_3_11_rsp_out[3]; - assign router_3_11_to_magia_tile_ni_3_11_rsp = router_3_11_rsp_out[4]; - - assign router_3_11_to_router_3_12_req = router_3_11_req_out[0]; - assign router_3_11_to_router_4_11_req = router_3_11_req_out[1]; - assign router_3_11_to_router_3_10_req = router_3_11_req_out[2]; - assign router_3_11_to_router_2_11_req = router_3_11_req_out[3]; - assign router_3_11_to_magia_tile_ni_3_11_req = router_3_11_req_out[4]; - - assign router_3_11_rsp_in[0] = router_3_12_to_router_3_11_rsp; - assign router_3_11_rsp_in[1] = router_4_11_to_router_3_11_rsp; - assign router_3_11_rsp_in[2] = router_3_10_to_router_3_11_rsp; - assign router_3_11_rsp_in[3] = router_2_11_to_router_3_11_rsp; - assign router_3_11_rsp_in[4] = magia_tile_ni_3_11_to_router_3_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_11_req_in), - .floo_rsp_o (router_3_11_rsp_out), - .floo_req_o (router_3_11_req_out), - .floo_rsp_i (router_3_11_rsp_in) -); - - -floo_req_t [4:0] router_3_12_req_in; -floo_rsp_t [4:0] router_3_12_rsp_out; -floo_req_t [4:0] router_3_12_req_out; -floo_rsp_t [4:0] router_3_12_rsp_in; - - assign router_3_12_req_in[0] = router_3_13_to_router_3_12_req; - assign router_3_12_req_in[1] = router_4_12_to_router_3_12_req; - assign router_3_12_req_in[2] = router_3_11_to_router_3_12_req; - assign router_3_12_req_in[3] = router_2_12_to_router_3_12_req; - assign router_3_12_req_in[4] = magia_tile_ni_3_12_to_router_3_12_req; - - assign router_3_12_to_router_3_13_rsp = router_3_12_rsp_out[0]; - assign router_3_12_to_router_4_12_rsp = router_3_12_rsp_out[1]; - assign router_3_12_to_router_3_11_rsp = router_3_12_rsp_out[2]; - assign router_3_12_to_router_2_12_rsp = router_3_12_rsp_out[3]; - assign router_3_12_to_magia_tile_ni_3_12_rsp = router_3_12_rsp_out[4]; - - assign router_3_12_to_router_3_13_req = router_3_12_req_out[0]; - assign router_3_12_to_router_4_12_req = router_3_12_req_out[1]; - assign router_3_12_to_router_3_11_req = router_3_12_req_out[2]; - assign router_3_12_to_router_2_12_req = router_3_12_req_out[3]; - assign router_3_12_to_magia_tile_ni_3_12_req = router_3_12_req_out[4]; - - assign router_3_12_rsp_in[0] = router_3_13_to_router_3_12_rsp; - assign router_3_12_rsp_in[1] = router_4_12_to_router_3_12_rsp; - assign router_3_12_rsp_in[2] = router_3_11_to_router_3_12_rsp; - assign router_3_12_rsp_in[3] = router_2_12_to_router_3_12_rsp; - assign router_3_12_rsp_in[4] = magia_tile_ni_3_12_to_router_3_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_12_req_in), - .floo_rsp_o (router_3_12_rsp_out), - .floo_req_o (router_3_12_req_out), - .floo_rsp_i (router_3_12_rsp_in) -); - - -floo_req_t [4:0] router_3_13_req_in; -floo_rsp_t [4:0] router_3_13_rsp_out; -floo_req_t [4:0] router_3_13_req_out; -floo_rsp_t [4:0] router_3_13_rsp_in; - - assign router_3_13_req_in[0] = router_3_14_to_router_3_13_req; - assign router_3_13_req_in[1] = router_4_13_to_router_3_13_req; - assign router_3_13_req_in[2] = router_3_12_to_router_3_13_req; - assign router_3_13_req_in[3] = router_2_13_to_router_3_13_req; - assign router_3_13_req_in[4] = magia_tile_ni_3_13_to_router_3_13_req; - - assign router_3_13_to_router_3_14_rsp = router_3_13_rsp_out[0]; - assign router_3_13_to_router_4_13_rsp = router_3_13_rsp_out[1]; - assign router_3_13_to_router_3_12_rsp = router_3_13_rsp_out[2]; - assign router_3_13_to_router_2_13_rsp = router_3_13_rsp_out[3]; - assign router_3_13_to_magia_tile_ni_3_13_rsp = router_3_13_rsp_out[4]; - - assign router_3_13_to_router_3_14_req = router_3_13_req_out[0]; - assign router_3_13_to_router_4_13_req = router_3_13_req_out[1]; - assign router_3_13_to_router_3_12_req = router_3_13_req_out[2]; - assign router_3_13_to_router_2_13_req = router_3_13_req_out[3]; - assign router_3_13_to_magia_tile_ni_3_13_req = router_3_13_req_out[4]; - - assign router_3_13_rsp_in[0] = router_3_14_to_router_3_13_rsp; - assign router_3_13_rsp_in[1] = router_4_13_to_router_3_13_rsp; - assign router_3_13_rsp_in[2] = router_3_12_to_router_3_13_rsp; - assign router_3_13_rsp_in[3] = router_2_13_to_router_3_13_rsp; - assign router_3_13_rsp_in[4] = magia_tile_ni_3_13_to_router_3_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_13_req_in), - .floo_rsp_o (router_3_13_rsp_out), - .floo_req_o (router_3_13_req_out), - .floo_rsp_i (router_3_13_rsp_in) -); - - -floo_req_t [4:0] router_3_14_req_in; -floo_rsp_t [4:0] router_3_14_rsp_out; -floo_req_t [4:0] router_3_14_req_out; -floo_rsp_t [4:0] router_3_14_rsp_in; - - assign router_3_14_req_in[0] = router_3_15_to_router_3_14_req; - assign router_3_14_req_in[1] = router_4_14_to_router_3_14_req; - assign router_3_14_req_in[2] = router_3_13_to_router_3_14_req; - assign router_3_14_req_in[3] = router_2_14_to_router_3_14_req; - assign router_3_14_req_in[4] = magia_tile_ni_3_14_to_router_3_14_req; - - assign router_3_14_to_router_3_15_rsp = router_3_14_rsp_out[0]; - assign router_3_14_to_router_4_14_rsp = router_3_14_rsp_out[1]; - assign router_3_14_to_router_3_13_rsp = router_3_14_rsp_out[2]; - assign router_3_14_to_router_2_14_rsp = router_3_14_rsp_out[3]; - assign router_3_14_to_magia_tile_ni_3_14_rsp = router_3_14_rsp_out[4]; - - assign router_3_14_to_router_3_15_req = router_3_14_req_out[0]; - assign router_3_14_to_router_4_14_req = router_3_14_req_out[1]; - assign router_3_14_to_router_3_13_req = router_3_14_req_out[2]; - assign router_3_14_to_router_2_14_req = router_3_14_req_out[3]; - assign router_3_14_to_magia_tile_ni_3_14_req = router_3_14_req_out[4]; - - assign router_3_14_rsp_in[0] = router_3_15_to_router_3_14_rsp; - assign router_3_14_rsp_in[1] = router_4_14_to_router_3_14_rsp; - assign router_3_14_rsp_in[2] = router_3_13_to_router_3_14_rsp; - assign router_3_14_rsp_in[3] = router_2_14_to_router_3_14_rsp; - assign router_3_14_rsp_in[4] = magia_tile_ni_3_14_to_router_3_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_14_req_in), - .floo_rsp_o (router_3_14_rsp_out), - .floo_req_o (router_3_14_req_out), - .floo_rsp_i (router_3_14_rsp_in) -); - - -floo_req_t [4:0] router_3_15_req_in; -floo_rsp_t [4:0] router_3_15_rsp_out; -floo_req_t [4:0] router_3_15_req_out; -floo_rsp_t [4:0] router_3_15_rsp_in; - - assign router_3_15_req_in[0] = router_3_16_to_router_3_15_req; - assign router_3_15_req_in[1] = router_4_15_to_router_3_15_req; - assign router_3_15_req_in[2] = router_3_14_to_router_3_15_req; - assign router_3_15_req_in[3] = router_2_15_to_router_3_15_req; - assign router_3_15_req_in[4] = magia_tile_ni_3_15_to_router_3_15_req; - - assign router_3_15_to_router_3_16_rsp = router_3_15_rsp_out[0]; - assign router_3_15_to_router_4_15_rsp = router_3_15_rsp_out[1]; - assign router_3_15_to_router_3_14_rsp = router_3_15_rsp_out[2]; - assign router_3_15_to_router_2_15_rsp = router_3_15_rsp_out[3]; - assign router_3_15_to_magia_tile_ni_3_15_rsp = router_3_15_rsp_out[4]; - - assign router_3_15_to_router_3_16_req = router_3_15_req_out[0]; - assign router_3_15_to_router_4_15_req = router_3_15_req_out[1]; - assign router_3_15_to_router_3_14_req = router_3_15_req_out[2]; - assign router_3_15_to_router_2_15_req = router_3_15_req_out[3]; - assign router_3_15_to_magia_tile_ni_3_15_req = router_3_15_req_out[4]; - - assign router_3_15_rsp_in[0] = router_3_16_to_router_3_15_rsp; - assign router_3_15_rsp_in[1] = router_4_15_to_router_3_15_rsp; - assign router_3_15_rsp_in[2] = router_3_14_to_router_3_15_rsp; - assign router_3_15_rsp_in[3] = router_2_15_to_router_3_15_rsp; - assign router_3_15_rsp_in[4] = magia_tile_ni_3_15_to_router_3_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_15_req_in), - .floo_rsp_o (router_3_15_rsp_out), - .floo_req_o (router_3_15_req_out), - .floo_rsp_i (router_3_15_rsp_in) -); - - -floo_req_t [4:0] router_3_16_req_in; -floo_rsp_t [4:0] router_3_16_rsp_out; -floo_req_t [4:0] router_3_16_req_out; -floo_rsp_t [4:0] router_3_16_rsp_in; - - assign router_3_16_req_in[0] = router_3_17_to_router_3_16_req; - assign router_3_16_req_in[1] = router_4_16_to_router_3_16_req; - assign router_3_16_req_in[2] = router_3_15_to_router_3_16_req; - assign router_3_16_req_in[3] = router_2_16_to_router_3_16_req; - assign router_3_16_req_in[4] = magia_tile_ni_3_16_to_router_3_16_req; - - assign router_3_16_to_router_3_17_rsp = router_3_16_rsp_out[0]; - assign router_3_16_to_router_4_16_rsp = router_3_16_rsp_out[1]; - assign router_3_16_to_router_3_15_rsp = router_3_16_rsp_out[2]; - assign router_3_16_to_router_2_16_rsp = router_3_16_rsp_out[3]; - assign router_3_16_to_magia_tile_ni_3_16_rsp = router_3_16_rsp_out[4]; - - assign router_3_16_to_router_3_17_req = router_3_16_req_out[0]; - assign router_3_16_to_router_4_16_req = router_3_16_req_out[1]; - assign router_3_16_to_router_3_15_req = router_3_16_req_out[2]; - assign router_3_16_to_router_2_16_req = router_3_16_req_out[3]; - assign router_3_16_to_magia_tile_ni_3_16_req = router_3_16_req_out[4]; - - assign router_3_16_rsp_in[0] = router_3_17_to_router_3_16_rsp; - assign router_3_16_rsp_in[1] = router_4_16_to_router_3_16_rsp; - assign router_3_16_rsp_in[2] = router_3_15_to_router_3_16_rsp; - assign router_3_16_rsp_in[3] = router_2_16_to_router_3_16_rsp; - assign router_3_16_rsp_in[4] = magia_tile_ni_3_16_to_router_3_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_16_req_in), - .floo_rsp_o (router_3_16_rsp_out), - .floo_req_o (router_3_16_req_out), - .floo_rsp_i (router_3_16_rsp_in) -); - - -floo_req_t [4:0] router_3_17_req_in; -floo_rsp_t [4:0] router_3_17_rsp_out; -floo_req_t [4:0] router_3_17_req_out; -floo_rsp_t [4:0] router_3_17_rsp_in; - - assign router_3_17_req_in[0] = router_3_18_to_router_3_17_req; - assign router_3_17_req_in[1] = router_4_17_to_router_3_17_req; - assign router_3_17_req_in[2] = router_3_16_to_router_3_17_req; - assign router_3_17_req_in[3] = router_2_17_to_router_3_17_req; - assign router_3_17_req_in[4] = magia_tile_ni_3_17_to_router_3_17_req; - - assign router_3_17_to_router_3_18_rsp = router_3_17_rsp_out[0]; - assign router_3_17_to_router_4_17_rsp = router_3_17_rsp_out[1]; - assign router_3_17_to_router_3_16_rsp = router_3_17_rsp_out[2]; - assign router_3_17_to_router_2_17_rsp = router_3_17_rsp_out[3]; - assign router_3_17_to_magia_tile_ni_3_17_rsp = router_3_17_rsp_out[4]; - - assign router_3_17_to_router_3_18_req = router_3_17_req_out[0]; - assign router_3_17_to_router_4_17_req = router_3_17_req_out[1]; - assign router_3_17_to_router_3_16_req = router_3_17_req_out[2]; - assign router_3_17_to_router_2_17_req = router_3_17_req_out[3]; - assign router_3_17_to_magia_tile_ni_3_17_req = router_3_17_req_out[4]; - - assign router_3_17_rsp_in[0] = router_3_18_to_router_3_17_rsp; - assign router_3_17_rsp_in[1] = router_4_17_to_router_3_17_rsp; - assign router_3_17_rsp_in[2] = router_3_16_to_router_3_17_rsp; - assign router_3_17_rsp_in[3] = router_2_17_to_router_3_17_rsp; - assign router_3_17_rsp_in[4] = magia_tile_ni_3_17_to_router_3_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_17_req_in), - .floo_rsp_o (router_3_17_rsp_out), - .floo_req_o (router_3_17_req_out), - .floo_rsp_i (router_3_17_rsp_in) -); - - -floo_req_t [4:0] router_3_18_req_in; -floo_rsp_t [4:0] router_3_18_rsp_out; -floo_req_t [4:0] router_3_18_req_out; -floo_rsp_t [4:0] router_3_18_rsp_in; - - assign router_3_18_req_in[0] = router_3_19_to_router_3_18_req; - assign router_3_18_req_in[1] = router_4_18_to_router_3_18_req; - assign router_3_18_req_in[2] = router_3_17_to_router_3_18_req; - assign router_3_18_req_in[3] = router_2_18_to_router_3_18_req; - assign router_3_18_req_in[4] = magia_tile_ni_3_18_to_router_3_18_req; - - assign router_3_18_to_router_3_19_rsp = router_3_18_rsp_out[0]; - assign router_3_18_to_router_4_18_rsp = router_3_18_rsp_out[1]; - assign router_3_18_to_router_3_17_rsp = router_3_18_rsp_out[2]; - assign router_3_18_to_router_2_18_rsp = router_3_18_rsp_out[3]; - assign router_3_18_to_magia_tile_ni_3_18_rsp = router_3_18_rsp_out[4]; - - assign router_3_18_to_router_3_19_req = router_3_18_req_out[0]; - assign router_3_18_to_router_4_18_req = router_3_18_req_out[1]; - assign router_3_18_to_router_3_17_req = router_3_18_req_out[2]; - assign router_3_18_to_router_2_18_req = router_3_18_req_out[3]; - assign router_3_18_to_magia_tile_ni_3_18_req = router_3_18_req_out[4]; - - assign router_3_18_rsp_in[0] = router_3_19_to_router_3_18_rsp; - assign router_3_18_rsp_in[1] = router_4_18_to_router_3_18_rsp; - assign router_3_18_rsp_in[2] = router_3_17_to_router_3_18_rsp; - assign router_3_18_rsp_in[3] = router_2_18_to_router_3_18_rsp; - assign router_3_18_rsp_in[4] = magia_tile_ni_3_18_to_router_3_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_18_req_in), - .floo_rsp_o (router_3_18_rsp_out), - .floo_req_o (router_3_18_req_out), - .floo_rsp_i (router_3_18_rsp_in) -); - - -floo_req_t [4:0] router_3_19_req_in; -floo_rsp_t [4:0] router_3_19_rsp_out; -floo_req_t [4:0] router_3_19_req_out; -floo_rsp_t [4:0] router_3_19_rsp_in; - - assign router_3_19_req_in[0] = router_3_20_to_router_3_19_req; - assign router_3_19_req_in[1] = router_4_19_to_router_3_19_req; - assign router_3_19_req_in[2] = router_3_18_to_router_3_19_req; - assign router_3_19_req_in[3] = router_2_19_to_router_3_19_req; - assign router_3_19_req_in[4] = magia_tile_ni_3_19_to_router_3_19_req; - - assign router_3_19_to_router_3_20_rsp = router_3_19_rsp_out[0]; - assign router_3_19_to_router_4_19_rsp = router_3_19_rsp_out[1]; - assign router_3_19_to_router_3_18_rsp = router_3_19_rsp_out[2]; - assign router_3_19_to_router_2_19_rsp = router_3_19_rsp_out[3]; - assign router_3_19_to_magia_tile_ni_3_19_rsp = router_3_19_rsp_out[4]; - - assign router_3_19_to_router_3_20_req = router_3_19_req_out[0]; - assign router_3_19_to_router_4_19_req = router_3_19_req_out[1]; - assign router_3_19_to_router_3_18_req = router_3_19_req_out[2]; - assign router_3_19_to_router_2_19_req = router_3_19_req_out[3]; - assign router_3_19_to_magia_tile_ni_3_19_req = router_3_19_req_out[4]; - - assign router_3_19_rsp_in[0] = router_3_20_to_router_3_19_rsp; - assign router_3_19_rsp_in[1] = router_4_19_to_router_3_19_rsp; - assign router_3_19_rsp_in[2] = router_3_18_to_router_3_19_rsp; - assign router_3_19_rsp_in[3] = router_2_19_to_router_3_19_rsp; - assign router_3_19_rsp_in[4] = magia_tile_ni_3_19_to_router_3_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_19_req_in), - .floo_rsp_o (router_3_19_rsp_out), - .floo_req_o (router_3_19_req_out), - .floo_rsp_i (router_3_19_rsp_in) -); - - -floo_req_t [4:0] router_3_20_req_in; -floo_rsp_t [4:0] router_3_20_rsp_out; -floo_req_t [4:0] router_3_20_req_out; -floo_rsp_t [4:0] router_3_20_rsp_in; - - assign router_3_20_req_in[0] = router_3_21_to_router_3_20_req; - assign router_3_20_req_in[1] = router_4_20_to_router_3_20_req; - assign router_3_20_req_in[2] = router_3_19_to_router_3_20_req; - assign router_3_20_req_in[3] = router_2_20_to_router_3_20_req; - assign router_3_20_req_in[4] = magia_tile_ni_3_20_to_router_3_20_req; - - assign router_3_20_to_router_3_21_rsp = router_3_20_rsp_out[0]; - assign router_3_20_to_router_4_20_rsp = router_3_20_rsp_out[1]; - assign router_3_20_to_router_3_19_rsp = router_3_20_rsp_out[2]; - assign router_3_20_to_router_2_20_rsp = router_3_20_rsp_out[3]; - assign router_3_20_to_magia_tile_ni_3_20_rsp = router_3_20_rsp_out[4]; - - assign router_3_20_to_router_3_21_req = router_3_20_req_out[0]; - assign router_3_20_to_router_4_20_req = router_3_20_req_out[1]; - assign router_3_20_to_router_3_19_req = router_3_20_req_out[2]; - assign router_3_20_to_router_2_20_req = router_3_20_req_out[3]; - assign router_3_20_to_magia_tile_ni_3_20_req = router_3_20_req_out[4]; - - assign router_3_20_rsp_in[0] = router_3_21_to_router_3_20_rsp; - assign router_3_20_rsp_in[1] = router_4_20_to_router_3_20_rsp; - assign router_3_20_rsp_in[2] = router_3_19_to_router_3_20_rsp; - assign router_3_20_rsp_in[3] = router_2_20_to_router_3_20_rsp; - assign router_3_20_rsp_in[4] = magia_tile_ni_3_20_to_router_3_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_20_req_in), - .floo_rsp_o (router_3_20_rsp_out), - .floo_req_o (router_3_20_req_out), - .floo_rsp_i (router_3_20_rsp_in) -); - - -floo_req_t [4:0] router_3_21_req_in; -floo_rsp_t [4:0] router_3_21_rsp_out; -floo_req_t [4:0] router_3_21_req_out; -floo_rsp_t [4:0] router_3_21_rsp_in; - - assign router_3_21_req_in[0] = router_3_22_to_router_3_21_req; - assign router_3_21_req_in[1] = router_4_21_to_router_3_21_req; - assign router_3_21_req_in[2] = router_3_20_to_router_3_21_req; - assign router_3_21_req_in[3] = router_2_21_to_router_3_21_req; - assign router_3_21_req_in[4] = magia_tile_ni_3_21_to_router_3_21_req; - - assign router_3_21_to_router_3_22_rsp = router_3_21_rsp_out[0]; - assign router_3_21_to_router_4_21_rsp = router_3_21_rsp_out[1]; - assign router_3_21_to_router_3_20_rsp = router_3_21_rsp_out[2]; - assign router_3_21_to_router_2_21_rsp = router_3_21_rsp_out[3]; - assign router_3_21_to_magia_tile_ni_3_21_rsp = router_3_21_rsp_out[4]; - - assign router_3_21_to_router_3_22_req = router_3_21_req_out[0]; - assign router_3_21_to_router_4_21_req = router_3_21_req_out[1]; - assign router_3_21_to_router_3_20_req = router_3_21_req_out[2]; - assign router_3_21_to_router_2_21_req = router_3_21_req_out[3]; - assign router_3_21_to_magia_tile_ni_3_21_req = router_3_21_req_out[4]; - - assign router_3_21_rsp_in[0] = router_3_22_to_router_3_21_rsp; - assign router_3_21_rsp_in[1] = router_4_21_to_router_3_21_rsp; - assign router_3_21_rsp_in[2] = router_3_20_to_router_3_21_rsp; - assign router_3_21_rsp_in[3] = router_2_21_to_router_3_21_rsp; - assign router_3_21_rsp_in[4] = magia_tile_ni_3_21_to_router_3_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_21_req_in), - .floo_rsp_o (router_3_21_rsp_out), - .floo_req_o (router_3_21_req_out), - .floo_rsp_i (router_3_21_rsp_in) -); - - -floo_req_t [4:0] router_3_22_req_in; -floo_rsp_t [4:0] router_3_22_rsp_out; -floo_req_t [4:0] router_3_22_req_out; -floo_rsp_t [4:0] router_3_22_rsp_in; - - assign router_3_22_req_in[0] = router_3_23_to_router_3_22_req; - assign router_3_22_req_in[1] = router_4_22_to_router_3_22_req; - assign router_3_22_req_in[2] = router_3_21_to_router_3_22_req; - assign router_3_22_req_in[3] = router_2_22_to_router_3_22_req; - assign router_3_22_req_in[4] = magia_tile_ni_3_22_to_router_3_22_req; - - assign router_3_22_to_router_3_23_rsp = router_3_22_rsp_out[0]; - assign router_3_22_to_router_4_22_rsp = router_3_22_rsp_out[1]; - assign router_3_22_to_router_3_21_rsp = router_3_22_rsp_out[2]; - assign router_3_22_to_router_2_22_rsp = router_3_22_rsp_out[3]; - assign router_3_22_to_magia_tile_ni_3_22_rsp = router_3_22_rsp_out[4]; - - assign router_3_22_to_router_3_23_req = router_3_22_req_out[0]; - assign router_3_22_to_router_4_22_req = router_3_22_req_out[1]; - assign router_3_22_to_router_3_21_req = router_3_22_req_out[2]; - assign router_3_22_to_router_2_22_req = router_3_22_req_out[3]; - assign router_3_22_to_magia_tile_ni_3_22_req = router_3_22_req_out[4]; - - assign router_3_22_rsp_in[0] = router_3_23_to_router_3_22_rsp; - assign router_3_22_rsp_in[1] = router_4_22_to_router_3_22_rsp; - assign router_3_22_rsp_in[2] = router_3_21_to_router_3_22_rsp; - assign router_3_22_rsp_in[3] = router_2_22_to_router_3_22_rsp; - assign router_3_22_rsp_in[4] = magia_tile_ni_3_22_to_router_3_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_22_req_in), - .floo_rsp_o (router_3_22_rsp_out), - .floo_req_o (router_3_22_req_out), - .floo_rsp_i (router_3_22_rsp_in) -); - - -floo_req_t [4:0] router_3_23_req_in; -floo_rsp_t [4:0] router_3_23_rsp_out; -floo_req_t [4:0] router_3_23_req_out; -floo_rsp_t [4:0] router_3_23_rsp_in; - - assign router_3_23_req_in[0] = router_3_24_to_router_3_23_req; - assign router_3_23_req_in[1] = router_4_23_to_router_3_23_req; - assign router_3_23_req_in[2] = router_3_22_to_router_3_23_req; - assign router_3_23_req_in[3] = router_2_23_to_router_3_23_req; - assign router_3_23_req_in[4] = magia_tile_ni_3_23_to_router_3_23_req; - - assign router_3_23_to_router_3_24_rsp = router_3_23_rsp_out[0]; - assign router_3_23_to_router_4_23_rsp = router_3_23_rsp_out[1]; - assign router_3_23_to_router_3_22_rsp = router_3_23_rsp_out[2]; - assign router_3_23_to_router_2_23_rsp = router_3_23_rsp_out[3]; - assign router_3_23_to_magia_tile_ni_3_23_rsp = router_3_23_rsp_out[4]; - - assign router_3_23_to_router_3_24_req = router_3_23_req_out[0]; - assign router_3_23_to_router_4_23_req = router_3_23_req_out[1]; - assign router_3_23_to_router_3_22_req = router_3_23_req_out[2]; - assign router_3_23_to_router_2_23_req = router_3_23_req_out[3]; - assign router_3_23_to_magia_tile_ni_3_23_req = router_3_23_req_out[4]; - - assign router_3_23_rsp_in[0] = router_3_24_to_router_3_23_rsp; - assign router_3_23_rsp_in[1] = router_4_23_to_router_3_23_rsp; - assign router_3_23_rsp_in[2] = router_3_22_to_router_3_23_rsp; - assign router_3_23_rsp_in[3] = router_2_23_to_router_3_23_rsp; - assign router_3_23_rsp_in[4] = magia_tile_ni_3_23_to_router_3_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_23_req_in), - .floo_rsp_o (router_3_23_rsp_out), - .floo_req_o (router_3_23_req_out), - .floo_rsp_i (router_3_23_rsp_in) -); - - -floo_req_t [4:0] router_3_24_req_in; -floo_rsp_t [4:0] router_3_24_rsp_out; -floo_req_t [4:0] router_3_24_req_out; -floo_rsp_t [4:0] router_3_24_rsp_in; - - assign router_3_24_req_in[0] = router_3_25_to_router_3_24_req; - assign router_3_24_req_in[1] = router_4_24_to_router_3_24_req; - assign router_3_24_req_in[2] = router_3_23_to_router_3_24_req; - assign router_3_24_req_in[3] = router_2_24_to_router_3_24_req; - assign router_3_24_req_in[4] = magia_tile_ni_3_24_to_router_3_24_req; - - assign router_3_24_to_router_3_25_rsp = router_3_24_rsp_out[0]; - assign router_3_24_to_router_4_24_rsp = router_3_24_rsp_out[1]; - assign router_3_24_to_router_3_23_rsp = router_3_24_rsp_out[2]; - assign router_3_24_to_router_2_24_rsp = router_3_24_rsp_out[3]; - assign router_3_24_to_magia_tile_ni_3_24_rsp = router_3_24_rsp_out[4]; - - assign router_3_24_to_router_3_25_req = router_3_24_req_out[0]; - assign router_3_24_to_router_4_24_req = router_3_24_req_out[1]; - assign router_3_24_to_router_3_23_req = router_3_24_req_out[2]; - assign router_3_24_to_router_2_24_req = router_3_24_req_out[3]; - assign router_3_24_to_magia_tile_ni_3_24_req = router_3_24_req_out[4]; - - assign router_3_24_rsp_in[0] = router_3_25_to_router_3_24_rsp; - assign router_3_24_rsp_in[1] = router_4_24_to_router_3_24_rsp; - assign router_3_24_rsp_in[2] = router_3_23_to_router_3_24_rsp; - assign router_3_24_rsp_in[3] = router_2_24_to_router_3_24_rsp; - assign router_3_24_rsp_in[4] = magia_tile_ni_3_24_to_router_3_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_24_req_in), - .floo_rsp_o (router_3_24_rsp_out), - .floo_req_o (router_3_24_req_out), - .floo_rsp_i (router_3_24_rsp_in) -); - - -floo_req_t [4:0] router_3_25_req_in; -floo_rsp_t [4:0] router_3_25_rsp_out; -floo_req_t [4:0] router_3_25_req_out; -floo_rsp_t [4:0] router_3_25_rsp_in; - - assign router_3_25_req_in[0] = router_3_26_to_router_3_25_req; - assign router_3_25_req_in[1] = router_4_25_to_router_3_25_req; - assign router_3_25_req_in[2] = router_3_24_to_router_3_25_req; - assign router_3_25_req_in[3] = router_2_25_to_router_3_25_req; - assign router_3_25_req_in[4] = magia_tile_ni_3_25_to_router_3_25_req; - - assign router_3_25_to_router_3_26_rsp = router_3_25_rsp_out[0]; - assign router_3_25_to_router_4_25_rsp = router_3_25_rsp_out[1]; - assign router_3_25_to_router_3_24_rsp = router_3_25_rsp_out[2]; - assign router_3_25_to_router_2_25_rsp = router_3_25_rsp_out[3]; - assign router_3_25_to_magia_tile_ni_3_25_rsp = router_3_25_rsp_out[4]; - - assign router_3_25_to_router_3_26_req = router_3_25_req_out[0]; - assign router_3_25_to_router_4_25_req = router_3_25_req_out[1]; - assign router_3_25_to_router_3_24_req = router_3_25_req_out[2]; - assign router_3_25_to_router_2_25_req = router_3_25_req_out[3]; - assign router_3_25_to_magia_tile_ni_3_25_req = router_3_25_req_out[4]; - - assign router_3_25_rsp_in[0] = router_3_26_to_router_3_25_rsp; - assign router_3_25_rsp_in[1] = router_4_25_to_router_3_25_rsp; - assign router_3_25_rsp_in[2] = router_3_24_to_router_3_25_rsp; - assign router_3_25_rsp_in[3] = router_2_25_to_router_3_25_rsp; - assign router_3_25_rsp_in[4] = magia_tile_ni_3_25_to_router_3_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_25_req_in), - .floo_rsp_o (router_3_25_rsp_out), - .floo_req_o (router_3_25_req_out), - .floo_rsp_i (router_3_25_rsp_in) -); - - -floo_req_t [4:0] router_3_26_req_in; -floo_rsp_t [4:0] router_3_26_rsp_out; -floo_req_t [4:0] router_3_26_req_out; -floo_rsp_t [4:0] router_3_26_rsp_in; - - assign router_3_26_req_in[0] = router_3_27_to_router_3_26_req; - assign router_3_26_req_in[1] = router_4_26_to_router_3_26_req; - assign router_3_26_req_in[2] = router_3_25_to_router_3_26_req; - assign router_3_26_req_in[3] = router_2_26_to_router_3_26_req; - assign router_3_26_req_in[4] = magia_tile_ni_3_26_to_router_3_26_req; - - assign router_3_26_to_router_3_27_rsp = router_3_26_rsp_out[0]; - assign router_3_26_to_router_4_26_rsp = router_3_26_rsp_out[1]; - assign router_3_26_to_router_3_25_rsp = router_3_26_rsp_out[2]; - assign router_3_26_to_router_2_26_rsp = router_3_26_rsp_out[3]; - assign router_3_26_to_magia_tile_ni_3_26_rsp = router_3_26_rsp_out[4]; - - assign router_3_26_to_router_3_27_req = router_3_26_req_out[0]; - assign router_3_26_to_router_4_26_req = router_3_26_req_out[1]; - assign router_3_26_to_router_3_25_req = router_3_26_req_out[2]; - assign router_3_26_to_router_2_26_req = router_3_26_req_out[3]; - assign router_3_26_to_magia_tile_ni_3_26_req = router_3_26_req_out[4]; - - assign router_3_26_rsp_in[0] = router_3_27_to_router_3_26_rsp; - assign router_3_26_rsp_in[1] = router_4_26_to_router_3_26_rsp; - assign router_3_26_rsp_in[2] = router_3_25_to_router_3_26_rsp; - assign router_3_26_rsp_in[3] = router_2_26_to_router_3_26_rsp; - assign router_3_26_rsp_in[4] = magia_tile_ni_3_26_to_router_3_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_26_req_in), - .floo_rsp_o (router_3_26_rsp_out), - .floo_req_o (router_3_26_req_out), - .floo_rsp_i (router_3_26_rsp_in) -); - - -floo_req_t [4:0] router_3_27_req_in; -floo_rsp_t [4:0] router_3_27_rsp_out; -floo_req_t [4:0] router_3_27_req_out; -floo_rsp_t [4:0] router_3_27_rsp_in; - - assign router_3_27_req_in[0] = router_3_28_to_router_3_27_req; - assign router_3_27_req_in[1] = router_4_27_to_router_3_27_req; - assign router_3_27_req_in[2] = router_3_26_to_router_3_27_req; - assign router_3_27_req_in[3] = router_2_27_to_router_3_27_req; - assign router_3_27_req_in[4] = magia_tile_ni_3_27_to_router_3_27_req; - - assign router_3_27_to_router_3_28_rsp = router_3_27_rsp_out[0]; - assign router_3_27_to_router_4_27_rsp = router_3_27_rsp_out[1]; - assign router_3_27_to_router_3_26_rsp = router_3_27_rsp_out[2]; - assign router_3_27_to_router_2_27_rsp = router_3_27_rsp_out[3]; - assign router_3_27_to_magia_tile_ni_3_27_rsp = router_3_27_rsp_out[4]; - - assign router_3_27_to_router_3_28_req = router_3_27_req_out[0]; - assign router_3_27_to_router_4_27_req = router_3_27_req_out[1]; - assign router_3_27_to_router_3_26_req = router_3_27_req_out[2]; - assign router_3_27_to_router_2_27_req = router_3_27_req_out[3]; - assign router_3_27_to_magia_tile_ni_3_27_req = router_3_27_req_out[4]; - - assign router_3_27_rsp_in[0] = router_3_28_to_router_3_27_rsp; - assign router_3_27_rsp_in[1] = router_4_27_to_router_3_27_rsp; - assign router_3_27_rsp_in[2] = router_3_26_to_router_3_27_rsp; - assign router_3_27_rsp_in[3] = router_2_27_to_router_3_27_rsp; - assign router_3_27_rsp_in[4] = magia_tile_ni_3_27_to_router_3_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_27_req_in), - .floo_rsp_o (router_3_27_rsp_out), - .floo_req_o (router_3_27_req_out), - .floo_rsp_i (router_3_27_rsp_in) -); - - -floo_req_t [4:0] router_3_28_req_in; -floo_rsp_t [4:0] router_3_28_rsp_out; -floo_req_t [4:0] router_3_28_req_out; -floo_rsp_t [4:0] router_3_28_rsp_in; - - assign router_3_28_req_in[0] = router_3_29_to_router_3_28_req; - assign router_3_28_req_in[1] = router_4_28_to_router_3_28_req; - assign router_3_28_req_in[2] = router_3_27_to_router_3_28_req; - assign router_3_28_req_in[3] = router_2_28_to_router_3_28_req; - assign router_3_28_req_in[4] = magia_tile_ni_3_28_to_router_3_28_req; - - assign router_3_28_to_router_3_29_rsp = router_3_28_rsp_out[0]; - assign router_3_28_to_router_4_28_rsp = router_3_28_rsp_out[1]; - assign router_3_28_to_router_3_27_rsp = router_3_28_rsp_out[2]; - assign router_3_28_to_router_2_28_rsp = router_3_28_rsp_out[3]; - assign router_3_28_to_magia_tile_ni_3_28_rsp = router_3_28_rsp_out[4]; - - assign router_3_28_to_router_3_29_req = router_3_28_req_out[0]; - assign router_3_28_to_router_4_28_req = router_3_28_req_out[1]; - assign router_3_28_to_router_3_27_req = router_3_28_req_out[2]; - assign router_3_28_to_router_2_28_req = router_3_28_req_out[3]; - assign router_3_28_to_magia_tile_ni_3_28_req = router_3_28_req_out[4]; - - assign router_3_28_rsp_in[0] = router_3_29_to_router_3_28_rsp; - assign router_3_28_rsp_in[1] = router_4_28_to_router_3_28_rsp; - assign router_3_28_rsp_in[2] = router_3_27_to_router_3_28_rsp; - assign router_3_28_rsp_in[3] = router_2_28_to_router_3_28_rsp; - assign router_3_28_rsp_in[4] = magia_tile_ni_3_28_to_router_3_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_28_req_in), - .floo_rsp_o (router_3_28_rsp_out), - .floo_req_o (router_3_28_req_out), - .floo_rsp_i (router_3_28_rsp_in) -); - - -floo_req_t [4:0] router_3_29_req_in; -floo_rsp_t [4:0] router_3_29_rsp_out; -floo_req_t [4:0] router_3_29_req_out; -floo_rsp_t [4:0] router_3_29_rsp_in; - - assign router_3_29_req_in[0] = router_3_30_to_router_3_29_req; - assign router_3_29_req_in[1] = router_4_29_to_router_3_29_req; - assign router_3_29_req_in[2] = router_3_28_to_router_3_29_req; - assign router_3_29_req_in[3] = router_2_29_to_router_3_29_req; - assign router_3_29_req_in[4] = magia_tile_ni_3_29_to_router_3_29_req; - - assign router_3_29_to_router_3_30_rsp = router_3_29_rsp_out[0]; - assign router_3_29_to_router_4_29_rsp = router_3_29_rsp_out[1]; - assign router_3_29_to_router_3_28_rsp = router_3_29_rsp_out[2]; - assign router_3_29_to_router_2_29_rsp = router_3_29_rsp_out[3]; - assign router_3_29_to_magia_tile_ni_3_29_rsp = router_3_29_rsp_out[4]; - - assign router_3_29_to_router_3_30_req = router_3_29_req_out[0]; - assign router_3_29_to_router_4_29_req = router_3_29_req_out[1]; - assign router_3_29_to_router_3_28_req = router_3_29_req_out[2]; - assign router_3_29_to_router_2_29_req = router_3_29_req_out[3]; - assign router_3_29_to_magia_tile_ni_3_29_req = router_3_29_req_out[4]; - - assign router_3_29_rsp_in[0] = router_3_30_to_router_3_29_rsp; - assign router_3_29_rsp_in[1] = router_4_29_to_router_3_29_rsp; - assign router_3_29_rsp_in[2] = router_3_28_to_router_3_29_rsp; - assign router_3_29_rsp_in[3] = router_2_29_to_router_3_29_rsp; - assign router_3_29_rsp_in[4] = magia_tile_ni_3_29_to_router_3_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_29_req_in), - .floo_rsp_o (router_3_29_rsp_out), - .floo_req_o (router_3_29_req_out), - .floo_rsp_i (router_3_29_rsp_in) -); - - -floo_req_t [4:0] router_3_30_req_in; -floo_rsp_t [4:0] router_3_30_rsp_out; -floo_req_t [4:0] router_3_30_req_out; -floo_rsp_t [4:0] router_3_30_rsp_in; - - assign router_3_30_req_in[0] = router_3_31_to_router_3_30_req; - assign router_3_30_req_in[1] = router_4_30_to_router_3_30_req; - assign router_3_30_req_in[2] = router_3_29_to_router_3_30_req; - assign router_3_30_req_in[3] = router_2_30_to_router_3_30_req; - assign router_3_30_req_in[4] = magia_tile_ni_3_30_to_router_3_30_req; - - assign router_3_30_to_router_3_31_rsp = router_3_30_rsp_out[0]; - assign router_3_30_to_router_4_30_rsp = router_3_30_rsp_out[1]; - assign router_3_30_to_router_3_29_rsp = router_3_30_rsp_out[2]; - assign router_3_30_to_router_2_30_rsp = router_3_30_rsp_out[3]; - assign router_3_30_to_magia_tile_ni_3_30_rsp = router_3_30_rsp_out[4]; - - assign router_3_30_to_router_3_31_req = router_3_30_req_out[0]; - assign router_3_30_to_router_4_30_req = router_3_30_req_out[1]; - assign router_3_30_to_router_3_29_req = router_3_30_req_out[2]; - assign router_3_30_to_router_2_30_req = router_3_30_req_out[3]; - assign router_3_30_to_magia_tile_ni_3_30_req = router_3_30_req_out[4]; - - assign router_3_30_rsp_in[0] = router_3_31_to_router_3_30_rsp; - assign router_3_30_rsp_in[1] = router_4_30_to_router_3_30_rsp; - assign router_3_30_rsp_in[2] = router_3_29_to_router_3_30_rsp; - assign router_3_30_rsp_in[3] = router_2_30_to_router_3_30_rsp; - assign router_3_30_rsp_in[4] = magia_tile_ni_3_30_to_router_3_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_30_req_in), - .floo_rsp_o (router_3_30_rsp_out), - .floo_req_o (router_3_30_req_out), - .floo_rsp_i (router_3_30_rsp_in) -); - - -floo_req_t [4:0] router_3_31_req_in; -floo_rsp_t [4:0] router_3_31_rsp_out; -floo_req_t [4:0] router_3_31_req_out; -floo_rsp_t [4:0] router_3_31_rsp_in; - - assign router_3_31_req_in[0] = '0; - assign router_3_31_req_in[1] = router_4_31_to_router_3_31_req; - assign router_3_31_req_in[2] = router_3_30_to_router_3_31_req; - assign router_3_31_req_in[3] = router_2_31_to_router_3_31_req; - assign router_3_31_req_in[4] = magia_tile_ni_3_31_to_router_3_31_req; - - assign router_3_31_to_router_4_31_rsp = router_3_31_rsp_out[1]; - assign router_3_31_to_router_3_30_rsp = router_3_31_rsp_out[2]; - assign router_3_31_to_router_2_31_rsp = router_3_31_rsp_out[3]; - assign router_3_31_to_magia_tile_ni_3_31_rsp = router_3_31_rsp_out[4]; - - assign router_3_31_to_router_4_31_req = router_3_31_req_out[1]; - assign router_3_31_to_router_3_30_req = router_3_31_req_out[2]; - assign router_3_31_to_router_2_31_req = router_3_31_req_out[3]; - assign router_3_31_to_magia_tile_ni_3_31_req = router_3_31_req_out[4]; - - assign router_3_31_rsp_in[0] = '0; - assign router_3_31_rsp_in[1] = router_4_31_to_router_3_31_rsp; - assign router_3_31_rsp_in[2] = router_3_30_to_router_3_31_rsp; - assign router_3_31_rsp_in[3] = router_2_31_to_router_3_31_rsp; - assign router_3_31_rsp_in[4] = magia_tile_ni_3_31_to_router_3_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_31_req_in), - .floo_rsp_o (router_3_31_rsp_out), - .floo_req_o (router_3_31_req_out), - .floo_rsp_i (router_3_31_rsp_in) -); - - -floo_req_t [4:0] router_4_0_req_in; -floo_rsp_t [4:0] router_4_0_rsp_out; -floo_req_t [4:0] router_4_0_req_out; -floo_rsp_t [4:0] router_4_0_rsp_in; - - assign router_4_0_req_in[0] = router_4_1_to_router_4_0_req; - assign router_4_0_req_in[1] = router_5_0_to_router_4_0_req; - assign router_4_0_req_in[2] = '0; - assign router_4_0_req_in[3] = router_3_0_to_router_4_0_req; - assign router_4_0_req_in[4] = magia_tile_ni_4_0_to_router_4_0_req; - - assign router_4_0_to_router_4_1_rsp = router_4_0_rsp_out[0]; - assign router_4_0_to_router_5_0_rsp = router_4_0_rsp_out[1]; - assign router_4_0_to_router_3_0_rsp = router_4_0_rsp_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_rsp = router_4_0_rsp_out[4]; - - assign router_4_0_to_router_4_1_req = router_4_0_req_out[0]; - assign router_4_0_to_router_5_0_req = router_4_0_req_out[1]; - assign router_4_0_to_router_3_0_req = router_4_0_req_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_req = router_4_0_req_out[4]; - - assign router_4_0_rsp_in[0] = router_4_1_to_router_4_0_rsp; - assign router_4_0_rsp_in[1] = router_5_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[2] = '0; - assign router_4_0_rsp_in[3] = router_3_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[4] = magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_0_req_in), - .floo_rsp_o (router_4_0_rsp_out), - .floo_req_o (router_4_0_req_out), - .floo_rsp_i (router_4_0_rsp_in) -); - - -floo_req_t [4:0] router_4_1_req_in; -floo_rsp_t [4:0] router_4_1_rsp_out; -floo_req_t [4:0] router_4_1_req_out; -floo_rsp_t [4:0] router_4_1_rsp_in; - - assign router_4_1_req_in[0] = router_4_2_to_router_4_1_req; - assign router_4_1_req_in[1] = router_5_1_to_router_4_1_req; - assign router_4_1_req_in[2] = router_4_0_to_router_4_1_req; - assign router_4_1_req_in[3] = router_3_1_to_router_4_1_req; - assign router_4_1_req_in[4] = magia_tile_ni_4_1_to_router_4_1_req; - - assign router_4_1_to_router_4_2_rsp = router_4_1_rsp_out[0]; - assign router_4_1_to_router_5_1_rsp = router_4_1_rsp_out[1]; - assign router_4_1_to_router_4_0_rsp = router_4_1_rsp_out[2]; - assign router_4_1_to_router_3_1_rsp = router_4_1_rsp_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_rsp = router_4_1_rsp_out[4]; - - assign router_4_1_to_router_4_2_req = router_4_1_req_out[0]; - assign router_4_1_to_router_5_1_req = router_4_1_req_out[1]; - assign router_4_1_to_router_4_0_req = router_4_1_req_out[2]; - assign router_4_1_to_router_3_1_req = router_4_1_req_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_req = router_4_1_req_out[4]; - - assign router_4_1_rsp_in[0] = router_4_2_to_router_4_1_rsp; - assign router_4_1_rsp_in[1] = router_5_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[2] = router_4_0_to_router_4_1_rsp; - assign router_4_1_rsp_in[3] = router_3_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[4] = magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_1_req_in), - .floo_rsp_o (router_4_1_rsp_out), - .floo_req_o (router_4_1_req_out), - .floo_rsp_i (router_4_1_rsp_in) -); - - -floo_req_t [4:0] router_4_2_req_in; -floo_rsp_t [4:0] router_4_2_rsp_out; -floo_req_t [4:0] router_4_2_req_out; -floo_rsp_t [4:0] router_4_2_rsp_in; - - assign router_4_2_req_in[0] = router_4_3_to_router_4_2_req; - assign router_4_2_req_in[1] = router_5_2_to_router_4_2_req; - assign router_4_2_req_in[2] = router_4_1_to_router_4_2_req; - assign router_4_2_req_in[3] = router_3_2_to_router_4_2_req; - assign router_4_2_req_in[4] = magia_tile_ni_4_2_to_router_4_2_req; - - assign router_4_2_to_router_4_3_rsp = router_4_2_rsp_out[0]; - assign router_4_2_to_router_5_2_rsp = router_4_2_rsp_out[1]; - assign router_4_2_to_router_4_1_rsp = router_4_2_rsp_out[2]; - assign router_4_2_to_router_3_2_rsp = router_4_2_rsp_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_rsp = router_4_2_rsp_out[4]; - - assign router_4_2_to_router_4_3_req = router_4_2_req_out[0]; - assign router_4_2_to_router_5_2_req = router_4_2_req_out[1]; - assign router_4_2_to_router_4_1_req = router_4_2_req_out[2]; - assign router_4_2_to_router_3_2_req = router_4_2_req_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_req = router_4_2_req_out[4]; - - assign router_4_2_rsp_in[0] = router_4_3_to_router_4_2_rsp; - assign router_4_2_rsp_in[1] = router_5_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[2] = router_4_1_to_router_4_2_rsp; - assign router_4_2_rsp_in[3] = router_3_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[4] = magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_2_req_in), - .floo_rsp_o (router_4_2_rsp_out), - .floo_req_o (router_4_2_req_out), - .floo_rsp_i (router_4_2_rsp_in) -); - - -floo_req_t [4:0] router_4_3_req_in; -floo_rsp_t [4:0] router_4_3_rsp_out; -floo_req_t [4:0] router_4_3_req_out; -floo_rsp_t [4:0] router_4_3_rsp_in; - - assign router_4_3_req_in[0] = router_4_4_to_router_4_3_req; - assign router_4_3_req_in[1] = router_5_3_to_router_4_3_req; - assign router_4_3_req_in[2] = router_4_2_to_router_4_3_req; - assign router_4_3_req_in[3] = router_3_3_to_router_4_3_req; - assign router_4_3_req_in[4] = magia_tile_ni_4_3_to_router_4_3_req; - - assign router_4_3_to_router_4_4_rsp = router_4_3_rsp_out[0]; - assign router_4_3_to_router_5_3_rsp = router_4_3_rsp_out[1]; - assign router_4_3_to_router_4_2_rsp = router_4_3_rsp_out[2]; - assign router_4_3_to_router_3_3_rsp = router_4_3_rsp_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_rsp = router_4_3_rsp_out[4]; - - assign router_4_3_to_router_4_4_req = router_4_3_req_out[0]; - assign router_4_3_to_router_5_3_req = router_4_3_req_out[1]; - assign router_4_3_to_router_4_2_req = router_4_3_req_out[2]; - assign router_4_3_to_router_3_3_req = router_4_3_req_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_req = router_4_3_req_out[4]; - - assign router_4_3_rsp_in[0] = router_4_4_to_router_4_3_rsp; - assign router_4_3_rsp_in[1] = router_5_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[2] = router_4_2_to_router_4_3_rsp; - assign router_4_3_rsp_in[3] = router_3_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[4] = magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_3_req_in), - .floo_rsp_o (router_4_3_rsp_out), - .floo_req_o (router_4_3_req_out), - .floo_rsp_i (router_4_3_rsp_in) -); - - -floo_req_t [4:0] router_4_4_req_in; -floo_rsp_t [4:0] router_4_4_rsp_out; -floo_req_t [4:0] router_4_4_req_out; -floo_rsp_t [4:0] router_4_4_rsp_in; - - assign router_4_4_req_in[0] = router_4_5_to_router_4_4_req; - assign router_4_4_req_in[1] = router_5_4_to_router_4_4_req; - assign router_4_4_req_in[2] = router_4_3_to_router_4_4_req; - assign router_4_4_req_in[3] = router_3_4_to_router_4_4_req; - assign router_4_4_req_in[4] = magia_tile_ni_4_4_to_router_4_4_req; - - assign router_4_4_to_router_4_5_rsp = router_4_4_rsp_out[0]; - assign router_4_4_to_router_5_4_rsp = router_4_4_rsp_out[1]; - assign router_4_4_to_router_4_3_rsp = router_4_4_rsp_out[2]; - assign router_4_4_to_router_3_4_rsp = router_4_4_rsp_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_rsp = router_4_4_rsp_out[4]; - - assign router_4_4_to_router_4_5_req = router_4_4_req_out[0]; - assign router_4_4_to_router_5_4_req = router_4_4_req_out[1]; - assign router_4_4_to_router_4_3_req = router_4_4_req_out[2]; - assign router_4_4_to_router_3_4_req = router_4_4_req_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_req = router_4_4_req_out[4]; - - assign router_4_4_rsp_in[0] = router_4_5_to_router_4_4_rsp; - assign router_4_4_rsp_in[1] = router_5_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[2] = router_4_3_to_router_4_4_rsp; - assign router_4_4_rsp_in[3] = router_3_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[4] = magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_4_req_in), - .floo_rsp_o (router_4_4_rsp_out), - .floo_req_o (router_4_4_req_out), - .floo_rsp_i (router_4_4_rsp_in) -); - - -floo_req_t [4:0] router_4_5_req_in; -floo_rsp_t [4:0] router_4_5_rsp_out; -floo_req_t [4:0] router_4_5_req_out; -floo_rsp_t [4:0] router_4_5_rsp_in; - - assign router_4_5_req_in[0] = router_4_6_to_router_4_5_req; - assign router_4_5_req_in[1] = router_5_5_to_router_4_5_req; - assign router_4_5_req_in[2] = router_4_4_to_router_4_5_req; - assign router_4_5_req_in[3] = router_3_5_to_router_4_5_req; - assign router_4_5_req_in[4] = magia_tile_ni_4_5_to_router_4_5_req; - - assign router_4_5_to_router_4_6_rsp = router_4_5_rsp_out[0]; - assign router_4_5_to_router_5_5_rsp = router_4_5_rsp_out[1]; - assign router_4_5_to_router_4_4_rsp = router_4_5_rsp_out[2]; - assign router_4_5_to_router_3_5_rsp = router_4_5_rsp_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_rsp = router_4_5_rsp_out[4]; - - assign router_4_5_to_router_4_6_req = router_4_5_req_out[0]; - assign router_4_5_to_router_5_5_req = router_4_5_req_out[1]; - assign router_4_5_to_router_4_4_req = router_4_5_req_out[2]; - assign router_4_5_to_router_3_5_req = router_4_5_req_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_req = router_4_5_req_out[4]; - - assign router_4_5_rsp_in[0] = router_4_6_to_router_4_5_rsp; - assign router_4_5_rsp_in[1] = router_5_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[2] = router_4_4_to_router_4_5_rsp; - assign router_4_5_rsp_in[3] = router_3_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[4] = magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_5_req_in), - .floo_rsp_o (router_4_5_rsp_out), - .floo_req_o (router_4_5_req_out), - .floo_rsp_i (router_4_5_rsp_in) -); - - -floo_req_t [4:0] router_4_6_req_in; -floo_rsp_t [4:0] router_4_6_rsp_out; -floo_req_t [4:0] router_4_6_req_out; -floo_rsp_t [4:0] router_4_6_rsp_in; - - assign router_4_6_req_in[0] = router_4_7_to_router_4_6_req; - assign router_4_6_req_in[1] = router_5_6_to_router_4_6_req; - assign router_4_6_req_in[2] = router_4_5_to_router_4_6_req; - assign router_4_6_req_in[3] = router_3_6_to_router_4_6_req; - assign router_4_6_req_in[4] = magia_tile_ni_4_6_to_router_4_6_req; - - assign router_4_6_to_router_4_7_rsp = router_4_6_rsp_out[0]; - assign router_4_6_to_router_5_6_rsp = router_4_6_rsp_out[1]; - assign router_4_6_to_router_4_5_rsp = router_4_6_rsp_out[2]; - assign router_4_6_to_router_3_6_rsp = router_4_6_rsp_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_rsp = router_4_6_rsp_out[4]; - - assign router_4_6_to_router_4_7_req = router_4_6_req_out[0]; - assign router_4_6_to_router_5_6_req = router_4_6_req_out[1]; - assign router_4_6_to_router_4_5_req = router_4_6_req_out[2]; - assign router_4_6_to_router_3_6_req = router_4_6_req_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_req = router_4_6_req_out[4]; - - assign router_4_6_rsp_in[0] = router_4_7_to_router_4_6_rsp; - assign router_4_6_rsp_in[1] = router_5_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[2] = router_4_5_to_router_4_6_rsp; - assign router_4_6_rsp_in[3] = router_3_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[4] = magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_6_req_in), - .floo_rsp_o (router_4_6_rsp_out), - .floo_req_o (router_4_6_req_out), - .floo_rsp_i (router_4_6_rsp_in) -); - - -floo_req_t [4:0] router_4_7_req_in; -floo_rsp_t [4:0] router_4_7_rsp_out; -floo_req_t [4:0] router_4_7_req_out; -floo_rsp_t [4:0] router_4_7_rsp_in; - - assign router_4_7_req_in[0] = router_4_8_to_router_4_7_req; - assign router_4_7_req_in[1] = router_5_7_to_router_4_7_req; - assign router_4_7_req_in[2] = router_4_6_to_router_4_7_req; - assign router_4_7_req_in[3] = router_3_7_to_router_4_7_req; - assign router_4_7_req_in[4] = magia_tile_ni_4_7_to_router_4_7_req; - - assign router_4_7_to_router_4_8_rsp = router_4_7_rsp_out[0]; - assign router_4_7_to_router_5_7_rsp = router_4_7_rsp_out[1]; - assign router_4_7_to_router_4_6_rsp = router_4_7_rsp_out[2]; - assign router_4_7_to_router_3_7_rsp = router_4_7_rsp_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_rsp = router_4_7_rsp_out[4]; - - assign router_4_7_to_router_4_8_req = router_4_7_req_out[0]; - assign router_4_7_to_router_5_7_req = router_4_7_req_out[1]; - assign router_4_7_to_router_4_6_req = router_4_7_req_out[2]; - assign router_4_7_to_router_3_7_req = router_4_7_req_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_req = router_4_7_req_out[4]; - - assign router_4_7_rsp_in[0] = router_4_8_to_router_4_7_rsp; - assign router_4_7_rsp_in[1] = router_5_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[2] = router_4_6_to_router_4_7_rsp; - assign router_4_7_rsp_in[3] = router_3_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[4] = magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_7_req_in), - .floo_rsp_o (router_4_7_rsp_out), - .floo_req_o (router_4_7_req_out), - .floo_rsp_i (router_4_7_rsp_in) -); - - -floo_req_t [4:0] router_4_8_req_in; -floo_rsp_t [4:0] router_4_8_rsp_out; -floo_req_t [4:0] router_4_8_req_out; -floo_rsp_t [4:0] router_4_8_rsp_in; - - assign router_4_8_req_in[0] = router_4_9_to_router_4_8_req; - assign router_4_8_req_in[1] = router_5_8_to_router_4_8_req; - assign router_4_8_req_in[2] = router_4_7_to_router_4_8_req; - assign router_4_8_req_in[3] = router_3_8_to_router_4_8_req; - assign router_4_8_req_in[4] = magia_tile_ni_4_8_to_router_4_8_req; - - assign router_4_8_to_router_4_9_rsp = router_4_8_rsp_out[0]; - assign router_4_8_to_router_5_8_rsp = router_4_8_rsp_out[1]; - assign router_4_8_to_router_4_7_rsp = router_4_8_rsp_out[2]; - assign router_4_8_to_router_3_8_rsp = router_4_8_rsp_out[3]; - assign router_4_8_to_magia_tile_ni_4_8_rsp = router_4_8_rsp_out[4]; - - assign router_4_8_to_router_4_9_req = router_4_8_req_out[0]; - assign router_4_8_to_router_5_8_req = router_4_8_req_out[1]; - assign router_4_8_to_router_4_7_req = router_4_8_req_out[2]; - assign router_4_8_to_router_3_8_req = router_4_8_req_out[3]; - assign router_4_8_to_magia_tile_ni_4_8_req = router_4_8_req_out[4]; - - assign router_4_8_rsp_in[0] = router_4_9_to_router_4_8_rsp; - assign router_4_8_rsp_in[1] = router_5_8_to_router_4_8_rsp; - assign router_4_8_rsp_in[2] = router_4_7_to_router_4_8_rsp; - assign router_4_8_rsp_in[3] = router_3_8_to_router_4_8_rsp; - assign router_4_8_rsp_in[4] = magia_tile_ni_4_8_to_router_4_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_8_req_in), - .floo_rsp_o (router_4_8_rsp_out), - .floo_req_o (router_4_8_req_out), - .floo_rsp_i (router_4_8_rsp_in) -); - - -floo_req_t [4:0] router_4_9_req_in; -floo_rsp_t [4:0] router_4_9_rsp_out; -floo_req_t [4:0] router_4_9_req_out; -floo_rsp_t [4:0] router_4_9_rsp_in; - - assign router_4_9_req_in[0] = router_4_10_to_router_4_9_req; - assign router_4_9_req_in[1] = router_5_9_to_router_4_9_req; - assign router_4_9_req_in[2] = router_4_8_to_router_4_9_req; - assign router_4_9_req_in[3] = router_3_9_to_router_4_9_req; - assign router_4_9_req_in[4] = magia_tile_ni_4_9_to_router_4_9_req; - - assign router_4_9_to_router_4_10_rsp = router_4_9_rsp_out[0]; - assign router_4_9_to_router_5_9_rsp = router_4_9_rsp_out[1]; - assign router_4_9_to_router_4_8_rsp = router_4_9_rsp_out[2]; - assign router_4_9_to_router_3_9_rsp = router_4_9_rsp_out[3]; - assign router_4_9_to_magia_tile_ni_4_9_rsp = router_4_9_rsp_out[4]; - - assign router_4_9_to_router_4_10_req = router_4_9_req_out[0]; - assign router_4_9_to_router_5_9_req = router_4_9_req_out[1]; - assign router_4_9_to_router_4_8_req = router_4_9_req_out[2]; - assign router_4_9_to_router_3_9_req = router_4_9_req_out[3]; - assign router_4_9_to_magia_tile_ni_4_9_req = router_4_9_req_out[4]; - - assign router_4_9_rsp_in[0] = router_4_10_to_router_4_9_rsp; - assign router_4_9_rsp_in[1] = router_5_9_to_router_4_9_rsp; - assign router_4_9_rsp_in[2] = router_4_8_to_router_4_9_rsp; - assign router_4_9_rsp_in[3] = router_3_9_to_router_4_9_rsp; - assign router_4_9_rsp_in[4] = magia_tile_ni_4_9_to_router_4_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_9_req_in), - .floo_rsp_o (router_4_9_rsp_out), - .floo_req_o (router_4_9_req_out), - .floo_rsp_i (router_4_9_rsp_in) -); - - -floo_req_t [4:0] router_4_10_req_in; -floo_rsp_t [4:0] router_4_10_rsp_out; -floo_req_t [4:0] router_4_10_req_out; -floo_rsp_t [4:0] router_4_10_rsp_in; - - assign router_4_10_req_in[0] = router_4_11_to_router_4_10_req; - assign router_4_10_req_in[1] = router_5_10_to_router_4_10_req; - assign router_4_10_req_in[2] = router_4_9_to_router_4_10_req; - assign router_4_10_req_in[3] = router_3_10_to_router_4_10_req; - assign router_4_10_req_in[4] = magia_tile_ni_4_10_to_router_4_10_req; - - assign router_4_10_to_router_4_11_rsp = router_4_10_rsp_out[0]; - assign router_4_10_to_router_5_10_rsp = router_4_10_rsp_out[1]; - assign router_4_10_to_router_4_9_rsp = router_4_10_rsp_out[2]; - assign router_4_10_to_router_3_10_rsp = router_4_10_rsp_out[3]; - assign router_4_10_to_magia_tile_ni_4_10_rsp = router_4_10_rsp_out[4]; - - assign router_4_10_to_router_4_11_req = router_4_10_req_out[0]; - assign router_4_10_to_router_5_10_req = router_4_10_req_out[1]; - assign router_4_10_to_router_4_9_req = router_4_10_req_out[2]; - assign router_4_10_to_router_3_10_req = router_4_10_req_out[3]; - assign router_4_10_to_magia_tile_ni_4_10_req = router_4_10_req_out[4]; - - assign router_4_10_rsp_in[0] = router_4_11_to_router_4_10_rsp; - assign router_4_10_rsp_in[1] = router_5_10_to_router_4_10_rsp; - assign router_4_10_rsp_in[2] = router_4_9_to_router_4_10_rsp; - assign router_4_10_rsp_in[3] = router_3_10_to_router_4_10_rsp; - assign router_4_10_rsp_in[4] = magia_tile_ni_4_10_to_router_4_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_10_req_in), - .floo_rsp_o (router_4_10_rsp_out), - .floo_req_o (router_4_10_req_out), - .floo_rsp_i (router_4_10_rsp_in) -); - - -floo_req_t [4:0] router_4_11_req_in; -floo_rsp_t [4:0] router_4_11_rsp_out; -floo_req_t [4:0] router_4_11_req_out; -floo_rsp_t [4:0] router_4_11_rsp_in; - - assign router_4_11_req_in[0] = router_4_12_to_router_4_11_req; - assign router_4_11_req_in[1] = router_5_11_to_router_4_11_req; - assign router_4_11_req_in[2] = router_4_10_to_router_4_11_req; - assign router_4_11_req_in[3] = router_3_11_to_router_4_11_req; - assign router_4_11_req_in[4] = magia_tile_ni_4_11_to_router_4_11_req; - - assign router_4_11_to_router_4_12_rsp = router_4_11_rsp_out[0]; - assign router_4_11_to_router_5_11_rsp = router_4_11_rsp_out[1]; - assign router_4_11_to_router_4_10_rsp = router_4_11_rsp_out[2]; - assign router_4_11_to_router_3_11_rsp = router_4_11_rsp_out[3]; - assign router_4_11_to_magia_tile_ni_4_11_rsp = router_4_11_rsp_out[4]; - - assign router_4_11_to_router_4_12_req = router_4_11_req_out[0]; - assign router_4_11_to_router_5_11_req = router_4_11_req_out[1]; - assign router_4_11_to_router_4_10_req = router_4_11_req_out[2]; - assign router_4_11_to_router_3_11_req = router_4_11_req_out[3]; - assign router_4_11_to_magia_tile_ni_4_11_req = router_4_11_req_out[4]; - - assign router_4_11_rsp_in[0] = router_4_12_to_router_4_11_rsp; - assign router_4_11_rsp_in[1] = router_5_11_to_router_4_11_rsp; - assign router_4_11_rsp_in[2] = router_4_10_to_router_4_11_rsp; - assign router_4_11_rsp_in[3] = router_3_11_to_router_4_11_rsp; - assign router_4_11_rsp_in[4] = magia_tile_ni_4_11_to_router_4_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_11_req_in), - .floo_rsp_o (router_4_11_rsp_out), - .floo_req_o (router_4_11_req_out), - .floo_rsp_i (router_4_11_rsp_in) -); - - -floo_req_t [4:0] router_4_12_req_in; -floo_rsp_t [4:0] router_4_12_rsp_out; -floo_req_t [4:0] router_4_12_req_out; -floo_rsp_t [4:0] router_4_12_rsp_in; - - assign router_4_12_req_in[0] = router_4_13_to_router_4_12_req; - assign router_4_12_req_in[1] = router_5_12_to_router_4_12_req; - assign router_4_12_req_in[2] = router_4_11_to_router_4_12_req; - assign router_4_12_req_in[3] = router_3_12_to_router_4_12_req; - assign router_4_12_req_in[4] = magia_tile_ni_4_12_to_router_4_12_req; - - assign router_4_12_to_router_4_13_rsp = router_4_12_rsp_out[0]; - assign router_4_12_to_router_5_12_rsp = router_4_12_rsp_out[1]; - assign router_4_12_to_router_4_11_rsp = router_4_12_rsp_out[2]; - assign router_4_12_to_router_3_12_rsp = router_4_12_rsp_out[3]; - assign router_4_12_to_magia_tile_ni_4_12_rsp = router_4_12_rsp_out[4]; - - assign router_4_12_to_router_4_13_req = router_4_12_req_out[0]; - assign router_4_12_to_router_5_12_req = router_4_12_req_out[1]; - assign router_4_12_to_router_4_11_req = router_4_12_req_out[2]; - assign router_4_12_to_router_3_12_req = router_4_12_req_out[3]; - assign router_4_12_to_magia_tile_ni_4_12_req = router_4_12_req_out[4]; - - assign router_4_12_rsp_in[0] = router_4_13_to_router_4_12_rsp; - assign router_4_12_rsp_in[1] = router_5_12_to_router_4_12_rsp; - assign router_4_12_rsp_in[2] = router_4_11_to_router_4_12_rsp; - assign router_4_12_rsp_in[3] = router_3_12_to_router_4_12_rsp; - assign router_4_12_rsp_in[4] = magia_tile_ni_4_12_to_router_4_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_12_req_in), - .floo_rsp_o (router_4_12_rsp_out), - .floo_req_o (router_4_12_req_out), - .floo_rsp_i (router_4_12_rsp_in) -); - - -floo_req_t [4:0] router_4_13_req_in; -floo_rsp_t [4:0] router_4_13_rsp_out; -floo_req_t [4:0] router_4_13_req_out; -floo_rsp_t [4:0] router_4_13_rsp_in; - - assign router_4_13_req_in[0] = router_4_14_to_router_4_13_req; - assign router_4_13_req_in[1] = router_5_13_to_router_4_13_req; - assign router_4_13_req_in[2] = router_4_12_to_router_4_13_req; - assign router_4_13_req_in[3] = router_3_13_to_router_4_13_req; - assign router_4_13_req_in[4] = magia_tile_ni_4_13_to_router_4_13_req; - - assign router_4_13_to_router_4_14_rsp = router_4_13_rsp_out[0]; - assign router_4_13_to_router_5_13_rsp = router_4_13_rsp_out[1]; - assign router_4_13_to_router_4_12_rsp = router_4_13_rsp_out[2]; - assign router_4_13_to_router_3_13_rsp = router_4_13_rsp_out[3]; - assign router_4_13_to_magia_tile_ni_4_13_rsp = router_4_13_rsp_out[4]; - - assign router_4_13_to_router_4_14_req = router_4_13_req_out[0]; - assign router_4_13_to_router_5_13_req = router_4_13_req_out[1]; - assign router_4_13_to_router_4_12_req = router_4_13_req_out[2]; - assign router_4_13_to_router_3_13_req = router_4_13_req_out[3]; - assign router_4_13_to_magia_tile_ni_4_13_req = router_4_13_req_out[4]; - - assign router_4_13_rsp_in[0] = router_4_14_to_router_4_13_rsp; - assign router_4_13_rsp_in[1] = router_5_13_to_router_4_13_rsp; - assign router_4_13_rsp_in[2] = router_4_12_to_router_4_13_rsp; - assign router_4_13_rsp_in[3] = router_3_13_to_router_4_13_rsp; - assign router_4_13_rsp_in[4] = magia_tile_ni_4_13_to_router_4_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_13_req_in), - .floo_rsp_o (router_4_13_rsp_out), - .floo_req_o (router_4_13_req_out), - .floo_rsp_i (router_4_13_rsp_in) -); - - -floo_req_t [4:0] router_4_14_req_in; -floo_rsp_t [4:0] router_4_14_rsp_out; -floo_req_t [4:0] router_4_14_req_out; -floo_rsp_t [4:0] router_4_14_rsp_in; - - assign router_4_14_req_in[0] = router_4_15_to_router_4_14_req; - assign router_4_14_req_in[1] = router_5_14_to_router_4_14_req; - assign router_4_14_req_in[2] = router_4_13_to_router_4_14_req; - assign router_4_14_req_in[3] = router_3_14_to_router_4_14_req; - assign router_4_14_req_in[4] = magia_tile_ni_4_14_to_router_4_14_req; - - assign router_4_14_to_router_4_15_rsp = router_4_14_rsp_out[0]; - assign router_4_14_to_router_5_14_rsp = router_4_14_rsp_out[1]; - assign router_4_14_to_router_4_13_rsp = router_4_14_rsp_out[2]; - assign router_4_14_to_router_3_14_rsp = router_4_14_rsp_out[3]; - assign router_4_14_to_magia_tile_ni_4_14_rsp = router_4_14_rsp_out[4]; - - assign router_4_14_to_router_4_15_req = router_4_14_req_out[0]; - assign router_4_14_to_router_5_14_req = router_4_14_req_out[1]; - assign router_4_14_to_router_4_13_req = router_4_14_req_out[2]; - assign router_4_14_to_router_3_14_req = router_4_14_req_out[3]; - assign router_4_14_to_magia_tile_ni_4_14_req = router_4_14_req_out[4]; - - assign router_4_14_rsp_in[0] = router_4_15_to_router_4_14_rsp; - assign router_4_14_rsp_in[1] = router_5_14_to_router_4_14_rsp; - assign router_4_14_rsp_in[2] = router_4_13_to_router_4_14_rsp; - assign router_4_14_rsp_in[3] = router_3_14_to_router_4_14_rsp; - assign router_4_14_rsp_in[4] = magia_tile_ni_4_14_to_router_4_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_14_req_in), - .floo_rsp_o (router_4_14_rsp_out), - .floo_req_o (router_4_14_req_out), - .floo_rsp_i (router_4_14_rsp_in) -); - - -floo_req_t [4:0] router_4_15_req_in; -floo_rsp_t [4:0] router_4_15_rsp_out; -floo_req_t [4:0] router_4_15_req_out; -floo_rsp_t [4:0] router_4_15_rsp_in; - - assign router_4_15_req_in[0] = router_4_16_to_router_4_15_req; - assign router_4_15_req_in[1] = router_5_15_to_router_4_15_req; - assign router_4_15_req_in[2] = router_4_14_to_router_4_15_req; - assign router_4_15_req_in[3] = router_3_15_to_router_4_15_req; - assign router_4_15_req_in[4] = magia_tile_ni_4_15_to_router_4_15_req; - - assign router_4_15_to_router_4_16_rsp = router_4_15_rsp_out[0]; - assign router_4_15_to_router_5_15_rsp = router_4_15_rsp_out[1]; - assign router_4_15_to_router_4_14_rsp = router_4_15_rsp_out[2]; - assign router_4_15_to_router_3_15_rsp = router_4_15_rsp_out[3]; - assign router_4_15_to_magia_tile_ni_4_15_rsp = router_4_15_rsp_out[4]; - - assign router_4_15_to_router_4_16_req = router_4_15_req_out[0]; - assign router_4_15_to_router_5_15_req = router_4_15_req_out[1]; - assign router_4_15_to_router_4_14_req = router_4_15_req_out[2]; - assign router_4_15_to_router_3_15_req = router_4_15_req_out[3]; - assign router_4_15_to_magia_tile_ni_4_15_req = router_4_15_req_out[4]; - - assign router_4_15_rsp_in[0] = router_4_16_to_router_4_15_rsp; - assign router_4_15_rsp_in[1] = router_5_15_to_router_4_15_rsp; - assign router_4_15_rsp_in[2] = router_4_14_to_router_4_15_rsp; - assign router_4_15_rsp_in[3] = router_3_15_to_router_4_15_rsp; - assign router_4_15_rsp_in[4] = magia_tile_ni_4_15_to_router_4_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_15_req_in), - .floo_rsp_o (router_4_15_rsp_out), - .floo_req_o (router_4_15_req_out), - .floo_rsp_i (router_4_15_rsp_in) -); - - -floo_req_t [4:0] router_4_16_req_in; -floo_rsp_t [4:0] router_4_16_rsp_out; -floo_req_t [4:0] router_4_16_req_out; -floo_rsp_t [4:0] router_4_16_rsp_in; - - assign router_4_16_req_in[0] = router_4_17_to_router_4_16_req; - assign router_4_16_req_in[1] = router_5_16_to_router_4_16_req; - assign router_4_16_req_in[2] = router_4_15_to_router_4_16_req; - assign router_4_16_req_in[3] = router_3_16_to_router_4_16_req; - assign router_4_16_req_in[4] = magia_tile_ni_4_16_to_router_4_16_req; - - assign router_4_16_to_router_4_17_rsp = router_4_16_rsp_out[0]; - assign router_4_16_to_router_5_16_rsp = router_4_16_rsp_out[1]; - assign router_4_16_to_router_4_15_rsp = router_4_16_rsp_out[2]; - assign router_4_16_to_router_3_16_rsp = router_4_16_rsp_out[3]; - assign router_4_16_to_magia_tile_ni_4_16_rsp = router_4_16_rsp_out[4]; - - assign router_4_16_to_router_4_17_req = router_4_16_req_out[0]; - assign router_4_16_to_router_5_16_req = router_4_16_req_out[1]; - assign router_4_16_to_router_4_15_req = router_4_16_req_out[2]; - assign router_4_16_to_router_3_16_req = router_4_16_req_out[3]; - assign router_4_16_to_magia_tile_ni_4_16_req = router_4_16_req_out[4]; - - assign router_4_16_rsp_in[0] = router_4_17_to_router_4_16_rsp; - assign router_4_16_rsp_in[1] = router_5_16_to_router_4_16_rsp; - assign router_4_16_rsp_in[2] = router_4_15_to_router_4_16_rsp; - assign router_4_16_rsp_in[3] = router_3_16_to_router_4_16_rsp; - assign router_4_16_rsp_in[4] = magia_tile_ni_4_16_to_router_4_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_16_req_in), - .floo_rsp_o (router_4_16_rsp_out), - .floo_req_o (router_4_16_req_out), - .floo_rsp_i (router_4_16_rsp_in) -); - - -floo_req_t [4:0] router_4_17_req_in; -floo_rsp_t [4:0] router_4_17_rsp_out; -floo_req_t [4:0] router_4_17_req_out; -floo_rsp_t [4:0] router_4_17_rsp_in; - - assign router_4_17_req_in[0] = router_4_18_to_router_4_17_req; - assign router_4_17_req_in[1] = router_5_17_to_router_4_17_req; - assign router_4_17_req_in[2] = router_4_16_to_router_4_17_req; - assign router_4_17_req_in[3] = router_3_17_to_router_4_17_req; - assign router_4_17_req_in[4] = magia_tile_ni_4_17_to_router_4_17_req; - - assign router_4_17_to_router_4_18_rsp = router_4_17_rsp_out[0]; - assign router_4_17_to_router_5_17_rsp = router_4_17_rsp_out[1]; - assign router_4_17_to_router_4_16_rsp = router_4_17_rsp_out[2]; - assign router_4_17_to_router_3_17_rsp = router_4_17_rsp_out[3]; - assign router_4_17_to_magia_tile_ni_4_17_rsp = router_4_17_rsp_out[4]; - - assign router_4_17_to_router_4_18_req = router_4_17_req_out[0]; - assign router_4_17_to_router_5_17_req = router_4_17_req_out[1]; - assign router_4_17_to_router_4_16_req = router_4_17_req_out[2]; - assign router_4_17_to_router_3_17_req = router_4_17_req_out[3]; - assign router_4_17_to_magia_tile_ni_4_17_req = router_4_17_req_out[4]; - - assign router_4_17_rsp_in[0] = router_4_18_to_router_4_17_rsp; - assign router_4_17_rsp_in[1] = router_5_17_to_router_4_17_rsp; - assign router_4_17_rsp_in[2] = router_4_16_to_router_4_17_rsp; - assign router_4_17_rsp_in[3] = router_3_17_to_router_4_17_rsp; - assign router_4_17_rsp_in[4] = magia_tile_ni_4_17_to_router_4_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_17_req_in), - .floo_rsp_o (router_4_17_rsp_out), - .floo_req_o (router_4_17_req_out), - .floo_rsp_i (router_4_17_rsp_in) -); - - -floo_req_t [4:0] router_4_18_req_in; -floo_rsp_t [4:0] router_4_18_rsp_out; -floo_req_t [4:0] router_4_18_req_out; -floo_rsp_t [4:0] router_4_18_rsp_in; - - assign router_4_18_req_in[0] = router_4_19_to_router_4_18_req; - assign router_4_18_req_in[1] = router_5_18_to_router_4_18_req; - assign router_4_18_req_in[2] = router_4_17_to_router_4_18_req; - assign router_4_18_req_in[3] = router_3_18_to_router_4_18_req; - assign router_4_18_req_in[4] = magia_tile_ni_4_18_to_router_4_18_req; - - assign router_4_18_to_router_4_19_rsp = router_4_18_rsp_out[0]; - assign router_4_18_to_router_5_18_rsp = router_4_18_rsp_out[1]; - assign router_4_18_to_router_4_17_rsp = router_4_18_rsp_out[2]; - assign router_4_18_to_router_3_18_rsp = router_4_18_rsp_out[3]; - assign router_4_18_to_magia_tile_ni_4_18_rsp = router_4_18_rsp_out[4]; - - assign router_4_18_to_router_4_19_req = router_4_18_req_out[0]; - assign router_4_18_to_router_5_18_req = router_4_18_req_out[1]; - assign router_4_18_to_router_4_17_req = router_4_18_req_out[2]; - assign router_4_18_to_router_3_18_req = router_4_18_req_out[3]; - assign router_4_18_to_magia_tile_ni_4_18_req = router_4_18_req_out[4]; - - assign router_4_18_rsp_in[0] = router_4_19_to_router_4_18_rsp; - assign router_4_18_rsp_in[1] = router_5_18_to_router_4_18_rsp; - assign router_4_18_rsp_in[2] = router_4_17_to_router_4_18_rsp; - assign router_4_18_rsp_in[3] = router_3_18_to_router_4_18_rsp; - assign router_4_18_rsp_in[4] = magia_tile_ni_4_18_to_router_4_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_18_req_in), - .floo_rsp_o (router_4_18_rsp_out), - .floo_req_o (router_4_18_req_out), - .floo_rsp_i (router_4_18_rsp_in) -); - - -floo_req_t [4:0] router_4_19_req_in; -floo_rsp_t [4:0] router_4_19_rsp_out; -floo_req_t [4:0] router_4_19_req_out; -floo_rsp_t [4:0] router_4_19_rsp_in; - - assign router_4_19_req_in[0] = router_4_20_to_router_4_19_req; - assign router_4_19_req_in[1] = router_5_19_to_router_4_19_req; - assign router_4_19_req_in[2] = router_4_18_to_router_4_19_req; - assign router_4_19_req_in[3] = router_3_19_to_router_4_19_req; - assign router_4_19_req_in[4] = magia_tile_ni_4_19_to_router_4_19_req; - - assign router_4_19_to_router_4_20_rsp = router_4_19_rsp_out[0]; - assign router_4_19_to_router_5_19_rsp = router_4_19_rsp_out[1]; - assign router_4_19_to_router_4_18_rsp = router_4_19_rsp_out[2]; - assign router_4_19_to_router_3_19_rsp = router_4_19_rsp_out[3]; - assign router_4_19_to_magia_tile_ni_4_19_rsp = router_4_19_rsp_out[4]; - - assign router_4_19_to_router_4_20_req = router_4_19_req_out[0]; - assign router_4_19_to_router_5_19_req = router_4_19_req_out[1]; - assign router_4_19_to_router_4_18_req = router_4_19_req_out[2]; - assign router_4_19_to_router_3_19_req = router_4_19_req_out[3]; - assign router_4_19_to_magia_tile_ni_4_19_req = router_4_19_req_out[4]; - - assign router_4_19_rsp_in[0] = router_4_20_to_router_4_19_rsp; - assign router_4_19_rsp_in[1] = router_5_19_to_router_4_19_rsp; - assign router_4_19_rsp_in[2] = router_4_18_to_router_4_19_rsp; - assign router_4_19_rsp_in[3] = router_3_19_to_router_4_19_rsp; - assign router_4_19_rsp_in[4] = magia_tile_ni_4_19_to_router_4_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_19_req_in), - .floo_rsp_o (router_4_19_rsp_out), - .floo_req_o (router_4_19_req_out), - .floo_rsp_i (router_4_19_rsp_in) -); - - -floo_req_t [4:0] router_4_20_req_in; -floo_rsp_t [4:0] router_4_20_rsp_out; -floo_req_t [4:0] router_4_20_req_out; -floo_rsp_t [4:0] router_4_20_rsp_in; - - assign router_4_20_req_in[0] = router_4_21_to_router_4_20_req; - assign router_4_20_req_in[1] = router_5_20_to_router_4_20_req; - assign router_4_20_req_in[2] = router_4_19_to_router_4_20_req; - assign router_4_20_req_in[3] = router_3_20_to_router_4_20_req; - assign router_4_20_req_in[4] = magia_tile_ni_4_20_to_router_4_20_req; - - assign router_4_20_to_router_4_21_rsp = router_4_20_rsp_out[0]; - assign router_4_20_to_router_5_20_rsp = router_4_20_rsp_out[1]; - assign router_4_20_to_router_4_19_rsp = router_4_20_rsp_out[2]; - assign router_4_20_to_router_3_20_rsp = router_4_20_rsp_out[3]; - assign router_4_20_to_magia_tile_ni_4_20_rsp = router_4_20_rsp_out[4]; - - assign router_4_20_to_router_4_21_req = router_4_20_req_out[0]; - assign router_4_20_to_router_5_20_req = router_4_20_req_out[1]; - assign router_4_20_to_router_4_19_req = router_4_20_req_out[2]; - assign router_4_20_to_router_3_20_req = router_4_20_req_out[3]; - assign router_4_20_to_magia_tile_ni_4_20_req = router_4_20_req_out[4]; - - assign router_4_20_rsp_in[0] = router_4_21_to_router_4_20_rsp; - assign router_4_20_rsp_in[1] = router_5_20_to_router_4_20_rsp; - assign router_4_20_rsp_in[2] = router_4_19_to_router_4_20_rsp; - assign router_4_20_rsp_in[3] = router_3_20_to_router_4_20_rsp; - assign router_4_20_rsp_in[4] = magia_tile_ni_4_20_to_router_4_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_20_req_in), - .floo_rsp_o (router_4_20_rsp_out), - .floo_req_o (router_4_20_req_out), - .floo_rsp_i (router_4_20_rsp_in) -); - - -floo_req_t [4:0] router_4_21_req_in; -floo_rsp_t [4:0] router_4_21_rsp_out; -floo_req_t [4:0] router_4_21_req_out; -floo_rsp_t [4:0] router_4_21_rsp_in; - - assign router_4_21_req_in[0] = router_4_22_to_router_4_21_req; - assign router_4_21_req_in[1] = router_5_21_to_router_4_21_req; - assign router_4_21_req_in[2] = router_4_20_to_router_4_21_req; - assign router_4_21_req_in[3] = router_3_21_to_router_4_21_req; - assign router_4_21_req_in[4] = magia_tile_ni_4_21_to_router_4_21_req; - - assign router_4_21_to_router_4_22_rsp = router_4_21_rsp_out[0]; - assign router_4_21_to_router_5_21_rsp = router_4_21_rsp_out[1]; - assign router_4_21_to_router_4_20_rsp = router_4_21_rsp_out[2]; - assign router_4_21_to_router_3_21_rsp = router_4_21_rsp_out[3]; - assign router_4_21_to_magia_tile_ni_4_21_rsp = router_4_21_rsp_out[4]; - - assign router_4_21_to_router_4_22_req = router_4_21_req_out[0]; - assign router_4_21_to_router_5_21_req = router_4_21_req_out[1]; - assign router_4_21_to_router_4_20_req = router_4_21_req_out[2]; - assign router_4_21_to_router_3_21_req = router_4_21_req_out[3]; - assign router_4_21_to_magia_tile_ni_4_21_req = router_4_21_req_out[4]; - - assign router_4_21_rsp_in[0] = router_4_22_to_router_4_21_rsp; - assign router_4_21_rsp_in[1] = router_5_21_to_router_4_21_rsp; - assign router_4_21_rsp_in[2] = router_4_20_to_router_4_21_rsp; - assign router_4_21_rsp_in[3] = router_3_21_to_router_4_21_rsp; - assign router_4_21_rsp_in[4] = magia_tile_ni_4_21_to_router_4_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_21_req_in), - .floo_rsp_o (router_4_21_rsp_out), - .floo_req_o (router_4_21_req_out), - .floo_rsp_i (router_4_21_rsp_in) -); - - -floo_req_t [4:0] router_4_22_req_in; -floo_rsp_t [4:0] router_4_22_rsp_out; -floo_req_t [4:0] router_4_22_req_out; -floo_rsp_t [4:0] router_4_22_rsp_in; - - assign router_4_22_req_in[0] = router_4_23_to_router_4_22_req; - assign router_4_22_req_in[1] = router_5_22_to_router_4_22_req; - assign router_4_22_req_in[2] = router_4_21_to_router_4_22_req; - assign router_4_22_req_in[3] = router_3_22_to_router_4_22_req; - assign router_4_22_req_in[4] = magia_tile_ni_4_22_to_router_4_22_req; - - assign router_4_22_to_router_4_23_rsp = router_4_22_rsp_out[0]; - assign router_4_22_to_router_5_22_rsp = router_4_22_rsp_out[1]; - assign router_4_22_to_router_4_21_rsp = router_4_22_rsp_out[2]; - assign router_4_22_to_router_3_22_rsp = router_4_22_rsp_out[3]; - assign router_4_22_to_magia_tile_ni_4_22_rsp = router_4_22_rsp_out[4]; - - assign router_4_22_to_router_4_23_req = router_4_22_req_out[0]; - assign router_4_22_to_router_5_22_req = router_4_22_req_out[1]; - assign router_4_22_to_router_4_21_req = router_4_22_req_out[2]; - assign router_4_22_to_router_3_22_req = router_4_22_req_out[3]; - assign router_4_22_to_magia_tile_ni_4_22_req = router_4_22_req_out[4]; - - assign router_4_22_rsp_in[0] = router_4_23_to_router_4_22_rsp; - assign router_4_22_rsp_in[1] = router_5_22_to_router_4_22_rsp; - assign router_4_22_rsp_in[2] = router_4_21_to_router_4_22_rsp; - assign router_4_22_rsp_in[3] = router_3_22_to_router_4_22_rsp; - assign router_4_22_rsp_in[4] = magia_tile_ni_4_22_to_router_4_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_22_req_in), - .floo_rsp_o (router_4_22_rsp_out), - .floo_req_o (router_4_22_req_out), - .floo_rsp_i (router_4_22_rsp_in) -); - - -floo_req_t [4:0] router_4_23_req_in; -floo_rsp_t [4:0] router_4_23_rsp_out; -floo_req_t [4:0] router_4_23_req_out; -floo_rsp_t [4:0] router_4_23_rsp_in; - - assign router_4_23_req_in[0] = router_4_24_to_router_4_23_req; - assign router_4_23_req_in[1] = router_5_23_to_router_4_23_req; - assign router_4_23_req_in[2] = router_4_22_to_router_4_23_req; - assign router_4_23_req_in[3] = router_3_23_to_router_4_23_req; - assign router_4_23_req_in[4] = magia_tile_ni_4_23_to_router_4_23_req; - - assign router_4_23_to_router_4_24_rsp = router_4_23_rsp_out[0]; - assign router_4_23_to_router_5_23_rsp = router_4_23_rsp_out[1]; - assign router_4_23_to_router_4_22_rsp = router_4_23_rsp_out[2]; - assign router_4_23_to_router_3_23_rsp = router_4_23_rsp_out[3]; - assign router_4_23_to_magia_tile_ni_4_23_rsp = router_4_23_rsp_out[4]; - - assign router_4_23_to_router_4_24_req = router_4_23_req_out[0]; - assign router_4_23_to_router_5_23_req = router_4_23_req_out[1]; - assign router_4_23_to_router_4_22_req = router_4_23_req_out[2]; - assign router_4_23_to_router_3_23_req = router_4_23_req_out[3]; - assign router_4_23_to_magia_tile_ni_4_23_req = router_4_23_req_out[4]; - - assign router_4_23_rsp_in[0] = router_4_24_to_router_4_23_rsp; - assign router_4_23_rsp_in[1] = router_5_23_to_router_4_23_rsp; - assign router_4_23_rsp_in[2] = router_4_22_to_router_4_23_rsp; - assign router_4_23_rsp_in[3] = router_3_23_to_router_4_23_rsp; - assign router_4_23_rsp_in[4] = magia_tile_ni_4_23_to_router_4_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_23_req_in), - .floo_rsp_o (router_4_23_rsp_out), - .floo_req_o (router_4_23_req_out), - .floo_rsp_i (router_4_23_rsp_in) -); - - -floo_req_t [4:0] router_4_24_req_in; -floo_rsp_t [4:0] router_4_24_rsp_out; -floo_req_t [4:0] router_4_24_req_out; -floo_rsp_t [4:0] router_4_24_rsp_in; - - assign router_4_24_req_in[0] = router_4_25_to_router_4_24_req; - assign router_4_24_req_in[1] = router_5_24_to_router_4_24_req; - assign router_4_24_req_in[2] = router_4_23_to_router_4_24_req; - assign router_4_24_req_in[3] = router_3_24_to_router_4_24_req; - assign router_4_24_req_in[4] = magia_tile_ni_4_24_to_router_4_24_req; - - assign router_4_24_to_router_4_25_rsp = router_4_24_rsp_out[0]; - assign router_4_24_to_router_5_24_rsp = router_4_24_rsp_out[1]; - assign router_4_24_to_router_4_23_rsp = router_4_24_rsp_out[2]; - assign router_4_24_to_router_3_24_rsp = router_4_24_rsp_out[3]; - assign router_4_24_to_magia_tile_ni_4_24_rsp = router_4_24_rsp_out[4]; - - assign router_4_24_to_router_4_25_req = router_4_24_req_out[0]; - assign router_4_24_to_router_5_24_req = router_4_24_req_out[1]; - assign router_4_24_to_router_4_23_req = router_4_24_req_out[2]; - assign router_4_24_to_router_3_24_req = router_4_24_req_out[3]; - assign router_4_24_to_magia_tile_ni_4_24_req = router_4_24_req_out[4]; - - assign router_4_24_rsp_in[0] = router_4_25_to_router_4_24_rsp; - assign router_4_24_rsp_in[1] = router_5_24_to_router_4_24_rsp; - assign router_4_24_rsp_in[2] = router_4_23_to_router_4_24_rsp; - assign router_4_24_rsp_in[3] = router_3_24_to_router_4_24_rsp; - assign router_4_24_rsp_in[4] = magia_tile_ni_4_24_to_router_4_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_24_req_in), - .floo_rsp_o (router_4_24_rsp_out), - .floo_req_o (router_4_24_req_out), - .floo_rsp_i (router_4_24_rsp_in) -); - - -floo_req_t [4:0] router_4_25_req_in; -floo_rsp_t [4:0] router_4_25_rsp_out; -floo_req_t [4:0] router_4_25_req_out; -floo_rsp_t [4:0] router_4_25_rsp_in; - - assign router_4_25_req_in[0] = router_4_26_to_router_4_25_req; - assign router_4_25_req_in[1] = router_5_25_to_router_4_25_req; - assign router_4_25_req_in[2] = router_4_24_to_router_4_25_req; - assign router_4_25_req_in[3] = router_3_25_to_router_4_25_req; - assign router_4_25_req_in[4] = magia_tile_ni_4_25_to_router_4_25_req; - - assign router_4_25_to_router_4_26_rsp = router_4_25_rsp_out[0]; - assign router_4_25_to_router_5_25_rsp = router_4_25_rsp_out[1]; - assign router_4_25_to_router_4_24_rsp = router_4_25_rsp_out[2]; - assign router_4_25_to_router_3_25_rsp = router_4_25_rsp_out[3]; - assign router_4_25_to_magia_tile_ni_4_25_rsp = router_4_25_rsp_out[4]; - - assign router_4_25_to_router_4_26_req = router_4_25_req_out[0]; - assign router_4_25_to_router_5_25_req = router_4_25_req_out[1]; - assign router_4_25_to_router_4_24_req = router_4_25_req_out[2]; - assign router_4_25_to_router_3_25_req = router_4_25_req_out[3]; - assign router_4_25_to_magia_tile_ni_4_25_req = router_4_25_req_out[4]; - - assign router_4_25_rsp_in[0] = router_4_26_to_router_4_25_rsp; - assign router_4_25_rsp_in[1] = router_5_25_to_router_4_25_rsp; - assign router_4_25_rsp_in[2] = router_4_24_to_router_4_25_rsp; - assign router_4_25_rsp_in[3] = router_3_25_to_router_4_25_rsp; - assign router_4_25_rsp_in[4] = magia_tile_ni_4_25_to_router_4_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_25_req_in), - .floo_rsp_o (router_4_25_rsp_out), - .floo_req_o (router_4_25_req_out), - .floo_rsp_i (router_4_25_rsp_in) -); - - -floo_req_t [4:0] router_4_26_req_in; -floo_rsp_t [4:0] router_4_26_rsp_out; -floo_req_t [4:0] router_4_26_req_out; -floo_rsp_t [4:0] router_4_26_rsp_in; - - assign router_4_26_req_in[0] = router_4_27_to_router_4_26_req; - assign router_4_26_req_in[1] = router_5_26_to_router_4_26_req; - assign router_4_26_req_in[2] = router_4_25_to_router_4_26_req; - assign router_4_26_req_in[3] = router_3_26_to_router_4_26_req; - assign router_4_26_req_in[4] = magia_tile_ni_4_26_to_router_4_26_req; - - assign router_4_26_to_router_4_27_rsp = router_4_26_rsp_out[0]; - assign router_4_26_to_router_5_26_rsp = router_4_26_rsp_out[1]; - assign router_4_26_to_router_4_25_rsp = router_4_26_rsp_out[2]; - assign router_4_26_to_router_3_26_rsp = router_4_26_rsp_out[3]; - assign router_4_26_to_magia_tile_ni_4_26_rsp = router_4_26_rsp_out[4]; - - assign router_4_26_to_router_4_27_req = router_4_26_req_out[0]; - assign router_4_26_to_router_5_26_req = router_4_26_req_out[1]; - assign router_4_26_to_router_4_25_req = router_4_26_req_out[2]; - assign router_4_26_to_router_3_26_req = router_4_26_req_out[3]; - assign router_4_26_to_magia_tile_ni_4_26_req = router_4_26_req_out[4]; - - assign router_4_26_rsp_in[0] = router_4_27_to_router_4_26_rsp; - assign router_4_26_rsp_in[1] = router_5_26_to_router_4_26_rsp; - assign router_4_26_rsp_in[2] = router_4_25_to_router_4_26_rsp; - assign router_4_26_rsp_in[3] = router_3_26_to_router_4_26_rsp; - assign router_4_26_rsp_in[4] = magia_tile_ni_4_26_to_router_4_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_26_req_in), - .floo_rsp_o (router_4_26_rsp_out), - .floo_req_o (router_4_26_req_out), - .floo_rsp_i (router_4_26_rsp_in) -); - - -floo_req_t [4:0] router_4_27_req_in; -floo_rsp_t [4:0] router_4_27_rsp_out; -floo_req_t [4:0] router_4_27_req_out; -floo_rsp_t [4:0] router_4_27_rsp_in; - - assign router_4_27_req_in[0] = router_4_28_to_router_4_27_req; - assign router_4_27_req_in[1] = router_5_27_to_router_4_27_req; - assign router_4_27_req_in[2] = router_4_26_to_router_4_27_req; - assign router_4_27_req_in[3] = router_3_27_to_router_4_27_req; - assign router_4_27_req_in[4] = magia_tile_ni_4_27_to_router_4_27_req; - - assign router_4_27_to_router_4_28_rsp = router_4_27_rsp_out[0]; - assign router_4_27_to_router_5_27_rsp = router_4_27_rsp_out[1]; - assign router_4_27_to_router_4_26_rsp = router_4_27_rsp_out[2]; - assign router_4_27_to_router_3_27_rsp = router_4_27_rsp_out[3]; - assign router_4_27_to_magia_tile_ni_4_27_rsp = router_4_27_rsp_out[4]; - - assign router_4_27_to_router_4_28_req = router_4_27_req_out[0]; - assign router_4_27_to_router_5_27_req = router_4_27_req_out[1]; - assign router_4_27_to_router_4_26_req = router_4_27_req_out[2]; - assign router_4_27_to_router_3_27_req = router_4_27_req_out[3]; - assign router_4_27_to_magia_tile_ni_4_27_req = router_4_27_req_out[4]; - - assign router_4_27_rsp_in[0] = router_4_28_to_router_4_27_rsp; - assign router_4_27_rsp_in[1] = router_5_27_to_router_4_27_rsp; - assign router_4_27_rsp_in[2] = router_4_26_to_router_4_27_rsp; - assign router_4_27_rsp_in[3] = router_3_27_to_router_4_27_rsp; - assign router_4_27_rsp_in[4] = magia_tile_ni_4_27_to_router_4_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_27_req_in), - .floo_rsp_o (router_4_27_rsp_out), - .floo_req_o (router_4_27_req_out), - .floo_rsp_i (router_4_27_rsp_in) -); - - -floo_req_t [4:0] router_4_28_req_in; -floo_rsp_t [4:0] router_4_28_rsp_out; -floo_req_t [4:0] router_4_28_req_out; -floo_rsp_t [4:0] router_4_28_rsp_in; - - assign router_4_28_req_in[0] = router_4_29_to_router_4_28_req; - assign router_4_28_req_in[1] = router_5_28_to_router_4_28_req; - assign router_4_28_req_in[2] = router_4_27_to_router_4_28_req; - assign router_4_28_req_in[3] = router_3_28_to_router_4_28_req; - assign router_4_28_req_in[4] = magia_tile_ni_4_28_to_router_4_28_req; - - assign router_4_28_to_router_4_29_rsp = router_4_28_rsp_out[0]; - assign router_4_28_to_router_5_28_rsp = router_4_28_rsp_out[1]; - assign router_4_28_to_router_4_27_rsp = router_4_28_rsp_out[2]; - assign router_4_28_to_router_3_28_rsp = router_4_28_rsp_out[3]; - assign router_4_28_to_magia_tile_ni_4_28_rsp = router_4_28_rsp_out[4]; - - assign router_4_28_to_router_4_29_req = router_4_28_req_out[0]; - assign router_4_28_to_router_5_28_req = router_4_28_req_out[1]; - assign router_4_28_to_router_4_27_req = router_4_28_req_out[2]; - assign router_4_28_to_router_3_28_req = router_4_28_req_out[3]; - assign router_4_28_to_magia_tile_ni_4_28_req = router_4_28_req_out[4]; - - assign router_4_28_rsp_in[0] = router_4_29_to_router_4_28_rsp; - assign router_4_28_rsp_in[1] = router_5_28_to_router_4_28_rsp; - assign router_4_28_rsp_in[2] = router_4_27_to_router_4_28_rsp; - assign router_4_28_rsp_in[3] = router_3_28_to_router_4_28_rsp; - assign router_4_28_rsp_in[4] = magia_tile_ni_4_28_to_router_4_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_28_req_in), - .floo_rsp_o (router_4_28_rsp_out), - .floo_req_o (router_4_28_req_out), - .floo_rsp_i (router_4_28_rsp_in) -); - - -floo_req_t [4:0] router_4_29_req_in; -floo_rsp_t [4:0] router_4_29_rsp_out; -floo_req_t [4:0] router_4_29_req_out; -floo_rsp_t [4:0] router_4_29_rsp_in; - - assign router_4_29_req_in[0] = router_4_30_to_router_4_29_req; - assign router_4_29_req_in[1] = router_5_29_to_router_4_29_req; - assign router_4_29_req_in[2] = router_4_28_to_router_4_29_req; - assign router_4_29_req_in[3] = router_3_29_to_router_4_29_req; - assign router_4_29_req_in[4] = magia_tile_ni_4_29_to_router_4_29_req; - - assign router_4_29_to_router_4_30_rsp = router_4_29_rsp_out[0]; - assign router_4_29_to_router_5_29_rsp = router_4_29_rsp_out[1]; - assign router_4_29_to_router_4_28_rsp = router_4_29_rsp_out[2]; - assign router_4_29_to_router_3_29_rsp = router_4_29_rsp_out[3]; - assign router_4_29_to_magia_tile_ni_4_29_rsp = router_4_29_rsp_out[4]; - - assign router_4_29_to_router_4_30_req = router_4_29_req_out[0]; - assign router_4_29_to_router_5_29_req = router_4_29_req_out[1]; - assign router_4_29_to_router_4_28_req = router_4_29_req_out[2]; - assign router_4_29_to_router_3_29_req = router_4_29_req_out[3]; - assign router_4_29_to_magia_tile_ni_4_29_req = router_4_29_req_out[4]; - - assign router_4_29_rsp_in[0] = router_4_30_to_router_4_29_rsp; - assign router_4_29_rsp_in[1] = router_5_29_to_router_4_29_rsp; - assign router_4_29_rsp_in[2] = router_4_28_to_router_4_29_rsp; - assign router_4_29_rsp_in[3] = router_3_29_to_router_4_29_rsp; - assign router_4_29_rsp_in[4] = magia_tile_ni_4_29_to_router_4_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_29_req_in), - .floo_rsp_o (router_4_29_rsp_out), - .floo_req_o (router_4_29_req_out), - .floo_rsp_i (router_4_29_rsp_in) -); - - -floo_req_t [4:0] router_4_30_req_in; -floo_rsp_t [4:0] router_4_30_rsp_out; -floo_req_t [4:0] router_4_30_req_out; -floo_rsp_t [4:0] router_4_30_rsp_in; - - assign router_4_30_req_in[0] = router_4_31_to_router_4_30_req; - assign router_4_30_req_in[1] = router_5_30_to_router_4_30_req; - assign router_4_30_req_in[2] = router_4_29_to_router_4_30_req; - assign router_4_30_req_in[3] = router_3_30_to_router_4_30_req; - assign router_4_30_req_in[4] = magia_tile_ni_4_30_to_router_4_30_req; - - assign router_4_30_to_router_4_31_rsp = router_4_30_rsp_out[0]; - assign router_4_30_to_router_5_30_rsp = router_4_30_rsp_out[1]; - assign router_4_30_to_router_4_29_rsp = router_4_30_rsp_out[2]; - assign router_4_30_to_router_3_30_rsp = router_4_30_rsp_out[3]; - assign router_4_30_to_magia_tile_ni_4_30_rsp = router_4_30_rsp_out[4]; - - assign router_4_30_to_router_4_31_req = router_4_30_req_out[0]; - assign router_4_30_to_router_5_30_req = router_4_30_req_out[1]; - assign router_4_30_to_router_4_29_req = router_4_30_req_out[2]; - assign router_4_30_to_router_3_30_req = router_4_30_req_out[3]; - assign router_4_30_to_magia_tile_ni_4_30_req = router_4_30_req_out[4]; - - assign router_4_30_rsp_in[0] = router_4_31_to_router_4_30_rsp; - assign router_4_30_rsp_in[1] = router_5_30_to_router_4_30_rsp; - assign router_4_30_rsp_in[2] = router_4_29_to_router_4_30_rsp; - assign router_4_30_rsp_in[3] = router_3_30_to_router_4_30_rsp; - assign router_4_30_rsp_in[4] = magia_tile_ni_4_30_to_router_4_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_30_req_in), - .floo_rsp_o (router_4_30_rsp_out), - .floo_req_o (router_4_30_req_out), - .floo_rsp_i (router_4_30_rsp_in) -); - - -floo_req_t [4:0] router_4_31_req_in; -floo_rsp_t [4:0] router_4_31_rsp_out; -floo_req_t [4:0] router_4_31_req_out; -floo_rsp_t [4:0] router_4_31_rsp_in; - - assign router_4_31_req_in[0] = '0; - assign router_4_31_req_in[1] = router_5_31_to_router_4_31_req; - assign router_4_31_req_in[2] = router_4_30_to_router_4_31_req; - assign router_4_31_req_in[3] = router_3_31_to_router_4_31_req; - assign router_4_31_req_in[4] = magia_tile_ni_4_31_to_router_4_31_req; - - assign router_4_31_to_router_5_31_rsp = router_4_31_rsp_out[1]; - assign router_4_31_to_router_4_30_rsp = router_4_31_rsp_out[2]; - assign router_4_31_to_router_3_31_rsp = router_4_31_rsp_out[3]; - assign router_4_31_to_magia_tile_ni_4_31_rsp = router_4_31_rsp_out[4]; - - assign router_4_31_to_router_5_31_req = router_4_31_req_out[1]; - assign router_4_31_to_router_4_30_req = router_4_31_req_out[2]; - assign router_4_31_to_router_3_31_req = router_4_31_req_out[3]; - assign router_4_31_to_magia_tile_ni_4_31_req = router_4_31_req_out[4]; - - assign router_4_31_rsp_in[0] = '0; - assign router_4_31_rsp_in[1] = router_5_31_to_router_4_31_rsp; - assign router_4_31_rsp_in[2] = router_4_30_to_router_4_31_rsp; - assign router_4_31_rsp_in[3] = router_3_31_to_router_4_31_rsp; - assign router_4_31_rsp_in[4] = magia_tile_ni_4_31_to_router_4_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_31_req_in), - .floo_rsp_o (router_4_31_rsp_out), - .floo_req_o (router_4_31_req_out), - .floo_rsp_i (router_4_31_rsp_in) -); - - -floo_req_t [4:0] router_5_0_req_in; -floo_rsp_t [4:0] router_5_0_rsp_out; -floo_req_t [4:0] router_5_0_req_out; -floo_rsp_t [4:0] router_5_0_rsp_in; - - assign router_5_0_req_in[0] = router_5_1_to_router_5_0_req; - assign router_5_0_req_in[1] = router_6_0_to_router_5_0_req; - assign router_5_0_req_in[2] = '0; - assign router_5_0_req_in[3] = router_4_0_to_router_5_0_req; - assign router_5_0_req_in[4] = magia_tile_ni_5_0_to_router_5_0_req; - - assign router_5_0_to_router_5_1_rsp = router_5_0_rsp_out[0]; - assign router_5_0_to_router_6_0_rsp = router_5_0_rsp_out[1]; - assign router_5_0_to_router_4_0_rsp = router_5_0_rsp_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_rsp = router_5_0_rsp_out[4]; - - assign router_5_0_to_router_5_1_req = router_5_0_req_out[0]; - assign router_5_0_to_router_6_0_req = router_5_0_req_out[1]; - assign router_5_0_to_router_4_0_req = router_5_0_req_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_req = router_5_0_req_out[4]; - - assign router_5_0_rsp_in[0] = router_5_1_to_router_5_0_rsp; - assign router_5_0_rsp_in[1] = router_6_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[2] = '0; - assign router_5_0_rsp_in[3] = router_4_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[4] = magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_0_req_in), - .floo_rsp_o (router_5_0_rsp_out), - .floo_req_o (router_5_0_req_out), - .floo_rsp_i (router_5_0_rsp_in) -); - - -floo_req_t [4:0] router_5_1_req_in; -floo_rsp_t [4:0] router_5_1_rsp_out; -floo_req_t [4:0] router_5_1_req_out; -floo_rsp_t [4:0] router_5_1_rsp_in; - - assign router_5_1_req_in[0] = router_5_2_to_router_5_1_req; - assign router_5_1_req_in[1] = router_6_1_to_router_5_1_req; - assign router_5_1_req_in[2] = router_5_0_to_router_5_1_req; - assign router_5_1_req_in[3] = router_4_1_to_router_5_1_req; - assign router_5_1_req_in[4] = magia_tile_ni_5_1_to_router_5_1_req; - - assign router_5_1_to_router_5_2_rsp = router_5_1_rsp_out[0]; - assign router_5_1_to_router_6_1_rsp = router_5_1_rsp_out[1]; - assign router_5_1_to_router_5_0_rsp = router_5_1_rsp_out[2]; - assign router_5_1_to_router_4_1_rsp = router_5_1_rsp_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_rsp = router_5_1_rsp_out[4]; - - assign router_5_1_to_router_5_2_req = router_5_1_req_out[0]; - assign router_5_1_to_router_6_1_req = router_5_1_req_out[1]; - assign router_5_1_to_router_5_0_req = router_5_1_req_out[2]; - assign router_5_1_to_router_4_1_req = router_5_1_req_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_req = router_5_1_req_out[4]; - - assign router_5_1_rsp_in[0] = router_5_2_to_router_5_1_rsp; - assign router_5_1_rsp_in[1] = router_6_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[2] = router_5_0_to_router_5_1_rsp; - assign router_5_1_rsp_in[3] = router_4_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[4] = magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_1_req_in), - .floo_rsp_o (router_5_1_rsp_out), - .floo_req_o (router_5_1_req_out), - .floo_rsp_i (router_5_1_rsp_in) -); - - -floo_req_t [4:0] router_5_2_req_in; -floo_rsp_t [4:0] router_5_2_rsp_out; -floo_req_t [4:0] router_5_2_req_out; -floo_rsp_t [4:0] router_5_2_rsp_in; - - assign router_5_2_req_in[0] = router_5_3_to_router_5_2_req; - assign router_5_2_req_in[1] = router_6_2_to_router_5_2_req; - assign router_5_2_req_in[2] = router_5_1_to_router_5_2_req; - assign router_5_2_req_in[3] = router_4_2_to_router_5_2_req; - assign router_5_2_req_in[4] = magia_tile_ni_5_2_to_router_5_2_req; - - assign router_5_2_to_router_5_3_rsp = router_5_2_rsp_out[0]; - assign router_5_2_to_router_6_2_rsp = router_5_2_rsp_out[1]; - assign router_5_2_to_router_5_1_rsp = router_5_2_rsp_out[2]; - assign router_5_2_to_router_4_2_rsp = router_5_2_rsp_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_rsp = router_5_2_rsp_out[4]; - - assign router_5_2_to_router_5_3_req = router_5_2_req_out[0]; - assign router_5_2_to_router_6_2_req = router_5_2_req_out[1]; - assign router_5_2_to_router_5_1_req = router_5_2_req_out[2]; - assign router_5_2_to_router_4_2_req = router_5_2_req_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_req = router_5_2_req_out[4]; - - assign router_5_2_rsp_in[0] = router_5_3_to_router_5_2_rsp; - assign router_5_2_rsp_in[1] = router_6_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[2] = router_5_1_to_router_5_2_rsp; - assign router_5_2_rsp_in[3] = router_4_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[4] = magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_2_req_in), - .floo_rsp_o (router_5_2_rsp_out), - .floo_req_o (router_5_2_req_out), - .floo_rsp_i (router_5_2_rsp_in) -); - - -floo_req_t [4:0] router_5_3_req_in; -floo_rsp_t [4:0] router_5_3_rsp_out; -floo_req_t [4:0] router_5_3_req_out; -floo_rsp_t [4:0] router_5_3_rsp_in; - - assign router_5_3_req_in[0] = router_5_4_to_router_5_3_req; - assign router_5_3_req_in[1] = router_6_3_to_router_5_3_req; - assign router_5_3_req_in[2] = router_5_2_to_router_5_3_req; - assign router_5_3_req_in[3] = router_4_3_to_router_5_3_req; - assign router_5_3_req_in[4] = magia_tile_ni_5_3_to_router_5_3_req; - - assign router_5_3_to_router_5_4_rsp = router_5_3_rsp_out[0]; - assign router_5_3_to_router_6_3_rsp = router_5_3_rsp_out[1]; - assign router_5_3_to_router_5_2_rsp = router_5_3_rsp_out[2]; - assign router_5_3_to_router_4_3_rsp = router_5_3_rsp_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_rsp = router_5_3_rsp_out[4]; - - assign router_5_3_to_router_5_4_req = router_5_3_req_out[0]; - assign router_5_3_to_router_6_3_req = router_5_3_req_out[1]; - assign router_5_3_to_router_5_2_req = router_5_3_req_out[2]; - assign router_5_3_to_router_4_3_req = router_5_3_req_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_req = router_5_3_req_out[4]; - - assign router_5_3_rsp_in[0] = router_5_4_to_router_5_3_rsp; - assign router_5_3_rsp_in[1] = router_6_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[2] = router_5_2_to_router_5_3_rsp; - assign router_5_3_rsp_in[3] = router_4_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[4] = magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_3_req_in), - .floo_rsp_o (router_5_3_rsp_out), - .floo_req_o (router_5_3_req_out), - .floo_rsp_i (router_5_3_rsp_in) -); - - -floo_req_t [4:0] router_5_4_req_in; -floo_rsp_t [4:0] router_5_4_rsp_out; -floo_req_t [4:0] router_5_4_req_out; -floo_rsp_t [4:0] router_5_4_rsp_in; - - assign router_5_4_req_in[0] = router_5_5_to_router_5_4_req; - assign router_5_4_req_in[1] = router_6_4_to_router_5_4_req; - assign router_5_4_req_in[2] = router_5_3_to_router_5_4_req; - assign router_5_4_req_in[3] = router_4_4_to_router_5_4_req; - assign router_5_4_req_in[4] = magia_tile_ni_5_4_to_router_5_4_req; - - assign router_5_4_to_router_5_5_rsp = router_5_4_rsp_out[0]; - assign router_5_4_to_router_6_4_rsp = router_5_4_rsp_out[1]; - assign router_5_4_to_router_5_3_rsp = router_5_4_rsp_out[2]; - assign router_5_4_to_router_4_4_rsp = router_5_4_rsp_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_rsp = router_5_4_rsp_out[4]; - - assign router_5_4_to_router_5_5_req = router_5_4_req_out[0]; - assign router_5_4_to_router_6_4_req = router_5_4_req_out[1]; - assign router_5_4_to_router_5_3_req = router_5_4_req_out[2]; - assign router_5_4_to_router_4_4_req = router_5_4_req_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_req = router_5_4_req_out[4]; - - assign router_5_4_rsp_in[0] = router_5_5_to_router_5_4_rsp; - assign router_5_4_rsp_in[1] = router_6_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[2] = router_5_3_to_router_5_4_rsp; - assign router_5_4_rsp_in[3] = router_4_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[4] = magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_4_req_in), - .floo_rsp_o (router_5_4_rsp_out), - .floo_req_o (router_5_4_req_out), - .floo_rsp_i (router_5_4_rsp_in) -); - - -floo_req_t [4:0] router_5_5_req_in; -floo_rsp_t [4:0] router_5_5_rsp_out; -floo_req_t [4:0] router_5_5_req_out; -floo_rsp_t [4:0] router_5_5_rsp_in; - - assign router_5_5_req_in[0] = router_5_6_to_router_5_5_req; - assign router_5_5_req_in[1] = router_6_5_to_router_5_5_req; - assign router_5_5_req_in[2] = router_5_4_to_router_5_5_req; - assign router_5_5_req_in[3] = router_4_5_to_router_5_5_req; - assign router_5_5_req_in[4] = magia_tile_ni_5_5_to_router_5_5_req; - - assign router_5_5_to_router_5_6_rsp = router_5_5_rsp_out[0]; - assign router_5_5_to_router_6_5_rsp = router_5_5_rsp_out[1]; - assign router_5_5_to_router_5_4_rsp = router_5_5_rsp_out[2]; - assign router_5_5_to_router_4_5_rsp = router_5_5_rsp_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_rsp = router_5_5_rsp_out[4]; - - assign router_5_5_to_router_5_6_req = router_5_5_req_out[0]; - assign router_5_5_to_router_6_5_req = router_5_5_req_out[1]; - assign router_5_5_to_router_5_4_req = router_5_5_req_out[2]; - assign router_5_5_to_router_4_5_req = router_5_5_req_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_req = router_5_5_req_out[4]; - - assign router_5_5_rsp_in[0] = router_5_6_to_router_5_5_rsp; - assign router_5_5_rsp_in[1] = router_6_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[2] = router_5_4_to_router_5_5_rsp; - assign router_5_5_rsp_in[3] = router_4_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[4] = magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_5_req_in), - .floo_rsp_o (router_5_5_rsp_out), - .floo_req_o (router_5_5_req_out), - .floo_rsp_i (router_5_5_rsp_in) -); - - -floo_req_t [4:0] router_5_6_req_in; -floo_rsp_t [4:0] router_5_6_rsp_out; -floo_req_t [4:0] router_5_6_req_out; -floo_rsp_t [4:0] router_5_6_rsp_in; - - assign router_5_6_req_in[0] = router_5_7_to_router_5_6_req; - assign router_5_6_req_in[1] = router_6_6_to_router_5_6_req; - assign router_5_6_req_in[2] = router_5_5_to_router_5_6_req; - assign router_5_6_req_in[3] = router_4_6_to_router_5_6_req; - assign router_5_6_req_in[4] = magia_tile_ni_5_6_to_router_5_6_req; - - assign router_5_6_to_router_5_7_rsp = router_5_6_rsp_out[0]; - assign router_5_6_to_router_6_6_rsp = router_5_6_rsp_out[1]; - assign router_5_6_to_router_5_5_rsp = router_5_6_rsp_out[2]; - assign router_5_6_to_router_4_6_rsp = router_5_6_rsp_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_rsp = router_5_6_rsp_out[4]; - - assign router_5_6_to_router_5_7_req = router_5_6_req_out[0]; - assign router_5_6_to_router_6_6_req = router_5_6_req_out[1]; - assign router_5_6_to_router_5_5_req = router_5_6_req_out[2]; - assign router_5_6_to_router_4_6_req = router_5_6_req_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_req = router_5_6_req_out[4]; - - assign router_5_6_rsp_in[0] = router_5_7_to_router_5_6_rsp; - assign router_5_6_rsp_in[1] = router_6_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[2] = router_5_5_to_router_5_6_rsp; - assign router_5_6_rsp_in[3] = router_4_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[4] = magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_6_req_in), - .floo_rsp_o (router_5_6_rsp_out), - .floo_req_o (router_5_6_req_out), - .floo_rsp_i (router_5_6_rsp_in) -); - - -floo_req_t [4:0] router_5_7_req_in; -floo_rsp_t [4:0] router_5_7_rsp_out; -floo_req_t [4:0] router_5_7_req_out; -floo_rsp_t [4:0] router_5_7_rsp_in; - - assign router_5_7_req_in[0] = router_5_8_to_router_5_7_req; - assign router_5_7_req_in[1] = router_6_7_to_router_5_7_req; - assign router_5_7_req_in[2] = router_5_6_to_router_5_7_req; - assign router_5_7_req_in[3] = router_4_7_to_router_5_7_req; - assign router_5_7_req_in[4] = magia_tile_ni_5_7_to_router_5_7_req; - - assign router_5_7_to_router_5_8_rsp = router_5_7_rsp_out[0]; - assign router_5_7_to_router_6_7_rsp = router_5_7_rsp_out[1]; - assign router_5_7_to_router_5_6_rsp = router_5_7_rsp_out[2]; - assign router_5_7_to_router_4_7_rsp = router_5_7_rsp_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_rsp = router_5_7_rsp_out[4]; - - assign router_5_7_to_router_5_8_req = router_5_7_req_out[0]; - assign router_5_7_to_router_6_7_req = router_5_7_req_out[1]; - assign router_5_7_to_router_5_6_req = router_5_7_req_out[2]; - assign router_5_7_to_router_4_7_req = router_5_7_req_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_req = router_5_7_req_out[4]; - - assign router_5_7_rsp_in[0] = router_5_8_to_router_5_7_rsp; - assign router_5_7_rsp_in[1] = router_6_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[2] = router_5_6_to_router_5_7_rsp; - assign router_5_7_rsp_in[3] = router_4_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[4] = magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_7_req_in), - .floo_rsp_o (router_5_7_rsp_out), - .floo_req_o (router_5_7_req_out), - .floo_rsp_i (router_5_7_rsp_in) -); - - -floo_req_t [4:0] router_5_8_req_in; -floo_rsp_t [4:0] router_5_8_rsp_out; -floo_req_t [4:0] router_5_8_req_out; -floo_rsp_t [4:0] router_5_8_rsp_in; - - assign router_5_8_req_in[0] = router_5_9_to_router_5_8_req; - assign router_5_8_req_in[1] = router_6_8_to_router_5_8_req; - assign router_5_8_req_in[2] = router_5_7_to_router_5_8_req; - assign router_5_8_req_in[3] = router_4_8_to_router_5_8_req; - assign router_5_8_req_in[4] = magia_tile_ni_5_8_to_router_5_8_req; - - assign router_5_8_to_router_5_9_rsp = router_5_8_rsp_out[0]; - assign router_5_8_to_router_6_8_rsp = router_5_8_rsp_out[1]; - assign router_5_8_to_router_5_7_rsp = router_5_8_rsp_out[2]; - assign router_5_8_to_router_4_8_rsp = router_5_8_rsp_out[3]; - assign router_5_8_to_magia_tile_ni_5_8_rsp = router_5_8_rsp_out[4]; - - assign router_5_8_to_router_5_9_req = router_5_8_req_out[0]; - assign router_5_8_to_router_6_8_req = router_5_8_req_out[1]; - assign router_5_8_to_router_5_7_req = router_5_8_req_out[2]; - assign router_5_8_to_router_4_8_req = router_5_8_req_out[3]; - assign router_5_8_to_magia_tile_ni_5_8_req = router_5_8_req_out[4]; - - assign router_5_8_rsp_in[0] = router_5_9_to_router_5_8_rsp; - assign router_5_8_rsp_in[1] = router_6_8_to_router_5_8_rsp; - assign router_5_8_rsp_in[2] = router_5_7_to_router_5_8_rsp; - assign router_5_8_rsp_in[3] = router_4_8_to_router_5_8_rsp; - assign router_5_8_rsp_in[4] = magia_tile_ni_5_8_to_router_5_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_8_req_in), - .floo_rsp_o (router_5_8_rsp_out), - .floo_req_o (router_5_8_req_out), - .floo_rsp_i (router_5_8_rsp_in) -); - - -floo_req_t [4:0] router_5_9_req_in; -floo_rsp_t [4:0] router_5_9_rsp_out; -floo_req_t [4:0] router_5_9_req_out; -floo_rsp_t [4:0] router_5_9_rsp_in; - - assign router_5_9_req_in[0] = router_5_10_to_router_5_9_req; - assign router_5_9_req_in[1] = router_6_9_to_router_5_9_req; - assign router_5_9_req_in[2] = router_5_8_to_router_5_9_req; - assign router_5_9_req_in[3] = router_4_9_to_router_5_9_req; - assign router_5_9_req_in[4] = magia_tile_ni_5_9_to_router_5_9_req; - - assign router_5_9_to_router_5_10_rsp = router_5_9_rsp_out[0]; - assign router_5_9_to_router_6_9_rsp = router_5_9_rsp_out[1]; - assign router_5_9_to_router_5_8_rsp = router_5_9_rsp_out[2]; - assign router_5_9_to_router_4_9_rsp = router_5_9_rsp_out[3]; - assign router_5_9_to_magia_tile_ni_5_9_rsp = router_5_9_rsp_out[4]; - - assign router_5_9_to_router_5_10_req = router_5_9_req_out[0]; - assign router_5_9_to_router_6_9_req = router_5_9_req_out[1]; - assign router_5_9_to_router_5_8_req = router_5_9_req_out[2]; - assign router_5_9_to_router_4_9_req = router_5_9_req_out[3]; - assign router_5_9_to_magia_tile_ni_5_9_req = router_5_9_req_out[4]; - - assign router_5_9_rsp_in[0] = router_5_10_to_router_5_9_rsp; - assign router_5_9_rsp_in[1] = router_6_9_to_router_5_9_rsp; - assign router_5_9_rsp_in[2] = router_5_8_to_router_5_9_rsp; - assign router_5_9_rsp_in[3] = router_4_9_to_router_5_9_rsp; - assign router_5_9_rsp_in[4] = magia_tile_ni_5_9_to_router_5_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_9_req_in), - .floo_rsp_o (router_5_9_rsp_out), - .floo_req_o (router_5_9_req_out), - .floo_rsp_i (router_5_9_rsp_in) -); - - -floo_req_t [4:0] router_5_10_req_in; -floo_rsp_t [4:0] router_5_10_rsp_out; -floo_req_t [4:0] router_5_10_req_out; -floo_rsp_t [4:0] router_5_10_rsp_in; - - assign router_5_10_req_in[0] = router_5_11_to_router_5_10_req; - assign router_5_10_req_in[1] = router_6_10_to_router_5_10_req; - assign router_5_10_req_in[2] = router_5_9_to_router_5_10_req; - assign router_5_10_req_in[3] = router_4_10_to_router_5_10_req; - assign router_5_10_req_in[4] = magia_tile_ni_5_10_to_router_5_10_req; - - assign router_5_10_to_router_5_11_rsp = router_5_10_rsp_out[0]; - assign router_5_10_to_router_6_10_rsp = router_5_10_rsp_out[1]; - assign router_5_10_to_router_5_9_rsp = router_5_10_rsp_out[2]; - assign router_5_10_to_router_4_10_rsp = router_5_10_rsp_out[3]; - assign router_5_10_to_magia_tile_ni_5_10_rsp = router_5_10_rsp_out[4]; - - assign router_5_10_to_router_5_11_req = router_5_10_req_out[0]; - assign router_5_10_to_router_6_10_req = router_5_10_req_out[1]; - assign router_5_10_to_router_5_9_req = router_5_10_req_out[2]; - assign router_5_10_to_router_4_10_req = router_5_10_req_out[3]; - assign router_5_10_to_magia_tile_ni_5_10_req = router_5_10_req_out[4]; - - assign router_5_10_rsp_in[0] = router_5_11_to_router_5_10_rsp; - assign router_5_10_rsp_in[1] = router_6_10_to_router_5_10_rsp; - assign router_5_10_rsp_in[2] = router_5_9_to_router_5_10_rsp; - assign router_5_10_rsp_in[3] = router_4_10_to_router_5_10_rsp; - assign router_5_10_rsp_in[4] = magia_tile_ni_5_10_to_router_5_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_10_req_in), - .floo_rsp_o (router_5_10_rsp_out), - .floo_req_o (router_5_10_req_out), - .floo_rsp_i (router_5_10_rsp_in) -); - - -floo_req_t [4:0] router_5_11_req_in; -floo_rsp_t [4:0] router_5_11_rsp_out; -floo_req_t [4:0] router_5_11_req_out; -floo_rsp_t [4:0] router_5_11_rsp_in; - - assign router_5_11_req_in[0] = router_5_12_to_router_5_11_req; - assign router_5_11_req_in[1] = router_6_11_to_router_5_11_req; - assign router_5_11_req_in[2] = router_5_10_to_router_5_11_req; - assign router_5_11_req_in[3] = router_4_11_to_router_5_11_req; - assign router_5_11_req_in[4] = magia_tile_ni_5_11_to_router_5_11_req; - - assign router_5_11_to_router_5_12_rsp = router_5_11_rsp_out[0]; - assign router_5_11_to_router_6_11_rsp = router_5_11_rsp_out[1]; - assign router_5_11_to_router_5_10_rsp = router_5_11_rsp_out[2]; - assign router_5_11_to_router_4_11_rsp = router_5_11_rsp_out[3]; - assign router_5_11_to_magia_tile_ni_5_11_rsp = router_5_11_rsp_out[4]; - - assign router_5_11_to_router_5_12_req = router_5_11_req_out[0]; - assign router_5_11_to_router_6_11_req = router_5_11_req_out[1]; - assign router_5_11_to_router_5_10_req = router_5_11_req_out[2]; - assign router_5_11_to_router_4_11_req = router_5_11_req_out[3]; - assign router_5_11_to_magia_tile_ni_5_11_req = router_5_11_req_out[4]; - - assign router_5_11_rsp_in[0] = router_5_12_to_router_5_11_rsp; - assign router_5_11_rsp_in[1] = router_6_11_to_router_5_11_rsp; - assign router_5_11_rsp_in[2] = router_5_10_to_router_5_11_rsp; - assign router_5_11_rsp_in[3] = router_4_11_to_router_5_11_rsp; - assign router_5_11_rsp_in[4] = magia_tile_ni_5_11_to_router_5_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_11_req_in), - .floo_rsp_o (router_5_11_rsp_out), - .floo_req_o (router_5_11_req_out), - .floo_rsp_i (router_5_11_rsp_in) -); - - -floo_req_t [4:0] router_5_12_req_in; -floo_rsp_t [4:0] router_5_12_rsp_out; -floo_req_t [4:0] router_5_12_req_out; -floo_rsp_t [4:0] router_5_12_rsp_in; - - assign router_5_12_req_in[0] = router_5_13_to_router_5_12_req; - assign router_5_12_req_in[1] = router_6_12_to_router_5_12_req; - assign router_5_12_req_in[2] = router_5_11_to_router_5_12_req; - assign router_5_12_req_in[3] = router_4_12_to_router_5_12_req; - assign router_5_12_req_in[4] = magia_tile_ni_5_12_to_router_5_12_req; - - assign router_5_12_to_router_5_13_rsp = router_5_12_rsp_out[0]; - assign router_5_12_to_router_6_12_rsp = router_5_12_rsp_out[1]; - assign router_5_12_to_router_5_11_rsp = router_5_12_rsp_out[2]; - assign router_5_12_to_router_4_12_rsp = router_5_12_rsp_out[3]; - assign router_5_12_to_magia_tile_ni_5_12_rsp = router_5_12_rsp_out[4]; - - assign router_5_12_to_router_5_13_req = router_5_12_req_out[0]; - assign router_5_12_to_router_6_12_req = router_5_12_req_out[1]; - assign router_5_12_to_router_5_11_req = router_5_12_req_out[2]; - assign router_5_12_to_router_4_12_req = router_5_12_req_out[3]; - assign router_5_12_to_magia_tile_ni_5_12_req = router_5_12_req_out[4]; - - assign router_5_12_rsp_in[0] = router_5_13_to_router_5_12_rsp; - assign router_5_12_rsp_in[1] = router_6_12_to_router_5_12_rsp; - assign router_5_12_rsp_in[2] = router_5_11_to_router_5_12_rsp; - assign router_5_12_rsp_in[3] = router_4_12_to_router_5_12_rsp; - assign router_5_12_rsp_in[4] = magia_tile_ni_5_12_to_router_5_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_12_req_in), - .floo_rsp_o (router_5_12_rsp_out), - .floo_req_o (router_5_12_req_out), - .floo_rsp_i (router_5_12_rsp_in) -); - - -floo_req_t [4:0] router_5_13_req_in; -floo_rsp_t [4:0] router_5_13_rsp_out; -floo_req_t [4:0] router_5_13_req_out; -floo_rsp_t [4:0] router_5_13_rsp_in; - - assign router_5_13_req_in[0] = router_5_14_to_router_5_13_req; - assign router_5_13_req_in[1] = router_6_13_to_router_5_13_req; - assign router_5_13_req_in[2] = router_5_12_to_router_5_13_req; - assign router_5_13_req_in[3] = router_4_13_to_router_5_13_req; - assign router_5_13_req_in[4] = magia_tile_ni_5_13_to_router_5_13_req; - - assign router_5_13_to_router_5_14_rsp = router_5_13_rsp_out[0]; - assign router_5_13_to_router_6_13_rsp = router_5_13_rsp_out[1]; - assign router_5_13_to_router_5_12_rsp = router_5_13_rsp_out[2]; - assign router_5_13_to_router_4_13_rsp = router_5_13_rsp_out[3]; - assign router_5_13_to_magia_tile_ni_5_13_rsp = router_5_13_rsp_out[4]; - - assign router_5_13_to_router_5_14_req = router_5_13_req_out[0]; - assign router_5_13_to_router_6_13_req = router_5_13_req_out[1]; - assign router_5_13_to_router_5_12_req = router_5_13_req_out[2]; - assign router_5_13_to_router_4_13_req = router_5_13_req_out[3]; - assign router_5_13_to_magia_tile_ni_5_13_req = router_5_13_req_out[4]; - - assign router_5_13_rsp_in[0] = router_5_14_to_router_5_13_rsp; - assign router_5_13_rsp_in[1] = router_6_13_to_router_5_13_rsp; - assign router_5_13_rsp_in[2] = router_5_12_to_router_5_13_rsp; - assign router_5_13_rsp_in[3] = router_4_13_to_router_5_13_rsp; - assign router_5_13_rsp_in[4] = magia_tile_ni_5_13_to_router_5_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_13_req_in), - .floo_rsp_o (router_5_13_rsp_out), - .floo_req_o (router_5_13_req_out), - .floo_rsp_i (router_5_13_rsp_in) -); - - -floo_req_t [4:0] router_5_14_req_in; -floo_rsp_t [4:0] router_5_14_rsp_out; -floo_req_t [4:0] router_5_14_req_out; -floo_rsp_t [4:0] router_5_14_rsp_in; - - assign router_5_14_req_in[0] = router_5_15_to_router_5_14_req; - assign router_5_14_req_in[1] = router_6_14_to_router_5_14_req; - assign router_5_14_req_in[2] = router_5_13_to_router_5_14_req; - assign router_5_14_req_in[3] = router_4_14_to_router_5_14_req; - assign router_5_14_req_in[4] = magia_tile_ni_5_14_to_router_5_14_req; - - assign router_5_14_to_router_5_15_rsp = router_5_14_rsp_out[0]; - assign router_5_14_to_router_6_14_rsp = router_5_14_rsp_out[1]; - assign router_5_14_to_router_5_13_rsp = router_5_14_rsp_out[2]; - assign router_5_14_to_router_4_14_rsp = router_5_14_rsp_out[3]; - assign router_5_14_to_magia_tile_ni_5_14_rsp = router_5_14_rsp_out[4]; - - assign router_5_14_to_router_5_15_req = router_5_14_req_out[0]; - assign router_5_14_to_router_6_14_req = router_5_14_req_out[1]; - assign router_5_14_to_router_5_13_req = router_5_14_req_out[2]; - assign router_5_14_to_router_4_14_req = router_5_14_req_out[3]; - assign router_5_14_to_magia_tile_ni_5_14_req = router_5_14_req_out[4]; - - assign router_5_14_rsp_in[0] = router_5_15_to_router_5_14_rsp; - assign router_5_14_rsp_in[1] = router_6_14_to_router_5_14_rsp; - assign router_5_14_rsp_in[2] = router_5_13_to_router_5_14_rsp; - assign router_5_14_rsp_in[3] = router_4_14_to_router_5_14_rsp; - assign router_5_14_rsp_in[4] = magia_tile_ni_5_14_to_router_5_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_14_req_in), - .floo_rsp_o (router_5_14_rsp_out), - .floo_req_o (router_5_14_req_out), - .floo_rsp_i (router_5_14_rsp_in) -); - - -floo_req_t [4:0] router_5_15_req_in; -floo_rsp_t [4:0] router_5_15_rsp_out; -floo_req_t [4:0] router_5_15_req_out; -floo_rsp_t [4:0] router_5_15_rsp_in; - - assign router_5_15_req_in[0] = router_5_16_to_router_5_15_req; - assign router_5_15_req_in[1] = router_6_15_to_router_5_15_req; - assign router_5_15_req_in[2] = router_5_14_to_router_5_15_req; - assign router_5_15_req_in[3] = router_4_15_to_router_5_15_req; - assign router_5_15_req_in[4] = magia_tile_ni_5_15_to_router_5_15_req; - - assign router_5_15_to_router_5_16_rsp = router_5_15_rsp_out[0]; - assign router_5_15_to_router_6_15_rsp = router_5_15_rsp_out[1]; - assign router_5_15_to_router_5_14_rsp = router_5_15_rsp_out[2]; - assign router_5_15_to_router_4_15_rsp = router_5_15_rsp_out[3]; - assign router_5_15_to_magia_tile_ni_5_15_rsp = router_5_15_rsp_out[4]; - - assign router_5_15_to_router_5_16_req = router_5_15_req_out[0]; - assign router_5_15_to_router_6_15_req = router_5_15_req_out[1]; - assign router_5_15_to_router_5_14_req = router_5_15_req_out[2]; - assign router_5_15_to_router_4_15_req = router_5_15_req_out[3]; - assign router_5_15_to_magia_tile_ni_5_15_req = router_5_15_req_out[4]; - - assign router_5_15_rsp_in[0] = router_5_16_to_router_5_15_rsp; - assign router_5_15_rsp_in[1] = router_6_15_to_router_5_15_rsp; - assign router_5_15_rsp_in[2] = router_5_14_to_router_5_15_rsp; - assign router_5_15_rsp_in[3] = router_4_15_to_router_5_15_rsp; - assign router_5_15_rsp_in[4] = magia_tile_ni_5_15_to_router_5_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_15_req_in), - .floo_rsp_o (router_5_15_rsp_out), - .floo_req_o (router_5_15_req_out), - .floo_rsp_i (router_5_15_rsp_in) -); - - -floo_req_t [4:0] router_5_16_req_in; -floo_rsp_t [4:0] router_5_16_rsp_out; -floo_req_t [4:0] router_5_16_req_out; -floo_rsp_t [4:0] router_5_16_rsp_in; - - assign router_5_16_req_in[0] = router_5_17_to_router_5_16_req; - assign router_5_16_req_in[1] = router_6_16_to_router_5_16_req; - assign router_5_16_req_in[2] = router_5_15_to_router_5_16_req; - assign router_5_16_req_in[3] = router_4_16_to_router_5_16_req; - assign router_5_16_req_in[4] = magia_tile_ni_5_16_to_router_5_16_req; - - assign router_5_16_to_router_5_17_rsp = router_5_16_rsp_out[0]; - assign router_5_16_to_router_6_16_rsp = router_5_16_rsp_out[1]; - assign router_5_16_to_router_5_15_rsp = router_5_16_rsp_out[2]; - assign router_5_16_to_router_4_16_rsp = router_5_16_rsp_out[3]; - assign router_5_16_to_magia_tile_ni_5_16_rsp = router_5_16_rsp_out[4]; - - assign router_5_16_to_router_5_17_req = router_5_16_req_out[0]; - assign router_5_16_to_router_6_16_req = router_5_16_req_out[1]; - assign router_5_16_to_router_5_15_req = router_5_16_req_out[2]; - assign router_5_16_to_router_4_16_req = router_5_16_req_out[3]; - assign router_5_16_to_magia_tile_ni_5_16_req = router_5_16_req_out[4]; - - assign router_5_16_rsp_in[0] = router_5_17_to_router_5_16_rsp; - assign router_5_16_rsp_in[1] = router_6_16_to_router_5_16_rsp; - assign router_5_16_rsp_in[2] = router_5_15_to_router_5_16_rsp; - assign router_5_16_rsp_in[3] = router_4_16_to_router_5_16_rsp; - assign router_5_16_rsp_in[4] = magia_tile_ni_5_16_to_router_5_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_16_req_in), - .floo_rsp_o (router_5_16_rsp_out), - .floo_req_o (router_5_16_req_out), - .floo_rsp_i (router_5_16_rsp_in) -); - - -floo_req_t [4:0] router_5_17_req_in; -floo_rsp_t [4:0] router_5_17_rsp_out; -floo_req_t [4:0] router_5_17_req_out; -floo_rsp_t [4:0] router_5_17_rsp_in; - - assign router_5_17_req_in[0] = router_5_18_to_router_5_17_req; - assign router_5_17_req_in[1] = router_6_17_to_router_5_17_req; - assign router_5_17_req_in[2] = router_5_16_to_router_5_17_req; - assign router_5_17_req_in[3] = router_4_17_to_router_5_17_req; - assign router_5_17_req_in[4] = magia_tile_ni_5_17_to_router_5_17_req; - - assign router_5_17_to_router_5_18_rsp = router_5_17_rsp_out[0]; - assign router_5_17_to_router_6_17_rsp = router_5_17_rsp_out[1]; - assign router_5_17_to_router_5_16_rsp = router_5_17_rsp_out[2]; - assign router_5_17_to_router_4_17_rsp = router_5_17_rsp_out[3]; - assign router_5_17_to_magia_tile_ni_5_17_rsp = router_5_17_rsp_out[4]; - - assign router_5_17_to_router_5_18_req = router_5_17_req_out[0]; - assign router_5_17_to_router_6_17_req = router_5_17_req_out[1]; - assign router_5_17_to_router_5_16_req = router_5_17_req_out[2]; - assign router_5_17_to_router_4_17_req = router_5_17_req_out[3]; - assign router_5_17_to_magia_tile_ni_5_17_req = router_5_17_req_out[4]; - - assign router_5_17_rsp_in[0] = router_5_18_to_router_5_17_rsp; - assign router_5_17_rsp_in[1] = router_6_17_to_router_5_17_rsp; - assign router_5_17_rsp_in[2] = router_5_16_to_router_5_17_rsp; - assign router_5_17_rsp_in[3] = router_4_17_to_router_5_17_rsp; - assign router_5_17_rsp_in[4] = magia_tile_ni_5_17_to_router_5_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_17_req_in), - .floo_rsp_o (router_5_17_rsp_out), - .floo_req_o (router_5_17_req_out), - .floo_rsp_i (router_5_17_rsp_in) -); - - -floo_req_t [4:0] router_5_18_req_in; -floo_rsp_t [4:0] router_5_18_rsp_out; -floo_req_t [4:0] router_5_18_req_out; -floo_rsp_t [4:0] router_5_18_rsp_in; - - assign router_5_18_req_in[0] = router_5_19_to_router_5_18_req; - assign router_5_18_req_in[1] = router_6_18_to_router_5_18_req; - assign router_5_18_req_in[2] = router_5_17_to_router_5_18_req; - assign router_5_18_req_in[3] = router_4_18_to_router_5_18_req; - assign router_5_18_req_in[4] = magia_tile_ni_5_18_to_router_5_18_req; - - assign router_5_18_to_router_5_19_rsp = router_5_18_rsp_out[0]; - assign router_5_18_to_router_6_18_rsp = router_5_18_rsp_out[1]; - assign router_5_18_to_router_5_17_rsp = router_5_18_rsp_out[2]; - assign router_5_18_to_router_4_18_rsp = router_5_18_rsp_out[3]; - assign router_5_18_to_magia_tile_ni_5_18_rsp = router_5_18_rsp_out[4]; - - assign router_5_18_to_router_5_19_req = router_5_18_req_out[0]; - assign router_5_18_to_router_6_18_req = router_5_18_req_out[1]; - assign router_5_18_to_router_5_17_req = router_5_18_req_out[2]; - assign router_5_18_to_router_4_18_req = router_5_18_req_out[3]; - assign router_5_18_to_magia_tile_ni_5_18_req = router_5_18_req_out[4]; - - assign router_5_18_rsp_in[0] = router_5_19_to_router_5_18_rsp; - assign router_5_18_rsp_in[1] = router_6_18_to_router_5_18_rsp; - assign router_5_18_rsp_in[2] = router_5_17_to_router_5_18_rsp; - assign router_5_18_rsp_in[3] = router_4_18_to_router_5_18_rsp; - assign router_5_18_rsp_in[4] = magia_tile_ni_5_18_to_router_5_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_18_req_in), - .floo_rsp_o (router_5_18_rsp_out), - .floo_req_o (router_5_18_req_out), - .floo_rsp_i (router_5_18_rsp_in) -); - - -floo_req_t [4:0] router_5_19_req_in; -floo_rsp_t [4:0] router_5_19_rsp_out; -floo_req_t [4:0] router_5_19_req_out; -floo_rsp_t [4:0] router_5_19_rsp_in; - - assign router_5_19_req_in[0] = router_5_20_to_router_5_19_req; - assign router_5_19_req_in[1] = router_6_19_to_router_5_19_req; - assign router_5_19_req_in[2] = router_5_18_to_router_5_19_req; - assign router_5_19_req_in[3] = router_4_19_to_router_5_19_req; - assign router_5_19_req_in[4] = magia_tile_ni_5_19_to_router_5_19_req; - - assign router_5_19_to_router_5_20_rsp = router_5_19_rsp_out[0]; - assign router_5_19_to_router_6_19_rsp = router_5_19_rsp_out[1]; - assign router_5_19_to_router_5_18_rsp = router_5_19_rsp_out[2]; - assign router_5_19_to_router_4_19_rsp = router_5_19_rsp_out[3]; - assign router_5_19_to_magia_tile_ni_5_19_rsp = router_5_19_rsp_out[4]; - - assign router_5_19_to_router_5_20_req = router_5_19_req_out[0]; - assign router_5_19_to_router_6_19_req = router_5_19_req_out[1]; - assign router_5_19_to_router_5_18_req = router_5_19_req_out[2]; - assign router_5_19_to_router_4_19_req = router_5_19_req_out[3]; - assign router_5_19_to_magia_tile_ni_5_19_req = router_5_19_req_out[4]; - - assign router_5_19_rsp_in[0] = router_5_20_to_router_5_19_rsp; - assign router_5_19_rsp_in[1] = router_6_19_to_router_5_19_rsp; - assign router_5_19_rsp_in[2] = router_5_18_to_router_5_19_rsp; - assign router_5_19_rsp_in[3] = router_4_19_to_router_5_19_rsp; - assign router_5_19_rsp_in[4] = magia_tile_ni_5_19_to_router_5_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_19_req_in), - .floo_rsp_o (router_5_19_rsp_out), - .floo_req_o (router_5_19_req_out), - .floo_rsp_i (router_5_19_rsp_in) -); - - -floo_req_t [4:0] router_5_20_req_in; -floo_rsp_t [4:0] router_5_20_rsp_out; -floo_req_t [4:0] router_5_20_req_out; -floo_rsp_t [4:0] router_5_20_rsp_in; - - assign router_5_20_req_in[0] = router_5_21_to_router_5_20_req; - assign router_5_20_req_in[1] = router_6_20_to_router_5_20_req; - assign router_5_20_req_in[2] = router_5_19_to_router_5_20_req; - assign router_5_20_req_in[3] = router_4_20_to_router_5_20_req; - assign router_5_20_req_in[4] = magia_tile_ni_5_20_to_router_5_20_req; - - assign router_5_20_to_router_5_21_rsp = router_5_20_rsp_out[0]; - assign router_5_20_to_router_6_20_rsp = router_5_20_rsp_out[1]; - assign router_5_20_to_router_5_19_rsp = router_5_20_rsp_out[2]; - assign router_5_20_to_router_4_20_rsp = router_5_20_rsp_out[3]; - assign router_5_20_to_magia_tile_ni_5_20_rsp = router_5_20_rsp_out[4]; - - assign router_5_20_to_router_5_21_req = router_5_20_req_out[0]; - assign router_5_20_to_router_6_20_req = router_5_20_req_out[1]; - assign router_5_20_to_router_5_19_req = router_5_20_req_out[2]; - assign router_5_20_to_router_4_20_req = router_5_20_req_out[3]; - assign router_5_20_to_magia_tile_ni_5_20_req = router_5_20_req_out[4]; - - assign router_5_20_rsp_in[0] = router_5_21_to_router_5_20_rsp; - assign router_5_20_rsp_in[1] = router_6_20_to_router_5_20_rsp; - assign router_5_20_rsp_in[2] = router_5_19_to_router_5_20_rsp; - assign router_5_20_rsp_in[3] = router_4_20_to_router_5_20_rsp; - assign router_5_20_rsp_in[4] = magia_tile_ni_5_20_to_router_5_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_20_req_in), - .floo_rsp_o (router_5_20_rsp_out), - .floo_req_o (router_5_20_req_out), - .floo_rsp_i (router_5_20_rsp_in) -); - - -floo_req_t [4:0] router_5_21_req_in; -floo_rsp_t [4:0] router_5_21_rsp_out; -floo_req_t [4:0] router_5_21_req_out; -floo_rsp_t [4:0] router_5_21_rsp_in; - - assign router_5_21_req_in[0] = router_5_22_to_router_5_21_req; - assign router_5_21_req_in[1] = router_6_21_to_router_5_21_req; - assign router_5_21_req_in[2] = router_5_20_to_router_5_21_req; - assign router_5_21_req_in[3] = router_4_21_to_router_5_21_req; - assign router_5_21_req_in[4] = magia_tile_ni_5_21_to_router_5_21_req; - - assign router_5_21_to_router_5_22_rsp = router_5_21_rsp_out[0]; - assign router_5_21_to_router_6_21_rsp = router_5_21_rsp_out[1]; - assign router_5_21_to_router_5_20_rsp = router_5_21_rsp_out[2]; - assign router_5_21_to_router_4_21_rsp = router_5_21_rsp_out[3]; - assign router_5_21_to_magia_tile_ni_5_21_rsp = router_5_21_rsp_out[4]; - - assign router_5_21_to_router_5_22_req = router_5_21_req_out[0]; - assign router_5_21_to_router_6_21_req = router_5_21_req_out[1]; - assign router_5_21_to_router_5_20_req = router_5_21_req_out[2]; - assign router_5_21_to_router_4_21_req = router_5_21_req_out[3]; - assign router_5_21_to_magia_tile_ni_5_21_req = router_5_21_req_out[4]; - - assign router_5_21_rsp_in[0] = router_5_22_to_router_5_21_rsp; - assign router_5_21_rsp_in[1] = router_6_21_to_router_5_21_rsp; - assign router_5_21_rsp_in[2] = router_5_20_to_router_5_21_rsp; - assign router_5_21_rsp_in[3] = router_4_21_to_router_5_21_rsp; - assign router_5_21_rsp_in[4] = magia_tile_ni_5_21_to_router_5_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_21_req_in), - .floo_rsp_o (router_5_21_rsp_out), - .floo_req_o (router_5_21_req_out), - .floo_rsp_i (router_5_21_rsp_in) -); - - -floo_req_t [4:0] router_5_22_req_in; -floo_rsp_t [4:0] router_5_22_rsp_out; -floo_req_t [4:0] router_5_22_req_out; -floo_rsp_t [4:0] router_5_22_rsp_in; - - assign router_5_22_req_in[0] = router_5_23_to_router_5_22_req; - assign router_5_22_req_in[1] = router_6_22_to_router_5_22_req; - assign router_5_22_req_in[2] = router_5_21_to_router_5_22_req; - assign router_5_22_req_in[3] = router_4_22_to_router_5_22_req; - assign router_5_22_req_in[4] = magia_tile_ni_5_22_to_router_5_22_req; - - assign router_5_22_to_router_5_23_rsp = router_5_22_rsp_out[0]; - assign router_5_22_to_router_6_22_rsp = router_5_22_rsp_out[1]; - assign router_5_22_to_router_5_21_rsp = router_5_22_rsp_out[2]; - assign router_5_22_to_router_4_22_rsp = router_5_22_rsp_out[3]; - assign router_5_22_to_magia_tile_ni_5_22_rsp = router_5_22_rsp_out[4]; - - assign router_5_22_to_router_5_23_req = router_5_22_req_out[0]; - assign router_5_22_to_router_6_22_req = router_5_22_req_out[1]; - assign router_5_22_to_router_5_21_req = router_5_22_req_out[2]; - assign router_5_22_to_router_4_22_req = router_5_22_req_out[3]; - assign router_5_22_to_magia_tile_ni_5_22_req = router_5_22_req_out[4]; - - assign router_5_22_rsp_in[0] = router_5_23_to_router_5_22_rsp; - assign router_5_22_rsp_in[1] = router_6_22_to_router_5_22_rsp; - assign router_5_22_rsp_in[2] = router_5_21_to_router_5_22_rsp; - assign router_5_22_rsp_in[3] = router_4_22_to_router_5_22_rsp; - assign router_5_22_rsp_in[4] = magia_tile_ni_5_22_to_router_5_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_22_req_in), - .floo_rsp_o (router_5_22_rsp_out), - .floo_req_o (router_5_22_req_out), - .floo_rsp_i (router_5_22_rsp_in) -); - - -floo_req_t [4:0] router_5_23_req_in; -floo_rsp_t [4:0] router_5_23_rsp_out; -floo_req_t [4:0] router_5_23_req_out; -floo_rsp_t [4:0] router_5_23_rsp_in; - - assign router_5_23_req_in[0] = router_5_24_to_router_5_23_req; - assign router_5_23_req_in[1] = router_6_23_to_router_5_23_req; - assign router_5_23_req_in[2] = router_5_22_to_router_5_23_req; - assign router_5_23_req_in[3] = router_4_23_to_router_5_23_req; - assign router_5_23_req_in[4] = magia_tile_ni_5_23_to_router_5_23_req; - - assign router_5_23_to_router_5_24_rsp = router_5_23_rsp_out[0]; - assign router_5_23_to_router_6_23_rsp = router_5_23_rsp_out[1]; - assign router_5_23_to_router_5_22_rsp = router_5_23_rsp_out[2]; - assign router_5_23_to_router_4_23_rsp = router_5_23_rsp_out[3]; - assign router_5_23_to_magia_tile_ni_5_23_rsp = router_5_23_rsp_out[4]; - - assign router_5_23_to_router_5_24_req = router_5_23_req_out[0]; - assign router_5_23_to_router_6_23_req = router_5_23_req_out[1]; - assign router_5_23_to_router_5_22_req = router_5_23_req_out[2]; - assign router_5_23_to_router_4_23_req = router_5_23_req_out[3]; - assign router_5_23_to_magia_tile_ni_5_23_req = router_5_23_req_out[4]; - - assign router_5_23_rsp_in[0] = router_5_24_to_router_5_23_rsp; - assign router_5_23_rsp_in[1] = router_6_23_to_router_5_23_rsp; - assign router_5_23_rsp_in[2] = router_5_22_to_router_5_23_rsp; - assign router_5_23_rsp_in[3] = router_4_23_to_router_5_23_rsp; - assign router_5_23_rsp_in[4] = magia_tile_ni_5_23_to_router_5_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_23_req_in), - .floo_rsp_o (router_5_23_rsp_out), - .floo_req_o (router_5_23_req_out), - .floo_rsp_i (router_5_23_rsp_in) -); - - -floo_req_t [4:0] router_5_24_req_in; -floo_rsp_t [4:0] router_5_24_rsp_out; -floo_req_t [4:0] router_5_24_req_out; -floo_rsp_t [4:0] router_5_24_rsp_in; - - assign router_5_24_req_in[0] = router_5_25_to_router_5_24_req; - assign router_5_24_req_in[1] = router_6_24_to_router_5_24_req; - assign router_5_24_req_in[2] = router_5_23_to_router_5_24_req; - assign router_5_24_req_in[3] = router_4_24_to_router_5_24_req; - assign router_5_24_req_in[4] = magia_tile_ni_5_24_to_router_5_24_req; - - assign router_5_24_to_router_5_25_rsp = router_5_24_rsp_out[0]; - assign router_5_24_to_router_6_24_rsp = router_5_24_rsp_out[1]; - assign router_5_24_to_router_5_23_rsp = router_5_24_rsp_out[2]; - assign router_5_24_to_router_4_24_rsp = router_5_24_rsp_out[3]; - assign router_5_24_to_magia_tile_ni_5_24_rsp = router_5_24_rsp_out[4]; - - assign router_5_24_to_router_5_25_req = router_5_24_req_out[0]; - assign router_5_24_to_router_6_24_req = router_5_24_req_out[1]; - assign router_5_24_to_router_5_23_req = router_5_24_req_out[2]; - assign router_5_24_to_router_4_24_req = router_5_24_req_out[3]; - assign router_5_24_to_magia_tile_ni_5_24_req = router_5_24_req_out[4]; - - assign router_5_24_rsp_in[0] = router_5_25_to_router_5_24_rsp; - assign router_5_24_rsp_in[1] = router_6_24_to_router_5_24_rsp; - assign router_5_24_rsp_in[2] = router_5_23_to_router_5_24_rsp; - assign router_5_24_rsp_in[3] = router_4_24_to_router_5_24_rsp; - assign router_5_24_rsp_in[4] = magia_tile_ni_5_24_to_router_5_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_24_req_in), - .floo_rsp_o (router_5_24_rsp_out), - .floo_req_o (router_5_24_req_out), - .floo_rsp_i (router_5_24_rsp_in) -); - - -floo_req_t [4:0] router_5_25_req_in; -floo_rsp_t [4:0] router_5_25_rsp_out; -floo_req_t [4:0] router_5_25_req_out; -floo_rsp_t [4:0] router_5_25_rsp_in; - - assign router_5_25_req_in[0] = router_5_26_to_router_5_25_req; - assign router_5_25_req_in[1] = router_6_25_to_router_5_25_req; - assign router_5_25_req_in[2] = router_5_24_to_router_5_25_req; - assign router_5_25_req_in[3] = router_4_25_to_router_5_25_req; - assign router_5_25_req_in[4] = magia_tile_ni_5_25_to_router_5_25_req; - - assign router_5_25_to_router_5_26_rsp = router_5_25_rsp_out[0]; - assign router_5_25_to_router_6_25_rsp = router_5_25_rsp_out[1]; - assign router_5_25_to_router_5_24_rsp = router_5_25_rsp_out[2]; - assign router_5_25_to_router_4_25_rsp = router_5_25_rsp_out[3]; - assign router_5_25_to_magia_tile_ni_5_25_rsp = router_5_25_rsp_out[4]; - - assign router_5_25_to_router_5_26_req = router_5_25_req_out[0]; - assign router_5_25_to_router_6_25_req = router_5_25_req_out[1]; - assign router_5_25_to_router_5_24_req = router_5_25_req_out[2]; - assign router_5_25_to_router_4_25_req = router_5_25_req_out[3]; - assign router_5_25_to_magia_tile_ni_5_25_req = router_5_25_req_out[4]; - - assign router_5_25_rsp_in[0] = router_5_26_to_router_5_25_rsp; - assign router_5_25_rsp_in[1] = router_6_25_to_router_5_25_rsp; - assign router_5_25_rsp_in[2] = router_5_24_to_router_5_25_rsp; - assign router_5_25_rsp_in[3] = router_4_25_to_router_5_25_rsp; - assign router_5_25_rsp_in[4] = magia_tile_ni_5_25_to_router_5_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_25_req_in), - .floo_rsp_o (router_5_25_rsp_out), - .floo_req_o (router_5_25_req_out), - .floo_rsp_i (router_5_25_rsp_in) -); - - -floo_req_t [4:0] router_5_26_req_in; -floo_rsp_t [4:0] router_5_26_rsp_out; -floo_req_t [4:0] router_5_26_req_out; -floo_rsp_t [4:0] router_5_26_rsp_in; - - assign router_5_26_req_in[0] = router_5_27_to_router_5_26_req; - assign router_5_26_req_in[1] = router_6_26_to_router_5_26_req; - assign router_5_26_req_in[2] = router_5_25_to_router_5_26_req; - assign router_5_26_req_in[3] = router_4_26_to_router_5_26_req; - assign router_5_26_req_in[4] = magia_tile_ni_5_26_to_router_5_26_req; - - assign router_5_26_to_router_5_27_rsp = router_5_26_rsp_out[0]; - assign router_5_26_to_router_6_26_rsp = router_5_26_rsp_out[1]; - assign router_5_26_to_router_5_25_rsp = router_5_26_rsp_out[2]; - assign router_5_26_to_router_4_26_rsp = router_5_26_rsp_out[3]; - assign router_5_26_to_magia_tile_ni_5_26_rsp = router_5_26_rsp_out[4]; - - assign router_5_26_to_router_5_27_req = router_5_26_req_out[0]; - assign router_5_26_to_router_6_26_req = router_5_26_req_out[1]; - assign router_5_26_to_router_5_25_req = router_5_26_req_out[2]; - assign router_5_26_to_router_4_26_req = router_5_26_req_out[3]; - assign router_5_26_to_magia_tile_ni_5_26_req = router_5_26_req_out[4]; - - assign router_5_26_rsp_in[0] = router_5_27_to_router_5_26_rsp; - assign router_5_26_rsp_in[1] = router_6_26_to_router_5_26_rsp; - assign router_5_26_rsp_in[2] = router_5_25_to_router_5_26_rsp; - assign router_5_26_rsp_in[3] = router_4_26_to_router_5_26_rsp; - assign router_5_26_rsp_in[4] = magia_tile_ni_5_26_to_router_5_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_26_req_in), - .floo_rsp_o (router_5_26_rsp_out), - .floo_req_o (router_5_26_req_out), - .floo_rsp_i (router_5_26_rsp_in) -); - - -floo_req_t [4:0] router_5_27_req_in; -floo_rsp_t [4:0] router_5_27_rsp_out; -floo_req_t [4:0] router_5_27_req_out; -floo_rsp_t [4:0] router_5_27_rsp_in; - - assign router_5_27_req_in[0] = router_5_28_to_router_5_27_req; - assign router_5_27_req_in[1] = router_6_27_to_router_5_27_req; - assign router_5_27_req_in[2] = router_5_26_to_router_5_27_req; - assign router_5_27_req_in[3] = router_4_27_to_router_5_27_req; - assign router_5_27_req_in[4] = magia_tile_ni_5_27_to_router_5_27_req; - - assign router_5_27_to_router_5_28_rsp = router_5_27_rsp_out[0]; - assign router_5_27_to_router_6_27_rsp = router_5_27_rsp_out[1]; - assign router_5_27_to_router_5_26_rsp = router_5_27_rsp_out[2]; - assign router_5_27_to_router_4_27_rsp = router_5_27_rsp_out[3]; - assign router_5_27_to_magia_tile_ni_5_27_rsp = router_5_27_rsp_out[4]; - - assign router_5_27_to_router_5_28_req = router_5_27_req_out[0]; - assign router_5_27_to_router_6_27_req = router_5_27_req_out[1]; - assign router_5_27_to_router_5_26_req = router_5_27_req_out[2]; - assign router_5_27_to_router_4_27_req = router_5_27_req_out[3]; - assign router_5_27_to_magia_tile_ni_5_27_req = router_5_27_req_out[4]; - - assign router_5_27_rsp_in[0] = router_5_28_to_router_5_27_rsp; - assign router_5_27_rsp_in[1] = router_6_27_to_router_5_27_rsp; - assign router_5_27_rsp_in[2] = router_5_26_to_router_5_27_rsp; - assign router_5_27_rsp_in[3] = router_4_27_to_router_5_27_rsp; - assign router_5_27_rsp_in[4] = magia_tile_ni_5_27_to_router_5_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_27_req_in), - .floo_rsp_o (router_5_27_rsp_out), - .floo_req_o (router_5_27_req_out), - .floo_rsp_i (router_5_27_rsp_in) -); - - -floo_req_t [4:0] router_5_28_req_in; -floo_rsp_t [4:0] router_5_28_rsp_out; -floo_req_t [4:0] router_5_28_req_out; -floo_rsp_t [4:0] router_5_28_rsp_in; - - assign router_5_28_req_in[0] = router_5_29_to_router_5_28_req; - assign router_5_28_req_in[1] = router_6_28_to_router_5_28_req; - assign router_5_28_req_in[2] = router_5_27_to_router_5_28_req; - assign router_5_28_req_in[3] = router_4_28_to_router_5_28_req; - assign router_5_28_req_in[4] = magia_tile_ni_5_28_to_router_5_28_req; - - assign router_5_28_to_router_5_29_rsp = router_5_28_rsp_out[0]; - assign router_5_28_to_router_6_28_rsp = router_5_28_rsp_out[1]; - assign router_5_28_to_router_5_27_rsp = router_5_28_rsp_out[2]; - assign router_5_28_to_router_4_28_rsp = router_5_28_rsp_out[3]; - assign router_5_28_to_magia_tile_ni_5_28_rsp = router_5_28_rsp_out[4]; - - assign router_5_28_to_router_5_29_req = router_5_28_req_out[0]; - assign router_5_28_to_router_6_28_req = router_5_28_req_out[1]; - assign router_5_28_to_router_5_27_req = router_5_28_req_out[2]; - assign router_5_28_to_router_4_28_req = router_5_28_req_out[3]; - assign router_5_28_to_magia_tile_ni_5_28_req = router_5_28_req_out[4]; - - assign router_5_28_rsp_in[0] = router_5_29_to_router_5_28_rsp; - assign router_5_28_rsp_in[1] = router_6_28_to_router_5_28_rsp; - assign router_5_28_rsp_in[2] = router_5_27_to_router_5_28_rsp; - assign router_5_28_rsp_in[3] = router_4_28_to_router_5_28_rsp; - assign router_5_28_rsp_in[4] = magia_tile_ni_5_28_to_router_5_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_28_req_in), - .floo_rsp_o (router_5_28_rsp_out), - .floo_req_o (router_5_28_req_out), - .floo_rsp_i (router_5_28_rsp_in) -); - - -floo_req_t [4:0] router_5_29_req_in; -floo_rsp_t [4:0] router_5_29_rsp_out; -floo_req_t [4:0] router_5_29_req_out; -floo_rsp_t [4:0] router_5_29_rsp_in; - - assign router_5_29_req_in[0] = router_5_30_to_router_5_29_req; - assign router_5_29_req_in[1] = router_6_29_to_router_5_29_req; - assign router_5_29_req_in[2] = router_5_28_to_router_5_29_req; - assign router_5_29_req_in[3] = router_4_29_to_router_5_29_req; - assign router_5_29_req_in[4] = magia_tile_ni_5_29_to_router_5_29_req; - - assign router_5_29_to_router_5_30_rsp = router_5_29_rsp_out[0]; - assign router_5_29_to_router_6_29_rsp = router_5_29_rsp_out[1]; - assign router_5_29_to_router_5_28_rsp = router_5_29_rsp_out[2]; - assign router_5_29_to_router_4_29_rsp = router_5_29_rsp_out[3]; - assign router_5_29_to_magia_tile_ni_5_29_rsp = router_5_29_rsp_out[4]; - - assign router_5_29_to_router_5_30_req = router_5_29_req_out[0]; - assign router_5_29_to_router_6_29_req = router_5_29_req_out[1]; - assign router_5_29_to_router_5_28_req = router_5_29_req_out[2]; - assign router_5_29_to_router_4_29_req = router_5_29_req_out[3]; - assign router_5_29_to_magia_tile_ni_5_29_req = router_5_29_req_out[4]; - - assign router_5_29_rsp_in[0] = router_5_30_to_router_5_29_rsp; - assign router_5_29_rsp_in[1] = router_6_29_to_router_5_29_rsp; - assign router_5_29_rsp_in[2] = router_5_28_to_router_5_29_rsp; - assign router_5_29_rsp_in[3] = router_4_29_to_router_5_29_rsp; - assign router_5_29_rsp_in[4] = magia_tile_ni_5_29_to_router_5_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_29_req_in), - .floo_rsp_o (router_5_29_rsp_out), - .floo_req_o (router_5_29_req_out), - .floo_rsp_i (router_5_29_rsp_in) -); - - -floo_req_t [4:0] router_5_30_req_in; -floo_rsp_t [4:0] router_5_30_rsp_out; -floo_req_t [4:0] router_5_30_req_out; -floo_rsp_t [4:0] router_5_30_rsp_in; - - assign router_5_30_req_in[0] = router_5_31_to_router_5_30_req; - assign router_5_30_req_in[1] = router_6_30_to_router_5_30_req; - assign router_5_30_req_in[2] = router_5_29_to_router_5_30_req; - assign router_5_30_req_in[3] = router_4_30_to_router_5_30_req; - assign router_5_30_req_in[4] = magia_tile_ni_5_30_to_router_5_30_req; - - assign router_5_30_to_router_5_31_rsp = router_5_30_rsp_out[0]; - assign router_5_30_to_router_6_30_rsp = router_5_30_rsp_out[1]; - assign router_5_30_to_router_5_29_rsp = router_5_30_rsp_out[2]; - assign router_5_30_to_router_4_30_rsp = router_5_30_rsp_out[3]; - assign router_5_30_to_magia_tile_ni_5_30_rsp = router_5_30_rsp_out[4]; - - assign router_5_30_to_router_5_31_req = router_5_30_req_out[0]; - assign router_5_30_to_router_6_30_req = router_5_30_req_out[1]; - assign router_5_30_to_router_5_29_req = router_5_30_req_out[2]; - assign router_5_30_to_router_4_30_req = router_5_30_req_out[3]; - assign router_5_30_to_magia_tile_ni_5_30_req = router_5_30_req_out[4]; - - assign router_5_30_rsp_in[0] = router_5_31_to_router_5_30_rsp; - assign router_5_30_rsp_in[1] = router_6_30_to_router_5_30_rsp; - assign router_5_30_rsp_in[2] = router_5_29_to_router_5_30_rsp; - assign router_5_30_rsp_in[3] = router_4_30_to_router_5_30_rsp; - assign router_5_30_rsp_in[4] = magia_tile_ni_5_30_to_router_5_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_30_req_in), - .floo_rsp_o (router_5_30_rsp_out), - .floo_req_o (router_5_30_req_out), - .floo_rsp_i (router_5_30_rsp_in) -); - - -floo_req_t [4:0] router_5_31_req_in; -floo_rsp_t [4:0] router_5_31_rsp_out; -floo_req_t [4:0] router_5_31_req_out; -floo_rsp_t [4:0] router_5_31_rsp_in; - - assign router_5_31_req_in[0] = '0; - assign router_5_31_req_in[1] = router_6_31_to_router_5_31_req; - assign router_5_31_req_in[2] = router_5_30_to_router_5_31_req; - assign router_5_31_req_in[3] = router_4_31_to_router_5_31_req; - assign router_5_31_req_in[4] = magia_tile_ni_5_31_to_router_5_31_req; - - assign router_5_31_to_router_6_31_rsp = router_5_31_rsp_out[1]; - assign router_5_31_to_router_5_30_rsp = router_5_31_rsp_out[2]; - assign router_5_31_to_router_4_31_rsp = router_5_31_rsp_out[3]; - assign router_5_31_to_magia_tile_ni_5_31_rsp = router_5_31_rsp_out[4]; - - assign router_5_31_to_router_6_31_req = router_5_31_req_out[1]; - assign router_5_31_to_router_5_30_req = router_5_31_req_out[2]; - assign router_5_31_to_router_4_31_req = router_5_31_req_out[3]; - assign router_5_31_to_magia_tile_ni_5_31_req = router_5_31_req_out[4]; - - assign router_5_31_rsp_in[0] = '0; - assign router_5_31_rsp_in[1] = router_6_31_to_router_5_31_rsp; - assign router_5_31_rsp_in[2] = router_5_30_to_router_5_31_rsp; - assign router_5_31_rsp_in[3] = router_4_31_to_router_5_31_rsp; - assign router_5_31_rsp_in[4] = magia_tile_ni_5_31_to_router_5_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_31_req_in), - .floo_rsp_o (router_5_31_rsp_out), - .floo_req_o (router_5_31_req_out), - .floo_rsp_i (router_5_31_rsp_in) -); - - -floo_req_t [4:0] router_6_0_req_in; -floo_rsp_t [4:0] router_6_0_rsp_out; -floo_req_t [4:0] router_6_0_req_out; -floo_rsp_t [4:0] router_6_0_rsp_in; - - assign router_6_0_req_in[0] = router_6_1_to_router_6_0_req; - assign router_6_0_req_in[1] = router_7_0_to_router_6_0_req; - assign router_6_0_req_in[2] = '0; - assign router_6_0_req_in[3] = router_5_0_to_router_6_0_req; - assign router_6_0_req_in[4] = magia_tile_ni_6_0_to_router_6_0_req; - - assign router_6_0_to_router_6_1_rsp = router_6_0_rsp_out[0]; - assign router_6_0_to_router_7_0_rsp = router_6_0_rsp_out[1]; - assign router_6_0_to_router_5_0_rsp = router_6_0_rsp_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_rsp = router_6_0_rsp_out[4]; - - assign router_6_0_to_router_6_1_req = router_6_0_req_out[0]; - assign router_6_0_to_router_7_0_req = router_6_0_req_out[1]; - assign router_6_0_to_router_5_0_req = router_6_0_req_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_req = router_6_0_req_out[4]; - - assign router_6_0_rsp_in[0] = router_6_1_to_router_6_0_rsp; - assign router_6_0_rsp_in[1] = router_7_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[2] = '0; - assign router_6_0_rsp_in[3] = router_5_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[4] = magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_0_req_in), - .floo_rsp_o (router_6_0_rsp_out), - .floo_req_o (router_6_0_req_out), - .floo_rsp_i (router_6_0_rsp_in) -); - - -floo_req_t [4:0] router_6_1_req_in; -floo_rsp_t [4:0] router_6_1_rsp_out; -floo_req_t [4:0] router_6_1_req_out; -floo_rsp_t [4:0] router_6_1_rsp_in; - - assign router_6_1_req_in[0] = router_6_2_to_router_6_1_req; - assign router_6_1_req_in[1] = router_7_1_to_router_6_1_req; - assign router_6_1_req_in[2] = router_6_0_to_router_6_1_req; - assign router_6_1_req_in[3] = router_5_1_to_router_6_1_req; - assign router_6_1_req_in[4] = magia_tile_ni_6_1_to_router_6_1_req; - - assign router_6_1_to_router_6_2_rsp = router_6_1_rsp_out[0]; - assign router_6_1_to_router_7_1_rsp = router_6_1_rsp_out[1]; - assign router_6_1_to_router_6_0_rsp = router_6_1_rsp_out[2]; - assign router_6_1_to_router_5_1_rsp = router_6_1_rsp_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_rsp = router_6_1_rsp_out[4]; - - assign router_6_1_to_router_6_2_req = router_6_1_req_out[0]; - assign router_6_1_to_router_7_1_req = router_6_1_req_out[1]; - assign router_6_1_to_router_6_0_req = router_6_1_req_out[2]; - assign router_6_1_to_router_5_1_req = router_6_1_req_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_req = router_6_1_req_out[4]; - - assign router_6_1_rsp_in[0] = router_6_2_to_router_6_1_rsp; - assign router_6_1_rsp_in[1] = router_7_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[2] = router_6_0_to_router_6_1_rsp; - assign router_6_1_rsp_in[3] = router_5_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[4] = magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_1_req_in), - .floo_rsp_o (router_6_1_rsp_out), - .floo_req_o (router_6_1_req_out), - .floo_rsp_i (router_6_1_rsp_in) -); - - -floo_req_t [4:0] router_6_2_req_in; -floo_rsp_t [4:0] router_6_2_rsp_out; -floo_req_t [4:0] router_6_2_req_out; -floo_rsp_t [4:0] router_6_2_rsp_in; - - assign router_6_2_req_in[0] = router_6_3_to_router_6_2_req; - assign router_6_2_req_in[1] = router_7_2_to_router_6_2_req; - assign router_6_2_req_in[2] = router_6_1_to_router_6_2_req; - assign router_6_2_req_in[3] = router_5_2_to_router_6_2_req; - assign router_6_2_req_in[4] = magia_tile_ni_6_2_to_router_6_2_req; - - assign router_6_2_to_router_6_3_rsp = router_6_2_rsp_out[0]; - assign router_6_2_to_router_7_2_rsp = router_6_2_rsp_out[1]; - assign router_6_2_to_router_6_1_rsp = router_6_2_rsp_out[2]; - assign router_6_2_to_router_5_2_rsp = router_6_2_rsp_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_rsp = router_6_2_rsp_out[4]; - - assign router_6_2_to_router_6_3_req = router_6_2_req_out[0]; - assign router_6_2_to_router_7_2_req = router_6_2_req_out[1]; - assign router_6_2_to_router_6_1_req = router_6_2_req_out[2]; - assign router_6_2_to_router_5_2_req = router_6_2_req_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_req = router_6_2_req_out[4]; - - assign router_6_2_rsp_in[0] = router_6_3_to_router_6_2_rsp; - assign router_6_2_rsp_in[1] = router_7_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[2] = router_6_1_to_router_6_2_rsp; - assign router_6_2_rsp_in[3] = router_5_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[4] = magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_2_req_in), - .floo_rsp_o (router_6_2_rsp_out), - .floo_req_o (router_6_2_req_out), - .floo_rsp_i (router_6_2_rsp_in) -); - - -floo_req_t [4:0] router_6_3_req_in; -floo_rsp_t [4:0] router_6_3_rsp_out; -floo_req_t [4:0] router_6_3_req_out; -floo_rsp_t [4:0] router_6_3_rsp_in; - - assign router_6_3_req_in[0] = router_6_4_to_router_6_3_req; - assign router_6_3_req_in[1] = router_7_3_to_router_6_3_req; - assign router_6_3_req_in[2] = router_6_2_to_router_6_3_req; - assign router_6_3_req_in[3] = router_5_3_to_router_6_3_req; - assign router_6_3_req_in[4] = magia_tile_ni_6_3_to_router_6_3_req; - - assign router_6_3_to_router_6_4_rsp = router_6_3_rsp_out[0]; - assign router_6_3_to_router_7_3_rsp = router_6_3_rsp_out[1]; - assign router_6_3_to_router_6_2_rsp = router_6_3_rsp_out[2]; - assign router_6_3_to_router_5_3_rsp = router_6_3_rsp_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_rsp = router_6_3_rsp_out[4]; - - assign router_6_3_to_router_6_4_req = router_6_3_req_out[0]; - assign router_6_3_to_router_7_3_req = router_6_3_req_out[1]; - assign router_6_3_to_router_6_2_req = router_6_3_req_out[2]; - assign router_6_3_to_router_5_3_req = router_6_3_req_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_req = router_6_3_req_out[4]; - - assign router_6_3_rsp_in[0] = router_6_4_to_router_6_3_rsp; - assign router_6_3_rsp_in[1] = router_7_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[2] = router_6_2_to_router_6_3_rsp; - assign router_6_3_rsp_in[3] = router_5_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[4] = magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_3_req_in), - .floo_rsp_o (router_6_3_rsp_out), - .floo_req_o (router_6_3_req_out), - .floo_rsp_i (router_6_3_rsp_in) -); - - -floo_req_t [4:0] router_6_4_req_in; -floo_rsp_t [4:0] router_6_4_rsp_out; -floo_req_t [4:0] router_6_4_req_out; -floo_rsp_t [4:0] router_6_4_rsp_in; - - assign router_6_4_req_in[0] = router_6_5_to_router_6_4_req; - assign router_6_4_req_in[1] = router_7_4_to_router_6_4_req; - assign router_6_4_req_in[2] = router_6_3_to_router_6_4_req; - assign router_6_4_req_in[3] = router_5_4_to_router_6_4_req; - assign router_6_4_req_in[4] = magia_tile_ni_6_4_to_router_6_4_req; - - assign router_6_4_to_router_6_5_rsp = router_6_4_rsp_out[0]; - assign router_6_4_to_router_7_4_rsp = router_6_4_rsp_out[1]; - assign router_6_4_to_router_6_3_rsp = router_6_4_rsp_out[2]; - assign router_6_4_to_router_5_4_rsp = router_6_4_rsp_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_rsp = router_6_4_rsp_out[4]; - - assign router_6_4_to_router_6_5_req = router_6_4_req_out[0]; - assign router_6_4_to_router_7_4_req = router_6_4_req_out[1]; - assign router_6_4_to_router_6_3_req = router_6_4_req_out[2]; - assign router_6_4_to_router_5_4_req = router_6_4_req_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_req = router_6_4_req_out[4]; - - assign router_6_4_rsp_in[0] = router_6_5_to_router_6_4_rsp; - assign router_6_4_rsp_in[1] = router_7_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[2] = router_6_3_to_router_6_4_rsp; - assign router_6_4_rsp_in[3] = router_5_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[4] = magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_4_req_in), - .floo_rsp_o (router_6_4_rsp_out), - .floo_req_o (router_6_4_req_out), - .floo_rsp_i (router_6_4_rsp_in) -); - - -floo_req_t [4:0] router_6_5_req_in; -floo_rsp_t [4:0] router_6_5_rsp_out; -floo_req_t [4:0] router_6_5_req_out; -floo_rsp_t [4:0] router_6_5_rsp_in; - - assign router_6_5_req_in[0] = router_6_6_to_router_6_5_req; - assign router_6_5_req_in[1] = router_7_5_to_router_6_5_req; - assign router_6_5_req_in[2] = router_6_4_to_router_6_5_req; - assign router_6_5_req_in[3] = router_5_5_to_router_6_5_req; - assign router_6_5_req_in[4] = magia_tile_ni_6_5_to_router_6_5_req; - - assign router_6_5_to_router_6_6_rsp = router_6_5_rsp_out[0]; - assign router_6_5_to_router_7_5_rsp = router_6_5_rsp_out[1]; - assign router_6_5_to_router_6_4_rsp = router_6_5_rsp_out[2]; - assign router_6_5_to_router_5_5_rsp = router_6_5_rsp_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_rsp = router_6_5_rsp_out[4]; - - assign router_6_5_to_router_6_6_req = router_6_5_req_out[0]; - assign router_6_5_to_router_7_5_req = router_6_5_req_out[1]; - assign router_6_5_to_router_6_4_req = router_6_5_req_out[2]; - assign router_6_5_to_router_5_5_req = router_6_5_req_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_req = router_6_5_req_out[4]; - - assign router_6_5_rsp_in[0] = router_6_6_to_router_6_5_rsp; - assign router_6_5_rsp_in[1] = router_7_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[2] = router_6_4_to_router_6_5_rsp; - assign router_6_5_rsp_in[3] = router_5_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[4] = magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_5_req_in), - .floo_rsp_o (router_6_5_rsp_out), - .floo_req_o (router_6_5_req_out), - .floo_rsp_i (router_6_5_rsp_in) -); - - -floo_req_t [4:0] router_6_6_req_in; -floo_rsp_t [4:0] router_6_6_rsp_out; -floo_req_t [4:0] router_6_6_req_out; -floo_rsp_t [4:0] router_6_6_rsp_in; - - assign router_6_6_req_in[0] = router_6_7_to_router_6_6_req; - assign router_6_6_req_in[1] = router_7_6_to_router_6_6_req; - assign router_6_6_req_in[2] = router_6_5_to_router_6_6_req; - assign router_6_6_req_in[3] = router_5_6_to_router_6_6_req; - assign router_6_6_req_in[4] = magia_tile_ni_6_6_to_router_6_6_req; - - assign router_6_6_to_router_6_7_rsp = router_6_6_rsp_out[0]; - assign router_6_6_to_router_7_6_rsp = router_6_6_rsp_out[1]; - assign router_6_6_to_router_6_5_rsp = router_6_6_rsp_out[2]; - assign router_6_6_to_router_5_6_rsp = router_6_6_rsp_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_rsp = router_6_6_rsp_out[4]; - - assign router_6_6_to_router_6_7_req = router_6_6_req_out[0]; - assign router_6_6_to_router_7_6_req = router_6_6_req_out[1]; - assign router_6_6_to_router_6_5_req = router_6_6_req_out[2]; - assign router_6_6_to_router_5_6_req = router_6_6_req_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_req = router_6_6_req_out[4]; - - assign router_6_6_rsp_in[0] = router_6_7_to_router_6_6_rsp; - assign router_6_6_rsp_in[1] = router_7_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[2] = router_6_5_to_router_6_6_rsp; - assign router_6_6_rsp_in[3] = router_5_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[4] = magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_6_req_in), - .floo_rsp_o (router_6_6_rsp_out), - .floo_req_o (router_6_6_req_out), - .floo_rsp_i (router_6_6_rsp_in) -); - - -floo_req_t [4:0] router_6_7_req_in; -floo_rsp_t [4:0] router_6_7_rsp_out; -floo_req_t [4:0] router_6_7_req_out; -floo_rsp_t [4:0] router_6_7_rsp_in; - - assign router_6_7_req_in[0] = router_6_8_to_router_6_7_req; - assign router_6_7_req_in[1] = router_7_7_to_router_6_7_req; - assign router_6_7_req_in[2] = router_6_6_to_router_6_7_req; - assign router_6_7_req_in[3] = router_5_7_to_router_6_7_req; - assign router_6_7_req_in[4] = magia_tile_ni_6_7_to_router_6_7_req; - - assign router_6_7_to_router_6_8_rsp = router_6_7_rsp_out[0]; - assign router_6_7_to_router_7_7_rsp = router_6_7_rsp_out[1]; - assign router_6_7_to_router_6_6_rsp = router_6_7_rsp_out[2]; - assign router_6_7_to_router_5_7_rsp = router_6_7_rsp_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_rsp = router_6_7_rsp_out[4]; - - assign router_6_7_to_router_6_8_req = router_6_7_req_out[0]; - assign router_6_7_to_router_7_7_req = router_6_7_req_out[1]; - assign router_6_7_to_router_6_6_req = router_6_7_req_out[2]; - assign router_6_7_to_router_5_7_req = router_6_7_req_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_req = router_6_7_req_out[4]; - - assign router_6_7_rsp_in[0] = router_6_8_to_router_6_7_rsp; - assign router_6_7_rsp_in[1] = router_7_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[2] = router_6_6_to_router_6_7_rsp; - assign router_6_7_rsp_in[3] = router_5_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[4] = magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_7_req_in), - .floo_rsp_o (router_6_7_rsp_out), - .floo_req_o (router_6_7_req_out), - .floo_rsp_i (router_6_7_rsp_in) -); - - -floo_req_t [4:0] router_6_8_req_in; -floo_rsp_t [4:0] router_6_8_rsp_out; -floo_req_t [4:0] router_6_8_req_out; -floo_rsp_t [4:0] router_6_8_rsp_in; - - assign router_6_8_req_in[0] = router_6_9_to_router_6_8_req; - assign router_6_8_req_in[1] = router_7_8_to_router_6_8_req; - assign router_6_8_req_in[2] = router_6_7_to_router_6_8_req; - assign router_6_8_req_in[3] = router_5_8_to_router_6_8_req; - assign router_6_8_req_in[4] = magia_tile_ni_6_8_to_router_6_8_req; - - assign router_6_8_to_router_6_9_rsp = router_6_8_rsp_out[0]; - assign router_6_8_to_router_7_8_rsp = router_6_8_rsp_out[1]; - assign router_6_8_to_router_6_7_rsp = router_6_8_rsp_out[2]; - assign router_6_8_to_router_5_8_rsp = router_6_8_rsp_out[3]; - assign router_6_8_to_magia_tile_ni_6_8_rsp = router_6_8_rsp_out[4]; - - assign router_6_8_to_router_6_9_req = router_6_8_req_out[0]; - assign router_6_8_to_router_7_8_req = router_6_8_req_out[1]; - assign router_6_8_to_router_6_7_req = router_6_8_req_out[2]; - assign router_6_8_to_router_5_8_req = router_6_8_req_out[3]; - assign router_6_8_to_magia_tile_ni_6_8_req = router_6_8_req_out[4]; - - assign router_6_8_rsp_in[0] = router_6_9_to_router_6_8_rsp; - assign router_6_8_rsp_in[1] = router_7_8_to_router_6_8_rsp; - assign router_6_8_rsp_in[2] = router_6_7_to_router_6_8_rsp; - assign router_6_8_rsp_in[3] = router_5_8_to_router_6_8_rsp; - assign router_6_8_rsp_in[4] = magia_tile_ni_6_8_to_router_6_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_8_req_in), - .floo_rsp_o (router_6_8_rsp_out), - .floo_req_o (router_6_8_req_out), - .floo_rsp_i (router_6_8_rsp_in) -); - - -floo_req_t [4:0] router_6_9_req_in; -floo_rsp_t [4:0] router_6_9_rsp_out; -floo_req_t [4:0] router_6_9_req_out; -floo_rsp_t [4:0] router_6_9_rsp_in; - - assign router_6_9_req_in[0] = router_6_10_to_router_6_9_req; - assign router_6_9_req_in[1] = router_7_9_to_router_6_9_req; - assign router_6_9_req_in[2] = router_6_8_to_router_6_9_req; - assign router_6_9_req_in[3] = router_5_9_to_router_6_9_req; - assign router_6_9_req_in[4] = magia_tile_ni_6_9_to_router_6_9_req; - - assign router_6_9_to_router_6_10_rsp = router_6_9_rsp_out[0]; - assign router_6_9_to_router_7_9_rsp = router_6_9_rsp_out[1]; - assign router_6_9_to_router_6_8_rsp = router_6_9_rsp_out[2]; - assign router_6_9_to_router_5_9_rsp = router_6_9_rsp_out[3]; - assign router_6_9_to_magia_tile_ni_6_9_rsp = router_6_9_rsp_out[4]; - - assign router_6_9_to_router_6_10_req = router_6_9_req_out[0]; - assign router_6_9_to_router_7_9_req = router_6_9_req_out[1]; - assign router_6_9_to_router_6_8_req = router_6_9_req_out[2]; - assign router_6_9_to_router_5_9_req = router_6_9_req_out[3]; - assign router_6_9_to_magia_tile_ni_6_9_req = router_6_9_req_out[4]; - - assign router_6_9_rsp_in[0] = router_6_10_to_router_6_9_rsp; - assign router_6_9_rsp_in[1] = router_7_9_to_router_6_9_rsp; - assign router_6_9_rsp_in[2] = router_6_8_to_router_6_9_rsp; - assign router_6_9_rsp_in[3] = router_5_9_to_router_6_9_rsp; - assign router_6_9_rsp_in[4] = magia_tile_ni_6_9_to_router_6_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_9_req_in), - .floo_rsp_o (router_6_9_rsp_out), - .floo_req_o (router_6_9_req_out), - .floo_rsp_i (router_6_9_rsp_in) -); - - -floo_req_t [4:0] router_6_10_req_in; -floo_rsp_t [4:0] router_6_10_rsp_out; -floo_req_t [4:0] router_6_10_req_out; -floo_rsp_t [4:0] router_6_10_rsp_in; - - assign router_6_10_req_in[0] = router_6_11_to_router_6_10_req; - assign router_6_10_req_in[1] = router_7_10_to_router_6_10_req; - assign router_6_10_req_in[2] = router_6_9_to_router_6_10_req; - assign router_6_10_req_in[3] = router_5_10_to_router_6_10_req; - assign router_6_10_req_in[4] = magia_tile_ni_6_10_to_router_6_10_req; - - assign router_6_10_to_router_6_11_rsp = router_6_10_rsp_out[0]; - assign router_6_10_to_router_7_10_rsp = router_6_10_rsp_out[1]; - assign router_6_10_to_router_6_9_rsp = router_6_10_rsp_out[2]; - assign router_6_10_to_router_5_10_rsp = router_6_10_rsp_out[3]; - assign router_6_10_to_magia_tile_ni_6_10_rsp = router_6_10_rsp_out[4]; - - assign router_6_10_to_router_6_11_req = router_6_10_req_out[0]; - assign router_6_10_to_router_7_10_req = router_6_10_req_out[1]; - assign router_6_10_to_router_6_9_req = router_6_10_req_out[2]; - assign router_6_10_to_router_5_10_req = router_6_10_req_out[3]; - assign router_6_10_to_magia_tile_ni_6_10_req = router_6_10_req_out[4]; - - assign router_6_10_rsp_in[0] = router_6_11_to_router_6_10_rsp; - assign router_6_10_rsp_in[1] = router_7_10_to_router_6_10_rsp; - assign router_6_10_rsp_in[2] = router_6_9_to_router_6_10_rsp; - assign router_6_10_rsp_in[3] = router_5_10_to_router_6_10_rsp; - assign router_6_10_rsp_in[4] = magia_tile_ni_6_10_to_router_6_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_10_req_in), - .floo_rsp_o (router_6_10_rsp_out), - .floo_req_o (router_6_10_req_out), - .floo_rsp_i (router_6_10_rsp_in) -); - - -floo_req_t [4:0] router_6_11_req_in; -floo_rsp_t [4:0] router_6_11_rsp_out; -floo_req_t [4:0] router_6_11_req_out; -floo_rsp_t [4:0] router_6_11_rsp_in; - - assign router_6_11_req_in[0] = router_6_12_to_router_6_11_req; - assign router_6_11_req_in[1] = router_7_11_to_router_6_11_req; - assign router_6_11_req_in[2] = router_6_10_to_router_6_11_req; - assign router_6_11_req_in[3] = router_5_11_to_router_6_11_req; - assign router_6_11_req_in[4] = magia_tile_ni_6_11_to_router_6_11_req; - - assign router_6_11_to_router_6_12_rsp = router_6_11_rsp_out[0]; - assign router_6_11_to_router_7_11_rsp = router_6_11_rsp_out[1]; - assign router_6_11_to_router_6_10_rsp = router_6_11_rsp_out[2]; - assign router_6_11_to_router_5_11_rsp = router_6_11_rsp_out[3]; - assign router_6_11_to_magia_tile_ni_6_11_rsp = router_6_11_rsp_out[4]; - - assign router_6_11_to_router_6_12_req = router_6_11_req_out[0]; - assign router_6_11_to_router_7_11_req = router_6_11_req_out[1]; - assign router_6_11_to_router_6_10_req = router_6_11_req_out[2]; - assign router_6_11_to_router_5_11_req = router_6_11_req_out[3]; - assign router_6_11_to_magia_tile_ni_6_11_req = router_6_11_req_out[4]; - - assign router_6_11_rsp_in[0] = router_6_12_to_router_6_11_rsp; - assign router_6_11_rsp_in[1] = router_7_11_to_router_6_11_rsp; - assign router_6_11_rsp_in[2] = router_6_10_to_router_6_11_rsp; - assign router_6_11_rsp_in[3] = router_5_11_to_router_6_11_rsp; - assign router_6_11_rsp_in[4] = magia_tile_ni_6_11_to_router_6_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_11_req_in), - .floo_rsp_o (router_6_11_rsp_out), - .floo_req_o (router_6_11_req_out), - .floo_rsp_i (router_6_11_rsp_in) -); - - -floo_req_t [4:0] router_6_12_req_in; -floo_rsp_t [4:0] router_6_12_rsp_out; -floo_req_t [4:0] router_6_12_req_out; -floo_rsp_t [4:0] router_6_12_rsp_in; - - assign router_6_12_req_in[0] = router_6_13_to_router_6_12_req; - assign router_6_12_req_in[1] = router_7_12_to_router_6_12_req; - assign router_6_12_req_in[2] = router_6_11_to_router_6_12_req; - assign router_6_12_req_in[3] = router_5_12_to_router_6_12_req; - assign router_6_12_req_in[4] = magia_tile_ni_6_12_to_router_6_12_req; - - assign router_6_12_to_router_6_13_rsp = router_6_12_rsp_out[0]; - assign router_6_12_to_router_7_12_rsp = router_6_12_rsp_out[1]; - assign router_6_12_to_router_6_11_rsp = router_6_12_rsp_out[2]; - assign router_6_12_to_router_5_12_rsp = router_6_12_rsp_out[3]; - assign router_6_12_to_magia_tile_ni_6_12_rsp = router_6_12_rsp_out[4]; - - assign router_6_12_to_router_6_13_req = router_6_12_req_out[0]; - assign router_6_12_to_router_7_12_req = router_6_12_req_out[1]; - assign router_6_12_to_router_6_11_req = router_6_12_req_out[2]; - assign router_6_12_to_router_5_12_req = router_6_12_req_out[3]; - assign router_6_12_to_magia_tile_ni_6_12_req = router_6_12_req_out[4]; - - assign router_6_12_rsp_in[0] = router_6_13_to_router_6_12_rsp; - assign router_6_12_rsp_in[1] = router_7_12_to_router_6_12_rsp; - assign router_6_12_rsp_in[2] = router_6_11_to_router_6_12_rsp; - assign router_6_12_rsp_in[3] = router_5_12_to_router_6_12_rsp; - assign router_6_12_rsp_in[4] = magia_tile_ni_6_12_to_router_6_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_12_req_in), - .floo_rsp_o (router_6_12_rsp_out), - .floo_req_o (router_6_12_req_out), - .floo_rsp_i (router_6_12_rsp_in) -); - - -floo_req_t [4:0] router_6_13_req_in; -floo_rsp_t [4:0] router_6_13_rsp_out; -floo_req_t [4:0] router_6_13_req_out; -floo_rsp_t [4:0] router_6_13_rsp_in; - - assign router_6_13_req_in[0] = router_6_14_to_router_6_13_req; - assign router_6_13_req_in[1] = router_7_13_to_router_6_13_req; - assign router_6_13_req_in[2] = router_6_12_to_router_6_13_req; - assign router_6_13_req_in[3] = router_5_13_to_router_6_13_req; - assign router_6_13_req_in[4] = magia_tile_ni_6_13_to_router_6_13_req; - - assign router_6_13_to_router_6_14_rsp = router_6_13_rsp_out[0]; - assign router_6_13_to_router_7_13_rsp = router_6_13_rsp_out[1]; - assign router_6_13_to_router_6_12_rsp = router_6_13_rsp_out[2]; - assign router_6_13_to_router_5_13_rsp = router_6_13_rsp_out[3]; - assign router_6_13_to_magia_tile_ni_6_13_rsp = router_6_13_rsp_out[4]; - - assign router_6_13_to_router_6_14_req = router_6_13_req_out[0]; - assign router_6_13_to_router_7_13_req = router_6_13_req_out[1]; - assign router_6_13_to_router_6_12_req = router_6_13_req_out[2]; - assign router_6_13_to_router_5_13_req = router_6_13_req_out[3]; - assign router_6_13_to_magia_tile_ni_6_13_req = router_6_13_req_out[4]; - - assign router_6_13_rsp_in[0] = router_6_14_to_router_6_13_rsp; - assign router_6_13_rsp_in[1] = router_7_13_to_router_6_13_rsp; - assign router_6_13_rsp_in[2] = router_6_12_to_router_6_13_rsp; - assign router_6_13_rsp_in[3] = router_5_13_to_router_6_13_rsp; - assign router_6_13_rsp_in[4] = magia_tile_ni_6_13_to_router_6_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_13_req_in), - .floo_rsp_o (router_6_13_rsp_out), - .floo_req_o (router_6_13_req_out), - .floo_rsp_i (router_6_13_rsp_in) -); - - -floo_req_t [4:0] router_6_14_req_in; -floo_rsp_t [4:0] router_6_14_rsp_out; -floo_req_t [4:0] router_6_14_req_out; -floo_rsp_t [4:0] router_6_14_rsp_in; - - assign router_6_14_req_in[0] = router_6_15_to_router_6_14_req; - assign router_6_14_req_in[1] = router_7_14_to_router_6_14_req; - assign router_6_14_req_in[2] = router_6_13_to_router_6_14_req; - assign router_6_14_req_in[3] = router_5_14_to_router_6_14_req; - assign router_6_14_req_in[4] = magia_tile_ni_6_14_to_router_6_14_req; - - assign router_6_14_to_router_6_15_rsp = router_6_14_rsp_out[0]; - assign router_6_14_to_router_7_14_rsp = router_6_14_rsp_out[1]; - assign router_6_14_to_router_6_13_rsp = router_6_14_rsp_out[2]; - assign router_6_14_to_router_5_14_rsp = router_6_14_rsp_out[3]; - assign router_6_14_to_magia_tile_ni_6_14_rsp = router_6_14_rsp_out[4]; - - assign router_6_14_to_router_6_15_req = router_6_14_req_out[0]; - assign router_6_14_to_router_7_14_req = router_6_14_req_out[1]; - assign router_6_14_to_router_6_13_req = router_6_14_req_out[2]; - assign router_6_14_to_router_5_14_req = router_6_14_req_out[3]; - assign router_6_14_to_magia_tile_ni_6_14_req = router_6_14_req_out[4]; - - assign router_6_14_rsp_in[0] = router_6_15_to_router_6_14_rsp; - assign router_6_14_rsp_in[1] = router_7_14_to_router_6_14_rsp; - assign router_6_14_rsp_in[2] = router_6_13_to_router_6_14_rsp; - assign router_6_14_rsp_in[3] = router_5_14_to_router_6_14_rsp; - assign router_6_14_rsp_in[4] = magia_tile_ni_6_14_to_router_6_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_14_req_in), - .floo_rsp_o (router_6_14_rsp_out), - .floo_req_o (router_6_14_req_out), - .floo_rsp_i (router_6_14_rsp_in) -); - - -floo_req_t [4:0] router_6_15_req_in; -floo_rsp_t [4:0] router_6_15_rsp_out; -floo_req_t [4:0] router_6_15_req_out; -floo_rsp_t [4:0] router_6_15_rsp_in; - - assign router_6_15_req_in[0] = router_6_16_to_router_6_15_req; - assign router_6_15_req_in[1] = router_7_15_to_router_6_15_req; - assign router_6_15_req_in[2] = router_6_14_to_router_6_15_req; - assign router_6_15_req_in[3] = router_5_15_to_router_6_15_req; - assign router_6_15_req_in[4] = magia_tile_ni_6_15_to_router_6_15_req; - - assign router_6_15_to_router_6_16_rsp = router_6_15_rsp_out[0]; - assign router_6_15_to_router_7_15_rsp = router_6_15_rsp_out[1]; - assign router_6_15_to_router_6_14_rsp = router_6_15_rsp_out[2]; - assign router_6_15_to_router_5_15_rsp = router_6_15_rsp_out[3]; - assign router_6_15_to_magia_tile_ni_6_15_rsp = router_6_15_rsp_out[4]; - - assign router_6_15_to_router_6_16_req = router_6_15_req_out[0]; - assign router_6_15_to_router_7_15_req = router_6_15_req_out[1]; - assign router_6_15_to_router_6_14_req = router_6_15_req_out[2]; - assign router_6_15_to_router_5_15_req = router_6_15_req_out[3]; - assign router_6_15_to_magia_tile_ni_6_15_req = router_6_15_req_out[4]; - - assign router_6_15_rsp_in[0] = router_6_16_to_router_6_15_rsp; - assign router_6_15_rsp_in[1] = router_7_15_to_router_6_15_rsp; - assign router_6_15_rsp_in[2] = router_6_14_to_router_6_15_rsp; - assign router_6_15_rsp_in[3] = router_5_15_to_router_6_15_rsp; - assign router_6_15_rsp_in[4] = magia_tile_ni_6_15_to_router_6_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_15_req_in), - .floo_rsp_o (router_6_15_rsp_out), - .floo_req_o (router_6_15_req_out), - .floo_rsp_i (router_6_15_rsp_in) -); - - -floo_req_t [4:0] router_6_16_req_in; -floo_rsp_t [4:0] router_6_16_rsp_out; -floo_req_t [4:0] router_6_16_req_out; -floo_rsp_t [4:0] router_6_16_rsp_in; - - assign router_6_16_req_in[0] = router_6_17_to_router_6_16_req; - assign router_6_16_req_in[1] = router_7_16_to_router_6_16_req; - assign router_6_16_req_in[2] = router_6_15_to_router_6_16_req; - assign router_6_16_req_in[3] = router_5_16_to_router_6_16_req; - assign router_6_16_req_in[4] = magia_tile_ni_6_16_to_router_6_16_req; - - assign router_6_16_to_router_6_17_rsp = router_6_16_rsp_out[0]; - assign router_6_16_to_router_7_16_rsp = router_6_16_rsp_out[1]; - assign router_6_16_to_router_6_15_rsp = router_6_16_rsp_out[2]; - assign router_6_16_to_router_5_16_rsp = router_6_16_rsp_out[3]; - assign router_6_16_to_magia_tile_ni_6_16_rsp = router_6_16_rsp_out[4]; - - assign router_6_16_to_router_6_17_req = router_6_16_req_out[0]; - assign router_6_16_to_router_7_16_req = router_6_16_req_out[1]; - assign router_6_16_to_router_6_15_req = router_6_16_req_out[2]; - assign router_6_16_to_router_5_16_req = router_6_16_req_out[3]; - assign router_6_16_to_magia_tile_ni_6_16_req = router_6_16_req_out[4]; - - assign router_6_16_rsp_in[0] = router_6_17_to_router_6_16_rsp; - assign router_6_16_rsp_in[1] = router_7_16_to_router_6_16_rsp; - assign router_6_16_rsp_in[2] = router_6_15_to_router_6_16_rsp; - assign router_6_16_rsp_in[3] = router_5_16_to_router_6_16_rsp; - assign router_6_16_rsp_in[4] = magia_tile_ni_6_16_to_router_6_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_16_req_in), - .floo_rsp_o (router_6_16_rsp_out), - .floo_req_o (router_6_16_req_out), - .floo_rsp_i (router_6_16_rsp_in) -); - - -floo_req_t [4:0] router_6_17_req_in; -floo_rsp_t [4:0] router_6_17_rsp_out; -floo_req_t [4:0] router_6_17_req_out; -floo_rsp_t [4:0] router_6_17_rsp_in; - - assign router_6_17_req_in[0] = router_6_18_to_router_6_17_req; - assign router_6_17_req_in[1] = router_7_17_to_router_6_17_req; - assign router_6_17_req_in[2] = router_6_16_to_router_6_17_req; - assign router_6_17_req_in[3] = router_5_17_to_router_6_17_req; - assign router_6_17_req_in[4] = magia_tile_ni_6_17_to_router_6_17_req; - - assign router_6_17_to_router_6_18_rsp = router_6_17_rsp_out[0]; - assign router_6_17_to_router_7_17_rsp = router_6_17_rsp_out[1]; - assign router_6_17_to_router_6_16_rsp = router_6_17_rsp_out[2]; - assign router_6_17_to_router_5_17_rsp = router_6_17_rsp_out[3]; - assign router_6_17_to_magia_tile_ni_6_17_rsp = router_6_17_rsp_out[4]; - - assign router_6_17_to_router_6_18_req = router_6_17_req_out[0]; - assign router_6_17_to_router_7_17_req = router_6_17_req_out[1]; - assign router_6_17_to_router_6_16_req = router_6_17_req_out[2]; - assign router_6_17_to_router_5_17_req = router_6_17_req_out[3]; - assign router_6_17_to_magia_tile_ni_6_17_req = router_6_17_req_out[4]; - - assign router_6_17_rsp_in[0] = router_6_18_to_router_6_17_rsp; - assign router_6_17_rsp_in[1] = router_7_17_to_router_6_17_rsp; - assign router_6_17_rsp_in[2] = router_6_16_to_router_6_17_rsp; - assign router_6_17_rsp_in[3] = router_5_17_to_router_6_17_rsp; - assign router_6_17_rsp_in[4] = magia_tile_ni_6_17_to_router_6_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_17_req_in), - .floo_rsp_o (router_6_17_rsp_out), - .floo_req_o (router_6_17_req_out), - .floo_rsp_i (router_6_17_rsp_in) -); - - -floo_req_t [4:0] router_6_18_req_in; -floo_rsp_t [4:0] router_6_18_rsp_out; -floo_req_t [4:0] router_6_18_req_out; -floo_rsp_t [4:0] router_6_18_rsp_in; - - assign router_6_18_req_in[0] = router_6_19_to_router_6_18_req; - assign router_6_18_req_in[1] = router_7_18_to_router_6_18_req; - assign router_6_18_req_in[2] = router_6_17_to_router_6_18_req; - assign router_6_18_req_in[3] = router_5_18_to_router_6_18_req; - assign router_6_18_req_in[4] = magia_tile_ni_6_18_to_router_6_18_req; - - assign router_6_18_to_router_6_19_rsp = router_6_18_rsp_out[0]; - assign router_6_18_to_router_7_18_rsp = router_6_18_rsp_out[1]; - assign router_6_18_to_router_6_17_rsp = router_6_18_rsp_out[2]; - assign router_6_18_to_router_5_18_rsp = router_6_18_rsp_out[3]; - assign router_6_18_to_magia_tile_ni_6_18_rsp = router_6_18_rsp_out[4]; - - assign router_6_18_to_router_6_19_req = router_6_18_req_out[0]; - assign router_6_18_to_router_7_18_req = router_6_18_req_out[1]; - assign router_6_18_to_router_6_17_req = router_6_18_req_out[2]; - assign router_6_18_to_router_5_18_req = router_6_18_req_out[3]; - assign router_6_18_to_magia_tile_ni_6_18_req = router_6_18_req_out[4]; - - assign router_6_18_rsp_in[0] = router_6_19_to_router_6_18_rsp; - assign router_6_18_rsp_in[1] = router_7_18_to_router_6_18_rsp; - assign router_6_18_rsp_in[2] = router_6_17_to_router_6_18_rsp; - assign router_6_18_rsp_in[3] = router_5_18_to_router_6_18_rsp; - assign router_6_18_rsp_in[4] = magia_tile_ni_6_18_to_router_6_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_18_req_in), - .floo_rsp_o (router_6_18_rsp_out), - .floo_req_o (router_6_18_req_out), - .floo_rsp_i (router_6_18_rsp_in) -); - - -floo_req_t [4:0] router_6_19_req_in; -floo_rsp_t [4:0] router_6_19_rsp_out; -floo_req_t [4:0] router_6_19_req_out; -floo_rsp_t [4:0] router_6_19_rsp_in; - - assign router_6_19_req_in[0] = router_6_20_to_router_6_19_req; - assign router_6_19_req_in[1] = router_7_19_to_router_6_19_req; - assign router_6_19_req_in[2] = router_6_18_to_router_6_19_req; - assign router_6_19_req_in[3] = router_5_19_to_router_6_19_req; - assign router_6_19_req_in[4] = magia_tile_ni_6_19_to_router_6_19_req; - - assign router_6_19_to_router_6_20_rsp = router_6_19_rsp_out[0]; - assign router_6_19_to_router_7_19_rsp = router_6_19_rsp_out[1]; - assign router_6_19_to_router_6_18_rsp = router_6_19_rsp_out[2]; - assign router_6_19_to_router_5_19_rsp = router_6_19_rsp_out[3]; - assign router_6_19_to_magia_tile_ni_6_19_rsp = router_6_19_rsp_out[4]; - - assign router_6_19_to_router_6_20_req = router_6_19_req_out[0]; - assign router_6_19_to_router_7_19_req = router_6_19_req_out[1]; - assign router_6_19_to_router_6_18_req = router_6_19_req_out[2]; - assign router_6_19_to_router_5_19_req = router_6_19_req_out[3]; - assign router_6_19_to_magia_tile_ni_6_19_req = router_6_19_req_out[4]; - - assign router_6_19_rsp_in[0] = router_6_20_to_router_6_19_rsp; - assign router_6_19_rsp_in[1] = router_7_19_to_router_6_19_rsp; - assign router_6_19_rsp_in[2] = router_6_18_to_router_6_19_rsp; - assign router_6_19_rsp_in[3] = router_5_19_to_router_6_19_rsp; - assign router_6_19_rsp_in[4] = magia_tile_ni_6_19_to_router_6_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_19_req_in), - .floo_rsp_o (router_6_19_rsp_out), - .floo_req_o (router_6_19_req_out), - .floo_rsp_i (router_6_19_rsp_in) -); - - -floo_req_t [4:0] router_6_20_req_in; -floo_rsp_t [4:0] router_6_20_rsp_out; -floo_req_t [4:0] router_6_20_req_out; -floo_rsp_t [4:0] router_6_20_rsp_in; - - assign router_6_20_req_in[0] = router_6_21_to_router_6_20_req; - assign router_6_20_req_in[1] = router_7_20_to_router_6_20_req; - assign router_6_20_req_in[2] = router_6_19_to_router_6_20_req; - assign router_6_20_req_in[3] = router_5_20_to_router_6_20_req; - assign router_6_20_req_in[4] = magia_tile_ni_6_20_to_router_6_20_req; - - assign router_6_20_to_router_6_21_rsp = router_6_20_rsp_out[0]; - assign router_6_20_to_router_7_20_rsp = router_6_20_rsp_out[1]; - assign router_6_20_to_router_6_19_rsp = router_6_20_rsp_out[2]; - assign router_6_20_to_router_5_20_rsp = router_6_20_rsp_out[3]; - assign router_6_20_to_magia_tile_ni_6_20_rsp = router_6_20_rsp_out[4]; - - assign router_6_20_to_router_6_21_req = router_6_20_req_out[0]; - assign router_6_20_to_router_7_20_req = router_6_20_req_out[1]; - assign router_6_20_to_router_6_19_req = router_6_20_req_out[2]; - assign router_6_20_to_router_5_20_req = router_6_20_req_out[3]; - assign router_6_20_to_magia_tile_ni_6_20_req = router_6_20_req_out[4]; - - assign router_6_20_rsp_in[0] = router_6_21_to_router_6_20_rsp; - assign router_6_20_rsp_in[1] = router_7_20_to_router_6_20_rsp; - assign router_6_20_rsp_in[2] = router_6_19_to_router_6_20_rsp; - assign router_6_20_rsp_in[3] = router_5_20_to_router_6_20_rsp; - assign router_6_20_rsp_in[4] = magia_tile_ni_6_20_to_router_6_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_20_req_in), - .floo_rsp_o (router_6_20_rsp_out), - .floo_req_o (router_6_20_req_out), - .floo_rsp_i (router_6_20_rsp_in) -); - - -floo_req_t [4:0] router_6_21_req_in; -floo_rsp_t [4:0] router_6_21_rsp_out; -floo_req_t [4:0] router_6_21_req_out; -floo_rsp_t [4:0] router_6_21_rsp_in; - - assign router_6_21_req_in[0] = router_6_22_to_router_6_21_req; - assign router_6_21_req_in[1] = router_7_21_to_router_6_21_req; - assign router_6_21_req_in[2] = router_6_20_to_router_6_21_req; - assign router_6_21_req_in[3] = router_5_21_to_router_6_21_req; - assign router_6_21_req_in[4] = magia_tile_ni_6_21_to_router_6_21_req; - - assign router_6_21_to_router_6_22_rsp = router_6_21_rsp_out[0]; - assign router_6_21_to_router_7_21_rsp = router_6_21_rsp_out[1]; - assign router_6_21_to_router_6_20_rsp = router_6_21_rsp_out[2]; - assign router_6_21_to_router_5_21_rsp = router_6_21_rsp_out[3]; - assign router_6_21_to_magia_tile_ni_6_21_rsp = router_6_21_rsp_out[4]; - - assign router_6_21_to_router_6_22_req = router_6_21_req_out[0]; - assign router_6_21_to_router_7_21_req = router_6_21_req_out[1]; - assign router_6_21_to_router_6_20_req = router_6_21_req_out[2]; - assign router_6_21_to_router_5_21_req = router_6_21_req_out[3]; - assign router_6_21_to_magia_tile_ni_6_21_req = router_6_21_req_out[4]; - - assign router_6_21_rsp_in[0] = router_6_22_to_router_6_21_rsp; - assign router_6_21_rsp_in[1] = router_7_21_to_router_6_21_rsp; - assign router_6_21_rsp_in[2] = router_6_20_to_router_6_21_rsp; - assign router_6_21_rsp_in[3] = router_5_21_to_router_6_21_rsp; - assign router_6_21_rsp_in[4] = magia_tile_ni_6_21_to_router_6_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_21_req_in), - .floo_rsp_o (router_6_21_rsp_out), - .floo_req_o (router_6_21_req_out), - .floo_rsp_i (router_6_21_rsp_in) -); - - -floo_req_t [4:0] router_6_22_req_in; -floo_rsp_t [4:0] router_6_22_rsp_out; -floo_req_t [4:0] router_6_22_req_out; -floo_rsp_t [4:0] router_6_22_rsp_in; - - assign router_6_22_req_in[0] = router_6_23_to_router_6_22_req; - assign router_6_22_req_in[1] = router_7_22_to_router_6_22_req; - assign router_6_22_req_in[2] = router_6_21_to_router_6_22_req; - assign router_6_22_req_in[3] = router_5_22_to_router_6_22_req; - assign router_6_22_req_in[4] = magia_tile_ni_6_22_to_router_6_22_req; - - assign router_6_22_to_router_6_23_rsp = router_6_22_rsp_out[0]; - assign router_6_22_to_router_7_22_rsp = router_6_22_rsp_out[1]; - assign router_6_22_to_router_6_21_rsp = router_6_22_rsp_out[2]; - assign router_6_22_to_router_5_22_rsp = router_6_22_rsp_out[3]; - assign router_6_22_to_magia_tile_ni_6_22_rsp = router_6_22_rsp_out[4]; - - assign router_6_22_to_router_6_23_req = router_6_22_req_out[0]; - assign router_6_22_to_router_7_22_req = router_6_22_req_out[1]; - assign router_6_22_to_router_6_21_req = router_6_22_req_out[2]; - assign router_6_22_to_router_5_22_req = router_6_22_req_out[3]; - assign router_6_22_to_magia_tile_ni_6_22_req = router_6_22_req_out[4]; - - assign router_6_22_rsp_in[0] = router_6_23_to_router_6_22_rsp; - assign router_6_22_rsp_in[1] = router_7_22_to_router_6_22_rsp; - assign router_6_22_rsp_in[2] = router_6_21_to_router_6_22_rsp; - assign router_6_22_rsp_in[3] = router_5_22_to_router_6_22_rsp; - assign router_6_22_rsp_in[4] = magia_tile_ni_6_22_to_router_6_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_22_req_in), - .floo_rsp_o (router_6_22_rsp_out), - .floo_req_o (router_6_22_req_out), - .floo_rsp_i (router_6_22_rsp_in) -); - - -floo_req_t [4:0] router_6_23_req_in; -floo_rsp_t [4:0] router_6_23_rsp_out; -floo_req_t [4:0] router_6_23_req_out; -floo_rsp_t [4:0] router_6_23_rsp_in; - - assign router_6_23_req_in[0] = router_6_24_to_router_6_23_req; - assign router_6_23_req_in[1] = router_7_23_to_router_6_23_req; - assign router_6_23_req_in[2] = router_6_22_to_router_6_23_req; - assign router_6_23_req_in[3] = router_5_23_to_router_6_23_req; - assign router_6_23_req_in[4] = magia_tile_ni_6_23_to_router_6_23_req; - - assign router_6_23_to_router_6_24_rsp = router_6_23_rsp_out[0]; - assign router_6_23_to_router_7_23_rsp = router_6_23_rsp_out[1]; - assign router_6_23_to_router_6_22_rsp = router_6_23_rsp_out[2]; - assign router_6_23_to_router_5_23_rsp = router_6_23_rsp_out[3]; - assign router_6_23_to_magia_tile_ni_6_23_rsp = router_6_23_rsp_out[4]; - - assign router_6_23_to_router_6_24_req = router_6_23_req_out[0]; - assign router_6_23_to_router_7_23_req = router_6_23_req_out[1]; - assign router_6_23_to_router_6_22_req = router_6_23_req_out[2]; - assign router_6_23_to_router_5_23_req = router_6_23_req_out[3]; - assign router_6_23_to_magia_tile_ni_6_23_req = router_6_23_req_out[4]; - - assign router_6_23_rsp_in[0] = router_6_24_to_router_6_23_rsp; - assign router_6_23_rsp_in[1] = router_7_23_to_router_6_23_rsp; - assign router_6_23_rsp_in[2] = router_6_22_to_router_6_23_rsp; - assign router_6_23_rsp_in[3] = router_5_23_to_router_6_23_rsp; - assign router_6_23_rsp_in[4] = magia_tile_ni_6_23_to_router_6_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_23_req_in), - .floo_rsp_o (router_6_23_rsp_out), - .floo_req_o (router_6_23_req_out), - .floo_rsp_i (router_6_23_rsp_in) -); - - -floo_req_t [4:0] router_6_24_req_in; -floo_rsp_t [4:0] router_6_24_rsp_out; -floo_req_t [4:0] router_6_24_req_out; -floo_rsp_t [4:0] router_6_24_rsp_in; - - assign router_6_24_req_in[0] = router_6_25_to_router_6_24_req; - assign router_6_24_req_in[1] = router_7_24_to_router_6_24_req; - assign router_6_24_req_in[2] = router_6_23_to_router_6_24_req; - assign router_6_24_req_in[3] = router_5_24_to_router_6_24_req; - assign router_6_24_req_in[4] = magia_tile_ni_6_24_to_router_6_24_req; - - assign router_6_24_to_router_6_25_rsp = router_6_24_rsp_out[0]; - assign router_6_24_to_router_7_24_rsp = router_6_24_rsp_out[1]; - assign router_6_24_to_router_6_23_rsp = router_6_24_rsp_out[2]; - assign router_6_24_to_router_5_24_rsp = router_6_24_rsp_out[3]; - assign router_6_24_to_magia_tile_ni_6_24_rsp = router_6_24_rsp_out[4]; - - assign router_6_24_to_router_6_25_req = router_6_24_req_out[0]; - assign router_6_24_to_router_7_24_req = router_6_24_req_out[1]; - assign router_6_24_to_router_6_23_req = router_6_24_req_out[2]; - assign router_6_24_to_router_5_24_req = router_6_24_req_out[3]; - assign router_6_24_to_magia_tile_ni_6_24_req = router_6_24_req_out[4]; - - assign router_6_24_rsp_in[0] = router_6_25_to_router_6_24_rsp; - assign router_6_24_rsp_in[1] = router_7_24_to_router_6_24_rsp; - assign router_6_24_rsp_in[2] = router_6_23_to_router_6_24_rsp; - assign router_6_24_rsp_in[3] = router_5_24_to_router_6_24_rsp; - assign router_6_24_rsp_in[4] = magia_tile_ni_6_24_to_router_6_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_24_req_in), - .floo_rsp_o (router_6_24_rsp_out), - .floo_req_o (router_6_24_req_out), - .floo_rsp_i (router_6_24_rsp_in) -); - - -floo_req_t [4:0] router_6_25_req_in; -floo_rsp_t [4:0] router_6_25_rsp_out; -floo_req_t [4:0] router_6_25_req_out; -floo_rsp_t [4:0] router_6_25_rsp_in; - - assign router_6_25_req_in[0] = router_6_26_to_router_6_25_req; - assign router_6_25_req_in[1] = router_7_25_to_router_6_25_req; - assign router_6_25_req_in[2] = router_6_24_to_router_6_25_req; - assign router_6_25_req_in[3] = router_5_25_to_router_6_25_req; - assign router_6_25_req_in[4] = magia_tile_ni_6_25_to_router_6_25_req; - - assign router_6_25_to_router_6_26_rsp = router_6_25_rsp_out[0]; - assign router_6_25_to_router_7_25_rsp = router_6_25_rsp_out[1]; - assign router_6_25_to_router_6_24_rsp = router_6_25_rsp_out[2]; - assign router_6_25_to_router_5_25_rsp = router_6_25_rsp_out[3]; - assign router_6_25_to_magia_tile_ni_6_25_rsp = router_6_25_rsp_out[4]; - - assign router_6_25_to_router_6_26_req = router_6_25_req_out[0]; - assign router_6_25_to_router_7_25_req = router_6_25_req_out[1]; - assign router_6_25_to_router_6_24_req = router_6_25_req_out[2]; - assign router_6_25_to_router_5_25_req = router_6_25_req_out[3]; - assign router_6_25_to_magia_tile_ni_6_25_req = router_6_25_req_out[4]; - - assign router_6_25_rsp_in[0] = router_6_26_to_router_6_25_rsp; - assign router_6_25_rsp_in[1] = router_7_25_to_router_6_25_rsp; - assign router_6_25_rsp_in[2] = router_6_24_to_router_6_25_rsp; - assign router_6_25_rsp_in[3] = router_5_25_to_router_6_25_rsp; - assign router_6_25_rsp_in[4] = magia_tile_ni_6_25_to_router_6_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_25_req_in), - .floo_rsp_o (router_6_25_rsp_out), - .floo_req_o (router_6_25_req_out), - .floo_rsp_i (router_6_25_rsp_in) -); - - -floo_req_t [4:0] router_6_26_req_in; -floo_rsp_t [4:0] router_6_26_rsp_out; -floo_req_t [4:0] router_6_26_req_out; -floo_rsp_t [4:0] router_6_26_rsp_in; - - assign router_6_26_req_in[0] = router_6_27_to_router_6_26_req; - assign router_6_26_req_in[1] = router_7_26_to_router_6_26_req; - assign router_6_26_req_in[2] = router_6_25_to_router_6_26_req; - assign router_6_26_req_in[3] = router_5_26_to_router_6_26_req; - assign router_6_26_req_in[4] = magia_tile_ni_6_26_to_router_6_26_req; - - assign router_6_26_to_router_6_27_rsp = router_6_26_rsp_out[0]; - assign router_6_26_to_router_7_26_rsp = router_6_26_rsp_out[1]; - assign router_6_26_to_router_6_25_rsp = router_6_26_rsp_out[2]; - assign router_6_26_to_router_5_26_rsp = router_6_26_rsp_out[3]; - assign router_6_26_to_magia_tile_ni_6_26_rsp = router_6_26_rsp_out[4]; - - assign router_6_26_to_router_6_27_req = router_6_26_req_out[0]; - assign router_6_26_to_router_7_26_req = router_6_26_req_out[1]; - assign router_6_26_to_router_6_25_req = router_6_26_req_out[2]; - assign router_6_26_to_router_5_26_req = router_6_26_req_out[3]; - assign router_6_26_to_magia_tile_ni_6_26_req = router_6_26_req_out[4]; - - assign router_6_26_rsp_in[0] = router_6_27_to_router_6_26_rsp; - assign router_6_26_rsp_in[1] = router_7_26_to_router_6_26_rsp; - assign router_6_26_rsp_in[2] = router_6_25_to_router_6_26_rsp; - assign router_6_26_rsp_in[3] = router_5_26_to_router_6_26_rsp; - assign router_6_26_rsp_in[4] = magia_tile_ni_6_26_to_router_6_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_26_req_in), - .floo_rsp_o (router_6_26_rsp_out), - .floo_req_o (router_6_26_req_out), - .floo_rsp_i (router_6_26_rsp_in) -); - - -floo_req_t [4:0] router_6_27_req_in; -floo_rsp_t [4:0] router_6_27_rsp_out; -floo_req_t [4:0] router_6_27_req_out; -floo_rsp_t [4:0] router_6_27_rsp_in; - - assign router_6_27_req_in[0] = router_6_28_to_router_6_27_req; - assign router_6_27_req_in[1] = router_7_27_to_router_6_27_req; - assign router_6_27_req_in[2] = router_6_26_to_router_6_27_req; - assign router_6_27_req_in[3] = router_5_27_to_router_6_27_req; - assign router_6_27_req_in[4] = magia_tile_ni_6_27_to_router_6_27_req; - - assign router_6_27_to_router_6_28_rsp = router_6_27_rsp_out[0]; - assign router_6_27_to_router_7_27_rsp = router_6_27_rsp_out[1]; - assign router_6_27_to_router_6_26_rsp = router_6_27_rsp_out[2]; - assign router_6_27_to_router_5_27_rsp = router_6_27_rsp_out[3]; - assign router_6_27_to_magia_tile_ni_6_27_rsp = router_6_27_rsp_out[4]; - - assign router_6_27_to_router_6_28_req = router_6_27_req_out[0]; - assign router_6_27_to_router_7_27_req = router_6_27_req_out[1]; - assign router_6_27_to_router_6_26_req = router_6_27_req_out[2]; - assign router_6_27_to_router_5_27_req = router_6_27_req_out[3]; - assign router_6_27_to_magia_tile_ni_6_27_req = router_6_27_req_out[4]; - - assign router_6_27_rsp_in[0] = router_6_28_to_router_6_27_rsp; - assign router_6_27_rsp_in[1] = router_7_27_to_router_6_27_rsp; - assign router_6_27_rsp_in[2] = router_6_26_to_router_6_27_rsp; - assign router_6_27_rsp_in[3] = router_5_27_to_router_6_27_rsp; - assign router_6_27_rsp_in[4] = magia_tile_ni_6_27_to_router_6_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_27_req_in), - .floo_rsp_o (router_6_27_rsp_out), - .floo_req_o (router_6_27_req_out), - .floo_rsp_i (router_6_27_rsp_in) -); - - -floo_req_t [4:0] router_6_28_req_in; -floo_rsp_t [4:0] router_6_28_rsp_out; -floo_req_t [4:0] router_6_28_req_out; -floo_rsp_t [4:0] router_6_28_rsp_in; - - assign router_6_28_req_in[0] = router_6_29_to_router_6_28_req; - assign router_6_28_req_in[1] = router_7_28_to_router_6_28_req; - assign router_6_28_req_in[2] = router_6_27_to_router_6_28_req; - assign router_6_28_req_in[3] = router_5_28_to_router_6_28_req; - assign router_6_28_req_in[4] = magia_tile_ni_6_28_to_router_6_28_req; - - assign router_6_28_to_router_6_29_rsp = router_6_28_rsp_out[0]; - assign router_6_28_to_router_7_28_rsp = router_6_28_rsp_out[1]; - assign router_6_28_to_router_6_27_rsp = router_6_28_rsp_out[2]; - assign router_6_28_to_router_5_28_rsp = router_6_28_rsp_out[3]; - assign router_6_28_to_magia_tile_ni_6_28_rsp = router_6_28_rsp_out[4]; - - assign router_6_28_to_router_6_29_req = router_6_28_req_out[0]; - assign router_6_28_to_router_7_28_req = router_6_28_req_out[1]; - assign router_6_28_to_router_6_27_req = router_6_28_req_out[2]; - assign router_6_28_to_router_5_28_req = router_6_28_req_out[3]; - assign router_6_28_to_magia_tile_ni_6_28_req = router_6_28_req_out[4]; - - assign router_6_28_rsp_in[0] = router_6_29_to_router_6_28_rsp; - assign router_6_28_rsp_in[1] = router_7_28_to_router_6_28_rsp; - assign router_6_28_rsp_in[2] = router_6_27_to_router_6_28_rsp; - assign router_6_28_rsp_in[3] = router_5_28_to_router_6_28_rsp; - assign router_6_28_rsp_in[4] = magia_tile_ni_6_28_to_router_6_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_28_req_in), - .floo_rsp_o (router_6_28_rsp_out), - .floo_req_o (router_6_28_req_out), - .floo_rsp_i (router_6_28_rsp_in) -); - - -floo_req_t [4:0] router_6_29_req_in; -floo_rsp_t [4:0] router_6_29_rsp_out; -floo_req_t [4:0] router_6_29_req_out; -floo_rsp_t [4:0] router_6_29_rsp_in; - - assign router_6_29_req_in[0] = router_6_30_to_router_6_29_req; - assign router_6_29_req_in[1] = router_7_29_to_router_6_29_req; - assign router_6_29_req_in[2] = router_6_28_to_router_6_29_req; - assign router_6_29_req_in[3] = router_5_29_to_router_6_29_req; - assign router_6_29_req_in[4] = magia_tile_ni_6_29_to_router_6_29_req; - - assign router_6_29_to_router_6_30_rsp = router_6_29_rsp_out[0]; - assign router_6_29_to_router_7_29_rsp = router_6_29_rsp_out[1]; - assign router_6_29_to_router_6_28_rsp = router_6_29_rsp_out[2]; - assign router_6_29_to_router_5_29_rsp = router_6_29_rsp_out[3]; - assign router_6_29_to_magia_tile_ni_6_29_rsp = router_6_29_rsp_out[4]; - - assign router_6_29_to_router_6_30_req = router_6_29_req_out[0]; - assign router_6_29_to_router_7_29_req = router_6_29_req_out[1]; - assign router_6_29_to_router_6_28_req = router_6_29_req_out[2]; - assign router_6_29_to_router_5_29_req = router_6_29_req_out[3]; - assign router_6_29_to_magia_tile_ni_6_29_req = router_6_29_req_out[4]; - - assign router_6_29_rsp_in[0] = router_6_30_to_router_6_29_rsp; - assign router_6_29_rsp_in[1] = router_7_29_to_router_6_29_rsp; - assign router_6_29_rsp_in[2] = router_6_28_to_router_6_29_rsp; - assign router_6_29_rsp_in[3] = router_5_29_to_router_6_29_rsp; - assign router_6_29_rsp_in[4] = magia_tile_ni_6_29_to_router_6_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_29_req_in), - .floo_rsp_o (router_6_29_rsp_out), - .floo_req_o (router_6_29_req_out), - .floo_rsp_i (router_6_29_rsp_in) -); - - -floo_req_t [4:0] router_6_30_req_in; -floo_rsp_t [4:0] router_6_30_rsp_out; -floo_req_t [4:0] router_6_30_req_out; -floo_rsp_t [4:0] router_6_30_rsp_in; - - assign router_6_30_req_in[0] = router_6_31_to_router_6_30_req; - assign router_6_30_req_in[1] = router_7_30_to_router_6_30_req; - assign router_6_30_req_in[2] = router_6_29_to_router_6_30_req; - assign router_6_30_req_in[3] = router_5_30_to_router_6_30_req; - assign router_6_30_req_in[4] = magia_tile_ni_6_30_to_router_6_30_req; - - assign router_6_30_to_router_6_31_rsp = router_6_30_rsp_out[0]; - assign router_6_30_to_router_7_30_rsp = router_6_30_rsp_out[1]; - assign router_6_30_to_router_6_29_rsp = router_6_30_rsp_out[2]; - assign router_6_30_to_router_5_30_rsp = router_6_30_rsp_out[3]; - assign router_6_30_to_magia_tile_ni_6_30_rsp = router_6_30_rsp_out[4]; - - assign router_6_30_to_router_6_31_req = router_6_30_req_out[0]; - assign router_6_30_to_router_7_30_req = router_6_30_req_out[1]; - assign router_6_30_to_router_6_29_req = router_6_30_req_out[2]; - assign router_6_30_to_router_5_30_req = router_6_30_req_out[3]; - assign router_6_30_to_magia_tile_ni_6_30_req = router_6_30_req_out[4]; - - assign router_6_30_rsp_in[0] = router_6_31_to_router_6_30_rsp; - assign router_6_30_rsp_in[1] = router_7_30_to_router_6_30_rsp; - assign router_6_30_rsp_in[2] = router_6_29_to_router_6_30_rsp; - assign router_6_30_rsp_in[3] = router_5_30_to_router_6_30_rsp; - assign router_6_30_rsp_in[4] = magia_tile_ni_6_30_to_router_6_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_30_req_in), - .floo_rsp_o (router_6_30_rsp_out), - .floo_req_o (router_6_30_req_out), - .floo_rsp_i (router_6_30_rsp_in) -); - - -floo_req_t [4:0] router_6_31_req_in; -floo_rsp_t [4:0] router_6_31_rsp_out; -floo_req_t [4:0] router_6_31_req_out; -floo_rsp_t [4:0] router_6_31_rsp_in; - - assign router_6_31_req_in[0] = '0; - assign router_6_31_req_in[1] = router_7_31_to_router_6_31_req; - assign router_6_31_req_in[2] = router_6_30_to_router_6_31_req; - assign router_6_31_req_in[3] = router_5_31_to_router_6_31_req; - assign router_6_31_req_in[4] = magia_tile_ni_6_31_to_router_6_31_req; - - assign router_6_31_to_router_7_31_rsp = router_6_31_rsp_out[1]; - assign router_6_31_to_router_6_30_rsp = router_6_31_rsp_out[2]; - assign router_6_31_to_router_5_31_rsp = router_6_31_rsp_out[3]; - assign router_6_31_to_magia_tile_ni_6_31_rsp = router_6_31_rsp_out[4]; - - assign router_6_31_to_router_7_31_req = router_6_31_req_out[1]; - assign router_6_31_to_router_6_30_req = router_6_31_req_out[2]; - assign router_6_31_to_router_5_31_req = router_6_31_req_out[3]; - assign router_6_31_to_magia_tile_ni_6_31_req = router_6_31_req_out[4]; - - assign router_6_31_rsp_in[0] = '0; - assign router_6_31_rsp_in[1] = router_7_31_to_router_6_31_rsp; - assign router_6_31_rsp_in[2] = router_6_30_to_router_6_31_rsp; - assign router_6_31_rsp_in[3] = router_5_31_to_router_6_31_rsp; - assign router_6_31_rsp_in[4] = magia_tile_ni_6_31_to_router_6_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_31_req_in), - .floo_rsp_o (router_6_31_rsp_out), - .floo_req_o (router_6_31_req_out), - .floo_rsp_i (router_6_31_rsp_in) -); - - -floo_req_t [4:0] router_7_0_req_in; -floo_rsp_t [4:0] router_7_0_rsp_out; -floo_req_t [4:0] router_7_0_req_out; -floo_rsp_t [4:0] router_7_0_rsp_in; - - assign router_7_0_req_in[0] = router_7_1_to_router_7_0_req; - assign router_7_0_req_in[1] = router_8_0_to_router_7_0_req; - assign router_7_0_req_in[2] = '0; - assign router_7_0_req_in[3] = router_6_0_to_router_7_0_req; - assign router_7_0_req_in[4] = magia_tile_ni_7_0_to_router_7_0_req; - - assign router_7_0_to_router_7_1_rsp = router_7_0_rsp_out[0]; - assign router_7_0_to_router_8_0_rsp = router_7_0_rsp_out[1]; - assign router_7_0_to_router_6_0_rsp = router_7_0_rsp_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_rsp = router_7_0_rsp_out[4]; - - assign router_7_0_to_router_7_1_req = router_7_0_req_out[0]; - assign router_7_0_to_router_8_0_req = router_7_0_req_out[1]; - assign router_7_0_to_router_6_0_req = router_7_0_req_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_req = router_7_0_req_out[4]; - - assign router_7_0_rsp_in[0] = router_7_1_to_router_7_0_rsp; - assign router_7_0_rsp_in[1] = router_8_0_to_router_7_0_rsp; - assign router_7_0_rsp_in[2] = '0; - assign router_7_0_rsp_in[3] = router_6_0_to_router_7_0_rsp; - assign router_7_0_rsp_in[4] = magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_0_req_in), - .floo_rsp_o (router_7_0_rsp_out), - .floo_req_o (router_7_0_req_out), - .floo_rsp_i (router_7_0_rsp_in) -); - - -floo_req_t [4:0] router_7_1_req_in; -floo_rsp_t [4:0] router_7_1_rsp_out; -floo_req_t [4:0] router_7_1_req_out; -floo_rsp_t [4:0] router_7_1_rsp_in; - - assign router_7_1_req_in[0] = router_7_2_to_router_7_1_req; - assign router_7_1_req_in[1] = router_8_1_to_router_7_1_req; - assign router_7_1_req_in[2] = router_7_0_to_router_7_1_req; - assign router_7_1_req_in[3] = router_6_1_to_router_7_1_req; - assign router_7_1_req_in[4] = magia_tile_ni_7_1_to_router_7_1_req; - - assign router_7_1_to_router_7_2_rsp = router_7_1_rsp_out[0]; - assign router_7_1_to_router_8_1_rsp = router_7_1_rsp_out[1]; - assign router_7_1_to_router_7_0_rsp = router_7_1_rsp_out[2]; - assign router_7_1_to_router_6_1_rsp = router_7_1_rsp_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_rsp = router_7_1_rsp_out[4]; - - assign router_7_1_to_router_7_2_req = router_7_1_req_out[0]; - assign router_7_1_to_router_8_1_req = router_7_1_req_out[1]; - assign router_7_1_to_router_7_0_req = router_7_1_req_out[2]; - assign router_7_1_to_router_6_1_req = router_7_1_req_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_req = router_7_1_req_out[4]; - - assign router_7_1_rsp_in[0] = router_7_2_to_router_7_1_rsp; - assign router_7_1_rsp_in[1] = router_8_1_to_router_7_1_rsp; - assign router_7_1_rsp_in[2] = router_7_0_to_router_7_1_rsp; - assign router_7_1_rsp_in[3] = router_6_1_to_router_7_1_rsp; - assign router_7_1_rsp_in[4] = magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_1_req_in), - .floo_rsp_o (router_7_1_rsp_out), - .floo_req_o (router_7_1_req_out), - .floo_rsp_i (router_7_1_rsp_in) -); - - -floo_req_t [4:0] router_7_2_req_in; -floo_rsp_t [4:0] router_7_2_rsp_out; -floo_req_t [4:0] router_7_2_req_out; -floo_rsp_t [4:0] router_7_2_rsp_in; - - assign router_7_2_req_in[0] = router_7_3_to_router_7_2_req; - assign router_7_2_req_in[1] = router_8_2_to_router_7_2_req; - assign router_7_2_req_in[2] = router_7_1_to_router_7_2_req; - assign router_7_2_req_in[3] = router_6_2_to_router_7_2_req; - assign router_7_2_req_in[4] = magia_tile_ni_7_2_to_router_7_2_req; - - assign router_7_2_to_router_7_3_rsp = router_7_2_rsp_out[0]; - assign router_7_2_to_router_8_2_rsp = router_7_2_rsp_out[1]; - assign router_7_2_to_router_7_1_rsp = router_7_2_rsp_out[2]; - assign router_7_2_to_router_6_2_rsp = router_7_2_rsp_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_rsp = router_7_2_rsp_out[4]; - - assign router_7_2_to_router_7_3_req = router_7_2_req_out[0]; - assign router_7_2_to_router_8_2_req = router_7_2_req_out[1]; - assign router_7_2_to_router_7_1_req = router_7_2_req_out[2]; - assign router_7_2_to_router_6_2_req = router_7_2_req_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_req = router_7_2_req_out[4]; - - assign router_7_2_rsp_in[0] = router_7_3_to_router_7_2_rsp; - assign router_7_2_rsp_in[1] = router_8_2_to_router_7_2_rsp; - assign router_7_2_rsp_in[2] = router_7_1_to_router_7_2_rsp; - assign router_7_2_rsp_in[3] = router_6_2_to_router_7_2_rsp; - assign router_7_2_rsp_in[4] = magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_2_req_in), - .floo_rsp_o (router_7_2_rsp_out), - .floo_req_o (router_7_2_req_out), - .floo_rsp_i (router_7_2_rsp_in) -); - - -floo_req_t [4:0] router_7_3_req_in; -floo_rsp_t [4:0] router_7_3_rsp_out; -floo_req_t [4:0] router_7_3_req_out; -floo_rsp_t [4:0] router_7_3_rsp_in; - - assign router_7_3_req_in[0] = router_7_4_to_router_7_3_req; - assign router_7_3_req_in[1] = router_8_3_to_router_7_3_req; - assign router_7_3_req_in[2] = router_7_2_to_router_7_3_req; - assign router_7_3_req_in[3] = router_6_3_to_router_7_3_req; - assign router_7_3_req_in[4] = magia_tile_ni_7_3_to_router_7_3_req; - - assign router_7_3_to_router_7_4_rsp = router_7_3_rsp_out[0]; - assign router_7_3_to_router_8_3_rsp = router_7_3_rsp_out[1]; - assign router_7_3_to_router_7_2_rsp = router_7_3_rsp_out[2]; - assign router_7_3_to_router_6_3_rsp = router_7_3_rsp_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_rsp = router_7_3_rsp_out[4]; - - assign router_7_3_to_router_7_4_req = router_7_3_req_out[0]; - assign router_7_3_to_router_8_3_req = router_7_3_req_out[1]; - assign router_7_3_to_router_7_2_req = router_7_3_req_out[2]; - assign router_7_3_to_router_6_3_req = router_7_3_req_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_req = router_7_3_req_out[4]; - - assign router_7_3_rsp_in[0] = router_7_4_to_router_7_3_rsp; - assign router_7_3_rsp_in[1] = router_8_3_to_router_7_3_rsp; - assign router_7_3_rsp_in[2] = router_7_2_to_router_7_3_rsp; - assign router_7_3_rsp_in[3] = router_6_3_to_router_7_3_rsp; - assign router_7_3_rsp_in[4] = magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_3_req_in), - .floo_rsp_o (router_7_3_rsp_out), - .floo_req_o (router_7_3_req_out), - .floo_rsp_i (router_7_3_rsp_in) -); - - -floo_req_t [4:0] router_7_4_req_in; -floo_rsp_t [4:0] router_7_4_rsp_out; -floo_req_t [4:0] router_7_4_req_out; -floo_rsp_t [4:0] router_7_4_rsp_in; - - assign router_7_4_req_in[0] = router_7_5_to_router_7_4_req; - assign router_7_4_req_in[1] = router_8_4_to_router_7_4_req; - assign router_7_4_req_in[2] = router_7_3_to_router_7_4_req; - assign router_7_4_req_in[3] = router_6_4_to_router_7_4_req; - assign router_7_4_req_in[4] = magia_tile_ni_7_4_to_router_7_4_req; - - assign router_7_4_to_router_7_5_rsp = router_7_4_rsp_out[0]; - assign router_7_4_to_router_8_4_rsp = router_7_4_rsp_out[1]; - assign router_7_4_to_router_7_3_rsp = router_7_4_rsp_out[2]; - assign router_7_4_to_router_6_4_rsp = router_7_4_rsp_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_rsp = router_7_4_rsp_out[4]; - - assign router_7_4_to_router_7_5_req = router_7_4_req_out[0]; - assign router_7_4_to_router_8_4_req = router_7_4_req_out[1]; - assign router_7_4_to_router_7_3_req = router_7_4_req_out[2]; - assign router_7_4_to_router_6_4_req = router_7_4_req_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_req = router_7_4_req_out[4]; - - assign router_7_4_rsp_in[0] = router_7_5_to_router_7_4_rsp; - assign router_7_4_rsp_in[1] = router_8_4_to_router_7_4_rsp; - assign router_7_4_rsp_in[2] = router_7_3_to_router_7_4_rsp; - assign router_7_4_rsp_in[3] = router_6_4_to_router_7_4_rsp; - assign router_7_4_rsp_in[4] = magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_4_req_in), - .floo_rsp_o (router_7_4_rsp_out), - .floo_req_o (router_7_4_req_out), - .floo_rsp_i (router_7_4_rsp_in) -); - - -floo_req_t [4:0] router_7_5_req_in; -floo_rsp_t [4:0] router_7_5_rsp_out; -floo_req_t [4:0] router_7_5_req_out; -floo_rsp_t [4:0] router_7_5_rsp_in; - - assign router_7_5_req_in[0] = router_7_6_to_router_7_5_req; - assign router_7_5_req_in[1] = router_8_5_to_router_7_5_req; - assign router_7_5_req_in[2] = router_7_4_to_router_7_5_req; - assign router_7_5_req_in[3] = router_6_5_to_router_7_5_req; - assign router_7_5_req_in[4] = magia_tile_ni_7_5_to_router_7_5_req; - - assign router_7_5_to_router_7_6_rsp = router_7_5_rsp_out[0]; - assign router_7_5_to_router_8_5_rsp = router_7_5_rsp_out[1]; - assign router_7_5_to_router_7_4_rsp = router_7_5_rsp_out[2]; - assign router_7_5_to_router_6_5_rsp = router_7_5_rsp_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_rsp = router_7_5_rsp_out[4]; - - assign router_7_5_to_router_7_6_req = router_7_5_req_out[0]; - assign router_7_5_to_router_8_5_req = router_7_5_req_out[1]; - assign router_7_5_to_router_7_4_req = router_7_5_req_out[2]; - assign router_7_5_to_router_6_5_req = router_7_5_req_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_req = router_7_5_req_out[4]; - - assign router_7_5_rsp_in[0] = router_7_6_to_router_7_5_rsp; - assign router_7_5_rsp_in[1] = router_8_5_to_router_7_5_rsp; - assign router_7_5_rsp_in[2] = router_7_4_to_router_7_5_rsp; - assign router_7_5_rsp_in[3] = router_6_5_to_router_7_5_rsp; - assign router_7_5_rsp_in[4] = magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_5_req_in), - .floo_rsp_o (router_7_5_rsp_out), - .floo_req_o (router_7_5_req_out), - .floo_rsp_i (router_7_5_rsp_in) -); - - -floo_req_t [4:0] router_7_6_req_in; -floo_rsp_t [4:0] router_7_6_rsp_out; -floo_req_t [4:0] router_7_6_req_out; -floo_rsp_t [4:0] router_7_6_rsp_in; - - assign router_7_6_req_in[0] = router_7_7_to_router_7_6_req; - assign router_7_6_req_in[1] = router_8_6_to_router_7_6_req; - assign router_7_6_req_in[2] = router_7_5_to_router_7_6_req; - assign router_7_6_req_in[3] = router_6_6_to_router_7_6_req; - assign router_7_6_req_in[4] = magia_tile_ni_7_6_to_router_7_6_req; - - assign router_7_6_to_router_7_7_rsp = router_7_6_rsp_out[0]; - assign router_7_6_to_router_8_6_rsp = router_7_6_rsp_out[1]; - assign router_7_6_to_router_7_5_rsp = router_7_6_rsp_out[2]; - assign router_7_6_to_router_6_6_rsp = router_7_6_rsp_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_rsp = router_7_6_rsp_out[4]; - - assign router_7_6_to_router_7_7_req = router_7_6_req_out[0]; - assign router_7_6_to_router_8_6_req = router_7_6_req_out[1]; - assign router_7_6_to_router_7_5_req = router_7_6_req_out[2]; - assign router_7_6_to_router_6_6_req = router_7_6_req_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_req = router_7_6_req_out[4]; - - assign router_7_6_rsp_in[0] = router_7_7_to_router_7_6_rsp; - assign router_7_6_rsp_in[1] = router_8_6_to_router_7_6_rsp; - assign router_7_6_rsp_in[2] = router_7_5_to_router_7_6_rsp; - assign router_7_6_rsp_in[3] = router_6_6_to_router_7_6_rsp; - assign router_7_6_rsp_in[4] = magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_6_req_in), - .floo_rsp_o (router_7_6_rsp_out), - .floo_req_o (router_7_6_req_out), - .floo_rsp_i (router_7_6_rsp_in) -); - - -floo_req_t [4:0] router_7_7_req_in; -floo_rsp_t [4:0] router_7_7_rsp_out; -floo_req_t [4:0] router_7_7_req_out; -floo_rsp_t [4:0] router_7_7_rsp_in; - - assign router_7_7_req_in[0] = router_7_8_to_router_7_7_req; - assign router_7_7_req_in[1] = router_8_7_to_router_7_7_req; - assign router_7_7_req_in[2] = router_7_6_to_router_7_7_req; - assign router_7_7_req_in[3] = router_6_7_to_router_7_7_req; - assign router_7_7_req_in[4] = magia_tile_ni_7_7_to_router_7_7_req; - - assign router_7_7_to_router_7_8_rsp = router_7_7_rsp_out[0]; - assign router_7_7_to_router_8_7_rsp = router_7_7_rsp_out[1]; - assign router_7_7_to_router_7_6_rsp = router_7_7_rsp_out[2]; - assign router_7_7_to_router_6_7_rsp = router_7_7_rsp_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_rsp = router_7_7_rsp_out[4]; - - assign router_7_7_to_router_7_8_req = router_7_7_req_out[0]; - assign router_7_7_to_router_8_7_req = router_7_7_req_out[1]; - assign router_7_7_to_router_7_6_req = router_7_7_req_out[2]; - assign router_7_7_to_router_6_7_req = router_7_7_req_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_req = router_7_7_req_out[4]; - - assign router_7_7_rsp_in[0] = router_7_8_to_router_7_7_rsp; - assign router_7_7_rsp_in[1] = router_8_7_to_router_7_7_rsp; - assign router_7_7_rsp_in[2] = router_7_6_to_router_7_7_rsp; - assign router_7_7_rsp_in[3] = router_6_7_to_router_7_7_rsp; - assign router_7_7_rsp_in[4] = magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_7_req_in), - .floo_rsp_o (router_7_7_rsp_out), - .floo_req_o (router_7_7_req_out), - .floo_rsp_i (router_7_7_rsp_in) -); - - -floo_req_t [4:0] router_7_8_req_in; -floo_rsp_t [4:0] router_7_8_rsp_out; -floo_req_t [4:0] router_7_8_req_out; -floo_rsp_t [4:0] router_7_8_rsp_in; - - assign router_7_8_req_in[0] = router_7_9_to_router_7_8_req; - assign router_7_8_req_in[1] = router_8_8_to_router_7_8_req; - assign router_7_8_req_in[2] = router_7_7_to_router_7_8_req; - assign router_7_8_req_in[3] = router_6_8_to_router_7_8_req; - assign router_7_8_req_in[4] = magia_tile_ni_7_8_to_router_7_8_req; - - assign router_7_8_to_router_7_9_rsp = router_7_8_rsp_out[0]; - assign router_7_8_to_router_8_8_rsp = router_7_8_rsp_out[1]; - assign router_7_8_to_router_7_7_rsp = router_7_8_rsp_out[2]; - assign router_7_8_to_router_6_8_rsp = router_7_8_rsp_out[3]; - assign router_7_8_to_magia_tile_ni_7_8_rsp = router_7_8_rsp_out[4]; - - assign router_7_8_to_router_7_9_req = router_7_8_req_out[0]; - assign router_7_8_to_router_8_8_req = router_7_8_req_out[1]; - assign router_7_8_to_router_7_7_req = router_7_8_req_out[2]; - assign router_7_8_to_router_6_8_req = router_7_8_req_out[3]; - assign router_7_8_to_magia_tile_ni_7_8_req = router_7_8_req_out[4]; - - assign router_7_8_rsp_in[0] = router_7_9_to_router_7_8_rsp; - assign router_7_8_rsp_in[1] = router_8_8_to_router_7_8_rsp; - assign router_7_8_rsp_in[2] = router_7_7_to_router_7_8_rsp; - assign router_7_8_rsp_in[3] = router_6_8_to_router_7_8_rsp; - assign router_7_8_rsp_in[4] = magia_tile_ni_7_8_to_router_7_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_8_req_in), - .floo_rsp_o (router_7_8_rsp_out), - .floo_req_o (router_7_8_req_out), - .floo_rsp_i (router_7_8_rsp_in) -); - - -floo_req_t [4:0] router_7_9_req_in; -floo_rsp_t [4:0] router_7_9_rsp_out; -floo_req_t [4:0] router_7_9_req_out; -floo_rsp_t [4:0] router_7_9_rsp_in; - - assign router_7_9_req_in[0] = router_7_10_to_router_7_9_req; - assign router_7_9_req_in[1] = router_8_9_to_router_7_9_req; - assign router_7_9_req_in[2] = router_7_8_to_router_7_9_req; - assign router_7_9_req_in[3] = router_6_9_to_router_7_9_req; - assign router_7_9_req_in[4] = magia_tile_ni_7_9_to_router_7_9_req; - - assign router_7_9_to_router_7_10_rsp = router_7_9_rsp_out[0]; - assign router_7_9_to_router_8_9_rsp = router_7_9_rsp_out[1]; - assign router_7_9_to_router_7_8_rsp = router_7_9_rsp_out[2]; - assign router_7_9_to_router_6_9_rsp = router_7_9_rsp_out[3]; - assign router_7_9_to_magia_tile_ni_7_9_rsp = router_7_9_rsp_out[4]; - - assign router_7_9_to_router_7_10_req = router_7_9_req_out[0]; - assign router_7_9_to_router_8_9_req = router_7_9_req_out[1]; - assign router_7_9_to_router_7_8_req = router_7_9_req_out[2]; - assign router_7_9_to_router_6_9_req = router_7_9_req_out[3]; - assign router_7_9_to_magia_tile_ni_7_9_req = router_7_9_req_out[4]; - - assign router_7_9_rsp_in[0] = router_7_10_to_router_7_9_rsp; - assign router_7_9_rsp_in[1] = router_8_9_to_router_7_9_rsp; - assign router_7_9_rsp_in[2] = router_7_8_to_router_7_9_rsp; - assign router_7_9_rsp_in[3] = router_6_9_to_router_7_9_rsp; - assign router_7_9_rsp_in[4] = magia_tile_ni_7_9_to_router_7_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_9_req_in), - .floo_rsp_o (router_7_9_rsp_out), - .floo_req_o (router_7_9_req_out), - .floo_rsp_i (router_7_9_rsp_in) -); - - -floo_req_t [4:0] router_7_10_req_in; -floo_rsp_t [4:0] router_7_10_rsp_out; -floo_req_t [4:0] router_7_10_req_out; -floo_rsp_t [4:0] router_7_10_rsp_in; - - assign router_7_10_req_in[0] = router_7_11_to_router_7_10_req; - assign router_7_10_req_in[1] = router_8_10_to_router_7_10_req; - assign router_7_10_req_in[2] = router_7_9_to_router_7_10_req; - assign router_7_10_req_in[3] = router_6_10_to_router_7_10_req; - assign router_7_10_req_in[4] = magia_tile_ni_7_10_to_router_7_10_req; - - assign router_7_10_to_router_7_11_rsp = router_7_10_rsp_out[0]; - assign router_7_10_to_router_8_10_rsp = router_7_10_rsp_out[1]; - assign router_7_10_to_router_7_9_rsp = router_7_10_rsp_out[2]; - assign router_7_10_to_router_6_10_rsp = router_7_10_rsp_out[3]; - assign router_7_10_to_magia_tile_ni_7_10_rsp = router_7_10_rsp_out[4]; - - assign router_7_10_to_router_7_11_req = router_7_10_req_out[0]; - assign router_7_10_to_router_8_10_req = router_7_10_req_out[1]; - assign router_7_10_to_router_7_9_req = router_7_10_req_out[2]; - assign router_7_10_to_router_6_10_req = router_7_10_req_out[3]; - assign router_7_10_to_magia_tile_ni_7_10_req = router_7_10_req_out[4]; - - assign router_7_10_rsp_in[0] = router_7_11_to_router_7_10_rsp; - assign router_7_10_rsp_in[1] = router_8_10_to_router_7_10_rsp; - assign router_7_10_rsp_in[2] = router_7_9_to_router_7_10_rsp; - assign router_7_10_rsp_in[3] = router_6_10_to_router_7_10_rsp; - assign router_7_10_rsp_in[4] = magia_tile_ni_7_10_to_router_7_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_10_req_in), - .floo_rsp_o (router_7_10_rsp_out), - .floo_req_o (router_7_10_req_out), - .floo_rsp_i (router_7_10_rsp_in) -); - - -floo_req_t [4:0] router_7_11_req_in; -floo_rsp_t [4:0] router_7_11_rsp_out; -floo_req_t [4:0] router_7_11_req_out; -floo_rsp_t [4:0] router_7_11_rsp_in; - - assign router_7_11_req_in[0] = router_7_12_to_router_7_11_req; - assign router_7_11_req_in[1] = router_8_11_to_router_7_11_req; - assign router_7_11_req_in[2] = router_7_10_to_router_7_11_req; - assign router_7_11_req_in[3] = router_6_11_to_router_7_11_req; - assign router_7_11_req_in[4] = magia_tile_ni_7_11_to_router_7_11_req; - - assign router_7_11_to_router_7_12_rsp = router_7_11_rsp_out[0]; - assign router_7_11_to_router_8_11_rsp = router_7_11_rsp_out[1]; - assign router_7_11_to_router_7_10_rsp = router_7_11_rsp_out[2]; - assign router_7_11_to_router_6_11_rsp = router_7_11_rsp_out[3]; - assign router_7_11_to_magia_tile_ni_7_11_rsp = router_7_11_rsp_out[4]; - - assign router_7_11_to_router_7_12_req = router_7_11_req_out[0]; - assign router_7_11_to_router_8_11_req = router_7_11_req_out[1]; - assign router_7_11_to_router_7_10_req = router_7_11_req_out[2]; - assign router_7_11_to_router_6_11_req = router_7_11_req_out[3]; - assign router_7_11_to_magia_tile_ni_7_11_req = router_7_11_req_out[4]; - - assign router_7_11_rsp_in[0] = router_7_12_to_router_7_11_rsp; - assign router_7_11_rsp_in[1] = router_8_11_to_router_7_11_rsp; - assign router_7_11_rsp_in[2] = router_7_10_to_router_7_11_rsp; - assign router_7_11_rsp_in[3] = router_6_11_to_router_7_11_rsp; - assign router_7_11_rsp_in[4] = magia_tile_ni_7_11_to_router_7_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_11_req_in), - .floo_rsp_o (router_7_11_rsp_out), - .floo_req_o (router_7_11_req_out), - .floo_rsp_i (router_7_11_rsp_in) -); - - -floo_req_t [4:0] router_7_12_req_in; -floo_rsp_t [4:0] router_7_12_rsp_out; -floo_req_t [4:0] router_7_12_req_out; -floo_rsp_t [4:0] router_7_12_rsp_in; - - assign router_7_12_req_in[0] = router_7_13_to_router_7_12_req; - assign router_7_12_req_in[1] = router_8_12_to_router_7_12_req; - assign router_7_12_req_in[2] = router_7_11_to_router_7_12_req; - assign router_7_12_req_in[3] = router_6_12_to_router_7_12_req; - assign router_7_12_req_in[4] = magia_tile_ni_7_12_to_router_7_12_req; - - assign router_7_12_to_router_7_13_rsp = router_7_12_rsp_out[0]; - assign router_7_12_to_router_8_12_rsp = router_7_12_rsp_out[1]; - assign router_7_12_to_router_7_11_rsp = router_7_12_rsp_out[2]; - assign router_7_12_to_router_6_12_rsp = router_7_12_rsp_out[3]; - assign router_7_12_to_magia_tile_ni_7_12_rsp = router_7_12_rsp_out[4]; - - assign router_7_12_to_router_7_13_req = router_7_12_req_out[0]; - assign router_7_12_to_router_8_12_req = router_7_12_req_out[1]; - assign router_7_12_to_router_7_11_req = router_7_12_req_out[2]; - assign router_7_12_to_router_6_12_req = router_7_12_req_out[3]; - assign router_7_12_to_magia_tile_ni_7_12_req = router_7_12_req_out[4]; - - assign router_7_12_rsp_in[0] = router_7_13_to_router_7_12_rsp; - assign router_7_12_rsp_in[1] = router_8_12_to_router_7_12_rsp; - assign router_7_12_rsp_in[2] = router_7_11_to_router_7_12_rsp; - assign router_7_12_rsp_in[3] = router_6_12_to_router_7_12_rsp; - assign router_7_12_rsp_in[4] = magia_tile_ni_7_12_to_router_7_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_12_req_in), - .floo_rsp_o (router_7_12_rsp_out), - .floo_req_o (router_7_12_req_out), - .floo_rsp_i (router_7_12_rsp_in) -); - - -floo_req_t [4:0] router_7_13_req_in; -floo_rsp_t [4:0] router_7_13_rsp_out; -floo_req_t [4:0] router_7_13_req_out; -floo_rsp_t [4:0] router_7_13_rsp_in; - - assign router_7_13_req_in[0] = router_7_14_to_router_7_13_req; - assign router_7_13_req_in[1] = router_8_13_to_router_7_13_req; - assign router_7_13_req_in[2] = router_7_12_to_router_7_13_req; - assign router_7_13_req_in[3] = router_6_13_to_router_7_13_req; - assign router_7_13_req_in[4] = magia_tile_ni_7_13_to_router_7_13_req; - - assign router_7_13_to_router_7_14_rsp = router_7_13_rsp_out[0]; - assign router_7_13_to_router_8_13_rsp = router_7_13_rsp_out[1]; - assign router_7_13_to_router_7_12_rsp = router_7_13_rsp_out[2]; - assign router_7_13_to_router_6_13_rsp = router_7_13_rsp_out[3]; - assign router_7_13_to_magia_tile_ni_7_13_rsp = router_7_13_rsp_out[4]; - - assign router_7_13_to_router_7_14_req = router_7_13_req_out[0]; - assign router_7_13_to_router_8_13_req = router_7_13_req_out[1]; - assign router_7_13_to_router_7_12_req = router_7_13_req_out[2]; - assign router_7_13_to_router_6_13_req = router_7_13_req_out[3]; - assign router_7_13_to_magia_tile_ni_7_13_req = router_7_13_req_out[4]; - - assign router_7_13_rsp_in[0] = router_7_14_to_router_7_13_rsp; - assign router_7_13_rsp_in[1] = router_8_13_to_router_7_13_rsp; - assign router_7_13_rsp_in[2] = router_7_12_to_router_7_13_rsp; - assign router_7_13_rsp_in[3] = router_6_13_to_router_7_13_rsp; - assign router_7_13_rsp_in[4] = magia_tile_ni_7_13_to_router_7_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_13_req_in), - .floo_rsp_o (router_7_13_rsp_out), - .floo_req_o (router_7_13_req_out), - .floo_rsp_i (router_7_13_rsp_in) -); - - -floo_req_t [4:0] router_7_14_req_in; -floo_rsp_t [4:0] router_7_14_rsp_out; -floo_req_t [4:0] router_7_14_req_out; -floo_rsp_t [4:0] router_7_14_rsp_in; - - assign router_7_14_req_in[0] = router_7_15_to_router_7_14_req; - assign router_7_14_req_in[1] = router_8_14_to_router_7_14_req; - assign router_7_14_req_in[2] = router_7_13_to_router_7_14_req; - assign router_7_14_req_in[3] = router_6_14_to_router_7_14_req; - assign router_7_14_req_in[4] = magia_tile_ni_7_14_to_router_7_14_req; - - assign router_7_14_to_router_7_15_rsp = router_7_14_rsp_out[0]; - assign router_7_14_to_router_8_14_rsp = router_7_14_rsp_out[1]; - assign router_7_14_to_router_7_13_rsp = router_7_14_rsp_out[2]; - assign router_7_14_to_router_6_14_rsp = router_7_14_rsp_out[3]; - assign router_7_14_to_magia_tile_ni_7_14_rsp = router_7_14_rsp_out[4]; - - assign router_7_14_to_router_7_15_req = router_7_14_req_out[0]; - assign router_7_14_to_router_8_14_req = router_7_14_req_out[1]; - assign router_7_14_to_router_7_13_req = router_7_14_req_out[2]; - assign router_7_14_to_router_6_14_req = router_7_14_req_out[3]; - assign router_7_14_to_magia_tile_ni_7_14_req = router_7_14_req_out[4]; - - assign router_7_14_rsp_in[0] = router_7_15_to_router_7_14_rsp; - assign router_7_14_rsp_in[1] = router_8_14_to_router_7_14_rsp; - assign router_7_14_rsp_in[2] = router_7_13_to_router_7_14_rsp; - assign router_7_14_rsp_in[3] = router_6_14_to_router_7_14_rsp; - assign router_7_14_rsp_in[4] = magia_tile_ni_7_14_to_router_7_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_14_req_in), - .floo_rsp_o (router_7_14_rsp_out), - .floo_req_o (router_7_14_req_out), - .floo_rsp_i (router_7_14_rsp_in) -); - - -floo_req_t [4:0] router_7_15_req_in; -floo_rsp_t [4:0] router_7_15_rsp_out; -floo_req_t [4:0] router_7_15_req_out; -floo_rsp_t [4:0] router_7_15_rsp_in; - - assign router_7_15_req_in[0] = router_7_16_to_router_7_15_req; - assign router_7_15_req_in[1] = router_8_15_to_router_7_15_req; - assign router_7_15_req_in[2] = router_7_14_to_router_7_15_req; - assign router_7_15_req_in[3] = router_6_15_to_router_7_15_req; - assign router_7_15_req_in[4] = magia_tile_ni_7_15_to_router_7_15_req; - - assign router_7_15_to_router_7_16_rsp = router_7_15_rsp_out[0]; - assign router_7_15_to_router_8_15_rsp = router_7_15_rsp_out[1]; - assign router_7_15_to_router_7_14_rsp = router_7_15_rsp_out[2]; - assign router_7_15_to_router_6_15_rsp = router_7_15_rsp_out[3]; - assign router_7_15_to_magia_tile_ni_7_15_rsp = router_7_15_rsp_out[4]; - - assign router_7_15_to_router_7_16_req = router_7_15_req_out[0]; - assign router_7_15_to_router_8_15_req = router_7_15_req_out[1]; - assign router_7_15_to_router_7_14_req = router_7_15_req_out[2]; - assign router_7_15_to_router_6_15_req = router_7_15_req_out[3]; - assign router_7_15_to_magia_tile_ni_7_15_req = router_7_15_req_out[4]; - - assign router_7_15_rsp_in[0] = router_7_16_to_router_7_15_rsp; - assign router_7_15_rsp_in[1] = router_8_15_to_router_7_15_rsp; - assign router_7_15_rsp_in[2] = router_7_14_to_router_7_15_rsp; - assign router_7_15_rsp_in[3] = router_6_15_to_router_7_15_rsp; - assign router_7_15_rsp_in[4] = magia_tile_ni_7_15_to_router_7_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_15_req_in), - .floo_rsp_o (router_7_15_rsp_out), - .floo_req_o (router_7_15_req_out), - .floo_rsp_i (router_7_15_rsp_in) -); - - -floo_req_t [4:0] router_7_16_req_in; -floo_rsp_t [4:0] router_7_16_rsp_out; -floo_req_t [4:0] router_7_16_req_out; -floo_rsp_t [4:0] router_7_16_rsp_in; - - assign router_7_16_req_in[0] = router_7_17_to_router_7_16_req; - assign router_7_16_req_in[1] = router_8_16_to_router_7_16_req; - assign router_7_16_req_in[2] = router_7_15_to_router_7_16_req; - assign router_7_16_req_in[3] = router_6_16_to_router_7_16_req; - assign router_7_16_req_in[4] = magia_tile_ni_7_16_to_router_7_16_req; - - assign router_7_16_to_router_7_17_rsp = router_7_16_rsp_out[0]; - assign router_7_16_to_router_8_16_rsp = router_7_16_rsp_out[1]; - assign router_7_16_to_router_7_15_rsp = router_7_16_rsp_out[2]; - assign router_7_16_to_router_6_16_rsp = router_7_16_rsp_out[3]; - assign router_7_16_to_magia_tile_ni_7_16_rsp = router_7_16_rsp_out[4]; - - assign router_7_16_to_router_7_17_req = router_7_16_req_out[0]; - assign router_7_16_to_router_8_16_req = router_7_16_req_out[1]; - assign router_7_16_to_router_7_15_req = router_7_16_req_out[2]; - assign router_7_16_to_router_6_16_req = router_7_16_req_out[3]; - assign router_7_16_to_magia_tile_ni_7_16_req = router_7_16_req_out[4]; - - assign router_7_16_rsp_in[0] = router_7_17_to_router_7_16_rsp; - assign router_7_16_rsp_in[1] = router_8_16_to_router_7_16_rsp; - assign router_7_16_rsp_in[2] = router_7_15_to_router_7_16_rsp; - assign router_7_16_rsp_in[3] = router_6_16_to_router_7_16_rsp; - assign router_7_16_rsp_in[4] = magia_tile_ni_7_16_to_router_7_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_16_req_in), - .floo_rsp_o (router_7_16_rsp_out), - .floo_req_o (router_7_16_req_out), - .floo_rsp_i (router_7_16_rsp_in) -); - - -floo_req_t [4:0] router_7_17_req_in; -floo_rsp_t [4:0] router_7_17_rsp_out; -floo_req_t [4:0] router_7_17_req_out; -floo_rsp_t [4:0] router_7_17_rsp_in; - - assign router_7_17_req_in[0] = router_7_18_to_router_7_17_req; - assign router_7_17_req_in[1] = router_8_17_to_router_7_17_req; - assign router_7_17_req_in[2] = router_7_16_to_router_7_17_req; - assign router_7_17_req_in[3] = router_6_17_to_router_7_17_req; - assign router_7_17_req_in[4] = magia_tile_ni_7_17_to_router_7_17_req; - - assign router_7_17_to_router_7_18_rsp = router_7_17_rsp_out[0]; - assign router_7_17_to_router_8_17_rsp = router_7_17_rsp_out[1]; - assign router_7_17_to_router_7_16_rsp = router_7_17_rsp_out[2]; - assign router_7_17_to_router_6_17_rsp = router_7_17_rsp_out[3]; - assign router_7_17_to_magia_tile_ni_7_17_rsp = router_7_17_rsp_out[4]; - - assign router_7_17_to_router_7_18_req = router_7_17_req_out[0]; - assign router_7_17_to_router_8_17_req = router_7_17_req_out[1]; - assign router_7_17_to_router_7_16_req = router_7_17_req_out[2]; - assign router_7_17_to_router_6_17_req = router_7_17_req_out[3]; - assign router_7_17_to_magia_tile_ni_7_17_req = router_7_17_req_out[4]; - - assign router_7_17_rsp_in[0] = router_7_18_to_router_7_17_rsp; - assign router_7_17_rsp_in[1] = router_8_17_to_router_7_17_rsp; - assign router_7_17_rsp_in[2] = router_7_16_to_router_7_17_rsp; - assign router_7_17_rsp_in[3] = router_6_17_to_router_7_17_rsp; - assign router_7_17_rsp_in[4] = magia_tile_ni_7_17_to_router_7_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_17_req_in), - .floo_rsp_o (router_7_17_rsp_out), - .floo_req_o (router_7_17_req_out), - .floo_rsp_i (router_7_17_rsp_in) -); - - -floo_req_t [4:0] router_7_18_req_in; -floo_rsp_t [4:0] router_7_18_rsp_out; -floo_req_t [4:0] router_7_18_req_out; -floo_rsp_t [4:0] router_7_18_rsp_in; - - assign router_7_18_req_in[0] = router_7_19_to_router_7_18_req; - assign router_7_18_req_in[1] = router_8_18_to_router_7_18_req; - assign router_7_18_req_in[2] = router_7_17_to_router_7_18_req; - assign router_7_18_req_in[3] = router_6_18_to_router_7_18_req; - assign router_7_18_req_in[4] = magia_tile_ni_7_18_to_router_7_18_req; - - assign router_7_18_to_router_7_19_rsp = router_7_18_rsp_out[0]; - assign router_7_18_to_router_8_18_rsp = router_7_18_rsp_out[1]; - assign router_7_18_to_router_7_17_rsp = router_7_18_rsp_out[2]; - assign router_7_18_to_router_6_18_rsp = router_7_18_rsp_out[3]; - assign router_7_18_to_magia_tile_ni_7_18_rsp = router_7_18_rsp_out[4]; - - assign router_7_18_to_router_7_19_req = router_7_18_req_out[0]; - assign router_7_18_to_router_8_18_req = router_7_18_req_out[1]; - assign router_7_18_to_router_7_17_req = router_7_18_req_out[2]; - assign router_7_18_to_router_6_18_req = router_7_18_req_out[3]; - assign router_7_18_to_magia_tile_ni_7_18_req = router_7_18_req_out[4]; - - assign router_7_18_rsp_in[0] = router_7_19_to_router_7_18_rsp; - assign router_7_18_rsp_in[1] = router_8_18_to_router_7_18_rsp; - assign router_7_18_rsp_in[2] = router_7_17_to_router_7_18_rsp; - assign router_7_18_rsp_in[3] = router_6_18_to_router_7_18_rsp; - assign router_7_18_rsp_in[4] = magia_tile_ni_7_18_to_router_7_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_18_req_in), - .floo_rsp_o (router_7_18_rsp_out), - .floo_req_o (router_7_18_req_out), - .floo_rsp_i (router_7_18_rsp_in) -); - - -floo_req_t [4:0] router_7_19_req_in; -floo_rsp_t [4:0] router_7_19_rsp_out; -floo_req_t [4:0] router_7_19_req_out; -floo_rsp_t [4:0] router_7_19_rsp_in; - - assign router_7_19_req_in[0] = router_7_20_to_router_7_19_req; - assign router_7_19_req_in[1] = router_8_19_to_router_7_19_req; - assign router_7_19_req_in[2] = router_7_18_to_router_7_19_req; - assign router_7_19_req_in[3] = router_6_19_to_router_7_19_req; - assign router_7_19_req_in[4] = magia_tile_ni_7_19_to_router_7_19_req; - - assign router_7_19_to_router_7_20_rsp = router_7_19_rsp_out[0]; - assign router_7_19_to_router_8_19_rsp = router_7_19_rsp_out[1]; - assign router_7_19_to_router_7_18_rsp = router_7_19_rsp_out[2]; - assign router_7_19_to_router_6_19_rsp = router_7_19_rsp_out[3]; - assign router_7_19_to_magia_tile_ni_7_19_rsp = router_7_19_rsp_out[4]; - - assign router_7_19_to_router_7_20_req = router_7_19_req_out[0]; - assign router_7_19_to_router_8_19_req = router_7_19_req_out[1]; - assign router_7_19_to_router_7_18_req = router_7_19_req_out[2]; - assign router_7_19_to_router_6_19_req = router_7_19_req_out[3]; - assign router_7_19_to_magia_tile_ni_7_19_req = router_7_19_req_out[4]; - - assign router_7_19_rsp_in[0] = router_7_20_to_router_7_19_rsp; - assign router_7_19_rsp_in[1] = router_8_19_to_router_7_19_rsp; - assign router_7_19_rsp_in[2] = router_7_18_to_router_7_19_rsp; - assign router_7_19_rsp_in[3] = router_6_19_to_router_7_19_rsp; - assign router_7_19_rsp_in[4] = magia_tile_ni_7_19_to_router_7_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_19_req_in), - .floo_rsp_o (router_7_19_rsp_out), - .floo_req_o (router_7_19_req_out), - .floo_rsp_i (router_7_19_rsp_in) -); - - -floo_req_t [4:0] router_7_20_req_in; -floo_rsp_t [4:0] router_7_20_rsp_out; -floo_req_t [4:0] router_7_20_req_out; -floo_rsp_t [4:0] router_7_20_rsp_in; - - assign router_7_20_req_in[0] = router_7_21_to_router_7_20_req; - assign router_7_20_req_in[1] = router_8_20_to_router_7_20_req; - assign router_7_20_req_in[2] = router_7_19_to_router_7_20_req; - assign router_7_20_req_in[3] = router_6_20_to_router_7_20_req; - assign router_7_20_req_in[4] = magia_tile_ni_7_20_to_router_7_20_req; - - assign router_7_20_to_router_7_21_rsp = router_7_20_rsp_out[0]; - assign router_7_20_to_router_8_20_rsp = router_7_20_rsp_out[1]; - assign router_7_20_to_router_7_19_rsp = router_7_20_rsp_out[2]; - assign router_7_20_to_router_6_20_rsp = router_7_20_rsp_out[3]; - assign router_7_20_to_magia_tile_ni_7_20_rsp = router_7_20_rsp_out[4]; - - assign router_7_20_to_router_7_21_req = router_7_20_req_out[0]; - assign router_7_20_to_router_8_20_req = router_7_20_req_out[1]; - assign router_7_20_to_router_7_19_req = router_7_20_req_out[2]; - assign router_7_20_to_router_6_20_req = router_7_20_req_out[3]; - assign router_7_20_to_magia_tile_ni_7_20_req = router_7_20_req_out[4]; - - assign router_7_20_rsp_in[0] = router_7_21_to_router_7_20_rsp; - assign router_7_20_rsp_in[1] = router_8_20_to_router_7_20_rsp; - assign router_7_20_rsp_in[2] = router_7_19_to_router_7_20_rsp; - assign router_7_20_rsp_in[3] = router_6_20_to_router_7_20_rsp; - assign router_7_20_rsp_in[4] = magia_tile_ni_7_20_to_router_7_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_20_req_in), - .floo_rsp_o (router_7_20_rsp_out), - .floo_req_o (router_7_20_req_out), - .floo_rsp_i (router_7_20_rsp_in) -); - - -floo_req_t [4:0] router_7_21_req_in; -floo_rsp_t [4:0] router_7_21_rsp_out; -floo_req_t [4:0] router_7_21_req_out; -floo_rsp_t [4:0] router_7_21_rsp_in; - - assign router_7_21_req_in[0] = router_7_22_to_router_7_21_req; - assign router_7_21_req_in[1] = router_8_21_to_router_7_21_req; - assign router_7_21_req_in[2] = router_7_20_to_router_7_21_req; - assign router_7_21_req_in[3] = router_6_21_to_router_7_21_req; - assign router_7_21_req_in[4] = magia_tile_ni_7_21_to_router_7_21_req; - - assign router_7_21_to_router_7_22_rsp = router_7_21_rsp_out[0]; - assign router_7_21_to_router_8_21_rsp = router_7_21_rsp_out[1]; - assign router_7_21_to_router_7_20_rsp = router_7_21_rsp_out[2]; - assign router_7_21_to_router_6_21_rsp = router_7_21_rsp_out[3]; - assign router_7_21_to_magia_tile_ni_7_21_rsp = router_7_21_rsp_out[4]; - - assign router_7_21_to_router_7_22_req = router_7_21_req_out[0]; - assign router_7_21_to_router_8_21_req = router_7_21_req_out[1]; - assign router_7_21_to_router_7_20_req = router_7_21_req_out[2]; - assign router_7_21_to_router_6_21_req = router_7_21_req_out[3]; - assign router_7_21_to_magia_tile_ni_7_21_req = router_7_21_req_out[4]; - - assign router_7_21_rsp_in[0] = router_7_22_to_router_7_21_rsp; - assign router_7_21_rsp_in[1] = router_8_21_to_router_7_21_rsp; - assign router_7_21_rsp_in[2] = router_7_20_to_router_7_21_rsp; - assign router_7_21_rsp_in[3] = router_6_21_to_router_7_21_rsp; - assign router_7_21_rsp_in[4] = magia_tile_ni_7_21_to_router_7_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_21_req_in), - .floo_rsp_o (router_7_21_rsp_out), - .floo_req_o (router_7_21_req_out), - .floo_rsp_i (router_7_21_rsp_in) -); - - -floo_req_t [4:0] router_7_22_req_in; -floo_rsp_t [4:0] router_7_22_rsp_out; -floo_req_t [4:0] router_7_22_req_out; -floo_rsp_t [4:0] router_7_22_rsp_in; - - assign router_7_22_req_in[0] = router_7_23_to_router_7_22_req; - assign router_7_22_req_in[1] = router_8_22_to_router_7_22_req; - assign router_7_22_req_in[2] = router_7_21_to_router_7_22_req; - assign router_7_22_req_in[3] = router_6_22_to_router_7_22_req; - assign router_7_22_req_in[4] = magia_tile_ni_7_22_to_router_7_22_req; - - assign router_7_22_to_router_7_23_rsp = router_7_22_rsp_out[0]; - assign router_7_22_to_router_8_22_rsp = router_7_22_rsp_out[1]; - assign router_7_22_to_router_7_21_rsp = router_7_22_rsp_out[2]; - assign router_7_22_to_router_6_22_rsp = router_7_22_rsp_out[3]; - assign router_7_22_to_magia_tile_ni_7_22_rsp = router_7_22_rsp_out[4]; - - assign router_7_22_to_router_7_23_req = router_7_22_req_out[0]; - assign router_7_22_to_router_8_22_req = router_7_22_req_out[1]; - assign router_7_22_to_router_7_21_req = router_7_22_req_out[2]; - assign router_7_22_to_router_6_22_req = router_7_22_req_out[3]; - assign router_7_22_to_magia_tile_ni_7_22_req = router_7_22_req_out[4]; - - assign router_7_22_rsp_in[0] = router_7_23_to_router_7_22_rsp; - assign router_7_22_rsp_in[1] = router_8_22_to_router_7_22_rsp; - assign router_7_22_rsp_in[2] = router_7_21_to_router_7_22_rsp; - assign router_7_22_rsp_in[3] = router_6_22_to_router_7_22_rsp; - assign router_7_22_rsp_in[4] = magia_tile_ni_7_22_to_router_7_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_22_req_in), - .floo_rsp_o (router_7_22_rsp_out), - .floo_req_o (router_7_22_req_out), - .floo_rsp_i (router_7_22_rsp_in) -); - - -floo_req_t [4:0] router_7_23_req_in; -floo_rsp_t [4:0] router_7_23_rsp_out; -floo_req_t [4:0] router_7_23_req_out; -floo_rsp_t [4:0] router_7_23_rsp_in; - - assign router_7_23_req_in[0] = router_7_24_to_router_7_23_req; - assign router_7_23_req_in[1] = router_8_23_to_router_7_23_req; - assign router_7_23_req_in[2] = router_7_22_to_router_7_23_req; - assign router_7_23_req_in[3] = router_6_23_to_router_7_23_req; - assign router_7_23_req_in[4] = magia_tile_ni_7_23_to_router_7_23_req; - - assign router_7_23_to_router_7_24_rsp = router_7_23_rsp_out[0]; - assign router_7_23_to_router_8_23_rsp = router_7_23_rsp_out[1]; - assign router_7_23_to_router_7_22_rsp = router_7_23_rsp_out[2]; - assign router_7_23_to_router_6_23_rsp = router_7_23_rsp_out[3]; - assign router_7_23_to_magia_tile_ni_7_23_rsp = router_7_23_rsp_out[4]; - - assign router_7_23_to_router_7_24_req = router_7_23_req_out[0]; - assign router_7_23_to_router_8_23_req = router_7_23_req_out[1]; - assign router_7_23_to_router_7_22_req = router_7_23_req_out[2]; - assign router_7_23_to_router_6_23_req = router_7_23_req_out[3]; - assign router_7_23_to_magia_tile_ni_7_23_req = router_7_23_req_out[4]; - - assign router_7_23_rsp_in[0] = router_7_24_to_router_7_23_rsp; - assign router_7_23_rsp_in[1] = router_8_23_to_router_7_23_rsp; - assign router_7_23_rsp_in[2] = router_7_22_to_router_7_23_rsp; - assign router_7_23_rsp_in[3] = router_6_23_to_router_7_23_rsp; - assign router_7_23_rsp_in[4] = magia_tile_ni_7_23_to_router_7_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_23_req_in), - .floo_rsp_o (router_7_23_rsp_out), - .floo_req_o (router_7_23_req_out), - .floo_rsp_i (router_7_23_rsp_in) -); - - -floo_req_t [4:0] router_7_24_req_in; -floo_rsp_t [4:0] router_7_24_rsp_out; -floo_req_t [4:0] router_7_24_req_out; -floo_rsp_t [4:0] router_7_24_rsp_in; - - assign router_7_24_req_in[0] = router_7_25_to_router_7_24_req; - assign router_7_24_req_in[1] = router_8_24_to_router_7_24_req; - assign router_7_24_req_in[2] = router_7_23_to_router_7_24_req; - assign router_7_24_req_in[3] = router_6_24_to_router_7_24_req; - assign router_7_24_req_in[4] = magia_tile_ni_7_24_to_router_7_24_req; - - assign router_7_24_to_router_7_25_rsp = router_7_24_rsp_out[0]; - assign router_7_24_to_router_8_24_rsp = router_7_24_rsp_out[1]; - assign router_7_24_to_router_7_23_rsp = router_7_24_rsp_out[2]; - assign router_7_24_to_router_6_24_rsp = router_7_24_rsp_out[3]; - assign router_7_24_to_magia_tile_ni_7_24_rsp = router_7_24_rsp_out[4]; - - assign router_7_24_to_router_7_25_req = router_7_24_req_out[0]; - assign router_7_24_to_router_8_24_req = router_7_24_req_out[1]; - assign router_7_24_to_router_7_23_req = router_7_24_req_out[2]; - assign router_7_24_to_router_6_24_req = router_7_24_req_out[3]; - assign router_7_24_to_magia_tile_ni_7_24_req = router_7_24_req_out[4]; - - assign router_7_24_rsp_in[0] = router_7_25_to_router_7_24_rsp; - assign router_7_24_rsp_in[1] = router_8_24_to_router_7_24_rsp; - assign router_7_24_rsp_in[2] = router_7_23_to_router_7_24_rsp; - assign router_7_24_rsp_in[3] = router_6_24_to_router_7_24_rsp; - assign router_7_24_rsp_in[4] = magia_tile_ni_7_24_to_router_7_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_24_req_in), - .floo_rsp_o (router_7_24_rsp_out), - .floo_req_o (router_7_24_req_out), - .floo_rsp_i (router_7_24_rsp_in) -); - - -floo_req_t [4:0] router_7_25_req_in; -floo_rsp_t [4:0] router_7_25_rsp_out; -floo_req_t [4:0] router_7_25_req_out; -floo_rsp_t [4:0] router_7_25_rsp_in; - - assign router_7_25_req_in[0] = router_7_26_to_router_7_25_req; - assign router_7_25_req_in[1] = router_8_25_to_router_7_25_req; - assign router_7_25_req_in[2] = router_7_24_to_router_7_25_req; - assign router_7_25_req_in[3] = router_6_25_to_router_7_25_req; - assign router_7_25_req_in[4] = magia_tile_ni_7_25_to_router_7_25_req; - - assign router_7_25_to_router_7_26_rsp = router_7_25_rsp_out[0]; - assign router_7_25_to_router_8_25_rsp = router_7_25_rsp_out[1]; - assign router_7_25_to_router_7_24_rsp = router_7_25_rsp_out[2]; - assign router_7_25_to_router_6_25_rsp = router_7_25_rsp_out[3]; - assign router_7_25_to_magia_tile_ni_7_25_rsp = router_7_25_rsp_out[4]; - - assign router_7_25_to_router_7_26_req = router_7_25_req_out[0]; - assign router_7_25_to_router_8_25_req = router_7_25_req_out[1]; - assign router_7_25_to_router_7_24_req = router_7_25_req_out[2]; - assign router_7_25_to_router_6_25_req = router_7_25_req_out[3]; - assign router_7_25_to_magia_tile_ni_7_25_req = router_7_25_req_out[4]; - - assign router_7_25_rsp_in[0] = router_7_26_to_router_7_25_rsp; - assign router_7_25_rsp_in[1] = router_8_25_to_router_7_25_rsp; - assign router_7_25_rsp_in[2] = router_7_24_to_router_7_25_rsp; - assign router_7_25_rsp_in[3] = router_6_25_to_router_7_25_rsp; - assign router_7_25_rsp_in[4] = magia_tile_ni_7_25_to_router_7_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_25_req_in), - .floo_rsp_o (router_7_25_rsp_out), - .floo_req_o (router_7_25_req_out), - .floo_rsp_i (router_7_25_rsp_in) -); - - -floo_req_t [4:0] router_7_26_req_in; -floo_rsp_t [4:0] router_7_26_rsp_out; -floo_req_t [4:0] router_7_26_req_out; -floo_rsp_t [4:0] router_7_26_rsp_in; - - assign router_7_26_req_in[0] = router_7_27_to_router_7_26_req; - assign router_7_26_req_in[1] = router_8_26_to_router_7_26_req; - assign router_7_26_req_in[2] = router_7_25_to_router_7_26_req; - assign router_7_26_req_in[3] = router_6_26_to_router_7_26_req; - assign router_7_26_req_in[4] = magia_tile_ni_7_26_to_router_7_26_req; - - assign router_7_26_to_router_7_27_rsp = router_7_26_rsp_out[0]; - assign router_7_26_to_router_8_26_rsp = router_7_26_rsp_out[1]; - assign router_7_26_to_router_7_25_rsp = router_7_26_rsp_out[2]; - assign router_7_26_to_router_6_26_rsp = router_7_26_rsp_out[3]; - assign router_7_26_to_magia_tile_ni_7_26_rsp = router_7_26_rsp_out[4]; - - assign router_7_26_to_router_7_27_req = router_7_26_req_out[0]; - assign router_7_26_to_router_8_26_req = router_7_26_req_out[1]; - assign router_7_26_to_router_7_25_req = router_7_26_req_out[2]; - assign router_7_26_to_router_6_26_req = router_7_26_req_out[3]; - assign router_7_26_to_magia_tile_ni_7_26_req = router_7_26_req_out[4]; - - assign router_7_26_rsp_in[0] = router_7_27_to_router_7_26_rsp; - assign router_7_26_rsp_in[1] = router_8_26_to_router_7_26_rsp; - assign router_7_26_rsp_in[2] = router_7_25_to_router_7_26_rsp; - assign router_7_26_rsp_in[3] = router_6_26_to_router_7_26_rsp; - assign router_7_26_rsp_in[4] = magia_tile_ni_7_26_to_router_7_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_26_req_in), - .floo_rsp_o (router_7_26_rsp_out), - .floo_req_o (router_7_26_req_out), - .floo_rsp_i (router_7_26_rsp_in) -); - - -floo_req_t [4:0] router_7_27_req_in; -floo_rsp_t [4:0] router_7_27_rsp_out; -floo_req_t [4:0] router_7_27_req_out; -floo_rsp_t [4:0] router_7_27_rsp_in; - - assign router_7_27_req_in[0] = router_7_28_to_router_7_27_req; - assign router_7_27_req_in[1] = router_8_27_to_router_7_27_req; - assign router_7_27_req_in[2] = router_7_26_to_router_7_27_req; - assign router_7_27_req_in[3] = router_6_27_to_router_7_27_req; - assign router_7_27_req_in[4] = magia_tile_ni_7_27_to_router_7_27_req; - - assign router_7_27_to_router_7_28_rsp = router_7_27_rsp_out[0]; - assign router_7_27_to_router_8_27_rsp = router_7_27_rsp_out[1]; - assign router_7_27_to_router_7_26_rsp = router_7_27_rsp_out[2]; - assign router_7_27_to_router_6_27_rsp = router_7_27_rsp_out[3]; - assign router_7_27_to_magia_tile_ni_7_27_rsp = router_7_27_rsp_out[4]; - - assign router_7_27_to_router_7_28_req = router_7_27_req_out[0]; - assign router_7_27_to_router_8_27_req = router_7_27_req_out[1]; - assign router_7_27_to_router_7_26_req = router_7_27_req_out[2]; - assign router_7_27_to_router_6_27_req = router_7_27_req_out[3]; - assign router_7_27_to_magia_tile_ni_7_27_req = router_7_27_req_out[4]; - - assign router_7_27_rsp_in[0] = router_7_28_to_router_7_27_rsp; - assign router_7_27_rsp_in[1] = router_8_27_to_router_7_27_rsp; - assign router_7_27_rsp_in[2] = router_7_26_to_router_7_27_rsp; - assign router_7_27_rsp_in[3] = router_6_27_to_router_7_27_rsp; - assign router_7_27_rsp_in[4] = magia_tile_ni_7_27_to_router_7_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_27_req_in), - .floo_rsp_o (router_7_27_rsp_out), - .floo_req_o (router_7_27_req_out), - .floo_rsp_i (router_7_27_rsp_in) -); - - -floo_req_t [4:0] router_7_28_req_in; -floo_rsp_t [4:0] router_7_28_rsp_out; -floo_req_t [4:0] router_7_28_req_out; -floo_rsp_t [4:0] router_7_28_rsp_in; - - assign router_7_28_req_in[0] = router_7_29_to_router_7_28_req; - assign router_7_28_req_in[1] = router_8_28_to_router_7_28_req; - assign router_7_28_req_in[2] = router_7_27_to_router_7_28_req; - assign router_7_28_req_in[3] = router_6_28_to_router_7_28_req; - assign router_7_28_req_in[4] = magia_tile_ni_7_28_to_router_7_28_req; - - assign router_7_28_to_router_7_29_rsp = router_7_28_rsp_out[0]; - assign router_7_28_to_router_8_28_rsp = router_7_28_rsp_out[1]; - assign router_7_28_to_router_7_27_rsp = router_7_28_rsp_out[2]; - assign router_7_28_to_router_6_28_rsp = router_7_28_rsp_out[3]; - assign router_7_28_to_magia_tile_ni_7_28_rsp = router_7_28_rsp_out[4]; - - assign router_7_28_to_router_7_29_req = router_7_28_req_out[0]; - assign router_7_28_to_router_8_28_req = router_7_28_req_out[1]; - assign router_7_28_to_router_7_27_req = router_7_28_req_out[2]; - assign router_7_28_to_router_6_28_req = router_7_28_req_out[3]; - assign router_7_28_to_magia_tile_ni_7_28_req = router_7_28_req_out[4]; - - assign router_7_28_rsp_in[0] = router_7_29_to_router_7_28_rsp; - assign router_7_28_rsp_in[1] = router_8_28_to_router_7_28_rsp; - assign router_7_28_rsp_in[2] = router_7_27_to_router_7_28_rsp; - assign router_7_28_rsp_in[3] = router_6_28_to_router_7_28_rsp; - assign router_7_28_rsp_in[4] = magia_tile_ni_7_28_to_router_7_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_28_req_in), - .floo_rsp_o (router_7_28_rsp_out), - .floo_req_o (router_7_28_req_out), - .floo_rsp_i (router_7_28_rsp_in) -); - - -floo_req_t [4:0] router_7_29_req_in; -floo_rsp_t [4:0] router_7_29_rsp_out; -floo_req_t [4:0] router_7_29_req_out; -floo_rsp_t [4:0] router_7_29_rsp_in; - - assign router_7_29_req_in[0] = router_7_30_to_router_7_29_req; - assign router_7_29_req_in[1] = router_8_29_to_router_7_29_req; - assign router_7_29_req_in[2] = router_7_28_to_router_7_29_req; - assign router_7_29_req_in[3] = router_6_29_to_router_7_29_req; - assign router_7_29_req_in[4] = magia_tile_ni_7_29_to_router_7_29_req; - - assign router_7_29_to_router_7_30_rsp = router_7_29_rsp_out[0]; - assign router_7_29_to_router_8_29_rsp = router_7_29_rsp_out[1]; - assign router_7_29_to_router_7_28_rsp = router_7_29_rsp_out[2]; - assign router_7_29_to_router_6_29_rsp = router_7_29_rsp_out[3]; - assign router_7_29_to_magia_tile_ni_7_29_rsp = router_7_29_rsp_out[4]; - - assign router_7_29_to_router_7_30_req = router_7_29_req_out[0]; - assign router_7_29_to_router_8_29_req = router_7_29_req_out[1]; - assign router_7_29_to_router_7_28_req = router_7_29_req_out[2]; - assign router_7_29_to_router_6_29_req = router_7_29_req_out[3]; - assign router_7_29_to_magia_tile_ni_7_29_req = router_7_29_req_out[4]; - - assign router_7_29_rsp_in[0] = router_7_30_to_router_7_29_rsp; - assign router_7_29_rsp_in[1] = router_8_29_to_router_7_29_rsp; - assign router_7_29_rsp_in[2] = router_7_28_to_router_7_29_rsp; - assign router_7_29_rsp_in[3] = router_6_29_to_router_7_29_rsp; - assign router_7_29_rsp_in[4] = magia_tile_ni_7_29_to_router_7_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_29_req_in), - .floo_rsp_o (router_7_29_rsp_out), - .floo_req_o (router_7_29_req_out), - .floo_rsp_i (router_7_29_rsp_in) -); - - -floo_req_t [4:0] router_7_30_req_in; -floo_rsp_t [4:0] router_7_30_rsp_out; -floo_req_t [4:0] router_7_30_req_out; -floo_rsp_t [4:0] router_7_30_rsp_in; - - assign router_7_30_req_in[0] = router_7_31_to_router_7_30_req; - assign router_7_30_req_in[1] = router_8_30_to_router_7_30_req; - assign router_7_30_req_in[2] = router_7_29_to_router_7_30_req; - assign router_7_30_req_in[3] = router_6_30_to_router_7_30_req; - assign router_7_30_req_in[4] = magia_tile_ni_7_30_to_router_7_30_req; - - assign router_7_30_to_router_7_31_rsp = router_7_30_rsp_out[0]; - assign router_7_30_to_router_8_30_rsp = router_7_30_rsp_out[1]; - assign router_7_30_to_router_7_29_rsp = router_7_30_rsp_out[2]; - assign router_7_30_to_router_6_30_rsp = router_7_30_rsp_out[3]; - assign router_7_30_to_magia_tile_ni_7_30_rsp = router_7_30_rsp_out[4]; - - assign router_7_30_to_router_7_31_req = router_7_30_req_out[0]; - assign router_7_30_to_router_8_30_req = router_7_30_req_out[1]; - assign router_7_30_to_router_7_29_req = router_7_30_req_out[2]; - assign router_7_30_to_router_6_30_req = router_7_30_req_out[3]; - assign router_7_30_to_magia_tile_ni_7_30_req = router_7_30_req_out[4]; - - assign router_7_30_rsp_in[0] = router_7_31_to_router_7_30_rsp; - assign router_7_30_rsp_in[1] = router_8_30_to_router_7_30_rsp; - assign router_7_30_rsp_in[2] = router_7_29_to_router_7_30_rsp; - assign router_7_30_rsp_in[3] = router_6_30_to_router_7_30_rsp; - assign router_7_30_rsp_in[4] = magia_tile_ni_7_30_to_router_7_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_30_req_in), - .floo_rsp_o (router_7_30_rsp_out), - .floo_req_o (router_7_30_req_out), - .floo_rsp_i (router_7_30_rsp_in) -); - - -floo_req_t [4:0] router_7_31_req_in; -floo_rsp_t [4:0] router_7_31_rsp_out; -floo_req_t [4:0] router_7_31_req_out; -floo_rsp_t [4:0] router_7_31_rsp_in; - - assign router_7_31_req_in[0] = '0; - assign router_7_31_req_in[1] = router_8_31_to_router_7_31_req; - assign router_7_31_req_in[2] = router_7_30_to_router_7_31_req; - assign router_7_31_req_in[3] = router_6_31_to_router_7_31_req; - assign router_7_31_req_in[4] = magia_tile_ni_7_31_to_router_7_31_req; - - assign router_7_31_to_router_8_31_rsp = router_7_31_rsp_out[1]; - assign router_7_31_to_router_7_30_rsp = router_7_31_rsp_out[2]; - assign router_7_31_to_router_6_31_rsp = router_7_31_rsp_out[3]; - assign router_7_31_to_magia_tile_ni_7_31_rsp = router_7_31_rsp_out[4]; - - assign router_7_31_to_router_8_31_req = router_7_31_req_out[1]; - assign router_7_31_to_router_7_30_req = router_7_31_req_out[2]; - assign router_7_31_to_router_6_31_req = router_7_31_req_out[3]; - assign router_7_31_to_magia_tile_ni_7_31_req = router_7_31_req_out[4]; - - assign router_7_31_rsp_in[0] = '0; - assign router_7_31_rsp_in[1] = router_8_31_to_router_7_31_rsp; - assign router_7_31_rsp_in[2] = router_7_30_to_router_7_31_rsp; - assign router_7_31_rsp_in[3] = router_6_31_to_router_7_31_rsp; - assign router_7_31_rsp_in[4] = magia_tile_ni_7_31_to_router_7_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_31_req_in), - .floo_rsp_o (router_7_31_rsp_out), - .floo_req_o (router_7_31_req_out), - .floo_rsp_i (router_7_31_rsp_in) -); - - -floo_req_t [4:0] router_8_0_req_in; -floo_rsp_t [4:0] router_8_0_rsp_out; -floo_req_t [4:0] router_8_0_req_out; -floo_rsp_t [4:0] router_8_0_rsp_in; - - assign router_8_0_req_in[0] = router_8_1_to_router_8_0_req; - assign router_8_0_req_in[1] = router_9_0_to_router_8_0_req; - assign router_8_0_req_in[2] = '0; - assign router_8_0_req_in[3] = router_7_0_to_router_8_0_req; - assign router_8_0_req_in[4] = magia_tile_ni_8_0_to_router_8_0_req; - - assign router_8_0_to_router_8_1_rsp = router_8_0_rsp_out[0]; - assign router_8_0_to_router_9_0_rsp = router_8_0_rsp_out[1]; - assign router_8_0_to_router_7_0_rsp = router_8_0_rsp_out[3]; - assign router_8_0_to_magia_tile_ni_8_0_rsp = router_8_0_rsp_out[4]; - - assign router_8_0_to_router_8_1_req = router_8_0_req_out[0]; - assign router_8_0_to_router_9_0_req = router_8_0_req_out[1]; - assign router_8_0_to_router_7_0_req = router_8_0_req_out[3]; - assign router_8_0_to_magia_tile_ni_8_0_req = router_8_0_req_out[4]; - - assign router_8_0_rsp_in[0] = router_8_1_to_router_8_0_rsp; - assign router_8_0_rsp_in[1] = router_9_0_to_router_8_0_rsp; - assign router_8_0_rsp_in[2] = '0; - assign router_8_0_rsp_in[3] = router_7_0_to_router_8_0_rsp; - assign router_8_0_rsp_in[4] = magia_tile_ni_8_0_to_router_8_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_0_req_in), - .floo_rsp_o (router_8_0_rsp_out), - .floo_req_o (router_8_0_req_out), - .floo_rsp_i (router_8_0_rsp_in) -); - - -floo_req_t [4:0] router_8_1_req_in; -floo_rsp_t [4:0] router_8_1_rsp_out; -floo_req_t [4:0] router_8_1_req_out; -floo_rsp_t [4:0] router_8_1_rsp_in; - - assign router_8_1_req_in[0] = router_8_2_to_router_8_1_req; - assign router_8_1_req_in[1] = router_9_1_to_router_8_1_req; - assign router_8_1_req_in[2] = router_8_0_to_router_8_1_req; - assign router_8_1_req_in[3] = router_7_1_to_router_8_1_req; - assign router_8_1_req_in[4] = magia_tile_ni_8_1_to_router_8_1_req; - - assign router_8_1_to_router_8_2_rsp = router_8_1_rsp_out[0]; - assign router_8_1_to_router_9_1_rsp = router_8_1_rsp_out[1]; - assign router_8_1_to_router_8_0_rsp = router_8_1_rsp_out[2]; - assign router_8_1_to_router_7_1_rsp = router_8_1_rsp_out[3]; - assign router_8_1_to_magia_tile_ni_8_1_rsp = router_8_1_rsp_out[4]; - - assign router_8_1_to_router_8_2_req = router_8_1_req_out[0]; - assign router_8_1_to_router_9_1_req = router_8_1_req_out[1]; - assign router_8_1_to_router_8_0_req = router_8_1_req_out[2]; - assign router_8_1_to_router_7_1_req = router_8_1_req_out[3]; - assign router_8_1_to_magia_tile_ni_8_1_req = router_8_1_req_out[4]; - - assign router_8_1_rsp_in[0] = router_8_2_to_router_8_1_rsp; - assign router_8_1_rsp_in[1] = router_9_1_to_router_8_1_rsp; - assign router_8_1_rsp_in[2] = router_8_0_to_router_8_1_rsp; - assign router_8_1_rsp_in[3] = router_7_1_to_router_8_1_rsp; - assign router_8_1_rsp_in[4] = magia_tile_ni_8_1_to_router_8_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_1_req_in), - .floo_rsp_o (router_8_1_rsp_out), - .floo_req_o (router_8_1_req_out), - .floo_rsp_i (router_8_1_rsp_in) -); - - -floo_req_t [4:0] router_8_2_req_in; -floo_rsp_t [4:0] router_8_2_rsp_out; -floo_req_t [4:0] router_8_2_req_out; -floo_rsp_t [4:0] router_8_2_rsp_in; - - assign router_8_2_req_in[0] = router_8_3_to_router_8_2_req; - assign router_8_2_req_in[1] = router_9_2_to_router_8_2_req; - assign router_8_2_req_in[2] = router_8_1_to_router_8_2_req; - assign router_8_2_req_in[3] = router_7_2_to_router_8_2_req; - assign router_8_2_req_in[4] = magia_tile_ni_8_2_to_router_8_2_req; - - assign router_8_2_to_router_8_3_rsp = router_8_2_rsp_out[0]; - assign router_8_2_to_router_9_2_rsp = router_8_2_rsp_out[1]; - assign router_8_2_to_router_8_1_rsp = router_8_2_rsp_out[2]; - assign router_8_2_to_router_7_2_rsp = router_8_2_rsp_out[3]; - assign router_8_2_to_magia_tile_ni_8_2_rsp = router_8_2_rsp_out[4]; - - assign router_8_2_to_router_8_3_req = router_8_2_req_out[0]; - assign router_8_2_to_router_9_2_req = router_8_2_req_out[1]; - assign router_8_2_to_router_8_1_req = router_8_2_req_out[2]; - assign router_8_2_to_router_7_2_req = router_8_2_req_out[3]; - assign router_8_2_to_magia_tile_ni_8_2_req = router_8_2_req_out[4]; - - assign router_8_2_rsp_in[0] = router_8_3_to_router_8_2_rsp; - assign router_8_2_rsp_in[1] = router_9_2_to_router_8_2_rsp; - assign router_8_2_rsp_in[2] = router_8_1_to_router_8_2_rsp; - assign router_8_2_rsp_in[3] = router_7_2_to_router_8_2_rsp; - assign router_8_2_rsp_in[4] = magia_tile_ni_8_2_to_router_8_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_2_req_in), - .floo_rsp_o (router_8_2_rsp_out), - .floo_req_o (router_8_2_req_out), - .floo_rsp_i (router_8_2_rsp_in) -); - - -floo_req_t [4:0] router_8_3_req_in; -floo_rsp_t [4:0] router_8_3_rsp_out; -floo_req_t [4:0] router_8_3_req_out; -floo_rsp_t [4:0] router_8_3_rsp_in; - - assign router_8_3_req_in[0] = router_8_4_to_router_8_3_req; - assign router_8_3_req_in[1] = router_9_3_to_router_8_3_req; - assign router_8_3_req_in[2] = router_8_2_to_router_8_3_req; - assign router_8_3_req_in[3] = router_7_3_to_router_8_3_req; - assign router_8_3_req_in[4] = magia_tile_ni_8_3_to_router_8_3_req; - - assign router_8_3_to_router_8_4_rsp = router_8_3_rsp_out[0]; - assign router_8_3_to_router_9_3_rsp = router_8_3_rsp_out[1]; - assign router_8_3_to_router_8_2_rsp = router_8_3_rsp_out[2]; - assign router_8_3_to_router_7_3_rsp = router_8_3_rsp_out[3]; - assign router_8_3_to_magia_tile_ni_8_3_rsp = router_8_3_rsp_out[4]; - - assign router_8_3_to_router_8_4_req = router_8_3_req_out[0]; - assign router_8_3_to_router_9_3_req = router_8_3_req_out[1]; - assign router_8_3_to_router_8_2_req = router_8_3_req_out[2]; - assign router_8_3_to_router_7_3_req = router_8_3_req_out[3]; - assign router_8_3_to_magia_tile_ni_8_3_req = router_8_3_req_out[4]; - - assign router_8_3_rsp_in[0] = router_8_4_to_router_8_3_rsp; - assign router_8_3_rsp_in[1] = router_9_3_to_router_8_3_rsp; - assign router_8_3_rsp_in[2] = router_8_2_to_router_8_3_rsp; - assign router_8_3_rsp_in[3] = router_7_3_to_router_8_3_rsp; - assign router_8_3_rsp_in[4] = magia_tile_ni_8_3_to_router_8_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_3_req_in), - .floo_rsp_o (router_8_3_rsp_out), - .floo_req_o (router_8_3_req_out), - .floo_rsp_i (router_8_3_rsp_in) -); - - -floo_req_t [4:0] router_8_4_req_in; -floo_rsp_t [4:0] router_8_4_rsp_out; -floo_req_t [4:0] router_8_4_req_out; -floo_rsp_t [4:0] router_8_4_rsp_in; - - assign router_8_4_req_in[0] = router_8_5_to_router_8_4_req; - assign router_8_4_req_in[1] = router_9_4_to_router_8_4_req; - assign router_8_4_req_in[2] = router_8_3_to_router_8_4_req; - assign router_8_4_req_in[3] = router_7_4_to_router_8_4_req; - assign router_8_4_req_in[4] = magia_tile_ni_8_4_to_router_8_4_req; - - assign router_8_4_to_router_8_5_rsp = router_8_4_rsp_out[0]; - assign router_8_4_to_router_9_4_rsp = router_8_4_rsp_out[1]; - assign router_8_4_to_router_8_3_rsp = router_8_4_rsp_out[2]; - assign router_8_4_to_router_7_4_rsp = router_8_4_rsp_out[3]; - assign router_8_4_to_magia_tile_ni_8_4_rsp = router_8_4_rsp_out[4]; - - assign router_8_4_to_router_8_5_req = router_8_4_req_out[0]; - assign router_8_4_to_router_9_4_req = router_8_4_req_out[1]; - assign router_8_4_to_router_8_3_req = router_8_4_req_out[2]; - assign router_8_4_to_router_7_4_req = router_8_4_req_out[3]; - assign router_8_4_to_magia_tile_ni_8_4_req = router_8_4_req_out[4]; - - assign router_8_4_rsp_in[0] = router_8_5_to_router_8_4_rsp; - assign router_8_4_rsp_in[1] = router_9_4_to_router_8_4_rsp; - assign router_8_4_rsp_in[2] = router_8_3_to_router_8_4_rsp; - assign router_8_4_rsp_in[3] = router_7_4_to_router_8_4_rsp; - assign router_8_4_rsp_in[4] = magia_tile_ni_8_4_to_router_8_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_4_req_in), - .floo_rsp_o (router_8_4_rsp_out), - .floo_req_o (router_8_4_req_out), - .floo_rsp_i (router_8_4_rsp_in) -); - - -floo_req_t [4:0] router_8_5_req_in; -floo_rsp_t [4:0] router_8_5_rsp_out; -floo_req_t [4:0] router_8_5_req_out; -floo_rsp_t [4:0] router_8_5_rsp_in; - - assign router_8_5_req_in[0] = router_8_6_to_router_8_5_req; - assign router_8_5_req_in[1] = router_9_5_to_router_8_5_req; - assign router_8_5_req_in[2] = router_8_4_to_router_8_5_req; - assign router_8_5_req_in[3] = router_7_5_to_router_8_5_req; - assign router_8_5_req_in[4] = magia_tile_ni_8_5_to_router_8_5_req; - - assign router_8_5_to_router_8_6_rsp = router_8_5_rsp_out[0]; - assign router_8_5_to_router_9_5_rsp = router_8_5_rsp_out[1]; - assign router_8_5_to_router_8_4_rsp = router_8_5_rsp_out[2]; - assign router_8_5_to_router_7_5_rsp = router_8_5_rsp_out[3]; - assign router_8_5_to_magia_tile_ni_8_5_rsp = router_8_5_rsp_out[4]; - - assign router_8_5_to_router_8_6_req = router_8_5_req_out[0]; - assign router_8_5_to_router_9_5_req = router_8_5_req_out[1]; - assign router_8_5_to_router_8_4_req = router_8_5_req_out[2]; - assign router_8_5_to_router_7_5_req = router_8_5_req_out[3]; - assign router_8_5_to_magia_tile_ni_8_5_req = router_8_5_req_out[4]; - - assign router_8_5_rsp_in[0] = router_8_6_to_router_8_5_rsp; - assign router_8_5_rsp_in[1] = router_9_5_to_router_8_5_rsp; - assign router_8_5_rsp_in[2] = router_8_4_to_router_8_5_rsp; - assign router_8_5_rsp_in[3] = router_7_5_to_router_8_5_rsp; - assign router_8_5_rsp_in[4] = magia_tile_ni_8_5_to_router_8_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_5_req_in), - .floo_rsp_o (router_8_5_rsp_out), - .floo_req_o (router_8_5_req_out), - .floo_rsp_i (router_8_5_rsp_in) -); - - -floo_req_t [4:0] router_8_6_req_in; -floo_rsp_t [4:0] router_8_6_rsp_out; -floo_req_t [4:0] router_8_6_req_out; -floo_rsp_t [4:0] router_8_6_rsp_in; - - assign router_8_6_req_in[0] = router_8_7_to_router_8_6_req; - assign router_8_6_req_in[1] = router_9_6_to_router_8_6_req; - assign router_8_6_req_in[2] = router_8_5_to_router_8_6_req; - assign router_8_6_req_in[3] = router_7_6_to_router_8_6_req; - assign router_8_6_req_in[4] = magia_tile_ni_8_6_to_router_8_6_req; - - assign router_8_6_to_router_8_7_rsp = router_8_6_rsp_out[0]; - assign router_8_6_to_router_9_6_rsp = router_8_6_rsp_out[1]; - assign router_8_6_to_router_8_5_rsp = router_8_6_rsp_out[2]; - assign router_8_6_to_router_7_6_rsp = router_8_6_rsp_out[3]; - assign router_8_6_to_magia_tile_ni_8_6_rsp = router_8_6_rsp_out[4]; - - assign router_8_6_to_router_8_7_req = router_8_6_req_out[0]; - assign router_8_6_to_router_9_6_req = router_8_6_req_out[1]; - assign router_8_6_to_router_8_5_req = router_8_6_req_out[2]; - assign router_8_6_to_router_7_6_req = router_8_6_req_out[3]; - assign router_8_6_to_magia_tile_ni_8_6_req = router_8_6_req_out[4]; - - assign router_8_6_rsp_in[0] = router_8_7_to_router_8_6_rsp; - assign router_8_6_rsp_in[1] = router_9_6_to_router_8_6_rsp; - assign router_8_6_rsp_in[2] = router_8_5_to_router_8_6_rsp; - assign router_8_6_rsp_in[3] = router_7_6_to_router_8_6_rsp; - assign router_8_6_rsp_in[4] = magia_tile_ni_8_6_to_router_8_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_6_req_in), - .floo_rsp_o (router_8_6_rsp_out), - .floo_req_o (router_8_6_req_out), - .floo_rsp_i (router_8_6_rsp_in) -); - - -floo_req_t [4:0] router_8_7_req_in; -floo_rsp_t [4:0] router_8_7_rsp_out; -floo_req_t [4:0] router_8_7_req_out; -floo_rsp_t [4:0] router_8_7_rsp_in; - - assign router_8_7_req_in[0] = router_8_8_to_router_8_7_req; - assign router_8_7_req_in[1] = router_9_7_to_router_8_7_req; - assign router_8_7_req_in[2] = router_8_6_to_router_8_7_req; - assign router_8_7_req_in[3] = router_7_7_to_router_8_7_req; - assign router_8_7_req_in[4] = magia_tile_ni_8_7_to_router_8_7_req; - - assign router_8_7_to_router_8_8_rsp = router_8_7_rsp_out[0]; - assign router_8_7_to_router_9_7_rsp = router_8_7_rsp_out[1]; - assign router_8_7_to_router_8_6_rsp = router_8_7_rsp_out[2]; - assign router_8_7_to_router_7_7_rsp = router_8_7_rsp_out[3]; - assign router_8_7_to_magia_tile_ni_8_7_rsp = router_8_7_rsp_out[4]; - - assign router_8_7_to_router_8_8_req = router_8_7_req_out[0]; - assign router_8_7_to_router_9_7_req = router_8_7_req_out[1]; - assign router_8_7_to_router_8_6_req = router_8_7_req_out[2]; - assign router_8_7_to_router_7_7_req = router_8_7_req_out[3]; - assign router_8_7_to_magia_tile_ni_8_7_req = router_8_7_req_out[4]; - - assign router_8_7_rsp_in[0] = router_8_8_to_router_8_7_rsp; - assign router_8_7_rsp_in[1] = router_9_7_to_router_8_7_rsp; - assign router_8_7_rsp_in[2] = router_8_6_to_router_8_7_rsp; - assign router_8_7_rsp_in[3] = router_7_7_to_router_8_7_rsp; - assign router_8_7_rsp_in[4] = magia_tile_ni_8_7_to_router_8_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_7_req_in), - .floo_rsp_o (router_8_7_rsp_out), - .floo_req_o (router_8_7_req_out), - .floo_rsp_i (router_8_7_rsp_in) -); - - -floo_req_t [4:0] router_8_8_req_in; -floo_rsp_t [4:0] router_8_8_rsp_out; -floo_req_t [4:0] router_8_8_req_out; -floo_rsp_t [4:0] router_8_8_rsp_in; - - assign router_8_8_req_in[0] = router_8_9_to_router_8_8_req; - assign router_8_8_req_in[1] = router_9_8_to_router_8_8_req; - assign router_8_8_req_in[2] = router_8_7_to_router_8_8_req; - assign router_8_8_req_in[3] = router_7_8_to_router_8_8_req; - assign router_8_8_req_in[4] = magia_tile_ni_8_8_to_router_8_8_req; - - assign router_8_8_to_router_8_9_rsp = router_8_8_rsp_out[0]; - assign router_8_8_to_router_9_8_rsp = router_8_8_rsp_out[1]; - assign router_8_8_to_router_8_7_rsp = router_8_8_rsp_out[2]; - assign router_8_8_to_router_7_8_rsp = router_8_8_rsp_out[3]; - assign router_8_8_to_magia_tile_ni_8_8_rsp = router_8_8_rsp_out[4]; - - assign router_8_8_to_router_8_9_req = router_8_8_req_out[0]; - assign router_8_8_to_router_9_8_req = router_8_8_req_out[1]; - assign router_8_8_to_router_8_7_req = router_8_8_req_out[2]; - assign router_8_8_to_router_7_8_req = router_8_8_req_out[3]; - assign router_8_8_to_magia_tile_ni_8_8_req = router_8_8_req_out[4]; - - assign router_8_8_rsp_in[0] = router_8_9_to_router_8_8_rsp; - assign router_8_8_rsp_in[1] = router_9_8_to_router_8_8_rsp; - assign router_8_8_rsp_in[2] = router_8_7_to_router_8_8_rsp; - assign router_8_8_rsp_in[3] = router_7_8_to_router_8_8_rsp; - assign router_8_8_rsp_in[4] = magia_tile_ni_8_8_to_router_8_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_8_req_in), - .floo_rsp_o (router_8_8_rsp_out), - .floo_req_o (router_8_8_req_out), - .floo_rsp_i (router_8_8_rsp_in) -); - - -floo_req_t [4:0] router_8_9_req_in; -floo_rsp_t [4:0] router_8_9_rsp_out; -floo_req_t [4:0] router_8_9_req_out; -floo_rsp_t [4:0] router_8_9_rsp_in; - - assign router_8_9_req_in[0] = router_8_10_to_router_8_9_req; - assign router_8_9_req_in[1] = router_9_9_to_router_8_9_req; - assign router_8_9_req_in[2] = router_8_8_to_router_8_9_req; - assign router_8_9_req_in[3] = router_7_9_to_router_8_9_req; - assign router_8_9_req_in[4] = magia_tile_ni_8_9_to_router_8_9_req; - - assign router_8_9_to_router_8_10_rsp = router_8_9_rsp_out[0]; - assign router_8_9_to_router_9_9_rsp = router_8_9_rsp_out[1]; - assign router_8_9_to_router_8_8_rsp = router_8_9_rsp_out[2]; - assign router_8_9_to_router_7_9_rsp = router_8_9_rsp_out[3]; - assign router_8_9_to_magia_tile_ni_8_9_rsp = router_8_9_rsp_out[4]; - - assign router_8_9_to_router_8_10_req = router_8_9_req_out[0]; - assign router_8_9_to_router_9_9_req = router_8_9_req_out[1]; - assign router_8_9_to_router_8_8_req = router_8_9_req_out[2]; - assign router_8_9_to_router_7_9_req = router_8_9_req_out[3]; - assign router_8_9_to_magia_tile_ni_8_9_req = router_8_9_req_out[4]; - - assign router_8_9_rsp_in[0] = router_8_10_to_router_8_9_rsp; - assign router_8_9_rsp_in[1] = router_9_9_to_router_8_9_rsp; - assign router_8_9_rsp_in[2] = router_8_8_to_router_8_9_rsp; - assign router_8_9_rsp_in[3] = router_7_9_to_router_8_9_rsp; - assign router_8_9_rsp_in[4] = magia_tile_ni_8_9_to_router_8_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_9_req_in), - .floo_rsp_o (router_8_9_rsp_out), - .floo_req_o (router_8_9_req_out), - .floo_rsp_i (router_8_9_rsp_in) -); - - -floo_req_t [4:0] router_8_10_req_in; -floo_rsp_t [4:0] router_8_10_rsp_out; -floo_req_t [4:0] router_8_10_req_out; -floo_rsp_t [4:0] router_8_10_rsp_in; - - assign router_8_10_req_in[0] = router_8_11_to_router_8_10_req; - assign router_8_10_req_in[1] = router_9_10_to_router_8_10_req; - assign router_8_10_req_in[2] = router_8_9_to_router_8_10_req; - assign router_8_10_req_in[3] = router_7_10_to_router_8_10_req; - assign router_8_10_req_in[4] = magia_tile_ni_8_10_to_router_8_10_req; - - assign router_8_10_to_router_8_11_rsp = router_8_10_rsp_out[0]; - assign router_8_10_to_router_9_10_rsp = router_8_10_rsp_out[1]; - assign router_8_10_to_router_8_9_rsp = router_8_10_rsp_out[2]; - assign router_8_10_to_router_7_10_rsp = router_8_10_rsp_out[3]; - assign router_8_10_to_magia_tile_ni_8_10_rsp = router_8_10_rsp_out[4]; - - assign router_8_10_to_router_8_11_req = router_8_10_req_out[0]; - assign router_8_10_to_router_9_10_req = router_8_10_req_out[1]; - assign router_8_10_to_router_8_9_req = router_8_10_req_out[2]; - assign router_8_10_to_router_7_10_req = router_8_10_req_out[3]; - assign router_8_10_to_magia_tile_ni_8_10_req = router_8_10_req_out[4]; - - assign router_8_10_rsp_in[0] = router_8_11_to_router_8_10_rsp; - assign router_8_10_rsp_in[1] = router_9_10_to_router_8_10_rsp; - assign router_8_10_rsp_in[2] = router_8_9_to_router_8_10_rsp; - assign router_8_10_rsp_in[3] = router_7_10_to_router_8_10_rsp; - assign router_8_10_rsp_in[4] = magia_tile_ni_8_10_to_router_8_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_10_req_in), - .floo_rsp_o (router_8_10_rsp_out), - .floo_req_o (router_8_10_req_out), - .floo_rsp_i (router_8_10_rsp_in) -); - - -floo_req_t [4:0] router_8_11_req_in; -floo_rsp_t [4:0] router_8_11_rsp_out; -floo_req_t [4:0] router_8_11_req_out; -floo_rsp_t [4:0] router_8_11_rsp_in; - - assign router_8_11_req_in[0] = router_8_12_to_router_8_11_req; - assign router_8_11_req_in[1] = router_9_11_to_router_8_11_req; - assign router_8_11_req_in[2] = router_8_10_to_router_8_11_req; - assign router_8_11_req_in[3] = router_7_11_to_router_8_11_req; - assign router_8_11_req_in[4] = magia_tile_ni_8_11_to_router_8_11_req; - - assign router_8_11_to_router_8_12_rsp = router_8_11_rsp_out[0]; - assign router_8_11_to_router_9_11_rsp = router_8_11_rsp_out[1]; - assign router_8_11_to_router_8_10_rsp = router_8_11_rsp_out[2]; - assign router_8_11_to_router_7_11_rsp = router_8_11_rsp_out[3]; - assign router_8_11_to_magia_tile_ni_8_11_rsp = router_8_11_rsp_out[4]; - - assign router_8_11_to_router_8_12_req = router_8_11_req_out[0]; - assign router_8_11_to_router_9_11_req = router_8_11_req_out[1]; - assign router_8_11_to_router_8_10_req = router_8_11_req_out[2]; - assign router_8_11_to_router_7_11_req = router_8_11_req_out[3]; - assign router_8_11_to_magia_tile_ni_8_11_req = router_8_11_req_out[4]; - - assign router_8_11_rsp_in[0] = router_8_12_to_router_8_11_rsp; - assign router_8_11_rsp_in[1] = router_9_11_to_router_8_11_rsp; - assign router_8_11_rsp_in[2] = router_8_10_to_router_8_11_rsp; - assign router_8_11_rsp_in[3] = router_7_11_to_router_8_11_rsp; - assign router_8_11_rsp_in[4] = magia_tile_ni_8_11_to_router_8_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_11_req_in), - .floo_rsp_o (router_8_11_rsp_out), - .floo_req_o (router_8_11_req_out), - .floo_rsp_i (router_8_11_rsp_in) -); - - -floo_req_t [4:0] router_8_12_req_in; -floo_rsp_t [4:0] router_8_12_rsp_out; -floo_req_t [4:0] router_8_12_req_out; -floo_rsp_t [4:0] router_8_12_rsp_in; - - assign router_8_12_req_in[0] = router_8_13_to_router_8_12_req; - assign router_8_12_req_in[1] = router_9_12_to_router_8_12_req; - assign router_8_12_req_in[2] = router_8_11_to_router_8_12_req; - assign router_8_12_req_in[3] = router_7_12_to_router_8_12_req; - assign router_8_12_req_in[4] = magia_tile_ni_8_12_to_router_8_12_req; - - assign router_8_12_to_router_8_13_rsp = router_8_12_rsp_out[0]; - assign router_8_12_to_router_9_12_rsp = router_8_12_rsp_out[1]; - assign router_8_12_to_router_8_11_rsp = router_8_12_rsp_out[2]; - assign router_8_12_to_router_7_12_rsp = router_8_12_rsp_out[3]; - assign router_8_12_to_magia_tile_ni_8_12_rsp = router_8_12_rsp_out[4]; - - assign router_8_12_to_router_8_13_req = router_8_12_req_out[0]; - assign router_8_12_to_router_9_12_req = router_8_12_req_out[1]; - assign router_8_12_to_router_8_11_req = router_8_12_req_out[2]; - assign router_8_12_to_router_7_12_req = router_8_12_req_out[3]; - assign router_8_12_to_magia_tile_ni_8_12_req = router_8_12_req_out[4]; - - assign router_8_12_rsp_in[0] = router_8_13_to_router_8_12_rsp; - assign router_8_12_rsp_in[1] = router_9_12_to_router_8_12_rsp; - assign router_8_12_rsp_in[2] = router_8_11_to_router_8_12_rsp; - assign router_8_12_rsp_in[3] = router_7_12_to_router_8_12_rsp; - assign router_8_12_rsp_in[4] = magia_tile_ni_8_12_to_router_8_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_12_req_in), - .floo_rsp_o (router_8_12_rsp_out), - .floo_req_o (router_8_12_req_out), - .floo_rsp_i (router_8_12_rsp_in) -); - - -floo_req_t [4:0] router_8_13_req_in; -floo_rsp_t [4:0] router_8_13_rsp_out; -floo_req_t [4:0] router_8_13_req_out; -floo_rsp_t [4:0] router_8_13_rsp_in; - - assign router_8_13_req_in[0] = router_8_14_to_router_8_13_req; - assign router_8_13_req_in[1] = router_9_13_to_router_8_13_req; - assign router_8_13_req_in[2] = router_8_12_to_router_8_13_req; - assign router_8_13_req_in[3] = router_7_13_to_router_8_13_req; - assign router_8_13_req_in[4] = magia_tile_ni_8_13_to_router_8_13_req; - - assign router_8_13_to_router_8_14_rsp = router_8_13_rsp_out[0]; - assign router_8_13_to_router_9_13_rsp = router_8_13_rsp_out[1]; - assign router_8_13_to_router_8_12_rsp = router_8_13_rsp_out[2]; - assign router_8_13_to_router_7_13_rsp = router_8_13_rsp_out[3]; - assign router_8_13_to_magia_tile_ni_8_13_rsp = router_8_13_rsp_out[4]; - - assign router_8_13_to_router_8_14_req = router_8_13_req_out[0]; - assign router_8_13_to_router_9_13_req = router_8_13_req_out[1]; - assign router_8_13_to_router_8_12_req = router_8_13_req_out[2]; - assign router_8_13_to_router_7_13_req = router_8_13_req_out[3]; - assign router_8_13_to_magia_tile_ni_8_13_req = router_8_13_req_out[4]; - - assign router_8_13_rsp_in[0] = router_8_14_to_router_8_13_rsp; - assign router_8_13_rsp_in[1] = router_9_13_to_router_8_13_rsp; - assign router_8_13_rsp_in[2] = router_8_12_to_router_8_13_rsp; - assign router_8_13_rsp_in[3] = router_7_13_to_router_8_13_rsp; - assign router_8_13_rsp_in[4] = magia_tile_ni_8_13_to_router_8_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_13_req_in), - .floo_rsp_o (router_8_13_rsp_out), - .floo_req_o (router_8_13_req_out), - .floo_rsp_i (router_8_13_rsp_in) -); - - -floo_req_t [4:0] router_8_14_req_in; -floo_rsp_t [4:0] router_8_14_rsp_out; -floo_req_t [4:0] router_8_14_req_out; -floo_rsp_t [4:0] router_8_14_rsp_in; - - assign router_8_14_req_in[0] = router_8_15_to_router_8_14_req; - assign router_8_14_req_in[1] = router_9_14_to_router_8_14_req; - assign router_8_14_req_in[2] = router_8_13_to_router_8_14_req; - assign router_8_14_req_in[3] = router_7_14_to_router_8_14_req; - assign router_8_14_req_in[4] = magia_tile_ni_8_14_to_router_8_14_req; - - assign router_8_14_to_router_8_15_rsp = router_8_14_rsp_out[0]; - assign router_8_14_to_router_9_14_rsp = router_8_14_rsp_out[1]; - assign router_8_14_to_router_8_13_rsp = router_8_14_rsp_out[2]; - assign router_8_14_to_router_7_14_rsp = router_8_14_rsp_out[3]; - assign router_8_14_to_magia_tile_ni_8_14_rsp = router_8_14_rsp_out[4]; - - assign router_8_14_to_router_8_15_req = router_8_14_req_out[0]; - assign router_8_14_to_router_9_14_req = router_8_14_req_out[1]; - assign router_8_14_to_router_8_13_req = router_8_14_req_out[2]; - assign router_8_14_to_router_7_14_req = router_8_14_req_out[3]; - assign router_8_14_to_magia_tile_ni_8_14_req = router_8_14_req_out[4]; - - assign router_8_14_rsp_in[0] = router_8_15_to_router_8_14_rsp; - assign router_8_14_rsp_in[1] = router_9_14_to_router_8_14_rsp; - assign router_8_14_rsp_in[2] = router_8_13_to_router_8_14_rsp; - assign router_8_14_rsp_in[3] = router_7_14_to_router_8_14_rsp; - assign router_8_14_rsp_in[4] = magia_tile_ni_8_14_to_router_8_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_14_req_in), - .floo_rsp_o (router_8_14_rsp_out), - .floo_req_o (router_8_14_req_out), - .floo_rsp_i (router_8_14_rsp_in) -); - - -floo_req_t [4:0] router_8_15_req_in; -floo_rsp_t [4:0] router_8_15_rsp_out; -floo_req_t [4:0] router_8_15_req_out; -floo_rsp_t [4:0] router_8_15_rsp_in; - - assign router_8_15_req_in[0] = router_8_16_to_router_8_15_req; - assign router_8_15_req_in[1] = router_9_15_to_router_8_15_req; - assign router_8_15_req_in[2] = router_8_14_to_router_8_15_req; - assign router_8_15_req_in[3] = router_7_15_to_router_8_15_req; - assign router_8_15_req_in[4] = magia_tile_ni_8_15_to_router_8_15_req; - - assign router_8_15_to_router_8_16_rsp = router_8_15_rsp_out[0]; - assign router_8_15_to_router_9_15_rsp = router_8_15_rsp_out[1]; - assign router_8_15_to_router_8_14_rsp = router_8_15_rsp_out[2]; - assign router_8_15_to_router_7_15_rsp = router_8_15_rsp_out[3]; - assign router_8_15_to_magia_tile_ni_8_15_rsp = router_8_15_rsp_out[4]; - - assign router_8_15_to_router_8_16_req = router_8_15_req_out[0]; - assign router_8_15_to_router_9_15_req = router_8_15_req_out[1]; - assign router_8_15_to_router_8_14_req = router_8_15_req_out[2]; - assign router_8_15_to_router_7_15_req = router_8_15_req_out[3]; - assign router_8_15_to_magia_tile_ni_8_15_req = router_8_15_req_out[4]; - - assign router_8_15_rsp_in[0] = router_8_16_to_router_8_15_rsp; - assign router_8_15_rsp_in[1] = router_9_15_to_router_8_15_rsp; - assign router_8_15_rsp_in[2] = router_8_14_to_router_8_15_rsp; - assign router_8_15_rsp_in[3] = router_7_15_to_router_8_15_rsp; - assign router_8_15_rsp_in[4] = magia_tile_ni_8_15_to_router_8_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_15_req_in), - .floo_rsp_o (router_8_15_rsp_out), - .floo_req_o (router_8_15_req_out), - .floo_rsp_i (router_8_15_rsp_in) -); - - -floo_req_t [4:0] router_8_16_req_in; -floo_rsp_t [4:0] router_8_16_rsp_out; -floo_req_t [4:0] router_8_16_req_out; -floo_rsp_t [4:0] router_8_16_rsp_in; - - assign router_8_16_req_in[0] = router_8_17_to_router_8_16_req; - assign router_8_16_req_in[1] = router_9_16_to_router_8_16_req; - assign router_8_16_req_in[2] = router_8_15_to_router_8_16_req; - assign router_8_16_req_in[3] = router_7_16_to_router_8_16_req; - assign router_8_16_req_in[4] = magia_tile_ni_8_16_to_router_8_16_req; - - assign router_8_16_to_router_8_17_rsp = router_8_16_rsp_out[0]; - assign router_8_16_to_router_9_16_rsp = router_8_16_rsp_out[1]; - assign router_8_16_to_router_8_15_rsp = router_8_16_rsp_out[2]; - assign router_8_16_to_router_7_16_rsp = router_8_16_rsp_out[3]; - assign router_8_16_to_magia_tile_ni_8_16_rsp = router_8_16_rsp_out[4]; - - assign router_8_16_to_router_8_17_req = router_8_16_req_out[0]; - assign router_8_16_to_router_9_16_req = router_8_16_req_out[1]; - assign router_8_16_to_router_8_15_req = router_8_16_req_out[2]; - assign router_8_16_to_router_7_16_req = router_8_16_req_out[3]; - assign router_8_16_to_magia_tile_ni_8_16_req = router_8_16_req_out[4]; - - assign router_8_16_rsp_in[0] = router_8_17_to_router_8_16_rsp; - assign router_8_16_rsp_in[1] = router_9_16_to_router_8_16_rsp; - assign router_8_16_rsp_in[2] = router_8_15_to_router_8_16_rsp; - assign router_8_16_rsp_in[3] = router_7_16_to_router_8_16_rsp; - assign router_8_16_rsp_in[4] = magia_tile_ni_8_16_to_router_8_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_16_req_in), - .floo_rsp_o (router_8_16_rsp_out), - .floo_req_o (router_8_16_req_out), - .floo_rsp_i (router_8_16_rsp_in) -); - - -floo_req_t [4:0] router_8_17_req_in; -floo_rsp_t [4:0] router_8_17_rsp_out; -floo_req_t [4:0] router_8_17_req_out; -floo_rsp_t [4:0] router_8_17_rsp_in; - - assign router_8_17_req_in[0] = router_8_18_to_router_8_17_req; - assign router_8_17_req_in[1] = router_9_17_to_router_8_17_req; - assign router_8_17_req_in[2] = router_8_16_to_router_8_17_req; - assign router_8_17_req_in[3] = router_7_17_to_router_8_17_req; - assign router_8_17_req_in[4] = magia_tile_ni_8_17_to_router_8_17_req; - - assign router_8_17_to_router_8_18_rsp = router_8_17_rsp_out[0]; - assign router_8_17_to_router_9_17_rsp = router_8_17_rsp_out[1]; - assign router_8_17_to_router_8_16_rsp = router_8_17_rsp_out[2]; - assign router_8_17_to_router_7_17_rsp = router_8_17_rsp_out[3]; - assign router_8_17_to_magia_tile_ni_8_17_rsp = router_8_17_rsp_out[4]; - - assign router_8_17_to_router_8_18_req = router_8_17_req_out[0]; - assign router_8_17_to_router_9_17_req = router_8_17_req_out[1]; - assign router_8_17_to_router_8_16_req = router_8_17_req_out[2]; - assign router_8_17_to_router_7_17_req = router_8_17_req_out[3]; - assign router_8_17_to_magia_tile_ni_8_17_req = router_8_17_req_out[4]; - - assign router_8_17_rsp_in[0] = router_8_18_to_router_8_17_rsp; - assign router_8_17_rsp_in[1] = router_9_17_to_router_8_17_rsp; - assign router_8_17_rsp_in[2] = router_8_16_to_router_8_17_rsp; - assign router_8_17_rsp_in[3] = router_7_17_to_router_8_17_rsp; - assign router_8_17_rsp_in[4] = magia_tile_ni_8_17_to_router_8_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_17_req_in), - .floo_rsp_o (router_8_17_rsp_out), - .floo_req_o (router_8_17_req_out), - .floo_rsp_i (router_8_17_rsp_in) -); - - -floo_req_t [4:0] router_8_18_req_in; -floo_rsp_t [4:0] router_8_18_rsp_out; -floo_req_t [4:0] router_8_18_req_out; -floo_rsp_t [4:0] router_8_18_rsp_in; - - assign router_8_18_req_in[0] = router_8_19_to_router_8_18_req; - assign router_8_18_req_in[1] = router_9_18_to_router_8_18_req; - assign router_8_18_req_in[2] = router_8_17_to_router_8_18_req; - assign router_8_18_req_in[3] = router_7_18_to_router_8_18_req; - assign router_8_18_req_in[4] = magia_tile_ni_8_18_to_router_8_18_req; - - assign router_8_18_to_router_8_19_rsp = router_8_18_rsp_out[0]; - assign router_8_18_to_router_9_18_rsp = router_8_18_rsp_out[1]; - assign router_8_18_to_router_8_17_rsp = router_8_18_rsp_out[2]; - assign router_8_18_to_router_7_18_rsp = router_8_18_rsp_out[3]; - assign router_8_18_to_magia_tile_ni_8_18_rsp = router_8_18_rsp_out[4]; - - assign router_8_18_to_router_8_19_req = router_8_18_req_out[0]; - assign router_8_18_to_router_9_18_req = router_8_18_req_out[1]; - assign router_8_18_to_router_8_17_req = router_8_18_req_out[2]; - assign router_8_18_to_router_7_18_req = router_8_18_req_out[3]; - assign router_8_18_to_magia_tile_ni_8_18_req = router_8_18_req_out[4]; - - assign router_8_18_rsp_in[0] = router_8_19_to_router_8_18_rsp; - assign router_8_18_rsp_in[1] = router_9_18_to_router_8_18_rsp; - assign router_8_18_rsp_in[2] = router_8_17_to_router_8_18_rsp; - assign router_8_18_rsp_in[3] = router_7_18_to_router_8_18_rsp; - assign router_8_18_rsp_in[4] = magia_tile_ni_8_18_to_router_8_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_18_req_in), - .floo_rsp_o (router_8_18_rsp_out), - .floo_req_o (router_8_18_req_out), - .floo_rsp_i (router_8_18_rsp_in) -); - - -floo_req_t [4:0] router_8_19_req_in; -floo_rsp_t [4:0] router_8_19_rsp_out; -floo_req_t [4:0] router_8_19_req_out; -floo_rsp_t [4:0] router_8_19_rsp_in; - - assign router_8_19_req_in[0] = router_8_20_to_router_8_19_req; - assign router_8_19_req_in[1] = router_9_19_to_router_8_19_req; - assign router_8_19_req_in[2] = router_8_18_to_router_8_19_req; - assign router_8_19_req_in[3] = router_7_19_to_router_8_19_req; - assign router_8_19_req_in[4] = magia_tile_ni_8_19_to_router_8_19_req; - - assign router_8_19_to_router_8_20_rsp = router_8_19_rsp_out[0]; - assign router_8_19_to_router_9_19_rsp = router_8_19_rsp_out[1]; - assign router_8_19_to_router_8_18_rsp = router_8_19_rsp_out[2]; - assign router_8_19_to_router_7_19_rsp = router_8_19_rsp_out[3]; - assign router_8_19_to_magia_tile_ni_8_19_rsp = router_8_19_rsp_out[4]; - - assign router_8_19_to_router_8_20_req = router_8_19_req_out[0]; - assign router_8_19_to_router_9_19_req = router_8_19_req_out[1]; - assign router_8_19_to_router_8_18_req = router_8_19_req_out[2]; - assign router_8_19_to_router_7_19_req = router_8_19_req_out[3]; - assign router_8_19_to_magia_tile_ni_8_19_req = router_8_19_req_out[4]; - - assign router_8_19_rsp_in[0] = router_8_20_to_router_8_19_rsp; - assign router_8_19_rsp_in[1] = router_9_19_to_router_8_19_rsp; - assign router_8_19_rsp_in[2] = router_8_18_to_router_8_19_rsp; - assign router_8_19_rsp_in[3] = router_7_19_to_router_8_19_rsp; - assign router_8_19_rsp_in[4] = magia_tile_ni_8_19_to_router_8_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_19_req_in), - .floo_rsp_o (router_8_19_rsp_out), - .floo_req_o (router_8_19_req_out), - .floo_rsp_i (router_8_19_rsp_in) -); - - -floo_req_t [4:0] router_8_20_req_in; -floo_rsp_t [4:0] router_8_20_rsp_out; -floo_req_t [4:0] router_8_20_req_out; -floo_rsp_t [4:0] router_8_20_rsp_in; - - assign router_8_20_req_in[0] = router_8_21_to_router_8_20_req; - assign router_8_20_req_in[1] = router_9_20_to_router_8_20_req; - assign router_8_20_req_in[2] = router_8_19_to_router_8_20_req; - assign router_8_20_req_in[3] = router_7_20_to_router_8_20_req; - assign router_8_20_req_in[4] = magia_tile_ni_8_20_to_router_8_20_req; - - assign router_8_20_to_router_8_21_rsp = router_8_20_rsp_out[0]; - assign router_8_20_to_router_9_20_rsp = router_8_20_rsp_out[1]; - assign router_8_20_to_router_8_19_rsp = router_8_20_rsp_out[2]; - assign router_8_20_to_router_7_20_rsp = router_8_20_rsp_out[3]; - assign router_8_20_to_magia_tile_ni_8_20_rsp = router_8_20_rsp_out[4]; - - assign router_8_20_to_router_8_21_req = router_8_20_req_out[0]; - assign router_8_20_to_router_9_20_req = router_8_20_req_out[1]; - assign router_8_20_to_router_8_19_req = router_8_20_req_out[2]; - assign router_8_20_to_router_7_20_req = router_8_20_req_out[3]; - assign router_8_20_to_magia_tile_ni_8_20_req = router_8_20_req_out[4]; - - assign router_8_20_rsp_in[0] = router_8_21_to_router_8_20_rsp; - assign router_8_20_rsp_in[1] = router_9_20_to_router_8_20_rsp; - assign router_8_20_rsp_in[2] = router_8_19_to_router_8_20_rsp; - assign router_8_20_rsp_in[3] = router_7_20_to_router_8_20_rsp; - assign router_8_20_rsp_in[4] = magia_tile_ni_8_20_to_router_8_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_20_req_in), - .floo_rsp_o (router_8_20_rsp_out), - .floo_req_o (router_8_20_req_out), - .floo_rsp_i (router_8_20_rsp_in) -); - - -floo_req_t [4:0] router_8_21_req_in; -floo_rsp_t [4:0] router_8_21_rsp_out; -floo_req_t [4:0] router_8_21_req_out; -floo_rsp_t [4:0] router_8_21_rsp_in; - - assign router_8_21_req_in[0] = router_8_22_to_router_8_21_req; - assign router_8_21_req_in[1] = router_9_21_to_router_8_21_req; - assign router_8_21_req_in[2] = router_8_20_to_router_8_21_req; - assign router_8_21_req_in[3] = router_7_21_to_router_8_21_req; - assign router_8_21_req_in[4] = magia_tile_ni_8_21_to_router_8_21_req; - - assign router_8_21_to_router_8_22_rsp = router_8_21_rsp_out[0]; - assign router_8_21_to_router_9_21_rsp = router_8_21_rsp_out[1]; - assign router_8_21_to_router_8_20_rsp = router_8_21_rsp_out[2]; - assign router_8_21_to_router_7_21_rsp = router_8_21_rsp_out[3]; - assign router_8_21_to_magia_tile_ni_8_21_rsp = router_8_21_rsp_out[4]; - - assign router_8_21_to_router_8_22_req = router_8_21_req_out[0]; - assign router_8_21_to_router_9_21_req = router_8_21_req_out[1]; - assign router_8_21_to_router_8_20_req = router_8_21_req_out[2]; - assign router_8_21_to_router_7_21_req = router_8_21_req_out[3]; - assign router_8_21_to_magia_tile_ni_8_21_req = router_8_21_req_out[4]; - - assign router_8_21_rsp_in[0] = router_8_22_to_router_8_21_rsp; - assign router_8_21_rsp_in[1] = router_9_21_to_router_8_21_rsp; - assign router_8_21_rsp_in[2] = router_8_20_to_router_8_21_rsp; - assign router_8_21_rsp_in[3] = router_7_21_to_router_8_21_rsp; - assign router_8_21_rsp_in[4] = magia_tile_ni_8_21_to_router_8_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_21_req_in), - .floo_rsp_o (router_8_21_rsp_out), - .floo_req_o (router_8_21_req_out), - .floo_rsp_i (router_8_21_rsp_in) -); - - -floo_req_t [4:0] router_8_22_req_in; -floo_rsp_t [4:0] router_8_22_rsp_out; -floo_req_t [4:0] router_8_22_req_out; -floo_rsp_t [4:0] router_8_22_rsp_in; - - assign router_8_22_req_in[0] = router_8_23_to_router_8_22_req; - assign router_8_22_req_in[1] = router_9_22_to_router_8_22_req; - assign router_8_22_req_in[2] = router_8_21_to_router_8_22_req; - assign router_8_22_req_in[3] = router_7_22_to_router_8_22_req; - assign router_8_22_req_in[4] = magia_tile_ni_8_22_to_router_8_22_req; - - assign router_8_22_to_router_8_23_rsp = router_8_22_rsp_out[0]; - assign router_8_22_to_router_9_22_rsp = router_8_22_rsp_out[1]; - assign router_8_22_to_router_8_21_rsp = router_8_22_rsp_out[2]; - assign router_8_22_to_router_7_22_rsp = router_8_22_rsp_out[3]; - assign router_8_22_to_magia_tile_ni_8_22_rsp = router_8_22_rsp_out[4]; - - assign router_8_22_to_router_8_23_req = router_8_22_req_out[0]; - assign router_8_22_to_router_9_22_req = router_8_22_req_out[1]; - assign router_8_22_to_router_8_21_req = router_8_22_req_out[2]; - assign router_8_22_to_router_7_22_req = router_8_22_req_out[3]; - assign router_8_22_to_magia_tile_ni_8_22_req = router_8_22_req_out[4]; - - assign router_8_22_rsp_in[0] = router_8_23_to_router_8_22_rsp; - assign router_8_22_rsp_in[1] = router_9_22_to_router_8_22_rsp; - assign router_8_22_rsp_in[2] = router_8_21_to_router_8_22_rsp; - assign router_8_22_rsp_in[3] = router_7_22_to_router_8_22_rsp; - assign router_8_22_rsp_in[4] = magia_tile_ni_8_22_to_router_8_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_22_req_in), - .floo_rsp_o (router_8_22_rsp_out), - .floo_req_o (router_8_22_req_out), - .floo_rsp_i (router_8_22_rsp_in) -); - - -floo_req_t [4:0] router_8_23_req_in; -floo_rsp_t [4:0] router_8_23_rsp_out; -floo_req_t [4:0] router_8_23_req_out; -floo_rsp_t [4:0] router_8_23_rsp_in; - - assign router_8_23_req_in[0] = router_8_24_to_router_8_23_req; - assign router_8_23_req_in[1] = router_9_23_to_router_8_23_req; - assign router_8_23_req_in[2] = router_8_22_to_router_8_23_req; - assign router_8_23_req_in[3] = router_7_23_to_router_8_23_req; - assign router_8_23_req_in[4] = magia_tile_ni_8_23_to_router_8_23_req; - - assign router_8_23_to_router_8_24_rsp = router_8_23_rsp_out[0]; - assign router_8_23_to_router_9_23_rsp = router_8_23_rsp_out[1]; - assign router_8_23_to_router_8_22_rsp = router_8_23_rsp_out[2]; - assign router_8_23_to_router_7_23_rsp = router_8_23_rsp_out[3]; - assign router_8_23_to_magia_tile_ni_8_23_rsp = router_8_23_rsp_out[4]; - - assign router_8_23_to_router_8_24_req = router_8_23_req_out[0]; - assign router_8_23_to_router_9_23_req = router_8_23_req_out[1]; - assign router_8_23_to_router_8_22_req = router_8_23_req_out[2]; - assign router_8_23_to_router_7_23_req = router_8_23_req_out[3]; - assign router_8_23_to_magia_tile_ni_8_23_req = router_8_23_req_out[4]; - - assign router_8_23_rsp_in[0] = router_8_24_to_router_8_23_rsp; - assign router_8_23_rsp_in[1] = router_9_23_to_router_8_23_rsp; - assign router_8_23_rsp_in[2] = router_8_22_to_router_8_23_rsp; - assign router_8_23_rsp_in[3] = router_7_23_to_router_8_23_rsp; - assign router_8_23_rsp_in[4] = magia_tile_ni_8_23_to_router_8_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_23_req_in), - .floo_rsp_o (router_8_23_rsp_out), - .floo_req_o (router_8_23_req_out), - .floo_rsp_i (router_8_23_rsp_in) -); - - -floo_req_t [4:0] router_8_24_req_in; -floo_rsp_t [4:0] router_8_24_rsp_out; -floo_req_t [4:0] router_8_24_req_out; -floo_rsp_t [4:0] router_8_24_rsp_in; - - assign router_8_24_req_in[0] = router_8_25_to_router_8_24_req; - assign router_8_24_req_in[1] = router_9_24_to_router_8_24_req; - assign router_8_24_req_in[2] = router_8_23_to_router_8_24_req; - assign router_8_24_req_in[3] = router_7_24_to_router_8_24_req; - assign router_8_24_req_in[4] = magia_tile_ni_8_24_to_router_8_24_req; - - assign router_8_24_to_router_8_25_rsp = router_8_24_rsp_out[0]; - assign router_8_24_to_router_9_24_rsp = router_8_24_rsp_out[1]; - assign router_8_24_to_router_8_23_rsp = router_8_24_rsp_out[2]; - assign router_8_24_to_router_7_24_rsp = router_8_24_rsp_out[3]; - assign router_8_24_to_magia_tile_ni_8_24_rsp = router_8_24_rsp_out[4]; - - assign router_8_24_to_router_8_25_req = router_8_24_req_out[0]; - assign router_8_24_to_router_9_24_req = router_8_24_req_out[1]; - assign router_8_24_to_router_8_23_req = router_8_24_req_out[2]; - assign router_8_24_to_router_7_24_req = router_8_24_req_out[3]; - assign router_8_24_to_magia_tile_ni_8_24_req = router_8_24_req_out[4]; - - assign router_8_24_rsp_in[0] = router_8_25_to_router_8_24_rsp; - assign router_8_24_rsp_in[1] = router_9_24_to_router_8_24_rsp; - assign router_8_24_rsp_in[2] = router_8_23_to_router_8_24_rsp; - assign router_8_24_rsp_in[3] = router_7_24_to_router_8_24_rsp; - assign router_8_24_rsp_in[4] = magia_tile_ni_8_24_to_router_8_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_24_req_in), - .floo_rsp_o (router_8_24_rsp_out), - .floo_req_o (router_8_24_req_out), - .floo_rsp_i (router_8_24_rsp_in) -); - - -floo_req_t [4:0] router_8_25_req_in; -floo_rsp_t [4:0] router_8_25_rsp_out; -floo_req_t [4:0] router_8_25_req_out; -floo_rsp_t [4:0] router_8_25_rsp_in; - - assign router_8_25_req_in[0] = router_8_26_to_router_8_25_req; - assign router_8_25_req_in[1] = router_9_25_to_router_8_25_req; - assign router_8_25_req_in[2] = router_8_24_to_router_8_25_req; - assign router_8_25_req_in[3] = router_7_25_to_router_8_25_req; - assign router_8_25_req_in[4] = magia_tile_ni_8_25_to_router_8_25_req; - - assign router_8_25_to_router_8_26_rsp = router_8_25_rsp_out[0]; - assign router_8_25_to_router_9_25_rsp = router_8_25_rsp_out[1]; - assign router_8_25_to_router_8_24_rsp = router_8_25_rsp_out[2]; - assign router_8_25_to_router_7_25_rsp = router_8_25_rsp_out[3]; - assign router_8_25_to_magia_tile_ni_8_25_rsp = router_8_25_rsp_out[4]; - - assign router_8_25_to_router_8_26_req = router_8_25_req_out[0]; - assign router_8_25_to_router_9_25_req = router_8_25_req_out[1]; - assign router_8_25_to_router_8_24_req = router_8_25_req_out[2]; - assign router_8_25_to_router_7_25_req = router_8_25_req_out[3]; - assign router_8_25_to_magia_tile_ni_8_25_req = router_8_25_req_out[4]; - - assign router_8_25_rsp_in[0] = router_8_26_to_router_8_25_rsp; - assign router_8_25_rsp_in[1] = router_9_25_to_router_8_25_rsp; - assign router_8_25_rsp_in[2] = router_8_24_to_router_8_25_rsp; - assign router_8_25_rsp_in[3] = router_7_25_to_router_8_25_rsp; - assign router_8_25_rsp_in[4] = magia_tile_ni_8_25_to_router_8_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_25_req_in), - .floo_rsp_o (router_8_25_rsp_out), - .floo_req_o (router_8_25_req_out), - .floo_rsp_i (router_8_25_rsp_in) -); - - -floo_req_t [4:0] router_8_26_req_in; -floo_rsp_t [4:0] router_8_26_rsp_out; -floo_req_t [4:0] router_8_26_req_out; -floo_rsp_t [4:0] router_8_26_rsp_in; - - assign router_8_26_req_in[0] = router_8_27_to_router_8_26_req; - assign router_8_26_req_in[1] = router_9_26_to_router_8_26_req; - assign router_8_26_req_in[2] = router_8_25_to_router_8_26_req; - assign router_8_26_req_in[3] = router_7_26_to_router_8_26_req; - assign router_8_26_req_in[4] = magia_tile_ni_8_26_to_router_8_26_req; - - assign router_8_26_to_router_8_27_rsp = router_8_26_rsp_out[0]; - assign router_8_26_to_router_9_26_rsp = router_8_26_rsp_out[1]; - assign router_8_26_to_router_8_25_rsp = router_8_26_rsp_out[2]; - assign router_8_26_to_router_7_26_rsp = router_8_26_rsp_out[3]; - assign router_8_26_to_magia_tile_ni_8_26_rsp = router_8_26_rsp_out[4]; - - assign router_8_26_to_router_8_27_req = router_8_26_req_out[0]; - assign router_8_26_to_router_9_26_req = router_8_26_req_out[1]; - assign router_8_26_to_router_8_25_req = router_8_26_req_out[2]; - assign router_8_26_to_router_7_26_req = router_8_26_req_out[3]; - assign router_8_26_to_magia_tile_ni_8_26_req = router_8_26_req_out[4]; - - assign router_8_26_rsp_in[0] = router_8_27_to_router_8_26_rsp; - assign router_8_26_rsp_in[1] = router_9_26_to_router_8_26_rsp; - assign router_8_26_rsp_in[2] = router_8_25_to_router_8_26_rsp; - assign router_8_26_rsp_in[3] = router_7_26_to_router_8_26_rsp; - assign router_8_26_rsp_in[4] = magia_tile_ni_8_26_to_router_8_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_26_req_in), - .floo_rsp_o (router_8_26_rsp_out), - .floo_req_o (router_8_26_req_out), - .floo_rsp_i (router_8_26_rsp_in) -); - - -floo_req_t [4:0] router_8_27_req_in; -floo_rsp_t [4:0] router_8_27_rsp_out; -floo_req_t [4:0] router_8_27_req_out; -floo_rsp_t [4:0] router_8_27_rsp_in; - - assign router_8_27_req_in[0] = router_8_28_to_router_8_27_req; - assign router_8_27_req_in[1] = router_9_27_to_router_8_27_req; - assign router_8_27_req_in[2] = router_8_26_to_router_8_27_req; - assign router_8_27_req_in[3] = router_7_27_to_router_8_27_req; - assign router_8_27_req_in[4] = magia_tile_ni_8_27_to_router_8_27_req; - - assign router_8_27_to_router_8_28_rsp = router_8_27_rsp_out[0]; - assign router_8_27_to_router_9_27_rsp = router_8_27_rsp_out[1]; - assign router_8_27_to_router_8_26_rsp = router_8_27_rsp_out[2]; - assign router_8_27_to_router_7_27_rsp = router_8_27_rsp_out[3]; - assign router_8_27_to_magia_tile_ni_8_27_rsp = router_8_27_rsp_out[4]; - - assign router_8_27_to_router_8_28_req = router_8_27_req_out[0]; - assign router_8_27_to_router_9_27_req = router_8_27_req_out[1]; - assign router_8_27_to_router_8_26_req = router_8_27_req_out[2]; - assign router_8_27_to_router_7_27_req = router_8_27_req_out[3]; - assign router_8_27_to_magia_tile_ni_8_27_req = router_8_27_req_out[4]; - - assign router_8_27_rsp_in[0] = router_8_28_to_router_8_27_rsp; - assign router_8_27_rsp_in[1] = router_9_27_to_router_8_27_rsp; - assign router_8_27_rsp_in[2] = router_8_26_to_router_8_27_rsp; - assign router_8_27_rsp_in[3] = router_7_27_to_router_8_27_rsp; - assign router_8_27_rsp_in[4] = magia_tile_ni_8_27_to_router_8_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_27_req_in), - .floo_rsp_o (router_8_27_rsp_out), - .floo_req_o (router_8_27_req_out), - .floo_rsp_i (router_8_27_rsp_in) -); - - -floo_req_t [4:0] router_8_28_req_in; -floo_rsp_t [4:0] router_8_28_rsp_out; -floo_req_t [4:0] router_8_28_req_out; -floo_rsp_t [4:0] router_8_28_rsp_in; - - assign router_8_28_req_in[0] = router_8_29_to_router_8_28_req; - assign router_8_28_req_in[1] = router_9_28_to_router_8_28_req; - assign router_8_28_req_in[2] = router_8_27_to_router_8_28_req; - assign router_8_28_req_in[3] = router_7_28_to_router_8_28_req; - assign router_8_28_req_in[4] = magia_tile_ni_8_28_to_router_8_28_req; - - assign router_8_28_to_router_8_29_rsp = router_8_28_rsp_out[0]; - assign router_8_28_to_router_9_28_rsp = router_8_28_rsp_out[1]; - assign router_8_28_to_router_8_27_rsp = router_8_28_rsp_out[2]; - assign router_8_28_to_router_7_28_rsp = router_8_28_rsp_out[3]; - assign router_8_28_to_magia_tile_ni_8_28_rsp = router_8_28_rsp_out[4]; - - assign router_8_28_to_router_8_29_req = router_8_28_req_out[0]; - assign router_8_28_to_router_9_28_req = router_8_28_req_out[1]; - assign router_8_28_to_router_8_27_req = router_8_28_req_out[2]; - assign router_8_28_to_router_7_28_req = router_8_28_req_out[3]; - assign router_8_28_to_magia_tile_ni_8_28_req = router_8_28_req_out[4]; - - assign router_8_28_rsp_in[0] = router_8_29_to_router_8_28_rsp; - assign router_8_28_rsp_in[1] = router_9_28_to_router_8_28_rsp; - assign router_8_28_rsp_in[2] = router_8_27_to_router_8_28_rsp; - assign router_8_28_rsp_in[3] = router_7_28_to_router_8_28_rsp; - assign router_8_28_rsp_in[4] = magia_tile_ni_8_28_to_router_8_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_28_req_in), - .floo_rsp_o (router_8_28_rsp_out), - .floo_req_o (router_8_28_req_out), - .floo_rsp_i (router_8_28_rsp_in) -); - - -floo_req_t [4:0] router_8_29_req_in; -floo_rsp_t [4:0] router_8_29_rsp_out; -floo_req_t [4:0] router_8_29_req_out; -floo_rsp_t [4:0] router_8_29_rsp_in; - - assign router_8_29_req_in[0] = router_8_30_to_router_8_29_req; - assign router_8_29_req_in[1] = router_9_29_to_router_8_29_req; - assign router_8_29_req_in[2] = router_8_28_to_router_8_29_req; - assign router_8_29_req_in[3] = router_7_29_to_router_8_29_req; - assign router_8_29_req_in[4] = magia_tile_ni_8_29_to_router_8_29_req; - - assign router_8_29_to_router_8_30_rsp = router_8_29_rsp_out[0]; - assign router_8_29_to_router_9_29_rsp = router_8_29_rsp_out[1]; - assign router_8_29_to_router_8_28_rsp = router_8_29_rsp_out[2]; - assign router_8_29_to_router_7_29_rsp = router_8_29_rsp_out[3]; - assign router_8_29_to_magia_tile_ni_8_29_rsp = router_8_29_rsp_out[4]; - - assign router_8_29_to_router_8_30_req = router_8_29_req_out[0]; - assign router_8_29_to_router_9_29_req = router_8_29_req_out[1]; - assign router_8_29_to_router_8_28_req = router_8_29_req_out[2]; - assign router_8_29_to_router_7_29_req = router_8_29_req_out[3]; - assign router_8_29_to_magia_tile_ni_8_29_req = router_8_29_req_out[4]; - - assign router_8_29_rsp_in[0] = router_8_30_to_router_8_29_rsp; - assign router_8_29_rsp_in[1] = router_9_29_to_router_8_29_rsp; - assign router_8_29_rsp_in[2] = router_8_28_to_router_8_29_rsp; - assign router_8_29_rsp_in[3] = router_7_29_to_router_8_29_rsp; - assign router_8_29_rsp_in[4] = magia_tile_ni_8_29_to_router_8_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_29_req_in), - .floo_rsp_o (router_8_29_rsp_out), - .floo_req_o (router_8_29_req_out), - .floo_rsp_i (router_8_29_rsp_in) -); - - -floo_req_t [4:0] router_8_30_req_in; -floo_rsp_t [4:0] router_8_30_rsp_out; -floo_req_t [4:0] router_8_30_req_out; -floo_rsp_t [4:0] router_8_30_rsp_in; - - assign router_8_30_req_in[0] = router_8_31_to_router_8_30_req; - assign router_8_30_req_in[1] = router_9_30_to_router_8_30_req; - assign router_8_30_req_in[2] = router_8_29_to_router_8_30_req; - assign router_8_30_req_in[3] = router_7_30_to_router_8_30_req; - assign router_8_30_req_in[4] = magia_tile_ni_8_30_to_router_8_30_req; - - assign router_8_30_to_router_8_31_rsp = router_8_30_rsp_out[0]; - assign router_8_30_to_router_9_30_rsp = router_8_30_rsp_out[1]; - assign router_8_30_to_router_8_29_rsp = router_8_30_rsp_out[2]; - assign router_8_30_to_router_7_30_rsp = router_8_30_rsp_out[3]; - assign router_8_30_to_magia_tile_ni_8_30_rsp = router_8_30_rsp_out[4]; - - assign router_8_30_to_router_8_31_req = router_8_30_req_out[0]; - assign router_8_30_to_router_9_30_req = router_8_30_req_out[1]; - assign router_8_30_to_router_8_29_req = router_8_30_req_out[2]; - assign router_8_30_to_router_7_30_req = router_8_30_req_out[3]; - assign router_8_30_to_magia_tile_ni_8_30_req = router_8_30_req_out[4]; - - assign router_8_30_rsp_in[0] = router_8_31_to_router_8_30_rsp; - assign router_8_30_rsp_in[1] = router_9_30_to_router_8_30_rsp; - assign router_8_30_rsp_in[2] = router_8_29_to_router_8_30_rsp; - assign router_8_30_rsp_in[3] = router_7_30_to_router_8_30_rsp; - assign router_8_30_rsp_in[4] = magia_tile_ni_8_30_to_router_8_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_30_req_in), - .floo_rsp_o (router_8_30_rsp_out), - .floo_req_o (router_8_30_req_out), - .floo_rsp_i (router_8_30_rsp_in) -); - - -floo_req_t [4:0] router_8_31_req_in; -floo_rsp_t [4:0] router_8_31_rsp_out; -floo_req_t [4:0] router_8_31_req_out; -floo_rsp_t [4:0] router_8_31_rsp_in; - - assign router_8_31_req_in[0] = '0; - assign router_8_31_req_in[1] = router_9_31_to_router_8_31_req; - assign router_8_31_req_in[2] = router_8_30_to_router_8_31_req; - assign router_8_31_req_in[3] = router_7_31_to_router_8_31_req; - assign router_8_31_req_in[4] = magia_tile_ni_8_31_to_router_8_31_req; - - assign router_8_31_to_router_9_31_rsp = router_8_31_rsp_out[1]; - assign router_8_31_to_router_8_30_rsp = router_8_31_rsp_out[2]; - assign router_8_31_to_router_7_31_rsp = router_8_31_rsp_out[3]; - assign router_8_31_to_magia_tile_ni_8_31_rsp = router_8_31_rsp_out[4]; - - assign router_8_31_to_router_9_31_req = router_8_31_req_out[1]; - assign router_8_31_to_router_8_30_req = router_8_31_req_out[2]; - assign router_8_31_to_router_7_31_req = router_8_31_req_out[3]; - assign router_8_31_to_magia_tile_ni_8_31_req = router_8_31_req_out[4]; - - assign router_8_31_rsp_in[0] = '0; - assign router_8_31_rsp_in[1] = router_9_31_to_router_8_31_rsp; - assign router_8_31_rsp_in[2] = router_8_30_to_router_8_31_rsp; - assign router_8_31_rsp_in[3] = router_7_31_to_router_8_31_rsp; - assign router_8_31_rsp_in[4] = magia_tile_ni_8_31_to_router_8_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_8_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 9, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_8_31_req_in), - .floo_rsp_o (router_8_31_rsp_out), - .floo_req_o (router_8_31_req_out), - .floo_rsp_i (router_8_31_rsp_in) -); - - -floo_req_t [4:0] router_9_0_req_in; -floo_rsp_t [4:0] router_9_0_rsp_out; -floo_req_t [4:0] router_9_0_req_out; -floo_rsp_t [4:0] router_9_0_rsp_in; - - assign router_9_0_req_in[0] = router_9_1_to_router_9_0_req; - assign router_9_0_req_in[1] = router_10_0_to_router_9_0_req; - assign router_9_0_req_in[2] = '0; - assign router_9_0_req_in[3] = router_8_0_to_router_9_0_req; - assign router_9_0_req_in[4] = magia_tile_ni_9_0_to_router_9_0_req; - - assign router_9_0_to_router_9_1_rsp = router_9_0_rsp_out[0]; - assign router_9_0_to_router_10_0_rsp = router_9_0_rsp_out[1]; - assign router_9_0_to_router_8_0_rsp = router_9_0_rsp_out[3]; - assign router_9_0_to_magia_tile_ni_9_0_rsp = router_9_0_rsp_out[4]; - - assign router_9_0_to_router_9_1_req = router_9_0_req_out[0]; - assign router_9_0_to_router_10_0_req = router_9_0_req_out[1]; - assign router_9_0_to_router_8_0_req = router_9_0_req_out[3]; - assign router_9_0_to_magia_tile_ni_9_0_req = router_9_0_req_out[4]; - - assign router_9_0_rsp_in[0] = router_9_1_to_router_9_0_rsp; - assign router_9_0_rsp_in[1] = router_10_0_to_router_9_0_rsp; - assign router_9_0_rsp_in[2] = '0; - assign router_9_0_rsp_in[3] = router_8_0_to_router_9_0_rsp; - assign router_9_0_rsp_in[4] = magia_tile_ni_9_0_to_router_9_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_0_req_in), - .floo_rsp_o (router_9_0_rsp_out), - .floo_req_o (router_9_0_req_out), - .floo_rsp_i (router_9_0_rsp_in) -); - - -floo_req_t [4:0] router_9_1_req_in; -floo_rsp_t [4:0] router_9_1_rsp_out; -floo_req_t [4:0] router_9_1_req_out; -floo_rsp_t [4:0] router_9_1_rsp_in; - - assign router_9_1_req_in[0] = router_9_2_to_router_9_1_req; - assign router_9_1_req_in[1] = router_10_1_to_router_9_1_req; - assign router_9_1_req_in[2] = router_9_0_to_router_9_1_req; - assign router_9_1_req_in[3] = router_8_1_to_router_9_1_req; - assign router_9_1_req_in[4] = magia_tile_ni_9_1_to_router_9_1_req; - - assign router_9_1_to_router_9_2_rsp = router_9_1_rsp_out[0]; - assign router_9_1_to_router_10_1_rsp = router_9_1_rsp_out[1]; - assign router_9_1_to_router_9_0_rsp = router_9_1_rsp_out[2]; - assign router_9_1_to_router_8_1_rsp = router_9_1_rsp_out[3]; - assign router_9_1_to_magia_tile_ni_9_1_rsp = router_9_1_rsp_out[4]; - - assign router_9_1_to_router_9_2_req = router_9_1_req_out[0]; - assign router_9_1_to_router_10_1_req = router_9_1_req_out[1]; - assign router_9_1_to_router_9_0_req = router_9_1_req_out[2]; - assign router_9_1_to_router_8_1_req = router_9_1_req_out[3]; - assign router_9_1_to_magia_tile_ni_9_1_req = router_9_1_req_out[4]; - - assign router_9_1_rsp_in[0] = router_9_2_to_router_9_1_rsp; - assign router_9_1_rsp_in[1] = router_10_1_to_router_9_1_rsp; - assign router_9_1_rsp_in[2] = router_9_0_to_router_9_1_rsp; - assign router_9_1_rsp_in[3] = router_8_1_to_router_9_1_rsp; - assign router_9_1_rsp_in[4] = magia_tile_ni_9_1_to_router_9_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_1_req_in), - .floo_rsp_o (router_9_1_rsp_out), - .floo_req_o (router_9_1_req_out), - .floo_rsp_i (router_9_1_rsp_in) -); - - -floo_req_t [4:0] router_9_2_req_in; -floo_rsp_t [4:0] router_9_2_rsp_out; -floo_req_t [4:0] router_9_2_req_out; -floo_rsp_t [4:0] router_9_2_rsp_in; - - assign router_9_2_req_in[0] = router_9_3_to_router_9_2_req; - assign router_9_2_req_in[1] = router_10_2_to_router_9_2_req; - assign router_9_2_req_in[2] = router_9_1_to_router_9_2_req; - assign router_9_2_req_in[3] = router_8_2_to_router_9_2_req; - assign router_9_2_req_in[4] = magia_tile_ni_9_2_to_router_9_2_req; - - assign router_9_2_to_router_9_3_rsp = router_9_2_rsp_out[0]; - assign router_9_2_to_router_10_2_rsp = router_9_2_rsp_out[1]; - assign router_9_2_to_router_9_1_rsp = router_9_2_rsp_out[2]; - assign router_9_2_to_router_8_2_rsp = router_9_2_rsp_out[3]; - assign router_9_2_to_magia_tile_ni_9_2_rsp = router_9_2_rsp_out[4]; - - assign router_9_2_to_router_9_3_req = router_9_2_req_out[0]; - assign router_9_2_to_router_10_2_req = router_9_2_req_out[1]; - assign router_9_2_to_router_9_1_req = router_9_2_req_out[2]; - assign router_9_2_to_router_8_2_req = router_9_2_req_out[3]; - assign router_9_2_to_magia_tile_ni_9_2_req = router_9_2_req_out[4]; - - assign router_9_2_rsp_in[0] = router_9_3_to_router_9_2_rsp; - assign router_9_2_rsp_in[1] = router_10_2_to_router_9_2_rsp; - assign router_9_2_rsp_in[2] = router_9_1_to_router_9_2_rsp; - assign router_9_2_rsp_in[3] = router_8_2_to_router_9_2_rsp; - assign router_9_2_rsp_in[4] = magia_tile_ni_9_2_to_router_9_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_2_req_in), - .floo_rsp_o (router_9_2_rsp_out), - .floo_req_o (router_9_2_req_out), - .floo_rsp_i (router_9_2_rsp_in) -); - - -floo_req_t [4:0] router_9_3_req_in; -floo_rsp_t [4:0] router_9_3_rsp_out; -floo_req_t [4:0] router_9_3_req_out; -floo_rsp_t [4:0] router_9_3_rsp_in; - - assign router_9_3_req_in[0] = router_9_4_to_router_9_3_req; - assign router_9_3_req_in[1] = router_10_3_to_router_9_3_req; - assign router_9_3_req_in[2] = router_9_2_to_router_9_3_req; - assign router_9_3_req_in[3] = router_8_3_to_router_9_3_req; - assign router_9_3_req_in[4] = magia_tile_ni_9_3_to_router_9_3_req; - - assign router_9_3_to_router_9_4_rsp = router_9_3_rsp_out[0]; - assign router_9_3_to_router_10_3_rsp = router_9_3_rsp_out[1]; - assign router_9_3_to_router_9_2_rsp = router_9_3_rsp_out[2]; - assign router_9_3_to_router_8_3_rsp = router_9_3_rsp_out[3]; - assign router_9_3_to_magia_tile_ni_9_3_rsp = router_9_3_rsp_out[4]; - - assign router_9_3_to_router_9_4_req = router_9_3_req_out[0]; - assign router_9_3_to_router_10_3_req = router_9_3_req_out[1]; - assign router_9_3_to_router_9_2_req = router_9_3_req_out[2]; - assign router_9_3_to_router_8_3_req = router_9_3_req_out[3]; - assign router_9_3_to_magia_tile_ni_9_3_req = router_9_3_req_out[4]; - - assign router_9_3_rsp_in[0] = router_9_4_to_router_9_3_rsp; - assign router_9_3_rsp_in[1] = router_10_3_to_router_9_3_rsp; - assign router_9_3_rsp_in[2] = router_9_2_to_router_9_3_rsp; - assign router_9_3_rsp_in[3] = router_8_3_to_router_9_3_rsp; - assign router_9_3_rsp_in[4] = magia_tile_ni_9_3_to_router_9_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_3_req_in), - .floo_rsp_o (router_9_3_rsp_out), - .floo_req_o (router_9_3_req_out), - .floo_rsp_i (router_9_3_rsp_in) -); - - -floo_req_t [4:0] router_9_4_req_in; -floo_rsp_t [4:0] router_9_4_rsp_out; -floo_req_t [4:0] router_9_4_req_out; -floo_rsp_t [4:0] router_9_4_rsp_in; - - assign router_9_4_req_in[0] = router_9_5_to_router_9_4_req; - assign router_9_4_req_in[1] = router_10_4_to_router_9_4_req; - assign router_9_4_req_in[2] = router_9_3_to_router_9_4_req; - assign router_9_4_req_in[3] = router_8_4_to_router_9_4_req; - assign router_9_4_req_in[4] = magia_tile_ni_9_4_to_router_9_4_req; - - assign router_9_4_to_router_9_5_rsp = router_9_4_rsp_out[0]; - assign router_9_4_to_router_10_4_rsp = router_9_4_rsp_out[1]; - assign router_9_4_to_router_9_3_rsp = router_9_4_rsp_out[2]; - assign router_9_4_to_router_8_4_rsp = router_9_4_rsp_out[3]; - assign router_9_4_to_magia_tile_ni_9_4_rsp = router_9_4_rsp_out[4]; - - assign router_9_4_to_router_9_5_req = router_9_4_req_out[0]; - assign router_9_4_to_router_10_4_req = router_9_4_req_out[1]; - assign router_9_4_to_router_9_3_req = router_9_4_req_out[2]; - assign router_9_4_to_router_8_4_req = router_9_4_req_out[3]; - assign router_9_4_to_magia_tile_ni_9_4_req = router_9_4_req_out[4]; - - assign router_9_4_rsp_in[0] = router_9_5_to_router_9_4_rsp; - assign router_9_4_rsp_in[1] = router_10_4_to_router_9_4_rsp; - assign router_9_4_rsp_in[2] = router_9_3_to_router_9_4_rsp; - assign router_9_4_rsp_in[3] = router_8_4_to_router_9_4_rsp; - assign router_9_4_rsp_in[4] = magia_tile_ni_9_4_to_router_9_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_4_req_in), - .floo_rsp_o (router_9_4_rsp_out), - .floo_req_o (router_9_4_req_out), - .floo_rsp_i (router_9_4_rsp_in) -); - - -floo_req_t [4:0] router_9_5_req_in; -floo_rsp_t [4:0] router_9_5_rsp_out; -floo_req_t [4:0] router_9_5_req_out; -floo_rsp_t [4:0] router_9_5_rsp_in; - - assign router_9_5_req_in[0] = router_9_6_to_router_9_5_req; - assign router_9_5_req_in[1] = router_10_5_to_router_9_5_req; - assign router_9_5_req_in[2] = router_9_4_to_router_9_5_req; - assign router_9_5_req_in[3] = router_8_5_to_router_9_5_req; - assign router_9_5_req_in[4] = magia_tile_ni_9_5_to_router_9_5_req; - - assign router_9_5_to_router_9_6_rsp = router_9_5_rsp_out[0]; - assign router_9_5_to_router_10_5_rsp = router_9_5_rsp_out[1]; - assign router_9_5_to_router_9_4_rsp = router_9_5_rsp_out[2]; - assign router_9_5_to_router_8_5_rsp = router_9_5_rsp_out[3]; - assign router_9_5_to_magia_tile_ni_9_5_rsp = router_9_5_rsp_out[4]; - - assign router_9_5_to_router_9_6_req = router_9_5_req_out[0]; - assign router_9_5_to_router_10_5_req = router_9_5_req_out[1]; - assign router_9_5_to_router_9_4_req = router_9_5_req_out[2]; - assign router_9_5_to_router_8_5_req = router_9_5_req_out[3]; - assign router_9_5_to_magia_tile_ni_9_5_req = router_9_5_req_out[4]; - - assign router_9_5_rsp_in[0] = router_9_6_to_router_9_5_rsp; - assign router_9_5_rsp_in[1] = router_10_5_to_router_9_5_rsp; - assign router_9_5_rsp_in[2] = router_9_4_to_router_9_5_rsp; - assign router_9_5_rsp_in[3] = router_8_5_to_router_9_5_rsp; - assign router_9_5_rsp_in[4] = magia_tile_ni_9_5_to_router_9_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_5_req_in), - .floo_rsp_o (router_9_5_rsp_out), - .floo_req_o (router_9_5_req_out), - .floo_rsp_i (router_9_5_rsp_in) -); - - -floo_req_t [4:0] router_9_6_req_in; -floo_rsp_t [4:0] router_9_6_rsp_out; -floo_req_t [4:0] router_9_6_req_out; -floo_rsp_t [4:0] router_9_6_rsp_in; - - assign router_9_6_req_in[0] = router_9_7_to_router_9_6_req; - assign router_9_6_req_in[1] = router_10_6_to_router_9_6_req; - assign router_9_6_req_in[2] = router_9_5_to_router_9_6_req; - assign router_9_6_req_in[3] = router_8_6_to_router_9_6_req; - assign router_9_6_req_in[4] = magia_tile_ni_9_6_to_router_9_6_req; - - assign router_9_6_to_router_9_7_rsp = router_9_6_rsp_out[0]; - assign router_9_6_to_router_10_6_rsp = router_9_6_rsp_out[1]; - assign router_9_6_to_router_9_5_rsp = router_9_6_rsp_out[2]; - assign router_9_6_to_router_8_6_rsp = router_9_6_rsp_out[3]; - assign router_9_6_to_magia_tile_ni_9_6_rsp = router_9_6_rsp_out[4]; - - assign router_9_6_to_router_9_7_req = router_9_6_req_out[0]; - assign router_9_6_to_router_10_6_req = router_9_6_req_out[1]; - assign router_9_6_to_router_9_5_req = router_9_6_req_out[2]; - assign router_9_6_to_router_8_6_req = router_9_6_req_out[3]; - assign router_9_6_to_magia_tile_ni_9_6_req = router_9_6_req_out[4]; - - assign router_9_6_rsp_in[0] = router_9_7_to_router_9_6_rsp; - assign router_9_6_rsp_in[1] = router_10_6_to_router_9_6_rsp; - assign router_9_6_rsp_in[2] = router_9_5_to_router_9_6_rsp; - assign router_9_6_rsp_in[3] = router_8_6_to_router_9_6_rsp; - assign router_9_6_rsp_in[4] = magia_tile_ni_9_6_to_router_9_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_6_req_in), - .floo_rsp_o (router_9_6_rsp_out), - .floo_req_o (router_9_6_req_out), - .floo_rsp_i (router_9_6_rsp_in) -); - - -floo_req_t [4:0] router_9_7_req_in; -floo_rsp_t [4:0] router_9_7_rsp_out; -floo_req_t [4:0] router_9_7_req_out; -floo_rsp_t [4:0] router_9_7_rsp_in; - - assign router_9_7_req_in[0] = router_9_8_to_router_9_7_req; - assign router_9_7_req_in[1] = router_10_7_to_router_9_7_req; - assign router_9_7_req_in[2] = router_9_6_to_router_9_7_req; - assign router_9_7_req_in[3] = router_8_7_to_router_9_7_req; - assign router_9_7_req_in[4] = magia_tile_ni_9_7_to_router_9_7_req; - - assign router_9_7_to_router_9_8_rsp = router_9_7_rsp_out[0]; - assign router_9_7_to_router_10_7_rsp = router_9_7_rsp_out[1]; - assign router_9_7_to_router_9_6_rsp = router_9_7_rsp_out[2]; - assign router_9_7_to_router_8_7_rsp = router_9_7_rsp_out[3]; - assign router_9_7_to_magia_tile_ni_9_7_rsp = router_9_7_rsp_out[4]; - - assign router_9_7_to_router_9_8_req = router_9_7_req_out[0]; - assign router_9_7_to_router_10_7_req = router_9_7_req_out[1]; - assign router_9_7_to_router_9_6_req = router_9_7_req_out[2]; - assign router_9_7_to_router_8_7_req = router_9_7_req_out[3]; - assign router_9_7_to_magia_tile_ni_9_7_req = router_9_7_req_out[4]; - - assign router_9_7_rsp_in[0] = router_9_8_to_router_9_7_rsp; - assign router_9_7_rsp_in[1] = router_10_7_to_router_9_7_rsp; - assign router_9_7_rsp_in[2] = router_9_6_to_router_9_7_rsp; - assign router_9_7_rsp_in[3] = router_8_7_to_router_9_7_rsp; - assign router_9_7_rsp_in[4] = magia_tile_ni_9_7_to_router_9_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_7_req_in), - .floo_rsp_o (router_9_7_rsp_out), - .floo_req_o (router_9_7_req_out), - .floo_rsp_i (router_9_7_rsp_in) -); - - -floo_req_t [4:0] router_9_8_req_in; -floo_rsp_t [4:0] router_9_8_rsp_out; -floo_req_t [4:0] router_9_8_req_out; -floo_rsp_t [4:0] router_9_8_rsp_in; - - assign router_9_8_req_in[0] = router_9_9_to_router_9_8_req; - assign router_9_8_req_in[1] = router_10_8_to_router_9_8_req; - assign router_9_8_req_in[2] = router_9_7_to_router_9_8_req; - assign router_9_8_req_in[3] = router_8_8_to_router_9_8_req; - assign router_9_8_req_in[4] = magia_tile_ni_9_8_to_router_9_8_req; - - assign router_9_8_to_router_9_9_rsp = router_9_8_rsp_out[0]; - assign router_9_8_to_router_10_8_rsp = router_9_8_rsp_out[1]; - assign router_9_8_to_router_9_7_rsp = router_9_8_rsp_out[2]; - assign router_9_8_to_router_8_8_rsp = router_9_8_rsp_out[3]; - assign router_9_8_to_magia_tile_ni_9_8_rsp = router_9_8_rsp_out[4]; - - assign router_9_8_to_router_9_9_req = router_9_8_req_out[0]; - assign router_9_8_to_router_10_8_req = router_9_8_req_out[1]; - assign router_9_8_to_router_9_7_req = router_9_8_req_out[2]; - assign router_9_8_to_router_8_8_req = router_9_8_req_out[3]; - assign router_9_8_to_magia_tile_ni_9_8_req = router_9_8_req_out[4]; - - assign router_9_8_rsp_in[0] = router_9_9_to_router_9_8_rsp; - assign router_9_8_rsp_in[1] = router_10_8_to_router_9_8_rsp; - assign router_9_8_rsp_in[2] = router_9_7_to_router_9_8_rsp; - assign router_9_8_rsp_in[3] = router_8_8_to_router_9_8_rsp; - assign router_9_8_rsp_in[4] = magia_tile_ni_9_8_to_router_9_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_8_req_in), - .floo_rsp_o (router_9_8_rsp_out), - .floo_req_o (router_9_8_req_out), - .floo_rsp_i (router_9_8_rsp_in) -); - - -floo_req_t [4:0] router_9_9_req_in; -floo_rsp_t [4:0] router_9_9_rsp_out; -floo_req_t [4:0] router_9_9_req_out; -floo_rsp_t [4:0] router_9_9_rsp_in; - - assign router_9_9_req_in[0] = router_9_10_to_router_9_9_req; - assign router_9_9_req_in[1] = router_10_9_to_router_9_9_req; - assign router_9_9_req_in[2] = router_9_8_to_router_9_9_req; - assign router_9_9_req_in[3] = router_8_9_to_router_9_9_req; - assign router_9_9_req_in[4] = magia_tile_ni_9_9_to_router_9_9_req; - - assign router_9_9_to_router_9_10_rsp = router_9_9_rsp_out[0]; - assign router_9_9_to_router_10_9_rsp = router_9_9_rsp_out[1]; - assign router_9_9_to_router_9_8_rsp = router_9_9_rsp_out[2]; - assign router_9_9_to_router_8_9_rsp = router_9_9_rsp_out[3]; - assign router_9_9_to_magia_tile_ni_9_9_rsp = router_9_9_rsp_out[4]; - - assign router_9_9_to_router_9_10_req = router_9_9_req_out[0]; - assign router_9_9_to_router_10_9_req = router_9_9_req_out[1]; - assign router_9_9_to_router_9_8_req = router_9_9_req_out[2]; - assign router_9_9_to_router_8_9_req = router_9_9_req_out[3]; - assign router_9_9_to_magia_tile_ni_9_9_req = router_9_9_req_out[4]; - - assign router_9_9_rsp_in[0] = router_9_10_to_router_9_9_rsp; - assign router_9_9_rsp_in[1] = router_10_9_to_router_9_9_rsp; - assign router_9_9_rsp_in[2] = router_9_8_to_router_9_9_rsp; - assign router_9_9_rsp_in[3] = router_8_9_to_router_9_9_rsp; - assign router_9_9_rsp_in[4] = magia_tile_ni_9_9_to_router_9_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_9_req_in), - .floo_rsp_o (router_9_9_rsp_out), - .floo_req_o (router_9_9_req_out), - .floo_rsp_i (router_9_9_rsp_in) -); - - -floo_req_t [4:0] router_9_10_req_in; -floo_rsp_t [4:0] router_9_10_rsp_out; -floo_req_t [4:0] router_9_10_req_out; -floo_rsp_t [4:0] router_9_10_rsp_in; - - assign router_9_10_req_in[0] = router_9_11_to_router_9_10_req; - assign router_9_10_req_in[1] = router_10_10_to_router_9_10_req; - assign router_9_10_req_in[2] = router_9_9_to_router_9_10_req; - assign router_9_10_req_in[3] = router_8_10_to_router_9_10_req; - assign router_9_10_req_in[4] = magia_tile_ni_9_10_to_router_9_10_req; - - assign router_9_10_to_router_9_11_rsp = router_9_10_rsp_out[0]; - assign router_9_10_to_router_10_10_rsp = router_9_10_rsp_out[1]; - assign router_9_10_to_router_9_9_rsp = router_9_10_rsp_out[2]; - assign router_9_10_to_router_8_10_rsp = router_9_10_rsp_out[3]; - assign router_9_10_to_magia_tile_ni_9_10_rsp = router_9_10_rsp_out[4]; - - assign router_9_10_to_router_9_11_req = router_9_10_req_out[0]; - assign router_9_10_to_router_10_10_req = router_9_10_req_out[1]; - assign router_9_10_to_router_9_9_req = router_9_10_req_out[2]; - assign router_9_10_to_router_8_10_req = router_9_10_req_out[3]; - assign router_9_10_to_magia_tile_ni_9_10_req = router_9_10_req_out[4]; - - assign router_9_10_rsp_in[0] = router_9_11_to_router_9_10_rsp; - assign router_9_10_rsp_in[1] = router_10_10_to_router_9_10_rsp; - assign router_9_10_rsp_in[2] = router_9_9_to_router_9_10_rsp; - assign router_9_10_rsp_in[3] = router_8_10_to_router_9_10_rsp; - assign router_9_10_rsp_in[4] = magia_tile_ni_9_10_to_router_9_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_10_req_in), - .floo_rsp_o (router_9_10_rsp_out), - .floo_req_o (router_9_10_req_out), - .floo_rsp_i (router_9_10_rsp_in) -); - - -floo_req_t [4:0] router_9_11_req_in; -floo_rsp_t [4:0] router_9_11_rsp_out; -floo_req_t [4:0] router_9_11_req_out; -floo_rsp_t [4:0] router_9_11_rsp_in; - - assign router_9_11_req_in[0] = router_9_12_to_router_9_11_req; - assign router_9_11_req_in[1] = router_10_11_to_router_9_11_req; - assign router_9_11_req_in[2] = router_9_10_to_router_9_11_req; - assign router_9_11_req_in[3] = router_8_11_to_router_9_11_req; - assign router_9_11_req_in[4] = magia_tile_ni_9_11_to_router_9_11_req; - - assign router_9_11_to_router_9_12_rsp = router_9_11_rsp_out[0]; - assign router_9_11_to_router_10_11_rsp = router_9_11_rsp_out[1]; - assign router_9_11_to_router_9_10_rsp = router_9_11_rsp_out[2]; - assign router_9_11_to_router_8_11_rsp = router_9_11_rsp_out[3]; - assign router_9_11_to_magia_tile_ni_9_11_rsp = router_9_11_rsp_out[4]; - - assign router_9_11_to_router_9_12_req = router_9_11_req_out[0]; - assign router_9_11_to_router_10_11_req = router_9_11_req_out[1]; - assign router_9_11_to_router_9_10_req = router_9_11_req_out[2]; - assign router_9_11_to_router_8_11_req = router_9_11_req_out[3]; - assign router_9_11_to_magia_tile_ni_9_11_req = router_9_11_req_out[4]; - - assign router_9_11_rsp_in[0] = router_9_12_to_router_9_11_rsp; - assign router_9_11_rsp_in[1] = router_10_11_to_router_9_11_rsp; - assign router_9_11_rsp_in[2] = router_9_10_to_router_9_11_rsp; - assign router_9_11_rsp_in[3] = router_8_11_to_router_9_11_rsp; - assign router_9_11_rsp_in[4] = magia_tile_ni_9_11_to_router_9_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_11_req_in), - .floo_rsp_o (router_9_11_rsp_out), - .floo_req_o (router_9_11_req_out), - .floo_rsp_i (router_9_11_rsp_in) -); - - -floo_req_t [4:0] router_9_12_req_in; -floo_rsp_t [4:0] router_9_12_rsp_out; -floo_req_t [4:0] router_9_12_req_out; -floo_rsp_t [4:0] router_9_12_rsp_in; - - assign router_9_12_req_in[0] = router_9_13_to_router_9_12_req; - assign router_9_12_req_in[1] = router_10_12_to_router_9_12_req; - assign router_9_12_req_in[2] = router_9_11_to_router_9_12_req; - assign router_9_12_req_in[3] = router_8_12_to_router_9_12_req; - assign router_9_12_req_in[4] = magia_tile_ni_9_12_to_router_9_12_req; - - assign router_9_12_to_router_9_13_rsp = router_9_12_rsp_out[0]; - assign router_9_12_to_router_10_12_rsp = router_9_12_rsp_out[1]; - assign router_9_12_to_router_9_11_rsp = router_9_12_rsp_out[2]; - assign router_9_12_to_router_8_12_rsp = router_9_12_rsp_out[3]; - assign router_9_12_to_magia_tile_ni_9_12_rsp = router_9_12_rsp_out[4]; - - assign router_9_12_to_router_9_13_req = router_9_12_req_out[0]; - assign router_9_12_to_router_10_12_req = router_9_12_req_out[1]; - assign router_9_12_to_router_9_11_req = router_9_12_req_out[2]; - assign router_9_12_to_router_8_12_req = router_9_12_req_out[3]; - assign router_9_12_to_magia_tile_ni_9_12_req = router_9_12_req_out[4]; - - assign router_9_12_rsp_in[0] = router_9_13_to_router_9_12_rsp; - assign router_9_12_rsp_in[1] = router_10_12_to_router_9_12_rsp; - assign router_9_12_rsp_in[2] = router_9_11_to_router_9_12_rsp; - assign router_9_12_rsp_in[3] = router_8_12_to_router_9_12_rsp; - assign router_9_12_rsp_in[4] = magia_tile_ni_9_12_to_router_9_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_12_req_in), - .floo_rsp_o (router_9_12_rsp_out), - .floo_req_o (router_9_12_req_out), - .floo_rsp_i (router_9_12_rsp_in) -); - - -floo_req_t [4:0] router_9_13_req_in; -floo_rsp_t [4:0] router_9_13_rsp_out; -floo_req_t [4:0] router_9_13_req_out; -floo_rsp_t [4:0] router_9_13_rsp_in; - - assign router_9_13_req_in[0] = router_9_14_to_router_9_13_req; - assign router_9_13_req_in[1] = router_10_13_to_router_9_13_req; - assign router_9_13_req_in[2] = router_9_12_to_router_9_13_req; - assign router_9_13_req_in[3] = router_8_13_to_router_9_13_req; - assign router_9_13_req_in[4] = magia_tile_ni_9_13_to_router_9_13_req; - - assign router_9_13_to_router_9_14_rsp = router_9_13_rsp_out[0]; - assign router_9_13_to_router_10_13_rsp = router_9_13_rsp_out[1]; - assign router_9_13_to_router_9_12_rsp = router_9_13_rsp_out[2]; - assign router_9_13_to_router_8_13_rsp = router_9_13_rsp_out[3]; - assign router_9_13_to_magia_tile_ni_9_13_rsp = router_9_13_rsp_out[4]; - - assign router_9_13_to_router_9_14_req = router_9_13_req_out[0]; - assign router_9_13_to_router_10_13_req = router_9_13_req_out[1]; - assign router_9_13_to_router_9_12_req = router_9_13_req_out[2]; - assign router_9_13_to_router_8_13_req = router_9_13_req_out[3]; - assign router_9_13_to_magia_tile_ni_9_13_req = router_9_13_req_out[4]; - - assign router_9_13_rsp_in[0] = router_9_14_to_router_9_13_rsp; - assign router_9_13_rsp_in[1] = router_10_13_to_router_9_13_rsp; - assign router_9_13_rsp_in[2] = router_9_12_to_router_9_13_rsp; - assign router_9_13_rsp_in[3] = router_8_13_to_router_9_13_rsp; - assign router_9_13_rsp_in[4] = magia_tile_ni_9_13_to_router_9_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_13_req_in), - .floo_rsp_o (router_9_13_rsp_out), - .floo_req_o (router_9_13_req_out), - .floo_rsp_i (router_9_13_rsp_in) -); - - -floo_req_t [4:0] router_9_14_req_in; -floo_rsp_t [4:0] router_9_14_rsp_out; -floo_req_t [4:0] router_9_14_req_out; -floo_rsp_t [4:0] router_9_14_rsp_in; - - assign router_9_14_req_in[0] = router_9_15_to_router_9_14_req; - assign router_9_14_req_in[1] = router_10_14_to_router_9_14_req; - assign router_9_14_req_in[2] = router_9_13_to_router_9_14_req; - assign router_9_14_req_in[3] = router_8_14_to_router_9_14_req; - assign router_9_14_req_in[4] = magia_tile_ni_9_14_to_router_9_14_req; - - assign router_9_14_to_router_9_15_rsp = router_9_14_rsp_out[0]; - assign router_9_14_to_router_10_14_rsp = router_9_14_rsp_out[1]; - assign router_9_14_to_router_9_13_rsp = router_9_14_rsp_out[2]; - assign router_9_14_to_router_8_14_rsp = router_9_14_rsp_out[3]; - assign router_9_14_to_magia_tile_ni_9_14_rsp = router_9_14_rsp_out[4]; - - assign router_9_14_to_router_9_15_req = router_9_14_req_out[0]; - assign router_9_14_to_router_10_14_req = router_9_14_req_out[1]; - assign router_9_14_to_router_9_13_req = router_9_14_req_out[2]; - assign router_9_14_to_router_8_14_req = router_9_14_req_out[3]; - assign router_9_14_to_magia_tile_ni_9_14_req = router_9_14_req_out[4]; - - assign router_9_14_rsp_in[0] = router_9_15_to_router_9_14_rsp; - assign router_9_14_rsp_in[1] = router_10_14_to_router_9_14_rsp; - assign router_9_14_rsp_in[2] = router_9_13_to_router_9_14_rsp; - assign router_9_14_rsp_in[3] = router_8_14_to_router_9_14_rsp; - assign router_9_14_rsp_in[4] = magia_tile_ni_9_14_to_router_9_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_14_req_in), - .floo_rsp_o (router_9_14_rsp_out), - .floo_req_o (router_9_14_req_out), - .floo_rsp_i (router_9_14_rsp_in) -); - - -floo_req_t [4:0] router_9_15_req_in; -floo_rsp_t [4:0] router_9_15_rsp_out; -floo_req_t [4:0] router_9_15_req_out; -floo_rsp_t [4:0] router_9_15_rsp_in; - - assign router_9_15_req_in[0] = router_9_16_to_router_9_15_req; - assign router_9_15_req_in[1] = router_10_15_to_router_9_15_req; - assign router_9_15_req_in[2] = router_9_14_to_router_9_15_req; - assign router_9_15_req_in[3] = router_8_15_to_router_9_15_req; - assign router_9_15_req_in[4] = magia_tile_ni_9_15_to_router_9_15_req; - - assign router_9_15_to_router_9_16_rsp = router_9_15_rsp_out[0]; - assign router_9_15_to_router_10_15_rsp = router_9_15_rsp_out[1]; - assign router_9_15_to_router_9_14_rsp = router_9_15_rsp_out[2]; - assign router_9_15_to_router_8_15_rsp = router_9_15_rsp_out[3]; - assign router_9_15_to_magia_tile_ni_9_15_rsp = router_9_15_rsp_out[4]; - - assign router_9_15_to_router_9_16_req = router_9_15_req_out[0]; - assign router_9_15_to_router_10_15_req = router_9_15_req_out[1]; - assign router_9_15_to_router_9_14_req = router_9_15_req_out[2]; - assign router_9_15_to_router_8_15_req = router_9_15_req_out[3]; - assign router_9_15_to_magia_tile_ni_9_15_req = router_9_15_req_out[4]; - - assign router_9_15_rsp_in[0] = router_9_16_to_router_9_15_rsp; - assign router_9_15_rsp_in[1] = router_10_15_to_router_9_15_rsp; - assign router_9_15_rsp_in[2] = router_9_14_to_router_9_15_rsp; - assign router_9_15_rsp_in[3] = router_8_15_to_router_9_15_rsp; - assign router_9_15_rsp_in[4] = magia_tile_ni_9_15_to_router_9_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_15_req_in), - .floo_rsp_o (router_9_15_rsp_out), - .floo_req_o (router_9_15_req_out), - .floo_rsp_i (router_9_15_rsp_in) -); - - -floo_req_t [4:0] router_9_16_req_in; -floo_rsp_t [4:0] router_9_16_rsp_out; -floo_req_t [4:0] router_9_16_req_out; -floo_rsp_t [4:0] router_9_16_rsp_in; - - assign router_9_16_req_in[0] = router_9_17_to_router_9_16_req; - assign router_9_16_req_in[1] = router_10_16_to_router_9_16_req; - assign router_9_16_req_in[2] = router_9_15_to_router_9_16_req; - assign router_9_16_req_in[3] = router_8_16_to_router_9_16_req; - assign router_9_16_req_in[4] = magia_tile_ni_9_16_to_router_9_16_req; - - assign router_9_16_to_router_9_17_rsp = router_9_16_rsp_out[0]; - assign router_9_16_to_router_10_16_rsp = router_9_16_rsp_out[1]; - assign router_9_16_to_router_9_15_rsp = router_9_16_rsp_out[2]; - assign router_9_16_to_router_8_16_rsp = router_9_16_rsp_out[3]; - assign router_9_16_to_magia_tile_ni_9_16_rsp = router_9_16_rsp_out[4]; - - assign router_9_16_to_router_9_17_req = router_9_16_req_out[0]; - assign router_9_16_to_router_10_16_req = router_9_16_req_out[1]; - assign router_9_16_to_router_9_15_req = router_9_16_req_out[2]; - assign router_9_16_to_router_8_16_req = router_9_16_req_out[3]; - assign router_9_16_to_magia_tile_ni_9_16_req = router_9_16_req_out[4]; - - assign router_9_16_rsp_in[0] = router_9_17_to_router_9_16_rsp; - assign router_9_16_rsp_in[1] = router_10_16_to_router_9_16_rsp; - assign router_9_16_rsp_in[2] = router_9_15_to_router_9_16_rsp; - assign router_9_16_rsp_in[3] = router_8_16_to_router_9_16_rsp; - assign router_9_16_rsp_in[4] = magia_tile_ni_9_16_to_router_9_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_16_req_in), - .floo_rsp_o (router_9_16_rsp_out), - .floo_req_o (router_9_16_req_out), - .floo_rsp_i (router_9_16_rsp_in) -); - - -floo_req_t [4:0] router_9_17_req_in; -floo_rsp_t [4:0] router_9_17_rsp_out; -floo_req_t [4:0] router_9_17_req_out; -floo_rsp_t [4:0] router_9_17_rsp_in; - - assign router_9_17_req_in[0] = router_9_18_to_router_9_17_req; - assign router_9_17_req_in[1] = router_10_17_to_router_9_17_req; - assign router_9_17_req_in[2] = router_9_16_to_router_9_17_req; - assign router_9_17_req_in[3] = router_8_17_to_router_9_17_req; - assign router_9_17_req_in[4] = magia_tile_ni_9_17_to_router_9_17_req; - - assign router_9_17_to_router_9_18_rsp = router_9_17_rsp_out[0]; - assign router_9_17_to_router_10_17_rsp = router_9_17_rsp_out[1]; - assign router_9_17_to_router_9_16_rsp = router_9_17_rsp_out[2]; - assign router_9_17_to_router_8_17_rsp = router_9_17_rsp_out[3]; - assign router_9_17_to_magia_tile_ni_9_17_rsp = router_9_17_rsp_out[4]; - - assign router_9_17_to_router_9_18_req = router_9_17_req_out[0]; - assign router_9_17_to_router_10_17_req = router_9_17_req_out[1]; - assign router_9_17_to_router_9_16_req = router_9_17_req_out[2]; - assign router_9_17_to_router_8_17_req = router_9_17_req_out[3]; - assign router_9_17_to_magia_tile_ni_9_17_req = router_9_17_req_out[4]; - - assign router_9_17_rsp_in[0] = router_9_18_to_router_9_17_rsp; - assign router_9_17_rsp_in[1] = router_10_17_to_router_9_17_rsp; - assign router_9_17_rsp_in[2] = router_9_16_to_router_9_17_rsp; - assign router_9_17_rsp_in[3] = router_8_17_to_router_9_17_rsp; - assign router_9_17_rsp_in[4] = magia_tile_ni_9_17_to_router_9_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_17_req_in), - .floo_rsp_o (router_9_17_rsp_out), - .floo_req_o (router_9_17_req_out), - .floo_rsp_i (router_9_17_rsp_in) -); - - -floo_req_t [4:0] router_9_18_req_in; -floo_rsp_t [4:0] router_9_18_rsp_out; -floo_req_t [4:0] router_9_18_req_out; -floo_rsp_t [4:0] router_9_18_rsp_in; - - assign router_9_18_req_in[0] = router_9_19_to_router_9_18_req; - assign router_9_18_req_in[1] = router_10_18_to_router_9_18_req; - assign router_9_18_req_in[2] = router_9_17_to_router_9_18_req; - assign router_9_18_req_in[3] = router_8_18_to_router_9_18_req; - assign router_9_18_req_in[4] = magia_tile_ni_9_18_to_router_9_18_req; - - assign router_9_18_to_router_9_19_rsp = router_9_18_rsp_out[0]; - assign router_9_18_to_router_10_18_rsp = router_9_18_rsp_out[1]; - assign router_9_18_to_router_9_17_rsp = router_9_18_rsp_out[2]; - assign router_9_18_to_router_8_18_rsp = router_9_18_rsp_out[3]; - assign router_9_18_to_magia_tile_ni_9_18_rsp = router_9_18_rsp_out[4]; - - assign router_9_18_to_router_9_19_req = router_9_18_req_out[0]; - assign router_9_18_to_router_10_18_req = router_9_18_req_out[1]; - assign router_9_18_to_router_9_17_req = router_9_18_req_out[2]; - assign router_9_18_to_router_8_18_req = router_9_18_req_out[3]; - assign router_9_18_to_magia_tile_ni_9_18_req = router_9_18_req_out[4]; - - assign router_9_18_rsp_in[0] = router_9_19_to_router_9_18_rsp; - assign router_9_18_rsp_in[1] = router_10_18_to_router_9_18_rsp; - assign router_9_18_rsp_in[2] = router_9_17_to_router_9_18_rsp; - assign router_9_18_rsp_in[3] = router_8_18_to_router_9_18_rsp; - assign router_9_18_rsp_in[4] = magia_tile_ni_9_18_to_router_9_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_18_req_in), - .floo_rsp_o (router_9_18_rsp_out), - .floo_req_o (router_9_18_req_out), - .floo_rsp_i (router_9_18_rsp_in) -); - - -floo_req_t [4:0] router_9_19_req_in; -floo_rsp_t [4:0] router_9_19_rsp_out; -floo_req_t [4:0] router_9_19_req_out; -floo_rsp_t [4:0] router_9_19_rsp_in; - - assign router_9_19_req_in[0] = router_9_20_to_router_9_19_req; - assign router_9_19_req_in[1] = router_10_19_to_router_9_19_req; - assign router_9_19_req_in[2] = router_9_18_to_router_9_19_req; - assign router_9_19_req_in[3] = router_8_19_to_router_9_19_req; - assign router_9_19_req_in[4] = magia_tile_ni_9_19_to_router_9_19_req; - - assign router_9_19_to_router_9_20_rsp = router_9_19_rsp_out[0]; - assign router_9_19_to_router_10_19_rsp = router_9_19_rsp_out[1]; - assign router_9_19_to_router_9_18_rsp = router_9_19_rsp_out[2]; - assign router_9_19_to_router_8_19_rsp = router_9_19_rsp_out[3]; - assign router_9_19_to_magia_tile_ni_9_19_rsp = router_9_19_rsp_out[4]; - - assign router_9_19_to_router_9_20_req = router_9_19_req_out[0]; - assign router_9_19_to_router_10_19_req = router_9_19_req_out[1]; - assign router_9_19_to_router_9_18_req = router_9_19_req_out[2]; - assign router_9_19_to_router_8_19_req = router_9_19_req_out[3]; - assign router_9_19_to_magia_tile_ni_9_19_req = router_9_19_req_out[4]; - - assign router_9_19_rsp_in[0] = router_9_20_to_router_9_19_rsp; - assign router_9_19_rsp_in[1] = router_10_19_to_router_9_19_rsp; - assign router_9_19_rsp_in[2] = router_9_18_to_router_9_19_rsp; - assign router_9_19_rsp_in[3] = router_8_19_to_router_9_19_rsp; - assign router_9_19_rsp_in[4] = magia_tile_ni_9_19_to_router_9_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_19_req_in), - .floo_rsp_o (router_9_19_rsp_out), - .floo_req_o (router_9_19_req_out), - .floo_rsp_i (router_9_19_rsp_in) -); - - -floo_req_t [4:0] router_9_20_req_in; -floo_rsp_t [4:0] router_9_20_rsp_out; -floo_req_t [4:0] router_9_20_req_out; -floo_rsp_t [4:0] router_9_20_rsp_in; - - assign router_9_20_req_in[0] = router_9_21_to_router_9_20_req; - assign router_9_20_req_in[1] = router_10_20_to_router_9_20_req; - assign router_9_20_req_in[2] = router_9_19_to_router_9_20_req; - assign router_9_20_req_in[3] = router_8_20_to_router_9_20_req; - assign router_9_20_req_in[4] = magia_tile_ni_9_20_to_router_9_20_req; - - assign router_9_20_to_router_9_21_rsp = router_9_20_rsp_out[0]; - assign router_9_20_to_router_10_20_rsp = router_9_20_rsp_out[1]; - assign router_9_20_to_router_9_19_rsp = router_9_20_rsp_out[2]; - assign router_9_20_to_router_8_20_rsp = router_9_20_rsp_out[3]; - assign router_9_20_to_magia_tile_ni_9_20_rsp = router_9_20_rsp_out[4]; - - assign router_9_20_to_router_9_21_req = router_9_20_req_out[0]; - assign router_9_20_to_router_10_20_req = router_9_20_req_out[1]; - assign router_9_20_to_router_9_19_req = router_9_20_req_out[2]; - assign router_9_20_to_router_8_20_req = router_9_20_req_out[3]; - assign router_9_20_to_magia_tile_ni_9_20_req = router_9_20_req_out[4]; - - assign router_9_20_rsp_in[0] = router_9_21_to_router_9_20_rsp; - assign router_9_20_rsp_in[1] = router_10_20_to_router_9_20_rsp; - assign router_9_20_rsp_in[2] = router_9_19_to_router_9_20_rsp; - assign router_9_20_rsp_in[3] = router_8_20_to_router_9_20_rsp; - assign router_9_20_rsp_in[4] = magia_tile_ni_9_20_to_router_9_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_20_req_in), - .floo_rsp_o (router_9_20_rsp_out), - .floo_req_o (router_9_20_req_out), - .floo_rsp_i (router_9_20_rsp_in) -); - - -floo_req_t [4:0] router_9_21_req_in; -floo_rsp_t [4:0] router_9_21_rsp_out; -floo_req_t [4:0] router_9_21_req_out; -floo_rsp_t [4:0] router_9_21_rsp_in; - - assign router_9_21_req_in[0] = router_9_22_to_router_9_21_req; - assign router_9_21_req_in[1] = router_10_21_to_router_9_21_req; - assign router_9_21_req_in[2] = router_9_20_to_router_9_21_req; - assign router_9_21_req_in[3] = router_8_21_to_router_9_21_req; - assign router_9_21_req_in[4] = magia_tile_ni_9_21_to_router_9_21_req; - - assign router_9_21_to_router_9_22_rsp = router_9_21_rsp_out[0]; - assign router_9_21_to_router_10_21_rsp = router_9_21_rsp_out[1]; - assign router_9_21_to_router_9_20_rsp = router_9_21_rsp_out[2]; - assign router_9_21_to_router_8_21_rsp = router_9_21_rsp_out[3]; - assign router_9_21_to_magia_tile_ni_9_21_rsp = router_9_21_rsp_out[4]; - - assign router_9_21_to_router_9_22_req = router_9_21_req_out[0]; - assign router_9_21_to_router_10_21_req = router_9_21_req_out[1]; - assign router_9_21_to_router_9_20_req = router_9_21_req_out[2]; - assign router_9_21_to_router_8_21_req = router_9_21_req_out[3]; - assign router_9_21_to_magia_tile_ni_9_21_req = router_9_21_req_out[4]; - - assign router_9_21_rsp_in[0] = router_9_22_to_router_9_21_rsp; - assign router_9_21_rsp_in[1] = router_10_21_to_router_9_21_rsp; - assign router_9_21_rsp_in[2] = router_9_20_to_router_9_21_rsp; - assign router_9_21_rsp_in[3] = router_8_21_to_router_9_21_rsp; - assign router_9_21_rsp_in[4] = magia_tile_ni_9_21_to_router_9_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_21_req_in), - .floo_rsp_o (router_9_21_rsp_out), - .floo_req_o (router_9_21_req_out), - .floo_rsp_i (router_9_21_rsp_in) -); - - -floo_req_t [4:0] router_9_22_req_in; -floo_rsp_t [4:0] router_9_22_rsp_out; -floo_req_t [4:0] router_9_22_req_out; -floo_rsp_t [4:0] router_9_22_rsp_in; - - assign router_9_22_req_in[0] = router_9_23_to_router_9_22_req; - assign router_9_22_req_in[1] = router_10_22_to_router_9_22_req; - assign router_9_22_req_in[2] = router_9_21_to_router_9_22_req; - assign router_9_22_req_in[3] = router_8_22_to_router_9_22_req; - assign router_9_22_req_in[4] = magia_tile_ni_9_22_to_router_9_22_req; - - assign router_9_22_to_router_9_23_rsp = router_9_22_rsp_out[0]; - assign router_9_22_to_router_10_22_rsp = router_9_22_rsp_out[1]; - assign router_9_22_to_router_9_21_rsp = router_9_22_rsp_out[2]; - assign router_9_22_to_router_8_22_rsp = router_9_22_rsp_out[3]; - assign router_9_22_to_magia_tile_ni_9_22_rsp = router_9_22_rsp_out[4]; - - assign router_9_22_to_router_9_23_req = router_9_22_req_out[0]; - assign router_9_22_to_router_10_22_req = router_9_22_req_out[1]; - assign router_9_22_to_router_9_21_req = router_9_22_req_out[2]; - assign router_9_22_to_router_8_22_req = router_9_22_req_out[3]; - assign router_9_22_to_magia_tile_ni_9_22_req = router_9_22_req_out[4]; - - assign router_9_22_rsp_in[0] = router_9_23_to_router_9_22_rsp; - assign router_9_22_rsp_in[1] = router_10_22_to_router_9_22_rsp; - assign router_9_22_rsp_in[2] = router_9_21_to_router_9_22_rsp; - assign router_9_22_rsp_in[3] = router_8_22_to_router_9_22_rsp; - assign router_9_22_rsp_in[4] = magia_tile_ni_9_22_to_router_9_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_22_req_in), - .floo_rsp_o (router_9_22_rsp_out), - .floo_req_o (router_9_22_req_out), - .floo_rsp_i (router_9_22_rsp_in) -); - - -floo_req_t [4:0] router_9_23_req_in; -floo_rsp_t [4:0] router_9_23_rsp_out; -floo_req_t [4:0] router_9_23_req_out; -floo_rsp_t [4:0] router_9_23_rsp_in; - - assign router_9_23_req_in[0] = router_9_24_to_router_9_23_req; - assign router_9_23_req_in[1] = router_10_23_to_router_9_23_req; - assign router_9_23_req_in[2] = router_9_22_to_router_9_23_req; - assign router_9_23_req_in[3] = router_8_23_to_router_9_23_req; - assign router_9_23_req_in[4] = magia_tile_ni_9_23_to_router_9_23_req; - - assign router_9_23_to_router_9_24_rsp = router_9_23_rsp_out[0]; - assign router_9_23_to_router_10_23_rsp = router_9_23_rsp_out[1]; - assign router_9_23_to_router_9_22_rsp = router_9_23_rsp_out[2]; - assign router_9_23_to_router_8_23_rsp = router_9_23_rsp_out[3]; - assign router_9_23_to_magia_tile_ni_9_23_rsp = router_9_23_rsp_out[4]; - - assign router_9_23_to_router_9_24_req = router_9_23_req_out[0]; - assign router_9_23_to_router_10_23_req = router_9_23_req_out[1]; - assign router_9_23_to_router_9_22_req = router_9_23_req_out[2]; - assign router_9_23_to_router_8_23_req = router_9_23_req_out[3]; - assign router_9_23_to_magia_tile_ni_9_23_req = router_9_23_req_out[4]; - - assign router_9_23_rsp_in[0] = router_9_24_to_router_9_23_rsp; - assign router_9_23_rsp_in[1] = router_10_23_to_router_9_23_rsp; - assign router_9_23_rsp_in[2] = router_9_22_to_router_9_23_rsp; - assign router_9_23_rsp_in[3] = router_8_23_to_router_9_23_rsp; - assign router_9_23_rsp_in[4] = magia_tile_ni_9_23_to_router_9_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_23_req_in), - .floo_rsp_o (router_9_23_rsp_out), - .floo_req_o (router_9_23_req_out), - .floo_rsp_i (router_9_23_rsp_in) -); - - -floo_req_t [4:0] router_9_24_req_in; -floo_rsp_t [4:0] router_9_24_rsp_out; -floo_req_t [4:0] router_9_24_req_out; -floo_rsp_t [4:0] router_9_24_rsp_in; - - assign router_9_24_req_in[0] = router_9_25_to_router_9_24_req; - assign router_9_24_req_in[1] = router_10_24_to_router_9_24_req; - assign router_9_24_req_in[2] = router_9_23_to_router_9_24_req; - assign router_9_24_req_in[3] = router_8_24_to_router_9_24_req; - assign router_9_24_req_in[4] = magia_tile_ni_9_24_to_router_9_24_req; - - assign router_9_24_to_router_9_25_rsp = router_9_24_rsp_out[0]; - assign router_9_24_to_router_10_24_rsp = router_9_24_rsp_out[1]; - assign router_9_24_to_router_9_23_rsp = router_9_24_rsp_out[2]; - assign router_9_24_to_router_8_24_rsp = router_9_24_rsp_out[3]; - assign router_9_24_to_magia_tile_ni_9_24_rsp = router_9_24_rsp_out[4]; - - assign router_9_24_to_router_9_25_req = router_9_24_req_out[0]; - assign router_9_24_to_router_10_24_req = router_9_24_req_out[1]; - assign router_9_24_to_router_9_23_req = router_9_24_req_out[2]; - assign router_9_24_to_router_8_24_req = router_9_24_req_out[3]; - assign router_9_24_to_magia_tile_ni_9_24_req = router_9_24_req_out[4]; - - assign router_9_24_rsp_in[0] = router_9_25_to_router_9_24_rsp; - assign router_9_24_rsp_in[1] = router_10_24_to_router_9_24_rsp; - assign router_9_24_rsp_in[2] = router_9_23_to_router_9_24_rsp; - assign router_9_24_rsp_in[3] = router_8_24_to_router_9_24_rsp; - assign router_9_24_rsp_in[4] = magia_tile_ni_9_24_to_router_9_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_24_req_in), - .floo_rsp_o (router_9_24_rsp_out), - .floo_req_o (router_9_24_req_out), - .floo_rsp_i (router_9_24_rsp_in) -); - - -floo_req_t [4:0] router_9_25_req_in; -floo_rsp_t [4:0] router_9_25_rsp_out; -floo_req_t [4:0] router_9_25_req_out; -floo_rsp_t [4:0] router_9_25_rsp_in; - - assign router_9_25_req_in[0] = router_9_26_to_router_9_25_req; - assign router_9_25_req_in[1] = router_10_25_to_router_9_25_req; - assign router_9_25_req_in[2] = router_9_24_to_router_9_25_req; - assign router_9_25_req_in[3] = router_8_25_to_router_9_25_req; - assign router_9_25_req_in[4] = magia_tile_ni_9_25_to_router_9_25_req; - - assign router_9_25_to_router_9_26_rsp = router_9_25_rsp_out[0]; - assign router_9_25_to_router_10_25_rsp = router_9_25_rsp_out[1]; - assign router_9_25_to_router_9_24_rsp = router_9_25_rsp_out[2]; - assign router_9_25_to_router_8_25_rsp = router_9_25_rsp_out[3]; - assign router_9_25_to_magia_tile_ni_9_25_rsp = router_9_25_rsp_out[4]; - - assign router_9_25_to_router_9_26_req = router_9_25_req_out[0]; - assign router_9_25_to_router_10_25_req = router_9_25_req_out[1]; - assign router_9_25_to_router_9_24_req = router_9_25_req_out[2]; - assign router_9_25_to_router_8_25_req = router_9_25_req_out[3]; - assign router_9_25_to_magia_tile_ni_9_25_req = router_9_25_req_out[4]; - - assign router_9_25_rsp_in[0] = router_9_26_to_router_9_25_rsp; - assign router_9_25_rsp_in[1] = router_10_25_to_router_9_25_rsp; - assign router_9_25_rsp_in[2] = router_9_24_to_router_9_25_rsp; - assign router_9_25_rsp_in[3] = router_8_25_to_router_9_25_rsp; - assign router_9_25_rsp_in[4] = magia_tile_ni_9_25_to_router_9_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_25_req_in), - .floo_rsp_o (router_9_25_rsp_out), - .floo_req_o (router_9_25_req_out), - .floo_rsp_i (router_9_25_rsp_in) -); - - -floo_req_t [4:0] router_9_26_req_in; -floo_rsp_t [4:0] router_9_26_rsp_out; -floo_req_t [4:0] router_9_26_req_out; -floo_rsp_t [4:0] router_9_26_rsp_in; - - assign router_9_26_req_in[0] = router_9_27_to_router_9_26_req; - assign router_9_26_req_in[1] = router_10_26_to_router_9_26_req; - assign router_9_26_req_in[2] = router_9_25_to_router_9_26_req; - assign router_9_26_req_in[3] = router_8_26_to_router_9_26_req; - assign router_9_26_req_in[4] = magia_tile_ni_9_26_to_router_9_26_req; - - assign router_9_26_to_router_9_27_rsp = router_9_26_rsp_out[0]; - assign router_9_26_to_router_10_26_rsp = router_9_26_rsp_out[1]; - assign router_9_26_to_router_9_25_rsp = router_9_26_rsp_out[2]; - assign router_9_26_to_router_8_26_rsp = router_9_26_rsp_out[3]; - assign router_9_26_to_magia_tile_ni_9_26_rsp = router_9_26_rsp_out[4]; - - assign router_9_26_to_router_9_27_req = router_9_26_req_out[0]; - assign router_9_26_to_router_10_26_req = router_9_26_req_out[1]; - assign router_9_26_to_router_9_25_req = router_9_26_req_out[2]; - assign router_9_26_to_router_8_26_req = router_9_26_req_out[3]; - assign router_9_26_to_magia_tile_ni_9_26_req = router_9_26_req_out[4]; - - assign router_9_26_rsp_in[0] = router_9_27_to_router_9_26_rsp; - assign router_9_26_rsp_in[1] = router_10_26_to_router_9_26_rsp; - assign router_9_26_rsp_in[2] = router_9_25_to_router_9_26_rsp; - assign router_9_26_rsp_in[3] = router_8_26_to_router_9_26_rsp; - assign router_9_26_rsp_in[4] = magia_tile_ni_9_26_to_router_9_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_26_req_in), - .floo_rsp_o (router_9_26_rsp_out), - .floo_req_o (router_9_26_req_out), - .floo_rsp_i (router_9_26_rsp_in) -); - - -floo_req_t [4:0] router_9_27_req_in; -floo_rsp_t [4:0] router_9_27_rsp_out; -floo_req_t [4:0] router_9_27_req_out; -floo_rsp_t [4:0] router_9_27_rsp_in; - - assign router_9_27_req_in[0] = router_9_28_to_router_9_27_req; - assign router_9_27_req_in[1] = router_10_27_to_router_9_27_req; - assign router_9_27_req_in[2] = router_9_26_to_router_9_27_req; - assign router_9_27_req_in[3] = router_8_27_to_router_9_27_req; - assign router_9_27_req_in[4] = magia_tile_ni_9_27_to_router_9_27_req; - - assign router_9_27_to_router_9_28_rsp = router_9_27_rsp_out[0]; - assign router_9_27_to_router_10_27_rsp = router_9_27_rsp_out[1]; - assign router_9_27_to_router_9_26_rsp = router_9_27_rsp_out[2]; - assign router_9_27_to_router_8_27_rsp = router_9_27_rsp_out[3]; - assign router_9_27_to_magia_tile_ni_9_27_rsp = router_9_27_rsp_out[4]; - - assign router_9_27_to_router_9_28_req = router_9_27_req_out[0]; - assign router_9_27_to_router_10_27_req = router_9_27_req_out[1]; - assign router_9_27_to_router_9_26_req = router_9_27_req_out[2]; - assign router_9_27_to_router_8_27_req = router_9_27_req_out[3]; - assign router_9_27_to_magia_tile_ni_9_27_req = router_9_27_req_out[4]; - - assign router_9_27_rsp_in[0] = router_9_28_to_router_9_27_rsp; - assign router_9_27_rsp_in[1] = router_10_27_to_router_9_27_rsp; - assign router_9_27_rsp_in[2] = router_9_26_to_router_9_27_rsp; - assign router_9_27_rsp_in[3] = router_8_27_to_router_9_27_rsp; - assign router_9_27_rsp_in[4] = magia_tile_ni_9_27_to_router_9_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_27_req_in), - .floo_rsp_o (router_9_27_rsp_out), - .floo_req_o (router_9_27_req_out), - .floo_rsp_i (router_9_27_rsp_in) -); - - -floo_req_t [4:0] router_9_28_req_in; -floo_rsp_t [4:0] router_9_28_rsp_out; -floo_req_t [4:0] router_9_28_req_out; -floo_rsp_t [4:0] router_9_28_rsp_in; - - assign router_9_28_req_in[0] = router_9_29_to_router_9_28_req; - assign router_9_28_req_in[1] = router_10_28_to_router_9_28_req; - assign router_9_28_req_in[2] = router_9_27_to_router_9_28_req; - assign router_9_28_req_in[3] = router_8_28_to_router_9_28_req; - assign router_9_28_req_in[4] = magia_tile_ni_9_28_to_router_9_28_req; - - assign router_9_28_to_router_9_29_rsp = router_9_28_rsp_out[0]; - assign router_9_28_to_router_10_28_rsp = router_9_28_rsp_out[1]; - assign router_9_28_to_router_9_27_rsp = router_9_28_rsp_out[2]; - assign router_9_28_to_router_8_28_rsp = router_9_28_rsp_out[3]; - assign router_9_28_to_magia_tile_ni_9_28_rsp = router_9_28_rsp_out[4]; - - assign router_9_28_to_router_9_29_req = router_9_28_req_out[0]; - assign router_9_28_to_router_10_28_req = router_9_28_req_out[1]; - assign router_9_28_to_router_9_27_req = router_9_28_req_out[2]; - assign router_9_28_to_router_8_28_req = router_9_28_req_out[3]; - assign router_9_28_to_magia_tile_ni_9_28_req = router_9_28_req_out[4]; - - assign router_9_28_rsp_in[0] = router_9_29_to_router_9_28_rsp; - assign router_9_28_rsp_in[1] = router_10_28_to_router_9_28_rsp; - assign router_9_28_rsp_in[2] = router_9_27_to_router_9_28_rsp; - assign router_9_28_rsp_in[3] = router_8_28_to_router_9_28_rsp; - assign router_9_28_rsp_in[4] = magia_tile_ni_9_28_to_router_9_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_28_req_in), - .floo_rsp_o (router_9_28_rsp_out), - .floo_req_o (router_9_28_req_out), - .floo_rsp_i (router_9_28_rsp_in) -); - - -floo_req_t [4:0] router_9_29_req_in; -floo_rsp_t [4:0] router_9_29_rsp_out; -floo_req_t [4:0] router_9_29_req_out; -floo_rsp_t [4:0] router_9_29_rsp_in; - - assign router_9_29_req_in[0] = router_9_30_to_router_9_29_req; - assign router_9_29_req_in[1] = router_10_29_to_router_9_29_req; - assign router_9_29_req_in[2] = router_9_28_to_router_9_29_req; - assign router_9_29_req_in[3] = router_8_29_to_router_9_29_req; - assign router_9_29_req_in[4] = magia_tile_ni_9_29_to_router_9_29_req; - - assign router_9_29_to_router_9_30_rsp = router_9_29_rsp_out[0]; - assign router_9_29_to_router_10_29_rsp = router_9_29_rsp_out[1]; - assign router_9_29_to_router_9_28_rsp = router_9_29_rsp_out[2]; - assign router_9_29_to_router_8_29_rsp = router_9_29_rsp_out[3]; - assign router_9_29_to_magia_tile_ni_9_29_rsp = router_9_29_rsp_out[4]; - - assign router_9_29_to_router_9_30_req = router_9_29_req_out[0]; - assign router_9_29_to_router_10_29_req = router_9_29_req_out[1]; - assign router_9_29_to_router_9_28_req = router_9_29_req_out[2]; - assign router_9_29_to_router_8_29_req = router_9_29_req_out[3]; - assign router_9_29_to_magia_tile_ni_9_29_req = router_9_29_req_out[4]; - - assign router_9_29_rsp_in[0] = router_9_30_to_router_9_29_rsp; - assign router_9_29_rsp_in[1] = router_10_29_to_router_9_29_rsp; - assign router_9_29_rsp_in[2] = router_9_28_to_router_9_29_rsp; - assign router_9_29_rsp_in[3] = router_8_29_to_router_9_29_rsp; - assign router_9_29_rsp_in[4] = magia_tile_ni_9_29_to_router_9_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_29_req_in), - .floo_rsp_o (router_9_29_rsp_out), - .floo_req_o (router_9_29_req_out), - .floo_rsp_i (router_9_29_rsp_in) -); - - -floo_req_t [4:0] router_9_30_req_in; -floo_rsp_t [4:0] router_9_30_rsp_out; -floo_req_t [4:0] router_9_30_req_out; -floo_rsp_t [4:0] router_9_30_rsp_in; - - assign router_9_30_req_in[0] = router_9_31_to_router_9_30_req; - assign router_9_30_req_in[1] = router_10_30_to_router_9_30_req; - assign router_9_30_req_in[2] = router_9_29_to_router_9_30_req; - assign router_9_30_req_in[3] = router_8_30_to_router_9_30_req; - assign router_9_30_req_in[4] = magia_tile_ni_9_30_to_router_9_30_req; - - assign router_9_30_to_router_9_31_rsp = router_9_30_rsp_out[0]; - assign router_9_30_to_router_10_30_rsp = router_9_30_rsp_out[1]; - assign router_9_30_to_router_9_29_rsp = router_9_30_rsp_out[2]; - assign router_9_30_to_router_8_30_rsp = router_9_30_rsp_out[3]; - assign router_9_30_to_magia_tile_ni_9_30_rsp = router_9_30_rsp_out[4]; - - assign router_9_30_to_router_9_31_req = router_9_30_req_out[0]; - assign router_9_30_to_router_10_30_req = router_9_30_req_out[1]; - assign router_9_30_to_router_9_29_req = router_9_30_req_out[2]; - assign router_9_30_to_router_8_30_req = router_9_30_req_out[3]; - assign router_9_30_to_magia_tile_ni_9_30_req = router_9_30_req_out[4]; - - assign router_9_30_rsp_in[0] = router_9_31_to_router_9_30_rsp; - assign router_9_30_rsp_in[1] = router_10_30_to_router_9_30_rsp; - assign router_9_30_rsp_in[2] = router_9_29_to_router_9_30_rsp; - assign router_9_30_rsp_in[3] = router_8_30_to_router_9_30_rsp; - assign router_9_30_rsp_in[4] = magia_tile_ni_9_30_to_router_9_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_30_req_in), - .floo_rsp_o (router_9_30_rsp_out), - .floo_req_o (router_9_30_req_out), - .floo_rsp_i (router_9_30_rsp_in) -); - - -floo_req_t [4:0] router_9_31_req_in; -floo_rsp_t [4:0] router_9_31_rsp_out; -floo_req_t [4:0] router_9_31_req_out; -floo_rsp_t [4:0] router_9_31_rsp_in; - - assign router_9_31_req_in[0] = '0; - assign router_9_31_req_in[1] = router_10_31_to_router_9_31_req; - assign router_9_31_req_in[2] = router_9_30_to_router_9_31_req; - assign router_9_31_req_in[3] = router_8_31_to_router_9_31_req; - assign router_9_31_req_in[4] = magia_tile_ni_9_31_to_router_9_31_req; - - assign router_9_31_to_router_10_31_rsp = router_9_31_rsp_out[1]; - assign router_9_31_to_router_9_30_rsp = router_9_31_rsp_out[2]; - assign router_9_31_to_router_8_31_rsp = router_9_31_rsp_out[3]; - assign router_9_31_to_magia_tile_ni_9_31_rsp = router_9_31_rsp_out[4]; - - assign router_9_31_to_router_10_31_req = router_9_31_req_out[1]; - assign router_9_31_to_router_9_30_req = router_9_31_req_out[2]; - assign router_9_31_to_router_8_31_req = router_9_31_req_out[3]; - assign router_9_31_to_magia_tile_ni_9_31_req = router_9_31_req_out[4]; - - assign router_9_31_rsp_in[0] = '0; - assign router_9_31_rsp_in[1] = router_10_31_to_router_9_31_rsp; - assign router_9_31_rsp_in[2] = router_9_30_to_router_9_31_rsp; - assign router_9_31_rsp_in[3] = router_8_31_to_router_9_31_rsp; - assign router_9_31_rsp_in[4] = magia_tile_ni_9_31_to_router_9_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_9_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 10, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_9_31_req_in), - .floo_rsp_o (router_9_31_rsp_out), - .floo_req_o (router_9_31_req_out), - .floo_rsp_i (router_9_31_rsp_in) -); - - -floo_req_t [4:0] router_10_0_req_in; -floo_rsp_t [4:0] router_10_0_rsp_out; -floo_req_t [4:0] router_10_0_req_out; -floo_rsp_t [4:0] router_10_0_rsp_in; - - assign router_10_0_req_in[0] = router_10_1_to_router_10_0_req; - assign router_10_0_req_in[1] = router_11_0_to_router_10_0_req; - assign router_10_0_req_in[2] = '0; - assign router_10_0_req_in[3] = router_9_0_to_router_10_0_req; - assign router_10_0_req_in[4] = magia_tile_ni_10_0_to_router_10_0_req; - - assign router_10_0_to_router_10_1_rsp = router_10_0_rsp_out[0]; - assign router_10_0_to_router_11_0_rsp = router_10_0_rsp_out[1]; - assign router_10_0_to_router_9_0_rsp = router_10_0_rsp_out[3]; - assign router_10_0_to_magia_tile_ni_10_0_rsp = router_10_0_rsp_out[4]; - - assign router_10_0_to_router_10_1_req = router_10_0_req_out[0]; - assign router_10_0_to_router_11_0_req = router_10_0_req_out[1]; - assign router_10_0_to_router_9_0_req = router_10_0_req_out[3]; - assign router_10_0_to_magia_tile_ni_10_0_req = router_10_0_req_out[4]; - - assign router_10_0_rsp_in[0] = router_10_1_to_router_10_0_rsp; - assign router_10_0_rsp_in[1] = router_11_0_to_router_10_0_rsp; - assign router_10_0_rsp_in[2] = '0; - assign router_10_0_rsp_in[3] = router_9_0_to_router_10_0_rsp; - assign router_10_0_rsp_in[4] = magia_tile_ni_10_0_to_router_10_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_0_req_in), - .floo_rsp_o (router_10_0_rsp_out), - .floo_req_o (router_10_0_req_out), - .floo_rsp_i (router_10_0_rsp_in) -); - - -floo_req_t [4:0] router_10_1_req_in; -floo_rsp_t [4:0] router_10_1_rsp_out; -floo_req_t [4:0] router_10_1_req_out; -floo_rsp_t [4:0] router_10_1_rsp_in; - - assign router_10_1_req_in[0] = router_10_2_to_router_10_1_req; - assign router_10_1_req_in[1] = router_11_1_to_router_10_1_req; - assign router_10_1_req_in[2] = router_10_0_to_router_10_1_req; - assign router_10_1_req_in[3] = router_9_1_to_router_10_1_req; - assign router_10_1_req_in[4] = magia_tile_ni_10_1_to_router_10_1_req; - - assign router_10_1_to_router_10_2_rsp = router_10_1_rsp_out[0]; - assign router_10_1_to_router_11_1_rsp = router_10_1_rsp_out[1]; - assign router_10_1_to_router_10_0_rsp = router_10_1_rsp_out[2]; - assign router_10_1_to_router_9_1_rsp = router_10_1_rsp_out[3]; - assign router_10_1_to_magia_tile_ni_10_1_rsp = router_10_1_rsp_out[4]; - - assign router_10_1_to_router_10_2_req = router_10_1_req_out[0]; - assign router_10_1_to_router_11_1_req = router_10_1_req_out[1]; - assign router_10_1_to_router_10_0_req = router_10_1_req_out[2]; - assign router_10_1_to_router_9_1_req = router_10_1_req_out[3]; - assign router_10_1_to_magia_tile_ni_10_1_req = router_10_1_req_out[4]; - - assign router_10_1_rsp_in[0] = router_10_2_to_router_10_1_rsp; - assign router_10_1_rsp_in[1] = router_11_1_to_router_10_1_rsp; - assign router_10_1_rsp_in[2] = router_10_0_to_router_10_1_rsp; - assign router_10_1_rsp_in[3] = router_9_1_to_router_10_1_rsp; - assign router_10_1_rsp_in[4] = magia_tile_ni_10_1_to_router_10_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_1_req_in), - .floo_rsp_o (router_10_1_rsp_out), - .floo_req_o (router_10_1_req_out), - .floo_rsp_i (router_10_1_rsp_in) -); - - -floo_req_t [4:0] router_10_2_req_in; -floo_rsp_t [4:0] router_10_2_rsp_out; -floo_req_t [4:0] router_10_2_req_out; -floo_rsp_t [4:0] router_10_2_rsp_in; - - assign router_10_2_req_in[0] = router_10_3_to_router_10_2_req; - assign router_10_2_req_in[1] = router_11_2_to_router_10_2_req; - assign router_10_2_req_in[2] = router_10_1_to_router_10_2_req; - assign router_10_2_req_in[3] = router_9_2_to_router_10_2_req; - assign router_10_2_req_in[4] = magia_tile_ni_10_2_to_router_10_2_req; - - assign router_10_2_to_router_10_3_rsp = router_10_2_rsp_out[0]; - assign router_10_2_to_router_11_2_rsp = router_10_2_rsp_out[1]; - assign router_10_2_to_router_10_1_rsp = router_10_2_rsp_out[2]; - assign router_10_2_to_router_9_2_rsp = router_10_2_rsp_out[3]; - assign router_10_2_to_magia_tile_ni_10_2_rsp = router_10_2_rsp_out[4]; - - assign router_10_2_to_router_10_3_req = router_10_2_req_out[0]; - assign router_10_2_to_router_11_2_req = router_10_2_req_out[1]; - assign router_10_2_to_router_10_1_req = router_10_2_req_out[2]; - assign router_10_2_to_router_9_2_req = router_10_2_req_out[3]; - assign router_10_2_to_magia_tile_ni_10_2_req = router_10_2_req_out[4]; - - assign router_10_2_rsp_in[0] = router_10_3_to_router_10_2_rsp; - assign router_10_2_rsp_in[1] = router_11_2_to_router_10_2_rsp; - assign router_10_2_rsp_in[2] = router_10_1_to_router_10_2_rsp; - assign router_10_2_rsp_in[3] = router_9_2_to_router_10_2_rsp; - assign router_10_2_rsp_in[4] = magia_tile_ni_10_2_to_router_10_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_2_req_in), - .floo_rsp_o (router_10_2_rsp_out), - .floo_req_o (router_10_2_req_out), - .floo_rsp_i (router_10_2_rsp_in) -); - - -floo_req_t [4:0] router_10_3_req_in; -floo_rsp_t [4:0] router_10_3_rsp_out; -floo_req_t [4:0] router_10_3_req_out; -floo_rsp_t [4:0] router_10_3_rsp_in; - - assign router_10_3_req_in[0] = router_10_4_to_router_10_3_req; - assign router_10_3_req_in[1] = router_11_3_to_router_10_3_req; - assign router_10_3_req_in[2] = router_10_2_to_router_10_3_req; - assign router_10_3_req_in[3] = router_9_3_to_router_10_3_req; - assign router_10_3_req_in[4] = magia_tile_ni_10_3_to_router_10_3_req; - - assign router_10_3_to_router_10_4_rsp = router_10_3_rsp_out[0]; - assign router_10_3_to_router_11_3_rsp = router_10_3_rsp_out[1]; - assign router_10_3_to_router_10_2_rsp = router_10_3_rsp_out[2]; - assign router_10_3_to_router_9_3_rsp = router_10_3_rsp_out[3]; - assign router_10_3_to_magia_tile_ni_10_3_rsp = router_10_3_rsp_out[4]; - - assign router_10_3_to_router_10_4_req = router_10_3_req_out[0]; - assign router_10_3_to_router_11_3_req = router_10_3_req_out[1]; - assign router_10_3_to_router_10_2_req = router_10_3_req_out[2]; - assign router_10_3_to_router_9_3_req = router_10_3_req_out[3]; - assign router_10_3_to_magia_tile_ni_10_3_req = router_10_3_req_out[4]; - - assign router_10_3_rsp_in[0] = router_10_4_to_router_10_3_rsp; - assign router_10_3_rsp_in[1] = router_11_3_to_router_10_3_rsp; - assign router_10_3_rsp_in[2] = router_10_2_to_router_10_3_rsp; - assign router_10_3_rsp_in[3] = router_9_3_to_router_10_3_rsp; - assign router_10_3_rsp_in[4] = magia_tile_ni_10_3_to_router_10_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_3_req_in), - .floo_rsp_o (router_10_3_rsp_out), - .floo_req_o (router_10_3_req_out), - .floo_rsp_i (router_10_3_rsp_in) -); - - -floo_req_t [4:0] router_10_4_req_in; -floo_rsp_t [4:0] router_10_4_rsp_out; -floo_req_t [4:0] router_10_4_req_out; -floo_rsp_t [4:0] router_10_4_rsp_in; - - assign router_10_4_req_in[0] = router_10_5_to_router_10_4_req; - assign router_10_4_req_in[1] = router_11_4_to_router_10_4_req; - assign router_10_4_req_in[2] = router_10_3_to_router_10_4_req; - assign router_10_4_req_in[3] = router_9_4_to_router_10_4_req; - assign router_10_4_req_in[4] = magia_tile_ni_10_4_to_router_10_4_req; - - assign router_10_4_to_router_10_5_rsp = router_10_4_rsp_out[0]; - assign router_10_4_to_router_11_4_rsp = router_10_4_rsp_out[1]; - assign router_10_4_to_router_10_3_rsp = router_10_4_rsp_out[2]; - assign router_10_4_to_router_9_4_rsp = router_10_4_rsp_out[3]; - assign router_10_4_to_magia_tile_ni_10_4_rsp = router_10_4_rsp_out[4]; - - assign router_10_4_to_router_10_5_req = router_10_4_req_out[0]; - assign router_10_4_to_router_11_4_req = router_10_4_req_out[1]; - assign router_10_4_to_router_10_3_req = router_10_4_req_out[2]; - assign router_10_4_to_router_9_4_req = router_10_4_req_out[3]; - assign router_10_4_to_magia_tile_ni_10_4_req = router_10_4_req_out[4]; - - assign router_10_4_rsp_in[0] = router_10_5_to_router_10_4_rsp; - assign router_10_4_rsp_in[1] = router_11_4_to_router_10_4_rsp; - assign router_10_4_rsp_in[2] = router_10_3_to_router_10_4_rsp; - assign router_10_4_rsp_in[3] = router_9_4_to_router_10_4_rsp; - assign router_10_4_rsp_in[4] = magia_tile_ni_10_4_to_router_10_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_4_req_in), - .floo_rsp_o (router_10_4_rsp_out), - .floo_req_o (router_10_4_req_out), - .floo_rsp_i (router_10_4_rsp_in) -); - - -floo_req_t [4:0] router_10_5_req_in; -floo_rsp_t [4:0] router_10_5_rsp_out; -floo_req_t [4:0] router_10_5_req_out; -floo_rsp_t [4:0] router_10_5_rsp_in; - - assign router_10_5_req_in[0] = router_10_6_to_router_10_5_req; - assign router_10_5_req_in[1] = router_11_5_to_router_10_5_req; - assign router_10_5_req_in[2] = router_10_4_to_router_10_5_req; - assign router_10_5_req_in[3] = router_9_5_to_router_10_5_req; - assign router_10_5_req_in[4] = magia_tile_ni_10_5_to_router_10_5_req; - - assign router_10_5_to_router_10_6_rsp = router_10_5_rsp_out[0]; - assign router_10_5_to_router_11_5_rsp = router_10_5_rsp_out[1]; - assign router_10_5_to_router_10_4_rsp = router_10_5_rsp_out[2]; - assign router_10_5_to_router_9_5_rsp = router_10_5_rsp_out[3]; - assign router_10_5_to_magia_tile_ni_10_5_rsp = router_10_5_rsp_out[4]; - - assign router_10_5_to_router_10_6_req = router_10_5_req_out[0]; - assign router_10_5_to_router_11_5_req = router_10_5_req_out[1]; - assign router_10_5_to_router_10_4_req = router_10_5_req_out[2]; - assign router_10_5_to_router_9_5_req = router_10_5_req_out[3]; - assign router_10_5_to_magia_tile_ni_10_5_req = router_10_5_req_out[4]; - - assign router_10_5_rsp_in[0] = router_10_6_to_router_10_5_rsp; - assign router_10_5_rsp_in[1] = router_11_5_to_router_10_5_rsp; - assign router_10_5_rsp_in[2] = router_10_4_to_router_10_5_rsp; - assign router_10_5_rsp_in[3] = router_9_5_to_router_10_5_rsp; - assign router_10_5_rsp_in[4] = magia_tile_ni_10_5_to_router_10_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_5_req_in), - .floo_rsp_o (router_10_5_rsp_out), - .floo_req_o (router_10_5_req_out), - .floo_rsp_i (router_10_5_rsp_in) -); - - -floo_req_t [4:0] router_10_6_req_in; -floo_rsp_t [4:0] router_10_6_rsp_out; -floo_req_t [4:0] router_10_6_req_out; -floo_rsp_t [4:0] router_10_6_rsp_in; - - assign router_10_6_req_in[0] = router_10_7_to_router_10_6_req; - assign router_10_6_req_in[1] = router_11_6_to_router_10_6_req; - assign router_10_6_req_in[2] = router_10_5_to_router_10_6_req; - assign router_10_6_req_in[3] = router_9_6_to_router_10_6_req; - assign router_10_6_req_in[4] = magia_tile_ni_10_6_to_router_10_6_req; - - assign router_10_6_to_router_10_7_rsp = router_10_6_rsp_out[0]; - assign router_10_6_to_router_11_6_rsp = router_10_6_rsp_out[1]; - assign router_10_6_to_router_10_5_rsp = router_10_6_rsp_out[2]; - assign router_10_6_to_router_9_6_rsp = router_10_6_rsp_out[3]; - assign router_10_6_to_magia_tile_ni_10_6_rsp = router_10_6_rsp_out[4]; - - assign router_10_6_to_router_10_7_req = router_10_6_req_out[0]; - assign router_10_6_to_router_11_6_req = router_10_6_req_out[1]; - assign router_10_6_to_router_10_5_req = router_10_6_req_out[2]; - assign router_10_6_to_router_9_6_req = router_10_6_req_out[3]; - assign router_10_6_to_magia_tile_ni_10_6_req = router_10_6_req_out[4]; - - assign router_10_6_rsp_in[0] = router_10_7_to_router_10_6_rsp; - assign router_10_6_rsp_in[1] = router_11_6_to_router_10_6_rsp; - assign router_10_6_rsp_in[2] = router_10_5_to_router_10_6_rsp; - assign router_10_6_rsp_in[3] = router_9_6_to_router_10_6_rsp; - assign router_10_6_rsp_in[4] = magia_tile_ni_10_6_to_router_10_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_6_req_in), - .floo_rsp_o (router_10_6_rsp_out), - .floo_req_o (router_10_6_req_out), - .floo_rsp_i (router_10_6_rsp_in) -); - - -floo_req_t [4:0] router_10_7_req_in; -floo_rsp_t [4:0] router_10_7_rsp_out; -floo_req_t [4:0] router_10_7_req_out; -floo_rsp_t [4:0] router_10_7_rsp_in; - - assign router_10_7_req_in[0] = router_10_8_to_router_10_7_req; - assign router_10_7_req_in[1] = router_11_7_to_router_10_7_req; - assign router_10_7_req_in[2] = router_10_6_to_router_10_7_req; - assign router_10_7_req_in[3] = router_9_7_to_router_10_7_req; - assign router_10_7_req_in[4] = magia_tile_ni_10_7_to_router_10_7_req; - - assign router_10_7_to_router_10_8_rsp = router_10_7_rsp_out[0]; - assign router_10_7_to_router_11_7_rsp = router_10_7_rsp_out[1]; - assign router_10_7_to_router_10_6_rsp = router_10_7_rsp_out[2]; - assign router_10_7_to_router_9_7_rsp = router_10_7_rsp_out[3]; - assign router_10_7_to_magia_tile_ni_10_7_rsp = router_10_7_rsp_out[4]; - - assign router_10_7_to_router_10_8_req = router_10_7_req_out[0]; - assign router_10_7_to_router_11_7_req = router_10_7_req_out[1]; - assign router_10_7_to_router_10_6_req = router_10_7_req_out[2]; - assign router_10_7_to_router_9_7_req = router_10_7_req_out[3]; - assign router_10_7_to_magia_tile_ni_10_7_req = router_10_7_req_out[4]; - - assign router_10_7_rsp_in[0] = router_10_8_to_router_10_7_rsp; - assign router_10_7_rsp_in[1] = router_11_7_to_router_10_7_rsp; - assign router_10_7_rsp_in[2] = router_10_6_to_router_10_7_rsp; - assign router_10_7_rsp_in[3] = router_9_7_to_router_10_7_rsp; - assign router_10_7_rsp_in[4] = magia_tile_ni_10_7_to_router_10_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_7_req_in), - .floo_rsp_o (router_10_7_rsp_out), - .floo_req_o (router_10_7_req_out), - .floo_rsp_i (router_10_7_rsp_in) -); - - -floo_req_t [4:0] router_10_8_req_in; -floo_rsp_t [4:0] router_10_8_rsp_out; -floo_req_t [4:0] router_10_8_req_out; -floo_rsp_t [4:0] router_10_8_rsp_in; - - assign router_10_8_req_in[0] = router_10_9_to_router_10_8_req; - assign router_10_8_req_in[1] = router_11_8_to_router_10_8_req; - assign router_10_8_req_in[2] = router_10_7_to_router_10_8_req; - assign router_10_8_req_in[3] = router_9_8_to_router_10_8_req; - assign router_10_8_req_in[4] = magia_tile_ni_10_8_to_router_10_8_req; - - assign router_10_8_to_router_10_9_rsp = router_10_8_rsp_out[0]; - assign router_10_8_to_router_11_8_rsp = router_10_8_rsp_out[1]; - assign router_10_8_to_router_10_7_rsp = router_10_8_rsp_out[2]; - assign router_10_8_to_router_9_8_rsp = router_10_8_rsp_out[3]; - assign router_10_8_to_magia_tile_ni_10_8_rsp = router_10_8_rsp_out[4]; - - assign router_10_8_to_router_10_9_req = router_10_8_req_out[0]; - assign router_10_8_to_router_11_8_req = router_10_8_req_out[1]; - assign router_10_8_to_router_10_7_req = router_10_8_req_out[2]; - assign router_10_8_to_router_9_8_req = router_10_8_req_out[3]; - assign router_10_8_to_magia_tile_ni_10_8_req = router_10_8_req_out[4]; - - assign router_10_8_rsp_in[0] = router_10_9_to_router_10_8_rsp; - assign router_10_8_rsp_in[1] = router_11_8_to_router_10_8_rsp; - assign router_10_8_rsp_in[2] = router_10_7_to_router_10_8_rsp; - assign router_10_8_rsp_in[3] = router_9_8_to_router_10_8_rsp; - assign router_10_8_rsp_in[4] = magia_tile_ni_10_8_to_router_10_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_8_req_in), - .floo_rsp_o (router_10_8_rsp_out), - .floo_req_o (router_10_8_req_out), - .floo_rsp_i (router_10_8_rsp_in) -); - - -floo_req_t [4:0] router_10_9_req_in; -floo_rsp_t [4:0] router_10_9_rsp_out; -floo_req_t [4:0] router_10_9_req_out; -floo_rsp_t [4:0] router_10_9_rsp_in; - - assign router_10_9_req_in[0] = router_10_10_to_router_10_9_req; - assign router_10_9_req_in[1] = router_11_9_to_router_10_9_req; - assign router_10_9_req_in[2] = router_10_8_to_router_10_9_req; - assign router_10_9_req_in[3] = router_9_9_to_router_10_9_req; - assign router_10_9_req_in[4] = magia_tile_ni_10_9_to_router_10_9_req; - - assign router_10_9_to_router_10_10_rsp = router_10_9_rsp_out[0]; - assign router_10_9_to_router_11_9_rsp = router_10_9_rsp_out[1]; - assign router_10_9_to_router_10_8_rsp = router_10_9_rsp_out[2]; - assign router_10_9_to_router_9_9_rsp = router_10_9_rsp_out[3]; - assign router_10_9_to_magia_tile_ni_10_9_rsp = router_10_9_rsp_out[4]; - - assign router_10_9_to_router_10_10_req = router_10_9_req_out[0]; - assign router_10_9_to_router_11_9_req = router_10_9_req_out[1]; - assign router_10_9_to_router_10_8_req = router_10_9_req_out[2]; - assign router_10_9_to_router_9_9_req = router_10_9_req_out[3]; - assign router_10_9_to_magia_tile_ni_10_9_req = router_10_9_req_out[4]; - - assign router_10_9_rsp_in[0] = router_10_10_to_router_10_9_rsp; - assign router_10_9_rsp_in[1] = router_11_9_to_router_10_9_rsp; - assign router_10_9_rsp_in[2] = router_10_8_to_router_10_9_rsp; - assign router_10_9_rsp_in[3] = router_9_9_to_router_10_9_rsp; - assign router_10_9_rsp_in[4] = magia_tile_ni_10_9_to_router_10_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_9_req_in), - .floo_rsp_o (router_10_9_rsp_out), - .floo_req_o (router_10_9_req_out), - .floo_rsp_i (router_10_9_rsp_in) -); - - -floo_req_t [4:0] router_10_10_req_in; -floo_rsp_t [4:0] router_10_10_rsp_out; -floo_req_t [4:0] router_10_10_req_out; -floo_rsp_t [4:0] router_10_10_rsp_in; - - assign router_10_10_req_in[0] = router_10_11_to_router_10_10_req; - assign router_10_10_req_in[1] = router_11_10_to_router_10_10_req; - assign router_10_10_req_in[2] = router_10_9_to_router_10_10_req; - assign router_10_10_req_in[3] = router_9_10_to_router_10_10_req; - assign router_10_10_req_in[4] = magia_tile_ni_10_10_to_router_10_10_req; - - assign router_10_10_to_router_10_11_rsp = router_10_10_rsp_out[0]; - assign router_10_10_to_router_11_10_rsp = router_10_10_rsp_out[1]; - assign router_10_10_to_router_10_9_rsp = router_10_10_rsp_out[2]; - assign router_10_10_to_router_9_10_rsp = router_10_10_rsp_out[3]; - assign router_10_10_to_magia_tile_ni_10_10_rsp = router_10_10_rsp_out[4]; - - assign router_10_10_to_router_10_11_req = router_10_10_req_out[0]; - assign router_10_10_to_router_11_10_req = router_10_10_req_out[1]; - assign router_10_10_to_router_10_9_req = router_10_10_req_out[2]; - assign router_10_10_to_router_9_10_req = router_10_10_req_out[3]; - assign router_10_10_to_magia_tile_ni_10_10_req = router_10_10_req_out[4]; - - assign router_10_10_rsp_in[0] = router_10_11_to_router_10_10_rsp; - assign router_10_10_rsp_in[1] = router_11_10_to_router_10_10_rsp; - assign router_10_10_rsp_in[2] = router_10_9_to_router_10_10_rsp; - assign router_10_10_rsp_in[3] = router_9_10_to_router_10_10_rsp; - assign router_10_10_rsp_in[4] = magia_tile_ni_10_10_to_router_10_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_10_req_in), - .floo_rsp_o (router_10_10_rsp_out), - .floo_req_o (router_10_10_req_out), - .floo_rsp_i (router_10_10_rsp_in) -); - - -floo_req_t [4:0] router_10_11_req_in; -floo_rsp_t [4:0] router_10_11_rsp_out; -floo_req_t [4:0] router_10_11_req_out; -floo_rsp_t [4:0] router_10_11_rsp_in; - - assign router_10_11_req_in[0] = router_10_12_to_router_10_11_req; - assign router_10_11_req_in[1] = router_11_11_to_router_10_11_req; - assign router_10_11_req_in[2] = router_10_10_to_router_10_11_req; - assign router_10_11_req_in[3] = router_9_11_to_router_10_11_req; - assign router_10_11_req_in[4] = magia_tile_ni_10_11_to_router_10_11_req; - - assign router_10_11_to_router_10_12_rsp = router_10_11_rsp_out[0]; - assign router_10_11_to_router_11_11_rsp = router_10_11_rsp_out[1]; - assign router_10_11_to_router_10_10_rsp = router_10_11_rsp_out[2]; - assign router_10_11_to_router_9_11_rsp = router_10_11_rsp_out[3]; - assign router_10_11_to_magia_tile_ni_10_11_rsp = router_10_11_rsp_out[4]; - - assign router_10_11_to_router_10_12_req = router_10_11_req_out[0]; - assign router_10_11_to_router_11_11_req = router_10_11_req_out[1]; - assign router_10_11_to_router_10_10_req = router_10_11_req_out[2]; - assign router_10_11_to_router_9_11_req = router_10_11_req_out[3]; - assign router_10_11_to_magia_tile_ni_10_11_req = router_10_11_req_out[4]; - - assign router_10_11_rsp_in[0] = router_10_12_to_router_10_11_rsp; - assign router_10_11_rsp_in[1] = router_11_11_to_router_10_11_rsp; - assign router_10_11_rsp_in[2] = router_10_10_to_router_10_11_rsp; - assign router_10_11_rsp_in[3] = router_9_11_to_router_10_11_rsp; - assign router_10_11_rsp_in[4] = magia_tile_ni_10_11_to_router_10_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_11_req_in), - .floo_rsp_o (router_10_11_rsp_out), - .floo_req_o (router_10_11_req_out), - .floo_rsp_i (router_10_11_rsp_in) -); - - -floo_req_t [4:0] router_10_12_req_in; -floo_rsp_t [4:0] router_10_12_rsp_out; -floo_req_t [4:0] router_10_12_req_out; -floo_rsp_t [4:0] router_10_12_rsp_in; - - assign router_10_12_req_in[0] = router_10_13_to_router_10_12_req; - assign router_10_12_req_in[1] = router_11_12_to_router_10_12_req; - assign router_10_12_req_in[2] = router_10_11_to_router_10_12_req; - assign router_10_12_req_in[3] = router_9_12_to_router_10_12_req; - assign router_10_12_req_in[4] = magia_tile_ni_10_12_to_router_10_12_req; - - assign router_10_12_to_router_10_13_rsp = router_10_12_rsp_out[0]; - assign router_10_12_to_router_11_12_rsp = router_10_12_rsp_out[1]; - assign router_10_12_to_router_10_11_rsp = router_10_12_rsp_out[2]; - assign router_10_12_to_router_9_12_rsp = router_10_12_rsp_out[3]; - assign router_10_12_to_magia_tile_ni_10_12_rsp = router_10_12_rsp_out[4]; - - assign router_10_12_to_router_10_13_req = router_10_12_req_out[0]; - assign router_10_12_to_router_11_12_req = router_10_12_req_out[1]; - assign router_10_12_to_router_10_11_req = router_10_12_req_out[2]; - assign router_10_12_to_router_9_12_req = router_10_12_req_out[3]; - assign router_10_12_to_magia_tile_ni_10_12_req = router_10_12_req_out[4]; - - assign router_10_12_rsp_in[0] = router_10_13_to_router_10_12_rsp; - assign router_10_12_rsp_in[1] = router_11_12_to_router_10_12_rsp; - assign router_10_12_rsp_in[2] = router_10_11_to_router_10_12_rsp; - assign router_10_12_rsp_in[3] = router_9_12_to_router_10_12_rsp; - assign router_10_12_rsp_in[4] = magia_tile_ni_10_12_to_router_10_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_12_req_in), - .floo_rsp_o (router_10_12_rsp_out), - .floo_req_o (router_10_12_req_out), - .floo_rsp_i (router_10_12_rsp_in) -); - - -floo_req_t [4:0] router_10_13_req_in; -floo_rsp_t [4:0] router_10_13_rsp_out; -floo_req_t [4:0] router_10_13_req_out; -floo_rsp_t [4:0] router_10_13_rsp_in; - - assign router_10_13_req_in[0] = router_10_14_to_router_10_13_req; - assign router_10_13_req_in[1] = router_11_13_to_router_10_13_req; - assign router_10_13_req_in[2] = router_10_12_to_router_10_13_req; - assign router_10_13_req_in[3] = router_9_13_to_router_10_13_req; - assign router_10_13_req_in[4] = magia_tile_ni_10_13_to_router_10_13_req; - - assign router_10_13_to_router_10_14_rsp = router_10_13_rsp_out[0]; - assign router_10_13_to_router_11_13_rsp = router_10_13_rsp_out[1]; - assign router_10_13_to_router_10_12_rsp = router_10_13_rsp_out[2]; - assign router_10_13_to_router_9_13_rsp = router_10_13_rsp_out[3]; - assign router_10_13_to_magia_tile_ni_10_13_rsp = router_10_13_rsp_out[4]; - - assign router_10_13_to_router_10_14_req = router_10_13_req_out[0]; - assign router_10_13_to_router_11_13_req = router_10_13_req_out[1]; - assign router_10_13_to_router_10_12_req = router_10_13_req_out[2]; - assign router_10_13_to_router_9_13_req = router_10_13_req_out[3]; - assign router_10_13_to_magia_tile_ni_10_13_req = router_10_13_req_out[4]; - - assign router_10_13_rsp_in[0] = router_10_14_to_router_10_13_rsp; - assign router_10_13_rsp_in[1] = router_11_13_to_router_10_13_rsp; - assign router_10_13_rsp_in[2] = router_10_12_to_router_10_13_rsp; - assign router_10_13_rsp_in[3] = router_9_13_to_router_10_13_rsp; - assign router_10_13_rsp_in[4] = magia_tile_ni_10_13_to_router_10_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_13_req_in), - .floo_rsp_o (router_10_13_rsp_out), - .floo_req_o (router_10_13_req_out), - .floo_rsp_i (router_10_13_rsp_in) -); - - -floo_req_t [4:0] router_10_14_req_in; -floo_rsp_t [4:0] router_10_14_rsp_out; -floo_req_t [4:0] router_10_14_req_out; -floo_rsp_t [4:0] router_10_14_rsp_in; - - assign router_10_14_req_in[0] = router_10_15_to_router_10_14_req; - assign router_10_14_req_in[1] = router_11_14_to_router_10_14_req; - assign router_10_14_req_in[2] = router_10_13_to_router_10_14_req; - assign router_10_14_req_in[3] = router_9_14_to_router_10_14_req; - assign router_10_14_req_in[4] = magia_tile_ni_10_14_to_router_10_14_req; - - assign router_10_14_to_router_10_15_rsp = router_10_14_rsp_out[0]; - assign router_10_14_to_router_11_14_rsp = router_10_14_rsp_out[1]; - assign router_10_14_to_router_10_13_rsp = router_10_14_rsp_out[2]; - assign router_10_14_to_router_9_14_rsp = router_10_14_rsp_out[3]; - assign router_10_14_to_magia_tile_ni_10_14_rsp = router_10_14_rsp_out[4]; - - assign router_10_14_to_router_10_15_req = router_10_14_req_out[0]; - assign router_10_14_to_router_11_14_req = router_10_14_req_out[1]; - assign router_10_14_to_router_10_13_req = router_10_14_req_out[2]; - assign router_10_14_to_router_9_14_req = router_10_14_req_out[3]; - assign router_10_14_to_magia_tile_ni_10_14_req = router_10_14_req_out[4]; - - assign router_10_14_rsp_in[0] = router_10_15_to_router_10_14_rsp; - assign router_10_14_rsp_in[1] = router_11_14_to_router_10_14_rsp; - assign router_10_14_rsp_in[2] = router_10_13_to_router_10_14_rsp; - assign router_10_14_rsp_in[3] = router_9_14_to_router_10_14_rsp; - assign router_10_14_rsp_in[4] = magia_tile_ni_10_14_to_router_10_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_14_req_in), - .floo_rsp_o (router_10_14_rsp_out), - .floo_req_o (router_10_14_req_out), - .floo_rsp_i (router_10_14_rsp_in) -); - - -floo_req_t [4:0] router_10_15_req_in; -floo_rsp_t [4:0] router_10_15_rsp_out; -floo_req_t [4:0] router_10_15_req_out; -floo_rsp_t [4:0] router_10_15_rsp_in; - - assign router_10_15_req_in[0] = router_10_16_to_router_10_15_req; - assign router_10_15_req_in[1] = router_11_15_to_router_10_15_req; - assign router_10_15_req_in[2] = router_10_14_to_router_10_15_req; - assign router_10_15_req_in[3] = router_9_15_to_router_10_15_req; - assign router_10_15_req_in[4] = magia_tile_ni_10_15_to_router_10_15_req; - - assign router_10_15_to_router_10_16_rsp = router_10_15_rsp_out[0]; - assign router_10_15_to_router_11_15_rsp = router_10_15_rsp_out[1]; - assign router_10_15_to_router_10_14_rsp = router_10_15_rsp_out[2]; - assign router_10_15_to_router_9_15_rsp = router_10_15_rsp_out[3]; - assign router_10_15_to_magia_tile_ni_10_15_rsp = router_10_15_rsp_out[4]; - - assign router_10_15_to_router_10_16_req = router_10_15_req_out[0]; - assign router_10_15_to_router_11_15_req = router_10_15_req_out[1]; - assign router_10_15_to_router_10_14_req = router_10_15_req_out[2]; - assign router_10_15_to_router_9_15_req = router_10_15_req_out[3]; - assign router_10_15_to_magia_tile_ni_10_15_req = router_10_15_req_out[4]; - - assign router_10_15_rsp_in[0] = router_10_16_to_router_10_15_rsp; - assign router_10_15_rsp_in[1] = router_11_15_to_router_10_15_rsp; - assign router_10_15_rsp_in[2] = router_10_14_to_router_10_15_rsp; - assign router_10_15_rsp_in[3] = router_9_15_to_router_10_15_rsp; - assign router_10_15_rsp_in[4] = magia_tile_ni_10_15_to_router_10_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_15_req_in), - .floo_rsp_o (router_10_15_rsp_out), - .floo_req_o (router_10_15_req_out), - .floo_rsp_i (router_10_15_rsp_in) -); - - -floo_req_t [4:0] router_10_16_req_in; -floo_rsp_t [4:0] router_10_16_rsp_out; -floo_req_t [4:0] router_10_16_req_out; -floo_rsp_t [4:0] router_10_16_rsp_in; - - assign router_10_16_req_in[0] = router_10_17_to_router_10_16_req; - assign router_10_16_req_in[1] = router_11_16_to_router_10_16_req; - assign router_10_16_req_in[2] = router_10_15_to_router_10_16_req; - assign router_10_16_req_in[3] = router_9_16_to_router_10_16_req; - assign router_10_16_req_in[4] = magia_tile_ni_10_16_to_router_10_16_req; - - assign router_10_16_to_router_10_17_rsp = router_10_16_rsp_out[0]; - assign router_10_16_to_router_11_16_rsp = router_10_16_rsp_out[1]; - assign router_10_16_to_router_10_15_rsp = router_10_16_rsp_out[2]; - assign router_10_16_to_router_9_16_rsp = router_10_16_rsp_out[3]; - assign router_10_16_to_magia_tile_ni_10_16_rsp = router_10_16_rsp_out[4]; - - assign router_10_16_to_router_10_17_req = router_10_16_req_out[0]; - assign router_10_16_to_router_11_16_req = router_10_16_req_out[1]; - assign router_10_16_to_router_10_15_req = router_10_16_req_out[2]; - assign router_10_16_to_router_9_16_req = router_10_16_req_out[3]; - assign router_10_16_to_magia_tile_ni_10_16_req = router_10_16_req_out[4]; - - assign router_10_16_rsp_in[0] = router_10_17_to_router_10_16_rsp; - assign router_10_16_rsp_in[1] = router_11_16_to_router_10_16_rsp; - assign router_10_16_rsp_in[2] = router_10_15_to_router_10_16_rsp; - assign router_10_16_rsp_in[3] = router_9_16_to_router_10_16_rsp; - assign router_10_16_rsp_in[4] = magia_tile_ni_10_16_to_router_10_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_16_req_in), - .floo_rsp_o (router_10_16_rsp_out), - .floo_req_o (router_10_16_req_out), - .floo_rsp_i (router_10_16_rsp_in) -); - - -floo_req_t [4:0] router_10_17_req_in; -floo_rsp_t [4:0] router_10_17_rsp_out; -floo_req_t [4:0] router_10_17_req_out; -floo_rsp_t [4:0] router_10_17_rsp_in; - - assign router_10_17_req_in[0] = router_10_18_to_router_10_17_req; - assign router_10_17_req_in[1] = router_11_17_to_router_10_17_req; - assign router_10_17_req_in[2] = router_10_16_to_router_10_17_req; - assign router_10_17_req_in[3] = router_9_17_to_router_10_17_req; - assign router_10_17_req_in[4] = magia_tile_ni_10_17_to_router_10_17_req; - - assign router_10_17_to_router_10_18_rsp = router_10_17_rsp_out[0]; - assign router_10_17_to_router_11_17_rsp = router_10_17_rsp_out[1]; - assign router_10_17_to_router_10_16_rsp = router_10_17_rsp_out[2]; - assign router_10_17_to_router_9_17_rsp = router_10_17_rsp_out[3]; - assign router_10_17_to_magia_tile_ni_10_17_rsp = router_10_17_rsp_out[4]; - - assign router_10_17_to_router_10_18_req = router_10_17_req_out[0]; - assign router_10_17_to_router_11_17_req = router_10_17_req_out[1]; - assign router_10_17_to_router_10_16_req = router_10_17_req_out[2]; - assign router_10_17_to_router_9_17_req = router_10_17_req_out[3]; - assign router_10_17_to_magia_tile_ni_10_17_req = router_10_17_req_out[4]; - - assign router_10_17_rsp_in[0] = router_10_18_to_router_10_17_rsp; - assign router_10_17_rsp_in[1] = router_11_17_to_router_10_17_rsp; - assign router_10_17_rsp_in[2] = router_10_16_to_router_10_17_rsp; - assign router_10_17_rsp_in[3] = router_9_17_to_router_10_17_rsp; - assign router_10_17_rsp_in[4] = magia_tile_ni_10_17_to_router_10_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_17_req_in), - .floo_rsp_o (router_10_17_rsp_out), - .floo_req_o (router_10_17_req_out), - .floo_rsp_i (router_10_17_rsp_in) -); - - -floo_req_t [4:0] router_10_18_req_in; -floo_rsp_t [4:0] router_10_18_rsp_out; -floo_req_t [4:0] router_10_18_req_out; -floo_rsp_t [4:0] router_10_18_rsp_in; - - assign router_10_18_req_in[0] = router_10_19_to_router_10_18_req; - assign router_10_18_req_in[1] = router_11_18_to_router_10_18_req; - assign router_10_18_req_in[2] = router_10_17_to_router_10_18_req; - assign router_10_18_req_in[3] = router_9_18_to_router_10_18_req; - assign router_10_18_req_in[4] = magia_tile_ni_10_18_to_router_10_18_req; - - assign router_10_18_to_router_10_19_rsp = router_10_18_rsp_out[0]; - assign router_10_18_to_router_11_18_rsp = router_10_18_rsp_out[1]; - assign router_10_18_to_router_10_17_rsp = router_10_18_rsp_out[2]; - assign router_10_18_to_router_9_18_rsp = router_10_18_rsp_out[3]; - assign router_10_18_to_magia_tile_ni_10_18_rsp = router_10_18_rsp_out[4]; - - assign router_10_18_to_router_10_19_req = router_10_18_req_out[0]; - assign router_10_18_to_router_11_18_req = router_10_18_req_out[1]; - assign router_10_18_to_router_10_17_req = router_10_18_req_out[2]; - assign router_10_18_to_router_9_18_req = router_10_18_req_out[3]; - assign router_10_18_to_magia_tile_ni_10_18_req = router_10_18_req_out[4]; - - assign router_10_18_rsp_in[0] = router_10_19_to_router_10_18_rsp; - assign router_10_18_rsp_in[1] = router_11_18_to_router_10_18_rsp; - assign router_10_18_rsp_in[2] = router_10_17_to_router_10_18_rsp; - assign router_10_18_rsp_in[3] = router_9_18_to_router_10_18_rsp; - assign router_10_18_rsp_in[4] = magia_tile_ni_10_18_to_router_10_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_18_req_in), - .floo_rsp_o (router_10_18_rsp_out), - .floo_req_o (router_10_18_req_out), - .floo_rsp_i (router_10_18_rsp_in) -); - - -floo_req_t [4:0] router_10_19_req_in; -floo_rsp_t [4:0] router_10_19_rsp_out; -floo_req_t [4:0] router_10_19_req_out; -floo_rsp_t [4:0] router_10_19_rsp_in; - - assign router_10_19_req_in[0] = router_10_20_to_router_10_19_req; - assign router_10_19_req_in[1] = router_11_19_to_router_10_19_req; - assign router_10_19_req_in[2] = router_10_18_to_router_10_19_req; - assign router_10_19_req_in[3] = router_9_19_to_router_10_19_req; - assign router_10_19_req_in[4] = magia_tile_ni_10_19_to_router_10_19_req; - - assign router_10_19_to_router_10_20_rsp = router_10_19_rsp_out[0]; - assign router_10_19_to_router_11_19_rsp = router_10_19_rsp_out[1]; - assign router_10_19_to_router_10_18_rsp = router_10_19_rsp_out[2]; - assign router_10_19_to_router_9_19_rsp = router_10_19_rsp_out[3]; - assign router_10_19_to_magia_tile_ni_10_19_rsp = router_10_19_rsp_out[4]; - - assign router_10_19_to_router_10_20_req = router_10_19_req_out[0]; - assign router_10_19_to_router_11_19_req = router_10_19_req_out[1]; - assign router_10_19_to_router_10_18_req = router_10_19_req_out[2]; - assign router_10_19_to_router_9_19_req = router_10_19_req_out[3]; - assign router_10_19_to_magia_tile_ni_10_19_req = router_10_19_req_out[4]; - - assign router_10_19_rsp_in[0] = router_10_20_to_router_10_19_rsp; - assign router_10_19_rsp_in[1] = router_11_19_to_router_10_19_rsp; - assign router_10_19_rsp_in[2] = router_10_18_to_router_10_19_rsp; - assign router_10_19_rsp_in[3] = router_9_19_to_router_10_19_rsp; - assign router_10_19_rsp_in[4] = magia_tile_ni_10_19_to_router_10_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_19_req_in), - .floo_rsp_o (router_10_19_rsp_out), - .floo_req_o (router_10_19_req_out), - .floo_rsp_i (router_10_19_rsp_in) -); - - -floo_req_t [4:0] router_10_20_req_in; -floo_rsp_t [4:0] router_10_20_rsp_out; -floo_req_t [4:0] router_10_20_req_out; -floo_rsp_t [4:0] router_10_20_rsp_in; - - assign router_10_20_req_in[0] = router_10_21_to_router_10_20_req; - assign router_10_20_req_in[1] = router_11_20_to_router_10_20_req; - assign router_10_20_req_in[2] = router_10_19_to_router_10_20_req; - assign router_10_20_req_in[3] = router_9_20_to_router_10_20_req; - assign router_10_20_req_in[4] = magia_tile_ni_10_20_to_router_10_20_req; - - assign router_10_20_to_router_10_21_rsp = router_10_20_rsp_out[0]; - assign router_10_20_to_router_11_20_rsp = router_10_20_rsp_out[1]; - assign router_10_20_to_router_10_19_rsp = router_10_20_rsp_out[2]; - assign router_10_20_to_router_9_20_rsp = router_10_20_rsp_out[3]; - assign router_10_20_to_magia_tile_ni_10_20_rsp = router_10_20_rsp_out[4]; - - assign router_10_20_to_router_10_21_req = router_10_20_req_out[0]; - assign router_10_20_to_router_11_20_req = router_10_20_req_out[1]; - assign router_10_20_to_router_10_19_req = router_10_20_req_out[2]; - assign router_10_20_to_router_9_20_req = router_10_20_req_out[3]; - assign router_10_20_to_magia_tile_ni_10_20_req = router_10_20_req_out[4]; - - assign router_10_20_rsp_in[0] = router_10_21_to_router_10_20_rsp; - assign router_10_20_rsp_in[1] = router_11_20_to_router_10_20_rsp; - assign router_10_20_rsp_in[2] = router_10_19_to_router_10_20_rsp; - assign router_10_20_rsp_in[3] = router_9_20_to_router_10_20_rsp; - assign router_10_20_rsp_in[4] = magia_tile_ni_10_20_to_router_10_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_20_req_in), - .floo_rsp_o (router_10_20_rsp_out), - .floo_req_o (router_10_20_req_out), - .floo_rsp_i (router_10_20_rsp_in) -); - - -floo_req_t [4:0] router_10_21_req_in; -floo_rsp_t [4:0] router_10_21_rsp_out; -floo_req_t [4:0] router_10_21_req_out; -floo_rsp_t [4:0] router_10_21_rsp_in; - - assign router_10_21_req_in[0] = router_10_22_to_router_10_21_req; - assign router_10_21_req_in[1] = router_11_21_to_router_10_21_req; - assign router_10_21_req_in[2] = router_10_20_to_router_10_21_req; - assign router_10_21_req_in[3] = router_9_21_to_router_10_21_req; - assign router_10_21_req_in[4] = magia_tile_ni_10_21_to_router_10_21_req; - - assign router_10_21_to_router_10_22_rsp = router_10_21_rsp_out[0]; - assign router_10_21_to_router_11_21_rsp = router_10_21_rsp_out[1]; - assign router_10_21_to_router_10_20_rsp = router_10_21_rsp_out[2]; - assign router_10_21_to_router_9_21_rsp = router_10_21_rsp_out[3]; - assign router_10_21_to_magia_tile_ni_10_21_rsp = router_10_21_rsp_out[4]; - - assign router_10_21_to_router_10_22_req = router_10_21_req_out[0]; - assign router_10_21_to_router_11_21_req = router_10_21_req_out[1]; - assign router_10_21_to_router_10_20_req = router_10_21_req_out[2]; - assign router_10_21_to_router_9_21_req = router_10_21_req_out[3]; - assign router_10_21_to_magia_tile_ni_10_21_req = router_10_21_req_out[4]; - - assign router_10_21_rsp_in[0] = router_10_22_to_router_10_21_rsp; - assign router_10_21_rsp_in[1] = router_11_21_to_router_10_21_rsp; - assign router_10_21_rsp_in[2] = router_10_20_to_router_10_21_rsp; - assign router_10_21_rsp_in[3] = router_9_21_to_router_10_21_rsp; - assign router_10_21_rsp_in[4] = magia_tile_ni_10_21_to_router_10_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_21_req_in), - .floo_rsp_o (router_10_21_rsp_out), - .floo_req_o (router_10_21_req_out), - .floo_rsp_i (router_10_21_rsp_in) -); - - -floo_req_t [4:0] router_10_22_req_in; -floo_rsp_t [4:0] router_10_22_rsp_out; -floo_req_t [4:0] router_10_22_req_out; -floo_rsp_t [4:0] router_10_22_rsp_in; - - assign router_10_22_req_in[0] = router_10_23_to_router_10_22_req; - assign router_10_22_req_in[1] = router_11_22_to_router_10_22_req; - assign router_10_22_req_in[2] = router_10_21_to_router_10_22_req; - assign router_10_22_req_in[3] = router_9_22_to_router_10_22_req; - assign router_10_22_req_in[4] = magia_tile_ni_10_22_to_router_10_22_req; - - assign router_10_22_to_router_10_23_rsp = router_10_22_rsp_out[0]; - assign router_10_22_to_router_11_22_rsp = router_10_22_rsp_out[1]; - assign router_10_22_to_router_10_21_rsp = router_10_22_rsp_out[2]; - assign router_10_22_to_router_9_22_rsp = router_10_22_rsp_out[3]; - assign router_10_22_to_magia_tile_ni_10_22_rsp = router_10_22_rsp_out[4]; - - assign router_10_22_to_router_10_23_req = router_10_22_req_out[0]; - assign router_10_22_to_router_11_22_req = router_10_22_req_out[1]; - assign router_10_22_to_router_10_21_req = router_10_22_req_out[2]; - assign router_10_22_to_router_9_22_req = router_10_22_req_out[3]; - assign router_10_22_to_magia_tile_ni_10_22_req = router_10_22_req_out[4]; - - assign router_10_22_rsp_in[0] = router_10_23_to_router_10_22_rsp; - assign router_10_22_rsp_in[1] = router_11_22_to_router_10_22_rsp; - assign router_10_22_rsp_in[2] = router_10_21_to_router_10_22_rsp; - assign router_10_22_rsp_in[3] = router_9_22_to_router_10_22_rsp; - assign router_10_22_rsp_in[4] = magia_tile_ni_10_22_to_router_10_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_22_req_in), - .floo_rsp_o (router_10_22_rsp_out), - .floo_req_o (router_10_22_req_out), - .floo_rsp_i (router_10_22_rsp_in) -); - - -floo_req_t [4:0] router_10_23_req_in; -floo_rsp_t [4:0] router_10_23_rsp_out; -floo_req_t [4:0] router_10_23_req_out; -floo_rsp_t [4:0] router_10_23_rsp_in; - - assign router_10_23_req_in[0] = router_10_24_to_router_10_23_req; - assign router_10_23_req_in[1] = router_11_23_to_router_10_23_req; - assign router_10_23_req_in[2] = router_10_22_to_router_10_23_req; - assign router_10_23_req_in[3] = router_9_23_to_router_10_23_req; - assign router_10_23_req_in[4] = magia_tile_ni_10_23_to_router_10_23_req; - - assign router_10_23_to_router_10_24_rsp = router_10_23_rsp_out[0]; - assign router_10_23_to_router_11_23_rsp = router_10_23_rsp_out[1]; - assign router_10_23_to_router_10_22_rsp = router_10_23_rsp_out[2]; - assign router_10_23_to_router_9_23_rsp = router_10_23_rsp_out[3]; - assign router_10_23_to_magia_tile_ni_10_23_rsp = router_10_23_rsp_out[4]; - - assign router_10_23_to_router_10_24_req = router_10_23_req_out[0]; - assign router_10_23_to_router_11_23_req = router_10_23_req_out[1]; - assign router_10_23_to_router_10_22_req = router_10_23_req_out[2]; - assign router_10_23_to_router_9_23_req = router_10_23_req_out[3]; - assign router_10_23_to_magia_tile_ni_10_23_req = router_10_23_req_out[4]; - - assign router_10_23_rsp_in[0] = router_10_24_to_router_10_23_rsp; - assign router_10_23_rsp_in[1] = router_11_23_to_router_10_23_rsp; - assign router_10_23_rsp_in[2] = router_10_22_to_router_10_23_rsp; - assign router_10_23_rsp_in[3] = router_9_23_to_router_10_23_rsp; - assign router_10_23_rsp_in[4] = magia_tile_ni_10_23_to_router_10_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_23_req_in), - .floo_rsp_o (router_10_23_rsp_out), - .floo_req_o (router_10_23_req_out), - .floo_rsp_i (router_10_23_rsp_in) -); - - -floo_req_t [4:0] router_10_24_req_in; -floo_rsp_t [4:0] router_10_24_rsp_out; -floo_req_t [4:0] router_10_24_req_out; -floo_rsp_t [4:0] router_10_24_rsp_in; - - assign router_10_24_req_in[0] = router_10_25_to_router_10_24_req; - assign router_10_24_req_in[1] = router_11_24_to_router_10_24_req; - assign router_10_24_req_in[2] = router_10_23_to_router_10_24_req; - assign router_10_24_req_in[3] = router_9_24_to_router_10_24_req; - assign router_10_24_req_in[4] = magia_tile_ni_10_24_to_router_10_24_req; - - assign router_10_24_to_router_10_25_rsp = router_10_24_rsp_out[0]; - assign router_10_24_to_router_11_24_rsp = router_10_24_rsp_out[1]; - assign router_10_24_to_router_10_23_rsp = router_10_24_rsp_out[2]; - assign router_10_24_to_router_9_24_rsp = router_10_24_rsp_out[3]; - assign router_10_24_to_magia_tile_ni_10_24_rsp = router_10_24_rsp_out[4]; - - assign router_10_24_to_router_10_25_req = router_10_24_req_out[0]; - assign router_10_24_to_router_11_24_req = router_10_24_req_out[1]; - assign router_10_24_to_router_10_23_req = router_10_24_req_out[2]; - assign router_10_24_to_router_9_24_req = router_10_24_req_out[3]; - assign router_10_24_to_magia_tile_ni_10_24_req = router_10_24_req_out[4]; - - assign router_10_24_rsp_in[0] = router_10_25_to_router_10_24_rsp; - assign router_10_24_rsp_in[1] = router_11_24_to_router_10_24_rsp; - assign router_10_24_rsp_in[2] = router_10_23_to_router_10_24_rsp; - assign router_10_24_rsp_in[3] = router_9_24_to_router_10_24_rsp; - assign router_10_24_rsp_in[4] = magia_tile_ni_10_24_to_router_10_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_24_req_in), - .floo_rsp_o (router_10_24_rsp_out), - .floo_req_o (router_10_24_req_out), - .floo_rsp_i (router_10_24_rsp_in) -); - - -floo_req_t [4:0] router_10_25_req_in; -floo_rsp_t [4:0] router_10_25_rsp_out; -floo_req_t [4:0] router_10_25_req_out; -floo_rsp_t [4:0] router_10_25_rsp_in; - - assign router_10_25_req_in[0] = router_10_26_to_router_10_25_req; - assign router_10_25_req_in[1] = router_11_25_to_router_10_25_req; - assign router_10_25_req_in[2] = router_10_24_to_router_10_25_req; - assign router_10_25_req_in[3] = router_9_25_to_router_10_25_req; - assign router_10_25_req_in[4] = magia_tile_ni_10_25_to_router_10_25_req; - - assign router_10_25_to_router_10_26_rsp = router_10_25_rsp_out[0]; - assign router_10_25_to_router_11_25_rsp = router_10_25_rsp_out[1]; - assign router_10_25_to_router_10_24_rsp = router_10_25_rsp_out[2]; - assign router_10_25_to_router_9_25_rsp = router_10_25_rsp_out[3]; - assign router_10_25_to_magia_tile_ni_10_25_rsp = router_10_25_rsp_out[4]; - - assign router_10_25_to_router_10_26_req = router_10_25_req_out[0]; - assign router_10_25_to_router_11_25_req = router_10_25_req_out[1]; - assign router_10_25_to_router_10_24_req = router_10_25_req_out[2]; - assign router_10_25_to_router_9_25_req = router_10_25_req_out[3]; - assign router_10_25_to_magia_tile_ni_10_25_req = router_10_25_req_out[4]; - - assign router_10_25_rsp_in[0] = router_10_26_to_router_10_25_rsp; - assign router_10_25_rsp_in[1] = router_11_25_to_router_10_25_rsp; - assign router_10_25_rsp_in[2] = router_10_24_to_router_10_25_rsp; - assign router_10_25_rsp_in[3] = router_9_25_to_router_10_25_rsp; - assign router_10_25_rsp_in[4] = magia_tile_ni_10_25_to_router_10_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_25_req_in), - .floo_rsp_o (router_10_25_rsp_out), - .floo_req_o (router_10_25_req_out), - .floo_rsp_i (router_10_25_rsp_in) -); - - -floo_req_t [4:0] router_10_26_req_in; -floo_rsp_t [4:0] router_10_26_rsp_out; -floo_req_t [4:0] router_10_26_req_out; -floo_rsp_t [4:0] router_10_26_rsp_in; - - assign router_10_26_req_in[0] = router_10_27_to_router_10_26_req; - assign router_10_26_req_in[1] = router_11_26_to_router_10_26_req; - assign router_10_26_req_in[2] = router_10_25_to_router_10_26_req; - assign router_10_26_req_in[3] = router_9_26_to_router_10_26_req; - assign router_10_26_req_in[4] = magia_tile_ni_10_26_to_router_10_26_req; - - assign router_10_26_to_router_10_27_rsp = router_10_26_rsp_out[0]; - assign router_10_26_to_router_11_26_rsp = router_10_26_rsp_out[1]; - assign router_10_26_to_router_10_25_rsp = router_10_26_rsp_out[2]; - assign router_10_26_to_router_9_26_rsp = router_10_26_rsp_out[3]; - assign router_10_26_to_magia_tile_ni_10_26_rsp = router_10_26_rsp_out[4]; - - assign router_10_26_to_router_10_27_req = router_10_26_req_out[0]; - assign router_10_26_to_router_11_26_req = router_10_26_req_out[1]; - assign router_10_26_to_router_10_25_req = router_10_26_req_out[2]; - assign router_10_26_to_router_9_26_req = router_10_26_req_out[3]; - assign router_10_26_to_magia_tile_ni_10_26_req = router_10_26_req_out[4]; - - assign router_10_26_rsp_in[0] = router_10_27_to_router_10_26_rsp; - assign router_10_26_rsp_in[1] = router_11_26_to_router_10_26_rsp; - assign router_10_26_rsp_in[2] = router_10_25_to_router_10_26_rsp; - assign router_10_26_rsp_in[3] = router_9_26_to_router_10_26_rsp; - assign router_10_26_rsp_in[4] = magia_tile_ni_10_26_to_router_10_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_26_req_in), - .floo_rsp_o (router_10_26_rsp_out), - .floo_req_o (router_10_26_req_out), - .floo_rsp_i (router_10_26_rsp_in) -); - - -floo_req_t [4:0] router_10_27_req_in; -floo_rsp_t [4:0] router_10_27_rsp_out; -floo_req_t [4:0] router_10_27_req_out; -floo_rsp_t [4:0] router_10_27_rsp_in; - - assign router_10_27_req_in[0] = router_10_28_to_router_10_27_req; - assign router_10_27_req_in[1] = router_11_27_to_router_10_27_req; - assign router_10_27_req_in[2] = router_10_26_to_router_10_27_req; - assign router_10_27_req_in[3] = router_9_27_to_router_10_27_req; - assign router_10_27_req_in[4] = magia_tile_ni_10_27_to_router_10_27_req; - - assign router_10_27_to_router_10_28_rsp = router_10_27_rsp_out[0]; - assign router_10_27_to_router_11_27_rsp = router_10_27_rsp_out[1]; - assign router_10_27_to_router_10_26_rsp = router_10_27_rsp_out[2]; - assign router_10_27_to_router_9_27_rsp = router_10_27_rsp_out[3]; - assign router_10_27_to_magia_tile_ni_10_27_rsp = router_10_27_rsp_out[4]; - - assign router_10_27_to_router_10_28_req = router_10_27_req_out[0]; - assign router_10_27_to_router_11_27_req = router_10_27_req_out[1]; - assign router_10_27_to_router_10_26_req = router_10_27_req_out[2]; - assign router_10_27_to_router_9_27_req = router_10_27_req_out[3]; - assign router_10_27_to_magia_tile_ni_10_27_req = router_10_27_req_out[4]; - - assign router_10_27_rsp_in[0] = router_10_28_to_router_10_27_rsp; - assign router_10_27_rsp_in[1] = router_11_27_to_router_10_27_rsp; - assign router_10_27_rsp_in[2] = router_10_26_to_router_10_27_rsp; - assign router_10_27_rsp_in[3] = router_9_27_to_router_10_27_rsp; - assign router_10_27_rsp_in[4] = magia_tile_ni_10_27_to_router_10_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_27_req_in), - .floo_rsp_o (router_10_27_rsp_out), - .floo_req_o (router_10_27_req_out), - .floo_rsp_i (router_10_27_rsp_in) -); - - -floo_req_t [4:0] router_10_28_req_in; -floo_rsp_t [4:0] router_10_28_rsp_out; -floo_req_t [4:0] router_10_28_req_out; -floo_rsp_t [4:0] router_10_28_rsp_in; - - assign router_10_28_req_in[0] = router_10_29_to_router_10_28_req; - assign router_10_28_req_in[1] = router_11_28_to_router_10_28_req; - assign router_10_28_req_in[2] = router_10_27_to_router_10_28_req; - assign router_10_28_req_in[3] = router_9_28_to_router_10_28_req; - assign router_10_28_req_in[4] = magia_tile_ni_10_28_to_router_10_28_req; - - assign router_10_28_to_router_10_29_rsp = router_10_28_rsp_out[0]; - assign router_10_28_to_router_11_28_rsp = router_10_28_rsp_out[1]; - assign router_10_28_to_router_10_27_rsp = router_10_28_rsp_out[2]; - assign router_10_28_to_router_9_28_rsp = router_10_28_rsp_out[3]; - assign router_10_28_to_magia_tile_ni_10_28_rsp = router_10_28_rsp_out[4]; - - assign router_10_28_to_router_10_29_req = router_10_28_req_out[0]; - assign router_10_28_to_router_11_28_req = router_10_28_req_out[1]; - assign router_10_28_to_router_10_27_req = router_10_28_req_out[2]; - assign router_10_28_to_router_9_28_req = router_10_28_req_out[3]; - assign router_10_28_to_magia_tile_ni_10_28_req = router_10_28_req_out[4]; - - assign router_10_28_rsp_in[0] = router_10_29_to_router_10_28_rsp; - assign router_10_28_rsp_in[1] = router_11_28_to_router_10_28_rsp; - assign router_10_28_rsp_in[2] = router_10_27_to_router_10_28_rsp; - assign router_10_28_rsp_in[3] = router_9_28_to_router_10_28_rsp; - assign router_10_28_rsp_in[4] = magia_tile_ni_10_28_to_router_10_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_28_req_in), - .floo_rsp_o (router_10_28_rsp_out), - .floo_req_o (router_10_28_req_out), - .floo_rsp_i (router_10_28_rsp_in) -); - - -floo_req_t [4:0] router_10_29_req_in; -floo_rsp_t [4:0] router_10_29_rsp_out; -floo_req_t [4:0] router_10_29_req_out; -floo_rsp_t [4:0] router_10_29_rsp_in; - - assign router_10_29_req_in[0] = router_10_30_to_router_10_29_req; - assign router_10_29_req_in[1] = router_11_29_to_router_10_29_req; - assign router_10_29_req_in[2] = router_10_28_to_router_10_29_req; - assign router_10_29_req_in[3] = router_9_29_to_router_10_29_req; - assign router_10_29_req_in[4] = magia_tile_ni_10_29_to_router_10_29_req; - - assign router_10_29_to_router_10_30_rsp = router_10_29_rsp_out[0]; - assign router_10_29_to_router_11_29_rsp = router_10_29_rsp_out[1]; - assign router_10_29_to_router_10_28_rsp = router_10_29_rsp_out[2]; - assign router_10_29_to_router_9_29_rsp = router_10_29_rsp_out[3]; - assign router_10_29_to_magia_tile_ni_10_29_rsp = router_10_29_rsp_out[4]; - - assign router_10_29_to_router_10_30_req = router_10_29_req_out[0]; - assign router_10_29_to_router_11_29_req = router_10_29_req_out[1]; - assign router_10_29_to_router_10_28_req = router_10_29_req_out[2]; - assign router_10_29_to_router_9_29_req = router_10_29_req_out[3]; - assign router_10_29_to_magia_tile_ni_10_29_req = router_10_29_req_out[4]; - - assign router_10_29_rsp_in[0] = router_10_30_to_router_10_29_rsp; - assign router_10_29_rsp_in[1] = router_11_29_to_router_10_29_rsp; - assign router_10_29_rsp_in[2] = router_10_28_to_router_10_29_rsp; - assign router_10_29_rsp_in[3] = router_9_29_to_router_10_29_rsp; - assign router_10_29_rsp_in[4] = magia_tile_ni_10_29_to_router_10_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_29_req_in), - .floo_rsp_o (router_10_29_rsp_out), - .floo_req_o (router_10_29_req_out), - .floo_rsp_i (router_10_29_rsp_in) -); - - -floo_req_t [4:0] router_10_30_req_in; -floo_rsp_t [4:0] router_10_30_rsp_out; -floo_req_t [4:0] router_10_30_req_out; -floo_rsp_t [4:0] router_10_30_rsp_in; - - assign router_10_30_req_in[0] = router_10_31_to_router_10_30_req; - assign router_10_30_req_in[1] = router_11_30_to_router_10_30_req; - assign router_10_30_req_in[2] = router_10_29_to_router_10_30_req; - assign router_10_30_req_in[3] = router_9_30_to_router_10_30_req; - assign router_10_30_req_in[4] = magia_tile_ni_10_30_to_router_10_30_req; - - assign router_10_30_to_router_10_31_rsp = router_10_30_rsp_out[0]; - assign router_10_30_to_router_11_30_rsp = router_10_30_rsp_out[1]; - assign router_10_30_to_router_10_29_rsp = router_10_30_rsp_out[2]; - assign router_10_30_to_router_9_30_rsp = router_10_30_rsp_out[3]; - assign router_10_30_to_magia_tile_ni_10_30_rsp = router_10_30_rsp_out[4]; - - assign router_10_30_to_router_10_31_req = router_10_30_req_out[0]; - assign router_10_30_to_router_11_30_req = router_10_30_req_out[1]; - assign router_10_30_to_router_10_29_req = router_10_30_req_out[2]; - assign router_10_30_to_router_9_30_req = router_10_30_req_out[3]; - assign router_10_30_to_magia_tile_ni_10_30_req = router_10_30_req_out[4]; - - assign router_10_30_rsp_in[0] = router_10_31_to_router_10_30_rsp; - assign router_10_30_rsp_in[1] = router_11_30_to_router_10_30_rsp; - assign router_10_30_rsp_in[2] = router_10_29_to_router_10_30_rsp; - assign router_10_30_rsp_in[3] = router_9_30_to_router_10_30_rsp; - assign router_10_30_rsp_in[4] = magia_tile_ni_10_30_to_router_10_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_30_req_in), - .floo_rsp_o (router_10_30_rsp_out), - .floo_req_o (router_10_30_req_out), - .floo_rsp_i (router_10_30_rsp_in) -); - - -floo_req_t [4:0] router_10_31_req_in; -floo_rsp_t [4:0] router_10_31_rsp_out; -floo_req_t [4:0] router_10_31_req_out; -floo_rsp_t [4:0] router_10_31_rsp_in; - - assign router_10_31_req_in[0] = '0; - assign router_10_31_req_in[1] = router_11_31_to_router_10_31_req; - assign router_10_31_req_in[2] = router_10_30_to_router_10_31_req; - assign router_10_31_req_in[3] = router_9_31_to_router_10_31_req; - assign router_10_31_req_in[4] = magia_tile_ni_10_31_to_router_10_31_req; - - assign router_10_31_to_router_11_31_rsp = router_10_31_rsp_out[1]; - assign router_10_31_to_router_10_30_rsp = router_10_31_rsp_out[2]; - assign router_10_31_to_router_9_31_rsp = router_10_31_rsp_out[3]; - assign router_10_31_to_magia_tile_ni_10_31_rsp = router_10_31_rsp_out[4]; - - assign router_10_31_to_router_11_31_req = router_10_31_req_out[1]; - assign router_10_31_to_router_10_30_req = router_10_31_req_out[2]; - assign router_10_31_to_router_9_31_req = router_10_31_req_out[3]; - assign router_10_31_to_magia_tile_ni_10_31_req = router_10_31_req_out[4]; - - assign router_10_31_rsp_in[0] = '0; - assign router_10_31_rsp_in[1] = router_11_31_to_router_10_31_rsp; - assign router_10_31_rsp_in[2] = router_10_30_to_router_10_31_rsp; - assign router_10_31_rsp_in[3] = router_9_31_to_router_10_31_rsp; - assign router_10_31_rsp_in[4] = magia_tile_ni_10_31_to_router_10_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_10_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 11, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_10_31_req_in), - .floo_rsp_o (router_10_31_rsp_out), - .floo_req_o (router_10_31_req_out), - .floo_rsp_i (router_10_31_rsp_in) -); - - -floo_req_t [4:0] router_11_0_req_in; -floo_rsp_t [4:0] router_11_0_rsp_out; -floo_req_t [4:0] router_11_0_req_out; -floo_rsp_t [4:0] router_11_0_rsp_in; - - assign router_11_0_req_in[0] = router_11_1_to_router_11_0_req; - assign router_11_0_req_in[1] = router_12_0_to_router_11_0_req; - assign router_11_0_req_in[2] = '0; - assign router_11_0_req_in[3] = router_10_0_to_router_11_0_req; - assign router_11_0_req_in[4] = magia_tile_ni_11_0_to_router_11_0_req; - - assign router_11_0_to_router_11_1_rsp = router_11_0_rsp_out[0]; - assign router_11_0_to_router_12_0_rsp = router_11_0_rsp_out[1]; - assign router_11_0_to_router_10_0_rsp = router_11_0_rsp_out[3]; - assign router_11_0_to_magia_tile_ni_11_0_rsp = router_11_0_rsp_out[4]; - - assign router_11_0_to_router_11_1_req = router_11_0_req_out[0]; - assign router_11_0_to_router_12_0_req = router_11_0_req_out[1]; - assign router_11_0_to_router_10_0_req = router_11_0_req_out[3]; - assign router_11_0_to_magia_tile_ni_11_0_req = router_11_0_req_out[4]; - - assign router_11_0_rsp_in[0] = router_11_1_to_router_11_0_rsp; - assign router_11_0_rsp_in[1] = router_12_0_to_router_11_0_rsp; - assign router_11_0_rsp_in[2] = '0; - assign router_11_0_rsp_in[3] = router_10_0_to_router_11_0_rsp; - assign router_11_0_rsp_in[4] = magia_tile_ni_11_0_to_router_11_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_0_req_in), - .floo_rsp_o (router_11_0_rsp_out), - .floo_req_o (router_11_0_req_out), - .floo_rsp_i (router_11_0_rsp_in) -); - - -floo_req_t [4:0] router_11_1_req_in; -floo_rsp_t [4:0] router_11_1_rsp_out; -floo_req_t [4:0] router_11_1_req_out; -floo_rsp_t [4:0] router_11_1_rsp_in; - - assign router_11_1_req_in[0] = router_11_2_to_router_11_1_req; - assign router_11_1_req_in[1] = router_12_1_to_router_11_1_req; - assign router_11_1_req_in[2] = router_11_0_to_router_11_1_req; - assign router_11_1_req_in[3] = router_10_1_to_router_11_1_req; - assign router_11_1_req_in[4] = magia_tile_ni_11_1_to_router_11_1_req; - - assign router_11_1_to_router_11_2_rsp = router_11_1_rsp_out[0]; - assign router_11_1_to_router_12_1_rsp = router_11_1_rsp_out[1]; - assign router_11_1_to_router_11_0_rsp = router_11_1_rsp_out[2]; - assign router_11_1_to_router_10_1_rsp = router_11_1_rsp_out[3]; - assign router_11_1_to_magia_tile_ni_11_1_rsp = router_11_1_rsp_out[4]; - - assign router_11_1_to_router_11_2_req = router_11_1_req_out[0]; - assign router_11_1_to_router_12_1_req = router_11_1_req_out[1]; - assign router_11_1_to_router_11_0_req = router_11_1_req_out[2]; - assign router_11_1_to_router_10_1_req = router_11_1_req_out[3]; - assign router_11_1_to_magia_tile_ni_11_1_req = router_11_1_req_out[4]; - - assign router_11_1_rsp_in[0] = router_11_2_to_router_11_1_rsp; - assign router_11_1_rsp_in[1] = router_12_1_to_router_11_1_rsp; - assign router_11_1_rsp_in[2] = router_11_0_to_router_11_1_rsp; - assign router_11_1_rsp_in[3] = router_10_1_to_router_11_1_rsp; - assign router_11_1_rsp_in[4] = magia_tile_ni_11_1_to_router_11_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_1_req_in), - .floo_rsp_o (router_11_1_rsp_out), - .floo_req_o (router_11_1_req_out), - .floo_rsp_i (router_11_1_rsp_in) -); - - -floo_req_t [4:0] router_11_2_req_in; -floo_rsp_t [4:0] router_11_2_rsp_out; -floo_req_t [4:0] router_11_2_req_out; -floo_rsp_t [4:0] router_11_2_rsp_in; - - assign router_11_2_req_in[0] = router_11_3_to_router_11_2_req; - assign router_11_2_req_in[1] = router_12_2_to_router_11_2_req; - assign router_11_2_req_in[2] = router_11_1_to_router_11_2_req; - assign router_11_2_req_in[3] = router_10_2_to_router_11_2_req; - assign router_11_2_req_in[4] = magia_tile_ni_11_2_to_router_11_2_req; - - assign router_11_2_to_router_11_3_rsp = router_11_2_rsp_out[0]; - assign router_11_2_to_router_12_2_rsp = router_11_2_rsp_out[1]; - assign router_11_2_to_router_11_1_rsp = router_11_2_rsp_out[2]; - assign router_11_2_to_router_10_2_rsp = router_11_2_rsp_out[3]; - assign router_11_2_to_magia_tile_ni_11_2_rsp = router_11_2_rsp_out[4]; - - assign router_11_2_to_router_11_3_req = router_11_2_req_out[0]; - assign router_11_2_to_router_12_2_req = router_11_2_req_out[1]; - assign router_11_2_to_router_11_1_req = router_11_2_req_out[2]; - assign router_11_2_to_router_10_2_req = router_11_2_req_out[3]; - assign router_11_2_to_magia_tile_ni_11_2_req = router_11_2_req_out[4]; - - assign router_11_2_rsp_in[0] = router_11_3_to_router_11_2_rsp; - assign router_11_2_rsp_in[1] = router_12_2_to_router_11_2_rsp; - assign router_11_2_rsp_in[2] = router_11_1_to_router_11_2_rsp; - assign router_11_2_rsp_in[3] = router_10_2_to_router_11_2_rsp; - assign router_11_2_rsp_in[4] = magia_tile_ni_11_2_to_router_11_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_2_req_in), - .floo_rsp_o (router_11_2_rsp_out), - .floo_req_o (router_11_2_req_out), - .floo_rsp_i (router_11_2_rsp_in) -); - - -floo_req_t [4:0] router_11_3_req_in; -floo_rsp_t [4:0] router_11_3_rsp_out; -floo_req_t [4:0] router_11_3_req_out; -floo_rsp_t [4:0] router_11_3_rsp_in; - - assign router_11_3_req_in[0] = router_11_4_to_router_11_3_req; - assign router_11_3_req_in[1] = router_12_3_to_router_11_3_req; - assign router_11_3_req_in[2] = router_11_2_to_router_11_3_req; - assign router_11_3_req_in[3] = router_10_3_to_router_11_3_req; - assign router_11_3_req_in[4] = magia_tile_ni_11_3_to_router_11_3_req; - - assign router_11_3_to_router_11_4_rsp = router_11_3_rsp_out[0]; - assign router_11_3_to_router_12_3_rsp = router_11_3_rsp_out[1]; - assign router_11_3_to_router_11_2_rsp = router_11_3_rsp_out[2]; - assign router_11_3_to_router_10_3_rsp = router_11_3_rsp_out[3]; - assign router_11_3_to_magia_tile_ni_11_3_rsp = router_11_3_rsp_out[4]; - - assign router_11_3_to_router_11_4_req = router_11_3_req_out[0]; - assign router_11_3_to_router_12_3_req = router_11_3_req_out[1]; - assign router_11_3_to_router_11_2_req = router_11_3_req_out[2]; - assign router_11_3_to_router_10_3_req = router_11_3_req_out[3]; - assign router_11_3_to_magia_tile_ni_11_3_req = router_11_3_req_out[4]; - - assign router_11_3_rsp_in[0] = router_11_4_to_router_11_3_rsp; - assign router_11_3_rsp_in[1] = router_12_3_to_router_11_3_rsp; - assign router_11_3_rsp_in[2] = router_11_2_to_router_11_3_rsp; - assign router_11_3_rsp_in[3] = router_10_3_to_router_11_3_rsp; - assign router_11_3_rsp_in[4] = magia_tile_ni_11_3_to_router_11_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_3_req_in), - .floo_rsp_o (router_11_3_rsp_out), - .floo_req_o (router_11_3_req_out), - .floo_rsp_i (router_11_3_rsp_in) -); - - -floo_req_t [4:0] router_11_4_req_in; -floo_rsp_t [4:0] router_11_4_rsp_out; -floo_req_t [4:0] router_11_4_req_out; -floo_rsp_t [4:0] router_11_4_rsp_in; - - assign router_11_4_req_in[0] = router_11_5_to_router_11_4_req; - assign router_11_4_req_in[1] = router_12_4_to_router_11_4_req; - assign router_11_4_req_in[2] = router_11_3_to_router_11_4_req; - assign router_11_4_req_in[3] = router_10_4_to_router_11_4_req; - assign router_11_4_req_in[4] = magia_tile_ni_11_4_to_router_11_4_req; - - assign router_11_4_to_router_11_5_rsp = router_11_4_rsp_out[0]; - assign router_11_4_to_router_12_4_rsp = router_11_4_rsp_out[1]; - assign router_11_4_to_router_11_3_rsp = router_11_4_rsp_out[2]; - assign router_11_4_to_router_10_4_rsp = router_11_4_rsp_out[3]; - assign router_11_4_to_magia_tile_ni_11_4_rsp = router_11_4_rsp_out[4]; - - assign router_11_4_to_router_11_5_req = router_11_4_req_out[0]; - assign router_11_4_to_router_12_4_req = router_11_4_req_out[1]; - assign router_11_4_to_router_11_3_req = router_11_4_req_out[2]; - assign router_11_4_to_router_10_4_req = router_11_4_req_out[3]; - assign router_11_4_to_magia_tile_ni_11_4_req = router_11_4_req_out[4]; - - assign router_11_4_rsp_in[0] = router_11_5_to_router_11_4_rsp; - assign router_11_4_rsp_in[1] = router_12_4_to_router_11_4_rsp; - assign router_11_4_rsp_in[2] = router_11_3_to_router_11_4_rsp; - assign router_11_4_rsp_in[3] = router_10_4_to_router_11_4_rsp; - assign router_11_4_rsp_in[4] = magia_tile_ni_11_4_to_router_11_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_4_req_in), - .floo_rsp_o (router_11_4_rsp_out), - .floo_req_o (router_11_4_req_out), - .floo_rsp_i (router_11_4_rsp_in) -); - - -floo_req_t [4:0] router_11_5_req_in; -floo_rsp_t [4:0] router_11_5_rsp_out; -floo_req_t [4:0] router_11_5_req_out; -floo_rsp_t [4:0] router_11_5_rsp_in; - - assign router_11_5_req_in[0] = router_11_6_to_router_11_5_req; - assign router_11_5_req_in[1] = router_12_5_to_router_11_5_req; - assign router_11_5_req_in[2] = router_11_4_to_router_11_5_req; - assign router_11_5_req_in[3] = router_10_5_to_router_11_5_req; - assign router_11_5_req_in[4] = magia_tile_ni_11_5_to_router_11_5_req; - - assign router_11_5_to_router_11_6_rsp = router_11_5_rsp_out[0]; - assign router_11_5_to_router_12_5_rsp = router_11_5_rsp_out[1]; - assign router_11_5_to_router_11_4_rsp = router_11_5_rsp_out[2]; - assign router_11_5_to_router_10_5_rsp = router_11_5_rsp_out[3]; - assign router_11_5_to_magia_tile_ni_11_5_rsp = router_11_5_rsp_out[4]; - - assign router_11_5_to_router_11_6_req = router_11_5_req_out[0]; - assign router_11_5_to_router_12_5_req = router_11_5_req_out[1]; - assign router_11_5_to_router_11_4_req = router_11_5_req_out[2]; - assign router_11_5_to_router_10_5_req = router_11_5_req_out[3]; - assign router_11_5_to_magia_tile_ni_11_5_req = router_11_5_req_out[4]; - - assign router_11_5_rsp_in[0] = router_11_6_to_router_11_5_rsp; - assign router_11_5_rsp_in[1] = router_12_5_to_router_11_5_rsp; - assign router_11_5_rsp_in[2] = router_11_4_to_router_11_5_rsp; - assign router_11_5_rsp_in[3] = router_10_5_to_router_11_5_rsp; - assign router_11_5_rsp_in[4] = magia_tile_ni_11_5_to_router_11_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_5_req_in), - .floo_rsp_o (router_11_5_rsp_out), - .floo_req_o (router_11_5_req_out), - .floo_rsp_i (router_11_5_rsp_in) -); - - -floo_req_t [4:0] router_11_6_req_in; -floo_rsp_t [4:0] router_11_6_rsp_out; -floo_req_t [4:0] router_11_6_req_out; -floo_rsp_t [4:0] router_11_6_rsp_in; - - assign router_11_6_req_in[0] = router_11_7_to_router_11_6_req; - assign router_11_6_req_in[1] = router_12_6_to_router_11_6_req; - assign router_11_6_req_in[2] = router_11_5_to_router_11_6_req; - assign router_11_6_req_in[3] = router_10_6_to_router_11_6_req; - assign router_11_6_req_in[4] = magia_tile_ni_11_6_to_router_11_6_req; - - assign router_11_6_to_router_11_7_rsp = router_11_6_rsp_out[0]; - assign router_11_6_to_router_12_6_rsp = router_11_6_rsp_out[1]; - assign router_11_6_to_router_11_5_rsp = router_11_6_rsp_out[2]; - assign router_11_6_to_router_10_6_rsp = router_11_6_rsp_out[3]; - assign router_11_6_to_magia_tile_ni_11_6_rsp = router_11_6_rsp_out[4]; - - assign router_11_6_to_router_11_7_req = router_11_6_req_out[0]; - assign router_11_6_to_router_12_6_req = router_11_6_req_out[1]; - assign router_11_6_to_router_11_5_req = router_11_6_req_out[2]; - assign router_11_6_to_router_10_6_req = router_11_6_req_out[3]; - assign router_11_6_to_magia_tile_ni_11_6_req = router_11_6_req_out[4]; - - assign router_11_6_rsp_in[0] = router_11_7_to_router_11_6_rsp; - assign router_11_6_rsp_in[1] = router_12_6_to_router_11_6_rsp; - assign router_11_6_rsp_in[2] = router_11_5_to_router_11_6_rsp; - assign router_11_6_rsp_in[3] = router_10_6_to_router_11_6_rsp; - assign router_11_6_rsp_in[4] = magia_tile_ni_11_6_to_router_11_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_6_req_in), - .floo_rsp_o (router_11_6_rsp_out), - .floo_req_o (router_11_6_req_out), - .floo_rsp_i (router_11_6_rsp_in) -); - - -floo_req_t [4:0] router_11_7_req_in; -floo_rsp_t [4:0] router_11_7_rsp_out; -floo_req_t [4:0] router_11_7_req_out; -floo_rsp_t [4:0] router_11_7_rsp_in; - - assign router_11_7_req_in[0] = router_11_8_to_router_11_7_req; - assign router_11_7_req_in[1] = router_12_7_to_router_11_7_req; - assign router_11_7_req_in[2] = router_11_6_to_router_11_7_req; - assign router_11_7_req_in[3] = router_10_7_to_router_11_7_req; - assign router_11_7_req_in[4] = magia_tile_ni_11_7_to_router_11_7_req; - - assign router_11_7_to_router_11_8_rsp = router_11_7_rsp_out[0]; - assign router_11_7_to_router_12_7_rsp = router_11_7_rsp_out[1]; - assign router_11_7_to_router_11_6_rsp = router_11_7_rsp_out[2]; - assign router_11_7_to_router_10_7_rsp = router_11_7_rsp_out[3]; - assign router_11_7_to_magia_tile_ni_11_7_rsp = router_11_7_rsp_out[4]; - - assign router_11_7_to_router_11_8_req = router_11_7_req_out[0]; - assign router_11_7_to_router_12_7_req = router_11_7_req_out[1]; - assign router_11_7_to_router_11_6_req = router_11_7_req_out[2]; - assign router_11_7_to_router_10_7_req = router_11_7_req_out[3]; - assign router_11_7_to_magia_tile_ni_11_7_req = router_11_7_req_out[4]; - - assign router_11_7_rsp_in[0] = router_11_8_to_router_11_7_rsp; - assign router_11_7_rsp_in[1] = router_12_7_to_router_11_7_rsp; - assign router_11_7_rsp_in[2] = router_11_6_to_router_11_7_rsp; - assign router_11_7_rsp_in[3] = router_10_7_to_router_11_7_rsp; - assign router_11_7_rsp_in[4] = magia_tile_ni_11_7_to_router_11_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_7_req_in), - .floo_rsp_o (router_11_7_rsp_out), - .floo_req_o (router_11_7_req_out), - .floo_rsp_i (router_11_7_rsp_in) -); - - -floo_req_t [4:0] router_11_8_req_in; -floo_rsp_t [4:0] router_11_8_rsp_out; -floo_req_t [4:0] router_11_8_req_out; -floo_rsp_t [4:0] router_11_8_rsp_in; - - assign router_11_8_req_in[0] = router_11_9_to_router_11_8_req; - assign router_11_8_req_in[1] = router_12_8_to_router_11_8_req; - assign router_11_8_req_in[2] = router_11_7_to_router_11_8_req; - assign router_11_8_req_in[3] = router_10_8_to_router_11_8_req; - assign router_11_8_req_in[4] = magia_tile_ni_11_8_to_router_11_8_req; - - assign router_11_8_to_router_11_9_rsp = router_11_8_rsp_out[0]; - assign router_11_8_to_router_12_8_rsp = router_11_8_rsp_out[1]; - assign router_11_8_to_router_11_7_rsp = router_11_8_rsp_out[2]; - assign router_11_8_to_router_10_8_rsp = router_11_8_rsp_out[3]; - assign router_11_8_to_magia_tile_ni_11_8_rsp = router_11_8_rsp_out[4]; - - assign router_11_8_to_router_11_9_req = router_11_8_req_out[0]; - assign router_11_8_to_router_12_8_req = router_11_8_req_out[1]; - assign router_11_8_to_router_11_7_req = router_11_8_req_out[2]; - assign router_11_8_to_router_10_8_req = router_11_8_req_out[3]; - assign router_11_8_to_magia_tile_ni_11_8_req = router_11_8_req_out[4]; - - assign router_11_8_rsp_in[0] = router_11_9_to_router_11_8_rsp; - assign router_11_8_rsp_in[1] = router_12_8_to_router_11_8_rsp; - assign router_11_8_rsp_in[2] = router_11_7_to_router_11_8_rsp; - assign router_11_8_rsp_in[3] = router_10_8_to_router_11_8_rsp; - assign router_11_8_rsp_in[4] = magia_tile_ni_11_8_to_router_11_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_8_req_in), - .floo_rsp_o (router_11_8_rsp_out), - .floo_req_o (router_11_8_req_out), - .floo_rsp_i (router_11_8_rsp_in) -); - - -floo_req_t [4:0] router_11_9_req_in; -floo_rsp_t [4:0] router_11_9_rsp_out; -floo_req_t [4:0] router_11_9_req_out; -floo_rsp_t [4:0] router_11_9_rsp_in; - - assign router_11_9_req_in[0] = router_11_10_to_router_11_9_req; - assign router_11_9_req_in[1] = router_12_9_to_router_11_9_req; - assign router_11_9_req_in[2] = router_11_8_to_router_11_9_req; - assign router_11_9_req_in[3] = router_10_9_to_router_11_9_req; - assign router_11_9_req_in[4] = magia_tile_ni_11_9_to_router_11_9_req; - - assign router_11_9_to_router_11_10_rsp = router_11_9_rsp_out[0]; - assign router_11_9_to_router_12_9_rsp = router_11_9_rsp_out[1]; - assign router_11_9_to_router_11_8_rsp = router_11_9_rsp_out[2]; - assign router_11_9_to_router_10_9_rsp = router_11_9_rsp_out[3]; - assign router_11_9_to_magia_tile_ni_11_9_rsp = router_11_9_rsp_out[4]; - - assign router_11_9_to_router_11_10_req = router_11_9_req_out[0]; - assign router_11_9_to_router_12_9_req = router_11_9_req_out[1]; - assign router_11_9_to_router_11_8_req = router_11_9_req_out[2]; - assign router_11_9_to_router_10_9_req = router_11_9_req_out[3]; - assign router_11_9_to_magia_tile_ni_11_9_req = router_11_9_req_out[4]; - - assign router_11_9_rsp_in[0] = router_11_10_to_router_11_9_rsp; - assign router_11_9_rsp_in[1] = router_12_9_to_router_11_9_rsp; - assign router_11_9_rsp_in[2] = router_11_8_to_router_11_9_rsp; - assign router_11_9_rsp_in[3] = router_10_9_to_router_11_9_rsp; - assign router_11_9_rsp_in[4] = magia_tile_ni_11_9_to_router_11_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_9_req_in), - .floo_rsp_o (router_11_9_rsp_out), - .floo_req_o (router_11_9_req_out), - .floo_rsp_i (router_11_9_rsp_in) -); - - -floo_req_t [4:0] router_11_10_req_in; -floo_rsp_t [4:0] router_11_10_rsp_out; -floo_req_t [4:0] router_11_10_req_out; -floo_rsp_t [4:0] router_11_10_rsp_in; - - assign router_11_10_req_in[0] = router_11_11_to_router_11_10_req; - assign router_11_10_req_in[1] = router_12_10_to_router_11_10_req; - assign router_11_10_req_in[2] = router_11_9_to_router_11_10_req; - assign router_11_10_req_in[3] = router_10_10_to_router_11_10_req; - assign router_11_10_req_in[4] = magia_tile_ni_11_10_to_router_11_10_req; - - assign router_11_10_to_router_11_11_rsp = router_11_10_rsp_out[0]; - assign router_11_10_to_router_12_10_rsp = router_11_10_rsp_out[1]; - assign router_11_10_to_router_11_9_rsp = router_11_10_rsp_out[2]; - assign router_11_10_to_router_10_10_rsp = router_11_10_rsp_out[3]; - assign router_11_10_to_magia_tile_ni_11_10_rsp = router_11_10_rsp_out[4]; - - assign router_11_10_to_router_11_11_req = router_11_10_req_out[0]; - assign router_11_10_to_router_12_10_req = router_11_10_req_out[1]; - assign router_11_10_to_router_11_9_req = router_11_10_req_out[2]; - assign router_11_10_to_router_10_10_req = router_11_10_req_out[3]; - assign router_11_10_to_magia_tile_ni_11_10_req = router_11_10_req_out[4]; - - assign router_11_10_rsp_in[0] = router_11_11_to_router_11_10_rsp; - assign router_11_10_rsp_in[1] = router_12_10_to_router_11_10_rsp; - assign router_11_10_rsp_in[2] = router_11_9_to_router_11_10_rsp; - assign router_11_10_rsp_in[3] = router_10_10_to_router_11_10_rsp; - assign router_11_10_rsp_in[4] = magia_tile_ni_11_10_to_router_11_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_10_req_in), - .floo_rsp_o (router_11_10_rsp_out), - .floo_req_o (router_11_10_req_out), - .floo_rsp_i (router_11_10_rsp_in) -); - - -floo_req_t [4:0] router_11_11_req_in; -floo_rsp_t [4:0] router_11_11_rsp_out; -floo_req_t [4:0] router_11_11_req_out; -floo_rsp_t [4:0] router_11_11_rsp_in; - - assign router_11_11_req_in[0] = router_11_12_to_router_11_11_req; - assign router_11_11_req_in[1] = router_12_11_to_router_11_11_req; - assign router_11_11_req_in[2] = router_11_10_to_router_11_11_req; - assign router_11_11_req_in[3] = router_10_11_to_router_11_11_req; - assign router_11_11_req_in[4] = magia_tile_ni_11_11_to_router_11_11_req; - - assign router_11_11_to_router_11_12_rsp = router_11_11_rsp_out[0]; - assign router_11_11_to_router_12_11_rsp = router_11_11_rsp_out[1]; - assign router_11_11_to_router_11_10_rsp = router_11_11_rsp_out[2]; - assign router_11_11_to_router_10_11_rsp = router_11_11_rsp_out[3]; - assign router_11_11_to_magia_tile_ni_11_11_rsp = router_11_11_rsp_out[4]; - - assign router_11_11_to_router_11_12_req = router_11_11_req_out[0]; - assign router_11_11_to_router_12_11_req = router_11_11_req_out[1]; - assign router_11_11_to_router_11_10_req = router_11_11_req_out[2]; - assign router_11_11_to_router_10_11_req = router_11_11_req_out[3]; - assign router_11_11_to_magia_tile_ni_11_11_req = router_11_11_req_out[4]; - - assign router_11_11_rsp_in[0] = router_11_12_to_router_11_11_rsp; - assign router_11_11_rsp_in[1] = router_12_11_to_router_11_11_rsp; - assign router_11_11_rsp_in[2] = router_11_10_to_router_11_11_rsp; - assign router_11_11_rsp_in[3] = router_10_11_to_router_11_11_rsp; - assign router_11_11_rsp_in[4] = magia_tile_ni_11_11_to_router_11_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_11_req_in), - .floo_rsp_o (router_11_11_rsp_out), - .floo_req_o (router_11_11_req_out), - .floo_rsp_i (router_11_11_rsp_in) -); - - -floo_req_t [4:0] router_11_12_req_in; -floo_rsp_t [4:0] router_11_12_rsp_out; -floo_req_t [4:0] router_11_12_req_out; -floo_rsp_t [4:0] router_11_12_rsp_in; - - assign router_11_12_req_in[0] = router_11_13_to_router_11_12_req; - assign router_11_12_req_in[1] = router_12_12_to_router_11_12_req; - assign router_11_12_req_in[2] = router_11_11_to_router_11_12_req; - assign router_11_12_req_in[3] = router_10_12_to_router_11_12_req; - assign router_11_12_req_in[4] = magia_tile_ni_11_12_to_router_11_12_req; - - assign router_11_12_to_router_11_13_rsp = router_11_12_rsp_out[0]; - assign router_11_12_to_router_12_12_rsp = router_11_12_rsp_out[1]; - assign router_11_12_to_router_11_11_rsp = router_11_12_rsp_out[2]; - assign router_11_12_to_router_10_12_rsp = router_11_12_rsp_out[3]; - assign router_11_12_to_magia_tile_ni_11_12_rsp = router_11_12_rsp_out[4]; - - assign router_11_12_to_router_11_13_req = router_11_12_req_out[0]; - assign router_11_12_to_router_12_12_req = router_11_12_req_out[1]; - assign router_11_12_to_router_11_11_req = router_11_12_req_out[2]; - assign router_11_12_to_router_10_12_req = router_11_12_req_out[3]; - assign router_11_12_to_magia_tile_ni_11_12_req = router_11_12_req_out[4]; - - assign router_11_12_rsp_in[0] = router_11_13_to_router_11_12_rsp; - assign router_11_12_rsp_in[1] = router_12_12_to_router_11_12_rsp; - assign router_11_12_rsp_in[2] = router_11_11_to_router_11_12_rsp; - assign router_11_12_rsp_in[3] = router_10_12_to_router_11_12_rsp; - assign router_11_12_rsp_in[4] = magia_tile_ni_11_12_to_router_11_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_12_req_in), - .floo_rsp_o (router_11_12_rsp_out), - .floo_req_o (router_11_12_req_out), - .floo_rsp_i (router_11_12_rsp_in) -); - - -floo_req_t [4:0] router_11_13_req_in; -floo_rsp_t [4:0] router_11_13_rsp_out; -floo_req_t [4:0] router_11_13_req_out; -floo_rsp_t [4:0] router_11_13_rsp_in; - - assign router_11_13_req_in[0] = router_11_14_to_router_11_13_req; - assign router_11_13_req_in[1] = router_12_13_to_router_11_13_req; - assign router_11_13_req_in[2] = router_11_12_to_router_11_13_req; - assign router_11_13_req_in[3] = router_10_13_to_router_11_13_req; - assign router_11_13_req_in[4] = magia_tile_ni_11_13_to_router_11_13_req; - - assign router_11_13_to_router_11_14_rsp = router_11_13_rsp_out[0]; - assign router_11_13_to_router_12_13_rsp = router_11_13_rsp_out[1]; - assign router_11_13_to_router_11_12_rsp = router_11_13_rsp_out[2]; - assign router_11_13_to_router_10_13_rsp = router_11_13_rsp_out[3]; - assign router_11_13_to_magia_tile_ni_11_13_rsp = router_11_13_rsp_out[4]; - - assign router_11_13_to_router_11_14_req = router_11_13_req_out[0]; - assign router_11_13_to_router_12_13_req = router_11_13_req_out[1]; - assign router_11_13_to_router_11_12_req = router_11_13_req_out[2]; - assign router_11_13_to_router_10_13_req = router_11_13_req_out[3]; - assign router_11_13_to_magia_tile_ni_11_13_req = router_11_13_req_out[4]; - - assign router_11_13_rsp_in[0] = router_11_14_to_router_11_13_rsp; - assign router_11_13_rsp_in[1] = router_12_13_to_router_11_13_rsp; - assign router_11_13_rsp_in[2] = router_11_12_to_router_11_13_rsp; - assign router_11_13_rsp_in[3] = router_10_13_to_router_11_13_rsp; - assign router_11_13_rsp_in[4] = magia_tile_ni_11_13_to_router_11_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_13_req_in), - .floo_rsp_o (router_11_13_rsp_out), - .floo_req_o (router_11_13_req_out), - .floo_rsp_i (router_11_13_rsp_in) -); - - -floo_req_t [4:0] router_11_14_req_in; -floo_rsp_t [4:0] router_11_14_rsp_out; -floo_req_t [4:0] router_11_14_req_out; -floo_rsp_t [4:0] router_11_14_rsp_in; - - assign router_11_14_req_in[0] = router_11_15_to_router_11_14_req; - assign router_11_14_req_in[1] = router_12_14_to_router_11_14_req; - assign router_11_14_req_in[2] = router_11_13_to_router_11_14_req; - assign router_11_14_req_in[3] = router_10_14_to_router_11_14_req; - assign router_11_14_req_in[4] = magia_tile_ni_11_14_to_router_11_14_req; - - assign router_11_14_to_router_11_15_rsp = router_11_14_rsp_out[0]; - assign router_11_14_to_router_12_14_rsp = router_11_14_rsp_out[1]; - assign router_11_14_to_router_11_13_rsp = router_11_14_rsp_out[2]; - assign router_11_14_to_router_10_14_rsp = router_11_14_rsp_out[3]; - assign router_11_14_to_magia_tile_ni_11_14_rsp = router_11_14_rsp_out[4]; - - assign router_11_14_to_router_11_15_req = router_11_14_req_out[0]; - assign router_11_14_to_router_12_14_req = router_11_14_req_out[1]; - assign router_11_14_to_router_11_13_req = router_11_14_req_out[2]; - assign router_11_14_to_router_10_14_req = router_11_14_req_out[3]; - assign router_11_14_to_magia_tile_ni_11_14_req = router_11_14_req_out[4]; - - assign router_11_14_rsp_in[0] = router_11_15_to_router_11_14_rsp; - assign router_11_14_rsp_in[1] = router_12_14_to_router_11_14_rsp; - assign router_11_14_rsp_in[2] = router_11_13_to_router_11_14_rsp; - assign router_11_14_rsp_in[3] = router_10_14_to_router_11_14_rsp; - assign router_11_14_rsp_in[4] = magia_tile_ni_11_14_to_router_11_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_14_req_in), - .floo_rsp_o (router_11_14_rsp_out), - .floo_req_o (router_11_14_req_out), - .floo_rsp_i (router_11_14_rsp_in) -); - - -floo_req_t [4:0] router_11_15_req_in; -floo_rsp_t [4:0] router_11_15_rsp_out; -floo_req_t [4:0] router_11_15_req_out; -floo_rsp_t [4:0] router_11_15_rsp_in; - - assign router_11_15_req_in[0] = router_11_16_to_router_11_15_req; - assign router_11_15_req_in[1] = router_12_15_to_router_11_15_req; - assign router_11_15_req_in[2] = router_11_14_to_router_11_15_req; - assign router_11_15_req_in[3] = router_10_15_to_router_11_15_req; - assign router_11_15_req_in[4] = magia_tile_ni_11_15_to_router_11_15_req; - - assign router_11_15_to_router_11_16_rsp = router_11_15_rsp_out[0]; - assign router_11_15_to_router_12_15_rsp = router_11_15_rsp_out[1]; - assign router_11_15_to_router_11_14_rsp = router_11_15_rsp_out[2]; - assign router_11_15_to_router_10_15_rsp = router_11_15_rsp_out[3]; - assign router_11_15_to_magia_tile_ni_11_15_rsp = router_11_15_rsp_out[4]; - - assign router_11_15_to_router_11_16_req = router_11_15_req_out[0]; - assign router_11_15_to_router_12_15_req = router_11_15_req_out[1]; - assign router_11_15_to_router_11_14_req = router_11_15_req_out[2]; - assign router_11_15_to_router_10_15_req = router_11_15_req_out[3]; - assign router_11_15_to_magia_tile_ni_11_15_req = router_11_15_req_out[4]; - - assign router_11_15_rsp_in[0] = router_11_16_to_router_11_15_rsp; - assign router_11_15_rsp_in[1] = router_12_15_to_router_11_15_rsp; - assign router_11_15_rsp_in[2] = router_11_14_to_router_11_15_rsp; - assign router_11_15_rsp_in[3] = router_10_15_to_router_11_15_rsp; - assign router_11_15_rsp_in[4] = magia_tile_ni_11_15_to_router_11_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_15_req_in), - .floo_rsp_o (router_11_15_rsp_out), - .floo_req_o (router_11_15_req_out), - .floo_rsp_i (router_11_15_rsp_in) -); - - -floo_req_t [4:0] router_11_16_req_in; -floo_rsp_t [4:0] router_11_16_rsp_out; -floo_req_t [4:0] router_11_16_req_out; -floo_rsp_t [4:0] router_11_16_rsp_in; - - assign router_11_16_req_in[0] = router_11_17_to_router_11_16_req; - assign router_11_16_req_in[1] = router_12_16_to_router_11_16_req; - assign router_11_16_req_in[2] = router_11_15_to_router_11_16_req; - assign router_11_16_req_in[3] = router_10_16_to_router_11_16_req; - assign router_11_16_req_in[4] = magia_tile_ni_11_16_to_router_11_16_req; - - assign router_11_16_to_router_11_17_rsp = router_11_16_rsp_out[0]; - assign router_11_16_to_router_12_16_rsp = router_11_16_rsp_out[1]; - assign router_11_16_to_router_11_15_rsp = router_11_16_rsp_out[2]; - assign router_11_16_to_router_10_16_rsp = router_11_16_rsp_out[3]; - assign router_11_16_to_magia_tile_ni_11_16_rsp = router_11_16_rsp_out[4]; - - assign router_11_16_to_router_11_17_req = router_11_16_req_out[0]; - assign router_11_16_to_router_12_16_req = router_11_16_req_out[1]; - assign router_11_16_to_router_11_15_req = router_11_16_req_out[2]; - assign router_11_16_to_router_10_16_req = router_11_16_req_out[3]; - assign router_11_16_to_magia_tile_ni_11_16_req = router_11_16_req_out[4]; - - assign router_11_16_rsp_in[0] = router_11_17_to_router_11_16_rsp; - assign router_11_16_rsp_in[1] = router_12_16_to_router_11_16_rsp; - assign router_11_16_rsp_in[2] = router_11_15_to_router_11_16_rsp; - assign router_11_16_rsp_in[3] = router_10_16_to_router_11_16_rsp; - assign router_11_16_rsp_in[4] = magia_tile_ni_11_16_to_router_11_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_16_req_in), - .floo_rsp_o (router_11_16_rsp_out), - .floo_req_o (router_11_16_req_out), - .floo_rsp_i (router_11_16_rsp_in) -); - - -floo_req_t [4:0] router_11_17_req_in; -floo_rsp_t [4:0] router_11_17_rsp_out; -floo_req_t [4:0] router_11_17_req_out; -floo_rsp_t [4:0] router_11_17_rsp_in; - - assign router_11_17_req_in[0] = router_11_18_to_router_11_17_req; - assign router_11_17_req_in[1] = router_12_17_to_router_11_17_req; - assign router_11_17_req_in[2] = router_11_16_to_router_11_17_req; - assign router_11_17_req_in[3] = router_10_17_to_router_11_17_req; - assign router_11_17_req_in[4] = magia_tile_ni_11_17_to_router_11_17_req; - - assign router_11_17_to_router_11_18_rsp = router_11_17_rsp_out[0]; - assign router_11_17_to_router_12_17_rsp = router_11_17_rsp_out[1]; - assign router_11_17_to_router_11_16_rsp = router_11_17_rsp_out[2]; - assign router_11_17_to_router_10_17_rsp = router_11_17_rsp_out[3]; - assign router_11_17_to_magia_tile_ni_11_17_rsp = router_11_17_rsp_out[4]; - - assign router_11_17_to_router_11_18_req = router_11_17_req_out[0]; - assign router_11_17_to_router_12_17_req = router_11_17_req_out[1]; - assign router_11_17_to_router_11_16_req = router_11_17_req_out[2]; - assign router_11_17_to_router_10_17_req = router_11_17_req_out[3]; - assign router_11_17_to_magia_tile_ni_11_17_req = router_11_17_req_out[4]; - - assign router_11_17_rsp_in[0] = router_11_18_to_router_11_17_rsp; - assign router_11_17_rsp_in[1] = router_12_17_to_router_11_17_rsp; - assign router_11_17_rsp_in[2] = router_11_16_to_router_11_17_rsp; - assign router_11_17_rsp_in[3] = router_10_17_to_router_11_17_rsp; - assign router_11_17_rsp_in[4] = magia_tile_ni_11_17_to_router_11_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_17_req_in), - .floo_rsp_o (router_11_17_rsp_out), - .floo_req_o (router_11_17_req_out), - .floo_rsp_i (router_11_17_rsp_in) -); - - -floo_req_t [4:0] router_11_18_req_in; -floo_rsp_t [4:0] router_11_18_rsp_out; -floo_req_t [4:0] router_11_18_req_out; -floo_rsp_t [4:0] router_11_18_rsp_in; - - assign router_11_18_req_in[0] = router_11_19_to_router_11_18_req; - assign router_11_18_req_in[1] = router_12_18_to_router_11_18_req; - assign router_11_18_req_in[2] = router_11_17_to_router_11_18_req; - assign router_11_18_req_in[3] = router_10_18_to_router_11_18_req; - assign router_11_18_req_in[4] = magia_tile_ni_11_18_to_router_11_18_req; - - assign router_11_18_to_router_11_19_rsp = router_11_18_rsp_out[0]; - assign router_11_18_to_router_12_18_rsp = router_11_18_rsp_out[1]; - assign router_11_18_to_router_11_17_rsp = router_11_18_rsp_out[2]; - assign router_11_18_to_router_10_18_rsp = router_11_18_rsp_out[3]; - assign router_11_18_to_magia_tile_ni_11_18_rsp = router_11_18_rsp_out[4]; - - assign router_11_18_to_router_11_19_req = router_11_18_req_out[0]; - assign router_11_18_to_router_12_18_req = router_11_18_req_out[1]; - assign router_11_18_to_router_11_17_req = router_11_18_req_out[2]; - assign router_11_18_to_router_10_18_req = router_11_18_req_out[3]; - assign router_11_18_to_magia_tile_ni_11_18_req = router_11_18_req_out[4]; - - assign router_11_18_rsp_in[0] = router_11_19_to_router_11_18_rsp; - assign router_11_18_rsp_in[1] = router_12_18_to_router_11_18_rsp; - assign router_11_18_rsp_in[2] = router_11_17_to_router_11_18_rsp; - assign router_11_18_rsp_in[3] = router_10_18_to_router_11_18_rsp; - assign router_11_18_rsp_in[4] = magia_tile_ni_11_18_to_router_11_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_18_req_in), - .floo_rsp_o (router_11_18_rsp_out), - .floo_req_o (router_11_18_req_out), - .floo_rsp_i (router_11_18_rsp_in) -); - - -floo_req_t [4:0] router_11_19_req_in; -floo_rsp_t [4:0] router_11_19_rsp_out; -floo_req_t [4:0] router_11_19_req_out; -floo_rsp_t [4:0] router_11_19_rsp_in; - - assign router_11_19_req_in[0] = router_11_20_to_router_11_19_req; - assign router_11_19_req_in[1] = router_12_19_to_router_11_19_req; - assign router_11_19_req_in[2] = router_11_18_to_router_11_19_req; - assign router_11_19_req_in[3] = router_10_19_to_router_11_19_req; - assign router_11_19_req_in[4] = magia_tile_ni_11_19_to_router_11_19_req; - - assign router_11_19_to_router_11_20_rsp = router_11_19_rsp_out[0]; - assign router_11_19_to_router_12_19_rsp = router_11_19_rsp_out[1]; - assign router_11_19_to_router_11_18_rsp = router_11_19_rsp_out[2]; - assign router_11_19_to_router_10_19_rsp = router_11_19_rsp_out[3]; - assign router_11_19_to_magia_tile_ni_11_19_rsp = router_11_19_rsp_out[4]; - - assign router_11_19_to_router_11_20_req = router_11_19_req_out[0]; - assign router_11_19_to_router_12_19_req = router_11_19_req_out[1]; - assign router_11_19_to_router_11_18_req = router_11_19_req_out[2]; - assign router_11_19_to_router_10_19_req = router_11_19_req_out[3]; - assign router_11_19_to_magia_tile_ni_11_19_req = router_11_19_req_out[4]; - - assign router_11_19_rsp_in[0] = router_11_20_to_router_11_19_rsp; - assign router_11_19_rsp_in[1] = router_12_19_to_router_11_19_rsp; - assign router_11_19_rsp_in[2] = router_11_18_to_router_11_19_rsp; - assign router_11_19_rsp_in[3] = router_10_19_to_router_11_19_rsp; - assign router_11_19_rsp_in[4] = magia_tile_ni_11_19_to_router_11_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_19_req_in), - .floo_rsp_o (router_11_19_rsp_out), - .floo_req_o (router_11_19_req_out), - .floo_rsp_i (router_11_19_rsp_in) -); - - -floo_req_t [4:0] router_11_20_req_in; -floo_rsp_t [4:0] router_11_20_rsp_out; -floo_req_t [4:0] router_11_20_req_out; -floo_rsp_t [4:0] router_11_20_rsp_in; - - assign router_11_20_req_in[0] = router_11_21_to_router_11_20_req; - assign router_11_20_req_in[1] = router_12_20_to_router_11_20_req; - assign router_11_20_req_in[2] = router_11_19_to_router_11_20_req; - assign router_11_20_req_in[3] = router_10_20_to_router_11_20_req; - assign router_11_20_req_in[4] = magia_tile_ni_11_20_to_router_11_20_req; - - assign router_11_20_to_router_11_21_rsp = router_11_20_rsp_out[0]; - assign router_11_20_to_router_12_20_rsp = router_11_20_rsp_out[1]; - assign router_11_20_to_router_11_19_rsp = router_11_20_rsp_out[2]; - assign router_11_20_to_router_10_20_rsp = router_11_20_rsp_out[3]; - assign router_11_20_to_magia_tile_ni_11_20_rsp = router_11_20_rsp_out[4]; - - assign router_11_20_to_router_11_21_req = router_11_20_req_out[0]; - assign router_11_20_to_router_12_20_req = router_11_20_req_out[1]; - assign router_11_20_to_router_11_19_req = router_11_20_req_out[2]; - assign router_11_20_to_router_10_20_req = router_11_20_req_out[3]; - assign router_11_20_to_magia_tile_ni_11_20_req = router_11_20_req_out[4]; - - assign router_11_20_rsp_in[0] = router_11_21_to_router_11_20_rsp; - assign router_11_20_rsp_in[1] = router_12_20_to_router_11_20_rsp; - assign router_11_20_rsp_in[2] = router_11_19_to_router_11_20_rsp; - assign router_11_20_rsp_in[3] = router_10_20_to_router_11_20_rsp; - assign router_11_20_rsp_in[4] = magia_tile_ni_11_20_to_router_11_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_20_req_in), - .floo_rsp_o (router_11_20_rsp_out), - .floo_req_o (router_11_20_req_out), - .floo_rsp_i (router_11_20_rsp_in) -); - - -floo_req_t [4:0] router_11_21_req_in; -floo_rsp_t [4:0] router_11_21_rsp_out; -floo_req_t [4:0] router_11_21_req_out; -floo_rsp_t [4:0] router_11_21_rsp_in; - - assign router_11_21_req_in[0] = router_11_22_to_router_11_21_req; - assign router_11_21_req_in[1] = router_12_21_to_router_11_21_req; - assign router_11_21_req_in[2] = router_11_20_to_router_11_21_req; - assign router_11_21_req_in[3] = router_10_21_to_router_11_21_req; - assign router_11_21_req_in[4] = magia_tile_ni_11_21_to_router_11_21_req; - - assign router_11_21_to_router_11_22_rsp = router_11_21_rsp_out[0]; - assign router_11_21_to_router_12_21_rsp = router_11_21_rsp_out[1]; - assign router_11_21_to_router_11_20_rsp = router_11_21_rsp_out[2]; - assign router_11_21_to_router_10_21_rsp = router_11_21_rsp_out[3]; - assign router_11_21_to_magia_tile_ni_11_21_rsp = router_11_21_rsp_out[4]; - - assign router_11_21_to_router_11_22_req = router_11_21_req_out[0]; - assign router_11_21_to_router_12_21_req = router_11_21_req_out[1]; - assign router_11_21_to_router_11_20_req = router_11_21_req_out[2]; - assign router_11_21_to_router_10_21_req = router_11_21_req_out[3]; - assign router_11_21_to_magia_tile_ni_11_21_req = router_11_21_req_out[4]; - - assign router_11_21_rsp_in[0] = router_11_22_to_router_11_21_rsp; - assign router_11_21_rsp_in[1] = router_12_21_to_router_11_21_rsp; - assign router_11_21_rsp_in[2] = router_11_20_to_router_11_21_rsp; - assign router_11_21_rsp_in[3] = router_10_21_to_router_11_21_rsp; - assign router_11_21_rsp_in[4] = magia_tile_ni_11_21_to_router_11_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_21_req_in), - .floo_rsp_o (router_11_21_rsp_out), - .floo_req_o (router_11_21_req_out), - .floo_rsp_i (router_11_21_rsp_in) -); - - -floo_req_t [4:0] router_11_22_req_in; -floo_rsp_t [4:0] router_11_22_rsp_out; -floo_req_t [4:0] router_11_22_req_out; -floo_rsp_t [4:0] router_11_22_rsp_in; - - assign router_11_22_req_in[0] = router_11_23_to_router_11_22_req; - assign router_11_22_req_in[1] = router_12_22_to_router_11_22_req; - assign router_11_22_req_in[2] = router_11_21_to_router_11_22_req; - assign router_11_22_req_in[3] = router_10_22_to_router_11_22_req; - assign router_11_22_req_in[4] = magia_tile_ni_11_22_to_router_11_22_req; - - assign router_11_22_to_router_11_23_rsp = router_11_22_rsp_out[0]; - assign router_11_22_to_router_12_22_rsp = router_11_22_rsp_out[1]; - assign router_11_22_to_router_11_21_rsp = router_11_22_rsp_out[2]; - assign router_11_22_to_router_10_22_rsp = router_11_22_rsp_out[3]; - assign router_11_22_to_magia_tile_ni_11_22_rsp = router_11_22_rsp_out[4]; - - assign router_11_22_to_router_11_23_req = router_11_22_req_out[0]; - assign router_11_22_to_router_12_22_req = router_11_22_req_out[1]; - assign router_11_22_to_router_11_21_req = router_11_22_req_out[2]; - assign router_11_22_to_router_10_22_req = router_11_22_req_out[3]; - assign router_11_22_to_magia_tile_ni_11_22_req = router_11_22_req_out[4]; - - assign router_11_22_rsp_in[0] = router_11_23_to_router_11_22_rsp; - assign router_11_22_rsp_in[1] = router_12_22_to_router_11_22_rsp; - assign router_11_22_rsp_in[2] = router_11_21_to_router_11_22_rsp; - assign router_11_22_rsp_in[3] = router_10_22_to_router_11_22_rsp; - assign router_11_22_rsp_in[4] = magia_tile_ni_11_22_to_router_11_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_22_req_in), - .floo_rsp_o (router_11_22_rsp_out), - .floo_req_o (router_11_22_req_out), - .floo_rsp_i (router_11_22_rsp_in) -); - - -floo_req_t [4:0] router_11_23_req_in; -floo_rsp_t [4:0] router_11_23_rsp_out; -floo_req_t [4:0] router_11_23_req_out; -floo_rsp_t [4:0] router_11_23_rsp_in; - - assign router_11_23_req_in[0] = router_11_24_to_router_11_23_req; - assign router_11_23_req_in[1] = router_12_23_to_router_11_23_req; - assign router_11_23_req_in[2] = router_11_22_to_router_11_23_req; - assign router_11_23_req_in[3] = router_10_23_to_router_11_23_req; - assign router_11_23_req_in[4] = magia_tile_ni_11_23_to_router_11_23_req; - - assign router_11_23_to_router_11_24_rsp = router_11_23_rsp_out[0]; - assign router_11_23_to_router_12_23_rsp = router_11_23_rsp_out[1]; - assign router_11_23_to_router_11_22_rsp = router_11_23_rsp_out[2]; - assign router_11_23_to_router_10_23_rsp = router_11_23_rsp_out[3]; - assign router_11_23_to_magia_tile_ni_11_23_rsp = router_11_23_rsp_out[4]; - - assign router_11_23_to_router_11_24_req = router_11_23_req_out[0]; - assign router_11_23_to_router_12_23_req = router_11_23_req_out[1]; - assign router_11_23_to_router_11_22_req = router_11_23_req_out[2]; - assign router_11_23_to_router_10_23_req = router_11_23_req_out[3]; - assign router_11_23_to_magia_tile_ni_11_23_req = router_11_23_req_out[4]; - - assign router_11_23_rsp_in[0] = router_11_24_to_router_11_23_rsp; - assign router_11_23_rsp_in[1] = router_12_23_to_router_11_23_rsp; - assign router_11_23_rsp_in[2] = router_11_22_to_router_11_23_rsp; - assign router_11_23_rsp_in[3] = router_10_23_to_router_11_23_rsp; - assign router_11_23_rsp_in[4] = magia_tile_ni_11_23_to_router_11_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_23_req_in), - .floo_rsp_o (router_11_23_rsp_out), - .floo_req_o (router_11_23_req_out), - .floo_rsp_i (router_11_23_rsp_in) -); - - -floo_req_t [4:0] router_11_24_req_in; -floo_rsp_t [4:0] router_11_24_rsp_out; -floo_req_t [4:0] router_11_24_req_out; -floo_rsp_t [4:0] router_11_24_rsp_in; - - assign router_11_24_req_in[0] = router_11_25_to_router_11_24_req; - assign router_11_24_req_in[1] = router_12_24_to_router_11_24_req; - assign router_11_24_req_in[2] = router_11_23_to_router_11_24_req; - assign router_11_24_req_in[3] = router_10_24_to_router_11_24_req; - assign router_11_24_req_in[4] = magia_tile_ni_11_24_to_router_11_24_req; - - assign router_11_24_to_router_11_25_rsp = router_11_24_rsp_out[0]; - assign router_11_24_to_router_12_24_rsp = router_11_24_rsp_out[1]; - assign router_11_24_to_router_11_23_rsp = router_11_24_rsp_out[2]; - assign router_11_24_to_router_10_24_rsp = router_11_24_rsp_out[3]; - assign router_11_24_to_magia_tile_ni_11_24_rsp = router_11_24_rsp_out[4]; - - assign router_11_24_to_router_11_25_req = router_11_24_req_out[0]; - assign router_11_24_to_router_12_24_req = router_11_24_req_out[1]; - assign router_11_24_to_router_11_23_req = router_11_24_req_out[2]; - assign router_11_24_to_router_10_24_req = router_11_24_req_out[3]; - assign router_11_24_to_magia_tile_ni_11_24_req = router_11_24_req_out[4]; - - assign router_11_24_rsp_in[0] = router_11_25_to_router_11_24_rsp; - assign router_11_24_rsp_in[1] = router_12_24_to_router_11_24_rsp; - assign router_11_24_rsp_in[2] = router_11_23_to_router_11_24_rsp; - assign router_11_24_rsp_in[3] = router_10_24_to_router_11_24_rsp; - assign router_11_24_rsp_in[4] = magia_tile_ni_11_24_to_router_11_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_24_req_in), - .floo_rsp_o (router_11_24_rsp_out), - .floo_req_o (router_11_24_req_out), - .floo_rsp_i (router_11_24_rsp_in) -); - - -floo_req_t [4:0] router_11_25_req_in; -floo_rsp_t [4:0] router_11_25_rsp_out; -floo_req_t [4:0] router_11_25_req_out; -floo_rsp_t [4:0] router_11_25_rsp_in; - - assign router_11_25_req_in[0] = router_11_26_to_router_11_25_req; - assign router_11_25_req_in[1] = router_12_25_to_router_11_25_req; - assign router_11_25_req_in[2] = router_11_24_to_router_11_25_req; - assign router_11_25_req_in[3] = router_10_25_to_router_11_25_req; - assign router_11_25_req_in[4] = magia_tile_ni_11_25_to_router_11_25_req; - - assign router_11_25_to_router_11_26_rsp = router_11_25_rsp_out[0]; - assign router_11_25_to_router_12_25_rsp = router_11_25_rsp_out[1]; - assign router_11_25_to_router_11_24_rsp = router_11_25_rsp_out[2]; - assign router_11_25_to_router_10_25_rsp = router_11_25_rsp_out[3]; - assign router_11_25_to_magia_tile_ni_11_25_rsp = router_11_25_rsp_out[4]; - - assign router_11_25_to_router_11_26_req = router_11_25_req_out[0]; - assign router_11_25_to_router_12_25_req = router_11_25_req_out[1]; - assign router_11_25_to_router_11_24_req = router_11_25_req_out[2]; - assign router_11_25_to_router_10_25_req = router_11_25_req_out[3]; - assign router_11_25_to_magia_tile_ni_11_25_req = router_11_25_req_out[4]; - - assign router_11_25_rsp_in[0] = router_11_26_to_router_11_25_rsp; - assign router_11_25_rsp_in[1] = router_12_25_to_router_11_25_rsp; - assign router_11_25_rsp_in[2] = router_11_24_to_router_11_25_rsp; - assign router_11_25_rsp_in[3] = router_10_25_to_router_11_25_rsp; - assign router_11_25_rsp_in[4] = magia_tile_ni_11_25_to_router_11_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_25_req_in), - .floo_rsp_o (router_11_25_rsp_out), - .floo_req_o (router_11_25_req_out), - .floo_rsp_i (router_11_25_rsp_in) -); - - -floo_req_t [4:0] router_11_26_req_in; -floo_rsp_t [4:0] router_11_26_rsp_out; -floo_req_t [4:0] router_11_26_req_out; -floo_rsp_t [4:0] router_11_26_rsp_in; - - assign router_11_26_req_in[0] = router_11_27_to_router_11_26_req; - assign router_11_26_req_in[1] = router_12_26_to_router_11_26_req; - assign router_11_26_req_in[2] = router_11_25_to_router_11_26_req; - assign router_11_26_req_in[3] = router_10_26_to_router_11_26_req; - assign router_11_26_req_in[4] = magia_tile_ni_11_26_to_router_11_26_req; - - assign router_11_26_to_router_11_27_rsp = router_11_26_rsp_out[0]; - assign router_11_26_to_router_12_26_rsp = router_11_26_rsp_out[1]; - assign router_11_26_to_router_11_25_rsp = router_11_26_rsp_out[2]; - assign router_11_26_to_router_10_26_rsp = router_11_26_rsp_out[3]; - assign router_11_26_to_magia_tile_ni_11_26_rsp = router_11_26_rsp_out[4]; - - assign router_11_26_to_router_11_27_req = router_11_26_req_out[0]; - assign router_11_26_to_router_12_26_req = router_11_26_req_out[1]; - assign router_11_26_to_router_11_25_req = router_11_26_req_out[2]; - assign router_11_26_to_router_10_26_req = router_11_26_req_out[3]; - assign router_11_26_to_magia_tile_ni_11_26_req = router_11_26_req_out[4]; - - assign router_11_26_rsp_in[0] = router_11_27_to_router_11_26_rsp; - assign router_11_26_rsp_in[1] = router_12_26_to_router_11_26_rsp; - assign router_11_26_rsp_in[2] = router_11_25_to_router_11_26_rsp; - assign router_11_26_rsp_in[3] = router_10_26_to_router_11_26_rsp; - assign router_11_26_rsp_in[4] = magia_tile_ni_11_26_to_router_11_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_26_req_in), - .floo_rsp_o (router_11_26_rsp_out), - .floo_req_o (router_11_26_req_out), - .floo_rsp_i (router_11_26_rsp_in) -); - - -floo_req_t [4:0] router_11_27_req_in; -floo_rsp_t [4:0] router_11_27_rsp_out; -floo_req_t [4:0] router_11_27_req_out; -floo_rsp_t [4:0] router_11_27_rsp_in; - - assign router_11_27_req_in[0] = router_11_28_to_router_11_27_req; - assign router_11_27_req_in[1] = router_12_27_to_router_11_27_req; - assign router_11_27_req_in[2] = router_11_26_to_router_11_27_req; - assign router_11_27_req_in[3] = router_10_27_to_router_11_27_req; - assign router_11_27_req_in[4] = magia_tile_ni_11_27_to_router_11_27_req; - - assign router_11_27_to_router_11_28_rsp = router_11_27_rsp_out[0]; - assign router_11_27_to_router_12_27_rsp = router_11_27_rsp_out[1]; - assign router_11_27_to_router_11_26_rsp = router_11_27_rsp_out[2]; - assign router_11_27_to_router_10_27_rsp = router_11_27_rsp_out[3]; - assign router_11_27_to_magia_tile_ni_11_27_rsp = router_11_27_rsp_out[4]; - - assign router_11_27_to_router_11_28_req = router_11_27_req_out[0]; - assign router_11_27_to_router_12_27_req = router_11_27_req_out[1]; - assign router_11_27_to_router_11_26_req = router_11_27_req_out[2]; - assign router_11_27_to_router_10_27_req = router_11_27_req_out[3]; - assign router_11_27_to_magia_tile_ni_11_27_req = router_11_27_req_out[4]; - - assign router_11_27_rsp_in[0] = router_11_28_to_router_11_27_rsp; - assign router_11_27_rsp_in[1] = router_12_27_to_router_11_27_rsp; - assign router_11_27_rsp_in[2] = router_11_26_to_router_11_27_rsp; - assign router_11_27_rsp_in[3] = router_10_27_to_router_11_27_rsp; - assign router_11_27_rsp_in[4] = magia_tile_ni_11_27_to_router_11_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_27_req_in), - .floo_rsp_o (router_11_27_rsp_out), - .floo_req_o (router_11_27_req_out), - .floo_rsp_i (router_11_27_rsp_in) -); - - -floo_req_t [4:0] router_11_28_req_in; -floo_rsp_t [4:0] router_11_28_rsp_out; -floo_req_t [4:0] router_11_28_req_out; -floo_rsp_t [4:0] router_11_28_rsp_in; - - assign router_11_28_req_in[0] = router_11_29_to_router_11_28_req; - assign router_11_28_req_in[1] = router_12_28_to_router_11_28_req; - assign router_11_28_req_in[2] = router_11_27_to_router_11_28_req; - assign router_11_28_req_in[3] = router_10_28_to_router_11_28_req; - assign router_11_28_req_in[4] = magia_tile_ni_11_28_to_router_11_28_req; - - assign router_11_28_to_router_11_29_rsp = router_11_28_rsp_out[0]; - assign router_11_28_to_router_12_28_rsp = router_11_28_rsp_out[1]; - assign router_11_28_to_router_11_27_rsp = router_11_28_rsp_out[2]; - assign router_11_28_to_router_10_28_rsp = router_11_28_rsp_out[3]; - assign router_11_28_to_magia_tile_ni_11_28_rsp = router_11_28_rsp_out[4]; - - assign router_11_28_to_router_11_29_req = router_11_28_req_out[0]; - assign router_11_28_to_router_12_28_req = router_11_28_req_out[1]; - assign router_11_28_to_router_11_27_req = router_11_28_req_out[2]; - assign router_11_28_to_router_10_28_req = router_11_28_req_out[3]; - assign router_11_28_to_magia_tile_ni_11_28_req = router_11_28_req_out[4]; - - assign router_11_28_rsp_in[0] = router_11_29_to_router_11_28_rsp; - assign router_11_28_rsp_in[1] = router_12_28_to_router_11_28_rsp; - assign router_11_28_rsp_in[2] = router_11_27_to_router_11_28_rsp; - assign router_11_28_rsp_in[3] = router_10_28_to_router_11_28_rsp; - assign router_11_28_rsp_in[4] = magia_tile_ni_11_28_to_router_11_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_28_req_in), - .floo_rsp_o (router_11_28_rsp_out), - .floo_req_o (router_11_28_req_out), - .floo_rsp_i (router_11_28_rsp_in) -); - - -floo_req_t [4:0] router_11_29_req_in; -floo_rsp_t [4:0] router_11_29_rsp_out; -floo_req_t [4:0] router_11_29_req_out; -floo_rsp_t [4:0] router_11_29_rsp_in; - - assign router_11_29_req_in[0] = router_11_30_to_router_11_29_req; - assign router_11_29_req_in[1] = router_12_29_to_router_11_29_req; - assign router_11_29_req_in[2] = router_11_28_to_router_11_29_req; - assign router_11_29_req_in[3] = router_10_29_to_router_11_29_req; - assign router_11_29_req_in[4] = magia_tile_ni_11_29_to_router_11_29_req; - - assign router_11_29_to_router_11_30_rsp = router_11_29_rsp_out[0]; - assign router_11_29_to_router_12_29_rsp = router_11_29_rsp_out[1]; - assign router_11_29_to_router_11_28_rsp = router_11_29_rsp_out[2]; - assign router_11_29_to_router_10_29_rsp = router_11_29_rsp_out[3]; - assign router_11_29_to_magia_tile_ni_11_29_rsp = router_11_29_rsp_out[4]; - - assign router_11_29_to_router_11_30_req = router_11_29_req_out[0]; - assign router_11_29_to_router_12_29_req = router_11_29_req_out[1]; - assign router_11_29_to_router_11_28_req = router_11_29_req_out[2]; - assign router_11_29_to_router_10_29_req = router_11_29_req_out[3]; - assign router_11_29_to_magia_tile_ni_11_29_req = router_11_29_req_out[4]; - - assign router_11_29_rsp_in[0] = router_11_30_to_router_11_29_rsp; - assign router_11_29_rsp_in[1] = router_12_29_to_router_11_29_rsp; - assign router_11_29_rsp_in[2] = router_11_28_to_router_11_29_rsp; - assign router_11_29_rsp_in[3] = router_10_29_to_router_11_29_rsp; - assign router_11_29_rsp_in[4] = magia_tile_ni_11_29_to_router_11_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_29_req_in), - .floo_rsp_o (router_11_29_rsp_out), - .floo_req_o (router_11_29_req_out), - .floo_rsp_i (router_11_29_rsp_in) -); - - -floo_req_t [4:0] router_11_30_req_in; -floo_rsp_t [4:0] router_11_30_rsp_out; -floo_req_t [4:0] router_11_30_req_out; -floo_rsp_t [4:0] router_11_30_rsp_in; - - assign router_11_30_req_in[0] = router_11_31_to_router_11_30_req; - assign router_11_30_req_in[1] = router_12_30_to_router_11_30_req; - assign router_11_30_req_in[2] = router_11_29_to_router_11_30_req; - assign router_11_30_req_in[3] = router_10_30_to_router_11_30_req; - assign router_11_30_req_in[4] = magia_tile_ni_11_30_to_router_11_30_req; - - assign router_11_30_to_router_11_31_rsp = router_11_30_rsp_out[0]; - assign router_11_30_to_router_12_30_rsp = router_11_30_rsp_out[1]; - assign router_11_30_to_router_11_29_rsp = router_11_30_rsp_out[2]; - assign router_11_30_to_router_10_30_rsp = router_11_30_rsp_out[3]; - assign router_11_30_to_magia_tile_ni_11_30_rsp = router_11_30_rsp_out[4]; - - assign router_11_30_to_router_11_31_req = router_11_30_req_out[0]; - assign router_11_30_to_router_12_30_req = router_11_30_req_out[1]; - assign router_11_30_to_router_11_29_req = router_11_30_req_out[2]; - assign router_11_30_to_router_10_30_req = router_11_30_req_out[3]; - assign router_11_30_to_magia_tile_ni_11_30_req = router_11_30_req_out[4]; - - assign router_11_30_rsp_in[0] = router_11_31_to_router_11_30_rsp; - assign router_11_30_rsp_in[1] = router_12_30_to_router_11_30_rsp; - assign router_11_30_rsp_in[2] = router_11_29_to_router_11_30_rsp; - assign router_11_30_rsp_in[3] = router_10_30_to_router_11_30_rsp; - assign router_11_30_rsp_in[4] = magia_tile_ni_11_30_to_router_11_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_30_req_in), - .floo_rsp_o (router_11_30_rsp_out), - .floo_req_o (router_11_30_req_out), - .floo_rsp_i (router_11_30_rsp_in) -); - - -floo_req_t [4:0] router_11_31_req_in; -floo_rsp_t [4:0] router_11_31_rsp_out; -floo_req_t [4:0] router_11_31_req_out; -floo_rsp_t [4:0] router_11_31_rsp_in; - - assign router_11_31_req_in[0] = '0; - assign router_11_31_req_in[1] = router_12_31_to_router_11_31_req; - assign router_11_31_req_in[2] = router_11_30_to_router_11_31_req; - assign router_11_31_req_in[3] = router_10_31_to_router_11_31_req; - assign router_11_31_req_in[4] = magia_tile_ni_11_31_to_router_11_31_req; - - assign router_11_31_to_router_12_31_rsp = router_11_31_rsp_out[1]; - assign router_11_31_to_router_11_30_rsp = router_11_31_rsp_out[2]; - assign router_11_31_to_router_10_31_rsp = router_11_31_rsp_out[3]; - assign router_11_31_to_magia_tile_ni_11_31_rsp = router_11_31_rsp_out[4]; - - assign router_11_31_to_router_12_31_req = router_11_31_req_out[1]; - assign router_11_31_to_router_11_30_req = router_11_31_req_out[2]; - assign router_11_31_to_router_10_31_req = router_11_31_req_out[3]; - assign router_11_31_to_magia_tile_ni_11_31_req = router_11_31_req_out[4]; - - assign router_11_31_rsp_in[0] = '0; - assign router_11_31_rsp_in[1] = router_12_31_to_router_11_31_rsp; - assign router_11_31_rsp_in[2] = router_11_30_to_router_11_31_rsp; - assign router_11_31_rsp_in[3] = router_10_31_to_router_11_31_rsp; - assign router_11_31_rsp_in[4] = magia_tile_ni_11_31_to_router_11_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_11_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 12, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_11_31_req_in), - .floo_rsp_o (router_11_31_rsp_out), - .floo_req_o (router_11_31_req_out), - .floo_rsp_i (router_11_31_rsp_in) -); - - -floo_req_t [4:0] router_12_0_req_in; -floo_rsp_t [4:0] router_12_0_rsp_out; -floo_req_t [4:0] router_12_0_req_out; -floo_rsp_t [4:0] router_12_0_rsp_in; - - assign router_12_0_req_in[0] = router_12_1_to_router_12_0_req; - assign router_12_0_req_in[1] = router_13_0_to_router_12_0_req; - assign router_12_0_req_in[2] = '0; - assign router_12_0_req_in[3] = router_11_0_to_router_12_0_req; - assign router_12_0_req_in[4] = magia_tile_ni_12_0_to_router_12_0_req; - - assign router_12_0_to_router_12_1_rsp = router_12_0_rsp_out[0]; - assign router_12_0_to_router_13_0_rsp = router_12_0_rsp_out[1]; - assign router_12_0_to_router_11_0_rsp = router_12_0_rsp_out[3]; - assign router_12_0_to_magia_tile_ni_12_0_rsp = router_12_0_rsp_out[4]; - - assign router_12_0_to_router_12_1_req = router_12_0_req_out[0]; - assign router_12_0_to_router_13_0_req = router_12_0_req_out[1]; - assign router_12_0_to_router_11_0_req = router_12_0_req_out[3]; - assign router_12_0_to_magia_tile_ni_12_0_req = router_12_0_req_out[4]; - - assign router_12_0_rsp_in[0] = router_12_1_to_router_12_0_rsp; - assign router_12_0_rsp_in[1] = router_13_0_to_router_12_0_rsp; - assign router_12_0_rsp_in[2] = '0; - assign router_12_0_rsp_in[3] = router_11_0_to_router_12_0_rsp; - assign router_12_0_rsp_in[4] = magia_tile_ni_12_0_to_router_12_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_0_req_in), - .floo_rsp_o (router_12_0_rsp_out), - .floo_req_o (router_12_0_req_out), - .floo_rsp_i (router_12_0_rsp_in) -); - - -floo_req_t [4:0] router_12_1_req_in; -floo_rsp_t [4:0] router_12_1_rsp_out; -floo_req_t [4:0] router_12_1_req_out; -floo_rsp_t [4:0] router_12_1_rsp_in; - - assign router_12_1_req_in[0] = router_12_2_to_router_12_1_req; - assign router_12_1_req_in[1] = router_13_1_to_router_12_1_req; - assign router_12_1_req_in[2] = router_12_0_to_router_12_1_req; - assign router_12_1_req_in[3] = router_11_1_to_router_12_1_req; - assign router_12_1_req_in[4] = magia_tile_ni_12_1_to_router_12_1_req; - - assign router_12_1_to_router_12_2_rsp = router_12_1_rsp_out[0]; - assign router_12_1_to_router_13_1_rsp = router_12_1_rsp_out[1]; - assign router_12_1_to_router_12_0_rsp = router_12_1_rsp_out[2]; - assign router_12_1_to_router_11_1_rsp = router_12_1_rsp_out[3]; - assign router_12_1_to_magia_tile_ni_12_1_rsp = router_12_1_rsp_out[4]; - - assign router_12_1_to_router_12_2_req = router_12_1_req_out[0]; - assign router_12_1_to_router_13_1_req = router_12_1_req_out[1]; - assign router_12_1_to_router_12_0_req = router_12_1_req_out[2]; - assign router_12_1_to_router_11_1_req = router_12_1_req_out[3]; - assign router_12_1_to_magia_tile_ni_12_1_req = router_12_1_req_out[4]; - - assign router_12_1_rsp_in[0] = router_12_2_to_router_12_1_rsp; - assign router_12_1_rsp_in[1] = router_13_1_to_router_12_1_rsp; - assign router_12_1_rsp_in[2] = router_12_0_to_router_12_1_rsp; - assign router_12_1_rsp_in[3] = router_11_1_to_router_12_1_rsp; - assign router_12_1_rsp_in[4] = magia_tile_ni_12_1_to_router_12_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_1_req_in), - .floo_rsp_o (router_12_1_rsp_out), - .floo_req_o (router_12_1_req_out), - .floo_rsp_i (router_12_1_rsp_in) -); - - -floo_req_t [4:0] router_12_2_req_in; -floo_rsp_t [4:0] router_12_2_rsp_out; -floo_req_t [4:0] router_12_2_req_out; -floo_rsp_t [4:0] router_12_2_rsp_in; - - assign router_12_2_req_in[0] = router_12_3_to_router_12_2_req; - assign router_12_2_req_in[1] = router_13_2_to_router_12_2_req; - assign router_12_2_req_in[2] = router_12_1_to_router_12_2_req; - assign router_12_2_req_in[3] = router_11_2_to_router_12_2_req; - assign router_12_2_req_in[4] = magia_tile_ni_12_2_to_router_12_2_req; - - assign router_12_2_to_router_12_3_rsp = router_12_2_rsp_out[0]; - assign router_12_2_to_router_13_2_rsp = router_12_2_rsp_out[1]; - assign router_12_2_to_router_12_1_rsp = router_12_2_rsp_out[2]; - assign router_12_2_to_router_11_2_rsp = router_12_2_rsp_out[3]; - assign router_12_2_to_magia_tile_ni_12_2_rsp = router_12_2_rsp_out[4]; - - assign router_12_2_to_router_12_3_req = router_12_2_req_out[0]; - assign router_12_2_to_router_13_2_req = router_12_2_req_out[1]; - assign router_12_2_to_router_12_1_req = router_12_2_req_out[2]; - assign router_12_2_to_router_11_2_req = router_12_2_req_out[3]; - assign router_12_2_to_magia_tile_ni_12_2_req = router_12_2_req_out[4]; - - assign router_12_2_rsp_in[0] = router_12_3_to_router_12_2_rsp; - assign router_12_2_rsp_in[1] = router_13_2_to_router_12_2_rsp; - assign router_12_2_rsp_in[2] = router_12_1_to_router_12_2_rsp; - assign router_12_2_rsp_in[3] = router_11_2_to_router_12_2_rsp; - assign router_12_2_rsp_in[4] = magia_tile_ni_12_2_to_router_12_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_2_req_in), - .floo_rsp_o (router_12_2_rsp_out), - .floo_req_o (router_12_2_req_out), - .floo_rsp_i (router_12_2_rsp_in) -); - - -floo_req_t [4:0] router_12_3_req_in; -floo_rsp_t [4:0] router_12_3_rsp_out; -floo_req_t [4:0] router_12_3_req_out; -floo_rsp_t [4:0] router_12_3_rsp_in; - - assign router_12_3_req_in[0] = router_12_4_to_router_12_3_req; - assign router_12_3_req_in[1] = router_13_3_to_router_12_3_req; - assign router_12_3_req_in[2] = router_12_2_to_router_12_3_req; - assign router_12_3_req_in[3] = router_11_3_to_router_12_3_req; - assign router_12_3_req_in[4] = magia_tile_ni_12_3_to_router_12_3_req; - - assign router_12_3_to_router_12_4_rsp = router_12_3_rsp_out[0]; - assign router_12_3_to_router_13_3_rsp = router_12_3_rsp_out[1]; - assign router_12_3_to_router_12_2_rsp = router_12_3_rsp_out[2]; - assign router_12_3_to_router_11_3_rsp = router_12_3_rsp_out[3]; - assign router_12_3_to_magia_tile_ni_12_3_rsp = router_12_3_rsp_out[4]; - - assign router_12_3_to_router_12_4_req = router_12_3_req_out[0]; - assign router_12_3_to_router_13_3_req = router_12_3_req_out[1]; - assign router_12_3_to_router_12_2_req = router_12_3_req_out[2]; - assign router_12_3_to_router_11_3_req = router_12_3_req_out[3]; - assign router_12_3_to_magia_tile_ni_12_3_req = router_12_3_req_out[4]; - - assign router_12_3_rsp_in[0] = router_12_4_to_router_12_3_rsp; - assign router_12_3_rsp_in[1] = router_13_3_to_router_12_3_rsp; - assign router_12_3_rsp_in[2] = router_12_2_to_router_12_3_rsp; - assign router_12_3_rsp_in[3] = router_11_3_to_router_12_3_rsp; - assign router_12_3_rsp_in[4] = magia_tile_ni_12_3_to_router_12_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_3_req_in), - .floo_rsp_o (router_12_3_rsp_out), - .floo_req_o (router_12_3_req_out), - .floo_rsp_i (router_12_3_rsp_in) -); - - -floo_req_t [4:0] router_12_4_req_in; -floo_rsp_t [4:0] router_12_4_rsp_out; -floo_req_t [4:0] router_12_4_req_out; -floo_rsp_t [4:0] router_12_4_rsp_in; - - assign router_12_4_req_in[0] = router_12_5_to_router_12_4_req; - assign router_12_4_req_in[1] = router_13_4_to_router_12_4_req; - assign router_12_4_req_in[2] = router_12_3_to_router_12_4_req; - assign router_12_4_req_in[3] = router_11_4_to_router_12_4_req; - assign router_12_4_req_in[4] = magia_tile_ni_12_4_to_router_12_4_req; - - assign router_12_4_to_router_12_5_rsp = router_12_4_rsp_out[0]; - assign router_12_4_to_router_13_4_rsp = router_12_4_rsp_out[1]; - assign router_12_4_to_router_12_3_rsp = router_12_4_rsp_out[2]; - assign router_12_4_to_router_11_4_rsp = router_12_4_rsp_out[3]; - assign router_12_4_to_magia_tile_ni_12_4_rsp = router_12_4_rsp_out[4]; - - assign router_12_4_to_router_12_5_req = router_12_4_req_out[0]; - assign router_12_4_to_router_13_4_req = router_12_4_req_out[1]; - assign router_12_4_to_router_12_3_req = router_12_4_req_out[2]; - assign router_12_4_to_router_11_4_req = router_12_4_req_out[3]; - assign router_12_4_to_magia_tile_ni_12_4_req = router_12_4_req_out[4]; - - assign router_12_4_rsp_in[0] = router_12_5_to_router_12_4_rsp; - assign router_12_4_rsp_in[1] = router_13_4_to_router_12_4_rsp; - assign router_12_4_rsp_in[2] = router_12_3_to_router_12_4_rsp; - assign router_12_4_rsp_in[3] = router_11_4_to_router_12_4_rsp; - assign router_12_4_rsp_in[4] = magia_tile_ni_12_4_to_router_12_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_4_req_in), - .floo_rsp_o (router_12_4_rsp_out), - .floo_req_o (router_12_4_req_out), - .floo_rsp_i (router_12_4_rsp_in) -); - - -floo_req_t [4:0] router_12_5_req_in; -floo_rsp_t [4:0] router_12_5_rsp_out; -floo_req_t [4:0] router_12_5_req_out; -floo_rsp_t [4:0] router_12_5_rsp_in; - - assign router_12_5_req_in[0] = router_12_6_to_router_12_5_req; - assign router_12_5_req_in[1] = router_13_5_to_router_12_5_req; - assign router_12_5_req_in[2] = router_12_4_to_router_12_5_req; - assign router_12_5_req_in[3] = router_11_5_to_router_12_5_req; - assign router_12_5_req_in[4] = magia_tile_ni_12_5_to_router_12_5_req; - - assign router_12_5_to_router_12_6_rsp = router_12_5_rsp_out[0]; - assign router_12_5_to_router_13_5_rsp = router_12_5_rsp_out[1]; - assign router_12_5_to_router_12_4_rsp = router_12_5_rsp_out[2]; - assign router_12_5_to_router_11_5_rsp = router_12_5_rsp_out[3]; - assign router_12_5_to_magia_tile_ni_12_5_rsp = router_12_5_rsp_out[4]; - - assign router_12_5_to_router_12_6_req = router_12_5_req_out[0]; - assign router_12_5_to_router_13_5_req = router_12_5_req_out[1]; - assign router_12_5_to_router_12_4_req = router_12_5_req_out[2]; - assign router_12_5_to_router_11_5_req = router_12_5_req_out[3]; - assign router_12_5_to_magia_tile_ni_12_5_req = router_12_5_req_out[4]; - - assign router_12_5_rsp_in[0] = router_12_6_to_router_12_5_rsp; - assign router_12_5_rsp_in[1] = router_13_5_to_router_12_5_rsp; - assign router_12_5_rsp_in[2] = router_12_4_to_router_12_5_rsp; - assign router_12_5_rsp_in[3] = router_11_5_to_router_12_5_rsp; - assign router_12_5_rsp_in[4] = magia_tile_ni_12_5_to_router_12_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_5_req_in), - .floo_rsp_o (router_12_5_rsp_out), - .floo_req_o (router_12_5_req_out), - .floo_rsp_i (router_12_5_rsp_in) -); - - -floo_req_t [4:0] router_12_6_req_in; -floo_rsp_t [4:0] router_12_6_rsp_out; -floo_req_t [4:0] router_12_6_req_out; -floo_rsp_t [4:0] router_12_6_rsp_in; - - assign router_12_6_req_in[0] = router_12_7_to_router_12_6_req; - assign router_12_6_req_in[1] = router_13_6_to_router_12_6_req; - assign router_12_6_req_in[2] = router_12_5_to_router_12_6_req; - assign router_12_6_req_in[3] = router_11_6_to_router_12_6_req; - assign router_12_6_req_in[4] = magia_tile_ni_12_6_to_router_12_6_req; - - assign router_12_6_to_router_12_7_rsp = router_12_6_rsp_out[0]; - assign router_12_6_to_router_13_6_rsp = router_12_6_rsp_out[1]; - assign router_12_6_to_router_12_5_rsp = router_12_6_rsp_out[2]; - assign router_12_6_to_router_11_6_rsp = router_12_6_rsp_out[3]; - assign router_12_6_to_magia_tile_ni_12_6_rsp = router_12_6_rsp_out[4]; - - assign router_12_6_to_router_12_7_req = router_12_6_req_out[0]; - assign router_12_6_to_router_13_6_req = router_12_6_req_out[1]; - assign router_12_6_to_router_12_5_req = router_12_6_req_out[2]; - assign router_12_6_to_router_11_6_req = router_12_6_req_out[3]; - assign router_12_6_to_magia_tile_ni_12_6_req = router_12_6_req_out[4]; - - assign router_12_6_rsp_in[0] = router_12_7_to_router_12_6_rsp; - assign router_12_6_rsp_in[1] = router_13_6_to_router_12_6_rsp; - assign router_12_6_rsp_in[2] = router_12_5_to_router_12_6_rsp; - assign router_12_6_rsp_in[3] = router_11_6_to_router_12_6_rsp; - assign router_12_6_rsp_in[4] = magia_tile_ni_12_6_to_router_12_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_6_req_in), - .floo_rsp_o (router_12_6_rsp_out), - .floo_req_o (router_12_6_req_out), - .floo_rsp_i (router_12_6_rsp_in) -); - - -floo_req_t [4:0] router_12_7_req_in; -floo_rsp_t [4:0] router_12_7_rsp_out; -floo_req_t [4:0] router_12_7_req_out; -floo_rsp_t [4:0] router_12_7_rsp_in; - - assign router_12_7_req_in[0] = router_12_8_to_router_12_7_req; - assign router_12_7_req_in[1] = router_13_7_to_router_12_7_req; - assign router_12_7_req_in[2] = router_12_6_to_router_12_7_req; - assign router_12_7_req_in[3] = router_11_7_to_router_12_7_req; - assign router_12_7_req_in[4] = magia_tile_ni_12_7_to_router_12_7_req; - - assign router_12_7_to_router_12_8_rsp = router_12_7_rsp_out[0]; - assign router_12_7_to_router_13_7_rsp = router_12_7_rsp_out[1]; - assign router_12_7_to_router_12_6_rsp = router_12_7_rsp_out[2]; - assign router_12_7_to_router_11_7_rsp = router_12_7_rsp_out[3]; - assign router_12_7_to_magia_tile_ni_12_7_rsp = router_12_7_rsp_out[4]; - - assign router_12_7_to_router_12_8_req = router_12_7_req_out[0]; - assign router_12_7_to_router_13_7_req = router_12_7_req_out[1]; - assign router_12_7_to_router_12_6_req = router_12_7_req_out[2]; - assign router_12_7_to_router_11_7_req = router_12_7_req_out[3]; - assign router_12_7_to_magia_tile_ni_12_7_req = router_12_7_req_out[4]; - - assign router_12_7_rsp_in[0] = router_12_8_to_router_12_7_rsp; - assign router_12_7_rsp_in[1] = router_13_7_to_router_12_7_rsp; - assign router_12_7_rsp_in[2] = router_12_6_to_router_12_7_rsp; - assign router_12_7_rsp_in[3] = router_11_7_to_router_12_7_rsp; - assign router_12_7_rsp_in[4] = magia_tile_ni_12_7_to_router_12_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_7_req_in), - .floo_rsp_o (router_12_7_rsp_out), - .floo_req_o (router_12_7_req_out), - .floo_rsp_i (router_12_7_rsp_in) -); - - -floo_req_t [4:0] router_12_8_req_in; -floo_rsp_t [4:0] router_12_8_rsp_out; -floo_req_t [4:0] router_12_8_req_out; -floo_rsp_t [4:0] router_12_8_rsp_in; - - assign router_12_8_req_in[0] = router_12_9_to_router_12_8_req; - assign router_12_8_req_in[1] = router_13_8_to_router_12_8_req; - assign router_12_8_req_in[2] = router_12_7_to_router_12_8_req; - assign router_12_8_req_in[3] = router_11_8_to_router_12_8_req; - assign router_12_8_req_in[4] = magia_tile_ni_12_8_to_router_12_8_req; - - assign router_12_8_to_router_12_9_rsp = router_12_8_rsp_out[0]; - assign router_12_8_to_router_13_8_rsp = router_12_8_rsp_out[1]; - assign router_12_8_to_router_12_7_rsp = router_12_8_rsp_out[2]; - assign router_12_8_to_router_11_8_rsp = router_12_8_rsp_out[3]; - assign router_12_8_to_magia_tile_ni_12_8_rsp = router_12_8_rsp_out[4]; - - assign router_12_8_to_router_12_9_req = router_12_8_req_out[0]; - assign router_12_8_to_router_13_8_req = router_12_8_req_out[1]; - assign router_12_8_to_router_12_7_req = router_12_8_req_out[2]; - assign router_12_8_to_router_11_8_req = router_12_8_req_out[3]; - assign router_12_8_to_magia_tile_ni_12_8_req = router_12_8_req_out[4]; - - assign router_12_8_rsp_in[0] = router_12_9_to_router_12_8_rsp; - assign router_12_8_rsp_in[1] = router_13_8_to_router_12_8_rsp; - assign router_12_8_rsp_in[2] = router_12_7_to_router_12_8_rsp; - assign router_12_8_rsp_in[3] = router_11_8_to_router_12_8_rsp; - assign router_12_8_rsp_in[4] = magia_tile_ni_12_8_to_router_12_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_8_req_in), - .floo_rsp_o (router_12_8_rsp_out), - .floo_req_o (router_12_8_req_out), - .floo_rsp_i (router_12_8_rsp_in) -); - - -floo_req_t [4:0] router_12_9_req_in; -floo_rsp_t [4:0] router_12_9_rsp_out; -floo_req_t [4:0] router_12_9_req_out; -floo_rsp_t [4:0] router_12_9_rsp_in; - - assign router_12_9_req_in[0] = router_12_10_to_router_12_9_req; - assign router_12_9_req_in[1] = router_13_9_to_router_12_9_req; - assign router_12_9_req_in[2] = router_12_8_to_router_12_9_req; - assign router_12_9_req_in[3] = router_11_9_to_router_12_9_req; - assign router_12_9_req_in[4] = magia_tile_ni_12_9_to_router_12_9_req; - - assign router_12_9_to_router_12_10_rsp = router_12_9_rsp_out[0]; - assign router_12_9_to_router_13_9_rsp = router_12_9_rsp_out[1]; - assign router_12_9_to_router_12_8_rsp = router_12_9_rsp_out[2]; - assign router_12_9_to_router_11_9_rsp = router_12_9_rsp_out[3]; - assign router_12_9_to_magia_tile_ni_12_9_rsp = router_12_9_rsp_out[4]; - - assign router_12_9_to_router_12_10_req = router_12_9_req_out[0]; - assign router_12_9_to_router_13_9_req = router_12_9_req_out[1]; - assign router_12_9_to_router_12_8_req = router_12_9_req_out[2]; - assign router_12_9_to_router_11_9_req = router_12_9_req_out[3]; - assign router_12_9_to_magia_tile_ni_12_9_req = router_12_9_req_out[4]; - - assign router_12_9_rsp_in[0] = router_12_10_to_router_12_9_rsp; - assign router_12_9_rsp_in[1] = router_13_9_to_router_12_9_rsp; - assign router_12_9_rsp_in[2] = router_12_8_to_router_12_9_rsp; - assign router_12_9_rsp_in[3] = router_11_9_to_router_12_9_rsp; - assign router_12_9_rsp_in[4] = magia_tile_ni_12_9_to_router_12_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_9_req_in), - .floo_rsp_o (router_12_9_rsp_out), - .floo_req_o (router_12_9_req_out), - .floo_rsp_i (router_12_9_rsp_in) -); - - -floo_req_t [4:0] router_12_10_req_in; -floo_rsp_t [4:0] router_12_10_rsp_out; -floo_req_t [4:0] router_12_10_req_out; -floo_rsp_t [4:0] router_12_10_rsp_in; - - assign router_12_10_req_in[0] = router_12_11_to_router_12_10_req; - assign router_12_10_req_in[1] = router_13_10_to_router_12_10_req; - assign router_12_10_req_in[2] = router_12_9_to_router_12_10_req; - assign router_12_10_req_in[3] = router_11_10_to_router_12_10_req; - assign router_12_10_req_in[4] = magia_tile_ni_12_10_to_router_12_10_req; - - assign router_12_10_to_router_12_11_rsp = router_12_10_rsp_out[0]; - assign router_12_10_to_router_13_10_rsp = router_12_10_rsp_out[1]; - assign router_12_10_to_router_12_9_rsp = router_12_10_rsp_out[2]; - assign router_12_10_to_router_11_10_rsp = router_12_10_rsp_out[3]; - assign router_12_10_to_magia_tile_ni_12_10_rsp = router_12_10_rsp_out[4]; - - assign router_12_10_to_router_12_11_req = router_12_10_req_out[0]; - assign router_12_10_to_router_13_10_req = router_12_10_req_out[1]; - assign router_12_10_to_router_12_9_req = router_12_10_req_out[2]; - assign router_12_10_to_router_11_10_req = router_12_10_req_out[3]; - assign router_12_10_to_magia_tile_ni_12_10_req = router_12_10_req_out[4]; - - assign router_12_10_rsp_in[0] = router_12_11_to_router_12_10_rsp; - assign router_12_10_rsp_in[1] = router_13_10_to_router_12_10_rsp; - assign router_12_10_rsp_in[2] = router_12_9_to_router_12_10_rsp; - assign router_12_10_rsp_in[3] = router_11_10_to_router_12_10_rsp; - assign router_12_10_rsp_in[4] = magia_tile_ni_12_10_to_router_12_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_10_req_in), - .floo_rsp_o (router_12_10_rsp_out), - .floo_req_o (router_12_10_req_out), - .floo_rsp_i (router_12_10_rsp_in) -); - - -floo_req_t [4:0] router_12_11_req_in; -floo_rsp_t [4:0] router_12_11_rsp_out; -floo_req_t [4:0] router_12_11_req_out; -floo_rsp_t [4:0] router_12_11_rsp_in; - - assign router_12_11_req_in[0] = router_12_12_to_router_12_11_req; - assign router_12_11_req_in[1] = router_13_11_to_router_12_11_req; - assign router_12_11_req_in[2] = router_12_10_to_router_12_11_req; - assign router_12_11_req_in[3] = router_11_11_to_router_12_11_req; - assign router_12_11_req_in[4] = magia_tile_ni_12_11_to_router_12_11_req; - - assign router_12_11_to_router_12_12_rsp = router_12_11_rsp_out[0]; - assign router_12_11_to_router_13_11_rsp = router_12_11_rsp_out[1]; - assign router_12_11_to_router_12_10_rsp = router_12_11_rsp_out[2]; - assign router_12_11_to_router_11_11_rsp = router_12_11_rsp_out[3]; - assign router_12_11_to_magia_tile_ni_12_11_rsp = router_12_11_rsp_out[4]; - - assign router_12_11_to_router_12_12_req = router_12_11_req_out[0]; - assign router_12_11_to_router_13_11_req = router_12_11_req_out[1]; - assign router_12_11_to_router_12_10_req = router_12_11_req_out[2]; - assign router_12_11_to_router_11_11_req = router_12_11_req_out[3]; - assign router_12_11_to_magia_tile_ni_12_11_req = router_12_11_req_out[4]; - - assign router_12_11_rsp_in[0] = router_12_12_to_router_12_11_rsp; - assign router_12_11_rsp_in[1] = router_13_11_to_router_12_11_rsp; - assign router_12_11_rsp_in[2] = router_12_10_to_router_12_11_rsp; - assign router_12_11_rsp_in[3] = router_11_11_to_router_12_11_rsp; - assign router_12_11_rsp_in[4] = magia_tile_ni_12_11_to_router_12_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_11_req_in), - .floo_rsp_o (router_12_11_rsp_out), - .floo_req_o (router_12_11_req_out), - .floo_rsp_i (router_12_11_rsp_in) -); - - -floo_req_t [4:0] router_12_12_req_in; -floo_rsp_t [4:0] router_12_12_rsp_out; -floo_req_t [4:0] router_12_12_req_out; -floo_rsp_t [4:0] router_12_12_rsp_in; - - assign router_12_12_req_in[0] = router_12_13_to_router_12_12_req; - assign router_12_12_req_in[1] = router_13_12_to_router_12_12_req; - assign router_12_12_req_in[2] = router_12_11_to_router_12_12_req; - assign router_12_12_req_in[3] = router_11_12_to_router_12_12_req; - assign router_12_12_req_in[4] = magia_tile_ni_12_12_to_router_12_12_req; - - assign router_12_12_to_router_12_13_rsp = router_12_12_rsp_out[0]; - assign router_12_12_to_router_13_12_rsp = router_12_12_rsp_out[1]; - assign router_12_12_to_router_12_11_rsp = router_12_12_rsp_out[2]; - assign router_12_12_to_router_11_12_rsp = router_12_12_rsp_out[3]; - assign router_12_12_to_magia_tile_ni_12_12_rsp = router_12_12_rsp_out[4]; - - assign router_12_12_to_router_12_13_req = router_12_12_req_out[0]; - assign router_12_12_to_router_13_12_req = router_12_12_req_out[1]; - assign router_12_12_to_router_12_11_req = router_12_12_req_out[2]; - assign router_12_12_to_router_11_12_req = router_12_12_req_out[3]; - assign router_12_12_to_magia_tile_ni_12_12_req = router_12_12_req_out[4]; - - assign router_12_12_rsp_in[0] = router_12_13_to_router_12_12_rsp; - assign router_12_12_rsp_in[1] = router_13_12_to_router_12_12_rsp; - assign router_12_12_rsp_in[2] = router_12_11_to_router_12_12_rsp; - assign router_12_12_rsp_in[3] = router_11_12_to_router_12_12_rsp; - assign router_12_12_rsp_in[4] = magia_tile_ni_12_12_to_router_12_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_12_req_in), - .floo_rsp_o (router_12_12_rsp_out), - .floo_req_o (router_12_12_req_out), - .floo_rsp_i (router_12_12_rsp_in) -); - - -floo_req_t [4:0] router_12_13_req_in; -floo_rsp_t [4:0] router_12_13_rsp_out; -floo_req_t [4:0] router_12_13_req_out; -floo_rsp_t [4:0] router_12_13_rsp_in; - - assign router_12_13_req_in[0] = router_12_14_to_router_12_13_req; - assign router_12_13_req_in[1] = router_13_13_to_router_12_13_req; - assign router_12_13_req_in[2] = router_12_12_to_router_12_13_req; - assign router_12_13_req_in[3] = router_11_13_to_router_12_13_req; - assign router_12_13_req_in[4] = magia_tile_ni_12_13_to_router_12_13_req; - - assign router_12_13_to_router_12_14_rsp = router_12_13_rsp_out[0]; - assign router_12_13_to_router_13_13_rsp = router_12_13_rsp_out[1]; - assign router_12_13_to_router_12_12_rsp = router_12_13_rsp_out[2]; - assign router_12_13_to_router_11_13_rsp = router_12_13_rsp_out[3]; - assign router_12_13_to_magia_tile_ni_12_13_rsp = router_12_13_rsp_out[4]; - - assign router_12_13_to_router_12_14_req = router_12_13_req_out[0]; - assign router_12_13_to_router_13_13_req = router_12_13_req_out[1]; - assign router_12_13_to_router_12_12_req = router_12_13_req_out[2]; - assign router_12_13_to_router_11_13_req = router_12_13_req_out[3]; - assign router_12_13_to_magia_tile_ni_12_13_req = router_12_13_req_out[4]; - - assign router_12_13_rsp_in[0] = router_12_14_to_router_12_13_rsp; - assign router_12_13_rsp_in[1] = router_13_13_to_router_12_13_rsp; - assign router_12_13_rsp_in[2] = router_12_12_to_router_12_13_rsp; - assign router_12_13_rsp_in[3] = router_11_13_to_router_12_13_rsp; - assign router_12_13_rsp_in[4] = magia_tile_ni_12_13_to_router_12_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_13_req_in), - .floo_rsp_o (router_12_13_rsp_out), - .floo_req_o (router_12_13_req_out), - .floo_rsp_i (router_12_13_rsp_in) -); - - -floo_req_t [4:0] router_12_14_req_in; -floo_rsp_t [4:0] router_12_14_rsp_out; -floo_req_t [4:0] router_12_14_req_out; -floo_rsp_t [4:0] router_12_14_rsp_in; - - assign router_12_14_req_in[0] = router_12_15_to_router_12_14_req; - assign router_12_14_req_in[1] = router_13_14_to_router_12_14_req; - assign router_12_14_req_in[2] = router_12_13_to_router_12_14_req; - assign router_12_14_req_in[3] = router_11_14_to_router_12_14_req; - assign router_12_14_req_in[4] = magia_tile_ni_12_14_to_router_12_14_req; - - assign router_12_14_to_router_12_15_rsp = router_12_14_rsp_out[0]; - assign router_12_14_to_router_13_14_rsp = router_12_14_rsp_out[1]; - assign router_12_14_to_router_12_13_rsp = router_12_14_rsp_out[2]; - assign router_12_14_to_router_11_14_rsp = router_12_14_rsp_out[3]; - assign router_12_14_to_magia_tile_ni_12_14_rsp = router_12_14_rsp_out[4]; - - assign router_12_14_to_router_12_15_req = router_12_14_req_out[0]; - assign router_12_14_to_router_13_14_req = router_12_14_req_out[1]; - assign router_12_14_to_router_12_13_req = router_12_14_req_out[2]; - assign router_12_14_to_router_11_14_req = router_12_14_req_out[3]; - assign router_12_14_to_magia_tile_ni_12_14_req = router_12_14_req_out[4]; - - assign router_12_14_rsp_in[0] = router_12_15_to_router_12_14_rsp; - assign router_12_14_rsp_in[1] = router_13_14_to_router_12_14_rsp; - assign router_12_14_rsp_in[2] = router_12_13_to_router_12_14_rsp; - assign router_12_14_rsp_in[3] = router_11_14_to_router_12_14_rsp; - assign router_12_14_rsp_in[4] = magia_tile_ni_12_14_to_router_12_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_14_req_in), - .floo_rsp_o (router_12_14_rsp_out), - .floo_req_o (router_12_14_req_out), - .floo_rsp_i (router_12_14_rsp_in) -); - - -floo_req_t [4:0] router_12_15_req_in; -floo_rsp_t [4:0] router_12_15_rsp_out; -floo_req_t [4:0] router_12_15_req_out; -floo_rsp_t [4:0] router_12_15_rsp_in; - - assign router_12_15_req_in[0] = router_12_16_to_router_12_15_req; - assign router_12_15_req_in[1] = router_13_15_to_router_12_15_req; - assign router_12_15_req_in[2] = router_12_14_to_router_12_15_req; - assign router_12_15_req_in[3] = router_11_15_to_router_12_15_req; - assign router_12_15_req_in[4] = magia_tile_ni_12_15_to_router_12_15_req; - - assign router_12_15_to_router_12_16_rsp = router_12_15_rsp_out[0]; - assign router_12_15_to_router_13_15_rsp = router_12_15_rsp_out[1]; - assign router_12_15_to_router_12_14_rsp = router_12_15_rsp_out[2]; - assign router_12_15_to_router_11_15_rsp = router_12_15_rsp_out[3]; - assign router_12_15_to_magia_tile_ni_12_15_rsp = router_12_15_rsp_out[4]; - - assign router_12_15_to_router_12_16_req = router_12_15_req_out[0]; - assign router_12_15_to_router_13_15_req = router_12_15_req_out[1]; - assign router_12_15_to_router_12_14_req = router_12_15_req_out[2]; - assign router_12_15_to_router_11_15_req = router_12_15_req_out[3]; - assign router_12_15_to_magia_tile_ni_12_15_req = router_12_15_req_out[4]; - - assign router_12_15_rsp_in[0] = router_12_16_to_router_12_15_rsp; - assign router_12_15_rsp_in[1] = router_13_15_to_router_12_15_rsp; - assign router_12_15_rsp_in[2] = router_12_14_to_router_12_15_rsp; - assign router_12_15_rsp_in[3] = router_11_15_to_router_12_15_rsp; - assign router_12_15_rsp_in[4] = magia_tile_ni_12_15_to_router_12_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_15_req_in), - .floo_rsp_o (router_12_15_rsp_out), - .floo_req_o (router_12_15_req_out), - .floo_rsp_i (router_12_15_rsp_in) -); - - -floo_req_t [4:0] router_12_16_req_in; -floo_rsp_t [4:0] router_12_16_rsp_out; -floo_req_t [4:0] router_12_16_req_out; -floo_rsp_t [4:0] router_12_16_rsp_in; - - assign router_12_16_req_in[0] = router_12_17_to_router_12_16_req; - assign router_12_16_req_in[1] = router_13_16_to_router_12_16_req; - assign router_12_16_req_in[2] = router_12_15_to_router_12_16_req; - assign router_12_16_req_in[3] = router_11_16_to_router_12_16_req; - assign router_12_16_req_in[4] = magia_tile_ni_12_16_to_router_12_16_req; - - assign router_12_16_to_router_12_17_rsp = router_12_16_rsp_out[0]; - assign router_12_16_to_router_13_16_rsp = router_12_16_rsp_out[1]; - assign router_12_16_to_router_12_15_rsp = router_12_16_rsp_out[2]; - assign router_12_16_to_router_11_16_rsp = router_12_16_rsp_out[3]; - assign router_12_16_to_magia_tile_ni_12_16_rsp = router_12_16_rsp_out[4]; - - assign router_12_16_to_router_12_17_req = router_12_16_req_out[0]; - assign router_12_16_to_router_13_16_req = router_12_16_req_out[1]; - assign router_12_16_to_router_12_15_req = router_12_16_req_out[2]; - assign router_12_16_to_router_11_16_req = router_12_16_req_out[3]; - assign router_12_16_to_magia_tile_ni_12_16_req = router_12_16_req_out[4]; - - assign router_12_16_rsp_in[0] = router_12_17_to_router_12_16_rsp; - assign router_12_16_rsp_in[1] = router_13_16_to_router_12_16_rsp; - assign router_12_16_rsp_in[2] = router_12_15_to_router_12_16_rsp; - assign router_12_16_rsp_in[3] = router_11_16_to_router_12_16_rsp; - assign router_12_16_rsp_in[4] = magia_tile_ni_12_16_to_router_12_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_16_req_in), - .floo_rsp_o (router_12_16_rsp_out), - .floo_req_o (router_12_16_req_out), - .floo_rsp_i (router_12_16_rsp_in) -); - - -floo_req_t [4:0] router_12_17_req_in; -floo_rsp_t [4:0] router_12_17_rsp_out; -floo_req_t [4:0] router_12_17_req_out; -floo_rsp_t [4:0] router_12_17_rsp_in; - - assign router_12_17_req_in[0] = router_12_18_to_router_12_17_req; - assign router_12_17_req_in[1] = router_13_17_to_router_12_17_req; - assign router_12_17_req_in[2] = router_12_16_to_router_12_17_req; - assign router_12_17_req_in[3] = router_11_17_to_router_12_17_req; - assign router_12_17_req_in[4] = magia_tile_ni_12_17_to_router_12_17_req; - - assign router_12_17_to_router_12_18_rsp = router_12_17_rsp_out[0]; - assign router_12_17_to_router_13_17_rsp = router_12_17_rsp_out[1]; - assign router_12_17_to_router_12_16_rsp = router_12_17_rsp_out[2]; - assign router_12_17_to_router_11_17_rsp = router_12_17_rsp_out[3]; - assign router_12_17_to_magia_tile_ni_12_17_rsp = router_12_17_rsp_out[4]; - - assign router_12_17_to_router_12_18_req = router_12_17_req_out[0]; - assign router_12_17_to_router_13_17_req = router_12_17_req_out[1]; - assign router_12_17_to_router_12_16_req = router_12_17_req_out[2]; - assign router_12_17_to_router_11_17_req = router_12_17_req_out[3]; - assign router_12_17_to_magia_tile_ni_12_17_req = router_12_17_req_out[4]; - - assign router_12_17_rsp_in[0] = router_12_18_to_router_12_17_rsp; - assign router_12_17_rsp_in[1] = router_13_17_to_router_12_17_rsp; - assign router_12_17_rsp_in[2] = router_12_16_to_router_12_17_rsp; - assign router_12_17_rsp_in[3] = router_11_17_to_router_12_17_rsp; - assign router_12_17_rsp_in[4] = magia_tile_ni_12_17_to_router_12_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_17_req_in), - .floo_rsp_o (router_12_17_rsp_out), - .floo_req_o (router_12_17_req_out), - .floo_rsp_i (router_12_17_rsp_in) -); - - -floo_req_t [4:0] router_12_18_req_in; -floo_rsp_t [4:0] router_12_18_rsp_out; -floo_req_t [4:0] router_12_18_req_out; -floo_rsp_t [4:0] router_12_18_rsp_in; - - assign router_12_18_req_in[0] = router_12_19_to_router_12_18_req; - assign router_12_18_req_in[1] = router_13_18_to_router_12_18_req; - assign router_12_18_req_in[2] = router_12_17_to_router_12_18_req; - assign router_12_18_req_in[3] = router_11_18_to_router_12_18_req; - assign router_12_18_req_in[4] = magia_tile_ni_12_18_to_router_12_18_req; - - assign router_12_18_to_router_12_19_rsp = router_12_18_rsp_out[0]; - assign router_12_18_to_router_13_18_rsp = router_12_18_rsp_out[1]; - assign router_12_18_to_router_12_17_rsp = router_12_18_rsp_out[2]; - assign router_12_18_to_router_11_18_rsp = router_12_18_rsp_out[3]; - assign router_12_18_to_magia_tile_ni_12_18_rsp = router_12_18_rsp_out[4]; - - assign router_12_18_to_router_12_19_req = router_12_18_req_out[0]; - assign router_12_18_to_router_13_18_req = router_12_18_req_out[1]; - assign router_12_18_to_router_12_17_req = router_12_18_req_out[2]; - assign router_12_18_to_router_11_18_req = router_12_18_req_out[3]; - assign router_12_18_to_magia_tile_ni_12_18_req = router_12_18_req_out[4]; - - assign router_12_18_rsp_in[0] = router_12_19_to_router_12_18_rsp; - assign router_12_18_rsp_in[1] = router_13_18_to_router_12_18_rsp; - assign router_12_18_rsp_in[2] = router_12_17_to_router_12_18_rsp; - assign router_12_18_rsp_in[3] = router_11_18_to_router_12_18_rsp; - assign router_12_18_rsp_in[4] = magia_tile_ni_12_18_to_router_12_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_18_req_in), - .floo_rsp_o (router_12_18_rsp_out), - .floo_req_o (router_12_18_req_out), - .floo_rsp_i (router_12_18_rsp_in) -); - - -floo_req_t [4:0] router_12_19_req_in; -floo_rsp_t [4:0] router_12_19_rsp_out; -floo_req_t [4:0] router_12_19_req_out; -floo_rsp_t [4:0] router_12_19_rsp_in; - - assign router_12_19_req_in[0] = router_12_20_to_router_12_19_req; - assign router_12_19_req_in[1] = router_13_19_to_router_12_19_req; - assign router_12_19_req_in[2] = router_12_18_to_router_12_19_req; - assign router_12_19_req_in[3] = router_11_19_to_router_12_19_req; - assign router_12_19_req_in[4] = magia_tile_ni_12_19_to_router_12_19_req; - - assign router_12_19_to_router_12_20_rsp = router_12_19_rsp_out[0]; - assign router_12_19_to_router_13_19_rsp = router_12_19_rsp_out[1]; - assign router_12_19_to_router_12_18_rsp = router_12_19_rsp_out[2]; - assign router_12_19_to_router_11_19_rsp = router_12_19_rsp_out[3]; - assign router_12_19_to_magia_tile_ni_12_19_rsp = router_12_19_rsp_out[4]; - - assign router_12_19_to_router_12_20_req = router_12_19_req_out[0]; - assign router_12_19_to_router_13_19_req = router_12_19_req_out[1]; - assign router_12_19_to_router_12_18_req = router_12_19_req_out[2]; - assign router_12_19_to_router_11_19_req = router_12_19_req_out[3]; - assign router_12_19_to_magia_tile_ni_12_19_req = router_12_19_req_out[4]; - - assign router_12_19_rsp_in[0] = router_12_20_to_router_12_19_rsp; - assign router_12_19_rsp_in[1] = router_13_19_to_router_12_19_rsp; - assign router_12_19_rsp_in[2] = router_12_18_to_router_12_19_rsp; - assign router_12_19_rsp_in[3] = router_11_19_to_router_12_19_rsp; - assign router_12_19_rsp_in[4] = magia_tile_ni_12_19_to_router_12_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_19_req_in), - .floo_rsp_o (router_12_19_rsp_out), - .floo_req_o (router_12_19_req_out), - .floo_rsp_i (router_12_19_rsp_in) -); - - -floo_req_t [4:0] router_12_20_req_in; -floo_rsp_t [4:0] router_12_20_rsp_out; -floo_req_t [4:0] router_12_20_req_out; -floo_rsp_t [4:0] router_12_20_rsp_in; - - assign router_12_20_req_in[0] = router_12_21_to_router_12_20_req; - assign router_12_20_req_in[1] = router_13_20_to_router_12_20_req; - assign router_12_20_req_in[2] = router_12_19_to_router_12_20_req; - assign router_12_20_req_in[3] = router_11_20_to_router_12_20_req; - assign router_12_20_req_in[4] = magia_tile_ni_12_20_to_router_12_20_req; - - assign router_12_20_to_router_12_21_rsp = router_12_20_rsp_out[0]; - assign router_12_20_to_router_13_20_rsp = router_12_20_rsp_out[1]; - assign router_12_20_to_router_12_19_rsp = router_12_20_rsp_out[2]; - assign router_12_20_to_router_11_20_rsp = router_12_20_rsp_out[3]; - assign router_12_20_to_magia_tile_ni_12_20_rsp = router_12_20_rsp_out[4]; - - assign router_12_20_to_router_12_21_req = router_12_20_req_out[0]; - assign router_12_20_to_router_13_20_req = router_12_20_req_out[1]; - assign router_12_20_to_router_12_19_req = router_12_20_req_out[2]; - assign router_12_20_to_router_11_20_req = router_12_20_req_out[3]; - assign router_12_20_to_magia_tile_ni_12_20_req = router_12_20_req_out[4]; - - assign router_12_20_rsp_in[0] = router_12_21_to_router_12_20_rsp; - assign router_12_20_rsp_in[1] = router_13_20_to_router_12_20_rsp; - assign router_12_20_rsp_in[2] = router_12_19_to_router_12_20_rsp; - assign router_12_20_rsp_in[3] = router_11_20_to_router_12_20_rsp; - assign router_12_20_rsp_in[4] = magia_tile_ni_12_20_to_router_12_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_20_req_in), - .floo_rsp_o (router_12_20_rsp_out), - .floo_req_o (router_12_20_req_out), - .floo_rsp_i (router_12_20_rsp_in) -); - - -floo_req_t [4:0] router_12_21_req_in; -floo_rsp_t [4:0] router_12_21_rsp_out; -floo_req_t [4:0] router_12_21_req_out; -floo_rsp_t [4:0] router_12_21_rsp_in; - - assign router_12_21_req_in[0] = router_12_22_to_router_12_21_req; - assign router_12_21_req_in[1] = router_13_21_to_router_12_21_req; - assign router_12_21_req_in[2] = router_12_20_to_router_12_21_req; - assign router_12_21_req_in[3] = router_11_21_to_router_12_21_req; - assign router_12_21_req_in[4] = magia_tile_ni_12_21_to_router_12_21_req; - - assign router_12_21_to_router_12_22_rsp = router_12_21_rsp_out[0]; - assign router_12_21_to_router_13_21_rsp = router_12_21_rsp_out[1]; - assign router_12_21_to_router_12_20_rsp = router_12_21_rsp_out[2]; - assign router_12_21_to_router_11_21_rsp = router_12_21_rsp_out[3]; - assign router_12_21_to_magia_tile_ni_12_21_rsp = router_12_21_rsp_out[4]; - - assign router_12_21_to_router_12_22_req = router_12_21_req_out[0]; - assign router_12_21_to_router_13_21_req = router_12_21_req_out[1]; - assign router_12_21_to_router_12_20_req = router_12_21_req_out[2]; - assign router_12_21_to_router_11_21_req = router_12_21_req_out[3]; - assign router_12_21_to_magia_tile_ni_12_21_req = router_12_21_req_out[4]; - - assign router_12_21_rsp_in[0] = router_12_22_to_router_12_21_rsp; - assign router_12_21_rsp_in[1] = router_13_21_to_router_12_21_rsp; - assign router_12_21_rsp_in[2] = router_12_20_to_router_12_21_rsp; - assign router_12_21_rsp_in[3] = router_11_21_to_router_12_21_rsp; - assign router_12_21_rsp_in[4] = magia_tile_ni_12_21_to_router_12_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_21_req_in), - .floo_rsp_o (router_12_21_rsp_out), - .floo_req_o (router_12_21_req_out), - .floo_rsp_i (router_12_21_rsp_in) -); - - -floo_req_t [4:0] router_12_22_req_in; -floo_rsp_t [4:0] router_12_22_rsp_out; -floo_req_t [4:0] router_12_22_req_out; -floo_rsp_t [4:0] router_12_22_rsp_in; - - assign router_12_22_req_in[0] = router_12_23_to_router_12_22_req; - assign router_12_22_req_in[1] = router_13_22_to_router_12_22_req; - assign router_12_22_req_in[2] = router_12_21_to_router_12_22_req; - assign router_12_22_req_in[3] = router_11_22_to_router_12_22_req; - assign router_12_22_req_in[4] = magia_tile_ni_12_22_to_router_12_22_req; - - assign router_12_22_to_router_12_23_rsp = router_12_22_rsp_out[0]; - assign router_12_22_to_router_13_22_rsp = router_12_22_rsp_out[1]; - assign router_12_22_to_router_12_21_rsp = router_12_22_rsp_out[2]; - assign router_12_22_to_router_11_22_rsp = router_12_22_rsp_out[3]; - assign router_12_22_to_magia_tile_ni_12_22_rsp = router_12_22_rsp_out[4]; - - assign router_12_22_to_router_12_23_req = router_12_22_req_out[0]; - assign router_12_22_to_router_13_22_req = router_12_22_req_out[1]; - assign router_12_22_to_router_12_21_req = router_12_22_req_out[2]; - assign router_12_22_to_router_11_22_req = router_12_22_req_out[3]; - assign router_12_22_to_magia_tile_ni_12_22_req = router_12_22_req_out[4]; - - assign router_12_22_rsp_in[0] = router_12_23_to_router_12_22_rsp; - assign router_12_22_rsp_in[1] = router_13_22_to_router_12_22_rsp; - assign router_12_22_rsp_in[2] = router_12_21_to_router_12_22_rsp; - assign router_12_22_rsp_in[3] = router_11_22_to_router_12_22_rsp; - assign router_12_22_rsp_in[4] = magia_tile_ni_12_22_to_router_12_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_22_req_in), - .floo_rsp_o (router_12_22_rsp_out), - .floo_req_o (router_12_22_req_out), - .floo_rsp_i (router_12_22_rsp_in) -); - - -floo_req_t [4:0] router_12_23_req_in; -floo_rsp_t [4:0] router_12_23_rsp_out; -floo_req_t [4:0] router_12_23_req_out; -floo_rsp_t [4:0] router_12_23_rsp_in; - - assign router_12_23_req_in[0] = router_12_24_to_router_12_23_req; - assign router_12_23_req_in[1] = router_13_23_to_router_12_23_req; - assign router_12_23_req_in[2] = router_12_22_to_router_12_23_req; - assign router_12_23_req_in[3] = router_11_23_to_router_12_23_req; - assign router_12_23_req_in[4] = magia_tile_ni_12_23_to_router_12_23_req; - - assign router_12_23_to_router_12_24_rsp = router_12_23_rsp_out[0]; - assign router_12_23_to_router_13_23_rsp = router_12_23_rsp_out[1]; - assign router_12_23_to_router_12_22_rsp = router_12_23_rsp_out[2]; - assign router_12_23_to_router_11_23_rsp = router_12_23_rsp_out[3]; - assign router_12_23_to_magia_tile_ni_12_23_rsp = router_12_23_rsp_out[4]; - - assign router_12_23_to_router_12_24_req = router_12_23_req_out[0]; - assign router_12_23_to_router_13_23_req = router_12_23_req_out[1]; - assign router_12_23_to_router_12_22_req = router_12_23_req_out[2]; - assign router_12_23_to_router_11_23_req = router_12_23_req_out[3]; - assign router_12_23_to_magia_tile_ni_12_23_req = router_12_23_req_out[4]; - - assign router_12_23_rsp_in[0] = router_12_24_to_router_12_23_rsp; - assign router_12_23_rsp_in[1] = router_13_23_to_router_12_23_rsp; - assign router_12_23_rsp_in[2] = router_12_22_to_router_12_23_rsp; - assign router_12_23_rsp_in[3] = router_11_23_to_router_12_23_rsp; - assign router_12_23_rsp_in[4] = magia_tile_ni_12_23_to_router_12_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_23_req_in), - .floo_rsp_o (router_12_23_rsp_out), - .floo_req_o (router_12_23_req_out), - .floo_rsp_i (router_12_23_rsp_in) -); - - -floo_req_t [4:0] router_12_24_req_in; -floo_rsp_t [4:0] router_12_24_rsp_out; -floo_req_t [4:0] router_12_24_req_out; -floo_rsp_t [4:0] router_12_24_rsp_in; - - assign router_12_24_req_in[0] = router_12_25_to_router_12_24_req; - assign router_12_24_req_in[1] = router_13_24_to_router_12_24_req; - assign router_12_24_req_in[2] = router_12_23_to_router_12_24_req; - assign router_12_24_req_in[3] = router_11_24_to_router_12_24_req; - assign router_12_24_req_in[4] = magia_tile_ni_12_24_to_router_12_24_req; - - assign router_12_24_to_router_12_25_rsp = router_12_24_rsp_out[0]; - assign router_12_24_to_router_13_24_rsp = router_12_24_rsp_out[1]; - assign router_12_24_to_router_12_23_rsp = router_12_24_rsp_out[2]; - assign router_12_24_to_router_11_24_rsp = router_12_24_rsp_out[3]; - assign router_12_24_to_magia_tile_ni_12_24_rsp = router_12_24_rsp_out[4]; - - assign router_12_24_to_router_12_25_req = router_12_24_req_out[0]; - assign router_12_24_to_router_13_24_req = router_12_24_req_out[1]; - assign router_12_24_to_router_12_23_req = router_12_24_req_out[2]; - assign router_12_24_to_router_11_24_req = router_12_24_req_out[3]; - assign router_12_24_to_magia_tile_ni_12_24_req = router_12_24_req_out[4]; - - assign router_12_24_rsp_in[0] = router_12_25_to_router_12_24_rsp; - assign router_12_24_rsp_in[1] = router_13_24_to_router_12_24_rsp; - assign router_12_24_rsp_in[2] = router_12_23_to_router_12_24_rsp; - assign router_12_24_rsp_in[3] = router_11_24_to_router_12_24_rsp; - assign router_12_24_rsp_in[4] = magia_tile_ni_12_24_to_router_12_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_24_req_in), - .floo_rsp_o (router_12_24_rsp_out), - .floo_req_o (router_12_24_req_out), - .floo_rsp_i (router_12_24_rsp_in) -); - - -floo_req_t [4:0] router_12_25_req_in; -floo_rsp_t [4:0] router_12_25_rsp_out; -floo_req_t [4:0] router_12_25_req_out; -floo_rsp_t [4:0] router_12_25_rsp_in; - - assign router_12_25_req_in[0] = router_12_26_to_router_12_25_req; - assign router_12_25_req_in[1] = router_13_25_to_router_12_25_req; - assign router_12_25_req_in[2] = router_12_24_to_router_12_25_req; - assign router_12_25_req_in[3] = router_11_25_to_router_12_25_req; - assign router_12_25_req_in[4] = magia_tile_ni_12_25_to_router_12_25_req; - - assign router_12_25_to_router_12_26_rsp = router_12_25_rsp_out[0]; - assign router_12_25_to_router_13_25_rsp = router_12_25_rsp_out[1]; - assign router_12_25_to_router_12_24_rsp = router_12_25_rsp_out[2]; - assign router_12_25_to_router_11_25_rsp = router_12_25_rsp_out[3]; - assign router_12_25_to_magia_tile_ni_12_25_rsp = router_12_25_rsp_out[4]; - - assign router_12_25_to_router_12_26_req = router_12_25_req_out[0]; - assign router_12_25_to_router_13_25_req = router_12_25_req_out[1]; - assign router_12_25_to_router_12_24_req = router_12_25_req_out[2]; - assign router_12_25_to_router_11_25_req = router_12_25_req_out[3]; - assign router_12_25_to_magia_tile_ni_12_25_req = router_12_25_req_out[4]; - - assign router_12_25_rsp_in[0] = router_12_26_to_router_12_25_rsp; - assign router_12_25_rsp_in[1] = router_13_25_to_router_12_25_rsp; - assign router_12_25_rsp_in[2] = router_12_24_to_router_12_25_rsp; - assign router_12_25_rsp_in[3] = router_11_25_to_router_12_25_rsp; - assign router_12_25_rsp_in[4] = magia_tile_ni_12_25_to_router_12_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_25_req_in), - .floo_rsp_o (router_12_25_rsp_out), - .floo_req_o (router_12_25_req_out), - .floo_rsp_i (router_12_25_rsp_in) -); - - -floo_req_t [4:0] router_12_26_req_in; -floo_rsp_t [4:0] router_12_26_rsp_out; -floo_req_t [4:0] router_12_26_req_out; -floo_rsp_t [4:0] router_12_26_rsp_in; - - assign router_12_26_req_in[0] = router_12_27_to_router_12_26_req; - assign router_12_26_req_in[1] = router_13_26_to_router_12_26_req; - assign router_12_26_req_in[2] = router_12_25_to_router_12_26_req; - assign router_12_26_req_in[3] = router_11_26_to_router_12_26_req; - assign router_12_26_req_in[4] = magia_tile_ni_12_26_to_router_12_26_req; - - assign router_12_26_to_router_12_27_rsp = router_12_26_rsp_out[0]; - assign router_12_26_to_router_13_26_rsp = router_12_26_rsp_out[1]; - assign router_12_26_to_router_12_25_rsp = router_12_26_rsp_out[2]; - assign router_12_26_to_router_11_26_rsp = router_12_26_rsp_out[3]; - assign router_12_26_to_magia_tile_ni_12_26_rsp = router_12_26_rsp_out[4]; - - assign router_12_26_to_router_12_27_req = router_12_26_req_out[0]; - assign router_12_26_to_router_13_26_req = router_12_26_req_out[1]; - assign router_12_26_to_router_12_25_req = router_12_26_req_out[2]; - assign router_12_26_to_router_11_26_req = router_12_26_req_out[3]; - assign router_12_26_to_magia_tile_ni_12_26_req = router_12_26_req_out[4]; - - assign router_12_26_rsp_in[0] = router_12_27_to_router_12_26_rsp; - assign router_12_26_rsp_in[1] = router_13_26_to_router_12_26_rsp; - assign router_12_26_rsp_in[2] = router_12_25_to_router_12_26_rsp; - assign router_12_26_rsp_in[3] = router_11_26_to_router_12_26_rsp; - assign router_12_26_rsp_in[4] = magia_tile_ni_12_26_to_router_12_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_26_req_in), - .floo_rsp_o (router_12_26_rsp_out), - .floo_req_o (router_12_26_req_out), - .floo_rsp_i (router_12_26_rsp_in) -); - - -floo_req_t [4:0] router_12_27_req_in; -floo_rsp_t [4:0] router_12_27_rsp_out; -floo_req_t [4:0] router_12_27_req_out; -floo_rsp_t [4:0] router_12_27_rsp_in; - - assign router_12_27_req_in[0] = router_12_28_to_router_12_27_req; - assign router_12_27_req_in[1] = router_13_27_to_router_12_27_req; - assign router_12_27_req_in[2] = router_12_26_to_router_12_27_req; - assign router_12_27_req_in[3] = router_11_27_to_router_12_27_req; - assign router_12_27_req_in[4] = magia_tile_ni_12_27_to_router_12_27_req; - - assign router_12_27_to_router_12_28_rsp = router_12_27_rsp_out[0]; - assign router_12_27_to_router_13_27_rsp = router_12_27_rsp_out[1]; - assign router_12_27_to_router_12_26_rsp = router_12_27_rsp_out[2]; - assign router_12_27_to_router_11_27_rsp = router_12_27_rsp_out[3]; - assign router_12_27_to_magia_tile_ni_12_27_rsp = router_12_27_rsp_out[4]; - - assign router_12_27_to_router_12_28_req = router_12_27_req_out[0]; - assign router_12_27_to_router_13_27_req = router_12_27_req_out[1]; - assign router_12_27_to_router_12_26_req = router_12_27_req_out[2]; - assign router_12_27_to_router_11_27_req = router_12_27_req_out[3]; - assign router_12_27_to_magia_tile_ni_12_27_req = router_12_27_req_out[4]; - - assign router_12_27_rsp_in[0] = router_12_28_to_router_12_27_rsp; - assign router_12_27_rsp_in[1] = router_13_27_to_router_12_27_rsp; - assign router_12_27_rsp_in[2] = router_12_26_to_router_12_27_rsp; - assign router_12_27_rsp_in[3] = router_11_27_to_router_12_27_rsp; - assign router_12_27_rsp_in[4] = magia_tile_ni_12_27_to_router_12_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_27_req_in), - .floo_rsp_o (router_12_27_rsp_out), - .floo_req_o (router_12_27_req_out), - .floo_rsp_i (router_12_27_rsp_in) -); - - -floo_req_t [4:0] router_12_28_req_in; -floo_rsp_t [4:0] router_12_28_rsp_out; -floo_req_t [4:0] router_12_28_req_out; -floo_rsp_t [4:0] router_12_28_rsp_in; - - assign router_12_28_req_in[0] = router_12_29_to_router_12_28_req; - assign router_12_28_req_in[1] = router_13_28_to_router_12_28_req; - assign router_12_28_req_in[2] = router_12_27_to_router_12_28_req; - assign router_12_28_req_in[3] = router_11_28_to_router_12_28_req; - assign router_12_28_req_in[4] = magia_tile_ni_12_28_to_router_12_28_req; - - assign router_12_28_to_router_12_29_rsp = router_12_28_rsp_out[0]; - assign router_12_28_to_router_13_28_rsp = router_12_28_rsp_out[1]; - assign router_12_28_to_router_12_27_rsp = router_12_28_rsp_out[2]; - assign router_12_28_to_router_11_28_rsp = router_12_28_rsp_out[3]; - assign router_12_28_to_magia_tile_ni_12_28_rsp = router_12_28_rsp_out[4]; - - assign router_12_28_to_router_12_29_req = router_12_28_req_out[0]; - assign router_12_28_to_router_13_28_req = router_12_28_req_out[1]; - assign router_12_28_to_router_12_27_req = router_12_28_req_out[2]; - assign router_12_28_to_router_11_28_req = router_12_28_req_out[3]; - assign router_12_28_to_magia_tile_ni_12_28_req = router_12_28_req_out[4]; - - assign router_12_28_rsp_in[0] = router_12_29_to_router_12_28_rsp; - assign router_12_28_rsp_in[1] = router_13_28_to_router_12_28_rsp; - assign router_12_28_rsp_in[2] = router_12_27_to_router_12_28_rsp; - assign router_12_28_rsp_in[3] = router_11_28_to_router_12_28_rsp; - assign router_12_28_rsp_in[4] = magia_tile_ni_12_28_to_router_12_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_28_req_in), - .floo_rsp_o (router_12_28_rsp_out), - .floo_req_o (router_12_28_req_out), - .floo_rsp_i (router_12_28_rsp_in) -); - - -floo_req_t [4:0] router_12_29_req_in; -floo_rsp_t [4:0] router_12_29_rsp_out; -floo_req_t [4:0] router_12_29_req_out; -floo_rsp_t [4:0] router_12_29_rsp_in; - - assign router_12_29_req_in[0] = router_12_30_to_router_12_29_req; - assign router_12_29_req_in[1] = router_13_29_to_router_12_29_req; - assign router_12_29_req_in[2] = router_12_28_to_router_12_29_req; - assign router_12_29_req_in[3] = router_11_29_to_router_12_29_req; - assign router_12_29_req_in[4] = magia_tile_ni_12_29_to_router_12_29_req; - - assign router_12_29_to_router_12_30_rsp = router_12_29_rsp_out[0]; - assign router_12_29_to_router_13_29_rsp = router_12_29_rsp_out[1]; - assign router_12_29_to_router_12_28_rsp = router_12_29_rsp_out[2]; - assign router_12_29_to_router_11_29_rsp = router_12_29_rsp_out[3]; - assign router_12_29_to_magia_tile_ni_12_29_rsp = router_12_29_rsp_out[4]; - - assign router_12_29_to_router_12_30_req = router_12_29_req_out[0]; - assign router_12_29_to_router_13_29_req = router_12_29_req_out[1]; - assign router_12_29_to_router_12_28_req = router_12_29_req_out[2]; - assign router_12_29_to_router_11_29_req = router_12_29_req_out[3]; - assign router_12_29_to_magia_tile_ni_12_29_req = router_12_29_req_out[4]; - - assign router_12_29_rsp_in[0] = router_12_30_to_router_12_29_rsp; - assign router_12_29_rsp_in[1] = router_13_29_to_router_12_29_rsp; - assign router_12_29_rsp_in[2] = router_12_28_to_router_12_29_rsp; - assign router_12_29_rsp_in[3] = router_11_29_to_router_12_29_rsp; - assign router_12_29_rsp_in[4] = magia_tile_ni_12_29_to_router_12_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_29_req_in), - .floo_rsp_o (router_12_29_rsp_out), - .floo_req_o (router_12_29_req_out), - .floo_rsp_i (router_12_29_rsp_in) -); - - -floo_req_t [4:0] router_12_30_req_in; -floo_rsp_t [4:0] router_12_30_rsp_out; -floo_req_t [4:0] router_12_30_req_out; -floo_rsp_t [4:0] router_12_30_rsp_in; - - assign router_12_30_req_in[0] = router_12_31_to_router_12_30_req; - assign router_12_30_req_in[1] = router_13_30_to_router_12_30_req; - assign router_12_30_req_in[2] = router_12_29_to_router_12_30_req; - assign router_12_30_req_in[3] = router_11_30_to_router_12_30_req; - assign router_12_30_req_in[4] = magia_tile_ni_12_30_to_router_12_30_req; - - assign router_12_30_to_router_12_31_rsp = router_12_30_rsp_out[0]; - assign router_12_30_to_router_13_30_rsp = router_12_30_rsp_out[1]; - assign router_12_30_to_router_12_29_rsp = router_12_30_rsp_out[2]; - assign router_12_30_to_router_11_30_rsp = router_12_30_rsp_out[3]; - assign router_12_30_to_magia_tile_ni_12_30_rsp = router_12_30_rsp_out[4]; - - assign router_12_30_to_router_12_31_req = router_12_30_req_out[0]; - assign router_12_30_to_router_13_30_req = router_12_30_req_out[1]; - assign router_12_30_to_router_12_29_req = router_12_30_req_out[2]; - assign router_12_30_to_router_11_30_req = router_12_30_req_out[3]; - assign router_12_30_to_magia_tile_ni_12_30_req = router_12_30_req_out[4]; - - assign router_12_30_rsp_in[0] = router_12_31_to_router_12_30_rsp; - assign router_12_30_rsp_in[1] = router_13_30_to_router_12_30_rsp; - assign router_12_30_rsp_in[2] = router_12_29_to_router_12_30_rsp; - assign router_12_30_rsp_in[3] = router_11_30_to_router_12_30_rsp; - assign router_12_30_rsp_in[4] = magia_tile_ni_12_30_to_router_12_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_30_req_in), - .floo_rsp_o (router_12_30_rsp_out), - .floo_req_o (router_12_30_req_out), - .floo_rsp_i (router_12_30_rsp_in) -); - - -floo_req_t [4:0] router_12_31_req_in; -floo_rsp_t [4:0] router_12_31_rsp_out; -floo_req_t [4:0] router_12_31_req_out; -floo_rsp_t [4:0] router_12_31_rsp_in; - - assign router_12_31_req_in[0] = '0; - assign router_12_31_req_in[1] = router_13_31_to_router_12_31_req; - assign router_12_31_req_in[2] = router_12_30_to_router_12_31_req; - assign router_12_31_req_in[3] = router_11_31_to_router_12_31_req; - assign router_12_31_req_in[4] = magia_tile_ni_12_31_to_router_12_31_req; - - assign router_12_31_to_router_13_31_rsp = router_12_31_rsp_out[1]; - assign router_12_31_to_router_12_30_rsp = router_12_31_rsp_out[2]; - assign router_12_31_to_router_11_31_rsp = router_12_31_rsp_out[3]; - assign router_12_31_to_magia_tile_ni_12_31_rsp = router_12_31_rsp_out[4]; - - assign router_12_31_to_router_13_31_req = router_12_31_req_out[1]; - assign router_12_31_to_router_12_30_req = router_12_31_req_out[2]; - assign router_12_31_to_router_11_31_req = router_12_31_req_out[3]; - assign router_12_31_to_magia_tile_ni_12_31_req = router_12_31_req_out[4]; - - assign router_12_31_rsp_in[0] = '0; - assign router_12_31_rsp_in[1] = router_13_31_to_router_12_31_rsp; - assign router_12_31_rsp_in[2] = router_12_30_to_router_12_31_rsp; - assign router_12_31_rsp_in[3] = router_11_31_to_router_12_31_rsp; - assign router_12_31_rsp_in[4] = magia_tile_ni_12_31_to_router_12_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_12_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 13, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_12_31_req_in), - .floo_rsp_o (router_12_31_rsp_out), - .floo_req_o (router_12_31_req_out), - .floo_rsp_i (router_12_31_rsp_in) -); - - -floo_req_t [4:0] router_13_0_req_in; -floo_rsp_t [4:0] router_13_0_rsp_out; -floo_req_t [4:0] router_13_0_req_out; -floo_rsp_t [4:0] router_13_0_rsp_in; - - assign router_13_0_req_in[0] = router_13_1_to_router_13_0_req; - assign router_13_0_req_in[1] = router_14_0_to_router_13_0_req; - assign router_13_0_req_in[2] = '0; - assign router_13_0_req_in[3] = router_12_0_to_router_13_0_req; - assign router_13_0_req_in[4] = magia_tile_ni_13_0_to_router_13_0_req; - - assign router_13_0_to_router_13_1_rsp = router_13_0_rsp_out[0]; - assign router_13_0_to_router_14_0_rsp = router_13_0_rsp_out[1]; - assign router_13_0_to_router_12_0_rsp = router_13_0_rsp_out[3]; - assign router_13_0_to_magia_tile_ni_13_0_rsp = router_13_0_rsp_out[4]; - - assign router_13_0_to_router_13_1_req = router_13_0_req_out[0]; - assign router_13_0_to_router_14_0_req = router_13_0_req_out[1]; - assign router_13_0_to_router_12_0_req = router_13_0_req_out[3]; - assign router_13_0_to_magia_tile_ni_13_0_req = router_13_0_req_out[4]; - - assign router_13_0_rsp_in[0] = router_13_1_to_router_13_0_rsp; - assign router_13_0_rsp_in[1] = router_14_0_to_router_13_0_rsp; - assign router_13_0_rsp_in[2] = '0; - assign router_13_0_rsp_in[3] = router_12_0_to_router_13_0_rsp; - assign router_13_0_rsp_in[4] = magia_tile_ni_13_0_to_router_13_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_0_req_in), - .floo_rsp_o (router_13_0_rsp_out), - .floo_req_o (router_13_0_req_out), - .floo_rsp_i (router_13_0_rsp_in) -); - - -floo_req_t [4:0] router_13_1_req_in; -floo_rsp_t [4:0] router_13_1_rsp_out; -floo_req_t [4:0] router_13_1_req_out; -floo_rsp_t [4:0] router_13_1_rsp_in; - - assign router_13_1_req_in[0] = router_13_2_to_router_13_1_req; - assign router_13_1_req_in[1] = router_14_1_to_router_13_1_req; - assign router_13_1_req_in[2] = router_13_0_to_router_13_1_req; - assign router_13_1_req_in[3] = router_12_1_to_router_13_1_req; - assign router_13_1_req_in[4] = magia_tile_ni_13_1_to_router_13_1_req; - - assign router_13_1_to_router_13_2_rsp = router_13_1_rsp_out[0]; - assign router_13_1_to_router_14_1_rsp = router_13_1_rsp_out[1]; - assign router_13_1_to_router_13_0_rsp = router_13_1_rsp_out[2]; - assign router_13_1_to_router_12_1_rsp = router_13_1_rsp_out[3]; - assign router_13_1_to_magia_tile_ni_13_1_rsp = router_13_1_rsp_out[4]; - - assign router_13_1_to_router_13_2_req = router_13_1_req_out[0]; - assign router_13_1_to_router_14_1_req = router_13_1_req_out[1]; - assign router_13_1_to_router_13_0_req = router_13_1_req_out[2]; - assign router_13_1_to_router_12_1_req = router_13_1_req_out[3]; - assign router_13_1_to_magia_tile_ni_13_1_req = router_13_1_req_out[4]; - - assign router_13_1_rsp_in[0] = router_13_2_to_router_13_1_rsp; - assign router_13_1_rsp_in[1] = router_14_1_to_router_13_1_rsp; - assign router_13_1_rsp_in[2] = router_13_0_to_router_13_1_rsp; - assign router_13_1_rsp_in[3] = router_12_1_to_router_13_1_rsp; - assign router_13_1_rsp_in[4] = magia_tile_ni_13_1_to_router_13_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_1_req_in), - .floo_rsp_o (router_13_1_rsp_out), - .floo_req_o (router_13_1_req_out), - .floo_rsp_i (router_13_1_rsp_in) -); - - -floo_req_t [4:0] router_13_2_req_in; -floo_rsp_t [4:0] router_13_2_rsp_out; -floo_req_t [4:0] router_13_2_req_out; -floo_rsp_t [4:0] router_13_2_rsp_in; - - assign router_13_2_req_in[0] = router_13_3_to_router_13_2_req; - assign router_13_2_req_in[1] = router_14_2_to_router_13_2_req; - assign router_13_2_req_in[2] = router_13_1_to_router_13_2_req; - assign router_13_2_req_in[3] = router_12_2_to_router_13_2_req; - assign router_13_2_req_in[4] = magia_tile_ni_13_2_to_router_13_2_req; - - assign router_13_2_to_router_13_3_rsp = router_13_2_rsp_out[0]; - assign router_13_2_to_router_14_2_rsp = router_13_2_rsp_out[1]; - assign router_13_2_to_router_13_1_rsp = router_13_2_rsp_out[2]; - assign router_13_2_to_router_12_2_rsp = router_13_2_rsp_out[3]; - assign router_13_2_to_magia_tile_ni_13_2_rsp = router_13_2_rsp_out[4]; - - assign router_13_2_to_router_13_3_req = router_13_2_req_out[0]; - assign router_13_2_to_router_14_2_req = router_13_2_req_out[1]; - assign router_13_2_to_router_13_1_req = router_13_2_req_out[2]; - assign router_13_2_to_router_12_2_req = router_13_2_req_out[3]; - assign router_13_2_to_magia_tile_ni_13_2_req = router_13_2_req_out[4]; - - assign router_13_2_rsp_in[0] = router_13_3_to_router_13_2_rsp; - assign router_13_2_rsp_in[1] = router_14_2_to_router_13_2_rsp; - assign router_13_2_rsp_in[2] = router_13_1_to_router_13_2_rsp; - assign router_13_2_rsp_in[3] = router_12_2_to_router_13_2_rsp; - assign router_13_2_rsp_in[4] = magia_tile_ni_13_2_to_router_13_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_2_req_in), - .floo_rsp_o (router_13_2_rsp_out), - .floo_req_o (router_13_2_req_out), - .floo_rsp_i (router_13_2_rsp_in) -); - - -floo_req_t [4:0] router_13_3_req_in; -floo_rsp_t [4:0] router_13_3_rsp_out; -floo_req_t [4:0] router_13_3_req_out; -floo_rsp_t [4:0] router_13_3_rsp_in; - - assign router_13_3_req_in[0] = router_13_4_to_router_13_3_req; - assign router_13_3_req_in[1] = router_14_3_to_router_13_3_req; - assign router_13_3_req_in[2] = router_13_2_to_router_13_3_req; - assign router_13_3_req_in[3] = router_12_3_to_router_13_3_req; - assign router_13_3_req_in[4] = magia_tile_ni_13_3_to_router_13_3_req; - - assign router_13_3_to_router_13_4_rsp = router_13_3_rsp_out[0]; - assign router_13_3_to_router_14_3_rsp = router_13_3_rsp_out[1]; - assign router_13_3_to_router_13_2_rsp = router_13_3_rsp_out[2]; - assign router_13_3_to_router_12_3_rsp = router_13_3_rsp_out[3]; - assign router_13_3_to_magia_tile_ni_13_3_rsp = router_13_3_rsp_out[4]; - - assign router_13_3_to_router_13_4_req = router_13_3_req_out[0]; - assign router_13_3_to_router_14_3_req = router_13_3_req_out[1]; - assign router_13_3_to_router_13_2_req = router_13_3_req_out[2]; - assign router_13_3_to_router_12_3_req = router_13_3_req_out[3]; - assign router_13_3_to_magia_tile_ni_13_3_req = router_13_3_req_out[4]; - - assign router_13_3_rsp_in[0] = router_13_4_to_router_13_3_rsp; - assign router_13_3_rsp_in[1] = router_14_3_to_router_13_3_rsp; - assign router_13_3_rsp_in[2] = router_13_2_to_router_13_3_rsp; - assign router_13_3_rsp_in[3] = router_12_3_to_router_13_3_rsp; - assign router_13_3_rsp_in[4] = magia_tile_ni_13_3_to_router_13_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_3_req_in), - .floo_rsp_o (router_13_3_rsp_out), - .floo_req_o (router_13_3_req_out), - .floo_rsp_i (router_13_3_rsp_in) -); - - -floo_req_t [4:0] router_13_4_req_in; -floo_rsp_t [4:0] router_13_4_rsp_out; -floo_req_t [4:0] router_13_4_req_out; -floo_rsp_t [4:0] router_13_4_rsp_in; - - assign router_13_4_req_in[0] = router_13_5_to_router_13_4_req; - assign router_13_4_req_in[1] = router_14_4_to_router_13_4_req; - assign router_13_4_req_in[2] = router_13_3_to_router_13_4_req; - assign router_13_4_req_in[3] = router_12_4_to_router_13_4_req; - assign router_13_4_req_in[4] = magia_tile_ni_13_4_to_router_13_4_req; - - assign router_13_4_to_router_13_5_rsp = router_13_4_rsp_out[0]; - assign router_13_4_to_router_14_4_rsp = router_13_4_rsp_out[1]; - assign router_13_4_to_router_13_3_rsp = router_13_4_rsp_out[2]; - assign router_13_4_to_router_12_4_rsp = router_13_4_rsp_out[3]; - assign router_13_4_to_magia_tile_ni_13_4_rsp = router_13_4_rsp_out[4]; - - assign router_13_4_to_router_13_5_req = router_13_4_req_out[0]; - assign router_13_4_to_router_14_4_req = router_13_4_req_out[1]; - assign router_13_4_to_router_13_3_req = router_13_4_req_out[2]; - assign router_13_4_to_router_12_4_req = router_13_4_req_out[3]; - assign router_13_4_to_magia_tile_ni_13_4_req = router_13_4_req_out[4]; - - assign router_13_4_rsp_in[0] = router_13_5_to_router_13_4_rsp; - assign router_13_4_rsp_in[1] = router_14_4_to_router_13_4_rsp; - assign router_13_4_rsp_in[2] = router_13_3_to_router_13_4_rsp; - assign router_13_4_rsp_in[3] = router_12_4_to_router_13_4_rsp; - assign router_13_4_rsp_in[4] = magia_tile_ni_13_4_to_router_13_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_4_req_in), - .floo_rsp_o (router_13_4_rsp_out), - .floo_req_o (router_13_4_req_out), - .floo_rsp_i (router_13_4_rsp_in) -); - - -floo_req_t [4:0] router_13_5_req_in; -floo_rsp_t [4:0] router_13_5_rsp_out; -floo_req_t [4:0] router_13_5_req_out; -floo_rsp_t [4:0] router_13_5_rsp_in; - - assign router_13_5_req_in[0] = router_13_6_to_router_13_5_req; - assign router_13_5_req_in[1] = router_14_5_to_router_13_5_req; - assign router_13_5_req_in[2] = router_13_4_to_router_13_5_req; - assign router_13_5_req_in[3] = router_12_5_to_router_13_5_req; - assign router_13_5_req_in[4] = magia_tile_ni_13_5_to_router_13_5_req; - - assign router_13_5_to_router_13_6_rsp = router_13_5_rsp_out[0]; - assign router_13_5_to_router_14_5_rsp = router_13_5_rsp_out[1]; - assign router_13_5_to_router_13_4_rsp = router_13_5_rsp_out[2]; - assign router_13_5_to_router_12_5_rsp = router_13_5_rsp_out[3]; - assign router_13_5_to_magia_tile_ni_13_5_rsp = router_13_5_rsp_out[4]; - - assign router_13_5_to_router_13_6_req = router_13_5_req_out[0]; - assign router_13_5_to_router_14_5_req = router_13_5_req_out[1]; - assign router_13_5_to_router_13_4_req = router_13_5_req_out[2]; - assign router_13_5_to_router_12_5_req = router_13_5_req_out[3]; - assign router_13_5_to_magia_tile_ni_13_5_req = router_13_5_req_out[4]; - - assign router_13_5_rsp_in[0] = router_13_6_to_router_13_5_rsp; - assign router_13_5_rsp_in[1] = router_14_5_to_router_13_5_rsp; - assign router_13_5_rsp_in[2] = router_13_4_to_router_13_5_rsp; - assign router_13_5_rsp_in[3] = router_12_5_to_router_13_5_rsp; - assign router_13_5_rsp_in[4] = magia_tile_ni_13_5_to_router_13_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_5_req_in), - .floo_rsp_o (router_13_5_rsp_out), - .floo_req_o (router_13_5_req_out), - .floo_rsp_i (router_13_5_rsp_in) -); - - -floo_req_t [4:0] router_13_6_req_in; -floo_rsp_t [4:0] router_13_6_rsp_out; -floo_req_t [4:0] router_13_6_req_out; -floo_rsp_t [4:0] router_13_6_rsp_in; - - assign router_13_6_req_in[0] = router_13_7_to_router_13_6_req; - assign router_13_6_req_in[1] = router_14_6_to_router_13_6_req; - assign router_13_6_req_in[2] = router_13_5_to_router_13_6_req; - assign router_13_6_req_in[3] = router_12_6_to_router_13_6_req; - assign router_13_6_req_in[4] = magia_tile_ni_13_6_to_router_13_6_req; - - assign router_13_6_to_router_13_7_rsp = router_13_6_rsp_out[0]; - assign router_13_6_to_router_14_6_rsp = router_13_6_rsp_out[1]; - assign router_13_6_to_router_13_5_rsp = router_13_6_rsp_out[2]; - assign router_13_6_to_router_12_6_rsp = router_13_6_rsp_out[3]; - assign router_13_6_to_magia_tile_ni_13_6_rsp = router_13_6_rsp_out[4]; - - assign router_13_6_to_router_13_7_req = router_13_6_req_out[0]; - assign router_13_6_to_router_14_6_req = router_13_6_req_out[1]; - assign router_13_6_to_router_13_5_req = router_13_6_req_out[2]; - assign router_13_6_to_router_12_6_req = router_13_6_req_out[3]; - assign router_13_6_to_magia_tile_ni_13_6_req = router_13_6_req_out[4]; - - assign router_13_6_rsp_in[0] = router_13_7_to_router_13_6_rsp; - assign router_13_6_rsp_in[1] = router_14_6_to_router_13_6_rsp; - assign router_13_6_rsp_in[2] = router_13_5_to_router_13_6_rsp; - assign router_13_6_rsp_in[3] = router_12_6_to_router_13_6_rsp; - assign router_13_6_rsp_in[4] = magia_tile_ni_13_6_to_router_13_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_6_req_in), - .floo_rsp_o (router_13_6_rsp_out), - .floo_req_o (router_13_6_req_out), - .floo_rsp_i (router_13_6_rsp_in) -); - - -floo_req_t [4:0] router_13_7_req_in; -floo_rsp_t [4:0] router_13_7_rsp_out; -floo_req_t [4:0] router_13_7_req_out; -floo_rsp_t [4:0] router_13_7_rsp_in; - - assign router_13_7_req_in[0] = router_13_8_to_router_13_7_req; - assign router_13_7_req_in[1] = router_14_7_to_router_13_7_req; - assign router_13_7_req_in[2] = router_13_6_to_router_13_7_req; - assign router_13_7_req_in[3] = router_12_7_to_router_13_7_req; - assign router_13_7_req_in[4] = magia_tile_ni_13_7_to_router_13_7_req; - - assign router_13_7_to_router_13_8_rsp = router_13_7_rsp_out[0]; - assign router_13_7_to_router_14_7_rsp = router_13_7_rsp_out[1]; - assign router_13_7_to_router_13_6_rsp = router_13_7_rsp_out[2]; - assign router_13_7_to_router_12_7_rsp = router_13_7_rsp_out[3]; - assign router_13_7_to_magia_tile_ni_13_7_rsp = router_13_7_rsp_out[4]; - - assign router_13_7_to_router_13_8_req = router_13_7_req_out[0]; - assign router_13_7_to_router_14_7_req = router_13_7_req_out[1]; - assign router_13_7_to_router_13_6_req = router_13_7_req_out[2]; - assign router_13_7_to_router_12_7_req = router_13_7_req_out[3]; - assign router_13_7_to_magia_tile_ni_13_7_req = router_13_7_req_out[4]; - - assign router_13_7_rsp_in[0] = router_13_8_to_router_13_7_rsp; - assign router_13_7_rsp_in[1] = router_14_7_to_router_13_7_rsp; - assign router_13_7_rsp_in[2] = router_13_6_to_router_13_7_rsp; - assign router_13_7_rsp_in[3] = router_12_7_to_router_13_7_rsp; - assign router_13_7_rsp_in[4] = magia_tile_ni_13_7_to_router_13_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_7_req_in), - .floo_rsp_o (router_13_7_rsp_out), - .floo_req_o (router_13_7_req_out), - .floo_rsp_i (router_13_7_rsp_in) -); - - -floo_req_t [4:0] router_13_8_req_in; -floo_rsp_t [4:0] router_13_8_rsp_out; -floo_req_t [4:0] router_13_8_req_out; -floo_rsp_t [4:0] router_13_8_rsp_in; - - assign router_13_8_req_in[0] = router_13_9_to_router_13_8_req; - assign router_13_8_req_in[1] = router_14_8_to_router_13_8_req; - assign router_13_8_req_in[2] = router_13_7_to_router_13_8_req; - assign router_13_8_req_in[3] = router_12_8_to_router_13_8_req; - assign router_13_8_req_in[4] = magia_tile_ni_13_8_to_router_13_8_req; - - assign router_13_8_to_router_13_9_rsp = router_13_8_rsp_out[0]; - assign router_13_8_to_router_14_8_rsp = router_13_8_rsp_out[1]; - assign router_13_8_to_router_13_7_rsp = router_13_8_rsp_out[2]; - assign router_13_8_to_router_12_8_rsp = router_13_8_rsp_out[3]; - assign router_13_8_to_magia_tile_ni_13_8_rsp = router_13_8_rsp_out[4]; - - assign router_13_8_to_router_13_9_req = router_13_8_req_out[0]; - assign router_13_8_to_router_14_8_req = router_13_8_req_out[1]; - assign router_13_8_to_router_13_7_req = router_13_8_req_out[2]; - assign router_13_8_to_router_12_8_req = router_13_8_req_out[3]; - assign router_13_8_to_magia_tile_ni_13_8_req = router_13_8_req_out[4]; - - assign router_13_8_rsp_in[0] = router_13_9_to_router_13_8_rsp; - assign router_13_8_rsp_in[1] = router_14_8_to_router_13_8_rsp; - assign router_13_8_rsp_in[2] = router_13_7_to_router_13_8_rsp; - assign router_13_8_rsp_in[3] = router_12_8_to_router_13_8_rsp; - assign router_13_8_rsp_in[4] = magia_tile_ni_13_8_to_router_13_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_8_req_in), - .floo_rsp_o (router_13_8_rsp_out), - .floo_req_o (router_13_8_req_out), - .floo_rsp_i (router_13_8_rsp_in) -); - - -floo_req_t [4:0] router_13_9_req_in; -floo_rsp_t [4:0] router_13_9_rsp_out; -floo_req_t [4:0] router_13_9_req_out; -floo_rsp_t [4:0] router_13_9_rsp_in; - - assign router_13_9_req_in[0] = router_13_10_to_router_13_9_req; - assign router_13_9_req_in[1] = router_14_9_to_router_13_9_req; - assign router_13_9_req_in[2] = router_13_8_to_router_13_9_req; - assign router_13_9_req_in[3] = router_12_9_to_router_13_9_req; - assign router_13_9_req_in[4] = magia_tile_ni_13_9_to_router_13_9_req; - - assign router_13_9_to_router_13_10_rsp = router_13_9_rsp_out[0]; - assign router_13_9_to_router_14_9_rsp = router_13_9_rsp_out[1]; - assign router_13_9_to_router_13_8_rsp = router_13_9_rsp_out[2]; - assign router_13_9_to_router_12_9_rsp = router_13_9_rsp_out[3]; - assign router_13_9_to_magia_tile_ni_13_9_rsp = router_13_9_rsp_out[4]; - - assign router_13_9_to_router_13_10_req = router_13_9_req_out[0]; - assign router_13_9_to_router_14_9_req = router_13_9_req_out[1]; - assign router_13_9_to_router_13_8_req = router_13_9_req_out[2]; - assign router_13_9_to_router_12_9_req = router_13_9_req_out[3]; - assign router_13_9_to_magia_tile_ni_13_9_req = router_13_9_req_out[4]; - - assign router_13_9_rsp_in[0] = router_13_10_to_router_13_9_rsp; - assign router_13_9_rsp_in[1] = router_14_9_to_router_13_9_rsp; - assign router_13_9_rsp_in[2] = router_13_8_to_router_13_9_rsp; - assign router_13_9_rsp_in[3] = router_12_9_to_router_13_9_rsp; - assign router_13_9_rsp_in[4] = magia_tile_ni_13_9_to_router_13_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_9_req_in), - .floo_rsp_o (router_13_9_rsp_out), - .floo_req_o (router_13_9_req_out), - .floo_rsp_i (router_13_9_rsp_in) -); - - -floo_req_t [4:0] router_13_10_req_in; -floo_rsp_t [4:0] router_13_10_rsp_out; -floo_req_t [4:0] router_13_10_req_out; -floo_rsp_t [4:0] router_13_10_rsp_in; - - assign router_13_10_req_in[0] = router_13_11_to_router_13_10_req; - assign router_13_10_req_in[1] = router_14_10_to_router_13_10_req; - assign router_13_10_req_in[2] = router_13_9_to_router_13_10_req; - assign router_13_10_req_in[3] = router_12_10_to_router_13_10_req; - assign router_13_10_req_in[4] = magia_tile_ni_13_10_to_router_13_10_req; - - assign router_13_10_to_router_13_11_rsp = router_13_10_rsp_out[0]; - assign router_13_10_to_router_14_10_rsp = router_13_10_rsp_out[1]; - assign router_13_10_to_router_13_9_rsp = router_13_10_rsp_out[2]; - assign router_13_10_to_router_12_10_rsp = router_13_10_rsp_out[3]; - assign router_13_10_to_magia_tile_ni_13_10_rsp = router_13_10_rsp_out[4]; - - assign router_13_10_to_router_13_11_req = router_13_10_req_out[0]; - assign router_13_10_to_router_14_10_req = router_13_10_req_out[1]; - assign router_13_10_to_router_13_9_req = router_13_10_req_out[2]; - assign router_13_10_to_router_12_10_req = router_13_10_req_out[3]; - assign router_13_10_to_magia_tile_ni_13_10_req = router_13_10_req_out[4]; - - assign router_13_10_rsp_in[0] = router_13_11_to_router_13_10_rsp; - assign router_13_10_rsp_in[1] = router_14_10_to_router_13_10_rsp; - assign router_13_10_rsp_in[2] = router_13_9_to_router_13_10_rsp; - assign router_13_10_rsp_in[3] = router_12_10_to_router_13_10_rsp; - assign router_13_10_rsp_in[4] = magia_tile_ni_13_10_to_router_13_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_10_req_in), - .floo_rsp_o (router_13_10_rsp_out), - .floo_req_o (router_13_10_req_out), - .floo_rsp_i (router_13_10_rsp_in) -); - - -floo_req_t [4:0] router_13_11_req_in; -floo_rsp_t [4:0] router_13_11_rsp_out; -floo_req_t [4:0] router_13_11_req_out; -floo_rsp_t [4:0] router_13_11_rsp_in; - - assign router_13_11_req_in[0] = router_13_12_to_router_13_11_req; - assign router_13_11_req_in[1] = router_14_11_to_router_13_11_req; - assign router_13_11_req_in[2] = router_13_10_to_router_13_11_req; - assign router_13_11_req_in[3] = router_12_11_to_router_13_11_req; - assign router_13_11_req_in[4] = magia_tile_ni_13_11_to_router_13_11_req; - - assign router_13_11_to_router_13_12_rsp = router_13_11_rsp_out[0]; - assign router_13_11_to_router_14_11_rsp = router_13_11_rsp_out[1]; - assign router_13_11_to_router_13_10_rsp = router_13_11_rsp_out[2]; - assign router_13_11_to_router_12_11_rsp = router_13_11_rsp_out[3]; - assign router_13_11_to_magia_tile_ni_13_11_rsp = router_13_11_rsp_out[4]; - - assign router_13_11_to_router_13_12_req = router_13_11_req_out[0]; - assign router_13_11_to_router_14_11_req = router_13_11_req_out[1]; - assign router_13_11_to_router_13_10_req = router_13_11_req_out[2]; - assign router_13_11_to_router_12_11_req = router_13_11_req_out[3]; - assign router_13_11_to_magia_tile_ni_13_11_req = router_13_11_req_out[4]; - - assign router_13_11_rsp_in[0] = router_13_12_to_router_13_11_rsp; - assign router_13_11_rsp_in[1] = router_14_11_to_router_13_11_rsp; - assign router_13_11_rsp_in[2] = router_13_10_to_router_13_11_rsp; - assign router_13_11_rsp_in[3] = router_12_11_to_router_13_11_rsp; - assign router_13_11_rsp_in[4] = magia_tile_ni_13_11_to_router_13_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_11_req_in), - .floo_rsp_o (router_13_11_rsp_out), - .floo_req_o (router_13_11_req_out), - .floo_rsp_i (router_13_11_rsp_in) -); - - -floo_req_t [4:0] router_13_12_req_in; -floo_rsp_t [4:0] router_13_12_rsp_out; -floo_req_t [4:0] router_13_12_req_out; -floo_rsp_t [4:0] router_13_12_rsp_in; - - assign router_13_12_req_in[0] = router_13_13_to_router_13_12_req; - assign router_13_12_req_in[1] = router_14_12_to_router_13_12_req; - assign router_13_12_req_in[2] = router_13_11_to_router_13_12_req; - assign router_13_12_req_in[3] = router_12_12_to_router_13_12_req; - assign router_13_12_req_in[4] = magia_tile_ni_13_12_to_router_13_12_req; - - assign router_13_12_to_router_13_13_rsp = router_13_12_rsp_out[0]; - assign router_13_12_to_router_14_12_rsp = router_13_12_rsp_out[1]; - assign router_13_12_to_router_13_11_rsp = router_13_12_rsp_out[2]; - assign router_13_12_to_router_12_12_rsp = router_13_12_rsp_out[3]; - assign router_13_12_to_magia_tile_ni_13_12_rsp = router_13_12_rsp_out[4]; - - assign router_13_12_to_router_13_13_req = router_13_12_req_out[0]; - assign router_13_12_to_router_14_12_req = router_13_12_req_out[1]; - assign router_13_12_to_router_13_11_req = router_13_12_req_out[2]; - assign router_13_12_to_router_12_12_req = router_13_12_req_out[3]; - assign router_13_12_to_magia_tile_ni_13_12_req = router_13_12_req_out[4]; - - assign router_13_12_rsp_in[0] = router_13_13_to_router_13_12_rsp; - assign router_13_12_rsp_in[1] = router_14_12_to_router_13_12_rsp; - assign router_13_12_rsp_in[2] = router_13_11_to_router_13_12_rsp; - assign router_13_12_rsp_in[3] = router_12_12_to_router_13_12_rsp; - assign router_13_12_rsp_in[4] = magia_tile_ni_13_12_to_router_13_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_12_req_in), - .floo_rsp_o (router_13_12_rsp_out), - .floo_req_o (router_13_12_req_out), - .floo_rsp_i (router_13_12_rsp_in) -); - - -floo_req_t [4:0] router_13_13_req_in; -floo_rsp_t [4:0] router_13_13_rsp_out; -floo_req_t [4:0] router_13_13_req_out; -floo_rsp_t [4:0] router_13_13_rsp_in; - - assign router_13_13_req_in[0] = router_13_14_to_router_13_13_req; - assign router_13_13_req_in[1] = router_14_13_to_router_13_13_req; - assign router_13_13_req_in[2] = router_13_12_to_router_13_13_req; - assign router_13_13_req_in[3] = router_12_13_to_router_13_13_req; - assign router_13_13_req_in[4] = magia_tile_ni_13_13_to_router_13_13_req; - - assign router_13_13_to_router_13_14_rsp = router_13_13_rsp_out[0]; - assign router_13_13_to_router_14_13_rsp = router_13_13_rsp_out[1]; - assign router_13_13_to_router_13_12_rsp = router_13_13_rsp_out[2]; - assign router_13_13_to_router_12_13_rsp = router_13_13_rsp_out[3]; - assign router_13_13_to_magia_tile_ni_13_13_rsp = router_13_13_rsp_out[4]; - - assign router_13_13_to_router_13_14_req = router_13_13_req_out[0]; - assign router_13_13_to_router_14_13_req = router_13_13_req_out[1]; - assign router_13_13_to_router_13_12_req = router_13_13_req_out[2]; - assign router_13_13_to_router_12_13_req = router_13_13_req_out[3]; - assign router_13_13_to_magia_tile_ni_13_13_req = router_13_13_req_out[4]; - - assign router_13_13_rsp_in[0] = router_13_14_to_router_13_13_rsp; - assign router_13_13_rsp_in[1] = router_14_13_to_router_13_13_rsp; - assign router_13_13_rsp_in[2] = router_13_12_to_router_13_13_rsp; - assign router_13_13_rsp_in[3] = router_12_13_to_router_13_13_rsp; - assign router_13_13_rsp_in[4] = magia_tile_ni_13_13_to_router_13_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_13_req_in), - .floo_rsp_o (router_13_13_rsp_out), - .floo_req_o (router_13_13_req_out), - .floo_rsp_i (router_13_13_rsp_in) -); - - -floo_req_t [4:0] router_13_14_req_in; -floo_rsp_t [4:0] router_13_14_rsp_out; -floo_req_t [4:0] router_13_14_req_out; -floo_rsp_t [4:0] router_13_14_rsp_in; - - assign router_13_14_req_in[0] = router_13_15_to_router_13_14_req; - assign router_13_14_req_in[1] = router_14_14_to_router_13_14_req; - assign router_13_14_req_in[2] = router_13_13_to_router_13_14_req; - assign router_13_14_req_in[3] = router_12_14_to_router_13_14_req; - assign router_13_14_req_in[4] = magia_tile_ni_13_14_to_router_13_14_req; - - assign router_13_14_to_router_13_15_rsp = router_13_14_rsp_out[0]; - assign router_13_14_to_router_14_14_rsp = router_13_14_rsp_out[1]; - assign router_13_14_to_router_13_13_rsp = router_13_14_rsp_out[2]; - assign router_13_14_to_router_12_14_rsp = router_13_14_rsp_out[3]; - assign router_13_14_to_magia_tile_ni_13_14_rsp = router_13_14_rsp_out[4]; - - assign router_13_14_to_router_13_15_req = router_13_14_req_out[0]; - assign router_13_14_to_router_14_14_req = router_13_14_req_out[1]; - assign router_13_14_to_router_13_13_req = router_13_14_req_out[2]; - assign router_13_14_to_router_12_14_req = router_13_14_req_out[3]; - assign router_13_14_to_magia_tile_ni_13_14_req = router_13_14_req_out[4]; - - assign router_13_14_rsp_in[0] = router_13_15_to_router_13_14_rsp; - assign router_13_14_rsp_in[1] = router_14_14_to_router_13_14_rsp; - assign router_13_14_rsp_in[2] = router_13_13_to_router_13_14_rsp; - assign router_13_14_rsp_in[3] = router_12_14_to_router_13_14_rsp; - assign router_13_14_rsp_in[4] = magia_tile_ni_13_14_to_router_13_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_14_req_in), - .floo_rsp_o (router_13_14_rsp_out), - .floo_req_o (router_13_14_req_out), - .floo_rsp_i (router_13_14_rsp_in) -); - - -floo_req_t [4:0] router_13_15_req_in; -floo_rsp_t [4:0] router_13_15_rsp_out; -floo_req_t [4:0] router_13_15_req_out; -floo_rsp_t [4:0] router_13_15_rsp_in; - - assign router_13_15_req_in[0] = router_13_16_to_router_13_15_req; - assign router_13_15_req_in[1] = router_14_15_to_router_13_15_req; - assign router_13_15_req_in[2] = router_13_14_to_router_13_15_req; - assign router_13_15_req_in[3] = router_12_15_to_router_13_15_req; - assign router_13_15_req_in[4] = magia_tile_ni_13_15_to_router_13_15_req; - - assign router_13_15_to_router_13_16_rsp = router_13_15_rsp_out[0]; - assign router_13_15_to_router_14_15_rsp = router_13_15_rsp_out[1]; - assign router_13_15_to_router_13_14_rsp = router_13_15_rsp_out[2]; - assign router_13_15_to_router_12_15_rsp = router_13_15_rsp_out[3]; - assign router_13_15_to_magia_tile_ni_13_15_rsp = router_13_15_rsp_out[4]; - - assign router_13_15_to_router_13_16_req = router_13_15_req_out[0]; - assign router_13_15_to_router_14_15_req = router_13_15_req_out[1]; - assign router_13_15_to_router_13_14_req = router_13_15_req_out[2]; - assign router_13_15_to_router_12_15_req = router_13_15_req_out[3]; - assign router_13_15_to_magia_tile_ni_13_15_req = router_13_15_req_out[4]; - - assign router_13_15_rsp_in[0] = router_13_16_to_router_13_15_rsp; - assign router_13_15_rsp_in[1] = router_14_15_to_router_13_15_rsp; - assign router_13_15_rsp_in[2] = router_13_14_to_router_13_15_rsp; - assign router_13_15_rsp_in[3] = router_12_15_to_router_13_15_rsp; - assign router_13_15_rsp_in[4] = magia_tile_ni_13_15_to_router_13_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_15_req_in), - .floo_rsp_o (router_13_15_rsp_out), - .floo_req_o (router_13_15_req_out), - .floo_rsp_i (router_13_15_rsp_in) -); - - -floo_req_t [4:0] router_13_16_req_in; -floo_rsp_t [4:0] router_13_16_rsp_out; -floo_req_t [4:0] router_13_16_req_out; -floo_rsp_t [4:0] router_13_16_rsp_in; - - assign router_13_16_req_in[0] = router_13_17_to_router_13_16_req; - assign router_13_16_req_in[1] = router_14_16_to_router_13_16_req; - assign router_13_16_req_in[2] = router_13_15_to_router_13_16_req; - assign router_13_16_req_in[3] = router_12_16_to_router_13_16_req; - assign router_13_16_req_in[4] = magia_tile_ni_13_16_to_router_13_16_req; - - assign router_13_16_to_router_13_17_rsp = router_13_16_rsp_out[0]; - assign router_13_16_to_router_14_16_rsp = router_13_16_rsp_out[1]; - assign router_13_16_to_router_13_15_rsp = router_13_16_rsp_out[2]; - assign router_13_16_to_router_12_16_rsp = router_13_16_rsp_out[3]; - assign router_13_16_to_magia_tile_ni_13_16_rsp = router_13_16_rsp_out[4]; - - assign router_13_16_to_router_13_17_req = router_13_16_req_out[0]; - assign router_13_16_to_router_14_16_req = router_13_16_req_out[1]; - assign router_13_16_to_router_13_15_req = router_13_16_req_out[2]; - assign router_13_16_to_router_12_16_req = router_13_16_req_out[3]; - assign router_13_16_to_magia_tile_ni_13_16_req = router_13_16_req_out[4]; - - assign router_13_16_rsp_in[0] = router_13_17_to_router_13_16_rsp; - assign router_13_16_rsp_in[1] = router_14_16_to_router_13_16_rsp; - assign router_13_16_rsp_in[2] = router_13_15_to_router_13_16_rsp; - assign router_13_16_rsp_in[3] = router_12_16_to_router_13_16_rsp; - assign router_13_16_rsp_in[4] = magia_tile_ni_13_16_to_router_13_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_16_req_in), - .floo_rsp_o (router_13_16_rsp_out), - .floo_req_o (router_13_16_req_out), - .floo_rsp_i (router_13_16_rsp_in) -); - - -floo_req_t [4:0] router_13_17_req_in; -floo_rsp_t [4:0] router_13_17_rsp_out; -floo_req_t [4:0] router_13_17_req_out; -floo_rsp_t [4:0] router_13_17_rsp_in; - - assign router_13_17_req_in[0] = router_13_18_to_router_13_17_req; - assign router_13_17_req_in[1] = router_14_17_to_router_13_17_req; - assign router_13_17_req_in[2] = router_13_16_to_router_13_17_req; - assign router_13_17_req_in[3] = router_12_17_to_router_13_17_req; - assign router_13_17_req_in[4] = magia_tile_ni_13_17_to_router_13_17_req; - - assign router_13_17_to_router_13_18_rsp = router_13_17_rsp_out[0]; - assign router_13_17_to_router_14_17_rsp = router_13_17_rsp_out[1]; - assign router_13_17_to_router_13_16_rsp = router_13_17_rsp_out[2]; - assign router_13_17_to_router_12_17_rsp = router_13_17_rsp_out[3]; - assign router_13_17_to_magia_tile_ni_13_17_rsp = router_13_17_rsp_out[4]; - - assign router_13_17_to_router_13_18_req = router_13_17_req_out[0]; - assign router_13_17_to_router_14_17_req = router_13_17_req_out[1]; - assign router_13_17_to_router_13_16_req = router_13_17_req_out[2]; - assign router_13_17_to_router_12_17_req = router_13_17_req_out[3]; - assign router_13_17_to_magia_tile_ni_13_17_req = router_13_17_req_out[4]; - - assign router_13_17_rsp_in[0] = router_13_18_to_router_13_17_rsp; - assign router_13_17_rsp_in[1] = router_14_17_to_router_13_17_rsp; - assign router_13_17_rsp_in[2] = router_13_16_to_router_13_17_rsp; - assign router_13_17_rsp_in[3] = router_12_17_to_router_13_17_rsp; - assign router_13_17_rsp_in[4] = magia_tile_ni_13_17_to_router_13_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_17_req_in), - .floo_rsp_o (router_13_17_rsp_out), - .floo_req_o (router_13_17_req_out), - .floo_rsp_i (router_13_17_rsp_in) -); - - -floo_req_t [4:0] router_13_18_req_in; -floo_rsp_t [4:0] router_13_18_rsp_out; -floo_req_t [4:0] router_13_18_req_out; -floo_rsp_t [4:0] router_13_18_rsp_in; - - assign router_13_18_req_in[0] = router_13_19_to_router_13_18_req; - assign router_13_18_req_in[1] = router_14_18_to_router_13_18_req; - assign router_13_18_req_in[2] = router_13_17_to_router_13_18_req; - assign router_13_18_req_in[3] = router_12_18_to_router_13_18_req; - assign router_13_18_req_in[4] = magia_tile_ni_13_18_to_router_13_18_req; - - assign router_13_18_to_router_13_19_rsp = router_13_18_rsp_out[0]; - assign router_13_18_to_router_14_18_rsp = router_13_18_rsp_out[1]; - assign router_13_18_to_router_13_17_rsp = router_13_18_rsp_out[2]; - assign router_13_18_to_router_12_18_rsp = router_13_18_rsp_out[3]; - assign router_13_18_to_magia_tile_ni_13_18_rsp = router_13_18_rsp_out[4]; - - assign router_13_18_to_router_13_19_req = router_13_18_req_out[0]; - assign router_13_18_to_router_14_18_req = router_13_18_req_out[1]; - assign router_13_18_to_router_13_17_req = router_13_18_req_out[2]; - assign router_13_18_to_router_12_18_req = router_13_18_req_out[3]; - assign router_13_18_to_magia_tile_ni_13_18_req = router_13_18_req_out[4]; - - assign router_13_18_rsp_in[0] = router_13_19_to_router_13_18_rsp; - assign router_13_18_rsp_in[1] = router_14_18_to_router_13_18_rsp; - assign router_13_18_rsp_in[2] = router_13_17_to_router_13_18_rsp; - assign router_13_18_rsp_in[3] = router_12_18_to_router_13_18_rsp; - assign router_13_18_rsp_in[4] = magia_tile_ni_13_18_to_router_13_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_18_req_in), - .floo_rsp_o (router_13_18_rsp_out), - .floo_req_o (router_13_18_req_out), - .floo_rsp_i (router_13_18_rsp_in) -); - - -floo_req_t [4:0] router_13_19_req_in; -floo_rsp_t [4:0] router_13_19_rsp_out; -floo_req_t [4:0] router_13_19_req_out; -floo_rsp_t [4:0] router_13_19_rsp_in; - - assign router_13_19_req_in[0] = router_13_20_to_router_13_19_req; - assign router_13_19_req_in[1] = router_14_19_to_router_13_19_req; - assign router_13_19_req_in[2] = router_13_18_to_router_13_19_req; - assign router_13_19_req_in[3] = router_12_19_to_router_13_19_req; - assign router_13_19_req_in[4] = magia_tile_ni_13_19_to_router_13_19_req; - - assign router_13_19_to_router_13_20_rsp = router_13_19_rsp_out[0]; - assign router_13_19_to_router_14_19_rsp = router_13_19_rsp_out[1]; - assign router_13_19_to_router_13_18_rsp = router_13_19_rsp_out[2]; - assign router_13_19_to_router_12_19_rsp = router_13_19_rsp_out[3]; - assign router_13_19_to_magia_tile_ni_13_19_rsp = router_13_19_rsp_out[4]; - - assign router_13_19_to_router_13_20_req = router_13_19_req_out[0]; - assign router_13_19_to_router_14_19_req = router_13_19_req_out[1]; - assign router_13_19_to_router_13_18_req = router_13_19_req_out[2]; - assign router_13_19_to_router_12_19_req = router_13_19_req_out[3]; - assign router_13_19_to_magia_tile_ni_13_19_req = router_13_19_req_out[4]; - - assign router_13_19_rsp_in[0] = router_13_20_to_router_13_19_rsp; - assign router_13_19_rsp_in[1] = router_14_19_to_router_13_19_rsp; - assign router_13_19_rsp_in[2] = router_13_18_to_router_13_19_rsp; - assign router_13_19_rsp_in[3] = router_12_19_to_router_13_19_rsp; - assign router_13_19_rsp_in[4] = magia_tile_ni_13_19_to_router_13_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_19_req_in), - .floo_rsp_o (router_13_19_rsp_out), - .floo_req_o (router_13_19_req_out), - .floo_rsp_i (router_13_19_rsp_in) -); - - -floo_req_t [4:0] router_13_20_req_in; -floo_rsp_t [4:0] router_13_20_rsp_out; -floo_req_t [4:0] router_13_20_req_out; -floo_rsp_t [4:0] router_13_20_rsp_in; - - assign router_13_20_req_in[0] = router_13_21_to_router_13_20_req; - assign router_13_20_req_in[1] = router_14_20_to_router_13_20_req; - assign router_13_20_req_in[2] = router_13_19_to_router_13_20_req; - assign router_13_20_req_in[3] = router_12_20_to_router_13_20_req; - assign router_13_20_req_in[4] = magia_tile_ni_13_20_to_router_13_20_req; - - assign router_13_20_to_router_13_21_rsp = router_13_20_rsp_out[0]; - assign router_13_20_to_router_14_20_rsp = router_13_20_rsp_out[1]; - assign router_13_20_to_router_13_19_rsp = router_13_20_rsp_out[2]; - assign router_13_20_to_router_12_20_rsp = router_13_20_rsp_out[3]; - assign router_13_20_to_magia_tile_ni_13_20_rsp = router_13_20_rsp_out[4]; - - assign router_13_20_to_router_13_21_req = router_13_20_req_out[0]; - assign router_13_20_to_router_14_20_req = router_13_20_req_out[1]; - assign router_13_20_to_router_13_19_req = router_13_20_req_out[2]; - assign router_13_20_to_router_12_20_req = router_13_20_req_out[3]; - assign router_13_20_to_magia_tile_ni_13_20_req = router_13_20_req_out[4]; - - assign router_13_20_rsp_in[0] = router_13_21_to_router_13_20_rsp; - assign router_13_20_rsp_in[1] = router_14_20_to_router_13_20_rsp; - assign router_13_20_rsp_in[2] = router_13_19_to_router_13_20_rsp; - assign router_13_20_rsp_in[3] = router_12_20_to_router_13_20_rsp; - assign router_13_20_rsp_in[4] = magia_tile_ni_13_20_to_router_13_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_20_req_in), - .floo_rsp_o (router_13_20_rsp_out), - .floo_req_o (router_13_20_req_out), - .floo_rsp_i (router_13_20_rsp_in) -); - - -floo_req_t [4:0] router_13_21_req_in; -floo_rsp_t [4:0] router_13_21_rsp_out; -floo_req_t [4:0] router_13_21_req_out; -floo_rsp_t [4:0] router_13_21_rsp_in; - - assign router_13_21_req_in[0] = router_13_22_to_router_13_21_req; - assign router_13_21_req_in[1] = router_14_21_to_router_13_21_req; - assign router_13_21_req_in[2] = router_13_20_to_router_13_21_req; - assign router_13_21_req_in[3] = router_12_21_to_router_13_21_req; - assign router_13_21_req_in[4] = magia_tile_ni_13_21_to_router_13_21_req; - - assign router_13_21_to_router_13_22_rsp = router_13_21_rsp_out[0]; - assign router_13_21_to_router_14_21_rsp = router_13_21_rsp_out[1]; - assign router_13_21_to_router_13_20_rsp = router_13_21_rsp_out[2]; - assign router_13_21_to_router_12_21_rsp = router_13_21_rsp_out[3]; - assign router_13_21_to_magia_tile_ni_13_21_rsp = router_13_21_rsp_out[4]; - - assign router_13_21_to_router_13_22_req = router_13_21_req_out[0]; - assign router_13_21_to_router_14_21_req = router_13_21_req_out[1]; - assign router_13_21_to_router_13_20_req = router_13_21_req_out[2]; - assign router_13_21_to_router_12_21_req = router_13_21_req_out[3]; - assign router_13_21_to_magia_tile_ni_13_21_req = router_13_21_req_out[4]; - - assign router_13_21_rsp_in[0] = router_13_22_to_router_13_21_rsp; - assign router_13_21_rsp_in[1] = router_14_21_to_router_13_21_rsp; - assign router_13_21_rsp_in[2] = router_13_20_to_router_13_21_rsp; - assign router_13_21_rsp_in[3] = router_12_21_to_router_13_21_rsp; - assign router_13_21_rsp_in[4] = magia_tile_ni_13_21_to_router_13_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_21_req_in), - .floo_rsp_o (router_13_21_rsp_out), - .floo_req_o (router_13_21_req_out), - .floo_rsp_i (router_13_21_rsp_in) -); - - -floo_req_t [4:0] router_13_22_req_in; -floo_rsp_t [4:0] router_13_22_rsp_out; -floo_req_t [4:0] router_13_22_req_out; -floo_rsp_t [4:0] router_13_22_rsp_in; - - assign router_13_22_req_in[0] = router_13_23_to_router_13_22_req; - assign router_13_22_req_in[1] = router_14_22_to_router_13_22_req; - assign router_13_22_req_in[2] = router_13_21_to_router_13_22_req; - assign router_13_22_req_in[3] = router_12_22_to_router_13_22_req; - assign router_13_22_req_in[4] = magia_tile_ni_13_22_to_router_13_22_req; - - assign router_13_22_to_router_13_23_rsp = router_13_22_rsp_out[0]; - assign router_13_22_to_router_14_22_rsp = router_13_22_rsp_out[1]; - assign router_13_22_to_router_13_21_rsp = router_13_22_rsp_out[2]; - assign router_13_22_to_router_12_22_rsp = router_13_22_rsp_out[3]; - assign router_13_22_to_magia_tile_ni_13_22_rsp = router_13_22_rsp_out[4]; - - assign router_13_22_to_router_13_23_req = router_13_22_req_out[0]; - assign router_13_22_to_router_14_22_req = router_13_22_req_out[1]; - assign router_13_22_to_router_13_21_req = router_13_22_req_out[2]; - assign router_13_22_to_router_12_22_req = router_13_22_req_out[3]; - assign router_13_22_to_magia_tile_ni_13_22_req = router_13_22_req_out[4]; - - assign router_13_22_rsp_in[0] = router_13_23_to_router_13_22_rsp; - assign router_13_22_rsp_in[1] = router_14_22_to_router_13_22_rsp; - assign router_13_22_rsp_in[2] = router_13_21_to_router_13_22_rsp; - assign router_13_22_rsp_in[3] = router_12_22_to_router_13_22_rsp; - assign router_13_22_rsp_in[4] = magia_tile_ni_13_22_to_router_13_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_22_req_in), - .floo_rsp_o (router_13_22_rsp_out), - .floo_req_o (router_13_22_req_out), - .floo_rsp_i (router_13_22_rsp_in) -); - - -floo_req_t [4:0] router_13_23_req_in; -floo_rsp_t [4:0] router_13_23_rsp_out; -floo_req_t [4:0] router_13_23_req_out; -floo_rsp_t [4:0] router_13_23_rsp_in; - - assign router_13_23_req_in[0] = router_13_24_to_router_13_23_req; - assign router_13_23_req_in[1] = router_14_23_to_router_13_23_req; - assign router_13_23_req_in[2] = router_13_22_to_router_13_23_req; - assign router_13_23_req_in[3] = router_12_23_to_router_13_23_req; - assign router_13_23_req_in[4] = magia_tile_ni_13_23_to_router_13_23_req; - - assign router_13_23_to_router_13_24_rsp = router_13_23_rsp_out[0]; - assign router_13_23_to_router_14_23_rsp = router_13_23_rsp_out[1]; - assign router_13_23_to_router_13_22_rsp = router_13_23_rsp_out[2]; - assign router_13_23_to_router_12_23_rsp = router_13_23_rsp_out[3]; - assign router_13_23_to_magia_tile_ni_13_23_rsp = router_13_23_rsp_out[4]; - - assign router_13_23_to_router_13_24_req = router_13_23_req_out[0]; - assign router_13_23_to_router_14_23_req = router_13_23_req_out[1]; - assign router_13_23_to_router_13_22_req = router_13_23_req_out[2]; - assign router_13_23_to_router_12_23_req = router_13_23_req_out[3]; - assign router_13_23_to_magia_tile_ni_13_23_req = router_13_23_req_out[4]; - - assign router_13_23_rsp_in[0] = router_13_24_to_router_13_23_rsp; - assign router_13_23_rsp_in[1] = router_14_23_to_router_13_23_rsp; - assign router_13_23_rsp_in[2] = router_13_22_to_router_13_23_rsp; - assign router_13_23_rsp_in[3] = router_12_23_to_router_13_23_rsp; - assign router_13_23_rsp_in[4] = magia_tile_ni_13_23_to_router_13_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_23_req_in), - .floo_rsp_o (router_13_23_rsp_out), - .floo_req_o (router_13_23_req_out), - .floo_rsp_i (router_13_23_rsp_in) -); - - -floo_req_t [4:0] router_13_24_req_in; -floo_rsp_t [4:0] router_13_24_rsp_out; -floo_req_t [4:0] router_13_24_req_out; -floo_rsp_t [4:0] router_13_24_rsp_in; - - assign router_13_24_req_in[0] = router_13_25_to_router_13_24_req; - assign router_13_24_req_in[1] = router_14_24_to_router_13_24_req; - assign router_13_24_req_in[2] = router_13_23_to_router_13_24_req; - assign router_13_24_req_in[3] = router_12_24_to_router_13_24_req; - assign router_13_24_req_in[4] = magia_tile_ni_13_24_to_router_13_24_req; - - assign router_13_24_to_router_13_25_rsp = router_13_24_rsp_out[0]; - assign router_13_24_to_router_14_24_rsp = router_13_24_rsp_out[1]; - assign router_13_24_to_router_13_23_rsp = router_13_24_rsp_out[2]; - assign router_13_24_to_router_12_24_rsp = router_13_24_rsp_out[3]; - assign router_13_24_to_magia_tile_ni_13_24_rsp = router_13_24_rsp_out[4]; - - assign router_13_24_to_router_13_25_req = router_13_24_req_out[0]; - assign router_13_24_to_router_14_24_req = router_13_24_req_out[1]; - assign router_13_24_to_router_13_23_req = router_13_24_req_out[2]; - assign router_13_24_to_router_12_24_req = router_13_24_req_out[3]; - assign router_13_24_to_magia_tile_ni_13_24_req = router_13_24_req_out[4]; - - assign router_13_24_rsp_in[0] = router_13_25_to_router_13_24_rsp; - assign router_13_24_rsp_in[1] = router_14_24_to_router_13_24_rsp; - assign router_13_24_rsp_in[2] = router_13_23_to_router_13_24_rsp; - assign router_13_24_rsp_in[3] = router_12_24_to_router_13_24_rsp; - assign router_13_24_rsp_in[4] = magia_tile_ni_13_24_to_router_13_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_24_req_in), - .floo_rsp_o (router_13_24_rsp_out), - .floo_req_o (router_13_24_req_out), - .floo_rsp_i (router_13_24_rsp_in) -); - - -floo_req_t [4:0] router_13_25_req_in; -floo_rsp_t [4:0] router_13_25_rsp_out; -floo_req_t [4:0] router_13_25_req_out; -floo_rsp_t [4:0] router_13_25_rsp_in; - - assign router_13_25_req_in[0] = router_13_26_to_router_13_25_req; - assign router_13_25_req_in[1] = router_14_25_to_router_13_25_req; - assign router_13_25_req_in[2] = router_13_24_to_router_13_25_req; - assign router_13_25_req_in[3] = router_12_25_to_router_13_25_req; - assign router_13_25_req_in[4] = magia_tile_ni_13_25_to_router_13_25_req; - - assign router_13_25_to_router_13_26_rsp = router_13_25_rsp_out[0]; - assign router_13_25_to_router_14_25_rsp = router_13_25_rsp_out[1]; - assign router_13_25_to_router_13_24_rsp = router_13_25_rsp_out[2]; - assign router_13_25_to_router_12_25_rsp = router_13_25_rsp_out[3]; - assign router_13_25_to_magia_tile_ni_13_25_rsp = router_13_25_rsp_out[4]; - - assign router_13_25_to_router_13_26_req = router_13_25_req_out[0]; - assign router_13_25_to_router_14_25_req = router_13_25_req_out[1]; - assign router_13_25_to_router_13_24_req = router_13_25_req_out[2]; - assign router_13_25_to_router_12_25_req = router_13_25_req_out[3]; - assign router_13_25_to_magia_tile_ni_13_25_req = router_13_25_req_out[4]; - - assign router_13_25_rsp_in[0] = router_13_26_to_router_13_25_rsp; - assign router_13_25_rsp_in[1] = router_14_25_to_router_13_25_rsp; - assign router_13_25_rsp_in[2] = router_13_24_to_router_13_25_rsp; - assign router_13_25_rsp_in[3] = router_12_25_to_router_13_25_rsp; - assign router_13_25_rsp_in[4] = magia_tile_ni_13_25_to_router_13_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_25_req_in), - .floo_rsp_o (router_13_25_rsp_out), - .floo_req_o (router_13_25_req_out), - .floo_rsp_i (router_13_25_rsp_in) -); - - -floo_req_t [4:0] router_13_26_req_in; -floo_rsp_t [4:0] router_13_26_rsp_out; -floo_req_t [4:0] router_13_26_req_out; -floo_rsp_t [4:0] router_13_26_rsp_in; - - assign router_13_26_req_in[0] = router_13_27_to_router_13_26_req; - assign router_13_26_req_in[1] = router_14_26_to_router_13_26_req; - assign router_13_26_req_in[2] = router_13_25_to_router_13_26_req; - assign router_13_26_req_in[3] = router_12_26_to_router_13_26_req; - assign router_13_26_req_in[4] = magia_tile_ni_13_26_to_router_13_26_req; - - assign router_13_26_to_router_13_27_rsp = router_13_26_rsp_out[0]; - assign router_13_26_to_router_14_26_rsp = router_13_26_rsp_out[1]; - assign router_13_26_to_router_13_25_rsp = router_13_26_rsp_out[2]; - assign router_13_26_to_router_12_26_rsp = router_13_26_rsp_out[3]; - assign router_13_26_to_magia_tile_ni_13_26_rsp = router_13_26_rsp_out[4]; - - assign router_13_26_to_router_13_27_req = router_13_26_req_out[0]; - assign router_13_26_to_router_14_26_req = router_13_26_req_out[1]; - assign router_13_26_to_router_13_25_req = router_13_26_req_out[2]; - assign router_13_26_to_router_12_26_req = router_13_26_req_out[3]; - assign router_13_26_to_magia_tile_ni_13_26_req = router_13_26_req_out[4]; - - assign router_13_26_rsp_in[0] = router_13_27_to_router_13_26_rsp; - assign router_13_26_rsp_in[1] = router_14_26_to_router_13_26_rsp; - assign router_13_26_rsp_in[2] = router_13_25_to_router_13_26_rsp; - assign router_13_26_rsp_in[3] = router_12_26_to_router_13_26_rsp; - assign router_13_26_rsp_in[4] = magia_tile_ni_13_26_to_router_13_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_26_req_in), - .floo_rsp_o (router_13_26_rsp_out), - .floo_req_o (router_13_26_req_out), - .floo_rsp_i (router_13_26_rsp_in) -); - - -floo_req_t [4:0] router_13_27_req_in; -floo_rsp_t [4:0] router_13_27_rsp_out; -floo_req_t [4:0] router_13_27_req_out; -floo_rsp_t [4:0] router_13_27_rsp_in; - - assign router_13_27_req_in[0] = router_13_28_to_router_13_27_req; - assign router_13_27_req_in[1] = router_14_27_to_router_13_27_req; - assign router_13_27_req_in[2] = router_13_26_to_router_13_27_req; - assign router_13_27_req_in[3] = router_12_27_to_router_13_27_req; - assign router_13_27_req_in[4] = magia_tile_ni_13_27_to_router_13_27_req; - - assign router_13_27_to_router_13_28_rsp = router_13_27_rsp_out[0]; - assign router_13_27_to_router_14_27_rsp = router_13_27_rsp_out[1]; - assign router_13_27_to_router_13_26_rsp = router_13_27_rsp_out[2]; - assign router_13_27_to_router_12_27_rsp = router_13_27_rsp_out[3]; - assign router_13_27_to_magia_tile_ni_13_27_rsp = router_13_27_rsp_out[4]; - - assign router_13_27_to_router_13_28_req = router_13_27_req_out[0]; - assign router_13_27_to_router_14_27_req = router_13_27_req_out[1]; - assign router_13_27_to_router_13_26_req = router_13_27_req_out[2]; - assign router_13_27_to_router_12_27_req = router_13_27_req_out[3]; - assign router_13_27_to_magia_tile_ni_13_27_req = router_13_27_req_out[4]; - - assign router_13_27_rsp_in[0] = router_13_28_to_router_13_27_rsp; - assign router_13_27_rsp_in[1] = router_14_27_to_router_13_27_rsp; - assign router_13_27_rsp_in[2] = router_13_26_to_router_13_27_rsp; - assign router_13_27_rsp_in[3] = router_12_27_to_router_13_27_rsp; - assign router_13_27_rsp_in[4] = magia_tile_ni_13_27_to_router_13_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_27_req_in), - .floo_rsp_o (router_13_27_rsp_out), - .floo_req_o (router_13_27_req_out), - .floo_rsp_i (router_13_27_rsp_in) -); - - -floo_req_t [4:0] router_13_28_req_in; -floo_rsp_t [4:0] router_13_28_rsp_out; -floo_req_t [4:0] router_13_28_req_out; -floo_rsp_t [4:0] router_13_28_rsp_in; - - assign router_13_28_req_in[0] = router_13_29_to_router_13_28_req; - assign router_13_28_req_in[1] = router_14_28_to_router_13_28_req; - assign router_13_28_req_in[2] = router_13_27_to_router_13_28_req; - assign router_13_28_req_in[3] = router_12_28_to_router_13_28_req; - assign router_13_28_req_in[4] = magia_tile_ni_13_28_to_router_13_28_req; - - assign router_13_28_to_router_13_29_rsp = router_13_28_rsp_out[0]; - assign router_13_28_to_router_14_28_rsp = router_13_28_rsp_out[1]; - assign router_13_28_to_router_13_27_rsp = router_13_28_rsp_out[2]; - assign router_13_28_to_router_12_28_rsp = router_13_28_rsp_out[3]; - assign router_13_28_to_magia_tile_ni_13_28_rsp = router_13_28_rsp_out[4]; - - assign router_13_28_to_router_13_29_req = router_13_28_req_out[0]; - assign router_13_28_to_router_14_28_req = router_13_28_req_out[1]; - assign router_13_28_to_router_13_27_req = router_13_28_req_out[2]; - assign router_13_28_to_router_12_28_req = router_13_28_req_out[3]; - assign router_13_28_to_magia_tile_ni_13_28_req = router_13_28_req_out[4]; - - assign router_13_28_rsp_in[0] = router_13_29_to_router_13_28_rsp; - assign router_13_28_rsp_in[1] = router_14_28_to_router_13_28_rsp; - assign router_13_28_rsp_in[2] = router_13_27_to_router_13_28_rsp; - assign router_13_28_rsp_in[3] = router_12_28_to_router_13_28_rsp; - assign router_13_28_rsp_in[4] = magia_tile_ni_13_28_to_router_13_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_28_req_in), - .floo_rsp_o (router_13_28_rsp_out), - .floo_req_o (router_13_28_req_out), - .floo_rsp_i (router_13_28_rsp_in) -); - - -floo_req_t [4:0] router_13_29_req_in; -floo_rsp_t [4:0] router_13_29_rsp_out; -floo_req_t [4:0] router_13_29_req_out; -floo_rsp_t [4:0] router_13_29_rsp_in; - - assign router_13_29_req_in[0] = router_13_30_to_router_13_29_req; - assign router_13_29_req_in[1] = router_14_29_to_router_13_29_req; - assign router_13_29_req_in[2] = router_13_28_to_router_13_29_req; - assign router_13_29_req_in[3] = router_12_29_to_router_13_29_req; - assign router_13_29_req_in[4] = magia_tile_ni_13_29_to_router_13_29_req; - - assign router_13_29_to_router_13_30_rsp = router_13_29_rsp_out[0]; - assign router_13_29_to_router_14_29_rsp = router_13_29_rsp_out[1]; - assign router_13_29_to_router_13_28_rsp = router_13_29_rsp_out[2]; - assign router_13_29_to_router_12_29_rsp = router_13_29_rsp_out[3]; - assign router_13_29_to_magia_tile_ni_13_29_rsp = router_13_29_rsp_out[4]; - - assign router_13_29_to_router_13_30_req = router_13_29_req_out[0]; - assign router_13_29_to_router_14_29_req = router_13_29_req_out[1]; - assign router_13_29_to_router_13_28_req = router_13_29_req_out[2]; - assign router_13_29_to_router_12_29_req = router_13_29_req_out[3]; - assign router_13_29_to_magia_tile_ni_13_29_req = router_13_29_req_out[4]; - - assign router_13_29_rsp_in[0] = router_13_30_to_router_13_29_rsp; - assign router_13_29_rsp_in[1] = router_14_29_to_router_13_29_rsp; - assign router_13_29_rsp_in[2] = router_13_28_to_router_13_29_rsp; - assign router_13_29_rsp_in[3] = router_12_29_to_router_13_29_rsp; - assign router_13_29_rsp_in[4] = magia_tile_ni_13_29_to_router_13_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_29_req_in), - .floo_rsp_o (router_13_29_rsp_out), - .floo_req_o (router_13_29_req_out), - .floo_rsp_i (router_13_29_rsp_in) -); - - -floo_req_t [4:0] router_13_30_req_in; -floo_rsp_t [4:0] router_13_30_rsp_out; -floo_req_t [4:0] router_13_30_req_out; -floo_rsp_t [4:0] router_13_30_rsp_in; - - assign router_13_30_req_in[0] = router_13_31_to_router_13_30_req; - assign router_13_30_req_in[1] = router_14_30_to_router_13_30_req; - assign router_13_30_req_in[2] = router_13_29_to_router_13_30_req; - assign router_13_30_req_in[3] = router_12_30_to_router_13_30_req; - assign router_13_30_req_in[4] = magia_tile_ni_13_30_to_router_13_30_req; - - assign router_13_30_to_router_13_31_rsp = router_13_30_rsp_out[0]; - assign router_13_30_to_router_14_30_rsp = router_13_30_rsp_out[1]; - assign router_13_30_to_router_13_29_rsp = router_13_30_rsp_out[2]; - assign router_13_30_to_router_12_30_rsp = router_13_30_rsp_out[3]; - assign router_13_30_to_magia_tile_ni_13_30_rsp = router_13_30_rsp_out[4]; - - assign router_13_30_to_router_13_31_req = router_13_30_req_out[0]; - assign router_13_30_to_router_14_30_req = router_13_30_req_out[1]; - assign router_13_30_to_router_13_29_req = router_13_30_req_out[2]; - assign router_13_30_to_router_12_30_req = router_13_30_req_out[3]; - assign router_13_30_to_magia_tile_ni_13_30_req = router_13_30_req_out[4]; - - assign router_13_30_rsp_in[0] = router_13_31_to_router_13_30_rsp; - assign router_13_30_rsp_in[1] = router_14_30_to_router_13_30_rsp; - assign router_13_30_rsp_in[2] = router_13_29_to_router_13_30_rsp; - assign router_13_30_rsp_in[3] = router_12_30_to_router_13_30_rsp; - assign router_13_30_rsp_in[4] = magia_tile_ni_13_30_to_router_13_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_30_req_in), - .floo_rsp_o (router_13_30_rsp_out), - .floo_req_o (router_13_30_req_out), - .floo_rsp_i (router_13_30_rsp_in) -); - - -floo_req_t [4:0] router_13_31_req_in; -floo_rsp_t [4:0] router_13_31_rsp_out; -floo_req_t [4:0] router_13_31_req_out; -floo_rsp_t [4:0] router_13_31_rsp_in; - - assign router_13_31_req_in[0] = '0; - assign router_13_31_req_in[1] = router_14_31_to_router_13_31_req; - assign router_13_31_req_in[2] = router_13_30_to_router_13_31_req; - assign router_13_31_req_in[3] = router_12_31_to_router_13_31_req; - assign router_13_31_req_in[4] = magia_tile_ni_13_31_to_router_13_31_req; - - assign router_13_31_to_router_14_31_rsp = router_13_31_rsp_out[1]; - assign router_13_31_to_router_13_30_rsp = router_13_31_rsp_out[2]; - assign router_13_31_to_router_12_31_rsp = router_13_31_rsp_out[3]; - assign router_13_31_to_magia_tile_ni_13_31_rsp = router_13_31_rsp_out[4]; - - assign router_13_31_to_router_14_31_req = router_13_31_req_out[1]; - assign router_13_31_to_router_13_30_req = router_13_31_req_out[2]; - assign router_13_31_to_router_12_31_req = router_13_31_req_out[3]; - assign router_13_31_to_magia_tile_ni_13_31_req = router_13_31_req_out[4]; - - assign router_13_31_rsp_in[0] = '0; - assign router_13_31_rsp_in[1] = router_14_31_to_router_13_31_rsp; - assign router_13_31_rsp_in[2] = router_13_30_to_router_13_31_rsp; - assign router_13_31_rsp_in[3] = router_12_31_to_router_13_31_rsp; - assign router_13_31_rsp_in[4] = magia_tile_ni_13_31_to_router_13_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_13_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 14, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_13_31_req_in), - .floo_rsp_o (router_13_31_rsp_out), - .floo_req_o (router_13_31_req_out), - .floo_rsp_i (router_13_31_rsp_in) -); - - -floo_req_t [4:0] router_14_0_req_in; -floo_rsp_t [4:0] router_14_0_rsp_out; -floo_req_t [4:0] router_14_0_req_out; -floo_rsp_t [4:0] router_14_0_rsp_in; - - assign router_14_0_req_in[0] = router_14_1_to_router_14_0_req; - assign router_14_0_req_in[1] = router_15_0_to_router_14_0_req; - assign router_14_0_req_in[2] = '0; - assign router_14_0_req_in[3] = router_13_0_to_router_14_0_req; - assign router_14_0_req_in[4] = magia_tile_ni_14_0_to_router_14_0_req; - - assign router_14_0_to_router_14_1_rsp = router_14_0_rsp_out[0]; - assign router_14_0_to_router_15_0_rsp = router_14_0_rsp_out[1]; - assign router_14_0_to_router_13_0_rsp = router_14_0_rsp_out[3]; - assign router_14_0_to_magia_tile_ni_14_0_rsp = router_14_0_rsp_out[4]; - - assign router_14_0_to_router_14_1_req = router_14_0_req_out[0]; - assign router_14_0_to_router_15_0_req = router_14_0_req_out[1]; - assign router_14_0_to_router_13_0_req = router_14_0_req_out[3]; - assign router_14_0_to_magia_tile_ni_14_0_req = router_14_0_req_out[4]; - - assign router_14_0_rsp_in[0] = router_14_1_to_router_14_0_rsp; - assign router_14_0_rsp_in[1] = router_15_0_to_router_14_0_rsp; - assign router_14_0_rsp_in[2] = '0; - assign router_14_0_rsp_in[3] = router_13_0_to_router_14_0_rsp; - assign router_14_0_rsp_in[4] = magia_tile_ni_14_0_to_router_14_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_0_req_in), - .floo_rsp_o (router_14_0_rsp_out), - .floo_req_o (router_14_0_req_out), - .floo_rsp_i (router_14_0_rsp_in) -); - - -floo_req_t [4:0] router_14_1_req_in; -floo_rsp_t [4:0] router_14_1_rsp_out; -floo_req_t [4:0] router_14_1_req_out; -floo_rsp_t [4:0] router_14_1_rsp_in; - - assign router_14_1_req_in[0] = router_14_2_to_router_14_1_req; - assign router_14_1_req_in[1] = router_15_1_to_router_14_1_req; - assign router_14_1_req_in[2] = router_14_0_to_router_14_1_req; - assign router_14_1_req_in[3] = router_13_1_to_router_14_1_req; - assign router_14_1_req_in[4] = magia_tile_ni_14_1_to_router_14_1_req; - - assign router_14_1_to_router_14_2_rsp = router_14_1_rsp_out[0]; - assign router_14_1_to_router_15_1_rsp = router_14_1_rsp_out[1]; - assign router_14_1_to_router_14_0_rsp = router_14_1_rsp_out[2]; - assign router_14_1_to_router_13_1_rsp = router_14_1_rsp_out[3]; - assign router_14_1_to_magia_tile_ni_14_1_rsp = router_14_1_rsp_out[4]; - - assign router_14_1_to_router_14_2_req = router_14_1_req_out[0]; - assign router_14_1_to_router_15_1_req = router_14_1_req_out[1]; - assign router_14_1_to_router_14_0_req = router_14_1_req_out[2]; - assign router_14_1_to_router_13_1_req = router_14_1_req_out[3]; - assign router_14_1_to_magia_tile_ni_14_1_req = router_14_1_req_out[4]; - - assign router_14_1_rsp_in[0] = router_14_2_to_router_14_1_rsp; - assign router_14_1_rsp_in[1] = router_15_1_to_router_14_1_rsp; - assign router_14_1_rsp_in[2] = router_14_0_to_router_14_1_rsp; - assign router_14_1_rsp_in[3] = router_13_1_to_router_14_1_rsp; - assign router_14_1_rsp_in[4] = magia_tile_ni_14_1_to_router_14_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_1_req_in), - .floo_rsp_o (router_14_1_rsp_out), - .floo_req_o (router_14_1_req_out), - .floo_rsp_i (router_14_1_rsp_in) -); - - -floo_req_t [4:0] router_14_2_req_in; -floo_rsp_t [4:0] router_14_2_rsp_out; -floo_req_t [4:0] router_14_2_req_out; -floo_rsp_t [4:0] router_14_2_rsp_in; - - assign router_14_2_req_in[0] = router_14_3_to_router_14_2_req; - assign router_14_2_req_in[1] = router_15_2_to_router_14_2_req; - assign router_14_2_req_in[2] = router_14_1_to_router_14_2_req; - assign router_14_2_req_in[3] = router_13_2_to_router_14_2_req; - assign router_14_2_req_in[4] = magia_tile_ni_14_2_to_router_14_2_req; - - assign router_14_2_to_router_14_3_rsp = router_14_2_rsp_out[0]; - assign router_14_2_to_router_15_2_rsp = router_14_2_rsp_out[1]; - assign router_14_2_to_router_14_1_rsp = router_14_2_rsp_out[2]; - assign router_14_2_to_router_13_2_rsp = router_14_2_rsp_out[3]; - assign router_14_2_to_magia_tile_ni_14_2_rsp = router_14_2_rsp_out[4]; - - assign router_14_2_to_router_14_3_req = router_14_2_req_out[0]; - assign router_14_2_to_router_15_2_req = router_14_2_req_out[1]; - assign router_14_2_to_router_14_1_req = router_14_2_req_out[2]; - assign router_14_2_to_router_13_2_req = router_14_2_req_out[3]; - assign router_14_2_to_magia_tile_ni_14_2_req = router_14_2_req_out[4]; - - assign router_14_2_rsp_in[0] = router_14_3_to_router_14_2_rsp; - assign router_14_2_rsp_in[1] = router_15_2_to_router_14_2_rsp; - assign router_14_2_rsp_in[2] = router_14_1_to_router_14_2_rsp; - assign router_14_2_rsp_in[3] = router_13_2_to_router_14_2_rsp; - assign router_14_2_rsp_in[4] = magia_tile_ni_14_2_to_router_14_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_2_req_in), - .floo_rsp_o (router_14_2_rsp_out), - .floo_req_o (router_14_2_req_out), - .floo_rsp_i (router_14_2_rsp_in) -); - - -floo_req_t [4:0] router_14_3_req_in; -floo_rsp_t [4:0] router_14_3_rsp_out; -floo_req_t [4:0] router_14_3_req_out; -floo_rsp_t [4:0] router_14_3_rsp_in; - - assign router_14_3_req_in[0] = router_14_4_to_router_14_3_req; - assign router_14_3_req_in[1] = router_15_3_to_router_14_3_req; - assign router_14_3_req_in[2] = router_14_2_to_router_14_3_req; - assign router_14_3_req_in[3] = router_13_3_to_router_14_3_req; - assign router_14_3_req_in[4] = magia_tile_ni_14_3_to_router_14_3_req; - - assign router_14_3_to_router_14_4_rsp = router_14_3_rsp_out[0]; - assign router_14_3_to_router_15_3_rsp = router_14_3_rsp_out[1]; - assign router_14_3_to_router_14_2_rsp = router_14_3_rsp_out[2]; - assign router_14_3_to_router_13_3_rsp = router_14_3_rsp_out[3]; - assign router_14_3_to_magia_tile_ni_14_3_rsp = router_14_3_rsp_out[4]; - - assign router_14_3_to_router_14_4_req = router_14_3_req_out[0]; - assign router_14_3_to_router_15_3_req = router_14_3_req_out[1]; - assign router_14_3_to_router_14_2_req = router_14_3_req_out[2]; - assign router_14_3_to_router_13_3_req = router_14_3_req_out[3]; - assign router_14_3_to_magia_tile_ni_14_3_req = router_14_3_req_out[4]; - - assign router_14_3_rsp_in[0] = router_14_4_to_router_14_3_rsp; - assign router_14_3_rsp_in[1] = router_15_3_to_router_14_3_rsp; - assign router_14_3_rsp_in[2] = router_14_2_to_router_14_3_rsp; - assign router_14_3_rsp_in[3] = router_13_3_to_router_14_3_rsp; - assign router_14_3_rsp_in[4] = magia_tile_ni_14_3_to_router_14_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_3_req_in), - .floo_rsp_o (router_14_3_rsp_out), - .floo_req_o (router_14_3_req_out), - .floo_rsp_i (router_14_3_rsp_in) -); - - -floo_req_t [4:0] router_14_4_req_in; -floo_rsp_t [4:0] router_14_4_rsp_out; -floo_req_t [4:0] router_14_4_req_out; -floo_rsp_t [4:0] router_14_4_rsp_in; - - assign router_14_4_req_in[0] = router_14_5_to_router_14_4_req; - assign router_14_4_req_in[1] = router_15_4_to_router_14_4_req; - assign router_14_4_req_in[2] = router_14_3_to_router_14_4_req; - assign router_14_4_req_in[3] = router_13_4_to_router_14_4_req; - assign router_14_4_req_in[4] = magia_tile_ni_14_4_to_router_14_4_req; - - assign router_14_4_to_router_14_5_rsp = router_14_4_rsp_out[0]; - assign router_14_4_to_router_15_4_rsp = router_14_4_rsp_out[1]; - assign router_14_4_to_router_14_3_rsp = router_14_4_rsp_out[2]; - assign router_14_4_to_router_13_4_rsp = router_14_4_rsp_out[3]; - assign router_14_4_to_magia_tile_ni_14_4_rsp = router_14_4_rsp_out[4]; - - assign router_14_4_to_router_14_5_req = router_14_4_req_out[0]; - assign router_14_4_to_router_15_4_req = router_14_4_req_out[1]; - assign router_14_4_to_router_14_3_req = router_14_4_req_out[2]; - assign router_14_4_to_router_13_4_req = router_14_4_req_out[3]; - assign router_14_4_to_magia_tile_ni_14_4_req = router_14_4_req_out[4]; - - assign router_14_4_rsp_in[0] = router_14_5_to_router_14_4_rsp; - assign router_14_4_rsp_in[1] = router_15_4_to_router_14_4_rsp; - assign router_14_4_rsp_in[2] = router_14_3_to_router_14_4_rsp; - assign router_14_4_rsp_in[3] = router_13_4_to_router_14_4_rsp; - assign router_14_4_rsp_in[4] = magia_tile_ni_14_4_to_router_14_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_4_req_in), - .floo_rsp_o (router_14_4_rsp_out), - .floo_req_o (router_14_4_req_out), - .floo_rsp_i (router_14_4_rsp_in) -); - - -floo_req_t [4:0] router_14_5_req_in; -floo_rsp_t [4:0] router_14_5_rsp_out; -floo_req_t [4:0] router_14_5_req_out; -floo_rsp_t [4:0] router_14_5_rsp_in; - - assign router_14_5_req_in[0] = router_14_6_to_router_14_5_req; - assign router_14_5_req_in[1] = router_15_5_to_router_14_5_req; - assign router_14_5_req_in[2] = router_14_4_to_router_14_5_req; - assign router_14_5_req_in[3] = router_13_5_to_router_14_5_req; - assign router_14_5_req_in[4] = magia_tile_ni_14_5_to_router_14_5_req; - - assign router_14_5_to_router_14_6_rsp = router_14_5_rsp_out[0]; - assign router_14_5_to_router_15_5_rsp = router_14_5_rsp_out[1]; - assign router_14_5_to_router_14_4_rsp = router_14_5_rsp_out[2]; - assign router_14_5_to_router_13_5_rsp = router_14_5_rsp_out[3]; - assign router_14_5_to_magia_tile_ni_14_5_rsp = router_14_5_rsp_out[4]; - - assign router_14_5_to_router_14_6_req = router_14_5_req_out[0]; - assign router_14_5_to_router_15_5_req = router_14_5_req_out[1]; - assign router_14_5_to_router_14_4_req = router_14_5_req_out[2]; - assign router_14_5_to_router_13_5_req = router_14_5_req_out[3]; - assign router_14_5_to_magia_tile_ni_14_5_req = router_14_5_req_out[4]; - - assign router_14_5_rsp_in[0] = router_14_6_to_router_14_5_rsp; - assign router_14_5_rsp_in[1] = router_15_5_to_router_14_5_rsp; - assign router_14_5_rsp_in[2] = router_14_4_to_router_14_5_rsp; - assign router_14_5_rsp_in[3] = router_13_5_to_router_14_5_rsp; - assign router_14_5_rsp_in[4] = magia_tile_ni_14_5_to_router_14_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_5_req_in), - .floo_rsp_o (router_14_5_rsp_out), - .floo_req_o (router_14_5_req_out), - .floo_rsp_i (router_14_5_rsp_in) -); - - -floo_req_t [4:0] router_14_6_req_in; -floo_rsp_t [4:0] router_14_6_rsp_out; -floo_req_t [4:0] router_14_6_req_out; -floo_rsp_t [4:0] router_14_6_rsp_in; - - assign router_14_6_req_in[0] = router_14_7_to_router_14_6_req; - assign router_14_6_req_in[1] = router_15_6_to_router_14_6_req; - assign router_14_6_req_in[2] = router_14_5_to_router_14_6_req; - assign router_14_6_req_in[3] = router_13_6_to_router_14_6_req; - assign router_14_6_req_in[4] = magia_tile_ni_14_6_to_router_14_6_req; - - assign router_14_6_to_router_14_7_rsp = router_14_6_rsp_out[0]; - assign router_14_6_to_router_15_6_rsp = router_14_6_rsp_out[1]; - assign router_14_6_to_router_14_5_rsp = router_14_6_rsp_out[2]; - assign router_14_6_to_router_13_6_rsp = router_14_6_rsp_out[3]; - assign router_14_6_to_magia_tile_ni_14_6_rsp = router_14_6_rsp_out[4]; - - assign router_14_6_to_router_14_7_req = router_14_6_req_out[0]; - assign router_14_6_to_router_15_6_req = router_14_6_req_out[1]; - assign router_14_6_to_router_14_5_req = router_14_6_req_out[2]; - assign router_14_6_to_router_13_6_req = router_14_6_req_out[3]; - assign router_14_6_to_magia_tile_ni_14_6_req = router_14_6_req_out[4]; - - assign router_14_6_rsp_in[0] = router_14_7_to_router_14_6_rsp; - assign router_14_6_rsp_in[1] = router_15_6_to_router_14_6_rsp; - assign router_14_6_rsp_in[2] = router_14_5_to_router_14_6_rsp; - assign router_14_6_rsp_in[3] = router_13_6_to_router_14_6_rsp; - assign router_14_6_rsp_in[4] = magia_tile_ni_14_6_to_router_14_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_6_req_in), - .floo_rsp_o (router_14_6_rsp_out), - .floo_req_o (router_14_6_req_out), - .floo_rsp_i (router_14_6_rsp_in) -); - - -floo_req_t [4:0] router_14_7_req_in; -floo_rsp_t [4:0] router_14_7_rsp_out; -floo_req_t [4:0] router_14_7_req_out; -floo_rsp_t [4:0] router_14_7_rsp_in; - - assign router_14_7_req_in[0] = router_14_8_to_router_14_7_req; - assign router_14_7_req_in[1] = router_15_7_to_router_14_7_req; - assign router_14_7_req_in[2] = router_14_6_to_router_14_7_req; - assign router_14_7_req_in[3] = router_13_7_to_router_14_7_req; - assign router_14_7_req_in[4] = magia_tile_ni_14_7_to_router_14_7_req; - - assign router_14_7_to_router_14_8_rsp = router_14_7_rsp_out[0]; - assign router_14_7_to_router_15_7_rsp = router_14_7_rsp_out[1]; - assign router_14_7_to_router_14_6_rsp = router_14_7_rsp_out[2]; - assign router_14_7_to_router_13_7_rsp = router_14_7_rsp_out[3]; - assign router_14_7_to_magia_tile_ni_14_7_rsp = router_14_7_rsp_out[4]; - - assign router_14_7_to_router_14_8_req = router_14_7_req_out[0]; - assign router_14_7_to_router_15_7_req = router_14_7_req_out[1]; - assign router_14_7_to_router_14_6_req = router_14_7_req_out[2]; - assign router_14_7_to_router_13_7_req = router_14_7_req_out[3]; - assign router_14_7_to_magia_tile_ni_14_7_req = router_14_7_req_out[4]; - - assign router_14_7_rsp_in[0] = router_14_8_to_router_14_7_rsp; - assign router_14_7_rsp_in[1] = router_15_7_to_router_14_7_rsp; - assign router_14_7_rsp_in[2] = router_14_6_to_router_14_7_rsp; - assign router_14_7_rsp_in[3] = router_13_7_to_router_14_7_rsp; - assign router_14_7_rsp_in[4] = magia_tile_ni_14_7_to_router_14_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_7_req_in), - .floo_rsp_o (router_14_7_rsp_out), - .floo_req_o (router_14_7_req_out), - .floo_rsp_i (router_14_7_rsp_in) -); - - -floo_req_t [4:0] router_14_8_req_in; -floo_rsp_t [4:0] router_14_8_rsp_out; -floo_req_t [4:0] router_14_8_req_out; -floo_rsp_t [4:0] router_14_8_rsp_in; - - assign router_14_8_req_in[0] = router_14_9_to_router_14_8_req; - assign router_14_8_req_in[1] = router_15_8_to_router_14_8_req; - assign router_14_8_req_in[2] = router_14_7_to_router_14_8_req; - assign router_14_8_req_in[3] = router_13_8_to_router_14_8_req; - assign router_14_8_req_in[4] = magia_tile_ni_14_8_to_router_14_8_req; - - assign router_14_8_to_router_14_9_rsp = router_14_8_rsp_out[0]; - assign router_14_8_to_router_15_8_rsp = router_14_8_rsp_out[1]; - assign router_14_8_to_router_14_7_rsp = router_14_8_rsp_out[2]; - assign router_14_8_to_router_13_8_rsp = router_14_8_rsp_out[3]; - assign router_14_8_to_magia_tile_ni_14_8_rsp = router_14_8_rsp_out[4]; - - assign router_14_8_to_router_14_9_req = router_14_8_req_out[0]; - assign router_14_8_to_router_15_8_req = router_14_8_req_out[1]; - assign router_14_8_to_router_14_7_req = router_14_8_req_out[2]; - assign router_14_8_to_router_13_8_req = router_14_8_req_out[3]; - assign router_14_8_to_magia_tile_ni_14_8_req = router_14_8_req_out[4]; - - assign router_14_8_rsp_in[0] = router_14_9_to_router_14_8_rsp; - assign router_14_8_rsp_in[1] = router_15_8_to_router_14_8_rsp; - assign router_14_8_rsp_in[2] = router_14_7_to_router_14_8_rsp; - assign router_14_8_rsp_in[3] = router_13_8_to_router_14_8_rsp; - assign router_14_8_rsp_in[4] = magia_tile_ni_14_8_to_router_14_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_8_req_in), - .floo_rsp_o (router_14_8_rsp_out), - .floo_req_o (router_14_8_req_out), - .floo_rsp_i (router_14_8_rsp_in) -); - - -floo_req_t [4:0] router_14_9_req_in; -floo_rsp_t [4:0] router_14_9_rsp_out; -floo_req_t [4:0] router_14_9_req_out; -floo_rsp_t [4:0] router_14_9_rsp_in; - - assign router_14_9_req_in[0] = router_14_10_to_router_14_9_req; - assign router_14_9_req_in[1] = router_15_9_to_router_14_9_req; - assign router_14_9_req_in[2] = router_14_8_to_router_14_9_req; - assign router_14_9_req_in[3] = router_13_9_to_router_14_9_req; - assign router_14_9_req_in[4] = magia_tile_ni_14_9_to_router_14_9_req; - - assign router_14_9_to_router_14_10_rsp = router_14_9_rsp_out[0]; - assign router_14_9_to_router_15_9_rsp = router_14_9_rsp_out[1]; - assign router_14_9_to_router_14_8_rsp = router_14_9_rsp_out[2]; - assign router_14_9_to_router_13_9_rsp = router_14_9_rsp_out[3]; - assign router_14_9_to_magia_tile_ni_14_9_rsp = router_14_9_rsp_out[4]; - - assign router_14_9_to_router_14_10_req = router_14_9_req_out[0]; - assign router_14_9_to_router_15_9_req = router_14_9_req_out[1]; - assign router_14_9_to_router_14_8_req = router_14_9_req_out[2]; - assign router_14_9_to_router_13_9_req = router_14_9_req_out[3]; - assign router_14_9_to_magia_tile_ni_14_9_req = router_14_9_req_out[4]; - - assign router_14_9_rsp_in[0] = router_14_10_to_router_14_9_rsp; - assign router_14_9_rsp_in[1] = router_15_9_to_router_14_9_rsp; - assign router_14_9_rsp_in[2] = router_14_8_to_router_14_9_rsp; - assign router_14_9_rsp_in[3] = router_13_9_to_router_14_9_rsp; - assign router_14_9_rsp_in[4] = magia_tile_ni_14_9_to_router_14_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_9_req_in), - .floo_rsp_o (router_14_9_rsp_out), - .floo_req_o (router_14_9_req_out), - .floo_rsp_i (router_14_9_rsp_in) -); - - -floo_req_t [4:0] router_14_10_req_in; -floo_rsp_t [4:0] router_14_10_rsp_out; -floo_req_t [4:0] router_14_10_req_out; -floo_rsp_t [4:0] router_14_10_rsp_in; - - assign router_14_10_req_in[0] = router_14_11_to_router_14_10_req; - assign router_14_10_req_in[1] = router_15_10_to_router_14_10_req; - assign router_14_10_req_in[2] = router_14_9_to_router_14_10_req; - assign router_14_10_req_in[3] = router_13_10_to_router_14_10_req; - assign router_14_10_req_in[4] = magia_tile_ni_14_10_to_router_14_10_req; - - assign router_14_10_to_router_14_11_rsp = router_14_10_rsp_out[0]; - assign router_14_10_to_router_15_10_rsp = router_14_10_rsp_out[1]; - assign router_14_10_to_router_14_9_rsp = router_14_10_rsp_out[2]; - assign router_14_10_to_router_13_10_rsp = router_14_10_rsp_out[3]; - assign router_14_10_to_magia_tile_ni_14_10_rsp = router_14_10_rsp_out[4]; - - assign router_14_10_to_router_14_11_req = router_14_10_req_out[0]; - assign router_14_10_to_router_15_10_req = router_14_10_req_out[1]; - assign router_14_10_to_router_14_9_req = router_14_10_req_out[2]; - assign router_14_10_to_router_13_10_req = router_14_10_req_out[3]; - assign router_14_10_to_magia_tile_ni_14_10_req = router_14_10_req_out[4]; - - assign router_14_10_rsp_in[0] = router_14_11_to_router_14_10_rsp; - assign router_14_10_rsp_in[1] = router_15_10_to_router_14_10_rsp; - assign router_14_10_rsp_in[2] = router_14_9_to_router_14_10_rsp; - assign router_14_10_rsp_in[3] = router_13_10_to_router_14_10_rsp; - assign router_14_10_rsp_in[4] = magia_tile_ni_14_10_to_router_14_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_10_req_in), - .floo_rsp_o (router_14_10_rsp_out), - .floo_req_o (router_14_10_req_out), - .floo_rsp_i (router_14_10_rsp_in) -); - - -floo_req_t [4:0] router_14_11_req_in; -floo_rsp_t [4:0] router_14_11_rsp_out; -floo_req_t [4:0] router_14_11_req_out; -floo_rsp_t [4:0] router_14_11_rsp_in; - - assign router_14_11_req_in[0] = router_14_12_to_router_14_11_req; - assign router_14_11_req_in[1] = router_15_11_to_router_14_11_req; - assign router_14_11_req_in[2] = router_14_10_to_router_14_11_req; - assign router_14_11_req_in[3] = router_13_11_to_router_14_11_req; - assign router_14_11_req_in[4] = magia_tile_ni_14_11_to_router_14_11_req; - - assign router_14_11_to_router_14_12_rsp = router_14_11_rsp_out[0]; - assign router_14_11_to_router_15_11_rsp = router_14_11_rsp_out[1]; - assign router_14_11_to_router_14_10_rsp = router_14_11_rsp_out[2]; - assign router_14_11_to_router_13_11_rsp = router_14_11_rsp_out[3]; - assign router_14_11_to_magia_tile_ni_14_11_rsp = router_14_11_rsp_out[4]; - - assign router_14_11_to_router_14_12_req = router_14_11_req_out[0]; - assign router_14_11_to_router_15_11_req = router_14_11_req_out[1]; - assign router_14_11_to_router_14_10_req = router_14_11_req_out[2]; - assign router_14_11_to_router_13_11_req = router_14_11_req_out[3]; - assign router_14_11_to_magia_tile_ni_14_11_req = router_14_11_req_out[4]; - - assign router_14_11_rsp_in[0] = router_14_12_to_router_14_11_rsp; - assign router_14_11_rsp_in[1] = router_15_11_to_router_14_11_rsp; - assign router_14_11_rsp_in[2] = router_14_10_to_router_14_11_rsp; - assign router_14_11_rsp_in[3] = router_13_11_to_router_14_11_rsp; - assign router_14_11_rsp_in[4] = magia_tile_ni_14_11_to_router_14_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_11_req_in), - .floo_rsp_o (router_14_11_rsp_out), - .floo_req_o (router_14_11_req_out), - .floo_rsp_i (router_14_11_rsp_in) -); - - -floo_req_t [4:0] router_14_12_req_in; -floo_rsp_t [4:0] router_14_12_rsp_out; -floo_req_t [4:0] router_14_12_req_out; -floo_rsp_t [4:0] router_14_12_rsp_in; - - assign router_14_12_req_in[0] = router_14_13_to_router_14_12_req; - assign router_14_12_req_in[1] = router_15_12_to_router_14_12_req; - assign router_14_12_req_in[2] = router_14_11_to_router_14_12_req; - assign router_14_12_req_in[3] = router_13_12_to_router_14_12_req; - assign router_14_12_req_in[4] = magia_tile_ni_14_12_to_router_14_12_req; - - assign router_14_12_to_router_14_13_rsp = router_14_12_rsp_out[0]; - assign router_14_12_to_router_15_12_rsp = router_14_12_rsp_out[1]; - assign router_14_12_to_router_14_11_rsp = router_14_12_rsp_out[2]; - assign router_14_12_to_router_13_12_rsp = router_14_12_rsp_out[3]; - assign router_14_12_to_magia_tile_ni_14_12_rsp = router_14_12_rsp_out[4]; - - assign router_14_12_to_router_14_13_req = router_14_12_req_out[0]; - assign router_14_12_to_router_15_12_req = router_14_12_req_out[1]; - assign router_14_12_to_router_14_11_req = router_14_12_req_out[2]; - assign router_14_12_to_router_13_12_req = router_14_12_req_out[3]; - assign router_14_12_to_magia_tile_ni_14_12_req = router_14_12_req_out[4]; - - assign router_14_12_rsp_in[0] = router_14_13_to_router_14_12_rsp; - assign router_14_12_rsp_in[1] = router_15_12_to_router_14_12_rsp; - assign router_14_12_rsp_in[2] = router_14_11_to_router_14_12_rsp; - assign router_14_12_rsp_in[3] = router_13_12_to_router_14_12_rsp; - assign router_14_12_rsp_in[4] = magia_tile_ni_14_12_to_router_14_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_12_req_in), - .floo_rsp_o (router_14_12_rsp_out), - .floo_req_o (router_14_12_req_out), - .floo_rsp_i (router_14_12_rsp_in) -); - - -floo_req_t [4:0] router_14_13_req_in; -floo_rsp_t [4:0] router_14_13_rsp_out; -floo_req_t [4:0] router_14_13_req_out; -floo_rsp_t [4:0] router_14_13_rsp_in; - - assign router_14_13_req_in[0] = router_14_14_to_router_14_13_req; - assign router_14_13_req_in[1] = router_15_13_to_router_14_13_req; - assign router_14_13_req_in[2] = router_14_12_to_router_14_13_req; - assign router_14_13_req_in[3] = router_13_13_to_router_14_13_req; - assign router_14_13_req_in[4] = magia_tile_ni_14_13_to_router_14_13_req; - - assign router_14_13_to_router_14_14_rsp = router_14_13_rsp_out[0]; - assign router_14_13_to_router_15_13_rsp = router_14_13_rsp_out[1]; - assign router_14_13_to_router_14_12_rsp = router_14_13_rsp_out[2]; - assign router_14_13_to_router_13_13_rsp = router_14_13_rsp_out[3]; - assign router_14_13_to_magia_tile_ni_14_13_rsp = router_14_13_rsp_out[4]; - - assign router_14_13_to_router_14_14_req = router_14_13_req_out[0]; - assign router_14_13_to_router_15_13_req = router_14_13_req_out[1]; - assign router_14_13_to_router_14_12_req = router_14_13_req_out[2]; - assign router_14_13_to_router_13_13_req = router_14_13_req_out[3]; - assign router_14_13_to_magia_tile_ni_14_13_req = router_14_13_req_out[4]; - - assign router_14_13_rsp_in[0] = router_14_14_to_router_14_13_rsp; - assign router_14_13_rsp_in[1] = router_15_13_to_router_14_13_rsp; - assign router_14_13_rsp_in[2] = router_14_12_to_router_14_13_rsp; - assign router_14_13_rsp_in[3] = router_13_13_to_router_14_13_rsp; - assign router_14_13_rsp_in[4] = magia_tile_ni_14_13_to_router_14_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_13_req_in), - .floo_rsp_o (router_14_13_rsp_out), - .floo_req_o (router_14_13_req_out), - .floo_rsp_i (router_14_13_rsp_in) -); - - -floo_req_t [4:0] router_14_14_req_in; -floo_rsp_t [4:0] router_14_14_rsp_out; -floo_req_t [4:0] router_14_14_req_out; -floo_rsp_t [4:0] router_14_14_rsp_in; - - assign router_14_14_req_in[0] = router_14_15_to_router_14_14_req; - assign router_14_14_req_in[1] = router_15_14_to_router_14_14_req; - assign router_14_14_req_in[2] = router_14_13_to_router_14_14_req; - assign router_14_14_req_in[3] = router_13_14_to_router_14_14_req; - assign router_14_14_req_in[4] = magia_tile_ni_14_14_to_router_14_14_req; - - assign router_14_14_to_router_14_15_rsp = router_14_14_rsp_out[0]; - assign router_14_14_to_router_15_14_rsp = router_14_14_rsp_out[1]; - assign router_14_14_to_router_14_13_rsp = router_14_14_rsp_out[2]; - assign router_14_14_to_router_13_14_rsp = router_14_14_rsp_out[3]; - assign router_14_14_to_magia_tile_ni_14_14_rsp = router_14_14_rsp_out[4]; - - assign router_14_14_to_router_14_15_req = router_14_14_req_out[0]; - assign router_14_14_to_router_15_14_req = router_14_14_req_out[1]; - assign router_14_14_to_router_14_13_req = router_14_14_req_out[2]; - assign router_14_14_to_router_13_14_req = router_14_14_req_out[3]; - assign router_14_14_to_magia_tile_ni_14_14_req = router_14_14_req_out[4]; - - assign router_14_14_rsp_in[0] = router_14_15_to_router_14_14_rsp; - assign router_14_14_rsp_in[1] = router_15_14_to_router_14_14_rsp; - assign router_14_14_rsp_in[2] = router_14_13_to_router_14_14_rsp; - assign router_14_14_rsp_in[3] = router_13_14_to_router_14_14_rsp; - assign router_14_14_rsp_in[4] = magia_tile_ni_14_14_to_router_14_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_14_req_in), - .floo_rsp_o (router_14_14_rsp_out), - .floo_req_o (router_14_14_req_out), - .floo_rsp_i (router_14_14_rsp_in) -); - - -floo_req_t [4:0] router_14_15_req_in; -floo_rsp_t [4:0] router_14_15_rsp_out; -floo_req_t [4:0] router_14_15_req_out; -floo_rsp_t [4:0] router_14_15_rsp_in; - - assign router_14_15_req_in[0] = router_14_16_to_router_14_15_req; - assign router_14_15_req_in[1] = router_15_15_to_router_14_15_req; - assign router_14_15_req_in[2] = router_14_14_to_router_14_15_req; - assign router_14_15_req_in[3] = router_13_15_to_router_14_15_req; - assign router_14_15_req_in[4] = magia_tile_ni_14_15_to_router_14_15_req; - - assign router_14_15_to_router_14_16_rsp = router_14_15_rsp_out[0]; - assign router_14_15_to_router_15_15_rsp = router_14_15_rsp_out[1]; - assign router_14_15_to_router_14_14_rsp = router_14_15_rsp_out[2]; - assign router_14_15_to_router_13_15_rsp = router_14_15_rsp_out[3]; - assign router_14_15_to_magia_tile_ni_14_15_rsp = router_14_15_rsp_out[4]; - - assign router_14_15_to_router_14_16_req = router_14_15_req_out[0]; - assign router_14_15_to_router_15_15_req = router_14_15_req_out[1]; - assign router_14_15_to_router_14_14_req = router_14_15_req_out[2]; - assign router_14_15_to_router_13_15_req = router_14_15_req_out[3]; - assign router_14_15_to_magia_tile_ni_14_15_req = router_14_15_req_out[4]; - - assign router_14_15_rsp_in[0] = router_14_16_to_router_14_15_rsp; - assign router_14_15_rsp_in[1] = router_15_15_to_router_14_15_rsp; - assign router_14_15_rsp_in[2] = router_14_14_to_router_14_15_rsp; - assign router_14_15_rsp_in[3] = router_13_15_to_router_14_15_rsp; - assign router_14_15_rsp_in[4] = magia_tile_ni_14_15_to_router_14_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_15_req_in), - .floo_rsp_o (router_14_15_rsp_out), - .floo_req_o (router_14_15_req_out), - .floo_rsp_i (router_14_15_rsp_in) -); - - -floo_req_t [4:0] router_14_16_req_in; -floo_rsp_t [4:0] router_14_16_rsp_out; -floo_req_t [4:0] router_14_16_req_out; -floo_rsp_t [4:0] router_14_16_rsp_in; - - assign router_14_16_req_in[0] = router_14_17_to_router_14_16_req; - assign router_14_16_req_in[1] = router_15_16_to_router_14_16_req; - assign router_14_16_req_in[2] = router_14_15_to_router_14_16_req; - assign router_14_16_req_in[3] = router_13_16_to_router_14_16_req; - assign router_14_16_req_in[4] = magia_tile_ni_14_16_to_router_14_16_req; - - assign router_14_16_to_router_14_17_rsp = router_14_16_rsp_out[0]; - assign router_14_16_to_router_15_16_rsp = router_14_16_rsp_out[1]; - assign router_14_16_to_router_14_15_rsp = router_14_16_rsp_out[2]; - assign router_14_16_to_router_13_16_rsp = router_14_16_rsp_out[3]; - assign router_14_16_to_magia_tile_ni_14_16_rsp = router_14_16_rsp_out[4]; - - assign router_14_16_to_router_14_17_req = router_14_16_req_out[0]; - assign router_14_16_to_router_15_16_req = router_14_16_req_out[1]; - assign router_14_16_to_router_14_15_req = router_14_16_req_out[2]; - assign router_14_16_to_router_13_16_req = router_14_16_req_out[3]; - assign router_14_16_to_magia_tile_ni_14_16_req = router_14_16_req_out[4]; - - assign router_14_16_rsp_in[0] = router_14_17_to_router_14_16_rsp; - assign router_14_16_rsp_in[1] = router_15_16_to_router_14_16_rsp; - assign router_14_16_rsp_in[2] = router_14_15_to_router_14_16_rsp; - assign router_14_16_rsp_in[3] = router_13_16_to_router_14_16_rsp; - assign router_14_16_rsp_in[4] = magia_tile_ni_14_16_to_router_14_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_16_req_in), - .floo_rsp_o (router_14_16_rsp_out), - .floo_req_o (router_14_16_req_out), - .floo_rsp_i (router_14_16_rsp_in) -); - - -floo_req_t [4:0] router_14_17_req_in; -floo_rsp_t [4:0] router_14_17_rsp_out; -floo_req_t [4:0] router_14_17_req_out; -floo_rsp_t [4:0] router_14_17_rsp_in; - - assign router_14_17_req_in[0] = router_14_18_to_router_14_17_req; - assign router_14_17_req_in[1] = router_15_17_to_router_14_17_req; - assign router_14_17_req_in[2] = router_14_16_to_router_14_17_req; - assign router_14_17_req_in[3] = router_13_17_to_router_14_17_req; - assign router_14_17_req_in[4] = magia_tile_ni_14_17_to_router_14_17_req; - - assign router_14_17_to_router_14_18_rsp = router_14_17_rsp_out[0]; - assign router_14_17_to_router_15_17_rsp = router_14_17_rsp_out[1]; - assign router_14_17_to_router_14_16_rsp = router_14_17_rsp_out[2]; - assign router_14_17_to_router_13_17_rsp = router_14_17_rsp_out[3]; - assign router_14_17_to_magia_tile_ni_14_17_rsp = router_14_17_rsp_out[4]; - - assign router_14_17_to_router_14_18_req = router_14_17_req_out[0]; - assign router_14_17_to_router_15_17_req = router_14_17_req_out[1]; - assign router_14_17_to_router_14_16_req = router_14_17_req_out[2]; - assign router_14_17_to_router_13_17_req = router_14_17_req_out[3]; - assign router_14_17_to_magia_tile_ni_14_17_req = router_14_17_req_out[4]; - - assign router_14_17_rsp_in[0] = router_14_18_to_router_14_17_rsp; - assign router_14_17_rsp_in[1] = router_15_17_to_router_14_17_rsp; - assign router_14_17_rsp_in[2] = router_14_16_to_router_14_17_rsp; - assign router_14_17_rsp_in[3] = router_13_17_to_router_14_17_rsp; - assign router_14_17_rsp_in[4] = magia_tile_ni_14_17_to_router_14_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_17_req_in), - .floo_rsp_o (router_14_17_rsp_out), - .floo_req_o (router_14_17_req_out), - .floo_rsp_i (router_14_17_rsp_in) -); - - -floo_req_t [4:0] router_14_18_req_in; -floo_rsp_t [4:0] router_14_18_rsp_out; -floo_req_t [4:0] router_14_18_req_out; -floo_rsp_t [4:0] router_14_18_rsp_in; - - assign router_14_18_req_in[0] = router_14_19_to_router_14_18_req; - assign router_14_18_req_in[1] = router_15_18_to_router_14_18_req; - assign router_14_18_req_in[2] = router_14_17_to_router_14_18_req; - assign router_14_18_req_in[3] = router_13_18_to_router_14_18_req; - assign router_14_18_req_in[4] = magia_tile_ni_14_18_to_router_14_18_req; - - assign router_14_18_to_router_14_19_rsp = router_14_18_rsp_out[0]; - assign router_14_18_to_router_15_18_rsp = router_14_18_rsp_out[1]; - assign router_14_18_to_router_14_17_rsp = router_14_18_rsp_out[2]; - assign router_14_18_to_router_13_18_rsp = router_14_18_rsp_out[3]; - assign router_14_18_to_magia_tile_ni_14_18_rsp = router_14_18_rsp_out[4]; - - assign router_14_18_to_router_14_19_req = router_14_18_req_out[0]; - assign router_14_18_to_router_15_18_req = router_14_18_req_out[1]; - assign router_14_18_to_router_14_17_req = router_14_18_req_out[2]; - assign router_14_18_to_router_13_18_req = router_14_18_req_out[3]; - assign router_14_18_to_magia_tile_ni_14_18_req = router_14_18_req_out[4]; - - assign router_14_18_rsp_in[0] = router_14_19_to_router_14_18_rsp; - assign router_14_18_rsp_in[1] = router_15_18_to_router_14_18_rsp; - assign router_14_18_rsp_in[2] = router_14_17_to_router_14_18_rsp; - assign router_14_18_rsp_in[3] = router_13_18_to_router_14_18_rsp; - assign router_14_18_rsp_in[4] = magia_tile_ni_14_18_to_router_14_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_18_req_in), - .floo_rsp_o (router_14_18_rsp_out), - .floo_req_o (router_14_18_req_out), - .floo_rsp_i (router_14_18_rsp_in) -); - - -floo_req_t [4:0] router_14_19_req_in; -floo_rsp_t [4:0] router_14_19_rsp_out; -floo_req_t [4:0] router_14_19_req_out; -floo_rsp_t [4:0] router_14_19_rsp_in; - - assign router_14_19_req_in[0] = router_14_20_to_router_14_19_req; - assign router_14_19_req_in[1] = router_15_19_to_router_14_19_req; - assign router_14_19_req_in[2] = router_14_18_to_router_14_19_req; - assign router_14_19_req_in[3] = router_13_19_to_router_14_19_req; - assign router_14_19_req_in[4] = magia_tile_ni_14_19_to_router_14_19_req; - - assign router_14_19_to_router_14_20_rsp = router_14_19_rsp_out[0]; - assign router_14_19_to_router_15_19_rsp = router_14_19_rsp_out[1]; - assign router_14_19_to_router_14_18_rsp = router_14_19_rsp_out[2]; - assign router_14_19_to_router_13_19_rsp = router_14_19_rsp_out[3]; - assign router_14_19_to_magia_tile_ni_14_19_rsp = router_14_19_rsp_out[4]; - - assign router_14_19_to_router_14_20_req = router_14_19_req_out[0]; - assign router_14_19_to_router_15_19_req = router_14_19_req_out[1]; - assign router_14_19_to_router_14_18_req = router_14_19_req_out[2]; - assign router_14_19_to_router_13_19_req = router_14_19_req_out[3]; - assign router_14_19_to_magia_tile_ni_14_19_req = router_14_19_req_out[4]; - - assign router_14_19_rsp_in[0] = router_14_20_to_router_14_19_rsp; - assign router_14_19_rsp_in[1] = router_15_19_to_router_14_19_rsp; - assign router_14_19_rsp_in[2] = router_14_18_to_router_14_19_rsp; - assign router_14_19_rsp_in[3] = router_13_19_to_router_14_19_rsp; - assign router_14_19_rsp_in[4] = magia_tile_ni_14_19_to_router_14_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_19_req_in), - .floo_rsp_o (router_14_19_rsp_out), - .floo_req_o (router_14_19_req_out), - .floo_rsp_i (router_14_19_rsp_in) -); - - -floo_req_t [4:0] router_14_20_req_in; -floo_rsp_t [4:0] router_14_20_rsp_out; -floo_req_t [4:0] router_14_20_req_out; -floo_rsp_t [4:0] router_14_20_rsp_in; - - assign router_14_20_req_in[0] = router_14_21_to_router_14_20_req; - assign router_14_20_req_in[1] = router_15_20_to_router_14_20_req; - assign router_14_20_req_in[2] = router_14_19_to_router_14_20_req; - assign router_14_20_req_in[3] = router_13_20_to_router_14_20_req; - assign router_14_20_req_in[4] = magia_tile_ni_14_20_to_router_14_20_req; - - assign router_14_20_to_router_14_21_rsp = router_14_20_rsp_out[0]; - assign router_14_20_to_router_15_20_rsp = router_14_20_rsp_out[1]; - assign router_14_20_to_router_14_19_rsp = router_14_20_rsp_out[2]; - assign router_14_20_to_router_13_20_rsp = router_14_20_rsp_out[3]; - assign router_14_20_to_magia_tile_ni_14_20_rsp = router_14_20_rsp_out[4]; - - assign router_14_20_to_router_14_21_req = router_14_20_req_out[0]; - assign router_14_20_to_router_15_20_req = router_14_20_req_out[1]; - assign router_14_20_to_router_14_19_req = router_14_20_req_out[2]; - assign router_14_20_to_router_13_20_req = router_14_20_req_out[3]; - assign router_14_20_to_magia_tile_ni_14_20_req = router_14_20_req_out[4]; - - assign router_14_20_rsp_in[0] = router_14_21_to_router_14_20_rsp; - assign router_14_20_rsp_in[1] = router_15_20_to_router_14_20_rsp; - assign router_14_20_rsp_in[2] = router_14_19_to_router_14_20_rsp; - assign router_14_20_rsp_in[3] = router_13_20_to_router_14_20_rsp; - assign router_14_20_rsp_in[4] = magia_tile_ni_14_20_to_router_14_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_20_req_in), - .floo_rsp_o (router_14_20_rsp_out), - .floo_req_o (router_14_20_req_out), - .floo_rsp_i (router_14_20_rsp_in) -); - - -floo_req_t [4:0] router_14_21_req_in; -floo_rsp_t [4:0] router_14_21_rsp_out; -floo_req_t [4:0] router_14_21_req_out; -floo_rsp_t [4:0] router_14_21_rsp_in; - - assign router_14_21_req_in[0] = router_14_22_to_router_14_21_req; - assign router_14_21_req_in[1] = router_15_21_to_router_14_21_req; - assign router_14_21_req_in[2] = router_14_20_to_router_14_21_req; - assign router_14_21_req_in[3] = router_13_21_to_router_14_21_req; - assign router_14_21_req_in[4] = magia_tile_ni_14_21_to_router_14_21_req; - - assign router_14_21_to_router_14_22_rsp = router_14_21_rsp_out[0]; - assign router_14_21_to_router_15_21_rsp = router_14_21_rsp_out[1]; - assign router_14_21_to_router_14_20_rsp = router_14_21_rsp_out[2]; - assign router_14_21_to_router_13_21_rsp = router_14_21_rsp_out[3]; - assign router_14_21_to_magia_tile_ni_14_21_rsp = router_14_21_rsp_out[4]; - - assign router_14_21_to_router_14_22_req = router_14_21_req_out[0]; - assign router_14_21_to_router_15_21_req = router_14_21_req_out[1]; - assign router_14_21_to_router_14_20_req = router_14_21_req_out[2]; - assign router_14_21_to_router_13_21_req = router_14_21_req_out[3]; - assign router_14_21_to_magia_tile_ni_14_21_req = router_14_21_req_out[4]; - - assign router_14_21_rsp_in[0] = router_14_22_to_router_14_21_rsp; - assign router_14_21_rsp_in[1] = router_15_21_to_router_14_21_rsp; - assign router_14_21_rsp_in[2] = router_14_20_to_router_14_21_rsp; - assign router_14_21_rsp_in[3] = router_13_21_to_router_14_21_rsp; - assign router_14_21_rsp_in[4] = magia_tile_ni_14_21_to_router_14_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_21_req_in), - .floo_rsp_o (router_14_21_rsp_out), - .floo_req_o (router_14_21_req_out), - .floo_rsp_i (router_14_21_rsp_in) -); - - -floo_req_t [4:0] router_14_22_req_in; -floo_rsp_t [4:0] router_14_22_rsp_out; -floo_req_t [4:0] router_14_22_req_out; -floo_rsp_t [4:0] router_14_22_rsp_in; - - assign router_14_22_req_in[0] = router_14_23_to_router_14_22_req; - assign router_14_22_req_in[1] = router_15_22_to_router_14_22_req; - assign router_14_22_req_in[2] = router_14_21_to_router_14_22_req; - assign router_14_22_req_in[3] = router_13_22_to_router_14_22_req; - assign router_14_22_req_in[4] = magia_tile_ni_14_22_to_router_14_22_req; - - assign router_14_22_to_router_14_23_rsp = router_14_22_rsp_out[0]; - assign router_14_22_to_router_15_22_rsp = router_14_22_rsp_out[1]; - assign router_14_22_to_router_14_21_rsp = router_14_22_rsp_out[2]; - assign router_14_22_to_router_13_22_rsp = router_14_22_rsp_out[3]; - assign router_14_22_to_magia_tile_ni_14_22_rsp = router_14_22_rsp_out[4]; - - assign router_14_22_to_router_14_23_req = router_14_22_req_out[0]; - assign router_14_22_to_router_15_22_req = router_14_22_req_out[1]; - assign router_14_22_to_router_14_21_req = router_14_22_req_out[2]; - assign router_14_22_to_router_13_22_req = router_14_22_req_out[3]; - assign router_14_22_to_magia_tile_ni_14_22_req = router_14_22_req_out[4]; - - assign router_14_22_rsp_in[0] = router_14_23_to_router_14_22_rsp; - assign router_14_22_rsp_in[1] = router_15_22_to_router_14_22_rsp; - assign router_14_22_rsp_in[2] = router_14_21_to_router_14_22_rsp; - assign router_14_22_rsp_in[3] = router_13_22_to_router_14_22_rsp; - assign router_14_22_rsp_in[4] = magia_tile_ni_14_22_to_router_14_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_22_req_in), - .floo_rsp_o (router_14_22_rsp_out), - .floo_req_o (router_14_22_req_out), - .floo_rsp_i (router_14_22_rsp_in) -); - - -floo_req_t [4:0] router_14_23_req_in; -floo_rsp_t [4:0] router_14_23_rsp_out; -floo_req_t [4:0] router_14_23_req_out; -floo_rsp_t [4:0] router_14_23_rsp_in; - - assign router_14_23_req_in[0] = router_14_24_to_router_14_23_req; - assign router_14_23_req_in[1] = router_15_23_to_router_14_23_req; - assign router_14_23_req_in[2] = router_14_22_to_router_14_23_req; - assign router_14_23_req_in[3] = router_13_23_to_router_14_23_req; - assign router_14_23_req_in[4] = magia_tile_ni_14_23_to_router_14_23_req; - - assign router_14_23_to_router_14_24_rsp = router_14_23_rsp_out[0]; - assign router_14_23_to_router_15_23_rsp = router_14_23_rsp_out[1]; - assign router_14_23_to_router_14_22_rsp = router_14_23_rsp_out[2]; - assign router_14_23_to_router_13_23_rsp = router_14_23_rsp_out[3]; - assign router_14_23_to_magia_tile_ni_14_23_rsp = router_14_23_rsp_out[4]; - - assign router_14_23_to_router_14_24_req = router_14_23_req_out[0]; - assign router_14_23_to_router_15_23_req = router_14_23_req_out[1]; - assign router_14_23_to_router_14_22_req = router_14_23_req_out[2]; - assign router_14_23_to_router_13_23_req = router_14_23_req_out[3]; - assign router_14_23_to_magia_tile_ni_14_23_req = router_14_23_req_out[4]; - - assign router_14_23_rsp_in[0] = router_14_24_to_router_14_23_rsp; - assign router_14_23_rsp_in[1] = router_15_23_to_router_14_23_rsp; - assign router_14_23_rsp_in[2] = router_14_22_to_router_14_23_rsp; - assign router_14_23_rsp_in[3] = router_13_23_to_router_14_23_rsp; - assign router_14_23_rsp_in[4] = magia_tile_ni_14_23_to_router_14_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_23_req_in), - .floo_rsp_o (router_14_23_rsp_out), - .floo_req_o (router_14_23_req_out), - .floo_rsp_i (router_14_23_rsp_in) -); - - -floo_req_t [4:0] router_14_24_req_in; -floo_rsp_t [4:0] router_14_24_rsp_out; -floo_req_t [4:0] router_14_24_req_out; -floo_rsp_t [4:0] router_14_24_rsp_in; - - assign router_14_24_req_in[0] = router_14_25_to_router_14_24_req; - assign router_14_24_req_in[1] = router_15_24_to_router_14_24_req; - assign router_14_24_req_in[2] = router_14_23_to_router_14_24_req; - assign router_14_24_req_in[3] = router_13_24_to_router_14_24_req; - assign router_14_24_req_in[4] = magia_tile_ni_14_24_to_router_14_24_req; - - assign router_14_24_to_router_14_25_rsp = router_14_24_rsp_out[0]; - assign router_14_24_to_router_15_24_rsp = router_14_24_rsp_out[1]; - assign router_14_24_to_router_14_23_rsp = router_14_24_rsp_out[2]; - assign router_14_24_to_router_13_24_rsp = router_14_24_rsp_out[3]; - assign router_14_24_to_magia_tile_ni_14_24_rsp = router_14_24_rsp_out[4]; - - assign router_14_24_to_router_14_25_req = router_14_24_req_out[0]; - assign router_14_24_to_router_15_24_req = router_14_24_req_out[1]; - assign router_14_24_to_router_14_23_req = router_14_24_req_out[2]; - assign router_14_24_to_router_13_24_req = router_14_24_req_out[3]; - assign router_14_24_to_magia_tile_ni_14_24_req = router_14_24_req_out[4]; - - assign router_14_24_rsp_in[0] = router_14_25_to_router_14_24_rsp; - assign router_14_24_rsp_in[1] = router_15_24_to_router_14_24_rsp; - assign router_14_24_rsp_in[2] = router_14_23_to_router_14_24_rsp; - assign router_14_24_rsp_in[3] = router_13_24_to_router_14_24_rsp; - assign router_14_24_rsp_in[4] = magia_tile_ni_14_24_to_router_14_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_24_req_in), - .floo_rsp_o (router_14_24_rsp_out), - .floo_req_o (router_14_24_req_out), - .floo_rsp_i (router_14_24_rsp_in) -); - - -floo_req_t [4:0] router_14_25_req_in; -floo_rsp_t [4:0] router_14_25_rsp_out; -floo_req_t [4:0] router_14_25_req_out; -floo_rsp_t [4:0] router_14_25_rsp_in; - - assign router_14_25_req_in[0] = router_14_26_to_router_14_25_req; - assign router_14_25_req_in[1] = router_15_25_to_router_14_25_req; - assign router_14_25_req_in[2] = router_14_24_to_router_14_25_req; - assign router_14_25_req_in[3] = router_13_25_to_router_14_25_req; - assign router_14_25_req_in[4] = magia_tile_ni_14_25_to_router_14_25_req; - - assign router_14_25_to_router_14_26_rsp = router_14_25_rsp_out[0]; - assign router_14_25_to_router_15_25_rsp = router_14_25_rsp_out[1]; - assign router_14_25_to_router_14_24_rsp = router_14_25_rsp_out[2]; - assign router_14_25_to_router_13_25_rsp = router_14_25_rsp_out[3]; - assign router_14_25_to_magia_tile_ni_14_25_rsp = router_14_25_rsp_out[4]; - - assign router_14_25_to_router_14_26_req = router_14_25_req_out[0]; - assign router_14_25_to_router_15_25_req = router_14_25_req_out[1]; - assign router_14_25_to_router_14_24_req = router_14_25_req_out[2]; - assign router_14_25_to_router_13_25_req = router_14_25_req_out[3]; - assign router_14_25_to_magia_tile_ni_14_25_req = router_14_25_req_out[4]; - - assign router_14_25_rsp_in[0] = router_14_26_to_router_14_25_rsp; - assign router_14_25_rsp_in[1] = router_15_25_to_router_14_25_rsp; - assign router_14_25_rsp_in[2] = router_14_24_to_router_14_25_rsp; - assign router_14_25_rsp_in[3] = router_13_25_to_router_14_25_rsp; - assign router_14_25_rsp_in[4] = magia_tile_ni_14_25_to_router_14_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_25_req_in), - .floo_rsp_o (router_14_25_rsp_out), - .floo_req_o (router_14_25_req_out), - .floo_rsp_i (router_14_25_rsp_in) -); - - -floo_req_t [4:0] router_14_26_req_in; -floo_rsp_t [4:0] router_14_26_rsp_out; -floo_req_t [4:0] router_14_26_req_out; -floo_rsp_t [4:0] router_14_26_rsp_in; - - assign router_14_26_req_in[0] = router_14_27_to_router_14_26_req; - assign router_14_26_req_in[1] = router_15_26_to_router_14_26_req; - assign router_14_26_req_in[2] = router_14_25_to_router_14_26_req; - assign router_14_26_req_in[3] = router_13_26_to_router_14_26_req; - assign router_14_26_req_in[4] = magia_tile_ni_14_26_to_router_14_26_req; - - assign router_14_26_to_router_14_27_rsp = router_14_26_rsp_out[0]; - assign router_14_26_to_router_15_26_rsp = router_14_26_rsp_out[1]; - assign router_14_26_to_router_14_25_rsp = router_14_26_rsp_out[2]; - assign router_14_26_to_router_13_26_rsp = router_14_26_rsp_out[3]; - assign router_14_26_to_magia_tile_ni_14_26_rsp = router_14_26_rsp_out[4]; - - assign router_14_26_to_router_14_27_req = router_14_26_req_out[0]; - assign router_14_26_to_router_15_26_req = router_14_26_req_out[1]; - assign router_14_26_to_router_14_25_req = router_14_26_req_out[2]; - assign router_14_26_to_router_13_26_req = router_14_26_req_out[3]; - assign router_14_26_to_magia_tile_ni_14_26_req = router_14_26_req_out[4]; - - assign router_14_26_rsp_in[0] = router_14_27_to_router_14_26_rsp; - assign router_14_26_rsp_in[1] = router_15_26_to_router_14_26_rsp; - assign router_14_26_rsp_in[2] = router_14_25_to_router_14_26_rsp; - assign router_14_26_rsp_in[3] = router_13_26_to_router_14_26_rsp; - assign router_14_26_rsp_in[4] = magia_tile_ni_14_26_to_router_14_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_26_req_in), - .floo_rsp_o (router_14_26_rsp_out), - .floo_req_o (router_14_26_req_out), - .floo_rsp_i (router_14_26_rsp_in) -); - - -floo_req_t [4:0] router_14_27_req_in; -floo_rsp_t [4:0] router_14_27_rsp_out; -floo_req_t [4:0] router_14_27_req_out; -floo_rsp_t [4:0] router_14_27_rsp_in; - - assign router_14_27_req_in[0] = router_14_28_to_router_14_27_req; - assign router_14_27_req_in[1] = router_15_27_to_router_14_27_req; - assign router_14_27_req_in[2] = router_14_26_to_router_14_27_req; - assign router_14_27_req_in[3] = router_13_27_to_router_14_27_req; - assign router_14_27_req_in[4] = magia_tile_ni_14_27_to_router_14_27_req; - - assign router_14_27_to_router_14_28_rsp = router_14_27_rsp_out[0]; - assign router_14_27_to_router_15_27_rsp = router_14_27_rsp_out[1]; - assign router_14_27_to_router_14_26_rsp = router_14_27_rsp_out[2]; - assign router_14_27_to_router_13_27_rsp = router_14_27_rsp_out[3]; - assign router_14_27_to_magia_tile_ni_14_27_rsp = router_14_27_rsp_out[4]; - - assign router_14_27_to_router_14_28_req = router_14_27_req_out[0]; - assign router_14_27_to_router_15_27_req = router_14_27_req_out[1]; - assign router_14_27_to_router_14_26_req = router_14_27_req_out[2]; - assign router_14_27_to_router_13_27_req = router_14_27_req_out[3]; - assign router_14_27_to_magia_tile_ni_14_27_req = router_14_27_req_out[4]; - - assign router_14_27_rsp_in[0] = router_14_28_to_router_14_27_rsp; - assign router_14_27_rsp_in[1] = router_15_27_to_router_14_27_rsp; - assign router_14_27_rsp_in[2] = router_14_26_to_router_14_27_rsp; - assign router_14_27_rsp_in[3] = router_13_27_to_router_14_27_rsp; - assign router_14_27_rsp_in[4] = magia_tile_ni_14_27_to_router_14_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_27_req_in), - .floo_rsp_o (router_14_27_rsp_out), - .floo_req_o (router_14_27_req_out), - .floo_rsp_i (router_14_27_rsp_in) -); - - -floo_req_t [4:0] router_14_28_req_in; -floo_rsp_t [4:0] router_14_28_rsp_out; -floo_req_t [4:0] router_14_28_req_out; -floo_rsp_t [4:0] router_14_28_rsp_in; - - assign router_14_28_req_in[0] = router_14_29_to_router_14_28_req; - assign router_14_28_req_in[1] = router_15_28_to_router_14_28_req; - assign router_14_28_req_in[2] = router_14_27_to_router_14_28_req; - assign router_14_28_req_in[3] = router_13_28_to_router_14_28_req; - assign router_14_28_req_in[4] = magia_tile_ni_14_28_to_router_14_28_req; - - assign router_14_28_to_router_14_29_rsp = router_14_28_rsp_out[0]; - assign router_14_28_to_router_15_28_rsp = router_14_28_rsp_out[1]; - assign router_14_28_to_router_14_27_rsp = router_14_28_rsp_out[2]; - assign router_14_28_to_router_13_28_rsp = router_14_28_rsp_out[3]; - assign router_14_28_to_magia_tile_ni_14_28_rsp = router_14_28_rsp_out[4]; - - assign router_14_28_to_router_14_29_req = router_14_28_req_out[0]; - assign router_14_28_to_router_15_28_req = router_14_28_req_out[1]; - assign router_14_28_to_router_14_27_req = router_14_28_req_out[2]; - assign router_14_28_to_router_13_28_req = router_14_28_req_out[3]; - assign router_14_28_to_magia_tile_ni_14_28_req = router_14_28_req_out[4]; - - assign router_14_28_rsp_in[0] = router_14_29_to_router_14_28_rsp; - assign router_14_28_rsp_in[1] = router_15_28_to_router_14_28_rsp; - assign router_14_28_rsp_in[2] = router_14_27_to_router_14_28_rsp; - assign router_14_28_rsp_in[3] = router_13_28_to_router_14_28_rsp; - assign router_14_28_rsp_in[4] = magia_tile_ni_14_28_to_router_14_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_28_req_in), - .floo_rsp_o (router_14_28_rsp_out), - .floo_req_o (router_14_28_req_out), - .floo_rsp_i (router_14_28_rsp_in) -); - - -floo_req_t [4:0] router_14_29_req_in; -floo_rsp_t [4:0] router_14_29_rsp_out; -floo_req_t [4:0] router_14_29_req_out; -floo_rsp_t [4:0] router_14_29_rsp_in; - - assign router_14_29_req_in[0] = router_14_30_to_router_14_29_req; - assign router_14_29_req_in[1] = router_15_29_to_router_14_29_req; - assign router_14_29_req_in[2] = router_14_28_to_router_14_29_req; - assign router_14_29_req_in[3] = router_13_29_to_router_14_29_req; - assign router_14_29_req_in[4] = magia_tile_ni_14_29_to_router_14_29_req; - - assign router_14_29_to_router_14_30_rsp = router_14_29_rsp_out[0]; - assign router_14_29_to_router_15_29_rsp = router_14_29_rsp_out[1]; - assign router_14_29_to_router_14_28_rsp = router_14_29_rsp_out[2]; - assign router_14_29_to_router_13_29_rsp = router_14_29_rsp_out[3]; - assign router_14_29_to_magia_tile_ni_14_29_rsp = router_14_29_rsp_out[4]; - - assign router_14_29_to_router_14_30_req = router_14_29_req_out[0]; - assign router_14_29_to_router_15_29_req = router_14_29_req_out[1]; - assign router_14_29_to_router_14_28_req = router_14_29_req_out[2]; - assign router_14_29_to_router_13_29_req = router_14_29_req_out[3]; - assign router_14_29_to_magia_tile_ni_14_29_req = router_14_29_req_out[4]; - - assign router_14_29_rsp_in[0] = router_14_30_to_router_14_29_rsp; - assign router_14_29_rsp_in[1] = router_15_29_to_router_14_29_rsp; - assign router_14_29_rsp_in[2] = router_14_28_to_router_14_29_rsp; - assign router_14_29_rsp_in[3] = router_13_29_to_router_14_29_rsp; - assign router_14_29_rsp_in[4] = magia_tile_ni_14_29_to_router_14_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_29_req_in), - .floo_rsp_o (router_14_29_rsp_out), - .floo_req_o (router_14_29_req_out), - .floo_rsp_i (router_14_29_rsp_in) -); - - -floo_req_t [4:0] router_14_30_req_in; -floo_rsp_t [4:0] router_14_30_rsp_out; -floo_req_t [4:0] router_14_30_req_out; -floo_rsp_t [4:0] router_14_30_rsp_in; - - assign router_14_30_req_in[0] = router_14_31_to_router_14_30_req; - assign router_14_30_req_in[1] = router_15_30_to_router_14_30_req; - assign router_14_30_req_in[2] = router_14_29_to_router_14_30_req; - assign router_14_30_req_in[3] = router_13_30_to_router_14_30_req; - assign router_14_30_req_in[4] = magia_tile_ni_14_30_to_router_14_30_req; - - assign router_14_30_to_router_14_31_rsp = router_14_30_rsp_out[0]; - assign router_14_30_to_router_15_30_rsp = router_14_30_rsp_out[1]; - assign router_14_30_to_router_14_29_rsp = router_14_30_rsp_out[2]; - assign router_14_30_to_router_13_30_rsp = router_14_30_rsp_out[3]; - assign router_14_30_to_magia_tile_ni_14_30_rsp = router_14_30_rsp_out[4]; - - assign router_14_30_to_router_14_31_req = router_14_30_req_out[0]; - assign router_14_30_to_router_15_30_req = router_14_30_req_out[1]; - assign router_14_30_to_router_14_29_req = router_14_30_req_out[2]; - assign router_14_30_to_router_13_30_req = router_14_30_req_out[3]; - assign router_14_30_to_magia_tile_ni_14_30_req = router_14_30_req_out[4]; - - assign router_14_30_rsp_in[0] = router_14_31_to_router_14_30_rsp; - assign router_14_30_rsp_in[1] = router_15_30_to_router_14_30_rsp; - assign router_14_30_rsp_in[2] = router_14_29_to_router_14_30_rsp; - assign router_14_30_rsp_in[3] = router_13_30_to_router_14_30_rsp; - assign router_14_30_rsp_in[4] = magia_tile_ni_14_30_to_router_14_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_30_req_in), - .floo_rsp_o (router_14_30_rsp_out), - .floo_req_o (router_14_30_req_out), - .floo_rsp_i (router_14_30_rsp_in) -); - - -floo_req_t [4:0] router_14_31_req_in; -floo_rsp_t [4:0] router_14_31_rsp_out; -floo_req_t [4:0] router_14_31_req_out; -floo_rsp_t [4:0] router_14_31_rsp_in; - - assign router_14_31_req_in[0] = '0; - assign router_14_31_req_in[1] = router_15_31_to_router_14_31_req; - assign router_14_31_req_in[2] = router_14_30_to_router_14_31_req; - assign router_14_31_req_in[3] = router_13_31_to_router_14_31_req; - assign router_14_31_req_in[4] = magia_tile_ni_14_31_to_router_14_31_req; - - assign router_14_31_to_router_15_31_rsp = router_14_31_rsp_out[1]; - assign router_14_31_to_router_14_30_rsp = router_14_31_rsp_out[2]; - assign router_14_31_to_router_13_31_rsp = router_14_31_rsp_out[3]; - assign router_14_31_to_magia_tile_ni_14_31_rsp = router_14_31_rsp_out[4]; - - assign router_14_31_to_router_15_31_req = router_14_31_req_out[1]; - assign router_14_31_to_router_14_30_req = router_14_31_req_out[2]; - assign router_14_31_to_router_13_31_req = router_14_31_req_out[3]; - assign router_14_31_to_magia_tile_ni_14_31_req = router_14_31_req_out[4]; - - assign router_14_31_rsp_in[0] = '0; - assign router_14_31_rsp_in[1] = router_15_31_to_router_14_31_rsp; - assign router_14_31_rsp_in[2] = router_14_30_to_router_14_31_rsp; - assign router_14_31_rsp_in[3] = router_13_31_to_router_14_31_rsp; - assign router_14_31_rsp_in[4] = magia_tile_ni_14_31_to_router_14_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_14_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 15, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_14_31_req_in), - .floo_rsp_o (router_14_31_rsp_out), - .floo_req_o (router_14_31_req_out), - .floo_rsp_i (router_14_31_rsp_in) -); - - -floo_req_t [4:0] router_15_0_req_in; -floo_rsp_t [4:0] router_15_0_rsp_out; -floo_req_t [4:0] router_15_0_req_out; -floo_rsp_t [4:0] router_15_0_rsp_in; - - assign router_15_0_req_in[0] = router_15_1_to_router_15_0_req; - assign router_15_0_req_in[1] = router_16_0_to_router_15_0_req; - assign router_15_0_req_in[2] = '0; - assign router_15_0_req_in[3] = router_14_0_to_router_15_0_req; - assign router_15_0_req_in[4] = magia_tile_ni_15_0_to_router_15_0_req; - - assign router_15_0_to_router_15_1_rsp = router_15_0_rsp_out[0]; - assign router_15_0_to_router_16_0_rsp = router_15_0_rsp_out[1]; - assign router_15_0_to_router_14_0_rsp = router_15_0_rsp_out[3]; - assign router_15_0_to_magia_tile_ni_15_0_rsp = router_15_0_rsp_out[4]; - - assign router_15_0_to_router_15_1_req = router_15_0_req_out[0]; - assign router_15_0_to_router_16_0_req = router_15_0_req_out[1]; - assign router_15_0_to_router_14_0_req = router_15_0_req_out[3]; - assign router_15_0_to_magia_tile_ni_15_0_req = router_15_0_req_out[4]; - - assign router_15_0_rsp_in[0] = router_15_1_to_router_15_0_rsp; - assign router_15_0_rsp_in[1] = router_16_0_to_router_15_0_rsp; - assign router_15_0_rsp_in[2] = '0; - assign router_15_0_rsp_in[3] = router_14_0_to_router_15_0_rsp; - assign router_15_0_rsp_in[4] = magia_tile_ni_15_0_to_router_15_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_0_req_in), - .floo_rsp_o (router_15_0_rsp_out), - .floo_req_o (router_15_0_req_out), - .floo_rsp_i (router_15_0_rsp_in) -); - - -floo_req_t [4:0] router_15_1_req_in; -floo_rsp_t [4:0] router_15_1_rsp_out; -floo_req_t [4:0] router_15_1_req_out; -floo_rsp_t [4:0] router_15_1_rsp_in; - - assign router_15_1_req_in[0] = router_15_2_to_router_15_1_req; - assign router_15_1_req_in[1] = router_16_1_to_router_15_1_req; - assign router_15_1_req_in[2] = router_15_0_to_router_15_1_req; - assign router_15_1_req_in[3] = router_14_1_to_router_15_1_req; - assign router_15_1_req_in[4] = magia_tile_ni_15_1_to_router_15_1_req; - - assign router_15_1_to_router_15_2_rsp = router_15_1_rsp_out[0]; - assign router_15_1_to_router_16_1_rsp = router_15_1_rsp_out[1]; - assign router_15_1_to_router_15_0_rsp = router_15_1_rsp_out[2]; - assign router_15_1_to_router_14_1_rsp = router_15_1_rsp_out[3]; - assign router_15_1_to_magia_tile_ni_15_1_rsp = router_15_1_rsp_out[4]; - - assign router_15_1_to_router_15_2_req = router_15_1_req_out[0]; - assign router_15_1_to_router_16_1_req = router_15_1_req_out[1]; - assign router_15_1_to_router_15_0_req = router_15_1_req_out[2]; - assign router_15_1_to_router_14_1_req = router_15_1_req_out[3]; - assign router_15_1_to_magia_tile_ni_15_1_req = router_15_1_req_out[4]; - - assign router_15_1_rsp_in[0] = router_15_2_to_router_15_1_rsp; - assign router_15_1_rsp_in[1] = router_16_1_to_router_15_1_rsp; - assign router_15_1_rsp_in[2] = router_15_0_to_router_15_1_rsp; - assign router_15_1_rsp_in[3] = router_14_1_to_router_15_1_rsp; - assign router_15_1_rsp_in[4] = magia_tile_ni_15_1_to_router_15_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_1_req_in), - .floo_rsp_o (router_15_1_rsp_out), - .floo_req_o (router_15_1_req_out), - .floo_rsp_i (router_15_1_rsp_in) -); - - -floo_req_t [4:0] router_15_2_req_in; -floo_rsp_t [4:0] router_15_2_rsp_out; -floo_req_t [4:0] router_15_2_req_out; -floo_rsp_t [4:0] router_15_2_rsp_in; - - assign router_15_2_req_in[0] = router_15_3_to_router_15_2_req; - assign router_15_2_req_in[1] = router_16_2_to_router_15_2_req; - assign router_15_2_req_in[2] = router_15_1_to_router_15_2_req; - assign router_15_2_req_in[3] = router_14_2_to_router_15_2_req; - assign router_15_2_req_in[4] = magia_tile_ni_15_2_to_router_15_2_req; - - assign router_15_2_to_router_15_3_rsp = router_15_2_rsp_out[0]; - assign router_15_2_to_router_16_2_rsp = router_15_2_rsp_out[1]; - assign router_15_2_to_router_15_1_rsp = router_15_2_rsp_out[2]; - assign router_15_2_to_router_14_2_rsp = router_15_2_rsp_out[3]; - assign router_15_2_to_magia_tile_ni_15_2_rsp = router_15_2_rsp_out[4]; - - assign router_15_2_to_router_15_3_req = router_15_2_req_out[0]; - assign router_15_2_to_router_16_2_req = router_15_2_req_out[1]; - assign router_15_2_to_router_15_1_req = router_15_2_req_out[2]; - assign router_15_2_to_router_14_2_req = router_15_2_req_out[3]; - assign router_15_2_to_magia_tile_ni_15_2_req = router_15_2_req_out[4]; - - assign router_15_2_rsp_in[0] = router_15_3_to_router_15_2_rsp; - assign router_15_2_rsp_in[1] = router_16_2_to_router_15_2_rsp; - assign router_15_2_rsp_in[2] = router_15_1_to_router_15_2_rsp; - assign router_15_2_rsp_in[3] = router_14_2_to_router_15_2_rsp; - assign router_15_2_rsp_in[4] = magia_tile_ni_15_2_to_router_15_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_2_req_in), - .floo_rsp_o (router_15_2_rsp_out), - .floo_req_o (router_15_2_req_out), - .floo_rsp_i (router_15_2_rsp_in) -); - - -floo_req_t [4:0] router_15_3_req_in; -floo_rsp_t [4:0] router_15_3_rsp_out; -floo_req_t [4:0] router_15_3_req_out; -floo_rsp_t [4:0] router_15_3_rsp_in; - - assign router_15_3_req_in[0] = router_15_4_to_router_15_3_req; - assign router_15_3_req_in[1] = router_16_3_to_router_15_3_req; - assign router_15_3_req_in[2] = router_15_2_to_router_15_3_req; - assign router_15_3_req_in[3] = router_14_3_to_router_15_3_req; - assign router_15_3_req_in[4] = magia_tile_ni_15_3_to_router_15_3_req; - - assign router_15_3_to_router_15_4_rsp = router_15_3_rsp_out[0]; - assign router_15_3_to_router_16_3_rsp = router_15_3_rsp_out[1]; - assign router_15_3_to_router_15_2_rsp = router_15_3_rsp_out[2]; - assign router_15_3_to_router_14_3_rsp = router_15_3_rsp_out[3]; - assign router_15_3_to_magia_tile_ni_15_3_rsp = router_15_3_rsp_out[4]; - - assign router_15_3_to_router_15_4_req = router_15_3_req_out[0]; - assign router_15_3_to_router_16_3_req = router_15_3_req_out[1]; - assign router_15_3_to_router_15_2_req = router_15_3_req_out[2]; - assign router_15_3_to_router_14_3_req = router_15_3_req_out[3]; - assign router_15_3_to_magia_tile_ni_15_3_req = router_15_3_req_out[4]; - - assign router_15_3_rsp_in[0] = router_15_4_to_router_15_3_rsp; - assign router_15_3_rsp_in[1] = router_16_3_to_router_15_3_rsp; - assign router_15_3_rsp_in[2] = router_15_2_to_router_15_3_rsp; - assign router_15_3_rsp_in[3] = router_14_3_to_router_15_3_rsp; - assign router_15_3_rsp_in[4] = magia_tile_ni_15_3_to_router_15_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_3_req_in), - .floo_rsp_o (router_15_3_rsp_out), - .floo_req_o (router_15_3_req_out), - .floo_rsp_i (router_15_3_rsp_in) -); - - -floo_req_t [4:0] router_15_4_req_in; -floo_rsp_t [4:0] router_15_4_rsp_out; -floo_req_t [4:0] router_15_4_req_out; -floo_rsp_t [4:0] router_15_4_rsp_in; - - assign router_15_4_req_in[0] = router_15_5_to_router_15_4_req; - assign router_15_4_req_in[1] = router_16_4_to_router_15_4_req; - assign router_15_4_req_in[2] = router_15_3_to_router_15_4_req; - assign router_15_4_req_in[3] = router_14_4_to_router_15_4_req; - assign router_15_4_req_in[4] = magia_tile_ni_15_4_to_router_15_4_req; - - assign router_15_4_to_router_15_5_rsp = router_15_4_rsp_out[0]; - assign router_15_4_to_router_16_4_rsp = router_15_4_rsp_out[1]; - assign router_15_4_to_router_15_3_rsp = router_15_4_rsp_out[2]; - assign router_15_4_to_router_14_4_rsp = router_15_4_rsp_out[3]; - assign router_15_4_to_magia_tile_ni_15_4_rsp = router_15_4_rsp_out[4]; - - assign router_15_4_to_router_15_5_req = router_15_4_req_out[0]; - assign router_15_4_to_router_16_4_req = router_15_4_req_out[1]; - assign router_15_4_to_router_15_3_req = router_15_4_req_out[2]; - assign router_15_4_to_router_14_4_req = router_15_4_req_out[3]; - assign router_15_4_to_magia_tile_ni_15_4_req = router_15_4_req_out[4]; - - assign router_15_4_rsp_in[0] = router_15_5_to_router_15_4_rsp; - assign router_15_4_rsp_in[1] = router_16_4_to_router_15_4_rsp; - assign router_15_4_rsp_in[2] = router_15_3_to_router_15_4_rsp; - assign router_15_4_rsp_in[3] = router_14_4_to_router_15_4_rsp; - assign router_15_4_rsp_in[4] = magia_tile_ni_15_4_to_router_15_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_4_req_in), - .floo_rsp_o (router_15_4_rsp_out), - .floo_req_o (router_15_4_req_out), - .floo_rsp_i (router_15_4_rsp_in) -); - - -floo_req_t [4:0] router_15_5_req_in; -floo_rsp_t [4:0] router_15_5_rsp_out; -floo_req_t [4:0] router_15_5_req_out; -floo_rsp_t [4:0] router_15_5_rsp_in; - - assign router_15_5_req_in[0] = router_15_6_to_router_15_5_req; - assign router_15_5_req_in[1] = router_16_5_to_router_15_5_req; - assign router_15_5_req_in[2] = router_15_4_to_router_15_5_req; - assign router_15_5_req_in[3] = router_14_5_to_router_15_5_req; - assign router_15_5_req_in[4] = magia_tile_ni_15_5_to_router_15_5_req; - - assign router_15_5_to_router_15_6_rsp = router_15_5_rsp_out[0]; - assign router_15_5_to_router_16_5_rsp = router_15_5_rsp_out[1]; - assign router_15_5_to_router_15_4_rsp = router_15_5_rsp_out[2]; - assign router_15_5_to_router_14_5_rsp = router_15_5_rsp_out[3]; - assign router_15_5_to_magia_tile_ni_15_5_rsp = router_15_5_rsp_out[4]; - - assign router_15_5_to_router_15_6_req = router_15_5_req_out[0]; - assign router_15_5_to_router_16_5_req = router_15_5_req_out[1]; - assign router_15_5_to_router_15_4_req = router_15_5_req_out[2]; - assign router_15_5_to_router_14_5_req = router_15_5_req_out[3]; - assign router_15_5_to_magia_tile_ni_15_5_req = router_15_5_req_out[4]; - - assign router_15_5_rsp_in[0] = router_15_6_to_router_15_5_rsp; - assign router_15_5_rsp_in[1] = router_16_5_to_router_15_5_rsp; - assign router_15_5_rsp_in[2] = router_15_4_to_router_15_5_rsp; - assign router_15_5_rsp_in[3] = router_14_5_to_router_15_5_rsp; - assign router_15_5_rsp_in[4] = magia_tile_ni_15_5_to_router_15_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_5_req_in), - .floo_rsp_o (router_15_5_rsp_out), - .floo_req_o (router_15_5_req_out), - .floo_rsp_i (router_15_5_rsp_in) -); - - -floo_req_t [4:0] router_15_6_req_in; -floo_rsp_t [4:0] router_15_6_rsp_out; -floo_req_t [4:0] router_15_6_req_out; -floo_rsp_t [4:0] router_15_6_rsp_in; - - assign router_15_6_req_in[0] = router_15_7_to_router_15_6_req; - assign router_15_6_req_in[1] = router_16_6_to_router_15_6_req; - assign router_15_6_req_in[2] = router_15_5_to_router_15_6_req; - assign router_15_6_req_in[3] = router_14_6_to_router_15_6_req; - assign router_15_6_req_in[4] = magia_tile_ni_15_6_to_router_15_6_req; - - assign router_15_6_to_router_15_7_rsp = router_15_6_rsp_out[0]; - assign router_15_6_to_router_16_6_rsp = router_15_6_rsp_out[1]; - assign router_15_6_to_router_15_5_rsp = router_15_6_rsp_out[2]; - assign router_15_6_to_router_14_6_rsp = router_15_6_rsp_out[3]; - assign router_15_6_to_magia_tile_ni_15_6_rsp = router_15_6_rsp_out[4]; - - assign router_15_6_to_router_15_7_req = router_15_6_req_out[0]; - assign router_15_6_to_router_16_6_req = router_15_6_req_out[1]; - assign router_15_6_to_router_15_5_req = router_15_6_req_out[2]; - assign router_15_6_to_router_14_6_req = router_15_6_req_out[3]; - assign router_15_6_to_magia_tile_ni_15_6_req = router_15_6_req_out[4]; - - assign router_15_6_rsp_in[0] = router_15_7_to_router_15_6_rsp; - assign router_15_6_rsp_in[1] = router_16_6_to_router_15_6_rsp; - assign router_15_6_rsp_in[2] = router_15_5_to_router_15_6_rsp; - assign router_15_6_rsp_in[3] = router_14_6_to_router_15_6_rsp; - assign router_15_6_rsp_in[4] = magia_tile_ni_15_6_to_router_15_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_6_req_in), - .floo_rsp_o (router_15_6_rsp_out), - .floo_req_o (router_15_6_req_out), - .floo_rsp_i (router_15_6_rsp_in) -); - - -floo_req_t [4:0] router_15_7_req_in; -floo_rsp_t [4:0] router_15_7_rsp_out; -floo_req_t [4:0] router_15_7_req_out; -floo_rsp_t [4:0] router_15_7_rsp_in; - - assign router_15_7_req_in[0] = router_15_8_to_router_15_7_req; - assign router_15_7_req_in[1] = router_16_7_to_router_15_7_req; - assign router_15_7_req_in[2] = router_15_6_to_router_15_7_req; - assign router_15_7_req_in[3] = router_14_7_to_router_15_7_req; - assign router_15_7_req_in[4] = magia_tile_ni_15_7_to_router_15_7_req; - - assign router_15_7_to_router_15_8_rsp = router_15_7_rsp_out[0]; - assign router_15_7_to_router_16_7_rsp = router_15_7_rsp_out[1]; - assign router_15_7_to_router_15_6_rsp = router_15_7_rsp_out[2]; - assign router_15_7_to_router_14_7_rsp = router_15_7_rsp_out[3]; - assign router_15_7_to_magia_tile_ni_15_7_rsp = router_15_7_rsp_out[4]; - - assign router_15_7_to_router_15_8_req = router_15_7_req_out[0]; - assign router_15_7_to_router_16_7_req = router_15_7_req_out[1]; - assign router_15_7_to_router_15_6_req = router_15_7_req_out[2]; - assign router_15_7_to_router_14_7_req = router_15_7_req_out[3]; - assign router_15_7_to_magia_tile_ni_15_7_req = router_15_7_req_out[4]; - - assign router_15_7_rsp_in[0] = router_15_8_to_router_15_7_rsp; - assign router_15_7_rsp_in[1] = router_16_7_to_router_15_7_rsp; - assign router_15_7_rsp_in[2] = router_15_6_to_router_15_7_rsp; - assign router_15_7_rsp_in[3] = router_14_7_to_router_15_7_rsp; - assign router_15_7_rsp_in[4] = magia_tile_ni_15_7_to_router_15_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_7_req_in), - .floo_rsp_o (router_15_7_rsp_out), - .floo_req_o (router_15_7_req_out), - .floo_rsp_i (router_15_7_rsp_in) -); - - -floo_req_t [4:0] router_15_8_req_in; -floo_rsp_t [4:0] router_15_8_rsp_out; -floo_req_t [4:0] router_15_8_req_out; -floo_rsp_t [4:0] router_15_8_rsp_in; - - assign router_15_8_req_in[0] = router_15_9_to_router_15_8_req; - assign router_15_8_req_in[1] = router_16_8_to_router_15_8_req; - assign router_15_8_req_in[2] = router_15_7_to_router_15_8_req; - assign router_15_8_req_in[3] = router_14_8_to_router_15_8_req; - assign router_15_8_req_in[4] = magia_tile_ni_15_8_to_router_15_8_req; - - assign router_15_8_to_router_15_9_rsp = router_15_8_rsp_out[0]; - assign router_15_8_to_router_16_8_rsp = router_15_8_rsp_out[1]; - assign router_15_8_to_router_15_7_rsp = router_15_8_rsp_out[2]; - assign router_15_8_to_router_14_8_rsp = router_15_8_rsp_out[3]; - assign router_15_8_to_magia_tile_ni_15_8_rsp = router_15_8_rsp_out[4]; - - assign router_15_8_to_router_15_9_req = router_15_8_req_out[0]; - assign router_15_8_to_router_16_8_req = router_15_8_req_out[1]; - assign router_15_8_to_router_15_7_req = router_15_8_req_out[2]; - assign router_15_8_to_router_14_8_req = router_15_8_req_out[3]; - assign router_15_8_to_magia_tile_ni_15_8_req = router_15_8_req_out[4]; - - assign router_15_8_rsp_in[0] = router_15_9_to_router_15_8_rsp; - assign router_15_8_rsp_in[1] = router_16_8_to_router_15_8_rsp; - assign router_15_8_rsp_in[2] = router_15_7_to_router_15_8_rsp; - assign router_15_8_rsp_in[3] = router_14_8_to_router_15_8_rsp; - assign router_15_8_rsp_in[4] = magia_tile_ni_15_8_to_router_15_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_8_req_in), - .floo_rsp_o (router_15_8_rsp_out), - .floo_req_o (router_15_8_req_out), - .floo_rsp_i (router_15_8_rsp_in) -); - - -floo_req_t [4:0] router_15_9_req_in; -floo_rsp_t [4:0] router_15_9_rsp_out; -floo_req_t [4:0] router_15_9_req_out; -floo_rsp_t [4:0] router_15_9_rsp_in; - - assign router_15_9_req_in[0] = router_15_10_to_router_15_9_req; - assign router_15_9_req_in[1] = router_16_9_to_router_15_9_req; - assign router_15_9_req_in[2] = router_15_8_to_router_15_9_req; - assign router_15_9_req_in[3] = router_14_9_to_router_15_9_req; - assign router_15_9_req_in[4] = magia_tile_ni_15_9_to_router_15_9_req; - - assign router_15_9_to_router_15_10_rsp = router_15_9_rsp_out[0]; - assign router_15_9_to_router_16_9_rsp = router_15_9_rsp_out[1]; - assign router_15_9_to_router_15_8_rsp = router_15_9_rsp_out[2]; - assign router_15_9_to_router_14_9_rsp = router_15_9_rsp_out[3]; - assign router_15_9_to_magia_tile_ni_15_9_rsp = router_15_9_rsp_out[4]; - - assign router_15_9_to_router_15_10_req = router_15_9_req_out[0]; - assign router_15_9_to_router_16_9_req = router_15_9_req_out[1]; - assign router_15_9_to_router_15_8_req = router_15_9_req_out[2]; - assign router_15_9_to_router_14_9_req = router_15_9_req_out[3]; - assign router_15_9_to_magia_tile_ni_15_9_req = router_15_9_req_out[4]; - - assign router_15_9_rsp_in[0] = router_15_10_to_router_15_9_rsp; - assign router_15_9_rsp_in[1] = router_16_9_to_router_15_9_rsp; - assign router_15_9_rsp_in[2] = router_15_8_to_router_15_9_rsp; - assign router_15_9_rsp_in[3] = router_14_9_to_router_15_9_rsp; - assign router_15_9_rsp_in[4] = magia_tile_ni_15_9_to_router_15_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_9_req_in), - .floo_rsp_o (router_15_9_rsp_out), - .floo_req_o (router_15_9_req_out), - .floo_rsp_i (router_15_9_rsp_in) -); - - -floo_req_t [4:0] router_15_10_req_in; -floo_rsp_t [4:0] router_15_10_rsp_out; -floo_req_t [4:0] router_15_10_req_out; -floo_rsp_t [4:0] router_15_10_rsp_in; - - assign router_15_10_req_in[0] = router_15_11_to_router_15_10_req; - assign router_15_10_req_in[1] = router_16_10_to_router_15_10_req; - assign router_15_10_req_in[2] = router_15_9_to_router_15_10_req; - assign router_15_10_req_in[3] = router_14_10_to_router_15_10_req; - assign router_15_10_req_in[4] = magia_tile_ni_15_10_to_router_15_10_req; - - assign router_15_10_to_router_15_11_rsp = router_15_10_rsp_out[0]; - assign router_15_10_to_router_16_10_rsp = router_15_10_rsp_out[1]; - assign router_15_10_to_router_15_9_rsp = router_15_10_rsp_out[2]; - assign router_15_10_to_router_14_10_rsp = router_15_10_rsp_out[3]; - assign router_15_10_to_magia_tile_ni_15_10_rsp = router_15_10_rsp_out[4]; - - assign router_15_10_to_router_15_11_req = router_15_10_req_out[0]; - assign router_15_10_to_router_16_10_req = router_15_10_req_out[1]; - assign router_15_10_to_router_15_9_req = router_15_10_req_out[2]; - assign router_15_10_to_router_14_10_req = router_15_10_req_out[3]; - assign router_15_10_to_magia_tile_ni_15_10_req = router_15_10_req_out[4]; - - assign router_15_10_rsp_in[0] = router_15_11_to_router_15_10_rsp; - assign router_15_10_rsp_in[1] = router_16_10_to_router_15_10_rsp; - assign router_15_10_rsp_in[2] = router_15_9_to_router_15_10_rsp; - assign router_15_10_rsp_in[3] = router_14_10_to_router_15_10_rsp; - assign router_15_10_rsp_in[4] = magia_tile_ni_15_10_to_router_15_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_10_req_in), - .floo_rsp_o (router_15_10_rsp_out), - .floo_req_o (router_15_10_req_out), - .floo_rsp_i (router_15_10_rsp_in) -); - - -floo_req_t [4:0] router_15_11_req_in; -floo_rsp_t [4:0] router_15_11_rsp_out; -floo_req_t [4:0] router_15_11_req_out; -floo_rsp_t [4:0] router_15_11_rsp_in; - - assign router_15_11_req_in[0] = router_15_12_to_router_15_11_req; - assign router_15_11_req_in[1] = router_16_11_to_router_15_11_req; - assign router_15_11_req_in[2] = router_15_10_to_router_15_11_req; - assign router_15_11_req_in[3] = router_14_11_to_router_15_11_req; - assign router_15_11_req_in[4] = magia_tile_ni_15_11_to_router_15_11_req; - - assign router_15_11_to_router_15_12_rsp = router_15_11_rsp_out[0]; - assign router_15_11_to_router_16_11_rsp = router_15_11_rsp_out[1]; - assign router_15_11_to_router_15_10_rsp = router_15_11_rsp_out[2]; - assign router_15_11_to_router_14_11_rsp = router_15_11_rsp_out[3]; - assign router_15_11_to_magia_tile_ni_15_11_rsp = router_15_11_rsp_out[4]; - - assign router_15_11_to_router_15_12_req = router_15_11_req_out[0]; - assign router_15_11_to_router_16_11_req = router_15_11_req_out[1]; - assign router_15_11_to_router_15_10_req = router_15_11_req_out[2]; - assign router_15_11_to_router_14_11_req = router_15_11_req_out[3]; - assign router_15_11_to_magia_tile_ni_15_11_req = router_15_11_req_out[4]; - - assign router_15_11_rsp_in[0] = router_15_12_to_router_15_11_rsp; - assign router_15_11_rsp_in[1] = router_16_11_to_router_15_11_rsp; - assign router_15_11_rsp_in[2] = router_15_10_to_router_15_11_rsp; - assign router_15_11_rsp_in[3] = router_14_11_to_router_15_11_rsp; - assign router_15_11_rsp_in[4] = magia_tile_ni_15_11_to_router_15_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_11_req_in), - .floo_rsp_o (router_15_11_rsp_out), - .floo_req_o (router_15_11_req_out), - .floo_rsp_i (router_15_11_rsp_in) -); - - -floo_req_t [4:0] router_15_12_req_in; -floo_rsp_t [4:0] router_15_12_rsp_out; -floo_req_t [4:0] router_15_12_req_out; -floo_rsp_t [4:0] router_15_12_rsp_in; - - assign router_15_12_req_in[0] = router_15_13_to_router_15_12_req; - assign router_15_12_req_in[1] = router_16_12_to_router_15_12_req; - assign router_15_12_req_in[2] = router_15_11_to_router_15_12_req; - assign router_15_12_req_in[3] = router_14_12_to_router_15_12_req; - assign router_15_12_req_in[4] = magia_tile_ni_15_12_to_router_15_12_req; - - assign router_15_12_to_router_15_13_rsp = router_15_12_rsp_out[0]; - assign router_15_12_to_router_16_12_rsp = router_15_12_rsp_out[1]; - assign router_15_12_to_router_15_11_rsp = router_15_12_rsp_out[2]; - assign router_15_12_to_router_14_12_rsp = router_15_12_rsp_out[3]; - assign router_15_12_to_magia_tile_ni_15_12_rsp = router_15_12_rsp_out[4]; - - assign router_15_12_to_router_15_13_req = router_15_12_req_out[0]; - assign router_15_12_to_router_16_12_req = router_15_12_req_out[1]; - assign router_15_12_to_router_15_11_req = router_15_12_req_out[2]; - assign router_15_12_to_router_14_12_req = router_15_12_req_out[3]; - assign router_15_12_to_magia_tile_ni_15_12_req = router_15_12_req_out[4]; - - assign router_15_12_rsp_in[0] = router_15_13_to_router_15_12_rsp; - assign router_15_12_rsp_in[1] = router_16_12_to_router_15_12_rsp; - assign router_15_12_rsp_in[2] = router_15_11_to_router_15_12_rsp; - assign router_15_12_rsp_in[3] = router_14_12_to_router_15_12_rsp; - assign router_15_12_rsp_in[4] = magia_tile_ni_15_12_to_router_15_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_12_req_in), - .floo_rsp_o (router_15_12_rsp_out), - .floo_req_o (router_15_12_req_out), - .floo_rsp_i (router_15_12_rsp_in) -); - - -floo_req_t [4:0] router_15_13_req_in; -floo_rsp_t [4:0] router_15_13_rsp_out; -floo_req_t [4:0] router_15_13_req_out; -floo_rsp_t [4:0] router_15_13_rsp_in; - - assign router_15_13_req_in[0] = router_15_14_to_router_15_13_req; - assign router_15_13_req_in[1] = router_16_13_to_router_15_13_req; - assign router_15_13_req_in[2] = router_15_12_to_router_15_13_req; - assign router_15_13_req_in[3] = router_14_13_to_router_15_13_req; - assign router_15_13_req_in[4] = magia_tile_ni_15_13_to_router_15_13_req; - - assign router_15_13_to_router_15_14_rsp = router_15_13_rsp_out[0]; - assign router_15_13_to_router_16_13_rsp = router_15_13_rsp_out[1]; - assign router_15_13_to_router_15_12_rsp = router_15_13_rsp_out[2]; - assign router_15_13_to_router_14_13_rsp = router_15_13_rsp_out[3]; - assign router_15_13_to_magia_tile_ni_15_13_rsp = router_15_13_rsp_out[4]; - - assign router_15_13_to_router_15_14_req = router_15_13_req_out[0]; - assign router_15_13_to_router_16_13_req = router_15_13_req_out[1]; - assign router_15_13_to_router_15_12_req = router_15_13_req_out[2]; - assign router_15_13_to_router_14_13_req = router_15_13_req_out[3]; - assign router_15_13_to_magia_tile_ni_15_13_req = router_15_13_req_out[4]; - - assign router_15_13_rsp_in[0] = router_15_14_to_router_15_13_rsp; - assign router_15_13_rsp_in[1] = router_16_13_to_router_15_13_rsp; - assign router_15_13_rsp_in[2] = router_15_12_to_router_15_13_rsp; - assign router_15_13_rsp_in[3] = router_14_13_to_router_15_13_rsp; - assign router_15_13_rsp_in[4] = magia_tile_ni_15_13_to_router_15_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_13_req_in), - .floo_rsp_o (router_15_13_rsp_out), - .floo_req_o (router_15_13_req_out), - .floo_rsp_i (router_15_13_rsp_in) -); - - -floo_req_t [4:0] router_15_14_req_in; -floo_rsp_t [4:0] router_15_14_rsp_out; -floo_req_t [4:0] router_15_14_req_out; -floo_rsp_t [4:0] router_15_14_rsp_in; - - assign router_15_14_req_in[0] = router_15_15_to_router_15_14_req; - assign router_15_14_req_in[1] = router_16_14_to_router_15_14_req; - assign router_15_14_req_in[2] = router_15_13_to_router_15_14_req; - assign router_15_14_req_in[3] = router_14_14_to_router_15_14_req; - assign router_15_14_req_in[4] = magia_tile_ni_15_14_to_router_15_14_req; - - assign router_15_14_to_router_15_15_rsp = router_15_14_rsp_out[0]; - assign router_15_14_to_router_16_14_rsp = router_15_14_rsp_out[1]; - assign router_15_14_to_router_15_13_rsp = router_15_14_rsp_out[2]; - assign router_15_14_to_router_14_14_rsp = router_15_14_rsp_out[3]; - assign router_15_14_to_magia_tile_ni_15_14_rsp = router_15_14_rsp_out[4]; - - assign router_15_14_to_router_15_15_req = router_15_14_req_out[0]; - assign router_15_14_to_router_16_14_req = router_15_14_req_out[1]; - assign router_15_14_to_router_15_13_req = router_15_14_req_out[2]; - assign router_15_14_to_router_14_14_req = router_15_14_req_out[3]; - assign router_15_14_to_magia_tile_ni_15_14_req = router_15_14_req_out[4]; - - assign router_15_14_rsp_in[0] = router_15_15_to_router_15_14_rsp; - assign router_15_14_rsp_in[1] = router_16_14_to_router_15_14_rsp; - assign router_15_14_rsp_in[2] = router_15_13_to_router_15_14_rsp; - assign router_15_14_rsp_in[3] = router_14_14_to_router_15_14_rsp; - assign router_15_14_rsp_in[4] = magia_tile_ni_15_14_to_router_15_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_14_req_in), - .floo_rsp_o (router_15_14_rsp_out), - .floo_req_o (router_15_14_req_out), - .floo_rsp_i (router_15_14_rsp_in) -); - - -floo_req_t [4:0] router_15_15_req_in; -floo_rsp_t [4:0] router_15_15_rsp_out; -floo_req_t [4:0] router_15_15_req_out; -floo_rsp_t [4:0] router_15_15_rsp_in; - - assign router_15_15_req_in[0] = router_15_16_to_router_15_15_req; - assign router_15_15_req_in[1] = router_16_15_to_router_15_15_req; - assign router_15_15_req_in[2] = router_15_14_to_router_15_15_req; - assign router_15_15_req_in[3] = router_14_15_to_router_15_15_req; - assign router_15_15_req_in[4] = magia_tile_ni_15_15_to_router_15_15_req; - - assign router_15_15_to_router_15_16_rsp = router_15_15_rsp_out[0]; - assign router_15_15_to_router_16_15_rsp = router_15_15_rsp_out[1]; - assign router_15_15_to_router_15_14_rsp = router_15_15_rsp_out[2]; - assign router_15_15_to_router_14_15_rsp = router_15_15_rsp_out[3]; - assign router_15_15_to_magia_tile_ni_15_15_rsp = router_15_15_rsp_out[4]; - - assign router_15_15_to_router_15_16_req = router_15_15_req_out[0]; - assign router_15_15_to_router_16_15_req = router_15_15_req_out[1]; - assign router_15_15_to_router_15_14_req = router_15_15_req_out[2]; - assign router_15_15_to_router_14_15_req = router_15_15_req_out[3]; - assign router_15_15_to_magia_tile_ni_15_15_req = router_15_15_req_out[4]; - - assign router_15_15_rsp_in[0] = router_15_16_to_router_15_15_rsp; - assign router_15_15_rsp_in[1] = router_16_15_to_router_15_15_rsp; - assign router_15_15_rsp_in[2] = router_15_14_to_router_15_15_rsp; - assign router_15_15_rsp_in[3] = router_14_15_to_router_15_15_rsp; - assign router_15_15_rsp_in[4] = magia_tile_ni_15_15_to_router_15_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_15_req_in), - .floo_rsp_o (router_15_15_rsp_out), - .floo_req_o (router_15_15_req_out), - .floo_rsp_i (router_15_15_rsp_in) -); - - -floo_req_t [4:0] router_15_16_req_in; -floo_rsp_t [4:0] router_15_16_rsp_out; -floo_req_t [4:0] router_15_16_req_out; -floo_rsp_t [4:0] router_15_16_rsp_in; - - assign router_15_16_req_in[0] = router_15_17_to_router_15_16_req; - assign router_15_16_req_in[1] = router_16_16_to_router_15_16_req; - assign router_15_16_req_in[2] = router_15_15_to_router_15_16_req; - assign router_15_16_req_in[3] = router_14_16_to_router_15_16_req; - assign router_15_16_req_in[4] = magia_tile_ni_15_16_to_router_15_16_req; - - assign router_15_16_to_router_15_17_rsp = router_15_16_rsp_out[0]; - assign router_15_16_to_router_16_16_rsp = router_15_16_rsp_out[1]; - assign router_15_16_to_router_15_15_rsp = router_15_16_rsp_out[2]; - assign router_15_16_to_router_14_16_rsp = router_15_16_rsp_out[3]; - assign router_15_16_to_magia_tile_ni_15_16_rsp = router_15_16_rsp_out[4]; - - assign router_15_16_to_router_15_17_req = router_15_16_req_out[0]; - assign router_15_16_to_router_16_16_req = router_15_16_req_out[1]; - assign router_15_16_to_router_15_15_req = router_15_16_req_out[2]; - assign router_15_16_to_router_14_16_req = router_15_16_req_out[3]; - assign router_15_16_to_magia_tile_ni_15_16_req = router_15_16_req_out[4]; - - assign router_15_16_rsp_in[0] = router_15_17_to_router_15_16_rsp; - assign router_15_16_rsp_in[1] = router_16_16_to_router_15_16_rsp; - assign router_15_16_rsp_in[2] = router_15_15_to_router_15_16_rsp; - assign router_15_16_rsp_in[3] = router_14_16_to_router_15_16_rsp; - assign router_15_16_rsp_in[4] = magia_tile_ni_15_16_to_router_15_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_16_req_in), - .floo_rsp_o (router_15_16_rsp_out), - .floo_req_o (router_15_16_req_out), - .floo_rsp_i (router_15_16_rsp_in) -); - - -floo_req_t [4:0] router_15_17_req_in; -floo_rsp_t [4:0] router_15_17_rsp_out; -floo_req_t [4:0] router_15_17_req_out; -floo_rsp_t [4:0] router_15_17_rsp_in; - - assign router_15_17_req_in[0] = router_15_18_to_router_15_17_req; - assign router_15_17_req_in[1] = router_16_17_to_router_15_17_req; - assign router_15_17_req_in[2] = router_15_16_to_router_15_17_req; - assign router_15_17_req_in[3] = router_14_17_to_router_15_17_req; - assign router_15_17_req_in[4] = magia_tile_ni_15_17_to_router_15_17_req; - - assign router_15_17_to_router_15_18_rsp = router_15_17_rsp_out[0]; - assign router_15_17_to_router_16_17_rsp = router_15_17_rsp_out[1]; - assign router_15_17_to_router_15_16_rsp = router_15_17_rsp_out[2]; - assign router_15_17_to_router_14_17_rsp = router_15_17_rsp_out[3]; - assign router_15_17_to_magia_tile_ni_15_17_rsp = router_15_17_rsp_out[4]; - - assign router_15_17_to_router_15_18_req = router_15_17_req_out[0]; - assign router_15_17_to_router_16_17_req = router_15_17_req_out[1]; - assign router_15_17_to_router_15_16_req = router_15_17_req_out[2]; - assign router_15_17_to_router_14_17_req = router_15_17_req_out[3]; - assign router_15_17_to_magia_tile_ni_15_17_req = router_15_17_req_out[4]; - - assign router_15_17_rsp_in[0] = router_15_18_to_router_15_17_rsp; - assign router_15_17_rsp_in[1] = router_16_17_to_router_15_17_rsp; - assign router_15_17_rsp_in[2] = router_15_16_to_router_15_17_rsp; - assign router_15_17_rsp_in[3] = router_14_17_to_router_15_17_rsp; - assign router_15_17_rsp_in[4] = magia_tile_ni_15_17_to_router_15_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_17_req_in), - .floo_rsp_o (router_15_17_rsp_out), - .floo_req_o (router_15_17_req_out), - .floo_rsp_i (router_15_17_rsp_in) -); - - -floo_req_t [4:0] router_15_18_req_in; -floo_rsp_t [4:0] router_15_18_rsp_out; -floo_req_t [4:0] router_15_18_req_out; -floo_rsp_t [4:0] router_15_18_rsp_in; - - assign router_15_18_req_in[0] = router_15_19_to_router_15_18_req; - assign router_15_18_req_in[1] = router_16_18_to_router_15_18_req; - assign router_15_18_req_in[2] = router_15_17_to_router_15_18_req; - assign router_15_18_req_in[3] = router_14_18_to_router_15_18_req; - assign router_15_18_req_in[4] = magia_tile_ni_15_18_to_router_15_18_req; - - assign router_15_18_to_router_15_19_rsp = router_15_18_rsp_out[0]; - assign router_15_18_to_router_16_18_rsp = router_15_18_rsp_out[1]; - assign router_15_18_to_router_15_17_rsp = router_15_18_rsp_out[2]; - assign router_15_18_to_router_14_18_rsp = router_15_18_rsp_out[3]; - assign router_15_18_to_magia_tile_ni_15_18_rsp = router_15_18_rsp_out[4]; - - assign router_15_18_to_router_15_19_req = router_15_18_req_out[0]; - assign router_15_18_to_router_16_18_req = router_15_18_req_out[1]; - assign router_15_18_to_router_15_17_req = router_15_18_req_out[2]; - assign router_15_18_to_router_14_18_req = router_15_18_req_out[3]; - assign router_15_18_to_magia_tile_ni_15_18_req = router_15_18_req_out[4]; - - assign router_15_18_rsp_in[0] = router_15_19_to_router_15_18_rsp; - assign router_15_18_rsp_in[1] = router_16_18_to_router_15_18_rsp; - assign router_15_18_rsp_in[2] = router_15_17_to_router_15_18_rsp; - assign router_15_18_rsp_in[3] = router_14_18_to_router_15_18_rsp; - assign router_15_18_rsp_in[4] = magia_tile_ni_15_18_to_router_15_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_18_req_in), - .floo_rsp_o (router_15_18_rsp_out), - .floo_req_o (router_15_18_req_out), - .floo_rsp_i (router_15_18_rsp_in) -); - - -floo_req_t [4:0] router_15_19_req_in; -floo_rsp_t [4:0] router_15_19_rsp_out; -floo_req_t [4:0] router_15_19_req_out; -floo_rsp_t [4:0] router_15_19_rsp_in; - - assign router_15_19_req_in[0] = router_15_20_to_router_15_19_req; - assign router_15_19_req_in[1] = router_16_19_to_router_15_19_req; - assign router_15_19_req_in[2] = router_15_18_to_router_15_19_req; - assign router_15_19_req_in[3] = router_14_19_to_router_15_19_req; - assign router_15_19_req_in[4] = magia_tile_ni_15_19_to_router_15_19_req; - - assign router_15_19_to_router_15_20_rsp = router_15_19_rsp_out[0]; - assign router_15_19_to_router_16_19_rsp = router_15_19_rsp_out[1]; - assign router_15_19_to_router_15_18_rsp = router_15_19_rsp_out[2]; - assign router_15_19_to_router_14_19_rsp = router_15_19_rsp_out[3]; - assign router_15_19_to_magia_tile_ni_15_19_rsp = router_15_19_rsp_out[4]; - - assign router_15_19_to_router_15_20_req = router_15_19_req_out[0]; - assign router_15_19_to_router_16_19_req = router_15_19_req_out[1]; - assign router_15_19_to_router_15_18_req = router_15_19_req_out[2]; - assign router_15_19_to_router_14_19_req = router_15_19_req_out[3]; - assign router_15_19_to_magia_tile_ni_15_19_req = router_15_19_req_out[4]; - - assign router_15_19_rsp_in[0] = router_15_20_to_router_15_19_rsp; - assign router_15_19_rsp_in[1] = router_16_19_to_router_15_19_rsp; - assign router_15_19_rsp_in[2] = router_15_18_to_router_15_19_rsp; - assign router_15_19_rsp_in[3] = router_14_19_to_router_15_19_rsp; - assign router_15_19_rsp_in[4] = magia_tile_ni_15_19_to_router_15_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_19_req_in), - .floo_rsp_o (router_15_19_rsp_out), - .floo_req_o (router_15_19_req_out), - .floo_rsp_i (router_15_19_rsp_in) -); - - -floo_req_t [4:0] router_15_20_req_in; -floo_rsp_t [4:0] router_15_20_rsp_out; -floo_req_t [4:0] router_15_20_req_out; -floo_rsp_t [4:0] router_15_20_rsp_in; - - assign router_15_20_req_in[0] = router_15_21_to_router_15_20_req; - assign router_15_20_req_in[1] = router_16_20_to_router_15_20_req; - assign router_15_20_req_in[2] = router_15_19_to_router_15_20_req; - assign router_15_20_req_in[3] = router_14_20_to_router_15_20_req; - assign router_15_20_req_in[4] = magia_tile_ni_15_20_to_router_15_20_req; - - assign router_15_20_to_router_15_21_rsp = router_15_20_rsp_out[0]; - assign router_15_20_to_router_16_20_rsp = router_15_20_rsp_out[1]; - assign router_15_20_to_router_15_19_rsp = router_15_20_rsp_out[2]; - assign router_15_20_to_router_14_20_rsp = router_15_20_rsp_out[3]; - assign router_15_20_to_magia_tile_ni_15_20_rsp = router_15_20_rsp_out[4]; - - assign router_15_20_to_router_15_21_req = router_15_20_req_out[0]; - assign router_15_20_to_router_16_20_req = router_15_20_req_out[1]; - assign router_15_20_to_router_15_19_req = router_15_20_req_out[2]; - assign router_15_20_to_router_14_20_req = router_15_20_req_out[3]; - assign router_15_20_to_magia_tile_ni_15_20_req = router_15_20_req_out[4]; - - assign router_15_20_rsp_in[0] = router_15_21_to_router_15_20_rsp; - assign router_15_20_rsp_in[1] = router_16_20_to_router_15_20_rsp; - assign router_15_20_rsp_in[2] = router_15_19_to_router_15_20_rsp; - assign router_15_20_rsp_in[3] = router_14_20_to_router_15_20_rsp; - assign router_15_20_rsp_in[4] = magia_tile_ni_15_20_to_router_15_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_20_req_in), - .floo_rsp_o (router_15_20_rsp_out), - .floo_req_o (router_15_20_req_out), - .floo_rsp_i (router_15_20_rsp_in) -); - - -floo_req_t [4:0] router_15_21_req_in; -floo_rsp_t [4:0] router_15_21_rsp_out; -floo_req_t [4:0] router_15_21_req_out; -floo_rsp_t [4:0] router_15_21_rsp_in; - - assign router_15_21_req_in[0] = router_15_22_to_router_15_21_req; - assign router_15_21_req_in[1] = router_16_21_to_router_15_21_req; - assign router_15_21_req_in[2] = router_15_20_to_router_15_21_req; - assign router_15_21_req_in[3] = router_14_21_to_router_15_21_req; - assign router_15_21_req_in[4] = magia_tile_ni_15_21_to_router_15_21_req; - - assign router_15_21_to_router_15_22_rsp = router_15_21_rsp_out[0]; - assign router_15_21_to_router_16_21_rsp = router_15_21_rsp_out[1]; - assign router_15_21_to_router_15_20_rsp = router_15_21_rsp_out[2]; - assign router_15_21_to_router_14_21_rsp = router_15_21_rsp_out[3]; - assign router_15_21_to_magia_tile_ni_15_21_rsp = router_15_21_rsp_out[4]; - - assign router_15_21_to_router_15_22_req = router_15_21_req_out[0]; - assign router_15_21_to_router_16_21_req = router_15_21_req_out[1]; - assign router_15_21_to_router_15_20_req = router_15_21_req_out[2]; - assign router_15_21_to_router_14_21_req = router_15_21_req_out[3]; - assign router_15_21_to_magia_tile_ni_15_21_req = router_15_21_req_out[4]; - - assign router_15_21_rsp_in[0] = router_15_22_to_router_15_21_rsp; - assign router_15_21_rsp_in[1] = router_16_21_to_router_15_21_rsp; - assign router_15_21_rsp_in[2] = router_15_20_to_router_15_21_rsp; - assign router_15_21_rsp_in[3] = router_14_21_to_router_15_21_rsp; - assign router_15_21_rsp_in[4] = magia_tile_ni_15_21_to_router_15_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_21_req_in), - .floo_rsp_o (router_15_21_rsp_out), - .floo_req_o (router_15_21_req_out), - .floo_rsp_i (router_15_21_rsp_in) -); - - -floo_req_t [4:0] router_15_22_req_in; -floo_rsp_t [4:0] router_15_22_rsp_out; -floo_req_t [4:0] router_15_22_req_out; -floo_rsp_t [4:0] router_15_22_rsp_in; - - assign router_15_22_req_in[0] = router_15_23_to_router_15_22_req; - assign router_15_22_req_in[1] = router_16_22_to_router_15_22_req; - assign router_15_22_req_in[2] = router_15_21_to_router_15_22_req; - assign router_15_22_req_in[3] = router_14_22_to_router_15_22_req; - assign router_15_22_req_in[4] = magia_tile_ni_15_22_to_router_15_22_req; - - assign router_15_22_to_router_15_23_rsp = router_15_22_rsp_out[0]; - assign router_15_22_to_router_16_22_rsp = router_15_22_rsp_out[1]; - assign router_15_22_to_router_15_21_rsp = router_15_22_rsp_out[2]; - assign router_15_22_to_router_14_22_rsp = router_15_22_rsp_out[3]; - assign router_15_22_to_magia_tile_ni_15_22_rsp = router_15_22_rsp_out[4]; - - assign router_15_22_to_router_15_23_req = router_15_22_req_out[0]; - assign router_15_22_to_router_16_22_req = router_15_22_req_out[1]; - assign router_15_22_to_router_15_21_req = router_15_22_req_out[2]; - assign router_15_22_to_router_14_22_req = router_15_22_req_out[3]; - assign router_15_22_to_magia_tile_ni_15_22_req = router_15_22_req_out[4]; - - assign router_15_22_rsp_in[0] = router_15_23_to_router_15_22_rsp; - assign router_15_22_rsp_in[1] = router_16_22_to_router_15_22_rsp; - assign router_15_22_rsp_in[2] = router_15_21_to_router_15_22_rsp; - assign router_15_22_rsp_in[3] = router_14_22_to_router_15_22_rsp; - assign router_15_22_rsp_in[4] = magia_tile_ni_15_22_to_router_15_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_22_req_in), - .floo_rsp_o (router_15_22_rsp_out), - .floo_req_o (router_15_22_req_out), - .floo_rsp_i (router_15_22_rsp_in) -); - - -floo_req_t [4:0] router_15_23_req_in; -floo_rsp_t [4:0] router_15_23_rsp_out; -floo_req_t [4:0] router_15_23_req_out; -floo_rsp_t [4:0] router_15_23_rsp_in; - - assign router_15_23_req_in[0] = router_15_24_to_router_15_23_req; - assign router_15_23_req_in[1] = router_16_23_to_router_15_23_req; - assign router_15_23_req_in[2] = router_15_22_to_router_15_23_req; - assign router_15_23_req_in[3] = router_14_23_to_router_15_23_req; - assign router_15_23_req_in[4] = magia_tile_ni_15_23_to_router_15_23_req; - - assign router_15_23_to_router_15_24_rsp = router_15_23_rsp_out[0]; - assign router_15_23_to_router_16_23_rsp = router_15_23_rsp_out[1]; - assign router_15_23_to_router_15_22_rsp = router_15_23_rsp_out[2]; - assign router_15_23_to_router_14_23_rsp = router_15_23_rsp_out[3]; - assign router_15_23_to_magia_tile_ni_15_23_rsp = router_15_23_rsp_out[4]; - - assign router_15_23_to_router_15_24_req = router_15_23_req_out[0]; - assign router_15_23_to_router_16_23_req = router_15_23_req_out[1]; - assign router_15_23_to_router_15_22_req = router_15_23_req_out[2]; - assign router_15_23_to_router_14_23_req = router_15_23_req_out[3]; - assign router_15_23_to_magia_tile_ni_15_23_req = router_15_23_req_out[4]; - - assign router_15_23_rsp_in[0] = router_15_24_to_router_15_23_rsp; - assign router_15_23_rsp_in[1] = router_16_23_to_router_15_23_rsp; - assign router_15_23_rsp_in[2] = router_15_22_to_router_15_23_rsp; - assign router_15_23_rsp_in[3] = router_14_23_to_router_15_23_rsp; - assign router_15_23_rsp_in[4] = magia_tile_ni_15_23_to_router_15_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_23_req_in), - .floo_rsp_o (router_15_23_rsp_out), - .floo_req_o (router_15_23_req_out), - .floo_rsp_i (router_15_23_rsp_in) -); - - -floo_req_t [4:0] router_15_24_req_in; -floo_rsp_t [4:0] router_15_24_rsp_out; -floo_req_t [4:0] router_15_24_req_out; -floo_rsp_t [4:0] router_15_24_rsp_in; - - assign router_15_24_req_in[0] = router_15_25_to_router_15_24_req; - assign router_15_24_req_in[1] = router_16_24_to_router_15_24_req; - assign router_15_24_req_in[2] = router_15_23_to_router_15_24_req; - assign router_15_24_req_in[3] = router_14_24_to_router_15_24_req; - assign router_15_24_req_in[4] = magia_tile_ni_15_24_to_router_15_24_req; - - assign router_15_24_to_router_15_25_rsp = router_15_24_rsp_out[0]; - assign router_15_24_to_router_16_24_rsp = router_15_24_rsp_out[1]; - assign router_15_24_to_router_15_23_rsp = router_15_24_rsp_out[2]; - assign router_15_24_to_router_14_24_rsp = router_15_24_rsp_out[3]; - assign router_15_24_to_magia_tile_ni_15_24_rsp = router_15_24_rsp_out[4]; - - assign router_15_24_to_router_15_25_req = router_15_24_req_out[0]; - assign router_15_24_to_router_16_24_req = router_15_24_req_out[1]; - assign router_15_24_to_router_15_23_req = router_15_24_req_out[2]; - assign router_15_24_to_router_14_24_req = router_15_24_req_out[3]; - assign router_15_24_to_magia_tile_ni_15_24_req = router_15_24_req_out[4]; - - assign router_15_24_rsp_in[0] = router_15_25_to_router_15_24_rsp; - assign router_15_24_rsp_in[1] = router_16_24_to_router_15_24_rsp; - assign router_15_24_rsp_in[2] = router_15_23_to_router_15_24_rsp; - assign router_15_24_rsp_in[3] = router_14_24_to_router_15_24_rsp; - assign router_15_24_rsp_in[4] = magia_tile_ni_15_24_to_router_15_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_24_req_in), - .floo_rsp_o (router_15_24_rsp_out), - .floo_req_o (router_15_24_req_out), - .floo_rsp_i (router_15_24_rsp_in) -); - - -floo_req_t [4:0] router_15_25_req_in; -floo_rsp_t [4:0] router_15_25_rsp_out; -floo_req_t [4:0] router_15_25_req_out; -floo_rsp_t [4:0] router_15_25_rsp_in; - - assign router_15_25_req_in[0] = router_15_26_to_router_15_25_req; - assign router_15_25_req_in[1] = router_16_25_to_router_15_25_req; - assign router_15_25_req_in[2] = router_15_24_to_router_15_25_req; - assign router_15_25_req_in[3] = router_14_25_to_router_15_25_req; - assign router_15_25_req_in[4] = magia_tile_ni_15_25_to_router_15_25_req; - - assign router_15_25_to_router_15_26_rsp = router_15_25_rsp_out[0]; - assign router_15_25_to_router_16_25_rsp = router_15_25_rsp_out[1]; - assign router_15_25_to_router_15_24_rsp = router_15_25_rsp_out[2]; - assign router_15_25_to_router_14_25_rsp = router_15_25_rsp_out[3]; - assign router_15_25_to_magia_tile_ni_15_25_rsp = router_15_25_rsp_out[4]; - - assign router_15_25_to_router_15_26_req = router_15_25_req_out[0]; - assign router_15_25_to_router_16_25_req = router_15_25_req_out[1]; - assign router_15_25_to_router_15_24_req = router_15_25_req_out[2]; - assign router_15_25_to_router_14_25_req = router_15_25_req_out[3]; - assign router_15_25_to_magia_tile_ni_15_25_req = router_15_25_req_out[4]; - - assign router_15_25_rsp_in[0] = router_15_26_to_router_15_25_rsp; - assign router_15_25_rsp_in[1] = router_16_25_to_router_15_25_rsp; - assign router_15_25_rsp_in[2] = router_15_24_to_router_15_25_rsp; - assign router_15_25_rsp_in[3] = router_14_25_to_router_15_25_rsp; - assign router_15_25_rsp_in[4] = magia_tile_ni_15_25_to_router_15_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_25_req_in), - .floo_rsp_o (router_15_25_rsp_out), - .floo_req_o (router_15_25_req_out), - .floo_rsp_i (router_15_25_rsp_in) -); - - -floo_req_t [4:0] router_15_26_req_in; -floo_rsp_t [4:0] router_15_26_rsp_out; -floo_req_t [4:0] router_15_26_req_out; -floo_rsp_t [4:0] router_15_26_rsp_in; - - assign router_15_26_req_in[0] = router_15_27_to_router_15_26_req; - assign router_15_26_req_in[1] = router_16_26_to_router_15_26_req; - assign router_15_26_req_in[2] = router_15_25_to_router_15_26_req; - assign router_15_26_req_in[3] = router_14_26_to_router_15_26_req; - assign router_15_26_req_in[4] = magia_tile_ni_15_26_to_router_15_26_req; - - assign router_15_26_to_router_15_27_rsp = router_15_26_rsp_out[0]; - assign router_15_26_to_router_16_26_rsp = router_15_26_rsp_out[1]; - assign router_15_26_to_router_15_25_rsp = router_15_26_rsp_out[2]; - assign router_15_26_to_router_14_26_rsp = router_15_26_rsp_out[3]; - assign router_15_26_to_magia_tile_ni_15_26_rsp = router_15_26_rsp_out[4]; - - assign router_15_26_to_router_15_27_req = router_15_26_req_out[0]; - assign router_15_26_to_router_16_26_req = router_15_26_req_out[1]; - assign router_15_26_to_router_15_25_req = router_15_26_req_out[2]; - assign router_15_26_to_router_14_26_req = router_15_26_req_out[3]; - assign router_15_26_to_magia_tile_ni_15_26_req = router_15_26_req_out[4]; - - assign router_15_26_rsp_in[0] = router_15_27_to_router_15_26_rsp; - assign router_15_26_rsp_in[1] = router_16_26_to_router_15_26_rsp; - assign router_15_26_rsp_in[2] = router_15_25_to_router_15_26_rsp; - assign router_15_26_rsp_in[3] = router_14_26_to_router_15_26_rsp; - assign router_15_26_rsp_in[4] = magia_tile_ni_15_26_to_router_15_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_26_req_in), - .floo_rsp_o (router_15_26_rsp_out), - .floo_req_o (router_15_26_req_out), - .floo_rsp_i (router_15_26_rsp_in) -); - - -floo_req_t [4:0] router_15_27_req_in; -floo_rsp_t [4:0] router_15_27_rsp_out; -floo_req_t [4:0] router_15_27_req_out; -floo_rsp_t [4:0] router_15_27_rsp_in; - - assign router_15_27_req_in[0] = router_15_28_to_router_15_27_req; - assign router_15_27_req_in[1] = router_16_27_to_router_15_27_req; - assign router_15_27_req_in[2] = router_15_26_to_router_15_27_req; - assign router_15_27_req_in[3] = router_14_27_to_router_15_27_req; - assign router_15_27_req_in[4] = magia_tile_ni_15_27_to_router_15_27_req; - - assign router_15_27_to_router_15_28_rsp = router_15_27_rsp_out[0]; - assign router_15_27_to_router_16_27_rsp = router_15_27_rsp_out[1]; - assign router_15_27_to_router_15_26_rsp = router_15_27_rsp_out[2]; - assign router_15_27_to_router_14_27_rsp = router_15_27_rsp_out[3]; - assign router_15_27_to_magia_tile_ni_15_27_rsp = router_15_27_rsp_out[4]; - - assign router_15_27_to_router_15_28_req = router_15_27_req_out[0]; - assign router_15_27_to_router_16_27_req = router_15_27_req_out[1]; - assign router_15_27_to_router_15_26_req = router_15_27_req_out[2]; - assign router_15_27_to_router_14_27_req = router_15_27_req_out[3]; - assign router_15_27_to_magia_tile_ni_15_27_req = router_15_27_req_out[4]; - - assign router_15_27_rsp_in[0] = router_15_28_to_router_15_27_rsp; - assign router_15_27_rsp_in[1] = router_16_27_to_router_15_27_rsp; - assign router_15_27_rsp_in[2] = router_15_26_to_router_15_27_rsp; - assign router_15_27_rsp_in[3] = router_14_27_to_router_15_27_rsp; - assign router_15_27_rsp_in[4] = magia_tile_ni_15_27_to_router_15_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_27_req_in), - .floo_rsp_o (router_15_27_rsp_out), - .floo_req_o (router_15_27_req_out), - .floo_rsp_i (router_15_27_rsp_in) -); - - -floo_req_t [4:0] router_15_28_req_in; -floo_rsp_t [4:0] router_15_28_rsp_out; -floo_req_t [4:0] router_15_28_req_out; -floo_rsp_t [4:0] router_15_28_rsp_in; - - assign router_15_28_req_in[0] = router_15_29_to_router_15_28_req; - assign router_15_28_req_in[1] = router_16_28_to_router_15_28_req; - assign router_15_28_req_in[2] = router_15_27_to_router_15_28_req; - assign router_15_28_req_in[3] = router_14_28_to_router_15_28_req; - assign router_15_28_req_in[4] = magia_tile_ni_15_28_to_router_15_28_req; - - assign router_15_28_to_router_15_29_rsp = router_15_28_rsp_out[0]; - assign router_15_28_to_router_16_28_rsp = router_15_28_rsp_out[1]; - assign router_15_28_to_router_15_27_rsp = router_15_28_rsp_out[2]; - assign router_15_28_to_router_14_28_rsp = router_15_28_rsp_out[3]; - assign router_15_28_to_magia_tile_ni_15_28_rsp = router_15_28_rsp_out[4]; - - assign router_15_28_to_router_15_29_req = router_15_28_req_out[0]; - assign router_15_28_to_router_16_28_req = router_15_28_req_out[1]; - assign router_15_28_to_router_15_27_req = router_15_28_req_out[2]; - assign router_15_28_to_router_14_28_req = router_15_28_req_out[3]; - assign router_15_28_to_magia_tile_ni_15_28_req = router_15_28_req_out[4]; - - assign router_15_28_rsp_in[0] = router_15_29_to_router_15_28_rsp; - assign router_15_28_rsp_in[1] = router_16_28_to_router_15_28_rsp; - assign router_15_28_rsp_in[2] = router_15_27_to_router_15_28_rsp; - assign router_15_28_rsp_in[3] = router_14_28_to_router_15_28_rsp; - assign router_15_28_rsp_in[4] = magia_tile_ni_15_28_to_router_15_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_28_req_in), - .floo_rsp_o (router_15_28_rsp_out), - .floo_req_o (router_15_28_req_out), - .floo_rsp_i (router_15_28_rsp_in) -); - - -floo_req_t [4:0] router_15_29_req_in; -floo_rsp_t [4:0] router_15_29_rsp_out; -floo_req_t [4:0] router_15_29_req_out; -floo_rsp_t [4:0] router_15_29_rsp_in; - - assign router_15_29_req_in[0] = router_15_30_to_router_15_29_req; - assign router_15_29_req_in[1] = router_16_29_to_router_15_29_req; - assign router_15_29_req_in[2] = router_15_28_to_router_15_29_req; - assign router_15_29_req_in[3] = router_14_29_to_router_15_29_req; - assign router_15_29_req_in[4] = magia_tile_ni_15_29_to_router_15_29_req; - - assign router_15_29_to_router_15_30_rsp = router_15_29_rsp_out[0]; - assign router_15_29_to_router_16_29_rsp = router_15_29_rsp_out[1]; - assign router_15_29_to_router_15_28_rsp = router_15_29_rsp_out[2]; - assign router_15_29_to_router_14_29_rsp = router_15_29_rsp_out[3]; - assign router_15_29_to_magia_tile_ni_15_29_rsp = router_15_29_rsp_out[4]; - - assign router_15_29_to_router_15_30_req = router_15_29_req_out[0]; - assign router_15_29_to_router_16_29_req = router_15_29_req_out[1]; - assign router_15_29_to_router_15_28_req = router_15_29_req_out[2]; - assign router_15_29_to_router_14_29_req = router_15_29_req_out[3]; - assign router_15_29_to_magia_tile_ni_15_29_req = router_15_29_req_out[4]; - - assign router_15_29_rsp_in[0] = router_15_30_to_router_15_29_rsp; - assign router_15_29_rsp_in[1] = router_16_29_to_router_15_29_rsp; - assign router_15_29_rsp_in[2] = router_15_28_to_router_15_29_rsp; - assign router_15_29_rsp_in[3] = router_14_29_to_router_15_29_rsp; - assign router_15_29_rsp_in[4] = magia_tile_ni_15_29_to_router_15_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_29_req_in), - .floo_rsp_o (router_15_29_rsp_out), - .floo_req_o (router_15_29_req_out), - .floo_rsp_i (router_15_29_rsp_in) -); - - -floo_req_t [4:0] router_15_30_req_in; -floo_rsp_t [4:0] router_15_30_rsp_out; -floo_req_t [4:0] router_15_30_req_out; -floo_rsp_t [4:0] router_15_30_rsp_in; - - assign router_15_30_req_in[0] = router_15_31_to_router_15_30_req; - assign router_15_30_req_in[1] = router_16_30_to_router_15_30_req; - assign router_15_30_req_in[2] = router_15_29_to_router_15_30_req; - assign router_15_30_req_in[3] = router_14_30_to_router_15_30_req; - assign router_15_30_req_in[4] = magia_tile_ni_15_30_to_router_15_30_req; - - assign router_15_30_to_router_15_31_rsp = router_15_30_rsp_out[0]; - assign router_15_30_to_router_16_30_rsp = router_15_30_rsp_out[1]; - assign router_15_30_to_router_15_29_rsp = router_15_30_rsp_out[2]; - assign router_15_30_to_router_14_30_rsp = router_15_30_rsp_out[3]; - assign router_15_30_to_magia_tile_ni_15_30_rsp = router_15_30_rsp_out[4]; - - assign router_15_30_to_router_15_31_req = router_15_30_req_out[0]; - assign router_15_30_to_router_16_30_req = router_15_30_req_out[1]; - assign router_15_30_to_router_15_29_req = router_15_30_req_out[2]; - assign router_15_30_to_router_14_30_req = router_15_30_req_out[3]; - assign router_15_30_to_magia_tile_ni_15_30_req = router_15_30_req_out[4]; - - assign router_15_30_rsp_in[0] = router_15_31_to_router_15_30_rsp; - assign router_15_30_rsp_in[1] = router_16_30_to_router_15_30_rsp; - assign router_15_30_rsp_in[2] = router_15_29_to_router_15_30_rsp; - assign router_15_30_rsp_in[3] = router_14_30_to_router_15_30_rsp; - assign router_15_30_rsp_in[4] = magia_tile_ni_15_30_to_router_15_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_30_req_in), - .floo_rsp_o (router_15_30_rsp_out), - .floo_req_o (router_15_30_req_out), - .floo_rsp_i (router_15_30_rsp_in) -); - - -floo_req_t [4:0] router_15_31_req_in; -floo_rsp_t [4:0] router_15_31_rsp_out; -floo_req_t [4:0] router_15_31_req_out; -floo_rsp_t [4:0] router_15_31_rsp_in; - - assign router_15_31_req_in[0] = '0; - assign router_15_31_req_in[1] = router_16_31_to_router_15_31_req; - assign router_15_31_req_in[2] = router_15_30_to_router_15_31_req; - assign router_15_31_req_in[3] = router_14_31_to_router_15_31_req; - assign router_15_31_req_in[4] = magia_tile_ni_15_31_to_router_15_31_req; - - assign router_15_31_to_router_16_31_rsp = router_15_31_rsp_out[1]; - assign router_15_31_to_router_15_30_rsp = router_15_31_rsp_out[2]; - assign router_15_31_to_router_14_31_rsp = router_15_31_rsp_out[3]; - assign router_15_31_to_magia_tile_ni_15_31_rsp = router_15_31_rsp_out[4]; - - assign router_15_31_to_router_16_31_req = router_15_31_req_out[1]; - assign router_15_31_to_router_15_30_req = router_15_31_req_out[2]; - assign router_15_31_to_router_14_31_req = router_15_31_req_out[3]; - assign router_15_31_to_magia_tile_ni_15_31_req = router_15_31_req_out[4]; - - assign router_15_31_rsp_in[0] = '0; - assign router_15_31_rsp_in[1] = router_16_31_to_router_15_31_rsp; - assign router_15_31_rsp_in[2] = router_15_30_to_router_15_31_rsp; - assign router_15_31_rsp_in[3] = router_14_31_to_router_15_31_rsp; - assign router_15_31_rsp_in[4] = magia_tile_ni_15_31_to_router_15_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_15_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 16, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_15_31_req_in), - .floo_rsp_o (router_15_31_rsp_out), - .floo_req_o (router_15_31_req_out), - .floo_rsp_i (router_15_31_rsp_in) -); - - -floo_req_t [4:0] router_16_0_req_in; -floo_rsp_t [4:0] router_16_0_rsp_out; -floo_req_t [4:0] router_16_0_req_out; -floo_rsp_t [4:0] router_16_0_rsp_in; - - assign router_16_0_req_in[0] = router_16_1_to_router_16_0_req; - assign router_16_0_req_in[1] = router_17_0_to_router_16_0_req; - assign router_16_0_req_in[2] = '0; - assign router_16_0_req_in[3] = router_15_0_to_router_16_0_req; - assign router_16_0_req_in[4] = magia_tile_ni_16_0_to_router_16_0_req; - - assign router_16_0_to_router_16_1_rsp = router_16_0_rsp_out[0]; - assign router_16_0_to_router_17_0_rsp = router_16_0_rsp_out[1]; - assign router_16_0_to_router_15_0_rsp = router_16_0_rsp_out[3]; - assign router_16_0_to_magia_tile_ni_16_0_rsp = router_16_0_rsp_out[4]; - - assign router_16_0_to_router_16_1_req = router_16_0_req_out[0]; - assign router_16_0_to_router_17_0_req = router_16_0_req_out[1]; - assign router_16_0_to_router_15_0_req = router_16_0_req_out[3]; - assign router_16_0_to_magia_tile_ni_16_0_req = router_16_0_req_out[4]; - - assign router_16_0_rsp_in[0] = router_16_1_to_router_16_0_rsp; - assign router_16_0_rsp_in[1] = router_17_0_to_router_16_0_rsp; - assign router_16_0_rsp_in[2] = '0; - assign router_16_0_rsp_in[3] = router_15_0_to_router_16_0_rsp; - assign router_16_0_rsp_in[4] = magia_tile_ni_16_0_to_router_16_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_0_req_in), - .floo_rsp_o (router_16_0_rsp_out), - .floo_req_o (router_16_0_req_out), - .floo_rsp_i (router_16_0_rsp_in) -); - - -floo_req_t [4:0] router_16_1_req_in; -floo_rsp_t [4:0] router_16_1_rsp_out; -floo_req_t [4:0] router_16_1_req_out; -floo_rsp_t [4:0] router_16_1_rsp_in; - - assign router_16_1_req_in[0] = router_16_2_to_router_16_1_req; - assign router_16_1_req_in[1] = router_17_1_to_router_16_1_req; - assign router_16_1_req_in[2] = router_16_0_to_router_16_1_req; - assign router_16_1_req_in[3] = router_15_1_to_router_16_1_req; - assign router_16_1_req_in[4] = magia_tile_ni_16_1_to_router_16_1_req; - - assign router_16_1_to_router_16_2_rsp = router_16_1_rsp_out[0]; - assign router_16_1_to_router_17_1_rsp = router_16_1_rsp_out[1]; - assign router_16_1_to_router_16_0_rsp = router_16_1_rsp_out[2]; - assign router_16_1_to_router_15_1_rsp = router_16_1_rsp_out[3]; - assign router_16_1_to_magia_tile_ni_16_1_rsp = router_16_1_rsp_out[4]; - - assign router_16_1_to_router_16_2_req = router_16_1_req_out[0]; - assign router_16_1_to_router_17_1_req = router_16_1_req_out[1]; - assign router_16_1_to_router_16_0_req = router_16_1_req_out[2]; - assign router_16_1_to_router_15_1_req = router_16_1_req_out[3]; - assign router_16_1_to_magia_tile_ni_16_1_req = router_16_1_req_out[4]; - - assign router_16_1_rsp_in[0] = router_16_2_to_router_16_1_rsp; - assign router_16_1_rsp_in[1] = router_17_1_to_router_16_1_rsp; - assign router_16_1_rsp_in[2] = router_16_0_to_router_16_1_rsp; - assign router_16_1_rsp_in[3] = router_15_1_to_router_16_1_rsp; - assign router_16_1_rsp_in[4] = magia_tile_ni_16_1_to_router_16_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_1_req_in), - .floo_rsp_o (router_16_1_rsp_out), - .floo_req_o (router_16_1_req_out), - .floo_rsp_i (router_16_1_rsp_in) -); - - -floo_req_t [4:0] router_16_2_req_in; -floo_rsp_t [4:0] router_16_2_rsp_out; -floo_req_t [4:0] router_16_2_req_out; -floo_rsp_t [4:0] router_16_2_rsp_in; - - assign router_16_2_req_in[0] = router_16_3_to_router_16_2_req; - assign router_16_2_req_in[1] = router_17_2_to_router_16_2_req; - assign router_16_2_req_in[2] = router_16_1_to_router_16_2_req; - assign router_16_2_req_in[3] = router_15_2_to_router_16_2_req; - assign router_16_2_req_in[4] = magia_tile_ni_16_2_to_router_16_2_req; - - assign router_16_2_to_router_16_3_rsp = router_16_2_rsp_out[0]; - assign router_16_2_to_router_17_2_rsp = router_16_2_rsp_out[1]; - assign router_16_2_to_router_16_1_rsp = router_16_2_rsp_out[2]; - assign router_16_2_to_router_15_2_rsp = router_16_2_rsp_out[3]; - assign router_16_2_to_magia_tile_ni_16_2_rsp = router_16_2_rsp_out[4]; - - assign router_16_2_to_router_16_3_req = router_16_2_req_out[0]; - assign router_16_2_to_router_17_2_req = router_16_2_req_out[1]; - assign router_16_2_to_router_16_1_req = router_16_2_req_out[2]; - assign router_16_2_to_router_15_2_req = router_16_2_req_out[3]; - assign router_16_2_to_magia_tile_ni_16_2_req = router_16_2_req_out[4]; - - assign router_16_2_rsp_in[0] = router_16_3_to_router_16_2_rsp; - assign router_16_2_rsp_in[1] = router_17_2_to_router_16_2_rsp; - assign router_16_2_rsp_in[2] = router_16_1_to_router_16_2_rsp; - assign router_16_2_rsp_in[3] = router_15_2_to_router_16_2_rsp; - assign router_16_2_rsp_in[4] = magia_tile_ni_16_2_to_router_16_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_2_req_in), - .floo_rsp_o (router_16_2_rsp_out), - .floo_req_o (router_16_2_req_out), - .floo_rsp_i (router_16_2_rsp_in) -); - - -floo_req_t [4:0] router_16_3_req_in; -floo_rsp_t [4:0] router_16_3_rsp_out; -floo_req_t [4:0] router_16_3_req_out; -floo_rsp_t [4:0] router_16_3_rsp_in; - - assign router_16_3_req_in[0] = router_16_4_to_router_16_3_req; - assign router_16_3_req_in[1] = router_17_3_to_router_16_3_req; - assign router_16_3_req_in[2] = router_16_2_to_router_16_3_req; - assign router_16_3_req_in[3] = router_15_3_to_router_16_3_req; - assign router_16_3_req_in[4] = magia_tile_ni_16_3_to_router_16_3_req; - - assign router_16_3_to_router_16_4_rsp = router_16_3_rsp_out[0]; - assign router_16_3_to_router_17_3_rsp = router_16_3_rsp_out[1]; - assign router_16_3_to_router_16_2_rsp = router_16_3_rsp_out[2]; - assign router_16_3_to_router_15_3_rsp = router_16_3_rsp_out[3]; - assign router_16_3_to_magia_tile_ni_16_3_rsp = router_16_3_rsp_out[4]; - - assign router_16_3_to_router_16_4_req = router_16_3_req_out[0]; - assign router_16_3_to_router_17_3_req = router_16_3_req_out[1]; - assign router_16_3_to_router_16_2_req = router_16_3_req_out[2]; - assign router_16_3_to_router_15_3_req = router_16_3_req_out[3]; - assign router_16_3_to_magia_tile_ni_16_3_req = router_16_3_req_out[4]; - - assign router_16_3_rsp_in[0] = router_16_4_to_router_16_3_rsp; - assign router_16_3_rsp_in[1] = router_17_3_to_router_16_3_rsp; - assign router_16_3_rsp_in[2] = router_16_2_to_router_16_3_rsp; - assign router_16_3_rsp_in[3] = router_15_3_to_router_16_3_rsp; - assign router_16_3_rsp_in[4] = magia_tile_ni_16_3_to_router_16_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_3_req_in), - .floo_rsp_o (router_16_3_rsp_out), - .floo_req_o (router_16_3_req_out), - .floo_rsp_i (router_16_3_rsp_in) -); - - -floo_req_t [4:0] router_16_4_req_in; -floo_rsp_t [4:0] router_16_4_rsp_out; -floo_req_t [4:0] router_16_4_req_out; -floo_rsp_t [4:0] router_16_4_rsp_in; - - assign router_16_4_req_in[0] = router_16_5_to_router_16_4_req; - assign router_16_4_req_in[1] = router_17_4_to_router_16_4_req; - assign router_16_4_req_in[2] = router_16_3_to_router_16_4_req; - assign router_16_4_req_in[3] = router_15_4_to_router_16_4_req; - assign router_16_4_req_in[4] = magia_tile_ni_16_4_to_router_16_4_req; - - assign router_16_4_to_router_16_5_rsp = router_16_4_rsp_out[0]; - assign router_16_4_to_router_17_4_rsp = router_16_4_rsp_out[1]; - assign router_16_4_to_router_16_3_rsp = router_16_4_rsp_out[2]; - assign router_16_4_to_router_15_4_rsp = router_16_4_rsp_out[3]; - assign router_16_4_to_magia_tile_ni_16_4_rsp = router_16_4_rsp_out[4]; - - assign router_16_4_to_router_16_5_req = router_16_4_req_out[0]; - assign router_16_4_to_router_17_4_req = router_16_4_req_out[1]; - assign router_16_4_to_router_16_3_req = router_16_4_req_out[2]; - assign router_16_4_to_router_15_4_req = router_16_4_req_out[3]; - assign router_16_4_to_magia_tile_ni_16_4_req = router_16_4_req_out[4]; - - assign router_16_4_rsp_in[0] = router_16_5_to_router_16_4_rsp; - assign router_16_4_rsp_in[1] = router_17_4_to_router_16_4_rsp; - assign router_16_4_rsp_in[2] = router_16_3_to_router_16_4_rsp; - assign router_16_4_rsp_in[3] = router_15_4_to_router_16_4_rsp; - assign router_16_4_rsp_in[4] = magia_tile_ni_16_4_to_router_16_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_4_req_in), - .floo_rsp_o (router_16_4_rsp_out), - .floo_req_o (router_16_4_req_out), - .floo_rsp_i (router_16_4_rsp_in) -); - - -floo_req_t [4:0] router_16_5_req_in; -floo_rsp_t [4:0] router_16_5_rsp_out; -floo_req_t [4:0] router_16_5_req_out; -floo_rsp_t [4:0] router_16_5_rsp_in; - - assign router_16_5_req_in[0] = router_16_6_to_router_16_5_req; - assign router_16_5_req_in[1] = router_17_5_to_router_16_5_req; - assign router_16_5_req_in[2] = router_16_4_to_router_16_5_req; - assign router_16_5_req_in[3] = router_15_5_to_router_16_5_req; - assign router_16_5_req_in[4] = magia_tile_ni_16_5_to_router_16_5_req; - - assign router_16_5_to_router_16_6_rsp = router_16_5_rsp_out[0]; - assign router_16_5_to_router_17_5_rsp = router_16_5_rsp_out[1]; - assign router_16_5_to_router_16_4_rsp = router_16_5_rsp_out[2]; - assign router_16_5_to_router_15_5_rsp = router_16_5_rsp_out[3]; - assign router_16_5_to_magia_tile_ni_16_5_rsp = router_16_5_rsp_out[4]; - - assign router_16_5_to_router_16_6_req = router_16_5_req_out[0]; - assign router_16_5_to_router_17_5_req = router_16_5_req_out[1]; - assign router_16_5_to_router_16_4_req = router_16_5_req_out[2]; - assign router_16_5_to_router_15_5_req = router_16_5_req_out[3]; - assign router_16_5_to_magia_tile_ni_16_5_req = router_16_5_req_out[4]; - - assign router_16_5_rsp_in[0] = router_16_6_to_router_16_5_rsp; - assign router_16_5_rsp_in[1] = router_17_5_to_router_16_5_rsp; - assign router_16_5_rsp_in[2] = router_16_4_to_router_16_5_rsp; - assign router_16_5_rsp_in[3] = router_15_5_to_router_16_5_rsp; - assign router_16_5_rsp_in[4] = magia_tile_ni_16_5_to_router_16_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_5_req_in), - .floo_rsp_o (router_16_5_rsp_out), - .floo_req_o (router_16_5_req_out), - .floo_rsp_i (router_16_5_rsp_in) -); - - -floo_req_t [4:0] router_16_6_req_in; -floo_rsp_t [4:0] router_16_6_rsp_out; -floo_req_t [4:0] router_16_6_req_out; -floo_rsp_t [4:0] router_16_6_rsp_in; - - assign router_16_6_req_in[0] = router_16_7_to_router_16_6_req; - assign router_16_6_req_in[1] = router_17_6_to_router_16_6_req; - assign router_16_6_req_in[2] = router_16_5_to_router_16_6_req; - assign router_16_6_req_in[3] = router_15_6_to_router_16_6_req; - assign router_16_6_req_in[4] = magia_tile_ni_16_6_to_router_16_6_req; - - assign router_16_6_to_router_16_7_rsp = router_16_6_rsp_out[0]; - assign router_16_6_to_router_17_6_rsp = router_16_6_rsp_out[1]; - assign router_16_6_to_router_16_5_rsp = router_16_6_rsp_out[2]; - assign router_16_6_to_router_15_6_rsp = router_16_6_rsp_out[3]; - assign router_16_6_to_magia_tile_ni_16_6_rsp = router_16_6_rsp_out[4]; - - assign router_16_6_to_router_16_7_req = router_16_6_req_out[0]; - assign router_16_6_to_router_17_6_req = router_16_6_req_out[1]; - assign router_16_6_to_router_16_5_req = router_16_6_req_out[2]; - assign router_16_6_to_router_15_6_req = router_16_6_req_out[3]; - assign router_16_6_to_magia_tile_ni_16_6_req = router_16_6_req_out[4]; - - assign router_16_6_rsp_in[0] = router_16_7_to_router_16_6_rsp; - assign router_16_6_rsp_in[1] = router_17_6_to_router_16_6_rsp; - assign router_16_6_rsp_in[2] = router_16_5_to_router_16_6_rsp; - assign router_16_6_rsp_in[3] = router_15_6_to_router_16_6_rsp; - assign router_16_6_rsp_in[4] = magia_tile_ni_16_6_to_router_16_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_6_req_in), - .floo_rsp_o (router_16_6_rsp_out), - .floo_req_o (router_16_6_req_out), - .floo_rsp_i (router_16_6_rsp_in) -); - - -floo_req_t [4:0] router_16_7_req_in; -floo_rsp_t [4:0] router_16_7_rsp_out; -floo_req_t [4:0] router_16_7_req_out; -floo_rsp_t [4:0] router_16_7_rsp_in; - - assign router_16_7_req_in[0] = router_16_8_to_router_16_7_req; - assign router_16_7_req_in[1] = router_17_7_to_router_16_7_req; - assign router_16_7_req_in[2] = router_16_6_to_router_16_7_req; - assign router_16_7_req_in[3] = router_15_7_to_router_16_7_req; - assign router_16_7_req_in[4] = magia_tile_ni_16_7_to_router_16_7_req; - - assign router_16_7_to_router_16_8_rsp = router_16_7_rsp_out[0]; - assign router_16_7_to_router_17_7_rsp = router_16_7_rsp_out[1]; - assign router_16_7_to_router_16_6_rsp = router_16_7_rsp_out[2]; - assign router_16_7_to_router_15_7_rsp = router_16_7_rsp_out[3]; - assign router_16_7_to_magia_tile_ni_16_7_rsp = router_16_7_rsp_out[4]; - - assign router_16_7_to_router_16_8_req = router_16_7_req_out[0]; - assign router_16_7_to_router_17_7_req = router_16_7_req_out[1]; - assign router_16_7_to_router_16_6_req = router_16_7_req_out[2]; - assign router_16_7_to_router_15_7_req = router_16_7_req_out[3]; - assign router_16_7_to_magia_tile_ni_16_7_req = router_16_7_req_out[4]; - - assign router_16_7_rsp_in[0] = router_16_8_to_router_16_7_rsp; - assign router_16_7_rsp_in[1] = router_17_7_to_router_16_7_rsp; - assign router_16_7_rsp_in[2] = router_16_6_to_router_16_7_rsp; - assign router_16_7_rsp_in[3] = router_15_7_to_router_16_7_rsp; - assign router_16_7_rsp_in[4] = magia_tile_ni_16_7_to_router_16_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_7_req_in), - .floo_rsp_o (router_16_7_rsp_out), - .floo_req_o (router_16_7_req_out), - .floo_rsp_i (router_16_7_rsp_in) -); - - -floo_req_t [4:0] router_16_8_req_in; -floo_rsp_t [4:0] router_16_8_rsp_out; -floo_req_t [4:0] router_16_8_req_out; -floo_rsp_t [4:0] router_16_8_rsp_in; - - assign router_16_8_req_in[0] = router_16_9_to_router_16_8_req; - assign router_16_8_req_in[1] = router_17_8_to_router_16_8_req; - assign router_16_8_req_in[2] = router_16_7_to_router_16_8_req; - assign router_16_8_req_in[3] = router_15_8_to_router_16_8_req; - assign router_16_8_req_in[4] = magia_tile_ni_16_8_to_router_16_8_req; - - assign router_16_8_to_router_16_9_rsp = router_16_8_rsp_out[0]; - assign router_16_8_to_router_17_8_rsp = router_16_8_rsp_out[1]; - assign router_16_8_to_router_16_7_rsp = router_16_8_rsp_out[2]; - assign router_16_8_to_router_15_8_rsp = router_16_8_rsp_out[3]; - assign router_16_8_to_magia_tile_ni_16_8_rsp = router_16_8_rsp_out[4]; - - assign router_16_8_to_router_16_9_req = router_16_8_req_out[0]; - assign router_16_8_to_router_17_8_req = router_16_8_req_out[1]; - assign router_16_8_to_router_16_7_req = router_16_8_req_out[2]; - assign router_16_8_to_router_15_8_req = router_16_8_req_out[3]; - assign router_16_8_to_magia_tile_ni_16_8_req = router_16_8_req_out[4]; - - assign router_16_8_rsp_in[0] = router_16_9_to_router_16_8_rsp; - assign router_16_8_rsp_in[1] = router_17_8_to_router_16_8_rsp; - assign router_16_8_rsp_in[2] = router_16_7_to_router_16_8_rsp; - assign router_16_8_rsp_in[3] = router_15_8_to_router_16_8_rsp; - assign router_16_8_rsp_in[4] = magia_tile_ni_16_8_to_router_16_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_8_req_in), - .floo_rsp_o (router_16_8_rsp_out), - .floo_req_o (router_16_8_req_out), - .floo_rsp_i (router_16_8_rsp_in) -); - - -floo_req_t [4:0] router_16_9_req_in; -floo_rsp_t [4:0] router_16_9_rsp_out; -floo_req_t [4:0] router_16_9_req_out; -floo_rsp_t [4:0] router_16_9_rsp_in; - - assign router_16_9_req_in[0] = router_16_10_to_router_16_9_req; - assign router_16_9_req_in[1] = router_17_9_to_router_16_9_req; - assign router_16_9_req_in[2] = router_16_8_to_router_16_9_req; - assign router_16_9_req_in[3] = router_15_9_to_router_16_9_req; - assign router_16_9_req_in[4] = magia_tile_ni_16_9_to_router_16_9_req; - - assign router_16_9_to_router_16_10_rsp = router_16_9_rsp_out[0]; - assign router_16_9_to_router_17_9_rsp = router_16_9_rsp_out[1]; - assign router_16_9_to_router_16_8_rsp = router_16_9_rsp_out[2]; - assign router_16_9_to_router_15_9_rsp = router_16_9_rsp_out[3]; - assign router_16_9_to_magia_tile_ni_16_9_rsp = router_16_9_rsp_out[4]; - - assign router_16_9_to_router_16_10_req = router_16_9_req_out[0]; - assign router_16_9_to_router_17_9_req = router_16_9_req_out[1]; - assign router_16_9_to_router_16_8_req = router_16_9_req_out[2]; - assign router_16_9_to_router_15_9_req = router_16_9_req_out[3]; - assign router_16_9_to_magia_tile_ni_16_9_req = router_16_9_req_out[4]; - - assign router_16_9_rsp_in[0] = router_16_10_to_router_16_9_rsp; - assign router_16_9_rsp_in[1] = router_17_9_to_router_16_9_rsp; - assign router_16_9_rsp_in[2] = router_16_8_to_router_16_9_rsp; - assign router_16_9_rsp_in[3] = router_15_9_to_router_16_9_rsp; - assign router_16_9_rsp_in[4] = magia_tile_ni_16_9_to_router_16_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_9_req_in), - .floo_rsp_o (router_16_9_rsp_out), - .floo_req_o (router_16_9_req_out), - .floo_rsp_i (router_16_9_rsp_in) -); - - -floo_req_t [4:0] router_16_10_req_in; -floo_rsp_t [4:0] router_16_10_rsp_out; -floo_req_t [4:0] router_16_10_req_out; -floo_rsp_t [4:0] router_16_10_rsp_in; - - assign router_16_10_req_in[0] = router_16_11_to_router_16_10_req; - assign router_16_10_req_in[1] = router_17_10_to_router_16_10_req; - assign router_16_10_req_in[2] = router_16_9_to_router_16_10_req; - assign router_16_10_req_in[3] = router_15_10_to_router_16_10_req; - assign router_16_10_req_in[4] = magia_tile_ni_16_10_to_router_16_10_req; - - assign router_16_10_to_router_16_11_rsp = router_16_10_rsp_out[0]; - assign router_16_10_to_router_17_10_rsp = router_16_10_rsp_out[1]; - assign router_16_10_to_router_16_9_rsp = router_16_10_rsp_out[2]; - assign router_16_10_to_router_15_10_rsp = router_16_10_rsp_out[3]; - assign router_16_10_to_magia_tile_ni_16_10_rsp = router_16_10_rsp_out[4]; - - assign router_16_10_to_router_16_11_req = router_16_10_req_out[0]; - assign router_16_10_to_router_17_10_req = router_16_10_req_out[1]; - assign router_16_10_to_router_16_9_req = router_16_10_req_out[2]; - assign router_16_10_to_router_15_10_req = router_16_10_req_out[3]; - assign router_16_10_to_magia_tile_ni_16_10_req = router_16_10_req_out[4]; - - assign router_16_10_rsp_in[0] = router_16_11_to_router_16_10_rsp; - assign router_16_10_rsp_in[1] = router_17_10_to_router_16_10_rsp; - assign router_16_10_rsp_in[2] = router_16_9_to_router_16_10_rsp; - assign router_16_10_rsp_in[3] = router_15_10_to_router_16_10_rsp; - assign router_16_10_rsp_in[4] = magia_tile_ni_16_10_to_router_16_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_10_req_in), - .floo_rsp_o (router_16_10_rsp_out), - .floo_req_o (router_16_10_req_out), - .floo_rsp_i (router_16_10_rsp_in) -); - - -floo_req_t [4:0] router_16_11_req_in; -floo_rsp_t [4:0] router_16_11_rsp_out; -floo_req_t [4:0] router_16_11_req_out; -floo_rsp_t [4:0] router_16_11_rsp_in; - - assign router_16_11_req_in[0] = router_16_12_to_router_16_11_req; - assign router_16_11_req_in[1] = router_17_11_to_router_16_11_req; - assign router_16_11_req_in[2] = router_16_10_to_router_16_11_req; - assign router_16_11_req_in[3] = router_15_11_to_router_16_11_req; - assign router_16_11_req_in[4] = magia_tile_ni_16_11_to_router_16_11_req; - - assign router_16_11_to_router_16_12_rsp = router_16_11_rsp_out[0]; - assign router_16_11_to_router_17_11_rsp = router_16_11_rsp_out[1]; - assign router_16_11_to_router_16_10_rsp = router_16_11_rsp_out[2]; - assign router_16_11_to_router_15_11_rsp = router_16_11_rsp_out[3]; - assign router_16_11_to_magia_tile_ni_16_11_rsp = router_16_11_rsp_out[4]; - - assign router_16_11_to_router_16_12_req = router_16_11_req_out[0]; - assign router_16_11_to_router_17_11_req = router_16_11_req_out[1]; - assign router_16_11_to_router_16_10_req = router_16_11_req_out[2]; - assign router_16_11_to_router_15_11_req = router_16_11_req_out[3]; - assign router_16_11_to_magia_tile_ni_16_11_req = router_16_11_req_out[4]; - - assign router_16_11_rsp_in[0] = router_16_12_to_router_16_11_rsp; - assign router_16_11_rsp_in[1] = router_17_11_to_router_16_11_rsp; - assign router_16_11_rsp_in[2] = router_16_10_to_router_16_11_rsp; - assign router_16_11_rsp_in[3] = router_15_11_to_router_16_11_rsp; - assign router_16_11_rsp_in[4] = magia_tile_ni_16_11_to_router_16_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_11_req_in), - .floo_rsp_o (router_16_11_rsp_out), - .floo_req_o (router_16_11_req_out), - .floo_rsp_i (router_16_11_rsp_in) -); - - -floo_req_t [4:0] router_16_12_req_in; -floo_rsp_t [4:0] router_16_12_rsp_out; -floo_req_t [4:0] router_16_12_req_out; -floo_rsp_t [4:0] router_16_12_rsp_in; - - assign router_16_12_req_in[0] = router_16_13_to_router_16_12_req; - assign router_16_12_req_in[1] = router_17_12_to_router_16_12_req; - assign router_16_12_req_in[2] = router_16_11_to_router_16_12_req; - assign router_16_12_req_in[3] = router_15_12_to_router_16_12_req; - assign router_16_12_req_in[4] = magia_tile_ni_16_12_to_router_16_12_req; - - assign router_16_12_to_router_16_13_rsp = router_16_12_rsp_out[0]; - assign router_16_12_to_router_17_12_rsp = router_16_12_rsp_out[1]; - assign router_16_12_to_router_16_11_rsp = router_16_12_rsp_out[2]; - assign router_16_12_to_router_15_12_rsp = router_16_12_rsp_out[3]; - assign router_16_12_to_magia_tile_ni_16_12_rsp = router_16_12_rsp_out[4]; - - assign router_16_12_to_router_16_13_req = router_16_12_req_out[0]; - assign router_16_12_to_router_17_12_req = router_16_12_req_out[1]; - assign router_16_12_to_router_16_11_req = router_16_12_req_out[2]; - assign router_16_12_to_router_15_12_req = router_16_12_req_out[3]; - assign router_16_12_to_magia_tile_ni_16_12_req = router_16_12_req_out[4]; - - assign router_16_12_rsp_in[0] = router_16_13_to_router_16_12_rsp; - assign router_16_12_rsp_in[1] = router_17_12_to_router_16_12_rsp; - assign router_16_12_rsp_in[2] = router_16_11_to_router_16_12_rsp; - assign router_16_12_rsp_in[3] = router_15_12_to_router_16_12_rsp; - assign router_16_12_rsp_in[4] = magia_tile_ni_16_12_to_router_16_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_12_req_in), - .floo_rsp_o (router_16_12_rsp_out), - .floo_req_o (router_16_12_req_out), - .floo_rsp_i (router_16_12_rsp_in) -); - - -floo_req_t [4:0] router_16_13_req_in; -floo_rsp_t [4:0] router_16_13_rsp_out; -floo_req_t [4:0] router_16_13_req_out; -floo_rsp_t [4:0] router_16_13_rsp_in; - - assign router_16_13_req_in[0] = router_16_14_to_router_16_13_req; - assign router_16_13_req_in[1] = router_17_13_to_router_16_13_req; - assign router_16_13_req_in[2] = router_16_12_to_router_16_13_req; - assign router_16_13_req_in[3] = router_15_13_to_router_16_13_req; - assign router_16_13_req_in[4] = magia_tile_ni_16_13_to_router_16_13_req; - - assign router_16_13_to_router_16_14_rsp = router_16_13_rsp_out[0]; - assign router_16_13_to_router_17_13_rsp = router_16_13_rsp_out[1]; - assign router_16_13_to_router_16_12_rsp = router_16_13_rsp_out[2]; - assign router_16_13_to_router_15_13_rsp = router_16_13_rsp_out[3]; - assign router_16_13_to_magia_tile_ni_16_13_rsp = router_16_13_rsp_out[4]; - - assign router_16_13_to_router_16_14_req = router_16_13_req_out[0]; - assign router_16_13_to_router_17_13_req = router_16_13_req_out[1]; - assign router_16_13_to_router_16_12_req = router_16_13_req_out[2]; - assign router_16_13_to_router_15_13_req = router_16_13_req_out[3]; - assign router_16_13_to_magia_tile_ni_16_13_req = router_16_13_req_out[4]; - - assign router_16_13_rsp_in[0] = router_16_14_to_router_16_13_rsp; - assign router_16_13_rsp_in[1] = router_17_13_to_router_16_13_rsp; - assign router_16_13_rsp_in[2] = router_16_12_to_router_16_13_rsp; - assign router_16_13_rsp_in[3] = router_15_13_to_router_16_13_rsp; - assign router_16_13_rsp_in[4] = magia_tile_ni_16_13_to_router_16_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_13_req_in), - .floo_rsp_o (router_16_13_rsp_out), - .floo_req_o (router_16_13_req_out), - .floo_rsp_i (router_16_13_rsp_in) -); - - -floo_req_t [4:0] router_16_14_req_in; -floo_rsp_t [4:0] router_16_14_rsp_out; -floo_req_t [4:0] router_16_14_req_out; -floo_rsp_t [4:0] router_16_14_rsp_in; - - assign router_16_14_req_in[0] = router_16_15_to_router_16_14_req; - assign router_16_14_req_in[1] = router_17_14_to_router_16_14_req; - assign router_16_14_req_in[2] = router_16_13_to_router_16_14_req; - assign router_16_14_req_in[3] = router_15_14_to_router_16_14_req; - assign router_16_14_req_in[4] = magia_tile_ni_16_14_to_router_16_14_req; - - assign router_16_14_to_router_16_15_rsp = router_16_14_rsp_out[0]; - assign router_16_14_to_router_17_14_rsp = router_16_14_rsp_out[1]; - assign router_16_14_to_router_16_13_rsp = router_16_14_rsp_out[2]; - assign router_16_14_to_router_15_14_rsp = router_16_14_rsp_out[3]; - assign router_16_14_to_magia_tile_ni_16_14_rsp = router_16_14_rsp_out[4]; - - assign router_16_14_to_router_16_15_req = router_16_14_req_out[0]; - assign router_16_14_to_router_17_14_req = router_16_14_req_out[1]; - assign router_16_14_to_router_16_13_req = router_16_14_req_out[2]; - assign router_16_14_to_router_15_14_req = router_16_14_req_out[3]; - assign router_16_14_to_magia_tile_ni_16_14_req = router_16_14_req_out[4]; - - assign router_16_14_rsp_in[0] = router_16_15_to_router_16_14_rsp; - assign router_16_14_rsp_in[1] = router_17_14_to_router_16_14_rsp; - assign router_16_14_rsp_in[2] = router_16_13_to_router_16_14_rsp; - assign router_16_14_rsp_in[3] = router_15_14_to_router_16_14_rsp; - assign router_16_14_rsp_in[4] = magia_tile_ni_16_14_to_router_16_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_14_req_in), - .floo_rsp_o (router_16_14_rsp_out), - .floo_req_o (router_16_14_req_out), - .floo_rsp_i (router_16_14_rsp_in) -); - - -floo_req_t [4:0] router_16_15_req_in; -floo_rsp_t [4:0] router_16_15_rsp_out; -floo_req_t [4:0] router_16_15_req_out; -floo_rsp_t [4:0] router_16_15_rsp_in; - - assign router_16_15_req_in[0] = router_16_16_to_router_16_15_req; - assign router_16_15_req_in[1] = router_17_15_to_router_16_15_req; - assign router_16_15_req_in[2] = router_16_14_to_router_16_15_req; - assign router_16_15_req_in[3] = router_15_15_to_router_16_15_req; - assign router_16_15_req_in[4] = magia_tile_ni_16_15_to_router_16_15_req; - - assign router_16_15_to_router_16_16_rsp = router_16_15_rsp_out[0]; - assign router_16_15_to_router_17_15_rsp = router_16_15_rsp_out[1]; - assign router_16_15_to_router_16_14_rsp = router_16_15_rsp_out[2]; - assign router_16_15_to_router_15_15_rsp = router_16_15_rsp_out[3]; - assign router_16_15_to_magia_tile_ni_16_15_rsp = router_16_15_rsp_out[4]; - - assign router_16_15_to_router_16_16_req = router_16_15_req_out[0]; - assign router_16_15_to_router_17_15_req = router_16_15_req_out[1]; - assign router_16_15_to_router_16_14_req = router_16_15_req_out[2]; - assign router_16_15_to_router_15_15_req = router_16_15_req_out[3]; - assign router_16_15_to_magia_tile_ni_16_15_req = router_16_15_req_out[4]; - - assign router_16_15_rsp_in[0] = router_16_16_to_router_16_15_rsp; - assign router_16_15_rsp_in[1] = router_17_15_to_router_16_15_rsp; - assign router_16_15_rsp_in[2] = router_16_14_to_router_16_15_rsp; - assign router_16_15_rsp_in[3] = router_15_15_to_router_16_15_rsp; - assign router_16_15_rsp_in[4] = magia_tile_ni_16_15_to_router_16_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_15_req_in), - .floo_rsp_o (router_16_15_rsp_out), - .floo_req_o (router_16_15_req_out), - .floo_rsp_i (router_16_15_rsp_in) -); - - -floo_req_t [4:0] router_16_16_req_in; -floo_rsp_t [4:0] router_16_16_rsp_out; -floo_req_t [4:0] router_16_16_req_out; -floo_rsp_t [4:0] router_16_16_rsp_in; - - assign router_16_16_req_in[0] = router_16_17_to_router_16_16_req; - assign router_16_16_req_in[1] = router_17_16_to_router_16_16_req; - assign router_16_16_req_in[2] = router_16_15_to_router_16_16_req; - assign router_16_16_req_in[3] = router_15_16_to_router_16_16_req; - assign router_16_16_req_in[4] = magia_tile_ni_16_16_to_router_16_16_req; - - assign router_16_16_to_router_16_17_rsp = router_16_16_rsp_out[0]; - assign router_16_16_to_router_17_16_rsp = router_16_16_rsp_out[1]; - assign router_16_16_to_router_16_15_rsp = router_16_16_rsp_out[2]; - assign router_16_16_to_router_15_16_rsp = router_16_16_rsp_out[3]; - assign router_16_16_to_magia_tile_ni_16_16_rsp = router_16_16_rsp_out[4]; - - assign router_16_16_to_router_16_17_req = router_16_16_req_out[0]; - assign router_16_16_to_router_17_16_req = router_16_16_req_out[1]; - assign router_16_16_to_router_16_15_req = router_16_16_req_out[2]; - assign router_16_16_to_router_15_16_req = router_16_16_req_out[3]; - assign router_16_16_to_magia_tile_ni_16_16_req = router_16_16_req_out[4]; - - assign router_16_16_rsp_in[0] = router_16_17_to_router_16_16_rsp; - assign router_16_16_rsp_in[1] = router_17_16_to_router_16_16_rsp; - assign router_16_16_rsp_in[2] = router_16_15_to_router_16_16_rsp; - assign router_16_16_rsp_in[3] = router_15_16_to_router_16_16_rsp; - assign router_16_16_rsp_in[4] = magia_tile_ni_16_16_to_router_16_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_16_req_in), - .floo_rsp_o (router_16_16_rsp_out), - .floo_req_o (router_16_16_req_out), - .floo_rsp_i (router_16_16_rsp_in) -); - - -floo_req_t [4:0] router_16_17_req_in; -floo_rsp_t [4:0] router_16_17_rsp_out; -floo_req_t [4:0] router_16_17_req_out; -floo_rsp_t [4:0] router_16_17_rsp_in; - - assign router_16_17_req_in[0] = router_16_18_to_router_16_17_req; - assign router_16_17_req_in[1] = router_17_17_to_router_16_17_req; - assign router_16_17_req_in[2] = router_16_16_to_router_16_17_req; - assign router_16_17_req_in[3] = router_15_17_to_router_16_17_req; - assign router_16_17_req_in[4] = magia_tile_ni_16_17_to_router_16_17_req; - - assign router_16_17_to_router_16_18_rsp = router_16_17_rsp_out[0]; - assign router_16_17_to_router_17_17_rsp = router_16_17_rsp_out[1]; - assign router_16_17_to_router_16_16_rsp = router_16_17_rsp_out[2]; - assign router_16_17_to_router_15_17_rsp = router_16_17_rsp_out[3]; - assign router_16_17_to_magia_tile_ni_16_17_rsp = router_16_17_rsp_out[4]; - - assign router_16_17_to_router_16_18_req = router_16_17_req_out[0]; - assign router_16_17_to_router_17_17_req = router_16_17_req_out[1]; - assign router_16_17_to_router_16_16_req = router_16_17_req_out[2]; - assign router_16_17_to_router_15_17_req = router_16_17_req_out[3]; - assign router_16_17_to_magia_tile_ni_16_17_req = router_16_17_req_out[4]; - - assign router_16_17_rsp_in[0] = router_16_18_to_router_16_17_rsp; - assign router_16_17_rsp_in[1] = router_17_17_to_router_16_17_rsp; - assign router_16_17_rsp_in[2] = router_16_16_to_router_16_17_rsp; - assign router_16_17_rsp_in[3] = router_15_17_to_router_16_17_rsp; - assign router_16_17_rsp_in[4] = magia_tile_ni_16_17_to_router_16_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_17_req_in), - .floo_rsp_o (router_16_17_rsp_out), - .floo_req_o (router_16_17_req_out), - .floo_rsp_i (router_16_17_rsp_in) -); - - -floo_req_t [4:0] router_16_18_req_in; -floo_rsp_t [4:0] router_16_18_rsp_out; -floo_req_t [4:0] router_16_18_req_out; -floo_rsp_t [4:0] router_16_18_rsp_in; - - assign router_16_18_req_in[0] = router_16_19_to_router_16_18_req; - assign router_16_18_req_in[1] = router_17_18_to_router_16_18_req; - assign router_16_18_req_in[2] = router_16_17_to_router_16_18_req; - assign router_16_18_req_in[3] = router_15_18_to_router_16_18_req; - assign router_16_18_req_in[4] = magia_tile_ni_16_18_to_router_16_18_req; - - assign router_16_18_to_router_16_19_rsp = router_16_18_rsp_out[0]; - assign router_16_18_to_router_17_18_rsp = router_16_18_rsp_out[1]; - assign router_16_18_to_router_16_17_rsp = router_16_18_rsp_out[2]; - assign router_16_18_to_router_15_18_rsp = router_16_18_rsp_out[3]; - assign router_16_18_to_magia_tile_ni_16_18_rsp = router_16_18_rsp_out[4]; - - assign router_16_18_to_router_16_19_req = router_16_18_req_out[0]; - assign router_16_18_to_router_17_18_req = router_16_18_req_out[1]; - assign router_16_18_to_router_16_17_req = router_16_18_req_out[2]; - assign router_16_18_to_router_15_18_req = router_16_18_req_out[3]; - assign router_16_18_to_magia_tile_ni_16_18_req = router_16_18_req_out[4]; - - assign router_16_18_rsp_in[0] = router_16_19_to_router_16_18_rsp; - assign router_16_18_rsp_in[1] = router_17_18_to_router_16_18_rsp; - assign router_16_18_rsp_in[2] = router_16_17_to_router_16_18_rsp; - assign router_16_18_rsp_in[3] = router_15_18_to_router_16_18_rsp; - assign router_16_18_rsp_in[4] = magia_tile_ni_16_18_to_router_16_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_18_req_in), - .floo_rsp_o (router_16_18_rsp_out), - .floo_req_o (router_16_18_req_out), - .floo_rsp_i (router_16_18_rsp_in) -); - - -floo_req_t [4:0] router_16_19_req_in; -floo_rsp_t [4:0] router_16_19_rsp_out; -floo_req_t [4:0] router_16_19_req_out; -floo_rsp_t [4:0] router_16_19_rsp_in; - - assign router_16_19_req_in[0] = router_16_20_to_router_16_19_req; - assign router_16_19_req_in[1] = router_17_19_to_router_16_19_req; - assign router_16_19_req_in[2] = router_16_18_to_router_16_19_req; - assign router_16_19_req_in[3] = router_15_19_to_router_16_19_req; - assign router_16_19_req_in[4] = magia_tile_ni_16_19_to_router_16_19_req; - - assign router_16_19_to_router_16_20_rsp = router_16_19_rsp_out[0]; - assign router_16_19_to_router_17_19_rsp = router_16_19_rsp_out[1]; - assign router_16_19_to_router_16_18_rsp = router_16_19_rsp_out[2]; - assign router_16_19_to_router_15_19_rsp = router_16_19_rsp_out[3]; - assign router_16_19_to_magia_tile_ni_16_19_rsp = router_16_19_rsp_out[4]; - - assign router_16_19_to_router_16_20_req = router_16_19_req_out[0]; - assign router_16_19_to_router_17_19_req = router_16_19_req_out[1]; - assign router_16_19_to_router_16_18_req = router_16_19_req_out[2]; - assign router_16_19_to_router_15_19_req = router_16_19_req_out[3]; - assign router_16_19_to_magia_tile_ni_16_19_req = router_16_19_req_out[4]; - - assign router_16_19_rsp_in[0] = router_16_20_to_router_16_19_rsp; - assign router_16_19_rsp_in[1] = router_17_19_to_router_16_19_rsp; - assign router_16_19_rsp_in[2] = router_16_18_to_router_16_19_rsp; - assign router_16_19_rsp_in[3] = router_15_19_to_router_16_19_rsp; - assign router_16_19_rsp_in[4] = magia_tile_ni_16_19_to_router_16_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_19_req_in), - .floo_rsp_o (router_16_19_rsp_out), - .floo_req_o (router_16_19_req_out), - .floo_rsp_i (router_16_19_rsp_in) -); - - -floo_req_t [4:0] router_16_20_req_in; -floo_rsp_t [4:0] router_16_20_rsp_out; -floo_req_t [4:0] router_16_20_req_out; -floo_rsp_t [4:0] router_16_20_rsp_in; - - assign router_16_20_req_in[0] = router_16_21_to_router_16_20_req; - assign router_16_20_req_in[1] = router_17_20_to_router_16_20_req; - assign router_16_20_req_in[2] = router_16_19_to_router_16_20_req; - assign router_16_20_req_in[3] = router_15_20_to_router_16_20_req; - assign router_16_20_req_in[4] = magia_tile_ni_16_20_to_router_16_20_req; - - assign router_16_20_to_router_16_21_rsp = router_16_20_rsp_out[0]; - assign router_16_20_to_router_17_20_rsp = router_16_20_rsp_out[1]; - assign router_16_20_to_router_16_19_rsp = router_16_20_rsp_out[2]; - assign router_16_20_to_router_15_20_rsp = router_16_20_rsp_out[3]; - assign router_16_20_to_magia_tile_ni_16_20_rsp = router_16_20_rsp_out[4]; - - assign router_16_20_to_router_16_21_req = router_16_20_req_out[0]; - assign router_16_20_to_router_17_20_req = router_16_20_req_out[1]; - assign router_16_20_to_router_16_19_req = router_16_20_req_out[2]; - assign router_16_20_to_router_15_20_req = router_16_20_req_out[3]; - assign router_16_20_to_magia_tile_ni_16_20_req = router_16_20_req_out[4]; - - assign router_16_20_rsp_in[0] = router_16_21_to_router_16_20_rsp; - assign router_16_20_rsp_in[1] = router_17_20_to_router_16_20_rsp; - assign router_16_20_rsp_in[2] = router_16_19_to_router_16_20_rsp; - assign router_16_20_rsp_in[3] = router_15_20_to_router_16_20_rsp; - assign router_16_20_rsp_in[4] = magia_tile_ni_16_20_to_router_16_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_20_req_in), - .floo_rsp_o (router_16_20_rsp_out), - .floo_req_o (router_16_20_req_out), - .floo_rsp_i (router_16_20_rsp_in) -); - - -floo_req_t [4:0] router_16_21_req_in; -floo_rsp_t [4:0] router_16_21_rsp_out; -floo_req_t [4:0] router_16_21_req_out; -floo_rsp_t [4:0] router_16_21_rsp_in; - - assign router_16_21_req_in[0] = router_16_22_to_router_16_21_req; - assign router_16_21_req_in[1] = router_17_21_to_router_16_21_req; - assign router_16_21_req_in[2] = router_16_20_to_router_16_21_req; - assign router_16_21_req_in[3] = router_15_21_to_router_16_21_req; - assign router_16_21_req_in[4] = magia_tile_ni_16_21_to_router_16_21_req; - - assign router_16_21_to_router_16_22_rsp = router_16_21_rsp_out[0]; - assign router_16_21_to_router_17_21_rsp = router_16_21_rsp_out[1]; - assign router_16_21_to_router_16_20_rsp = router_16_21_rsp_out[2]; - assign router_16_21_to_router_15_21_rsp = router_16_21_rsp_out[3]; - assign router_16_21_to_magia_tile_ni_16_21_rsp = router_16_21_rsp_out[4]; - - assign router_16_21_to_router_16_22_req = router_16_21_req_out[0]; - assign router_16_21_to_router_17_21_req = router_16_21_req_out[1]; - assign router_16_21_to_router_16_20_req = router_16_21_req_out[2]; - assign router_16_21_to_router_15_21_req = router_16_21_req_out[3]; - assign router_16_21_to_magia_tile_ni_16_21_req = router_16_21_req_out[4]; - - assign router_16_21_rsp_in[0] = router_16_22_to_router_16_21_rsp; - assign router_16_21_rsp_in[1] = router_17_21_to_router_16_21_rsp; - assign router_16_21_rsp_in[2] = router_16_20_to_router_16_21_rsp; - assign router_16_21_rsp_in[3] = router_15_21_to_router_16_21_rsp; - assign router_16_21_rsp_in[4] = magia_tile_ni_16_21_to_router_16_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_21_req_in), - .floo_rsp_o (router_16_21_rsp_out), - .floo_req_o (router_16_21_req_out), - .floo_rsp_i (router_16_21_rsp_in) -); - - -floo_req_t [4:0] router_16_22_req_in; -floo_rsp_t [4:0] router_16_22_rsp_out; -floo_req_t [4:0] router_16_22_req_out; -floo_rsp_t [4:0] router_16_22_rsp_in; - - assign router_16_22_req_in[0] = router_16_23_to_router_16_22_req; - assign router_16_22_req_in[1] = router_17_22_to_router_16_22_req; - assign router_16_22_req_in[2] = router_16_21_to_router_16_22_req; - assign router_16_22_req_in[3] = router_15_22_to_router_16_22_req; - assign router_16_22_req_in[4] = magia_tile_ni_16_22_to_router_16_22_req; - - assign router_16_22_to_router_16_23_rsp = router_16_22_rsp_out[0]; - assign router_16_22_to_router_17_22_rsp = router_16_22_rsp_out[1]; - assign router_16_22_to_router_16_21_rsp = router_16_22_rsp_out[2]; - assign router_16_22_to_router_15_22_rsp = router_16_22_rsp_out[3]; - assign router_16_22_to_magia_tile_ni_16_22_rsp = router_16_22_rsp_out[4]; - - assign router_16_22_to_router_16_23_req = router_16_22_req_out[0]; - assign router_16_22_to_router_17_22_req = router_16_22_req_out[1]; - assign router_16_22_to_router_16_21_req = router_16_22_req_out[2]; - assign router_16_22_to_router_15_22_req = router_16_22_req_out[3]; - assign router_16_22_to_magia_tile_ni_16_22_req = router_16_22_req_out[4]; - - assign router_16_22_rsp_in[0] = router_16_23_to_router_16_22_rsp; - assign router_16_22_rsp_in[1] = router_17_22_to_router_16_22_rsp; - assign router_16_22_rsp_in[2] = router_16_21_to_router_16_22_rsp; - assign router_16_22_rsp_in[3] = router_15_22_to_router_16_22_rsp; - assign router_16_22_rsp_in[4] = magia_tile_ni_16_22_to_router_16_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_22_req_in), - .floo_rsp_o (router_16_22_rsp_out), - .floo_req_o (router_16_22_req_out), - .floo_rsp_i (router_16_22_rsp_in) -); - - -floo_req_t [4:0] router_16_23_req_in; -floo_rsp_t [4:0] router_16_23_rsp_out; -floo_req_t [4:0] router_16_23_req_out; -floo_rsp_t [4:0] router_16_23_rsp_in; - - assign router_16_23_req_in[0] = router_16_24_to_router_16_23_req; - assign router_16_23_req_in[1] = router_17_23_to_router_16_23_req; - assign router_16_23_req_in[2] = router_16_22_to_router_16_23_req; - assign router_16_23_req_in[3] = router_15_23_to_router_16_23_req; - assign router_16_23_req_in[4] = magia_tile_ni_16_23_to_router_16_23_req; - - assign router_16_23_to_router_16_24_rsp = router_16_23_rsp_out[0]; - assign router_16_23_to_router_17_23_rsp = router_16_23_rsp_out[1]; - assign router_16_23_to_router_16_22_rsp = router_16_23_rsp_out[2]; - assign router_16_23_to_router_15_23_rsp = router_16_23_rsp_out[3]; - assign router_16_23_to_magia_tile_ni_16_23_rsp = router_16_23_rsp_out[4]; - - assign router_16_23_to_router_16_24_req = router_16_23_req_out[0]; - assign router_16_23_to_router_17_23_req = router_16_23_req_out[1]; - assign router_16_23_to_router_16_22_req = router_16_23_req_out[2]; - assign router_16_23_to_router_15_23_req = router_16_23_req_out[3]; - assign router_16_23_to_magia_tile_ni_16_23_req = router_16_23_req_out[4]; - - assign router_16_23_rsp_in[0] = router_16_24_to_router_16_23_rsp; - assign router_16_23_rsp_in[1] = router_17_23_to_router_16_23_rsp; - assign router_16_23_rsp_in[2] = router_16_22_to_router_16_23_rsp; - assign router_16_23_rsp_in[3] = router_15_23_to_router_16_23_rsp; - assign router_16_23_rsp_in[4] = magia_tile_ni_16_23_to_router_16_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_23_req_in), - .floo_rsp_o (router_16_23_rsp_out), - .floo_req_o (router_16_23_req_out), - .floo_rsp_i (router_16_23_rsp_in) -); - - -floo_req_t [4:0] router_16_24_req_in; -floo_rsp_t [4:0] router_16_24_rsp_out; -floo_req_t [4:0] router_16_24_req_out; -floo_rsp_t [4:0] router_16_24_rsp_in; - - assign router_16_24_req_in[0] = router_16_25_to_router_16_24_req; - assign router_16_24_req_in[1] = router_17_24_to_router_16_24_req; - assign router_16_24_req_in[2] = router_16_23_to_router_16_24_req; - assign router_16_24_req_in[3] = router_15_24_to_router_16_24_req; - assign router_16_24_req_in[4] = magia_tile_ni_16_24_to_router_16_24_req; - - assign router_16_24_to_router_16_25_rsp = router_16_24_rsp_out[0]; - assign router_16_24_to_router_17_24_rsp = router_16_24_rsp_out[1]; - assign router_16_24_to_router_16_23_rsp = router_16_24_rsp_out[2]; - assign router_16_24_to_router_15_24_rsp = router_16_24_rsp_out[3]; - assign router_16_24_to_magia_tile_ni_16_24_rsp = router_16_24_rsp_out[4]; - - assign router_16_24_to_router_16_25_req = router_16_24_req_out[0]; - assign router_16_24_to_router_17_24_req = router_16_24_req_out[1]; - assign router_16_24_to_router_16_23_req = router_16_24_req_out[2]; - assign router_16_24_to_router_15_24_req = router_16_24_req_out[3]; - assign router_16_24_to_magia_tile_ni_16_24_req = router_16_24_req_out[4]; - - assign router_16_24_rsp_in[0] = router_16_25_to_router_16_24_rsp; - assign router_16_24_rsp_in[1] = router_17_24_to_router_16_24_rsp; - assign router_16_24_rsp_in[2] = router_16_23_to_router_16_24_rsp; - assign router_16_24_rsp_in[3] = router_15_24_to_router_16_24_rsp; - assign router_16_24_rsp_in[4] = magia_tile_ni_16_24_to_router_16_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_24_req_in), - .floo_rsp_o (router_16_24_rsp_out), - .floo_req_o (router_16_24_req_out), - .floo_rsp_i (router_16_24_rsp_in) -); - - -floo_req_t [4:0] router_16_25_req_in; -floo_rsp_t [4:0] router_16_25_rsp_out; -floo_req_t [4:0] router_16_25_req_out; -floo_rsp_t [4:0] router_16_25_rsp_in; - - assign router_16_25_req_in[0] = router_16_26_to_router_16_25_req; - assign router_16_25_req_in[1] = router_17_25_to_router_16_25_req; - assign router_16_25_req_in[2] = router_16_24_to_router_16_25_req; - assign router_16_25_req_in[3] = router_15_25_to_router_16_25_req; - assign router_16_25_req_in[4] = magia_tile_ni_16_25_to_router_16_25_req; - - assign router_16_25_to_router_16_26_rsp = router_16_25_rsp_out[0]; - assign router_16_25_to_router_17_25_rsp = router_16_25_rsp_out[1]; - assign router_16_25_to_router_16_24_rsp = router_16_25_rsp_out[2]; - assign router_16_25_to_router_15_25_rsp = router_16_25_rsp_out[3]; - assign router_16_25_to_magia_tile_ni_16_25_rsp = router_16_25_rsp_out[4]; - - assign router_16_25_to_router_16_26_req = router_16_25_req_out[0]; - assign router_16_25_to_router_17_25_req = router_16_25_req_out[1]; - assign router_16_25_to_router_16_24_req = router_16_25_req_out[2]; - assign router_16_25_to_router_15_25_req = router_16_25_req_out[3]; - assign router_16_25_to_magia_tile_ni_16_25_req = router_16_25_req_out[4]; - - assign router_16_25_rsp_in[0] = router_16_26_to_router_16_25_rsp; - assign router_16_25_rsp_in[1] = router_17_25_to_router_16_25_rsp; - assign router_16_25_rsp_in[2] = router_16_24_to_router_16_25_rsp; - assign router_16_25_rsp_in[3] = router_15_25_to_router_16_25_rsp; - assign router_16_25_rsp_in[4] = magia_tile_ni_16_25_to_router_16_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_25_req_in), - .floo_rsp_o (router_16_25_rsp_out), - .floo_req_o (router_16_25_req_out), - .floo_rsp_i (router_16_25_rsp_in) -); - - -floo_req_t [4:0] router_16_26_req_in; -floo_rsp_t [4:0] router_16_26_rsp_out; -floo_req_t [4:0] router_16_26_req_out; -floo_rsp_t [4:0] router_16_26_rsp_in; - - assign router_16_26_req_in[0] = router_16_27_to_router_16_26_req; - assign router_16_26_req_in[1] = router_17_26_to_router_16_26_req; - assign router_16_26_req_in[2] = router_16_25_to_router_16_26_req; - assign router_16_26_req_in[3] = router_15_26_to_router_16_26_req; - assign router_16_26_req_in[4] = magia_tile_ni_16_26_to_router_16_26_req; - - assign router_16_26_to_router_16_27_rsp = router_16_26_rsp_out[0]; - assign router_16_26_to_router_17_26_rsp = router_16_26_rsp_out[1]; - assign router_16_26_to_router_16_25_rsp = router_16_26_rsp_out[2]; - assign router_16_26_to_router_15_26_rsp = router_16_26_rsp_out[3]; - assign router_16_26_to_magia_tile_ni_16_26_rsp = router_16_26_rsp_out[4]; - - assign router_16_26_to_router_16_27_req = router_16_26_req_out[0]; - assign router_16_26_to_router_17_26_req = router_16_26_req_out[1]; - assign router_16_26_to_router_16_25_req = router_16_26_req_out[2]; - assign router_16_26_to_router_15_26_req = router_16_26_req_out[3]; - assign router_16_26_to_magia_tile_ni_16_26_req = router_16_26_req_out[4]; - - assign router_16_26_rsp_in[0] = router_16_27_to_router_16_26_rsp; - assign router_16_26_rsp_in[1] = router_17_26_to_router_16_26_rsp; - assign router_16_26_rsp_in[2] = router_16_25_to_router_16_26_rsp; - assign router_16_26_rsp_in[3] = router_15_26_to_router_16_26_rsp; - assign router_16_26_rsp_in[4] = magia_tile_ni_16_26_to_router_16_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_26_req_in), - .floo_rsp_o (router_16_26_rsp_out), - .floo_req_o (router_16_26_req_out), - .floo_rsp_i (router_16_26_rsp_in) -); - - -floo_req_t [4:0] router_16_27_req_in; -floo_rsp_t [4:0] router_16_27_rsp_out; -floo_req_t [4:0] router_16_27_req_out; -floo_rsp_t [4:0] router_16_27_rsp_in; - - assign router_16_27_req_in[0] = router_16_28_to_router_16_27_req; - assign router_16_27_req_in[1] = router_17_27_to_router_16_27_req; - assign router_16_27_req_in[2] = router_16_26_to_router_16_27_req; - assign router_16_27_req_in[3] = router_15_27_to_router_16_27_req; - assign router_16_27_req_in[4] = magia_tile_ni_16_27_to_router_16_27_req; - - assign router_16_27_to_router_16_28_rsp = router_16_27_rsp_out[0]; - assign router_16_27_to_router_17_27_rsp = router_16_27_rsp_out[1]; - assign router_16_27_to_router_16_26_rsp = router_16_27_rsp_out[2]; - assign router_16_27_to_router_15_27_rsp = router_16_27_rsp_out[3]; - assign router_16_27_to_magia_tile_ni_16_27_rsp = router_16_27_rsp_out[4]; - - assign router_16_27_to_router_16_28_req = router_16_27_req_out[0]; - assign router_16_27_to_router_17_27_req = router_16_27_req_out[1]; - assign router_16_27_to_router_16_26_req = router_16_27_req_out[2]; - assign router_16_27_to_router_15_27_req = router_16_27_req_out[3]; - assign router_16_27_to_magia_tile_ni_16_27_req = router_16_27_req_out[4]; - - assign router_16_27_rsp_in[0] = router_16_28_to_router_16_27_rsp; - assign router_16_27_rsp_in[1] = router_17_27_to_router_16_27_rsp; - assign router_16_27_rsp_in[2] = router_16_26_to_router_16_27_rsp; - assign router_16_27_rsp_in[3] = router_15_27_to_router_16_27_rsp; - assign router_16_27_rsp_in[4] = magia_tile_ni_16_27_to_router_16_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_27_req_in), - .floo_rsp_o (router_16_27_rsp_out), - .floo_req_o (router_16_27_req_out), - .floo_rsp_i (router_16_27_rsp_in) -); - - -floo_req_t [4:0] router_16_28_req_in; -floo_rsp_t [4:0] router_16_28_rsp_out; -floo_req_t [4:0] router_16_28_req_out; -floo_rsp_t [4:0] router_16_28_rsp_in; - - assign router_16_28_req_in[0] = router_16_29_to_router_16_28_req; - assign router_16_28_req_in[1] = router_17_28_to_router_16_28_req; - assign router_16_28_req_in[2] = router_16_27_to_router_16_28_req; - assign router_16_28_req_in[3] = router_15_28_to_router_16_28_req; - assign router_16_28_req_in[4] = magia_tile_ni_16_28_to_router_16_28_req; - - assign router_16_28_to_router_16_29_rsp = router_16_28_rsp_out[0]; - assign router_16_28_to_router_17_28_rsp = router_16_28_rsp_out[1]; - assign router_16_28_to_router_16_27_rsp = router_16_28_rsp_out[2]; - assign router_16_28_to_router_15_28_rsp = router_16_28_rsp_out[3]; - assign router_16_28_to_magia_tile_ni_16_28_rsp = router_16_28_rsp_out[4]; - - assign router_16_28_to_router_16_29_req = router_16_28_req_out[0]; - assign router_16_28_to_router_17_28_req = router_16_28_req_out[1]; - assign router_16_28_to_router_16_27_req = router_16_28_req_out[2]; - assign router_16_28_to_router_15_28_req = router_16_28_req_out[3]; - assign router_16_28_to_magia_tile_ni_16_28_req = router_16_28_req_out[4]; - - assign router_16_28_rsp_in[0] = router_16_29_to_router_16_28_rsp; - assign router_16_28_rsp_in[1] = router_17_28_to_router_16_28_rsp; - assign router_16_28_rsp_in[2] = router_16_27_to_router_16_28_rsp; - assign router_16_28_rsp_in[3] = router_15_28_to_router_16_28_rsp; - assign router_16_28_rsp_in[4] = magia_tile_ni_16_28_to_router_16_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_28_req_in), - .floo_rsp_o (router_16_28_rsp_out), - .floo_req_o (router_16_28_req_out), - .floo_rsp_i (router_16_28_rsp_in) -); - - -floo_req_t [4:0] router_16_29_req_in; -floo_rsp_t [4:0] router_16_29_rsp_out; -floo_req_t [4:0] router_16_29_req_out; -floo_rsp_t [4:0] router_16_29_rsp_in; - - assign router_16_29_req_in[0] = router_16_30_to_router_16_29_req; - assign router_16_29_req_in[1] = router_17_29_to_router_16_29_req; - assign router_16_29_req_in[2] = router_16_28_to_router_16_29_req; - assign router_16_29_req_in[3] = router_15_29_to_router_16_29_req; - assign router_16_29_req_in[4] = magia_tile_ni_16_29_to_router_16_29_req; - - assign router_16_29_to_router_16_30_rsp = router_16_29_rsp_out[0]; - assign router_16_29_to_router_17_29_rsp = router_16_29_rsp_out[1]; - assign router_16_29_to_router_16_28_rsp = router_16_29_rsp_out[2]; - assign router_16_29_to_router_15_29_rsp = router_16_29_rsp_out[3]; - assign router_16_29_to_magia_tile_ni_16_29_rsp = router_16_29_rsp_out[4]; - - assign router_16_29_to_router_16_30_req = router_16_29_req_out[0]; - assign router_16_29_to_router_17_29_req = router_16_29_req_out[1]; - assign router_16_29_to_router_16_28_req = router_16_29_req_out[2]; - assign router_16_29_to_router_15_29_req = router_16_29_req_out[3]; - assign router_16_29_to_magia_tile_ni_16_29_req = router_16_29_req_out[4]; - - assign router_16_29_rsp_in[0] = router_16_30_to_router_16_29_rsp; - assign router_16_29_rsp_in[1] = router_17_29_to_router_16_29_rsp; - assign router_16_29_rsp_in[2] = router_16_28_to_router_16_29_rsp; - assign router_16_29_rsp_in[3] = router_15_29_to_router_16_29_rsp; - assign router_16_29_rsp_in[4] = magia_tile_ni_16_29_to_router_16_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_29_req_in), - .floo_rsp_o (router_16_29_rsp_out), - .floo_req_o (router_16_29_req_out), - .floo_rsp_i (router_16_29_rsp_in) -); - - -floo_req_t [4:0] router_16_30_req_in; -floo_rsp_t [4:0] router_16_30_rsp_out; -floo_req_t [4:0] router_16_30_req_out; -floo_rsp_t [4:0] router_16_30_rsp_in; - - assign router_16_30_req_in[0] = router_16_31_to_router_16_30_req; - assign router_16_30_req_in[1] = router_17_30_to_router_16_30_req; - assign router_16_30_req_in[2] = router_16_29_to_router_16_30_req; - assign router_16_30_req_in[3] = router_15_30_to_router_16_30_req; - assign router_16_30_req_in[4] = magia_tile_ni_16_30_to_router_16_30_req; - - assign router_16_30_to_router_16_31_rsp = router_16_30_rsp_out[0]; - assign router_16_30_to_router_17_30_rsp = router_16_30_rsp_out[1]; - assign router_16_30_to_router_16_29_rsp = router_16_30_rsp_out[2]; - assign router_16_30_to_router_15_30_rsp = router_16_30_rsp_out[3]; - assign router_16_30_to_magia_tile_ni_16_30_rsp = router_16_30_rsp_out[4]; - - assign router_16_30_to_router_16_31_req = router_16_30_req_out[0]; - assign router_16_30_to_router_17_30_req = router_16_30_req_out[1]; - assign router_16_30_to_router_16_29_req = router_16_30_req_out[2]; - assign router_16_30_to_router_15_30_req = router_16_30_req_out[3]; - assign router_16_30_to_magia_tile_ni_16_30_req = router_16_30_req_out[4]; - - assign router_16_30_rsp_in[0] = router_16_31_to_router_16_30_rsp; - assign router_16_30_rsp_in[1] = router_17_30_to_router_16_30_rsp; - assign router_16_30_rsp_in[2] = router_16_29_to_router_16_30_rsp; - assign router_16_30_rsp_in[3] = router_15_30_to_router_16_30_rsp; - assign router_16_30_rsp_in[4] = magia_tile_ni_16_30_to_router_16_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_30_req_in), - .floo_rsp_o (router_16_30_rsp_out), - .floo_req_o (router_16_30_req_out), - .floo_rsp_i (router_16_30_rsp_in) -); - - -floo_req_t [4:0] router_16_31_req_in; -floo_rsp_t [4:0] router_16_31_rsp_out; -floo_req_t [4:0] router_16_31_req_out; -floo_rsp_t [4:0] router_16_31_rsp_in; - - assign router_16_31_req_in[0] = '0; - assign router_16_31_req_in[1] = router_17_31_to_router_16_31_req; - assign router_16_31_req_in[2] = router_16_30_to_router_16_31_req; - assign router_16_31_req_in[3] = router_15_31_to_router_16_31_req; - assign router_16_31_req_in[4] = magia_tile_ni_16_31_to_router_16_31_req; - - assign router_16_31_to_router_17_31_rsp = router_16_31_rsp_out[1]; - assign router_16_31_to_router_16_30_rsp = router_16_31_rsp_out[2]; - assign router_16_31_to_router_15_31_rsp = router_16_31_rsp_out[3]; - assign router_16_31_to_magia_tile_ni_16_31_rsp = router_16_31_rsp_out[4]; - - assign router_16_31_to_router_17_31_req = router_16_31_req_out[1]; - assign router_16_31_to_router_16_30_req = router_16_31_req_out[2]; - assign router_16_31_to_router_15_31_req = router_16_31_req_out[3]; - assign router_16_31_to_magia_tile_ni_16_31_req = router_16_31_req_out[4]; - - assign router_16_31_rsp_in[0] = '0; - assign router_16_31_rsp_in[1] = router_17_31_to_router_16_31_rsp; - assign router_16_31_rsp_in[2] = router_16_30_to_router_16_31_rsp; - assign router_16_31_rsp_in[3] = router_15_31_to_router_16_31_rsp; - assign router_16_31_rsp_in[4] = magia_tile_ni_16_31_to_router_16_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_16_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 17, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_16_31_req_in), - .floo_rsp_o (router_16_31_rsp_out), - .floo_req_o (router_16_31_req_out), - .floo_rsp_i (router_16_31_rsp_in) -); - - -floo_req_t [4:0] router_17_0_req_in; -floo_rsp_t [4:0] router_17_0_rsp_out; -floo_req_t [4:0] router_17_0_req_out; -floo_rsp_t [4:0] router_17_0_rsp_in; - - assign router_17_0_req_in[0] = router_17_1_to_router_17_0_req; - assign router_17_0_req_in[1] = router_18_0_to_router_17_0_req; - assign router_17_0_req_in[2] = '0; - assign router_17_0_req_in[3] = router_16_0_to_router_17_0_req; - assign router_17_0_req_in[4] = magia_tile_ni_17_0_to_router_17_0_req; - - assign router_17_0_to_router_17_1_rsp = router_17_0_rsp_out[0]; - assign router_17_0_to_router_18_0_rsp = router_17_0_rsp_out[1]; - assign router_17_0_to_router_16_0_rsp = router_17_0_rsp_out[3]; - assign router_17_0_to_magia_tile_ni_17_0_rsp = router_17_0_rsp_out[4]; - - assign router_17_0_to_router_17_1_req = router_17_0_req_out[0]; - assign router_17_0_to_router_18_0_req = router_17_0_req_out[1]; - assign router_17_0_to_router_16_0_req = router_17_0_req_out[3]; - assign router_17_0_to_magia_tile_ni_17_0_req = router_17_0_req_out[4]; - - assign router_17_0_rsp_in[0] = router_17_1_to_router_17_0_rsp; - assign router_17_0_rsp_in[1] = router_18_0_to_router_17_0_rsp; - assign router_17_0_rsp_in[2] = '0; - assign router_17_0_rsp_in[3] = router_16_0_to_router_17_0_rsp; - assign router_17_0_rsp_in[4] = magia_tile_ni_17_0_to_router_17_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_0_req_in), - .floo_rsp_o (router_17_0_rsp_out), - .floo_req_o (router_17_0_req_out), - .floo_rsp_i (router_17_0_rsp_in) -); - - -floo_req_t [4:0] router_17_1_req_in; -floo_rsp_t [4:0] router_17_1_rsp_out; -floo_req_t [4:0] router_17_1_req_out; -floo_rsp_t [4:0] router_17_1_rsp_in; - - assign router_17_1_req_in[0] = router_17_2_to_router_17_1_req; - assign router_17_1_req_in[1] = router_18_1_to_router_17_1_req; - assign router_17_1_req_in[2] = router_17_0_to_router_17_1_req; - assign router_17_1_req_in[3] = router_16_1_to_router_17_1_req; - assign router_17_1_req_in[4] = magia_tile_ni_17_1_to_router_17_1_req; - - assign router_17_1_to_router_17_2_rsp = router_17_1_rsp_out[0]; - assign router_17_1_to_router_18_1_rsp = router_17_1_rsp_out[1]; - assign router_17_1_to_router_17_0_rsp = router_17_1_rsp_out[2]; - assign router_17_1_to_router_16_1_rsp = router_17_1_rsp_out[3]; - assign router_17_1_to_magia_tile_ni_17_1_rsp = router_17_1_rsp_out[4]; - - assign router_17_1_to_router_17_2_req = router_17_1_req_out[0]; - assign router_17_1_to_router_18_1_req = router_17_1_req_out[1]; - assign router_17_1_to_router_17_0_req = router_17_1_req_out[2]; - assign router_17_1_to_router_16_1_req = router_17_1_req_out[3]; - assign router_17_1_to_magia_tile_ni_17_1_req = router_17_1_req_out[4]; - - assign router_17_1_rsp_in[0] = router_17_2_to_router_17_1_rsp; - assign router_17_1_rsp_in[1] = router_18_1_to_router_17_1_rsp; - assign router_17_1_rsp_in[2] = router_17_0_to_router_17_1_rsp; - assign router_17_1_rsp_in[3] = router_16_1_to_router_17_1_rsp; - assign router_17_1_rsp_in[4] = magia_tile_ni_17_1_to_router_17_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_1_req_in), - .floo_rsp_o (router_17_1_rsp_out), - .floo_req_o (router_17_1_req_out), - .floo_rsp_i (router_17_1_rsp_in) -); - - -floo_req_t [4:0] router_17_2_req_in; -floo_rsp_t [4:0] router_17_2_rsp_out; -floo_req_t [4:0] router_17_2_req_out; -floo_rsp_t [4:0] router_17_2_rsp_in; - - assign router_17_2_req_in[0] = router_17_3_to_router_17_2_req; - assign router_17_2_req_in[1] = router_18_2_to_router_17_2_req; - assign router_17_2_req_in[2] = router_17_1_to_router_17_2_req; - assign router_17_2_req_in[3] = router_16_2_to_router_17_2_req; - assign router_17_2_req_in[4] = magia_tile_ni_17_2_to_router_17_2_req; - - assign router_17_2_to_router_17_3_rsp = router_17_2_rsp_out[0]; - assign router_17_2_to_router_18_2_rsp = router_17_2_rsp_out[1]; - assign router_17_2_to_router_17_1_rsp = router_17_2_rsp_out[2]; - assign router_17_2_to_router_16_2_rsp = router_17_2_rsp_out[3]; - assign router_17_2_to_magia_tile_ni_17_2_rsp = router_17_2_rsp_out[4]; - - assign router_17_2_to_router_17_3_req = router_17_2_req_out[0]; - assign router_17_2_to_router_18_2_req = router_17_2_req_out[1]; - assign router_17_2_to_router_17_1_req = router_17_2_req_out[2]; - assign router_17_2_to_router_16_2_req = router_17_2_req_out[3]; - assign router_17_2_to_magia_tile_ni_17_2_req = router_17_2_req_out[4]; - - assign router_17_2_rsp_in[0] = router_17_3_to_router_17_2_rsp; - assign router_17_2_rsp_in[1] = router_18_2_to_router_17_2_rsp; - assign router_17_2_rsp_in[2] = router_17_1_to_router_17_2_rsp; - assign router_17_2_rsp_in[3] = router_16_2_to_router_17_2_rsp; - assign router_17_2_rsp_in[4] = magia_tile_ni_17_2_to_router_17_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_2_req_in), - .floo_rsp_o (router_17_2_rsp_out), - .floo_req_o (router_17_2_req_out), - .floo_rsp_i (router_17_2_rsp_in) -); - - -floo_req_t [4:0] router_17_3_req_in; -floo_rsp_t [4:0] router_17_3_rsp_out; -floo_req_t [4:0] router_17_3_req_out; -floo_rsp_t [4:0] router_17_3_rsp_in; - - assign router_17_3_req_in[0] = router_17_4_to_router_17_3_req; - assign router_17_3_req_in[1] = router_18_3_to_router_17_3_req; - assign router_17_3_req_in[2] = router_17_2_to_router_17_3_req; - assign router_17_3_req_in[3] = router_16_3_to_router_17_3_req; - assign router_17_3_req_in[4] = magia_tile_ni_17_3_to_router_17_3_req; - - assign router_17_3_to_router_17_4_rsp = router_17_3_rsp_out[0]; - assign router_17_3_to_router_18_3_rsp = router_17_3_rsp_out[1]; - assign router_17_3_to_router_17_2_rsp = router_17_3_rsp_out[2]; - assign router_17_3_to_router_16_3_rsp = router_17_3_rsp_out[3]; - assign router_17_3_to_magia_tile_ni_17_3_rsp = router_17_3_rsp_out[4]; - - assign router_17_3_to_router_17_4_req = router_17_3_req_out[0]; - assign router_17_3_to_router_18_3_req = router_17_3_req_out[1]; - assign router_17_3_to_router_17_2_req = router_17_3_req_out[2]; - assign router_17_3_to_router_16_3_req = router_17_3_req_out[3]; - assign router_17_3_to_magia_tile_ni_17_3_req = router_17_3_req_out[4]; - - assign router_17_3_rsp_in[0] = router_17_4_to_router_17_3_rsp; - assign router_17_3_rsp_in[1] = router_18_3_to_router_17_3_rsp; - assign router_17_3_rsp_in[2] = router_17_2_to_router_17_3_rsp; - assign router_17_3_rsp_in[3] = router_16_3_to_router_17_3_rsp; - assign router_17_3_rsp_in[4] = magia_tile_ni_17_3_to_router_17_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_3_req_in), - .floo_rsp_o (router_17_3_rsp_out), - .floo_req_o (router_17_3_req_out), - .floo_rsp_i (router_17_3_rsp_in) -); - - -floo_req_t [4:0] router_17_4_req_in; -floo_rsp_t [4:0] router_17_4_rsp_out; -floo_req_t [4:0] router_17_4_req_out; -floo_rsp_t [4:0] router_17_4_rsp_in; - - assign router_17_4_req_in[0] = router_17_5_to_router_17_4_req; - assign router_17_4_req_in[1] = router_18_4_to_router_17_4_req; - assign router_17_4_req_in[2] = router_17_3_to_router_17_4_req; - assign router_17_4_req_in[3] = router_16_4_to_router_17_4_req; - assign router_17_4_req_in[4] = magia_tile_ni_17_4_to_router_17_4_req; - - assign router_17_4_to_router_17_5_rsp = router_17_4_rsp_out[0]; - assign router_17_4_to_router_18_4_rsp = router_17_4_rsp_out[1]; - assign router_17_4_to_router_17_3_rsp = router_17_4_rsp_out[2]; - assign router_17_4_to_router_16_4_rsp = router_17_4_rsp_out[3]; - assign router_17_4_to_magia_tile_ni_17_4_rsp = router_17_4_rsp_out[4]; - - assign router_17_4_to_router_17_5_req = router_17_4_req_out[0]; - assign router_17_4_to_router_18_4_req = router_17_4_req_out[1]; - assign router_17_4_to_router_17_3_req = router_17_4_req_out[2]; - assign router_17_4_to_router_16_4_req = router_17_4_req_out[3]; - assign router_17_4_to_magia_tile_ni_17_4_req = router_17_4_req_out[4]; - - assign router_17_4_rsp_in[0] = router_17_5_to_router_17_4_rsp; - assign router_17_4_rsp_in[1] = router_18_4_to_router_17_4_rsp; - assign router_17_4_rsp_in[2] = router_17_3_to_router_17_4_rsp; - assign router_17_4_rsp_in[3] = router_16_4_to_router_17_4_rsp; - assign router_17_4_rsp_in[4] = magia_tile_ni_17_4_to_router_17_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_4_req_in), - .floo_rsp_o (router_17_4_rsp_out), - .floo_req_o (router_17_4_req_out), - .floo_rsp_i (router_17_4_rsp_in) -); - - -floo_req_t [4:0] router_17_5_req_in; -floo_rsp_t [4:0] router_17_5_rsp_out; -floo_req_t [4:0] router_17_5_req_out; -floo_rsp_t [4:0] router_17_5_rsp_in; - - assign router_17_5_req_in[0] = router_17_6_to_router_17_5_req; - assign router_17_5_req_in[1] = router_18_5_to_router_17_5_req; - assign router_17_5_req_in[2] = router_17_4_to_router_17_5_req; - assign router_17_5_req_in[3] = router_16_5_to_router_17_5_req; - assign router_17_5_req_in[4] = magia_tile_ni_17_5_to_router_17_5_req; - - assign router_17_5_to_router_17_6_rsp = router_17_5_rsp_out[0]; - assign router_17_5_to_router_18_5_rsp = router_17_5_rsp_out[1]; - assign router_17_5_to_router_17_4_rsp = router_17_5_rsp_out[2]; - assign router_17_5_to_router_16_5_rsp = router_17_5_rsp_out[3]; - assign router_17_5_to_magia_tile_ni_17_5_rsp = router_17_5_rsp_out[4]; - - assign router_17_5_to_router_17_6_req = router_17_5_req_out[0]; - assign router_17_5_to_router_18_5_req = router_17_5_req_out[1]; - assign router_17_5_to_router_17_4_req = router_17_5_req_out[2]; - assign router_17_5_to_router_16_5_req = router_17_5_req_out[3]; - assign router_17_5_to_magia_tile_ni_17_5_req = router_17_5_req_out[4]; - - assign router_17_5_rsp_in[0] = router_17_6_to_router_17_5_rsp; - assign router_17_5_rsp_in[1] = router_18_5_to_router_17_5_rsp; - assign router_17_5_rsp_in[2] = router_17_4_to_router_17_5_rsp; - assign router_17_5_rsp_in[3] = router_16_5_to_router_17_5_rsp; - assign router_17_5_rsp_in[4] = magia_tile_ni_17_5_to_router_17_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_5_req_in), - .floo_rsp_o (router_17_5_rsp_out), - .floo_req_o (router_17_5_req_out), - .floo_rsp_i (router_17_5_rsp_in) -); - - -floo_req_t [4:0] router_17_6_req_in; -floo_rsp_t [4:0] router_17_6_rsp_out; -floo_req_t [4:0] router_17_6_req_out; -floo_rsp_t [4:0] router_17_6_rsp_in; - - assign router_17_6_req_in[0] = router_17_7_to_router_17_6_req; - assign router_17_6_req_in[1] = router_18_6_to_router_17_6_req; - assign router_17_6_req_in[2] = router_17_5_to_router_17_6_req; - assign router_17_6_req_in[3] = router_16_6_to_router_17_6_req; - assign router_17_6_req_in[4] = magia_tile_ni_17_6_to_router_17_6_req; - - assign router_17_6_to_router_17_7_rsp = router_17_6_rsp_out[0]; - assign router_17_6_to_router_18_6_rsp = router_17_6_rsp_out[1]; - assign router_17_6_to_router_17_5_rsp = router_17_6_rsp_out[2]; - assign router_17_6_to_router_16_6_rsp = router_17_6_rsp_out[3]; - assign router_17_6_to_magia_tile_ni_17_6_rsp = router_17_6_rsp_out[4]; - - assign router_17_6_to_router_17_7_req = router_17_6_req_out[0]; - assign router_17_6_to_router_18_6_req = router_17_6_req_out[1]; - assign router_17_6_to_router_17_5_req = router_17_6_req_out[2]; - assign router_17_6_to_router_16_6_req = router_17_6_req_out[3]; - assign router_17_6_to_magia_tile_ni_17_6_req = router_17_6_req_out[4]; - - assign router_17_6_rsp_in[0] = router_17_7_to_router_17_6_rsp; - assign router_17_6_rsp_in[1] = router_18_6_to_router_17_6_rsp; - assign router_17_6_rsp_in[2] = router_17_5_to_router_17_6_rsp; - assign router_17_6_rsp_in[3] = router_16_6_to_router_17_6_rsp; - assign router_17_6_rsp_in[4] = magia_tile_ni_17_6_to_router_17_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_6_req_in), - .floo_rsp_o (router_17_6_rsp_out), - .floo_req_o (router_17_6_req_out), - .floo_rsp_i (router_17_6_rsp_in) -); - - -floo_req_t [4:0] router_17_7_req_in; -floo_rsp_t [4:0] router_17_7_rsp_out; -floo_req_t [4:0] router_17_7_req_out; -floo_rsp_t [4:0] router_17_7_rsp_in; - - assign router_17_7_req_in[0] = router_17_8_to_router_17_7_req; - assign router_17_7_req_in[1] = router_18_7_to_router_17_7_req; - assign router_17_7_req_in[2] = router_17_6_to_router_17_7_req; - assign router_17_7_req_in[3] = router_16_7_to_router_17_7_req; - assign router_17_7_req_in[4] = magia_tile_ni_17_7_to_router_17_7_req; - - assign router_17_7_to_router_17_8_rsp = router_17_7_rsp_out[0]; - assign router_17_7_to_router_18_7_rsp = router_17_7_rsp_out[1]; - assign router_17_7_to_router_17_6_rsp = router_17_7_rsp_out[2]; - assign router_17_7_to_router_16_7_rsp = router_17_7_rsp_out[3]; - assign router_17_7_to_magia_tile_ni_17_7_rsp = router_17_7_rsp_out[4]; - - assign router_17_7_to_router_17_8_req = router_17_7_req_out[0]; - assign router_17_7_to_router_18_7_req = router_17_7_req_out[1]; - assign router_17_7_to_router_17_6_req = router_17_7_req_out[2]; - assign router_17_7_to_router_16_7_req = router_17_7_req_out[3]; - assign router_17_7_to_magia_tile_ni_17_7_req = router_17_7_req_out[4]; - - assign router_17_7_rsp_in[0] = router_17_8_to_router_17_7_rsp; - assign router_17_7_rsp_in[1] = router_18_7_to_router_17_7_rsp; - assign router_17_7_rsp_in[2] = router_17_6_to_router_17_7_rsp; - assign router_17_7_rsp_in[3] = router_16_7_to_router_17_7_rsp; - assign router_17_7_rsp_in[4] = magia_tile_ni_17_7_to_router_17_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_7_req_in), - .floo_rsp_o (router_17_7_rsp_out), - .floo_req_o (router_17_7_req_out), - .floo_rsp_i (router_17_7_rsp_in) -); - - -floo_req_t [4:0] router_17_8_req_in; -floo_rsp_t [4:0] router_17_8_rsp_out; -floo_req_t [4:0] router_17_8_req_out; -floo_rsp_t [4:0] router_17_8_rsp_in; - - assign router_17_8_req_in[0] = router_17_9_to_router_17_8_req; - assign router_17_8_req_in[1] = router_18_8_to_router_17_8_req; - assign router_17_8_req_in[2] = router_17_7_to_router_17_8_req; - assign router_17_8_req_in[3] = router_16_8_to_router_17_8_req; - assign router_17_8_req_in[4] = magia_tile_ni_17_8_to_router_17_8_req; - - assign router_17_8_to_router_17_9_rsp = router_17_8_rsp_out[0]; - assign router_17_8_to_router_18_8_rsp = router_17_8_rsp_out[1]; - assign router_17_8_to_router_17_7_rsp = router_17_8_rsp_out[2]; - assign router_17_8_to_router_16_8_rsp = router_17_8_rsp_out[3]; - assign router_17_8_to_magia_tile_ni_17_8_rsp = router_17_8_rsp_out[4]; - - assign router_17_8_to_router_17_9_req = router_17_8_req_out[0]; - assign router_17_8_to_router_18_8_req = router_17_8_req_out[1]; - assign router_17_8_to_router_17_7_req = router_17_8_req_out[2]; - assign router_17_8_to_router_16_8_req = router_17_8_req_out[3]; - assign router_17_8_to_magia_tile_ni_17_8_req = router_17_8_req_out[4]; - - assign router_17_8_rsp_in[0] = router_17_9_to_router_17_8_rsp; - assign router_17_8_rsp_in[1] = router_18_8_to_router_17_8_rsp; - assign router_17_8_rsp_in[2] = router_17_7_to_router_17_8_rsp; - assign router_17_8_rsp_in[3] = router_16_8_to_router_17_8_rsp; - assign router_17_8_rsp_in[4] = magia_tile_ni_17_8_to_router_17_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_8_req_in), - .floo_rsp_o (router_17_8_rsp_out), - .floo_req_o (router_17_8_req_out), - .floo_rsp_i (router_17_8_rsp_in) -); - - -floo_req_t [4:0] router_17_9_req_in; -floo_rsp_t [4:0] router_17_9_rsp_out; -floo_req_t [4:0] router_17_9_req_out; -floo_rsp_t [4:0] router_17_9_rsp_in; - - assign router_17_9_req_in[0] = router_17_10_to_router_17_9_req; - assign router_17_9_req_in[1] = router_18_9_to_router_17_9_req; - assign router_17_9_req_in[2] = router_17_8_to_router_17_9_req; - assign router_17_9_req_in[3] = router_16_9_to_router_17_9_req; - assign router_17_9_req_in[4] = magia_tile_ni_17_9_to_router_17_9_req; - - assign router_17_9_to_router_17_10_rsp = router_17_9_rsp_out[0]; - assign router_17_9_to_router_18_9_rsp = router_17_9_rsp_out[1]; - assign router_17_9_to_router_17_8_rsp = router_17_9_rsp_out[2]; - assign router_17_9_to_router_16_9_rsp = router_17_9_rsp_out[3]; - assign router_17_9_to_magia_tile_ni_17_9_rsp = router_17_9_rsp_out[4]; - - assign router_17_9_to_router_17_10_req = router_17_9_req_out[0]; - assign router_17_9_to_router_18_9_req = router_17_9_req_out[1]; - assign router_17_9_to_router_17_8_req = router_17_9_req_out[2]; - assign router_17_9_to_router_16_9_req = router_17_9_req_out[3]; - assign router_17_9_to_magia_tile_ni_17_9_req = router_17_9_req_out[4]; - - assign router_17_9_rsp_in[0] = router_17_10_to_router_17_9_rsp; - assign router_17_9_rsp_in[1] = router_18_9_to_router_17_9_rsp; - assign router_17_9_rsp_in[2] = router_17_8_to_router_17_9_rsp; - assign router_17_9_rsp_in[3] = router_16_9_to_router_17_9_rsp; - assign router_17_9_rsp_in[4] = magia_tile_ni_17_9_to_router_17_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_9_req_in), - .floo_rsp_o (router_17_9_rsp_out), - .floo_req_o (router_17_9_req_out), - .floo_rsp_i (router_17_9_rsp_in) -); - - -floo_req_t [4:0] router_17_10_req_in; -floo_rsp_t [4:0] router_17_10_rsp_out; -floo_req_t [4:0] router_17_10_req_out; -floo_rsp_t [4:0] router_17_10_rsp_in; - - assign router_17_10_req_in[0] = router_17_11_to_router_17_10_req; - assign router_17_10_req_in[1] = router_18_10_to_router_17_10_req; - assign router_17_10_req_in[2] = router_17_9_to_router_17_10_req; - assign router_17_10_req_in[3] = router_16_10_to_router_17_10_req; - assign router_17_10_req_in[4] = magia_tile_ni_17_10_to_router_17_10_req; - - assign router_17_10_to_router_17_11_rsp = router_17_10_rsp_out[0]; - assign router_17_10_to_router_18_10_rsp = router_17_10_rsp_out[1]; - assign router_17_10_to_router_17_9_rsp = router_17_10_rsp_out[2]; - assign router_17_10_to_router_16_10_rsp = router_17_10_rsp_out[3]; - assign router_17_10_to_magia_tile_ni_17_10_rsp = router_17_10_rsp_out[4]; - - assign router_17_10_to_router_17_11_req = router_17_10_req_out[0]; - assign router_17_10_to_router_18_10_req = router_17_10_req_out[1]; - assign router_17_10_to_router_17_9_req = router_17_10_req_out[2]; - assign router_17_10_to_router_16_10_req = router_17_10_req_out[3]; - assign router_17_10_to_magia_tile_ni_17_10_req = router_17_10_req_out[4]; - - assign router_17_10_rsp_in[0] = router_17_11_to_router_17_10_rsp; - assign router_17_10_rsp_in[1] = router_18_10_to_router_17_10_rsp; - assign router_17_10_rsp_in[2] = router_17_9_to_router_17_10_rsp; - assign router_17_10_rsp_in[3] = router_16_10_to_router_17_10_rsp; - assign router_17_10_rsp_in[4] = magia_tile_ni_17_10_to_router_17_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_10_req_in), - .floo_rsp_o (router_17_10_rsp_out), - .floo_req_o (router_17_10_req_out), - .floo_rsp_i (router_17_10_rsp_in) -); - - -floo_req_t [4:0] router_17_11_req_in; -floo_rsp_t [4:0] router_17_11_rsp_out; -floo_req_t [4:0] router_17_11_req_out; -floo_rsp_t [4:0] router_17_11_rsp_in; - - assign router_17_11_req_in[0] = router_17_12_to_router_17_11_req; - assign router_17_11_req_in[1] = router_18_11_to_router_17_11_req; - assign router_17_11_req_in[2] = router_17_10_to_router_17_11_req; - assign router_17_11_req_in[3] = router_16_11_to_router_17_11_req; - assign router_17_11_req_in[4] = magia_tile_ni_17_11_to_router_17_11_req; - - assign router_17_11_to_router_17_12_rsp = router_17_11_rsp_out[0]; - assign router_17_11_to_router_18_11_rsp = router_17_11_rsp_out[1]; - assign router_17_11_to_router_17_10_rsp = router_17_11_rsp_out[2]; - assign router_17_11_to_router_16_11_rsp = router_17_11_rsp_out[3]; - assign router_17_11_to_magia_tile_ni_17_11_rsp = router_17_11_rsp_out[4]; - - assign router_17_11_to_router_17_12_req = router_17_11_req_out[0]; - assign router_17_11_to_router_18_11_req = router_17_11_req_out[1]; - assign router_17_11_to_router_17_10_req = router_17_11_req_out[2]; - assign router_17_11_to_router_16_11_req = router_17_11_req_out[3]; - assign router_17_11_to_magia_tile_ni_17_11_req = router_17_11_req_out[4]; - - assign router_17_11_rsp_in[0] = router_17_12_to_router_17_11_rsp; - assign router_17_11_rsp_in[1] = router_18_11_to_router_17_11_rsp; - assign router_17_11_rsp_in[2] = router_17_10_to_router_17_11_rsp; - assign router_17_11_rsp_in[3] = router_16_11_to_router_17_11_rsp; - assign router_17_11_rsp_in[4] = magia_tile_ni_17_11_to_router_17_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_11_req_in), - .floo_rsp_o (router_17_11_rsp_out), - .floo_req_o (router_17_11_req_out), - .floo_rsp_i (router_17_11_rsp_in) -); - - -floo_req_t [4:0] router_17_12_req_in; -floo_rsp_t [4:0] router_17_12_rsp_out; -floo_req_t [4:0] router_17_12_req_out; -floo_rsp_t [4:0] router_17_12_rsp_in; - - assign router_17_12_req_in[0] = router_17_13_to_router_17_12_req; - assign router_17_12_req_in[1] = router_18_12_to_router_17_12_req; - assign router_17_12_req_in[2] = router_17_11_to_router_17_12_req; - assign router_17_12_req_in[3] = router_16_12_to_router_17_12_req; - assign router_17_12_req_in[4] = magia_tile_ni_17_12_to_router_17_12_req; - - assign router_17_12_to_router_17_13_rsp = router_17_12_rsp_out[0]; - assign router_17_12_to_router_18_12_rsp = router_17_12_rsp_out[1]; - assign router_17_12_to_router_17_11_rsp = router_17_12_rsp_out[2]; - assign router_17_12_to_router_16_12_rsp = router_17_12_rsp_out[3]; - assign router_17_12_to_magia_tile_ni_17_12_rsp = router_17_12_rsp_out[4]; - - assign router_17_12_to_router_17_13_req = router_17_12_req_out[0]; - assign router_17_12_to_router_18_12_req = router_17_12_req_out[1]; - assign router_17_12_to_router_17_11_req = router_17_12_req_out[2]; - assign router_17_12_to_router_16_12_req = router_17_12_req_out[3]; - assign router_17_12_to_magia_tile_ni_17_12_req = router_17_12_req_out[4]; - - assign router_17_12_rsp_in[0] = router_17_13_to_router_17_12_rsp; - assign router_17_12_rsp_in[1] = router_18_12_to_router_17_12_rsp; - assign router_17_12_rsp_in[2] = router_17_11_to_router_17_12_rsp; - assign router_17_12_rsp_in[3] = router_16_12_to_router_17_12_rsp; - assign router_17_12_rsp_in[4] = magia_tile_ni_17_12_to_router_17_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_12_req_in), - .floo_rsp_o (router_17_12_rsp_out), - .floo_req_o (router_17_12_req_out), - .floo_rsp_i (router_17_12_rsp_in) -); - - -floo_req_t [4:0] router_17_13_req_in; -floo_rsp_t [4:0] router_17_13_rsp_out; -floo_req_t [4:0] router_17_13_req_out; -floo_rsp_t [4:0] router_17_13_rsp_in; - - assign router_17_13_req_in[0] = router_17_14_to_router_17_13_req; - assign router_17_13_req_in[1] = router_18_13_to_router_17_13_req; - assign router_17_13_req_in[2] = router_17_12_to_router_17_13_req; - assign router_17_13_req_in[3] = router_16_13_to_router_17_13_req; - assign router_17_13_req_in[4] = magia_tile_ni_17_13_to_router_17_13_req; - - assign router_17_13_to_router_17_14_rsp = router_17_13_rsp_out[0]; - assign router_17_13_to_router_18_13_rsp = router_17_13_rsp_out[1]; - assign router_17_13_to_router_17_12_rsp = router_17_13_rsp_out[2]; - assign router_17_13_to_router_16_13_rsp = router_17_13_rsp_out[3]; - assign router_17_13_to_magia_tile_ni_17_13_rsp = router_17_13_rsp_out[4]; - - assign router_17_13_to_router_17_14_req = router_17_13_req_out[0]; - assign router_17_13_to_router_18_13_req = router_17_13_req_out[1]; - assign router_17_13_to_router_17_12_req = router_17_13_req_out[2]; - assign router_17_13_to_router_16_13_req = router_17_13_req_out[3]; - assign router_17_13_to_magia_tile_ni_17_13_req = router_17_13_req_out[4]; - - assign router_17_13_rsp_in[0] = router_17_14_to_router_17_13_rsp; - assign router_17_13_rsp_in[1] = router_18_13_to_router_17_13_rsp; - assign router_17_13_rsp_in[2] = router_17_12_to_router_17_13_rsp; - assign router_17_13_rsp_in[3] = router_16_13_to_router_17_13_rsp; - assign router_17_13_rsp_in[4] = magia_tile_ni_17_13_to_router_17_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_13_req_in), - .floo_rsp_o (router_17_13_rsp_out), - .floo_req_o (router_17_13_req_out), - .floo_rsp_i (router_17_13_rsp_in) -); - - -floo_req_t [4:0] router_17_14_req_in; -floo_rsp_t [4:0] router_17_14_rsp_out; -floo_req_t [4:0] router_17_14_req_out; -floo_rsp_t [4:0] router_17_14_rsp_in; - - assign router_17_14_req_in[0] = router_17_15_to_router_17_14_req; - assign router_17_14_req_in[1] = router_18_14_to_router_17_14_req; - assign router_17_14_req_in[2] = router_17_13_to_router_17_14_req; - assign router_17_14_req_in[3] = router_16_14_to_router_17_14_req; - assign router_17_14_req_in[4] = magia_tile_ni_17_14_to_router_17_14_req; - - assign router_17_14_to_router_17_15_rsp = router_17_14_rsp_out[0]; - assign router_17_14_to_router_18_14_rsp = router_17_14_rsp_out[1]; - assign router_17_14_to_router_17_13_rsp = router_17_14_rsp_out[2]; - assign router_17_14_to_router_16_14_rsp = router_17_14_rsp_out[3]; - assign router_17_14_to_magia_tile_ni_17_14_rsp = router_17_14_rsp_out[4]; - - assign router_17_14_to_router_17_15_req = router_17_14_req_out[0]; - assign router_17_14_to_router_18_14_req = router_17_14_req_out[1]; - assign router_17_14_to_router_17_13_req = router_17_14_req_out[2]; - assign router_17_14_to_router_16_14_req = router_17_14_req_out[3]; - assign router_17_14_to_magia_tile_ni_17_14_req = router_17_14_req_out[4]; - - assign router_17_14_rsp_in[0] = router_17_15_to_router_17_14_rsp; - assign router_17_14_rsp_in[1] = router_18_14_to_router_17_14_rsp; - assign router_17_14_rsp_in[2] = router_17_13_to_router_17_14_rsp; - assign router_17_14_rsp_in[3] = router_16_14_to_router_17_14_rsp; - assign router_17_14_rsp_in[4] = magia_tile_ni_17_14_to_router_17_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_14_req_in), - .floo_rsp_o (router_17_14_rsp_out), - .floo_req_o (router_17_14_req_out), - .floo_rsp_i (router_17_14_rsp_in) -); - - -floo_req_t [4:0] router_17_15_req_in; -floo_rsp_t [4:0] router_17_15_rsp_out; -floo_req_t [4:0] router_17_15_req_out; -floo_rsp_t [4:0] router_17_15_rsp_in; - - assign router_17_15_req_in[0] = router_17_16_to_router_17_15_req; - assign router_17_15_req_in[1] = router_18_15_to_router_17_15_req; - assign router_17_15_req_in[2] = router_17_14_to_router_17_15_req; - assign router_17_15_req_in[3] = router_16_15_to_router_17_15_req; - assign router_17_15_req_in[4] = magia_tile_ni_17_15_to_router_17_15_req; - - assign router_17_15_to_router_17_16_rsp = router_17_15_rsp_out[0]; - assign router_17_15_to_router_18_15_rsp = router_17_15_rsp_out[1]; - assign router_17_15_to_router_17_14_rsp = router_17_15_rsp_out[2]; - assign router_17_15_to_router_16_15_rsp = router_17_15_rsp_out[3]; - assign router_17_15_to_magia_tile_ni_17_15_rsp = router_17_15_rsp_out[4]; - - assign router_17_15_to_router_17_16_req = router_17_15_req_out[0]; - assign router_17_15_to_router_18_15_req = router_17_15_req_out[1]; - assign router_17_15_to_router_17_14_req = router_17_15_req_out[2]; - assign router_17_15_to_router_16_15_req = router_17_15_req_out[3]; - assign router_17_15_to_magia_tile_ni_17_15_req = router_17_15_req_out[4]; - - assign router_17_15_rsp_in[0] = router_17_16_to_router_17_15_rsp; - assign router_17_15_rsp_in[1] = router_18_15_to_router_17_15_rsp; - assign router_17_15_rsp_in[2] = router_17_14_to_router_17_15_rsp; - assign router_17_15_rsp_in[3] = router_16_15_to_router_17_15_rsp; - assign router_17_15_rsp_in[4] = magia_tile_ni_17_15_to_router_17_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_15_req_in), - .floo_rsp_o (router_17_15_rsp_out), - .floo_req_o (router_17_15_req_out), - .floo_rsp_i (router_17_15_rsp_in) -); - - -floo_req_t [4:0] router_17_16_req_in; -floo_rsp_t [4:0] router_17_16_rsp_out; -floo_req_t [4:0] router_17_16_req_out; -floo_rsp_t [4:0] router_17_16_rsp_in; - - assign router_17_16_req_in[0] = router_17_17_to_router_17_16_req; - assign router_17_16_req_in[1] = router_18_16_to_router_17_16_req; - assign router_17_16_req_in[2] = router_17_15_to_router_17_16_req; - assign router_17_16_req_in[3] = router_16_16_to_router_17_16_req; - assign router_17_16_req_in[4] = magia_tile_ni_17_16_to_router_17_16_req; - - assign router_17_16_to_router_17_17_rsp = router_17_16_rsp_out[0]; - assign router_17_16_to_router_18_16_rsp = router_17_16_rsp_out[1]; - assign router_17_16_to_router_17_15_rsp = router_17_16_rsp_out[2]; - assign router_17_16_to_router_16_16_rsp = router_17_16_rsp_out[3]; - assign router_17_16_to_magia_tile_ni_17_16_rsp = router_17_16_rsp_out[4]; - - assign router_17_16_to_router_17_17_req = router_17_16_req_out[0]; - assign router_17_16_to_router_18_16_req = router_17_16_req_out[1]; - assign router_17_16_to_router_17_15_req = router_17_16_req_out[2]; - assign router_17_16_to_router_16_16_req = router_17_16_req_out[3]; - assign router_17_16_to_magia_tile_ni_17_16_req = router_17_16_req_out[4]; - - assign router_17_16_rsp_in[0] = router_17_17_to_router_17_16_rsp; - assign router_17_16_rsp_in[1] = router_18_16_to_router_17_16_rsp; - assign router_17_16_rsp_in[2] = router_17_15_to_router_17_16_rsp; - assign router_17_16_rsp_in[3] = router_16_16_to_router_17_16_rsp; - assign router_17_16_rsp_in[4] = magia_tile_ni_17_16_to_router_17_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_16_req_in), - .floo_rsp_o (router_17_16_rsp_out), - .floo_req_o (router_17_16_req_out), - .floo_rsp_i (router_17_16_rsp_in) -); - - -floo_req_t [4:0] router_17_17_req_in; -floo_rsp_t [4:0] router_17_17_rsp_out; -floo_req_t [4:0] router_17_17_req_out; -floo_rsp_t [4:0] router_17_17_rsp_in; - - assign router_17_17_req_in[0] = router_17_18_to_router_17_17_req; - assign router_17_17_req_in[1] = router_18_17_to_router_17_17_req; - assign router_17_17_req_in[2] = router_17_16_to_router_17_17_req; - assign router_17_17_req_in[3] = router_16_17_to_router_17_17_req; - assign router_17_17_req_in[4] = magia_tile_ni_17_17_to_router_17_17_req; - - assign router_17_17_to_router_17_18_rsp = router_17_17_rsp_out[0]; - assign router_17_17_to_router_18_17_rsp = router_17_17_rsp_out[1]; - assign router_17_17_to_router_17_16_rsp = router_17_17_rsp_out[2]; - assign router_17_17_to_router_16_17_rsp = router_17_17_rsp_out[3]; - assign router_17_17_to_magia_tile_ni_17_17_rsp = router_17_17_rsp_out[4]; - - assign router_17_17_to_router_17_18_req = router_17_17_req_out[0]; - assign router_17_17_to_router_18_17_req = router_17_17_req_out[1]; - assign router_17_17_to_router_17_16_req = router_17_17_req_out[2]; - assign router_17_17_to_router_16_17_req = router_17_17_req_out[3]; - assign router_17_17_to_magia_tile_ni_17_17_req = router_17_17_req_out[4]; - - assign router_17_17_rsp_in[0] = router_17_18_to_router_17_17_rsp; - assign router_17_17_rsp_in[1] = router_18_17_to_router_17_17_rsp; - assign router_17_17_rsp_in[2] = router_17_16_to_router_17_17_rsp; - assign router_17_17_rsp_in[3] = router_16_17_to_router_17_17_rsp; - assign router_17_17_rsp_in[4] = magia_tile_ni_17_17_to_router_17_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_17_req_in), - .floo_rsp_o (router_17_17_rsp_out), - .floo_req_o (router_17_17_req_out), - .floo_rsp_i (router_17_17_rsp_in) -); - - -floo_req_t [4:0] router_17_18_req_in; -floo_rsp_t [4:0] router_17_18_rsp_out; -floo_req_t [4:0] router_17_18_req_out; -floo_rsp_t [4:0] router_17_18_rsp_in; - - assign router_17_18_req_in[0] = router_17_19_to_router_17_18_req; - assign router_17_18_req_in[1] = router_18_18_to_router_17_18_req; - assign router_17_18_req_in[2] = router_17_17_to_router_17_18_req; - assign router_17_18_req_in[3] = router_16_18_to_router_17_18_req; - assign router_17_18_req_in[4] = magia_tile_ni_17_18_to_router_17_18_req; - - assign router_17_18_to_router_17_19_rsp = router_17_18_rsp_out[0]; - assign router_17_18_to_router_18_18_rsp = router_17_18_rsp_out[1]; - assign router_17_18_to_router_17_17_rsp = router_17_18_rsp_out[2]; - assign router_17_18_to_router_16_18_rsp = router_17_18_rsp_out[3]; - assign router_17_18_to_magia_tile_ni_17_18_rsp = router_17_18_rsp_out[4]; - - assign router_17_18_to_router_17_19_req = router_17_18_req_out[0]; - assign router_17_18_to_router_18_18_req = router_17_18_req_out[1]; - assign router_17_18_to_router_17_17_req = router_17_18_req_out[2]; - assign router_17_18_to_router_16_18_req = router_17_18_req_out[3]; - assign router_17_18_to_magia_tile_ni_17_18_req = router_17_18_req_out[4]; - - assign router_17_18_rsp_in[0] = router_17_19_to_router_17_18_rsp; - assign router_17_18_rsp_in[1] = router_18_18_to_router_17_18_rsp; - assign router_17_18_rsp_in[2] = router_17_17_to_router_17_18_rsp; - assign router_17_18_rsp_in[3] = router_16_18_to_router_17_18_rsp; - assign router_17_18_rsp_in[4] = magia_tile_ni_17_18_to_router_17_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_18_req_in), - .floo_rsp_o (router_17_18_rsp_out), - .floo_req_o (router_17_18_req_out), - .floo_rsp_i (router_17_18_rsp_in) -); - - -floo_req_t [4:0] router_17_19_req_in; -floo_rsp_t [4:0] router_17_19_rsp_out; -floo_req_t [4:0] router_17_19_req_out; -floo_rsp_t [4:0] router_17_19_rsp_in; - - assign router_17_19_req_in[0] = router_17_20_to_router_17_19_req; - assign router_17_19_req_in[1] = router_18_19_to_router_17_19_req; - assign router_17_19_req_in[2] = router_17_18_to_router_17_19_req; - assign router_17_19_req_in[3] = router_16_19_to_router_17_19_req; - assign router_17_19_req_in[4] = magia_tile_ni_17_19_to_router_17_19_req; - - assign router_17_19_to_router_17_20_rsp = router_17_19_rsp_out[0]; - assign router_17_19_to_router_18_19_rsp = router_17_19_rsp_out[1]; - assign router_17_19_to_router_17_18_rsp = router_17_19_rsp_out[2]; - assign router_17_19_to_router_16_19_rsp = router_17_19_rsp_out[3]; - assign router_17_19_to_magia_tile_ni_17_19_rsp = router_17_19_rsp_out[4]; - - assign router_17_19_to_router_17_20_req = router_17_19_req_out[0]; - assign router_17_19_to_router_18_19_req = router_17_19_req_out[1]; - assign router_17_19_to_router_17_18_req = router_17_19_req_out[2]; - assign router_17_19_to_router_16_19_req = router_17_19_req_out[3]; - assign router_17_19_to_magia_tile_ni_17_19_req = router_17_19_req_out[4]; - - assign router_17_19_rsp_in[0] = router_17_20_to_router_17_19_rsp; - assign router_17_19_rsp_in[1] = router_18_19_to_router_17_19_rsp; - assign router_17_19_rsp_in[2] = router_17_18_to_router_17_19_rsp; - assign router_17_19_rsp_in[3] = router_16_19_to_router_17_19_rsp; - assign router_17_19_rsp_in[4] = magia_tile_ni_17_19_to_router_17_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_19_req_in), - .floo_rsp_o (router_17_19_rsp_out), - .floo_req_o (router_17_19_req_out), - .floo_rsp_i (router_17_19_rsp_in) -); - - -floo_req_t [4:0] router_17_20_req_in; -floo_rsp_t [4:0] router_17_20_rsp_out; -floo_req_t [4:0] router_17_20_req_out; -floo_rsp_t [4:0] router_17_20_rsp_in; - - assign router_17_20_req_in[0] = router_17_21_to_router_17_20_req; - assign router_17_20_req_in[1] = router_18_20_to_router_17_20_req; - assign router_17_20_req_in[2] = router_17_19_to_router_17_20_req; - assign router_17_20_req_in[3] = router_16_20_to_router_17_20_req; - assign router_17_20_req_in[4] = magia_tile_ni_17_20_to_router_17_20_req; - - assign router_17_20_to_router_17_21_rsp = router_17_20_rsp_out[0]; - assign router_17_20_to_router_18_20_rsp = router_17_20_rsp_out[1]; - assign router_17_20_to_router_17_19_rsp = router_17_20_rsp_out[2]; - assign router_17_20_to_router_16_20_rsp = router_17_20_rsp_out[3]; - assign router_17_20_to_magia_tile_ni_17_20_rsp = router_17_20_rsp_out[4]; - - assign router_17_20_to_router_17_21_req = router_17_20_req_out[0]; - assign router_17_20_to_router_18_20_req = router_17_20_req_out[1]; - assign router_17_20_to_router_17_19_req = router_17_20_req_out[2]; - assign router_17_20_to_router_16_20_req = router_17_20_req_out[3]; - assign router_17_20_to_magia_tile_ni_17_20_req = router_17_20_req_out[4]; - - assign router_17_20_rsp_in[0] = router_17_21_to_router_17_20_rsp; - assign router_17_20_rsp_in[1] = router_18_20_to_router_17_20_rsp; - assign router_17_20_rsp_in[2] = router_17_19_to_router_17_20_rsp; - assign router_17_20_rsp_in[3] = router_16_20_to_router_17_20_rsp; - assign router_17_20_rsp_in[4] = magia_tile_ni_17_20_to_router_17_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_20_req_in), - .floo_rsp_o (router_17_20_rsp_out), - .floo_req_o (router_17_20_req_out), - .floo_rsp_i (router_17_20_rsp_in) -); - - -floo_req_t [4:0] router_17_21_req_in; -floo_rsp_t [4:0] router_17_21_rsp_out; -floo_req_t [4:0] router_17_21_req_out; -floo_rsp_t [4:0] router_17_21_rsp_in; - - assign router_17_21_req_in[0] = router_17_22_to_router_17_21_req; - assign router_17_21_req_in[1] = router_18_21_to_router_17_21_req; - assign router_17_21_req_in[2] = router_17_20_to_router_17_21_req; - assign router_17_21_req_in[3] = router_16_21_to_router_17_21_req; - assign router_17_21_req_in[4] = magia_tile_ni_17_21_to_router_17_21_req; - - assign router_17_21_to_router_17_22_rsp = router_17_21_rsp_out[0]; - assign router_17_21_to_router_18_21_rsp = router_17_21_rsp_out[1]; - assign router_17_21_to_router_17_20_rsp = router_17_21_rsp_out[2]; - assign router_17_21_to_router_16_21_rsp = router_17_21_rsp_out[3]; - assign router_17_21_to_magia_tile_ni_17_21_rsp = router_17_21_rsp_out[4]; - - assign router_17_21_to_router_17_22_req = router_17_21_req_out[0]; - assign router_17_21_to_router_18_21_req = router_17_21_req_out[1]; - assign router_17_21_to_router_17_20_req = router_17_21_req_out[2]; - assign router_17_21_to_router_16_21_req = router_17_21_req_out[3]; - assign router_17_21_to_magia_tile_ni_17_21_req = router_17_21_req_out[4]; - - assign router_17_21_rsp_in[0] = router_17_22_to_router_17_21_rsp; - assign router_17_21_rsp_in[1] = router_18_21_to_router_17_21_rsp; - assign router_17_21_rsp_in[2] = router_17_20_to_router_17_21_rsp; - assign router_17_21_rsp_in[3] = router_16_21_to_router_17_21_rsp; - assign router_17_21_rsp_in[4] = magia_tile_ni_17_21_to_router_17_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_21_req_in), - .floo_rsp_o (router_17_21_rsp_out), - .floo_req_o (router_17_21_req_out), - .floo_rsp_i (router_17_21_rsp_in) -); - - -floo_req_t [4:0] router_17_22_req_in; -floo_rsp_t [4:0] router_17_22_rsp_out; -floo_req_t [4:0] router_17_22_req_out; -floo_rsp_t [4:0] router_17_22_rsp_in; - - assign router_17_22_req_in[0] = router_17_23_to_router_17_22_req; - assign router_17_22_req_in[1] = router_18_22_to_router_17_22_req; - assign router_17_22_req_in[2] = router_17_21_to_router_17_22_req; - assign router_17_22_req_in[3] = router_16_22_to_router_17_22_req; - assign router_17_22_req_in[4] = magia_tile_ni_17_22_to_router_17_22_req; - - assign router_17_22_to_router_17_23_rsp = router_17_22_rsp_out[0]; - assign router_17_22_to_router_18_22_rsp = router_17_22_rsp_out[1]; - assign router_17_22_to_router_17_21_rsp = router_17_22_rsp_out[2]; - assign router_17_22_to_router_16_22_rsp = router_17_22_rsp_out[3]; - assign router_17_22_to_magia_tile_ni_17_22_rsp = router_17_22_rsp_out[4]; - - assign router_17_22_to_router_17_23_req = router_17_22_req_out[0]; - assign router_17_22_to_router_18_22_req = router_17_22_req_out[1]; - assign router_17_22_to_router_17_21_req = router_17_22_req_out[2]; - assign router_17_22_to_router_16_22_req = router_17_22_req_out[3]; - assign router_17_22_to_magia_tile_ni_17_22_req = router_17_22_req_out[4]; - - assign router_17_22_rsp_in[0] = router_17_23_to_router_17_22_rsp; - assign router_17_22_rsp_in[1] = router_18_22_to_router_17_22_rsp; - assign router_17_22_rsp_in[2] = router_17_21_to_router_17_22_rsp; - assign router_17_22_rsp_in[3] = router_16_22_to_router_17_22_rsp; - assign router_17_22_rsp_in[4] = magia_tile_ni_17_22_to_router_17_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_22_req_in), - .floo_rsp_o (router_17_22_rsp_out), - .floo_req_o (router_17_22_req_out), - .floo_rsp_i (router_17_22_rsp_in) -); - - -floo_req_t [4:0] router_17_23_req_in; -floo_rsp_t [4:0] router_17_23_rsp_out; -floo_req_t [4:0] router_17_23_req_out; -floo_rsp_t [4:0] router_17_23_rsp_in; - - assign router_17_23_req_in[0] = router_17_24_to_router_17_23_req; - assign router_17_23_req_in[1] = router_18_23_to_router_17_23_req; - assign router_17_23_req_in[2] = router_17_22_to_router_17_23_req; - assign router_17_23_req_in[3] = router_16_23_to_router_17_23_req; - assign router_17_23_req_in[4] = magia_tile_ni_17_23_to_router_17_23_req; - - assign router_17_23_to_router_17_24_rsp = router_17_23_rsp_out[0]; - assign router_17_23_to_router_18_23_rsp = router_17_23_rsp_out[1]; - assign router_17_23_to_router_17_22_rsp = router_17_23_rsp_out[2]; - assign router_17_23_to_router_16_23_rsp = router_17_23_rsp_out[3]; - assign router_17_23_to_magia_tile_ni_17_23_rsp = router_17_23_rsp_out[4]; - - assign router_17_23_to_router_17_24_req = router_17_23_req_out[0]; - assign router_17_23_to_router_18_23_req = router_17_23_req_out[1]; - assign router_17_23_to_router_17_22_req = router_17_23_req_out[2]; - assign router_17_23_to_router_16_23_req = router_17_23_req_out[3]; - assign router_17_23_to_magia_tile_ni_17_23_req = router_17_23_req_out[4]; - - assign router_17_23_rsp_in[0] = router_17_24_to_router_17_23_rsp; - assign router_17_23_rsp_in[1] = router_18_23_to_router_17_23_rsp; - assign router_17_23_rsp_in[2] = router_17_22_to_router_17_23_rsp; - assign router_17_23_rsp_in[3] = router_16_23_to_router_17_23_rsp; - assign router_17_23_rsp_in[4] = magia_tile_ni_17_23_to_router_17_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_23_req_in), - .floo_rsp_o (router_17_23_rsp_out), - .floo_req_o (router_17_23_req_out), - .floo_rsp_i (router_17_23_rsp_in) -); - - -floo_req_t [4:0] router_17_24_req_in; -floo_rsp_t [4:0] router_17_24_rsp_out; -floo_req_t [4:0] router_17_24_req_out; -floo_rsp_t [4:0] router_17_24_rsp_in; - - assign router_17_24_req_in[0] = router_17_25_to_router_17_24_req; - assign router_17_24_req_in[1] = router_18_24_to_router_17_24_req; - assign router_17_24_req_in[2] = router_17_23_to_router_17_24_req; - assign router_17_24_req_in[3] = router_16_24_to_router_17_24_req; - assign router_17_24_req_in[4] = magia_tile_ni_17_24_to_router_17_24_req; - - assign router_17_24_to_router_17_25_rsp = router_17_24_rsp_out[0]; - assign router_17_24_to_router_18_24_rsp = router_17_24_rsp_out[1]; - assign router_17_24_to_router_17_23_rsp = router_17_24_rsp_out[2]; - assign router_17_24_to_router_16_24_rsp = router_17_24_rsp_out[3]; - assign router_17_24_to_magia_tile_ni_17_24_rsp = router_17_24_rsp_out[4]; - - assign router_17_24_to_router_17_25_req = router_17_24_req_out[0]; - assign router_17_24_to_router_18_24_req = router_17_24_req_out[1]; - assign router_17_24_to_router_17_23_req = router_17_24_req_out[2]; - assign router_17_24_to_router_16_24_req = router_17_24_req_out[3]; - assign router_17_24_to_magia_tile_ni_17_24_req = router_17_24_req_out[4]; - - assign router_17_24_rsp_in[0] = router_17_25_to_router_17_24_rsp; - assign router_17_24_rsp_in[1] = router_18_24_to_router_17_24_rsp; - assign router_17_24_rsp_in[2] = router_17_23_to_router_17_24_rsp; - assign router_17_24_rsp_in[3] = router_16_24_to_router_17_24_rsp; - assign router_17_24_rsp_in[4] = magia_tile_ni_17_24_to_router_17_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_24_req_in), - .floo_rsp_o (router_17_24_rsp_out), - .floo_req_o (router_17_24_req_out), - .floo_rsp_i (router_17_24_rsp_in) -); - - -floo_req_t [4:0] router_17_25_req_in; -floo_rsp_t [4:0] router_17_25_rsp_out; -floo_req_t [4:0] router_17_25_req_out; -floo_rsp_t [4:0] router_17_25_rsp_in; - - assign router_17_25_req_in[0] = router_17_26_to_router_17_25_req; - assign router_17_25_req_in[1] = router_18_25_to_router_17_25_req; - assign router_17_25_req_in[2] = router_17_24_to_router_17_25_req; - assign router_17_25_req_in[3] = router_16_25_to_router_17_25_req; - assign router_17_25_req_in[4] = magia_tile_ni_17_25_to_router_17_25_req; - - assign router_17_25_to_router_17_26_rsp = router_17_25_rsp_out[0]; - assign router_17_25_to_router_18_25_rsp = router_17_25_rsp_out[1]; - assign router_17_25_to_router_17_24_rsp = router_17_25_rsp_out[2]; - assign router_17_25_to_router_16_25_rsp = router_17_25_rsp_out[3]; - assign router_17_25_to_magia_tile_ni_17_25_rsp = router_17_25_rsp_out[4]; - - assign router_17_25_to_router_17_26_req = router_17_25_req_out[0]; - assign router_17_25_to_router_18_25_req = router_17_25_req_out[1]; - assign router_17_25_to_router_17_24_req = router_17_25_req_out[2]; - assign router_17_25_to_router_16_25_req = router_17_25_req_out[3]; - assign router_17_25_to_magia_tile_ni_17_25_req = router_17_25_req_out[4]; - - assign router_17_25_rsp_in[0] = router_17_26_to_router_17_25_rsp; - assign router_17_25_rsp_in[1] = router_18_25_to_router_17_25_rsp; - assign router_17_25_rsp_in[2] = router_17_24_to_router_17_25_rsp; - assign router_17_25_rsp_in[3] = router_16_25_to_router_17_25_rsp; - assign router_17_25_rsp_in[4] = magia_tile_ni_17_25_to_router_17_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_25_req_in), - .floo_rsp_o (router_17_25_rsp_out), - .floo_req_o (router_17_25_req_out), - .floo_rsp_i (router_17_25_rsp_in) -); - - -floo_req_t [4:0] router_17_26_req_in; -floo_rsp_t [4:0] router_17_26_rsp_out; -floo_req_t [4:0] router_17_26_req_out; -floo_rsp_t [4:0] router_17_26_rsp_in; - - assign router_17_26_req_in[0] = router_17_27_to_router_17_26_req; - assign router_17_26_req_in[1] = router_18_26_to_router_17_26_req; - assign router_17_26_req_in[2] = router_17_25_to_router_17_26_req; - assign router_17_26_req_in[3] = router_16_26_to_router_17_26_req; - assign router_17_26_req_in[4] = magia_tile_ni_17_26_to_router_17_26_req; - - assign router_17_26_to_router_17_27_rsp = router_17_26_rsp_out[0]; - assign router_17_26_to_router_18_26_rsp = router_17_26_rsp_out[1]; - assign router_17_26_to_router_17_25_rsp = router_17_26_rsp_out[2]; - assign router_17_26_to_router_16_26_rsp = router_17_26_rsp_out[3]; - assign router_17_26_to_magia_tile_ni_17_26_rsp = router_17_26_rsp_out[4]; - - assign router_17_26_to_router_17_27_req = router_17_26_req_out[0]; - assign router_17_26_to_router_18_26_req = router_17_26_req_out[1]; - assign router_17_26_to_router_17_25_req = router_17_26_req_out[2]; - assign router_17_26_to_router_16_26_req = router_17_26_req_out[3]; - assign router_17_26_to_magia_tile_ni_17_26_req = router_17_26_req_out[4]; - - assign router_17_26_rsp_in[0] = router_17_27_to_router_17_26_rsp; - assign router_17_26_rsp_in[1] = router_18_26_to_router_17_26_rsp; - assign router_17_26_rsp_in[2] = router_17_25_to_router_17_26_rsp; - assign router_17_26_rsp_in[3] = router_16_26_to_router_17_26_rsp; - assign router_17_26_rsp_in[4] = magia_tile_ni_17_26_to_router_17_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_26_req_in), - .floo_rsp_o (router_17_26_rsp_out), - .floo_req_o (router_17_26_req_out), - .floo_rsp_i (router_17_26_rsp_in) -); - - -floo_req_t [4:0] router_17_27_req_in; -floo_rsp_t [4:0] router_17_27_rsp_out; -floo_req_t [4:0] router_17_27_req_out; -floo_rsp_t [4:0] router_17_27_rsp_in; - - assign router_17_27_req_in[0] = router_17_28_to_router_17_27_req; - assign router_17_27_req_in[1] = router_18_27_to_router_17_27_req; - assign router_17_27_req_in[2] = router_17_26_to_router_17_27_req; - assign router_17_27_req_in[3] = router_16_27_to_router_17_27_req; - assign router_17_27_req_in[4] = magia_tile_ni_17_27_to_router_17_27_req; - - assign router_17_27_to_router_17_28_rsp = router_17_27_rsp_out[0]; - assign router_17_27_to_router_18_27_rsp = router_17_27_rsp_out[1]; - assign router_17_27_to_router_17_26_rsp = router_17_27_rsp_out[2]; - assign router_17_27_to_router_16_27_rsp = router_17_27_rsp_out[3]; - assign router_17_27_to_magia_tile_ni_17_27_rsp = router_17_27_rsp_out[4]; - - assign router_17_27_to_router_17_28_req = router_17_27_req_out[0]; - assign router_17_27_to_router_18_27_req = router_17_27_req_out[1]; - assign router_17_27_to_router_17_26_req = router_17_27_req_out[2]; - assign router_17_27_to_router_16_27_req = router_17_27_req_out[3]; - assign router_17_27_to_magia_tile_ni_17_27_req = router_17_27_req_out[4]; - - assign router_17_27_rsp_in[0] = router_17_28_to_router_17_27_rsp; - assign router_17_27_rsp_in[1] = router_18_27_to_router_17_27_rsp; - assign router_17_27_rsp_in[2] = router_17_26_to_router_17_27_rsp; - assign router_17_27_rsp_in[3] = router_16_27_to_router_17_27_rsp; - assign router_17_27_rsp_in[4] = magia_tile_ni_17_27_to_router_17_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_27_req_in), - .floo_rsp_o (router_17_27_rsp_out), - .floo_req_o (router_17_27_req_out), - .floo_rsp_i (router_17_27_rsp_in) -); - - -floo_req_t [4:0] router_17_28_req_in; -floo_rsp_t [4:0] router_17_28_rsp_out; -floo_req_t [4:0] router_17_28_req_out; -floo_rsp_t [4:0] router_17_28_rsp_in; - - assign router_17_28_req_in[0] = router_17_29_to_router_17_28_req; - assign router_17_28_req_in[1] = router_18_28_to_router_17_28_req; - assign router_17_28_req_in[2] = router_17_27_to_router_17_28_req; - assign router_17_28_req_in[3] = router_16_28_to_router_17_28_req; - assign router_17_28_req_in[4] = magia_tile_ni_17_28_to_router_17_28_req; - - assign router_17_28_to_router_17_29_rsp = router_17_28_rsp_out[0]; - assign router_17_28_to_router_18_28_rsp = router_17_28_rsp_out[1]; - assign router_17_28_to_router_17_27_rsp = router_17_28_rsp_out[2]; - assign router_17_28_to_router_16_28_rsp = router_17_28_rsp_out[3]; - assign router_17_28_to_magia_tile_ni_17_28_rsp = router_17_28_rsp_out[4]; - - assign router_17_28_to_router_17_29_req = router_17_28_req_out[0]; - assign router_17_28_to_router_18_28_req = router_17_28_req_out[1]; - assign router_17_28_to_router_17_27_req = router_17_28_req_out[2]; - assign router_17_28_to_router_16_28_req = router_17_28_req_out[3]; - assign router_17_28_to_magia_tile_ni_17_28_req = router_17_28_req_out[4]; - - assign router_17_28_rsp_in[0] = router_17_29_to_router_17_28_rsp; - assign router_17_28_rsp_in[1] = router_18_28_to_router_17_28_rsp; - assign router_17_28_rsp_in[2] = router_17_27_to_router_17_28_rsp; - assign router_17_28_rsp_in[3] = router_16_28_to_router_17_28_rsp; - assign router_17_28_rsp_in[4] = magia_tile_ni_17_28_to_router_17_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_28_req_in), - .floo_rsp_o (router_17_28_rsp_out), - .floo_req_o (router_17_28_req_out), - .floo_rsp_i (router_17_28_rsp_in) -); - - -floo_req_t [4:0] router_17_29_req_in; -floo_rsp_t [4:0] router_17_29_rsp_out; -floo_req_t [4:0] router_17_29_req_out; -floo_rsp_t [4:0] router_17_29_rsp_in; - - assign router_17_29_req_in[0] = router_17_30_to_router_17_29_req; - assign router_17_29_req_in[1] = router_18_29_to_router_17_29_req; - assign router_17_29_req_in[2] = router_17_28_to_router_17_29_req; - assign router_17_29_req_in[3] = router_16_29_to_router_17_29_req; - assign router_17_29_req_in[4] = magia_tile_ni_17_29_to_router_17_29_req; - - assign router_17_29_to_router_17_30_rsp = router_17_29_rsp_out[0]; - assign router_17_29_to_router_18_29_rsp = router_17_29_rsp_out[1]; - assign router_17_29_to_router_17_28_rsp = router_17_29_rsp_out[2]; - assign router_17_29_to_router_16_29_rsp = router_17_29_rsp_out[3]; - assign router_17_29_to_magia_tile_ni_17_29_rsp = router_17_29_rsp_out[4]; - - assign router_17_29_to_router_17_30_req = router_17_29_req_out[0]; - assign router_17_29_to_router_18_29_req = router_17_29_req_out[1]; - assign router_17_29_to_router_17_28_req = router_17_29_req_out[2]; - assign router_17_29_to_router_16_29_req = router_17_29_req_out[3]; - assign router_17_29_to_magia_tile_ni_17_29_req = router_17_29_req_out[4]; - - assign router_17_29_rsp_in[0] = router_17_30_to_router_17_29_rsp; - assign router_17_29_rsp_in[1] = router_18_29_to_router_17_29_rsp; - assign router_17_29_rsp_in[2] = router_17_28_to_router_17_29_rsp; - assign router_17_29_rsp_in[3] = router_16_29_to_router_17_29_rsp; - assign router_17_29_rsp_in[4] = magia_tile_ni_17_29_to_router_17_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_29_req_in), - .floo_rsp_o (router_17_29_rsp_out), - .floo_req_o (router_17_29_req_out), - .floo_rsp_i (router_17_29_rsp_in) -); - - -floo_req_t [4:0] router_17_30_req_in; -floo_rsp_t [4:0] router_17_30_rsp_out; -floo_req_t [4:0] router_17_30_req_out; -floo_rsp_t [4:0] router_17_30_rsp_in; - - assign router_17_30_req_in[0] = router_17_31_to_router_17_30_req; - assign router_17_30_req_in[1] = router_18_30_to_router_17_30_req; - assign router_17_30_req_in[2] = router_17_29_to_router_17_30_req; - assign router_17_30_req_in[3] = router_16_30_to_router_17_30_req; - assign router_17_30_req_in[4] = magia_tile_ni_17_30_to_router_17_30_req; - - assign router_17_30_to_router_17_31_rsp = router_17_30_rsp_out[0]; - assign router_17_30_to_router_18_30_rsp = router_17_30_rsp_out[1]; - assign router_17_30_to_router_17_29_rsp = router_17_30_rsp_out[2]; - assign router_17_30_to_router_16_30_rsp = router_17_30_rsp_out[3]; - assign router_17_30_to_magia_tile_ni_17_30_rsp = router_17_30_rsp_out[4]; - - assign router_17_30_to_router_17_31_req = router_17_30_req_out[0]; - assign router_17_30_to_router_18_30_req = router_17_30_req_out[1]; - assign router_17_30_to_router_17_29_req = router_17_30_req_out[2]; - assign router_17_30_to_router_16_30_req = router_17_30_req_out[3]; - assign router_17_30_to_magia_tile_ni_17_30_req = router_17_30_req_out[4]; - - assign router_17_30_rsp_in[0] = router_17_31_to_router_17_30_rsp; - assign router_17_30_rsp_in[1] = router_18_30_to_router_17_30_rsp; - assign router_17_30_rsp_in[2] = router_17_29_to_router_17_30_rsp; - assign router_17_30_rsp_in[3] = router_16_30_to_router_17_30_rsp; - assign router_17_30_rsp_in[4] = magia_tile_ni_17_30_to_router_17_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_30_req_in), - .floo_rsp_o (router_17_30_rsp_out), - .floo_req_o (router_17_30_req_out), - .floo_rsp_i (router_17_30_rsp_in) -); - - -floo_req_t [4:0] router_17_31_req_in; -floo_rsp_t [4:0] router_17_31_rsp_out; -floo_req_t [4:0] router_17_31_req_out; -floo_rsp_t [4:0] router_17_31_rsp_in; - - assign router_17_31_req_in[0] = '0; - assign router_17_31_req_in[1] = router_18_31_to_router_17_31_req; - assign router_17_31_req_in[2] = router_17_30_to_router_17_31_req; - assign router_17_31_req_in[3] = router_16_31_to_router_17_31_req; - assign router_17_31_req_in[4] = magia_tile_ni_17_31_to_router_17_31_req; - - assign router_17_31_to_router_18_31_rsp = router_17_31_rsp_out[1]; - assign router_17_31_to_router_17_30_rsp = router_17_31_rsp_out[2]; - assign router_17_31_to_router_16_31_rsp = router_17_31_rsp_out[3]; - assign router_17_31_to_magia_tile_ni_17_31_rsp = router_17_31_rsp_out[4]; - - assign router_17_31_to_router_18_31_req = router_17_31_req_out[1]; - assign router_17_31_to_router_17_30_req = router_17_31_req_out[2]; - assign router_17_31_to_router_16_31_req = router_17_31_req_out[3]; - assign router_17_31_to_magia_tile_ni_17_31_req = router_17_31_req_out[4]; - - assign router_17_31_rsp_in[0] = '0; - assign router_17_31_rsp_in[1] = router_18_31_to_router_17_31_rsp; - assign router_17_31_rsp_in[2] = router_17_30_to_router_17_31_rsp; - assign router_17_31_rsp_in[3] = router_16_31_to_router_17_31_rsp; - assign router_17_31_rsp_in[4] = magia_tile_ni_17_31_to_router_17_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_17_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 18, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_17_31_req_in), - .floo_rsp_o (router_17_31_rsp_out), - .floo_req_o (router_17_31_req_out), - .floo_rsp_i (router_17_31_rsp_in) -); - - -floo_req_t [4:0] router_18_0_req_in; -floo_rsp_t [4:0] router_18_0_rsp_out; -floo_req_t [4:0] router_18_0_req_out; -floo_rsp_t [4:0] router_18_0_rsp_in; - - assign router_18_0_req_in[0] = router_18_1_to_router_18_0_req; - assign router_18_0_req_in[1] = router_19_0_to_router_18_0_req; - assign router_18_0_req_in[2] = '0; - assign router_18_0_req_in[3] = router_17_0_to_router_18_0_req; - assign router_18_0_req_in[4] = magia_tile_ni_18_0_to_router_18_0_req; - - assign router_18_0_to_router_18_1_rsp = router_18_0_rsp_out[0]; - assign router_18_0_to_router_19_0_rsp = router_18_0_rsp_out[1]; - assign router_18_0_to_router_17_0_rsp = router_18_0_rsp_out[3]; - assign router_18_0_to_magia_tile_ni_18_0_rsp = router_18_0_rsp_out[4]; - - assign router_18_0_to_router_18_1_req = router_18_0_req_out[0]; - assign router_18_0_to_router_19_0_req = router_18_0_req_out[1]; - assign router_18_0_to_router_17_0_req = router_18_0_req_out[3]; - assign router_18_0_to_magia_tile_ni_18_0_req = router_18_0_req_out[4]; - - assign router_18_0_rsp_in[0] = router_18_1_to_router_18_0_rsp; - assign router_18_0_rsp_in[1] = router_19_0_to_router_18_0_rsp; - assign router_18_0_rsp_in[2] = '0; - assign router_18_0_rsp_in[3] = router_17_0_to_router_18_0_rsp; - assign router_18_0_rsp_in[4] = magia_tile_ni_18_0_to_router_18_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_0_req_in), - .floo_rsp_o (router_18_0_rsp_out), - .floo_req_o (router_18_0_req_out), - .floo_rsp_i (router_18_0_rsp_in) -); - - -floo_req_t [4:0] router_18_1_req_in; -floo_rsp_t [4:0] router_18_1_rsp_out; -floo_req_t [4:0] router_18_1_req_out; -floo_rsp_t [4:0] router_18_1_rsp_in; - - assign router_18_1_req_in[0] = router_18_2_to_router_18_1_req; - assign router_18_1_req_in[1] = router_19_1_to_router_18_1_req; - assign router_18_1_req_in[2] = router_18_0_to_router_18_1_req; - assign router_18_1_req_in[3] = router_17_1_to_router_18_1_req; - assign router_18_1_req_in[4] = magia_tile_ni_18_1_to_router_18_1_req; - - assign router_18_1_to_router_18_2_rsp = router_18_1_rsp_out[0]; - assign router_18_1_to_router_19_1_rsp = router_18_1_rsp_out[1]; - assign router_18_1_to_router_18_0_rsp = router_18_1_rsp_out[2]; - assign router_18_1_to_router_17_1_rsp = router_18_1_rsp_out[3]; - assign router_18_1_to_magia_tile_ni_18_1_rsp = router_18_1_rsp_out[4]; - - assign router_18_1_to_router_18_2_req = router_18_1_req_out[0]; - assign router_18_1_to_router_19_1_req = router_18_1_req_out[1]; - assign router_18_1_to_router_18_0_req = router_18_1_req_out[2]; - assign router_18_1_to_router_17_1_req = router_18_1_req_out[3]; - assign router_18_1_to_magia_tile_ni_18_1_req = router_18_1_req_out[4]; - - assign router_18_1_rsp_in[0] = router_18_2_to_router_18_1_rsp; - assign router_18_1_rsp_in[1] = router_19_1_to_router_18_1_rsp; - assign router_18_1_rsp_in[2] = router_18_0_to_router_18_1_rsp; - assign router_18_1_rsp_in[3] = router_17_1_to_router_18_1_rsp; - assign router_18_1_rsp_in[4] = magia_tile_ni_18_1_to_router_18_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_1_req_in), - .floo_rsp_o (router_18_1_rsp_out), - .floo_req_o (router_18_1_req_out), - .floo_rsp_i (router_18_1_rsp_in) -); - - -floo_req_t [4:0] router_18_2_req_in; -floo_rsp_t [4:0] router_18_2_rsp_out; -floo_req_t [4:0] router_18_2_req_out; -floo_rsp_t [4:0] router_18_2_rsp_in; - - assign router_18_2_req_in[0] = router_18_3_to_router_18_2_req; - assign router_18_2_req_in[1] = router_19_2_to_router_18_2_req; - assign router_18_2_req_in[2] = router_18_1_to_router_18_2_req; - assign router_18_2_req_in[3] = router_17_2_to_router_18_2_req; - assign router_18_2_req_in[4] = magia_tile_ni_18_2_to_router_18_2_req; - - assign router_18_2_to_router_18_3_rsp = router_18_2_rsp_out[0]; - assign router_18_2_to_router_19_2_rsp = router_18_2_rsp_out[1]; - assign router_18_2_to_router_18_1_rsp = router_18_2_rsp_out[2]; - assign router_18_2_to_router_17_2_rsp = router_18_2_rsp_out[3]; - assign router_18_2_to_magia_tile_ni_18_2_rsp = router_18_2_rsp_out[4]; - - assign router_18_2_to_router_18_3_req = router_18_2_req_out[0]; - assign router_18_2_to_router_19_2_req = router_18_2_req_out[1]; - assign router_18_2_to_router_18_1_req = router_18_2_req_out[2]; - assign router_18_2_to_router_17_2_req = router_18_2_req_out[3]; - assign router_18_2_to_magia_tile_ni_18_2_req = router_18_2_req_out[4]; - - assign router_18_2_rsp_in[0] = router_18_3_to_router_18_2_rsp; - assign router_18_2_rsp_in[1] = router_19_2_to_router_18_2_rsp; - assign router_18_2_rsp_in[2] = router_18_1_to_router_18_2_rsp; - assign router_18_2_rsp_in[3] = router_17_2_to_router_18_2_rsp; - assign router_18_2_rsp_in[4] = magia_tile_ni_18_2_to_router_18_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_2_req_in), - .floo_rsp_o (router_18_2_rsp_out), - .floo_req_o (router_18_2_req_out), - .floo_rsp_i (router_18_2_rsp_in) -); - - -floo_req_t [4:0] router_18_3_req_in; -floo_rsp_t [4:0] router_18_3_rsp_out; -floo_req_t [4:0] router_18_3_req_out; -floo_rsp_t [4:0] router_18_3_rsp_in; - - assign router_18_3_req_in[0] = router_18_4_to_router_18_3_req; - assign router_18_3_req_in[1] = router_19_3_to_router_18_3_req; - assign router_18_3_req_in[2] = router_18_2_to_router_18_3_req; - assign router_18_3_req_in[3] = router_17_3_to_router_18_3_req; - assign router_18_3_req_in[4] = magia_tile_ni_18_3_to_router_18_3_req; - - assign router_18_3_to_router_18_4_rsp = router_18_3_rsp_out[0]; - assign router_18_3_to_router_19_3_rsp = router_18_3_rsp_out[1]; - assign router_18_3_to_router_18_2_rsp = router_18_3_rsp_out[2]; - assign router_18_3_to_router_17_3_rsp = router_18_3_rsp_out[3]; - assign router_18_3_to_magia_tile_ni_18_3_rsp = router_18_3_rsp_out[4]; - - assign router_18_3_to_router_18_4_req = router_18_3_req_out[0]; - assign router_18_3_to_router_19_3_req = router_18_3_req_out[1]; - assign router_18_3_to_router_18_2_req = router_18_3_req_out[2]; - assign router_18_3_to_router_17_3_req = router_18_3_req_out[3]; - assign router_18_3_to_magia_tile_ni_18_3_req = router_18_3_req_out[4]; - - assign router_18_3_rsp_in[0] = router_18_4_to_router_18_3_rsp; - assign router_18_3_rsp_in[1] = router_19_3_to_router_18_3_rsp; - assign router_18_3_rsp_in[2] = router_18_2_to_router_18_3_rsp; - assign router_18_3_rsp_in[3] = router_17_3_to_router_18_3_rsp; - assign router_18_3_rsp_in[4] = magia_tile_ni_18_3_to_router_18_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_3_req_in), - .floo_rsp_o (router_18_3_rsp_out), - .floo_req_o (router_18_3_req_out), - .floo_rsp_i (router_18_3_rsp_in) -); - - -floo_req_t [4:0] router_18_4_req_in; -floo_rsp_t [4:0] router_18_4_rsp_out; -floo_req_t [4:0] router_18_4_req_out; -floo_rsp_t [4:0] router_18_4_rsp_in; - - assign router_18_4_req_in[0] = router_18_5_to_router_18_4_req; - assign router_18_4_req_in[1] = router_19_4_to_router_18_4_req; - assign router_18_4_req_in[2] = router_18_3_to_router_18_4_req; - assign router_18_4_req_in[3] = router_17_4_to_router_18_4_req; - assign router_18_4_req_in[4] = magia_tile_ni_18_4_to_router_18_4_req; - - assign router_18_4_to_router_18_5_rsp = router_18_4_rsp_out[0]; - assign router_18_4_to_router_19_4_rsp = router_18_4_rsp_out[1]; - assign router_18_4_to_router_18_3_rsp = router_18_4_rsp_out[2]; - assign router_18_4_to_router_17_4_rsp = router_18_4_rsp_out[3]; - assign router_18_4_to_magia_tile_ni_18_4_rsp = router_18_4_rsp_out[4]; - - assign router_18_4_to_router_18_5_req = router_18_4_req_out[0]; - assign router_18_4_to_router_19_4_req = router_18_4_req_out[1]; - assign router_18_4_to_router_18_3_req = router_18_4_req_out[2]; - assign router_18_4_to_router_17_4_req = router_18_4_req_out[3]; - assign router_18_4_to_magia_tile_ni_18_4_req = router_18_4_req_out[4]; - - assign router_18_4_rsp_in[0] = router_18_5_to_router_18_4_rsp; - assign router_18_4_rsp_in[1] = router_19_4_to_router_18_4_rsp; - assign router_18_4_rsp_in[2] = router_18_3_to_router_18_4_rsp; - assign router_18_4_rsp_in[3] = router_17_4_to_router_18_4_rsp; - assign router_18_4_rsp_in[4] = magia_tile_ni_18_4_to_router_18_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_4_req_in), - .floo_rsp_o (router_18_4_rsp_out), - .floo_req_o (router_18_4_req_out), - .floo_rsp_i (router_18_4_rsp_in) -); - - -floo_req_t [4:0] router_18_5_req_in; -floo_rsp_t [4:0] router_18_5_rsp_out; -floo_req_t [4:0] router_18_5_req_out; -floo_rsp_t [4:0] router_18_5_rsp_in; - - assign router_18_5_req_in[0] = router_18_6_to_router_18_5_req; - assign router_18_5_req_in[1] = router_19_5_to_router_18_5_req; - assign router_18_5_req_in[2] = router_18_4_to_router_18_5_req; - assign router_18_5_req_in[3] = router_17_5_to_router_18_5_req; - assign router_18_5_req_in[4] = magia_tile_ni_18_5_to_router_18_5_req; - - assign router_18_5_to_router_18_6_rsp = router_18_5_rsp_out[0]; - assign router_18_5_to_router_19_5_rsp = router_18_5_rsp_out[1]; - assign router_18_5_to_router_18_4_rsp = router_18_5_rsp_out[2]; - assign router_18_5_to_router_17_5_rsp = router_18_5_rsp_out[3]; - assign router_18_5_to_magia_tile_ni_18_5_rsp = router_18_5_rsp_out[4]; - - assign router_18_5_to_router_18_6_req = router_18_5_req_out[0]; - assign router_18_5_to_router_19_5_req = router_18_5_req_out[1]; - assign router_18_5_to_router_18_4_req = router_18_5_req_out[2]; - assign router_18_5_to_router_17_5_req = router_18_5_req_out[3]; - assign router_18_5_to_magia_tile_ni_18_5_req = router_18_5_req_out[4]; - - assign router_18_5_rsp_in[0] = router_18_6_to_router_18_5_rsp; - assign router_18_5_rsp_in[1] = router_19_5_to_router_18_5_rsp; - assign router_18_5_rsp_in[2] = router_18_4_to_router_18_5_rsp; - assign router_18_5_rsp_in[3] = router_17_5_to_router_18_5_rsp; - assign router_18_5_rsp_in[4] = magia_tile_ni_18_5_to_router_18_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_5_req_in), - .floo_rsp_o (router_18_5_rsp_out), - .floo_req_o (router_18_5_req_out), - .floo_rsp_i (router_18_5_rsp_in) -); - - -floo_req_t [4:0] router_18_6_req_in; -floo_rsp_t [4:0] router_18_6_rsp_out; -floo_req_t [4:0] router_18_6_req_out; -floo_rsp_t [4:0] router_18_6_rsp_in; - - assign router_18_6_req_in[0] = router_18_7_to_router_18_6_req; - assign router_18_6_req_in[1] = router_19_6_to_router_18_6_req; - assign router_18_6_req_in[2] = router_18_5_to_router_18_6_req; - assign router_18_6_req_in[3] = router_17_6_to_router_18_6_req; - assign router_18_6_req_in[4] = magia_tile_ni_18_6_to_router_18_6_req; - - assign router_18_6_to_router_18_7_rsp = router_18_6_rsp_out[0]; - assign router_18_6_to_router_19_6_rsp = router_18_6_rsp_out[1]; - assign router_18_6_to_router_18_5_rsp = router_18_6_rsp_out[2]; - assign router_18_6_to_router_17_6_rsp = router_18_6_rsp_out[3]; - assign router_18_6_to_magia_tile_ni_18_6_rsp = router_18_6_rsp_out[4]; - - assign router_18_6_to_router_18_7_req = router_18_6_req_out[0]; - assign router_18_6_to_router_19_6_req = router_18_6_req_out[1]; - assign router_18_6_to_router_18_5_req = router_18_6_req_out[2]; - assign router_18_6_to_router_17_6_req = router_18_6_req_out[3]; - assign router_18_6_to_magia_tile_ni_18_6_req = router_18_6_req_out[4]; - - assign router_18_6_rsp_in[0] = router_18_7_to_router_18_6_rsp; - assign router_18_6_rsp_in[1] = router_19_6_to_router_18_6_rsp; - assign router_18_6_rsp_in[2] = router_18_5_to_router_18_6_rsp; - assign router_18_6_rsp_in[3] = router_17_6_to_router_18_6_rsp; - assign router_18_6_rsp_in[4] = magia_tile_ni_18_6_to_router_18_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_6_req_in), - .floo_rsp_o (router_18_6_rsp_out), - .floo_req_o (router_18_6_req_out), - .floo_rsp_i (router_18_6_rsp_in) -); - - -floo_req_t [4:0] router_18_7_req_in; -floo_rsp_t [4:0] router_18_7_rsp_out; -floo_req_t [4:0] router_18_7_req_out; -floo_rsp_t [4:0] router_18_7_rsp_in; - - assign router_18_7_req_in[0] = router_18_8_to_router_18_7_req; - assign router_18_7_req_in[1] = router_19_7_to_router_18_7_req; - assign router_18_7_req_in[2] = router_18_6_to_router_18_7_req; - assign router_18_7_req_in[3] = router_17_7_to_router_18_7_req; - assign router_18_7_req_in[4] = magia_tile_ni_18_7_to_router_18_7_req; - - assign router_18_7_to_router_18_8_rsp = router_18_7_rsp_out[0]; - assign router_18_7_to_router_19_7_rsp = router_18_7_rsp_out[1]; - assign router_18_7_to_router_18_6_rsp = router_18_7_rsp_out[2]; - assign router_18_7_to_router_17_7_rsp = router_18_7_rsp_out[3]; - assign router_18_7_to_magia_tile_ni_18_7_rsp = router_18_7_rsp_out[4]; - - assign router_18_7_to_router_18_8_req = router_18_7_req_out[0]; - assign router_18_7_to_router_19_7_req = router_18_7_req_out[1]; - assign router_18_7_to_router_18_6_req = router_18_7_req_out[2]; - assign router_18_7_to_router_17_7_req = router_18_7_req_out[3]; - assign router_18_7_to_magia_tile_ni_18_7_req = router_18_7_req_out[4]; - - assign router_18_7_rsp_in[0] = router_18_8_to_router_18_7_rsp; - assign router_18_7_rsp_in[1] = router_19_7_to_router_18_7_rsp; - assign router_18_7_rsp_in[2] = router_18_6_to_router_18_7_rsp; - assign router_18_7_rsp_in[3] = router_17_7_to_router_18_7_rsp; - assign router_18_7_rsp_in[4] = magia_tile_ni_18_7_to_router_18_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_7_req_in), - .floo_rsp_o (router_18_7_rsp_out), - .floo_req_o (router_18_7_req_out), - .floo_rsp_i (router_18_7_rsp_in) -); - - -floo_req_t [4:0] router_18_8_req_in; -floo_rsp_t [4:0] router_18_8_rsp_out; -floo_req_t [4:0] router_18_8_req_out; -floo_rsp_t [4:0] router_18_8_rsp_in; - - assign router_18_8_req_in[0] = router_18_9_to_router_18_8_req; - assign router_18_8_req_in[1] = router_19_8_to_router_18_8_req; - assign router_18_8_req_in[2] = router_18_7_to_router_18_8_req; - assign router_18_8_req_in[3] = router_17_8_to_router_18_8_req; - assign router_18_8_req_in[4] = magia_tile_ni_18_8_to_router_18_8_req; - - assign router_18_8_to_router_18_9_rsp = router_18_8_rsp_out[0]; - assign router_18_8_to_router_19_8_rsp = router_18_8_rsp_out[1]; - assign router_18_8_to_router_18_7_rsp = router_18_8_rsp_out[2]; - assign router_18_8_to_router_17_8_rsp = router_18_8_rsp_out[3]; - assign router_18_8_to_magia_tile_ni_18_8_rsp = router_18_8_rsp_out[4]; - - assign router_18_8_to_router_18_9_req = router_18_8_req_out[0]; - assign router_18_8_to_router_19_8_req = router_18_8_req_out[1]; - assign router_18_8_to_router_18_7_req = router_18_8_req_out[2]; - assign router_18_8_to_router_17_8_req = router_18_8_req_out[3]; - assign router_18_8_to_magia_tile_ni_18_8_req = router_18_8_req_out[4]; - - assign router_18_8_rsp_in[0] = router_18_9_to_router_18_8_rsp; - assign router_18_8_rsp_in[1] = router_19_8_to_router_18_8_rsp; - assign router_18_8_rsp_in[2] = router_18_7_to_router_18_8_rsp; - assign router_18_8_rsp_in[3] = router_17_8_to_router_18_8_rsp; - assign router_18_8_rsp_in[4] = magia_tile_ni_18_8_to_router_18_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_8_req_in), - .floo_rsp_o (router_18_8_rsp_out), - .floo_req_o (router_18_8_req_out), - .floo_rsp_i (router_18_8_rsp_in) -); - - -floo_req_t [4:0] router_18_9_req_in; -floo_rsp_t [4:0] router_18_9_rsp_out; -floo_req_t [4:0] router_18_9_req_out; -floo_rsp_t [4:0] router_18_9_rsp_in; - - assign router_18_9_req_in[0] = router_18_10_to_router_18_9_req; - assign router_18_9_req_in[1] = router_19_9_to_router_18_9_req; - assign router_18_9_req_in[2] = router_18_8_to_router_18_9_req; - assign router_18_9_req_in[3] = router_17_9_to_router_18_9_req; - assign router_18_9_req_in[4] = magia_tile_ni_18_9_to_router_18_9_req; - - assign router_18_9_to_router_18_10_rsp = router_18_9_rsp_out[0]; - assign router_18_9_to_router_19_9_rsp = router_18_9_rsp_out[1]; - assign router_18_9_to_router_18_8_rsp = router_18_9_rsp_out[2]; - assign router_18_9_to_router_17_9_rsp = router_18_9_rsp_out[3]; - assign router_18_9_to_magia_tile_ni_18_9_rsp = router_18_9_rsp_out[4]; - - assign router_18_9_to_router_18_10_req = router_18_9_req_out[0]; - assign router_18_9_to_router_19_9_req = router_18_9_req_out[1]; - assign router_18_9_to_router_18_8_req = router_18_9_req_out[2]; - assign router_18_9_to_router_17_9_req = router_18_9_req_out[3]; - assign router_18_9_to_magia_tile_ni_18_9_req = router_18_9_req_out[4]; - - assign router_18_9_rsp_in[0] = router_18_10_to_router_18_9_rsp; - assign router_18_9_rsp_in[1] = router_19_9_to_router_18_9_rsp; - assign router_18_9_rsp_in[2] = router_18_8_to_router_18_9_rsp; - assign router_18_9_rsp_in[3] = router_17_9_to_router_18_9_rsp; - assign router_18_9_rsp_in[4] = magia_tile_ni_18_9_to_router_18_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_9_req_in), - .floo_rsp_o (router_18_9_rsp_out), - .floo_req_o (router_18_9_req_out), - .floo_rsp_i (router_18_9_rsp_in) -); - - -floo_req_t [4:0] router_18_10_req_in; -floo_rsp_t [4:0] router_18_10_rsp_out; -floo_req_t [4:0] router_18_10_req_out; -floo_rsp_t [4:0] router_18_10_rsp_in; - - assign router_18_10_req_in[0] = router_18_11_to_router_18_10_req; - assign router_18_10_req_in[1] = router_19_10_to_router_18_10_req; - assign router_18_10_req_in[2] = router_18_9_to_router_18_10_req; - assign router_18_10_req_in[3] = router_17_10_to_router_18_10_req; - assign router_18_10_req_in[4] = magia_tile_ni_18_10_to_router_18_10_req; - - assign router_18_10_to_router_18_11_rsp = router_18_10_rsp_out[0]; - assign router_18_10_to_router_19_10_rsp = router_18_10_rsp_out[1]; - assign router_18_10_to_router_18_9_rsp = router_18_10_rsp_out[2]; - assign router_18_10_to_router_17_10_rsp = router_18_10_rsp_out[3]; - assign router_18_10_to_magia_tile_ni_18_10_rsp = router_18_10_rsp_out[4]; - - assign router_18_10_to_router_18_11_req = router_18_10_req_out[0]; - assign router_18_10_to_router_19_10_req = router_18_10_req_out[1]; - assign router_18_10_to_router_18_9_req = router_18_10_req_out[2]; - assign router_18_10_to_router_17_10_req = router_18_10_req_out[3]; - assign router_18_10_to_magia_tile_ni_18_10_req = router_18_10_req_out[4]; - - assign router_18_10_rsp_in[0] = router_18_11_to_router_18_10_rsp; - assign router_18_10_rsp_in[1] = router_19_10_to_router_18_10_rsp; - assign router_18_10_rsp_in[2] = router_18_9_to_router_18_10_rsp; - assign router_18_10_rsp_in[3] = router_17_10_to_router_18_10_rsp; - assign router_18_10_rsp_in[4] = magia_tile_ni_18_10_to_router_18_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_10_req_in), - .floo_rsp_o (router_18_10_rsp_out), - .floo_req_o (router_18_10_req_out), - .floo_rsp_i (router_18_10_rsp_in) -); - - -floo_req_t [4:0] router_18_11_req_in; -floo_rsp_t [4:0] router_18_11_rsp_out; -floo_req_t [4:0] router_18_11_req_out; -floo_rsp_t [4:0] router_18_11_rsp_in; - - assign router_18_11_req_in[0] = router_18_12_to_router_18_11_req; - assign router_18_11_req_in[1] = router_19_11_to_router_18_11_req; - assign router_18_11_req_in[2] = router_18_10_to_router_18_11_req; - assign router_18_11_req_in[3] = router_17_11_to_router_18_11_req; - assign router_18_11_req_in[4] = magia_tile_ni_18_11_to_router_18_11_req; - - assign router_18_11_to_router_18_12_rsp = router_18_11_rsp_out[0]; - assign router_18_11_to_router_19_11_rsp = router_18_11_rsp_out[1]; - assign router_18_11_to_router_18_10_rsp = router_18_11_rsp_out[2]; - assign router_18_11_to_router_17_11_rsp = router_18_11_rsp_out[3]; - assign router_18_11_to_magia_tile_ni_18_11_rsp = router_18_11_rsp_out[4]; - - assign router_18_11_to_router_18_12_req = router_18_11_req_out[0]; - assign router_18_11_to_router_19_11_req = router_18_11_req_out[1]; - assign router_18_11_to_router_18_10_req = router_18_11_req_out[2]; - assign router_18_11_to_router_17_11_req = router_18_11_req_out[3]; - assign router_18_11_to_magia_tile_ni_18_11_req = router_18_11_req_out[4]; - - assign router_18_11_rsp_in[0] = router_18_12_to_router_18_11_rsp; - assign router_18_11_rsp_in[1] = router_19_11_to_router_18_11_rsp; - assign router_18_11_rsp_in[2] = router_18_10_to_router_18_11_rsp; - assign router_18_11_rsp_in[3] = router_17_11_to_router_18_11_rsp; - assign router_18_11_rsp_in[4] = magia_tile_ni_18_11_to_router_18_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_11_req_in), - .floo_rsp_o (router_18_11_rsp_out), - .floo_req_o (router_18_11_req_out), - .floo_rsp_i (router_18_11_rsp_in) -); - - -floo_req_t [4:0] router_18_12_req_in; -floo_rsp_t [4:0] router_18_12_rsp_out; -floo_req_t [4:0] router_18_12_req_out; -floo_rsp_t [4:0] router_18_12_rsp_in; - - assign router_18_12_req_in[0] = router_18_13_to_router_18_12_req; - assign router_18_12_req_in[1] = router_19_12_to_router_18_12_req; - assign router_18_12_req_in[2] = router_18_11_to_router_18_12_req; - assign router_18_12_req_in[3] = router_17_12_to_router_18_12_req; - assign router_18_12_req_in[4] = magia_tile_ni_18_12_to_router_18_12_req; - - assign router_18_12_to_router_18_13_rsp = router_18_12_rsp_out[0]; - assign router_18_12_to_router_19_12_rsp = router_18_12_rsp_out[1]; - assign router_18_12_to_router_18_11_rsp = router_18_12_rsp_out[2]; - assign router_18_12_to_router_17_12_rsp = router_18_12_rsp_out[3]; - assign router_18_12_to_magia_tile_ni_18_12_rsp = router_18_12_rsp_out[4]; - - assign router_18_12_to_router_18_13_req = router_18_12_req_out[0]; - assign router_18_12_to_router_19_12_req = router_18_12_req_out[1]; - assign router_18_12_to_router_18_11_req = router_18_12_req_out[2]; - assign router_18_12_to_router_17_12_req = router_18_12_req_out[3]; - assign router_18_12_to_magia_tile_ni_18_12_req = router_18_12_req_out[4]; - - assign router_18_12_rsp_in[0] = router_18_13_to_router_18_12_rsp; - assign router_18_12_rsp_in[1] = router_19_12_to_router_18_12_rsp; - assign router_18_12_rsp_in[2] = router_18_11_to_router_18_12_rsp; - assign router_18_12_rsp_in[3] = router_17_12_to_router_18_12_rsp; - assign router_18_12_rsp_in[4] = magia_tile_ni_18_12_to_router_18_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_12_req_in), - .floo_rsp_o (router_18_12_rsp_out), - .floo_req_o (router_18_12_req_out), - .floo_rsp_i (router_18_12_rsp_in) -); - - -floo_req_t [4:0] router_18_13_req_in; -floo_rsp_t [4:0] router_18_13_rsp_out; -floo_req_t [4:0] router_18_13_req_out; -floo_rsp_t [4:0] router_18_13_rsp_in; - - assign router_18_13_req_in[0] = router_18_14_to_router_18_13_req; - assign router_18_13_req_in[1] = router_19_13_to_router_18_13_req; - assign router_18_13_req_in[2] = router_18_12_to_router_18_13_req; - assign router_18_13_req_in[3] = router_17_13_to_router_18_13_req; - assign router_18_13_req_in[4] = magia_tile_ni_18_13_to_router_18_13_req; - - assign router_18_13_to_router_18_14_rsp = router_18_13_rsp_out[0]; - assign router_18_13_to_router_19_13_rsp = router_18_13_rsp_out[1]; - assign router_18_13_to_router_18_12_rsp = router_18_13_rsp_out[2]; - assign router_18_13_to_router_17_13_rsp = router_18_13_rsp_out[3]; - assign router_18_13_to_magia_tile_ni_18_13_rsp = router_18_13_rsp_out[4]; - - assign router_18_13_to_router_18_14_req = router_18_13_req_out[0]; - assign router_18_13_to_router_19_13_req = router_18_13_req_out[1]; - assign router_18_13_to_router_18_12_req = router_18_13_req_out[2]; - assign router_18_13_to_router_17_13_req = router_18_13_req_out[3]; - assign router_18_13_to_magia_tile_ni_18_13_req = router_18_13_req_out[4]; - - assign router_18_13_rsp_in[0] = router_18_14_to_router_18_13_rsp; - assign router_18_13_rsp_in[1] = router_19_13_to_router_18_13_rsp; - assign router_18_13_rsp_in[2] = router_18_12_to_router_18_13_rsp; - assign router_18_13_rsp_in[3] = router_17_13_to_router_18_13_rsp; - assign router_18_13_rsp_in[4] = magia_tile_ni_18_13_to_router_18_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_13_req_in), - .floo_rsp_o (router_18_13_rsp_out), - .floo_req_o (router_18_13_req_out), - .floo_rsp_i (router_18_13_rsp_in) -); - - -floo_req_t [4:0] router_18_14_req_in; -floo_rsp_t [4:0] router_18_14_rsp_out; -floo_req_t [4:0] router_18_14_req_out; -floo_rsp_t [4:0] router_18_14_rsp_in; - - assign router_18_14_req_in[0] = router_18_15_to_router_18_14_req; - assign router_18_14_req_in[1] = router_19_14_to_router_18_14_req; - assign router_18_14_req_in[2] = router_18_13_to_router_18_14_req; - assign router_18_14_req_in[3] = router_17_14_to_router_18_14_req; - assign router_18_14_req_in[4] = magia_tile_ni_18_14_to_router_18_14_req; - - assign router_18_14_to_router_18_15_rsp = router_18_14_rsp_out[0]; - assign router_18_14_to_router_19_14_rsp = router_18_14_rsp_out[1]; - assign router_18_14_to_router_18_13_rsp = router_18_14_rsp_out[2]; - assign router_18_14_to_router_17_14_rsp = router_18_14_rsp_out[3]; - assign router_18_14_to_magia_tile_ni_18_14_rsp = router_18_14_rsp_out[4]; - - assign router_18_14_to_router_18_15_req = router_18_14_req_out[0]; - assign router_18_14_to_router_19_14_req = router_18_14_req_out[1]; - assign router_18_14_to_router_18_13_req = router_18_14_req_out[2]; - assign router_18_14_to_router_17_14_req = router_18_14_req_out[3]; - assign router_18_14_to_magia_tile_ni_18_14_req = router_18_14_req_out[4]; - - assign router_18_14_rsp_in[0] = router_18_15_to_router_18_14_rsp; - assign router_18_14_rsp_in[1] = router_19_14_to_router_18_14_rsp; - assign router_18_14_rsp_in[2] = router_18_13_to_router_18_14_rsp; - assign router_18_14_rsp_in[3] = router_17_14_to_router_18_14_rsp; - assign router_18_14_rsp_in[4] = magia_tile_ni_18_14_to_router_18_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_14_req_in), - .floo_rsp_o (router_18_14_rsp_out), - .floo_req_o (router_18_14_req_out), - .floo_rsp_i (router_18_14_rsp_in) -); - - -floo_req_t [4:0] router_18_15_req_in; -floo_rsp_t [4:0] router_18_15_rsp_out; -floo_req_t [4:0] router_18_15_req_out; -floo_rsp_t [4:0] router_18_15_rsp_in; - - assign router_18_15_req_in[0] = router_18_16_to_router_18_15_req; - assign router_18_15_req_in[1] = router_19_15_to_router_18_15_req; - assign router_18_15_req_in[2] = router_18_14_to_router_18_15_req; - assign router_18_15_req_in[3] = router_17_15_to_router_18_15_req; - assign router_18_15_req_in[4] = magia_tile_ni_18_15_to_router_18_15_req; - - assign router_18_15_to_router_18_16_rsp = router_18_15_rsp_out[0]; - assign router_18_15_to_router_19_15_rsp = router_18_15_rsp_out[1]; - assign router_18_15_to_router_18_14_rsp = router_18_15_rsp_out[2]; - assign router_18_15_to_router_17_15_rsp = router_18_15_rsp_out[3]; - assign router_18_15_to_magia_tile_ni_18_15_rsp = router_18_15_rsp_out[4]; - - assign router_18_15_to_router_18_16_req = router_18_15_req_out[0]; - assign router_18_15_to_router_19_15_req = router_18_15_req_out[1]; - assign router_18_15_to_router_18_14_req = router_18_15_req_out[2]; - assign router_18_15_to_router_17_15_req = router_18_15_req_out[3]; - assign router_18_15_to_magia_tile_ni_18_15_req = router_18_15_req_out[4]; - - assign router_18_15_rsp_in[0] = router_18_16_to_router_18_15_rsp; - assign router_18_15_rsp_in[1] = router_19_15_to_router_18_15_rsp; - assign router_18_15_rsp_in[2] = router_18_14_to_router_18_15_rsp; - assign router_18_15_rsp_in[3] = router_17_15_to_router_18_15_rsp; - assign router_18_15_rsp_in[4] = magia_tile_ni_18_15_to_router_18_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_15_req_in), - .floo_rsp_o (router_18_15_rsp_out), - .floo_req_o (router_18_15_req_out), - .floo_rsp_i (router_18_15_rsp_in) -); - - -floo_req_t [4:0] router_18_16_req_in; -floo_rsp_t [4:0] router_18_16_rsp_out; -floo_req_t [4:0] router_18_16_req_out; -floo_rsp_t [4:0] router_18_16_rsp_in; - - assign router_18_16_req_in[0] = router_18_17_to_router_18_16_req; - assign router_18_16_req_in[1] = router_19_16_to_router_18_16_req; - assign router_18_16_req_in[2] = router_18_15_to_router_18_16_req; - assign router_18_16_req_in[3] = router_17_16_to_router_18_16_req; - assign router_18_16_req_in[4] = magia_tile_ni_18_16_to_router_18_16_req; - - assign router_18_16_to_router_18_17_rsp = router_18_16_rsp_out[0]; - assign router_18_16_to_router_19_16_rsp = router_18_16_rsp_out[1]; - assign router_18_16_to_router_18_15_rsp = router_18_16_rsp_out[2]; - assign router_18_16_to_router_17_16_rsp = router_18_16_rsp_out[3]; - assign router_18_16_to_magia_tile_ni_18_16_rsp = router_18_16_rsp_out[4]; - - assign router_18_16_to_router_18_17_req = router_18_16_req_out[0]; - assign router_18_16_to_router_19_16_req = router_18_16_req_out[1]; - assign router_18_16_to_router_18_15_req = router_18_16_req_out[2]; - assign router_18_16_to_router_17_16_req = router_18_16_req_out[3]; - assign router_18_16_to_magia_tile_ni_18_16_req = router_18_16_req_out[4]; - - assign router_18_16_rsp_in[0] = router_18_17_to_router_18_16_rsp; - assign router_18_16_rsp_in[1] = router_19_16_to_router_18_16_rsp; - assign router_18_16_rsp_in[2] = router_18_15_to_router_18_16_rsp; - assign router_18_16_rsp_in[3] = router_17_16_to_router_18_16_rsp; - assign router_18_16_rsp_in[4] = magia_tile_ni_18_16_to_router_18_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_16_req_in), - .floo_rsp_o (router_18_16_rsp_out), - .floo_req_o (router_18_16_req_out), - .floo_rsp_i (router_18_16_rsp_in) -); - - -floo_req_t [4:0] router_18_17_req_in; -floo_rsp_t [4:0] router_18_17_rsp_out; -floo_req_t [4:0] router_18_17_req_out; -floo_rsp_t [4:0] router_18_17_rsp_in; - - assign router_18_17_req_in[0] = router_18_18_to_router_18_17_req; - assign router_18_17_req_in[1] = router_19_17_to_router_18_17_req; - assign router_18_17_req_in[2] = router_18_16_to_router_18_17_req; - assign router_18_17_req_in[3] = router_17_17_to_router_18_17_req; - assign router_18_17_req_in[4] = magia_tile_ni_18_17_to_router_18_17_req; - - assign router_18_17_to_router_18_18_rsp = router_18_17_rsp_out[0]; - assign router_18_17_to_router_19_17_rsp = router_18_17_rsp_out[1]; - assign router_18_17_to_router_18_16_rsp = router_18_17_rsp_out[2]; - assign router_18_17_to_router_17_17_rsp = router_18_17_rsp_out[3]; - assign router_18_17_to_magia_tile_ni_18_17_rsp = router_18_17_rsp_out[4]; - - assign router_18_17_to_router_18_18_req = router_18_17_req_out[0]; - assign router_18_17_to_router_19_17_req = router_18_17_req_out[1]; - assign router_18_17_to_router_18_16_req = router_18_17_req_out[2]; - assign router_18_17_to_router_17_17_req = router_18_17_req_out[3]; - assign router_18_17_to_magia_tile_ni_18_17_req = router_18_17_req_out[4]; - - assign router_18_17_rsp_in[0] = router_18_18_to_router_18_17_rsp; - assign router_18_17_rsp_in[1] = router_19_17_to_router_18_17_rsp; - assign router_18_17_rsp_in[2] = router_18_16_to_router_18_17_rsp; - assign router_18_17_rsp_in[3] = router_17_17_to_router_18_17_rsp; - assign router_18_17_rsp_in[4] = magia_tile_ni_18_17_to_router_18_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_17_req_in), - .floo_rsp_o (router_18_17_rsp_out), - .floo_req_o (router_18_17_req_out), - .floo_rsp_i (router_18_17_rsp_in) -); - - -floo_req_t [4:0] router_18_18_req_in; -floo_rsp_t [4:0] router_18_18_rsp_out; -floo_req_t [4:0] router_18_18_req_out; -floo_rsp_t [4:0] router_18_18_rsp_in; - - assign router_18_18_req_in[0] = router_18_19_to_router_18_18_req; - assign router_18_18_req_in[1] = router_19_18_to_router_18_18_req; - assign router_18_18_req_in[2] = router_18_17_to_router_18_18_req; - assign router_18_18_req_in[3] = router_17_18_to_router_18_18_req; - assign router_18_18_req_in[4] = magia_tile_ni_18_18_to_router_18_18_req; - - assign router_18_18_to_router_18_19_rsp = router_18_18_rsp_out[0]; - assign router_18_18_to_router_19_18_rsp = router_18_18_rsp_out[1]; - assign router_18_18_to_router_18_17_rsp = router_18_18_rsp_out[2]; - assign router_18_18_to_router_17_18_rsp = router_18_18_rsp_out[3]; - assign router_18_18_to_magia_tile_ni_18_18_rsp = router_18_18_rsp_out[4]; - - assign router_18_18_to_router_18_19_req = router_18_18_req_out[0]; - assign router_18_18_to_router_19_18_req = router_18_18_req_out[1]; - assign router_18_18_to_router_18_17_req = router_18_18_req_out[2]; - assign router_18_18_to_router_17_18_req = router_18_18_req_out[3]; - assign router_18_18_to_magia_tile_ni_18_18_req = router_18_18_req_out[4]; - - assign router_18_18_rsp_in[0] = router_18_19_to_router_18_18_rsp; - assign router_18_18_rsp_in[1] = router_19_18_to_router_18_18_rsp; - assign router_18_18_rsp_in[2] = router_18_17_to_router_18_18_rsp; - assign router_18_18_rsp_in[3] = router_17_18_to_router_18_18_rsp; - assign router_18_18_rsp_in[4] = magia_tile_ni_18_18_to_router_18_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_18_req_in), - .floo_rsp_o (router_18_18_rsp_out), - .floo_req_o (router_18_18_req_out), - .floo_rsp_i (router_18_18_rsp_in) -); - - -floo_req_t [4:0] router_18_19_req_in; -floo_rsp_t [4:0] router_18_19_rsp_out; -floo_req_t [4:0] router_18_19_req_out; -floo_rsp_t [4:0] router_18_19_rsp_in; - - assign router_18_19_req_in[0] = router_18_20_to_router_18_19_req; - assign router_18_19_req_in[1] = router_19_19_to_router_18_19_req; - assign router_18_19_req_in[2] = router_18_18_to_router_18_19_req; - assign router_18_19_req_in[3] = router_17_19_to_router_18_19_req; - assign router_18_19_req_in[4] = magia_tile_ni_18_19_to_router_18_19_req; - - assign router_18_19_to_router_18_20_rsp = router_18_19_rsp_out[0]; - assign router_18_19_to_router_19_19_rsp = router_18_19_rsp_out[1]; - assign router_18_19_to_router_18_18_rsp = router_18_19_rsp_out[2]; - assign router_18_19_to_router_17_19_rsp = router_18_19_rsp_out[3]; - assign router_18_19_to_magia_tile_ni_18_19_rsp = router_18_19_rsp_out[4]; - - assign router_18_19_to_router_18_20_req = router_18_19_req_out[0]; - assign router_18_19_to_router_19_19_req = router_18_19_req_out[1]; - assign router_18_19_to_router_18_18_req = router_18_19_req_out[2]; - assign router_18_19_to_router_17_19_req = router_18_19_req_out[3]; - assign router_18_19_to_magia_tile_ni_18_19_req = router_18_19_req_out[4]; - - assign router_18_19_rsp_in[0] = router_18_20_to_router_18_19_rsp; - assign router_18_19_rsp_in[1] = router_19_19_to_router_18_19_rsp; - assign router_18_19_rsp_in[2] = router_18_18_to_router_18_19_rsp; - assign router_18_19_rsp_in[3] = router_17_19_to_router_18_19_rsp; - assign router_18_19_rsp_in[4] = magia_tile_ni_18_19_to_router_18_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_19_req_in), - .floo_rsp_o (router_18_19_rsp_out), - .floo_req_o (router_18_19_req_out), - .floo_rsp_i (router_18_19_rsp_in) -); - - -floo_req_t [4:0] router_18_20_req_in; -floo_rsp_t [4:0] router_18_20_rsp_out; -floo_req_t [4:0] router_18_20_req_out; -floo_rsp_t [4:0] router_18_20_rsp_in; - - assign router_18_20_req_in[0] = router_18_21_to_router_18_20_req; - assign router_18_20_req_in[1] = router_19_20_to_router_18_20_req; - assign router_18_20_req_in[2] = router_18_19_to_router_18_20_req; - assign router_18_20_req_in[3] = router_17_20_to_router_18_20_req; - assign router_18_20_req_in[4] = magia_tile_ni_18_20_to_router_18_20_req; - - assign router_18_20_to_router_18_21_rsp = router_18_20_rsp_out[0]; - assign router_18_20_to_router_19_20_rsp = router_18_20_rsp_out[1]; - assign router_18_20_to_router_18_19_rsp = router_18_20_rsp_out[2]; - assign router_18_20_to_router_17_20_rsp = router_18_20_rsp_out[3]; - assign router_18_20_to_magia_tile_ni_18_20_rsp = router_18_20_rsp_out[4]; - - assign router_18_20_to_router_18_21_req = router_18_20_req_out[0]; - assign router_18_20_to_router_19_20_req = router_18_20_req_out[1]; - assign router_18_20_to_router_18_19_req = router_18_20_req_out[2]; - assign router_18_20_to_router_17_20_req = router_18_20_req_out[3]; - assign router_18_20_to_magia_tile_ni_18_20_req = router_18_20_req_out[4]; - - assign router_18_20_rsp_in[0] = router_18_21_to_router_18_20_rsp; - assign router_18_20_rsp_in[1] = router_19_20_to_router_18_20_rsp; - assign router_18_20_rsp_in[2] = router_18_19_to_router_18_20_rsp; - assign router_18_20_rsp_in[3] = router_17_20_to_router_18_20_rsp; - assign router_18_20_rsp_in[4] = magia_tile_ni_18_20_to_router_18_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_20_req_in), - .floo_rsp_o (router_18_20_rsp_out), - .floo_req_o (router_18_20_req_out), - .floo_rsp_i (router_18_20_rsp_in) -); - - -floo_req_t [4:0] router_18_21_req_in; -floo_rsp_t [4:0] router_18_21_rsp_out; -floo_req_t [4:0] router_18_21_req_out; -floo_rsp_t [4:0] router_18_21_rsp_in; - - assign router_18_21_req_in[0] = router_18_22_to_router_18_21_req; - assign router_18_21_req_in[1] = router_19_21_to_router_18_21_req; - assign router_18_21_req_in[2] = router_18_20_to_router_18_21_req; - assign router_18_21_req_in[3] = router_17_21_to_router_18_21_req; - assign router_18_21_req_in[4] = magia_tile_ni_18_21_to_router_18_21_req; - - assign router_18_21_to_router_18_22_rsp = router_18_21_rsp_out[0]; - assign router_18_21_to_router_19_21_rsp = router_18_21_rsp_out[1]; - assign router_18_21_to_router_18_20_rsp = router_18_21_rsp_out[2]; - assign router_18_21_to_router_17_21_rsp = router_18_21_rsp_out[3]; - assign router_18_21_to_magia_tile_ni_18_21_rsp = router_18_21_rsp_out[4]; - - assign router_18_21_to_router_18_22_req = router_18_21_req_out[0]; - assign router_18_21_to_router_19_21_req = router_18_21_req_out[1]; - assign router_18_21_to_router_18_20_req = router_18_21_req_out[2]; - assign router_18_21_to_router_17_21_req = router_18_21_req_out[3]; - assign router_18_21_to_magia_tile_ni_18_21_req = router_18_21_req_out[4]; - - assign router_18_21_rsp_in[0] = router_18_22_to_router_18_21_rsp; - assign router_18_21_rsp_in[1] = router_19_21_to_router_18_21_rsp; - assign router_18_21_rsp_in[2] = router_18_20_to_router_18_21_rsp; - assign router_18_21_rsp_in[3] = router_17_21_to_router_18_21_rsp; - assign router_18_21_rsp_in[4] = magia_tile_ni_18_21_to_router_18_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_21_req_in), - .floo_rsp_o (router_18_21_rsp_out), - .floo_req_o (router_18_21_req_out), - .floo_rsp_i (router_18_21_rsp_in) -); - - -floo_req_t [4:0] router_18_22_req_in; -floo_rsp_t [4:0] router_18_22_rsp_out; -floo_req_t [4:0] router_18_22_req_out; -floo_rsp_t [4:0] router_18_22_rsp_in; - - assign router_18_22_req_in[0] = router_18_23_to_router_18_22_req; - assign router_18_22_req_in[1] = router_19_22_to_router_18_22_req; - assign router_18_22_req_in[2] = router_18_21_to_router_18_22_req; - assign router_18_22_req_in[3] = router_17_22_to_router_18_22_req; - assign router_18_22_req_in[4] = magia_tile_ni_18_22_to_router_18_22_req; - - assign router_18_22_to_router_18_23_rsp = router_18_22_rsp_out[0]; - assign router_18_22_to_router_19_22_rsp = router_18_22_rsp_out[1]; - assign router_18_22_to_router_18_21_rsp = router_18_22_rsp_out[2]; - assign router_18_22_to_router_17_22_rsp = router_18_22_rsp_out[3]; - assign router_18_22_to_magia_tile_ni_18_22_rsp = router_18_22_rsp_out[4]; - - assign router_18_22_to_router_18_23_req = router_18_22_req_out[0]; - assign router_18_22_to_router_19_22_req = router_18_22_req_out[1]; - assign router_18_22_to_router_18_21_req = router_18_22_req_out[2]; - assign router_18_22_to_router_17_22_req = router_18_22_req_out[3]; - assign router_18_22_to_magia_tile_ni_18_22_req = router_18_22_req_out[4]; - - assign router_18_22_rsp_in[0] = router_18_23_to_router_18_22_rsp; - assign router_18_22_rsp_in[1] = router_19_22_to_router_18_22_rsp; - assign router_18_22_rsp_in[2] = router_18_21_to_router_18_22_rsp; - assign router_18_22_rsp_in[3] = router_17_22_to_router_18_22_rsp; - assign router_18_22_rsp_in[4] = magia_tile_ni_18_22_to_router_18_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_22_req_in), - .floo_rsp_o (router_18_22_rsp_out), - .floo_req_o (router_18_22_req_out), - .floo_rsp_i (router_18_22_rsp_in) -); - - -floo_req_t [4:0] router_18_23_req_in; -floo_rsp_t [4:0] router_18_23_rsp_out; -floo_req_t [4:0] router_18_23_req_out; -floo_rsp_t [4:0] router_18_23_rsp_in; - - assign router_18_23_req_in[0] = router_18_24_to_router_18_23_req; - assign router_18_23_req_in[1] = router_19_23_to_router_18_23_req; - assign router_18_23_req_in[2] = router_18_22_to_router_18_23_req; - assign router_18_23_req_in[3] = router_17_23_to_router_18_23_req; - assign router_18_23_req_in[4] = magia_tile_ni_18_23_to_router_18_23_req; - - assign router_18_23_to_router_18_24_rsp = router_18_23_rsp_out[0]; - assign router_18_23_to_router_19_23_rsp = router_18_23_rsp_out[1]; - assign router_18_23_to_router_18_22_rsp = router_18_23_rsp_out[2]; - assign router_18_23_to_router_17_23_rsp = router_18_23_rsp_out[3]; - assign router_18_23_to_magia_tile_ni_18_23_rsp = router_18_23_rsp_out[4]; - - assign router_18_23_to_router_18_24_req = router_18_23_req_out[0]; - assign router_18_23_to_router_19_23_req = router_18_23_req_out[1]; - assign router_18_23_to_router_18_22_req = router_18_23_req_out[2]; - assign router_18_23_to_router_17_23_req = router_18_23_req_out[3]; - assign router_18_23_to_magia_tile_ni_18_23_req = router_18_23_req_out[4]; - - assign router_18_23_rsp_in[0] = router_18_24_to_router_18_23_rsp; - assign router_18_23_rsp_in[1] = router_19_23_to_router_18_23_rsp; - assign router_18_23_rsp_in[2] = router_18_22_to_router_18_23_rsp; - assign router_18_23_rsp_in[3] = router_17_23_to_router_18_23_rsp; - assign router_18_23_rsp_in[4] = magia_tile_ni_18_23_to_router_18_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_23_req_in), - .floo_rsp_o (router_18_23_rsp_out), - .floo_req_o (router_18_23_req_out), - .floo_rsp_i (router_18_23_rsp_in) -); - - -floo_req_t [4:0] router_18_24_req_in; -floo_rsp_t [4:0] router_18_24_rsp_out; -floo_req_t [4:0] router_18_24_req_out; -floo_rsp_t [4:0] router_18_24_rsp_in; - - assign router_18_24_req_in[0] = router_18_25_to_router_18_24_req; - assign router_18_24_req_in[1] = router_19_24_to_router_18_24_req; - assign router_18_24_req_in[2] = router_18_23_to_router_18_24_req; - assign router_18_24_req_in[3] = router_17_24_to_router_18_24_req; - assign router_18_24_req_in[4] = magia_tile_ni_18_24_to_router_18_24_req; - - assign router_18_24_to_router_18_25_rsp = router_18_24_rsp_out[0]; - assign router_18_24_to_router_19_24_rsp = router_18_24_rsp_out[1]; - assign router_18_24_to_router_18_23_rsp = router_18_24_rsp_out[2]; - assign router_18_24_to_router_17_24_rsp = router_18_24_rsp_out[3]; - assign router_18_24_to_magia_tile_ni_18_24_rsp = router_18_24_rsp_out[4]; - - assign router_18_24_to_router_18_25_req = router_18_24_req_out[0]; - assign router_18_24_to_router_19_24_req = router_18_24_req_out[1]; - assign router_18_24_to_router_18_23_req = router_18_24_req_out[2]; - assign router_18_24_to_router_17_24_req = router_18_24_req_out[3]; - assign router_18_24_to_magia_tile_ni_18_24_req = router_18_24_req_out[4]; - - assign router_18_24_rsp_in[0] = router_18_25_to_router_18_24_rsp; - assign router_18_24_rsp_in[1] = router_19_24_to_router_18_24_rsp; - assign router_18_24_rsp_in[2] = router_18_23_to_router_18_24_rsp; - assign router_18_24_rsp_in[3] = router_17_24_to_router_18_24_rsp; - assign router_18_24_rsp_in[4] = magia_tile_ni_18_24_to_router_18_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_24_req_in), - .floo_rsp_o (router_18_24_rsp_out), - .floo_req_o (router_18_24_req_out), - .floo_rsp_i (router_18_24_rsp_in) -); - - -floo_req_t [4:0] router_18_25_req_in; -floo_rsp_t [4:0] router_18_25_rsp_out; -floo_req_t [4:0] router_18_25_req_out; -floo_rsp_t [4:0] router_18_25_rsp_in; - - assign router_18_25_req_in[0] = router_18_26_to_router_18_25_req; - assign router_18_25_req_in[1] = router_19_25_to_router_18_25_req; - assign router_18_25_req_in[2] = router_18_24_to_router_18_25_req; - assign router_18_25_req_in[3] = router_17_25_to_router_18_25_req; - assign router_18_25_req_in[4] = magia_tile_ni_18_25_to_router_18_25_req; - - assign router_18_25_to_router_18_26_rsp = router_18_25_rsp_out[0]; - assign router_18_25_to_router_19_25_rsp = router_18_25_rsp_out[1]; - assign router_18_25_to_router_18_24_rsp = router_18_25_rsp_out[2]; - assign router_18_25_to_router_17_25_rsp = router_18_25_rsp_out[3]; - assign router_18_25_to_magia_tile_ni_18_25_rsp = router_18_25_rsp_out[4]; - - assign router_18_25_to_router_18_26_req = router_18_25_req_out[0]; - assign router_18_25_to_router_19_25_req = router_18_25_req_out[1]; - assign router_18_25_to_router_18_24_req = router_18_25_req_out[2]; - assign router_18_25_to_router_17_25_req = router_18_25_req_out[3]; - assign router_18_25_to_magia_tile_ni_18_25_req = router_18_25_req_out[4]; - - assign router_18_25_rsp_in[0] = router_18_26_to_router_18_25_rsp; - assign router_18_25_rsp_in[1] = router_19_25_to_router_18_25_rsp; - assign router_18_25_rsp_in[2] = router_18_24_to_router_18_25_rsp; - assign router_18_25_rsp_in[3] = router_17_25_to_router_18_25_rsp; - assign router_18_25_rsp_in[4] = magia_tile_ni_18_25_to_router_18_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_25_req_in), - .floo_rsp_o (router_18_25_rsp_out), - .floo_req_o (router_18_25_req_out), - .floo_rsp_i (router_18_25_rsp_in) -); - - -floo_req_t [4:0] router_18_26_req_in; -floo_rsp_t [4:0] router_18_26_rsp_out; -floo_req_t [4:0] router_18_26_req_out; -floo_rsp_t [4:0] router_18_26_rsp_in; - - assign router_18_26_req_in[0] = router_18_27_to_router_18_26_req; - assign router_18_26_req_in[1] = router_19_26_to_router_18_26_req; - assign router_18_26_req_in[2] = router_18_25_to_router_18_26_req; - assign router_18_26_req_in[3] = router_17_26_to_router_18_26_req; - assign router_18_26_req_in[4] = magia_tile_ni_18_26_to_router_18_26_req; - - assign router_18_26_to_router_18_27_rsp = router_18_26_rsp_out[0]; - assign router_18_26_to_router_19_26_rsp = router_18_26_rsp_out[1]; - assign router_18_26_to_router_18_25_rsp = router_18_26_rsp_out[2]; - assign router_18_26_to_router_17_26_rsp = router_18_26_rsp_out[3]; - assign router_18_26_to_magia_tile_ni_18_26_rsp = router_18_26_rsp_out[4]; - - assign router_18_26_to_router_18_27_req = router_18_26_req_out[0]; - assign router_18_26_to_router_19_26_req = router_18_26_req_out[1]; - assign router_18_26_to_router_18_25_req = router_18_26_req_out[2]; - assign router_18_26_to_router_17_26_req = router_18_26_req_out[3]; - assign router_18_26_to_magia_tile_ni_18_26_req = router_18_26_req_out[4]; - - assign router_18_26_rsp_in[0] = router_18_27_to_router_18_26_rsp; - assign router_18_26_rsp_in[1] = router_19_26_to_router_18_26_rsp; - assign router_18_26_rsp_in[2] = router_18_25_to_router_18_26_rsp; - assign router_18_26_rsp_in[3] = router_17_26_to_router_18_26_rsp; - assign router_18_26_rsp_in[4] = magia_tile_ni_18_26_to_router_18_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_26_req_in), - .floo_rsp_o (router_18_26_rsp_out), - .floo_req_o (router_18_26_req_out), - .floo_rsp_i (router_18_26_rsp_in) -); - - -floo_req_t [4:0] router_18_27_req_in; -floo_rsp_t [4:0] router_18_27_rsp_out; -floo_req_t [4:0] router_18_27_req_out; -floo_rsp_t [4:0] router_18_27_rsp_in; - - assign router_18_27_req_in[0] = router_18_28_to_router_18_27_req; - assign router_18_27_req_in[1] = router_19_27_to_router_18_27_req; - assign router_18_27_req_in[2] = router_18_26_to_router_18_27_req; - assign router_18_27_req_in[3] = router_17_27_to_router_18_27_req; - assign router_18_27_req_in[4] = magia_tile_ni_18_27_to_router_18_27_req; - - assign router_18_27_to_router_18_28_rsp = router_18_27_rsp_out[0]; - assign router_18_27_to_router_19_27_rsp = router_18_27_rsp_out[1]; - assign router_18_27_to_router_18_26_rsp = router_18_27_rsp_out[2]; - assign router_18_27_to_router_17_27_rsp = router_18_27_rsp_out[3]; - assign router_18_27_to_magia_tile_ni_18_27_rsp = router_18_27_rsp_out[4]; - - assign router_18_27_to_router_18_28_req = router_18_27_req_out[0]; - assign router_18_27_to_router_19_27_req = router_18_27_req_out[1]; - assign router_18_27_to_router_18_26_req = router_18_27_req_out[2]; - assign router_18_27_to_router_17_27_req = router_18_27_req_out[3]; - assign router_18_27_to_magia_tile_ni_18_27_req = router_18_27_req_out[4]; - - assign router_18_27_rsp_in[0] = router_18_28_to_router_18_27_rsp; - assign router_18_27_rsp_in[1] = router_19_27_to_router_18_27_rsp; - assign router_18_27_rsp_in[2] = router_18_26_to_router_18_27_rsp; - assign router_18_27_rsp_in[3] = router_17_27_to_router_18_27_rsp; - assign router_18_27_rsp_in[4] = magia_tile_ni_18_27_to_router_18_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_27_req_in), - .floo_rsp_o (router_18_27_rsp_out), - .floo_req_o (router_18_27_req_out), - .floo_rsp_i (router_18_27_rsp_in) -); - - -floo_req_t [4:0] router_18_28_req_in; -floo_rsp_t [4:0] router_18_28_rsp_out; -floo_req_t [4:0] router_18_28_req_out; -floo_rsp_t [4:0] router_18_28_rsp_in; - - assign router_18_28_req_in[0] = router_18_29_to_router_18_28_req; - assign router_18_28_req_in[1] = router_19_28_to_router_18_28_req; - assign router_18_28_req_in[2] = router_18_27_to_router_18_28_req; - assign router_18_28_req_in[3] = router_17_28_to_router_18_28_req; - assign router_18_28_req_in[4] = magia_tile_ni_18_28_to_router_18_28_req; - - assign router_18_28_to_router_18_29_rsp = router_18_28_rsp_out[0]; - assign router_18_28_to_router_19_28_rsp = router_18_28_rsp_out[1]; - assign router_18_28_to_router_18_27_rsp = router_18_28_rsp_out[2]; - assign router_18_28_to_router_17_28_rsp = router_18_28_rsp_out[3]; - assign router_18_28_to_magia_tile_ni_18_28_rsp = router_18_28_rsp_out[4]; - - assign router_18_28_to_router_18_29_req = router_18_28_req_out[0]; - assign router_18_28_to_router_19_28_req = router_18_28_req_out[1]; - assign router_18_28_to_router_18_27_req = router_18_28_req_out[2]; - assign router_18_28_to_router_17_28_req = router_18_28_req_out[3]; - assign router_18_28_to_magia_tile_ni_18_28_req = router_18_28_req_out[4]; - - assign router_18_28_rsp_in[0] = router_18_29_to_router_18_28_rsp; - assign router_18_28_rsp_in[1] = router_19_28_to_router_18_28_rsp; - assign router_18_28_rsp_in[2] = router_18_27_to_router_18_28_rsp; - assign router_18_28_rsp_in[3] = router_17_28_to_router_18_28_rsp; - assign router_18_28_rsp_in[4] = magia_tile_ni_18_28_to_router_18_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_28_req_in), - .floo_rsp_o (router_18_28_rsp_out), - .floo_req_o (router_18_28_req_out), - .floo_rsp_i (router_18_28_rsp_in) -); - - -floo_req_t [4:0] router_18_29_req_in; -floo_rsp_t [4:0] router_18_29_rsp_out; -floo_req_t [4:0] router_18_29_req_out; -floo_rsp_t [4:0] router_18_29_rsp_in; - - assign router_18_29_req_in[0] = router_18_30_to_router_18_29_req; - assign router_18_29_req_in[1] = router_19_29_to_router_18_29_req; - assign router_18_29_req_in[2] = router_18_28_to_router_18_29_req; - assign router_18_29_req_in[3] = router_17_29_to_router_18_29_req; - assign router_18_29_req_in[4] = magia_tile_ni_18_29_to_router_18_29_req; - - assign router_18_29_to_router_18_30_rsp = router_18_29_rsp_out[0]; - assign router_18_29_to_router_19_29_rsp = router_18_29_rsp_out[1]; - assign router_18_29_to_router_18_28_rsp = router_18_29_rsp_out[2]; - assign router_18_29_to_router_17_29_rsp = router_18_29_rsp_out[3]; - assign router_18_29_to_magia_tile_ni_18_29_rsp = router_18_29_rsp_out[4]; - - assign router_18_29_to_router_18_30_req = router_18_29_req_out[0]; - assign router_18_29_to_router_19_29_req = router_18_29_req_out[1]; - assign router_18_29_to_router_18_28_req = router_18_29_req_out[2]; - assign router_18_29_to_router_17_29_req = router_18_29_req_out[3]; - assign router_18_29_to_magia_tile_ni_18_29_req = router_18_29_req_out[4]; - - assign router_18_29_rsp_in[0] = router_18_30_to_router_18_29_rsp; - assign router_18_29_rsp_in[1] = router_19_29_to_router_18_29_rsp; - assign router_18_29_rsp_in[2] = router_18_28_to_router_18_29_rsp; - assign router_18_29_rsp_in[3] = router_17_29_to_router_18_29_rsp; - assign router_18_29_rsp_in[4] = magia_tile_ni_18_29_to_router_18_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_29_req_in), - .floo_rsp_o (router_18_29_rsp_out), - .floo_req_o (router_18_29_req_out), - .floo_rsp_i (router_18_29_rsp_in) -); - - -floo_req_t [4:0] router_18_30_req_in; -floo_rsp_t [4:0] router_18_30_rsp_out; -floo_req_t [4:0] router_18_30_req_out; -floo_rsp_t [4:0] router_18_30_rsp_in; - - assign router_18_30_req_in[0] = router_18_31_to_router_18_30_req; - assign router_18_30_req_in[1] = router_19_30_to_router_18_30_req; - assign router_18_30_req_in[2] = router_18_29_to_router_18_30_req; - assign router_18_30_req_in[3] = router_17_30_to_router_18_30_req; - assign router_18_30_req_in[4] = magia_tile_ni_18_30_to_router_18_30_req; - - assign router_18_30_to_router_18_31_rsp = router_18_30_rsp_out[0]; - assign router_18_30_to_router_19_30_rsp = router_18_30_rsp_out[1]; - assign router_18_30_to_router_18_29_rsp = router_18_30_rsp_out[2]; - assign router_18_30_to_router_17_30_rsp = router_18_30_rsp_out[3]; - assign router_18_30_to_magia_tile_ni_18_30_rsp = router_18_30_rsp_out[4]; - - assign router_18_30_to_router_18_31_req = router_18_30_req_out[0]; - assign router_18_30_to_router_19_30_req = router_18_30_req_out[1]; - assign router_18_30_to_router_18_29_req = router_18_30_req_out[2]; - assign router_18_30_to_router_17_30_req = router_18_30_req_out[3]; - assign router_18_30_to_magia_tile_ni_18_30_req = router_18_30_req_out[4]; - - assign router_18_30_rsp_in[0] = router_18_31_to_router_18_30_rsp; - assign router_18_30_rsp_in[1] = router_19_30_to_router_18_30_rsp; - assign router_18_30_rsp_in[2] = router_18_29_to_router_18_30_rsp; - assign router_18_30_rsp_in[3] = router_17_30_to_router_18_30_rsp; - assign router_18_30_rsp_in[4] = magia_tile_ni_18_30_to_router_18_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_30_req_in), - .floo_rsp_o (router_18_30_rsp_out), - .floo_req_o (router_18_30_req_out), - .floo_rsp_i (router_18_30_rsp_in) -); - - -floo_req_t [4:0] router_18_31_req_in; -floo_rsp_t [4:0] router_18_31_rsp_out; -floo_req_t [4:0] router_18_31_req_out; -floo_rsp_t [4:0] router_18_31_rsp_in; - - assign router_18_31_req_in[0] = '0; - assign router_18_31_req_in[1] = router_19_31_to_router_18_31_req; - assign router_18_31_req_in[2] = router_18_30_to_router_18_31_req; - assign router_18_31_req_in[3] = router_17_31_to_router_18_31_req; - assign router_18_31_req_in[4] = magia_tile_ni_18_31_to_router_18_31_req; - - assign router_18_31_to_router_19_31_rsp = router_18_31_rsp_out[1]; - assign router_18_31_to_router_18_30_rsp = router_18_31_rsp_out[2]; - assign router_18_31_to_router_17_31_rsp = router_18_31_rsp_out[3]; - assign router_18_31_to_magia_tile_ni_18_31_rsp = router_18_31_rsp_out[4]; - - assign router_18_31_to_router_19_31_req = router_18_31_req_out[1]; - assign router_18_31_to_router_18_30_req = router_18_31_req_out[2]; - assign router_18_31_to_router_17_31_req = router_18_31_req_out[3]; - assign router_18_31_to_magia_tile_ni_18_31_req = router_18_31_req_out[4]; - - assign router_18_31_rsp_in[0] = '0; - assign router_18_31_rsp_in[1] = router_19_31_to_router_18_31_rsp; - assign router_18_31_rsp_in[2] = router_18_30_to_router_18_31_rsp; - assign router_18_31_rsp_in[3] = router_17_31_to_router_18_31_rsp; - assign router_18_31_rsp_in[4] = magia_tile_ni_18_31_to_router_18_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_18_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 19, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_18_31_req_in), - .floo_rsp_o (router_18_31_rsp_out), - .floo_req_o (router_18_31_req_out), - .floo_rsp_i (router_18_31_rsp_in) -); - - -floo_req_t [4:0] router_19_0_req_in; -floo_rsp_t [4:0] router_19_0_rsp_out; -floo_req_t [4:0] router_19_0_req_out; -floo_rsp_t [4:0] router_19_0_rsp_in; - - assign router_19_0_req_in[0] = router_19_1_to_router_19_0_req; - assign router_19_0_req_in[1] = router_20_0_to_router_19_0_req; - assign router_19_0_req_in[2] = '0; - assign router_19_0_req_in[3] = router_18_0_to_router_19_0_req; - assign router_19_0_req_in[4] = magia_tile_ni_19_0_to_router_19_0_req; - - assign router_19_0_to_router_19_1_rsp = router_19_0_rsp_out[0]; - assign router_19_0_to_router_20_0_rsp = router_19_0_rsp_out[1]; - assign router_19_0_to_router_18_0_rsp = router_19_0_rsp_out[3]; - assign router_19_0_to_magia_tile_ni_19_0_rsp = router_19_0_rsp_out[4]; - - assign router_19_0_to_router_19_1_req = router_19_0_req_out[0]; - assign router_19_0_to_router_20_0_req = router_19_0_req_out[1]; - assign router_19_0_to_router_18_0_req = router_19_0_req_out[3]; - assign router_19_0_to_magia_tile_ni_19_0_req = router_19_0_req_out[4]; - - assign router_19_0_rsp_in[0] = router_19_1_to_router_19_0_rsp; - assign router_19_0_rsp_in[1] = router_20_0_to_router_19_0_rsp; - assign router_19_0_rsp_in[2] = '0; - assign router_19_0_rsp_in[3] = router_18_0_to_router_19_0_rsp; - assign router_19_0_rsp_in[4] = magia_tile_ni_19_0_to_router_19_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_0_req_in), - .floo_rsp_o (router_19_0_rsp_out), - .floo_req_o (router_19_0_req_out), - .floo_rsp_i (router_19_0_rsp_in) -); - - -floo_req_t [4:0] router_19_1_req_in; -floo_rsp_t [4:0] router_19_1_rsp_out; -floo_req_t [4:0] router_19_1_req_out; -floo_rsp_t [4:0] router_19_1_rsp_in; - - assign router_19_1_req_in[0] = router_19_2_to_router_19_1_req; - assign router_19_1_req_in[1] = router_20_1_to_router_19_1_req; - assign router_19_1_req_in[2] = router_19_0_to_router_19_1_req; - assign router_19_1_req_in[3] = router_18_1_to_router_19_1_req; - assign router_19_1_req_in[4] = magia_tile_ni_19_1_to_router_19_1_req; - - assign router_19_1_to_router_19_2_rsp = router_19_1_rsp_out[0]; - assign router_19_1_to_router_20_1_rsp = router_19_1_rsp_out[1]; - assign router_19_1_to_router_19_0_rsp = router_19_1_rsp_out[2]; - assign router_19_1_to_router_18_1_rsp = router_19_1_rsp_out[3]; - assign router_19_1_to_magia_tile_ni_19_1_rsp = router_19_1_rsp_out[4]; - - assign router_19_1_to_router_19_2_req = router_19_1_req_out[0]; - assign router_19_1_to_router_20_1_req = router_19_1_req_out[1]; - assign router_19_1_to_router_19_0_req = router_19_1_req_out[2]; - assign router_19_1_to_router_18_1_req = router_19_1_req_out[3]; - assign router_19_1_to_magia_tile_ni_19_1_req = router_19_1_req_out[4]; - - assign router_19_1_rsp_in[0] = router_19_2_to_router_19_1_rsp; - assign router_19_1_rsp_in[1] = router_20_1_to_router_19_1_rsp; - assign router_19_1_rsp_in[2] = router_19_0_to_router_19_1_rsp; - assign router_19_1_rsp_in[3] = router_18_1_to_router_19_1_rsp; - assign router_19_1_rsp_in[4] = magia_tile_ni_19_1_to_router_19_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_1_req_in), - .floo_rsp_o (router_19_1_rsp_out), - .floo_req_o (router_19_1_req_out), - .floo_rsp_i (router_19_1_rsp_in) -); - - -floo_req_t [4:0] router_19_2_req_in; -floo_rsp_t [4:0] router_19_2_rsp_out; -floo_req_t [4:0] router_19_2_req_out; -floo_rsp_t [4:0] router_19_2_rsp_in; - - assign router_19_2_req_in[0] = router_19_3_to_router_19_2_req; - assign router_19_2_req_in[1] = router_20_2_to_router_19_2_req; - assign router_19_2_req_in[2] = router_19_1_to_router_19_2_req; - assign router_19_2_req_in[3] = router_18_2_to_router_19_2_req; - assign router_19_2_req_in[4] = magia_tile_ni_19_2_to_router_19_2_req; - - assign router_19_2_to_router_19_3_rsp = router_19_2_rsp_out[0]; - assign router_19_2_to_router_20_2_rsp = router_19_2_rsp_out[1]; - assign router_19_2_to_router_19_1_rsp = router_19_2_rsp_out[2]; - assign router_19_2_to_router_18_2_rsp = router_19_2_rsp_out[3]; - assign router_19_2_to_magia_tile_ni_19_2_rsp = router_19_2_rsp_out[4]; - - assign router_19_2_to_router_19_3_req = router_19_2_req_out[0]; - assign router_19_2_to_router_20_2_req = router_19_2_req_out[1]; - assign router_19_2_to_router_19_1_req = router_19_2_req_out[2]; - assign router_19_2_to_router_18_2_req = router_19_2_req_out[3]; - assign router_19_2_to_magia_tile_ni_19_2_req = router_19_2_req_out[4]; - - assign router_19_2_rsp_in[0] = router_19_3_to_router_19_2_rsp; - assign router_19_2_rsp_in[1] = router_20_2_to_router_19_2_rsp; - assign router_19_2_rsp_in[2] = router_19_1_to_router_19_2_rsp; - assign router_19_2_rsp_in[3] = router_18_2_to_router_19_2_rsp; - assign router_19_2_rsp_in[4] = magia_tile_ni_19_2_to_router_19_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_2_req_in), - .floo_rsp_o (router_19_2_rsp_out), - .floo_req_o (router_19_2_req_out), - .floo_rsp_i (router_19_2_rsp_in) -); - - -floo_req_t [4:0] router_19_3_req_in; -floo_rsp_t [4:0] router_19_3_rsp_out; -floo_req_t [4:0] router_19_3_req_out; -floo_rsp_t [4:0] router_19_3_rsp_in; - - assign router_19_3_req_in[0] = router_19_4_to_router_19_3_req; - assign router_19_3_req_in[1] = router_20_3_to_router_19_3_req; - assign router_19_3_req_in[2] = router_19_2_to_router_19_3_req; - assign router_19_3_req_in[3] = router_18_3_to_router_19_3_req; - assign router_19_3_req_in[4] = magia_tile_ni_19_3_to_router_19_3_req; - - assign router_19_3_to_router_19_4_rsp = router_19_3_rsp_out[0]; - assign router_19_3_to_router_20_3_rsp = router_19_3_rsp_out[1]; - assign router_19_3_to_router_19_2_rsp = router_19_3_rsp_out[2]; - assign router_19_3_to_router_18_3_rsp = router_19_3_rsp_out[3]; - assign router_19_3_to_magia_tile_ni_19_3_rsp = router_19_3_rsp_out[4]; - - assign router_19_3_to_router_19_4_req = router_19_3_req_out[0]; - assign router_19_3_to_router_20_3_req = router_19_3_req_out[1]; - assign router_19_3_to_router_19_2_req = router_19_3_req_out[2]; - assign router_19_3_to_router_18_3_req = router_19_3_req_out[3]; - assign router_19_3_to_magia_tile_ni_19_3_req = router_19_3_req_out[4]; - - assign router_19_3_rsp_in[0] = router_19_4_to_router_19_3_rsp; - assign router_19_3_rsp_in[1] = router_20_3_to_router_19_3_rsp; - assign router_19_3_rsp_in[2] = router_19_2_to_router_19_3_rsp; - assign router_19_3_rsp_in[3] = router_18_3_to_router_19_3_rsp; - assign router_19_3_rsp_in[4] = magia_tile_ni_19_3_to_router_19_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_3_req_in), - .floo_rsp_o (router_19_3_rsp_out), - .floo_req_o (router_19_3_req_out), - .floo_rsp_i (router_19_3_rsp_in) -); - - -floo_req_t [4:0] router_19_4_req_in; -floo_rsp_t [4:0] router_19_4_rsp_out; -floo_req_t [4:0] router_19_4_req_out; -floo_rsp_t [4:0] router_19_4_rsp_in; - - assign router_19_4_req_in[0] = router_19_5_to_router_19_4_req; - assign router_19_4_req_in[1] = router_20_4_to_router_19_4_req; - assign router_19_4_req_in[2] = router_19_3_to_router_19_4_req; - assign router_19_4_req_in[3] = router_18_4_to_router_19_4_req; - assign router_19_4_req_in[4] = magia_tile_ni_19_4_to_router_19_4_req; - - assign router_19_4_to_router_19_5_rsp = router_19_4_rsp_out[0]; - assign router_19_4_to_router_20_4_rsp = router_19_4_rsp_out[1]; - assign router_19_4_to_router_19_3_rsp = router_19_4_rsp_out[2]; - assign router_19_4_to_router_18_4_rsp = router_19_4_rsp_out[3]; - assign router_19_4_to_magia_tile_ni_19_4_rsp = router_19_4_rsp_out[4]; - - assign router_19_4_to_router_19_5_req = router_19_4_req_out[0]; - assign router_19_4_to_router_20_4_req = router_19_4_req_out[1]; - assign router_19_4_to_router_19_3_req = router_19_4_req_out[2]; - assign router_19_4_to_router_18_4_req = router_19_4_req_out[3]; - assign router_19_4_to_magia_tile_ni_19_4_req = router_19_4_req_out[4]; - - assign router_19_4_rsp_in[0] = router_19_5_to_router_19_4_rsp; - assign router_19_4_rsp_in[1] = router_20_4_to_router_19_4_rsp; - assign router_19_4_rsp_in[2] = router_19_3_to_router_19_4_rsp; - assign router_19_4_rsp_in[3] = router_18_4_to_router_19_4_rsp; - assign router_19_4_rsp_in[4] = magia_tile_ni_19_4_to_router_19_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_4_req_in), - .floo_rsp_o (router_19_4_rsp_out), - .floo_req_o (router_19_4_req_out), - .floo_rsp_i (router_19_4_rsp_in) -); - - -floo_req_t [4:0] router_19_5_req_in; -floo_rsp_t [4:0] router_19_5_rsp_out; -floo_req_t [4:0] router_19_5_req_out; -floo_rsp_t [4:0] router_19_5_rsp_in; - - assign router_19_5_req_in[0] = router_19_6_to_router_19_5_req; - assign router_19_5_req_in[1] = router_20_5_to_router_19_5_req; - assign router_19_5_req_in[2] = router_19_4_to_router_19_5_req; - assign router_19_5_req_in[3] = router_18_5_to_router_19_5_req; - assign router_19_5_req_in[4] = magia_tile_ni_19_5_to_router_19_5_req; - - assign router_19_5_to_router_19_6_rsp = router_19_5_rsp_out[0]; - assign router_19_5_to_router_20_5_rsp = router_19_5_rsp_out[1]; - assign router_19_5_to_router_19_4_rsp = router_19_5_rsp_out[2]; - assign router_19_5_to_router_18_5_rsp = router_19_5_rsp_out[3]; - assign router_19_5_to_magia_tile_ni_19_5_rsp = router_19_5_rsp_out[4]; - - assign router_19_5_to_router_19_6_req = router_19_5_req_out[0]; - assign router_19_5_to_router_20_5_req = router_19_5_req_out[1]; - assign router_19_5_to_router_19_4_req = router_19_5_req_out[2]; - assign router_19_5_to_router_18_5_req = router_19_5_req_out[3]; - assign router_19_5_to_magia_tile_ni_19_5_req = router_19_5_req_out[4]; - - assign router_19_5_rsp_in[0] = router_19_6_to_router_19_5_rsp; - assign router_19_5_rsp_in[1] = router_20_5_to_router_19_5_rsp; - assign router_19_5_rsp_in[2] = router_19_4_to_router_19_5_rsp; - assign router_19_5_rsp_in[3] = router_18_5_to_router_19_5_rsp; - assign router_19_5_rsp_in[4] = magia_tile_ni_19_5_to_router_19_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_5_req_in), - .floo_rsp_o (router_19_5_rsp_out), - .floo_req_o (router_19_5_req_out), - .floo_rsp_i (router_19_5_rsp_in) -); - - -floo_req_t [4:0] router_19_6_req_in; -floo_rsp_t [4:0] router_19_6_rsp_out; -floo_req_t [4:0] router_19_6_req_out; -floo_rsp_t [4:0] router_19_6_rsp_in; - - assign router_19_6_req_in[0] = router_19_7_to_router_19_6_req; - assign router_19_6_req_in[1] = router_20_6_to_router_19_6_req; - assign router_19_6_req_in[2] = router_19_5_to_router_19_6_req; - assign router_19_6_req_in[3] = router_18_6_to_router_19_6_req; - assign router_19_6_req_in[4] = magia_tile_ni_19_6_to_router_19_6_req; - - assign router_19_6_to_router_19_7_rsp = router_19_6_rsp_out[0]; - assign router_19_6_to_router_20_6_rsp = router_19_6_rsp_out[1]; - assign router_19_6_to_router_19_5_rsp = router_19_6_rsp_out[2]; - assign router_19_6_to_router_18_6_rsp = router_19_6_rsp_out[3]; - assign router_19_6_to_magia_tile_ni_19_6_rsp = router_19_6_rsp_out[4]; - - assign router_19_6_to_router_19_7_req = router_19_6_req_out[0]; - assign router_19_6_to_router_20_6_req = router_19_6_req_out[1]; - assign router_19_6_to_router_19_5_req = router_19_6_req_out[2]; - assign router_19_6_to_router_18_6_req = router_19_6_req_out[3]; - assign router_19_6_to_magia_tile_ni_19_6_req = router_19_6_req_out[4]; - - assign router_19_6_rsp_in[0] = router_19_7_to_router_19_6_rsp; - assign router_19_6_rsp_in[1] = router_20_6_to_router_19_6_rsp; - assign router_19_6_rsp_in[2] = router_19_5_to_router_19_6_rsp; - assign router_19_6_rsp_in[3] = router_18_6_to_router_19_6_rsp; - assign router_19_6_rsp_in[4] = magia_tile_ni_19_6_to_router_19_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_6_req_in), - .floo_rsp_o (router_19_6_rsp_out), - .floo_req_o (router_19_6_req_out), - .floo_rsp_i (router_19_6_rsp_in) -); - - -floo_req_t [4:0] router_19_7_req_in; -floo_rsp_t [4:0] router_19_7_rsp_out; -floo_req_t [4:0] router_19_7_req_out; -floo_rsp_t [4:0] router_19_7_rsp_in; - - assign router_19_7_req_in[0] = router_19_8_to_router_19_7_req; - assign router_19_7_req_in[1] = router_20_7_to_router_19_7_req; - assign router_19_7_req_in[2] = router_19_6_to_router_19_7_req; - assign router_19_7_req_in[3] = router_18_7_to_router_19_7_req; - assign router_19_7_req_in[4] = magia_tile_ni_19_7_to_router_19_7_req; - - assign router_19_7_to_router_19_8_rsp = router_19_7_rsp_out[0]; - assign router_19_7_to_router_20_7_rsp = router_19_7_rsp_out[1]; - assign router_19_7_to_router_19_6_rsp = router_19_7_rsp_out[2]; - assign router_19_7_to_router_18_7_rsp = router_19_7_rsp_out[3]; - assign router_19_7_to_magia_tile_ni_19_7_rsp = router_19_7_rsp_out[4]; - - assign router_19_7_to_router_19_8_req = router_19_7_req_out[0]; - assign router_19_7_to_router_20_7_req = router_19_7_req_out[1]; - assign router_19_7_to_router_19_6_req = router_19_7_req_out[2]; - assign router_19_7_to_router_18_7_req = router_19_7_req_out[3]; - assign router_19_7_to_magia_tile_ni_19_7_req = router_19_7_req_out[4]; - - assign router_19_7_rsp_in[0] = router_19_8_to_router_19_7_rsp; - assign router_19_7_rsp_in[1] = router_20_7_to_router_19_7_rsp; - assign router_19_7_rsp_in[2] = router_19_6_to_router_19_7_rsp; - assign router_19_7_rsp_in[3] = router_18_7_to_router_19_7_rsp; - assign router_19_7_rsp_in[4] = magia_tile_ni_19_7_to_router_19_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_7_req_in), - .floo_rsp_o (router_19_7_rsp_out), - .floo_req_o (router_19_7_req_out), - .floo_rsp_i (router_19_7_rsp_in) -); - - -floo_req_t [4:0] router_19_8_req_in; -floo_rsp_t [4:0] router_19_8_rsp_out; -floo_req_t [4:0] router_19_8_req_out; -floo_rsp_t [4:0] router_19_8_rsp_in; - - assign router_19_8_req_in[0] = router_19_9_to_router_19_8_req; - assign router_19_8_req_in[1] = router_20_8_to_router_19_8_req; - assign router_19_8_req_in[2] = router_19_7_to_router_19_8_req; - assign router_19_8_req_in[3] = router_18_8_to_router_19_8_req; - assign router_19_8_req_in[4] = magia_tile_ni_19_8_to_router_19_8_req; - - assign router_19_8_to_router_19_9_rsp = router_19_8_rsp_out[0]; - assign router_19_8_to_router_20_8_rsp = router_19_8_rsp_out[1]; - assign router_19_8_to_router_19_7_rsp = router_19_8_rsp_out[2]; - assign router_19_8_to_router_18_8_rsp = router_19_8_rsp_out[3]; - assign router_19_8_to_magia_tile_ni_19_8_rsp = router_19_8_rsp_out[4]; - - assign router_19_8_to_router_19_9_req = router_19_8_req_out[0]; - assign router_19_8_to_router_20_8_req = router_19_8_req_out[1]; - assign router_19_8_to_router_19_7_req = router_19_8_req_out[2]; - assign router_19_8_to_router_18_8_req = router_19_8_req_out[3]; - assign router_19_8_to_magia_tile_ni_19_8_req = router_19_8_req_out[4]; - - assign router_19_8_rsp_in[0] = router_19_9_to_router_19_8_rsp; - assign router_19_8_rsp_in[1] = router_20_8_to_router_19_8_rsp; - assign router_19_8_rsp_in[2] = router_19_7_to_router_19_8_rsp; - assign router_19_8_rsp_in[3] = router_18_8_to_router_19_8_rsp; - assign router_19_8_rsp_in[4] = magia_tile_ni_19_8_to_router_19_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_8_req_in), - .floo_rsp_o (router_19_8_rsp_out), - .floo_req_o (router_19_8_req_out), - .floo_rsp_i (router_19_8_rsp_in) -); - - -floo_req_t [4:0] router_19_9_req_in; -floo_rsp_t [4:0] router_19_9_rsp_out; -floo_req_t [4:0] router_19_9_req_out; -floo_rsp_t [4:0] router_19_9_rsp_in; - - assign router_19_9_req_in[0] = router_19_10_to_router_19_9_req; - assign router_19_9_req_in[1] = router_20_9_to_router_19_9_req; - assign router_19_9_req_in[2] = router_19_8_to_router_19_9_req; - assign router_19_9_req_in[3] = router_18_9_to_router_19_9_req; - assign router_19_9_req_in[4] = magia_tile_ni_19_9_to_router_19_9_req; - - assign router_19_9_to_router_19_10_rsp = router_19_9_rsp_out[0]; - assign router_19_9_to_router_20_9_rsp = router_19_9_rsp_out[1]; - assign router_19_9_to_router_19_8_rsp = router_19_9_rsp_out[2]; - assign router_19_9_to_router_18_9_rsp = router_19_9_rsp_out[3]; - assign router_19_9_to_magia_tile_ni_19_9_rsp = router_19_9_rsp_out[4]; - - assign router_19_9_to_router_19_10_req = router_19_9_req_out[0]; - assign router_19_9_to_router_20_9_req = router_19_9_req_out[1]; - assign router_19_9_to_router_19_8_req = router_19_9_req_out[2]; - assign router_19_9_to_router_18_9_req = router_19_9_req_out[3]; - assign router_19_9_to_magia_tile_ni_19_9_req = router_19_9_req_out[4]; - - assign router_19_9_rsp_in[0] = router_19_10_to_router_19_9_rsp; - assign router_19_9_rsp_in[1] = router_20_9_to_router_19_9_rsp; - assign router_19_9_rsp_in[2] = router_19_8_to_router_19_9_rsp; - assign router_19_9_rsp_in[3] = router_18_9_to_router_19_9_rsp; - assign router_19_9_rsp_in[4] = magia_tile_ni_19_9_to_router_19_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_9_req_in), - .floo_rsp_o (router_19_9_rsp_out), - .floo_req_o (router_19_9_req_out), - .floo_rsp_i (router_19_9_rsp_in) -); - - -floo_req_t [4:0] router_19_10_req_in; -floo_rsp_t [4:0] router_19_10_rsp_out; -floo_req_t [4:0] router_19_10_req_out; -floo_rsp_t [4:0] router_19_10_rsp_in; - - assign router_19_10_req_in[0] = router_19_11_to_router_19_10_req; - assign router_19_10_req_in[1] = router_20_10_to_router_19_10_req; - assign router_19_10_req_in[2] = router_19_9_to_router_19_10_req; - assign router_19_10_req_in[3] = router_18_10_to_router_19_10_req; - assign router_19_10_req_in[4] = magia_tile_ni_19_10_to_router_19_10_req; - - assign router_19_10_to_router_19_11_rsp = router_19_10_rsp_out[0]; - assign router_19_10_to_router_20_10_rsp = router_19_10_rsp_out[1]; - assign router_19_10_to_router_19_9_rsp = router_19_10_rsp_out[2]; - assign router_19_10_to_router_18_10_rsp = router_19_10_rsp_out[3]; - assign router_19_10_to_magia_tile_ni_19_10_rsp = router_19_10_rsp_out[4]; - - assign router_19_10_to_router_19_11_req = router_19_10_req_out[0]; - assign router_19_10_to_router_20_10_req = router_19_10_req_out[1]; - assign router_19_10_to_router_19_9_req = router_19_10_req_out[2]; - assign router_19_10_to_router_18_10_req = router_19_10_req_out[3]; - assign router_19_10_to_magia_tile_ni_19_10_req = router_19_10_req_out[4]; - - assign router_19_10_rsp_in[0] = router_19_11_to_router_19_10_rsp; - assign router_19_10_rsp_in[1] = router_20_10_to_router_19_10_rsp; - assign router_19_10_rsp_in[2] = router_19_9_to_router_19_10_rsp; - assign router_19_10_rsp_in[3] = router_18_10_to_router_19_10_rsp; - assign router_19_10_rsp_in[4] = magia_tile_ni_19_10_to_router_19_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_10_req_in), - .floo_rsp_o (router_19_10_rsp_out), - .floo_req_o (router_19_10_req_out), - .floo_rsp_i (router_19_10_rsp_in) -); - - -floo_req_t [4:0] router_19_11_req_in; -floo_rsp_t [4:0] router_19_11_rsp_out; -floo_req_t [4:0] router_19_11_req_out; -floo_rsp_t [4:0] router_19_11_rsp_in; - - assign router_19_11_req_in[0] = router_19_12_to_router_19_11_req; - assign router_19_11_req_in[1] = router_20_11_to_router_19_11_req; - assign router_19_11_req_in[2] = router_19_10_to_router_19_11_req; - assign router_19_11_req_in[3] = router_18_11_to_router_19_11_req; - assign router_19_11_req_in[4] = magia_tile_ni_19_11_to_router_19_11_req; - - assign router_19_11_to_router_19_12_rsp = router_19_11_rsp_out[0]; - assign router_19_11_to_router_20_11_rsp = router_19_11_rsp_out[1]; - assign router_19_11_to_router_19_10_rsp = router_19_11_rsp_out[2]; - assign router_19_11_to_router_18_11_rsp = router_19_11_rsp_out[3]; - assign router_19_11_to_magia_tile_ni_19_11_rsp = router_19_11_rsp_out[4]; - - assign router_19_11_to_router_19_12_req = router_19_11_req_out[0]; - assign router_19_11_to_router_20_11_req = router_19_11_req_out[1]; - assign router_19_11_to_router_19_10_req = router_19_11_req_out[2]; - assign router_19_11_to_router_18_11_req = router_19_11_req_out[3]; - assign router_19_11_to_magia_tile_ni_19_11_req = router_19_11_req_out[4]; - - assign router_19_11_rsp_in[0] = router_19_12_to_router_19_11_rsp; - assign router_19_11_rsp_in[1] = router_20_11_to_router_19_11_rsp; - assign router_19_11_rsp_in[2] = router_19_10_to_router_19_11_rsp; - assign router_19_11_rsp_in[3] = router_18_11_to_router_19_11_rsp; - assign router_19_11_rsp_in[4] = magia_tile_ni_19_11_to_router_19_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_11_req_in), - .floo_rsp_o (router_19_11_rsp_out), - .floo_req_o (router_19_11_req_out), - .floo_rsp_i (router_19_11_rsp_in) -); - - -floo_req_t [4:0] router_19_12_req_in; -floo_rsp_t [4:0] router_19_12_rsp_out; -floo_req_t [4:0] router_19_12_req_out; -floo_rsp_t [4:0] router_19_12_rsp_in; - - assign router_19_12_req_in[0] = router_19_13_to_router_19_12_req; - assign router_19_12_req_in[1] = router_20_12_to_router_19_12_req; - assign router_19_12_req_in[2] = router_19_11_to_router_19_12_req; - assign router_19_12_req_in[3] = router_18_12_to_router_19_12_req; - assign router_19_12_req_in[4] = magia_tile_ni_19_12_to_router_19_12_req; - - assign router_19_12_to_router_19_13_rsp = router_19_12_rsp_out[0]; - assign router_19_12_to_router_20_12_rsp = router_19_12_rsp_out[1]; - assign router_19_12_to_router_19_11_rsp = router_19_12_rsp_out[2]; - assign router_19_12_to_router_18_12_rsp = router_19_12_rsp_out[3]; - assign router_19_12_to_magia_tile_ni_19_12_rsp = router_19_12_rsp_out[4]; - - assign router_19_12_to_router_19_13_req = router_19_12_req_out[0]; - assign router_19_12_to_router_20_12_req = router_19_12_req_out[1]; - assign router_19_12_to_router_19_11_req = router_19_12_req_out[2]; - assign router_19_12_to_router_18_12_req = router_19_12_req_out[3]; - assign router_19_12_to_magia_tile_ni_19_12_req = router_19_12_req_out[4]; - - assign router_19_12_rsp_in[0] = router_19_13_to_router_19_12_rsp; - assign router_19_12_rsp_in[1] = router_20_12_to_router_19_12_rsp; - assign router_19_12_rsp_in[2] = router_19_11_to_router_19_12_rsp; - assign router_19_12_rsp_in[3] = router_18_12_to_router_19_12_rsp; - assign router_19_12_rsp_in[4] = magia_tile_ni_19_12_to_router_19_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_12_req_in), - .floo_rsp_o (router_19_12_rsp_out), - .floo_req_o (router_19_12_req_out), - .floo_rsp_i (router_19_12_rsp_in) -); - - -floo_req_t [4:0] router_19_13_req_in; -floo_rsp_t [4:0] router_19_13_rsp_out; -floo_req_t [4:0] router_19_13_req_out; -floo_rsp_t [4:0] router_19_13_rsp_in; - - assign router_19_13_req_in[0] = router_19_14_to_router_19_13_req; - assign router_19_13_req_in[1] = router_20_13_to_router_19_13_req; - assign router_19_13_req_in[2] = router_19_12_to_router_19_13_req; - assign router_19_13_req_in[3] = router_18_13_to_router_19_13_req; - assign router_19_13_req_in[4] = magia_tile_ni_19_13_to_router_19_13_req; - - assign router_19_13_to_router_19_14_rsp = router_19_13_rsp_out[0]; - assign router_19_13_to_router_20_13_rsp = router_19_13_rsp_out[1]; - assign router_19_13_to_router_19_12_rsp = router_19_13_rsp_out[2]; - assign router_19_13_to_router_18_13_rsp = router_19_13_rsp_out[3]; - assign router_19_13_to_magia_tile_ni_19_13_rsp = router_19_13_rsp_out[4]; - - assign router_19_13_to_router_19_14_req = router_19_13_req_out[0]; - assign router_19_13_to_router_20_13_req = router_19_13_req_out[1]; - assign router_19_13_to_router_19_12_req = router_19_13_req_out[2]; - assign router_19_13_to_router_18_13_req = router_19_13_req_out[3]; - assign router_19_13_to_magia_tile_ni_19_13_req = router_19_13_req_out[4]; - - assign router_19_13_rsp_in[0] = router_19_14_to_router_19_13_rsp; - assign router_19_13_rsp_in[1] = router_20_13_to_router_19_13_rsp; - assign router_19_13_rsp_in[2] = router_19_12_to_router_19_13_rsp; - assign router_19_13_rsp_in[3] = router_18_13_to_router_19_13_rsp; - assign router_19_13_rsp_in[4] = magia_tile_ni_19_13_to_router_19_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_13_req_in), - .floo_rsp_o (router_19_13_rsp_out), - .floo_req_o (router_19_13_req_out), - .floo_rsp_i (router_19_13_rsp_in) -); - - -floo_req_t [4:0] router_19_14_req_in; -floo_rsp_t [4:0] router_19_14_rsp_out; -floo_req_t [4:0] router_19_14_req_out; -floo_rsp_t [4:0] router_19_14_rsp_in; - - assign router_19_14_req_in[0] = router_19_15_to_router_19_14_req; - assign router_19_14_req_in[1] = router_20_14_to_router_19_14_req; - assign router_19_14_req_in[2] = router_19_13_to_router_19_14_req; - assign router_19_14_req_in[3] = router_18_14_to_router_19_14_req; - assign router_19_14_req_in[4] = magia_tile_ni_19_14_to_router_19_14_req; - - assign router_19_14_to_router_19_15_rsp = router_19_14_rsp_out[0]; - assign router_19_14_to_router_20_14_rsp = router_19_14_rsp_out[1]; - assign router_19_14_to_router_19_13_rsp = router_19_14_rsp_out[2]; - assign router_19_14_to_router_18_14_rsp = router_19_14_rsp_out[3]; - assign router_19_14_to_magia_tile_ni_19_14_rsp = router_19_14_rsp_out[4]; - - assign router_19_14_to_router_19_15_req = router_19_14_req_out[0]; - assign router_19_14_to_router_20_14_req = router_19_14_req_out[1]; - assign router_19_14_to_router_19_13_req = router_19_14_req_out[2]; - assign router_19_14_to_router_18_14_req = router_19_14_req_out[3]; - assign router_19_14_to_magia_tile_ni_19_14_req = router_19_14_req_out[4]; - - assign router_19_14_rsp_in[0] = router_19_15_to_router_19_14_rsp; - assign router_19_14_rsp_in[1] = router_20_14_to_router_19_14_rsp; - assign router_19_14_rsp_in[2] = router_19_13_to_router_19_14_rsp; - assign router_19_14_rsp_in[3] = router_18_14_to_router_19_14_rsp; - assign router_19_14_rsp_in[4] = magia_tile_ni_19_14_to_router_19_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_14_req_in), - .floo_rsp_o (router_19_14_rsp_out), - .floo_req_o (router_19_14_req_out), - .floo_rsp_i (router_19_14_rsp_in) -); - - -floo_req_t [4:0] router_19_15_req_in; -floo_rsp_t [4:0] router_19_15_rsp_out; -floo_req_t [4:0] router_19_15_req_out; -floo_rsp_t [4:0] router_19_15_rsp_in; - - assign router_19_15_req_in[0] = router_19_16_to_router_19_15_req; - assign router_19_15_req_in[1] = router_20_15_to_router_19_15_req; - assign router_19_15_req_in[2] = router_19_14_to_router_19_15_req; - assign router_19_15_req_in[3] = router_18_15_to_router_19_15_req; - assign router_19_15_req_in[4] = magia_tile_ni_19_15_to_router_19_15_req; - - assign router_19_15_to_router_19_16_rsp = router_19_15_rsp_out[0]; - assign router_19_15_to_router_20_15_rsp = router_19_15_rsp_out[1]; - assign router_19_15_to_router_19_14_rsp = router_19_15_rsp_out[2]; - assign router_19_15_to_router_18_15_rsp = router_19_15_rsp_out[3]; - assign router_19_15_to_magia_tile_ni_19_15_rsp = router_19_15_rsp_out[4]; - - assign router_19_15_to_router_19_16_req = router_19_15_req_out[0]; - assign router_19_15_to_router_20_15_req = router_19_15_req_out[1]; - assign router_19_15_to_router_19_14_req = router_19_15_req_out[2]; - assign router_19_15_to_router_18_15_req = router_19_15_req_out[3]; - assign router_19_15_to_magia_tile_ni_19_15_req = router_19_15_req_out[4]; - - assign router_19_15_rsp_in[0] = router_19_16_to_router_19_15_rsp; - assign router_19_15_rsp_in[1] = router_20_15_to_router_19_15_rsp; - assign router_19_15_rsp_in[2] = router_19_14_to_router_19_15_rsp; - assign router_19_15_rsp_in[3] = router_18_15_to_router_19_15_rsp; - assign router_19_15_rsp_in[4] = magia_tile_ni_19_15_to_router_19_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_15_req_in), - .floo_rsp_o (router_19_15_rsp_out), - .floo_req_o (router_19_15_req_out), - .floo_rsp_i (router_19_15_rsp_in) -); - - -floo_req_t [4:0] router_19_16_req_in; -floo_rsp_t [4:0] router_19_16_rsp_out; -floo_req_t [4:0] router_19_16_req_out; -floo_rsp_t [4:0] router_19_16_rsp_in; - - assign router_19_16_req_in[0] = router_19_17_to_router_19_16_req; - assign router_19_16_req_in[1] = router_20_16_to_router_19_16_req; - assign router_19_16_req_in[2] = router_19_15_to_router_19_16_req; - assign router_19_16_req_in[3] = router_18_16_to_router_19_16_req; - assign router_19_16_req_in[4] = magia_tile_ni_19_16_to_router_19_16_req; - - assign router_19_16_to_router_19_17_rsp = router_19_16_rsp_out[0]; - assign router_19_16_to_router_20_16_rsp = router_19_16_rsp_out[1]; - assign router_19_16_to_router_19_15_rsp = router_19_16_rsp_out[2]; - assign router_19_16_to_router_18_16_rsp = router_19_16_rsp_out[3]; - assign router_19_16_to_magia_tile_ni_19_16_rsp = router_19_16_rsp_out[4]; - - assign router_19_16_to_router_19_17_req = router_19_16_req_out[0]; - assign router_19_16_to_router_20_16_req = router_19_16_req_out[1]; - assign router_19_16_to_router_19_15_req = router_19_16_req_out[2]; - assign router_19_16_to_router_18_16_req = router_19_16_req_out[3]; - assign router_19_16_to_magia_tile_ni_19_16_req = router_19_16_req_out[4]; - - assign router_19_16_rsp_in[0] = router_19_17_to_router_19_16_rsp; - assign router_19_16_rsp_in[1] = router_20_16_to_router_19_16_rsp; - assign router_19_16_rsp_in[2] = router_19_15_to_router_19_16_rsp; - assign router_19_16_rsp_in[3] = router_18_16_to_router_19_16_rsp; - assign router_19_16_rsp_in[4] = magia_tile_ni_19_16_to_router_19_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_16_req_in), - .floo_rsp_o (router_19_16_rsp_out), - .floo_req_o (router_19_16_req_out), - .floo_rsp_i (router_19_16_rsp_in) -); - - -floo_req_t [4:0] router_19_17_req_in; -floo_rsp_t [4:0] router_19_17_rsp_out; -floo_req_t [4:0] router_19_17_req_out; -floo_rsp_t [4:0] router_19_17_rsp_in; - - assign router_19_17_req_in[0] = router_19_18_to_router_19_17_req; - assign router_19_17_req_in[1] = router_20_17_to_router_19_17_req; - assign router_19_17_req_in[2] = router_19_16_to_router_19_17_req; - assign router_19_17_req_in[3] = router_18_17_to_router_19_17_req; - assign router_19_17_req_in[4] = magia_tile_ni_19_17_to_router_19_17_req; - - assign router_19_17_to_router_19_18_rsp = router_19_17_rsp_out[0]; - assign router_19_17_to_router_20_17_rsp = router_19_17_rsp_out[1]; - assign router_19_17_to_router_19_16_rsp = router_19_17_rsp_out[2]; - assign router_19_17_to_router_18_17_rsp = router_19_17_rsp_out[3]; - assign router_19_17_to_magia_tile_ni_19_17_rsp = router_19_17_rsp_out[4]; - - assign router_19_17_to_router_19_18_req = router_19_17_req_out[0]; - assign router_19_17_to_router_20_17_req = router_19_17_req_out[1]; - assign router_19_17_to_router_19_16_req = router_19_17_req_out[2]; - assign router_19_17_to_router_18_17_req = router_19_17_req_out[3]; - assign router_19_17_to_magia_tile_ni_19_17_req = router_19_17_req_out[4]; - - assign router_19_17_rsp_in[0] = router_19_18_to_router_19_17_rsp; - assign router_19_17_rsp_in[1] = router_20_17_to_router_19_17_rsp; - assign router_19_17_rsp_in[2] = router_19_16_to_router_19_17_rsp; - assign router_19_17_rsp_in[3] = router_18_17_to_router_19_17_rsp; - assign router_19_17_rsp_in[4] = magia_tile_ni_19_17_to_router_19_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_17_req_in), - .floo_rsp_o (router_19_17_rsp_out), - .floo_req_o (router_19_17_req_out), - .floo_rsp_i (router_19_17_rsp_in) -); - - -floo_req_t [4:0] router_19_18_req_in; -floo_rsp_t [4:0] router_19_18_rsp_out; -floo_req_t [4:0] router_19_18_req_out; -floo_rsp_t [4:0] router_19_18_rsp_in; - - assign router_19_18_req_in[0] = router_19_19_to_router_19_18_req; - assign router_19_18_req_in[1] = router_20_18_to_router_19_18_req; - assign router_19_18_req_in[2] = router_19_17_to_router_19_18_req; - assign router_19_18_req_in[3] = router_18_18_to_router_19_18_req; - assign router_19_18_req_in[4] = magia_tile_ni_19_18_to_router_19_18_req; - - assign router_19_18_to_router_19_19_rsp = router_19_18_rsp_out[0]; - assign router_19_18_to_router_20_18_rsp = router_19_18_rsp_out[1]; - assign router_19_18_to_router_19_17_rsp = router_19_18_rsp_out[2]; - assign router_19_18_to_router_18_18_rsp = router_19_18_rsp_out[3]; - assign router_19_18_to_magia_tile_ni_19_18_rsp = router_19_18_rsp_out[4]; - - assign router_19_18_to_router_19_19_req = router_19_18_req_out[0]; - assign router_19_18_to_router_20_18_req = router_19_18_req_out[1]; - assign router_19_18_to_router_19_17_req = router_19_18_req_out[2]; - assign router_19_18_to_router_18_18_req = router_19_18_req_out[3]; - assign router_19_18_to_magia_tile_ni_19_18_req = router_19_18_req_out[4]; - - assign router_19_18_rsp_in[0] = router_19_19_to_router_19_18_rsp; - assign router_19_18_rsp_in[1] = router_20_18_to_router_19_18_rsp; - assign router_19_18_rsp_in[2] = router_19_17_to_router_19_18_rsp; - assign router_19_18_rsp_in[3] = router_18_18_to_router_19_18_rsp; - assign router_19_18_rsp_in[4] = magia_tile_ni_19_18_to_router_19_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_18_req_in), - .floo_rsp_o (router_19_18_rsp_out), - .floo_req_o (router_19_18_req_out), - .floo_rsp_i (router_19_18_rsp_in) -); - - -floo_req_t [4:0] router_19_19_req_in; -floo_rsp_t [4:0] router_19_19_rsp_out; -floo_req_t [4:0] router_19_19_req_out; -floo_rsp_t [4:0] router_19_19_rsp_in; - - assign router_19_19_req_in[0] = router_19_20_to_router_19_19_req; - assign router_19_19_req_in[1] = router_20_19_to_router_19_19_req; - assign router_19_19_req_in[2] = router_19_18_to_router_19_19_req; - assign router_19_19_req_in[3] = router_18_19_to_router_19_19_req; - assign router_19_19_req_in[4] = magia_tile_ni_19_19_to_router_19_19_req; - - assign router_19_19_to_router_19_20_rsp = router_19_19_rsp_out[0]; - assign router_19_19_to_router_20_19_rsp = router_19_19_rsp_out[1]; - assign router_19_19_to_router_19_18_rsp = router_19_19_rsp_out[2]; - assign router_19_19_to_router_18_19_rsp = router_19_19_rsp_out[3]; - assign router_19_19_to_magia_tile_ni_19_19_rsp = router_19_19_rsp_out[4]; - - assign router_19_19_to_router_19_20_req = router_19_19_req_out[0]; - assign router_19_19_to_router_20_19_req = router_19_19_req_out[1]; - assign router_19_19_to_router_19_18_req = router_19_19_req_out[2]; - assign router_19_19_to_router_18_19_req = router_19_19_req_out[3]; - assign router_19_19_to_magia_tile_ni_19_19_req = router_19_19_req_out[4]; - - assign router_19_19_rsp_in[0] = router_19_20_to_router_19_19_rsp; - assign router_19_19_rsp_in[1] = router_20_19_to_router_19_19_rsp; - assign router_19_19_rsp_in[2] = router_19_18_to_router_19_19_rsp; - assign router_19_19_rsp_in[3] = router_18_19_to_router_19_19_rsp; - assign router_19_19_rsp_in[4] = magia_tile_ni_19_19_to_router_19_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_19_req_in), - .floo_rsp_o (router_19_19_rsp_out), - .floo_req_o (router_19_19_req_out), - .floo_rsp_i (router_19_19_rsp_in) -); - - -floo_req_t [4:0] router_19_20_req_in; -floo_rsp_t [4:0] router_19_20_rsp_out; -floo_req_t [4:0] router_19_20_req_out; -floo_rsp_t [4:0] router_19_20_rsp_in; - - assign router_19_20_req_in[0] = router_19_21_to_router_19_20_req; - assign router_19_20_req_in[1] = router_20_20_to_router_19_20_req; - assign router_19_20_req_in[2] = router_19_19_to_router_19_20_req; - assign router_19_20_req_in[3] = router_18_20_to_router_19_20_req; - assign router_19_20_req_in[4] = magia_tile_ni_19_20_to_router_19_20_req; - - assign router_19_20_to_router_19_21_rsp = router_19_20_rsp_out[0]; - assign router_19_20_to_router_20_20_rsp = router_19_20_rsp_out[1]; - assign router_19_20_to_router_19_19_rsp = router_19_20_rsp_out[2]; - assign router_19_20_to_router_18_20_rsp = router_19_20_rsp_out[3]; - assign router_19_20_to_magia_tile_ni_19_20_rsp = router_19_20_rsp_out[4]; - - assign router_19_20_to_router_19_21_req = router_19_20_req_out[0]; - assign router_19_20_to_router_20_20_req = router_19_20_req_out[1]; - assign router_19_20_to_router_19_19_req = router_19_20_req_out[2]; - assign router_19_20_to_router_18_20_req = router_19_20_req_out[3]; - assign router_19_20_to_magia_tile_ni_19_20_req = router_19_20_req_out[4]; - - assign router_19_20_rsp_in[0] = router_19_21_to_router_19_20_rsp; - assign router_19_20_rsp_in[1] = router_20_20_to_router_19_20_rsp; - assign router_19_20_rsp_in[2] = router_19_19_to_router_19_20_rsp; - assign router_19_20_rsp_in[3] = router_18_20_to_router_19_20_rsp; - assign router_19_20_rsp_in[4] = magia_tile_ni_19_20_to_router_19_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_20_req_in), - .floo_rsp_o (router_19_20_rsp_out), - .floo_req_o (router_19_20_req_out), - .floo_rsp_i (router_19_20_rsp_in) -); - - -floo_req_t [4:0] router_19_21_req_in; -floo_rsp_t [4:0] router_19_21_rsp_out; -floo_req_t [4:0] router_19_21_req_out; -floo_rsp_t [4:0] router_19_21_rsp_in; - - assign router_19_21_req_in[0] = router_19_22_to_router_19_21_req; - assign router_19_21_req_in[1] = router_20_21_to_router_19_21_req; - assign router_19_21_req_in[2] = router_19_20_to_router_19_21_req; - assign router_19_21_req_in[3] = router_18_21_to_router_19_21_req; - assign router_19_21_req_in[4] = magia_tile_ni_19_21_to_router_19_21_req; - - assign router_19_21_to_router_19_22_rsp = router_19_21_rsp_out[0]; - assign router_19_21_to_router_20_21_rsp = router_19_21_rsp_out[1]; - assign router_19_21_to_router_19_20_rsp = router_19_21_rsp_out[2]; - assign router_19_21_to_router_18_21_rsp = router_19_21_rsp_out[3]; - assign router_19_21_to_magia_tile_ni_19_21_rsp = router_19_21_rsp_out[4]; - - assign router_19_21_to_router_19_22_req = router_19_21_req_out[0]; - assign router_19_21_to_router_20_21_req = router_19_21_req_out[1]; - assign router_19_21_to_router_19_20_req = router_19_21_req_out[2]; - assign router_19_21_to_router_18_21_req = router_19_21_req_out[3]; - assign router_19_21_to_magia_tile_ni_19_21_req = router_19_21_req_out[4]; - - assign router_19_21_rsp_in[0] = router_19_22_to_router_19_21_rsp; - assign router_19_21_rsp_in[1] = router_20_21_to_router_19_21_rsp; - assign router_19_21_rsp_in[2] = router_19_20_to_router_19_21_rsp; - assign router_19_21_rsp_in[3] = router_18_21_to_router_19_21_rsp; - assign router_19_21_rsp_in[4] = magia_tile_ni_19_21_to_router_19_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_21_req_in), - .floo_rsp_o (router_19_21_rsp_out), - .floo_req_o (router_19_21_req_out), - .floo_rsp_i (router_19_21_rsp_in) -); - - -floo_req_t [4:0] router_19_22_req_in; -floo_rsp_t [4:0] router_19_22_rsp_out; -floo_req_t [4:0] router_19_22_req_out; -floo_rsp_t [4:0] router_19_22_rsp_in; - - assign router_19_22_req_in[0] = router_19_23_to_router_19_22_req; - assign router_19_22_req_in[1] = router_20_22_to_router_19_22_req; - assign router_19_22_req_in[2] = router_19_21_to_router_19_22_req; - assign router_19_22_req_in[3] = router_18_22_to_router_19_22_req; - assign router_19_22_req_in[4] = magia_tile_ni_19_22_to_router_19_22_req; - - assign router_19_22_to_router_19_23_rsp = router_19_22_rsp_out[0]; - assign router_19_22_to_router_20_22_rsp = router_19_22_rsp_out[1]; - assign router_19_22_to_router_19_21_rsp = router_19_22_rsp_out[2]; - assign router_19_22_to_router_18_22_rsp = router_19_22_rsp_out[3]; - assign router_19_22_to_magia_tile_ni_19_22_rsp = router_19_22_rsp_out[4]; - - assign router_19_22_to_router_19_23_req = router_19_22_req_out[0]; - assign router_19_22_to_router_20_22_req = router_19_22_req_out[1]; - assign router_19_22_to_router_19_21_req = router_19_22_req_out[2]; - assign router_19_22_to_router_18_22_req = router_19_22_req_out[3]; - assign router_19_22_to_magia_tile_ni_19_22_req = router_19_22_req_out[4]; - - assign router_19_22_rsp_in[0] = router_19_23_to_router_19_22_rsp; - assign router_19_22_rsp_in[1] = router_20_22_to_router_19_22_rsp; - assign router_19_22_rsp_in[2] = router_19_21_to_router_19_22_rsp; - assign router_19_22_rsp_in[3] = router_18_22_to_router_19_22_rsp; - assign router_19_22_rsp_in[4] = magia_tile_ni_19_22_to_router_19_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_22_req_in), - .floo_rsp_o (router_19_22_rsp_out), - .floo_req_o (router_19_22_req_out), - .floo_rsp_i (router_19_22_rsp_in) -); - - -floo_req_t [4:0] router_19_23_req_in; -floo_rsp_t [4:0] router_19_23_rsp_out; -floo_req_t [4:0] router_19_23_req_out; -floo_rsp_t [4:0] router_19_23_rsp_in; - - assign router_19_23_req_in[0] = router_19_24_to_router_19_23_req; - assign router_19_23_req_in[1] = router_20_23_to_router_19_23_req; - assign router_19_23_req_in[2] = router_19_22_to_router_19_23_req; - assign router_19_23_req_in[3] = router_18_23_to_router_19_23_req; - assign router_19_23_req_in[4] = magia_tile_ni_19_23_to_router_19_23_req; - - assign router_19_23_to_router_19_24_rsp = router_19_23_rsp_out[0]; - assign router_19_23_to_router_20_23_rsp = router_19_23_rsp_out[1]; - assign router_19_23_to_router_19_22_rsp = router_19_23_rsp_out[2]; - assign router_19_23_to_router_18_23_rsp = router_19_23_rsp_out[3]; - assign router_19_23_to_magia_tile_ni_19_23_rsp = router_19_23_rsp_out[4]; - - assign router_19_23_to_router_19_24_req = router_19_23_req_out[0]; - assign router_19_23_to_router_20_23_req = router_19_23_req_out[1]; - assign router_19_23_to_router_19_22_req = router_19_23_req_out[2]; - assign router_19_23_to_router_18_23_req = router_19_23_req_out[3]; - assign router_19_23_to_magia_tile_ni_19_23_req = router_19_23_req_out[4]; - - assign router_19_23_rsp_in[0] = router_19_24_to_router_19_23_rsp; - assign router_19_23_rsp_in[1] = router_20_23_to_router_19_23_rsp; - assign router_19_23_rsp_in[2] = router_19_22_to_router_19_23_rsp; - assign router_19_23_rsp_in[3] = router_18_23_to_router_19_23_rsp; - assign router_19_23_rsp_in[4] = magia_tile_ni_19_23_to_router_19_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_23_req_in), - .floo_rsp_o (router_19_23_rsp_out), - .floo_req_o (router_19_23_req_out), - .floo_rsp_i (router_19_23_rsp_in) -); - - -floo_req_t [4:0] router_19_24_req_in; -floo_rsp_t [4:0] router_19_24_rsp_out; -floo_req_t [4:0] router_19_24_req_out; -floo_rsp_t [4:0] router_19_24_rsp_in; - - assign router_19_24_req_in[0] = router_19_25_to_router_19_24_req; - assign router_19_24_req_in[1] = router_20_24_to_router_19_24_req; - assign router_19_24_req_in[2] = router_19_23_to_router_19_24_req; - assign router_19_24_req_in[3] = router_18_24_to_router_19_24_req; - assign router_19_24_req_in[4] = magia_tile_ni_19_24_to_router_19_24_req; - - assign router_19_24_to_router_19_25_rsp = router_19_24_rsp_out[0]; - assign router_19_24_to_router_20_24_rsp = router_19_24_rsp_out[1]; - assign router_19_24_to_router_19_23_rsp = router_19_24_rsp_out[2]; - assign router_19_24_to_router_18_24_rsp = router_19_24_rsp_out[3]; - assign router_19_24_to_magia_tile_ni_19_24_rsp = router_19_24_rsp_out[4]; - - assign router_19_24_to_router_19_25_req = router_19_24_req_out[0]; - assign router_19_24_to_router_20_24_req = router_19_24_req_out[1]; - assign router_19_24_to_router_19_23_req = router_19_24_req_out[2]; - assign router_19_24_to_router_18_24_req = router_19_24_req_out[3]; - assign router_19_24_to_magia_tile_ni_19_24_req = router_19_24_req_out[4]; - - assign router_19_24_rsp_in[0] = router_19_25_to_router_19_24_rsp; - assign router_19_24_rsp_in[1] = router_20_24_to_router_19_24_rsp; - assign router_19_24_rsp_in[2] = router_19_23_to_router_19_24_rsp; - assign router_19_24_rsp_in[3] = router_18_24_to_router_19_24_rsp; - assign router_19_24_rsp_in[4] = magia_tile_ni_19_24_to_router_19_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_24_req_in), - .floo_rsp_o (router_19_24_rsp_out), - .floo_req_o (router_19_24_req_out), - .floo_rsp_i (router_19_24_rsp_in) -); - - -floo_req_t [4:0] router_19_25_req_in; -floo_rsp_t [4:0] router_19_25_rsp_out; -floo_req_t [4:0] router_19_25_req_out; -floo_rsp_t [4:0] router_19_25_rsp_in; - - assign router_19_25_req_in[0] = router_19_26_to_router_19_25_req; - assign router_19_25_req_in[1] = router_20_25_to_router_19_25_req; - assign router_19_25_req_in[2] = router_19_24_to_router_19_25_req; - assign router_19_25_req_in[3] = router_18_25_to_router_19_25_req; - assign router_19_25_req_in[4] = magia_tile_ni_19_25_to_router_19_25_req; - - assign router_19_25_to_router_19_26_rsp = router_19_25_rsp_out[0]; - assign router_19_25_to_router_20_25_rsp = router_19_25_rsp_out[1]; - assign router_19_25_to_router_19_24_rsp = router_19_25_rsp_out[2]; - assign router_19_25_to_router_18_25_rsp = router_19_25_rsp_out[3]; - assign router_19_25_to_magia_tile_ni_19_25_rsp = router_19_25_rsp_out[4]; - - assign router_19_25_to_router_19_26_req = router_19_25_req_out[0]; - assign router_19_25_to_router_20_25_req = router_19_25_req_out[1]; - assign router_19_25_to_router_19_24_req = router_19_25_req_out[2]; - assign router_19_25_to_router_18_25_req = router_19_25_req_out[3]; - assign router_19_25_to_magia_tile_ni_19_25_req = router_19_25_req_out[4]; - - assign router_19_25_rsp_in[0] = router_19_26_to_router_19_25_rsp; - assign router_19_25_rsp_in[1] = router_20_25_to_router_19_25_rsp; - assign router_19_25_rsp_in[2] = router_19_24_to_router_19_25_rsp; - assign router_19_25_rsp_in[3] = router_18_25_to_router_19_25_rsp; - assign router_19_25_rsp_in[4] = magia_tile_ni_19_25_to_router_19_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_25_req_in), - .floo_rsp_o (router_19_25_rsp_out), - .floo_req_o (router_19_25_req_out), - .floo_rsp_i (router_19_25_rsp_in) -); - - -floo_req_t [4:0] router_19_26_req_in; -floo_rsp_t [4:0] router_19_26_rsp_out; -floo_req_t [4:0] router_19_26_req_out; -floo_rsp_t [4:0] router_19_26_rsp_in; - - assign router_19_26_req_in[0] = router_19_27_to_router_19_26_req; - assign router_19_26_req_in[1] = router_20_26_to_router_19_26_req; - assign router_19_26_req_in[2] = router_19_25_to_router_19_26_req; - assign router_19_26_req_in[3] = router_18_26_to_router_19_26_req; - assign router_19_26_req_in[4] = magia_tile_ni_19_26_to_router_19_26_req; - - assign router_19_26_to_router_19_27_rsp = router_19_26_rsp_out[0]; - assign router_19_26_to_router_20_26_rsp = router_19_26_rsp_out[1]; - assign router_19_26_to_router_19_25_rsp = router_19_26_rsp_out[2]; - assign router_19_26_to_router_18_26_rsp = router_19_26_rsp_out[3]; - assign router_19_26_to_magia_tile_ni_19_26_rsp = router_19_26_rsp_out[4]; - - assign router_19_26_to_router_19_27_req = router_19_26_req_out[0]; - assign router_19_26_to_router_20_26_req = router_19_26_req_out[1]; - assign router_19_26_to_router_19_25_req = router_19_26_req_out[2]; - assign router_19_26_to_router_18_26_req = router_19_26_req_out[3]; - assign router_19_26_to_magia_tile_ni_19_26_req = router_19_26_req_out[4]; - - assign router_19_26_rsp_in[0] = router_19_27_to_router_19_26_rsp; - assign router_19_26_rsp_in[1] = router_20_26_to_router_19_26_rsp; - assign router_19_26_rsp_in[2] = router_19_25_to_router_19_26_rsp; - assign router_19_26_rsp_in[3] = router_18_26_to_router_19_26_rsp; - assign router_19_26_rsp_in[4] = magia_tile_ni_19_26_to_router_19_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_26_req_in), - .floo_rsp_o (router_19_26_rsp_out), - .floo_req_o (router_19_26_req_out), - .floo_rsp_i (router_19_26_rsp_in) -); - - -floo_req_t [4:0] router_19_27_req_in; -floo_rsp_t [4:0] router_19_27_rsp_out; -floo_req_t [4:0] router_19_27_req_out; -floo_rsp_t [4:0] router_19_27_rsp_in; - - assign router_19_27_req_in[0] = router_19_28_to_router_19_27_req; - assign router_19_27_req_in[1] = router_20_27_to_router_19_27_req; - assign router_19_27_req_in[2] = router_19_26_to_router_19_27_req; - assign router_19_27_req_in[3] = router_18_27_to_router_19_27_req; - assign router_19_27_req_in[4] = magia_tile_ni_19_27_to_router_19_27_req; - - assign router_19_27_to_router_19_28_rsp = router_19_27_rsp_out[0]; - assign router_19_27_to_router_20_27_rsp = router_19_27_rsp_out[1]; - assign router_19_27_to_router_19_26_rsp = router_19_27_rsp_out[2]; - assign router_19_27_to_router_18_27_rsp = router_19_27_rsp_out[3]; - assign router_19_27_to_magia_tile_ni_19_27_rsp = router_19_27_rsp_out[4]; - - assign router_19_27_to_router_19_28_req = router_19_27_req_out[0]; - assign router_19_27_to_router_20_27_req = router_19_27_req_out[1]; - assign router_19_27_to_router_19_26_req = router_19_27_req_out[2]; - assign router_19_27_to_router_18_27_req = router_19_27_req_out[3]; - assign router_19_27_to_magia_tile_ni_19_27_req = router_19_27_req_out[4]; - - assign router_19_27_rsp_in[0] = router_19_28_to_router_19_27_rsp; - assign router_19_27_rsp_in[1] = router_20_27_to_router_19_27_rsp; - assign router_19_27_rsp_in[2] = router_19_26_to_router_19_27_rsp; - assign router_19_27_rsp_in[3] = router_18_27_to_router_19_27_rsp; - assign router_19_27_rsp_in[4] = magia_tile_ni_19_27_to_router_19_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_27_req_in), - .floo_rsp_o (router_19_27_rsp_out), - .floo_req_o (router_19_27_req_out), - .floo_rsp_i (router_19_27_rsp_in) -); - - -floo_req_t [4:0] router_19_28_req_in; -floo_rsp_t [4:0] router_19_28_rsp_out; -floo_req_t [4:0] router_19_28_req_out; -floo_rsp_t [4:0] router_19_28_rsp_in; - - assign router_19_28_req_in[0] = router_19_29_to_router_19_28_req; - assign router_19_28_req_in[1] = router_20_28_to_router_19_28_req; - assign router_19_28_req_in[2] = router_19_27_to_router_19_28_req; - assign router_19_28_req_in[3] = router_18_28_to_router_19_28_req; - assign router_19_28_req_in[4] = magia_tile_ni_19_28_to_router_19_28_req; - - assign router_19_28_to_router_19_29_rsp = router_19_28_rsp_out[0]; - assign router_19_28_to_router_20_28_rsp = router_19_28_rsp_out[1]; - assign router_19_28_to_router_19_27_rsp = router_19_28_rsp_out[2]; - assign router_19_28_to_router_18_28_rsp = router_19_28_rsp_out[3]; - assign router_19_28_to_magia_tile_ni_19_28_rsp = router_19_28_rsp_out[4]; - - assign router_19_28_to_router_19_29_req = router_19_28_req_out[0]; - assign router_19_28_to_router_20_28_req = router_19_28_req_out[1]; - assign router_19_28_to_router_19_27_req = router_19_28_req_out[2]; - assign router_19_28_to_router_18_28_req = router_19_28_req_out[3]; - assign router_19_28_to_magia_tile_ni_19_28_req = router_19_28_req_out[4]; - - assign router_19_28_rsp_in[0] = router_19_29_to_router_19_28_rsp; - assign router_19_28_rsp_in[1] = router_20_28_to_router_19_28_rsp; - assign router_19_28_rsp_in[2] = router_19_27_to_router_19_28_rsp; - assign router_19_28_rsp_in[3] = router_18_28_to_router_19_28_rsp; - assign router_19_28_rsp_in[4] = magia_tile_ni_19_28_to_router_19_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_28_req_in), - .floo_rsp_o (router_19_28_rsp_out), - .floo_req_o (router_19_28_req_out), - .floo_rsp_i (router_19_28_rsp_in) -); - - -floo_req_t [4:0] router_19_29_req_in; -floo_rsp_t [4:0] router_19_29_rsp_out; -floo_req_t [4:0] router_19_29_req_out; -floo_rsp_t [4:0] router_19_29_rsp_in; - - assign router_19_29_req_in[0] = router_19_30_to_router_19_29_req; - assign router_19_29_req_in[1] = router_20_29_to_router_19_29_req; - assign router_19_29_req_in[2] = router_19_28_to_router_19_29_req; - assign router_19_29_req_in[3] = router_18_29_to_router_19_29_req; - assign router_19_29_req_in[4] = magia_tile_ni_19_29_to_router_19_29_req; - - assign router_19_29_to_router_19_30_rsp = router_19_29_rsp_out[0]; - assign router_19_29_to_router_20_29_rsp = router_19_29_rsp_out[1]; - assign router_19_29_to_router_19_28_rsp = router_19_29_rsp_out[2]; - assign router_19_29_to_router_18_29_rsp = router_19_29_rsp_out[3]; - assign router_19_29_to_magia_tile_ni_19_29_rsp = router_19_29_rsp_out[4]; - - assign router_19_29_to_router_19_30_req = router_19_29_req_out[0]; - assign router_19_29_to_router_20_29_req = router_19_29_req_out[1]; - assign router_19_29_to_router_19_28_req = router_19_29_req_out[2]; - assign router_19_29_to_router_18_29_req = router_19_29_req_out[3]; - assign router_19_29_to_magia_tile_ni_19_29_req = router_19_29_req_out[4]; - - assign router_19_29_rsp_in[0] = router_19_30_to_router_19_29_rsp; - assign router_19_29_rsp_in[1] = router_20_29_to_router_19_29_rsp; - assign router_19_29_rsp_in[2] = router_19_28_to_router_19_29_rsp; - assign router_19_29_rsp_in[3] = router_18_29_to_router_19_29_rsp; - assign router_19_29_rsp_in[4] = magia_tile_ni_19_29_to_router_19_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_29_req_in), - .floo_rsp_o (router_19_29_rsp_out), - .floo_req_o (router_19_29_req_out), - .floo_rsp_i (router_19_29_rsp_in) -); - - -floo_req_t [4:0] router_19_30_req_in; -floo_rsp_t [4:0] router_19_30_rsp_out; -floo_req_t [4:0] router_19_30_req_out; -floo_rsp_t [4:0] router_19_30_rsp_in; - - assign router_19_30_req_in[0] = router_19_31_to_router_19_30_req; - assign router_19_30_req_in[1] = router_20_30_to_router_19_30_req; - assign router_19_30_req_in[2] = router_19_29_to_router_19_30_req; - assign router_19_30_req_in[3] = router_18_30_to_router_19_30_req; - assign router_19_30_req_in[4] = magia_tile_ni_19_30_to_router_19_30_req; - - assign router_19_30_to_router_19_31_rsp = router_19_30_rsp_out[0]; - assign router_19_30_to_router_20_30_rsp = router_19_30_rsp_out[1]; - assign router_19_30_to_router_19_29_rsp = router_19_30_rsp_out[2]; - assign router_19_30_to_router_18_30_rsp = router_19_30_rsp_out[3]; - assign router_19_30_to_magia_tile_ni_19_30_rsp = router_19_30_rsp_out[4]; - - assign router_19_30_to_router_19_31_req = router_19_30_req_out[0]; - assign router_19_30_to_router_20_30_req = router_19_30_req_out[1]; - assign router_19_30_to_router_19_29_req = router_19_30_req_out[2]; - assign router_19_30_to_router_18_30_req = router_19_30_req_out[3]; - assign router_19_30_to_magia_tile_ni_19_30_req = router_19_30_req_out[4]; - - assign router_19_30_rsp_in[0] = router_19_31_to_router_19_30_rsp; - assign router_19_30_rsp_in[1] = router_20_30_to_router_19_30_rsp; - assign router_19_30_rsp_in[2] = router_19_29_to_router_19_30_rsp; - assign router_19_30_rsp_in[3] = router_18_30_to_router_19_30_rsp; - assign router_19_30_rsp_in[4] = magia_tile_ni_19_30_to_router_19_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_30_req_in), - .floo_rsp_o (router_19_30_rsp_out), - .floo_req_o (router_19_30_req_out), - .floo_rsp_i (router_19_30_rsp_in) -); - - -floo_req_t [4:0] router_19_31_req_in; -floo_rsp_t [4:0] router_19_31_rsp_out; -floo_req_t [4:0] router_19_31_req_out; -floo_rsp_t [4:0] router_19_31_rsp_in; - - assign router_19_31_req_in[0] = '0; - assign router_19_31_req_in[1] = router_20_31_to_router_19_31_req; - assign router_19_31_req_in[2] = router_19_30_to_router_19_31_req; - assign router_19_31_req_in[3] = router_18_31_to_router_19_31_req; - assign router_19_31_req_in[4] = magia_tile_ni_19_31_to_router_19_31_req; - - assign router_19_31_to_router_20_31_rsp = router_19_31_rsp_out[1]; - assign router_19_31_to_router_19_30_rsp = router_19_31_rsp_out[2]; - assign router_19_31_to_router_18_31_rsp = router_19_31_rsp_out[3]; - assign router_19_31_to_magia_tile_ni_19_31_rsp = router_19_31_rsp_out[4]; - - assign router_19_31_to_router_20_31_req = router_19_31_req_out[1]; - assign router_19_31_to_router_19_30_req = router_19_31_req_out[2]; - assign router_19_31_to_router_18_31_req = router_19_31_req_out[3]; - assign router_19_31_to_magia_tile_ni_19_31_req = router_19_31_req_out[4]; - - assign router_19_31_rsp_in[0] = '0; - assign router_19_31_rsp_in[1] = router_20_31_to_router_19_31_rsp; - assign router_19_31_rsp_in[2] = router_19_30_to_router_19_31_rsp; - assign router_19_31_rsp_in[3] = router_18_31_to_router_19_31_rsp; - assign router_19_31_rsp_in[4] = magia_tile_ni_19_31_to_router_19_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_19_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 20, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_19_31_req_in), - .floo_rsp_o (router_19_31_rsp_out), - .floo_req_o (router_19_31_req_out), - .floo_rsp_i (router_19_31_rsp_in) -); - - -floo_req_t [4:0] router_20_0_req_in; -floo_rsp_t [4:0] router_20_0_rsp_out; -floo_req_t [4:0] router_20_0_req_out; -floo_rsp_t [4:0] router_20_0_rsp_in; - - assign router_20_0_req_in[0] = router_20_1_to_router_20_0_req; - assign router_20_0_req_in[1] = router_21_0_to_router_20_0_req; - assign router_20_0_req_in[2] = '0; - assign router_20_0_req_in[3] = router_19_0_to_router_20_0_req; - assign router_20_0_req_in[4] = magia_tile_ni_20_0_to_router_20_0_req; - - assign router_20_0_to_router_20_1_rsp = router_20_0_rsp_out[0]; - assign router_20_0_to_router_21_0_rsp = router_20_0_rsp_out[1]; - assign router_20_0_to_router_19_0_rsp = router_20_0_rsp_out[3]; - assign router_20_0_to_magia_tile_ni_20_0_rsp = router_20_0_rsp_out[4]; - - assign router_20_0_to_router_20_1_req = router_20_0_req_out[0]; - assign router_20_0_to_router_21_0_req = router_20_0_req_out[1]; - assign router_20_0_to_router_19_0_req = router_20_0_req_out[3]; - assign router_20_0_to_magia_tile_ni_20_0_req = router_20_0_req_out[4]; - - assign router_20_0_rsp_in[0] = router_20_1_to_router_20_0_rsp; - assign router_20_0_rsp_in[1] = router_21_0_to_router_20_0_rsp; - assign router_20_0_rsp_in[2] = '0; - assign router_20_0_rsp_in[3] = router_19_0_to_router_20_0_rsp; - assign router_20_0_rsp_in[4] = magia_tile_ni_20_0_to_router_20_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_0_req_in), - .floo_rsp_o (router_20_0_rsp_out), - .floo_req_o (router_20_0_req_out), - .floo_rsp_i (router_20_0_rsp_in) -); - - -floo_req_t [4:0] router_20_1_req_in; -floo_rsp_t [4:0] router_20_1_rsp_out; -floo_req_t [4:0] router_20_1_req_out; -floo_rsp_t [4:0] router_20_1_rsp_in; - - assign router_20_1_req_in[0] = router_20_2_to_router_20_1_req; - assign router_20_1_req_in[1] = router_21_1_to_router_20_1_req; - assign router_20_1_req_in[2] = router_20_0_to_router_20_1_req; - assign router_20_1_req_in[3] = router_19_1_to_router_20_1_req; - assign router_20_1_req_in[4] = magia_tile_ni_20_1_to_router_20_1_req; - - assign router_20_1_to_router_20_2_rsp = router_20_1_rsp_out[0]; - assign router_20_1_to_router_21_1_rsp = router_20_1_rsp_out[1]; - assign router_20_1_to_router_20_0_rsp = router_20_1_rsp_out[2]; - assign router_20_1_to_router_19_1_rsp = router_20_1_rsp_out[3]; - assign router_20_1_to_magia_tile_ni_20_1_rsp = router_20_1_rsp_out[4]; - - assign router_20_1_to_router_20_2_req = router_20_1_req_out[0]; - assign router_20_1_to_router_21_1_req = router_20_1_req_out[1]; - assign router_20_1_to_router_20_0_req = router_20_1_req_out[2]; - assign router_20_1_to_router_19_1_req = router_20_1_req_out[3]; - assign router_20_1_to_magia_tile_ni_20_1_req = router_20_1_req_out[4]; - - assign router_20_1_rsp_in[0] = router_20_2_to_router_20_1_rsp; - assign router_20_1_rsp_in[1] = router_21_1_to_router_20_1_rsp; - assign router_20_1_rsp_in[2] = router_20_0_to_router_20_1_rsp; - assign router_20_1_rsp_in[3] = router_19_1_to_router_20_1_rsp; - assign router_20_1_rsp_in[4] = magia_tile_ni_20_1_to_router_20_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_1_req_in), - .floo_rsp_o (router_20_1_rsp_out), - .floo_req_o (router_20_1_req_out), - .floo_rsp_i (router_20_1_rsp_in) -); - - -floo_req_t [4:0] router_20_2_req_in; -floo_rsp_t [4:0] router_20_2_rsp_out; -floo_req_t [4:0] router_20_2_req_out; -floo_rsp_t [4:0] router_20_2_rsp_in; - - assign router_20_2_req_in[0] = router_20_3_to_router_20_2_req; - assign router_20_2_req_in[1] = router_21_2_to_router_20_2_req; - assign router_20_2_req_in[2] = router_20_1_to_router_20_2_req; - assign router_20_2_req_in[3] = router_19_2_to_router_20_2_req; - assign router_20_2_req_in[4] = magia_tile_ni_20_2_to_router_20_2_req; - - assign router_20_2_to_router_20_3_rsp = router_20_2_rsp_out[0]; - assign router_20_2_to_router_21_2_rsp = router_20_2_rsp_out[1]; - assign router_20_2_to_router_20_1_rsp = router_20_2_rsp_out[2]; - assign router_20_2_to_router_19_2_rsp = router_20_2_rsp_out[3]; - assign router_20_2_to_magia_tile_ni_20_2_rsp = router_20_2_rsp_out[4]; - - assign router_20_2_to_router_20_3_req = router_20_2_req_out[0]; - assign router_20_2_to_router_21_2_req = router_20_2_req_out[1]; - assign router_20_2_to_router_20_1_req = router_20_2_req_out[2]; - assign router_20_2_to_router_19_2_req = router_20_2_req_out[3]; - assign router_20_2_to_magia_tile_ni_20_2_req = router_20_2_req_out[4]; - - assign router_20_2_rsp_in[0] = router_20_3_to_router_20_2_rsp; - assign router_20_2_rsp_in[1] = router_21_2_to_router_20_2_rsp; - assign router_20_2_rsp_in[2] = router_20_1_to_router_20_2_rsp; - assign router_20_2_rsp_in[3] = router_19_2_to_router_20_2_rsp; - assign router_20_2_rsp_in[4] = magia_tile_ni_20_2_to_router_20_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_2_req_in), - .floo_rsp_o (router_20_2_rsp_out), - .floo_req_o (router_20_2_req_out), - .floo_rsp_i (router_20_2_rsp_in) -); - - -floo_req_t [4:0] router_20_3_req_in; -floo_rsp_t [4:0] router_20_3_rsp_out; -floo_req_t [4:0] router_20_3_req_out; -floo_rsp_t [4:0] router_20_3_rsp_in; - - assign router_20_3_req_in[0] = router_20_4_to_router_20_3_req; - assign router_20_3_req_in[1] = router_21_3_to_router_20_3_req; - assign router_20_3_req_in[2] = router_20_2_to_router_20_3_req; - assign router_20_3_req_in[3] = router_19_3_to_router_20_3_req; - assign router_20_3_req_in[4] = magia_tile_ni_20_3_to_router_20_3_req; - - assign router_20_3_to_router_20_4_rsp = router_20_3_rsp_out[0]; - assign router_20_3_to_router_21_3_rsp = router_20_3_rsp_out[1]; - assign router_20_3_to_router_20_2_rsp = router_20_3_rsp_out[2]; - assign router_20_3_to_router_19_3_rsp = router_20_3_rsp_out[3]; - assign router_20_3_to_magia_tile_ni_20_3_rsp = router_20_3_rsp_out[4]; - - assign router_20_3_to_router_20_4_req = router_20_3_req_out[0]; - assign router_20_3_to_router_21_3_req = router_20_3_req_out[1]; - assign router_20_3_to_router_20_2_req = router_20_3_req_out[2]; - assign router_20_3_to_router_19_3_req = router_20_3_req_out[3]; - assign router_20_3_to_magia_tile_ni_20_3_req = router_20_3_req_out[4]; - - assign router_20_3_rsp_in[0] = router_20_4_to_router_20_3_rsp; - assign router_20_3_rsp_in[1] = router_21_3_to_router_20_3_rsp; - assign router_20_3_rsp_in[2] = router_20_2_to_router_20_3_rsp; - assign router_20_3_rsp_in[3] = router_19_3_to_router_20_3_rsp; - assign router_20_3_rsp_in[4] = magia_tile_ni_20_3_to_router_20_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_3_req_in), - .floo_rsp_o (router_20_3_rsp_out), - .floo_req_o (router_20_3_req_out), - .floo_rsp_i (router_20_3_rsp_in) -); - - -floo_req_t [4:0] router_20_4_req_in; -floo_rsp_t [4:0] router_20_4_rsp_out; -floo_req_t [4:0] router_20_4_req_out; -floo_rsp_t [4:0] router_20_4_rsp_in; - - assign router_20_4_req_in[0] = router_20_5_to_router_20_4_req; - assign router_20_4_req_in[1] = router_21_4_to_router_20_4_req; - assign router_20_4_req_in[2] = router_20_3_to_router_20_4_req; - assign router_20_4_req_in[3] = router_19_4_to_router_20_4_req; - assign router_20_4_req_in[4] = magia_tile_ni_20_4_to_router_20_4_req; - - assign router_20_4_to_router_20_5_rsp = router_20_4_rsp_out[0]; - assign router_20_4_to_router_21_4_rsp = router_20_4_rsp_out[1]; - assign router_20_4_to_router_20_3_rsp = router_20_4_rsp_out[2]; - assign router_20_4_to_router_19_4_rsp = router_20_4_rsp_out[3]; - assign router_20_4_to_magia_tile_ni_20_4_rsp = router_20_4_rsp_out[4]; - - assign router_20_4_to_router_20_5_req = router_20_4_req_out[0]; - assign router_20_4_to_router_21_4_req = router_20_4_req_out[1]; - assign router_20_4_to_router_20_3_req = router_20_4_req_out[2]; - assign router_20_4_to_router_19_4_req = router_20_4_req_out[3]; - assign router_20_4_to_magia_tile_ni_20_4_req = router_20_4_req_out[4]; - - assign router_20_4_rsp_in[0] = router_20_5_to_router_20_4_rsp; - assign router_20_4_rsp_in[1] = router_21_4_to_router_20_4_rsp; - assign router_20_4_rsp_in[2] = router_20_3_to_router_20_4_rsp; - assign router_20_4_rsp_in[3] = router_19_4_to_router_20_4_rsp; - assign router_20_4_rsp_in[4] = magia_tile_ni_20_4_to_router_20_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_4_req_in), - .floo_rsp_o (router_20_4_rsp_out), - .floo_req_o (router_20_4_req_out), - .floo_rsp_i (router_20_4_rsp_in) -); - - -floo_req_t [4:0] router_20_5_req_in; -floo_rsp_t [4:0] router_20_5_rsp_out; -floo_req_t [4:0] router_20_5_req_out; -floo_rsp_t [4:0] router_20_5_rsp_in; - - assign router_20_5_req_in[0] = router_20_6_to_router_20_5_req; - assign router_20_5_req_in[1] = router_21_5_to_router_20_5_req; - assign router_20_5_req_in[2] = router_20_4_to_router_20_5_req; - assign router_20_5_req_in[3] = router_19_5_to_router_20_5_req; - assign router_20_5_req_in[4] = magia_tile_ni_20_5_to_router_20_5_req; - - assign router_20_5_to_router_20_6_rsp = router_20_5_rsp_out[0]; - assign router_20_5_to_router_21_5_rsp = router_20_5_rsp_out[1]; - assign router_20_5_to_router_20_4_rsp = router_20_5_rsp_out[2]; - assign router_20_5_to_router_19_5_rsp = router_20_5_rsp_out[3]; - assign router_20_5_to_magia_tile_ni_20_5_rsp = router_20_5_rsp_out[4]; - - assign router_20_5_to_router_20_6_req = router_20_5_req_out[0]; - assign router_20_5_to_router_21_5_req = router_20_5_req_out[1]; - assign router_20_5_to_router_20_4_req = router_20_5_req_out[2]; - assign router_20_5_to_router_19_5_req = router_20_5_req_out[3]; - assign router_20_5_to_magia_tile_ni_20_5_req = router_20_5_req_out[4]; - - assign router_20_5_rsp_in[0] = router_20_6_to_router_20_5_rsp; - assign router_20_5_rsp_in[1] = router_21_5_to_router_20_5_rsp; - assign router_20_5_rsp_in[2] = router_20_4_to_router_20_5_rsp; - assign router_20_5_rsp_in[3] = router_19_5_to_router_20_5_rsp; - assign router_20_5_rsp_in[4] = magia_tile_ni_20_5_to_router_20_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_5_req_in), - .floo_rsp_o (router_20_5_rsp_out), - .floo_req_o (router_20_5_req_out), - .floo_rsp_i (router_20_5_rsp_in) -); - - -floo_req_t [4:0] router_20_6_req_in; -floo_rsp_t [4:0] router_20_6_rsp_out; -floo_req_t [4:0] router_20_6_req_out; -floo_rsp_t [4:0] router_20_6_rsp_in; - - assign router_20_6_req_in[0] = router_20_7_to_router_20_6_req; - assign router_20_6_req_in[1] = router_21_6_to_router_20_6_req; - assign router_20_6_req_in[2] = router_20_5_to_router_20_6_req; - assign router_20_6_req_in[3] = router_19_6_to_router_20_6_req; - assign router_20_6_req_in[4] = magia_tile_ni_20_6_to_router_20_6_req; - - assign router_20_6_to_router_20_7_rsp = router_20_6_rsp_out[0]; - assign router_20_6_to_router_21_6_rsp = router_20_6_rsp_out[1]; - assign router_20_6_to_router_20_5_rsp = router_20_6_rsp_out[2]; - assign router_20_6_to_router_19_6_rsp = router_20_6_rsp_out[3]; - assign router_20_6_to_magia_tile_ni_20_6_rsp = router_20_6_rsp_out[4]; - - assign router_20_6_to_router_20_7_req = router_20_6_req_out[0]; - assign router_20_6_to_router_21_6_req = router_20_6_req_out[1]; - assign router_20_6_to_router_20_5_req = router_20_6_req_out[2]; - assign router_20_6_to_router_19_6_req = router_20_6_req_out[3]; - assign router_20_6_to_magia_tile_ni_20_6_req = router_20_6_req_out[4]; - - assign router_20_6_rsp_in[0] = router_20_7_to_router_20_6_rsp; - assign router_20_6_rsp_in[1] = router_21_6_to_router_20_6_rsp; - assign router_20_6_rsp_in[2] = router_20_5_to_router_20_6_rsp; - assign router_20_6_rsp_in[3] = router_19_6_to_router_20_6_rsp; - assign router_20_6_rsp_in[4] = magia_tile_ni_20_6_to_router_20_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_6_req_in), - .floo_rsp_o (router_20_6_rsp_out), - .floo_req_o (router_20_6_req_out), - .floo_rsp_i (router_20_6_rsp_in) -); - - -floo_req_t [4:0] router_20_7_req_in; -floo_rsp_t [4:0] router_20_7_rsp_out; -floo_req_t [4:0] router_20_7_req_out; -floo_rsp_t [4:0] router_20_7_rsp_in; - - assign router_20_7_req_in[0] = router_20_8_to_router_20_7_req; - assign router_20_7_req_in[1] = router_21_7_to_router_20_7_req; - assign router_20_7_req_in[2] = router_20_6_to_router_20_7_req; - assign router_20_7_req_in[3] = router_19_7_to_router_20_7_req; - assign router_20_7_req_in[4] = magia_tile_ni_20_7_to_router_20_7_req; - - assign router_20_7_to_router_20_8_rsp = router_20_7_rsp_out[0]; - assign router_20_7_to_router_21_7_rsp = router_20_7_rsp_out[1]; - assign router_20_7_to_router_20_6_rsp = router_20_7_rsp_out[2]; - assign router_20_7_to_router_19_7_rsp = router_20_7_rsp_out[3]; - assign router_20_7_to_magia_tile_ni_20_7_rsp = router_20_7_rsp_out[4]; - - assign router_20_7_to_router_20_8_req = router_20_7_req_out[0]; - assign router_20_7_to_router_21_7_req = router_20_7_req_out[1]; - assign router_20_7_to_router_20_6_req = router_20_7_req_out[2]; - assign router_20_7_to_router_19_7_req = router_20_7_req_out[3]; - assign router_20_7_to_magia_tile_ni_20_7_req = router_20_7_req_out[4]; - - assign router_20_7_rsp_in[0] = router_20_8_to_router_20_7_rsp; - assign router_20_7_rsp_in[1] = router_21_7_to_router_20_7_rsp; - assign router_20_7_rsp_in[2] = router_20_6_to_router_20_7_rsp; - assign router_20_7_rsp_in[3] = router_19_7_to_router_20_7_rsp; - assign router_20_7_rsp_in[4] = magia_tile_ni_20_7_to_router_20_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_7_req_in), - .floo_rsp_o (router_20_7_rsp_out), - .floo_req_o (router_20_7_req_out), - .floo_rsp_i (router_20_7_rsp_in) -); - - -floo_req_t [4:0] router_20_8_req_in; -floo_rsp_t [4:0] router_20_8_rsp_out; -floo_req_t [4:0] router_20_8_req_out; -floo_rsp_t [4:0] router_20_8_rsp_in; - - assign router_20_8_req_in[0] = router_20_9_to_router_20_8_req; - assign router_20_8_req_in[1] = router_21_8_to_router_20_8_req; - assign router_20_8_req_in[2] = router_20_7_to_router_20_8_req; - assign router_20_8_req_in[3] = router_19_8_to_router_20_8_req; - assign router_20_8_req_in[4] = magia_tile_ni_20_8_to_router_20_8_req; - - assign router_20_8_to_router_20_9_rsp = router_20_8_rsp_out[0]; - assign router_20_8_to_router_21_8_rsp = router_20_8_rsp_out[1]; - assign router_20_8_to_router_20_7_rsp = router_20_8_rsp_out[2]; - assign router_20_8_to_router_19_8_rsp = router_20_8_rsp_out[3]; - assign router_20_8_to_magia_tile_ni_20_8_rsp = router_20_8_rsp_out[4]; - - assign router_20_8_to_router_20_9_req = router_20_8_req_out[0]; - assign router_20_8_to_router_21_8_req = router_20_8_req_out[1]; - assign router_20_8_to_router_20_7_req = router_20_8_req_out[2]; - assign router_20_8_to_router_19_8_req = router_20_8_req_out[3]; - assign router_20_8_to_magia_tile_ni_20_8_req = router_20_8_req_out[4]; - - assign router_20_8_rsp_in[0] = router_20_9_to_router_20_8_rsp; - assign router_20_8_rsp_in[1] = router_21_8_to_router_20_8_rsp; - assign router_20_8_rsp_in[2] = router_20_7_to_router_20_8_rsp; - assign router_20_8_rsp_in[3] = router_19_8_to_router_20_8_rsp; - assign router_20_8_rsp_in[4] = magia_tile_ni_20_8_to_router_20_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_8_req_in), - .floo_rsp_o (router_20_8_rsp_out), - .floo_req_o (router_20_8_req_out), - .floo_rsp_i (router_20_8_rsp_in) -); - - -floo_req_t [4:0] router_20_9_req_in; -floo_rsp_t [4:0] router_20_9_rsp_out; -floo_req_t [4:0] router_20_9_req_out; -floo_rsp_t [4:0] router_20_9_rsp_in; - - assign router_20_9_req_in[0] = router_20_10_to_router_20_9_req; - assign router_20_9_req_in[1] = router_21_9_to_router_20_9_req; - assign router_20_9_req_in[2] = router_20_8_to_router_20_9_req; - assign router_20_9_req_in[3] = router_19_9_to_router_20_9_req; - assign router_20_9_req_in[4] = magia_tile_ni_20_9_to_router_20_9_req; - - assign router_20_9_to_router_20_10_rsp = router_20_9_rsp_out[0]; - assign router_20_9_to_router_21_9_rsp = router_20_9_rsp_out[1]; - assign router_20_9_to_router_20_8_rsp = router_20_9_rsp_out[2]; - assign router_20_9_to_router_19_9_rsp = router_20_9_rsp_out[3]; - assign router_20_9_to_magia_tile_ni_20_9_rsp = router_20_9_rsp_out[4]; - - assign router_20_9_to_router_20_10_req = router_20_9_req_out[0]; - assign router_20_9_to_router_21_9_req = router_20_9_req_out[1]; - assign router_20_9_to_router_20_8_req = router_20_9_req_out[2]; - assign router_20_9_to_router_19_9_req = router_20_9_req_out[3]; - assign router_20_9_to_magia_tile_ni_20_9_req = router_20_9_req_out[4]; - - assign router_20_9_rsp_in[0] = router_20_10_to_router_20_9_rsp; - assign router_20_9_rsp_in[1] = router_21_9_to_router_20_9_rsp; - assign router_20_9_rsp_in[2] = router_20_8_to_router_20_9_rsp; - assign router_20_9_rsp_in[3] = router_19_9_to_router_20_9_rsp; - assign router_20_9_rsp_in[4] = magia_tile_ni_20_9_to_router_20_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_9_req_in), - .floo_rsp_o (router_20_9_rsp_out), - .floo_req_o (router_20_9_req_out), - .floo_rsp_i (router_20_9_rsp_in) -); - - -floo_req_t [4:0] router_20_10_req_in; -floo_rsp_t [4:0] router_20_10_rsp_out; -floo_req_t [4:0] router_20_10_req_out; -floo_rsp_t [4:0] router_20_10_rsp_in; - - assign router_20_10_req_in[0] = router_20_11_to_router_20_10_req; - assign router_20_10_req_in[1] = router_21_10_to_router_20_10_req; - assign router_20_10_req_in[2] = router_20_9_to_router_20_10_req; - assign router_20_10_req_in[3] = router_19_10_to_router_20_10_req; - assign router_20_10_req_in[4] = magia_tile_ni_20_10_to_router_20_10_req; - - assign router_20_10_to_router_20_11_rsp = router_20_10_rsp_out[0]; - assign router_20_10_to_router_21_10_rsp = router_20_10_rsp_out[1]; - assign router_20_10_to_router_20_9_rsp = router_20_10_rsp_out[2]; - assign router_20_10_to_router_19_10_rsp = router_20_10_rsp_out[3]; - assign router_20_10_to_magia_tile_ni_20_10_rsp = router_20_10_rsp_out[4]; - - assign router_20_10_to_router_20_11_req = router_20_10_req_out[0]; - assign router_20_10_to_router_21_10_req = router_20_10_req_out[1]; - assign router_20_10_to_router_20_9_req = router_20_10_req_out[2]; - assign router_20_10_to_router_19_10_req = router_20_10_req_out[3]; - assign router_20_10_to_magia_tile_ni_20_10_req = router_20_10_req_out[4]; - - assign router_20_10_rsp_in[0] = router_20_11_to_router_20_10_rsp; - assign router_20_10_rsp_in[1] = router_21_10_to_router_20_10_rsp; - assign router_20_10_rsp_in[2] = router_20_9_to_router_20_10_rsp; - assign router_20_10_rsp_in[3] = router_19_10_to_router_20_10_rsp; - assign router_20_10_rsp_in[4] = magia_tile_ni_20_10_to_router_20_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_10_req_in), - .floo_rsp_o (router_20_10_rsp_out), - .floo_req_o (router_20_10_req_out), - .floo_rsp_i (router_20_10_rsp_in) -); - - -floo_req_t [4:0] router_20_11_req_in; -floo_rsp_t [4:0] router_20_11_rsp_out; -floo_req_t [4:0] router_20_11_req_out; -floo_rsp_t [4:0] router_20_11_rsp_in; - - assign router_20_11_req_in[0] = router_20_12_to_router_20_11_req; - assign router_20_11_req_in[1] = router_21_11_to_router_20_11_req; - assign router_20_11_req_in[2] = router_20_10_to_router_20_11_req; - assign router_20_11_req_in[3] = router_19_11_to_router_20_11_req; - assign router_20_11_req_in[4] = magia_tile_ni_20_11_to_router_20_11_req; - - assign router_20_11_to_router_20_12_rsp = router_20_11_rsp_out[0]; - assign router_20_11_to_router_21_11_rsp = router_20_11_rsp_out[1]; - assign router_20_11_to_router_20_10_rsp = router_20_11_rsp_out[2]; - assign router_20_11_to_router_19_11_rsp = router_20_11_rsp_out[3]; - assign router_20_11_to_magia_tile_ni_20_11_rsp = router_20_11_rsp_out[4]; - - assign router_20_11_to_router_20_12_req = router_20_11_req_out[0]; - assign router_20_11_to_router_21_11_req = router_20_11_req_out[1]; - assign router_20_11_to_router_20_10_req = router_20_11_req_out[2]; - assign router_20_11_to_router_19_11_req = router_20_11_req_out[3]; - assign router_20_11_to_magia_tile_ni_20_11_req = router_20_11_req_out[4]; - - assign router_20_11_rsp_in[0] = router_20_12_to_router_20_11_rsp; - assign router_20_11_rsp_in[1] = router_21_11_to_router_20_11_rsp; - assign router_20_11_rsp_in[2] = router_20_10_to_router_20_11_rsp; - assign router_20_11_rsp_in[3] = router_19_11_to_router_20_11_rsp; - assign router_20_11_rsp_in[4] = magia_tile_ni_20_11_to_router_20_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_11_req_in), - .floo_rsp_o (router_20_11_rsp_out), - .floo_req_o (router_20_11_req_out), - .floo_rsp_i (router_20_11_rsp_in) -); - - -floo_req_t [4:0] router_20_12_req_in; -floo_rsp_t [4:0] router_20_12_rsp_out; -floo_req_t [4:0] router_20_12_req_out; -floo_rsp_t [4:0] router_20_12_rsp_in; - - assign router_20_12_req_in[0] = router_20_13_to_router_20_12_req; - assign router_20_12_req_in[1] = router_21_12_to_router_20_12_req; - assign router_20_12_req_in[2] = router_20_11_to_router_20_12_req; - assign router_20_12_req_in[3] = router_19_12_to_router_20_12_req; - assign router_20_12_req_in[4] = magia_tile_ni_20_12_to_router_20_12_req; - - assign router_20_12_to_router_20_13_rsp = router_20_12_rsp_out[0]; - assign router_20_12_to_router_21_12_rsp = router_20_12_rsp_out[1]; - assign router_20_12_to_router_20_11_rsp = router_20_12_rsp_out[2]; - assign router_20_12_to_router_19_12_rsp = router_20_12_rsp_out[3]; - assign router_20_12_to_magia_tile_ni_20_12_rsp = router_20_12_rsp_out[4]; - - assign router_20_12_to_router_20_13_req = router_20_12_req_out[0]; - assign router_20_12_to_router_21_12_req = router_20_12_req_out[1]; - assign router_20_12_to_router_20_11_req = router_20_12_req_out[2]; - assign router_20_12_to_router_19_12_req = router_20_12_req_out[3]; - assign router_20_12_to_magia_tile_ni_20_12_req = router_20_12_req_out[4]; - - assign router_20_12_rsp_in[0] = router_20_13_to_router_20_12_rsp; - assign router_20_12_rsp_in[1] = router_21_12_to_router_20_12_rsp; - assign router_20_12_rsp_in[2] = router_20_11_to_router_20_12_rsp; - assign router_20_12_rsp_in[3] = router_19_12_to_router_20_12_rsp; - assign router_20_12_rsp_in[4] = magia_tile_ni_20_12_to_router_20_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_12_req_in), - .floo_rsp_o (router_20_12_rsp_out), - .floo_req_o (router_20_12_req_out), - .floo_rsp_i (router_20_12_rsp_in) -); - - -floo_req_t [4:0] router_20_13_req_in; -floo_rsp_t [4:0] router_20_13_rsp_out; -floo_req_t [4:0] router_20_13_req_out; -floo_rsp_t [4:0] router_20_13_rsp_in; - - assign router_20_13_req_in[0] = router_20_14_to_router_20_13_req; - assign router_20_13_req_in[1] = router_21_13_to_router_20_13_req; - assign router_20_13_req_in[2] = router_20_12_to_router_20_13_req; - assign router_20_13_req_in[3] = router_19_13_to_router_20_13_req; - assign router_20_13_req_in[4] = magia_tile_ni_20_13_to_router_20_13_req; - - assign router_20_13_to_router_20_14_rsp = router_20_13_rsp_out[0]; - assign router_20_13_to_router_21_13_rsp = router_20_13_rsp_out[1]; - assign router_20_13_to_router_20_12_rsp = router_20_13_rsp_out[2]; - assign router_20_13_to_router_19_13_rsp = router_20_13_rsp_out[3]; - assign router_20_13_to_magia_tile_ni_20_13_rsp = router_20_13_rsp_out[4]; - - assign router_20_13_to_router_20_14_req = router_20_13_req_out[0]; - assign router_20_13_to_router_21_13_req = router_20_13_req_out[1]; - assign router_20_13_to_router_20_12_req = router_20_13_req_out[2]; - assign router_20_13_to_router_19_13_req = router_20_13_req_out[3]; - assign router_20_13_to_magia_tile_ni_20_13_req = router_20_13_req_out[4]; - - assign router_20_13_rsp_in[0] = router_20_14_to_router_20_13_rsp; - assign router_20_13_rsp_in[1] = router_21_13_to_router_20_13_rsp; - assign router_20_13_rsp_in[2] = router_20_12_to_router_20_13_rsp; - assign router_20_13_rsp_in[3] = router_19_13_to_router_20_13_rsp; - assign router_20_13_rsp_in[4] = magia_tile_ni_20_13_to_router_20_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_13_req_in), - .floo_rsp_o (router_20_13_rsp_out), - .floo_req_o (router_20_13_req_out), - .floo_rsp_i (router_20_13_rsp_in) -); - - -floo_req_t [4:0] router_20_14_req_in; -floo_rsp_t [4:0] router_20_14_rsp_out; -floo_req_t [4:0] router_20_14_req_out; -floo_rsp_t [4:0] router_20_14_rsp_in; - - assign router_20_14_req_in[0] = router_20_15_to_router_20_14_req; - assign router_20_14_req_in[1] = router_21_14_to_router_20_14_req; - assign router_20_14_req_in[2] = router_20_13_to_router_20_14_req; - assign router_20_14_req_in[3] = router_19_14_to_router_20_14_req; - assign router_20_14_req_in[4] = magia_tile_ni_20_14_to_router_20_14_req; - - assign router_20_14_to_router_20_15_rsp = router_20_14_rsp_out[0]; - assign router_20_14_to_router_21_14_rsp = router_20_14_rsp_out[1]; - assign router_20_14_to_router_20_13_rsp = router_20_14_rsp_out[2]; - assign router_20_14_to_router_19_14_rsp = router_20_14_rsp_out[3]; - assign router_20_14_to_magia_tile_ni_20_14_rsp = router_20_14_rsp_out[4]; - - assign router_20_14_to_router_20_15_req = router_20_14_req_out[0]; - assign router_20_14_to_router_21_14_req = router_20_14_req_out[1]; - assign router_20_14_to_router_20_13_req = router_20_14_req_out[2]; - assign router_20_14_to_router_19_14_req = router_20_14_req_out[3]; - assign router_20_14_to_magia_tile_ni_20_14_req = router_20_14_req_out[4]; - - assign router_20_14_rsp_in[0] = router_20_15_to_router_20_14_rsp; - assign router_20_14_rsp_in[1] = router_21_14_to_router_20_14_rsp; - assign router_20_14_rsp_in[2] = router_20_13_to_router_20_14_rsp; - assign router_20_14_rsp_in[3] = router_19_14_to_router_20_14_rsp; - assign router_20_14_rsp_in[4] = magia_tile_ni_20_14_to_router_20_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_14_req_in), - .floo_rsp_o (router_20_14_rsp_out), - .floo_req_o (router_20_14_req_out), - .floo_rsp_i (router_20_14_rsp_in) -); - - -floo_req_t [4:0] router_20_15_req_in; -floo_rsp_t [4:0] router_20_15_rsp_out; -floo_req_t [4:0] router_20_15_req_out; -floo_rsp_t [4:0] router_20_15_rsp_in; - - assign router_20_15_req_in[0] = router_20_16_to_router_20_15_req; - assign router_20_15_req_in[1] = router_21_15_to_router_20_15_req; - assign router_20_15_req_in[2] = router_20_14_to_router_20_15_req; - assign router_20_15_req_in[3] = router_19_15_to_router_20_15_req; - assign router_20_15_req_in[4] = magia_tile_ni_20_15_to_router_20_15_req; - - assign router_20_15_to_router_20_16_rsp = router_20_15_rsp_out[0]; - assign router_20_15_to_router_21_15_rsp = router_20_15_rsp_out[1]; - assign router_20_15_to_router_20_14_rsp = router_20_15_rsp_out[2]; - assign router_20_15_to_router_19_15_rsp = router_20_15_rsp_out[3]; - assign router_20_15_to_magia_tile_ni_20_15_rsp = router_20_15_rsp_out[4]; - - assign router_20_15_to_router_20_16_req = router_20_15_req_out[0]; - assign router_20_15_to_router_21_15_req = router_20_15_req_out[1]; - assign router_20_15_to_router_20_14_req = router_20_15_req_out[2]; - assign router_20_15_to_router_19_15_req = router_20_15_req_out[3]; - assign router_20_15_to_magia_tile_ni_20_15_req = router_20_15_req_out[4]; - - assign router_20_15_rsp_in[0] = router_20_16_to_router_20_15_rsp; - assign router_20_15_rsp_in[1] = router_21_15_to_router_20_15_rsp; - assign router_20_15_rsp_in[2] = router_20_14_to_router_20_15_rsp; - assign router_20_15_rsp_in[3] = router_19_15_to_router_20_15_rsp; - assign router_20_15_rsp_in[4] = magia_tile_ni_20_15_to_router_20_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_15_req_in), - .floo_rsp_o (router_20_15_rsp_out), - .floo_req_o (router_20_15_req_out), - .floo_rsp_i (router_20_15_rsp_in) -); - - -floo_req_t [4:0] router_20_16_req_in; -floo_rsp_t [4:0] router_20_16_rsp_out; -floo_req_t [4:0] router_20_16_req_out; -floo_rsp_t [4:0] router_20_16_rsp_in; - - assign router_20_16_req_in[0] = router_20_17_to_router_20_16_req; - assign router_20_16_req_in[1] = router_21_16_to_router_20_16_req; - assign router_20_16_req_in[2] = router_20_15_to_router_20_16_req; - assign router_20_16_req_in[3] = router_19_16_to_router_20_16_req; - assign router_20_16_req_in[4] = magia_tile_ni_20_16_to_router_20_16_req; - - assign router_20_16_to_router_20_17_rsp = router_20_16_rsp_out[0]; - assign router_20_16_to_router_21_16_rsp = router_20_16_rsp_out[1]; - assign router_20_16_to_router_20_15_rsp = router_20_16_rsp_out[2]; - assign router_20_16_to_router_19_16_rsp = router_20_16_rsp_out[3]; - assign router_20_16_to_magia_tile_ni_20_16_rsp = router_20_16_rsp_out[4]; - - assign router_20_16_to_router_20_17_req = router_20_16_req_out[0]; - assign router_20_16_to_router_21_16_req = router_20_16_req_out[1]; - assign router_20_16_to_router_20_15_req = router_20_16_req_out[2]; - assign router_20_16_to_router_19_16_req = router_20_16_req_out[3]; - assign router_20_16_to_magia_tile_ni_20_16_req = router_20_16_req_out[4]; - - assign router_20_16_rsp_in[0] = router_20_17_to_router_20_16_rsp; - assign router_20_16_rsp_in[1] = router_21_16_to_router_20_16_rsp; - assign router_20_16_rsp_in[2] = router_20_15_to_router_20_16_rsp; - assign router_20_16_rsp_in[3] = router_19_16_to_router_20_16_rsp; - assign router_20_16_rsp_in[4] = magia_tile_ni_20_16_to_router_20_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_16_req_in), - .floo_rsp_o (router_20_16_rsp_out), - .floo_req_o (router_20_16_req_out), - .floo_rsp_i (router_20_16_rsp_in) -); - - -floo_req_t [4:0] router_20_17_req_in; -floo_rsp_t [4:0] router_20_17_rsp_out; -floo_req_t [4:0] router_20_17_req_out; -floo_rsp_t [4:0] router_20_17_rsp_in; - - assign router_20_17_req_in[0] = router_20_18_to_router_20_17_req; - assign router_20_17_req_in[1] = router_21_17_to_router_20_17_req; - assign router_20_17_req_in[2] = router_20_16_to_router_20_17_req; - assign router_20_17_req_in[3] = router_19_17_to_router_20_17_req; - assign router_20_17_req_in[4] = magia_tile_ni_20_17_to_router_20_17_req; - - assign router_20_17_to_router_20_18_rsp = router_20_17_rsp_out[0]; - assign router_20_17_to_router_21_17_rsp = router_20_17_rsp_out[1]; - assign router_20_17_to_router_20_16_rsp = router_20_17_rsp_out[2]; - assign router_20_17_to_router_19_17_rsp = router_20_17_rsp_out[3]; - assign router_20_17_to_magia_tile_ni_20_17_rsp = router_20_17_rsp_out[4]; - - assign router_20_17_to_router_20_18_req = router_20_17_req_out[0]; - assign router_20_17_to_router_21_17_req = router_20_17_req_out[1]; - assign router_20_17_to_router_20_16_req = router_20_17_req_out[2]; - assign router_20_17_to_router_19_17_req = router_20_17_req_out[3]; - assign router_20_17_to_magia_tile_ni_20_17_req = router_20_17_req_out[4]; - - assign router_20_17_rsp_in[0] = router_20_18_to_router_20_17_rsp; - assign router_20_17_rsp_in[1] = router_21_17_to_router_20_17_rsp; - assign router_20_17_rsp_in[2] = router_20_16_to_router_20_17_rsp; - assign router_20_17_rsp_in[3] = router_19_17_to_router_20_17_rsp; - assign router_20_17_rsp_in[4] = magia_tile_ni_20_17_to_router_20_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_17_req_in), - .floo_rsp_o (router_20_17_rsp_out), - .floo_req_o (router_20_17_req_out), - .floo_rsp_i (router_20_17_rsp_in) -); - - -floo_req_t [4:0] router_20_18_req_in; -floo_rsp_t [4:0] router_20_18_rsp_out; -floo_req_t [4:0] router_20_18_req_out; -floo_rsp_t [4:0] router_20_18_rsp_in; - - assign router_20_18_req_in[0] = router_20_19_to_router_20_18_req; - assign router_20_18_req_in[1] = router_21_18_to_router_20_18_req; - assign router_20_18_req_in[2] = router_20_17_to_router_20_18_req; - assign router_20_18_req_in[3] = router_19_18_to_router_20_18_req; - assign router_20_18_req_in[4] = magia_tile_ni_20_18_to_router_20_18_req; - - assign router_20_18_to_router_20_19_rsp = router_20_18_rsp_out[0]; - assign router_20_18_to_router_21_18_rsp = router_20_18_rsp_out[1]; - assign router_20_18_to_router_20_17_rsp = router_20_18_rsp_out[2]; - assign router_20_18_to_router_19_18_rsp = router_20_18_rsp_out[3]; - assign router_20_18_to_magia_tile_ni_20_18_rsp = router_20_18_rsp_out[4]; - - assign router_20_18_to_router_20_19_req = router_20_18_req_out[0]; - assign router_20_18_to_router_21_18_req = router_20_18_req_out[1]; - assign router_20_18_to_router_20_17_req = router_20_18_req_out[2]; - assign router_20_18_to_router_19_18_req = router_20_18_req_out[3]; - assign router_20_18_to_magia_tile_ni_20_18_req = router_20_18_req_out[4]; - - assign router_20_18_rsp_in[0] = router_20_19_to_router_20_18_rsp; - assign router_20_18_rsp_in[1] = router_21_18_to_router_20_18_rsp; - assign router_20_18_rsp_in[2] = router_20_17_to_router_20_18_rsp; - assign router_20_18_rsp_in[3] = router_19_18_to_router_20_18_rsp; - assign router_20_18_rsp_in[4] = magia_tile_ni_20_18_to_router_20_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_18_req_in), - .floo_rsp_o (router_20_18_rsp_out), - .floo_req_o (router_20_18_req_out), - .floo_rsp_i (router_20_18_rsp_in) -); - - -floo_req_t [4:0] router_20_19_req_in; -floo_rsp_t [4:0] router_20_19_rsp_out; -floo_req_t [4:0] router_20_19_req_out; -floo_rsp_t [4:0] router_20_19_rsp_in; - - assign router_20_19_req_in[0] = router_20_20_to_router_20_19_req; - assign router_20_19_req_in[1] = router_21_19_to_router_20_19_req; - assign router_20_19_req_in[2] = router_20_18_to_router_20_19_req; - assign router_20_19_req_in[3] = router_19_19_to_router_20_19_req; - assign router_20_19_req_in[4] = magia_tile_ni_20_19_to_router_20_19_req; - - assign router_20_19_to_router_20_20_rsp = router_20_19_rsp_out[0]; - assign router_20_19_to_router_21_19_rsp = router_20_19_rsp_out[1]; - assign router_20_19_to_router_20_18_rsp = router_20_19_rsp_out[2]; - assign router_20_19_to_router_19_19_rsp = router_20_19_rsp_out[3]; - assign router_20_19_to_magia_tile_ni_20_19_rsp = router_20_19_rsp_out[4]; - - assign router_20_19_to_router_20_20_req = router_20_19_req_out[0]; - assign router_20_19_to_router_21_19_req = router_20_19_req_out[1]; - assign router_20_19_to_router_20_18_req = router_20_19_req_out[2]; - assign router_20_19_to_router_19_19_req = router_20_19_req_out[3]; - assign router_20_19_to_magia_tile_ni_20_19_req = router_20_19_req_out[4]; - - assign router_20_19_rsp_in[0] = router_20_20_to_router_20_19_rsp; - assign router_20_19_rsp_in[1] = router_21_19_to_router_20_19_rsp; - assign router_20_19_rsp_in[2] = router_20_18_to_router_20_19_rsp; - assign router_20_19_rsp_in[3] = router_19_19_to_router_20_19_rsp; - assign router_20_19_rsp_in[4] = magia_tile_ni_20_19_to_router_20_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_19_req_in), - .floo_rsp_o (router_20_19_rsp_out), - .floo_req_o (router_20_19_req_out), - .floo_rsp_i (router_20_19_rsp_in) -); - - -floo_req_t [4:0] router_20_20_req_in; -floo_rsp_t [4:0] router_20_20_rsp_out; -floo_req_t [4:0] router_20_20_req_out; -floo_rsp_t [4:0] router_20_20_rsp_in; - - assign router_20_20_req_in[0] = router_20_21_to_router_20_20_req; - assign router_20_20_req_in[1] = router_21_20_to_router_20_20_req; - assign router_20_20_req_in[2] = router_20_19_to_router_20_20_req; - assign router_20_20_req_in[3] = router_19_20_to_router_20_20_req; - assign router_20_20_req_in[4] = magia_tile_ni_20_20_to_router_20_20_req; - - assign router_20_20_to_router_20_21_rsp = router_20_20_rsp_out[0]; - assign router_20_20_to_router_21_20_rsp = router_20_20_rsp_out[1]; - assign router_20_20_to_router_20_19_rsp = router_20_20_rsp_out[2]; - assign router_20_20_to_router_19_20_rsp = router_20_20_rsp_out[3]; - assign router_20_20_to_magia_tile_ni_20_20_rsp = router_20_20_rsp_out[4]; - - assign router_20_20_to_router_20_21_req = router_20_20_req_out[0]; - assign router_20_20_to_router_21_20_req = router_20_20_req_out[1]; - assign router_20_20_to_router_20_19_req = router_20_20_req_out[2]; - assign router_20_20_to_router_19_20_req = router_20_20_req_out[3]; - assign router_20_20_to_magia_tile_ni_20_20_req = router_20_20_req_out[4]; - - assign router_20_20_rsp_in[0] = router_20_21_to_router_20_20_rsp; - assign router_20_20_rsp_in[1] = router_21_20_to_router_20_20_rsp; - assign router_20_20_rsp_in[2] = router_20_19_to_router_20_20_rsp; - assign router_20_20_rsp_in[3] = router_19_20_to_router_20_20_rsp; - assign router_20_20_rsp_in[4] = magia_tile_ni_20_20_to_router_20_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_20_req_in), - .floo_rsp_o (router_20_20_rsp_out), - .floo_req_o (router_20_20_req_out), - .floo_rsp_i (router_20_20_rsp_in) -); - - -floo_req_t [4:0] router_20_21_req_in; -floo_rsp_t [4:0] router_20_21_rsp_out; -floo_req_t [4:0] router_20_21_req_out; -floo_rsp_t [4:0] router_20_21_rsp_in; - - assign router_20_21_req_in[0] = router_20_22_to_router_20_21_req; - assign router_20_21_req_in[1] = router_21_21_to_router_20_21_req; - assign router_20_21_req_in[2] = router_20_20_to_router_20_21_req; - assign router_20_21_req_in[3] = router_19_21_to_router_20_21_req; - assign router_20_21_req_in[4] = magia_tile_ni_20_21_to_router_20_21_req; - - assign router_20_21_to_router_20_22_rsp = router_20_21_rsp_out[0]; - assign router_20_21_to_router_21_21_rsp = router_20_21_rsp_out[1]; - assign router_20_21_to_router_20_20_rsp = router_20_21_rsp_out[2]; - assign router_20_21_to_router_19_21_rsp = router_20_21_rsp_out[3]; - assign router_20_21_to_magia_tile_ni_20_21_rsp = router_20_21_rsp_out[4]; - - assign router_20_21_to_router_20_22_req = router_20_21_req_out[0]; - assign router_20_21_to_router_21_21_req = router_20_21_req_out[1]; - assign router_20_21_to_router_20_20_req = router_20_21_req_out[2]; - assign router_20_21_to_router_19_21_req = router_20_21_req_out[3]; - assign router_20_21_to_magia_tile_ni_20_21_req = router_20_21_req_out[4]; - - assign router_20_21_rsp_in[0] = router_20_22_to_router_20_21_rsp; - assign router_20_21_rsp_in[1] = router_21_21_to_router_20_21_rsp; - assign router_20_21_rsp_in[2] = router_20_20_to_router_20_21_rsp; - assign router_20_21_rsp_in[3] = router_19_21_to_router_20_21_rsp; - assign router_20_21_rsp_in[4] = magia_tile_ni_20_21_to_router_20_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_21_req_in), - .floo_rsp_o (router_20_21_rsp_out), - .floo_req_o (router_20_21_req_out), - .floo_rsp_i (router_20_21_rsp_in) -); - - -floo_req_t [4:0] router_20_22_req_in; -floo_rsp_t [4:0] router_20_22_rsp_out; -floo_req_t [4:0] router_20_22_req_out; -floo_rsp_t [4:0] router_20_22_rsp_in; - - assign router_20_22_req_in[0] = router_20_23_to_router_20_22_req; - assign router_20_22_req_in[1] = router_21_22_to_router_20_22_req; - assign router_20_22_req_in[2] = router_20_21_to_router_20_22_req; - assign router_20_22_req_in[3] = router_19_22_to_router_20_22_req; - assign router_20_22_req_in[4] = magia_tile_ni_20_22_to_router_20_22_req; - - assign router_20_22_to_router_20_23_rsp = router_20_22_rsp_out[0]; - assign router_20_22_to_router_21_22_rsp = router_20_22_rsp_out[1]; - assign router_20_22_to_router_20_21_rsp = router_20_22_rsp_out[2]; - assign router_20_22_to_router_19_22_rsp = router_20_22_rsp_out[3]; - assign router_20_22_to_magia_tile_ni_20_22_rsp = router_20_22_rsp_out[4]; - - assign router_20_22_to_router_20_23_req = router_20_22_req_out[0]; - assign router_20_22_to_router_21_22_req = router_20_22_req_out[1]; - assign router_20_22_to_router_20_21_req = router_20_22_req_out[2]; - assign router_20_22_to_router_19_22_req = router_20_22_req_out[3]; - assign router_20_22_to_magia_tile_ni_20_22_req = router_20_22_req_out[4]; - - assign router_20_22_rsp_in[0] = router_20_23_to_router_20_22_rsp; - assign router_20_22_rsp_in[1] = router_21_22_to_router_20_22_rsp; - assign router_20_22_rsp_in[2] = router_20_21_to_router_20_22_rsp; - assign router_20_22_rsp_in[3] = router_19_22_to_router_20_22_rsp; - assign router_20_22_rsp_in[4] = magia_tile_ni_20_22_to_router_20_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_22_req_in), - .floo_rsp_o (router_20_22_rsp_out), - .floo_req_o (router_20_22_req_out), - .floo_rsp_i (router_20_22_rsp_in) -); - - -floo_req_t [4:0] router_20_23_req_in; -floo_rsp_t [4:0] router_20_23_rsp_out; -floo_req_t [4:0] router_20_23_req_out; -floo_rsp_t [4:0] router_20_23_rsp_in; - - assign router_20_23_req_in[0] = router_20_24_to_router_20_23_req; - assign router_20_23_req_in[1] = router_21_23_to_router_20_23_req; - assign router_20_23_req_in[2] = router_20_22_to_router_20_23_req; - assign router_20_23_req_in[3] = router_19_23_to_router_20_23_req; - assign router_20_23_req_in[4] = magia_tile_ni_20_23_to_router_20_23_req; - - assign router_20_23_to_router_20_24_rsp = router_20_23_rsp_out[0]; - assign router_20_23_to_router_21_23_rsp = router_20_23_rsp_out[1]; - assign router_20_23_to_router_20_22_rsp = router_20_23_rsp_out[2]; - assign router_20_23_to_router_19_23_rsp = router_20_23_rsp_out[3]; - assign router_20_23_to_magia_tile_ni_20_23_rsp = router_20_23_rsp_out[4]; - - assign router_20_23_to_router_20_24_req = router_20_23_req_out[0]; - assign router_20_23_to_router_21_23_req = router_20_23_req_out[1]; - assign router_20_23_to_router_20_22_req = router_20_23_req_out[2]; - assign router_20_23_to_router_19_23_req = router_20_23_req_out[3]; - assign router_20_23_to_magia_tile_ni_20_23_req = router_20_23_req_out[4]; - - assign router_20_23_rsp_in[0] = router_20_24_to_router_20_23_rsp; - assign router_20_23_rsp_in[1] = router_21_23_to_router_20_23_rsp; - assign router_20_23_rsp_in[2] = router_20_22_to_router_20_23_rsp; - assign router_20_23_rsp_in[3] = router_19_23_to_router_20_23_rsp; - assign router_20_23_rsp_in[4] = magia_tile_ni_20_23_to_router_20_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_23_req_in), - .floo_rsp_o (router_20_23_rsp_out), - .floo_req_o (router_20_23_req_out), - .floo_rsp_i (router_20_23_rsp_in) -); - - -floo_req_t [4:0] router_20_24_req_in; -floo_rsp_t [4:0] router_20_24_rsp_out; -floo_req_t [4:0] router_20_24_req_out; -floo_rsp_t [4:0] router_20_24_rsp_in; - - assign router_20_24_req_in[0] = router_20_25_to_router_20_24_req; - assign router_20_24_req_in[1] = router_21_24_to_router_20_24_req; - assign router_20_24_req_in[2] = router_20_23_to_router_20_24_req; - assign router_20_24_req_in[3] = router_19_24_to_router_20_24_req; - assign router_20_24_req_in[4] = magia_tile_ni_20_24_to_router_20_24_req; - - assign router_20_24_to_router_20_25_rsp = router_20_24_rsp_out[0]; - assign router_20_24_to_router_21_24_rsp = router_20_24_rsp_out[1]; - assign router_20_24_to_router_20_23_rsp = router_20_24_rsp_out[2]; - assign router_20_24_to_router_19_24_rsp = router_20_24_rsp_out[3]; - assign router_20_24_to_magia_tile_ni_20_24_rsp = router_20_24_rsp_out[4]; - - assign router_20_24_to_router_20_25_req = router_20_24_req_out[0]; - assign router_20_24_to_router_21_24_req = router_20_24_req_out[1]; - assign router_20_24_to_router_20_23_req = router_20_24_req_out[2]; - assign router_20_24_to_router_19_24_req = router_20_24_req_out[3]; - assign router_20_24_to_magia_tile_ni_20_24_req = router_20_24_req_out[4]; - - assign router_20_24_rsp_in[0] = router_20_25_to_router_20_24_rsp; - assign router_20_24_rsp_in[1] = router_21_24_to_router_20_24_rsp; - assign router_20_24_rsp_in[2] = router_20_23_to_router_20_24_rsp; - assign router_20_24_rsp_in[3] = router_19_24_to_router_20_24_rsp; - assign router_20_24_rsp_in[4] = magia_tile_ni_20_24_to_router_20_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_24_req_in), - .floo_rsp_o (router_20_24_rsp_out), - .floo_req_o (router_20_24_req_out), - .floo_rsp_i (router_20_24_rsp_in) -); - - -floo_req_t [4:0] router_20_25_req_in; -floo_rsp_t [4:0] router_20_25_rsp_out; -floo_req_t [4:0] router_20_25_req_out; -floo_rsp_t [4:0] router_20_25_rsp_in; - - assign router_20_25_req_in[0] = router_20_26_to_router_20_25_req; - assign router_20_25_req_in[1] = router_21_25_to_router_20_25_req; - assign router_20_25_req_in[2] = router_20_24_to_router_20_25_req; - assign router_20_25_req_in[3] = router_19_25_to_router_20_25_req; - assign router_20_25_req_in[4] = magia_tile_ni_20_25_to_router_20_25_req; - - assign router_20_25_to_router_20_26_rsp = router_20_25_rsp_out[0]; - assign router_20_25_to_router_21_25_rsp = router_20_25_rsp_out[1]; - assign router_20_25_to_router_20_24_rsp = router_20_25_rsp_out[2]; - assign router_20_25_to_router_19_25_rsp = router_20_25_rsp_out[3]; - assign router_20_25_to_magia_tile_ni_20_25_rsp = router_20_25_rsp_out[4]; - - assign router_20_25_to_router_20_26_req = router_20_25_req_out[0]; - assign router_20_25_to_router_21_25_req = router_20_25_req_out[1]; - assign router_20_25_to_router_20_24_req = router_20_25_req_out[2]; - assign router_20_25_to_router_19_25_req = router_20_25_req_out[3]; - assign router_20_25_to_magia_tile_ni_20_25_req = router_20_25_req_out[4]; - - assign router_20_25_rsp_in[0] = router_20_26_to_router_20_25_rsp; - assign router_20_25_rsp_in[1] = router_21_25_to_router_20_25_rsp; - assign router_20_25_rsp_in[2] = router_20_24_to_router_20_25_rsp; - assign router_20_25_rsp_in[3] = router_19_25_to_router_20_25_rsp; - assign router_20_25_rsp_in[4] = magia_tile_ni_20_25_to_router_20_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_25_req_in), - .floo_rsp_o (router_20_25_rsp_out), - .floo_req_o (router_20_25_req_out), - .floo_rsp_i (router_20_25_rsp_in) -); - - -floo_req_t [4:0] router_20_26_req_in; -floo_rsp_t [4:0] router_20_26_rsp_out; -floo_req_t [4:0] router_20_26_req_out; -floo_rsp_t [4:0] router_20_26_rsp_in; - - assign router_20_26_req_in[0] = router_20_27_to_router_20_26_req; - assign router_20_26_req_in[1] = router_21_26_to_router_20_26_req; - assign router_20_26_req_in[2] = router_20_25_to_router_20_26_req; - assign router_20_26_req_in[3] = router_19_26_to_router_20_26_req; - assign router_20_26_req_in[4] = magia_tile_ni_20_26_to_router_20_26_req; - - assign router_20_26_to_router_20_27_rsp = router_20_26_rsp_out[0]; - assign router_20_26_to_router_21_26_rsp = router_20_26_rsp_out[1]; - assign router_20_26_to_router_20_25_rsp = router_20_26_rsp_out[2]; - assign router_20_26_to_router_19_26_rsp = router_20_26_rsp_out[3]; - assign router_20_26_to_magia_tile_ni_20_26_rsp = router_20_26_rsp_out[4]; - - assign router_20_26_to_router_20_27_req = router_20_26_req_out[0]; - assign router_20_26_to_router_21_26_req = router_20_26_req_out[1]; - assign router_20_26_to_router_20_25_req = router_20_26_req_out[2]; - assign router_20_26_to_router_19_26_req = router_20_26_req_out[3]; - assign router_20_26_to_magia_tile_ni_20_26_req = router_20_26_req_out[4]; - - assign router_20_26_rsp_in[0] = router_20_27_to_router_20_26_rsp; - assign router_20_26_rsp_in[1] = router_21_26_to_router_20_26_rsp; - assign router_20_26_rsp_in[2] = router_20_25_to_router_20_26_rsp; - assign router_20_26_rsp_in[3] = router_19_26_to_router_20_26_rsp; - assign router_20_26_rsp_in[4] = magia_tile_ni_20_26_to_router_20_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_26_req_in), - .floo_rsp_o (router_20_26_rsp_out), - .floo_req_o (router_20_26_req_out), - .floo_rsp_i (router_20_26_rsp_in) -); - - -floo_req_t [4:0] router_20_27_req_in; -floo_rsp_t [4:0] router_20_27_rsp_out; -floo_req_t [4:0] router_20_27_req_out; -floo_rsp_t [4:0] router_20_27_rsp_in; - - assign router_20_27_req_in[0] = router_20_28_to_router_20_27_req; - assign router_20_27_req_in[1] = router_21_27_to_router_20_27_req; - assign router_20_27_req_in[2] = router_20_26_to_router_20_27_req; - assign router_20_27_req_in[3] = router_19_27_to_router_20_27_req; - assign router_20_27_req_in[4] = magia_tile_ni_20_27_to_router_20_27_req; - - assign router_20_27_to_router_20_28_rsp = router_20_27_rsp_out[0]; - assign router_20_27_to_router_21_27_rsp = router_20_27_rsp_out[1]; - assign router_20_27_to_router_20_26_rsp = router_20_27_rsp_out[2]; - assign router_20_27_to_router_19_27_rsp = router_20_27_rsp_out[3]; - assign router_20_27_to_magia_tile_ni_20_27_rsp = router_20_27_rsp_out[4]; - - assign router_20_27_to_router_20_28_req = router_20_27_req_out[0]; - assign router_20_27_to_router_21_27_req = router_20_27_req_out[1]; - assign router_20_27_to_router_20_26_req = router_20_27_req_out[2]; - assign router_20_27_to_router_19_27_req = router_20_27_req_out[3]; - assign router_20_27_to_magia_tile_ni_20_27_req = router_20_27_req_out[4]; - - assign router_20_27_rsp_in[0] = router_20_28_to_router_20_27_rsp; - assign router_20_27_rsp_in[1] = router_21_27_to_router_20_27_rsp; - assign router_20_27_rsp_in[2] = router_20_26_to_router_20_27_rsp; - assign router_20_27_rsp_in[3] = router_19_27_to_router_20_27_rsp; - assign router_20_27_rsp_in[4] = magia_tile_ni_20_27_to_router_20_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_27_req_in), - .floo_rsp_o (router_20_27_rsp_out), - .floo_req_o (router_20_27_req_out), - .floo_rsp_i (router_20_27_rsp_in) -); - - -floo_req_t [4:0] router_20_28_req_in; -floo_rsp_t [4:0] router_20_28_rsp_out; -floo_req_t [4:0] router_20_28_req_out; -floo_rsp_t [4:0] router_20_28_rsp_in; - - assign router_20_28_req_in[0] = router_20_29_to_router_20_28_req; - assign router_20_28_req_in[1] = router_21_28_to_router_20_28_req; - assign router_20_28_req_in[2] = router_20_27_to_router_20_28_req; - assign router_20_28_req_in[3] = router_19_28_to_router_20_28_req; - assign router_20_28_req_in[4] = magia_tile_ni_20_28_to_router_20_28_req; - - assign router_20_28_to_router_20_29_rsp = router_20_28_rsp_out[0]; - assign router_20_28_to_router_21_28_rsp = router_20_28_rsp_out[1]; - assign router_20_28_to_router_20_27_rsp = router_20_28_rsp_out[2]; - assign router_20_28_to_router_19_28_rsp = router_20_28_rsp_out[3]; - assign router_20_28_to_magia_tile_ni_20_28_rsp = router_20_28_rsp_out[4]; - - assign router_20_28_to_router_20_29_req = router_20_28_req_out[0]; - assign router_20_28_to_router_21_28_req = router_20_28_req_out[1]; - assign router_20_28_to_router_20_27_req = router_20_28_req_out[2]; - assign router_20_28_to_router_19_28_req = router_20_28_req_out[3]; - assign router_20_28_to_magia_tile_ni_20_28_req = router_20_28_req_out[4]; - - assign router_20_28_rsp_in[0] = router_20_29_to_router_20_28_rsp; - assign router_20_28_rsp_in[1] = router_21_28_to_router_20_28_rsp; - assign router_20_28_rsp_in[2] = router_20_27_to_router_20_28_rsp; - assign router_20_28_rsp_in[3] = router_19_28_to_router_20_28_rsp; - assign router_20_28_rsp_in[4] = magia_tile_ni_20_28_to_router_20_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_28_req_in), - .floo_rsp_o (router_20_28_rsp_out), - .floo_req_o (router_20_28_req_out), - .floo_rsp_i (router_20_28_rsp_in) -); - - -floo_req_t [4:0] router_20_29_req_in; -floo_rsp_t [4:0] router_20_29_rsp_out; -floo_req_t [4:0] router_20_29_req_out; -floo_rsp_t [4:0] router_20_29_rsp_in; - - assign router_20_29_req_in[0] = router_20_30_to_router_20_29_req; - assign router_20_29_req_in[1] = router_21_29_to_router_20_29_req; - assign router_20_29_req_in[2] = router_20_28_to_router_20_29_req; - assign router_20_29_req_in[3] = router_19_29_to_router_20_29_req; - assign router_20_29_req_in[4] = magia_tile_ni_20_29_to_router_20_29_req; - - assign router_20_29_to_router_20_30_rsp = router_20_29_rsp_out[0]; - assign router_20_29_to_router_21_29_rsp = router_20_29_rsp_out[1]; - assign router_20_29_to_router_20_28_rsp = router_20_29_rsp_out[2]; - assign router_20_29_to_router_19_29_rsp = router_20_29_rsp_out[3]; - assign router_20_29_to_magia_tile_ni_20_29_rsp = router_20_29_rsp_out[4]; - - assign router_20_29_to_router_20_30_req = router_20_29_req_out[0]; - assign router_20_29_to_router_21_29_req = router_20_29_req_out[1]; - assign router_20_29_to_router_20_28_req = router_20_29_req_out[2]; - assign router_20_29_to_router_19_29_req = router_20_29_req_out[3]; - assign router_20_29_to_magia_tile_ni_20_29_req = router_20_29_req_out[4]; - - assign router_20_29_rsp_in[0] = router_20_30_to_router_20_29_rsp; - assign router_20_29_rsp_in[1] = router_21_29_to_router_20_29_rsp; - assign router_20_29_rsp_in[2] = router_20_28_to_router_20_29_rsp; - assign router_20_29_rsp_in[3] = router_19_29_to_router_20_29_rsp; - assign router_20_29_rsp_in[4] = magia_tile_ni_20_29_to_router_20_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_29_req_in), - .floo_rsp_o (router_20_29_rsp_out), - .floo_req_o (router_20_29_req_out), - .floo_rsp_i (router_20_29_rsp_in) -); - - -floo_req_t [4:0] router_20_30_req_in; -floo_rsp_t [4:0] router_20_30_rsp_out; -floo_req_t [4:0] router_20_30_req_out; -floo_rsp_t [4:0] router_20_30_rsp_in; - - assign router_20_30_req_in[0] = router_20_31_to_router_20_30_req; - assign router_20_30_req_in[1] = router_21_30_to_router_20_30_req; - assign router_20_30_req_in[2] = router_20_29_to_router_20_30_req; - assign router_20_30_req_in[3] = router_19_30_to_router_20_30_req; - assign router_20_30_req_in[4] = magia_tile_ni_20_30_to_router_20_30_req; - - assign router_20_30_to_router_20_31_rsp = router_20_30_rsp_out[0]; - assign router_20_30_to_router_21_30_rsp = router_20_30_rsp_out[1]; - assign router_20_30_to_router_20_29_rsp = router_20_30_rsp_out[2]; - assign router_20_30_to_router_19_30_rsp = router_20_30_rsp_out[3]; - assign router_20_30_to_magia_tile_ni_20_30_rsp = router_20_30_rsp_out[4]; - - assign router_20_30_to_router_20_31_req = router_20_30_req_out[0]; - assign router_20_30_to_router_21_30_req = router_20_30_req_out[1]; - assign router_20_30_to_router_20_29_req = router_20_30_req_out[2]; - assign router_20_30_to_router_19_30_req = router_20_30_req_out[3]; - assign router_20_30_to_magia_tile_ni_20_30_req = router_20_30_req_out[4]; - - assign router_20_30_rsp_in[0] = router_20_31_to_router_20_30_rsp; - assign router_20_30_rsp_in[1] = router_21_30_to_router_20_30_rsp; - assign router_20_30_rsp_in[2] = router_20_29_to_router_20_30_rsp; - assign router_20_30_rsp_in[3] = router_19_30_to_router_20_30_rsp; - assign router_20_30_rsp_in[4] = magia_tile_ni_20_30_to_router_20_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_30_req_in), - .floo_rsp_o (router_20_30_rsp_out), - .floo_req_o (router_20_30_req_out), - .floo_rsp_i (router_20_30_rsp_in) -); - - -floo_req_t [4:0] router_20_31_req_in; -floo_rsp_t [4:0] router_20_31_rsp_out; -floo_req_t [4:0] router_20_31_req_out; -floo_rsp_t [4:0] router_20_31_rsp_in; - - assign router_20_31_req_in[0] = '0; - assign router_20_31_req_in[1] = router_21_31_to_router_20_31_req; - assign router_20_31_req_in[2] = router_20_30_to_router_20_31_req; - assign router_20_31_req_in[3] = router_19_31_to_router_20_31_req; - assign router_20_31_req_in[4] = magia_tile_ni_20_31_to_router_20_31_req; - - assign router_20_31_to_router_21_31_rsp = router_20_31_rsp_out[1]; - assign router_20_31_to_router_20_30_rsp = router_20_31_rsp_out[2]; - assign router_20_31_to_router_19_31_rsp = router_20_31_rsp_out[3]; - assign router_20_31_to_magia_tile_ni_20_31_rsp = router_20_31_rsp_out[4]; - - assign router_20_31_to_router_21_31_req = router_20_31_req_out[1]; - assign router_20_31_to_router_20_30_req = router_20_31_req_out[2]; - assign router_20_31_to_router_19_31_req = router_20_31_req_out[3]; - assign router_20_31_to_magia_tile_ni_20_31_req = router_20_31_req_out[4]; - - assign router_20_31_rsp_in[0] = '0; - assign router_20_31_rsp_in[1] = router_21_31_to_router_20_31_rsp; - assign router_20_31_rsp_in[2] = router_20_30_to_router_20_31_rsp; - assign router_20_31_rsp_in[3] = router_19_31_to_router_20_31_rsp; - assign router_20_31_rsp_in[4] = magia_tile_ni_20_31_to_router_20_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_20_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 21, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_20_31_req_in), - .floo_rsp_o (router_20_31_rsp_out), - .floo_req_o (router_20_31_req_out), - .floo_rsp_i (router_20_31_rsp_in) -); - - -floo_req_t [4:0] router_21_0_req_in; -floo_rsp_t [4:0] router_21_0_rsp_out; -floo_req_t [4:0] router_21_0_req_out; -floo_rsp_t [4:0] router_21_0_rsp_in; - - assign router_21_0_req_in[0] = router_21_1_to_router_21_0_req; - assign router_21_0_req_in[1] = router_22_0_to_router_21_0_req; - assign router_21_0_req_in[2] = '0; - assign router_21_0_req_in[3] = router_20_0_to_router_21_0_req; - assign router_21_0_req_in[4] = magia_tile_ni_21_0_to_router_21_0_req; - - assign router_21_0_to_router_21_1_rsp = router_21_0_rsp_out[0]; - assign router_21_0_to_router_22_0_rsp = router_21_0_rsp_out[1]; - assign router_21_0_to_router_20_0_rsp = router_21_0_rsp_out[3]; - assign router_21_0_to_magia_tile_ni_21_0_rsp = router_21_0_rsp_out[4]; - - assign router_21_0_to_router_21_1_req = router_21_0_req_out[0]; - assign router_21_0_to_router_22_0_req = router_21_0_req_out[1]; - assign router_21_0_to_router_20_0_req = router_21_0_req_out[3]; - assign router_21_0_to_magia_tile_ni_21_0_req = router_21_0_req_out[4]; - - assign router_21_0_rsp_in[0] = router_21_1_to_router_21_0_rsp; - assign router_21_0_rsp_in[1] = router_22_0_to_router_21_0_rsp; - assign router_21_0_rsp_in[2] = '0; - assign router_21_0_rsp_in[3] = router_20_0_to_router_21_0_rsp; - assign router_21_0_rsp_in[4] = magia_tile_ni_21_0_to_router_21_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_0_req_in), - .floo_rsp_o (router_21_0_rsp_out), - .floo_req_o (router_21_0_req_out), - .floo_rsp_i (router_21_0_rsp_in) -); - - -floo_req_t [4:0] router_21_1_req_in; -floo_rsp_t [4:0] router_21_1_rsp_out; -floo_req_t [4:0] router_21_1_req_out; -floo_rsp_t [4:0] router_21_1_rsp_in; - - assign router_21_1_req_in[0] = router_21_2_to_router_21_1_req; - assign router_21_1_req_in[1] = router_22_1_to_router_21_1_req; - assign router_21_1_req_in[2] = router_21_0_to_router_21_1_req; - assign router_21_1_req_in[3] = router_20_1_to_router_21_1_req; - assign router_21_1_req_in[4] = magia_tile_ni_21_1_to_router_21_1_req; - - assign router_21_1_to_router_21_2_rsp = router_21_1_rsp_out[0]; - assign router_21_1_to_router_22_1_rsp = router_21_1_rsp_out[1]; - assign router_21_1_to_router_21_0_rsp = router_21_1_rsp_out[2]; - assign router_21_1_to_router_20_1_rsp = router_21_1_rsp_out[3]; - assign router_21_1_to_magia_tile_ni_21_1_rsp = router_21_1_rsp_out[4]; - - assign router_21_1_to_router_21_2_req = router_21_1_req_out[0]; - assign router_21_1_to_router_22_1_req = router_21_1_req_out[1]; - assign router_21_1_to_router_21_0_req = router_21_1_req_out[2]; - assign router_21_1_to_router_20_1_req = router_21_1_req_out[3]; - assign router_21_1_to_magia_tile_ni_21_1_req = router_21_1_req_out[4]; - - assign router_21_1_rsp_in[0] = router_21_2_to_router_21_1_rsp; - assign router_21_1_rsp_in[1] = router_22_1_to_router_21_1_rsp; - assign router_21_1_rsp_in[2] = router_21_0_to_router_21_1_rsp; - assign router_21_1_rsp_in[3] = router_20_1_to_router_21_1_rsp; - assign router_21_1_rsp_in[4] = magia_tile_ni_21_1_to_router_21_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_1_req_in), - .floo_rsp_o (router_21_1_rsp_out), - .floo_req_o (router_21_1_req_out), - .floo_rsp_i (router_21_1_rsp_in) -); - - -floo_req_t [4:0] router_21_2_req_in; -floo_rsp_t [4:0] router_21_2_rsp_out; -floo_req_t [4:0] router_21_2_req_out; -floo_rsp_t [4:0] router_21_2_rsp_in; - - assign router_21_2_req_in[0] = router_21_3_to_router_21_2_req; - assign router_21_2_req_in[1] = router_22_2_to_router_21_2_req; - assign router_21_2_req_in[2] = router_21_1_to_router_21_2_req; - assign router_21_2_req_in[3] = router_20_2_to_router_21_2_req; - assign router_21_2_req_in[4] = magia_tile_ni_21_2_to_router_21_2_req; - - assign router_21_2_to_router_21_3_rsp = router_21_2_rsp_out[0]; - assign router_21_2_to_router_22_2_rsp = router_21_2_rsp_out[1]; - assign router_21_2_to_router_21_1_rsp = router_21_2_rsp_out[2]; - assign router_21_2_to_router_20_2_rsp = router_21_2_rsp_out[3]; - assign router_21_2_to_magia_tile_ni_21_2_rsp = router_21_2_rsp_out[4]; - - assign router_21_2_to_router_21_3_req = router_21_2_req_out[0]; - assign router_21_2_to_router_22_2_req = router_21_2_req_out[1]; - assign router_21_2_to_router_21_1_req = router_21_2_req_out[2]; - assign router_21_2_to_router_20_2_req = router_21_2_req_out[3]; - assign router_21_2_to_magia_tile_ni_21_2_req = router_21_2_req_out[4]; - - assign router_21_2_rsp_in[0] = router_21_3_to_router_21_2_rsp; - assign router_21_2_rsp_in[1] = router_22_2_to_router_21_2_rsp; - assign router_21_2_rsp_in[2] = router_21_1_to_router_21_2_rsp; - assign router_21_2_rsp_in[3] = router_20_2_to_router_21_2_rsp; - assign router_21_2_rsp_in[4] = magia_tile_ni_21_2_to_router_21_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_2_req_in), - .floo_rsp_o (router_21_2_rsp_out), - .floo_req_o (router_21_2_req_out), - .floo_rsp_i (router_21_2_rsp_in) -); - - -floo_req_t [4:0] router_21_3_req_in; -floo_rsp_t [4:0] router_21_3_rsp_out; -floo_req_t [4:0] router_21_3_req_out; -floo_rsp_t [4:0] router_21_3_rsp_in; - - assign router_21_3_req_in[0] = router_21_4_to_router_21_3_req; - assign router_21_3_req_in[1] = router_22_3_to_router_21_3_req; - assign router_21_3_req_in[2] = router_21_2_to_router_21_3_req; - assign router_21_3_req_in[3] = router_20_3_to_router_21_3_req; - assign router_21_3_req_in[4] = magia_tile_ni_21_3_to_router_21_3_req; - - assign router_21_3_to_router_21_4_rsp = router_21_3_rsp_out[0]; - assign router_21_3_to_router_22_3_rsp = router_21_3_rsp_out[1]; - assign router_21_3_to_router_21_2_rsp = router_21_3_rsp_out[2]; - assign router_21_3_to_router_20_3_rsp = router_21_3_rsp_out[3]; - assign router_21_3_to_magia_tile_ni_21_3_rsp = router_21_3_rsp_out[4]; - - assign router_21_3_to_router_21_4_req = router_21_3_req_out[0]; - assign router_21_3_to_router_22_3_req = router_21_3_req_out[1]; - assign router_21_3_to_router_21_2_req = router_21_3_req_out[2]; - assign router_21_3_to_router_20_3_req = router_21_3_req_out[3]; - assign router_21_3_to_magia_tile_ni_21_3_req = router_21_3_req_out[4]; - - assign router_21_3_rsp_in[0] = router_21_4_to_router_21_3_rsp; - assign router_21_3_rsp_in[1] = router_22_3_to_router_21_3_rsp; - assign router_21_3_rsp_in[2] = router_21_2_to_router_21_3_rsp; - assign router_21_3_rsp_in[3] = router_20_3_to_router_21_3_rsp; - assign router_21_3_rsp_in[4] = magia_tile_ni_21_3_to_router_21_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_3_req_in), - .floo_rsp_o (router_21_3_rsp_out), - .floo_req_o (router_21_3_req_out), - .floo_rsp_i (router_21_3_rsp_in) -); - - -floo_req_t [4:0] router_21_4_req_in; -floo_rsp_t [4:0] router_21_4_rsp_out; -floo_req_t [4:0] router_21_4_req_out; -floo_rsp_t [4:0] router_21_4_rsp_in; - - assign router_21_4_req_in[0] = router_21_5_to_router_21_4_req; - assign router_21_4_req_in[1] = router_22_4_to_router_21_4_req; - assign router_21_4_req_in[2] = router_21_3_to_router_21_4_req; - assign router_21_4_req_in[3] = router_20_4_to_router_21_4_req; - assign router_21_4_req_in[4] = magia_tile_ni_21_4_to_router_21_4_req; - - assign router_21_4_to_router_21_5_rsp = router_21_4_rsp_out[0]; - assign router_21_4_to_router_22_4_rsp = router_21_4_rsp_out[1]; - assign router_21_4_to_router_21_3_rsp = router_21_4_rsp_out[2]; - assign router_21_4_to_router_20_4_rsp = router_21_4_rsp_out[3]; - assign router_21_4_to_magia_tile_ni_21_4_rsp = router_21_4_rsp_out[4]; - - assign router_21_4_to_router_21_5_req = router_21_4_req_out[0]; - assign router_21_4_to_router_22_4_req = router_21_4_req_out[1]; - assign router_21_4_to_router_21_3_req = router_21_4_req_out[2]; - assign router_21_4_to_router_20_4_req = router_21_4_req_out[3]; - assign router_21_4_to_magia_tile_ni_21_4_req = router_21_4_req_out[4]; - - assign router_21_4_rsp_in[0] = router_21_5_to_router_21_4_rsp; - assign router_21_4_rsp_in[1] = router_22_4_to_router_21_4_rsp; - assign router_21_4_rsp_in[2] = router_21_3_to_router_21_4_rsp; - assign router_21_4_rsp_in[3] = router_20_4_to_router_21_4_rsp; - assign router_21_4_rsp_in[4] = magia_tile_ni_21_4_to_router_21_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_4_req_in), - .floo_rsp_o (router_21_4_rsp_out), - .floo_req_o (router_21_4_req_out), - .floo_rsp_i (router_21_4_rsp_in) -); - - -floo_req_t [4:0] router_21_5_req_in; -floo_rsp_t [4:0] router_21_5_rsp_out; -floo_req_t [4:0] router_21_5_req_out; -floo_rsp_t [4:0] router_21_5_rsp_in; - - assign router_21_5_req_in[0] = router_21_6_to_router_21_5_req; - assign router_21_5_req_in[1] = router_22_5_to_router_21_5_req; - assign router_21_5_req_in[2] = router_21_4_to_router_21_5_req; - assign router_21_5_req_in[3] = router_20_5_to_router_21_5_req; - assign router_21_5_req_in[4] = magia_tile_ni_21_5_to_router_21_5_req; - - assign router_21_5_to_router_21_6_rsp = router_21_5_rsp_out[0]; - assign router_21_5_to_router_22_5_rsp = router_21_5_rsp_out[1]; - assign router_21_5_to_router_21_4_rsp = router_21_5_rsp_out[2]; - assign router_21_5_to_router_20_5_rsp = router_21_5_rsp_out[3]; - assign router_21_5_to_magia_tile_ni_21_5_rsp = router_21_5_rsp_out[4]; - - assign router_21_5_to_router_21_6_req = router_21_5_req_out[0]; - assign router_21_5_to_router_22_5_req = router_21_5_req_out[1]; - assign router_21_5_to_router_21_4_req = router_21_5_req_out[2]; - assign router_21_5_to_router_20_5_req = router_21_5_req_out[3]; - assign router_21_5_to_magia_tile_ni_21_5_req = router_21_5_req_out[4]; - - assign router_21_5_rsp_in[0] = router_21_6_to_router_21_5_rsp; - assign router_21_5_rsp_in[1] = router_22_5_to_router_21_5_rsp; - assign router_21_5_rsp_in[2] = router_21_4_to_router_21_5_rsp; - assign router_21_5_rsp_in[3] = router_20_5_to_router_21_5_rsp; - assign router_21_5_rsp_in[4] = magia_tile_ni_21_5_to_router_21_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_5_req_in), - .floo_rsp_o (router_21_5_rsp_out), - .floo_req_o (router_21_5_req_out), - .floo_rsp_i (router_21_5_rsp_in) -); - - -floo_req_t [4:0] router_21_6_req_in; -floo_rsp_t [4:0] router_21_6_rsp_out; -floo_req_t [4:0] router_21_6_req_out; -floo_rsp_t [4:0] router_21_6_rsp_in; - - assign router_21_6_req_in[0] = router_21_7_to_router_21_6_req; - assign router_21_6_req_in[1] = router_22_6_to_router_21_6_req; - assign router_21_6_req_in[2] = router_21_5_to_router_21_6_req; - assign router_21_6_req_in[3] = router_20_6_to_router_21_6_req; - assign router_21_6_req_in[4] = magia_tile_ni_21_6_to_router_21_6_req; - - assign router_21_6_to_router_21_7_rsp = router_21_6_rsp_out[0]; - assign router_21_6_to_router_22_6_rsp = router_21_6_rsp_out[1]; - assign router_21_6_to_router_21_5_rsp = router_21_6_rsp_out[2]; - assign router_21_6_to_router_20_6_rsp = router_21_6_rsp_out[3]; - assign router_21_6_to_magia_tile_ni_21_6_rsp = router_21_6_rsp_out[4]; - - assign router_21_6_to_router_21_7_req = router_21_6_req_out[0]; - assign router_21_6_to_router_22_6_req = router_21_6_req_out[1]; - assign router_21_6_to_router_21_5_req = router_21_6_req_out[2]; - assign router_21_6_to_router_20_6_req = router_21_6_req_out[3]; - assign router_21_6_to_magia_tile_ni_21_6_req = router_21_6_req_out[4]; - - assign router_21_6_rsp_in[0] = router_21_7_to_router_21_6_rsp; - assign router_21_6_rsp_in[1] = router_22_6_to_router_21_6_rsp; - assign router_21_6_rsp_in[2] = router_21_5_to_router_21_6_rsp; - assign router_21_6_rsp_in[3] = router_20_6_to_router_21_6_rsp; - assign router_21_6_rsp_in[4] = magia_tile_ni_21_6_to_router_21_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_6_req_in), - .floo_rsp_o (router_21_6_rsp_out), - .floo_req_o (router_21_6_req_out), - .floo_rsp_i (router_21_6_rsp_in) -); - - -floo_req_t [4:0] router_21_7_req_in; -floo_rsp_t [4:0] router_21_7_rsp_out; -floo_req_t [4:0] router_21_7_req_out; -floo_rsp_t [4:0] router_21_7_rsp_in; - - assign router_21_7_req_in[0] = router_21_8_to_router_21_7_req; - assign router_21_7_req_in[1] = router_22_7_to_router_21_7_req; - assign router_21_7_req_in[2] = router_21_6_to_router_21_7_req; - assign router_21_7_req_in[3] = router_20_7_to_router_21_7_req; - assign router_21_7_req_in[4] = magia_tile_ni_21_7_to_router_21_7_req; - - assign router_21_7_to_router_21_8_rsp = router_21_7_rsp_out[0]; - assign router_21_7_to_router_22_7_rsp = router_21_7_rsp_out[1]; - assign router_21_7_to_router_21_6_rsp = router_21_7_rsp_out[2]; - assign router_21_7_to_router_20_7_rsp = router_21_7_rsp_out[3]; - assign router_21_7_to_magia_tile_ni_21_7_rsp = router_21_7_rsp_out[4]; - - assign router_21_7_to_router_21_8_req = router_21_7_req_out[0]; - assign router_21_7_to_router_22_7_req = router_21_7_req_out[1]; - assign router_21_7_to_router_21_6_req = router_21_7_req_out[2]; - assign router_21_7_to_router_20_7_req = router_21_7_req_out[3]; - assign router_21_7_to_magia_tile_ni_21_7_req = router_21_7_req_out[4]; - - assign router_21_7_rsp_in[0] = router_21_8_to_router_21_7_rsp; - assign router_21_7_rsp_in[1] = router_22_7_to_router_21_7_rsp; - assign router_21_7_rsp_in[2] = router_21_6_to_router_21_7_rsp; - assign router_21_7_rsp_in[3] = router_20_7_to_router_21_7_rsp; - assign router_21_7_rsp_in[4] = magia_tile_ni_21_7_to_router_21_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_7_req_in), - .floo_rsp_o (router_21_7_rsp_out), - .floo_req_o (router_21_7_req_out), - .floo_rsp_i (router_21_7_rsp_in) -); - - -floo_req_t [4:0] router_21_8_req_in; -floo_rsp_t [4:0] router_21_8_rsp_out; -floo_req_t [4:0] router_21_8_req_out; -floo_rsp_t [4:0] router_21_8_rsp_in; - - assign router_21_8_req_in[0] = router_21_9_to_router_21_8_req; - assign router_21_8_req_in[1] = router_22_8_to_router_21_8_req; - assign router_21_8_req_in[2] = router_21_7_to_router_21_8_req; - assign router_21_8_req_in[3] = router_20_8_to_router_21_8_req; - assign router_21_8_req_in[4] = magia_tile_ni_21_8_to_router_21_8_req; - - assign router_21_8_to_router_21_9_rsp = router_21_8_rsp_out[0]; - assign router_21_8_to_router_22_8_rsp = router_21_8_rsp_out[1]; - assign router_21_8_to_router_21_7_rsp = router_21_8_rsp_out[2]; - assign router_21_8_to_router_20_8_rsp = router_21_8_rsp_out[3]; - assign router_21_8_to_magia_tile_ni_21_8_rsp = router_21_8_rsp_out[4]; - - assign router_21_8_to_router_21_9_req = router_21_8_req_out[0]; - assign router_21_8_to_router_22_8_req = router_21_8_req_out[1]; - assign router_21_8_to_router_21_7_req = router_21_8_req_out[2]; - assign router_21_8_to_router_20_8_req = router_21_8_req_out[3]; - assign router_21_8_to_magia_tile_ni_21_8_req = router_21_8_req_out[4]; - - assign router_21_8_rsp_in[0] = router_21_9_to_router_21_8_rsp; - assign router_21_8_rsp_in[1] = router_22_8_to_router_21_8_rsp; - assign router_21_8_rsp_in[2] = router_21_7_to_router_21_8_rsp; - assign router_21_8_rsp_in[3] = router_20_8_to_router_21_8_rsp; - assign router_21_8_rsp_in[4] = magia_tile_ni_21_8_to_router_21_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_8_req_in), - .floo_rsp_o (router_21_8_rsp_out), - .floo_req_o (router_21_8_req_out), - .floo_rsp_i (router_21_8_rsp_in) -); - - -floo_req_t [4:0] router_21_9_req_in; -floo_rsp_t [4:0] router_21_9_rsp_out; -floo_req_t [4:0] router_21_9_req_out; -floo_rsp_t [4:0] router_21_9_rsp_in; - - assign router_21_9_req_in[0] = router_21_10_to_router_21_9_req; - assign router_21_9_req_in[1] = router_22_9_to_router_21_9_req; - assign router_21_9_req_in[2] = router_21_8_to_router_21_9_req; - assign router_21_9_req_in[3] = router_20_9_to_router_21_9_req; - assign router_21_9_req_in[4] = magia_tile_ni_21_9_to_router_21_9_req; - - assign router_21_9_to_router_21_10_rsp = router_21_9_rsp_out[0]; - assign router_21_9_to_router_22_9_rsp = router_21_9_rsp_out[1]; - assign router_21_9_to_router_21_8_rsp = router_21_9_rsp_out[2]; - assign router_21_9_to_router_20_9_rsp = router_21_9_rsp_out[3]; - assign router_21_9_to_magia_tile_ni_21_9_rsp = router_21_9_rsp_out[4]; - - assign router_21_9_to_router_21_10_req = router_21_9_req_out[0]; - assign router_21_9_to_router_22_9_req = router_21_9_req_out[1]; - assign router_21_9_to_router_21_8_req = router_21_9_req_out[2]; - assign router_21_9_to_router_20_9_req = router_21_9_req_out[3]; - assign router_21_9_to_magia_tile_ni_21_9_req = router_21_9_req_out[4]; - - assign router_21_9_rsp_in[0] = router_21_10_to_router_21_9_rsp; - assign router_21_9_rsp_in[1] = router_22_9_to_router_21_9_rsp; - assign router_21_9_rsp_in[2] = router_21_8_to_router_21_9_rsp; - assign router_21_9_rsp_in[3] = router_20_9_to_router_21_9_rsp; - assign router_21_9_rsp_in[4] = magia_tile_ni_21_9_to_router_21_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_9_req_in), - .floo_rsp_o (router_21_9_rsp_out), - .floo_req_o (router_21_9_req_out), - .floo_rsp_i (router_21_9_rsp_in) -); - - -floo_req_t [4:0] router_21_10_req_in; -floo_rsp_t [4:0] router_21_10_rsp_out; -floo_req_t [4:0] router_21_10_req_out; -floo_rsp_t [4:0] router_21_10_rsp_in; - - assign router_21_10_req_in[0] = router_21_11_to_router_21_10_req; - assign router_21_10_req_in[1] = router_22_10_to_router_21_10_req; - assign router_21_10_req_in[2] = router_21_9_to_router_21_10_req; - assign router_21_10_req_in[3] = router_20_10_to_router_21_10_req; - assign router_21_10_req_in[4] = magia_tile_ni_21_10_to_router_21_10_req; - - assign router_21_10_to_router_21_11_rsp = router_21_10_rsp_out[0]; - assign router_21_10_to_router_22_10_rsp = router_21_10_rsp_out[1]; - assign router_21_10_to_router_21_9_rsp = router_21_10_rsp_out[2]; - assign router_21_10_to_router_20_10_rsp = router_21_10_rsp_out[3]; - assign router_21_10_to_magia_tile_ni_21_10_rsp = router_21_10_rsp_out[4]; - - assign router_21_10_to_router_21_11_req = router_21_10_req_out[0]; - assign router_21_10_to_router_22_10_req = router_21_10_req_out[1]; - assign router_21_10_to_router_21_9_req = router_21_10_req_out[2]; - assign router_21_10_to_router_20_10_req = router_21_10_req_out[3]; - assign router_21_10_to_magia_tile_ni_21_10_req = router_21_10_req_out[4]; - - assign router_21_10_rsp_in[0] = router_21_11_to_router_21_10_rsp; - assign router_21_10_rsp_in[1] = router_22_10_to_router_21_10_rsp; - assign router_21_10_rsp_in[2] = router_21_9_to_router_21_10_rsp; - assign router_21_10_rsp_in[3] = router_20_10_to_router_21_10_rsp; - assign router_21_10_rsp_in[4] = magia_tile_ni_21_10_to_router_21_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_10_req_in), - .floo_rsp_o (router_21_10_rsp_out), - .floo_req_o (router_21_10_req_out), - .floo_rsp_i (router_21_10_rsp_in) -); - - -floo_req_t [4:0] router_21_11_req_in; -floo_rsp_t [4:0] router_21_11_rsp_out; -floo_req_t [4:0] router_21_11_req_out; -floo_rsp_t [4:0] router_21_11_rsp_in; - - assign router_21_11_req_in[0] = router_21_12_to_router_21_11_req; - assign router_21_11_req_in[1] = router_22_11_to_router_21_11_req; - assign router_21_11_req_in[2] = router_21_10_to_router_21_11_req; - assign router_21_11_req_in[3] = router_20_11_to_router_21_11_req; - assign router_21_11_req_in[4] = magia_tile_ni_21_11_to_router_21_11_req; - - assign router_21_11_to_router_21_12_rsp = router_21_11_rsp_out[0]; - assign router_21_11_to_router_22_11_rsp = router_21_11_rsp_out[1]; - assign router_21_11_to_router_21_10_rsp = router_21_11_rsp_out[2]; - assign router_21_11_to_router_20_11_rsp = router_21_11_rsp_out[3]; - assign router_21_11_to_magia_tile_ni_21_11_rsp = router_21_11_rsp_out[4]; - - assign router_21_11_to_router_21_12_req = router_21_11_req_out[0]; - assign router_21_11_to_router_22_11_req = router_21_11_req_out[1]; - assign router_21_11_to_router_21_10_req = router_21_11_req_out[2]; - assign router_21_11_to_router_20_11_req = router_21_11_req_out[3]; - assign router_21_11_to_magia_tile_ni_21_11_req = router_21_11_req_out[4]; - - assign router_21_11_rsp_in[0] = router_21_12_to_router_21_11_rsp; - assign router_21_11_rsp_in[1] = router_22_11_to_router_21_11_rsp; - assign router_21_11_rsp_in[2] = router_21_10_to_router_21_11_rsp; - assign router_21_11_rsp_in[3] = router_20_11_to_router_21_11_rsp; - assign router_21_11_rsp_in[4] = magia_tile_ni_21_11_to_router_21_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_11_req_in), - .floo_rsp_o (router_21_11_rsp_out), - .floo_req_o (router_21_11_req_out), - .floo_rsp_i (router_21_11_rsp_in) -); - - -floo_req_t [4:0] router_21_12_req_in; -floo_rsp_t [4:0] router_21_12_rsp_out; -floo_req_t [4:0] router_21_12_req_out; -floo_rsp_t [4:0] router_21_12_rsp_in; - - assign router_21_12_req_in[0] = router_21_13_to_router_21_12_req; - assign router_21_12_req_in[1] = router_22_12_to_router_21_12_req; - assign router_21_12_req_in[2] = router_21_11_to_router_21_12_req; - assign router_21_12_req_in[3] = router_20_12_to_router_21_12_req; - assign router_21_12_req_in[4] = magia_tile_ni_21_12_to_router_21_12_req; - - assign router_21_12_to_router_21_13_rsp = router_21_12_rsp_out[0]; - assign router_21_12_to_router_22_12_rsp = router_21_12_rsp_out[1]; - assign router_21_12_to_router_21_11_rsp = router_21_12_rsp_out[2]; - assign router_21_12_to_router_20_12_rsp = router_21_12_rsp_out[3]; - assign router_21_12_to_magia_tile_ni_21_12_rsp = router_21_12_rsp_out[4]; - - assign router_21_12_to_router_21_13_req = router_21_12_req_out[0]; - assign router_21_12_to_router_22_12_req = router_21_12_req_out[1]; - assign router_21_12_to_router_21_11_req = router_21_12_req_out[2]; - assign router_21_12_to_router_20_12_req = router_21_12_req_out[3]; - assign router_21_12_to_magia_tile_ni_21_12_req = router_21_12_req_out[4]; - - assign router_21_12_rsp_in[0] = router_21_13_to_router_21_12_rsp; - assign router_21_12_rsp_in[1] = router_22_12_to_router_21_12_rsp; - assign router_21_12_rsp_in[2] = router_21_11_to_router_21_12_rsp; - assign router_21_12_rsp_in[3] = router_20_12_to_router_21_12_rsp; - assign router_21_12_rsp_in[4] = magia_tile_ni_21_12_to_router_21_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_12_req_in), - .floo_rsp_o (router_21_12_rsp_out), - .floo_req_o (router_21_12_req_out), - .floo_rsp_i (router_21_12_rsp_in) -); - - -floo_req_t [4:0] router_21_13_req_in; -floo_rsp_t [4:0] router_21_13_rsp_out; -floo_req_t [4:0] router_21_13_req_out; -floo_rsp_t [4:0] router_21_13_rsp_in; - - assign router_21_13_req_in[0] = router_21_14_to_router_21_13_req; - assign router_21_13_req_in[1] = router_22_13_to_router_21_13_req; - assign router_21_13_req_in[2] = router_21_12_to_router_21_13_req; - assign router_21_13_req_in[3] = router_20_13_to_router_21_13_req; - assign router_21_13_req_in[4] = magia_tile_ni_21_13_to_router_21_13_req; - - assign router_21_13_to_router_21_14_rsp = router_21_13_rsp_out[0]; - assign router_21_13_to_router_22_13_rsp = router_21_13_rsp_out[1]; - assign router_21_13_to_router_21_12_rsp = router_21_13_rsp_out[2]; - assign router_21_13_to_router_20_13_rsp = router_21_13_rsp_out[3]; - assign router_21_13_to_magia_tile_ni_21_13_rsp = router_21_13_rsp_out[4]; - - assign router_21_13_to_router_21_14_req = router_21_13_req_out[0]; - assign router_21_13_to_router_22_13_req = router_21_13_req_out[1]; - assign router_21_13_to_router_21_12_req = router_21_13_req_out[2]; - assign router_21_13_to_router_20_13_req = router_21_13_req_out[3]; - assign router_21_13_to_magia_tile_ni_21_13_req = router_21_13_req_out[4]; - - assign router_21_13_rsp_in[0] = router_21_14_to_router_21_13_rsp; - assign router_21_13_rsp_in[1] = router_22_13_to_router_21_13_rsp; - assign router_21_13_rsp_in[2] = router_21_12_to_router_21_13_rsp; - assign router_21_13_rsp_in[3] = router_20_13_to_router_21_13_rsp; - assign router_21_13_rsp_in[4] = magia_tile_ni_21_13_to_router_21_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_13_req_in), - .floo_rsp_o (router_21_13_rsp_out), - .floo_req_o (router_21_13_req_out), - .floo_rsp_i (router_21_13_rsp_in) -); - - -floo_req_t [4:0] router_21_14_req_in; -floo_rsp_t [4:0] router_21_14_rsp_out; -floo_req_t [4:0] router_21_14_req_out; -floo_rsp_t [4:0] router_21_14_rsp_in; - - assign router_21_14_req_in[0] = router_21_15_to_router_21_14_req; - assign router_21_14_req_in[1] = router_22_14_to_router_21_14_req; - assign router_21_14_req_in[2] = router_21_13_to_router_21_14_req; - assign router_21_14_req_in[3] = router_20_14_to_router_21_14_req; - assign router_21_14_req_in[4] = magia_tile_ni_21_14_to_router_21_14_req; - - assign router_21_14_to_router_21_15_rsp = router_21_14_rsp_out[0]; - assign router_21_14_to_router_22_14_rsp = router_21_14_rsp_out[1]; - assign router_21_14_to_router_21_13_rsp = router_21_14_rsp_out[2]; - assign router_21_14_to_router_20_14_rsp = router_21_14_rsp_out[3]; - assign router_21_14_to_magia_tile_ni_21_14_rsp = router_21_14_rsp_out[4]; - - assign router_21_14_to_router_21_15_req = router_21_14_req_out[0]; - assign router_21_14_to_router_22_14_req = router_21_14_req_out[1]; - assign router_21_14_to_router_21_13_req = router_21_14_req_out[2]; - assign router_21_14_to_router_20_14_req = router_21_14_req_out[3]; - assign router_21_14_to_magia_tile_ni_21_14_req = router_21_14_req_out[4]; - - assign router_21_14_rsp_in[0] = router_21_15_to_router_21_14_rsp; - assign router_21_14_rsp_in[1] = router_22_14_to_router_21_14_rsp; - assign router_21_14_rsp_in[2] = router_21_13_to_router_21_14_rsp; - assign router_21_14_rsp_in[3] = router_20_14_to_router_21_14_rsp; - assign router_21_14_rsp_in[4] = magia_tile_ni_21_14_to_router_21_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_14_req_in), - .floo_rsp_o (router_21_14_rsp_out), - .floo_req_o (router_21_14_req_out), - .floo_rsp_i (router_21_14_rsp_in) -); - - -floo_req_t [4:0] router_21_15_req_in; -floo_rsp_t [4:0] router_21_15_rsp_out; -floo_req_t [4:0] router_21_15_req_out; -floo_rsp_t [4:0] router_21_15_rsp_in; - - assign router_21_15_req_in[0] = router_21_16_to_router_21_15_req; - assign router_21_15_req_in[1] = router_22_15_to_router_21_15_req; - assign router_21_15_req_in[2] = router_21_14_to_router_21_15_req; - assign router_21_15_req_in[3] = router_20_15_to_router_21_15_req; - assign router_21_15_req_in[4] = magia_tile_ni_21_15_to_router_21_15_req; - - assign router_21_15_to_router_21_16_rsp = router_21_15_rsp_out[0]; - assign router_21_15_to_router_22_15_rsp = router_21_15_rsp_out[1]; - assign router_21_15_to_router_21_14_rsp = router_21_15_rsp_out[2]; - assign router_21_15_to_router_20_15_rsp = router_21_15_rsp_out[3]; - assign router_21_15_to_magia_tile_ni_21_15_rsp = router_21_15_rsp_out[4]; - - assign router_21_15_to_router_21_16_req = router_21_15_req_out[0]; - assign router_21_15_to_router_22_15_req = router_21_15_req_out[1]; - assign router_21_15_to_router_21_14_req = router_21_15_req_out[2]; - assign router_21_15_to_router_20_15_req = router_21_15_req_out[3]; - assign router_21_15_to_magia_tile_ni_21_15_req = router_21_15_req_out[4]; - - assign router_21_15_rsp_in[0] = router_21_16_to_router_21_15_rsp; - assign router_21_15_rsp_in[1] = router_22_15_to_router_21_15_rsp; - assign router_21_15_rsp_in[2] = router_21_14_to_router_21_15_rsp; - assign router_21_15_rsp_in[3] = router_20_15_to_router_21_15_rsp; - assign router_21_15_rsp_in[4] = magia_tile_ni_21_15_to_router_21_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_15_req_in), - .floo_rsp_o (router_21_15_rsp_out), - .floo_req_o (router_21_15_req_out), - .floo_rsp_i (router_21_15_rsp_in) -); - - -floo_req_t [4:0] router_21_16_req_in; -floo_rsp_t [4:0] router_21_16_rsp_out; -floo_req_t [4:0] router_21_16_req_out; -floo_rsp_t [4:0] router_21_16_rsp_in; - - assign router_21_16_req_in[0] = router_21_17_to_router_21_16_req; - assign router_21_16_req_in[1] = router_22_16_to_router_21_16_req; - assign router_21_16_req_in[2] = router_21_15_to_router_21_16_req; - assign router_21_16_req_in[3] = router_20_16_to_router_21_16_req; - assign router_21_16_req_in[4] = magia_tile_ni_21_16_to_router_21_16_req; - - assign router_21_16_to_router_21_17_rsp = router_21_16_rsp_out[0]; - assign router_21_16_to_router_22_16_rsp = router_21_16_rsp_out[1]; - assign router_21_16_to_router_21_15_rsp = router_21_16_rsp_out[2]; - assign router_21_16_to_router_20_16_rsp = router_21_16_rsp_out[3]; - assign router_21_16_to_magia_tile_ni_21_16_rsp = router_21_16_rsp_out[4]; - - assign router_21_16_to_router_21_17_req = router_21_16_req_out[0]; - assign router_21_16_to_router_22_16_req = router_21_16_req_out[1]; - assign router_21_16_to_router_21_15_req = router_21_16_req_out[2]; - assign router_21_16_to_router_20_16_req = router_21_16_req_out[3]; - assign router_21_16_to_magia_tile_ni_21_16_req = router_21_16_req_out[4]; - - assign router_21_16_rsp_in[0] = router_21_17_to_router_21_16_rsp; - assign router_21_16_rsp_in[1] = router_22_16_to_router_21_16_rsp; - assign router_21_16_rsp_in[2] = router_21_15_to_router_21_16_rsp; - assign router_21_16_rsp_in[3] = router_20_16_to_router_21_16_rsp; - assign router_21_16_rsp_in[4] = magia_tile_ni_21_16_to_router_21_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_16_req_in), - .floo_rsp_o (router_21_16_rsp_out), - .floo_req_o (router_21_16_req_out), - .floo_rsp_i (router_21_16_rsp_in) -); - - -floo_req_t [4:0] router_21_17_req_in; -floo_rsp_t [4:0] router_21_17_rsp_out; -floo_req_t [4:0] router_21_17_req_out; -floo_rsp_t [4:0] router_21_17_rsp_in; - - assign router_21_17_req_in[0] = router_21_18_to_router_21_17_req; - assign router_21_17_req_in[1] = router_22_17_to_router_21_17_req; - assign router_21_17_req_in[2] = router_21_16_to_router_21_17_req; - assign router_21_17_req_in[3] = router_20_17_to_router_21_17_req; - assign router_21_17_req_in[4] = magia_tile_ni_21_17_to_router_21_17_req; - - assign router_21_17_to_router_21_18_rsp = router_21_17_rsp_out[0]; - assign router_21_17_to_router_22_17_rsp = router_21_17_rsp_out[1]; - assign router_21_17_to_router_21_16_rsp = router_21_17_rsp_out[2]; - assign router_21_17_to_router_20_17_rsp = router_21_17_rsp_out[3]; - assign router_21_17_to_magia_tile_ni_21_17_rsp = router_21_17_rsp_out[4]; - - assign router_21_17_to_router_21_18_req = router_21_17_req_out[0]; - assign router_21_17_to_router_22_17_req = router_21_17_req_out[1]; - assign router_21_17_to_router_21_16_req = router_21_17_req_out[2]; - assign router_21_17_to_router_20_17_req = router_21_17_req_out[3]; - assign router_21_17_to_magia_tile_ni_21_17_req = router_21_17_req_out[4]; - - assign router_21_17_rsp_in[0] = router_21_18_to_router_21_17_rsp; - assign router_21_17_rsp_in[1] = router_22_17_to_router_21_17_rsp; - assign router_21_17_rsp_in[2] = router_21_16_to_router_21_17_rsp; - assign router_21_17_rsp_in[3] = router_20_17_to_router_21_17_rsp; - assign router_21_17_rsp_in[4] = magia_tile_ni_21_17_to_router_21_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_17_req_in), - .floo_rsp_o (router_21_17_rsp_out), - .floo_req_o (router_21_17_req_out), - .floo_rsp_i (router_21_17_rsp_in) -); - - -floo_req_t [4:0] router_21_18_req_in; -floo_rsp_t [4:0] router_21_18_rsp_out; -floo_req_t [4:0] router_21_18_req_out; -floo_rsp_t [4:0] router_21_18_rsp_in; - - assign router_21_18_req_in[0] = router_21_19_to_router_21_18_req; - assign router_21_18_req_in[1] = router_22_18_to_router_21_18_req; - assign router_21_18_req_in[2] = router_21_17_to_router_21_18_req; - assign router_21_18_req_in[3] = router_20_18_to_router_21_18_req; - assign router_21_18_req_in[4] = magia_tile_ni_21_18_to_router_21_18_req; - - assign router_21_18_to_router_21_19_rsp = router_21_18_rsp_out[0]; - assign router_21_18_to_router_22_18_rsp = router_21_18_rsp_out[1]; - assign router_21_18_to_router_21_17_rsp = router_21_18_rsp_out[2]; - assign router_21_18_to_router_20_18_rsp = router_21_18_rsp_out[3]; - assign router_21_18_to_magia_tile_ni_21_18_rsp = router_21_18_rsp_out[4]; - - assign router_21_18_to_router_21_19_req = router_21_18_req_out[0]; - assign router_21_18_to_router_22_18_req = router_21_18_req_out[1]; - assign router_21_18_to_router_21_17_req = router_21_18_req_out[2]; - assign router_21_18_to_router_20_18_req = router_21_18_req_out[3]; - assign router_21_18_to_magia_tile_ni_21_18_req = router_21_18_req_out[4]; - - assign router_21_18_rsp_in[0] = router_21_19_to_router_21_18_rsp; - assign router_21_18_rsp_in[1] = router_22_18_to_router_21_18_rsp; - assign router_21_18_rsp_in[2] = router_21_17_to_router_21_18_rsp; - assign router_21_18_rsp_in[3] = router_20_18_to_router_21_18_rsp; - assign router_21_18_rsp_in[4] = magia_tile_ni_21_18_to_router_21_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_18_req_in), - .floo_rsp_o (router_21_18_rsp_out), - .floo_req_o (router_21_18_req_out), - .floo_rsp_i (router_21_18_rsp_in) -); - - -floo_req_t [4:0] router_21_19_req_in; -floo_rsp_t [4:0] router_21_19_rsp_out; -floo_req_t [4:0] router_21_19_req_out; -floo_rsp_t [4:0] router_21_19_rsp_in; - - assign router_21_19_req_in[0] = router_21_20_to_router_21_19_req; - assign router_21_19_req_in[1] = router_22_19_to_router_21_19_req; - assign router_21_19_req_in[2] = router_21_18_to_router_21_19_req; - assign router_21_19_req_in[3] = router_20_19_to_router_21_19_req; - assign router_21_19_req_in[4] = magia_tile_ni_21_19_to_router_21_19_req; - - assign router_21_19_to_router_21_20_rsp = router_21_19_rsp_out[0]; - assign router_21_19_to_router_22_19_rsp = router_21_19_rsp_out[1]; - assign router_21_19_to_router_21_18_rsp = router_21_19_rsp_out[2]; - assign router_21_19_to_router_20_19_rsp = router_21_19_rsp_out[3]; - assign router_21_19_to_magia_tile_ni_21_19_rsp = router_21_19_rsp_out[4]; - - assign router_21_19_to_router_21_20_req = router_21_19_req_out[0]; - assign router_21_19_to_router_22_19_req = router_21_19_req_out[1]; - assign router_21_19_to_router_21_18_req = router_21_19_req_out[2]; - assign router_21_19_to_router_20_19_req = router_21_19_req_out[3]; - assign router_21_19_to_magia_tile_ni_21_19_req = router_21_19_req_out[4]; - - assign router_21_19_rsp_in[0] = router_21_20_to_router_21_19_rsp; - assign router_21_19_rsp_in[1] = router_22_19_to_router_21_19_rsp; - assign router_21_19_rsp_in[2] = router_21_18_to_router_21_19_rsp; - assign router_21_19_rsp_in[3] = router_20_19_to_router_21_19_rsp; - assign router_21_19_rsp_in[4] = magia_tile_ni_21_19_to_router_21_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_19_req_in), - .floo_rsp_o (router_21_19_rsp_out), - .floo_req_o (router_21_19_req_out), - .floo_rsp_i (router_21_19_rsp_in) -); - - -floo_req_t [4:0] router_21_20_req_in; -floo_rsp_t [4:0] router_21_20_rsp_out; -floo_req_t [4:0] router_21_20_req_out; -floo_rsp_t [4:0] router_21_20_rsp_in; - - assign router_21_20_req_in[0] = router_21_21_to_router_21_20_req; - assign router_21_20_req_in[1] = router_22_20_to_router_21_20_req; - assign router_21_20_req_in[2] = router_21_19_to_router_21_20_req; - assign router_21_20_req_in[3] = router_20_20_to_router_21_20_req; - assign router_21_20_req_in[4] = magia_tile_ni_21_20_to_router_21_20_req; - - assign router_21_20_to_router_21_21_rsp = router_21_20_rsp_out[0]; - assign router_21_20_to_router_22_20_rsp = router_21_20_rsp_out[1]; - assign router_21_20_to_router_21_19_rsp = router_21_20_rsp_out[2]; - assign router_21_20_to_router_20_20_rsp = router_21_20_rsp_out[3]; - assign router_21_20_to_magia_tile_ni_21_20_rsp = router_21_20_rsp_out[4]; - - assign router_21_20_to_router_21_21_req = router_21_20_req_out[0]; - assign router_21_20_to_router_22_20_req = router_21_20_req_out[1]; - assign router_21_20_to_router_21_19_req = router_21_20_req_out[2]; - assign router_21_20_to_router_20_20_req = router_21_20_req_out[3]; - assign router_21_20_to_magia_tile_ni_21_20_req = router_21_20_req_out[4]; - - assign router_21_20_rsp_in[0] = router_21_21_to_router_21_20_rsp; - assign router_21_20_rsp_in[1] = router_22_20_to_router_21_20_rsp; - assign router_21_20_rsp_in[2] = router_21_19_to_router_21_20_rsp; - assign router_21_20_rsp_in[3] = router_20_20_to_router_21_20_rsp; - assign router_21_20_rsp_in[4] = magia_tile_ni_21_20_to_router_21_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_20_req_in), - .floo_rsp_o (router_21_20_rsp_out), - .floo_req_o (router_21_20_req_out), - .floo_rsp_i (router_21_20_rsp_in) -); - - -floo_req_t [4:0] router_21_21_req_in; -floo_rsp_t [4:0] router_21_21_rsp_out; -floo_req_t [4:0] router_21_21_req_out; -floo_rsp_t [4:0] router_21_21_rsp_in; - - assign router_21_21_req_in[0] = router_21_22_to_router_21_21_req; - assign router_21_21_req_in[1] = router_22_21_to_router_21_21_req; - assign router_21_21_req_in[2] = router_21_20_to_router_21_21_req; - assign router_21_21_req_in[3] = router_20_21_to_router_21_21_req; - assign router_21_21_req_in[4] = magia_tile_ni_21_21_to_router_21_21_req; - - assign router_21_21_to_router_21_22_rsp = router_21_21_rsp_out[0]; - assign router_21_21_to_router_22_21_rsp = router_21_21_rsp_out[1]; - assign router_21_21_to_router_21_20_rsp = router_21_21_rsp_out[2]; - assign router_21_21_to_router_20_21_rsp = router_21_21_rsp_out[3]; - assign router_21_21_to_magia_tile_ni_21_21_rsp = router_21_21_rsp_out[4]; - - assign router_21_21_to_router_21_22_req = router_21_21_req_out[0]; - assign router_21_21_to_router_22_21_req = router_21_21_req_out[1]; - assign router_21_21_to_router_21_20_req = router_21_21_req_out[2]; - assign router_21_21_to_router_20_21_req = router_21_21_req_out[3]; - assign router_21_21_to_magia_tile_ni_21_21_req = router_21_21_req_out[4]; - - assign router_21_21_rsp_in[0] = router_21_22_to_router_21_21_rsp; - assign router_21_21_rsp_in[1] = router_22_21_to_router_21_21_rsp; - assign router_21_21_rsp_in[2] = router_21_20_to_router_21_21_rsp; - assign router_21_21_rsp_in[3] = router_20_21_to_router_21_21_rsp; - assign router_21_21_rsp_in[4] = magia_tile_ni_21_21_to_router_21_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_21_req_in), - .floo_rsp_o (router_21_21_rsp_out), - .floo_req_o (router_21_21_req_out), - .floo_rsp_i (router_21_21_rsp_in) -); - - -floo_req_t [4:0] router_21_22_req_in; -floo_rsp_t [4:0] router_21_22_rsp_out; -floo_req_t [4:0] router_21_22_req_out; -floo_rsp_t [4:0] router_21_22_rsp_in; - - assign router_21_22_req_in[0] = router_21_23_to_router_21_22_req; - assign router_21_22_req_in[1] = router_22_22_to_router_21_22_req; - assign router_21_22_req_in[2] = router_21_21_to_router_21_22_req; - assign router_21_22_req_in[3] = router_20_22_to_router_21_22_req; - assign router_21_22_req_in[4] = magia_tile_ni_21_22_to_router_21_22_req; - - assign router_21_22_to_router_21_23_rsp = router_21_22_rsp_out[0]; - assign router_21_22_to_router_22_22_rsp = router_21_22_rsp_out[1]; - assign router_21_22_to_router_21_21_rsp = router_21_22_rsp_out[2]; - assign router_21_22_to_router_20_22_rsp = router_21_22_rsp_out[3]; - assign router_21_22_to_magia_tile_ni_21_22_rsp = router_21_22_rsp_out[4]; - - assign router_21_22_to_router_21_23_req = router_21_22_req_out[0]; - assign router_21_22_to_router_22_22_req = router_21_22_req_out[1]; - assign router_21_22_to_router_21_21_req = router_21_22_req_out[2]; - assign router_21_22_to_router_20_22_req = router_21_22_req_out[3]; - assign router_21_22_to_magia_tile_ni_21_22_req = router_21_22_req_out[4]; - - assign router_21_22_rsp_in[0] = router_21_23_to_router_21_22_rsp; - assign router_21_22_rsp_in[1] = router_22_22_to_router_21_22_rsp; - assign router_21_22_rsp_in[2] = router_21_21_to_router_21_22_rsp; - assign router_21_22_rsp_in[3] = router_20_22_to_router_21_22_rsp; - assign router_21_22_rsp_in[4] = magia_tile_ni_21_22_to_router_21_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_22_req_in), - .floo_rsp_o (router_21_22_rsp_out), - .floo_req_o (router_21_22_req_out), - .floo_rsp_i (router_21_22_rsp_in) -); - - -floo_req_t [4:0] router_21_23_req_in; -floo_rsp_t [4:0] router_21_23_rsp_out; -floo_req_t [4:0] router_21_23_req_out; -floo_rsp_t [4:0] router_21_23_rsp_in; - - assign router_21_23_req_in[0] = router_21_24_to_router_21_23_req; - assign router_21_23_req_in[1] = router_22_23_to_router_21_23_req; - assign router_21_23_req_in[2] = router_21_22_to_router_21_23_req; - assign router_21_23_req_in[3] = router_20_23_to_router_21_23_req; - assign router_21_23_req_in[4] = magia_tile_ni_21_23_to_router_21_23_req; - - assign router_21_23_to_router_21_24_rsp = router_21_23_rsp_out[0]; - assign router_21_23_to_router_22_23_rsp = router_21_23_rsp_out[1]; - assign router_21_23_to_router_21_22_rsp = router_21_23_rsp_out[2]; - assign router_21_23_to_router_20_23_rsp = router_21_23_rsp_out[3]; - assign router_21_23_to_magia_tile_ni_21_23_rsp = router_21_23_rsp_out[4]; - - assign router_21_23_to_router_21_24_req = router_21_23_req_out[0]; - assign router_21_23_to_router_22_23_req = router_21_23_req_out[1]; - assign router_21_23_to_router_21_22_req = router_21_23_req_out[2]; - assign router_21_23_to_router_20_23_req = router_21_23_req_out[3]; - assign router_21_23_to_magia_tile_ni_21_23_req = router_21_23_req_out[4]; - - assign router_21_23_rsp_in[0] = router_21_24_to_router_21_23_rsp; - assign router_21_23_rsp_in[1] = router_22_23_to_router_21_23_rsp; - assign router_21_23_rsp_in[2] = router_21_22_to_router_21_23_rsp; - assign router_21_23_rsp_in[3] = router_20_23_to_router_21_23_rsp; - assign router_21_23_rsp_in[4] = magia_tile_ni_21_23_to_router_21_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_23_req_in), - .floo_rsp_o (router_21_23_rsp_out), - .floo_req_o (router_21_23_req_out), - .floo_rsp_i (router_21_23_rsp_in) -); - - -floo_req_t [4:0] router_21_24_req_in; -floo_rsp_t [4:0] router_21_24_rsp_out; -floo_req_t [4:0] router_21_24_req_out; -floo_rsp_t [4:0] router_21_24_rsp_in; - - assign router_21_24_req_in[0] = router_21_25_to_router_21_24_req; - assign router_21_24_req_in[1] = router_22_24_to_router_21_24_req; - assign router_21_24_req_in[2] = router_21_23_to_router_21_24_req; - assign router_21_24_req_in[3] = router_20_24_to_router_21_24_req; - assign router_21_24_req_in[4] = magia_tile_ni_21_24_to_router_21_24_req; - - assign router_21_24_to_router_21_25_rsp = router_21_24_rsp_out[0]; - assign router_21_24_to_router_22_24_rsp = router_21_24_rsp_out[1]; - assign router_21_24_to_router_21_23_rsp = router_21_24_rsp_out[2]; - assign router_21_24_to_router_20_24_rsp = router_21_24_rsp_out[3]; - assign router_21_24_to_magia_tile_ni_21_24_rsp = router_21_24_rsp_out[4]; - - assign router_21_24_to_router_21_25_req = router_21_24_req_out[0]; - assign router_21_24_to_router_22_24_req = router_21_24_req_out[1]; - assign router_21_24_to_router_21_23_req = router_21_24_req_out[2]; - assign router_21_24_to_router_20_24_req = router_21_24_req_out[3]; - assign router_21_24_to_magia_tile_ni_21_24_req = router_21_24_req_out[4]; - - assign router_21_24_rsp_in[0] = router_21_25_to_router_21_24_rsp; - assign router_21_24_rsp_in[1] = router_22_24_to_router_21_24_rsp; - assign router_21_24_rsp_in[2] = router_21_23_to_router_21_24_rsp; - assign router_21_24_rsp_in[3] = router_20_24_to_router_21_24_rsp; - assign router_21_24_rsp_in[4] = magia_tile_ni_21_24_to_router_21_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_24_req_in), - .floo_rsp_o (router_21_24_rsp_out), - .floo_req_o (router_21_24_req_out), - .floo_rsp_i (router_21_24_rsp_in) -); - - -floo_req_t [4:0] router_21_25_req_in; -floo_rsp_t [4:0] router_21_25_rsp_out; -floo_req_t [4:0] router_21_25_req_out; -floo_rsp_t [4:0] router_21_25_rsp_in; - - assign router_21_25_req_in[0] = router_21_26_to_router_21_25_req; - assign router_21_25_req_in[1] = router_22_25_to_router_21_25_req; - assign router_21_25_req_in[2] = router_21_24_to_router_21_25_req; - assign router_21_25_req_in[3] = router_20_25_to_router_21_25_req; - assign router_21_25_req_in[4] = magia_tile_ni_21_25_to_router_21_25_req; - - assign router_21_25_to_router_21_26_rsp = router_21_25_rsp_out[0]; - assign router_21_25_to_router_22_25_rsp = router_21_25_rsp_out[1]; - assign router_21_25_to_router_21_24_rsp = router_21_25_rsp_out[2]; - assign router_21_25_to_router_20_25_rsp = router_21_25_rsp_out[3]; - assign router_21_25_to_magia_tile_ni_21_25_rsp = router_21_25_rsp_out[4]; - - assign router_21_25_to_router_21_26_req = router_21_25_req_out[0]; - assign router_21_25_to_router_22_25_req = router_21_25_req_out[1]; - assign router_21_25_to_router_21_24_req = router_21_25_req_out[2]; - assign router_21_25_to_router_20_25_req = router_21_25_req_out[3]; - assign router_21_25_to_magia_tile_ni_21_25_req = router_21_25_req_out[4]; - - assign router_21_25_rsp_in[0] = router_21_26_to_router_21_25_rsp; - assign router_21_25_rsp_in[1] = router_22_25_to_router_21_25_rsp; - assign router_21_25_rsp_in[2] = router_21_24_to_router_21_25_rsp; - assign router_21_25_rsp_in[3] = router_20_25_to_router_21_25_rsp; - assign router_21_25_rsp_in[4] = magia_tile_ni_21_25_to_router_21_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_25_req_in), - .floo_rsp_o (router_21_25_rsp_out), - .floo_req_o (router_21_25_req_out), - .floo_rsp_i (router_21_25_rsp_in) -); - - -floo_req_t [4:0] router_21_26_req_in; -floo_rsp_t [4:0] router_21_26_rsp_out; -floo_req_t [4:0] router_21_26_req_out; -floo_rsp_t [4:0] router_21_26_rsp_in; - - assign router_21_26_req_in[0] = router_21_27_to_router_21_26_req; - assign router_21_26_req_in[1] = router_22_26_to_router_21_26_req; - assign router_21_26_req_in[2] = router_21_25_to_router_21_26_req; - assign router_21_26_req_in[3] = router_20_26_to_router_21_26_req; - assign router_21_26_req_in[4] = magia_tile_ni_21_26_to_router_21_26_req; - - assign router_21_26_to_router_21_27_rsp = router_21_26_rsp_out[0]; - assign router_21_26_to_router_22_26_rsp = router_21_26_rsp_out[1]; - assign router_21_26_to_router_21_25_rsp = router_21_26_rsp_out[2]; - assign router_21_26_to_router_20_26_rsp = router_21_26_rsp_out[3]; - assign router_21_26_to_magia_tile_ni_21_26_rsp = router_21_26_rsp_out[4]; - - assign router_21_26_to_router_21_27_req = router_21_26_req_out[0]; - assign router_21_26_to_router_22_26_req = router_21_26_req_out[1]; - assign router_21_26_to_router_21_25_req = router_21_26_req_out[2]; - assign router_21_26_to_router_20_26_req = router_21_26_req_out[3]; - assign router_21_26_to_magia_tile_ni_21_26_req = router_21_26_req_out[4]; - - assign router_21_26_rsp_in[0] = router_21_27_to_router_21_26_rsp; - assign router_21_26_rsp_in[1] = router_22_26_to_router_21_26_rsp; - assign router_21_26_rsp_in[2] = router_21_25_to_router_21_26_rsp; - assign router_21_26_rsp_in[3] = router_20_26_to_router_21_26_rsp; - assign router_21_26_rsp_in[4] = magia_tile_ni_21_26_to_router_21_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_26_req_in), - .floo_rsp_o (router_21_26_rsp_out), - .floo_req_o (router_21_26_req_out), - .floo_rsp_i (router_21_26_rsp_in) -); - - -floo_req_t [4:0] router_21_27_req_in; -floo_rsp_t [4:0] router_21_27_rsp_out; -floo_req_t [4:0] router_21_27_req_out; -floo_rsp_t [4:0] router_21_27_rsp_in; - - assign router_21_27_req_in[0] = router_21_28_to_router_21_27_req; - assign router_21_27_req_in[1] = router_22_27_to_router_21_27_req; - assign router_21_27_req_in[2] = router_21_26_to_router_21_27_req; - assign router_21_27_req_in[3] = router_20_27_to_router_21_27_req; - assign router_21_27_req_in[4] = magia_tile_ni_21_27_to_router_21_27_req; - - assign router_21_27_to_router_21_28_rsp = router_21_27_rsp_out[0]; - assign router_21_27_to_router_22_27_rsp = router_21_27_rsp_out[1]; - assign router_21_27_to_router_21_26_rsp = router_21_27_rsp_out[2]; - assign router_21_27_to_router_20_27_rsp = router_21_27_rsp_out[3]; - assign router_21_27_to_magia_tile_ni_21_27_rsp = router_21_27_rsp_out[4]; - - assign router_21_27_to_router_21_28_req = router_21_27_req_out[0]; - assign router_21_27_to_router_22_27_req = router_21_27_req_out[1]; - assign router_21_27_to_router_21_26_req = router_21_27_req_out[2]; - assign router_21_27_to_router_20_27_req = router_21_27_req_out[3]; - assign router_21_27_to_magia_tile_ni_21_27_req = router_21_27_req_out[4]; - - assign router_21_27_rsp_in[0] = router_21_28_to_router_21_27_rsp; - assign router_21_27_rsp_in[1] = router_22_27_to_router_21_27_rsp; - assign router_21_27_rsp_in[2] = router_21_26_to_router_21_27_rsp; - assign router_21_27_rsp_in[3] = router_20_27_to_router_21_27_rsp; - assign router_21_27_rsp_in[4] = magia_tile_ni_21_27_to_router_21_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_27_req_in), - .floo_rsp_o (router_21_27_rsp_out), - .floo_req_o (router_21_27_req_out), - .floo_rsp_i (router_21_27_rsp_in) -); - - -floo_req_t [4:0] router_21_28_req_in; -floo_rsp_t [4:0] router_21_28_rsp_out; -floo_req_t [4:0] router_21_28_req_out; -floo_rsp_t [4:0] router_21_28_rsp_in; - - assign router_21_28_req_in[0] = router_21_29_to_router_21_28_req; - assign router_21_28_req_in[1] = router_22_28_to_router_21_28_req; - assign router_21_28_req_in[2] = router_21_27_to_router_21_28_req; - assign router_21_28_req_in[3] = router_20_28_to_router_21_28_req; - assign router_21_28_req_in[4] = magia_tile_ni_21_28_to_router_21_28_req; - - assign router_21_28_to_router_21_29_rsp = router_21_28_rsp_out[0]; - assign router_21_28_to_router_22_28_rsp = router_21_28_rsp_out[1]; - assign router_21_28_to_router_21_27_rsp = router_21_28_rsp_out[2]; - assign router_21_28_to_router_20_28_rsp = router_21_28_rsp_out[3]; - assign router_21_28_to_magia_tile_ni_21_28_rsp = router_21_28_rsp_out[4]; - - assign router_21_28_to_router_21_29_req = router_21_28_req_out[0]; - assign router_21_28_to_router_22_28_req = router_21_28_req_out[1]; - assign router_21_28_to_router_21_27_req = router_21_28_req_out[2]; - assign router_21_28_to_router_20_28_req = router_21_28_req_out[3]; - assign router_21_28_to_magia_tile_ni_21_28_req = router_21_28_req_out[4]; - - assign router_21_28_rsp_in[0] = router_21_29_to_router_21_28_rsp; - assign router_21_28_rsp_in[1] = router_22_28_to_router_21_28_rsp; - assign router_21_28_rsp_in[2] = router_21_27_to_router_21_28_rsp; - assign router_21_28_rsp_in[3] = router_20_28_to_router_21_28_rsp; - assign router_21_28_rsp_in[4] = magia_tile_ni_21_28_to_router_21_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_28_req_in), - .floo_rsp_o (router_21_28_rsp_out), - .floo_req_o (router_21_28_req_out), - .floo_rsp_i (router_21_28_rsp_in) -); - - -floo_req_t [4:0] router_21_29_req_in; -floo_rsp_t [4:0] router_21_29_rsp_out; -floo_req_t [4:0] router_21_29_req_out; -floo_rsp_t [4:0] router_21_29_rsp_in; - - assign router_21_29_req_in[0] = router_21_30_to_router_21_29_req; - assign router_21_29_req_in[1] = router_22_29_to_router_21_29_req; - assign router_21_29_req_in[2] = router_21_28_to_router_21_29_req; - assign router_21_29_req_in[3] = router_20_29_to_router_21_29_req; - assign router_21_29_req_in[4] = magia_tile_ni_21_29_to_router_21_29_req; - - assign router_21_29_to_router_21_30_rsp = router_21_29_rsp_out[0]; - assign router_21_29_to_router_22_29_rsp = router_21_29_rsp_out[1]; - assign router_21_29_to_router_21_28_rsp = router_21_29_rsp_out[2]; - assign router_21_29_to_router_20_29_rsp = router_21_29_rsp_out[3]; - assign router_21_29_to_magia_tile_ni_21_29_rsp = router_21_29_rsp_out[4]; - - assign router_21_29_to_router_21_30_req = router_21_29_req_out[0]; - assign router_21_29_to_router_22_29_req = router_21_29_req_out[1]; - assign router_21_29_to_router_21_28_req = router_21_29_req_out[2]; - assign router_21_29_to_router_20_29_req = router_21_29_req_out[3]; - assign router_21_29_to_magia_tile_ni_21_29_req = router_21_29_req_out[4]; - - assign router_21_29_rsp_in[0] = router_21_30_to_router_21_29_rsp; - assign router_21_29_rsp_in[1] = router_22_29_to_router_21_29_rsp; - assign router_21_29_rsp_in[2] = router_21_28_to_router_21_29_rsp; - assign router_21_29_rsp_in[3] = router_20_29_to_router_21_29_rsp; - assign router_21_29_rsp_in[4] = magia_tile_ni_21_29_to_router_21_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_29_req_in), - .floo_rsp_o (router_21_29_rsp_out), - .floo_req_o (router_21_29_req_out), - .floo_rsp_i (router_21_29_rsp_in) -); - - -floo_req_t [4:0] router_21_30_req_in; -floo_rsp_t [4:0] router_21_30_rsp_out; -floo_req_t [4:0] router_21_30_req_out; -floo_rsp_t [4:0] router_21_30_rsp_in; - - assign router_21_30_req_in[0] = router_21_31_to_router_21_30_req; - assign router_21_30_req_in[1] = router_22_30_to_router_21_30_req; - assign router_21_30_req_in[2] = router_21_29_to_router_21_30_req; - assign router_21_30_req_in[3] = router_20_30_to_router_21_30_req; - assign router_21_30_req_in[4] = magia_tile_ni_21_30_to_router_21_30_req; - - assign router_21_30_to_router_21_31_rsp = router_21_30_rsp_out[0]; - assign router_21_30_to_router_22_30_rsp = router_21_30_rsp_out[1]; - assign router_21_30_to_router_21_29_rsp = router_21_30_rsp_out[2]; - assign router_21_30_to_router_20_30_rsp = router_21_30_rsp_out[3]; - assign router_21_30_to_magia_tile_ni_21_30_rsp = router_21_30_rsp_out[4]; - - assign router_21_30_to_router_21_31_req = router_21_30_req_out[0]; - assign router_21_30_to_router_22_30_req = router_21_30_req_out[1]; - assign router_21_30_to_router_21_29_req = router_21_30_req_out[2]; - assign router_21_30_to_router_20_30_req = router_21_30_req_out[3]; - assign router_21_30_to_magia_tile_ni_21_30_req = router_21_30_req_out[4]; - - assign router_21_30_rsp_in[0] = router_21_31_to_router_21_30_rsp; - assign router_21_30_rsp_in[1] = router_22_30_to_router_21_30_rsp; - assign router_21_30_rsp_in[2] = router_21_29_to_router_21_30_rsp; - assign router_21_30_rsp_in[3] = router_20_30_to_router_21_30_rsp; - assign router_21_30_rsp_in[4] = magia_tile_ni_21_30_to_router_21_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_30_req_in), - .floo_rsp_o (router_21_30_rsp_out), - .floo_req_o (router_21_30_req_out), - .floo_rsp_i (router_21_30_rsp_in) -); - - -floo_req_t [4:0] router_21_31_req_in; -floo_rsp_t [4:0] router_21_31_rsp_out; -floo_req_t [4:0] router_21_31_req_out; -floo_rsp_t [4:0] router_21_31_rsp_in; - - assign router_21_31_req_in[0] = '0; - assign router_21_31_req_in[1] = router_22_31_to_router_21_31_req; - assign router_21_31_req_in[2] = router_21_30_to_router_21_31_req; - assign router_21_31_req_in[3] = router_20_31_to_router_21_31_req; - assign router_21_31_req_in[4] = magia_tile_ni_21_31_to_router_21_31_req; - - assign router_21_31_to_router_22_31_rsp = router_21_31_rsp_out[1]; - assign router_21_31_to_router_21_30_rsp = router_21_31_rsp_out[2]; - assign router_21_31_to_router_20_31_rsp = router_21_31_rsp_out[3]; - assign router_21_31_to_magia_tile_ni_21_31_rsp = router_21_31_rsp_out[4]; - - assign router_21_31_to_router_22_31_req = router_21_31_req_out[1]; - assign router_21_31_to_router_21_30_req = router_21_31_req_out[2]; - assign router_21_31_to_router_20_31_req = router_21_31_req_out[3]; - assign router_21_31_to_magia_tile_ni_21_31_req = router_21_31_req_out[4]; - - assign router_21_31_rsp_in[0] = '0; - assign router_21_31_rsp_in[1] = router_22_31_to_router_21_31_rsp; - assign router_21_31_rsp_in[2] = router_21_30_to_router_21_31_rsp; - assign router_21_31_rsp_in[3] = router_20_31_to_router_21_31_rsp; - assign router_21_31_rsp_in[4] = magia_tile_ni_21_31_to_router_21_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_21_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 22, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_21_31_req_in), - .floo_rsp_o (router_21_31_rsp_out), - .floo_req_o (router_21_31_req_out), - .floo_rsp_i (router_21_31_rsp_in) -); - - -floo_req_t [4:0] router_22_0_req_in; -floo_rsp_t [4:0] router_22_0_rsp_out; -floo_req_t [4:0] router_22_0_req_out; -floo_rsp_t [4:0] router_22_0_rsp_in; - - assign router_22_0_req_in[0] = router_22_1_to_router_22_0_req; - assign router_22_0_req_in[1] = router_23_0_to_router_22_0_req; - assign router_22_0_req_in[2] = '0; - assign router_22_0_req_in[3] = router_21_0_to_router_22_0_req; - assign router_22_0_req_in[4] = magia_tile_ni_22_0_to_router_22_0_req; - - assign router_22_0_to_router_22_1_rsp = router_22_0_rsp_out[0]; - assign router_22_0_to_router_23_0_rsp = router_22_0_rsp_out[1]; - assign router_22_0_to_router_21_0_rsp = router_22_0_rsp_out[3]; - assign router_22_0_to_magia_tile_ni_22_0_rsp = router_22_0_rsp_out[4]; - - assign router_22_0_to_router_22_1_req = router_22_0_req_out[0]; - assign router_22_0_to_router_23_0_req = router_22_0_req_out[1]; - assign router_22_0_to_router_21_0_req = router_22_0_req_out[3]; - assign router_22_0_to_magia_tile_ni_22_0_req = router_22_0_req_out[4]; - - assign router_22_0_rsp_in[0] = router_22_1_to_router_22_0_rsp; - assign router_22_0_rsp_in[1] = router_23_0_to_router_22_0_rsp; - assign router_22_0_rsp_in[2] = '0; - assign router_22_0_rsp_in[3] = router_21_0_to_router_22_0_rsp; - assign router_22_0_rsp_in[4] = magia_tile_ni_22_0_to_router_22_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_0_req_in), - .floo_rsp_o (router_22_0_rsp_out), - .floo_req_o (router_22_0_req_out), - .floo_rsp_i (router_22_0_rsp_in) -); - - -floo_req_t [4:0] router_22_1_req_in; -floo_rsp_t [4:0] router_22_1_rsp_out; -floo_req_t [4:0] router_22_1_req_out; -floo_rsp_t [4:0] router_22_1_rsp_in; - - assign router_22_1_req_in[0] = router_22_2_to_router_22_1_req; - assign router_22_1_req_in[1] = router_23_1_to_router_22_1_req; - assign router_22_1_req_in[2] = router_22_0_to_router_22_1_req; - assign router_22_1_req_in[3] = router_21_1_to_router_22_1_req; - assign router_22_1_req_in[4] = magia_tile_ni_22_1_to_router_22_1_req; - - assign router_22_1_to_router_22_2_rsp = router_22_1_rsp_out[0]; - assign router_22_1_to_router_23_1_rsp = router_22_1_rsp_out[1]; - assign router_22_1_to_router_22_0_rsp = router_22_1_rsp_out[2]; - assign router_22_1_to_router_21_1_rsp = router_22_1_rsp_out[3]; - assign router_22_1_to_magia_tile_ni_22_1_rsp = router_22_1_rsp_out[4]; - - assign router_22_1_to_router_22_2_req = router_22_1_req_out[0]; - assign router_22_1_to_router_23_1_req = router_22_1_req_out[1]; - assign router_22_1_to_router_22_0_req = router_22_1_req_out[2]; - assign router_22_1_to_router_21_1_req = router_22_1_req_out[3]; - assign router_22_1_to_magia_tile_ni_22_1_req = router_22_1_req_out[4]; - - assign router_22_1_rsp_in[0] = router_22_2_to_router_22_1_rsp; - assign router_22_1_rsp_in[1] = router_23_1_to_router_22_1_rsp; - assign router_22_1_rsp_in[2] = router_22_0_to_router_22_1_rsp; - assign router_22_1_rsp_in[3] = router_21_1_to_router_22_1_rsp; - assign router_22_1_rsp_in[4] = magia_tile_ni_22_1_to_router_22_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_1_req_in), - .floo_rsp_o (router_22_1_rsp_out), - .floo_req_o (router_22_1_req_out), - .floo_rsp_i (router_22_1_rsp_in) -); - - -floo_req_t [4:0] router_22_2_req_in; -floo_rsp_t [4:0] router_22_2_rsp_out; -floo_req_t [4:0] router_22_2_req_out; -floo_rsp_t [4:0] router_22_2_rsp_in; - - assign router_22_2_req_in[0] = router_22_3_to_router_22_2_req; - assign router_22_2_req_in[1] = router_23_2_to_router_22_2_req; - assign router_22_2_req_in[2] = router_22_1_to_router_22_2_req; - assign router_22_2_req_in[3] = router_21_2_to_router_22_2_req; - assign router_22_2_req_in[4] = magia_tile_ni_22_2_to_router_22_2_req; - - assign router_22_2_to_router_22_3_rsp = router_22_2_rsp_out[0]; - assign router_22_2_to_router_23_2_rsp = router_22_2_rsp_out[1]; - assign router_22_2_to_router_22_1_rsp = router_22_2_rsp_out[2]; - assign router_22_2_to_router_21_2_rsp = router_22_2_rsp_out[3]; - assign router_22_2_to_magia_tile_ni_22_2_rsp = router_22_2_rsp_out[4]; - - assign router_22_2_to_router_22_3_req = router_22_2_req_out[0]; - assign router_22_2_to_router_23_2_req = router_22_2_req_out[1]; - assign router_22_2_to_router_22_1_req = router_22_2_req_out[2]; - assign router_22_2_to_router_21_2_req = router_22_2_req_out[3]; - assign router_22_2_to_magia_tile_ni_22_2_req = router_22_2_req_out[4]; - - assign router_22_2_rsp_in[0] = router_22_3_to_router_22_2_rsp; - assign router_22_2_rsp_in[1] = router_23_2_to_router_22_2_rsp; - assign router_22_2_rsp_in[2] = router_22_1_to_router_22_2_rsp; - assign router_22_2_rsp_in[3] = router_21_2_to_router_22_2_rsp; - assign router_22_2_rsp_in[4] = magia_tile_ni_22_2_to_router_22_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_2_req_in), - .floo_rsp_o (router_22_2_rsp_out), - .floo_req_o (router_22_2_req_out), - .floo_rsp_i (router_22_2_rsp_in) -); - - -floo_req_t [4:0] router_22_3_req_in; -floo_rsp_t [4:0] router_22_3_rsp_out; -floo_req_t [4:0] router_22_3_req_out; -floo_rsp_t [4:0] router_22_3_rsp_in; - - assign router_22_3_req_in[0] = router_22_4_to_router_22_3_req; - assign router_22_3_req_in[1] = router_23_3_to_router_22_3_req; - assign router_22_3_req_in[2] = router_22_2_to_router_22_3_req; - assign router_22_3_req_in[3] = router_21_3_to_router_22_3_req; - assign router_22_3_req_in[4] = magia_tile_ni_22_3_to_router_22_3_req; - - assign router_22_3_to_router_22_4_rsp = router_22_3_rsp_out[0]; - assign router_22_3_to_router_23_3_rsp = router_22_3_rsp_out[1]; - assign router_22_3_to_router_22_2_rsp = router_22_3_rsp_out[2]; - assign router_22_3_to_router_21_3_rsp = router_22_3_rsp_out[3]; - assign router_22_3_to_magia_tile_ni_22_3_rsp = router_22_3_rsp_out[4]; - - assign router_22_3_to_router_22_4_req = router_22_3_req_out[0]; - assign router_22_3_to_router_23_3_req = router_22_3_req_out[1]; - assign router_22_3_to_router_22_2_req = router_22_3_req_out[2]; - assign router_22_3_to_router_21_3_req = router_22_3_req_out[3]; - assign router_22_3_to_magia_tile_ni_22_3_req = router_22_3_req_out[4]; - - assign router_22_3_rsp_in[0] = router_22_4_to_router_22_3_rsp; - assign router_22_3_rsp_in[1] = router_23_3_to_router_22_3_rsp; - assign router_22_3_rsp_in[2] = router_22_2_to_router_22_3_rsp; - assign router_22_3_rsp_in[3] = router_21_3_to_router_22_3_rsp; - assign router_22_3_rsp_in[4] = magia_tile_ni_22_3_to_router_22_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_3_req_in), - .floo_rsp_o (router_22_3_rsp_out), - .floo_req_o (router_22_3_req_out), - .floo_rsp_i (router_22_3_rsp_in) -); - - -floo_req_t [4:0] router_22_4_req_in; -floo_rsp_t [4:0] router_22_4_rsp_out; -floo_req_t [4:0] router_22_4_req_out; -floo_rsp_t [4:0] router_22_4_rsp_in; - - assign router_22_4_req_in[0] = router_22_5_to_router_22_4_req; - assign router_22_4_req_in[1] = router_23_4_to_router_22_4_req; - assign router_22_4_req_in[2] = router_22_3_to_router_22_4_req; - assign router_22_4_req_in[3] = router_21_4_to_router_22_4_req; - assign router_22_4_req_in[4] = magia_tile_ni_22_4_to_router_22_4_req; - - assign router_22_4_to_router_22_5_rsp = router_22_4_rsp_out[0]; - assign router_22_4_to_router_23_4_rsp = router_22_4_rsp_out[1]; - assign router_22_4_to_router_22_3_rsp = router_22_4_rsp_out[2]; - assign router_22_4_to_router_21_4_rsp = router_22_4_rsp_out[3]; - assign router_22_4_to_magia_tile_ni_22_4_rsp = router_22_4_rsp_out[4]; - - assign router_22_4_to_router_22_5_req = router_22_4_req_out[0]; - assign router_22_4_to_router_23_4_req = router_22_4_req_out[1]; - assign router_22_4_to_router_22_3_req = router_22_4_req_out[2]; - assign router_22_4_to_router_21_4_req = router_22_4_req_out[3]; - assign router_22_4_to_magia_tile_ni_22_4_req = router_22_4_req_out[4]; - - assign router_22_4_rsp_in[0] = router_22_5_to_router_22_4_rsp; - assign router_22_4_rsp_in[1] = router_23_4_to_router_22_4_rsp; - assign router_22_4_rsp_in[2] = router_22_3_to_router_22_4_rsp; - assign router_22_4_rsp_in[3] = router_21_4_to_router_22_4_rsp; - assign router_22_4_rsp_in[4] = magia_tile_ni_22_4_to_router_22_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_4_req_in), - .floo_rsp_o (router_22_4_rsp_out), - .floo_req_o (router_22_4_req_out), - .floo_rsp_i (router_22_4_rsp_in) -); - - -floo_req_t [4:0] router_22_5_req_in; -floo_rsp_t [4:0] router_22_5_rsp_out; -floo_req_t [4:0] router_22_5_req_out; -floo_rsp_t [4:0] router_22_5_rsp_in; - - assign router_22_5_req_in[0] = router_22_6_to_router_22_5_req; - assign router_22_5_req_in[1] = router_23_5_to_router_22_5_req; - assign router_22_5_req_in[2] = router_22_4_to_router_22_5_req; - assign router_22_5_req_in[3] = router_21_5_to_router_22_5_req; - assign router_22_5_req_in[4] = magia_tile_ni_22_5_to_router_22_5_req; - - assign router_22_5_to_router_22_6_rsp = router_22_5_rsp_out[0]; - assign router_22_5_to_router_23_5_rsp = router_22_5_rsp_out[1]; - assign router_22_5_to_router_22_4_rsp = router_22_5_rsp_out[2]; - assign router_22_5_to_router_21_5_rsp = router_22_5_rsp_out[3]; - assign router_22_5_to_magia_tile_ni_22_5_rsp = router_22_5_rsp_out[4]; - - assign router_22_5_to_router_22_6_req = router_22_5_req_out[0]; - assign router_22_5_to_router_23_5_req = router_22_5_req_out[1]; - assign router_22_5_to_router_22_4_req = router_22_5_req_out[2]; - assign router_22_5_to_router_21_5_req = router_22_5_req_out[3]; - assign router_22_5_to_magia_tile_ni_22_5_req = router_22_5_req_out[4]; - - assign router_22_5_rsp_in[0] = router_22_6_to_router_22_5_rsp; - assign router_22_5_rsp_in[1] = router_23_5_to_router_22_5_rsp; - assign router_22_5_rsp_in[2] = router_22_4_to_router_22_5_rsp; - assign router_22_5_rsp_in[3] = router_21_5_to_router_22_5_rsp; - assign router_22_5_rsp_in[4] = magia_tile_ni_22_5_to_router_22_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_5_req_in), - .floo_rsp_o (router_22_5_rsp_out), - .floo_req_o (router_22_5_req_out), - .floo_rsp_i (router_22_5_rsp_in) -); - - -floo_req_t [4:0] router_22_6_req_in; -floo_rsp_t [4:0] router_22_6_rsp_out; -floo_req_t [4:0] router_22_6_req_out; -floo_rsp_t [4:0] router_22_6_rsp_in; - - assign router_22_6_req_in[0] = router_22_7_to_router_22_6_req; - assign router_22_6_req_in[1] = router_23_6_to_router_22_6_req; - assign router_22_6_req_in[2] = router_22_5_to_router_22_6_req; - assign router_22_6_req_in[3] = router_21_6_to_router_22_6_req; - assign router_22_6_req_in[4] = magia_tile_ni_22_6_to_router_22_6_req; - - assign router_22_6_to_router_22_7_rsp = router_22_6_rsp_out[0]; - assign router_22_6_to_router_23_6_rsp = router_22_6_rsp_out[1]; - assign router_22_6_to_router_22_5_rsp = router_22_6_rsp_out[2]; - assign router_22_6_to_router_21_6_rsp = router_22_6_rsp_out[3]; - assign router_22_6_to_magia_tile_ni_22_6_rsp = router_22_6_rsp_out[4]; - - assign router_22_6_to_router_22_7_req = router_22_6_req_out[0]; - assign router_22_6_to_router_23_6_req = router_22_6_req_out[1]; - assign router_22_6_to_router_22_5_req = router_22_6_req_out[2]; - assign router_22_6_to_router_21_6_req = router_22_6_req_out[3]; - assign router_22_6_to_magia_tile_ni_22_6_req = router_22_6_req_out[4]; - - assign router_22_6_rsp_in[0] = router_22_7_to_router_22_6_rsp; - assign router_22_6_rsp_in[1] = router_23_6_to_router_22_6_rsp; - assign router_22_6_rsp_in[2] = router_22_5_to_router_22_6_rsp; - assign router_22_6_rsp_in[3] = router_21_6_to_router_22_6_rsp; - assign router_22_6_rsp_in[4] = magia_tile_ni_22_6_to_router_22_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_6_req_in), - .floo_rsp_o (router_22_6_rsp_out), - .floo_req_o (router_22_6_req_out), - .floo_rsp_i (router_22_6_rsp_in) -); - - -floo_req_t [4:0] router_22_7_req_in; -floo_rsp_t [4:0] router_22_7_rsp_out; -floo_req_t [4:0] router_22_7_req_out; -floo_rsp_t [4:0] router_22_7_rsp_in; - - assign router_22_7_req_in[0] = router_22_8_to_router_22_7_req; - assign router_22_7_req_in[1] = router_23_7_to_router_22_7_req; - assign router_22_7_req_in[2] = router_22_6_to_router_22_7_req; - assign router_22_7_req_in[3] = router_21_7_to_router_22_7_req; - assign router_22_7_req_in[4] = magia_tile_ni_22_7_to_router_22_7_req; - - assign router_22_7_to_router_22_8_rsp = router_22_7_rsp_out[0]; - assign router_22_7_to_router_23_7_rsp = router_22_7_rsp_out[1]; - assign router_22_7_to_router_22_6_rsp = router_22_7_rsp_out[2]; - assign router_22_7_to_router_21_7_rsp = router_22_7_rsp_out[3]; - assign router_22_7_to_magia_tile_ni_22_7_rsp = router_22_7_rsp_out[4]; - - assign router_22_7_to_router_22_8_req = router_22_7_req_out[0]; - assign router_22_7_to_router_23_7_req = router_22_7_req_out[1]; - assign router_22_7_to_router_22_6_req = router_22_7_req_out[2]; - assign router_22_7_to_router_21_7_req = router_22_7_req_out[3]; - assign router_22_7_to_magia_tile_ni_22_7_req = router_22_7_req_out[4]; - - assign router_22_7_rsp_in[0] = router_22_8_to_router_22_7_rsp; - assign router_22_7_rsp_in[1] = router_23_7_to_router_22_7_rsp; - assign router_22_7_rsp_in[2] = router_22_6_to_router_22_7_rsp; - assign router_22_7_rsp_in[3] = router_21_7_to_router_22_7_rsp; - assign router_22_7_rsp_in[4] = magia_tile_ni_22_7_to_router_22_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_7_req_in), - .floo_rsp_o (router_22_7_rsp_out), - .floo_req_o (router_22_7_req_out), - .floo_rsp_i (router_22_7_rsp_in) -); - - -floo_req_t [4:0] router_22_8_req_in; -floo_rsp_t [4:0] router_22_8_rsp_out; -floo_req_t [4:0] router_22_8_req_out; -floo_rsp_t [4:0] router_22_8_rsp_in; - - assign router_22_8_req_in[0] = router_22_9_to_router_22_8_req; - assign router_22_8_req_in[1] = router_23_8_to_router_22_8_req; - assign router_22_8_req_in[2] = router_22_7_to_router_22_8_req; - assign router_22_8_req_in[3] = router_21_8_to_router_22_8_req; - assign router_22_8_req_in[4] = magia_tile_ni_22_8_to_router_22_8_req; - - assign router_22_8_to_router_22_9_rsp = router_22_8_rsp_out[0]; - assign router_22_8_to_router_23_8_rsp = router_22_8_rsp_out[1]; - assign router_22_8_to_router_22_7_rsp = router_22_8_rsp_out[2]; - assign router_22_8_to_router_21_8_rsp = router_22_8_rsp_out[3]; - assign router_22_8_to_magia_tile_ni_22_8_rsp = router_22_8_rsp_out[4]; - - assign router_22_8_to_router_22_9_req = router_22_8_req_out[0]; - assign router_22_8_to_router_23_8_req = router_22_8_req_out[1]; - assign router_22_8_to_router_22_7_req = router_22_8_req_out[2]; - assign router_22_8_to_router_21_8_req = router_22_8_req_out[3]; - assign router_22_8_to_magia_tile_ni_22_8_req = router_22_8_req_out[4]; - - assign router_22_8_rsp_in[0] = router_22_9_to_router_22_8_rsp; - assign router_22_8_rsp_in[1] = router_23_8_to_router_22_8_rsp; - assign router_22_8_rsp_in[2] = router_22_7_to_router_22_8_rsp; - assign router_22_8_rsp_in[3] = router_21_8_to_router_22_8_rsp; - assign router_22_8_rsp_in[4] = magia_tile_ni_22_8_to_router_22_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_8_req_in), - .floo_rsp_o (router_22_8_rsp_out), - .floo_req_o (router_22_8_req_out), - .floo_rsp_i (router_22_8_rsp_in) -); - - -floo_req_t [4:0] router_22_9_req_in; -floo_rsp_t [4:0] router_22_9_rsp_out; -floo_req_t [4:0] router_22_9_req_out; -floo_rsp_t [4:0] router_22_9_rsp_in; - - assign router_22_9_req_in[0] = router_22_10_to_router_22_9_req; - assign router_22_9_req_in[1] = router_23_9_to_router_22_9_req; - assign router_22_9_req_in[2] = router_22_8_to_router_22_9_req; - assign router_22_9_req_in[3] = router_21_9_to_router_22_9_req; - assign router_22_9_req_in[4] = magia_tile_ni_22_9_to_router_22_9_req; - - assign router_22_9_to_router_22_10_rsp = router_22_9_rsp_out[0]; - assign router_22_9_to_router_23_9_rsp = router_22_9_rsp_out[1]; - assign router_22_9_to_router_22_8_rsp = router_22_9_rsp_out[2]; - assign router_22_9_to_router_21_9_rsp = router_22_9_rsp_out[3]; - assign router_22_9_to_magia_tile_ni_22_9_rsp = router_22_9_rsp_out[4]; - - assign router_22_9_to_router_22_10_req = router_22_9_req_out[0]; - assign router_22_9_to_router_23_9_req = router_22_9_req_out[1]; - assign router_22_9_to_router_22_8_req = router_22_9_req_out[2]; - assign router_22_9_to_router_21_9_req = router_22_9_req_out[3]; - assign router_22_9_to_magia_tile_ni_22_9_req = router_22_9_req_out[4]; - - assign router_22_9_rsp_in[0] = router_22_10_to_router_22_9_rsp; - assign router_22_9_rsp_in[1] = router_23_9_to_router_22_9_rsp; - assign router_22_9_rsp_in[2] = router_22_8_to_router_22_9_rsp; - assign router_22_9_rsp_in[3] = router_21_9_to_router_22_9_rsp; - assign router_22_9_rsp_in[4] = magia_tile_ni_22_9_to_router_22_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_9_req_in), - .floo_rsp_o (router_22_9_rsp_out), - .floo_req_o (router_22_9_req_out), - .floo_rsp_i (router_22_9_rsp_in) -); - - -floo_req_t [4:0] router_22_10_req_in; -floo_rsp_t [4:0] router_22_10_rsp_out; -floo_req_t [4:0] router_22_10_req_out; -floo_rsp_t [4:0] router_22_10_rsp_in; - - assign router_22_10_req_in[0] = router_22_11_to_router_22_10_req; - assign router_22_10_req_in[1] = router_23_10_to_router_22_10_req; - assign router_22_10_req_in[2] = router_22_9_to_router_22_10_req; - assign router_22_10_req_in[3] = router_21_10_to_router_22_10_req; - assign router_22_10_req_in[4] = magia_tile_ni_22_10_to_router_22_10_req; - - assign router_22_10_to_router_22_11_rsp = router_22_10_rsp_out[0]; - assign router_22_10_to_router_23_10_rsp = router_22_10_rsp_out[1]; - assign router_22_10_to_router_22_9_rsp = router_22_10_rsp_out[2]; - assign router_22_10_to_router_21_10_rsp = router_22_10_rsp_out[3]; - assign router_22_10_to_magia_tile_ni_22_10_rsp = router_22_10_rsp_out[4]; - - assign router_22_10_to_router_22_11_req = router_22_10_req_out[0]; - assign router_22_10_to_router_23_10_req = router_22_10_req_out[1]; - assign router_22_10_to_router_22_9_req = router_22_10_req_out[2]; - assign router_22_10_to_router_21_10_req = router_22_10_req_out[3]; - assign router_22_10_to_magia_tile_ni_22_10_req = router_22_10_req_out[4]; - - assign router_22_10_rsp_in[0] = router_22_11_to_router_22_10_rsp; - assign router_22_10_rsp_in[1] = router_23_10_to_router_22_10_rsp; - assign router_22_10_rsp_in[2] = router_22_9_to_router_22_10_rsp; - assign router_22_10_rsp_in[3] = router_21_10_to_router_22_10_rsp; - assign router_22_10_rsp_in[4] = magia_tile_ni_22_10_to_router_22_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_10_req_in), - .floo_rsp_o (router_22_10_rsp_out), - .floo_req_o (router_22_10_req_out), - .floo_rsp_i (router_22_10_rsp_in) -); - - -floo_req_t [4:0] router_22_11_req_in; -floo_rsp_t [4:0] router_22_11_rsp_out; -floo_req_t [4:0] router_22_11_req_out; -floo_rsp_t [4:0] router_22_11_rsp_in; - - assign router_22_11_req_in[0] = router_22_12_to_router_22_11_req; - assign router_22_11_req_in[1] = router_23_11_to_router_22_11_req; - assign router_22_11_req_in[2] = router_22_10_to_router_22_11_req; - assign router_22_11_req_in[3] = router_21_11_to_router_22_11_req; - assign router_22_11_req_in[4] = magia_tile_ni_22_11_to_router_22_11_req; - - assign router_22_11_to_router_22_12_rsp = router_22_11_rsp_out[0]; - assign router_22_11_to_router_23_11_rsp = router_22_11_rsp_out[1]; - assign router_22_11_to_router_22_10_rsp = router_22_11_rsp_out[2]; - assign router_22_11_to_router_21_11_rsp = router_22_11_rsp_out[3]; - assign router_22_11_to_magia_tile_ni_22_11_rsp = router_22_11_rsp_out[4]; - - assign router_22_11_to_router_22_12_req = router_22_11_req_out[0]; - assign router_22_11_to_router_23_11_req = router_22_11_req_out[1]; - assign router_22_11_to_router_22_10_req = router_22_11_req_out[2]; - assign router_22_11_to_router_21_11_req = router_22_11_req_out[3]; - assign router_22_11_to_magia_tile_ni_22_11_req = router_22_11_req_out[4]; - - assign router_22_11_rsp_in[0] = router_22_12_to_router_22_11_rsp; - assign router_22_11_rsp_in[1] = router_23_11_to_router_22_11_rsp; - assign router_22_11_rsp_in[2] = router_22_10_to_router_22_11_rsp; - assign router_22_11_rsp_in[3] = router_21_11_to_router_22_11_rsp; - assign router_22_11_rsp_in[4] = magia_tile_ni_22_11_to_router_22_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_11_req_in), - .floo_rsp_o (router_22_11_rsp_out), - .floo_req_o (router_22_11_req_out), - .floo_rsp_i (router_22_11_rsp_in) -); - - -floo_req_t [4:0] router_22_12_req_in; -floo_rsp_t [4:0] router_22_12_rsp_out; -floo_req_t [4:0] router_22_12_req_out; -floo_rsp_t [4:0] router_22_12_rsp_in; - - assign router_22_12_req_in[0] = router_22_13_to_router_22_12_req; - assign router_22_12_req_in[1] = router_23_12_to_router_22_12_req; - assign router_22_12_req_in[2] = router_22_11_to_router_22_12_req; - assign router_22_12_req_in[3] = router_21_12_to_router_22_12_req; - assign router_22_12_req_in[4] = magia_tile_ni_22_12_to_router_22_12_req; - - assign router_22_12_to_router_22_13_rsp = router_22_12_rsp_out[0]; - assign router_22_12_to_router_23_12_rsp = router_22_12_rsp_out[1]; - assign router_22_12_to_router_22_11_rsp = router_22_12_rsp_out[2]; - assign router_22_12_to_router_21_12_rsp = router_22_12_rsp_out[3]; - assign router_22_12_to_magia_tile_ni_22_12_rsp = router_22_12_rsp_out[4]; - - assign router_22_12_to_router_22_13_req = router_22_12_req_out[0]; - assign router_22_12_to_router_23_12_req = router_22_12_req_out[1]; - assign router_22_12_to_router_22_11_req = router_22_12_req_out[2]; - assign router_22_12_to_router_21_12_req = router_22_12_req_out[3]; - assign router_22_12_to_magia_tile_ni_22_12_req = router_22_12_req_out[4]; - - assign router_22_12_rsp_in[0] = router_22_13_to_router_22_12_rsp; - assign router_22_12_rsp_in[1] = router_23_12_to_router_22_12_rsp; - assign router_22_12_rsp_in[2] = router_22_11_to_router_22_12_rsp; - assign router_22_12_rsp_in[3] = router_21_12_to_router_22_12_rsp; - assign router_22_12_rsp_in[4] = magia_tile_ni_22_12_to_router_22_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_12_req_in), - .floo_rsp_o (router_22_12_rsp_out), - .floo_req_o (router_22_12_req_out), - .floo_rsp_i (router_22_12_rsp_in) -); - - -floo_req_t [4:0] router_22_13_req_in; -floo_rsp_t [4:0] router_22_13_rsp_out; -floo_req_t [4:0] router_22_13_req_out; -floo_rsp_t [4:0] router_22_13_rsp_in; - - assign router_22_13_req_in[0] = router_22_14_to_router_22_13_req; - assign router_22_13_req_in[1] = router_23_13_to_router_22_13_req; - assign router_22_13_req_in[2] = router_22_12_to_router_22_13_req; - assign router_22_13_req_in[3] = router_21_13_to_router_22_13_req; - assign router_22_13_req_in[4] = magia_tile_ni_22_13_to_router_22_13_req; - - assign router_22_13_to_router_22_14_rsp = router_22_13_rsp_out[0]; - assign router_22_13_to_router_23_13_rsp = router_22_13_rsp_out[1]; - assign router_22_13_to_router_22_12_rsp = router_22_13_rsp_out[2]; - assign router_22_13_to_router_21_13_rsp = router_22_13_rsp_out[3]; - assign router_22_13_to_magia_tile_ni_22_13_rsp = router_22_13_rsp_out[4]; - - assign router_22_13_to_router_22_14_req = router_22_13_req_out[0]; - assign router_22_13_to_router_23_13_req = router_22_13_req_out[1]; - assign router_22_13_to_router_22_12_req = router_22_13_req_out[2]; - assign router_22_13_to_router_21_13_req = router_22_13_req_out[3]; - assign router_22_13_to_magia_tile_ni_22_13_req = router_22_13_req_out[4]; - - assign router_22_13_rsp_in[0] = router_22_14_to_router_22_13_rsp; - assign router_22_13_rsp_in[1] = router_23_13_to_router_22_13_rsp; - assign router_22_13_rsp_in[2] = router_22_12_to_router_22_13_rsp; - assign router_22_13_rsp_in[3] = router_21_13_to_router_22_13_rsp; - assign router_22_13_rsp_in[4] = magia_tile_ni_22_13_to_router_22_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_13_req_in), - .floo_rsp_o (router_22_13_rsp_out), - .floo_req_o (router_22_13_req_out), - .floo_rsp_i (router_22_13_rsp_in) -); - - -floo_req_t [4:0] router_22_14_req_in; -floo_rsp_t [4:0] router_22_14_rsp_out; -floo_req_t [4:0] router_22_14_req_out; -floo_rsp_t [4:0] router_22_14_rsp_in; - - assign router_22_14_req_in[0] = router_22_15_to_router_22_14_req; - assign router_22_14_req_in[1] = router_23_14_to_router_22_14_req; - assign router_22_14_req_in[2] = router_22_13_to_router_22_14_req; - assign router_22_14_req_in[3] = router_21_14_to_router_22_14_req; - assign router_22_14_req_in[4] = magia_tile_ni_22_14_to_router_22_14_req; - - assign router_22_14_to_router_22_15_rsp = router_22_14_rsp_out[0]; - assign router_22_14_to_router_23_14_rsp = router_22_14_rsp_out[1]; - assign router_22_14_to_router_22_13_rsp = router_22_14_rsp_out[2]; - assign router_22_14_to_router_21_14_rsp = router_22_14_rsp_out[3]; - assign router_22_14_to_magia_tile_ni_22_14_rsp = router_22_14_rsp_out[4]; - - assign router_22_14_to_router_22_15_req = router_22_14_req_out[0]; - assign router_22_14_to_router_23_14_req = router_22_14_req_out[1]; - assign router_22_14_to_router_22_13_req = router_22_14_req_out[2]; - assign router_22_14_to_router_21_14_req = router_22_14_req_out[3]; - assign router_22_14_to_magia_tile_ni_22_14_req = router_22_14_req_out[4]; - - assign router_22_14_rsp_in[0] = router_22_15_to_router_22_14_rsp; - assign router_22_14_rsp_in[1] = router_23_14_to_router_22_14_rsp; - assign router_22_14_rsp_in[2] = router_22_13_to_router_22_14_rsp; - assign router_22_14_rsp_in[3] = router_21_14_to_router_22_14_rsp; - assign router_22_14_rsp_in[4] = magia_tile_ni_22_14_to_router_22_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_14_req_in), - .floo_rsp_o (router_22_14_rsp_out), - .floo_req_o (router_22_14_req_out), - .floo_rsp_i (router_22_14_rsp_in) -); - - -floo_req_t [4:0] router_22_15_req_in; -floo_rsp_t [4:0] router_22_15_rsp_out; -floo_req_t [4:0] router_22_15_req_out; -floo_rsp_t [4:0] router_22_15_rsp_in; - - assign router_22_15_req_in[0] = router_22_16_to_router_22_15_req; - assign router_22_15_req_in[1] = router_23_15_to_router_22_15_req; - assign router_22_15_req_in[2] = router_22_14_to_router_22_15_req; - assign router_22_15_req_in[3] = router_21_15_to_router_22_15_req; - assign router_22_15_req_in[4] = magia_tile_ni_22_15_to_router_22_15_req; - - assign router_22_15_to_router_22_16_rsp = router_22_15_rsp_out[0]; - assign router_22_15_to_router_23_15_rsp = router_22_15_rsp_out[1]; - assign router_22_15_to_router_22_14_rsp = router_22_15_rsp_out[2]; - assign router_22_15_to_router_21_15_rsp = router_22_15_rsp_out[3]; - assign router_22_15_to_magia_tile_ni_22_15_rsp = router_22_15_rsp_out[4]; - - assign router_22_15_to_router_22_16_req = router_22_15_req_out[0]; - assign router_22_15_to_router_23_15_req = router_22_15_req_out[1]; - assign router_22_15_to_router_22_14_req = router_22_15_req_out[2]; - assign router_22_15_to_router_21_15_req = router_22_15_req_out[3]; - assign router_22_15_to_magia_tile_ni_22_15_req = router_22_15_req_out[4]; - - assign router_22_15_rsp_in[0] = router_22_16_to_router_22_15_rsp; - assign router_22_15_rsp_in[1] = router_23_15_to_router_22_15_rsp; - assign router_22_15_rsp_in[2] = router_22_14_to_router_22_15_rsp; - assign router_22_15_rsp_in[3] = router_21_15_to_router_22_15_rsp; - assign router_22_15_rsp_in[4] = magia_tile_ni_22_15_to_router_22_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_15_req_in), - .floo_rsp_o (router_22_15_rsp_out), - .floo_req_o (router_22_15_req_out), - .floo_rsp_i (router_22_15_rsp_in) -); - - -floo_req_t [4:0] router_22_16_req_in; -floo_rsp_t [4:0] router_22_16_rsp_out; -floo_req_t [4:0] router_22_16_req_out; -floo_rsp_t [4:0] router_22_16_rsp_in; - - assign router_22_16_req_in[0] = router_22_17_to_router_22_16_req; - assign router_22_16_req_in[1] = router_23_16_to_router_22_16_req; - assign router_22_16_req_in[2] = router_22_15_to_router_22_16_req; - assign router_22_16_req_in[3] = router_21_16_to_router_22_16_req; - assign router_22_16_req_in[4] = magia_tile_ni_22_16_to_router_22_16_req; - - assign router_22_16_to_router_22_17_rsp = router_22_16_rsp_out[0]; - assign router_22_16_to_router_23_16_rsp = router_22_16_rsp_out[1]; - assign router_22_16_to_router_22_15_rsp = router_22_16_rsp_out[2]; - assign router_22_16_to_router_21_16_rsp = router_22_16_rsp_out[3]; - assign router_22_16_to_magia_tile_ni_22_16_rsp = router_22_16_rsp_out[4]; - - assign router_22_16_to_router_22_17_req = router_22_16_req_out[0]; - assign router_22_16_to_router_23_16_req = router_22_16_req_out[1]; - assign router_22_16_to_router_22_15_req = router_22_16_req_out[2]; - assign router_22_16_to_router_21_16_req = router_22_16_req_out[3]; - assign router_22_16_to_magia_tile_ni_22_16_req = router_22_16_req_out[4]; - - assign router_22_16_rsp_in[0] = router_22_17_to_router_22_16_rsp; - assign router_22_16_rsp_in[1] = router_23_16_to_router_22_16_rsp; - assign router_22_16_rsp_in[2] = router_22_15_to_router_22_16_rsp; - assign router_22_16_rsp_in[3] = router_21_16_to_router_22_16_rsp; - assign router_22_16_rsp_in[4] = magia_tile_ni_22_16_to_router_22_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_16_req_in), - .floo_rsp_o (router_22_16_rsp_out), - .floo_req_o (router_22_16_req_out), - .floo_rsp_i (router_22_16_rsp_in) -); - - -floo_req_t [4:0] router_22_17_req_in; -floo_rsp_t [4:0] router_22_17_rsp_out; -floo_req_t [4:0] router_22_17_req_out; -floo_rsp_t [4:0] router_22_17_rsp_in; - - assign router_22_17_req_in[0] = router_22_18_to_router_22_17_req; - assign router_22_17_req_in[1] = router_23_17_to_router_22_17_req; - assign router_22_17_req_in[2] = router_22_16_to_router_22_17_req; - assign router_22_17_req_in[3] = router_21_17_to_router_22_17_req; - assign router_22_17_req_in[4] = magia_tile_ni_22_17_to_router_22_17_req; - - assign router_22_17_to_router_22_18_rsp = router_22_17_rsp_out[0]; - assign router_22_17_to_router_23_17_rsp = router_22_17_rsp_out[1]; - assign router_22_17_to_router_22_16_rsp = router_22_17_rsp_out[2]; - assign router_22_17_to_router_21_17_rsp = router_22_17_rsp_out[3]; - assign router_22_17_to_magia_tile_ni_22_17_rsp = router_22_17_rsp_out[4]; - - assign router_22_17_to_router_22_18_req = router_22_17_req_out[0]; - assign router_22_17_to_router_23_17_req = router_22_17_req_out[1]; - assign router_22_17_to_router_22_16_req = router_22_17_req_out[2]; - assign router_22_17_to_router_21_17_req = router_22_17_req_out[3]; - assign router_22_17_to_magia_tile_ni_22_17_req = router_22_17_req_out[4]; - - assign router_22_17_rsp_in[0] = router_22_18_to_router_22_17_rsp; - assign router_22_17_rsp_in[1] = router_23_17_to_router_22_17_rsp; - assign router_22_17_rsp_in[2] = router_22_16_to_router_22_17_rsp; - assign router_22_17_rsp_in[3] = router_21_17_to_router_22_17_rsp; - assign router_22_17_rsp_in[4] = magia_tile_ni_22_17_to_router_22_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_17_req_in), - .floo_rsp_o (router_22_17_rsp_out), - .floo_req_o (router_22_17_req_out), - .floo_rsp_i (router_22_17_rsp_in) -); - - -floo_req_t [4:0] router_22_18_req_in; -floo_rsp_t [4:0] router_22_18_rsp_out; -floo_req_t [4:0] router_22_18_req_out; -floo_rsp_t [4:0] router_22_18_rsp_in; - - assign router_22_18_req_in[0] = router_22_19_to_router_22_18_req; - assign router_22_18_req_in[1] = router_23_18_to_router_22_18_req; - assign router_22_18_req_in[2] = router_22_17_to_router_22_18_req; - assign router_22_18_req_in[3] = router_21_18_to_router_22_18_req; - assign router_22_18_req_in[4] = magia_tile_ni_22_18_to_router_22_18_req; - - assign router_22_18_to_router_22_19_rsp = router_22_18_rsp_out[0]; - assign router_22_18_to_router_23_18_rsp = router_22_18_rsp_out[1]; - assign router_22_18_to_router_22_17_rsp = router_22_18_rsp_out[2]; - assign router_22_18_to_router_21_18_rsp = router_22_18_rsp_out[3]; - assign router_22_18_to_magia_tile_ni_22_18_rsp = router_22_18_rsp_out[4]; - - assign router_22_18_to_router_22_19_req = router_22_18_req_out[0]; - assign router_22_18_to_router_23_18_req = router_22_18_req_out[1]; - assign router_22_18_to_router_22_17_req = router_22_18_req_out[2]; - assign router_22_18_to_router_21_18_req = router_22_18_req_out[3]; - assign router_22_18_to_magia_tile_ni_22_18_req = router_22_18_req_out[4]; - - assign router_22_18_rsp_in[0] = router_22_19_to_router_22_18_rsp; - assign router_22_18_rsp_in[1] = router_23_18_to_router_22_18_rsp; - assign router_22_18_rsp_in[2] = router_22_17_to_router_22_18_rsp; - assign router_22_18_rsp_in[3] = router_21_18_to_router_22_18_rsp; - assign router_22_18_rsp_in[4] = magia_tile_ni_22_18_to_router_22_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_18_req_in), - .floo_rsp_o (router_22_18_rsp_out), - .floo_req_o (router_22_18_req_out), - .floo_rsp_i (router_22_18_rsp_in) -); - - -floo_req_t [4:0] router_22_19_req_in; -floo_rsp_t [4:0] router_22_19_rsp_out; -floo_req_t [4:0] router_22_19_req_out; -floo_rsp_t [4:0] router_22_19_rsp_in; - - assign router_22_19_req_in[0] = router_22_20_to_router_22_19_req; - assign router_22_19_req_in[1] = router_23_19_to_router_22_19_req; - assign router_22_19_req_in[2] = router_22_18_to_router_22_19_req; - assign router_22_19_req_in[3] = router_21_19_to_router_22_19_req; - assign router_22_19_req_in[4] = magia_tile_ni_22_19_to_router_22_19_req; - - assign router_22_19_to_router_22_20_rsp = router_22_19_rsp_out[0]; - assign router_22_19_to_router_23_19_rsp = router_22_19_rsp_out[1]; - assign router_22_19_to_router_22_18_rsp = router_22_19_rsp_out[2]; - assign router_22_19_to_router_21_19_rsp = router_22_19_rsp_out[3]; - assign router_22_19_to_magia_tile_ni_22_19_rsp = router_22_19_rsp_out[4]; - - assign router_22_19_to_router_22_20_req = router_22_19_req_out[0]; - assign router_22_19_to_router_23_19_req = router_22_19_req_out[1]; - assign router_22_19_to_router_22_18_req = router_22_19_req_out[2]; - assign router_22_19_to_router_21_19_req = router_22_19_req_out[3]; - assign router_22_19_to_magia_tile_ni_22_19_req = router_22_19_req_out[4]; - - assign router_22_19_rsp_in[0] = router_22_20_to_router_22_19_rsp; - assign router_22_19_rsp_in[1] = router_23_19_to_router_22_19_rsp; - assign router_22_19_rsp_in[2] = router_22_18_to_router_22_19_rsp; - assign router_22_19_rsp_in[3] = router_21_19_to_router_22_19_rsp; - assign router_22_19_rsp_in[4] = magia_tile_ni_22_19_to_router_22_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_19_req_in), - .floo_rsp_o (router_22_19_rsp_out), - .floo_req_o (router_22_19_req_out), - .floo_rsp_i (router_22_19_rsp_in) -); - - -floo_req_t [4:0] router_22_20_req_in; -floo_rsp_t [4:0] router_22_20_rsp_out; -floo_req_t [4:0] router_22_20_req_out; -floo_rsp_t [4:0] router_22_20_rsp_in; - - assign router_22_20_req_in[0] = router_22_21_to_router_22_20_req; - assign router_22_20_req_in[1] = router_23_20_to_router_22_20_req; - assign router_22_20_req_in[2] = router_22_19_to_router_22_20_req; - assign router_22_20_req_in[3] = router_21_20_to_router_22_20_req; - assign router_22_20_req_in[4] = magia_tile_ni_22_20_to_router_22_20_req; - - assign router_22_20_to_router_22_21_rsp = router_22_20_rsp_out[0]; - assign router_22_20_to_router_23_20_rsp = router_22_20_rsp_out[1]; - assign router_22_20_to_router_22_19_rsp = router_22_20_rsp_out[2]; - assign router_22_20_to_router_21_20_rsp = router_22_20_rsp_out[3]; - assign router_22_20_to_magia_tile_ni_22_20_rsp = router_22_20_rsp_out[4]; - - assign router_22_20_to_router_22_21_req = router_22_20_req_out[0]; - assign router_22_20_to_router_23_20_req = router_22_20_req_out[1]; - assign router_22_20_to_router_22_19_req = router_22_20_req_out[2]; - assign router_22_20_to_router_21_20_req = router_22_20_req_out[3]; - assign router_22_20_to_magia_tile_ni_22_20_req = router_22_20_req_out[4]; - - assign router_22_20_rsp_in[0] = router_22_21_to_router_22_20_rsp; - assign router_22_20_rsp_in[1] = router_23_20_to_router_22_20_rsp; - assign router_22_20_rsp_in[2] = router_22_19_to_router_22_20_rsp; - assign router_22_20_rsp_in[3] = router_21_20_to_router_22_20_rsp; - assign router_22_20_rsp_in[4] = magia_tile_ni_22_20_to_router_22_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_20_req_in), - .floo_rsp_o (router_22_20_rsp_out), - .floo_req_o (router_22_20_req_out), - .floo_rsp_i (router_22_20_rsp_in) -); - - -floo_req_t [4:0] router_22_21_req_in; -floo_rsp_t [4:0] router_22_21_rsp_out; -floo_req_t [4:0] router_22_21_req_out; -floo_rsp_t [4:0] router_22_21_rsp_in; - - assign router_22_21_req_in[0] = router_22_22_to_router_22_21_req; - assign router_22_21_req_in[1] = router_23_21_to_router_22_21_req; - assign router_22_21_req_in[2] = router_22_20_to_router_22_21_req; - assign router_22_21_req_in[3] = router_21_21_to_router_22_21_req; - assign router_22_21_req_in[4] = magia_tile_ni_22_21_to_router_22_21_req; - - assign router_22_21_to_router_22_22_rsp = router_22_21_rsp_out[0]; - assign router_22_21_to_router_23_21_rsp = router_22_21_rsp_out[1]; - assign router_22_21_to_router_22_20_rsp = router_22_21_rsp_out[2]; - assign router_22_21_to_router_21_21_rsp = router_22_21_rsp_out[3]; - assign router_22_21_to_magia_tile_ni_22_21_rsp = router_22_21_rsp_out[4]; - - assign router_22_21_to_router_22_22_req = router_22_21_req_out[0]; - assign router_22_21_to_router_23_21_req = router_22_21_req_out[1]; - assign router_22_21_to_router_22_20_req = router_22_21_req_out[2]; - assign router_22_21_to_router_21_21_req = router_22_21_req_out[3]; - assign router_22_21_to_magia_tile_ni_22_21_req = router_22_21_req_out[4]; - - assign router_22_21_rsp_in[0] = router_22_22_to_router_22_21_rsp; - assign router_22_21_rsp_in[1] = router_23_21_to_router_22_21_rsp; - assign router_22_21_rsp_in[2] = router_22_20_to_router_22_21_rsp; - assign router_22_21_rsp_in[3] = router_21_21_to_router_22_21_rsp; - assign router_22_21_rsp_in[4] = magia_tile_ni_22_21_to_router_22_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_21_req_in), - .floo_rsp_o (router_22_21_rsp_out), - .floo_req_o (router_22_21_req_out), - .floo_rsp_i (router_22_21_rsp_in) -); - - -floo_req_t [4:0] router_22_22_req_in; -floo_rsp_t [4:0] router_22_22_rsp_out; -floo_req_t [4:0] router_22_22_req_out; -floo_rsp_t [4:0] router_22_22_rsp_in; - - assign router_22_22_req_in[0] = router_22_23_to_router_22_22_req; - assign router_22_22_req_in[1] = router_23_22_to_router_22_22_req; - assign router_22_22_req_in[2] = router_22_21_to_router_22_22_req; - assign router_22_22_req_in[3] = router_21_22_to_router_22_22_req; - assign router_22_22_req_in[4] = magia_tile_ni_22_22_to_router_22_22_req; - - assign router_22_22_to_router_22_23_rsp = router_22_22_rsp_out[0]; - assign router_22_22_to_router_23_22_rsp = router_22_22_rsp_out[1]; - assign router_22_22_to_router_22_21_rsp = router_22_22_rsp_out[2]; - assign router_22_22_to_router_21_22_rsp = router_22_22_rsp_out[3]; - assign router_22_22_to_magia_tile_ni_22_22_rsp = router_22_22_rsp_out[4]; - - assign router_22_22_to_router_22_23_req = router_22_22_req_out[0]; - assign router_22_22_to_router_23_22_req = router_22_22_req_out[1]; - assign router_22_22_to_router_22_21_req = router_22_22_req_out[2]; - assign router_22_22_to_router_21_22_req = router_22_22_req_out[3]; - assign router_22_22_to_magia_tile_ni_22_22_req = router_22_22_req_out[4]; - - assign router_22_22_rsp_in[0] = router_22_23_to_router_22_22_rsp; - assign router_22_22_rsp_in[1] = router_23_22_to_router_22_22_rsp; - assign router_22_22_rsp_in[2] = router_22_21_to_router_22_22_rsp; - assign router_22_22_rsp_in[3] = router_21_22_to_router_22_22_rsp; - assign router_22_22_rsp_in[4] = magia_tile_ni_22_22_to_router_22_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_22_req_in), - .floo_rsp_o (router_22_22_rsp_out), - .floo_req_o (router_22_22_req_out), - .floo_rsp_i (router_22_22_rsp_in) -); - - -floo_req_t [4:0] router_22_23_req_in; -floo_rsp_t [4:0] router_22_23_rsp_out; -floo_req_t [4:0] router_22_23_req_out; -floo_rsp_t [4:0] router_22_23_rsp_in; - - assign router_22_23_req_in[0] = router_22_24_to_router_22_23_req; - assign router_22_23_req_in[1] = router_23_23_to_router_22_23_req; - assign router_22_23_req_in[2] = router_22_22_to_router_22_23_req; - assign router_22_23_req_in[3] = router_21_23_to_router_22_23_req; - assign router_22_23_req_in[4] = magia_tile_ni_22_23_to_router_22_23_req; - - assign router_22_23_to_router_22_24_rsp = router_22_23_rsp_out[0]; - assign router_22_23_to_router_23_23_rsp = router_22_23_rsp_out[1]; - assign router_22_23_to_router_22_22_rsp = router_22_23_rsp_out[2]; - assign router_22_23_to_router_21_23_rsp = router_22_23_rsp_out[3]; - assign router_22_23_to_magia_tile_ni_22_23_rsp = router_22_23_rsp_out[4]; - - assign router_22_23_to_router_22_24_req = router_22_23_req_out[0]; - assign router_22_23_to_router_23_23_req = router_22_23_req_out[1]; - assign router_22_23_to_router_22_22_req = router_22_23_req_out[2]; - assign router_22_23_to_router_21_23_req = router_22_23_req_out[3]; - assign router_22_23_to_magia_tile_ni_22_23_req = router_22_23_req_out[4]; - - assign router_22_23_rsp_in[0] = router_22_24_to_router_22_23_rsp; - assign router_22_23_rsp_in[1] = router_23_23_to_router_22_23_rsp; - assign router_22_23_rsp_in[2] = router_22_22_to_router_22_23_rsp; - assign router_22_23_rsp_in[3] = router_21_23_to_router_22_23_rsp; - assign router_22_23_rsp_in[4] = magia_tile_ni_22_23_to_router_22_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_23_req_in), - .floo_rsp_o (router_22_23_rsp_out), - .floo_req_o (router_22_23_req_out), - .floo_rsp_i (router_22_23_rsp_in) -); - - -floo_req_t [4:0] router_22_24_req_in; -floo_rsp_t [4:0] router_22_24_rsp_out; -floo_req_t [4:0] router_22_24_req_out; -floo_rsp_t [4:0] router_22_24_rsp_in; - - assign router_22_24_req_in[0] = router_22_25_to_router_22_24_req; - assign router_22_24_req_in[1] = router_23_24_to_router_22_24_req; - assign router_22_24_req_in[2] = router_22_23_to_router_22_24_req; - assign router_22_24_req_in[3] = router_21_24_to_router_22_24_req; - assign router_22_24_req_in[4] = magia_tile_ni_22_24_to_router_22_24_req; - - assign router_22_24_to_router_22_25_rsp = router_22_24_rsp_out[0]; - assign router_22_24_to_router_23_24_rsp = router_22_24_rsp_out[1]; - assign router_22_24_to_router_22_23_rsp = router_22_24_rsp_out[2]; - assign router_22_24_to_router_21_24_rsp = router_22_24_rsp_out[3]; - assign router_22_24_to_magia_tile_ni_22_24_rsp = router_22_24_rsp_out[4]; - - assign router_22_24_to_router_22_25_req = router_22_24_req_out[0]; - assign router_22_24_to_router_23_24_req = router_22_24_req_out[1]; - assign router_22_24_to_router_22_23_req = router_22_24_req_out[2]; - assign router_22_24_to_router_21_24_req = router_22_24_req_out[3]; - assign router_22_24_to_magia_tile_ni_22_24_req = router_22_24_req_out[4]; - - assign router_22_24_rsp_in[0] = router_22_25_to_router_22_24_rsp; - assign router_22_24_rsp_in[1] = router_23_24_to_router_22_24_rsp; - assign router_22_24_rsp_in[2] = router_22_23_to_router_22_24_rsp; - assign router_22_24_rsp_in[3] = router_21_24_to_router_22_24_rsp; - assign router_22_24_rsp_in[4] = magia_tile_ni_22_24_to_router_22_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_24_req_in), - .floo_rsp_o (router_22_24_rsp_out), - .floo_req_o (router_22_24_req_out), - .floo_rsp_i (router_22_24_rsp_in) -); - - -floo_req_t [4:0] router_22_25_req_in; -floo_rsp_t [4:0] router_22_25_rsp_out; -floo_req_t [4:0] router_22_25_req_out; -floo_rsp_t [4:0] router_22_25_rsp_in; - - assign router_22_25_req_in[0] = router_22_26_to_router_22_25_req; - assign router_22_25_req_in[1] = router_23_25_to_router_22_25_req; - assign router_22_25_req_in[2] = router_22_24_to_router_22_25_req; - assign router_22_25_req_in[3] = router_21_25_to_router_22_25_req; - assign router_22_25_req_in[4] = magia_tile_ni_22_25_to_router_22_25_req; - - assign router_22_25_to_router_22_26_rsp = router_22_25_rsp_out[0]; - assign router_22_25_to_router_23_25_rsp = router_22_25_rsp_out[1]; - assign router_22_25_to_router_22_24_rsp = router_22_25_rsp_out[2]; - assign router_22_25_to_router_21_25_rsp = router_22_25_rsp_out[3]; - assign router_22_25_to_magia_tile_ni_22_25_rsp = router_22_25_rsp_out[4]; - - assign router_22_25_to_router_22_26_req = router_22_25_req_out[0]; - assign router_22_25_to_router_23_25_req = router_22_25_req_out[1]; - assign router_22_25_to_router_22_24_req = router_22_25_req_out[2]; - assign router_22_25_to_router_21_25_req = router_22_25_req_out[3]; - assign router_22_25_to_magia_tile_ni_22_25_req = router_22_25_req_out[4]; - - assign router_22_25_rsp_in[0] = router_22_26_to_router_22_25_rsp; - assign router_22_25_rsp_in[1] = router_23_25_to_router_22_25_rsp; - assign router_22_25_rsp_in[2] = router_22_24_to_router_22_25_rsp; - assign router_22_25_rsp_in[3] = router_21_25_to_router_22_25_rsp; - assign router_22_25_rsp_in[4] = magia_tile_ni_22_25_to_router_22_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_25_req_in), - .floo_rsp_o (router_22_25_rsp_out), - .floo_req_o (router_22_25_req_out), - .floo_rsp_i (router_22_25_rsp_in) -); - - -floo_req_t [4:0] router_22_26_req_in; -floo_rsp_t [4:0] router_22_26_rsp_out; -floo_req_t [4:0] router_22_26_req_out; -floo_rsp_t [4:0] router_22_26_rsp_in; - - assign router_22_26_req_in[0] = router_22_27_to_router_22_26_req; - assign router_22_26_req_in[1] = router_23_26_to_router_22_26_req; - assign router_22_26_req_in[2] = router_22_25_to_router_22_26_req; - assign router_22_26_req_in[3] = router_21_26_to_router_22_26_req; - assign router_22_26_req_in[4] = magia_tile_ni_22_26_to_router_22_26_req; - - assign router_22_26_to_router_22_27_rsp = router_22_26_rsp_out[0]; - assign router_22_26_to_router_23_26_rsp = router_22_26_rsp_out[1]; - assign router_22_26_to_router_22_25_rsp = router_22_26_rsp_out[2]; - assign router_22_26_to_router_21_26_rsp = router_22_26_rsp_out[3]; - assign router_22_26_to_magia_tile_ni_22_26_rsp = router_22_26_rsp_out[4]; - - assign router_22_26_to_router_22_27_req = router_22_26_req_out[0]; - assign router_22_26_to_router_23_26_req = router_22_26_req_out[1]; - assign router_22_26_to_router_22_25_req = router_22_26_req_out[2]; - assign router_22_26_to_router_21_26_req = router_22_26_req_out[3]; - assign router_22_26_to_magia_tile_ni_22_26_req = router_22_26_req_out[4]; - - assign router_22_26_rsp_in[0] = router_22_27_to_router_22_26_rsp; - assign router_22_26_rsp_in[1] = router_23_26_to_router_22_26_rsp; - assign router_22_26_rsp_in[2] = router_22_25_to_router_22_26_rsp; - assign router_22_26_rsp_in[3] = router_21_26_to_router_22_26_rsp; - assign router_22_26_rsp_in[4] = magia_tile_ni_22_26_to_router_22_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_26_req_in), - .floo_rsp_o (router_22_26_rsp_out), - .floo_req_o (router_22_26_req_out), - .floo_rsp_i (router_22_26_rsp_in) -); - - -floo_req_t [4:0] router_22_27_req_in; -floo_rsp_t [4:0] router_22_27_rsp_out; -floo_req_t [4:0] router_22_27_req_out; -floo_rsp_t [4:0] router_22_27_rsp_in; - - assign router_22_27_req_in[0] = router_22_28_to_router_22_27_req; - assign router_22_27_req_in[1] = router_23_27_to_router_22_27_req; - assign router_22_27_req_in[2] = router_22_26_to_router_22_27_req; - assign router_22_27_req_in[3] = router_21_27_to_router_22_27_req; - assign router_22_27_req_in[4] = magia_tile_ni_22_27_to_router_22_27_req; - - assign router_22_27_to_router_22_28_rsp = router_22_27_rsp_out[0]; - assign router_22_27_to_router_23_27_rsp = router_22_27_rsp_out[1]; - assign router_22_27_to_router_22_26_rsp = router_22_27_rsp_out[2]; - assign router_22_27_to_router_21_27_rsp = router_22_27_rsp_out[3]; - assign router_22_27_to_magia_tile_ni_22_27_rsp = router_22_27_rsp_out[4]; - - assign router_22_27_to_router_22_28_req = router_22_27_req_out[0]; - assign router_22_27_to_router_23_27_req = router_22_27_req_out[1]; - assign router_22_27_to_router_22_26_req = router_22_27_req_out[2]; - assign router_22_27_to_router_21_27_req = router_22_27_req_out[3]; - assign router_22_27_to_magia_tile_ni_22_27_req = router_22_27_req_out[4]; - - assign router_22_27_rsp_in[0] = router_22_28_to_router_22_27_rsp; - assign router_22_27_rsp_in[1] = router_23_27_to_router_22_27_rsp; - assign router_22_27_rsp_in[2] = router_22_26_to_router_22_27_rsp; - assign router_22_27_rsp_in[3] = router_21_27_to_router_22_27_rsp; - assign router_22_27_rsp_in[4] = magia_tile_ni_22_27_to_router_22_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_27_req_in), - .floo_rsp_o (router_22_27_rsp_out), - .floo_req_o (router_22_27_req_out), - .floo_rsp_i (router_22_27_rsp_in) -); - - -floo_req_t [4:0] router_22_28_req_in; -floo_rsp_t [4:0] router_22_28_rsp_out; -floo_req_t [4:0] router_22_28_req_out; -floo_rsp_t [4:0] router_22_28_rsp_in; - - assign router_22_28_req_in[0] = router_22_29_to_router_22_28_req; - assign router_22_28_req_in[1] = router_23_28_to_router_22_28_req; - assign router_22_28_req_in[2] = router_22_27_to_router_22_28_req; - assign router_22_28_req_in[3] = router_21_28_to_router_22_28_req; - assign router_22_28_req_in[4] = magia_tile_ni_22_28_to_router_22_28_req; - - assign router_22_28_to_router_22_29_rsp = router_22_28_rsp_out[0]; - assign router_22_28_to_router_23_28_rsp = router_22_28_rsp_out[1]; - assign router_22_28_to_router_22_27_rsp = router_22_28_rsp_out[2]; - assign router_22_28_to_router_21_28_rsp = router_22_28_rsp_out[3]; - assign router_22_28_to_magia_tile_ni_22_28_rsp = router_22_28_rsp_out[4]; - - assign router_22_28_to_router_22_29_req = router_22_28_req_out[0]; - assign router_22_28_to_router_23_28_req = router_22_28_req_out[1]; - assign router_22_28_to_router_22_27_req = router_22_28_req_out[2]; - assign router_22_28_to_router_21_28_req = router_22_28_req_out[3]; - assign router_22_28_to_magia_tile_ni_22_28_req = router_22_28_req_out[4]; - - assign router_22_28_rsp_in[0] = router_22_29_to_router_22_28_rsp; - assign router_22_28_rsp_in[1] = router_23_28_to_router_22_28_rsp; - assign router_22_28_rsp_in[2] = router_22_27_to_router_22_28_rsp; - assign router_22_28_rsp_in[3] = router_21_28_to_router_22_28_rsp; - assign router_22_28_rsp_in[4] = magia_tile_ni_22_28_to_router_22_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_28_req_in), - .floo_rsp_o (router_22_28_rsp_out), - .floo_req_o (router_22_28_req_out), - .floo_rsp_i (router_22_28_rsp_in) -); - - -floo_req_t [4:0] router_22_29_req_in; -floo_rsp_t [4:0] router_22_29_rsp_out; -floo_req_t [4:0] router_22_29_req_out; -floo_rsp_t [4:0] router_22_29_rsp_in; - - assign router_22_29_req_in[0] = router_22_30_to_router_22_29_req; - assign router_22_29_req_in[1] = router_23_29_to_router_22_29_req; - assign router_22_29_req_in[2] = router_22_28_to_router_22_29_req; - assign router_22_29_req_in[3] = router_21_29_to_router_22_29_req; - assign router_22_29_req_in[4] = magia_tile_ni_22_29_to_router_22_29_req; - - assign router_22_29_to_router_22_30_rsp = router_22_29_rsp_out[0]; - assign router_22_29_to_router_23_29_rsp = router_22_29_rsp_out[1]; - assign router_22_29_to_router_22_28_rsp = router_22_29_rsp_out[2]; - assign router_22_29_to_router_21_29_rsp = router_22_29_rsp_out[3]; - assign router_22_29_to_magia_tile_ni_22_29_rsp = router_22_29_rsp_out[4]; - - assign router_22_29_to_router_22_30_req = router_22_29_req_out[0]; - assign router_22_29_to_router_23_29_req = router_22_29_req_out[1]; - assign router_22_29_to_router_22_28_req = router_22_29_req_out[2]; - assign router_22_29_to_router_21_29_req = router_22_29_req_out[3]; - assign router_22_29_to_magia_tile_ni_22_29_req = router_22_29_req_out[4]; - - assign router_22_29_rsp_in[0] = router_22_30_to_router_22_29_rsp; - assign router_22_29_rsp_in[1] = router_23_29_to_router_22_29_rsp; - assign router_22_29_rsp_in[2] = router_22_28_to_router_22_29_rsp; - assign router_22_29_rsp_in[3] = router_21_29_to_router_22_29_rsp; - assign router_22_29_rsp_in[4] = magia_tile_ni_22_29_to_router_22_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_29_req_in), - .floo_rsp_o (router_22_29_rsp_out), - .floo_req_o (router_22_29_req_out), - .floo_rsp_i (router_22_29_rsp_in) -); - - -floo_req_t [4:0] router_22_30_req_in; -floo_rsp_t [4:0] router_22_30_rsp_out; -floo_req_t [4:0] router_22_30_req_out; -floo_rsp_t [4:0] router_22_30_rsp_in; - - assign router_22_30_req_in[0] = router_22_31_to_router_22_30_req; - assign router_22_30_req_in[1] = router_23_30_to_router_22_30_req; - assign router_22_30_req_in[2] = router_22_29_to_router_22_30_req; - assign router_22_30_req_in[3] = router_21_30_to_router_22_30_req; - assign router_22_30_req_in[4] = magia_tile_ni_22_30_to_router_22_30_req; - - assign router_22_30_to_router_22_31_rsp = router_22_30_rsp_out[0]; - assign router_22_30_to_router_23_30_rsp = router_22_30_rsp_out[1]; - assign router_22_30_to_router_22_29_rsp = router_22_30_rsp_out[2]; - assign router_22_30_to_router_21_30_rsp = router_22_30_rsp_out[3]; - assign router_22_30_to_magia_tile_ni_22_30_rsp = router_22_30_rsp_out[4]; - - assign router_22_30_to_router_22_31_req = router_22_30_req_out[0]; - assign router_22_30_to_router_23_30_req = router_22_30_req_out[1]; - assign router_22_30_to_router_22_29_req = router_22_30_req_out[2]; - assign router_22_30_to_router_21_30_req = router_22_30_req_out[3]; - assign router_22_30_to_magia_tile_ni_22_30_req = router_22_30_req_out[4]; - - assign router_22_30_rsp_in[0] = router_22_31_to_router_22_30_rsp; - assign router_22_30_rsp_in[1] = router_23_30_to_router_22_30_rsp; - assign router_22_30_rsp_in[2] = router_22_29_to_router_22_30_rsp; - assign router_22_30_rsp_in[3] = router_21_30_to_router_22_30_rsp; - assign router_22_30_rsp_in[4] = magia_tile_ni_22_30_to_router_22_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_30_req_in), - .floo_rsp_o (router_22_30_rsp_out), - .floo_req_o (router_22_30_req_out), - .floo_rsp_i (router_22_30_rsp_in) -); - - -floo_req_t [4:0] router_22_31_req_in; -floo_rsp_t [4:0] router_22_31_rsp_out; -floo_req_t [4:0] router_22_31_req_out; -floo_rsp_t [4:0] router_22_31_rsp_in; - - assign router_22_31_req_in[0] = '0; - assign router_22_31_req_in[1] = router_23_31_to_router_22_31_req; - assign router_22_31_req_in[2] = router_22_30_to_router_22_31_req; - assign router_22_31_req_in[3] = router_21_31_to_router_22_31_req; - assign router_22_31_req_in[4] = magia_tile_ni_22_31_to_router_22_31_req; - - assign router_22_31_to_router_23_31_rsp = router_22_31_rsp_out[1]; - assign router_22_31_to_router_22_30_rsp = router_22_31_rsp_out[2]; - assign router_22_31_to_router_21_31_rsp = router_22_31_rsp_out[3]; - assign router_22_31_to_magia_tile_ni_22_31_rsp = router_22_31_rsp_out[4]; - - assign router_22_31_to_router_23_31_req = router_22_31_req_out[1]; - assign router_22_31_to_router_22_30_req = router_22_31_req_out[2]; - assign router_22_31_to_router_21_31_req = router_22_31_req_out[3]; - assign router_22_31_to_magia_tile_ni_22_31_req = router_22_31_req_out[4]; - - assign router_22_31_rsp_in[0] = '0; - assign router_22_31_rsp_in[1] = router_23_31_to_router_22_31_rsp; - assign router_22_31_rsp_in[2] = router_22_30_to_router_22_31_rsp; - assign router_22_31_rsp_in[3] = router_21_31_to_router_22_31_rsp; - assign router_22_31_rsp_in[4] = magia_tile_ni_22_31_to_router_22_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_22_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 23, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_22_31_req_in), - .floo_rsp_o (router_22_31_rsp_out), - .floo_req_o (router_22_31_req_out), - .floo_rsp_i (router_22_31_rsp_in) -); - - -floo_req_t [4:0] router_23_0_req_in; -floo_rsp_t [4:0] router_23_0_rsp_out; -floo_req_t [4:0] router_23_0_req_out; -floo_rsp_t [4:0] router_23_0_rsp_in; - - assign router_23_0_req_in[0] = router_23_1_to_router_23_0_req; - assign router_23_0_req_in[1] = router_24_0_to_router_23_0_req; - assign router_23_0_req_in[2] = '0; - assign router_23_0_req_in[3] = router_22_0_to_router_23_0_req; - assign router_23_0_req_in[4] = magia_tile_ni_23_0_to_router_23_0_req; - - assign router_23_0_to_router_23_1_rsp = router_23_0_rsp_out[0]; - assign router_23_0_to_router_24_0_rsp = router_23_0_rsp_out[1]; - assign router_23_0_to_router_22_0_rsp = router_23_0_rsp_out[3]; - assign router_23_0_to_magia_tile_ni_23_0_rsp = router_23_0_rsp_out[4]; - - assign router_23_0_to_router_23_1_req = router_23_0_req_out[0]; - assign router_23_0_to_router_24_0_req = router_23_0_req_out[1]; - assign router_23_0_to_router_22_0_req = router_23_0_req_out[3]; - assign router_23_0_to_magia_tile_ni_23_0_req = router_23_0_req_out[4]; - - assign router_23_0_rsp_in[0] = router_23_1_to_router_23_0_rsp; - assign router_23_0_rsp_in[1] = router_24_0_to_router_23_0_rsp; - assign router_23_0_rsp_in[2] = '0; - assign router_23_0_rsp_in[3] = router_22_0_to_router_23_0_rsp; - assign router_23_0_rsp_in[4] = magia_tile_ni_23_0_to_router_23_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_0_req_in), - .floo_rsp_o (router_23_0_rsp_out), - .floo_req_o (router_23_0_req_out), - .floo_rsp_i (router_23_0_rsp_in) -); - - -floo_req_t [4:0] router_23_1_req_in; -floo_rsp_t [4:0] router_23_1_rsp_out; -floo_req_t [4:0] router_23_1_req_out; -floo_rsp_t [4:0] router_23_1_rsp_in; - - assign router_23_1_req_in[0] = router_23_2_to_router_23_1_req; - assign router_23_1_req_in[1] = router_24_1_to_router_23_1_req; - assign router_23_1_req_in[2] = router_23_0_to_router_23_1_req; - assign router_23_1_req_in[3] = router_22_1_to_router_23_1_req; - assign router_23_1_req_in[4] = magia_tile_ni_23_1_to_router_23_1_req; - - assign router_23_1_to_router_23_2_rsp = router_23_1_rsp_out[0]; - assign router_23_1_to_router_24_1_rsp = router_23_1_rsp_out[1]; - assign router_23_1_to_router_23_0_rsp = router_23_1_rsp_out[2]; - assign router_23_1_to_router_22_1_rsp = router_23_1_rsp_out[3]; - assign router_23_1_to_magia_tile_ni_23_1_rsp = router_23_1_rsp_out[4]; - - assign router_23_1_to_router_23_2_req = router_23_1_req_out[0]; - assign router_23_1_to_router_24_1_req = router_23_1_req_out[1]; - assign router_23_1_to_router_23_0_req = router_23_1_req_out[2]; - assign router_23_1_to_router_22_1_req = router_23_1_req_out[3]; - assign router_23_1_to_magia_tile_ni_23_1_req = router_23_1_req_out[4]; - - assign router_23_1_rsp_in[0] = router_23_2_to_router_23_1_rsp; - assign router_23_1_rsp_in[1] = router_24_1_to_router_23_1_rsp; - assign router_23_1_rsp_in[2] = router_23_0_to_router_23_1_rsp; - assign router_23_1_rsp_in[3] = router_22_1_to_router_23_1_rsp; - assign router_23_1_rsp_in[4] = magia_tile_ni_23_1_to_router_23_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_1_req_in), - .floo_rsp_o (router_23_1_rsp_out), - .floo_req_o (router_23_1_req_out), - .floo_rsp_i (router_23_1_rsp_in) -); - - -floo_req_t [4:0] router_23_2_req_in; -floo_rsp_t [4:0] router_23_2_rsp_out; -floo_req_t [4:0] router_23_2_req_out; -floo_rsp_t [4:0] router_23_2_rsp_in; - - assign router_23_2_req_in[0] = router_23_3_to_router_23_2_req; - assign router_23_2_req_in[1] = router_24_2_to_router_23_2_req; - assign router_23_2_req_in[2] = router_23_1_to_router_23_2_req; - assign router_23_2_req_in[3] = router_22_2_to_router_23_2_req; - assign router_23_2_req_in[4] = magia_tile_ni_23_2_to_router_23_2_req; - - assign router_23_2_to_router_23_3_rsp = router_23_2_rsp_out[0]; - assign router_23_2_to_router_24_2_rsp = router_23_2_rsp_out[1]; - assign router_23_2_to_router_23_1_rsp = router_23_2_rsp_out[2]; - assign router_23_2_to_router_22_2_rsp = router_23_2_rsp_out[3]; - assign router_23_2_to_magia_tile_ni_23_2_rsp = router_23_2_rsp_out[4]; - - assign router_23_2_to_router_23_3_req = router_23_2_req_out[0]; - assign router_23_2_to_router_24_2_req = router_23_2_req_out[1]; - assign router_23_2_to_router_23_1_req = router_23_2_req_out[2]; - assign router_23_2_to_router_22_2_req = router_23_2_req_out[3]; - assign router_23_2_to_magia_tile_ni_23_2_req = router_23_2_req_out[4]; - - assign router_23_2_rsp_in[0] = router_23_3_to_router_23_2_rsp; - assign router_23_2_rsp_in[1] = router_24_2_to_router_23_2_rsp; - assign router_23_2_rsp_in[2] = router_23_1_to_router_23_2_rsp; - assign router_23_2_rsp_in[3] = router_22_2_to_router_23_2_rsp; - assign router_23_2_rsp_in[4] = magia_tile_ni_23_2_to_router_23_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_2_req_in), - .floo_rsp_o (router_23_2_rsp_out), - .floo_req_o (router_23_2_req_out), - .floo_rsp_i (router_23_2_rsp_in) -); - - -floo_req_t [4:0] router_23_3_req_in; -floo_rsp_t [4:0] router_23_3_rsp_out; -floo_req_t [4:0] router_23_3_req_out; -floo_rsp_t [4:0] router_23_3_rsp_in; - - assign router_23_3_req_in[0] = router_23_4_to_router_23_3_req; - assign router_23_3_req_in[1] = router_24_3_to_router_23_3_req; - assign router_23_3_req_in[2] = router_23_2_to_router_23_3_req; - assign router_23_3_req_in[3] = router_22_3_to_router_23_3_req; - assign router_23_3_req_in[4] = magia_tile_ni_23_3_to_router_23_3_req; - - assign router_23_3_to_router_23_4_rsp = router_23_3_rsp_out[0]; - assign router_23_3_to_router_24_3_rsp = router_23_3_rsp_out[1]; - assign router_23_3_to_router_23_2_rsp = router_23_3_rsp_out[2]; - assign router_23_3_to_router_22_3_rsp = router_23_3_rsp_out[3]; - assign router_23_3_to_magia_tile_ni_23_3_rsp = router_23_3_rsp_out[4]; - - assign router_23_3_to_router_23_4_req = router_23_3_req_out[0]; - assign router_23_3_to_router_24_3_req = router_23_3_req_out[1]; - assign router_23_3_to_router_23_2_req = router_23_3_req_out[2]; - assign router_23_3_to_router_22_3_req = router_23_3_req_out[3]; - assign router_23_3_to_magia_tile_ni_23_3_req = router_23_3_req_out[4]; - - assign router_23_3_rsp_in[0] = router_23_4_to_router_23_3_rsp; - assign router_23_3_rsp_in[1] = router_24_3_to_router_23_3_rsp; - assign router_23_3_rsp_in[2] = router_23_2_to_router_23_3_rsp; - assign router_23_3_rsp_in[3] = router_22_3_to_router_23_3_rsp; - assign router_23_3_rsp_in[4] = magia_tile_ni_23_3_to_router_23_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_3_req_in), - .floo_rsp_o (router_23_3_rsp_out), - .floo_req_o (router_23_3_req_out), - .floo_rsp_i (router_23_3_rsp_in) -); - - -floo_req_t [4:0] router_23_4_req_in; -floo_rsp_t [4:0] router_23_4_rsp_out; -floo_req_t [4:0] router_23_4_req_out; -floo_rsp_t [4:0] router_23_4_rsp_in; - - assign router_23_4_req_in[0] = router_23_5_to_router_23_4_req; - assign router_23_4_req_in[1] = router_24_4_to_router_23_4_req; - assign router_23_4_req_in[2] = router_23_3_to_router_23_4_req; - assign router_23_4_req_in[3] = router_22_4_to_router_23_4_req; - assign router_23_4_req_in[4] = magia_tile_ni_23_4_to_router_23_4_req; - - assign router_23_4_to_router_23_5_rsp = router_23_4_rsp_out[0]; - assign router_23_4_to_router_24_4_rsp = router_23_4_rsp_out[1]; - assign router_23_4_to_router_23_3_rsp = router_23_4_rsp_out[2]; - assign router_23_4_to_router_22_4_rsp = router_23_4_rsp_out[3]; - assign router_23_4_to_magia_tile_ni_23_4_rsp = router_23_4_rsp_out[4]; - - assign router_23_4_to_router_23_5_req = router_23_4_req_out[0]; - assign router_23_4_to_router_24_4_req = router_23_4_req_out[1]; - assign router_23_4_to_router_23_3_req = router_23_4_req_out[2]; - assign router_23_4_to_router_22_4_req = router_23_4_req_out[3]; - assign router_23_4_to_magia_tile_ni_23_4_req = router_23_4_req_out[4]; - - assign router_23_4_rsp_in[0] = router_23_5_to_router_23_4_rsp; - assign router_23_4_rsp_in[1] = router_24_4_to_router_23_4_rsp; - assign router_23_4_rsp_in[2] = router_23_3_to_router_23_4_rsp; - assign router_23_4_rsp_in[3] = router_22_4_to_router_23_4_rsp; - assign router_23_4_rsp_in[4] = magia_tile_ni_23_4_to_router_23_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_4_req_in), - .floo_rsp_o (router_23_4_rsp_out), - .floo_req_o (router_23_4_req_out), - .floo_rsp_i (router_23_4_rsp_in) -); - - -floo_req_t [4:0] router_23_5_req_in; -floo_rsp_t [4:0] router_23_5_rsp_out; -floo_req_t [4:0] router_23_5_req_out; -floo_rsp_t [4:0] router_23_5_rsp_in; - - assign router_23_5_req_in[0] = router_23_6_to_router_23_5_req; - assign router_23_5_req_in[1] = router_24_5_to_router_23_5_req; - assign router_23_5_req_in[2] = router_23_4_to_router_23_5_req; - assign router_23_5_req_in[3] = router_22_5_to_router_23_5_req; - assign router_23_5_req_in[4] = magia_tile_ni_23_5_to_router_23_5_req; - - assign router_23_5_to_router_23_6_rsp = router_23_5_rsp_out[0]; - assign router_23_5_to_router_24_5_rsp = router_23_5_rsp_out[1]; - assign router_23_5_to_router_23_4_rsp = router_23_5_rsp_out[2]; - assign router_23_5_to_router_22_5_rsp = router_23_5_rsp_out[3]; - assign router_23_5_to_magia_tile_ni_23_5_rsp = router_23_5_rsp_out[4]; - - assign router_23_5_to_router_23_6_req = router_23_5_req_out[0]; - assign router_23_5_to_router_24_5_req = router_23_5_req_out[1]; - assign router_23_5_to_router_23_4_req = router_23_5_req_out[2]; - assign router_23_5_to_router_22_5_req = router_23_5_req_out[3]; - assign router_23_5_to_magia_tile_ni_23_5_req = router_23_5_req_out[4]; - - assign router_23_5_rsp_in[0] = router_23_6_to_router_23_5_rsp; - assign router_23_5_rsp_in[1] = router_24_5_to_router_23_5_rsp; - assign router_23_5_rsp_in[2] = router_23_4_to_router_23_5_rsp; - assign router_23_5_rsp_in[3] = router_22_5_to_router_23_5_rsp; - assign router_23_5_rsp_in[4] = magia_tile_ni_23_5_to_router_23_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_5_req_in), - .floo_rsp_o (router_23_5_rsp_out), - .floo_req_o (router_23_5_req_out), - .floo_rsp_i (router_23_5_rsp_in) -); - - -floo_req_t [4:0] router_23_6_req_in; -floo_rsp_t [4:0] router_23_6_rsp_out; -floo_req_t [4:0] router_23_6_req_out; -floo_rsp_t [4:0] router_23_6_rsp_in; - - assign router_23_6_req_in[0] = router_23_7_to_router_23_6_req; - assign router_23_6_req_in[1] = router_24_6_to_router_23_6_req; - assign router_23_6_req_in[2] = router_23_5_to_router_23_6_req; - assign router_23_6_req_in[3] = router_22_6_to_router_23_6_req; - assign router_23_6_req_in[4] = magia_tile_ni_23_6_to_router_23_6_req; - - assign router_23_6_to_router_23_7_rsp = router_23_6_rsp_out[0]; - assign router_23_6_to_router_24_6_rsp = router_23_6_rsp_out[1]; - assign router_23_6_to_router_23_5_rsp = router_23_6_rsp_out[2]; - assign router_23_6_to_router_22_6_rsp = router_23_6_rsp_out[3]; - assign router_23_6_to_magia_tile_ni_23_6_rsp = router_23_6_rsp_out[4]; - - assign router_23_6_to_router_23_7_req = router_23_6_req_out[0]; - assign router_23_6_to_router_24_6_req = router_23_6_req_out[1]; - assign router_23_6_to_router_23_5_req = router_23_6_req_out[2]; - assign router_23_6_to_router_22_6_req = router_23_6_req_out[3]; - assign router_23_6_to_magia_tile_ni_23_6_req = router_23_6_req_out[4]; - - assign router_23_6_rsp_in[0] = router_23_7_to_router_23_6_rsp; - assign router_23_6_rsp_in[1] = router_24_6_to_router_23_6_rsp; - assign router_23_6_rsp_in[2] = router_23_5_to_router_23_6_rsp; - assign router_23_6_rsp_in[3] = router_22_6_to_router_23_6_rsp; - assign router_23_6_rsp_in[4] = magia_tile_ni_23_6_to_router_23_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_6_req_in), - .floo_rsp_o (router_23_6_rsp_out), - .floo_req_o (router_23_6_req_out), - .floo_rsp_i (router_23_6_rsp_in) -); - - -floo_req_t [4:0] router_23_7_req_in; -floo_rsp_t [4:0] router_23_7_rsp_out; -floo_req_t [4:0] router_23_7_req_out; -floo_rsp_t [4:0] router_23_7_rsp_in; - - assign router_23_7_req_in[0] = router_23_8_to_router_23_7_req; - assign router_23_7_req_in[1] = router_24_7_to_router_23_7_req; - assign router_23_7_req_in[2] = router_23_6_to_router_23_7_req; - assign router_23_7_req_in[3] = router_22_7_to_router_23_7_req; - assign router_23_7_req_in[4] = magia_tile_ni_23_7_to_router_23_7_req; - - assign router_23_7_to_router_23_8_rsp = router_23_7_rsp_out[0]; - assign router_23_7_to_router_24_7_rsp = router_23_7_rsp_out[1]; - assign router_23_7_to_router_23_6_rsp = router_23_7_rsp_out[2]; - assign router_23_7_to_router_22_7_rsp = router_23_7_rsp_out[3]; - assign router_23_7_to_magia_tile_ni_23_7_rsp = router_23_7_rsp_out[4]; - - assign router_23_7_to_router_23_8_req = router_23_7_req_out[0]; - assign router_23_7_to_router_24_7_req = router_23_7_req_out[1]; - assign router_23_7_to_router_23_6_req = router_23_7_req_out[2]; - assign router_23_7_to_router_22_7_req = router_23_7_req_out[3]; - assign router_23_7_to_magia_tile_ni_23_7_req = router_23_7_req_out[4]; - - assign router_23_7_rsp_in[0] = router_23_8_to_router_23_7_rsp; - assign router_23_7_rsp_in[1] = router_24_7_to_router_23_7_rsp; - assign router_23_7_rsp_in[2] = router_23_6_to_router_23_7_rsp; - assign router_23_7_rsp_in[3] = router_22_7_to_router_23_7_rsp; - assign router_23_7_rsp_in[4] = magia_tile_ni_23_7_to_router_23_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_7_req_in), - .floo_rsp_o (router_23_7_rsp_out), - .floo_req_o (router_23_7_req_out), - .floo_rsp_i (router_23_7_rsp_in) -); - - -floo_req_t [4:0] router_23_8_req_in; -floo_rsp_t [4:0] router_23_8_rsp_out; -floo_req_t [4:0] router_23_8_req_out; -floo_rsp_t [4:0] router_23_8_rsp_in; - - assign router_23_8_req_in[0] = router_23_9_to_router_23_8_req; - assign router_23_8_req_in[1] = router_24_8_to_router_23_8_req; - assign router_23_8_req_in[2] = router_23_7_to_router_23_8_req; - assign router_23_8_req_in[3] = router_22_8_to_router_23_8_req; - assign router_23_8_req_in[4] = magia_tile_ni_23_8_to_router_23_8_req; - - assign router_23_8_to_router_23_9_rsp = router_23_8_rsp_out[0]; - assign router_23_8_to_router_24_8_rsp = router_23_8_rsp_out[1]; - assign router_23_8_to_router_23_7_rsp = router_23_8_rsp_out[2]; - assign router_23_8_to_router_22_8_rsp = router_23_8_rsp_out[3]; - assign router_23_8_to_magia_tile_ni_23_8_rsp = router_23_8_rsp_out[4]; - - assign router_23_8_to_router_23_9_req = router_23_8_req_out[0]; - assign router_23_8_to_router_24_8_req = router_23_8_req_out[1]; - assign router_23_8_to_router_23_7_req = router_23_8_req_out[2]; - assign router_23_8_to_router_22_8_req = router_23_8_req_out[3]; - assign router_23_8_to_magia_tile_ni_23_8_req = router_23_8_req_out[4]; - - assign router_23_8_rsp_in[0] = router_23_9_to_router_23_8_rsp; - assign router_23_8_rsp_in[1] = router_24_8_to_router_23_8_rsp; - assign router_23_8_rsp_in[2] = router_23_7_to_router_23_8_rsp; - assign router_23_8_rsp_in[3] = router_22_8_to_router_23_8_rsp; - assign router_23_8_rsp_in[4] = magia_tile_ni_23_8_to_router_23_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_8_req_in), - .floo_rsp_o (router_23_8_rsp_out), - .floo_req_o (router_23_8_req_out), - .floo_rsp_i (router_23_8_rsp_in) -); - - -floo_req_t [4:0] router_23_9_req_in; -floo_rsp_t [4:0] router_23_9_rsp_out; -floo_req_t [4:0] router_23_9_req_out; -floo_rsp_t [4:0] router_23_9_rsp_in; - - assign router_23_9_req_in[0] = router_23_10_to_router_23_9_req; - assign router_23_9_req_in[1] = router_24_9_to_router_23_9_req; - assign router_23_9_req_in[2] = router_23_8_to_router_23_9_req; - assign router_23_9_req_in[3] = router_22_9_to_router_23_9_req; - assign router_23_9_req_in[4] = magia_tile_ni_23_9_to_router_23_9_req; - - assign router_23_9_to_router_23_10_rsp = router_23_9_rsp_out[0]; - assign router_23_9_to_router_24_9_rsp = router_23_9_rsp_out[1]; - assign router_23_9_to_router_23_8_rsp = router_23_9_rsp_out[2]; - assign router_23_9_to_router_22_9_rsp = router_23_9_rsp_out[3]; - assign router_23_9_to_magia_tile_ni_23_9_rsp = router_23_9_rsp_out[4]; - - assign router_23_9_to_router_23_10_req = router_23_9_req_out[0]; - assign router_23_9_to_router_24_9_req = router_23_9_req_out[1]; - assign router_23_9_to_router_23_8_req = router_23_9_req_out[2]; - assign router_23_9_to_router_22_9_req = router_23_9_req_out[3]; - assign router_23_9_to_magia_tile_ni_23_9_req = router_23_9_req_out[4]; - - assign router_23_9_rsp_in[0] = router_23_10_to_router_23_9_rsp; - assign router_23_9_rsp_in[1] = router_24_9_to_router_23_9_rsp; - assign router_23_9_rsp_in[2] = router_23_8_to_router_23_9_rsp; - assign router_23_9_rsp_in[3] = router_22_9_to_router_23_9_rsp; - assign router_23_9_rsp_in[4] = magia_tile_ni_23_9_to_router_23_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_9_req_in), - .floo_rsp_o (router_23_9_rsp_out), - .floo_req_o (router_23_9_req_out), - .floo_rsp_i (router_23_9_rsp_in) -); - - -floo_req_t [4:0] router_23_10_req_in; -floo_rsp_t [4:0] router_23_10_rsp_out; -floo_req_t [4:0] router_23_10_req_out; -floo_rsp_t [4:0] router_23_10_rsp_in; - - assign router_23_10_req_in[0] = router_23_11_to_router_23_10_req; - assign router_23_10_req_in[1] = router_24_10_to_router_23_10_req; - assign router_23_10_req_in[2] = router_23_9_to_router_23_10_req; - assign router_23_10_req_in[3] = router_22_10_to_router_23_10_req; - assign router_23_10_req_in[4] = magia_tile_ni_23_10_to_router_23_10_req; - - assign router_23_10_to_router_23_11_rsp = router_23_10_rsp_out[0]; - assign router_23_10_to_router_24_10_rsp = router_23_10_rsp_out[1]; - assign router_23_10_to_router_23_9_rsp = router_23_10_rsp_out[2]; - assign router_23_10_to_router_22_10_rsp = router_23_10_rsp_out[3]; - assign router_23_10_to_magia_tile_ni_23_10_rsp = router_23_10_rsp_out[4]; - - assign router_23_10_to_router_23_11_req = router_23_10_req_out[0]; - assign router_23_10_to_router_24_10_req = router_23_10_req_out[1]; - assign router_23_10_to_router_23_9_req = router_23_10_req_out[2]; - assign router_23_10_to_router_22_10_req = router_23_10_req_out[3]; - assign router_23_10_to_magia_tile_ni_23_10_req = router_23_10_req_out[4]; - - assign router_23_10_rsp_in[0] = router_23_11_to_router_23_10_rsp; - assign router_23_10_rsp_in[1] = router_24_10_to_router_23_10_rsp; - assign router_23_10_rsp_in[2] = router_23_9_to_router_23_10_rsp; - assign router_23_10_rsp_in[3] = router_22_10_to_router_23_10_rsp; - assign router_23_10_rsp_in[4] = magia_tile_ni_23_10_to_router_23_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_10_req_in), - .floo_rsp_o (router_23_10_rsp_out), - .floo_req_o (router_23_10_req_out), - .floo_rsp_i (router_23_10_rsp_in) -); - - -floo_req_t [4:0] router_23_11_req_in; -floo_rsp_t [4:0] router_23_11_rsp_out; -floo_req_t [4:0] router_23_11_req_out; -floo_rsp_t [4:0] router_23_11_rsp_in; - - assign router_23_11_req_in[0] = router_23_12_to_router_23_11_req; - assign router_23_11_req_in[1] = router_24_11_to_router_23_11_req; - assign router_23_11_req_in[2] = router_23_10_to_router_23_11_req; - assign router_23_11_req_in[3] = router_22_11_to_router_23_11_req; - assign router_23_11_req_in[4] = magia_tile_ni_23_11_to_router_23_11_req; - - assign router_23_11_to_router_23_12_rsp = router_23_11_rsp_out[0]; - assign router_23_11_to_router_24_11_rsp = router_23_11_rsp_out[1]; - assign router_23_11_to_router_23_10_rsp = router_23_11_rsp_out[2]; - assign router_23_11_to_router_22_11_rsp = router_23_11_rsp_out[3]; - assign router_23_11_to_magia_tile_ni_23_11_rsp = router_23_11_rsp_out[4]; - - assign router_23_11_to_router_23_12_req = router_23_11_req_out[0]; - assign router_23_11_to_router_24_11_req = router_23_11_req_out[1]; - assign router_23_11_to_router_23_10_req = router_23_11_req_out[2]; - assign router_23_11_to_router_22_11_req = router_23_11_req_out[3]; - assign router_23_11_to_magia_tile_ni_23_11_req = router_23_11_req_out[4]; - - assign router_23_11_rsp_in[0] = router_23_12_to_router_23_11_rsp; - assign router_23_11_rsp_in[1] = router_24_11_to_router_23_11_rsp; - assign router_23_11_rsp_in[2] = router_23_10_to_router_23_11_rsp; - assign router_23_11_rsp_in[3] = router_22_11_to_router_23_11_rsp; - assign router_23_11_rsp_in[4] = magia_tile_ni_23_11_to_router_23_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_11_req_in), - .floo_rsp_o (router_23_11_rsp_out), - .floo_req_o (router_23_11_req_out), - .floo_rsp_i (router_23_11_rsp_in) -); - - -floo_req_t [4:0] router_23_12_req_in; -floo_rsp_t [4:0] router_23_12_rsp_out; -floo_req_t [4:0] router_23_12_req_out; -floo_rsp_t [4:0] router_23_12_rsp_in; - - assign router_23_12_req_in[0] = router_23_13_to_router_23_12_req; - assign router_23_12_req_in[1] = router_24_12_to_router_23_12_req; - assign router_23_12_req_in[2] = router_23_11_to_router_23_12_req; - assign router_23_12_req_in[3] = router_22_12_to_router_23_12_req; - assign router_23_12_req_in[4] = magia_tile_ni_23_12_to_router_23_12_req; - - assign router_23_12_to_router_23_13_rsp = router_23_12_rsp_out[0]; - assign router_23_12_to_router_24_12_rsp = router_23_12_rsp_out[1]; - assign router_23_12_to_router_23_11_rsp = router_23_12_rsp_out[2]; - assign router_23_12_to_router_22_12_rsp = router_23_12_rsp_out[3]; - assign router_23_12_to_magia_tile_ni_23_12_rsp = router_23_12_rsp_out[4]; - - assign router_23_12_to_router_23_13_req = router_23_12_req_out[0]; - assign router_23_12_to_router_24_12_req = router_23_12_req_out[1]; - assign router_23_12_to_router_23_11_req = router_23_12_req_out[2]; - assign router_23_12_to_router_22_12_req = router_23_12_req_out[3]; - assign router_23_12_to_magia_tile_ni_23_12_req = router_23_12_req_out[4]; - - assign router_23_12_rsp_in[0] = router_23_13_to_router_23_12_rsp; - assign router_23_12_rsp_in[1] = router_24_12_to_router_23_12_rsp; - assign router_23_12_rsp_in[2] = router_23_11_to_router_23_12_rsp; - assign router_23_12_rsp_in[3] = router_22_12_to_router_23_12_rsp; - assign router_23_12_rsp_in[4] = magia_tile_ni_23_12_to_router_23_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_12_req_in), - .floo_rsp_o (router_23_12_rsp_out), - .floo_req_o (router_23_12_req_out), - .floo_rsp_i (router_23_12_rsp_in) -); - - -floo_req_t [4:0] router_23_13_req_in; -floo_rsp_t [4:0] router_23_13_rsp_out; -floo_req_t [4:0] router_23_13_req_out; -floo_rsp_t [4:0] router_23_13_rsp_in; - - assign router_23_13_req_in[0] = router_23_14_to_router_23_13_req; - assign router_23_13_req_in[1] = router_24_13_to_router_23_13_req; - assign router_23_13_req_in[2] = router_23_12_to_router_23_13_req; - assign router_23_13_req_in[3] = router_22_13_to_router_23_13_req; - assign router_23_13_req_in[4] = magia_tile_ni_23_13_to_router_23_13_req; - - assign router_23_13_to_router_23_14_rsp = router_23_13_rsp_out[0]; - assign router_23_13_to_router_24_13_rsp = router_23_13_rsp_out[1]; - assign router_23_13_to_router_23_12_rsp = router_23_13_rsp_out[2]; - assign router_23_13_to_router_22_13_rsp = router_23_13_rsp_out[3]; - assign router_23_13_to_magia_tile_ni_23_13_rsp = router_23_13_rsp_out[4]; - - assign router_23_13_to_router_23_14_req = router_23_13_req_out[0]; - assign router_23_13_to_router_24_13_req = router_23_13_req_out[1]; - assign router_23_13_to_router_23_12_req = router_23_13_req_out[2]; - assign router_23_13_to_router_22_13_req = router_23_13_req_out[3]; - assign router_23_13_to_magia_tile_ni_23_13_req = router_23_13_req_out[4]; - - assign router_23_13_rsp_in[0] = router_23_14_to_router_23_13_rsp; - assign router_23_13_rsp_in[1] = router_24_13_to_router_23_13_rsp; - assign router_23_13_rsp_in[2] = router_23_12_to_router_23_13_rsp; - assign router_23_13_rsp_in[3] = router_22_13_to_router_23_13_rsp; - assign router_23_13_rsp_in[4] = magia_tile_ni_23_13_to_router_23_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_13_req_in), - .floo_rsp_o (router_23_13_rsp_out), - .floo_req_o (router_23_13_req_out), - .floo_rsp_i (router_23_13_rsp_in) -); - - -floo_req_t [4:0] router_23_14_req_in; -floo_rsp_t [4:0] router_23_14_rsp_out; -floo_req_t [4:0] router_23_14_req_out; -floo_rsp_t [4:0] router_23_14_rsp_in; - - assign router_23_14_req_in[0] = router_23_15_to_router_23_14_req; - assign router_23_14_req_in[1] = router_24_14_to_router_23_14_req; - assign router_23_14_req_in[2] = router_23_13_to_router_23_14_req; - assign router_23_14_req_in[3] = router_22_14_to_router_23_14_req; - assign router_23_14_req_in[4] = magia_tile_ni_23_14_to_router_23_14_req; - - assign router_23_14_to_router_23_15_rsp = router_23_14_rsp_out[0]; - assign router_23_14_to_router_24_14_rsp = router_23_14_rsp_out[1]; - assign router_23_14_to_router_23_13_rsp = router_23_14_rsp_out[2]; - assign router_23_14_to_router_22_14_rsp = router_23_14_rsp_out[3]; - assign router_23_14_to_magia_tile_ni_23_14_rsp = router_23_14_rsp_out[4]; - - assign router_23_14_to_router_23_15_req = router_23_14_req_out[0]; - assign router_23_14_to_router_24_14_req = router_23_14_req_out[1]; - assign router_23_14_to_router_23_13_req = router_23_14_req_out[2]; - assign router_23_14_to_router_22_14_req = router_23_14_req_out[3]; - assign router_23_14_to_magia_tile_ni_23_14_req = router_23_14_req_out[4]; - - assign router_23_14_rsp_in[0] = router_23_15_to_router_23_14_rsp; - assign router_23_14_rsp_in[1] = router_24_14_to_router_23_14_rsp; - assign router_23_14_rsp_in[2] = router_23_13_to_router_23_14_rsp; - assign router_23_14_rsp_in[3] = router_22_14_to_router_23_14_rsp; - assign router_23_14_rsp_in[4] = magia_tile_ni_23_14_to_router_23_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_14_req_in), - .floo_rsp_o (router_23_14_rsp_out), - .floo_req_o (router_23_14_req_out), - .floo_rsp_i (router_23_14_rsp_in) -); - - -floo_req_t [4:0] router_23_15_req_in; -floo_rsp_t [4:0] router_23_15_rsp_out; -floo_req_t [4:0] router_23_15_req_out; -floo_rsp_t [4:0] router_23_15_rsp_in; - - assign router_23_15_req_in[0] = router_23_16_to_router_23_15_req; - assign router_23_15_req_in[1] = router_24_15_to_router_23_15_req; - assign router_23_15_req_in[2] = router_23_14_to_router_23_15_req; - assign router_23_15_req_in[3] = router_22_15_to_router_23_15_req; - assign router_23_15_req_in[4] = magia_tile_ni_23_15_to_router_23_15_req; - - assign router_23_15_to_router_23_16_rsp = router_23_15_rsp_out[0]; - assign router_23_15_to_router_24_15_rsp = router_23_15_rsp_out[1]; - assign router_23_15_to_router_23_14_rsp = router_23_15_rsp_out[2]; - assign router_23_15_to_router_22_15_rsp = router_23_15_rsp_out[3]; - assign router_23_15_to_magia_tile_ni_23_15_rsp = router_23_15_rsp_out[4]; - - assign router_23_15_to_router_23_16_req = router_23_15_req_out[0]; - assign router_23_15_to_router_24_15_req = router_23_15_req_out[1]; - assign router_23_15_to_router_23_14_req = router_23_15_req_out[2]; - assign router_23_15_to_router_22_15_req = router_23_15_req_out[3]; - assign router_23_15_to_magia_tile_ni_23_15_req = router_23_15_req_out[4]; - - assign router_23_15_rsp_in[0] = router_23_16_to_router_23_15_rsp; - assign router_23_15_rsp_in[1] = router_24_15_to_router_23_15_rsp; - assign router_23_15_rsp_in[2] = router_23_14_to_router_23_15_rsp; - assign router_23_15_rsp_in[3] = router_22_15_to_router_23_15_rsp; - assign router_23_15_rsp_in[4] = magia_tile_ni_23_15_to_router_23_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_15_req_in), - .floo_rsp_o (router_23_15_rsp_out), - .floo_req_o (router_23_15_req_out), - .floo_rsp_i (router_23_15_rsp_in) -); - - -floo_req_t [4:0] router_23_16_req_in; -floo_rsp_t [4:0] router_23_16_rsp_out; -floo_req_t [4:0] router_23_16_req_out; -floo_rsp_t [4:0] router_23_16_rsp_in; - - assign router_23_16_req_in[0] = router_23_17_to_router_23_16_req; - assign router_23_16_req_in[1] = router_24_16_to_router_23_16_req; - assign router_23_16_req_in[2] = router_23_15_to_router_23_16_req; - assign router_23_16_req_in[3] = router_22_16_to_router_23_16_req; - assign router_23_16_req_in[4] = magia_tile_ni_23_16_to_router_23_16_req; - - assign router_23_16_to_router_23_17_rsp = router_23_16_rsp_out[0]; - assign router_23_16_to_router_24_16_rsp = router_23_16_rsp_out[1]; - assign router_23_16_to_router_23_15_rsp = router_23_16_rsp_out[2]; - assign router_23_16_to_router_22_16_rsp = router_23_16_rsp_out[3]; - assign router_23_16_to_magia_tile_ni_23_16_rsp = router_23_16_rsp_out[4]; - - assign router_23_16_to_router_23_17_req = router_23_16_req_out[0]; - assign router_23_16_to_router_24_16_req = router_23_16_req_out[1]; - assign router_23_16_to_router_23_15_req = router_23_16_req_out[2]; - assign router_23_16_to_router_22_16_req = router_23_16_req_out[3]; - assign router_23_16_to_magia_tile_ni_23_16_req = router_23_16_req_out[4]; - - assign router_23_16_rsp_in[0] = router_23_17_to_router_23_16_rsp; - assign router_23_16_rsp_in[1] = router_24_16_to_router_23_16_rsp; - assign router_23_16_rsp_in[2] = router_23_15_to_router_23_16_rsp; - assign router_23_16_rsp_in[3] = router_22_16_to_router_23_16_rsp; - assign router_23_16_rsp_in[4] = magia_tile_ni_23_16_to_router_23_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_16_req_in), - .floo_rsp_o (router_23_16_rsp_out), - .floo_req_o (router_23_16_req_out), - .floo_rsp_i (router_23_16_rsp_in) -); - - -floo_req_t [4:0] router_23_17_req_in; -floo_rsp_t [4:0] router_23_17_rsp_out; -floo_req_t [4:0] router_23_17_req_out; -floo_rsp_t [4:0] router_23_17_rsp_in; - - assign router_23_17_req_in[0] = router_23_18_to_router_23_17_req; - assign router_23_17_req_in[1] = router_24_17_to_router_23_17_req; - assign router_23_17_req_in[2] = router_23_16_to_router_23_17_req; - assign router_23_17_req_in[3] = router_22_17_to_router_23_17_req; - assign router_23_17_req_in[4] = magia_tile_ni_23_17_to_router_23_17_req; - - assign router_23_17_to_router_23_18_rsp = router_23_17_rsp_out[0]; - assign router_23_17_to_router_24_17_rsp = router_23_17_rsp_out[1]; - assign router_23_17_to_router_23_16_rsp = router_23_17_rsp_out[2]; - assign router_23_17_to_router_22_17_rsp = router_23_17_rsp_out[3]; - assign router_23_17_to_magia_tile_ni_23_17_rsp = router_23_17_rsp_out[4]; - - assign router_23_17_to_router_23_18_req = router_23_17_req_out[0]; - assign router_23_17_to_router_24_17_req = router_23_17_req_out[1]; - assign router_23_17_to_router_23_16_req = router_23_17_req_out[2]; - assign router_23_17_to_router_22_17_req = router_23_17_req_out[3]; - assign router_23_17_to_magia_tile_ni_23_17_req = router_23_17_req_out[4]; - - assign router_23_17_rsp_in[0] = router_23_18_to_router_23_17_rsp; - assign router_23_17_rsp_in[1] = router_24_17_to_router_23_17_rsp; - assign router_23_17_rsp_in[2] = router_23_16_to_router_23_17_rsp; - assign router_23_17_rsp_in[3] = router_22_17_to_router_23_17_rsp; - assign router_23_17_rsp_in[4] = magia_tile_ni_23_17_to_router_23_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_17_req_in), - .floo_rsp_o (router_23_17_rsp_out), - .floo_req_o (router_23_17_req_out), - .floo_rsp_i (router_23_17_rsp_in) -); - - -floo_req_t [4:0] router_23_18_req_in; -floo_rsp_t [4:0] router_23_18_rsp_out; -floo_req_t [4:0] router_23_18_req_out; -floo_rsp_t [4:0] router_23_18_rsp_in; - - assign router_23_18_req_in[0] = router_23_19_to_router_23_18_req; - assign router_23_18_req_in[1] = router_24_18_to_router_23_18_req; - assign router_23_18_req_in[2] = router_23_17_to_router_23_18_req; - assign router_23_18_req_in[3] = router_22_18_to_router_23_18_req; - assign router_23_18_req_in[4] = magia_tile_ni_23_18_to_router_23_18_req; - - assign router_23_18_to_router_23_19_rsp = router_23_18_rsp_out[0]; - assign router_23_18_to_router_24_18_rsp = router_23_18_rsp_out[1]; - assign router_23_18_to_router_23_17_rsp = router_23_18_rsp_out[2]; - assign router_23_18_to_router_22_18_rsp = router_23_18_rsp_out[3]; - assign router_23_18_to_magia_tile_ni_23_18_rsp = router_23_18_rsp_out[4]; - - assign router_23_18_to_router_23_19_req = router_23_18_req_out[0]; - assign router_23_18_to_router_24_18_req = router_23_18_req_out[1]; - assign router_23_18_to_router_23_17_req = router_23_18_req_out[2]; - assign router_23_18_to_router_22_18_req = router_23_18_req_out[3]; - assign router_23_18_to_magia_tile_ni_23_18_req = router_23_18_req_out[4]; - - assign router_23_18_rsp_in[0] = router_23_19_to_router_23_18_rsp; - assign router_23_18_rsp_in[1] = router_24_18_to_router_23_18_rsp; - assign router_23_18_rsp_in[2] = router_23_17_to_router_23_18_rsp; - assign router_23_18_rsp_in[3] = router_22_18_to_router_23_18_rsp; - assign router_23_18_rsp_in[4] = magia_tile_ni_23_18_to_router_23_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_18_req_in), - .floo_rsp_o (router_23_18_rsp_out), - .floo_req_o (router_23_18_req_out), - .floo_rsp_i (router_23_18_rsp_in) -); - - -floo_req_t [4:0] router_23_19_req_in; -floo_rsp_t [4:0] router_23_19_rsp_out; -floo_req_t [4:0] router_23_19_req_out; -floo_rsp_t [4:0] router_23_19_rsp_in; - - assign router_23_19_req_in[0] = router_23_20_to_router_23_19_req; - assign router_23_19_req_in[1] = router_24_19_to_router_23_19_req; - assign router_23_19_req_in[2] = router_23_18_to_router_23_19_req; - assign router_23_19_req_in[3] = router_22_19_to_router_23_19_req; - assign router_23_19_req_in[4] = magia_tile_ni_23_19_to_router_23_19_req; - - assign router_23_19_to_router_23_20_rsp = router_23_19_rsp_out[0]; - assign router_23_19_to_router_24_19_rsp = router_23_19_rsp_out[1]; - assign router_23_19_to_router_23_18_rsp = router_23_19_rsp_out[2]; - assign router_23_19_to_router_22_19_rsp = router_23_19_rsp_out[3]; - assign router_23_19_to_magia_tile_ni_23_19_rsp = router_23_19_rsp_out[4]; - - assign router_23_19_to_router_23_20_req = router_23_19_req_out[0]; - assign router_23_19_to_router_24_19_req = router_23_19_req_out[1]; - assign router_23_19_to_router_23_18_req = router_23_19_req_out[2]; - assign router_23_19_to_router_22_19_req = router_23_19_req_out[3]; - assign router_23_19_to_magia_tile_ni_23_19_req = router_23_19_req_out[4]; - - assign router_23_19_rsp_in[0] = router_23_20_to_router_23_19_rsp; - assign router_23_19_rsp_in[1] = router_24_19_to_router_23_19_rsp; - assign router_23_19_rsp_in[2] = router_23_18_to_router_23_19_rsp; - assign router_23_19_rsp_in[3] = router_22_19_to_router_23_19_rsp; - assign router_23_19_rsp_in[4] = magia_tile_ni_23_19_to_router_23_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_19_req_in), - .floo_rsp_o (router_23_19_rsp_out), - .floo_req_o (router_23_19_req_out), - .floo_rsp_i (router_23_19_rsp_in) -); - - -floo_req_t [4:0] router_23_20_req_in; -floo_rsp_t [4:0] router_23_20_rsp_out; -floo_req_t [4:0] router_23_20_req_out; -floo_rsp_t [4:0] router_23_20_rsp_in; - - assign router_23_20_req_in[0] = router_23_21_to_router_23_20_req; - assign router_23_20_req_in[1] = router_24_20_to_router_23_20_req; - assign router_23_20_req_in[2] = router_23_19_to_router_23_20_req; - assign router_23_20_req_in[3] = router_22_20_to_router_23_20_req; - assign router_23_20_req_in[4] = magia_tile_ni_23_20_to_router_23_20_req; - - assign router_23_20_to_router_23_21_rsp = router_23_20_rsp_out[0]; - assign router_23_20_to_router_24_20_rsp = router_23_20_rsp_out[1]; - assign router_23_20_to_router_23_19_rsp = router_23_20_rsp_out[2]; - assign router_23_20_to_router_22_20_rsp = router_23_20_rsp_out[3]; - assign router_23_20_to_magia_tile_ni_23_20_rsp = router_23_20_rsp_out[4]; - - assign router_23_20_to_router_23_21_req = router_23_20_req_out[0]; - assign router_23_20_to_router_24_20_req = router_23_20_req_out[1]; - assign router_23_20_to_router_23_19_req = router_23_20_req_out[2]; - assign router_23_20_to_router_22_20_req = router_23_20_req_out[3]; - assign router_23_20_to_magia_tile_ni_23_20_req = router_23_20_req_out[4]; - - assign router_23_20_rsp_in[0] = router_23_21_to_router_23_20_rsp; - assign router_23_20_rsp_in[1] = router_24_20_to_router_23_20_rsp; - assign router_23_20_rsp_in[2] = router_23_19_to_router_23_20_rsp; - assign router_23_20_rsp_in[3] = router_22_20_to_router_23_20_rsp; - assign router_23_20_rsp_in[4] = magia_tile_ni_23_20_to_router_23_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_20_req_in), - .floo_rsp_o (router_23_20_rsp_out), - .floo_req_o (router_23_20_req_out), - .floo_rsp_i (router_23_20_rsp_in) -); - - -floo_req_t [4:0] router_23_21_req_in; -floo_rsp_t [4:0] router_23_21_rsp_out; -floo_req_t [4:0] router_23_21_req_out; -floo_rsp_t [4:0] router_23_21_rsp_in; - - assign router_23_21_req_in[0] = router_23_22_to_router_23_21_req; - assign router_23_21_req_in[1] = router_24_21_to_router_23_21_req; - assign router_23_21_req_in[2] = router_23_20_to_router_23_21_req; - assign router_23_21_req_in[3] = router_22_21_to_router_23_21_req; - assign router_23_21_req_in[4] = magia_tile_ni_23_21_to_router_23_21_req; - - assign router_23_21_to_router_23_22_rsp = router_23_21_rsp_out[0]; - assign router_23_21_to_router_24_21_rsp = router_23_21_rsp_out[1]; - assign router_23_21_to_router_23_20_rsp = router_23_21_rsp_out[2]; - assign router_23_21_to_router_22_21_rsp = router_23_21_rsp_out[3]; - assign router_23_21_to_magia_tile_ni_23_21_rsp = router_23_21_rsp_out[4]; - - assign router_23_21_to_router_23_22_req = router_23_21_req_out[0]; - assign router_23_21_to_router_24_21_req = router_23_21_req_out[1]; - assign router_23_21_to_router_23_20_req = router_23_21_req_out[2]; - assign router_23_21_to_router_22_21_req = router_23_21_req_out[3]; - assign router_23_21_to_magia_tile_ni_23_21_req = router_23_21_req_out[4]; - - assign router_23_21_rsp_in[0] = router_23_22_to_router_23_21_rsp; - assign router_23_21_rsp_in[1] = router_24_21_to_router_23_21_rsp; - assign router_23_21_rsp_in[2] = router_23_20_to_router_23_21_rsp; - assign router_23_21_rsp_in[3] = router_22_21_to_router_23_21_rsp; - assign router_23_21_rsp_in[4] = magia_tile_ni_23_21_to_router_23_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_21_req_in), - .floo_rsp_o (router_23_21_rsp_out), - .floo_req_o (router_23_21_req_out), - .floo_rsp_i (router_23_21_rsp_in) -); - - -floo_req_t [4:0] router_23_22_req_in; -floo_rsp_t [4:0] router_23_22_rsp_out; -floo_req_t [4:0] router_23_22_req_out; -floo_rsp_t [4:0] router_23_22_rsp_in; - - assign router_23_22_req_in[0] = router_23_23_to_router_23_22_req; - assign router_23_22_req_in[1] = router_24_22_to_router_23_22_req; - assign router_23_22_req_in[2] = router_23_21_to_router_23_22_req; - assign router_23_22_req_in[3] = router_22_22_to_router_23_22_req; - assign router_23_22_req_in[4] = magia_tile_ni_23_22_to_router_23_22_req; - - assign router_23_22_to_router_23_23_rsp = router_23_22_rsp_out[0]; - assign router_23_22_to_router_24_22_rsp = router_23_22_rsp_out[1]; - assign router_23_22_to_router_23_21_rsp = router_23_22_rsp_out[2]; - assign router_23_22_to_router_22_22_rsp = router_23_22_rsp_out[3]; - assign router_23_22_to_magia_tile_ni_23_22_rsp = router_23_22_rsp_out[4]; - - assign router_23_22_to_router_23_23_req = router_23_22_req_out[0]; - assign router_23_22_to_router_24_22_req = router_23_22_req_out[1]; - assign router_23_22_to_router_23_21_req = router_23_22_req_out[2]; - assign router_23_22_to_router_22_22_req = router_23_22_req_out[3]; - assign router_23_22_to_magia_tile_ni_23_22_req = router_23_22_req_out[4]; - - assign router_23_22_rsp_in[0] = router_23_23_to_router_23_22_rsp; - assign router_23_22_rsp_in[1] = router_24_22_to_router_23_22_rsp; - assign router_23_22_rsp_in[2] = router_23_21_to_router_23_22_rsp; - assign router_23_22_rsp_in[3] = router_22_22_to_router_23_22_rsp; - assign router_23_22_rsp_in[4] = magia_tile_ni_23_22_to_router_23_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_22_req_in), - .floo_rsp_o (router_23_22_rsp_out), - .floo_req_o (router_23_22_req_out), - .floo_rsp_i (router_23_22_rsp_in) -); - - -floo_req_t [4:0] router_23_23_req_in; -floo_rsp_t [4:0] router_23_23_rsp_out; -floo_req_t [4:0] router_23_23_req_out; -floo_rsp_t [4:0] router_23_23_rsp_in; - - assign router_23_23_req_in[0] = router_23_24_to_router_23_23_req; - assign router_23_23_req_in[1] = router_24_23_to_router_23_23_req; - assign router_23_23_req_in[2] = router_23_22_to_router_23_23_req; - assign router_23_23_req_in[3] = router_22_23_to_router_23_23_req; - assign router_23_23_req_in[4] = magia_tile_ni_23_23_to_router_23_23_req; - - assign router_23_23_to_router_23_24_rsp = router_23_23_rsp_out[0]; - assign router_23_23_to_router_24_23_rsp = router_23_23_rsp_out[1]; - assign router_23_23_to_router_23_22_rsp = router_23_23_rsp_out[2]; - assign router_23_23_to_router_22_23_rsp = router_23_23_rsp_out[3]; - assign router_23_23_to_magia_tile_ni_23_23_rsp = router_23_23_rsp_out[4]; - - assign router_23_23_to_router_23_24_req = router_23_23_req_out[0]; - assign router_23_23_to_router_24_23_req = router_23_23_req_out[1]; - assign router_23_23_to_router_23_22_req = router_23_23_req_out[2]; - assign router_23_23_to_router_22_23_req = router_23_23_req_out[3]; - assign router_23_23_to_magia_tile_ni_23_23_req = router_23_23_req_out[4]; - - assign router_23_23_rsp_in[0] = router_23_24_to_router_23_23_rsp; - assign router_23_23_rsp_in[1] = router_24_23_to_router_23_23_rsp; - assign router_23_23_rsp_in[2] = router_23_22_to_router_23_23_rsp; - assign router_23_23_rsp_in[3] = router_22_23_to_router_23_23_rsp; - assign router_23_23_rsp_in[4] = magia_tile_ni_23_23_to_router_23_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_23_req_in), - .floo_rsp_o (router_23_23_rsp_out), - .floo_req_o (router_23_23_req_out), - .floo_rsp_i (router_23_23_rsp_in) -); - - -floo_req_t [4:0] router_23_24_req_in; -floo_rsp_t [4:0] router_23_24_rsp_out; -floo_req_t [4:0] router_23_24_req_out; -floo_rsp_t [4:0] router_23_24_rsp_in; - - assign router_23_24_req_in[0] = router_23_25_to_router_23_24_req; - assign router_23_24_req_in[1] = router_24_24_to_router_23_24_req; - assign router_23_24_req_in[2] = router_23_23_to_router_23_24_req; - assign router_23_24_req_in[3] = router_22_24_to_router_23_24_req; - assign router_23_24_req_in[4] = magia_tile_ni_23_24_to_router_23_24_req; - - assign router_23_24_to_router_23_25_rsp = router_23_24_rsp_out[0]; - assign router_23_24_to_router_24_24_rsp = router_23_24_rsp_out[1]; - assign router_23_24_to_router_23_23_rsp = router_23_24_rsp_out[2]; - assign router_23_24_to_router_22_24_rsp = router_23_24_rsp_out[3]; - assign router_23_24_to_magia_tile_ni_23_24_rsp = router_23_24_rsp_out[4]; - - assign router_23_24_to_router_23_25_req = router_23_24_req_out[0]; - assign router_23_24_to_router_24_24_req = router_23_24_req_out[1]; - assign router_23_24_to_router_23_23_req = router_23_24_req_out[2]; - assign router_23_24_to_router_22_24_req = router_23_24_req_out[3]; - assign router_23_24_to_magia_tile_ni_23_24_req = router_23_24_req_out[4]; - - assign router_23_24_rsp_in[0] = router_23_25_to_router_23_24_rsp; - assign router_23_24_rsp_in[1] = router_24_24_to_router_23_24_rsp; - assign router_23_24_rsp_in[2] = router_23_23_to_router_23_24_rsp; - assign router_23_24_rsp_in[3] = router_22_24_to_router_23_24_rsp; - assign router_23_24_rsp_in[4] = magia_tile_ni_23_24_to_router_23_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_24_req_in), - .floo_rsp_o (router_23_24_rsp_out), - .floo_req_o (router_23_24_req_out), - .floo_rsp_i (router_23_24_rsp_in) -); - - -floo_req_t [4:0] router_23_25_req_in; -floo_rsp_t [4:0] router_23_25_rsp_out; -floo_req_t [4:0] router_23_25_req_out; -floo_rsp_t [4:0] router_23_25_rsp_in; - - assign router_23_25_req_in[0] = router_23_26_to_router_23_25_req; - assign router_23_25_req_in[1] = router_24_25_to_router_23_25_req; - assign router_23_25_req_in[2] = router_23_24_to_router_23_25_req; - assign router_23_25_req_in[3] = router_22_25_to_router_23_25_req; - assign router_23_25_req_in[4] = magia_tile_ni_23_25_to_router_23_25_req; - - assign router_23_25_to_router_23_26_rsp = router_23_25_rsp_out[0]; - assign router_23_25_to_router_24_25_rsp = router_23_25_rsp_out[1]; - assign router_23_25_to_router_23_24_rsp = router_23_25_rsp_out[2]; - assign router_23_25_to_router_22_25_rsp = router_23_25_rsp_out[3]; - assign router_23_25_to_magia_tile_ni_23_25_rsp = router_23_25_rsp_out[4]; - - assign router_23_25_to_router_23_26_req = router_23_25_req_out[0]; - assign router_23_25_to_router_24_25_req = router_23_25_req_out[1]; - assign router_23_25_to_router_23_24_req = router_23_25_req_out[2]; - assign router_23_25_to_router_22_25_req = router_23_25_req_out[3]; - assign router_23_25_to_magia_tile_ni_23_25_req = router_23_25_req_out[4]; - - assign router_23_25_rsp_in[0] = router_23_26_to_router_23_25_rsp; - assign router_23_25_rsp_in[1] = router_24_25_to_router_23_25_rsp; - assign router_23_25_rsp_in[2] = router_23_24_to_router_23_25_rsp; - assign router_23_25_rsp_in[3] = router_22_25_to_router_23_25_rsp; - assign router_23_25_rsp_in[4] = magia_tile_ni_23_25_to_router_23_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_25_req_in), - .floo_rsp_o (router_23_25_rsp_out), - .floo_req_o (router_23_25_req_out), - .floo_rsp_i (router_23_25_rsp_in) -); - - -floo_req_t [4:0] router_23_26_req_in; -floo_rsp_t [4:0] router_23_26_rsp_out; -floo_req_t [4:0] router_23_26_req_out; -floo_rsp_t [4:0] router_23_26_rsp_in; - - assign router_23_26_req_in[0] = router_23_27_to_router_23_26_req; - assign router_23_26_req_in[1] = router_24_26_to_router_23_26_req; - assign router_23_26_req_in[2] = router_23_25_to_router_23_26_req; - assign router_23_26_req_in[3] = router_22_26_to_router_23_26_req; - assign router_23_26_req_in[4] = magia_tile_ni_23_26_to_router_23_26_req; - - assign router_23_26_to_router_23_27_rsp = router_23_26_rsp_out[0]; - assign router_23_26_to_router_24_26_rsp = router_23_26_rsp_out[1]; - assign router_23_26_to_router_23_25_rsp = router_23_26_rsp_out[2]; - assign router_23_26_to_router_22_26_rsp = router_23_26_rsp_out[3]; - assign router_23_26_to_magia_tile_ni_23_26_rsp = router_23_26_rsp_out[4]; - - assign router_23_26_to_router_23_27_req = router_23_26_req_out[0]; - assign router_23_26_to_router_24_26_req = router_23_26_req_out[1]; - assign router_23_26_to_router_23_25_req = router_23_26_req_out[2]; - assign router_23_26_to_router_22_26_req = router_23_26_req_out[3]; - assign router_23_26_to_magia_tile_ni_23_26_req = router_23_26_req_out[4]; - - assign router_23_26_rsp_in[0] = router_23_27_to_router_23_26_rsp; - assign router_23_26_rsp_in[1] = router_24_26_to_router_23_26_rsp; - assign router_23_26_rsp_in[2] = router_23_25_to_router_23_26_rsp; - assign router_23_26_rsp_in[3] = router_22_26_to_router_23_26_rsp; - assign router_23_26_rsp_in[4] = magia_tile_ni_23_26_to_router_23_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_26_req_in), - .floo_rsp_o (router_23_26_rsp_out), - .floo_req_o (router_23_26_req_out), - .floo_rsp_i (router_23_26_rsp_in) -); - - -floo_req_t [4:0] router_23_27_req_in; -floo_rsp_t [4:0] router_23_27_rsp_out; -floo_req_t [4:0] router_23_27_req_out; -floo_rsp_t [4:0] router_23_27_rsp_in; - - assign router_23_27_req_in[0] = router_23_28_to_router_23_27_req; - assign router_23_27_req_in[1] = router_24_27_to_router_23_27_req; - assign router_23_27_req_in[2] = router_23_26_to_router_23_27_req; - assign router_23_27_req_in[3] = router_22_27_to_router_23_27_req; - assign router_23_27_req_in[4] = magia_tile_ni_23_27_to_router_23_27_req; - - assign router_23_27_to_router_23_28_rsp = router_23_27_rsp_out[0]; - assign router_23_27_to_router_24_27_rsp = router_23_27_rsp_out[1]; - assign router_23_27_to_router_23_26_rsp = router_23_27_rsp_out[2]; - assign router_23_27_to_router_22_27_rsp = router_23_27_rsp_out[3]; - assign router_23_27_to_magia_tile_ni_23_27_rsp = router_23_27_rsp_out[4]; - - assign router_23_27_to_router_23_28_req = router_23_27_req_out[0]; - assign router_23_27_to_router_24_27_req = router_23_27_req_out[1]; - assign router_23_27_to_router_23_26_req = router_23_27_req_out[2]; - assign router_23_27_to_router_22_27_req = router_23_27_req_out[3]; - assign router_23_27_to_magia_tile_ni_23_27_req = router_23_27_req_out[4]; - - assign router_23_27_rsp_in[0] = router_23_28_to_router_23_27_rsp; - assign router_23_27_rsp_in[1] = router_24_27_to_router_23_27_rsp; - assign router_23_27_rsp_in[2] = router_23_26_to_router_23_27_rsp; - assign router_23_27_rsp_in[3] = router_22_27_to_router_23_27_rsp; - assign router_23_27_rsp_in[4] = magia_tile_ni_23_27_to_router_23_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_27_req_in), - .floo_rsp_o (router_23_27_rsp_out), - .floo_req_o (router_23_27_req_out), - .floo_rsp_i (router_23_27_rsp_in) -); - - -floo_req_t [4:0] router_23_28_req_in; -floo_rsp_t [4:0] router_23_28_rsp_out; -floo_req_t [4:0] router_23_28_req_out; -floo_rsp_t [4:0] router_23_28_rsp_in; - - assign router_23_28_req_in[0] = router_23_29_to_router_23_28_req; - assign router_23_28_req_in[1] = router_24_28_to_router_23_28_req; - assign router_23_28_req_in[2] = router_23_27_to_router_23_28_req; - assign router_23_28_req_in[3] = router_22_28_to_router_23_28_req; - assign router_23_28_req_in[4] = magia_tile_ni_23_28_to_router_23_28_req; - - assign router_23_28_to_router_23_29_rsp = router_23_28_rsp_out[0]; - assign router_23_28_to_router_24_28_rsp = router_23_28_rsp_out[1]; - assign router_23_28_to_router_23_27_rsp = router_23_28_rsp_out[2]; - assign router_23_28_to_router_22_28_rsp = router_23_28_rsp_out[3]; - assign router_23_28_to_magia_tile_ni_23_28_rsp = router_23_28_rsp_out[4]; - - assign router_23_28_to_router_23_29_req = router_23_28_req_out[0]; - assign router_23_28_to_router_24_28_req = router_23_28_req_out[1]; - assign router_23_28_to_router_23_27_req = router_23_28_req_out[2]; - assign router_23_28_to_router_22_28_req = router_23_28_req_out[3]; - assign router_23_28_to_magia_tile_ni_23_28_req = router_23_28_req_out[4]; - - assign router_23_28_rsp_in[0] = router_23_29_to_router_23_28_rsp; - assign router_23_28_rsp_in[1] = router_24_28_to_router_23_28_rsp; - assign router_23_28_rsp_in[2] = router_23_27_to_router_23_28_rsp; - assign router_23_28_rsp_in[3] = router_22_28_to_router_23_28_rsp; - assign router_23_28_rsp_in[4] = magia_tile_ni_23_28_to_router_23_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_28_req_in), - .floo_rsp_o (router_23_28_rsp_out), - .floo_req_o (router_23_28_req_out), - .floo_rsp_i (router_23_28_rsp_in) -); - - -floo_req_t [4:0] router_23_29_req_in; -floo_rsp_t [4:0] router_23_29_rsp_out; -floo_req_t [4:0] router_23_29_req_out; -floo_rsp_t [4:0] router_23_29_rsp_in; - - assign router_23_29_req_in[0] = router_23_30_to_router_23_29_req; - assign router_23_29_req_in[1] = router_24_29_to_router_23_29_req; - assign router_23_29_req_in[2] = router_23_28_to_router_23_29_req; - assign router_23_29_req_in[3] = router_22_29_to_router_23_29_req; - assign router_23_29_req_in[4] = magia_tile_ni_23_29_to_router_23_29_req; - - assign router_23_29_to_router_23_30_rsp = router_23_29_rsp_out[0]; - assign router_23_29_to_router_24_29_rsp = router_23_29_rsp_out[1]; - assign router_23_29_to_router_23_28_rsp = router_23_29_rsp_out[2]; - assign router_23_29_to_router_22_29_rsp = router_23_29_rsp_out[3]; - assign router_23_29_to_magia_tile_ni_23_29_rsp = router_23_29_rsp_out[4]; - - assign router_23_29_to_router_23_30_req = router_23_29_req_out[0]; - assign router_23_29_to_router_24_29_req = router_23_29_req_out[1]; - assign router_23_29_to_router_23_28_req = router_23_29_req_out[2]; - assign router_23_29_to_router_22_29_req = router_23_29_req_out[3]; - assign router_23_29_to_magia_tile_ni_23_29_req = router_23_29_req_out[4]; - - assign router_23_29_rsp_in[0] = router_23_30_to_router_23_29_rsp; - assign router_23_29_rsp_in[1] = router_24_29_to_router_23_29_rsp; - assign router_23_29_rsp_in[2] = router_23_28_to_router_23_29_rsp; - assign router_23_29_rsp_in[3] = router_22_29_to_router_23_29_rsp; - assign router_23_29_rsp_in[4] = magia_tile_ni_23_29_to_router_23_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_29_req_in), - .floo_rsp_o (router_23_29_rsp_out), - .floo_req_o (router_23_29_req_out), - .floo_rsp_i (router_23_29_rsp_in) -); - - -floo_req_t [4:0] router_23_30_req_in; -floo_rsp_t [4:0] router_23_30_rsp_out; -floo_req_t [4:0] router_23_30_req_out; -floo_rsp_t [4:0] router_23_30_rsp_in; - - assign router_23_30_req_in[0] = router_23_31_to_router_23_30_req; - assign router_23_30_req_in[1] = router_24_30_to_router_23_30_req; - assign router_23_30_req_in[2] = router_23_29_to_router_23_30_req; - assign router_23_30_req_in[3] = router_22_30_to_router_23_30_req; - assign router_23_30_req_in[4] = magia_tile_ni_23_30_to_router_23_30_req; - - assign router_23_30_to_router_23_31_rsp = router_23_30_rsp_out[0]; - assign router_23_30_to_router_24_30_rsp = router_23_30_rsp_out[1]; - assign router_23_30_to_router_23_29_rsp = router_23_30_rsp_out[2]; - assign router_23_30_to_router_22_30_rsp = router_23_30_rsp_out[3]; - assign router_23_30_to_magia_tile_ni_23_30_rsp = router_23_30_rsp_out[4]; - - assign router_23_30_to_router_23_31_req = router_23_30_req_out[0]; - assign router_23_30_to_router_24_30_req = router_23_30_req_out[1]; - assign router_23_30_to_router_23_29_req = router_23_30_req_out[2]; - assign router_23_30_to_router_22_30_req = router_23_30_req_out[3]; - assign router_23_30_to_magia_tile_ni_23_30_req = router_23_30_req_out[4]; - - assign router_23_30_rsp_in[0] = router_23_31_to_router_23_30_rsp; - assign router_23_30_rsp_in[1] = router_24_30_to_router_23_30_rsp; - assign router_23_30_rsp_in[2] = router_23_29_to_router_23_30_rsp; - assign router_23_30_rsp_in[3] = router_22_30_to_router_23_30_rsp; - assign router_23_30_rsp_in[4] = magia_tile_ni_23_30_to_router_23_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_30_req_in), - .floo_rsp_o (router_23_30_rsp_out), - .floo_req_o (router_23_30_req_out), - .floo_rsp_i (router_23_30_rsp_in) -); - - -floo_req_t [4:0] router_23_31_req_in; -floo_rsp_t [4:0] router_23_31_rsp_out; -floo_req_t [4:0] router_23_31_req_out; -floo_rsp_t [4:0] router_23_31_rsp_in; - - assign router_23_31_req_in[0] = '0; - assign router_23_31_req_in[1] = router_24_31_to_router_23_31_req; - assign router_23_31_req_in[2] = router_23_30_to_router_23_31_req; - assign router_23_31_req_in[3] = router_22_31_to_router_23_31_req; - assign router_23_31_req_in[4] = magia_tile_ni_23_31_to_router_23_31_req; - - assign router_23_31_to_router_24_31_rsp = router_23_31_rsp_out[1]; - assign router_23_31_to_router_23_30_rsp = router_23_31_rsp_out[2]; - assign router_23_31_to_router_22_31_rsp = router_23_31_rsp_out[3]; - assign router_23_31_to_magia_tile_ni_23_31_rsp = router_23_31_rsp_out[4]; - - assign router_23_31_to_router_24_31_req = router_23_31_req_out[1]; - assign router_23_31_to_router_23_30_req = router_23_31_req_out[2]; - assign router_23_31_to_router_22_31_req = router_23_31_req_out[3]; - assign router_23_31_to_magia_tile_ni_23_31_req = router_23_31_req_out[4]; - - assign router_23_31_rsp_in[0] = '0; - assign router_23_31_rsp_in[1] = router_24_31_to_router_23_31_rsp; - assign router_23_31_rsp_in[2] = router_23_30_to_router_23_31_rsp; - assign router_23_31_rsp_in[3] = router_22_31_to_router_23_31_rsp; - assign router_23_31_rsp_in[4] = magia_tile_ni_23_31_to_router_23_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_23_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 24, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_23_31_req_in), - .floo_rsp_o (router_23_31_rsp_out), - .floo_req_o (router_23_31_req_out), - .floo_rsp_i (router_23_31_rsp_in) -); - - -floo_req_t [4:0] router_24_0_req_in; -floo_rsp_t [4:0] router_24_0_rsp_out; -floo_req_t [4:0] router_24_0_req_out; -floo_rsp_t [4:0] router_24_0_rsp_in; - - assign router_24_0_req_in[0] = router_24_1_to_router_24_0_req; - assign router_24_0_req_in[1] = router_25_0_to_router_24_0_req; - assign router_24_0_req_in[2] = '0; - assign router_24_0_req_in[3] = router_23_0_to_router_24_0_req; - assign router_24_0_req_in[4] = magia_tile_ni_24_0_to_router_24_0_req; - - assign router_24_0_to_router_24_1_rsp = router_24_0_rsp_out[0]; - assign router_24_0_to_router_25_0_rsp = router_24_0_rsp_out[1]; - assign router_24_0_to_router_23_0_rsp = router_24_0_rsp_out[3]; - assign router_24_0_to_magia_tile_ni_24_0_rsp = router_24_0_rsp_out[4]; - - assign router_24_0_to_router_24_1_req = router_24_0_req_out[0]; - assign router_24_0_to_router_25_0_req = router_24_0_req_out[1]; - assign router_24_0_to_router_23_0_req = router_24_0_req_out[3]; - assign router_24_0_to_magia_tile_ni_24_0_req = router_24_0_req_out[4]; - - assign router_24_0_rsp_in[0] = router_24_1_to_router_24_0_rsp; - assign router_24_0_rsp_in[1] = router_25_0_to_router_24_0_rsp; - assign router_24_0_rsp_in[2] = '0; - assign router_24_0_rsp_in[3] = router_23_0_to_router_24_0_rsp; - assign router_24_0_rsp_in[4] = magia_tile_ni_24_0_to_router_24_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_0_req_in), - .floo_rsp_o (router_24_0_rsp_out), - .floo_req_o (router_24_0_req_out), - .floo_rsp_i (router_24_0_rsp_in) -); - - -floo_req_t [4:0] router_24_1_req_in; -floo_rsp_t [4:0] router_24_1_rsp_out; -floo_req_t [4:0] router_24_1_req_out; -floo_rsp_t [4:0] router_24_1_rsp_in; - - assign router_24_1_req_in[0] = router_24_2_to_router_24_1_req; - assign router_24_1_req_in[1] = router_25_1_to_router_24_1_req; - assign router_24_1_req_in[2] = router_24_0_to_router_24_1_req; - assign router_24_1_req_in[3] = router_23_1_to_router_24_1_req; - assign router_24_1_req_in[4] = magia_tile_ni_24_1_to_router_24_1_req; - - assign router_24_1_to_router_24_2_rsp = router_24_1_rsp_out[0]; - assign router_24_1_to_router_25_1_rsp = router_24_1_rsp_out[1]; - assign router_24_1_to_router_24_0_rsp = router_24_1_rsp_out[2]; - assign router_24_1_to_router_23_1_rsp = router_24_1_rsp_out[3]; - assign router_24_1_to_magia_tile_ni_24_1_rsp = router_24_1_rsp_out[4]; - - assign router_24_1_to_router_24_2_req = router_24_1_req_out[0]; - assign router_24_1_to_router_25_1_req = router_24_1_req_out[1]; - assign router_24_1_to_router_24_0_req = router_24_1_req_out[2]; - assign router_24_1_to_router_23_1_req = router_24_1_req_out[3]; - assign router_24_1_to_magia_tile_ni_24_1_req = router_24_1_req_out[4]; - - assign router_24_1_rsp_in[0] = router_24_2_to_router_24_1_rsp; - assign router_24_1_rsp_in[1] = router_25_1_to_router_24_1_rsp; - assign router_24_1_rsp_in[2] = router_24_0_to_router_24_1_rsp; - assign router_24_1_rsp_in[3] = router_23_1_to_router_24_1_rsp; - assign router_24_1_rsp_in[4] = magia_tile_ni_24_1_to_router_24_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_1_req_in), - .floo_rsp_o (router_24_1_rsp_out), - .floo_req_o (router_24_1_req_out), - .floo_rsp_i (router_24_1_rsp_in) -); - - -floo_req_t [4:0] router_24_2_req_in; -floo_rsp_t [4:0] router_24_2_rsp_out; -floo_req_t [4:0] router_24_2_req_out; -floo_rsp_t [4:0] router_24_2_rsp_in; - - assign router_24_2_req_in[0] = router_24_3_to_router_24_2_req; - assign router_24_2_req_in[1] = router_25_2_to_router_24_2_req; - assign router_24_2_req_in[2] = router_24_1_to_router_24_2_req; - assign router_24_2_req_in[3] = router_23_2_to_router_24_2_req; - assign router_24_2_req_in[4] = magia_tile_ni_24_2_to_router_24_2_req; - - assign router_24_2_to_router_24_3_rsp = router_24_2_rsp_out[0]; - assign router_24_2_to_router_25_2_rsp = router_24_2_rsp_out[1]; - assign router_24_2_to_router_24_1_rsp = router_24_2_rsp_out[2]; - assign router_24_2_to_router_23_2_rsp = router_24_2_rsp_out[3]; - assign router_24_2_to_magia_tile_ni_24_2_rsp = router_24_2_rsp_out[4]; - - assign router_24_2_to_router_24_3_req = router_24_2_req_out[0]; - assign router_24_2_to_router_25_2_req = router_24_2_req_out[1]; - assign router_24_2_to_router_24_1_req = router_24_2_req_out[2]; - assign router_24_2_to_router_23_2_req = router_24_2_req_out[3]; - assign router_24_2_to_magia_tile_ni_24_2_req = router_24_2_req_out[4]; - - assign router_24_2_rsp_in[0] = router_24_3_to_router_24_2_rsp; - assign router_24_2_rsp_in[1] = router_25_2_to_router_24_2_rsp; - assign router_24_2_rsp_in[2] = router_24_1_to_router_24_2_rsp; - assign router_24_2_rsp_in[3] = router_23_2_to_router_24_2_rsp; - assign router_24_2_rsp_in[4] = magia_tile_ni_24_2_to_router_24_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_2_req_in), - .floo_rsp_o (router_24_2_rsp_out), - .floo_req_o (router_24_2_req_out), - .floo_rsp_i (router_24_2_rsp_in) -); - - -floo_req_t [4:0] router_24_3_req_in; -floo_rsp_t [4:0] router_24_3_rsp_out; -floo_req_t [4:0] router_24_3_req_out; -floo_rsp_t [4:0] router_24_3_rsp_in; - - assign router_24_3_req_in[0] = router_24_4_to_router_24_3_req; - assign router_24_3_req_in[1] = router_25_3_to_router_24_3_req; - assign router_24_3_req_in[2] = router_24_2_to_router_24_3_req; - assign router_24_3_req_in[3] = router_23_3_to_router_24_3_req; - assign router_24_3_req_in[4] = magia_tile_ni_24_3_to_router_24_3_req; - - assign router_24_3_to_router_24_4_rsp = router_24_3_rsp_out[0]; - assign router_24_3_to_router_25_3_rsp = router_24_3_rsp_out[1]; - assign router_24_3_to_router_24_2_rsp = router_24_3_rsp_out[2]; - assign router_24_3_to_router_23_3_rsp = router_24_3_rsp_out[3]; - assign router_24_3_to_magia_tile_ni_24_3_rsp = router_24_3_rsp_out[4]; - - assign router_24_3_to_router_24_4_req = router_24_3_req_out[0]; - assign router_24_3_to_router_25_3_req = router_24_3_req_out[1]; - assign router_24_3_to_router_24_2_req = router_24_3_req_out[2]; - assign router_24_3_to_router_23_3_req = router_24_3_req_out[3]; - assign router_24_3_to_magia_tile_ni_24_3_req = router_24_3_req_out[4]; - - assign router_24_3_rsp_in[0] = router_24_4_to_router_24_3_rsp; - assign router_24_3_rsp_in[1] = router_25_3_to_router_24_3_rsp; - assign router_24_3_rsp_in[2] = router_24_2_to_router_24_3_rsp; - assign router_24_3_rsp_in[3] = router_23_3_to_router_24_3_rsp; - assign router_24_3_rsp_in[4] = magia_tile_ni_24_3_to_router_24_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_3_req_in), - .floo_rsp_o (router_24_3_rsp_out), - .floo_req_o (router_24_3_req_out), - .floo_rsp_i (router_24_3_rsp_in) -); - - -floo_req_t [4:0] router_24_4_req_in; -floo_rsp_t [4:0] router_24_4_rsp_out; -floo_req_t [4:0] router_24_4_req_out; -floo_rsp_t [4:0] router_24_4_rsp_in; - - assign router_24_4_req_in[0] = router_24_5_to_router_24_4_req; - assign router_24_4_req_in[1] = router_25_4_to_router_24_4_req; - assign router_24_4_req_in[2] = router_24_3_to_router_24_4_req; - assign router_24_4_req_in[3] = router_23_4_to_router_24_4_req; - assign router_24_4_req_in[4] = magia_tile_ni_24_4_to_router_24_4_req; - - assign router_24_4_to_router_24_5_rsp = router_24_4_rsp_out[0]; - assign router_24_4_to_router_25_4_rsp = router_24_4_rsp_out[1]; - assign router_24_4_to_router_24_3_rsp = router_24_4_rsp_out[2]; - assign router_24_4_to_router_23_4_rsp = router_24_4_rsp_out[3]; - assign router_24_4_to_magia_tile_ni_24_4_rsp = router_24_4_rsp_out[4]; - - assign router_24_4_to_router_24_5_req = router_24_4_req_out[0]; - assign router_24_4_to_router_25_4_req = router_24_4_req_out[1]; - assign router_24_4_to_router_24_3_req = router_24_4_req_out[2]; - assign router_24_4_to_router_23_4_req = router_24_4_req_out[3]; - assign router_24_4_to_magia_tile_ni_24_4_req = router_24_4_req_out[4]; - - assign router_24_4_rsp_in[0] = router_24_5_to_router_24_4_rsp; - assign router_24_4_rsp_in[1] = router_25_4_to_router_24_4_rsp; - assign router_24_4_rsp_in[2] = router_24_3_to_router_24_4_rsp; - assign router_24_4_rsp_in[3] = router_23_4_to_router_24_4_rsp; - assign router_24_4_rsp_in[4] = magia_tile_ni_24_4_to_router_24_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_4_req_in), - .floo_rsp_o (router_24_4_rsp_out), - .floo_req_o (router_24_4_req_out), - .floo_rsp_i (router_24_4_rsp_in) -); - - -floo_req_t [4:0] router_24_5_req_in; -floo_rsp_t [4:0] router_24_5_rsp_out; -floo_req_t [4:0] router_24_5_req_out; -floo_rsp_t [4:0] router_24_5_rsp_in; - - assign router_24_5_req_in[0] = router_24_6_to_router_24_5_req; - assign router_24_5_req_in[1] = router_25_5_to_router_24_5_req; - assign router_24_5_req_in[2] = router_24_4_to_router_24_5_req; - assign router_24_5_req_in[3] = router_23_5_to_router_24_5_req; - assign router_24_5_req_in[4] = magia_tile_ni_24_5_to_router_24_5_req; - - assign router_24_5_to_router_24_6_rsp = router_24_5_rsp_out[0]; - assign router_24_5_to_router_25_5_rsp = router_24_5_rsp_out[1]; - assign router_24_5_to_router_24_4_rsp = router_24_5_rsp_out[2]; - assign router_24_5_to_router_23_5_rsp = router_24_5_rsp_out[3]; - assign router_24_5_to_magia_tile_ni_24_5_rsp = router_24_5_rsp_out[4]; - - assign router_24_5_to_router_24_6_req = router_24_5_req_out[0]; - assign router_24_5_to_router_25_5_req = router_24_5_req_out[1]; - assign router_24_5_to_router_24_4_req = router_24_5_req_out[2]; - assign router_24_5_to_router_23_5_req = router_24_5_req_out[3]; - assign router_24_5_to_magia_tile_ni_24_5_req = router_24_5_req_out[4]; - - assign router_24_5_rsp_in[0] = router_24_6_to_router_24_5_rsp; - assign router_24_5_rsp_in[1] = router_25_5_to_router_24_5_rsp; - assign router_24_5_rsp_in[2] = router_24_4_to_router_24_5_rsp; - assign router_24_5_rsp_in[3] = router_23_5_to_router_24_5_rsp; - assign router_24_5_rsp_in[4] = magia_tile_ni_24_5_to_router_24_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_5_req_in), - .floo_rsp_o (router_24_5_rsp_out), - .floo_req_o (router_24_5_req_out), - .floo_rsp_i (router_24_5_rsp_in) -); - - -floo_req_t [4:0] router_24_6_req_in; -floo_rsp_t [4:0] router_24_6_rsp_out; -floo_req_t [4:0] router_24_6_req_out; -floo_rsp_t [4:0] router_24_6_rsp_in; - - assign router_24_6_req_in[0] = router_24_7_to_router_24_6_req; - assign router_24_6_req_in[1] = router_25_6_to_router_24_6_req; - assign router_24_6_req_in[2] = router_24_5_to_router_24_6_req; - assign router_24_6_req_in[3] = router_23_6_to_router_24_6_req; - assign router_24_6_req_in[4] = magia_tile_ni_24_6_to_router_24_6_req; - - assign router_24_6_to_router_24_7_rsp = router_24_6_rsp_out[0]; - assign router_24_6_to_router_25_6_rsp = router_24_6_rsp_out[1]; - assign router_24_6_to_router_24_5_rsp = router_24_6_rsp_out[2]; - assign router_24_6_to_router_23_6_rsp = router_24_6_rsp_out[3]; - assign router_24_6_to_magia_tile_ni_24_6_rsp = router_24_6_rsp_out[4]; - - assign router_24_6_to_router_24_7_req = router_24_6_req_out[0]; - assign router_24_6_to_router_25_6_req = router_24_6_req_out[1]; - assign router_24_6_to_router_24_5_req = router_24_6_req_out[2]; - assign router_24_6_to_router_23_6_req = router_24_6_req_out[3]; - assign router_24_6_to_magia_tile_ni_24_6_req = router_24_6_req_out[4]; - - assign router_24_6_rsp_in[0] = router_24_7_to_router_24_6_rsp; - assign router_24_6_rsp_in[1] = router_25_6_to_router_24_6_rsp; - assign router_24_6_rsp_in[2] = router_24_5_to_router_24_6_rsp; - assign router_24_6_rsp_in[3] = router_23_6_to_router_24_6_rsp; - assign router_24_6_rsp_in[4] = magia_tile_ni_24_6_to_router_24_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_6_req_in), - .floo_rsp_o (router_24_6_rsp_out), - .floo_req_o (router_24_6_req_out), - .floo_rsp_i (router_24_6_rsp_in) -); - - -floo_req_t [4:0] router_24_7_req_in; -floo_rsp_t [4:0] router_24_7_rsp_out; -floo_req_t [4:0] router_24_7_req_out; -floo_rsp_t [4:0] router_24_7_rsp_in; - - assign router_24_7_req_in[0] = router_24_8_to_router_24_7_req; - assign router_24_7_req_in[1] = router_25_7_to_router_24_7_req; - assign router_24_7_req_in[2] = router_24_6_to_router_24_7_req; - assign router_24_7_req_in[3] = router_23_7_to_router_24_7_req; - assign router_24_7_req_in[4] = magia_tile_ni_24_7_to_router_24_7_req; - - assign router_24_7_to_router_24_8_rsp = router_24_7_rsp_out[0]; - assign router_24_7_to_router_25_7_rsp = router_24_7_rsp_out[1]; - assign router_24_7_to_router_24_6_rsp = router_24_7_rsp_out[2]; - assign router_24_7_to_router_23_7_rsp = router_24_7_rsp_out[3]; - assign router_24_7_to_magia_tile_ni_24_7_rsp = router_24_7_rsp_out[4]; - - assign router_24_7_to_router_24_8_req = router_24_7_req_out[0]; - assign router_24_7_to_router_25_7_req = router_24_7_req_out[1]; - assign router_24_7_to_router_24_6_req = router_24_7_req_out[2]; - assign router_24_7_to_router_23_7_req = router_24_7_req_out[3]; - assign router_24_7_to_magia_tile_ni_24_7_req = router_24_7_req_out[4]; - - assign router_24_7_rsp_in[0] = router_24_8_to_router_24_7_rsp; - assign router_24_7_rsp_in[1] = router_25_7_to_router_24_7_rsp; - assign router_24_7_rsp_in[2] = router_24_6_to_router_24_7_rsp; - assign router_24_7_rsp_in[3] = router_23_7_to_router_24_7_rsp; - assign router_24_7_rsp_in[4] = magia_tile_ni_24_7_to_router_24_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_7_req_in), - .floo_rsp_o (router_24_7_rsp_out), - .floo_req_o (router_24_7_req_out), - .floo_rsp_i (router_24_7_rsp_in) -); - - -floo_req_t [4:0] router_24_8_req_in; -floo_rsp_t [4:0] router_24_8_rsp_out; -floo_req_t [4:0] router_24_8_req_out; -floo_rsp_t [4:0] router_24_8_rsp_in; - - assign router_24_8_req_in[0] = router_24_9_to_router_24_8_req; - assign router_24_8_req_in[1] = router_25_8_to_router_24_8_req; - assign router_24_8_req_in[2] = router_24_7_to_router_24_8_req; - assign router_24_8_req_in[3] = router_23_8_to_router_24_8_req; - assign router_24_8_req_in[4] = magia_tile_ni_24_8_to_router_24_8_req; - - assign router_24_8_to_router_24_9_rsp = router_24_8_rsp_out[0]; - assign router_24_8_to_router_25_8_rsp = router_24_8_rsp_out[1]; - assign router_24_8_to_router_24_7_rsp = router_24_8_rsp_out[2]; - assign router_24_8_to_router_23_8_rsp = router_24_8_rsp_out[3]; - assign router_24_8_to_magia_tile_ni_24_8_rsp = router_24_8_rsp_out[4]; - - assign router_24_8_to_router_24_9_req = router_24_8_req_out[0]; - assign router_24_8_to_router_25_8_req = router_24_8_req_out[1]; - assign router_24_8_to_router_24_7_req = router_24_8_req_out[2]; - assign router_24_8_to_router_23_8_req = router_24_8_req_out[3]; - assign router_24_8_to_magia_tile_ni_24_8_req = router_24_8_req_out[4]; - - assign router_24_8_rsp_in[0] = router_24_9_to_router_24_8_rsp; - assign router_24_8_rsp_in[1] = router_25_8_to_router_24_8_rsp; - assign router_24_8_rsp_in[2] = router_24_7_to_router_24_8_rsp; - assign router_24_8_rsp_in[3] = router_23_8_to_router_24_8_rsp; - assign router_24_8_rsp_in[4] = magia_tile_ni_24_8_to_router_24_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_8_req_in), - .floo_rsp_o (router_24_8_rsp_out), - .floo_req_o (router_24_8_req_out), - .floo_rsp_i (router_24_8_rsp_in) -); - - -floo_req_t [4:0] router_24_9_req_in; -floo_rsp_t [4:0] router_24_9_rsp_out; -floo_req_t [4:0] router_24_9_req_out; -floo_rsp_t [4:0] router_24_9_rsp_in; - - assign router_24_9_req_in[0] = router_24_10_to_router_24_9_req; - assign router_24_9_req_in[1] = router_25_9_to_router_24_9_req; - assign router_24_9_req_in[2] = router_24_8_to_router_24_9_req; - assign router_24_9_req_in[3] = router_23_9_to_router_24_9_req; - assign router_24_9_req_in[4] = magia_tile_ni_24_9_to_router_24_9_req; - - assign router_24_9_to_router_24_10_rsp = router_24_9_rsp_out[0]; - assign router_24_9_to_router_25_9_rsp = router_24_9_rsp_out[1]; - assign router_24_9_to_router_24_8_rsp = router_24_9_rsp_out[2]; - assign router_24_9_to_router_23_9_rsp = router_24_9_rsp_out[3]; - assign router_24_9_to_magia_tile_ni_24_9_rsp = router_24_9_rsp_out[4]; - - assign router_24_9_to_router_24_10_req = router_24_9_req_out[0]; - assign router_24_9_to_router_25_9_req = router_24_9_req_out[1]; - assign router_24_9_to_router_24_8_req = router_24_9_req_out[2]; - assign router_24_9_to_router_23_9_req = router_24_9_req_out[3]; - assign router_24_9_to_magia_tile_ni_24_9_req = router_24_9_req_out[4]; - - assign router_24_9_rsp_in[0] = router_24_10_to_router_24_9_rsp; - assign router_24_9_rsp_in[1] = router_25_9_to_router_24_9_rsp; - assign router_24_9_rsp_in[2] = router_24_8_to_router_24_9_rsp; - assign router_24_9_rsp_in[3] = router_23_9_to_router_24_9_rsp; - assign router_24_9_rsp_in[4] = magia_tile_ni_24_9_to_router_24_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_9_req_in), - .floo_rsp_o (router_24_9_rsp_out), - .floo_req_o (router_24_9_req_out), - .floo_rsp_i (router_24_9_rsp_in) -); - - -floo_req_t [4:0] router_24_10_req_in; -floo_rsp_t [4:0] router_24_10_rsp_out; -floo_req_t [4:0] router_24_10_req_out; -floo_rsp_t [4:0] router_24_10_rsp_in; - - assign router_24_10_req_in[0] = router_24_11_to_router_24_10_req; - assign router_24_10_req_in[1] = router_25_10_to_router_24_10_req; - assign router_24_10_req_in[2] = router_24_9_to_router_24_10_req; - assign router_24_10_req_in[3] = router_23_10_to_router_24_10_req; - assign router_24_10_req_in[4] = magia_tile_ni_24_10_to_router_24_10_req; - - assign router_24_10_to_router_24_11_rsp = router_24_10_rsp_out[0]; - assign router_24_10_to_router_25_10_rsp = router_24_10_rsp_out[1]; - assign router_24_10_to_router_24_9_rsp = router_24_10_rsp_out[2]; - assign router_24_10_to_router_23_10_rsp = router_24_10_rsp_out[3]; - assign router_24_10_to_magia_tile_ni_24_10_rsp = router_24_10_rsp_out[4]; - - assign router_24_10_to_router_24_11_req = router_24_10_req_out[0]; - assign router_24_10_to_router_25_10_req = router_24_10_req_out[1]; - assign router_24_10_to_router_24_9_req = router_24_10_req_out[2]; - assign router_24_10_to_router_23_10_req = router_24_10_req_out[3]; - assign router_24_10_to_magia_tile_ni_24_10_req = router_24_10_req_out[4]; - - assign router_24_10_rsp_in[0] = router_24_11_to_router_24_10_rsp; - assign router_24_10_rsp_in[1] = router_25_10_to_router_24_10_rsp; - assign router_24_10_rsp_in[2] = router_24_9_to_router_24_10_rsp; - assign router_24_10_rsp_in[3] = router_23_10_to_router_24_10_rsp; - assign router_24_10_rsp_in[4] = magia_tile_ni_24_10_to_router_24_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_10_req_in), - .floo_rsp_o (router_24_10_rsp_out), - .floo_req_o (router_24_10_req_out), - .floo_rsp_i (router_24_10_rsp_in) -); - - -floo_req_t [4:0] router_24_11_req_in; -floo_rsp_t [4:0] router_24_11_rsp_out; -floo_req_t [4:0] router_24_11_req_out; -floo_rsp_t [4:0] router_24_11_rsp_in; - - assign router_24_11_req_in[0] = router_24_12_to_router_24_11_req; - assign router_24_11_req_in[1] = router_25_11_to_router_24_11_req; - assign router_24_11_req_in[2] = router_24_10_to_router_24_11_req; - assign router_24_11_req_in[3] = router_23_11_to_router_24_11_req; - assign router_24_11_req_in[4] = magia_tile_ni_24_11_to_router_24_11_req; - - assign router_24_11_to_router_24_12_rsp = router_24_11_rsp_out[0]; - assign router_24_11_to_router_25_11_rsp = router_24_11_rsp_out[1]; - assign router_24_11_to_router_24_10_rsp = router_24_11_rsp_out[2]; - assign router_24_11_to_router_23_11_rsp = router_24_11_rsp_out[3]; - assign router_24_11_to_magia_tile_ni_24_11_rsp = router_24_11_rsp_out[4]; - - assign router_24_11_to_router_24_12_req = router_24_11_req_out[0]; - assign router_24_11_to_router_25_11_req = router_24_11_req_out[1]; - assign router_24_11_to_router_24_10_req = router_24_11_req_out[2]; - assign router_24_11_to_router_23_11_req = router_24_11_req_out[3]; - assign router_24_11_to_magia_tile_ni_24_11_req = router_24_11_req_out[4]; - - assign router_24_11_rsp_in[0] = router_24_12_to_router_24_11_rsp; - assign router_24_11_rsp_in[1] = router_25_11_to_router_24_11_rsp; - assign router_24_11_rsp_in[2] = router_24_10_to_router_24_11_rsp; - assign router_24_11_rsp_in[3] = router_23_11_to_router_24_11_rsp; - assign router_24_11_rsp_in[4] = magia_tile_ni_24_11_to_router_24_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_11_req_in), - .floo_rsp_o (router_24_11_rsp_out), - .floo_req_o (router_24_11_req_out), - .floo_rsp_i (router_24_11_rsp_in) -); - - -floo_req_t [4:0] router_24_12_req_in; -floo_rsp_t [4:0] router_24_12_rsp_out; -floo_req_t [4:0] router_24_12_req_out; -floo_rsp_t [4:0] router_24_12_rsp_in; - - assign router_24_12_req_in[0] = router_24_13_to_router_24_12_req; - assign router_24_12_req_in[1] = router_25_12_to_router_24_12_req; - assign router_24_12_req_in[2] = router_24_11_to_router_24_12_req; - assign router_24_12_req_in[3] = router_23_12_to_router_24_12_req; - assign router_24_12_req_in[4] = magia_tile_ni_24_12_to_router_24_12_req; - - assign router_24_12_to_router_24_13_rsp = router_24_12_rsp_out[0]; - assign router_24_12_to_router_25_12_rsp = router_24_12_rsp_out[1]; - assign router_24_12_to_router_24_11_rsp = router_24_12_rsp_out[2]; - assign router_24_12_to_router_23_12_rsp = router_24_12_rsp_out[3]; - assign router_24_12_to_magia_tile_ni_24_12_rsp = router_24_12_rsp_out[4]; - - assign router_24_12_to_router_24_13_req = router_24_12_req_out[0]; - assign router_24_12_to_router_25_12_req = router_24_12_req_out[1]; - assign router_24_12_to_router_24_11_req = router_24_12_req_out[2]; - assign router_24_12_to_router_23_12_req = router_24_12_req_out[3]; - assign router_24_12_to_magia_tile_ni_24_12_req = router_24_12_req_out[4]; - - assign router_24_12_rsp_in[0] = router_24_13_to_router_24_12_rsp; - assign router_24_12_rsp_in[1] = router_25_12_to_router_24_12_rsp; - assign router_24_12_rsp_in[2] = router_24_11_to_router_24_12_rsp; - assign router_24_12_rsp_in[3] = router_23_12_to_router_24_12_rsp; - assign router_24_12_rsp_in[4] = magia_tile_ni_24_12_to_router_24_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_12_req_in), - .floo_rsp_o (router_24_12_rsp_out), - .floo_req_o (router_24_12_req_out), - .floo_rsp_i (router_24_12_rsp_in) -); - - -floo_req_t [4:0] router_24_13_req_in; -floo_rsp_t [4:0] router_24_13_rsp_out; -floo_req_t [4:0] router_24_13_req_out; -floo_rsp_t [4:0] router_24_13_rsp_in; - - assign router_24_13_req_in[0] = router_24_14_to_router_24_13_req; - assign router_24_13_req_in[1] = router_25_13_to_router_24_13_req; - assign router_24_13_req_in[2] = router_24_12_to_router_24_13_req; - assign router_24_13_req_in[3] = router_23_13_to_router_24_13_req; - assign router_24_13_req_in[4] = magia_tile_ni_24_13_to_router_24_13_req; - - assign router_24_13_to_router_24_14_rsp = router_24_13_rsp_out[0]; - assign router_24_13_to_router_25_13_rsp = router_24_13_rsp_out[1]; - assign router_24_13_to_router_24_12_rsp = router_24_13_rsp_out[2]; - assign router_24_13_to_router_23_13_rsp = router_24_13_rsp_out[3]; - assign router_24_13_to_magia_tile_ni_24_13_rsp = router_24_13_rsp_out[4]; - - assign router_24_13_to_router_24_14_req = router_24_13_req_out[0]; - assign router_24_13_to_router_25_13_req = router_24_13_req_out[1]; - assign router_24_13_to_router_24_12_req = router_24_13_req_out[2]; - assign router_24_13_to_router_23_13_req = router_24_13_req_out[3]; - assign router_24_13_to_magia_tile_ni_24_13_req = router_24_13_req_out[4]; - - assign router_24_13_rsp_in[0] = router_24_14_to_router_24_13_rsp; - assign router_24_13_rsp_in[1] = router_25_13_to_router_24_13_rsp; - assign router_24_13_rsp_in[2] = router_24_12_to_router_24_13_rsp; - assign router_24_13_rsp_in[3] = router_23_13_to_router_24_13_rsp; - assign router_24_13_rsp_in[4] = magia_tile_ni_24_13_to_router_24_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_13_req_in), - .floo_rsp_o (router_24_13_rsp_out), - .floo_req_o (router_24_13_req_out), - .floo_rsp_i (router_24_13_rsp_in) -); - - -floo_req_t [4:0] router_24_14_req_in; -floo_rsp_t [4:0] router_24_14_rsp_out; -floo_req_t [4:0] router_24_14_req_out; -floo_rsp_t [4:0] router_24_14_rsp_in; - - assign router_24_14_req_in[0] = router_24_15_to_router_24_14_req; - assign router_24_14_req_in[1] = router_25_14_to_router_24_14_req; - assign router_24_14_req_in[2] = router_24_13_to_router_24_14_req; - assign router_24_14_req_in[3] = router_23_14_to_router_24_14_req; - assign router_24_14_req_in[4] = magia_tile_ni_24_14_to_router_24_14_req; - - assign router_24_14_to_router_24_15_rsp = router_24_14_rsp_out[0]; - assign router_24_14_to_router_25_14_rsp = router_24_14_rsp_out[1]; - assign router_24_14_to_router_24_13_rsp = router_24_14_rsp_out[2]; - assign router_24_14_to_router_23_14_rsp = router_24_14_rsp_out[3]; - assign router_24_14_to_magia_tile_ni_24_14_rsp = router_24_14_rsp_out[4]; - - assign router_24_14_to_router_24_15_req = router_24_14_req_out[0]; - assign router_24_14_to_router_25_14_req = router_24_14_req_out[1]; - assign router_24_14_to_router_24_13_req = router_24_14_req_out[2]; - assign router_24_14_to_router_23_14_req = router_24_14_req_out[3]; - assign router_24_14_to_magia_tile_ni_24_14_req = router_24_14_req_out[4]; - - assign router_24_14_rsp_in[0] = router_24_15_to_router_24_14_rsp; - assign router_24_14_rsp_in[1] = router_25_14_to_router_24_14_rsp; - assign router_24_14_rsp_in[2] = router_24_13_to_router_24_14_rsp; - assign router_24_14_rsp_in[3] = router_23_14_to_router_24_14_rsp; - assign router_24_14_rsp_in[4] = magia_tile_ni_24_14_to_router_24_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_14_req_in), - .floo_rsp_o (router_24_14_rsp_out), - .floo_req_o (router_24_14_req_out), - .floo_rsp_i (router_24_14_rsp_in) -); - - -floo_req_t [4:0] router_24_15_req_in; -floo_rsp_t [4:0] router_24_15_rsp_out; -floo_req_t [4:0] router_24_15_req_out; -floo_rsp_t [4:0] router_24_15_rsp_in; - - assign router_24_15_req_in[0] = router_24_16_to_router_24_15_req; - assign router_24_15_req_in[1] = router_25_15_to_router_24_15_req; - assign router_24_15_req_in[2] = router_24_14_to_router_24_15_req; - assign router_24_15_req_in[3] = router_23_15_to_router_24_15_req; - assign router_24_15_req_in[4] = magia_tile_ni_24_15_to_router_24_15_req; - - assign router_24_15_to_router_24_16_rsp = router_24_15_rsp_out[0]; - assign router_24_15_to_router_25_15_rsp = router_24_15_rsp_out[1]; - assign router_24_15_to_router_24_14_rsp = router_24_15_rsp_out[2]; - assign router_24_15_to_router_23_15_rsp = router_24_15_rsp_out[3]; - assign router_24_15_to_magia_tile_ni_24_15_rsp = router_24_15_rsp_out[4]; - - assign router_24_15_to_router_24_16_req = router_24_15_req_out[0]; - assign router_24_15_to_router_25_15_req = router_24_15_req_out[1]; - assign router_24_15_to_router_24_14_req = router_24_15_req_out[2]; - assign router_24_15_to_router_23_15_req = router_24_15_req_out[3]; - assign router_24_15_to_magia_tile_ni_24_15_req = router_24_15_req_out[4]; - - assign router_24_15_rsp_in[0] = router_24_16_to_router_24_15_rsp; - assign router_24_15_rsp_in[1] = router_25_15_to_router_24_15_rsp; - assign router_24_15_rsp_in[2] = router_24_14_to_router_24_15_rsp; - assign router_24_15_rsp_in[3] = router_23_15_to_router_24_15_rsp; - assign router_24_15_rsp_in[4] = magia_tile_ni_24_15_to_router_24_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_15_req_in), - .floo_rsp_o (router_24_15_rsp_out), - .floo_req_o (router_24_15_req_out), - .floo_rsp_i (router_24_15_rsp_in) -); - - -floo_req_t [4:0] router_24_16_req_in; -floo_rsp_t [4:0] router_24_16_rsp_out; -floo_req_t [4:0] router_24_16_req_out; -floo_rsp_t [4:0] router_24_16_rsp_in; - - assign router_24_16_req_in[0] = router_24_17_to_router_24_16_req; - assign router_24_16_req_in[1] = router_25_16_to_router_24_16_req; - assign router_24_16_req_in[2] = router_24_15_to_router_24_16_req; - assign router_24_16_req_in[3] = router_23_16_to_router_24_16_req; - assign router_24_16_req_in[4] = magia_tile_ni_24_16_to_router_24_16_req; - - assign router_24_16_to_router_24_17_rsp = router_24_16_rsp_out[0]; - assign router_24_16_to_router_25_16_rsp = router_24_16_rsp_out[1]; - assign router_24_16_to_router_24_15_rsp = router_24_16_rsp_out[2]; - assign router_24_16_to_router_23_16_rsp = router_24_16_rsp_out[3]; - assign router_24_16_to_magia_tile_ni_24_16_rsp = router_24_16_rsp_out[4]; - - assign router_24_16_to_router_24_17_req = router_24_16_req_out[0]; - assign router_24_16_to_router_25_16_req = router_24_16_req_out[1]; - assign router_24_16_to_router_24_15_req = router_24_16_req_out[2]; - assign router_24_16_to_router_23_16_req = router_24_16_req_out[3]; - assign router_24_16_to_magia_tile_ni_24_16_req = router_24_16_req_out[4]; - - assign router_24_16_rsp_in[0] = router_24_17_to_router_24_16_rsp; - assign router_24_16_rsp_in[1] = router_25_16_to_router_24_16_rsp; - assign router_24_16_rsp_in[2] = router_24_15_to_router_24_16_rsp; - assign router_24_16_rsp_in[3] = router_23_16_to_router_24_16_rsp; - assign router_24_16_rsp_in[4] = magia_tile_ni_24_16_to_router_24_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_16_req_in), - .floo_rsp_o (router_24_16_rsp_out), - .floo_req_o (router_24_16_req_out), - .floo_rsp_i (router_24_16_rsp_in) -); - - -floo_req_t [4:0] router_24_17_req_in; -floo_rsp_t [4:0] router_24_17_rsp_out; -floo_req_t [4:0] router_24_17_req_out; -floo_rsp_t [4:0] router_24_17_rsp_in; - - assign router_24_17_req_in[0] = router_24_18_to_router_24_17_req; - assign router_24_17_req_in[1] = router_25_17_to_router_24_17_req; - assign router_24_17_req_in[2] = router_24_16_to_router_24_17_req; - assign router_24_17_req_in[3] = router_23_17_to_router_24_17_req; - assign router_24_17_req_in[4] = magia_tile_ni_24_17_to_router_24_17_req; - - assign router_24_17_to_router_24_18_rsp = router_24_17_rsp_out[0]; - assign router_24_17_to_router_25_17_rsp = router_24_17_rsp_out[1]; - assign router_24_17_to_router_24_16_rsp = router_24_17_rsp_out[2]; - assign router_24_17_to_router_23_17_rsp = router_24_17_rsp_out[3]; - assign router_24_17_to_magia_tile_ni_24_17_rsp = router_24_17_rsp_out[4]; - - assign router_24_17_to_router_24_18_req = router_24_17_req_out[0]; - assign router_24_17_to_router_25_17_req = router_24_17_req_out[1]; - assign router_24_17_to_router_24_16_req = router_24_17_req_out[2]; - assign router_24_17_to_router_23_17_req = router_24_17_req_out[3]; - assign router_24_17_to_magia_tile_ni_24_17_req = router_24_17_req_out[4]; - - assign router_24_17_rsp_in[0] = router_24_18_to_router_24_17_rsp; - assign router_24_17_rsp_in[1] = router_25_17_to_router_24_17_rsp; - assign router_24_17_rsp_in[2] = router_24_16_to_router_24_17_rsp; - assign router_24_17_rsp_in[3] = router_23_17_to_router_24_17_rsp; - assign router_24_17_rsp_in[4] = magia_tile_ni_24_17_to_router_24_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_17_req_in), - .floo_rsp_o (router_24_17_rsp_out), - .floo_req_o (router_24_17_req_out), - .floo_rsp_i (router_24_17_rsp_in) -); - - -floo_req_t [4:0] router_24_18_req_in; -floo_rsp_t [4:0] router_24_18_rsp_out; -floo_req_t [4:0] router_24_18_req_out; -floo_rsp_t [4:0] router_24_18_rsp_in; - - assign router_24_18_req_in[0] = router_24_19_to_router_24_18_req; - assign router_24_18_req_in[1] = router_25_18_to_router_24_18_req; - assign router_24_18_req_in[2] = router_24_17_to_router_24_18_req; - assign router_24_18_req_in[3] = router_23_18_to_router_24_18_req; - assign router_24_18_req_in[4] = magia_tile_ni_24_18_to_router_24_18_req; - - assign router_24_18_to_router_24_19_rsp = router_24_18_rsp_out[0]; - assign router_24_18_to_router_25_18_rsp = router_24_18_rsp_out[1]; - assign router_24_18_to_router_24_17_rsp = router_24_18_rsp_out[2]; - assign router_24_18_to_router_23_18_rsp = router_24_18_rsp_out[3]; - assign router_24_18_to_magia_tile_ni_24_18_rsp = router_24_18_rsp_out[4]; - - assign router_24_18_to_router_24_19_req = router_24_18_req_out[0]; - assign router_24_18_to_router_25_18_req = router_24_18_req_out[1]; - assign router_24_18_to_router_24_17_req = router_24_18_req_out[2]; - assign router_24_18_to_router_23_18_req = router_24_18_req_out[3]; - assign router_24_18_to_magia_tile_ni_24_18_req = router_24_18_req_out[4]; - - assign router_24_18_rsp_in[0] = router_24_19_to_router_24_18_rsp; - assign router_24_18_rsp_in[1] = router_25_18_to_router_24_18_rsp; - assign router_24_18_rsp_in[2] = router_24_17_to_router_24_18_rsp; - assign router_24_18_rsp_in[3] = router_23_18_to_router_24_18_rsp; - assign router_24_18_rsp_in[4] = magia_tile_ni_24_18_to_router_24_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_18_req_in), - .floo_rsp_o (router_24_18_rsp_out), - .floo_req_o (router_24_18_req_out), - .floo_rsp_i (router_24_18_rsp_in) -); - - -floo_req_t [4:0] router_24_19_req_in; -floo_rsp_t [4:0] router_24_19_rsp_out; -floo_req_t [4:0] router_24_19_req_out; -floo_rsp_t [4:0] router_24_19_rsp_in; - - assign router_24_19_req_in[0] = router_24_20_to_router_24_19_req; - assign router_24_19_req_in[1] = router_25_19_to_router_24_19_req; - assign router_24_19_req_in[2] = router_24_18_to_router_24_19_req; - assign router_24_19_req_in[3] = router_23_19_to_router_24_19_req; - assign router_24_19_req_in[4] = magia_tile_ni_24_19_to_router_24_19_req; - - assign router_24_19_to_router_24_20_rsp = router_24_19_rsp_out[0]; - assign router_24_19_to_router_25_19_rsp = router_24_19_rsp_out[1]; - assign router_24_19_to_router_24_18_rsp = router_24_19_rsp_out[2]; - assign router_24_19_to_router_23_19_rsp = router_24_19_rsp_out[3]; - assign router_24_19_to_magia_tile_ni_24_19_rsp = router_24_19_rsp_out[4]; - - assign router_24_19_to_router_24_20_req = router_24_19_req_out[0]; - assign router_24_19_to_router_25_19_req = router_24_19_req_out[1]; - assign router_24_19_to_router_24_18_req = router_24_19_req_out[2]; - assign router_24_19_to_router_23_19_req = router_24_19_req_out[3]; - assign router_24_19_to_magia_tile_ni_24_19_req = router_24_19_req_out[4]; - - assign router_24_19_rsp_in[0] = router_24_20_to_router_24_19_rsp; - assign router_24_19_rsp_in[1] = router_25_19_to_router_24_19_rsp; - assign router_24_19_rsp_in[2] = router_24_18_to_router_24_19_rsp; - assign router_24_19_rsp_in[3] = router_23_19_to_router_24_19_rsp; - assign router_24_19_rsp_in[4] = magia_tile_ni_24_19_to_router_24_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_19_req_in), - .floo_rsp_o (router_24_19_rsp_out), - .floo_req_o (router_24_19_req_out), - .floo_rsp_i (router_24_19_rsp_in) -); - - -floo_req_t [4:0] router_24_20_req_in; -floo_rsp_t [4:0] router_24_20_rsp_out; -floo_req_t [4:0] router_24_20_req_out; -floo_rsp_t [4:0] router_24_20_rsp_in; - - assign router_24_20_req_in[0] = router_24_21_to_router_24_20_req; - assign router_24_20_req_in[1] = router_25_20_to_router_24_20_req; - assign router_24_20_req_in[2] = router_24_19_to_router_24_20_req; - assign router_24_20_req_in[3] = router_23_20_to_router_24_20_req; - assign router_24_20_req_in[4] = magia_tile_ni_24_20_to_router_24_20_req; - - assign router_24_20_to_router_24_21_rsp = router_24_20_rsp_out[0]; - assign router_24_20_to_router_25_20_rsp = router_24_20_rsp_out[1]; - assign router_24_20_to_router_24_19_rsp = router_24_20_rsp_out[2]; - assign router_24_20_to_router_23_20_rsp = router_24_20_rsp_out[3]; - assign router_24_20_to_magia_tile_ni_24_20_rsp = router_24_20_rsp_out[4]; - - assign router_24_20_to_router_24_21_req = router_24_20_req_out[0]; - assign router_24_20_to_router_25_20_req = router_24_20_req_out[1]; - assign router_24_20_to_router_24_19_req = router_24_20_req_out[2]; - assign router_24_20_to_router_23_20_req = router_24_20_req_out[3]; - assign router_24_20_to_magia_tile_ni_24_20_req = router_24_20_req_out[4]; - - assign router_24_20_rsp_in[0] = router_24_21_to_router_24_20_rsp; - assign router_24_20_rsp_in[1] = router_25_20_to_router_24_20_rsp; - assign router_24_20_rsp_in[2] = router_24_19_to_router_24_20_rsp; - assign router_24_20_rsp_in[3] = router_23_20_to_router_24_20_rsp; - assign router_24_20_rsp_in[4] = magia_tile_ni_24_20_to_router_24_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_20_req_in), - .floo_rsp_o (router_24_20_rsp_out), - .floo_req_o (router_24_20_req_out), - .floo_rsp_i (router_24_20_rsp_in) -); - - -floo_req_t [4:0] router_24_21_req_in; -floo_rsp_t [4:0] router_24_21_rsp_out; -floo_req_t [4:0] router_24_21_req_out; -floo_rsp_t [4:0] router_24_21_rsp_in; - - assign router_24_21_req_in[0] = router_24_22_to_router_24_21_req; - assign router_24_21_req_in[1] = router_25_21_to_router_24_21_req; - assign router_24_21_req_in[2] = router_24_20_to_router_24_21_req; - assign router_24_21_req_in[3] = router_23_21_to_router_24_21_req; - assign router_24_21_req_in[4] = magia_tile_ni_24_21_to_router_24_21_req; - - assign router_24_21_to_router_24_22_rsp = router_24_21_rsp_out[0]; - assign router_24_21_to_router_25_21_rsp = router_24_21_rsp_out[1]; - assign router_24_21_to_router_24_20_rsp = router_24_21_rsp_out[2]; - assign router_24_21_to_router_23_21_rsp = router_24_21_rsp_out[3]; - assign router_24_21_to_magia_tile_ni_24_21_rsp = router_24_21_rsp_out[4]; - - assign router_24_21_to_router_24_22_req = router_24_21_req_out[0]; - assign router_24_21_to_router_25_21_req = router_24_21_req_out[1]; - assign router_24_21_to_router_24_20_req = router_24_21_req_out[2]; - assign router_24_21_to_router_23_21_req = router_24_21_req_out[3]; - assign router_24_21_to_magia_tile_ni_24_21_req = router_24_21_req_out[4]; - - assign router_24_21_rsp_in[0] = router_24_22_to_router_24_21_rsp; - assign router_24_21_rsp_in[1] = router_25_21_to_router_24_21_rsp; - assign router_24_21_rsp_in[2] = router_24_20_to_router_24_21_rsp; - assign router_24_21_rsp_in[3] = router_23_21_to_router_24_21_rsp; - assign router_24_21_rsp_in[4] = magia_tile_ni_24_21_to_router_24_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_21_req_in), - .floo_rsp_o (router_24_21_rsp_out), - .floo_req_o (router_24_21_req_out), - .floo_rsp_i (router_24_21_rsp_in) -); - - -floo_req_t [4:0] router_24_22_req_in; -floo_rsp_t [4:0] router_24_22_rsp_out; -floo_req_t [4:0] router_24_22_req_out; -floo_rsp_t [4:0] router_24_22_rsp_in; - - assign router_24_22_req_in[0] = router_24_23_to_router_24_22_req; - assign router_24_22_req_in[1] = router_25_22_to_router_24_22_req; - assign router_24_22_req_in[2] = router_24_21_to_router_24_22_req; - assign router_24_22_req_in[3] = router_23_22_to_router_24_22_req; - assign router_24_22_req_in[4] = magia_tile_ni_24_22_to_router_24_22_req; - - assign router_24_22_to_router_24_23_rsp = router_24_22_rsp_out[0]; - assign router_24_22_to_router_25_22_rsp = router_24_22_rsp_out[1]; - assign router_24_22_to_router_24_21_rsp = router_24_22_rsp_out[2]; - assign router_24_22_to_router_23_22_rsp = router_24_22_rsp_out[3]; - assign router_24_22_to_magia_tile_ni_24_22_rsp = router_24_22_rsp_out[4]; - - assign router_24_22_to_router_24_23_req = router_24_22_req_out[0]; - assign router_24_22_to_router_25_22_req = router_24_22_req_out[1]; - assign router_24_22_to_router_24_21_req = router_24_22_req_out[2]; - assign router_24_22_to_router_23_22_req = router_24_22_req_out[3]; - assign router_24_22_to_magia_tile_ni_24_22_req = router_24_22_req_out[4]; - - assign router_24_22_rsp_in[0] = router_24_23_to_router_24_22_rsp; - assign router_24_22_rsp_in[1] = router_25_22_to_router_24_22_rsp; - assign router_24_22_rsp_in[2] = router_24_21_to_router_24_22_rsp; - assign router_24_22_rsp_in[3] = router_23_22_to_router_24_22_rsp; - assign router_24_22_rsp_in[4] = magia_tile_ni_24_22_to_router_24_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_22_req_in), - .floo_rsp_o (router_24_22_rsp_out), - .floo_req_o (router_24_22_req_out), - .floo_rsp_i (router_24_22_rsp_in) -); - - -floo_req_t [4:0] router_24_23_req_in; -floo_rsp_t [4:0] router_24_23_rsp_out; -floo_req_t [4:0] router_24_23_req_out; -floo_rsp_t [4:0] router_24_23_rsp_in; - - assign router_24_23_req_in[0] = router_24_24_to_router_24_23_req; - assign router_24_23_req_in[1] = router_25_23_to_router_24_23_req; - assign router_24_23_req_in[2] = router_24_22_to_router_24_23_req; - assign router_24_23_req_in[3] = router_23_23_to_router_24_23_req; - assign router_24_23_req_in[4] = magia_tile_ni_24_23_to_router_24_23_req; - - assign router_24_23_to_router_24_24_rsp = router_24_23_rsp_out[0]; - assign router_24_23_to_router_25_23_rsp = router_24_23_rsp_out[1]; - assign router_24_23_to_router_24_22_rsp = router_24_23_rsp_out[2]; - assign router_24_23_to_router_23_23_rsp = router_24_23_rsp_out[3]; - assign router_24_23_to_magia_tile_ni_24_23_rsp = router_24_23_rsp_out[4]; - - assign router_24_23_to_router_24_24_req = router_24_23_req_out[0]; - assign router_24_23_to_router_25_23_req = router_24_23_req_out[1]; - assign router_24_23_to_router_24_22_req = router_24_23_req_out[2]; - assign router_24_23_to_router_23_23_req = router_24_23_req_out[3]; - assign router_24_23_to_magia_tile_ni_24_23_req = router_24_23_req_out[4]; - - assign router_24_23_rsp_in[0] = router_24_24_to_router_24_23_rsp; - assign router_24_23_rsp_in[1] = router_25_23_to_router_24_23_rsp; - assign router_24_23_rsp_in[2] = router_24_22_to_router_24_23_rsp; - assign router_24_23_rsp_in[3] = router_23_23_to_router_24_23_rsp; - assign router_24_23_rsp_in[4] = magia_tile_ni_24_23_to_router_24_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_23_req_in), - .floo_rsp_o (router_24_23_rsp_out), - .floo_req_o (router_24_23_req_out), - .floo_rsp_i (router_24_23_rsp_in) -); - - -floo_req_t [4:0] router_24_24_req_in; -floo_rsp_t [4:0] router_24_24_rsp_out; -floo_req_t [4:0] router_24_24_req_out; -floo_rsp_t [4:0] router_24_24_rsp_in; - - assign router_24_24_req_in[0] = router_24_25_to_router_24_24_req; - assign router_24_24_req_in[1] = router_25_24_to_router_24_24_req; - assign router_24_24_req_in[2] = router_24_23_to_router_24_24_req; - assign router_24_24_req_in[3] = router_23_24_to_router_24_24_req; - assign router_24_24_req_in[4] = magia_tile_ni_24_24_to_router_24_24_req; - - assign router_24_24_to_router_24_25_rsp = router_24_24_rsp_out[0]; - assign router_24_24_to_router_25_24_rsp = router_24_24_rsp_out[1]; - assign router_24_24_to_router_24_23_rsp = router_24_24_rsp_out[2]; - assign router_24_24_to_router_23_24_rsp = router_24_24_rsp_out[3]; - assign router_24_24_to_magia_tile_ni_24_24_rsp = router_24_24_rsp_out[4]; - - assign router_24_24_to_router_24_25_req = router_24_24_req_out[0]; - assign router_24_24_to_router_25_24_req = router_24_24_req_out[1]; - assign router_24_24_to_router_24_23_req = router_24_24_req_out[2]; - assign router_24_24_to_router_23_24_req = router_24_24_req_out[3]; - assign router_24_24_to_magia_tile_ni_24_24_req = router_24_24_req_out[4]; - - assign router_24_24_rsp_in[0] = router_24_25_to_router_24_24_rsp; - assign router_24_24_rsp_in[1] = router_25_24_to_router_24_24_rsp; - assign router_24_24_rsp_in[2] = router_24_23_to_router_24_24_rsp; - assign router_24_24_rsp_in[3] = router_23_24_to_router_24_24_rsp; - assign router_24_24_rsp_in[4] = magia_tile_ni_24_24_to_router_24_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_24_req_in), - .floo_rsp_o (router_24_24_rsp_out), - .floo_req_o (router_24_24_req_out), - .floo_rsp_i (router_24_24_rsp_in) -); - - -floo_req_t [4:0] router_24_25_req_in; -floo_rsp_t [4:0] router_24_25_rsp_out; -floo_req_t [4:0] router_24_25_req_out; -floo_rsp_t [4:0] router_24_25_rsp_in; - - assign router_24_25_req_in[0] = router_24_26_to_router_24_25_req; - assign router_24_25_req_in[1] = router_25_25_to_router_24_25_req; - assign router_24_25_req_in[2] = router_24_24_to_router_24_25_req; - assign router_24_25_req_in[3] = router_23_25_to_router_24_25_req; - assign router_24_25_req_in[4] = magia_tile_ni_24_25_to_router_24_25_req; - - assign router_24_25_to_router_24_26_rsp = router_24_25_rsp_out[0]; - assign router_24_25_to_router_25_25_rsp = router_24_25_rsp_out[1]; - assign router_24_25_to_router_24_24_rsp = router_24_25_rsp_out[2]; - assign router_24_25_to_router_23_25_rsp = router_24_25_rsp_out[3]; - assign router_24_25_to_magia_tile_ni_24_25_rsp = router_24_25_rsp_out[4]; - - assign router_24_25_to_router_24_26_req = router_24_25_req_out[0]; - assign router_24_25_to_router_25_25_req = router_24_25_req_out[1]; - assign router_24_25_to_router_24_24_req = router_24_25_req_out[2]; - assign router_24_25_to_router_23_25_req = router_24_25_req_out[3]; - assign router_24_25_to_magia_tile_ni_24_25_req = router_24_25_req_out[4]; - - assign router_24_25_rsp_in[0] = router_24_26_to_router_24_25_rsp; - assign router_24_25_rsp_in[1] = router_25_25_to_router_24_25_rsp; - assign router_24_25_rsp_in[2] = router_24_24_to_router_24_25_rsp; - assign router_24_25_rsp_in[3] = router_23_25_to_router_24_25_rsp; - assign router_24_25_rsp_in[4] = magia_tile_ni_24_25_to_router_24_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_25_req_in), - .floo_rsp_o (router_24_25_rsp_out), - .floo_req_o (router_24_25_req_out), - .floo_rsp_i (router_24_25_rsp_in) -); - - -floo_req_t [4:0] router_24_26_req_in; -floo_rsp_t [4:0] router_24_26_rsp_out; -floo_req_t [4:0] router_24_26_req_out; -floo_rsp_t [4:0] router_24_26_rsp_in; - - assign router_24_26_req_in[0] = router_24_27_to_router_24_26_req; - assign router_24_26_req_in[1] = router_25_26_to_router_24_26_req; - assign router_24_26_req_in[2] = router_24_25_to_router_24_26_req; - assign router_24_26_req_in[3] = router_23_26_to_router_24_26_req; - assign router_24_26_req_in[4] = magia_tile_ni_24_26_to_router_24_26_req; - - assign router_24_26_to_router_24_27_rsp = router_24_26_rsp_out[0]; - assign router_24_26_to_router_25_26_rsp = router_24_26_rsp_out[1]; - assign router_24_26_to_router_24_25_rsp = router_24_26_rsp_out[2]; - assign router_24_26_to_router_23_26_rsp = router_24_26_rsp_out[3]; - assign router_24_26_to_magia_tile_ni_24_26_rsp = router_24_26_rsp_out[4]; - - assign router_24_26_to_router_24_27_req = router_24_26_req_out[0]; - assign router_24_26_to_router_25_26_req = router_24_26_req_out[1]; - assign router_24_26_to_router_24_25_req = router_24_26_req_out[2]; - assign router_24_26_to_router_23_26_req = router_24_26_req_out[3]; - assign router_24_26_to_magia_tile_ni_24_26_req = router_24_26_req_out[4]; - - assign router_24_26_rsp_in[0] = router_24_27_to_router_24_26_rsp; - assign router_24_26_rsp_in[1] = router_25_26_to_router_24_26_rsp; - assign router_24_26_rsp_in[2] = router_24_25_to_router_24_26_rsp; - assign router_24_26_rsp_in[3] = router_23_26_to_router_24_26_rsp; - assign router_24_26_rsp_in[4] = magia_tile_ni_24_26_to_router_24_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_26_req_in), - .floo_rsp_o (router_24_26_rsp_out), - .floo_req_o (router_24_26_req_out), - .floo_rsp_i (router_24_26_rsp_in) -); - - -floo_req_t [4:0] router_24_27_req_in; -floo_rsp_t [4:0] router_24_27_rsp_out; -floo_req_t [4:0] router_24_27_req_out; -floo_rsp_t [4:0] router_24_27_rsp_in; - - assign router_24_27_req_in[0] = router_24_28_to_router_24_27_req; - assign router_24_27_req_in[1] = router_25_27_to_router_24_27_req; - assign router_24_27_req_in[2] = router_24_26_to_router_24_27_req; - assign router_24_27_req_in[3] = router_23_27_to_router_24_27_req; - assign router_24_27_req_in[4] = magia_tile_ni_24_27_to_router_24_27_req; - - assign router_24_27_to_router_24_28_rsp = router_24_27_rsp_out[0]; - assign router_24_27_to_router_25_27_rsp = router_24_27_rsp_out[1]; - assign router_24_27_to_router_24_26_rsp = router_24_27_rsp_out[2]; - assign router_24_27_to_router_23_27_rsp = router_24_27_rsp_out[3]; - assign router_24_27_to_magia_tile_ni_24_27_rsp = router_24_27_rsp_out[4]; - - assign router_24_27_to_router_24_28_req = router_24_27_req_out[0]; - assign router_24_27_to_router_25_27_req = router_24_27_req_out[1]; - assign router_24_27_to_router_24_26_req = router_24_27_req_out[2]; - assign router_24_27_to_router_23_27_req = router_24_27_req_out[3]; - assign router_24_27_to_magia_tile_ni_24_27_req = router_24_27_req_out[4]; - - assign router_24_27_rsp_in[0] = router_24_28_to_router_24_27_rsp; - assign router_24_27_rsp_in[1] = router_25_27_to_router_24_27_rsp; - assign router_24_27_rsp_in[2] = router_24_26_to_router_24_27_rsp; - assign router_24_27_rsp_in[3] = router_23_27_to_router_24_27_rsp; - assign router_24_27_rsp_in[4] = magia_tile_ni_24_27_to_router_24_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_27_req_in), - .floo_rsp_o (router_24_27_rsp_out), - .floo_req_o (router_24_27_req_out), - .floo_rsp_i (router_24_27_rsp_in) -); - - -floo_req_t [4:0] router_24_28_req_in; -floo_rsp_t [4:0] router_24_28_rsp_out; -floo_req_t [4:0] router_24_28_req_out; -floo_rsp_t [4:0] router_24_28_rsp_in; - - assign router_24_28_req_in[0] = router_24_29_to_router_24_28_req; - assign router_24_28_req_in[1] = router_25_28_to_router_24_28_req; - assign router_24_28_req_in[2] = router_24_27_to_router_24_28_req; - assign router_24_28_req_in[3] = router_23_28_to_router_24_28_req; - assign router_24_28_req_in[4] = magia_tile_ni_24_28_to_router_24_28_req; - - assign router_24_28_to_router_24_29_rsp = router_24_28_rsp_out[0]; - assign router_24_28_to_router_25_28_rsp = router_24_28_rsp_out[1]; - assign router_24_28_to_router_24_27_rsp = router_24_28_rsp_out[2]; - assign router_24_28_to_router_23_28_rsp = router_24_28_rsp_out[3]; - assign router_24_28_to_magia_tile_ni_24_28_rsp = router_24_28_rsp_out[4]; - - assign router_24_28_to_router_24_29_req = router_24_28_req_out[0]; - assign router_24_28_to_router_25_28_req = router_24_28_req_out[1]; - assign router_24_28_to_router_24_27_req = router_24_28_req_out[2]; - assign router_24_28_to_router_23_28_req = router_24_28_req_out[3]; - assign router_24_28_to_magia_tile_ni_24_28_req = router_24_28_req_out[4]; - - assign router_24_28_rsp_in[0] = router_24_29_to_router_24_28_rsp; - assign router_24_28_rsp_in[1] = router_25_28_to_router_24_28_rsp; - assign router_24_28_rsp_in[2] = router_24_27_to_router_24_28_rsp; - assign router_24_28_rsp_in[3] = router_23_28_to_router_24_28_rsp; - assign router_24_28_rsp_in[4] = magia_tile_ni_24_28_to_router_24_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_28_req_in), - .floo_rsp_o (router_24_28_rsp_out), - .floo_req_o (router_24_28_req_out), - .floo_rsp_i (router_24_28_rsp_in) -); - - -floo_req_t [4:0] router_24_29_req_in; -floo_rsp_t [4:0] router_24_29_rsp_out; -floo_req_t [4:0] router_24_29_req_out; -floo_rsp_t [4:0] router_24_29_rsp_in; - - assign router_24_29_req_in[0] = router_24_30_to_router_24_29_req; - assign router_24_29_req_in[1] = router_25_29_to_router_24_29_req; - assign router_24_29_req_in[2] = router_24_28_to_router_24_29_req; - assign router_24_29_req_in[3] = router_23_29_to_router_24_29_req; - assign router_24_29_req_in[4] = magia_tile_ni_24_29_to_router_24_29_req; - - assign router_24_29_to_router_24_30_rsp = router_24_29_rsp_out[0]; - assign router_24_29_to_router_25_29_rsp = router_24_29_rsp_out[1]; - assign router_24_29_to_router_24_28_rsp = router_24_29_rsp_out[2]; - assign router_24_29_to_router_23_29_rsp = router_24_29_rsp_out[3]; - assign router_24_29_to_magia_tile_ni_24_29_rsp = router_24_29_rsp_out[4]; - - assign router_24_29_to_router_24_30_req = router_24_29_req_out[0]; - assign router_24_29_to_router_25_29_req = router_24_29_req_out[1]; - assign router_24_29_to_router_24_28_req = router_24_29_req_out[2]; - assign router_24_29_to_router_23_29_req = router_24_29_req_out[3]; - assign router_24_29_to_magia_tile_ni_24_29_req = router_24_29_req_out[4]; - - assign router_24_29_rsp_in[0] = router_24_30_to_router_24_29_rsp; - assign router_24_29_rsp_in[1] = router_25_29_to_router_24_29_rsp; - assign router_24_29_rsp_in[2] = router_24_28_to_router_24_29_rsp; - assign router_24_29_rsp_in[3] = router_23_29_to_router_24_29_rsp; - assign router_24_29_rsp_in[4] = magia_tile_ni_24_29_to_router_24_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_29_req_in), - .floo_rsp_o (router_24_29_rsp_out), - .floo_req_o (router_24_29_req_out), - .floo_rsp_i (router_24_29_rsp_in) -); - - -floo_req_t [4:0] router_24_30_req_in; -floo_rsp_t [4:0] router_24_30_rsp_out; -floo_req_t [4:0] router_24_30_req_out; -floo_rsp_t [4:0] router_24_30_rsp_in; - - assign router_24_30_req_in[0] = router_24_31_to_router_24_30_req; - assign router_24_30_req_in[1] = router_25_30_to_router_24_30_req; - assign router_24_30_req_in[2] = router_24_29_to_router_24_30_req; - assign router_24_30_req_in[3] = router_23_30_to_router_24_30_req; - assign router_24_30_req_in[4] = magia_tile_ni_24_30_to_router_24_30_req; - - assign router_24_30_to_router_24_31_rsp = router_24_30_rsp_out[0]; - assign router_24_30_to_router_25_30_rsp = router_24_30_rsp_out[1]; - assign router_24_30_to_router_24_29_rsp = router_24_30_rsp_out[2]; - assign router_24_30_to_router_23_30_rsp = router_24_30_rsp_out[3]; - assign router_24_30_to_magia_tile_ni_24_30_rsp = router_24_30_rsp_out[4]; - - assign router_24_30_to_router_24_31_req = router_24_30_req_out[0]; - assign router_24_30_to_router_25_30_req = router_24_30_req_out[1]; - assign router_24_30_to_router_24_29_req = router_24_30_req_out[2]; - assign router_24_30_to_router_23_30_req = router_24_30_req_out[3]; - assign router_24_30_to_magia_tile_ni_24_30_req = router_24_30_req_out[4]; - - assign router_24_30_rsp_in[0] = router_24_31_to_router_24_30_rsp; - assign router_24_30_rsp_in[1] = router_25_30_to_router_24_30_rsp; - assign router_24_30_rsp_in[2] = router_24_29_to_router_24_30_rsp; - assign router_24_30_rsp_in[3] = router_23_30_to_router_24_30_rsp; - assign router_24_30_rsp_in[4] = magia_tile_ni_24_30_to_router_24_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_30_req_in), - .floo_rsp_o (router_24_30_rsp_out), - .floo_req_o (router_24_30_req_out), - .floo_rsp_i (router_24_30_rsp_in) -); - - -floo_req_t [4:0] router_24_31_req_in; -floo_rsp_t [4:0] router_24_31_rsp_out; -floo_req_t [4:0] router_24_31_req_out; -floo_rsp_t [4:0] router_24_31_rsp_in; - - assign router_24_31_req_in[0] = '0; - assign router_24_31_req_in[1] = router_25_31_to_router_24_31_req; - assign router_24_31_req_in[2] = router_24_30_to_router_24_31_req; - assign router_24_31_req_in[3] = router_23_31_to_router_24_31_req; - assign router_24_31_req_in[4] = magia_tile_ni_24_31_to_router_24_31_req; - - assign router_24_31_to_router_25_31_rsp = router_24_31_rsp_out[1]; - assign router_24_31_to_router_24_30_rsp = router_24_31_rsp_out[2]; - assign router_24_31_to_router_23_31_rsp = router_24_31_rsp_out[3]; - assign router_24_31_to_magia_tile_ni_24_31_rsp = router_24_31_rsp_out[4]; - - assign router_24_31_to_router_25_31_req = router_24_31_req_out[1]; - assign router_24_31_to_router_24_30_req = router_24_31_req_out[2]; - assign router_24_31_to_router_23_31_req = router_24_31_req_out[3]; - assign router_24_31_to_magia_tile_ni_24_31_req = router_24_31_req_out[4]; - - assign router_24_31_rsp_in[0] = '0; - assign router_24_31_rsp_in[1] = router_25_31_to_router_24_31_rsp; - assign router_24_31_rsp_in[2] = router_24_30_to_router_24_31_rsp; - assign router_24_31_rsp_in[3] = router_23_31_to_router_24_31_rsp; - assign router_24_31_rsp_in[4] = magia_tile_ni_24_31_to_router_24_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_24_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 25, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_24_31_req_in), - .floo_rsp_o (router_24_31_rsp_out), - .floo_req_o (router_24_31_req_out), - .floo_rsp_i (router_24_31_rsp_in) -); - - -floo_req_t [4:0] router_25_0_req_in; -floo_rsp_t [4:0] router_25_0_rsp_out; -floo_req_t [4:0] router_25_0_req_out; -floo_rsp_t [4:0] router_25_0_rsp_in; - - assign router_25_0_req_in[0] = router_25_1_to_router_25_0_req; - assign router_25_0_req_in[1] = router_26_0_to_router_25_0_req; - assign router_25_0_req_in[2] = '0; - assign router_25_0_req_in[3] = router_24_0_to_router_25_0_req; - assign router_25_0_req_in[4] = magia_tile_ni_25_0_to_router_25_0_req; - - assign router_25_0_to_router_25_1_rsp = router_25_0_rsp_out[0]; - assign router_25_0_to_router_26_0_rsp = router_25_0_rsp_out[1]; - assign router_25_0_to_router_24_0_rsp = router_25_0_rsp_out[3]; - assign router_25_0_to_magia_tile_ni_25_0_rsp = router_25_0_rsp_out[4]; - - assign router_25_0_to_router_25_1_req = router_25_0_req_out[0]; - assign router_25_0_to_router_26_0_req = router_25_0_req_out[1]; - assign router_25_0_to_router_24_0_req = router_25_0_req_out[3]; - assign router_25_0_to_magia_tile_ni_25_0_req = router_25_0_req_out[4]; - - assign router_25_0_rsp_in[0] = router_25_1_to_router_25_0_rsp; - assign router_25_0_rsp_in[1] = router_26_0_to_router_25_0_rsp; - assign router_25_0_rsp_in[2] = '0; - assign router_25_0_rsp_in[3] = router_24_0_to_router_25_0_rsp; - assign router_25_0_rsp_in[4] = magia_tile_ni_25_0_to_router_25_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_0_req_in), - .floo_rsp_o (router_25_0_rsp_out), - .floo_req_o (router_25_0_req_out), - .floo_rsp_i (router_25_0_rsp_in) -); - - -floo_req_t [4:0] router_25_1_req_in; -floo_rsp_t [4:0] router_25_1_rsp_out; -floo_req_t [4:0] router_25_1_req_out; -floo_rsp_t [4:0] router_25_1_rsp_in; - - assign router_25_1_req_in[0] = router_25_2_to_router_25_1_req; - assign router_25_1_req_in[1] = router_26_1_to_router_25_1_req; - assign router_25_1_req_in[2] = router_25_0_to_router_25_1_req; - assign router_25_1_req_in[3] = router_24_1_to_router_25_1_req; - assign router_25_1_req_in[4] = magia_tile_ni_25_1_to_router_25_1_req; - - assign router_25_1_to_router_25_2_rsp = router_25_1_rsp_out[0]; - assign router_25_1_to_router_26_1_rsp = router_25_1_rsp_out[1]; - assign router_25_1_to_router_25_0_rsp = router_25_1_rsp_out[2]; - assign router_25_1_to_router_24_1_rsp = router_25_1_rsp_out[3]; - assign router_25_1_to_magia_tile_ni_25_1_rsp = router_25_1_rsp_out[4]; - - assign router_25_1_to_router_25_2_req = router_25_1_req_out[0]; - assign router_25_1_to_router_26_1_req = router_25_1_req_out[1]; - assign router_25_1_to_router_25_0_req = router_25_1_req_out[2]; - assign router_25_1_to_router_24_1_req = router_25_1_req_out[3]; - assign router_25_1_to_magia_tile_ni_25_1_req = router_25_1_req_out[4]; - - assign router_25_1_rsp_in[0] = router_25_2_to_router_25_1_rsp; - assign router_25_1_rsp_in[1] = router_26_1_to_router_25_1_rsp; - assign router_25_1_rsp_in[2] = router_25_0_to_router_25_1_rsp; - assign router_25_1_rsp_in[3] = router_24_1_to_router_25_1_rsp; - assign router_25_1_rsp_in[4] = magia_tile_ni_25_1_to_router_25_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_1_req_in), - .floo_rsp_o (router_25_1_rsp_out), - .floo_req_o (router_25_1_req_out), - .floo_rsp_i (router_25_1_rsp_in) -); - - -floo_req_t [4:0] router_25_2_req_in; -floo_rsp_t [4:0] router_25_2_rsp_out; -floo_req_t [4:0] router_25_2_req_out; -floo_rsp_t [4:0] router_25_2_rsp_in; - - assign router_25_2_req_in[0] = router_25_3_to_router_25_2_req; - assign router_25_2_req_in[1] = router_26_2_to_router_25_2_req; - assign router_25_2_req_in[2] = router_25_1_to_router_25_2_req; - assign router_25_2_req_in[3] = router_24_2_to_router_25_2_req; - assign router_25_2_req_in[4] = magia_tile_ni_25_2_to_router_25_2_req; - - assign router_25_2_to_router_25_3_rsp = router_25_2_rsp_out[0]; - assign router_25_2_to_router_26_2_rsp = router_25_2_rsp_out[1]; - assign router_25_2_to_router_25_1_rsp = router_25_2_rsp_out[2]; - assign router_25_2_to_router_24_2_rsp = router_25_2_rsp_out[3]; - assign router_25_2_to_magia_tile_ni_25_2_rsp = router_25_2_rsp_out[4]; - - assign router_25_2_to_router_25_3_req = router_25_2_req_out[0]; - assign router_25_2_to_router_26_2_req = router_25_2_req_out[1]; - assign router_25_2_to_router_25_1_req = router_25_2_req_out[2]; - assign router_25_2_to_router_24_2_req = router_25_2_req_out[3]; - assign router_25_2_to_magia_tile_ni_25_2_req = router_25_2_req_out[4]; - - assign router_25_2_rsp_in[0] = router_25_3_to_router_25_2_rsp; - assign router_25_2_rsp_in[1] = router_26_2_to_router_25_2_rsp; - assign router_25_2_rsp_in[2] = router_25_1_to_router_25_2_rsp; - assign router_25_2_rsp_in[3] = router_24_2_to_router_25_2_rsp; - assign router_25_2_rsp_in[4] = magia_tile_ni_25_2_to_router_25_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_2_req_in), - .floo_rsp_o (router_25_2_rsp_out), - .floo_req_o (router_25_2_req_out), - .floo_rsp_i (router_25_2_rsp_in) -); - - -floo_req_t [4:0] router_25_3_req_in; -floo_rsp_t [4:0] router_25_3_rsp_out; -floo_req_t [4:0] router_25_3_req_out; -floo_rsp_t [4:0] router_25_3_rsp_in; - - assign router_25_3_req_in[0] = router_25_4_to_router_25_3_req; - assign router_25_3_req_in[1] = router_26_3_to_router_25_3_req; - assign router_25_3_req_in[2] = router_25_2_to_router_25_3_req; - assign router_25_3_req_in[3] = router_24_3_to_router_25_3_req; - assign router_25_3_req_in[4] = magia_tile_ni_25_3_to_router_25_3_req; - - assign router_25_3_to_router_25_4_rsp = router_25_3_rsp_out[0]; - assign router_25_3_to_router_26_3_rsp = router_25_3_rsp_out[1]; - assign router_25_3_to_router_25_2_rsp = router_25_3_rsp_out[2]; - assign router_25_3_to_router_24_3_rsp = router_25_3_rsp_out[3]; - assign router_25_3_to_magia_tile_ni_25_3_rsp = router_25_3_rsp_out[4]; - - assign router_25_3_to_router_25_4_req = router_25_3_req_out[0]; - assign router_25_3_to_router_26_3_req = router_25_3_req_out[1]; - assign router_25_3_to_router_25_2_req = router_25_3_req_out[2]; - assign router_25_3_to_router_24_3_req = router_25_3_req_out[3]; - assign router_25_3_to_magia_tile_ni_25_3_req = router_25_3_req_out[4]; - - assign router_25_3_rsp_in[0] = router_25_4_to_router_25_3_rsp; - assign router_25_3_rsp_in[1] = router_26_3_to_router_25_3_rsp; - assign router_25_3_rsp_in[2] = router_25_2_to_router_25_3_rsp; - assign router_25_3_rsp_in[3] = router_24_3_to_router_25_3_rsp; - assign router_25_3_rsp_in[4] = magia_tile_ni_25_3_to_router_25_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_3_req_in), - .floo_rsp_o (router_25_3_rsp_out), - .floo_req_o (router_25_3_req_out), - .floo_rsp_i (router_25_3_rsp_in) -); - - -floo_req_t [4:0] router_25_4_req_in; -floo_rsp_t [4:0] router_25_4_rsp_out; -floo_req_t [4:0] router_25_4_req_out; -floo_rsp_t [4:0] router_25_4_rsp_in; - - assign router_25_4_req_in[0] = router_25_5_to_router_25_4_req; - assign router_25_4_req_in[1] = router_26_4_to_router_25_4_req; - assign router_25_4_req_in[2] = router_25_3_to_router_25_4_req; - assign router_25_4_req_in[3] = router_24_4_to_router_25_4_req; - assign router_25_4_req_in[4] = magia_tile_ni_25_4_to_router_25_4_req; - - assign router_25_4_to_router_25_5_rsp = router_25_4_rsp_out[0]; - assign router_25_4_to_router_26_4_rsp = router_25_4_rsp_out[1]; - assign router_25_4_to_router_25_3_rsp = router_25_4_rsp_out[2]; - assign router_25_4_to_router_24_4_rsp = router_25_4_rsp_out[3]; - assign router_25_4_to_magia_tile_ni_25_4_rsp = router_25_4_rsp_out[4]; - - assign router_25_4_to_router_25_5_req = router_25_4_req_out[0]; - assign router_25_4_to_router_26_4_req = router_25_4_req_out[1]; - assign router_25_4_to_router_25_3_req = router_25_4_req_out[2]; - assign router_25_4_to_router_24_4_req = router_25_4_req_out[3]; - assign router_25_4_to_magia_tile_ni_25_4_req = router_25_4_req_out[4]; - - assign router_25_4_rsp_in[0] = router_25_5_to_router_25_4_rsp; - assign router_25_4_rsp_in[1] = router_26_4_to_router_25_4_rsp; - assign router_25_4_rsp_in[2] = router_25_3_to_router_25_4_rsp; - assign router_25_4_rsp_in[3] = router_24_4_to_router_25_4_rsp; - assign router_25_4_rsp_in[4] = magia_tile_ni_25_4_to_router_25_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_4_req_in), - .floo_rsp_o (router_25_4_rsp_out), - .floo_req_o (router_25_4_req_out), - .floo_rsp_i (router_25_4_rsp_in) -); - - -floo_req_t [4:0] router_25_5_req_in; -floo_rsp_t [4:0] router_25_5_rsp_out; -floo_req_t [4:0] router_25_5_req_out; -floo_rsp_t [4:0] router_25_5_rsp_in; - - assign router_25_5_req_in[0] = router_25_6_to_router_25_5_req; - assign router_25_5_req_in[1] = router_26_5_to_router_25_5_req; - assign router_25_5_req_in[2] = router_25_4_to_router_25_5_req; - assign router_25_5_req_in[3] = router_24_5_to_router_25_5_req; - assign router_25_5_req_in[4] = magia_tile_ni_25_5_to_router_25_5_req; - - assign router_25_5_to_router_25_6_rsp = router_25_5_rsp_out[0]; - assign router_25_5_to_router_26_5_rsp = router_25_5_rsp_out[1]; - assign router_25_5_to_router_25_4_rsp = router_25_5_rsp_out[2]; - assign router_25_5_to_router_24_5_rsp = router_25_5_rsp_out[3]; - assign router_25_5_to_magia_tile_ni_25_5_rsp = router_25_5_rsp_out[4]; - - assign router_25_5_to_router_25_6_req = router_25_5_req_out[0]; - assign router_25_5_to_router_26_5_req = router_25_5_req_out[1]; - assign router_25_5_to_router_25_4_req = router_25_5_req_out[2]; - assign router_25_5_to_router_24_5_req = router_25_5_req_out[3]; - assign router_25_5_to_magia_tile_ni_25_5_req = router_25_5_req_out[4]; - - assign router_25_5_rsp_in[0] = router_25_6_to_router_25_5_rsp; - assign router_25_5_rsp_in[1] = router_26_5_to_router_25_5_rsp; - assign router_25_5_rsp_in[2] = router_25_4_to_router_25_5_rsp; - assign router_25_5_rsp_in[3] = router_24_5_to_router_25_5_rsp; - assign router_25_5_rsp_in[4] = magia_tile_ni_25_5_to_router_25_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_5_req_in), - .floo_rsp_o (router_25_5_rsp_out), - .floo_req_o (router_25_5_req_out), - .floo_rsp_i (router_25_5_rsp_in) -); - - -floo_req_t [4:0] router_25_6_req_in; -floo_rsp_t [4:0] router_25_6_rsp_out; -floo_req_t [4:0] router_25_6_req_out; -floo_rsp_t [4:0] router_25_6_rsp_in; - - assign router_25_6_req_in[0] = router_25_7_to_router_25_6_req; - assign router_25_6_req_in[1] = router_26_6_to_router_25_6_req; - assign router_25_6_req_in[2] = router_25_5_to_router_25_6_req; - assign router_25_6_req_in[3] = router_24_6_to_router_25_6_req; - assign router_25_6_req_in[4] = magia_tile_ni_25_6_to_router_25_6_req; - - assign router_25_6_to_router_25_7_rsp = router_25_6_rsp_out[0]; - assign router_25_6_to_router_26_6_rsp = router_25_6_rsp_out[1]; - assign router_25_6_to_router_25_5_rsp = router_25_6_rsp_out[2]; - assign router_25_6_to_router_24_6_rsp = router_25_6_rsp_out[3]; - assign router_25_6_to_magia_tile_ni_25_6_rsp = router_25_6_rsp_out[4]; - - assign router_25_6_to_router_25_7_req = router_25_6_req_out[0]; - assign router_25_6_to_router_26_6_req = router_25_6_req_out[1]; - assign router_25_6_to_router_25_5_req = router_25_6_req_out[2]; - assign router_25_6_to_router_24_6_req = router_25_6_req_out[3]; - assign router_25_6_to_magia_tile_ni_25_6_req = router_25_6_req_out[4]; - - assign router_25_6_rsp_in[0] = router_25_7_to_router_25_6_rsp; - assign router_25_6_rsp_in[1] = router_26_6_to_router_25_6_rsp; - assign router_25_6_rsp_in[2] = router_25_5_to_router_25_6_rsp; - assign router_25_6_rsp_in[3] = router_24_6_to_router_25_6_rsp; - assign router_25_6_rsp_in[4] = magia_tile_ni_25_6_to_router_25_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_6_req_in), - .floo_rsp_o (router_25_6_rsp_out), - .floo_req_o (router_25_6_req_out), - .floo_rsp_i (router_25_6_rsp_in) -); - - -floo_req_t [4:0] router_25_7_req_in; -floo_rsp_t [4:0] router_25_7_rsp_out; -floo_req_t [4:0] router_25_7_req_out; -floo_rsp_t [4:0] router_25_7_rsp_in; - - assign router_25_7_req_in[0] = router_25_8_to_router_25_7_req; - assign router_25_7_req_in[1] = router_26_7_to_router_25_7_req; - assign router_25_7_req_in[2] = router_25_6_to_router_25_7_req; - assign router_25_7_req_in[3] = router_24_7_to_router_25_7_req; - assign router_25_7_req_in[4] = magia_tile_ni_25_7_to_router_25_7_req; - - assign router_25_7_to_router_25_8_rsp = router_25_7_rsp_out[0]; - assign router_25_7_to_router_26_7_rsp = router_25_7_rsp_out[1]; - assign router_25_7_to_router_25_6_rsp = router_25_7_rsp_out[2]; - assign router_25_7_to_router_24_7_rsp = router_25_7_rsp_out[3]; - assign router_25_7_to_magia_tile_ni_25_7_rsp = router_25_7_rsp_out[4]; - - assign router_25_7_to_router_25_8_req = router_25_7_req_out[0]; - assign router_25_7_to_router_26_7_req = router_25_7_req_out[1]; - assign router_25_7_to_router_25_6_req = router_25_7_req_out[2]; - assign router_25_7_to_router_24_7_req = router_25_7_req_out[3]; - assign router_25_7_to_magia_tile_ni_25_7_req = router_25_7_req_out[4]; - - assign router_25_7_rsp_in[0] = router_25_8_to_router_25_7_rsp; - assign router_25_7_rsp_in[1] = router_26_7_to_router_25_7_rsp; - assign router_25_7_rsp_in[2] = router_25_6_to_router_25_7_rsp; - assign router_25_7_rsp_in[3] = router_24_7_to_router_25_7_rsp; - assign router_25_7_rsp_in[4] = magia_tile_ni_25_7_to_router_25_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_7_req_in), - .floo_rsp_o (router_25_7_rsp_out), - .floo_req_o (router_25_7_req_out), - .floo_rsp_i (router_25_7_rsp_in) -); - - -floo_req_t [4:0] router_25_8_req_in; -floo_rsp_t [4:0] router_25_8_rsp_out; -floo_req_t [4:0] router_25_8_req_out; -floo_rsp_t [4:0] router_25_8_rsp_in; - - assign router_25_8_req_in[0] = router_25_9_to_router_25_8_req; - assign router_25_8_req_in[1] = router_26_8_to_router_25_8_req; - assign router_25_8_req_in[2] = router_25_7_to_router_25_8_req; - assign router_25_8_req_in[3] = router_24_8_to_router_25_8_req; - assign router_25_8_req_in[4] = magia_tile_ni_25_8_to_router_25_8_req; - - assign router_25_8_to_router_25_9_rsp = router_25_8_rsp_out[0]; - assign router_25_8_to_router_26_8_rsp = router_25_8_rsp_out[1]; - assign router_25_8_to_router_25_7_rsp = router_25_8_rsp_out[2]; - assign router_25_8_to_router_24_8_rsp = router_25_8_rsp_out[3]; - assign router_25_8_to_magia_tile_ni_25_8_rsp = router_25_8_rsp_out[4]; - - assign router_25_8_to_router_25_9_req = router_25_8_req_out[0]; - assign router_25_8_to_router_26_8_req = router_25_8_req_out[1]; - assign router_25_8_to_router_25_7_req = router_25_8_req_out[2]; - assign router_25_8_to_router_24_8_req = router_25_8_req_out[3]; - assign router_25_8_to_magia_tile_ni_25_8_req = router_25_8_req_out[4]; - - assign router_25_8_rsp_in[0] = router_25_9_to_router_25_8_rsp; - assign router_25_8_rsp_in[1] = router_26_8_to_router_25_8_rsp; - assign router_25_8_rsp_in[2] = router_25_7_to_router_25_8_rsp; - assign router_25_8_rsp_in[3] = router_24_8_to_router_25_8_rsp; - assign router_25_8_rsp_in[4] = magia_tile_ni_25_8_to_router_25_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_8_req_in), - .floo_rsp_o (router_25_8_rsp_out), - .floo_req_o (router_25_8_req_out), - .floo_rsp_i (router_25_8_rsp_in) -); - - -floo_req_t [4:0] router_25_9_req_in; -floo_rsp_t [4:0] router_25_9_rsp_out; -floo_req_t [4:0] router_25_9_req_out; -floo_rsp_t [4:0] router_25_9_rsp_in; - - assign router_25_9_req_in[0] = router_25_10_to_router_25_9_req; - assign router_25_9_req_in[1] = router_26_9_to_router_25_9_req; - assign router_25_9_req_in[2] = router_25_8_to_router_25_9_req; - assign router_25_9_req_in[3] = router_24_9_to_router_25_9_req; - assign router_25_9_req_in[4] = magia_tile_ni_25_9_to_router_25_9_req; - - assign router_25_9_to_router_25_10_rsp = router_25_9_rsp_out[0]; - assign router_25_9_to_router_26_9_rsp = router_25_9_rsp_out[1]; - assign router_25_9_to_router_25_8_rsp = router_25_9_rsp_out[2]; - assign router_25_9_to_router_24_9_rsp = router_25_9_rsp_out[3]; - assign router_25_9_to_magia_tile_ni_25_9_rsp = router_25_9_rsp_out[4]; - - assign router_25_9_to_router_25_10_req = router_25_9_req_out[0]; - assign router_25_9_to_router_26_9_req = router_25_9_req_out[1]; - assign router_25_9_to_router_25_8_req = router_25_9_req_out[2]; - assign router_25_9_to_router_24_9_req = router_25_9_req_out[3]; - assign router_25_9_to_magia_tile_ni_25_9_req = router_25_9_req_out[4]; - - assign router_25_9_rsp_in[0] = router_25_10_to_router_25_9_rsp; - assign router_25_9_rsp_in[1] = router_26_9_to_router_25_9_rsp; - assign router_25_9_rsp_in[2] = router_25_8_to_router_25_9_rsp; - assign router_25_9_rsp_in[3] = router_24_9_to_router_25_9_rsp; - assign router_25_9_rsp_in[4] = magia_tile_ni_25_9_to_router_25_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_9_req_in), - .floo_rsp_o (router_25_9_rsp_out), - .floo_req_o (router_25_9_req_out), - .floo_rsp_i (router_25_9_rsp_in) -); - - -floo_req_t [4:0] router_25_10_req_in; -floo_rsp_t [4:0] router_25_10_rsp_out; -floo_req_t [4:0] router_25_10_req_out; -floo_rsp_t [4:0] router_25_10_rsp_in; - - assign router_25_10_req_in[0] = router_25_11_to_router_25_10_req; - assign router_25_10_req_in[1] = router_26_10_to_router_25_10_req; - assign router_25_10_req_in[2] = router_25_9_to_router_25_10_req; - assign router_25_10_req_in[3] = router_24_10_to_router_25_10_req; - assign router_25_10_req_in[4] = magia_tile_ni_25_10_to_router_25_10_req; - - assign router_25_10_to_router_25_11_rsp = router_25_10_rsp_out[0]; - assign router_25_10_to_router_26_10_rsp = router_25_10_rsp_out[1]; - assign router_25_10_to_router_25_9_rsp = router_25_10_rsp_out[2]; - assign router_25_10_to_router_24_10_rsp = router_25_10_rsp_out[3]; - assign router_25_10_to_magia_tile_ni_25_10_rsp = router_25_10_rsp_out[4]; - - assign router_25_10_to_router_25_11_req = router_25_10_req_out[0]; - assign router_25_10_to_router_26_10_req = router_25_10_req_out[1]; - assign router_25_10_to_router_25_9_req = router_25_10_req_out[2]; - assign router_25_10_to_router_24_10_req = router_25_10_req_out[3]; - assign router_25_10_to_magia_tile_ni_25_10_req = router_25_10_req_out[4]; - - assign router_25_10_rsp_in[0] = router_25_11_to_router_25_10_rsp; - assign router_25_10_rsp_in[1] = router_26_10_to_router_25_10_rsp; - assign router_25_10_rsp_in[2] = router_25_9_to_router_25_10_rsp; - assign router_25_10_rsp_in[3] = router_24_10_to_router_25_10_rsp; - assign router_25_10_rsp_in[4] = magia_tile_ni_25_10_to_router_25_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_10_req_in), - .floo_rsp_o (router_25_10_rsp_out), - .floo_req_o (router_25_10_req_out), - .floo_rsp_i (router_25_10_rsp_in) -); - - -floo_req_t [4:0] router_25_11_req_in; -floo_rsp_t [4:0] router_25_11_rsp_out; -floo_req_t [4:0] router_25_11_req_out; -floo_rsp_t [4:0] router_25_11_rsp_in; - - assign router_25_11_req_in[0] = router_25_12_to_router_25_11_req; - assign router_25_11_req_in[1] = router_26_11_to_router_25_11_req; - assign router_25_11_req_in[2] = router_25_10_to_router_25_11_req; - assign router_25_11_req_in[3] = router_24_11_to_router_25_11_req; - assign router_25_11_req_in[4] = magia_tile_ni_25_11_to_router_25_11_req; - - assign router_25_11_to_router_25_12_rsp = router_25_11_rsp_out[0]; - assign router_25_11_to_router_26_11_rsp = router_25_11_rsp_out[1]; - assign router_25_11_to_router_25_10_rsp = router_25_11_rsp_out[2]; - assign router_25_11_to_router_24_11_rsp = router_25_11_rsp_out[3]; - assign router_25_11_to_magia_tile_ni_25_11_rsp = router_25_11_rsp_out[4]; - - assign router_25_11_to_router_25_12_req = router_25_11_req_out[0]; - assign router_25_11_to_router_26_11_req = router_25_11_req_out[1]; - assign router_25_11_to_router_25_10_req = router_25_11_req_out[2]; - assign router_25_11_to_router_24_11_req = router_25_11_req_out[3]; - assign router_25_11_to_magia_tile_ni_25_11_req = router_25_11_req_out[4]; - - assign router_25_11_rsp_in[0] = router_25_12_to_router_25_11_rsp; - assign router_25_11_rsp_in[1] = router_26_11_to_router_25_11_rsp; - assign router_25_11_rsp_in[2] = router_25_10_to_router_25_11_rsp; - assign router_25_11_rsp_in[3] = router_24_11_to_router_25_11_rsp; - assign router_25_11_rsp_in[4] = magia_tile_ni_25_11_to_router_25_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_11_req_in), - .floo_rsp_o (router_25_11_rsp_out), - .floo_req_o (router_25_11_req_out), - .floo_rsp_i (router_25_11_rsp_in) -); - - -floo_req_t [4:0] router_25_12_req_in; -floo_rsp_t [4:0] router_25_12_rsp_out; -floo_req_t [4:0] router_25_12_req_out; -floo_rsp_t [4:0] router_25_12_rsp_in; - - assign router_25_12_req_in[0] = router_25_13_to_router_25_12_req; - assign router_25_12_req_in[1] = router_26_12_to_router_25_12_req; - assign router_25_12_req_in[2] = router_25_11_to_router_25_12_req; - assign router_25_12_req_in[3] = router_24_12_to_router_25_12_req; - assign router_25_12_req_in[4] = magia_tile_ni_25_12_to_router_25_12_req; - - assign router_25_12_to_router_25_13_rsp = router_25_12_rsp_out[0]; - assign router_25_12_to_router_26_12_rsp = router_25_12_rsp_out[1]; - assign router_25_12_to_router_25_11_rsp = router_25_12_rsp_out[2]; - assign router_25_12_to_router_24_12_rsp = router_25_12_rsp_out[3]; - assign router_25_12_to_magia_tile_ni_25_12_rsp = router_25_12_rsp_out[4]; - - assign router_25_12_to_router_25_13_req = router_25_12_req_out[0]; - assign router_25_12_to_router_26_12_req = router_25_12_req_out[1]; - assign router_25_12_to_router_25_11_req = router_25_12_req_out[2]; - assign router_25_12_to_router_24_12_req = router_25_12_req_out[3]; - assign router_25_12_to_magia_tile_ni_25_12_req = router_25_12_req_out[4]; - - assign router_25_12_rsp_in[0] = router_25_13_to_router_25_12_rsp; - assign router_25_12_rsp_in[1] = router_26_12_to_router_25_12_rsp; - assign router_25_12_rsp_in[2] = router_25_11_to_router_25_12_rsp; - assign router_25_12_rsp_in[3] = router_24_12_to_router_25_12_rsp; - assign router_25_12_rsp_in[4] = magia_tile_ni_25_12_to_router_25_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_12_req_in), - .floo_rsp_o (router_25_12_rsp_out), - .floo_req_o (router_25_12_req_out), - .floo_rsp_i (router_25_12_rsp_in) -); - - -floo_req_t [4:0] router_25_13_req_in; -floo_rsp_t [4:0] router_25_13_rsp_out; -floo_req_t [4:0] router_25_13_req_out; -floo_rsp_t [4:0] router_25_13_rsp_in; - - assign router_25_13_req_in[0] = router_25_14_to_router_25_13_req; - assign router_25_13_req_in[1] = router_26_13_to_router_25_13_req; - assign router_25_13_req_in[2] = router_25_12_to_router_25_13_req; - assign router_25_13_req_in[3] = router_24_13_to_router_25_13_req; - assign router_25_13_req_in[4] = magia_tile_ni_25_13_to_router_25_13_req; - - assign router_25_13_to_router_25_14_rsp = router_25_13_rsp_out[0]; - assign router_25_13_to_router_26_13_rsp = router_25_13_rsp_out[1]; - assign router_25_13_to_router_25_12_rsp = router_25_13_rsp_out[2]; - assign router_25_13_to_router_24_13_rsp = router_25_13_rsp_out[3]; - assign router_25_13_to_magia_tile_ni_25_13_rsp = router_25_13_rsp_out[4]; - - assign router_25_13_to_router_25_14_req = router_25_13_req_out[0]; - assign router_25_13_to_router_26_13_req = router_25_13_req_out[1]; - assign router_25_13_to_router_25_12_req = router_25_13_req_out[2]; - assign router_25_13_to_router_24_13_req = router_25_13_req_out[3]; - assign router_25_13_to_magia_tile_ni_25_13_req = router_25_13_req_out[4]; - - assign router_25_13_rsp_in[0] = router_25_14_to_router_25_13_rsp; - assign router_25_13_rsp_in[1] = router_26_13_to_router_25_13_rsp; - assign router_25_13_rsp_in[2] = router_25_12_to_router_25_13_rsp; - assign router_25_13_rsp_in[3] = router_24_13_to_router_25_13_rsp; - assign router_25_13_rsp_in[4] = magia_tile_ni_25_13_to_router_25_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_13_req_in), - .floo_rsp_o (router_25_13_rsp_out), - .floo_req_o (router_25_13_req_out), - .floo_rsp_i (router_25_13_rsp_in) -); - - -floo_req_t [4:0] router_25_14_req_in; -floo_rsp_t [4:0] router_25_14_rsp_out; -floo_req_t [4:0] router_25_14_req_out; -floo_rsp_t [4:0] router_25_14_rsp_in; - - assign router_25_14_req_in[0] = router_25_15_to_router_25_14_req; - assign router_25_14_req_in[1] = router_26_14_to_router_25_14_req; - assign router_25_14_req_in[2] = router_25_13_to_router_25_14_req; - assign router_25_14_req_in[3] = router_24_14_to_router_25_14_req; - assign router_25_14_req_in[4] = magia_tile_ni_25_14_to_router_25_14_req; - - assign router_25_14_to_router_25_15_rsp = router_25_14_rsp_out[0]; - assign router_25_14_to_router_26_14_rsp = router_25_14_rsp_out[1]; - assign router_25_14_to_router_25_13_rsp = router_25_14_rsp_out[2]; - assign router_25_14_to_router_24_14_rsp = router_25_14_rsp_out[3]; - assign router_25_14_to_magia_tile_ni_25_14_rsp = router_25_14_rsp_out[4]; - - assign router_25_14_to_router_25_15_req = router_25_14_req_out[0]; - assign router_25_14_to_router_26_14_req = router_25_14_req_out[1]; - assign router_25_14_to_router_25_13_req = router_25_14_req_out[2]; - assign router_25_14_to_router_24_14_req = router_25_14_req_out[3]; - assign router_25_14_to_magia_tile_ni_25_14_req = router_25_14_req_out[4]; - - assign router_25_14_rsp_in[0] = router_25_15_to_router_25_14_rsp; - assign router_25_14_rsp_in[1] = router_26_14_to_router_25_14_rsp; - assign router_25_14_rsp_in[2] = router_25_13_to_router_25_14_rsp; - assign router_25_14_rsp_in[3] = router_24_14_to_router_25_14_rsp; - assign router_25_14_rsp_in[4] = magia_tile_ni_25_14_to_router_25_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_14_req_in), - .floo_rsp_o (router_25_14_rsp_out), - .floo_req_o (router_25_14_req_out), - .floo_rsp_i (router_25_14_rsp_in) -); - - -floo_req_t [4:0] router_25_15_req_in; -floo_rsp_t [4:0] router_25_15_rsp_out; -floo_req_t [4:0] router_25_15_req_out; -floo_rsp_t [4:0] router_25_15_rsp_in; - - assign router_25_15_req_in[0] = router_25_16_to_router_25_15_req; - assign router_25_15_req_in[1] = router_26_15_to_router_25_15_req; - assign router_25_15_req_in[2] = router_25_14_to_router_25_15_req; - assign router_25_15_req_in[3] = router_24_15_to_router_25_15_req; - assign router_25_15_req_in[4] = magia_tile_ni_25_15_to_router_25_15_req; - - assign router_25_15_to_router_25_16_rsp = router_25_15_rsp_out[0]; - assign router_25_15_to_router_26_15_rsp = router_25_15_rsp_out[1]; - assign router_25_15_to_router_25_14_rsp = router_25_15_rsp_out[2]; - assign router_25_15_to_router_24_15_rsp = router_25_15_rsp_out[3]; - assign router_25_15_to_magia_tile_ni_25_15_rsp = router_25_15_rsp_out[4]; - - assign router_25_15_to_router_25_16_req = router_25_15_req_out[0]; - assign router_25_15_to_router_26_15_req = router_25_15_req_out[1]; - assign router_25_15_to_router_25_14_req = router_25_15_req_out[2]; - assign router_25_15_to_router_24_15_req = router_25_15_req_out[3]; - assign router_25_15_to_magia_tile_ni_25_15_req = router_25_15_req_out[4]; - - assign router_25_15_rsp_in[0] = router_25_16_to_router_25_15_rsp; - assign router_25_15_rsp_in[1] = router_26_15_to_router_25_15_rsp; - assign router_25_15_rsp_in[2] = router_25_14_to_router_25_15_rsp; - assign router_25_15_rsp_in[3] = router_24_15_to_router_25_15_rsp; - assign router_25_15_rsp_in[4] = magia_tile_ni_25_15_to_router_25_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_15_req_in), - .floo_rsp_o (router_25_15_rsp_out), - .floo_req_o (router_25_15_req_out), - .floo_rsp_i (router_25_15_rsp_in) -); - - -floo_req_t [4:0] router_25_16_req_in; -floo_rsp_t [4:0] router_25_16_rsp_out; -floo_req_t [4:0] router_25_16_req_out; -floo_rsp_t [4:0] router_25_16_rsp_in; - - assign router_25_16_req_in[0] = router_25_17_to_router_25_16_req; - assign router_25_16_req_in[1] = router_26_16_to_router_25_16_req; - assign router_25_16_req_in[2] = router_25_15_to_router_25_16_req; - assign router_25_16_req_in[3] = router_24_16_to_router_25_16_req; - assign router_25_16_req_in[4] = magia_tile_ni_25_16_to_router_25_16_req; - - assign router_25_16_to_router_25_17_rsp = router_25_16_rsp_out[0]; - assign router_25_16_to_router_26_16_rsp = router_25_16_rsp_out[1]; - assign router_25_16_to_router_25_15_rsp = router_25_16_rsp_out[2]; - assign router_25_16_to_router_24_16_rsp = router_25_16_rsp_out[3]; - assign router_25_16_to_magia_tile_ni_25_16_rsp = router_25_16_rsp_out[4]; - - assign router_25_16_to_router_25_17_req = router_25_16_req_out[0]; - assign router_25_16_to_router_26_16_req = router_25_16_req_out[1]; - assign router_25_16_to_router_25_15_req = router_25_16_req_out[2]; - assign router_25_16_to_router_24_16_req = router_25_16_req_out[3]; - assign router_25_16_to_magia_tile_ni_25_16_req = router_25_16_req_out[4]; - - assign router_25_16_rsp_in[0] = router_25_17_to_router_25_16_rsp; - assign router_25_16_rsp_in[1] = router_26_16_to_router_25_16_rsp; - assign router_25_16_rsp_in[2] = router_25_15_to_router_25_16_rsp; - assign router_25_16_rsp_in[3] = router_24_16_to_router_25_16_rsp; - assign router_25_16_rsp_in[4] = magia_tile_ni_25_16_to_router_25_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_16_req_in), - .floo_rsp_o (router_25_16_rsp_out), - .floo_req_o (router_25_16_req_out), - .floo_rsp_i (router_25_16_rsp_in) -); - - -floo_req_t [4:0] router_25_17_req_in; -floo_rsp_t [4:0] router_25_17_rsp_out; -floo_req_t [4:0] router_25_17_req_out; -floo_rsp_t [4:0] router_25_17_rsp_in; - - assign router_25_17_req_in[0] = router_25_18_to_router_25_17_req; - assign router_25_17_req_in[1] = router_26_17_to_router_25_17_req; - assign router_25_17_req_in[2] = router_25_16_to_router_25_17_req; - assign router_25_17_req_in[3] = router_24_17_to_router_25_17_req; - assign router_25_17_req_in[4] = magia_tile_ni_25_17_to_router_25_17_req; - - assign router_25_17_to_router_25_18_rsp = router_25_17_rsp_out[0]; - assign router_25_17_to_router_26_17_rsp = router_25_17_rsp_out[1]; - assign router_25_17_to_router_25_16_rsp = router_25_17_rsp_out[2]; - assign router_25_17_to_router_24_17_rsp = router_25_17_rsp_out[3]; - assign router_25_17_to_magia_tile_ni_25_17_rsp = router_25_17_rsp_out[4]; - - assign router_25_17_to_router_25_18_req = router_25_17_req_out[0]; - assign router_25_17_to_router_26_17_req = router_25_17_req_out[1]; - assign router_25_17_to_router_25_16_req = router_25_17_req_out[2]; - assign router_25_17_to_router_24_17_req = router_25_17_req_out[3]; - assign router_25_17_to_magia_tile_ni_25_17_req = router_25_17_req_out[4]; - - assign router_25_17_rsp_in[0] = router_25_18_to_router_25_17_rsp; - assign router_25_17_rsp_in[1] = router_26_17_to_router_25_17_rsp; - assign router_25_17_rsp_in[2] = router_25_16_to_router_25_17_rsp; - assign router_25_17_rsp_in[3] = router_24_17_to_router_25_17_rsp; - assign router_25_17_rsp_in[4] = magia_tile_ni_25_17_to_router_25_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_17_req_in), - .floo_rsp_o (router_25_17_rsp_out), - .floo_req_o (router_25_17_req_out), - .floo_rsp_i (router_25_17_rsp_in) -); - - -floo_req_t [4:0] router_25_18_req_in; -floo_rsp_t [4:0] router_25_18_rsp_out; -floo_req_t [4:0] router_25_18_req_out; -floo_rsp_t [4:0] router_25_18_rsp_in; - - assign router_25_18_req_in[0] = router_25_19_to_router_25_18_req; - assign router_25_18_req_in[1] = router_26_18_to_router_25_18_req; - assign router_25_18_req_in[2] = router_25_17_to_router_25_18_req; - assign router_25_18_req_in[3] = router_24_18_to_router_25_18_req; - assign router_25_18_req_in[4] = magia_tile_ni_25_18_to_router_25_18_req; - - assign router_25_18_to_router_25_19_rsp = router_25_18_rsp_out[0]; - assign router_25_18_to_router_26_18_rsp = router_25_18_rsp_out[1]; - assign router_25_18_to_router_25_17_rsp = router_25_18_rsp_out[2]; - assign router_25_18_to_router_24_18_rsp = router_25_18_rsp_out[3]; - assign router_25_18_to_magia_tile_ni_25_18_rsp = router_25_18_rsp_out[4]; - - assign router_25_18_to_router_25_19_req = router_25_18_req_out[0]; - assign router_25_18_to_router_26_18_req = router_25_18_req_out[1]; - assign router_25_18_to_router_25_17_req = router_25_18_req_out[2]; - assign router_25_18_to_router_24_18_req = router_25_18_req_out[3]; - assign router_25_18_to_magia_tile_ni_25_18_req = router_25_18_req_out[4]; - - assign router_25_18_rsp_in[0] = router_25_19_to_router_25_18_rsp; - assign router_25_18_rsp_in[1] = router_26_18_to_router_25_18_rsp; - assign router_25_18_rsp_in[2] = router_25_17_to_router_25_18_rsp; - assign router_25_18_rsp_in[3] = router_24_18_to_router_25_18_rsp; - assign router_25_18_rsp_in[4] = magia_tile_ni_25_18_to_router_25_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_18_req_in), - .floo_rsp_o (router_25_18_rsp_out), - .floo_req_o (router_25_18_req_out), - .floo_rsp_i (router_25_18_rsp_in) -); - - -floo_req_t [4:0] router_25_19_req_in; -floo_rsp_t [4:0] router_25_19_rsp_out; -floo_req_t [4:0] router_25_19_req_out; -floo_rsp_t [4:0] router_25_19_rsp_in; - - assign router_25_19_req_in[0] = router_25_20_to_router_25_19_req; - assign router_25_19_req_in[1] = router_26_19_to_router_25_19_req; - assign router_25_19_req_in[2] = router_25_18_to_router_25_19_req; - assign router_25_19_req_in[3] = router_24_19_to_router_25_19_req; - assign router_25_19_req_in[4] = magia_tile_ni_25_19_to_router_25_19_req; - - assign router_25_19_to_router_25_20_rsp = router_25_19_rsp_out[0]; - assign router_25_19_to_router_26_19_rsp = router_25_19_rsp_out[1]; - assign router_25_19_to_router_25_18_rsp = router_25_19_rsp_out[2]; - assign router_25_19_to_router_24_19_rsp = router_25_19_rsp_out[3]; - assign router_25_19_to_magia_tile_ni_25_19_rsp = router_25_19_rsp_out[4]; - - assign router_25_19_to_router_25_20_req = router_25_19_req_out[0]; - assign router_25_19_to_router_26_19_req = router_25_19_req_out[1]; - assign router_25_19_to_router_25_18_req = router_25_19_req_out[2]; - assign router_25_19_to_router_24_19_req = router_25_19_req_out[3]; - assign router_25_19_to_magia_tile_ni_25_19_req = router_25_19_req_out[4]; - - assign router_25_19_rsp_in[0] = router_25_20_to_router_25_19_rsp; - assign router_25_19_rsp_in[1] = router_26_19_to_router_25_19_rsp; - assign router_25_19_rsp_in[2] = router_25_18_to_router_25_19_rsp; - assign router_25_19_rsp_in[3] = router_24_19_to_router_25_19_rsp; - assign router_25_19_rsp_in[4] = magia_tile_ni_25_19_to_router_25_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_19_req_in), - .floo_rsp_o (router_25_19_rsp_out), - .floo_req_o (router_25_19_req_out), - .floo_rsp_i (router_25_19_rsp_in) -); - - -floo_req_t [4:0] router_25_20_req_in; -floo_rsp_t [4:0] router_25_20_rsp_out; -floo_req_t [4:0] router_25_20_req_out; -floo_rsp_t [4:0] router_25_20_rsp_in; - - assign router_25_20_req_in[0] = router_25_21_to_router_25_20_req; - assign router_25_20_req_in[1] = router_26_20_to_router_25_20_req; - assign router_25_20_req_in[2] = router_25_19_to_router_25_20_req; - assign router_25_20_req_in[3] = router_24_20_to_router_25_20_req; - assign router_25_20_req_in[4] = magia_tile_ni_25_20_to_router_25_20_req; - - assign router_25_20_to_router_25_21_rsp = router_25_20_rsp_out[0]; - assign router_25_20_to_router_26_20_rsp = router_25_20_rsp_out[1]; - assign router_25_20_to_router_25_19_rsp = router_25_20_rsp_out[2]; - assign router_25_20_to_router_24_20_rsp = router_25_20_rsp_out[3]; - assign router_25_20_to_magia_tile_ni_25_20_rsp = router_25_20_rsp_out[4]; - - assign router_25_20_to_router_25_21_req = router_25_20_req_out[0]; - assign router_25_20_to_router_26_20_req = router_25_20_req_out[1]; - assign router_25_20_to_router_25_19_req = router_25_20_req_out[2]; - assign router_25_20_to_router_24_20_req = router_25_20_req_out[3]; - assign router_25_20_to_magia_tile_ni_25_20_req = router_25_20_req_out[4]; - - assign router_25_20_rsp_in[0] = router_25_21_to_router_25_20_rsp; - assign router_25_20_rsp_in[1] = router_26_20_to_router_25_20_rsp; - assign router_25_20_rsp_in[2] = router_25_19_to_router_25_20_rsp; - assign router_25_20_rsp_in[3] = router_24_20_to_router_25_20_rsp; - assign router_25_20_rsp_in[4] = magia_tile_ni_25_20_to_router_25_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_20_req_in), - .floo_rsp_o (router_25_20_rsp_out), - .floo_req_o (router_25_20_req_out), - .floo_rsp_i (router_25_20_rsp_in) -); - - -floo_req_t [4:0] router_25_21_req_in; -floo_rsp_t [4:0] router_25_21_rsp_out; -floo_req_t [4:0] router_25_21_req_out; -floo_rsp_t [4:0] router_25_21_rsp_in; - - assign router_25_21_req_in[0] = router_25_22_to_router_25_21_req; - assign router_25_21_req_in[1] = router_26_21_to_router_25_21_req; - assign router_25_21_req_in[2] = router_25_20_to_router_25_21_req; - assign router_25_21_req_in[3] = router_24_21_to_router_25_21_req; - assign router_25_21_req_in[4] = magia_tile_ni_25_21_to_router_25_21_req; - - assign router_25_21_to_router_25_22_rsp = router_25_21_rsp_out[0]; - assign router_25_21_to_router_26_21_rsp = router_25_21_rsp_out[1]; - assign router_25_21_to_router_25_20_rsp = router_25_21_rsp_out[2]; - assign router_25_21_to_router_24_21_rsp = router_25_21_rsp_out[3]; - assign router_25_21_to_magia_tile_ni_25_21_rsp = router_25_21_rsp_out[4]; - - assign router_25_21_to_router_25_22_req = router_25_21_req_out[0]; - assign router_25_21_to_router_26_21_req = router_25_21_req_out[1]; - assign router_25_21_to_router_25_20_req = router_25_21_req_out[2]; - assign router_25_21_to_router_24_21_req = router_25_21_req_out[3]; - assign router_25_21_to_magia_tile_ni_25_21_req = router_25_21_req_out[4]; - - assign router_25_21_rsp_in[0] = router_25_22_to_router_25_21_rsp; - assign router_25_21_rsp_in[1] = router_26_21_to_router_25_21_rsp; - assign router_25_21_rsp_in[2] = router_25_20_to_router_25_21_rsp; - assign router_25_21_rsp_in[3] = router_24_21_to_router_25_21_rsp; - assign router_25_21_rsp_in[4] = magia_tile_ni_25_21_to_router_25_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_21_req_in), - .floo_rsp_o (router_25_21_rsp_out), - .floo_req_o (router_25_21_req_out), - .floo_rsp_i (router_25_21_rsp_in) -); - - -floo_req_t [4:0] router_25_22_req_in; -floo_rsp_t [4:0] router_25_22_rsp_out; -floo_req_t [4:0] router_25_22_req_out; -floo_rsp_t [4:0] router_25_22_rsp_in; - - assign router_25_22_req_in[0] = router_25_23_to_router_25_22_req; - assign router_25_22_req_in[1] = router_26_22_to_router_25_22_req; - assign router_25_22_req_in[2] = router_25_21_to_router_25_22_req; - assign router_25_22_req_in[3] = router_24_22_to_router_25_22_req; - assign router_25_22_req_in[4] = magia_tile_ni_25_22_to_router_25_22_req; - - assign router_25_22_to_router_25_23_rsp = router_25_22_rsp_out[0]; - assign router_25_22_to_router_26_22_rsp = router_25_22_rsp_out[1]; - assign router_25_22_to_router_25_21_rsp = router_25_22_rsp_out[2]; - assign router_25_22_to_router_24_22_rsp = router_25_22_rsp_out[3]; - assign router_25_22_to_magia_tile_ni_25_22_rsp = router_25_22_rsp_out[4]; - - assign router_25_22_to_router_25_23_req = router_25_22_req_out[0]; - assign router_25_22_to_router_26_22_req = router_25_22_req_out[1]; - assign router_25_22_to_router_25_21_req = router_25_22_req_out[2]; - assign router_25_22_to_router_24_22_req = router_25_22_req_out[3]; - assign router_25_22_to_magia_tile_ni_25_22_req = router_25_22_req_out[4]; - - assign router_25_22_rsp_in[0] = router_25_23_to_router_25_22_rsp; - assign router_25_22_rsp_in[1] = router_26_22_to_router_25_22_rsp; - assign router_25_22_rsp_in[2] = router_25_21_to_router_25_22_rsp; - assign router_25_22_rsp_in[3] = router_24_22_to_router_25_22_rsp; - assign router_25_22_rsp_in[4] = magia_tile_ni_25_22_to_router_25_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_22_req_in), - .floo_rsp_o (router_25_22_rsp_out), - .floo_req_o (router_25_22_req_out), - .floo_rsp_i (router_25_22_rsp_in) -); - - -floo_req_t [4:0] router_25_23_req_in; -floo_rsp_t [4:0] router_25_23_rsp_out; -floo_req_t [4:0] router_25_23_req_out; -floo_rsp_t [4:0] router_25_23_rsp_in; - - assign router_25_23_req_in[0] = router_25_24_to_router_25_23_req; - assign router_25_23_req_in[1] = router_26_23_to_router_25_23_req; - assign router_25_23_req_in[2] = router_25_22_to_router_25_23_req; - assign router_25_23_req_in[3] = router_24_23_to_router_25_23_req; - assign router_25_23_req_in[4] = magia_tile_ni_25_23_to_router_25_23_req; - - assign router_25_23_to_router_25_24_rsp = router_25_23_rsp_out[0]; - assign router_25_23_to_router_26_23_rsp = router_25_23_rsp_out[1]; - assign router_25_23_to_router_25_22_rsp = router_25_23_rsp_out[2]; - assign router_25_23_to_router_24_23_rsp = router_25_23_rsp_out[3]; - assign router_25_23_to_magia_tile_ni_25_23_rsp = router_25_23_rsp_out[4]; - - assign router_25_23_to_router_25_24_req = router_25_23_req_out[0]; - assign router_25_23_to_router_26_23_req = router_25_23_req_out[1]; - assign router_25_23_to_router_25_22_req = router_25_23_req_out[2]; - assign router_25_23_to_router_24_23_req = router_25_23_req_out[3]; - assign router_25_23_to_magia_tile_ni_25_23_req = router_25_23_req_out[4]; - - assign router_25_23_rsp_in[0] = router_25_24_to_router_25_23_rsp; - assign router_25_23_rsp_in[1] = router_26_23_to_router_25_23_rsp; - assign router_25_23_rsp_in[2] = router_25_22_to_router_25_23_rsp; - assign router_25_23_rsp_in[3] = router_24_23_to_router_25_23_rsp; - assign router_25_23_rsp_in[4] = magia_tile_ni_25_23_to_router_25_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_23_req_in), - .floo_rsp_o (router_25_23_rsp_out), - .floo_req_o (router_25_23_req_out), - .floo_rsp_i (router_25_23_rsp_in) -); - - -floo_req_t [4:0] router_25_24_req_in; -floo_rsp_t [4:0] router_25_24_rsp_out; -floo_req_t [4:0] router_25_24_req_out; -floo_rsp_t [4:0] router_25_24_rsp_in; - - assign router_25_24_req_in[0] = router_25_25_to_router_25_24_req; - assign router_25_24_req_in[1] = router_26_24_to_router_25_24_req; - assign router_25_24_req_in[2] = router_25_23_to_router_25_24_req; - assign router_25_24_req_in[3] = router_24_24_to_router_25_24_req; - assign router_25_24_req_in[4] = magia_tile_ni_25_24_to_router_25_24_req; - - assign router_25_24_to_router_25_25_rsp = router_25_24_rsp_out[0]; - assign router_25_24_to_router_26_24_rsp = router_25_24_rsp_out[1]; - assign router_25_24_to_router_25_23_rsp = router_25_24_rsp_out[2]; - assign router_25_24_to_router_24_24_rsp = router_25_24_rsp_out[3]; - assign router_25_24_to_magia_tile_ni_25_24_rsp = router_25_24_rsp_out[4]; - - assign router_25_24_to_router_25_25_req = router_25_24_req_out[0]; - assign router_25_24_to_router_26_24_req = router_25_24_req_out[1]; - assign router_25_24_to_router_25_23_req = router_25_24_req_out[2]; - assign router_25_24_to_router_24_24_req = router_25_24_req_out[3]; - assign router_25_24_to_magia_tile_ni_25_24_req = router_25_24_req_out[4]; - - assign router_25_24_rsp_in[0] = router_25_25_to_router_25_24_rsp; - assign router_25_24_rsp_in[1] = router_26_24_to_router_25_24_rsp; - assign router_25_24_rsp_in[2] = router_25_23_to_router_25_24_rsp; - assign router_25_24_rsp_in[3] = router_24_24_to_router_25_24_rsp; - assign router_25_24_rsp_in[4] = magia_tile_ni_25_24_to_router_25_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_24_req_in), - .floo_rsp_o (router_25_24_rsp_out), - .floo_req_o (router_25_24_req_out), - .floo_rsp_i (router_25_24_rsp_in) -); - - -floo_req_t [4:0] router_25_25_req_in; -floo_rsp_t [4:0] router_25_25_rsp_out; -floo_req_t [4:0] router_25_25_req_out; -floo_rsp_t [4:0] router_25_25_rsp_in; - - assign router_25_25_req_in[0] = router_25_26_to_router_25_25_req; - assign router_25_25_req_in[1] = router_26_25_to_router_25_25_req; - assign router_25_25_req_in[2] = router_25_24_to_router_25_25_req; - assign router_25_25_req_in[3] = router_24_25_to_router_25_25_req; - assign router_25_25_req_in[4] = magia_tile_ni_25_25_to_router_25_25_req; - - assign router_25_25_to_router_25_26_rsp = router_25_25_rsp_out[0]; - assign router_25_25_to_router_26_25_rsp = router_25_25_rsp_out[1]; - assign router_25_25_to_router_25_24_rsp = router_25_25_rsp_out[2]; - assign router_25_25_to_router_24_25_rsp = router_25_25_rsp_out[3]; - assign router_25_25_to_magia_tile_ni_25_25_rsp = router_25_25_rsp_out[4]; - - assign router_25_25_to_router_25_26_req = router_25_25_req_out[0]; - assign router_25_25_to_router_26_25_req = router_25_25_req_out[1]; - assign router_25_25_to_router_25_24_req = router_25_25_req_out[2]; - assign router_25_25_to_router_24_25_req = router_25_25_req_out[3]; - assign router_25_25_to_magia_tile_ni_25_25_req = router_25_25_req_out[4]; - - assign router_25_25_rsp_in[0] = router_25_26_to_router_25_25_rsp; - assign router_25_25_rsp_in[1] = router_26_25_to_router_25_25_rsp; - assign router_25_25_rsp_in[2] = router_25_24_to_router_25_25_rsp; - assign router_25_25_rsp_in[3] = router_24_25_to_router_25_25_rsp; - assign router_25_25_rsp_in[4] = magia_tile_ni_25_25_to_router_25_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_25_req_in), - .floo_rsp_o (router_25_25_rsp_out), - .floo_req_o (router_25_25_req_out), - .floo_rsp_i (router_25_25_rsp_in) -); - - -floo_req_t [4:0] router_25_26_req_in; -floo_rsp_t [4:0] router_25_26_rsp_out; -floo_req_t [4:0] router_25_26_req_out; -floo_rsp_t [4:0] router_25_26_rsp_in; - - assign router_25_26_req_in[0] = router_25_27_to_router_25_26_req; - assign router_25_26_req_in[1] = router_26_26_to_router_25_26_req; - assign router_25_26_req_in[2] = router_25_25_to_router_25_26_req; - assign router_25_26_req_in[3] = router_24_26_to_router_25_26_req; - assign router_25_26_req_in[4] = magia_tile_ni_25_26_to_router_25_26_req; - - assign router_25_26_to_router_25_27_rsp = router_25_26_rsp_out[0]; - assign router_25_26_to_router_26_26_rsp = router_25_26_rsp_out[1]; - assign router_25_26_to_router_25_25_rsp = router_25_26_rsp_out[2]; - assign router_25_26_to_router_24_26_rsp = router_25_26_rsp_out[3]; - assign router_25_26_to_magia_tile_ni_25_26_rsp = router_25_26_rsp_out[4]; - - assign router_25_26_to_router_25_27_req = router_25_26_req_out[0]; - assign router_25_26_to_router_26_26_req = router_25_26_req_out[1]; - assign router_25_26_to_router_25_25_req = router_25_26_req_out[2]; - assign router_25_26_to_router_24_26_req = router_25_26_req_out[3]; - assign router_25_26_to_magia_tile_ni_25_26_req = router_25_26_req_out[4]; - - assign router_25_26_rsp_in[0] = router_25_27_to_router_25_26_rsp; - assign router_25_26_rsp_in[1] = router_26_26_to_router_25_26_rsp; - assign router_25_26_rsp_in[2] = router_25_25_to_router_25_26_rsp; - assign router_25_26_rsp_in[3] = router_24_26_to_router_25_26_rsp; - assign router_25_26_rsp_in[4] = magia_tile_ni_25_26_to_router_25_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_26_req_in), - .floo_rsp_o (router_25_26_rsp_out), - .floo_req_o (router_25_26_req_out), - .floo_rsp_i (router_25_26_rsp_in) -); - - -floo_req_t [4:0] router_25_27_req_in; -floo_rsp_t [4:0] router_25_27_rsp_out; -floo_req_t [4:0] router_25_27_req_out; -floo_rsp_t [4:0] router_25_27_rsp_in; - - assign router_25_27_req_in[0] = router_25_28_to_router_25_27_req; - assign router_25_27_req_in[1] = router_26_27_to_router_25_27_req; - assign router_25_27_req_in[2] = router_25_26_to_router_25_27_req; - assign router_25_27_req_in[3] = router_24_27_to_router_25_27_req; - assign router_25_27_req_in[4] = magia_tile_ni_25_27_to_router_25_27_req; - - assign router_25_27_to_router_25_28_rsp = router_25_27_rsp_out[0]; - assign router_25_27_to_router_26_27_rsp = router_25_27_rsp_out[1]; - assign router_25_27_to_router_25_26_rsp = router_25_27_rsp_out[2]; - assign router_25_27_to_router_24_27_rsp = router_25_27_rsp_out[3]; - assign router_25_27_to_magia_tile_ni_25_27_rsp = router_25_27_rsp_out[4]; - - assign router_25_27_to_router_25_28_req = router_25_27_req_out[0]; - assign router_25_27_to_router_26_27_req = router_25_27_req_out[1]; - assign router_25_27_to_router_25_26_req = router_25_27_req_out[2]; - assign router_25_27_to_router_24_27_req = router_25_27_req_out[3]; - assign router_25_27_to_magia_tile_ni_25_27_req = router_25_27_req_out[4]; - - assign router_25_27_rsp_in[0] = router_25_28_to_router_25_27_rsp; - assign router_25_27_rsp_in[1] = router_26_27_to_router_25_27_rsp; - assign router_25_27_rsp_in[2] = router_25_26_to_router_25_27_rsp; - assign router_25_27_rsp_in[3] = router_24_27_to_router_25_27_rsp; - assign router_25_27_rsp_in[4] = magia_tile_ni_25_27_to_router_25_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_27_req_in), - .floo_rsp_o (router_25_27_rsp_out), - .floo_req_o (router_25_27_req_out), - .floo_rsp_i (router_25_27_rsp_in) -); - - -floo_req_t [4:0] router_25_28_req_in; -floo_rsp_t [4:0] router_25_28_rsp_out; -floo_req_t [4:0] router_25_28_req_out; -floo_rsp_t [4:0] router_25_28_rsp_in; - - assign router_25_28_req_in[0] = router_25_29_to_router_25_28_req; - assign router_25_28_req_in[1] = router_26_28_to_router_25_28_req; - assign router_25_28_req_in[2] = router_25_27_to_router_25_28_req; - assign router_25_28_req_in[3] = router_24_28_to_router_25_28_req; - assign router_25_28_req_in[4] = magia_tile_ni_25_28_to_router_25_28_req; - - assign router_25_28_to_router_25_29_rsp = router_25_28_rsp_out[0]; - assign router_25_28_to_router_26_28_rsp = router_25_28_rsp_out[1]; - assign router_25_28_to_router_25_27_rsp = router_25_28_rsp_out[2]; - assign router_25_28_to_router_24_28_rsp = router_25_28_rsp_out[3]; - assign router_25_28_to_magia_tile_ni_25_28_rsp = router_25_28_rsp_out[4]; - - assign router_25_28_to_router_25_29_req = router_25_28_req_out[0]; - assign router_25_28_to_router_26_28_req = router_25_28_req_out[1]; - assign router_25_28_to_router_25_27_req = router_25_28_req_out[2]; - assign router_25_28_to_router_24_28_req = router_25_28_req_out[3]; - assign router_25_28_to_magia_tile_ni_25_28_req = router_25_28_req_out[4]; - - assign router_25_28_rsp_in[0] = router_25_29_to_router_25_28_rsp; - assign router_25_28_rsp_in[1] = router_26_28_to_router_25_28_rsp; - assign router_25_28_rsp_in[2] = router_25_27_to_router_25_28_rsp; - assign router_25_28_rsp_in[3] = router_24_28_to_router_25_28_rsp; - assign router_25_28_rsp_in[4] = magia_tile_ni_25_28_to_router_25_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_28_req_in), - .floo_rsp_o (router_25_28_rsp_out), - .floo_req_o (router_25_28_req_out), - .floo_rsp_i (router_25_28_rsp_in) -); - - -floo_req_t [4:0] router_25_29_req_in; -floo_rsp_t [4:0] router_25_29_rsp_out; -floo_req_t [4:0] router_25_29_req_out; -floo_rsp_t [4:0] router_25_29_rsp_in; - - assign router_25_29_req_in[0] = router_25_30_to_router_25_29_req; - assign router_25_29_req_in[1] = router_26_29_to_router_25_29_req; - assign router_25_29_req_in[2] = router_25_28_to_router_25_29_req; - assign router_25_29_req_in[3] = router_24_29_to_router_25_29_req; - assign router_25_29_req_in[4] = magia_tile_ni_25_29_to_router_25_29_req; - - assign router_25_29_to_router_25_30_rsp = router_25_29_rsp_out[0]; - assign router_25_29_to_router_26_29_rsp = router_25_29_rsp_out[1]; - assign router_25_29_to_router_25_28_rsp = router_25_29_rsp_out[2]; - assign router_25_29_to_router_24_29_rsp = router_25_29_rsp_out[3]; - assign router_25_29_to_magia_tile_ni_25_29_rsp = router_25_29_rsp_out[4]; - - assign router_25_29_to_router_25_30_req = router_25_29_req_out[0]; - assign router_25_29_to_router_26_29_req = router_25_29_req_out[1]; - assign router_25_29_to_router_25_28_req = router_25_29_req_out[2]; - assign router_25_29_to_router_24_29_req = router_25_29_req_out[3]; - assign router_25_29_to_magia_tile_ni_25_29_req = router_25_29_req_out[4]; - - assign router_25_29_rsp_in[0] = router_25_30_to_router_25_29_rsp; - assign router_25_29_rsp_in[1] = router_26_29_to_router_25_29_rsp; - assign router_25_29_rsp_in[2] = router_25_28_to_router_25_29_rsp; - assign router_25_29_rsp_in[3] = router_24_29_to_router_25_29_rsp; - assign router_25_29_rsp_in[4] = magia_tile_ni_25_29_to_router_25_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_29_req_in), - .floo_rsp_o (router_25_29_rsp_out), - .floo_req_o (router_25_29_req_out), - .floo_rsp_i (router_25_29_rsp_in) -); - - -floo_req_t [4:0] router_25_30_req_in; -floo_rsp_t [4:0] router_25_30_rsp_out; -floo_req_t [4:0] router_25_30_req_out; -floo_rsp_t [4:0] router_25_30_rsp_in; - - assign router_25_30_req_in[0] = router_25_31_to_router_25_30_req; - assign router_25_30_req_in[1] = router_26_30_to_router_25_30_req; - assign router_25_30_req_in[2] = router_25_29_to_router_25_30_req; - assign router_25_30_req_in[3] = router_24_30_to_router_25_30_req; - assign router_25_30_req_in[4] = magia_tile_ni_25_30_to_router_25_30_req; - - assign router_25_30_to_router_25_31_rsp = router_25_30_rsp_out[0]; - assign router_25_30_to_router_26_30_rsp = router_25_30_rsp_out[1]; - assign router_25_30_to_router_25_29_rsp = router_25_30_rsp_out[2]; - assign router_25_30_to_router_24_30_rsp = router_25_30_rsp_out[3]; - assign router_25_30_to_magia_tile_ni_25_30_rsp = router_25_30_rsp_out[4]; - - assign router_25_30_to_router_25_31_req = router_25_30_req_out[0]; - assign router_25_30_to_router_26_30_req = router_25_30_req_out[1]; - assign router_25_30_to_router_25_29_req = router_25_30_req_out[2]; - assign router_25_30_to_router_24_30_req = router_25_30_req_out[3]; - assign router_25_30_to_magia_tile_ni_25_30_req = router_25_30_req_out[4]; - - assign router_25_30_rsp_in[0] = router_25_31_to_router_25_30_rsp; - assign router_25_30_rsp_in[1] = router_26_30_to_router_25_30_rsp; - assign router_25_30_rsp_in[2] = router_25_29_to_router_25_30_rsp; - assign router_25_30_rsp_in[3] = router_24_30_to_router_25_30_rsp; - assign router_25_30_rsp_in[4] = magia_tile_ni_25_30_to_router_25_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_30_req_in), - .floo_rsp_o (router_25_30_rsp_out), - .floo_req_o (router_25_30_req_out), - .floo_rsp_i (router_25_30_rsp_in) -); - - -floo_req_t [4:0] router_25_31_req_in; -floo_rsp_t [4:0] router_25_31_rsp_out; -floo_req_t [4:0] router_25_31_req_out; -floo_rsp_t [4:0] router_25_31_rsp_in; - - assign router_25_31_req_in[0] = '0; - assign router_25_31_req_in[1] = router_26_31_to_router_25_31_req; - assign router_25_31_req_in[2] = router_25_30_to_router_25_31_req; - assign router_25_31_req_in[3] = router_24_31_to_router_25_31_req; - assign router_25_31_req_in[4] = magia_tile_ni_25_31_to_router_25_31_req; - - assign router_25_31_to_router_26_31_rsp = router_25_31_rsp_out[1]; - assign router_25_31_to_router_25_30_rsp = router_25_31_rsp_out[2]; - assign router_25_31_to_router_24_31_rsp = router_25_31_rsp_out[3]; - assign router_25_31_to_magia_tile_ni_25_31_rsp = router_25_31_rsp_out[4]; - - assign router_25_31_to_router_26_31_req = router_25_31_req_out[1]; - assign router_25_31_to_router_25_30_req = router_25_31_req_out[2]; - assign router_25_31_to_router_24_31_req = router_25_31_req_out[3]; - assign router_25_31_to_magia_tile_ni_25_31_req = router_25_31_req_out[4]; - - assign router_25_31_rsp_in[0] = '0; - assign router_25_31_rsp_in[1] = router_26_31_to_router_25_31_rsp; - assign router_25_31_rsp_in[2] = router_25_30_to_router_25_31_rsp; - assign router_25_31_rsp_in[3] = router_24_31_to_router_25_31_rsp; - assign router_25_31_rsp_in[4] = magia_tile_ni_25_31_to_router_25_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_25_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 26, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_25_31_req_in), - .floo_rsp_o (router_25_31_rsp_out), - .floo_req_o (router_25_31_req_out), - .floo_rsp_i (router_25_31_rsp_in) -); - - -floo_req_t [4:0] router_26_0_req_in; -floo_rsp_t [4:0] router_26_0_rsp_out; -floo_req_t [4:0] router_26_0_req_out; -floo_rsp_t [4:0] router_26_0_rsp_in; - - assign router_26_0_req_in[0] = router_26_1_to_router_26_0_req; - assign router_26_0_req_in[1] = router_27_0_to_router_26_0_req; - assign router_26_0_req_in[2] = '0; - assign router_26_0_req_in[3] = router_25_0_to_router_26_0_req; - assign router_26_0_req_in[4] = magia_tile_ni_26_0_to_router_26_0_req; - - assign router_26_0_to_router_26_1_rsp = router_26_0_rsp_out[0]; - assign router_26_0_to_router_27_0_rsp = router_26_0_rsp_out[1]; - assign router_26_0_to_router_25_0_rsp = router_26_0_rsp_out[3]; - assign router_26_0_to_magia_tile_ni_26_0_rsp = router_26_0_rsp_out[4]; - - assign router_26_0_to_router_26_1_req = router_26_0_req_out[0]; - assign router_26_0_to_router_27_0_req = router_26_0_req_out[1]; - assign router_26_0_to_router_25_0_req = router_26_0_req_out[3]; - assign router_26_0_to_magia_tile_ni_26_0_req = router_26_0_req_out[4]; - - assign router_26_0_rsp_in[0] = router_26_1_to_router_26_0_rsp; - assign router_26_0_rsp_in[1] = router_27_0_to_router_26_0_rsp; - assign router_26_0_rsp_in[2] = '0; - assign router_26_0_rsp_in[3] = router_25_0_to_router_26_0_rsp; - assign router_26_0_rsp_in[4] = magia_tile_ni_26_0_to_router_26_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_0_req_in), - .floo_rsp_o (router_26_0_rsp_out), - .floo_req_o (router_26_0_req_out), - .floo_rsp_i (router_26_0_rsp_in) -); - - -floo_req_t [4:0] router_26_1_req_in; -floo_rsp_t [4:0] router_26_1_rsp_out; -floo_req_t [4:0] router_26_1_req_out; -floo_rsp_t [4:0] router_26_1_rsp_in; - - assign router_26_1_req_in[0] = router_26_2_to_router_26_1_req; - assign router_26_1_req_in[1] = router_27_1_to_router_26_1_req; - assign router_26_1_req_in[2] = router_26_0_to_router_26_1_req; - assign router_26_1_req_in[3] = router_25_1_to_router_26_1_req; - assign router_26_1_req_in[4] = magia_tile_ni_26_1_to_router_26_1_req; - - assign router_26_1_to_router_26_2_rsp = router_26_1_rsp_out[0]; - assign router_26_1_to_router_27_1_rsp = router_26_1_rsp_out[1]; - assign router_26_1_to_router_26_0_rsp = router_26_1_rsp_out[2]; - assign router_26_1_to_router_25_1_rsp = router_26_1_rsp_out[3]; - assign router_26_1_to_magia_tile_ni_26_1_rsp = router_26_1_rsp_out[4]; - - assign router_26_1_to_router_26_2_req = router_26_1_req_out[0]; - assign router_26_1_to_router_27_1_req = router_26_1_req_out[1]; - assign router_26_1_to_router_26_0_req = router_26_1_req_out[2]; - assign router_26_1_to_router_25_1_req = router_26_1_req_out[3]; - assign router_26_1_to_magia_tile_ni_26_1_req = router_26_1_req_out[4]; - - assign router_26_1_rsp_in[0] = router_26_2_to_router_26_1_rsp; - assign router_26_1_rsp_in[1] = router_27_1_to_router_26_1_rsp; - assign router_26_1_rsp_in[2] = router_26_0_to_router_26_1_rsp; - assign router_26_1_rsp_in[3] = router_25_1_to_router_26_1_rsp; - assign router_26_1_rsp_in[4] = magia_tile_ni_26_1_to_router_26_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_1_req_in), - .floo_rsp_o (router_26_1_rsp_out), - .floo_req_o (router_26_1_req_out), - .floo_rsp_i (router_26_1_rsp_in) -); - - -floo_req_t [4:0] router_26_2_req_in; -floo_rsp_t [4:0] router_26_2_rsp_out; -floo_req_t [4:0] router_26_2_req_out; -floo_rsp_t [4:0] router_26_2_rsp_in; - - assign router_26_2_req_in[0] = router_26_3_to_router_26_2_req; - assign router_26_2_req_in[1] = router_27_2_to_router_26_2_req; - assign router_26_2_req_in[2] = router_26_1_to_router_26_2_req; - assign router_26_2_req_in[3] = router_25_2_to_router_26_2_req; - assign router_26_2_req_in[4] = magia_tile_ni_26_2_to_router_26_2_req; - - assign router_26_2_to_router_26_3_rsp = router_26_2_rsp_out[0]; - assign router_26_2_to_router_27_2_rsp = router_26_2_rsp_out[1]; - assign router_26_2_to_router_26_1_rsp = router_26_2_rsp_out[2]; - assign router_26_2_to_router_25_2_rsp = router_26_2_rsp_out[3]; - assign router_26_2_to_magia_tile_ni_26_2_rsp = router_26_2_rsp_out[4]; - - assign router_26_2_to_router_26_3_req = router_26_2_req_out[0]; - assign router_26_2_to_router_27_2_req = router_26_2_req_out[1]; - assign router_26_2_to_router_26_1_req = router_26_2_req_out[2]; - assign router_26_2_to_router_25_2_req = router_26_2_req_out[3]; - assign router_26_2_to_magia_tile_ni_26_2_req = router_26_2_req_out[4]; - - assign router_26_2_rsp_in[0] = router_26_3_to_router_26_2_rsp; - assign router_26_2_rsp_in[1] = router_27_2_to_router_26_2_rsp; - assign router_26_2_rsp_in[2] = router_26_1_to_router_26_2_rsp; - assign router_26_2_rsp_in[3] = router_25_2_to_router_26_2_rsp; - assign router_26_2_rsp_in[4] = magia_tile_ni_26_2_to_router_26_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_2_req_in), - .floo_rsp_o (router_26_2_rsp_out), - .floo_req_o (router_26_2_req_out), - .floo_rsp_i (router_26_2_rsp_in) -); - - -floo_req_t [4:0] router_26_3_req_in; -floo_rsp_t [4:0] router_26_3_rsp_out; -floo_req_t [4:0] router_26_3_req_out; -floo_rsp_t [4:0] router_26_3_rsp_in; - - assign router_26_3_req_in[0] = router_26_4_to_router_26_3_req; - assign router_26_3_req_in[1] = router_27_3_to_router_26_3_req; - assign router_26_3_req_in[2] = router_26_2_to_router_26_3_req; - assign router_26_3_req_in[3] = router_25_3_to_router_26_3_req; - assign router_26_3_req_in[4] = magia_tile_ni_26_3_to_router_26_3_req; - - assign router_26_3_to_router_26_4_rsp = router_26_3_rsp_out[0]; - assign router_26_3_to_router_27_3_rsp = router_26_3_rsp_out[1]; - assign router_26_3_to_router_26_2_rsp = router_26_3_rsp_out[2]; - assign router_26_3_to_router_25_3_rsp = router_26_3_rsp_out[3]; - assign router_26_3_to_magia_tile_ni_26_3_rsp = router_26_3_rsp_out[4]; - - assign router_26_3_to_router_26_4_req = router_26_3_req_out[0]; - assign router_26_3_to_router_27_3_req = router_26_3_req_out[1]; - assign router_26_3_to_router_26_2_req = router_26_3_req_out[2]; - assign router_26_3_to_router_25_3_req = router_26_3_req_out[3]; - assign router_26_3_to_magia_tile_ni_26_3_req = router_26_3_req_out[4]; - - assign router_26_3_rsp_in[0] = router_26_4_to_router_26_3_rsp; - assign router_26_3_rsp_in[1] = router_27_3_to_router_26_3_rsp; - assign router_26_3_rsp_in[2] = router_26_2_to_router_26_3_rsp; - assign router_26_3_rsp_in[3] = router_25_3_to_router_26_3_rsp; - assign router_26_3_rsp_in[4] = magia_tile_ni_26_3_to_router_26_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_3_req_in), - .floo_rsp_o (router_26_3_rsp_out), - .floo_req_o (router_26_3_req_out), - .floo_rsp_i (router_26_3_rsp_in) -); - - -floo_req_t [4:0] router_26_4_req_in; -floo_rsp_t [4:0] router_26_4_rsp_out; -floo_req_t [4:0] router_26_4_req_out; -floo_rsp_t [4:0] router_26_4_rsp_in; - - assign router_26_4_req_in[0] = router_26_5_to_router_26_4_req; - assign router_26_4_req_in[1] = router_27_4_to_router_26_4_req; - assign router_26_4_req_in[2] = router_26_3_to_router_26_4_req; - assign router_26_4_req_in[3] = router_25_4_to_router_26_4_req; - assign router_26_4_req_in[4] = magia_tile_ni_26_4_to_router_26_4_req; - - assign router_26_4_to_router_26_5_rsp = router_26_4_rsp_out[0]; - assign router_26_4_to_router_27_4_rsp = router_26_4_rsp_out[1]; - assign router_26_4_to_router_26_3_rsp = router_26_4_rsp_out[2]; - assign router_26_4_to_router_25_4_rsp = router_26_4_rsp_out[3]; - assign router_26_4_to_magia_tile_ni_26_4_rsp = router_26_4_rsp_out[4]; - - assign router_26_4_to_router_26_5_req = router_26_4_req_out[0]; - assign router_26_4_to_router_27_4_req = router_26_4_req_out[1]; - assign router_26_4_to_router_26_3_req = router_26_4_req_out[2]; - assign router_26_4_to_router_25_4_req = router_26_4_req_out[3]; - assign router_26_4_to_magia_tile_ni_26_4_req = router_26_4_req_out[4]; - - assign router_26_4_rsp_in[0] = router_26_5_to_router_26_4_rsp; - assign router_26_4_rsp_in[1] = router_27_4_to_router_26_4_rsp; - assign router_26_4_rsp_in[2] = router_26_3_to_router_26_4_rsp; - assign router_26_4_rsp_in[3] = router_25_4_to_router_26_4_rsp; - assign router_26_4_rsp_in[4] = magia_tile_ni_26_4_to_router_26_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_4_req_in), - .floo_rsp_o (router_26_4_rsp_out), - .floo_req_o (router_26_4_req_out), - .floo_rsp_i (router_26_4_rsp_in) -); - - -floo_req_t [4:0] router_26_5_req_in; -floo_rsp_t [4:0] router_26_5_rsp_out; -floo_req_t [4:0] router_26_5_req_out; -floo_rsp_t [4:0] router_26_5_rsp_in; - - assign router_26_5_req_in[0] = router_26_6_to_router_26_5_req; - assign router_26_5_req_in[1] = router_27_5_to_router_26_5_req; - assign router_26_5_req_in[2] = router_26_4_to_router_26_5_req; - assign router_26_5_req_in[3] = router_25_5_to_router_26_5_req; - assign router_26_5_req_in[4] = magia_tile_ni_26_5_to_router_26_5_req; - - assign router_26_5_to_router_26_6_rsp = router_26_5_rsp_out[0]; - assign router_26_5_to_router_27_5_rsp = router_26_5_rsp_out[1]; - assign router_26_5_to_router_26_4_rsp = router_26_5_rsp_out[2]; - assign router_26_5_to_router_25_5_rsp = router_26_5_rsp_out[3]; - assign router_26_5_to_magia_tile_ni_26_5_rsp = router_26_5_rsp_out[4]; - - assign router_26_5_to_router_26_6_req = router_26_5_req_out[0]; - assign router_26_5_to_router_27_5_req = router_26_5_req_out[1]; - assign router_26_5_to_router_26_4_req = router_26_5_req_out[2]; - assign router_26_5_to_router_25_5_req = router_26_5_req_out[3]; - assign router_26_5_to_magia_tile_ni_26_5_req = router_26_5_req_out[4]; - - assign router_26_5_rsp_in[0] = router_26_6_to_router_26_5_rsp; - assign router_26_5_rsp_in[1] = router_27_5_to_router_26_5_rsp; - assign router_26_5_rsp_in[2] = router_26_4_to_router_26_5_rsp; - assign router_26_5_rsp_in[3] = router_25_5_to_router_26_5_rsp; - assign router_26_5_rsp_in[4] = magia_tile_ni_26_5_to_router_26_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_5_req_in), - .floo_rsp_o (router_26_5_rsp_out), - .floo_req_o (router_26_5_req_out), - .floo_rsp_i (router_26_5_rsp_in) -); - - -floo_req_t [4:0] router_26_6_req_in; -floo_rsp_t [4:0] router_26_6_rsp_out; -floo_req_t [4:0] router_26_6_req_out; -floo_rsp_t [4:0] router_26_6_rsp_in; - - assign router_26_6_req_in[0] = router_26_7_to_router_26_6_req; - assign router_26_6_req_in[1] = router_27_6_to_router_26_6_req; - assign router_26_6_req_in[2] = router_26_5_to_router_26_6_req; - assign router_26_6_req_in[3] = router_25_6_to_router_26_6_req; - assign router_26_6_req_in[4] = magia_tile_ni_26_6_to_router_26_6_req; - - assign router_26_6_to_router_26_7_rsp = router_26_6_rsp_out[0]; - assign router_26_6_to_router_27_6_rsp = router_26_6_rsp_out[1]; - assign router_26_6_to_router_26_5_rsp = router_26_6_rsp_out[2]; - assign router_26_6_to_router_25_6_rsp = router_26_6_rsp_out[3]; - assign router_26_6_to_magia_tile_ni_26_6_rsp = router_26_6_rsp_out[4]; - - assign router_26_6_to_router_26_7_req = router_26_6_req_out[0]; - assign router_26_6_to_router_27_6_req = router_26_6_req_out[1]; - assign router_26_6_to_router_26_5_req = router_26_6_req_out[2]; - assign router_26_6_to_router_25_6_req = router_26_6_req_out[3]; - assign router_26_6_to_magia_tile_ni_26_6_req = router_26_6_req_out[4]; - - assign router_26_6_rsp_in[0] = router_26_7_to_router_26_6_rsp; - assign router_26_6_rsp_in[1] = router_27_6_to_router_26_6_rsp; - assign router_26_6_rsp_in[2] = router_26_5_to_router_26_6_rsp; - assign router_26_6_rsp_in[3] = router_25_6_to_router_26_6_rsp; - assign router_26_6_rsp_in[4] = magia_tile_ni_26_6_to_router_26_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_6_req_in), - .floo_rsp_o (router_26_6_rsp_out), - .floo_req_o (router_26_6_req_out), - .floo_rsp_i (router_26_6_rsp_in) -); - - -floo_req_t [4:0] router_26_7_req_in; -floo_rsp_t [4:0] router_26_7_rsp_out; -floo_req_t [4:0] router_26_7_req_out; -floo_rsp_t [4:0] router_26_7_rsp_in; - - assign router_26_7_req_in[0] = router_26_8_to_router_26_7_req; - assign router_26_7_req_in[1] = router_27_7_to_router_26_7_req; - assign router_26_7_req_in[2] = router_26_6_to_router_26_7_req; - assign router_26_7_req_in[3] = router_25_7_to_router_26_7_req; - assign router_26_7_req_in[4] = magia_tile_ni_26_7_to_router_26_7_req; - - assign router_26_7_to_router_26_8_rsp = router_26_7_rsp_out[0]; - assign router_26_7_to_router_27_7_rsp = router_26_7_rsp_out[1]; - assign router_26_7_to_router_26_6_rsp = router_26_7_rsp_out[2]; - assign router_26_7_to_router_25_7_rsp = router_26_7_rsp_out[3]; - assign router_26_7_to_magia_tile_ni_26_7_rsp = router_26_7_rsp_out[4]; - - assign router_26_7_to_router_26_8_req = router_26_7_req_out[0]; - assign router_26_7_to_router_27_7_req = router_26_7_req_out[1]; - assign router_26_7_to_router_26_6_req = router_26_7_req_out[2]; - assign router_26_7_to_router_25_7_req = router_26_7_req_out[3]; - assign router_26_7_to_magia_tile_ni_26_7_req = router_26_7_req_out[4]; - - assign router_26_7_rsp_in[0] = router_26_8_to_router_26_7_rsp; - assign router_26_7_rsp_in[1] = router_27_7_to_router_26_7_rsp; - assign router_26_7_rsp_in[2] = router_26_6_to_router_26_7_rsp; - assign router_26_7_rsp_in[3] = router_25_7_to_router_26_7_rsp; - assign router_26_7_rsp_in[4] = magia_tile_ni_26_7_to_router_26_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_7_req_in), - .floo_rsp_o (router_26_7_rsp_out), - .floo_req_o (router_26_7_req_out), - .floo_rsp_i (router_26_7_rsp_in) -); - - -floo_req_t [4:0] router_26_8_req_in; -floo_rsp_t [4:0] router_26_8_rsp_out; -floo_req_t [4:0] router_26_8_req_out; -floo_rsp_t [4:0] router_26_8_rsp_in; - - assign router_26_8_req_in[0] = router_26_9_to_router_26_8_req; - assign router_26_8_req_in[1] = router_27_8_to_router_26_8_req; - assign router_26_8_req_in[2] = router_26_7_to_router_26_8_req; - assign router_26_8_req_in[3] = router_25_8_to_router_26_8_req; - assign router_26_8_req_in[4] = magia_tile_ni_26_8_to_router_26_8_req; - - assign router_26_8_to_router_26_9_rsp = router_26_8_rsp_out[0]; - assign router_26_8_to_router_27_8_rsp = router_26_8_rsp_out[1]; - assign router_26_8_to_router_26_7_rsp = router_26_8_rsp_out[2]; - assign router_26_8_to_router_25_8_rsp = router_26_8_rsp_out[3]; - assign router_26_8_to_magia_tile_ni_26_8_rsp = router_26_8_rsp_out[4]; - - assign router_26_8_to_router_26_9_req = router_26_8_req_out[0]; - assign router_26_8_to_router_27_8_req = router_26_8_req_out[1]; - assign router_26_8_to_router_26_7_req = router_26_8_req_out[2]; - assign router_26_8_to_router_25_8_req = router_26_8_req_out[3]; - assign router_26_8_to_magia_tile_ni_26_8_req = router_26_8_req_out[4]; - - assign router_26_8_rsp_in[0] = router_26_9_to_router_26_8_rsp; - assign router_26_8_rsp_in[1] = router_27_8_to_router_26_8_rsp; - assign router_26_8_rsp_in[2] = router_26_7_to_router_26_8_rsp; - assign router_26_8_rsp_in[3] = router_25_8_to_router_26_8_rsp; - assign router_26_8_rsp_in[4] = magia_tile_ni_26_8_to_router_26_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_8_req_in), - .floo_rsp_o (router_26_8_rsp_out), - .floo_req_o (router_26_8_req_out), - .floo_rsp_i (router_26_8_rsp_in) -); - - -floo_req_t [4:0] router_26_9_req_in; -floo_rsp_t [4:0] router_26_9_rsp_out; -floo_req_t [4:0] router_26_9_req_out; -floo_rsp_t [4:0] router_26_9_rsp_in; - - assign router_26_9_req_in[0] = router_26_10_to_router_26_9_req; - assign router_26_9_req_in[1] = router_27_9_to_router_26_9_req; - assign router_26_9_req_in[2] = router_26_8_to_router_26_9_req; - assign router_26_9_req_in[3] = router_25_9_to_router_26_9_req; - assign router_26_9_req_in[4] = magia_tile_ni_26_9_to_router_26_9_req; - - assign router_26_9_to_router_26_10_rsp = router_26_9_rsp_out[0]; - assign router_26_9_to_router_27_9_rsp = router_26_9_rsp_out[1]; - assign router_26_9_to_router_26_8_rsp = router_26_9_rsp_out[2]; - assign router_26_9_to_router_25_9_rsp = router_26_9_rsp_out[3]; - assign router_26_9_to_magia_tile_ni_26_9_rsp = router_26_9_rsp_out[4]; - - assign router_26_9_to_router_26_10_req = router_26_9_req_out[0]; - assign router_26_9_to_router_27_9_req = router_26_9_req_out[1]; - assign router_26_9_to_router_26_8_req = router_26_9_req_out[2]; - assign router_26_9_to_router_25_9_req = router_26_9_req_out[3]; - assign router_26_9_to_magia_tile_ni_26_9_req = router_26_9_req_out[4]; - - assign router_26_9_rsp_in[0] = router_26_10_to_router_26_9_rsp; - assign router_26_9_rsp_in[1] = router_27_9_to_router_26_9_rsp; - assign router_26_9_rsp_in[2] = router_26_8_to_router_26_9_rsp; - assign router_26_9_rsp_in[3] = router_25_9_to_router_26_9_rsp; - assign router_26_9_rsp_in[4] = magia_tile_ni_26_9_to_router_26_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_9_req_in), - .floo_rsp_o (router_26_9_rsp_out), - .floo_req_o (router_26_9_req_out), - .floo_rsp_i (router_26_9_rsp_in) -); - - -floo_req_t [4:0] router_26_10_req_in; -floo_rsp_t [4:0] router_26_10_rsp_out; -floo_req_t [4:0] router_26_10_req_out; -floo_rsp_t [4:0] router_26_10_rsp_in; - - assign router_26_10_req_in[0] = router_26_11_to_router_26_10_req; - assign router_26_10_req_in[1] = router_27_10_to_router_26_10_req; - assign router_26_10_req_in[2] = router_26_9_to_router_26_10_req; - assign router_26_10_req_in[3] = router_25_10_to_router_26_10_req; - assign router_26_10_req_in[4] = magia_tile_ni_26_10_to_router_26_10_req; - - assign router_26_10_to_router_26_11_rsp = router_26_10_rsp_out[0]; - assign router_26_10_to_router_27_10_rsp = router_26_10_rsp_out[1]; - assign router_26_10_to_router_26_9_rsp = router_26_10_rsp_out[2]; - assign router_26_10_to_router_25_10_rsp = router_26_10_rsp_out[3]; - assign router_26_10_to_magia_tile_ni_26_10_rsp = router_26_10_rsp_out[4]; - - assign router_26_10_to_router_26_11_req = router_26_10_req_out[0]; - assign router_26_10_to_router_27_10_req = router_26_10_req_out[1]; - assign router_26_10_to_router_26_9_req = router_26_10_req_out[2]; - assign router_26_10_to_router_25_10_req = router_26_10_req_out[3]; - assign router_26_10_to_magia_tile_ni_26_10_req = router_26_10_req_out[4]; - - assign router_26_10_rsp_in[0] = router_26_11_to_router_26_10_rsp; - assign router_26_10_rsp_in[1] = router_27_10_to_router_26_10_rsp; - assign router_26_10_rsp_in[2] = router_26_9_to_router_26_10_rsp; - assign router_26_10_rsp_in[3] = router_25_10_to_router_26_10_rsp; - assign router_26_10_rsp_in[4] = magia_tile_ni_26_10_to_router_26_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_10_req_in), - .floo_rsp_o (router_26_10_rsp_out), - .floo_req_o (router_26_10_req_out), - .floo_rsp_i (router_26_10_rsp_in) -); - - -floo_req_t [4:0] router_26_11_req_in; -floo_rsp_t [4:0] router_26_11_rsp_out; -floo_req_t [4:0] router_26_11_req_out; -floo_rsp_t [4:0] router_26_11_rsp_in; - - assign router_26_11_req_in[0] = router_26_12_to_router_26_11_req; - assign router_26_11_req_in[1] = router_27_11_to_router_26_11_req; - assign router_26_11_req_in[2] = router_26_10_to_router_26_11_req; - assign router_26_11_req_in[3] = router_25_11_to_router_26_11_req; - assign router_26_11_req_in[4] = magia_tile_ni_26_11_to_router_26_11_req; - - assign router_26_11_to_router_26_12_rsp = router_26_11_rsp_out[0]; - assign router_26_11_to_router_27_11_rsp = router_26_11_rsp_out[1]; - assign router_26_11_to_router_26_10_rsp = router_26_11_rsp_out[2]; - assign router_26_11_to_router_25_11_rsp = router_26_11_rsp_out[3]; - assign router_26_11_to_magia_tile_ni_26_11_rsp = router_26_11_rsp_out[4]; - - assign router_26_11_to_router_26_12_req = router_26_11_req_out[0]; - assign router_26_11_to_router_27_11_req = router_26_11_req_out[1]; - assign router_26_11_to_router_26_10_req = router_26_11_req_out[2]; - assign router_26_11_to_router_25_11_req = router_26_11_req_out[3]; - assign router_26_11_to_magia_tile_ni_26_11_req = router_26_11_req_out[4]; - - assign router_26_11_rsp_in[0] = router_26_12_to_router_26_11_rsp; - assign router_26_11_rsp_in[1] = router_27_11_to_router_26_11_rsp; - assign router_26_11_rsp_in[2] = router_26_10_to_router_26_11_rsp; - assign router_26_11_rsp_in[3] = router_25_11_to_router_26_11_rsp; - assign router_26_11_rsp_in[4] = magia_tile_ni_26_11_to_router_26_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_11_req_in), - .floo_rsp_o (router_26_11_rsp_out), - .floo_req_o (router_26_11_req_out), - .floo_rsp_i (router_26_11_rsp_in) -); - - -floo_req_t [4:0] router_26_12_req_in; -floo_rsp_t [4:0] router_26_12_rsp_out; -floo_req_t [4:0] router_26_12_req_out; -floo_rsp_t [4:0] router_26_12_rsp_in; - - assign router_26_12_req_in[0] = router_26_13_to_router_26_12_req; - assign router_26_12_req_in[1] = router_27_12_to_router_26_12_req; - assign router_26_12_req_in[2] = router_26_11_to_router_26_12_req; - assign router_26_12_req_in[3] = router_25_12_to_router_26_12_req; - assign router_26_12_req_in[4] = magia_tile_ni_26_12_to_router_26_12_req; - - assign router_26_12_to_router_26_13_rsp = router_26_12_rsp_out[0]; - assign router_26_12_to_router_27_12_rsp = router_26_12_rsp_out[1]; - assign router_26_12_to_router_26_11_rsp = router_26_12_rsp_out[2]; - assign router_26_12_to_router_25_12_rsp = router_26_12_rsp_out[3]; - assign router_26_12_to_magia_tile_ni_26_12_rsp = router_26_12_rsp_out[4]; - - assign router_26_12_to_router_26_13_req = router_26_12_req_out[0]; - assign router_26_12_to_router_27_12_req = router_26_12_req_out[1]; - assign router_26_12_to_router_26_11_req = router_26_12_req_out[2]; - assign router_26_12_to_router_25_12_req = router_26_12_req_out[3]; - assign router_26_12_to_magia_tile_ni_26_12_req = router_26_12_req_out[4]; - - assign router_26_12_rsp_in[0] = router_26_13_to_router_26_12_rsp; - assign router_26_12_rsp_in[1] = router_27_12_to_router_26_12_rsp; - assign router_26_12_rsp_in[2] = router_26_11_to_router_26_12_rsp; - assign router_26_12_rsp_in[3] = router_25_12_to_router_26_12_rsp; - assign router_26_12_rsp_in[4] = magia_tile_ni_26_12_to_router_26_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_12_req_in), - .floo_rsp_o (router_26_12_rsp_out), - .floo_req_o (router_26_12_req_out), - .floo_rsp_i (router_26_12_rsp_in) -); - - -floo_req_t [4:0] router_26_13_req_in; -floo_rsp_t [4:0] router_26_13_rsp_out; -floo_req_t [4:0] router_26_13_req_out; -floo_rsp_t [4:0] router_26_13_rsp_in; - - assign router_26_13_req_in[0] = router_26_14_to_router_26_13_req; - assign router_26_13_req_in[1] = router_27_13_to_router_26_13_req; - assign router_26_13_req_in[2] = router_26_12_to_router_26_13_req; - assign router_26_13_req_in[3] = router_25_13_to_router_26_13_req; - assign router_26_13_req_in[4] = magia_tile_ni_26_13_to_router_26_13_req; - - assign router_26_13_to_router_26_14_rsp = router_26_13_rsp_out[0]; - assign router_26_13_to_router_27_13_rsp = router_26_13_rsp_out[1]; - assign router_26_13_to_router_26_12_rsp = router_26_13_rsp_out[2]; - assign router_26_13_to_router_25_13_rsp = router_26_13_rsp_out[3]; - assign router_26_13_to_magia_tile_ni_26_13_rsp = router_26_13_rsp_out[4]; - - assign router_26_13_to_router_26_14_req = router_26_13_req_out[0]; - assign router_26_13_to_router_27_13_req = router_26_13_req_out[1]; - assign router_26_13_to_router_26_12_req = router_26_13_req_out[2]; - assign router_26_13_to_router_25_13_req = router_26_13_req_out[3]; - assign router_26_13_to_magia_tile_ni_26_13_req = router_26_13_req_out[4]; - - assign router_26_13_rsp_in[0] = router_26_14_to_router_26_13_rsp; - assign router_26_13_rsp_in[1] = router_27_13_to_router_26_13_rsp; - assign router_26_13_rsp_in[2] = router_26_12_to_router_26_13_rsp; - assign router_26_13_rsp_in[3] = router_25_13_to_router_26_13_rsp; - assign router_26_13_rsp_in[4] = magia_tile_ni_26_13_to_router_26_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_13_req_in), - .floo_rsp_o (router_26_13_rsp_out), - .floo_req_o (router_26_13_req_out), - .floo_rsp_i (router_26_13_rsp_in) -); - - -floo_req_t [4:0] router_26_14_req_in; -floo_rsp_t [4:0] router_26_14_rsp_out; -floo_req_t [4:0] router_26_14_req_out; -floo_rsp_t [4:0] router_26_14_rsp_in; - - assign router_26_14_req_in[0] = router_26_15_to_router_26_14_req; - assign router_26_14_req_in[1] = router_27_14_to_router_26_14_req; - assign router_26_14_req_in[2] = router_26_13_to_router_26_14_req; - assign router_26_14_req_in[3] = router_25_14_to_router_26_14_req; - assign router_26_14_req_in[4] = magia_tile_ni_26_14_to_router_26_14_req; - - assign router_26_14_to_router_26_15_rsp = router_26_14_rsp_out[0]; - assign router_26_14_to_router_27_14_rsp = router_26_14_rsp_out[1]; - assign router_26_14_to_router_26_13_rsp = router_26_14_rsp_out[2]; - assign router_26_14_to_router_25_14_rsp = router_26_14_rsp_out[3]; - assign router_26_14_to_magia_tile_ni_26_14_rsp = router_26_14_rsp_out[4]; - - assign router_26_14_to_router_26_15_req = router_26_14_req_out[0]; - assign router_26_14_to_router_27_14_req = router_26_14_req_out[1]; - assign router_26_14_to_router_26_13_req = router_26_14_req_out[2]; - assign router_26_14_to_router_25_14_req = router_26_14_req_out[3]; - assign router_26_14_to_magia_tile_ni_26_14_req = router_26_14_req_out[4]; - - assign router_26_14_rsp_in[0] = router_26_15_to_router_26_14_rsp; - assign router_26_14_rsp_in[1] = router_27_14_to_router_26_14_rsp; - assign router_26_14_rsp_in[2] = router_26_13_to_router_26_14_rsp; - assign router_26_14_rsp_in[3] = router_25_14_to_router_26_14_rsp; - assign router_26_14_rsp_in[4] = magia_tile_ni_26_14_to_router_26_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_14_req_in), - .floo_rsp_o (router_26_14_rsp_out), - .floo_req_o (router_26_14_req_out), - .floo_rsp_i (router_26_14_rsp_in) -); - - -floo_req_t [4:0] router_26_15_req_in; -floo_rsp_t [4:0] router_26_15_rsp_out; -floo_req_t [4:0] router_26_15_req_out; -floo_rsp_t [4:0] router_26_15_rsp_in; - - assign router_26_15_req_in[0] = router_26_16_to_router_26_15_req; - assign router_26_15_req_in[1] = router_27_15_to_router_26_15_req; - assign router_26_15_req_in[2] = router_26_14_to_router_26_15_req; - assign router_26_15_req_in[3] = router_25_15_to_router_26_15_req; - assign router_26_15_req_in[4] = magia_tile_ni_26_15_to_router_26_15_req; - - assign router_26_15_to_router_26_16_rsp = router_26_15_rsp_out[0]; - assign router_26_15_to_router_27_15_rsp = router_26_15_rsp_out[1]; - assign router_26_15_to_router_26_14_rsp = router_26_15_rsp_out[2]; - assign router_26_15_to_router_25_15_rsp = router_26_15_rsp_out[3]; - assign router_26_15_to_magia_tile_ni_26_15_rsp = router_26_15_rsp_out[4]; - - assign router_26_15_to_router_26_16_req = router_26_15_req_out[0]; - assign router_26_15_to_router_27_15_req = router_26_15_req_out[1]; - assign router_26_15_to_router_26_14_req = router_26_15_req_out[2]; - assign router_26_15_to_router_25_15_req = router_26_15_req_out[3]; - assign router_26_15_to_magia_tile_ni_26_15_req = router_26_15_req_out[4]; - - assign router_26_15_rsp_in[0] = router_26_16_to_router_26_15_rsp; - assign router_26_15_rsp_in[1] = router_27_15_to_router_26_15_rsp; - assign router_26_15_rsp_in[2] = router_26_14_to_router_26_15_rsp; - assign router_26_15_rsp_in[3] = router_25_15_to_router_26_15_rsp; - assign router_26_15_rsp_in[4] = magia_tile_ni_26_15_to_router_26_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_15_req_in), - .floo_rsp_o (router_26_15_rsp_out), - .floo_req_o (router_26_15_req_out), - .floo_rsp_i (router_26_15_rsp_in) -); - - -floo_req_t [4:0] router_26_16_req_in; -floo_rsp_t [4:0] router_26_16_rsp_out; -floo_req_t [4:0] router_26_16_req_out; -floo_rsp_t [4:0] router_26_16_rsp_in; - - assign router_26_16_req_in[0] = router_26_17_to_router_26_16_req; - assign router_26_16_req_in[1] = router_27_16_to_router_26_16_req; - assign router_26_16_req_in[2] = router_26_15_to_router_26_16_req; - assign router_26_16_req_in[3] = router_25_16_to_router_26_16_req; - assign router_26_16_req_in[4] = magia_tile_ni_26_16_to_router_26_16_req; - - assign router_26_16_to_router_26_17_rsp = router_26_16_rsp_out[0]; - assign router_26_16_to_router_27_16_rsp = router_26_16_rsp_out[1]; - assign router_26_16_to_router_26_15_rsp = router_26_16_rsp_out[2]; - assign router_26_16_to_router_25_16_rsp = router_26_16_rsp_out[3]; - assign router_26_16_to_magia_tile_ni_26_16_rsp = router_26_16_rsp_out[4]; - - assign router_26_16_to_router_26_17_req = router_26_16_req_out[0]; - assign router_26_16_to_router_27_16_req = router_26_16_req_out[1]; - assign router_26_16_to_router_26_15_req = router_26_16_req_out[2]; - assign router_26_16_to_router_25_16_req = router_26_16_req_out[3]; - assign router_26_16_to_magia_tile_ni_26_16_req = router_26_16_req_out[4]; - - assign router_26_16_rsp_in[0] = router_26_17_to_router_26_16_rsp; - assign router_26_16_rsp_in[1] = router_27_16_to_router_26_16_rsp; - assign router_26_16_rsp_in[2] = router_26_15_to_router_26_16_rsp; - assign router_26_16_rsp_in[3] = router_25_16_to_router_26_16_rsp; - assign router_26_16_rsp_in[4] = magia_tile_ni_26_16_to_router_26_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_16_req_in), - .floo_rsp_o (router_26_16_rsp_out), - .floo_req_o (router_26_16_req_out), - .floo_rsp_i (router_26_16_rsp_in) -); - - -floo_req_t [4:0] router_26_17_req_in; -floo_rsp_t [4:0] router_26_17_rsp_out; -floo_req_t [4:0] router_26_17_req_out; -floo_rsp_t [4:0] router_26_17_rsp_in; - - assign router_26_17_req_in[0] = router_26_18_to_router_26_17_req; - assign router_26_17_req_in[1] = router_27_17_to_router_26_17_req; - assign router_26_17_req_in[2] = router_26_16_to_router_26_17_req; - assign router_26_17_req_in[3] = router_25_17_to_router_26_17_req; - assign router_26_17_req_in[4] = magia_tile_ni_26_17_to_router_26_17_req; - - assign router_26_17_to_router_26_18_rsp = router_26_17_rsp_out[0]; - assign router_26_17_to_router_27_17_rsp = router_26_17_rsp_out[1]; - assign router_26_17_to_router_26_16_rsp = router_26_17_rsp_out[2]; - assign router_26_17_to_router_25_17_rsp = router_26_17_rsp_out[3]; - assign router_26_17_to_magia_tile_ni_26_17_rsp = router_26_17_rsp_out[4]; - - assign router_26_17_to_router_26_18_req = router_26_17_req_out[0]; - assign router_26_17_to_router_27_17_req = router_26_17_req_out[1]; - assign router_26_17_to_router_26_16_req = router_26_17_req_out[2]; - assign router_26_17_to_router_25_17_req = router_26_17_req_out[3]; - assign router_26_17_to_magia_tile_ni_26_17_req = router_26_17_req_out[4]; - - assign router_26_17_rsp_in[0] = router_26_18_to_router_26_17_rsp; - assign router_26_17_rsp_in[1] = router_27_17_to_router_26_17_rsp; - assign router_26_17_rsp_in[2] = router_26_16_to_router_26_17_rsp; - assign router_26_17_rsp_in[3] = router_25_17_to_router_26_17_rsp; - assign router_26_17_rsp_in[4] = magia_tile_ni_26_17_to_router_26_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_17_req_in), - .floo_rsp_o (router_26_17_rsp_out), - .floo_req_o (router_26_17_req_out), - .floo_rsp_i (router_26_17_rsp_in) -); - - -floo_req_t [4:0] router_26_18_req_in; -floo_rsp_t [4:0] router_26_18_rsp_out; -floo_req_t [4:0] router_26_18_req_out; -floo_rsp_t [4:0] router_26_18_rsp_in; - - assign router_26_18_req_in[0] = router_26_19_to_router_26_18_req; - assign router_26_18_req_in[1] = router_27_18_to_router_26_18_req; - assign router_26_18_req_in[2] = router_26_17_to_router_26_18_req; - assign router_26_18_req_in[3] = router_25_18_to_router_26_18_req; - assign router_26_18_req_in[4] = magia_tile_ni_26_18_to_router_26_18_req; - - assign router_26_18_to_router_26_19_rsp = router_26_18_rsp_out[0]; - assign router_26_18_to_router_27_18_rsp = router_26_18_rsp_out[1]; - assign router_26_18_to_router_26_17_rsp = router_26_18_rsp_out[2]; - assign router_26_18_to_router_25_18_rsp = router_26_18_rsp_out[3]; - assign router_26_18_to_magia_tile_ni_26_18_rsp = router_26_18_rsp_out[4]; - - assign router_26_18_to_router_26_19_req = router_26_18_req_out[0]; - assign router_26_18_to_router_27_18_req = router_26_18_req_out[1]; - assign router_26_18_to_router_26_17_req = router_26_18_req_out[2]; - assign router_26_18_to_router_25_18_req = router_26_18_req_out[3]; - assign router_26_18_to_magia_tile_ni_26_18_req = router_26_18_req_out[4]; - - assign router_26_18_rsp_in[0] = router_26_19_to_router_26_18_rsp; - assign router_26_18_rsp_in[1] = router_27_18_to_router_26_18_rsp; - assign router_26_18_rsp_in[2] = router_26_17_to_router_26_18_rsp; - assign router_26_18_rsp_in[3] = router_25_18_to_router_26_18_rsp; - assign router_26_18_rsp_in[4] = magia_tile_ni_26_18_to_router_26_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_18_req_in), - .floo_rsp_o (router_26_18_rsp_out), - .floo_req_o (router_26_18_req_out), - .floo_rsp_i (router_26_18_rsp_in) -); - - -floo_req_t [4:0] router_26_19_req_in; -floo_rsp_t [4:0] router_26_19_rsp_out; -floo_req_t [4:0] router_26_19_req_out; -floo_rsp_t [4:0] router_26_19_rsp_in; - - assign router_26_19_req_in[0] = router_26_20_to_router_26_19_req; - assign router_26_19_req_in[1] = router_27_19_to_router_26_19_req; - assign router_26_19_req_in[2] = router_26_18_to_router_26_19_req; - assign router_26_19_req_in[3] = router_25_19_to_router_26_19_req; - assign router_26_19_req_in[4] = magia_tile_ni_26_19_to_router_26_19_req; - - assign router_26_19_to_router_26_20_rsp = router_26_19_rsp_out[0]; - assign router_26_19_to_router_27_19_rsp = router_26_19_rsp_out[1]; - assign router_26_19_to_router_26_18_rsp = router_26_19_rsp_out[2]; - assign router_26_19_to_router_25_19_rsp = router_26_19_rsp_out[3]; - assign router_26_19_to_magia_tile_ni_26_19_rsp = router_26_19_rsp_out[4]; - - assign router_26_19_to_router_26_20_req = router_26_19_req_out[0]; - assign router_26_19_to_router_27_19_req = router_26_19_req_out[1]; - assign router_26_19_to_router_26_18_req = router_26_19_req_out[2]; - assign router_26_19_to_router_25_19_req = router_26_19_req_out[3]; - assign router_26_19_to_magia_tile_ni_26_19_req = router_26_19_req_out[4]; - - assign router_26_19_rsp_in[0] = router_26_20_to_router_26_19_rsp; - assign router_26_19_rsp_in[1] = router_27_19_to_router_26_19_rsp; - assign router_26_19_rsp_in[2] = router_26_18_to_router_26_19_rsp; - assign router_26_19_rsp_in[3] = router_25_19_to_router_26_19_rsp; - assign router_26_19_rsp_in[4] = magia_tile_ni_26_19_to_router_26_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_19_req_in), - .floo_rsp_o (router_26_19_rsp_out), - .floo_req_o (router_26_19_req_out), - .floo_rsp_i (router_26_19_rsp_in) -); - - -floo_req_t [4:0] router_26_20_req_in; -floo_rsp_t [4:0] router_26_20_rsp_out; -floo_req_t [4:0] router_26_20_req_out; -floo_rsp_t [4:0] router_26_20_rsp_in; - - assign router_26_20_req_in[0] = router_26_21_to_router_26_20_req; - assign router_26_20_req_in[1] = router_27_20_to_router_26_20_req; - assign router_26_20_req_in[2] = router_26_19_to_router_26_20_req; - assign router_26_20_req_in[3] = router_25_20_to_router_26_20_req; - assign router_26_20_req_in[4] = magia_tile_ni_26_20_to_router_26_20_req; - - assign router_26_20_to_router_26_21_rsp = router_26_20_rsp_out[0]; - assign router_26_20_to_router_27_20_rsp = router_26_20_rsp_out[1]; - assign router_26_20_to_router_26_19_rsp = router_26_20_rsp_out[2]; - assign router_26_20_to_router_25_20_rsp = router_26_20_rsp_out[3]; - assign router_26_20_to_magia_tile_ni_26_20_rsp = router_26_20_rsp_out[4]; - - assign router_26_20_to_router_26_21_req = router_26_20_req_out[0]; - assign router_26_20_to_router_27_20_req = router_26_20_req_out[1]; - assign router_26_20_to_router_26_19_req = router_26_20_req_out[2]; - assign router_26_20_to_router_25_20_req = router_26_20_req_out[3]; - assign router_26_20_to_magia_tile_ni_26_20_req = router_26_20_req_out[4]; - - assign router_26_20_rsp_in[0] = router_26_21_to_router_26_20_rsp; - assign router_26_20_rsp_in[1] = router_27_20_to_router_26_20_rsp; - assign router_26_20_rsp_in[2] = router_26_19_to_router_26_20_rsp; - assign router_26_20_rsp_in[3] = router_25_20_to_router_26_20_rsp; - assign router_26_20_rsp_in[4] = magia_tile_ni_26_20_to_router_26_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_20_req_in), - .floo_rsp_o (router_26_20_rsp_out), - .floo_req_o (router_26_20_req_out), - .floo_rsp_i (router_26_20_rsp_in) -); - - -floo_req_t [4:0] router_26_21_req_in; -floo_rsp_t [4:0] router_26_21_rsp_out; -floo_req_t [4:0] router_26_21_req_out; -floo_rsp_t [4:0] router_26_21_rsp_in; - - assign router_26_21_req_in[0] = router_26_22_to_router_26_21_req; - assign router_26_21_req_in[1] = router_27_21_to_router_26_21_req; - assign router_26_21_req_in[2] = router_26_20_to_router_26_21_req; - assign router_26_21_req_in[3] = router_25_21_to_router_26_21_req; - assign router_26_21_req_in[4] = magia_tile_ni_26_21_to_router_26_21_req; - - assign router_26_21_to_router_26_22_rsp = router_26_21_rsp_out[0]; - assign router_26_21_to_router_27_21_rsp = router_26_21_rsp_out[1]; - assign router_26_21_to_router_26_20_rsp = router_26_21_rsp_out[2]; - assign router_26_21_to_router_25_21_rsp = router_26_21_rsp_out[3]; - assign router_26_21_to_magia_tile_ni_26_21_rsp = router_26_21_rsp_out[4]; - - assign router_26_21_to_router_26_22_req = router_26_21_req_out[0]; - assign router_26_21_to_router_27_21_req = router_26_21_req_out[1]; - assign router_26_21_to_router_26_20_req = router_26_21_req_out[2]; - assign router_26_21_to_router_25_21_req = router_26_21_req_out[3]; - assign router_26_21_to_magia_tile_ni_26_21_req = router_26_21_req_out[4]; - - assign router_26_21_rsp_in[0] = router_26_22_to_router_26_21_rsp; - assign router_26_21_rsp_in[1] = router_27_21_to_router_26_21_rsp; - assign router_26_21_rsp_in[2] = router_26_20_to_router_26_21_rsp; - assign router_26_21_rsp_in[3] = router_25_21_to_router_26_21_rsp; - assign router_26_21_rsp_in[4] = magia_tile_ni_26_21_to_router_26_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_21_req_in), - .floo_rsp_o (router_26_21_rsp_out), - .floo_req_o (router_26_21_req_out), - .floo_rsp_i (router_26_21_rsp_in) -); - - -floo_req_t [4:0] router_26_22_req_in; -floo_rsp_t [4:0] router_26_22_rsp_out; -floo_req_t [4:0] router_26_22_req_out; -floo_rsp_t [4:0] router_26_22_rsp_in; - - assign router_26_22_req_in[0] = router_26_23_to_router_26_22_req; - assign router_26_22_req_in[1] = router_27_22_to_router_26_22_req; - assign router_26_22_req_in[2] = router_26_21_to_router_26_22_req; - assign router_26_22_req_in[3] = router_25_22_to_router_26_22_req; - assign router_26_22_req_in[4] = magia_tile_ni_26_22_to_router_26_22_req; - - assign router_26_22_to_router_26_23_rsp = router_26_22_rsp_out[0]; - assign router_26_22_to_router_27_22_rsp = router_26_22_rsp_out[1]; - assign router_26_22_to_router_26_21_rsp = router_26_22_rsp_out[2]; - assign router_26_22_to_router_25_22_rsp = router_26_22_rsp_out[3]; - assign router_26_22_to_magia_tile_ni_26_22_rsp = router_26_22_rsp_out[4]; - - assign router_26_22_to_router_26_23_req = router_26_22_req_out[0]; - assign router_26_22_to_router_27_22_req = router_26_22_req_out[1]; - assign router_26_22_to_router_26_21_req = router_26_22_req_out[2]; - assign router_26_22_to_router_25_22_req = router_26_22_req_out[3]; - assign router_26_22_to_magia_tile_ni_26_22_req = router_26_22_req_out[4]; - - assign router_26_22_rsp_in[0] = router_26_23_to_router_26_22_rsp; - assign router_26_22_rsp_in[1] = router_27_22_to_router_26_22_rsp; - assign router_26_22_rsp_in[2] = router_26_21_to_router_26_22_rsp; - assign router_26_22_rsp_in[3] = router_25_22_to_router_26_22_rsp; - assign router_26_22_rsp_in[4] = magia_tile_ni_26_22_to_router_26_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_22_req_in), - .floo_rsp_o (router_26_22_rsp_out), - .floo_req_o (router_26_22_req_out), - .floo_rsp_i (router_26_22_rsp_in) -); - - -floo_req_t [4:0] router_26_23_req_in; -floo_rsp_t [4:0] router_26_23_rsp_out; -floo_req_t [4:0] router_26_23_req_out; -floo_rsp_t [4:0] router_26_23_rsp_in; - - assign router_26_23_req_in[0] = router_26_24_to_router_26_23_req; - assign router_26_23_req_in[1] = router_27_23_to_router_26_23_req; - assign router_26_23_req_in[2] = router_26_22_to_router_26_23_req; - assign router_26_23_req_in[3] = router_25_23_to_router_26_23_req; - assign router_26_23_req_in[4] = magia_tile_ni_26_23_to_router_26_23_req; - - assign router_26_23_to_router_26_24_rsp = router_26_23_rsp_out[0]; - assign router_26_23_to_router_27_23_rsp = router_26_23_rsp_out[1]; - assign router_26_23_to_router_26_22_rsp = router_26_23_rsp_out[2]; - assign router_26_23_to_router_25_23_rsp = router_26_23_rsp_out[3]; - assign router_26_23_to_magia_tile_ni_26_23_rsp = router_26_23_rsp_out[4]; - - assign router_26_23_to_router_26_24_req = router_26_23_req_out[0]; - assign router_26_23_to_router_27_23_req = router_26_23_req_out[1]; - assign router_26_23_to_router_26_22_req = router_26_23_req_out[2]; - assign router_26_23_to_router_25_23_req = router_26_23_req_out[3]; - assign router_26_23_to_magia_tile_ni_26_23_req = router_26_23_req_out[4]; - - assign router_26_23_rsp_in[0] = router_26_24_to_router_26_23_rsp; - assign router_26_23_rsp_in[1] = router_27_23_to_router_26_23_rsp; - assign router_26_23_rsp_in[2] = router_26_22_to_router_26_23_rsp; - assign router_26_23_rsp_in[3] = router_25_23_to_router_26_23_rsp; - assign router_26_23_rsp_in[4] = magia_tile_ni_26_23_to_router_26_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_23_req_in), - .floo_rsp_o (router_26_23_rsp_out), - .floo_req_o (router_26_23_req_out), - .floo_rsp_i (router_26_23_rsp_in) -); - - -floo_req_t [4:0] router_26_24_req_in; -floo_rsp_t [4:0] router_26_24_rsp_out; -floo_req_t [4:0] router_26_24_req_out; -floo_rsp_t [4:0] router_26_24_rsp_in; - - assign router_26_24_req_in[0] = router_26_25_to_router_26_24_req; - assign router_26_24_req_in[1] = router_27_24_to_router_26_24_req; - assign router_26_24_req_in[2] = router_26_23_to_router_26_24_req; - assign router_26_24_req_in[3] = router_25_24_to_router_26_24_req; - assign router_26_24_req_in[4] = magia_tile_ni_26_24_to_router_26_24_req; - - assign router_26_24_to_router_26_25_rsp = router_26_24_rsp_out[0]; - assign router_26_24_to_router_27_24_rsp = router_26_24_rsp_out[1]; - assign router_26_24_to_router_26_23_rsp = router_26_24_rsp_out[2]; - assign router_26_24_to_router_25_24_rsp = router_26_24_rsp_out[3]; - assign router_26_24_to_magia_tile_ni_26_24_rsp = router_26_24_rsp_out[4]; - - assign router_26_24_to_router_26_25_req = router_26_24_req_out[0]; - assign router_26_24_to_router_27_24_req = router_26_24_req_out[1]; - assign router_26_24_to_router_26_23_req = router_26_24_req_out[2]; - assign router_26_24_to_router_25_24_req = router_26_24_req_out[3]; - assign router_26_24_to_magia_tile_ni_26_24_req = router_26_24_req_out[4]; - - assign router_26_24_rsp_in[0] = router_26_25_to_router_26_24_rsp; - assign router_26_24_rsp_in[1] = router_27_24_to_router_26_24_rsp; - assign router_26_24_rsp_in[2] = router_26_23_to_router_26_24_rsp; - assign router_26_24_rsp_in[3] = router_25_24_to_router_26_24_rsp; - assign router_26_24_rsp_in[4] = magia_tile_ni_26_24_to_router_26_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_24_req_in), - .floo_rsp_o (router_26_24_rsp_out), - .floo_req_o (router_26_24_req_out), - .floo_rsp_i (router_26_24_rsp_in) -); - - -floo_req_t [4:0] router_26_25_req_in; -floo_rsp_t [4:0] router_26_25_rsp_out; -floo_req_t [4:0] router_26_25_req_out; -floo_rsp_t [4:0] router_26_25_rsp_in; - - assign router_26_25_req_in[0] = router_26_26_to_router_26_25_req; - assign router_26_25_req_in[1] = router_27_25_to_router_26_25_req; - assign router_26_25_req_in[2] = router_26_24_to_router_26_25_req; - assign router_26_25_req_in[3] = router_25_25_to_router_26_25_req; - assign router_26_25_req_in[4] = magia_tile_ni_26_25_to_router_26_25_req; - - assign router_26_25_to_router_26_26_rsp = router_26_25_rsp_out[0]; - assign router_26_25_to_router_27_25_rsp = router_26_25_rsp_out[1]; - assign router_26_25_to_router_26_24_rsp = router_26_25_rsp_out[2]; - assign router_26_25_to_router_25_25_rsp = router_26_25_rsp_out[3]; - assign router_26_25_to_magia_tile_ni_26_25_rsp = router_26_25_rsp_out[4]; - - assign router_26_25_to_router_26_26_req = router_26_25_req_out[0]; - assign router_26_25_to_router_27_25_req = router_26_25_req_out[1]; - assign router_26_25_to_router_26_24_req = router_26_25_req_out[2]; - assign router_26_25_to_router_25_25_req = router_26_25_req_out[3]; - assign router_26_25_to_magia_tile_ni_26_25_req = router_26_25_req_out[4]; - - assign router_26_25_rsp_in[0] = router_26_26_to_router_26_25_rsp; - assign router_26_25_rsp_in[1] = router_27_25_to_router_26_25_rsp; - assign router_26_25_rsp_in[2] = router_26_24_to_router_26_25_rsp; - assign router_26_25_rsp_in[3] = router_25_25_to_router_26_25_rsp; - assign router_26_25_rsp_in[4] = magia_tile_ni_26_25_to_router_26_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_25_req_in), - .floo_rsp_o (router_26_25_rsp_out), - .floo_req_o (router_26_25_req_out), - .floo_rsp_i (router_26_25_rsp_in) -); - - -floo_req_t [4:0] router_26_26_req_in; -floo_rsp_t [4:0] router_26_26_rsp_out; -floo_req_t [4:0] router_26_26_req_out; -floo_rsp_t [4:0] router_26_26_rsp_in; - - assign router_26_26_req_in[0] = router_26_27_to_router_26_26_req; - assign router_26_26_req_in[1] = router_27_26_to_router_26_26_req; - assign router_26_26_req_in[2] = router_26_25_to_router_26_26_req; - assign router_26_26_req_in[3] = router_25_26_to_router_26_26_req; - assign router_26_26_req_in[4] = magia_tile_ni_26_26_to_router_26_26_req; - - assign router_26_26_to_router_26_27_rsp = router_26_26_rsp_out[0]; - assign router_26_26_to_router_27_26_rsp = router_26_26_rsp_out[1]; - assign router_26_26_to_router_26_25_rsp = router_26_26_rsp_out[2]; - assign router_26_26_to_router_25_26_rsp = router_26_26_rsp_out[3]; - assign router_26_26_to_magia_tile_ni_26_26_rsp = router_26_26_rsp_out[4]; - - assign router_26_26_to_router_26_27_req = router_26_26_req_out[0]; - assign router_26_26_to_router_27_26_req = router_26_26_req_out[1]; - assign router_26_26_to_router_26_25_req = router_26_26_req_out[2]; - assign router_26_26_to_router_25_26_req = router_26_26_req_out[3]; - assign router_26_26_to_magia_tile_ni_26_26_req = router_26_26_req_out[4]; - - assign router_26_26_rsp_in[0] = router_26_27_to_router_26_26_rsp; - assign router_26_26_rsp_in[1] = router_27_26_to_router_26_26_rsp; - assign router_26_26_rsp_in[2] = router_26_25_to_router_26_26_rsp; - assign router_26_26_rsp_in[3] = router_25_26_to_router_26_26_rsp; - assign router_26_26_rsp_in[4] = magia_tile_ni_26_26_to_router_26_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_26_req_in), - .floo_rsp_o (router_26_26_rsp_out), - .floo_req_o (router_26_26_req_out), - .floo_rsp_i (router_26_26_rsp_in) -); - - -floo_req_t [4:0] router_26_27_req_in; -floo_rsp_t [4:0] router_26_27_rsp_out; -floo_req_t [4:0] router_26_27_req_out; -floo_rsp_t [4:0] router_26_27_rsp_in; - - assign router_26_27_req_in[0] = router_26_28_to_router_26_27_req; - assign router_26_27_req_in[1] = router_27_27_to_router_26_27_req; - assign router_26_27_req_in[2] = router_26_26_to_router_26_27_req; - assign router_26_27_req_in[3] = router_25_27_to_router_26_27_req; - assign router_26_27_req_in[4] = magia_tile_ni_26_27_to_router_26_27_req; - - assign router_26_27_to_router_26_28_rsp = router_26_27_rsp_out[0]; - assign router_26_27_to_router_27_27_rsp = router_26_27_rsp_out[1]; - assign router_26_27_to_router_26_26_rsp = router_26_27_rsp_out[2]; - assign router_26_27_to_router_25_27_rsp = router_26_27_rsp_out[3]; - assign router_26_27_to_magia_tile_ni_26_27_rsp = router_26_27_rsp_out[4]; - - assign router_26_27_to_router_26_28_req = router_26_27_req_out[0]; - assign router_26_27_to_router_27_27_req = router_26_27_req_out[1]; - assign router_26_27_to_router_26_26_req = router_26_27_req_out[2]; - assign router_26_27_to_router_25_27_req = router_26_27_req_out[3]; - assign router_26_27_to_magia_tile_ni_26_27_req = router_26_27_req_out[4]; - - assign router_26_27_rsp_in[0] = router_26_28_to_router_26_27_rsp; - assign router_26_27_rsp_in[1] = router_27_27_to_router_26_27_rsp; - assign router_26_27_rsp_in[2] = router_26_26_to_router_26_27_rsp; - assign router_26_27_rsp_in[3] = router_25_27_to_router_26_27_rsp; - assign router_26_27_rsp_in[4] = magia_tile_ni_26_27_to_router_26_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_27_req_in), - .floo_rsp_o (router_26_27_rsp_out), - .floo_req_o (router_26_27_req_out), - .floo_rsp_i (router_26_27_rsp_in) -); - - -floo_req_t [4:0] router_26_28_req_in; -floo_rsp_t [4:0] router_26_28_rsp_out; -floo_req_t [4:0] router_26_28_req_out; -floo_rsp_t [4:0] router_26_28_rsp_in; - - assign router_26_28_req_in[0] = router_26_29_to_router_26_28_req; - assign router_26_28_req_in[1] = router_27_28_to_router_26_28_req; - assign router_26_28_req_in[2] = router_26_27_to_router_26_28_req; - assign router_26_28_req_in[3] = router_25_28_to_router_26_28_req; - assign router_26_28_req_in[4] = magia_tile_ni_26_28_to_router_26_28_req; - - assign router_26_28_to_router_26_29_rsp = router_26_28_rsp_out[0]; - assign router_26_28_to_router_27_28_rsp = router_26_28_rsp_out[1]; - assign router_26_28_to_router_26_27_rsp = router_26_28_rsp_out[2]; - assign router_26_28_to_router_25_28_rsp = router_26_28_rsp_out[3]; - assign router_26_28_to_magia_tile_ni_26_28_rsp = router_26_28_rsp_out[4]; - - assign router_26_28_to_router_26_29_req = router_26_28_req_out[0]; - assign router_26_28_to_router_27_28_req = router_26_28_req_out[1]; - assign router_26_28_to_router_26_27_req = router_26_28_req_out[2]; - assign router_26_28_to_router_25_28_req = router_26_28_req_out[3]; - assign router_26_28_to_magia_tile_ni_26_28_req = router_26_28_req_out[4]; - - assign router_26_28_rsp_in[0] = router_26_29_to_router_26_28_rsp; - assign router_26_28_rsp_in[1] = router_27_28_to_router_26_28_rsp; - assign router_26_28_rsp_in[2] = router_26_27_to_router_26_28_rsp; - assign router_26_28_rsp_in[3] = router_25_28_to_router_26_28_rsp; - assign router_26_28_rsp_in[4] = magia_tile_ni_26_28_to_router_26_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_28_req_in), - .floo_rsp_o (router_26_28_rsp_out), - .floo_req_o (router_26_28_req_out), - .floo_rsp_i (router_26_28_rsp_in) -); - - -floo_req_t [4:0] router_26_29_req_in; -floo_rsp_t [4:0] router_26_29_rsp_out; -floo_req_t [4:0] router_26_29_req_out; -floo_rsp_t [4:0] router_26_29_rsp_in; - - assign router_26_29_req_in[0] = router_26_30_to_router_26_29_req; - assign router_26_29_req_in[1] = router_27_29_to_router_26_29_req; - assign router_26_29_req_in[2] = router_26_28_to_router_26_29_req; - assign router_26_29_req_in[3] = router_25_29_to_router_26_29_req; - assign router_26_29_req_in[4] = magia_tile_ni_26_29_to_router_26_29_req; - - assign router_26_29_to_router_26_30_rsp = router_26_29_rsp_out[0]; - assign router_26_29_to_router_27_29_rsp = router_26_29_rsp_out[1]; - assign router_26_29_to_router_26_28_rsp = router_26_29_rsp_out[2]; - assign router_26_29_to_router_25_29_rsp = router_26_29_rsp_out[3]; - assign router_26_29_to_magia_tile_ni_26_29_rsp = router_26_29_rsp_out[4]; - - assign router_26_29_to_router_26_30_req = router_26_29_req_out[0]; - assign router_26_29_to_router_27_29_req = router_26_29_req_out[1]; - assign router_26_29_to_router_26_28_req = router_26_29_req_out[2]; - assign router_26_29_to_router_25_29_req = router_26_29_req_out[3]; - assign router_26_29_to_magia_tile_ni_26_29_req = router_26_29_req_out[4]; - - assign router_26_29_rsp_in[0] = router_26_30_to_router_26_29_rsp; - assign router_26_29_rsp_in[1] = router_27_29_to_router_26_29_rsp; - assign router_26_29_rsp_in[2] = router_26_28_to_router_26_29_rsp; - assign router_26_29_rsp_in[3] = router_25_29_to_router_26_29_rsp; - assign router_26_29_rsp_in[4] = magia_tile_ni_26_29_to_router_26_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_29_req_in), - .floo_rsp_o (router_26_29_rsp_out), - .floo_req_o (router_26_29_req_out), - .floo_rsp_i (router_26_29_rsp_in) -); - - -floo_req_t [4:0] router_26_30_req_in; -floo_rsp_t [4:0] router_26_30_rsp_out; -floo_req_t [4:0] router_26_30_req_out; -floo_rsp_t [4:0] router_26_30_rsp_in; - - assign router_26_30_req_in[0] = router_26_31_to_router_26_30_req; - assign router_26_30_req_in[1] = router_27_30_to_router_26_30_req; - assign router_26_30_req_in[2] = router_26_29_to_router_26_30_req; - assign router_26_30_req_in[3] = router_25_30_to_router_26_30_req; - assign router_26_30_req_in[4] = magia_tile_ni_26_30_to_router_26_30_req; - - assign router_26_30_to_router_26_31_rsp = router_26_30_rsp_out[0]; - assign router_26_30_to_router_27_30_rsp = router_26_30_rsp_out[1]; - assign router_26_30_to_router_26_29_rsp = router_26_30_rsp_out[2]; - assign router_26_30_to_router_25_30_rsp = router_26_30_rsp_out[3]; - assign router_26_30_to_magia_tile_ni_26_30_rsp = router_26_30_rsp_out[4]; - - assign router_26_30_to_router_26_31_req = router_26_30_req_out[0]; - assign router_26_30_to_router_27_30_req = router_26_30_req_out[1]; - assign router_26_30_to_router_26_29_req = router_26_30_req_out[2]; - assign router_26_30_to_router_25_30_req = router_26_30_req_out[3]; - assign router_26_30_to_magia_tile_ni_26_30_req = router_26_30_req_out[4]; - - assign router_26_30_rsp_in[0] = router_26_31_to_router_26_30_rsp; - assign router_26_30_rsp_in[1] = router_27_30_to_router_26_30_rsp; - assign router_26_30_rsp_in[2] = router_26_29_to_router_26_30_rsp; - assign router_26_30_rsp_in[3] = router_25_30_to_router_26_30_rsp; - assign router_26_30_rsp_in[4] = magia_tile_ni_26_30_to_router_26_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_30_req_in), - .floo_rsp_o (router_26_30_rsp_out), - .floo_req_o (router_26_30_req_out), - .floo_rsp_i (router_26_30_rsp_in) -); - - -floo_req_t [4:0] router_26_31_req_in; -floo_rsp_t [4:0] router_26_31_rsp_out; -floo_req_t [4:0] router_26_31_req_out; -floo_rsp_t [4:0] router_26_31_rsp_in; - - assign router_26_31_req_in[0] = '0; - assign router_26_31_req_in[1] = router_27_31_to_router_26_31_req; - assign router_26_31_req_in[2] = router_26_30_to_router_26_31_req; - assign router_26_31_req_in[3] = router_25_31_to_router_26_31_req; - assign router_26_31_req_in[4] = magia_tile_ni_26_31_to_router_26_31_req; - - assign router_26_31_to_router_27_31_rsp = router_26_31_rsp_out[1]; - assign router_26_31_to_router_26_30_rsp = router_26_31_rsp_out[2]; - assign router_26_31_to_router_25_31_rsp = router_26_31_rsp_out[3]; - assign router_26_31_to_magia_tile_ni_26_31_rsp = router_26_31_rsp_out[4]; - - assign router_26_31_to_router_27_31_req = router_26_31_req_out[1]; - assign router_26_31_to_router_26_30_req = router_26_31_req_out[2]; - assign router_26_31_to_router_25_31_req = router_26_31_req_out[3]; - assign router_26_31_to_magia_tile_ni_26_31_req = router_26_31_req_out[4]; - - assign router_26_31_rsp_in[0] = '0; - assign router_26_31_rsp_in[1] = router_27_31_to_router_26_31_rsp; - assign router_26_31_rsp_in[2] = router_26_30_to_router_26_31_rsp; - assign router_26_31_rsp_in[3] = router_25_31_to_router_26_31_rsp; - assign router_26_31_rsp_in[4] = magia_tile_ni_26_31_to_router_26_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_26_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 27, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_26_31_req_in), - .floo_rsp_o (router_26_31_rsp_out), - .floo_req_o (router_26_31_req_out), - .floo_rsp_i (router_26_31_rsp_in) -); - - -floo_req_t [4:0] router_27_0_req_in; -floo_rsp_t [4:0] router_27_0_rsp_out; -floo_req_t [4:0] router_27_0_req_out; -floo_rsp_t [4:0] router_27_0_rsp_in; - - assign router_27_0_req_in[0] = router_27_1_to_router_27_0_req; - assign router_27_0_req_in[1] = router_28_0_to_router_27_0_req; - assign router_27_0_req_in[2] = '0; - assign router_27_0_req_in[3] = router_26_0_to_router_27_0_req; - assign router_27_0_req_in[4] = magia_tile_ni_27_0_to_router_27_0_req; - - assign router_27_0_to_router_27_1_rsp = router_27_0_rsp_out[0]; - assign router_27_0_to_router_28_0_rsp = router_27_0_rsp_out[1]; - assign router_27_0_to_router_26_0_rsp = router_27_0_rsp_out[3]; - assign router_27_0_to_magia_tile_ni_27_0_rsp = router_27_0_rsp_out[4]; - - assign router_27_0_to_router_27_1_req = router_27_0_req_out[0]; - assign router_27_0_to_router_28_0_req = router_27_0_req_out[1]; - assign router_27_0_to_router_26_0_req = router_27_0_req_out[3]; - assign router_27_0_to_magia_tile_ni_27_0_req = router_27_0_req_out[4]; - - assign router_27_0_rsp_in[0] = router_27_1_to_router_27_0_rsp; - assign router_27_0_rsp_in[1] = router_28_0_to_router_27_0_rsp; - assign router_27_0_rsp_in[2] = '0; - assign router_27_0_rsp_in[3] = router_26_0_to_router_27_0_rsp; - assign router_27_0_rsp_in[4] = magia_tile_ni_27_0_to_router_27_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_0_req_in), - .floo_rsp_o (router_27_0_rsp_out), - .floo_req_o (router_27_0_req_out), - .floo_rsp_i (router_27_0_rsp_in) -); - - -floo_req_t [4:0] router_27_1_req_in; -floo_rsp_t [4:0] router_27_1_rsp_out; -floo_req_t [4:0] router_27_1_req_out; -floo_rsp_t [4:0] router_27_1_rsp_in; - - assign router_27_1_req_in[0] = router_27_2_to_router_27_1_req; - assign router_27_1_req_in[1] = router_28_1_to_router_27_1_req; - assign router_27_1_req_in[2] = router_27_0_to_router_27_1_req; - assign router_27_1_req_in[3] = router_26_1_to_router_27_1_req; - assign router_27_1_req_in[4] = magia_tile_ni_27_1_to_router_27_1_req; - - assign router_27_1_to_router_27_2_rsp = router_27_1_rsp_out[0]; - assign router_27_1_to_router_28_1_rsp = router_27_1_rsp_out[1]; - assign router_27_1_to_router_27_0_rsp = router_27_1_rsp_out[2]; - assign router_27_1_to_router_26_1_rsp = router_27_1_rsp_out[3]; - assign router_27_1_to_magia_tile_ni_27_1_rsp = router_27_1_rsp_out[4]; - - assign router_27_1_to_router_27_2_req = router_27_1_req_out[0]; - assign router_27_1_to_router_28_1_req = router_27_1_req_out[1]; - assign router_27_1_to_router_27_0_req = router_27_1_req_out[2]; - assign router_27_1_to_router_26_1_req = router_27_1_req_out[3]; - assign router_27_1_to_magia_tile_ni_27_1_req = router_27_1_req_out[4]; - - assign router_27_1_rsp_in[0] = router_27_2_to_router_27_1_rsp; - assign router_27_1_rsp_in[1] = router_28_1_to_router_27_1_rsp; - assign router_27_1_rsp_in[2] = router_27_0_to_router_27_1_rsp; - assign router_27_1_rsp_in[3] = router_26_1_to_router_27_1_rsp; - assign router_27_1_rsp_in[4] = magia_tile_ni_27_1_to_router_27_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_1_req_in), - .floo_rsp_o (router_27_1_rsp_out), - .floo_req_o (router_27_1_req_out), - .floo_rsp_i (router_27_1_rsp_in) -); - - -floo_req_t [4:0] router_27_2_req_in; -floo_rsp_t [4:0] router_27_2_rsp_out; -floo_req_t [4:0] router_27_2_req_out; -floo_rsp_t [4:0] router_27_2_rsp_in; - - assign router_27_2_req_in[0] = router_27_3_to_router_27_2_req; - assign router_27_2_req_in[1] = router_28_2_to_router_27_2_req; - assign router_27_2_req_in[2] = router_27_1_to_router_27_2_req; - assign router_27_2_req_in[3] = router_26_2_to_router_27_2_req; - assign router_27_2_req_in[4] = magia_tile_ni_27_2_to_router_27_2_req; - - assign router_27_2_to_router_27_3_rsp = router_27_2_rsp_out[0]; - assign router_27_2_to_router_28_2_rsp = router_27_2_rsp_out[1]; - assign router_27_2_to_router_27_1_rsp = router_27_2_rsp_out[2]; - assign router_27_2_to_router_26_2_rsp = router_27_2_rsp_out[3]; - assign router_27_2_to_magia_tile_ni_27_2_rsp = router_27_2_rsp_out[4]; - - assign router_27_2_to_router_27_3_req = router_27_2_req_out[0]; - assign router_27_2_to_router_28_2_req = router_27_2_req_out[1]; - assign router_27_2_to_router_27_1_req = router_27_2_req_out[2]; - assign router_27_2_to_router_26_2_req = router_27_2_req_out[3]; - assign router_27_2_to_magia_tile_ni_27_2_req = router_27_2_req_out[4]; - - assign router_27_2_rsp_in[0] = router_27_3_to_router_27_2_rsp; - assign router_27_2_rsp_in[1] = router_28_2_to_router_27_2_rsp; - assign router_27_2_rsp_in[2] = router_27_1_to_router_27_2_rsp; - assign router_27_2_rsp_in[3] = router_26_2_to_router_27_2_rsp; - assign router_27_2_rsp_in[4] = magia_tile_ni_27_2_to_router_27_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_2_req_in), - .floo_rsp_o (router_27_2_rsp_out), - .floo_req_o (router_27_2_req_out), - .floo_rsp_i (router_27_2_rsp_in) -); - - -floo_req_t [4:0] router_27_3_req_in; -floo_rsp_t [4:0] router_27_3_rsp_out; -floo_req_t [4:0] router_27_3_req_out; -floo_rsp_t [4:0] router_27_3_rsp_in; - - assign router_27_3_req_in[0] = router_27_4_to_router_27_3_req; - assign router_27_3_req_in[1] = router_28_3_to_router_27_3_req; - assign router_27_3_req_in[2] = router_27_2_to_router_27_3_req; - assign router_27_3_req_in[3] = router_26_3_to_router_27_3_req; - assign router_27_3_req_in[4] = magia_tile_ni_27_3_to_router_27_3_req; - - assign router_27_3_to_router_27_4_rsp = router_27_3_rsp_out[0]; - assign router_27_3_to_router_28_3_rsp = router_27_3_rsp_out[1]; - assign router_27_3_to_router_27_2_rsp = router_27_3_rsp_out[2]; - assign router_27_3_to_router_26_3_rsp = router_27_3_rsp_out[3]; - assign router_27_3_to_magia_tile_ni_27_3_rsp = router_27_3_rsp_out[4]; - - assign router_27_3_to_router_27_4_req = router_27_3_req_out[0]; - assign router_27_3_to_router_28_3_req = router_27_3_req_out[1]; - assign router_27_3_to_router_27_2_req = router_27_3_req_out[2]; - assign router_27_3_to_router_26_3_req = router_27_3_req_out[3]; - assign router_27_3_to_magia_tile_ni_27_3_req = router_27_3_req_out[4]; - - assign router_27_3_rsp_in[0] = router_27_4_to_router_27_3_rsp; - assign router_27_3_rsp_in[1] = router_28_3_to_router_27_3_rsp; - assign router_27_3_rsp_in[2] = router_27_2_to_router_27_3_rsp; - assign router_27_3_rsp_in[3] = router_26_3_to_router_27_3_rsp; - assign router_27_3_rsp_in[4] = magia_tile_ni_27_3_to_router_27_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_3_req_in), - .floo_rsp_o (router_27_3_rsp_out), - .floo_req_o (router_27_3_req_out), - .floo_rsp_i (router_27_3_rsp_in) -); - - -floo_req_t [4:0] router_27_4_req_in; -floo_rsp_t [4:0] router_27_4_rsp_out; -floo_req_t [4:0] router_27_4_req_out; -floo_rsp_t [4:0] router_27_4_rsp_in; - - assign router_27_4_req_in[0] = router_27_5_to_router_27_4_req; - assign router_27_4_req_in[1] = router_28_4_to_router_27_4_req; - assign router_27_4_req_in[2] = router_27_3_to_router_27_4_req; - assign router_27_4_req_in[3] = router_26_4_to_router_27_4_req; - assign router_27_4_req_in[4] = magia_tile_ni_27_4_to_router_27_4_req; - - assign router_27_4_to_router_27_5_rsp = router_27_4_rsp_out[0]; - assign router_27_4_to_router_28_4_rsp = router_27_4_rsp_out[1]; - assign router_27_4_to_router_27_3_rsp = router_27_4_rsp_out[2]; - assign router_27_4_to_router_26_4_rsp = router_27_4_rsp_out[3]; - assign router_27_4_to_magia_tile_ni_27_4_rsp = router_27_4_rsp_out[4]; - - assign router_27_4_to_router_27_5_req = router_27_4_req_out[0]; - assign router_27_4_to_router_28_4_req = router_27_4_req_out[1]; - assign router_27_4_to_router_27_3_req = router_27_4_req_out[2]; - assign router_27_4_to_router_26_4_req = router_27_4_req_out[3]; - assign router_27_4_to_magia_tile_ni_27_4_req = router_27_4_req_out[4]; - - assign router_27_4_rsp_in[0] = router_27_5_to_router_27_4_rsp; - assign router_27_4_rsp_in[1] = router_28_4_to_router_27_4_rsp; - assign router_27_4_rsp_in[2] = router_27_3_to_router_27_4_rsp; - assign router_27_4_rsp_in[3] = router_26_4_to_router_27_4_rsp; - assign router_27_4_rsp_in[4] = magia_tile_ni_27_4_to_router_27_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_4_req_in), - .floo_rsp_o (router_27_4_rsp_out), - .floo_req_o (router_27_4_req_out), - .floo_rsp_i (router_27_4_rsp_in) -); - - -floo_req_t [4:0] router_27_5_req_in; -floo_rsp_t [4:0] router_27_5_rsp_out; -floo_req_t [4:0] router_27_5_req_out; -floo_rsp_t [4:0] router_27_5_rsp_in; - - assign router_27_5_req_in[0] = router_27_6_to_router_27_5_req; - assign router_27_5_req_in[1] = router_28_5_to_router_27_5_req; - assign router_27_5_req_in[2] = router_27_4_to_router_27_5_req; - assign router_27_5_req_in[3] = router_26_5_to_router_27_5_req; - assign router_27_5_req_in[4] = magia_tile_ni_27_5_to_router_27_5_req; - - assign router_27_5_to_router_27_6_rsp = router_27_5_rsp_out[0]; - assign router_27_5_to_router_28_5_rsp = router_27_5_rsp_out[1]; - assign router_27_5_to_router_27_4_rsp = router_27_5_rsp_out[2]; - assign router_27_5_to_router_26_5_rsp = router_27_5_rsp_out[3]; - assign router_27_5_to_magia_tile_ni_27_5_rsp = router_27_5_rsp_out[4]; - - assign router_27_5_to_router_27_6_req = router_27_5_req_out[0]; - assign router_27_5_to_router_28_5_req = router_27_5_req_out[1]; - assign router_27_5_to_router_27_4_req = router_27_5_req_out[2]; - assign router_27_5_to_router_26_5_req = router_27_5_req_out[3]; - assign router_27_5_to_magia_tile_ni_27_5_req = router_27_5_req_out[4]; - - assign router_27_5_rsp_in[0] = router_27_6_to_router_27_5_rsp; - assign router_27_5_rsp_in[1] = router_28_5_to_router_27_5_rsp; - assign router_27_5_rsp_in[2] = router_27_4_to_router_27_5_rsp; - assign router_27_5_rsp_in[3] = router_26_5_to_router_27_5_rsp; - assign router_27_5_rsp_in[4] = magia_tile_ni_27_5_to_router_27_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_5_req_in), - .floo_rsp_o (router_27_5_rsp_out), - .floo_req_o (router_27_5_req_out), - .floo_rsp_i (router_27_5_rsp_in) -); - - -floo_req_t [4:0] router_27_6_req_in; -floo_rsp_t [4:0] router_27_6_rsp_out; -floo_req_t [4:0] router_27_6_req_out; -floo_rsp_t [4:0] router_27_6_rsp_in; - - assign router_27_6_req_in[0] = router_27_7_to_router_27_6_req; - assign router_27_6_req_in[1] = router_28_6_to_router_27_6_req; - assign router_27_6_req_in[2] = router_27_5_to_router_27_6_req; - assign router_27_6_req_in[3] = router_26_6_to_router_27_6_req; - assign router_27_6_req_in[4] = magia_tile_ni_27_6_to_router_27_6_req; - - assign router_27_6_to_router_27_7_rsp = router_27_6_rsp_out[0]; - assign router_27_6_to_router_28_6_rsp = router_27_6_rsp_out[1]; - assign router_27_6_to_router_27_5_rsp = router_27_6_rsp_out[2]; - assign router_27_6_to_router_26_6_rsp = router_27_6_rsp_out[3]; - assign router_27_6_to_magia_tile_ni_27_6_rsp = router_27_6_rsp_out[4]; - - assign router_27_6_to_router_27_7_req = router_27_6_req_out[0]; - assign router_27_6_to_router_28_6_req = router_27_6_req_out[1]; - assign router_27_6_to_router_27_5_req = router_27_6_req_out[2]; - assign router_27_6_to_router_26_6_req = router_27_6_req_out[3]; - assign router_27_6_to_magia_tile_ni_27_6_req = router_27_6_req_out[4]; - - assign router_27_6_rsp_in[0] = router_27_7_to_router_27_6_rsp; - assign router_27_6_rsp_in[1] = router_28_6_to_router_27_6_rsp; - assign router_27_6_rsp_in[2] = router_27_5_to_router_27_6_rsp; - assign router_27_6_rsp_in[3] = router_26_6_to_router_27_6_rsp; - assign router_27_6_rsp_in[4] = magia_tile_ni_27_6_to_router_27_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_6_req_in), - .floo_rsp_o (router_27_6_rsp_out), - .floo_req_o (router_27_6_req_out), - .floo_rsp_i (router_27_6_rsp_in) -); - - -floo_req_t [4:0] router_27_7_req_in; -floo_rsp_t [4:0] router_27_7_rsp_out; -floo_req_t [4:0] router_27_7_req_out; -floo_rsp_t [4:0] router_27_7_rsp_in; - - assign router_27_7_req_in[0] = router_27_8_to_router_27_7_req; - assign router_27_7_req_in[1] = router_28_7_to_router_27_7_req; - assign router_27_7_req_in[2] = router_27_6_to_router_27_7_req; - assign router_27_7_req_in[3] = router_26_7_to_router_27_7_req; - assign router_27_7_req_in[4] = magia_tile_ni_27_7_to_router_27_7_req; - - assign router_27_7_to_router_27_8_rsp = router_27_7_rsp_out[0]; - assign router_27_7_to_router_28_7_rsp = router_27_7_rsp_out[1]; - assign router_27_7_to_router_27_6_rsp = router_27_7_rsp_out[2]; - assign router_27_7_to_router_26_7_rsp = router_27_7_rsp_out[3]; - assign router_27_7_to_magia_tile_ni_27_7_rsp = router_27_7_rsp_out[4]; - - assign router_27_7_to_router_27_8_req = router_27_7_req_out[0]; - assign router_27_7_to_router_28_7_req = router_27_7_req_out[1]; - assign router_27_7_to_router_27_6_req = router_27_7_req_out[2]; - assign router_27_7_to_router_26_7_req = router_27_7_req_out[3]; - assign router_27_7_to_magia_tile_ni_27_7_req = router_27_7_req_out[4]; - - assign router_27_7_rsp_in[0] = router_27_8_to_router_27_7_rsp; - assign router_27_7_rsp_in[1] = router_28_7_to_router_27_7_rsp; - assign router_27_7_rsp_in[2] = router_27_6_to_router_27_7_rsp; - assign router_27_7_rsp_in[3] = router_26_7_to_router_27_7_rsp; - assign router_27_7_rsp_in[4] = magia_tile_ni_27_7_to_router_27_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_7_req_in), - .floo_rsp_o (router_27_7_rsp_out), - .floo_req_o (router_27_7_req_out), - .floo_rsp_i (router_27_7_rsp_in) -); - - -floo_req_t [4:0] router_27_8_req_in; -floo_rsp_t [4:0] router_27_8_rsp_out; -floo_req_t [4:0] router_27_8_req_out; -floo_rsp_t [4:0] router_27_8_rsp_in; - - assign router_27_8_req_in[0] = router_27_9_to_router_27_8_req; - assign router_27_8_req_in[1] = router_28_8_to_router_27_8_req; - assign router_27_8_req_in[2] = router_27_7_to_router_27_8_req; - assign router_27_8_req_in[3] = router_26_8_to_router_27_8_req; - assign router_27_8_req_in[4] = magia_tile_ni_27_8_to_router_27_8_req; - - assign router_27_8_to_router_27_9_rsp = router_27_8_rsp_out[0]; - assign router_27_8_to_router_28_8_rsp = router_27_8_rsp_out[1]; - assign router_27_8_to_router_27_7_rsp = router_27_8_rsp_out[2]; - assign router_27_8_to_router_26_8_rsp = router_27_8_rsp_out[3]; - assign router_27_8_to_magia_tile_ni_27_8_rsp = router_27_8_rsp_out[4]; - - assign router_27_8_to_router_27_9_req = router_27_8_req_out[0]; - assign router_27_8_to_router_28_8_req = router_27_8_req_out[1]; - assign router_27_8_to_router_27_7_req = router_27_8_req_out[2]; - assign router_27_8_to_router_26_8_req = router_27_8_req_out[3]; - assign router_27_8_to_magia_tile_ni_27_8_req = router_27_8_req_out[4]; - - assign router_27_8_rsp_in[0] = router_27_9_to_router_27_8_rsp; - assign router_27_8_rsp_in[1] = router_28_8_to_router_27_8_rsp; - assign router_27_8_rsp_in[2] = router_27_7_to_router_27_8_rsp; - assign router_27_8_rsp_in[3] = router_26_8_to_router_27_8_rsp; - assign router_27_8_rsp_in[4] = magia_tile_ni_27_8_to_router_27_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_8_req_in), - .floo_rsp_o (router_27_8_rsp_out), - .floo_req_o (router_27_8_req_out), - .floo_rsp_i (router_27_8_rsp_in) -); - - -floo_req_t [4:0] router_27_9_req_in; -floo_rsp_t [4:0] router_27_9_rsp_out; -floo_req_t [4:0] router_27_9_req_out; -floo_rsp_t [4:0] router_27_9_rsp_in; - - assign router_27_9_req_in[0] = router_27_10_to_router_27_9_req; - assign router_27_9_req_in[1] = router_28_9_to_router_27_9_req; - assign router_27_9_req_in[2] = router_27_8_to_router_27_9_req; - assign router_27_9_req_in[3] = router_26_9_to_router_27_9_req; - assign router_27_9_req_in[4] = magia_tile_ni_27_9_to_router_27_9_req; - - assign router_27_9_to_router_27_10_rsp = router_27_9_rsp_out[0]; - assign router_27_9_to_router_28_9_rsp = router_27_9_rsp_out[1]; - assign router_27_9_to_router_27_8_rsp = router_27_9_rsp_out[2]; - assign router_27_9_to_router_26_9_rsp = router_27_9_rsp_out[3]; - assign router_27_9_to_magia_tile_ni_27_9_rsp = router_27_9_rsp_out[4]; - - assign router_27_9_to_router_27_10_req = router_27_9_req_out[0]; - assign router_27_9_to_router_28_9_req = router_27_9_req_out[1]; - assign router_27_9_to_router_27_8_req = router_27_9_req_out[2]; - assign router_27_9_to_router_26_9_req = router_27_9_req_out[3]; - assign router_27_9_to_magia_tile_ni_27_9_req = router_27_9_req_out[4]; - - assign router_27_9_rsp_in[0] = router_27_10_to_router_27_9_rsp; - assign router_27_9_rsp_in[1] = router_28_9_to_router_27_9_rsp; - assign router_27_9_rsp_in[2] = router_27_8_to_router_27_9_rsp; - assign router_27_9_rsp_in[3] = router_26_9_to_router_27_9_rsp; - assign router_27_9_rsp_in[4] = magia_tile_ni_27_9_to_router_27_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_9_req_in), - .floo_rsp_o (router_27_9_rsp_out), - .floo_req_o (router_27_9_req_out), - .floo_rsp_i (router_27_9_rsp_in) -); - - -floo_req_t [4:0] router_27_10_req_in; -floo_rsp_t [4:0] router_27_10_rsp_out; -floo_req_t [4:0] router_27_10_req_out; -floo_rsp_t [4:0] router_27_10_rsp_in; - - assign router_27_10_req_in[0] = router_27_11_to_router_27_10_req; - assign router_27_10_req_in[1] = router_28_10_to_router_27_10_req; - assign router_27_10_req_in[2] = router_27_9_to_router_27_10_req; - assign router_27_10_req_in[3] = router_26_10_to_router_27_10_req; - assign router_27_10_req_in[4] = magia_tile_ni_27_10_to_router_27_10_req; - - assign router_27_10_to_router_27_11_rsp = router_27_10_rsp_out[0]; - assign router_27_10_to_router_28_10_rsp = router_27_10_rsp_out[1]; - assign router_27_10_to_router_27_9_rsp = router_27_10_rsp_out[2]; - assign router_27_10_to_router_26_10_rsp = router_27_10_rsp_out[3]; - assign router_27_10_to_magia_tile_ni_27_10_rsp = router_27_10_rsp_out[4]; - - assign router_27_10_to_router_27_11_req = router_27_10_req_out[0]; - assign router_27_10_to_router_28_10_req = router_27_10_req_out[1]; - assign router_27_10_to_router_27_9_req = router_27_10_req_out[2]; - assign router_27_10_to_router_26_10_req = router_27_10_req_out[3]; - assign router_27_10_to_magia_tile_ni_27_10_req = router_27_10_req_out[4]; - - assign router_27_10_rsp_in[0] = router_27_11_to_router_27_10_rsp; - assign router_27_10_rsp_in[1] = router_28_10_to_router_27_10_rsp; - assign router_27_10_rsp_in[2] = router_27_9_to_router_27_10_rsp; - assign router_27_10_rsp_in[3] = router_26_10_to_router_27_10_rsp; - assign router_27_10_rsp_in[4] = magia_tile_ni_27_10_to_router_27_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_10_req_in), - .floo_rsp_o (router_27_10_rsp_out), - .floo_req_o (router_27_10_req_out), - .floo_rsp_i (router_27_10_rsp_in) -); - - -floo_req_t [4:0] router_27_11_req_in; -floo_rsp_t [4:0] router_27_11_rsp_out; -floo_req_t [4:0] router_27_11_req_out; -floo_rsp_t [4:0] router_27_11_rsp_in; - - assign router_27_11_req_in[0] = router_27_12_to_router_27_11_req; - assign router_27_11_req_in[1] = router_28_11_to_router_27_11_req; - assign router_27_11_req_in[2] = router_27_10_to_router_27_11_req; - assign router_27_11_req_in[3] = router_26_11_to_router_27_11_req; - assign router_27_11_req_in[4] = magia_tile_ni_27_11_to_router_27_11_req; - - assign router_27_11_to_router_27_12_rsp = router_27_11_rsp_out[0]; - assign router_27_11_to_router_28_11_rsp = router_27_11_rsp_out[1]; - assign router_27_11_to_router_27_10_rsp = router_27_11_rsp_out[2]; - assign router_27_11_to_router_26_11_rsp = router_27_11_rsp_out[3]; - assign router_27_11_to_magia_tile_ni_27_11_rsp = router_27_11_rsp_out[4]; - - assign router_27_11_to_router_27_12_req = router_27_11_req_out[0]; - assign router_27_11_to_router_28_11_req = router_27_11_req_out[1]; - assign router_27_11_to_router_27_10_req = router_27_11_req_out[2]; - assign router_27_11_to_router_26_11_req = router_27_11_req_out[3]; - assign router_27_11_to_magia_tile_ni_27_11_req = router_27_11_req_out[4]; - - assign router_27_11_rsp_in[0] = router_27_12_to_router_27_11_rsp; - assign router_27_11_rsp_in[1] = router_28_11_to_router_27_11_rsp; - assign router_27_11_rsp_in[2] = router_27_10_to_router_27_11_rsp; - assign router_27_11_rsp_in[3] = router_26_11_to_router_27_11_rsp; - assign router_27_11_rsp_in[4] = magia_tile_ni_27_11_to_router_27_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_11_req_in), - .floo_rsp_o (router_27_11_rsp_out), - .floo_req_o (router_27_11_req_out), - .floo_rsp_i (router_27_11_rsp_in) -); - - -floo_req_t [4:0] router_27_12_req_in; -floo_rsp_t [4:0] router_27_12_rsp_out; -floo_req_t [4:0] router_27_12_req_out; -floo_rsp_t [4:0] router_27_12_rsp_in; - - assign router_27_12_req_in[0] = router_27_13_to_router_27_12_req; - assign router_27_12_req_in[1] = router_28_12_to_router_27_12_req; - assign router_27_12_req_in[2] = router_27_11_to_router_27_12_req; - assign router_27_12_req_in[3] = router_26_12_to_router_27_12_req; - assign router_27_12_req_in[4] = magia_tile_ni_27_12_to_router_27_12_req; - - assign router_27_12_to_router_27_13_rsp = router_27_12_rsp_out[0]; - assign router_27_12_to_router_28_12_rsp = router_27_12_rsp_out[1]; - assign router_27_12_to_router_27_11_rsp = router_27_12_rsp_out[2]; - assign router_27_12_to_router_26_12_rsp = router_27_12_rsp_out[3]; - assign router_27_12_to_magia_tile_ni_27_12_rsp = router_27_12_rsp_out[4]; - - assign router_27_12_to_router_27_13_req = router_27_12_req_out[0]; - assign router_27_12_to_router_28_12_req = router_27_12_req_out[1]; - assign router_27_12_to_router_27_11_req = router_27_12_req_out[2]; - assign router_27_12_to_router_26_12_req = router_27_12_req_out[3]; - assign router_27_12_to_magia_tile_ni_27_12_req = router_27_12_req_out[4]; - - assign router_27_12_rsp_in[0] = router_27_13_to_router_27_12_rsp; - assign router_27_12_rsp_in[1] = router_28_12_to_router_27_12_rsp; - assign router_27_12_rsp_in[2] = router_27_11_to_router_27_12_rsp; - assign router_27_12_rsp_in[3] = router_26_12_to_router_27_12_rsp; - assign router_27_12_rsp_in[4] = magia_tile_ni_27_12_to_router_27_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_12_req_in), - .floo_rsp_o (router_27_12_rsp_out), - .floo_req_o (router_27_12_req_out), - .floo_rsp_i (router_27_12_rsp_in) -); - - -floo_req_t [4:0] router_27_13_req_in; -floo_rsp_t [4:0] router_27_13_rsp_out; -floo_req_t [4:0] router_27_13_req_out; -floo_rsp_t [4:0] router_27_13_rsp_in; - - assign router_27_13_req_in[0] = router_27_14_to_router_27_13_req; - assign router_27_13_req_in[1] = router_28_13_to_router_27_13_req; - assign router_27_13_req_in[2] = router_27_12_to_router_27_13_req; - assign router_27_13_req_in[3] = router_26_13_to_router_27_13_req; - assign router_27_13_req_in[4] = magia_tile_ni_27_13_to_router_27_13_req; - - assign router_27_13_to_router_27_14_rsp = router_27_13_rsp_out[0]; - assign router_27_13_to_router_28_13_rsp = router_27_13_rsp_out[1]; - assign router_27_13_to_router_27_12_rsp = router_27_13_rsp_out[2]; - assign router_27_13_to_router_26_13_rsp = router_27_13_rsp_out[3]; - assign router_27_13_to_magia_tile_ni_27_13_rsp = router_27_13_rsp_out[4]; - - assign router_27_13_to_router_27_14_req = router_27_13_req_out[0]; - assign router_27_13_to_router_28_13_req = router_27_13_req_out[1]; - assign router_27_13_to_router_27_12_req = router_27_13_req_out[2]; - assign router_27_13_to_router_26_13_req = router_27_13_req_out[3]; - assign router_27_13_to_magia_tile_ni_27_13_req = router_27_13_req_out[4]; - - assign router_27_13_rsp_in[0] = router_27_14_to_router_27_13_rsp; - assign router_27_13_rsp_in[1] = router_28_13_to_router_27_13_rsp; - assign router_27_13_rsp_in[2] = router_27_12_to_router_27_13_rsp; - assign router_27_13_rsp_in[3] = router_26_13_to_router_27_13_rsp; - assign router_27_13_rsp_in[4] = magia_tile_ni_27_13_to_router_27_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_13_req_in), - .floo_rsp_o (router_27_13_rsp_out), - .floo_req_o (router_27_13_req_out), - .floo_rsp_i (router_27_13_rsp_in) -); - - -floo_req_t [4:0] router_27_14_req_in; -floo_rsp_t [4:0] router_27_14_rsp_out; -floo_req_t [4:0] router_27_14_req_out; -floo_rsp_t [4:0] router_27_14_rsp_in; - - assign router_27_14_req_in[0] = router_27_15_to_router_27_14_req; - assign router_27_14_req_in[1] = router_28_14_to_router_27_14_req; - assign router_27_14_req_in[2] = router_27_13_to_router_27_14_req; - assign router_27_14_req_in[3] = router_26_14_to_router_27_14_req; - assign router_27_14_req_in[4] = magia_tile_ni_27_14_to_router_27_14_req; - - assign router_27_14_to_router_27_15_rsp = router_27_14_rsp_out[0]; - assign router_27_14_to_router_28_14_rsp = router_27_14_rsp_out[1]; - assign router_27_14_to_router_27_13_rsp = router_27_14_rsp_out[2]; - assign router_27_14_to_router_26_14_rsp = router_27_14_rsp_out[3]; - assign router_27_14_to_magia_tile_ni_27_14_rsp = router_27_14_rsp_out[4]; - - assign router_27_14_to_router_27_15_req = router_27_14_req_out[0]; - assign router_27_14_to_router_28_14_req = router_27_14_req_out[1]; - assign router_27_14_to_router_27_13_req = router_27_14_req_out[2]; - assign router_27_14_to_router_26_14_req = router_27_14_req_out[3]; - assign router_27_14_to_magia_tile_ni_27_14_req = router_27_14_req_out[4]; - - assign router_27_14_rsp_in[0] = router_27_15_to_router_27_14_rsp; - assign router_27_14_rsp_in[1] = router_28_14_to_router_27_14_rsp; - assign router_27_14_rsp_in[2] = router_27_13_to_router_27_14_rsp; - assign router_27_14_rsp_in[3] = router_26_14_to_router_27_14_rsp; - assign router_27_14_rsp_in[4] = magia_tile_ni_27_14_to_router_27_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_14_req_in), - .floo_rsp_o (router_27_14_rsp_out), - .floo_req_o (router_27_14_req_out), - .floo_rsp_i (router_27_14_rsp_in) -); - - -floo_req_t [4:0] router_27_15_req_in; -floo_rsp_t [4:0] router_27_15_rsp_out; -floo_req_t [4:0] router_27_15_req_out; -floo_rsp_t [4:0] router_27_15_rsp_in; - - assign router_27_15_req_in[0] = router_27_16_to_router_27_15_req; - assign router_27_15_req_in[1] = router_28_15_to_router_27_15_req; - assign router_27_15_req_in[2] = router_27_14_to_router_27_15_req; - assign router_27_15_req_in[3] = router_26_15_to_router_27_15_req; - assign router_27_15_req_in[4] = magia_tile_ni_27_15_to_router_27_15_req; - - assign router_27_15_to_router_27_16_rsp = router_27_15_rsp_out[0]; - assign router_27_15_to_router_28_15_rsp = router_27_15_rsp_out[1]; - assign router_27_15_to_router_27_14_rsp = router_27_15_rsp_out[2]; - assign router_27_15_to_router_26_15_rsp = router_27_15_rsp_out[3]; - assign router_27_15_to_magia_tile_ni_27_15_rsp = router_27_15_rsp_out[4]; - - assign router_27_15_to_router_27_16_req = router_27_15_req_out[0]; - assign router_27_15_to_router_28_15_req = router_27_15_req_out[1]; - assign router_27_15_to_router_27_14_req = router_27_15_req_out[2]; - assign router_27_15_to_router_26_15_req = router_27_15_req_out[3]; - assign router_27_15_to_magia_tile_ni_27_15_req = router_27_15_req_out[4]; - - assign router_27_15_rsp_in[0] = router_27_16_to_router_27_15_rsp; - assign router_27_15_rsp_in[1] = router_28_15_to_router_27_15_rsp; - assign router_27_15_rsp_in[2] = router_27_14_to_router_27_15_rsp; - assign router_27_15_rsp_in[3] = router_26_15_to_router_27_15_rsp; - assign router_27_15_rsp_in[4] = magia_tile_ni_27_15_to_router_27_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_15_req_in), - .floo_rsp_o (router_27_15_rsp_out), - .floo_req_o (router_27_15_req_out), - .floo_rsp_i (router_27_15_rsp_in) -); - - -floo_req_t [4:0] router_27_16_req_in; -floo_rsp_t [4:0] router_27_16_rsp_out; -floo_req_t [4:0] router_27_16_req_out; -floo_rsp_t [4:0] router_27_16_rsp_in; - - assign router_27_16_req_in[0] = router_27_17_to_router_27_16_req; - assign router_27_16_req_in[1] = router_28_16_to_router_27_16_req; - assign router_27_16_req_in[2] = router_27_15_to_router_27_16_req; - assign router_27_16_req_in[3] = router_26_16_to_router_27_16_req; - assign router_27_16_req_in[4] = magia_tile_ni_27_16_to_router_27_16_req; - - assign router_27_16_to_router_27_17_rsp = router_27_16_rsp_out[0]; - assign router_27_16_to_router_28_16_rsp = router_27_16_rsp_out[1]; - assign router_27_16_to_router_27_15_rsp = router_27_16_rsp_out[2]; - assign router_27_16_to_router_26_16_rsp = router_27_16_rsp_out[3]; - assign router_27_16_to_magia_tile_ni_27_16_rsp = router_27_16_rsp_out[4]; - - assign router_27_16_to_router_27_17_req = router_27_16_req_out[0]; - assign router_27_16_to_router_28_16_req = router_27_16_req_out[1]; - assign router_27_16_to_router_27_15_req = router_27_16_req_out[2]; - assign router_27_16_to_router_26_16_req = router_27_16_req_out[3]; - assign router_27_16_to_magia_tile_ni_27_16_req = router_27_16_req_out[4]; - - assign router_27_16_rsp_in[0] = router_27_17_to_router_27_16_rsp; - assign router_27_16_rsp_in[1] = router_28_16_to_router_27_16_rsp; - assign router_27_16_rsp_in[2] = router_27_15_to_router_27_16_rsp; - assign router_27_16_rsp_in[3] = router_26_16_to_router_27_16_rsp; - assign router_27_16_rsp_in[4] = magia_tile_ni_27_16_to_router_27_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_16_req_in), - .floo_rsp_o (router_27_16_rsp_out), - .floo_req_o (router_27_16_req_out), - .floo_rsp_i (router_27_16_rsp_in) -); - - -floo_req_t [4:0] router_27_17_req_in; -floo_rsp_t [4:0] router_27_17_rsp_out; -floo_req_t [4:0] router_27_17_req_out; -floo_rsp_t [4:0] router_27_17_rsp_in; - - assign router_27_17_req_in[0] = router_27_18_to_router_27_17_req; - assign router_27_17_req_in[1] = router_28_17_to_router_27_17_req; - assign router_27_17_req_in[2] = router_27_16_to_router_27_17_req; - assign router_27_17_req_in[3] = router_26_17_to_router_27_17_req; - assign router_27_17_req_in[4] = magia_tile_ni_27_17_to_router_27_17_req; - - assign router_27_17_to_router_27_18_rsp = router_27_17_rsp_out[0]; - assign router_27_17_to_router_28_17_rsp = router_27_17_rsp_out[1]; - assign router_27_17_to_router_27_16_rsp = router_27_17_rsp_out[2]; - assign router_27_17_to_router_26_17_rsp = router_27_17_rsp_out[3]; - assign router_27_17_to_magia_tile_ni_27_17_rsp = router_27_17_rsp_out[4]; - - assign router_27_17_to_router_27_18_req = router_27_17_req_out[0]; - assign router_27_17_to_router_28_17_req = router_27_17_req_out[1]; - assign router_27_17_to_router_27_16_req = router_27_17_req_out[2]; - assign router_27_17_to_router_26_17_req = router_27_17_req_out[3]; - assign router_27_17_to_magia_tile_ni_27_17_req = router_27_17_req_out[4]; - - assign router_27_17_rsp_in[0] = router_27_18_to_router_27_17_rsp; - assign router_27_17_rsp_in[1] = router_28_17_to_router_27_17_rsp; - assign router_27_17_rsp_in[2] = router_27_16_to_router_27_17_rsp; - assign router_27_17_rsp_in[3] = router_26_17_to_router_27_17_rsp; - assign router_27_17_rsp_in[4] = magia_tile_ni_27_17_to_router_27_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_17_req_in), - .floo_rsp_o (router_27_17_rsp_out), - .floo_req_o (router_27_17_req_out), - .floo_rsp_i (router_27_17_rsp_in) -); - - -floo_req_t [4:0] router_27_18_req_in; -floo_rsp_t [4:0] router_27_18_rsp_out; -floo_req_t [4:0] router_27_18_req_out; -floo_rsp_t [4:0] router_27_18_rsp_in; - - assign router_27_18_req_in[0] = router_27_19_to_router_27_18_req; - assign router_27_18_req_in[1] = router_28_18_to_router_27_18_req; - assign router_27_18_req_in[2] = router_27_17_to_router_27_18_req; - assign router_27_18_req_in[3] = router_26_18_to_router_27_18_req; - assign router_27_18_req_in[4] = magia_tile_ni_27_18_to_router_27_18_req; - - assign router_27_18_to_router_27_19_rsp = router_27_18_rsp_out[0]; - assign router_27_18_to_router_28_18_rsp = router_27_18_rsp_out[1]; - assign router_27_18_to_router_27_17_rsp = router_27_18_rsp_out[2]; - assign router_27_18_to_router_26_18_rsp = router_27_18_rsp_out[3]; - assign router_27_18_to_magia_tile_ni_27_18_rsp = router_27_18_rsp_out[4]; - - assign router_27_18_to_router_27_19_req = router_27_18_req_out[0]; - assign router_27_18_to_router_28_18_req = router_27_18_req_out[1]; - assign router_27_18_to_router_27_17_req = router_27_18_req_out[2]; - assign router_27_18_to_router_26_18_req = router_27_18_req_out[3]; - assign router_27_18_to_magia_tile_ni_27_18_req = router_27_18_req_out[4]; - - assign router_27_18_rsp_in[0] = router_27_19_to_router_27_18_rsp; - assign router_27_18_rsp_in[1] = router_28_18_to_router_27_18_rsp; - assign router_27_18_rsp_in[2] = router_27_17_to_router_27_18_rsp; - assign router_27_18_rsp_in[3] = router_26_18_to_router_27_18_rsp; - assign router_27_18_rsp_in[4] = magia_tile_ni_27_18_to_router_27_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_18_req_in), - .floo_rsp_o (router_27_18_rsp_out), - .floo_req_o (router_27_18_req_out), - .floo_rsp_i (router_27_18_rsp_in) -); - - -floo_req_t [4:0] router_27_19_req_in; -floo_rsp_t [4:0] router_27_19_rsp_out; -floo_req_t [4:0] router_27_19_req_out; -floo_rsp_t [4:0] router_27_19_rsp_in; - - assign router_27_19_req_in[0] = router_27_20_to_router_27_19_req; - assign router_27_19_req_in[1] = router_28_19_to_router_27_19_req; - assign router_27_19_req_in[2] = router_27_18_to_router_27_19_req; - assign router_27_19_req_in[3] = router_26_19_to_router_27_19_req; - assign router_27_19_req_in[4] = magia_tile_ni_27_19_to_router_27_19_req; - - assign router_27_19_to_router_27_20_rsp = router_27_19_rsp_out[0]; - assign router_27_19_to_router_28_19_rsp = router_27_19_rsp_out[1]; - assign router_27_19_to_router_27_18_rsp = router_27_19_rsp_out[2]; - assign router_27_19_to_router_26_19_rsp = router_27_19_rsp_out[3]; - assign router_27_19_to_magia_tile_ni_27_19_rsp = router_27_19_rsp_out[4]; - - assign router_27_19_to_router_27_20_req = router_27_19_req_out[0]; - assign router_27_19_to_router_28_19_req = router_27_19_req_out[1]; - assign router_27_19_to_router_27_18_req = router_27_19_req_out[2]; - assign router_27_19_to_router_26_19_req = router_27_19_req_out[3]; - assign router_27_19_to_magia_tile_ni_27_19_req = router_27_19_req_out[4]; - - assign router_27_19_rsp_in[0] = router_27_20_to_router_27_19_rsp; - assign router_27_19_rsp_in[1] = router_28_19_to_router_27_19_rsp; - assign router_27_19_rsp_in[2] = router_27_18_to_router_27_19_rsp; - assign router_27_19_rsp_in[3] = router_26_19_to_router_27_19_rsp; - assign router_27_19_rsp_in[4] = magia_tile_ni_27_19_to_router_27_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_19_req_in), - .floo_rsp_o (router_27_19_rsp_out), - .floo_req_o (router_27_19_req_out), - .floo_rsp_i (router_27_19_rsp_in) -); - - -floo_req_t [4:0] router_27_20_req_in; -floo_rsp_t [4:0] router_27_20_rsp_out; -floo_req_t [4:0] router_27_20_req_out; -floo_rsp_t [4:0] router_27_20_rsp_in; - - assign router_27_20_req_in[0] = router_27_21_to_router_27_20_req; - assign router_27_20_req_in[1] = router_28_20_to_router_27_20_req; - assign router_27_20_req_in[2] = router_27_19_to_router_27_20_req; - assign router_27_20_req_in[3] = router_26_20_to_router_27_20_req; - assign router_27_20_req_in[4] = magia_tile_ni_27_20_to_router_27_20_req; - - assign router_27_20_to_router_27_21_rsp = router_27_20_rsp_out[0]; - assign router_27_20_to_router_28_20_rsp = router_27_20_rsp_out[1]; - assign router_27_20_to_router_27_19_rsp = router_27_20_rsp_out[2]; - assign router_27_20_to_router_26_20_rsp = router_27_20_rsp_out[3]; - assign router_27_20_to_magia_tile_ni_27_20_rsp = router_27_20_rsp_out[4]; - - assign router_27_20_to_router_27_21_req = router_27_20_req_out[0]; - assign router_27_20_to_router_28_20_req = router_27_20_req_out[1]; - assign router_27_20_to_router_27_19_req = router_27_20_req_out[2]; - assign router_27_20_to_router_26_20_req = router_27_20_req_out[3]; - assign router_27_20_to_magia_tile_ni_27_20_req = router_27_20_req_out[4]; - - assign router_27_20_rsp_in[0] = router_27_21_to_router_27_20_rsp; - assign router_27_20_rsp_in[1] = router_28_20_to_router_27_20_rsp; - assign router_27_20_rsp_in[2] = router_27_19_to_router_27_20_rsp; - assign router_27_20_rsp_in[3] = router_26_20_to_router_27_20_rsp; - assign router_27_20_rsp_in[4] = magia_tile_ni_27_20_to_router_27_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_20_req_in), - .floo_rsp_o (router_27_20_rsp_out), - .floo_req_o (router_27_20_req_out), - .floo_rsp_i (router_27_20_rsp_in) -); - - -floo_req_t [4:0] router_27_21_req_in; -floo_rsp_t [4:0] router_27_21_rsp_out; -floo_req_t [4:0] router_27_21_req_out; -floo_rsp_t [4:0] router_27_21_rsp_in; - - assign router_27_21_req_in[0] = router_27_22_to_router_27_21_req; - assign router_27_21_req_in[1] = router_28_21_to_router_27_21_req; - assign router_27_21_req_in[2] = router_27_20_to_router_27_21_req; - assign router_27_21_req_in[3] = router_26_21_to_router_27_21_req; - assign router_27_21_req_in[4] = magia_tile_ni_27_21_to_router_27_21_req; - - assign router_27_21_to_router_27_22_rsp = router_27_21_rsp_out[0]; - assign router_27_21_to_router_28_21_rsp = router_27_21_rsp_out[1]; - assign router_27_21_to_router_27_20_rsp = router_27_21_rsp_out[2]; - assign router_27_21_to_router_26_21_rsp = router_27_21_rsp_out[3]; - assign router_27_21_to_magia_tile_ni_27_21_rsp = router_27_21_rsp_out[4]; - - assign router_27_21_to_router_27_22_req = router_27_21_req_out[0]; - assign router_27_21_to_router_28_21_req = router_27_21_req_out[1]; - assign router_27_21_to_router_27_20_req = router_27_21_req_out[2]; - assign router_27_21_to_router_26_21_req = router_27_21_req_out[3]; - assign router_27_21_to_magia_tile_ni_27_21_req = router_27_21_req_out[4]; - - assign router_27_21_rsp_in[0] = router_27_22_to_router_27_21_rsp; - assign router_27_21_rsp_in[1] = router_28_21_to_router_27_21_rsp; - assign router_27_21_rsp_in[2] = router_27_20_to_router_27_21_rsp; - assign router_27_21_rsp_in[3] = router_26_21_to_router_27_21_rsp; - assign router_27_21_rsp_in[4] = magia_tile_ni_27_21_to_router_27_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_21_req_in), - .floo_rsp_o (router_27_21_rsp_out), - .floo_req_o (router_27_21_req_out), - .floo_rsp_i (router_27_21_rsp_in) -); - - -floo_req_t [4:0] router_27_22_req_in; -floo_rsp_t [4:0] router_27_22_rsp_out; -floo_req_t [4:0] router_27_22_req_out; -floo_rsp_t [4:0] router_27_22_rsp_in; - - assign router_27_22_req_in[0] = router_27_23_to_router_27_22_req; - assign router_27_22_req_in[1] = router_28_22_to_router_27_22_req; - assign router_27_22_req_in[2] = router_27_21_to_router_27_22_req; - assign router_27_22_req_in[3] = router_26_22_to_router_27_22_req; - assign router_27_22_req_in[4] = magia_tile_ni_27_22_to_router_27_22_req; - - assign router_27_22_to_router_27_23_rsp = router_27_22_rsp_out[0]; - assign router_27_22_to_router_28_22_rsp = router_27_22_rsp_out[1]; - assign router_27_22_to_router_27_21_rsp = router_27_22_rsp_out[2]; - assign router_27_22_to_router_26_22_rsp = router_27_22_rsp_out[3]; - assign router_27_22_to_magia_tile_ni_27_22_rsp = router_27_22_rsp_out[4]; - - assign router_27_22_to_router_27_23_req = router_27_22_req_out[0]; - assign router_27_22_to_router_28_22_req = router_27_22_req_out[1]; - assign router_27_22_to_router_27_21_req = router_27_22_req_out[2]; - assign router_27_22_to_router_26_22_req = router_27_22_req_out[3]; - assign router_27_22_to_magia_tile_ni_27_22_req = router_27_22_req_out[4]; - - assign router_27_22_rsp_in[0] = router_27_23_to_router_27_22_rsp; - assign router_27_22_rsp_in[1] = router_28_22_to_router_27_22_rsp; - assign router_27_22_rsp_in[2] = router_27_21_to_router_27_22_rsp; - assign router_27_22_rsp_in[3] = router_26_22_to_router_27_22_rsp; - assign router_27_22_rsp_in[4] = magia_tile_ni_27_22_to_router_27_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_22_req_in), - .floo_rsp_o (router_27_22_rsp_out), - .floo_req_o (router_27_22_req_out), - .floo_rsp_i (router_27_22_rsp_in) -); - - -floo_req_t [4:0] router_27_23_req_in; -floo_rsp_t [4:0] router_27_23_rsp_out; -floo_req_t [4:0] router_27_23_req_out; -floo_rsp_t [4:0] router_27_23_rsp_in; - - assign router_27_23_req_in[0] = router_27_24_to_router_27_23_req; - assign router_27_23_req_in[1] = router_28_23_to_router_27_23_req; - assign router_27_23_req_in[2] = router_27_22_to_router_27_23_req; - assign router_27_23_req_in[3] = router_26_23_to_router_27_23_req; - assign router_27_23_req_in[4] = magia_tile_ni_27_23_to_router_27_23_req; - - assign router_27_23_to_router_27_24_rsp = router_27_23_rsp_out[0]; - assign router_27_23_to_router_28_23_rsp = router_27_23_rsp_out[1]; - assign router_27_23_to_router_27_22_rsp = router_27_23_rsp_out[2]; - assign router_27_23_to_router_26_23_rsp = router_27_23_rsp_out[3]; - assign router_27_23_to_magia_tile_ni_27_23_rsp = router_27_23_rsp_out[4]; - - assign router_27_23_to_router_27_24_req = router_27_23_req_out[0]; - assign router_27_23_to_router_28_23_req = router_27_23_req_out[1]; - assign router_27_23_to_router_27_22_req = router_27_23_req_out[2]; - assign router_27_23_to_router_26_23_req = router_27_23_req_out[3]; - assign router_27_23_to_magia_tile_ni_27_23_req = router_27_23_req_out[4]; - - assign router_27_23_rsp_in[0] = router_27_24_to_router_27_23_rsp; - assign router_27_23_rsp_in[1] = router_28_23_to_router_27_23_rsp; - assign router_27_23_rsp_in[2] = router_27_22_to_router_27_23_rsp; - assign router_27_23_rsp_in[3] = router_26_23_to_router_27_23_rsp; - assign router_27_23_rsp_in[4] = magia_tile_ni_27_23_to_router_27_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_23_req_in), - .floo_rsp_o (router_27_23_rsp_out), - .floo_req_o (router_27_23_req_out), - .floo_rsp_i (router_27_23_rsp_in) -); - - -floo_req_t [4:0] router_27_24_req_in; -floo_rsp_t [4:0] router_27_24_rsp_out; -floo_req_t [4:0] router_27_24_req_out; -floo_rsp_t [4:0] router_27_24_rsp_in; - - assign router_27_24_req_in[0] = router_27_25_to_router_27_24_req; - assign router_27_24_req_in[1] = router_28_24_to_router_27_24_req; - assign router_27_24_req_in[2] = router_27_23_to_router_27_24_req; - assign router_27_24_req_in[3] = router_26_24_to_router_27_24_req; - assign router_27_24_req_in[4] = magia_tile_ni_27_24_to_router_27_24_req; - - assign router_27_24_to_router_27_25_rsp = router_27_24_rsp_out[0]; - assign router_27_24_to_router_28_24_rsp = router_27_24_rsp_out[1]; - assign router_27_24_to_router_27_23_rsp = router_27_24_rsp_out[2]; - assign router_27_24_to_router_26_24_rsp = router_27_24_rsp_out[3]; - assign router_27_24_to_magia_tile_ni_27_24_rsp = router_27_24_rsp_out[4]; - - assign router_27_24_to_router_27_25_req = router_27_24_req_out[0]; - assign router_27_24_to_router_28_24_req = router_27_24_req_out[1]; - assign router_27_24_to_router_27_23_req = router_27_24_req_out[2]; - assign router_27_24_to_router_26_24_req = router_27_24_req_out[3]; - assign router_27_24_to_magia_tile_ni_27_24_req = router_27_24_req_out[4]; - - assign router_27_24_rsp_in[0] = router_27_25_to_router_27_24_rsp; - assign router_27_24_rsp_in[1] = router_28_24_to_router_27_24_rsp; - assign router_27_24_rsp_in[2] = router_27_23_to_router_27_24_rsp; - assign router_27_24_rsp_in[3] = router_26_24_to_router_27_24_rsp; - assign router_27_24_rsp_in[4] = magia_tile_ni_27_24_to_router_27_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_24_req_in), - .floo_rsp_o (router_27_24_rsp_out), - .floo_req_o (router_27_24_req_out), - .floo_rsp_i (router_27_24_rsp_in) -); - - -floo_req_t [4:0] router_27_25_req_in; -floo_rsp_t [4:0] router_27_25_rsp_out; -floo_req_t [4:0] router_27_25_req_out; -floo_rsp_t [4:0] router_27_25_rsp_in; - - assign router_27_25_req_in[0] = router_27_26_to_router_27_25_req; - assign router_27_25_req_in[1] = router_28_25_to_router_27_25_req; - assign router_27_25_req_in[2] = router_27_24_to_router_27_25_req; - assign router_27_25_req_in[3] = router_26_25_to_router_27_25_req; - assign router_27_25_req_in[4] = magia_tile_ni_27_25_to_router_27_25_req; - - assign router_27_25_to_router_27_26_rsp = router_27_25_rsp_out[0]; - assign router_27_25_to_router_28_25_rsp = router_27_25_rsp_out[1]; - assign router_27_25_to_router_27_24_rsp = router_27_25_rsp_out[2]; - assign router_27_25_to_router_26_25_rsp = router_27_25_rsp_out[3]; - assign router_27_25_to_magia_tile_ni_27_25_rsp = router_27_25_rsp_out[4]; - - assign router_27_25_to_router_27_26_req = router_27_25_req_out[0]; - assign router_27_25_to_router_28_25_req = router_27_25_req_out[1]; - assign router_27_25_to_router_27_24_req = router_27_25_req_out[2]; - assign router_27_25_to_router_26_25_req = router_27_25_req_out[3]; - assign router_27_25_to_magia_tile_ni_27_25_req = router_27_25_req_out[4]; - - assign router_27_25_rsp_in[0] = router_27_26_to_router_27_25_rsp; - assign router_27_25_rsp_in[1] = router_28_25_to_router_27_25_rsp; - assign router_27_25_rsp_in[2] = router_27_24_to_router_27_25_rsp; - assign router_27_25_rsp_in[3] = router_26_25_to_router_27_25_rsp; - assign router_27_25_rsp_in[4] = magia_tile_ni_27_25_to_router_27_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_25_req_in), - .floo_rsp_o (router_27_25_rsp_out), - .floo_req_o (router_27_25_req_out), - .floo_rsp_i (router_27_25_rsp_in) -); - - -floo_req_t [4:0] router_27_26_req_in; -floo_rsp_t [4:0] router_27_26_rsp_out; -floo_req_t [4:0] router_27_26_req_out; -floo_rsp_t [4:0] router_27_26_rsp_in; - - assign router_27_26_req_in[0] = router_27_27_to_router_27_26_req; - assign router_27_26_req_in[1] = router_28_26_to_router_27_26_req; - assign router_27_26_req_in[2] = router_27_25_to_router_27_26_req; - assign router_27_26_req_in[3] = router_26_26_to_router_27_26_req; - assign router_27_26_req_in[4] = magia_tile_ni_27_26_to_router_27_26_req; - - assign router_27_26_to_router_27_27_rsp = router_27_26_rsp_out[0]; - assign router_27_26_to_router_28_26_rsp = router_27_26_rsp_out[1]; - assign router_27_26_to_router_27_25_rsp = router_27_26_rsp_out[2]; - assign router_27_26_to_router_26_26_rsp = router_27_26_rsp_out[3]; - assign router_27_26_to_magia_tile_ni_27_26_rsp = router_27_26_rsp_out[4]; - - assign router_27_26_to_router_27_27_req = router_27_26_req_out[0]; - assign router_27_26_to_router_28_26_req = router_27_26_req_out[1]; - assign router_27_26_to_router_27_25_req = router_27_26_req_out[2]; - assign router_27_26_to_router_26_26_req = router_27_26_req_out[3]; - assign router_27_26_to_magia_tile_ni_27_26_req = router_27_26_req_out[4]; - - assign router_27_26_rsp_in[0] = router_27_27_to_router_27_26_rsp; - assign router_27_26_rsp_in[1] = router_28_26_to_router_27_26_rsp; - assign router_27_26_rsp_in[2] = router_27_25_to_router_27_26_rsp; - assign router_27_26_rsp_in[3] = router_26_26_to_router_27_26_rsp; - assign router_27_26_rsp_in[4] = magia_tile_ni_27_26_to_router_27_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_26_req_in), - .floo_rsp_o (router_27_26_rsp_out), - .floo_req_o (router_27_26_req_out), - .floo_rsp_i (router_27_26_rsp_in) -); - - -floo_req_t [4:0] router_27_27_req_in; -floo_rsp_t [4:0] router_27_27_rsp_out; -floo_req_t [4:0] router_27_27_req_out; -floo_rsp_t [4:0] router_27_27_rsp_in; - - assign router_27_27_req_in[0] = router_27_28_to_router_27_27_req; - assign router_27_27_req_in[1] = router_28_27_to_router_27_27_req; - assign router_27_27_req_in[2] = router_27_26_to_router_27_27_req; - assign router_27_27_req_in[3] = router_26_27_to_router_27_27_req; - assign router_27_27_req_in[4] = magia_tile_ni_27_27_to_router_27_27_req; - - assign router_27_27_to_router_27_28_rsp = router_27_27_rsp_out[0]; - assign router_27_27_to_router_28_27_rsp = router_27_27_rsp_out[1]; - assign router_27_27_to_router_27_26_rsp = router_27_27_rsp_out[2]; - assign router_27_27_to_router_26_27_rsp = router_27_27_rsp_out[3]; - assign router_27_27_to_magia_tile_ni_27_27_rsp = router_27_27_rsp_out[4]; - - assign router_27_27_to_router_27_28_req = router_27_27_req_out[0]; - assign router_27_27_to_router_28_27_req = router_27_27_req_out[1]; - assign router_27_27_to_router_27_26_req = router_27_27_req_out[2]; - assign router_27_27_to_router_26_27_req = router_27_27_req_out[3]; - assign router_27_27_to_magia_tile_ni_27_27_req = router_27_27_req_out[4]; - - assign router_27_27_rsp_in[0] = router_27_28_to_router_27_27_rsp; - assign router_27_27_rsp_in[1] = router_28_27_to_router_27_27_rsp; - assign router_27_27_rsp_in[2] = router_27_26_to_router_27_27_rsp; - assign router_27_27_rsp_in[3] = router_26_27_to_router_27_27_rsp; - assign router_27_27_rsp_in[4] = magia_tile_ni_27_27_to_router_27_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_27_req_in), - .floo_rsp_o (router_27_27_rsp_out), - .floo_req_o (router_27_27_req_out), - .floo_rsp_i (router_27_27_rsp_in) -); - - -floo_req_t [4:0] router_27_28_req_in; -floo_rsp_t [4:0] router_27_28_rsp_out; -floo_req_t [4:0] router_27_28_req_out; -floo_rsp_t [4:0] router_27_28_rsp_in; - - assign router_27_28_req_in[0] = router_27_29_to_router_27_28_req; - assign router_27_28_req_in[1] = router_28_28_to_router_27_28_req; - assign router_27_28_req_in[2] = router_27_27_to_router_27_28_req; - assign router_27_28_req_in[3] = router_26_28_to_router_27_28_req; - assign router_27_28_req_in[4] = magia_tile_ni_27_28_to_router_27_28_req; - - assign router_27_28_to_router_27_29_rsp = router_27_28_rsp_out[0]; - assign router_27_28_to_router_28_28_rsp = router_27_28_rsp_out[1]; - assign router_27_28_to_router_27_27_rsp = router_27_28_rsp_out[2]; - assign router_27_28_to_router_26_28_rsp = router_27_28_rsp_out[3]; - assign router_27_28_to_magia_tile_ni_27_28_rsp = router_27_28_rsp_out[4]; - - assign router_27_28_to_router_27_29_req = router_27_28_req_out[0]; - assign router_27_28_to_router_28_28_req = router_27_28_req_out[1]; - assign router_27_28_to_router_27_27_req = router_27_28_req_out[2]; - assign router_27_28_to_router_26_28_req = router_27_28_req_out[3]; - assign router_27_28_to_magia_tile_ni_27_28_req = router_27_28_req_out[4]; - - assign router_27_28_rsp_in[0] = router_27_29_to_router_27_28_rsp; - assign router_27_28_rsp_in[1] = router_28_28_to_router_27_28_rsp; - assign router_27_28_rsp_in[2] = router_27_27_to_router_27_28_rsp; - assign router_27_28_rsp_in[3] = router_26_28_to_router_27_28_rsp; - assign router_27_28_rsp_in[4] = magia_tile_ni_27_28_to_router_27_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_28_req_in), - .floo_rsp_o (router_27_28_rsp_out), - .floo_req_o (router_27_28_req_out), - .floo_rsp_i (router_27_28_rsp_in) -); - - -floo_req_t [4:0] router_27_29_req_in; -floo_rsp_t [4:0] router_27_29_rsp_out; -floo_req_t [4:0] router_27_29_req_out; -floo_rsp_t [4:0] router_27_29_rsp_in; - - assign router_27_29_req_in[0] = router_27_30_to_router_27_29_req; - assign router_27_29_req_in[1] = router_28_29_to_router_27_29_req; - assign router_27_29_req_in[2] = router_27_28_to_router_27_29_req; - assign router_27_29_req_in[3] = router_26_29_to_router_27_29_req; - assign router_27_29_req_in[4] = magia_tile_ni_27_29_to_router_27_29_req; - - assign router_27_29_to_router_27_30_rsp = router_27_29_rsp_out[0]; - assign router_27_29_to_router_28_29_rsp = router_27_29_rsp_out[1]; - assign router_27_29_to_router_27_28_rsp = router_27_29_rsp_out[2]; - assign router_27_29_to_router_26_29_rsp = router_27_29_rsp_out[3]; - assign router_27_29_to_magia_tile_ni_27_29_rsp = router_27_29_rsp_out[4]; - - assign router_27_29_to_router_27_30_req = router_27_29_req_out[0]; - assign router_27_29_to_router_28_29_req = router_27_29_req_out[1]; - assign router_27_29_to_router_27_28_req = router_27_29_req_out[2]; - assign router_27_29_to_router_26_29_req = router_27_29_req_out[3]; - assign router_27_29_to_magia_tile_ni_27_29_req = router_27_29_req_out[4]; - - assign router_27_29_rsp_in[0] = router_27_30_to_router_27_29_rsp; - assign router_27_29_rsp_in[1] = router_28_29_to_router_27_29_rsp; - assign router_27_29_rsp_in[2] = router_27_28_to_router_27_29_rsp; - assign router_27_29_rsp_in[3] = router_26_29_to_router_27_29_rsp; - assign router_27_29_rsp_in[4] = magia_tile_ni_27_29_to_router_27_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_29_req_in), - .floo_rsp_o (router_27_29_rsp_out), - .floo_req_o (router_27_29_req_out), - .floo_rsp_i (router_27_29_rsp_in) -); - - -floo_req_t [4:0] router_27_30_req_in; -floo_rsp_t [4:0] router_27_30_rsp_out; -floo_req_t [4:0] router_27_30_req_out; -floo_rsp_t [4:0] router_27_30_rsp_in; - - assign router_27_30_req_in[0] = router_27_31_to_router_27_30_req; - assign router_27_30_req_in[1] = router_28_30_to_router_27_30_req; - assign router_27_30_req_in[2] = router_27_29_to_router_27_30_req; - assign router_27_30_req_in[3] = router_26_30_to_router_27_30_req; - assign router_27_30_req_in[4] = magia_tile_ni_27_30_to_router_27_30_req; - - assign router_27_30_to_router_27_31_rsp = router_27_30_rsp_out[0]; - assign router_27_30_to_router_28_30_rsp = router_27_30_rsp_out[1]; - assign router_27_30_to_router_27_29_rsp = router_27_30_rsp_out[2]; - assign router_27_30_to_router_26_30_rsp = router_27_30_rsp_out[3]; - assign router_27_30_to_magia_tile_ni_27_30_rsp = router_27_30_rsp_out[4]; - - assign router_27_30_to_router_27_31_req = router_27_30_req_out[0]; - assign router_27_30_to_router_28_30_req = router_27_30_req_out[1]; - assign router_27_30_to_router_27_29_req = router_27_30_req_out[2]; - assign router_27_30_to_router_26_30_req = router_27_30_req_out[3]; - assign router_27_30_to_magia_tile_ni_27_30_req = router_27_30_req_out[4]; - - assign router_27_30_rsp_in[0] = router_27_31_to_router_27_30_rsp; - assign router_27_30_rsp_in[1] = router_28_30_to_router_27_30_rsp; - assign router_27_30_rsp_in[2] = router_27_29_to_router_27_30_rsp; - assign router_27_30_rsp_in[3] = router_26_30_to_router_27_30_rsp; - assign router_27_30_rsp_in[4] = magia_tile_ni_27_30_to_router_27_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_30_req_in), - .floo_rsp_o (router_27_30_rsp_out), - .floo_req_o (router_27_30_req_out), - .floo_rsp_i (router_27_30_rsp_in) -); - - -floo_req_t [4:0] router_27_31_req_in; -floo_rsp_t [4:0] router_27_31_rsp_out; -floo_req_t [4:0] router_27_31_req_out; -floo_rsp_t [4:0] router_27_31_rsp_in; - - assign router_27_31_req_in[0] = '0; - assign router_27_31_req_in[1] = router_28_31_to_router_27_31_req; - assign router_27_31_req_in[2] = router_27_30_to_router_27_31_req; - assign router_27_31_req_in[3] = router_26_31_to_router_27_31_req; - assign router_27_31_req_in[4] = magia_tile_ni_27_31_to_router_27_31_req; - - assign router_27_31_to_router_28_31_rsp = router_27_31_rsp_out[1]; - assign router_27_31_to_router_27_30_rsp = router_27_31_rsp_out[2]; - assign router_27_31_to_router_26_31_rsp = router_27_31_rsp_out[3]; - assign router_27_31_to_magia_tile_ni_27_31_rsp = router_27_31_rsp_out[4]; - - assign router_27_31_to_router_28_31_req = router_27_31_req_out[1]; - assign router_27_31_to_router_27_30_req = router_27_31_req_out[2]; - assign router_27_31_to_router_26_31_req = router_27_31_req_out[3]; - assign router_27_31_to_magia_tile_ni_27_31_req = router_27_31_req_out[4]; - - assign router_27_31_rsp_in[0] = '0; - assign router_27_31_rsp_in[1] = router_28_31_to_router_27_31_rsp; - assign router_27_31_rsp_in[2] = router_27_30_to_router_27_31_rsp; - assign router_27_31_rsp_in[3] = router_26_31_to_router_27_31_rsp; - assign router_27_31_rsp_in[4] = magia_tile_ni_27_31_to_router_27_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_27_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 28, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_27_31_req_in), - .floo_rsp_o (router_27_31_rsp_out), - .floo_req_o (router_27_31_req_out), - .floo_rsp_i (router_27_31_rsp_in) -); - - -floo_req_t [4:0] router_28_0_req_in; -floo_rsp_t [4:0] router_28_0_rsp_out; -floo_req_t [4:0] router_28_0_req_out; -floo_rsp_t [4:0] router_28_0_rsp_in; - - assign router_28_0_req_in[0] = router_28_1_to_router_28_0_req; - assign router_28_0_req_in[1] = router_29_0_to_router_28_0_req; - assign router_28_0_req_in[2] = '0; - assign router_28_0_req_in[3] = router_27_0_to_router_28_0_req; - assign router_28_0_req_in[4] = magia_tile_ni_28_0_to_router_28_0_req; - - assign router_28_0_to_router_28_1_rsp = router_28_0_rsp_out[0]; - assign router_28_0_to_router_29_0_rsp = router_28_0_rsp_out[1]; - assign router_28_0_to_router_27_0_rsp = router_28_0_rsp_out[3]; - assign router_28_0_to_magia_tile_ni_28_0_rsp = router_28_0_rsp_out[4]; - - assign router_28_0_to_router_28_1_req = router_28_0_req_out[0]; - assign router_28_0_to_router_29_0_req = router_28_0_req_out[1]; - assign router_28_0_to_router_27_0_req = router_28_0_req_out[3]; - assign router_28_0_to_magia_tile_ni_28_0_req = router_28_0_req_out[4]; - - assign router_28_0_rsp_in[0] = router_28_1_to_router_28_0_rsp; - assign router_28_0_rsp_in[1] = router_29_0_to_router_28_0_rsp; - assign router_28_0_rsp_in[2] = '0; - assign router_28_0_rsp_in[3] = router_27_0_to_router_28_0_rsp; - assign router_28_0_rsp_in[4] = magia_tile_ni_28_0_to_router_28_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_0_req_in), - .floo_rsp_o (router_28_0_rsp_out), - .floo_req_o (router_28_0_req_out), - .floo_rsp_i (router_28_0_rsp_in) -); - - -floo_req_t [4:0] router_28_1_req_in; -floo_rsp_t [4:0] router_28_1_rsp_out; -floo_req_t [4:0] router_28_1_req_out; -floo_rsp_t [4:0] router_28_1_rsp_in; - - assign router_28_1_req_in[0] = router_28_2_to_router_28_1_req; - assign router_28_1_req_in[1] = router_29_1_to_router_28_1_req; - assign router_28_1_req_in[2] = router_28_0_to_router_28_1_req; - assign router_28_1_req_in[3] = router_27_1_to_router_28_1_req; - assign router_28_1_req_in[4] = magia_tile_ni_28_1_to_router_28_1_req; - - assign router_28_1_to_router_28_2_rsp = router_28_1_rsp_out[0]; - assign router_28_1_to_router_29_1_rsp = router_28_1_rsp_out[1]; - assign router_28_1_to_router_28_0_rsp = router_28_1_rsp_out[2]; - assign router_28_1_to_router_27_1_rsp = router_28_1_rsp_out[3]; - assign router_28_1_to_magia_tile_ni_28_1_rsp = router_28_1_rsp_out[4]; - - assign router_28_1_to_router_28_2_req = router_28_1_req_out[0]; - assign router_28_1_to_router_29_1_req = router_28_1_req_out[1]; - assign router_28_1_to_router_28_0_req = router_28_1_req_out[2]; - assign router_28_1_to_router_27_1_req = router_28_1_req_out[3]; - assign router_28_1_to_magia_tile_ni_28_1_req = router_28_1_req_out[4]; - - assign router_28_1_rsp_in[0] = router_28_2_to_router_28_1_rsp; - assign router_28_1_rsp_in[1] = router_29_1_to_router_28_1_rsp; - assign router_28_1_rsp_in[2] = router_28_0_to_router_28_1_rsp; - assign router_28_1_rsp_in[3] = router_27_1_to_router_28_1_rsp; - assign router_28_1_rsp_in[4] = magia_tile_ni_28_1_to_router_28_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_1_req_in), - .floo_rsp_o (router_28_1_rsp_out), - .floo_req_o (router_28_1_req_out), - .floo_rsp_i (router_28_1_rsp_in) -); - - -floo_req_t [4:0] router_28_2_req_in; -floo_rsp_t [4:0] router_28_2_rsp_out; -floo_req_t [4:0] router_28_2_req_out; -floo_rsp_t [4:0] router_28_2_rsp_in; - - assign router_28_2_req_in[0] = router_28_3_to_router_28_2_req; - assign router_28_2_req_in[1] = router_29_2_to_router_28_2_req; - assign router_28_2_req_in[2] = router_28_1_to_router_28_2_req; - assign router_28_2_req_in[3] = router_27_2_to_router_28_2_req; - assign router_28_2_req_in[4] = magia_tile_ni_28_2_to_router_28_2_req; - - assign router_28_2_to_router_28_3_rsp = router_28_2_rsp_out[0]; - assign router_28_2_to_router_29_2_rsp = router_28_2_rsp_out[1]; - assign router_28_2_to_router_28_1_rsp = router_28_2_rsp_out[2]; - assign router_28_2_to_router_27_2_rsp = router_28_2_rsp_out[3]; - assign router_28_2_to_magia_tile_ni_28_2_rsp = router_28_2_rsp_out[4]; - - assign router_28_2_to_router_28_3_req = router_28_2_req_out[0]; - assign router_28_2_to_router_29_2_req = router_28_2_req_out[1]; - assign router_28_2_to_router_28_1_req = router_28_2_req_out[2]; - assign router_28_2_to_router_27_2_req = router_28_2_req_out[3]; - assign router_28_2_to_magia_tile_ni_28_2_req = router_28_2_req_out[4]; - - assign router_28_2_rsp_in[0] = router_28_3_to_router_28_2_rsp; - assign router_28_2_rsp_in[1] = router_29_2_to_router_28_2_rsp; - assign router_28_2_rsp_in[2] = router_28_1_to_router_28_2_rsp; - assign router_28_2_rsp_in[3] = router_27_2_to_router_28_2_rsp; - assign router_28_2_rsp_in[4] = magia_tile_ni_28_2_to_router_28_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_2_req_in), - .floo_rsp_o (router_28_2_rsp_out), - .floo_req_o (router_28_2_req_out), - .floo_rsp_i (router_28_2_rsp_in) -); - - -floo_req_t [4:0] router_28_3_req_in; -floo_rsp_t [4:0] router_28_3_rsp_out; -floo_req_t [4:0] router_28_3_req_out; -floo_rsp_t [4:0] router_28_3_rsp_in; - - assign router_28_3_req_in[0] = router_28_4_to_router_28_3_req; - assign router_28_3_req_in[1] = router_29_3_to_router_28_3_req; - assign router_28_3_req_in[2] = router_28_2_to_router_28_3_req; - assign router_28_3_req_in[3] = router_27_3_to_router_28_3_req; - assign router_28_3_req_in[4] = magia_tile_ni_28_3_to_router_28_3_req; - - assign router_28_3_to_router_28_4_rsp = router_28_3_rsp_out[0]; - assign router_28_3_to_router_29_3_rsp = router_28_3_rsp_out[1]; - assign router_28_3_to_router_28_2_rsp = router_28_3_rsp_out[2]; - assign router_28_3_to_router_27_3_rsp = router_28_3_rsp_out[3]; - assign router_28_3_to_magia_tile_ni_28_3_rsp = router_28_3_rsp_out[4]; - - assign router_28_3_to_router_28_4_req = router_28_3_req_out[0]; - assign router_28_3_to_router_29_3_req = router_28_3_req_out[1]; - assign router_28_3_to_router_28_2_req = router_28_3_req_out[2]; - assign router_28_3_to_router_27_3_req = router_28_3_req_out[3]; - assign router_28_3_to_magia_tile_ni_28_3_req = router_28_3_req_out[4]; - - assign router_28_3_rsp_in[0] = router_28_4_to_router_28_3_rsp; - assign router_28_3_rsp_in[1] = router_29_3_to_router_28_3_rsp; - assign router_28_3_rsp_in[2] = router_28_2_to_router_28_3_rsp; - assign router_28_3_rsp_in[3] = router_27_3_to_router_28_3_rsp; - assign router_28_3_rsp_in[4] = magia_tile_ni_28_3_to_router_28_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_3_req_in), - .floo_rsp_o (router_28_3_rsp_out), - .floo_req_o (router_28_3_req_out), - .floo_rsp_i (router_28_3_rsp_in) -); - - -floo_req_t [4:0] router_28_4_req_in; -floo_rsp_t [4:0] router_28_4_rsp_out; -floo_req_t [4:0] router_28_4_req_out; -floo_rsp_t [4:0] router_28_4_rsp_in; - - assign router_28_4_req_in[0] = router_28_5_to_router_28_4_req; - assign router_28_4_req_in[1] = router_29_4_to_router_28_4_req; - assign router_28_4_req_in[2] = router_28_3_to_router_28_4_req; - assign router_28_4_req_in[3] = router_27_4_to_router_28_4_req; - assign router_28_4_req_in[4] = magia_tile_ni_28_4_to_router_28_4_req; - - assign router_28_4_to_router_28_5_rsp = router_28_4_rsp_out[0]; - assign router_28_4_to_router_29_4_rsp = router_28_4_rsp_out[1]; - assign router_28_4_to_router_28_3_rsp = router_28_4_rsp_out[2]; - assign router_28_4_to_router_27_4_rsp = router_28_4_rsp_out[3]; - assign router_28_4_to_magia_tile_ni_28_4_rsp = router_28_4_rsp_out[4]; - - assign router_28_4_to_router_28_5_req = router_28_4_req_out[0]; - assign router_28_4_to_router_29_4_req = router_28_4_req_out[1]; - assign router_28_4_to_router_28_3_req = router_28_4_req_out[2]; - assign router_28_4_to_router_27_4_req = router_28_4_req_out[3]; - assign router_28_4_to_magia_tile_ni_28_4_req = router_28_4_req_out[4]; - - assign router_28_4_rsp_in[0] = router_28_5_to_router_28_4_rsp; - assign router_28_4_rsp_in[1] = router_29_4_to_router_28_4_rsp; - assign router_28_4_rsp_in[2] = router_28_3_to_router_28_4_rsp; - assign router_28_4_rsp_in[3] = router_27_4_to_router_28_4_rsp; - assign router_28_4_rsp_in[4] = magia_tile_ni_28_4_to_router_28_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_4_req_in), - .floo_rsp_o (router_28_4_rsp_out), - .floo_req_o (router_28_4_req_out), - .floo_rsp_i (router_28_4_rsp_in) -); - - -floo_req_t [4:0] router_28_5_req_in; -floo_rsp_t [4:0] router_28_5_rsp_out; -floo_req_t [4:0] router_28_5_req_out; -floo_rsp_t [4:0] router_28_5_rsp_in; - - assign router_28_5_req_in[0] = router_28_6_to_router_28_5_req; - assign router_28_5_req_in[1] = router_29_5_to_router_28_5_req; - assign router_28_5_req_in[2] = router_28_4_to_router_28_5_req; - assign router_28_5_req_in[3] = router_27_5_to_router_28_5_req; - assign router_28_5_req_in[4] = magia_tile_ni_28_5_to_router_28_5_req; - - assign router_28_5_to_router_28_6_rsp = router_28_5_rsp_out[0]; - assign router_28_5_to_router_29_5_rsp = router_28_5_rsp_out[1]; - assign router_28_5_to_router_28_4_rsp = router_28_5_rsp_out[2]; - assign router_28_5_to_router_27_5_rsp = router_28_5_rsp_out[3]; - assign router_28_5_to_magia_tile_ni_28_5_rsp = router_28_5_rsp_out[4]; - - assign router_28_5_to_router_28_6_req = router_28_5_req_out[0]; - assign router_28_5_to_router_29_5_req = router_28_5_req_out[1]; - assign router_28_5_to_router_28_4_req = router_28_5_req_out[2]; - assign router_28_5_to_router_27_5_req = router_28_5_req_out[3]; - assign router_28_5_to_magia_tile_ni_28_5_req = router_28_5_req_out[4]; - - assign router_28_5_rsp_in[0] = router_28_6_to_router_28_5_rsp; - assign router_28_5_rsp_in[1] = router_29_5_to_router_28_5_rsp; - assign router_28_5_rsp_in[2] = router_28_4_to_router_28_5_rsp; - assign router_28_5_rsp_in[3] = router_27_5_to_router_28_5_rsp; - assign router_28_5_rsp_in[4] = magia_tile_ni_28_5_to_router_28_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_5_req_in), - .floo_rsp_o (router_28_5_rsp_out), - .floo_req_o (router_28_5_req_out), - .floo_rsp_i (router_28_5_rsp_in) -); - - -floo_req_t [4:0] router_28_6_req_in; -floo_rsp_t [4:0] router_28_6_rsp_out; -floo_req_t [4:0] router_28_6_req_out; -floo_rsp_t [4:0] router_28_6_rsp_in; - - assign router_28_6_req_in[0] = router_28_7_to_router_28_6_req; - assign router_28_6_req_in[1] = router_29_6_to_router_28_6_req; - assign router_28_6_req_in[2] = router_28_5_to_router_28_6_req; - assign router_28_6_req_in[3] = router_27_6_to_router_28_6_req; - assign router_28_6_req_in[4] = magia_tile_ni_28_6_to_router_28_6_req; - - assign router_28_6_to_router_28_7_rsp = router_28_6_rsp_out[0]; - assign router_28_6_to_router_29_6_rsp = router_28_6_rsp_out[1]; - assign router_28_6_to_router_28_5_rsp = router_28_6_rsp_out[2]; - assign router_28_6_to_router_27_6_rsp = router_28_6_rsp_out[3]; - assign router_28_6_to_magia_tile_ni_28_6_rsp = router_28_6_rsp_out[4]; - - assign router_28_6_to_router_28_7_req = router_28_6_req_out[0]; - assign router_28_6_to_router_29_6_req = router_28_6_req_out[1]; - assign router_28_6_to_router_28_5_req = router_28_6_req_out[2]; - assign router_28_6_to_router_27_6_req = router_28_6_req_out[3]; - assign router_28_6_to_magia_tile_ni_28_6_req = router_28_6_req_out[4]; - - assign router_28_6_rsp_in[0] = router_28_7_to_router_28_6_rsp; - assign router_28_6_rsp_in[1] = router_29_6_to_router_28_6_rsp; - assign router_28_6_rsp_in[2] = router_28_5_to_router_28_6_rsp; - assign router_28_6_rsp_in[3] = router_27_6_to_router_28_6_rsp; - assign router_28_6_rsp_in[4] = magia_tile_ni_28_6_to_router_28_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_6_req_in), - .floo_rsp_o (router_28_6_rsp_out), - .floo_req_o (router_28_6_req_out), - .floo_rsp_i (router_28_6_rsp_in) -); - - -floo_req_t [4:0] router_28_7_req_in; -floo_rsp_t [4:0] router_28_7_rsp_out; -floo_req_t [4:0] router_28_7_req_out; -floo_rsp_t [4:0] router_28_7_rsp_in; - - assign router_28_7_req_in[0] = router_28_8_to_router_28_7_req; - assign router_28_7_req_in[1] = router_29_7_to_router_28_7_req; - assign router_28_7_req_in[2] = router_28_6_to_router_28_7_req; - assign router_28_7_req_in[3] = router_27_7_to_router_28_7_req; - assign router_28_7_req_in[4] = magia_tile_ni_28_7_to_router_28_7_req; - - assign router_28_7_to_router_28_8_rsp = router_28_7_rsp_out[0]; - assign router_28_7_to_router_29_7_rsp = router_28_7_rsp_out[1]; - assign router_28_7_to_router_28_6_rsp = router_28_7_rsp_out[2]; - assign router_28_7_to_router_27_7_rsp = router_28_7_rsp_out[3]; - assign router_28_7_to_magia_tile_ni_28_7_rsp = router_28_7_rsp_out[4]; - - assign router_28_7_to_router_28_8_req = router_28_7_req_out[0]; - assign router_28_7_to_router_29_7_req = router_28_7_req_out[1]; - assign router_28_7_to_router_28_6_req = router_28_7_req_out[2]; - assign router_28_7_to_router_27_7_req = router_28_7_req_out[3]; - assign router_28_7_to_magia_tile_ni_28_7_req = router_28_7_req_out[4]; - - assign router_28_7_rsp_in[0] = router_28_8_to_router_28_7_rsp; - assign router_28_7_rsp_in[1] = router_29_7_to_router_28_7_rsp; - assign router_28_7_rsp_in[2] = router_28_6_to_router_28_7_rsp; - assign router_28_7_rsp_in[3] = router_27_7_to_router_28_7_rsp; - assign router_28_7_rsp_in[4] = magia_tile_ni_28_7_to_router_28_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_7_req_in), - .floo_rsp_o (router_28_7_rsp_out), - .floo_req_o (router_28_7_req_out), - .floo_rsp_i (router_28_7_rsp_in) -); - - -floo_req_t [4:0] router_28_8_req_in; -floo_rsp_t [4:0] router_28_8_rsp_out; -floo_req_t [4:0] router_28_8_req_out; -floo_rsp_t [4:0] router_28_8_rsp_in; - - assign router_28_8_req_in[0] = router_28_9_to_router_28_8_req; - assign router_28_8_req_in[1] = router_29_8_to_router_28_8_req; - assign router_28_8_req_in[2] = router_28_7_to_router_28_8_req; - assign router_28_8_req_in[3] = router_27_8_to_router_28_8_req; - assign router_28_8_req_in[4] = magia_tile_ni_28_8_to_router_28_8_req; - - assign router_28_8_to_router_28_9_rsp = router_28_8_rsp_out[0]; - assign router_28_8_to_router_29_8_rsp = router_28_8_rsp_out[1]; - assign router_28_8_to_router_28_7_rsp = router_28_8_rsp_out[2]; - assign router_28_8_to_router_27_8_rsp = router_28_8_rsp_out[3]; - assign router_28_8_to_magia_tile_ni_28_8_rsp = router_28_8_rsp_out[4]; - - assign router_28_8_to_router_28_9_req = router_28_8_req_out[0]; - assign router_28_8_to_router_29_8_req = router_28_8_req_out[1]; - assign router_28_8_to_router_28_7_req = router_28_8_req_out[2]; - assign router_28_8_to_router_27_8_req = router_28_8_req_out[3]; - assign router_28_8_to_magia_tile_ni_28_8_req = router_28_8_req_out[4]; - - assign router_28_8_rsp_in[0] = router_28_9_to_router_28_8_rsp; - assign router_28_8_rsp_in[1] = router_29_8_to_router_28_8_rsp; - assign router_28_8_rsp_in[2] = router_28_7_to_router_28_8_rsp; - assign router_28_8_rsp_in[3] = router_27_8_to_router_28_8_rsp; - assign router_28_8_rsp_in[4] = magia_tile_ni_28_8_to_router_28_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_8_req_in), - .floo_rsp_o (router_28_8_rsp_out), - .floo_req_o (router_28_8_req_out), - .floo_rsp_i (router_28_8_rsp_in) -); - - -floo_req_t [4:0] router_28_9_req_in; -floo_rsp_t [4:0] router_28_9_rsp_out; -floo_req_t [4:0] router_28_9_req_out; -floo_rsp_t [4:0] router_28_9_rsp_in; - - assign router_28_9_req_in[0] = router_28_10_to_router_28_9_req; - assign router_28_9_req_in[1] = router_29_9_to_router_28_9_req; - assign router_28_9_req_in[2] = router_28_8_to_router_28_9_req; - assign router_28_9_req_in[3] = router_27_9_to_router_28_9_req; - assign router_28_9_req_in[4] = magia_tile_ni_28_9_to_router_28_9_req; - - assign router_28_9_to_router_28_10_rsp = router_28_9_rsp_out[0]; - assign router_28_9_to_router_29_9_rsp = router_28_9_rsp_out[1]; - assign router_28_9_to_router_28_8_rsp = router_28_9_rsp_out[2]; - assign router_28_9_to_router_27_9_rsp = router_28_9_rsp_out[3]; - assign router_28_9_to_magia_tile_ni_28_9_rsp = router_28_9_rsp_out[4]; - - assign router_28_9_to_router_28_10_req = router_28_9_req_out[0]; - assign router_28_9_to_router_29_9_req = router_28_9_req_out[1]; - assign router_28_9_to_router_28_8_req = router_28_9_req_out[2]; - assign router_28_9_to_router_27_9_req = router_28_9_req_out[3]; - assign router_28_9_to_magia_tile_ni_28_9_req = router_28_9_req_out[4]; - - assign router_28_9_rsp_in[0] = router_28_10_to_router_28_9_rsp; - assign router_28_9_rsp_in[1] = router_29_9_to_router_28_9_rsp; - assign router_28_9_rsp_in[2] = router_28_8_to_router_28_9_rsp; - assign router_28_9_rsp_in[3] = router_27_9_to_router_28_9_rsp; - assign router_28_9_rsp_in[4] = magia_tile_ni_28_9_to_router_28_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_9_req_in), - .floo_rsp_o (router_28_9_rsp_out), - .floo_req_o (router_28_9_req_out), - .floo_rsp_i (router_28_9_rsp_in) -); - - -floo_req_t [4:0] router_28_10_req_in; -floo_rsp_t [4:0] router_28_10_rsp_out; -floo_req_t [4:0] router_28_10_req_out; -floo_rsp_t [4:0] router_28_10_rsp_in; - - assign router_28_10_req_in[0] = router_28_11_to_router_28_10_req; - assign router_28_10_req_in[1] = router_29_10_to_router_28_10_req; - assign router_28_10_req_in[2] = router_28_9_to_router_28_10_req; - assign router_28_10_req_in[3] = router_27_10_to_router_28_10_req; - assign router_28_10_req_in[4] = magia_tile_ni_28_10_to_router_28_10_req; - - assign router_28_10_to_router_28_11_rsp = router_28_10_rsp_out[0]; - assign router_28_10_to_router_29_10_rsp = router_28_10_rsp_out[1]; - assign router_28_10_to_router_28_9_rsp = router_28_10_rsp_out[2]; - assign router_28_10_to_router_27_10_rsp = router_28_10_rsp_out[3]; - assign router_28_10_to_magia_tile_ni_28_10_rsp = router_28_10_rsp_out[4]; - - assign router_28_10_to_router_28_11_req = router_28_10_req_out[0]; - assign router_28_10_to_router_29_10_req = router_28_10_req_out[1]; - assign router_28_10_to_router_28_9_req = router_28_10_req_out[2]; - assign router_28_10_to_router_27_10_req = router_28_10_req_out[3]; - assign router_28_10_to_magia_tile_ni_28_10_req = router_28_10_req_out[4]; - - assign router_28_10_rsp_in[0] = router_28_11_to_router_28_10_rsp; - assign router_28_10_rsp_in[1] = router_29_10_to_router_28_10_rsp; - assign router_28_10_rsp_in[2] = router_28_9_to_router_28_10_rsp; - assign router_28_10_rsp_in[3] = router_27_10_to_router_28_10_rsp; - assign router_28_10_rsp_in[4] = magia_tile_ni_28_10_to_router_28_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_10_req_in), - .floo_rsp_o (router_28_10_rsp_out), - .floo_req_o (router_28_10_req_out), - .floo_rsp_i (router_28_10_rsp_in) -); - - -floo_req_t [4:0] router_28_11_req_in; -floo_rsp_t [4:0] router_28_11_rsp_out; -floo_req_t [4:0] router_28_11_req_out; -floo_rsp_t [4:0] router_28_11_rsp_in; - - assign router_28_11_req_in[0] = router_28_12_to_router_28_11_req; - assign router_28_11_req_in[1] = router_29_11_to_router_28_11_req; - assign router_28_11_req_in[2] = router_28_10_to_router_28_11_req; - assign router_28_11_req_in[3] = router_27_11_to_router_28_11_req; - assign router_28_11_req_in[4] = magia_tile_ni_28_11_to_router_28_11_req; - - assign router_28_11_to_router_28_12_rsp = router_28_11_rsp_out[0]; - assign router_28_11_to_router_29_11_rsp = router_28_11_rsp_out[1]; - assign router_28_11_to_router_28_10_rsp = router_28_11_rsp_out[2]; - assign router_28_11_to_router_27_11_rsp = router_28_11_rsp_out[3]; - assign router_28_11_to_magia_tile_ni_28_11_rsp = router_28_11_rsp_out[4]; - - assign router_28_11_to_router_28_12_req = router_28_11_req_out[0]; - assign router_28_11_to_router_29_11_req = router_28_11_req_out[1]; - assign router_28_11_to_router_28_10_req = router_28_11_req_out[2]; - assign router_28_11_to_router_27_11_req = router_28_11_req_out[3]; - assign router_28_11_to_magia_tile_ni_28_11_req = router_28_11_req_out[4]; - - assign router_28_11_rsp_in[0] = router_28_12_to_router_28_11_rsp; - assign router_28_11_rsp_in[1] = router_29_11_to_router_28_11_rsp; - assign router_28_11_rsp_in[2] = router_28_10_to_router_28_11_rsp; - assign router_28_11_rsp_in[3] = router_27_11_to_router_28_11_rsp; - assign router_28_11_rsp_in[4] = magia_tile_ni_28_11_to_router_28_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_11_req_in), - .floo_rsp_o (router_28_11_rsp_out), - .floo_req_o (router_28_11_req_out), - .floo_rsp_i (router_28_11_rsp_in) -); - - -floo_req_t [4:0] router_28_12_req_in; -floo_rsp_t [4:0] router_28_12_rsp_out; -floo_req_t [4:0] router_28_12_req_out; -floo_rsp_t [4:0] router_28_12_rsp_in; - - assign router_28_12_req_in[0] = router_28_13_to_router_28_12_req; - assign router_28_12_req_in[1] = router_29_12_to_router_28_12_req; - assign router_28_12_req_in[2] = router_28_11_to_router_28_12_req; - assign router_28_12_req_in[3] = router_27_12_to_router_28_12_req; - assign router_28_12_req_in[4] = magia_tile_ni_28_12_to_router_28_12_req; - - assign router_28_12_to_router_28_13_rsp = router_28_12_rsp_out[0]; - assign router_28_12_to_router_29_12_rsp = router_28_12_rsp_out[1]; - assign router_28_12_to_router_28_11_rsp = router_28_12_rsp_out[2]; - assign router_28_12_to_router_27_12_rsp = router_28_12_rsp_out[3]; - assign router_28_12_to_magia_tile_ni_28_12_rsp = router_28_12_rsp_out[4]; - - assign router_28_12_to_router_28_13_req = router_28_12_req_out[0]; - assign router_28_12_to_router_29_12_req = router_28_12_req_out[1]; - assign router_28_12_to_router_28_11_req = router_28_12_req_out[2]; - assign router_28_12_to_router_27_12_req = router_28_12_req_out[3]; - assign router_28_12_to_magia_tile_ni_28_12_req = router_28_12_req_out[4]; - - assign router_28_12_rsp_in[0] = router_28_13_to_router_28_12_rsp; - assign router_28_12_rsp_in[1] = router_29_12_to_router_28_12_rsp; - assign router_28_12_rsp_in[2] = router_28_11_to_router_28_12_rsp; - assign router_28_12_rsp_in[3] = router_27_12_to_router_28_12_rsp; - assign router_28_12_rsp_in[4] = magia_tile_ni_28_12_to_router_28_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_12_req_in), - .floo_rsp_o (router_28_12_rsp_out), - .floo_req_o (router_28_12_req_out), - .floo_rsp_i (router_28_12_rsp_in) -); - - -floo_req_t [4:0] router_28_13_req_in; -floo_rsp_t [4:0] router_28_13_rsp_out; -floo_req_t [4:0] router_28_13_req_out; -floo_rsp_t [4:0] router_28_13_rsp_in; - - assign router_28_13_req_in[0] = router_28_14_to_router_28_13_req; - assign router_28_13_req_in[1] = router_29_13_to_router_28_13_req; - assign router_28_13_req_in[2] = router_28_12_to_router_28_13_req; - assign router_28_13_req_in[3] = router_27_13_to_router_28_13_req; - assign router_28_13_req_in[4] = magia_tile_ni_28_13_to_router_28_13_req; - - assign router_28_13_to_router_28_14_rsp = router_28_13_rsp_out[0]; - assign router_28_13_to_router_29_13_rsp = router_28_13_rsp_out[1]; - assign router_28_13_to_router_28_12_rsp = router_28_13_rsp_out[2]; - assign router_28_13_to_router_27_13_rsp = router_28_13_rsp_out[3]; - assign router_28_13_to_magia_tile_ni_28_13_rsp = router_28_13_rsp_out[4]; - - assign router_28_13_to_router_28_14_req = router_28_13_req_out[0]; - assign router_28_13_to_router_29_13_req = router_28_13_req_out[1]; - assign router_28_13_to_router_28_12_req = router_28_13_req_out[2]; - assign router_28_13_to_router_27_13_req = router_28_13_req_out[3]; - assign router_28_13_to_magia_tile_ni_28_13_req = router_28_13_req_out[4]; - - assign router_28_13_rsp_in[0] = router_28_14_to_router_28_13_rsp; - assign router_28_13_rsp_in[1] = router_29_13_to_router_28_13_rsp; - assign router_28_13_rsp_in[2] = router_28_12_to_router_28_13_rsp; - assign router_28_13_rsp_in[3] = router_27_13_to_router_28_13_rsp; - assign router_28_13_rsp_in[4] = magia_tile_ni_28_13_to_router_28_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_13_req_in), - .floo_rsp_o (router_28_13_rsp_out), - .floo_req_o (router_28_13_req_out), - .floo_rsp_i (router_28_13_rsp_in) -); - - -floo_req_t [4:0] router_28_14_req_in; -floo_rsp_t [4:0] router_28_14_rsp_out; -floo_req_t [4:0] router_28_14_req_out; -floo_rsp_t [4:0] router_28_14_rsp_in; - - assign router_28_14_req_in[0] = router_28_15_to_router_28_14_req; - assign router_28_14_req_in[1] = router_29_14_to_router_28_14_req; - assign router_28_14_req_in[2] = router_28_13_to_router_28_14_req; - assign router_28_14_req_in[3] = router_27_14_to_router_28_14_req; - assign router_28_14_req_in[4] = magia_tile_ni_28_14_to_router_28_14_req; - - assign router_28_14_to_router_28_15_rsp = router_28_14_rsp_out[0]; - assign router_28_14_to_router_29_14_rsp = router_28_14_rsp_out[1]; - assign router_28_14_to_router_28_13_rsp = router_28_14_rsp_out[2]; - assign router_28_14_to_router_27_14_rsp = router_28_14_rsp_out[3]; - assign router_28_14_to_magia_tile_ni_28_14_rsp = router_28_14_rsp_out[4]; - - assign router_28_14_to_router_28_15_req = router_28_14_req_out[0]; - assign router_28_14_to_router_29_14_req = router_28_14_req_out[1]; - assign router_28_14_to_router_28_13_req = router_28_14_req_out[2]; - assign router_28_14_to_router_27_14_req = router_28_14_req_out[3]; - assign router_28_14_to_magia_tile_ni_28_14_req = router_28_14_req_out[4]; - - assign router_28_14_rsp_in[0] = router_28_15_to_router_28_14_rsp; - assign router_28_14_rsp_in[1] = router_29_14_to_router_28_14_rsp; - assign router_28_14_rsp_in[2] = router_28_13_to_router_28_14_rsp; - assign router_28_14_rsp_in[3] = router_27_14_to_router_28_14_rsp; - assign router_28_14_rsp_in[4] = magia_tile_ni_28_14_to_router_28_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_14_req_in), - .floo_rsp_o (router_28_14_rsp_out), - .floo_req_o (router_28_14_req_out), - .floo_rsp_i (router_28_14_rsp_in) -); - - -floo_req_t [4:0] router_28_15_req_in; -floo_rsp_t [4:0] router_28_15_rsp_out; -floo_req_t [4:0] router_28_15_req_out; -floo_rsp_t [4:0] router_28_15_rsp_in; - - assign router_28_15_req_in[0] = router_28_16_to_router_28_15_req; - assign router_28_15_req_in[1] = router_29_15_to_router_28_15_req; - assign router_28_15_req_in[2] = router_28_14_to_router_28_15_req; - assign router_28_15_req_in[3] = router_27_15_to_router_28_15_req; - assign router_28_15_req_in[4] = magia_tile_ni_28_15_to_router_28_15_req; - - assign router_28_15_to_router_28_16_rsp = router_28_15_rsp_out[0]; - assign router_28_15_to_router_29_15_rsp = router_28_15_rsp_out[1]; - assign router_28_15_to_router_28_14_rsp = router_28_15_rsp_out[2]; - assign router_28_15_to_router_27_15_rsp = router_28_15_rsp_out[3]; - assign router_28_15_to_magia_tile_ni_28_15_rsp = router_28_15_rsp_out[4]; - - assign router_28_15_to_router_28_16_req = router_28_15_req_out[0]; - assign router_28_15_to_router_29_15_req = router_28_15_req_out[1]; - assign router_28_15_to_router_28_14_req = router_28_15_req_out[2]; - assign router_28_15_to_router_27_15_req = router_28_15_req_out[3]; - assign router_28_15_to_magia_tile_ni_28_15_req = router_28_15_req_out[4]; - - assign router_28_15_rsp_in[0] = router_28_16_to_router_28_15_rsp; - assign router_28_15_rsp_in[1] = router_29_15_to_router_28_15_rsp; - assign router_28_15_rsp_in[2] = router_28_14_to_router_28_15_rsp; - assign router_28_15_rsp_in[3] = router_27_15_to_router_28_15_rsp; - assign router_28_15_rsp_in[4] = magia_tile_ni_28_15_to_router_28_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_15_req_in), - .floo_rsp_o (router_28_15_rsp_out), - .floo_req_o (router_28_15_req_out), - .floo_rsp_i (router_28_15_rsp_in) -); - - -floo_req_t [4:0] router_28_16_req_in; -floo_rsp_t [4:0] router_28_16_rsp_out; -floo_req_t [4:0] router_28_16_req_out; -floo_rsp_t [4:0] router_28_16_rsp_in; - - assign router_28_16_req_in[0] = router_28_17_to_router_28_16_req; - assign router_28_16_req_in[1] = router_29_16_to_router_28_16_req; - assign router_28_16_req_in[2] = router_28_15_to_router_28_16_req; - assign router_28_16_req_in[3] = router_27_16_to_router_28_16_req; - assign router_28_16_req_in[4] = magia_tile_ni_28_16_to_router_28_16_req; - - assign router_28_16_to_router_28_17_rsp = router_28_16_rsp_out[0]; - assign router_28_16_to_router_29_16_rsp = router_28_16_rsp_out[1]; - assign router_28_16_to_router_28_15_rsp = router_28_16_rsp_out[2]; - assign router_28_16_to_router_27_16_rsp = router_28_16_rsp_out[3]; - assign router_28_16_to_magia_tile_ni_28_16_rsp = router_28_16_rsp_out[4]; - - assign router_28_16_to_router_28_17_req = router_28_16_req_out[0]; - assign router_28_16_to_router_29_16_req = router_28_16_req_out[1]; - assign router_28_16_to_router_28_15_req = router_28_16_req_out[2]; - assign router_28_16_to_router_27_16_req = router_28_16_req_out[3]; - assign router_28_16_to_magia_tile_ni_28_16_req = router_28_16_req_out[4]; - - assign router_28_16_rsp_in[0] = router_28_17_to_router_28_16_rsp; - assign router_28_16_rsp_in[1] = router_29_16_to_router_28_16_rsp; - assign router_28_16_rsp_in[2] = router_28_15_to_router_28_16_rsp; - assign router_28_16_rsp_in[3] = router_27_16_to_router_28_16_rsp; - assign router_28_16_rsp_in[4] = magia_tile_ni_28_16_to_router_28_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_16_req_in), - .floo_rsp_o (router_28_16_rsp_out), - .floo_req_o (router_28_16_req_out), - .floo_rsp_i (router_28_16_rsp_in) -); - - -floo_req_t [4:0] router_28_17_req_in; -floo_rsp_t [4:0] router_28_17_rsp_out; -floo_req_t [4:0] router_28_17_req_out; -floo_rsp_t [4:0] router_28_17_rsp_in; - - assign router_28_17_req_in[0] = router_28_18_to_router_28_17_req; - assign router_28_17_req_in[1] = router_29_17_to_router_28_17_req; - assign router_28_17_req_in[2] = router_28_16_to_router_28_17_req; - assign router_28_17_req_in[3] = router_27_17_to_router_28_17_req; - assign router_28_17_req_in[4] = magia_tile_ni_28_17_to_router_28_17_req; - - assign router_28_17_to_router_28_18_rsp = router_28_17_rsp_out[0]; - assign router_28_17_to_router_29_17_rsp = router_28_17_rsp_out[1]; - assign router_28_17_to_router_28_16_rsp = router_28_17_rsp_out[2]; - assign router_28_17_to_router_27_17_rsp = router_28_17_rsp_out[3]; - assign router_28_17_to_magia_tile_ni_28_17_rsp = router_28_17_rsp_out[4]; - - assign router_28_17_to_router_28_18_req = router_28_17_req_out[0]; - assign router_28_17_to_router_29_17_req = router_28_17_req_out[1]; - assign router_28_17_to_router_28_16_req = router_28_17_req_out[2]; - assign router_28_17_to_router_27_17_req = router_28_17_req_out[3]; - assign router_28_17_to_magia_tile_ni_28_17_req = router_28_17_req_out[4]; - - assign router_28_17_rsp_in[0] = router_28_18_to_router_28_17_rsp; - assign router_28_17_rsp_in[1] = router_29_17_to_router_28_17_rsp; - assign router_28_17_rsp_in[2] = router_28_16_to_router_28_17_rsp; - assign router_28_17_rsp_in[3] = router_27_17_to_router_28_17_rsp; - assign router_28_17_rsp_in[4] = magia_tile_ni_28_17_to_router_28_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_17_req_in), - .floo_rsp_o (router_28_17_rsp_out), - .floo_req_o (router_28_17_req_out), - .floo_rsp_i (router_28_17_rsp_in) -); - - -floo_req_t [4:0] router_28_18_req_in; -floo_rsp_t [4:0] router_28_18_rsp_out; -floo_req_t [4:0] router_28_18_req_out; -floo_rsp_t [4:0] router_28_18_rsp_in; - - assign router_28_18_req_in[0] = router_28_19_to_router_28_18_req; - assign router_28_18_req_in[1] = router_29_18_to_router_28_18_req; - assign router_28_18_req_in[2] = router_28_17_to_router_28_18_req; - assign router_28_18_req_in[3] = router_27_18_to_router_28_18_req; - assign router_28_18_req_in[4] = magia_tile_ni_28_18_to_router_28_18_req; - - assign router_28_18_to_router_28_19_rsp = router_28_18_rsp_out[0]; - assign router_28_18_to_router_29_18_rsp = router_28_18_rsp_out[1]; - assign router_28_18_to_router_28_17_rsp = router_28_18_rsp_out[2]; - assign router_28_18_to_router_27_18_rsp = router_28_18_rsp_out[3]; - assign router_28_18_to_magia_tile_ni_28_18_rsp = router_28_18_rsp_out[4]; - - assign router_28_18_to_router_28_19_req = router_28_18_req_out[0]; - assign router_28_18_to_router_29_18_req = router_28_18_req_out[1]; - assign router_28_18_to_router_28_17_req = router_28_18_req_out[2]; - assign router_28_18_to_router_27_18_req = router_28_18_req_out[3]; - assign router_28_18_to_magia_tile_ni_28_18_req = router_28_18_req_out[4]; - - assign router_28_18_rsp_in[0] = router_28_19_to_router_28_18_rsp; - assign router_28_18_rsp_in[1] = router_29_18_to_router_28_18_rsp; - assign router_28_18_rsp_in[2] = router_28_17_to_router_28_18_rsp; - assign router_28_18_rsp_in[3] = router_27_18_to_router_28_18_rsp; - assign router_28_18_rsp_in[4] = magia_tile_ni_28_18_to_router_28_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_18_req_in), - .floo_rsp_o (router_28_18_rsp_out), - .floo_req_o (router_28_18_req_out), - .floo_rsp_i (router_28_18_rsp_in) -); - - -floo_req_t [4:0] router_28_19_req_in; -floo_rsp_t [4:0] router_28_19_rsp_out; -floo_req_t [4:0] router_28_19_req_out; -floo_rsp_t [4:0] router_28_19_rsp_in; - - assign router_28_19_req_in[0] = router_28_20_to_router_28_19_req; - assign router_28_19_req_in[1] = router_29_19_to_router_28_19_req; - assign router_28_19_req_in[2] = router_28_18_to_router_28_19_req; - assign router_28_19_req_in[3] = router_27_19_to_router_28_19_req; - assign router_28_19_req_in[4] = magia_tile_ni_28_19_to_router_28_19_req; - - assign router_28_19_to_router_28_20_rsp = router_28_19_rsp_out[0]; - assign router_28_19_to_router_29_19_rsp = router_28_19_rsp_out[1]; - assign router_28_19_to_router_28_18_rsp = router_28_19_rsp_out[2]; - assign router_28_19_to_router_27_19_rsp = router_28_19_rsp_out[3]; - assign router_28_19_to_magia_tile_ni_28_19_rsp = router_28_19_rsp_out[4]; - - assign router_28_19_to_router_28_20_req = router_28_19_req_out[0]; - assign router_28_19_to_router_29_19_req = router_28_19_req_out[1]; - assign router_28_19_to_router_28_18_req = router_28_19_req_out[2]; - assign router_28_19_to_router_27_19_req = router_28_19_req_out[3]; - assign router_28_19_to_magia_tile_ni_28_19_req = router_28_19_req_out[4]; - - assign router_28_19_rsp_in[0] = router_28_20_to_router_28_19_rsp; - assign router_28_19_rsp_in[1] = router_29_19_to_router_28_19_rsp; - assign router_28_19_rsp_in[2] = router_28_18_to_router_28_19_rsp; - assign router_28_19_rsp_in[3] = router_27_19_to_router_28_19_rsp; - assign router_28_19_rsp_in[4] = magia_tile_ni_28_19_to_router_28_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_19_req_in), - .floo_rsp_o (router_28_19_rsp_out), - .floo_req_o (router_28_19_req_out), - .floo_rsp_i (router_28_19_rsp_in) -); - - -floo_req_t [4:0] router_28_20_req_in; -floo_rsp_t [4:0] router_28_20_rsp_out; -floo_req_t [4:0] router_28_20_req_out; -floo_rsp_t [4:0] router_28_20_rsp_in; - - assign router_28_20_req_in[0] = router_28_21_to_router_28_20_req; - assign router_28_20_req_in[1] = router_29_20_to_router_28_20_req; - assign router_28_20_req_in[2] = router_28_19_to_router_28_20_req; - assign router_28_20_req_in[3] = router_27_20_to_router_28_20_req; - assign router_28_20_req_in[4] = magia_tile_ni_28_20_to_router_28_20_req; - - assign router_28_20_to_router_28_21_rsp = router_28_20_rsp_out[0]; - assign router_28_20_to_router_29_20_rsp = router_28_20_rsp_out[1]; - assign router_28_20_to_router_28_19_rsp = router_28_20_rsp_out[2]; - assign router_28_20_to_router_27_20_rsp = router_28_20_rsp_out[3]; - assign router_28_20_to_magia_tile_ni_28_20_rsp = router_28_20_rsp_out[4]; - - assign router_28_20_to_router_28_21_req = router_28_20_req_out[0]; - assign router_28_20_to_router_29_20_req = router_28_20_req_out[1]; - assign router_28_20_to_router_28_19_req = router_28_20_req_out[2]; - assign router_28_20_to_router_27_20_req = router_28_20_req_out[3]; - assign router_28_20_to_magia_tile_ni_28_20_req = router_28_20_req_out[4]; - - assign router_28_20_rsp_in[0] = router_28_21_to_router_28_20_rsp; - assign router_28_20_rsp_in[1] = router_29_20_to_router_28_20_rsp; - assign router_28_20_rsp_in[2] = router_28_19_to_router_28_20_rsp; - assign router_28_20_rsp_in[3] = router_27_20_to_router_28_20_rsp; - assign router_28_20_rsp_in[4] = magia_tile_ni_28_20_to_router_28_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_20_req_in), - .floo_rsp_o (router_28_20_rsp_out), - .floo_req_o (router_28_20_req_out), - .floo_rsp_i (router_28_20_rsp_in) -); - - -floo_req_t [4:0] router_28_21_req_in; -floo_rsp_t [4:0] router_28_21_rsp_out; -floo_req_t [4:0] router_28_21_req_out; -floo_rsp_t [4:0] router_28_21_rsp_in; - - assign router_28_21_req_in[0] = router_28_22_to_router_28_21_req; - assign router_28_21_req_in[1] = router_29_21_to_router_28_21_req; - assign router_28_21_req_in[2] = router_28_20_to_router_28_21_req; - assign router_28_21_req_in[3] = router_27_21_to_router_28_21_req; - assign router_28_21_req_in[4] = magia_tile_ni_28_21_to_router_28_21_req; - - assign router_28_21_to_router_28_22_rsp = router_28_21_rsp_out[0]; - assign router_28_21_to_router_29_21_rsp = router_28_21_rsp_out[1]; - assign router_28_21_to_router_28_20_rsp = router_28_21_rsp_out[2]; - assign router_28_21_to_router_27_21_rsp = router_28_21_rsp_out[3]; - assign router_28_21_to_magia_tile_ni_28_21_rsp = router_28_21_rsp_out[4]; - - assign router_28_21_to_router_28_22_req = router_28_21_req_out[0]; - assign router_28_21_to_router_29_21_req = router_28_21_req_out[1]; - assign router_28_21_to_router_28_20_req = router_28_21_req_out[2]; - assign router_28_21_to_router_27_21_req = router_28_21_req_out[3]; - assign router_28_21_to_magia_tile_ni_28_21_req = router_28_21_req_out[4]; - - assign router_28_21_rsp_in[0] = router_28_22_to_router_28_21_rsp; - assign router_28_21_rsp_in[1] = router_29_21_to_router_28_21_rsp; - assign router_28_21_rsp_in[2] = router_28_20_to_router_28_21_rsp; - assign router_28_21_rsp_in[3] = router_27_21_to_router_28_21_rsp; - assign router_28_21_rsp_in[4] = magia_tile_ni_28_21_to_router_28_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_21_req_in), - .floo_rsp_o (router_28_21_rsp_out), - .floo_req_o (router_28_21_req_out), - .floo_rsp_i (router_28_21_rsp_in) -); - - -floo_req_t [4:0] router_28_22_req_in; -floo_rsp_t [4:0] router_28_22_rsp_out; -floo_req_t [4:0] router_28_22_req_out; -floo_rsp_t [4:0] router_28_22_rsp_in; - - assign router_28_22_req_in[0] = router_28_23_to_router_28_22_req; - assign router_28_22_req_in[1] = router_29_22_to_router_28_22_req; - assign router_28_22_req_in[2] = router_28_21_to_router_28_22_req; - assign router_28_22_req_in[3] = router_27_22_to_router_28_22_req; - assign router_28_22_req_in[4] = magia_tile_ni_28_22_to_router_28_22_req; - - assign router_28_22_to_router_28_23_rsp = router_28_22_rsp_out[0]; - assign router_28_22_to_router_29_22_rsp = router_28_22_rsp_out[1]; - assign router_28_22_to_router_28_21_rsp = router_28_22_rsp_out[2]; - assign router_28_22_to_router_27_22_rsp = router_28_22_rsp_out[3]; - assign router_28_22_to_magia_tile_ni_28_22_rsp = router_28_22_rsp_out[4]; - - assign router_28_22_to_router_28_23_req = router_28_22_req_out[0]; - assign router_28_22_to_router_29_22_req = router_28_22_req_out[1]; - assign router_28_22_to_router_28_21_req = router_28_22_req_out[2]; - assign router_28_22_to_router_27_22_req = router_28_22_req_out[3]; - assign router_28_22_to_magia_tile_ni_28_22_req = router_28_22_req_out[4]; - - assign router_28_22_rsp_in[0] = router_28_23_to_router_28_22_rsp; - assign router_28_22_rsp_in[1] = router_29_22_to_router_28_22_rsp; - assign router_28_22_rsp_in[2] = router_28_21_to_router_28_22_rsp; - assign router_28_22_rsp_in[3] = router_27_22_to_router_28_22_rsp; - assign router_28_22_rsp_in[4] = magia_tile_ni_28_22_to_router_28_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_22_req_in), - .floo_rsp_o (router_28_22_rsp_out), - .floo_req_o (router_28_22_req_out), - .floo_rsp_i (router_28_22_rsp_in) -); - - -floo_req_t [4:0] router_28_23_req_in; -floo_rsp_t [4:0] router_28_23_rsp_out; -floo_req_t [4:0] router_28_23_req_out; -floo_rsp_t [4:0] router_28_23_rsp_in; - - assign router_28_23_req_in[0] = router_28_24_to_router_28_23_req; - assign router_28_23_req_in[1] = router_29_23_to_router_28_23_req; - assign router_28_23_req_in[2] = router_28_22_to_router_28_23_req; - assign router_28_23_req_in[3] = router_27_23_to_router_28_23_req; - assign router_28_23_req_in[4] = magia_tile_ni_28_23_to_router_28_23_req; - - assign router_28_23_to_router_28_24_rsp = router_28_23_rsp_out[0]; - assign router_28_23_to_router_29_23_rsp = router_28_23_rsp_out[1]; - assign router_28_23_to_router_28_22_rsp = router_28_23_rsp_out[2]; - assign router_28_23_to_router_27_23_rsp = router_28_23_rsp_out[3]; - assign router_28_23_to_magia_tile_ni_28_23_rsp = router_28_23_rsp_out[4]; - - assign router_28_23_to_router_28_24_req = router_28_23_req_out[0]; - assign router_28_23_to_router_29_23_req = router_28_23_req_out[1]; - assign router_28_23_to_router_28_22_req = router_28_23_req_out[2]; - assign router_28_23_to_router_27_23_req = router_28_23_req_out[3]; - assign router_28_23_to_magia_tile_ni_28_23_req = router_28_23_req_out[4]; - - assign router_28_23_rsp_in[0] = router_28_24_to_router_28_23_rsp; - assign router_28_23_rsp_in[1] = router_29_23_to_router_28_23_rsp; - assign router_28_23_rsp_in[2] = router_28_22_to_router_28_23_rsp; - assign router_28_23_rsp_in[3] = router_27_23_to_router_28_23_rsp; - assign router_28_23_rsp_in[4] = magia_tile_ni_28_23_to_router_28_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_23_req_in), - .floo_rsp_o (router_28_23_rsp_out), - .floo_req_o (router_28_23_req_out), - .floo_rsp_i (router_28_23_rsp_in) -); - - -floo_req_t [4:0] router_28_24_req_in; -floo_rsp_t [4:0] router_28_24_rsp_out; -floo_req_t [4:0] router_28_24_req_out; -floo_rsp_t [4:0] router_28_24_rsp_in; - - assign router_28_24_req_in[0] = router_28_25_to_router_28_24_req; - assign router_28_24_req_in[1] = router_29_24_to_router_28_24_req; - assign router_28_24_req_in[2] = router_28_23_to_router_28_24_req; - assign router_28_24_req_in[3] = router_27_24_to_router_28_24_req; - assign router_28_24_req_in[4] = magia_tile_ni_28_24_to_router_28_24_req; - - assign router_28_24_to_router_28_25_rsp = router_28_24_rsp_out[0]; - assign router_28_24_to_router_29_24_rsp = router_28_24_rsp_out[1]; - assign router_28_24_to_router_28_23_rsp = router_28_24_rsp_out[2]; - assign router_28_24_to_router_27_24_rsp = router_28_24_rsp_out[3]; - assign router_28_24_to_magia_tile_ni_28_24_rsp = router_28_24_rsp_out[4]; - - assign router_28_24_to_router_28_25_req = router_28_24_req_out[0]; - assign router_28_24_to_router_29_24_req = router_28_24_req_out[1]; - assign router_28_24_to_router_28_23_req = router_28_24_req_out[2]; - assign router_28_24_to_router_27_24_req = router_28_24_req_out[3]; - assign router_28_24_to_magia_tile_ni_28_24_req = router_28_24_req_out[4]; - - assign router_28_24_rsp_in[0] = router_28_25_to_router_28_24_rsp; - assign router_28_24_rsp_in[1] = router_29_24_to_router_28_24_rsp; - assign router_28_24_rsp_in[2] = router_28_23_to_router_28_24_rsp; - assign router_28_24_rsp_in[3] = router_27_24_to_router_28_24_rsp; - assign router_28_24_rsp_in[4] = magia_tile_ni_28_24_to_router_28_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_24_req_in), - .floo_rsp_o (router_28_24_rsp_out), - .floo_req_o (router_28_24_req_out), - .floo_rsp_i (router_28_24_rsp_in) -); - - -floo_req_t [4:0] router_28_25_req_in; -floo_rsp_t [4:0] router_28_25_rsp_out; -floo_req_t [4:0] router_28_25_req_out; -floo_rsp_t [4:0] router_28_25_rsp_in; - - assign router_28_25_req_in[0] = router_28_26_to_router_28_25_req; - assign router_28_25_req_in[1] = router_29_25_to_router_28_25_req; - assign router_28_25_req_in[2] = router_28_24_to_router_28_25_req; - assign router_28_25_req_in[3] = router_27_25_to_router_28_25_req; - assign router_28_25_req_in[4] = magia_tile_ni_28_25_to_router_28_25_req; - - assign router_28_25_to_router_28_26_rsp = router_28_25_rsp_out[0]; - assign router_28_25_to_router_29_25_rsp = router_28_25_rsp_out[1]; - assign router_28_25_to_router_28_24_rsp = router_28_25_rsp_out[2]; - assign router_28_25_to_router_27_25_rsp = router_28_25_rsp_out[3]; - assign router_28_25_to_magia_tile_ni_28_25_rsp = router_28_25_rsp_out[4]; - - assign router_28_25_to_router_28_26_req = router_28_25_req_out[0]; - assign router_28_25_to_router_29_25_req = router_28_25_req_out[1]; - assign router_28_25_to_router_28_24_req = router_28_25_req_out[2]; - assign router_28_25_to_router_27_25_req = router_28_25_req_out[3]; - assign router_28_25_to_magia_tile_ni_28_25_req = router_28_25_req_out[4]; - - assign router_28_25_rsp_in[0] = router_28_26_to_router_28_25_rsp; - assign router_28_25_rsp_in[1] = router_29_25_to_router_28_25_rsp; - assign router_28_25_rsp_in[2] = router_28_24_to_router_28_25_rsp; - assign router_28_25_rsp_in[3] = router_27_25_to_router_28_25_rsp; - assign router_28_25_rsp_in[4] = magia_tile_ni_28_25_to_router_28_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_25_req_in), - .floo_rsp_o (router_28_25_rsp_out), - .floo_req_o (router_28_25_req_out), - .floo_rsp_i (router_28_25_rsp_in) -); - - -floo_req_t [4:0] router_28_26_req_in; -floo_rsp_t [4:0] router_28_26_rsp_out; -floo_req_t [4:0] router_28_26_req_out; -floo_rsp_t [4:0] router_28_26_rsp_in; - - assign router_28_26_req_in[0] = router_28_27_to_router_28_26_req; - assign router_28_26_req_in[1] = router_29_26_to_router_28_26_req; - assign router_28_26_req_in[2] = router_28_25_to_router_28_26_req; - assign router_28_26_req_in[3] = router_27_26_to_router_28_26_req; - assign router_28_26_req_in[4] = magia_tile_ni_28_26_to_router_28_26_req; - - assign router_28_26_to_router_28_27_rsp = router_28_26_rsp_out[0]; - assign router_28_26_to_router_29_26_rsp = router_28_26_rsp_out[1]; - assign router_28_26_to_router_28_25_rsp = router_28_26_rsp_out[2]; - assign router_28_26_to_router_27_26_rsp = router_28_26_rsp_out[3]; - assign router_28_26_to_magia_tile_ni_28_26_rsp = router_28_26_rsp_out[4]; - - assign router_28_26_to_router_28_27_req = router_28_26_req_out[0]; - assign router_28_26_to_router_29_26_req = router_28_26_req_out[1]; - assign router_28_26_to_router_28_25_req = router_28_26_req_out[2]; - assign router_28_26_to_router_27_26_req = router_28_26_req_out[3]; - assign router_28_26_to_magia_tile_ni_28_26_req = router_28_26_req_out[4]; - - assign router_28_26_rsp_in[0] = router_28_27_to_router_28_26_rsp; - assign router_28_26_rsp_in[1] = router_29_26_to_router_28_26_rsp; - assign router_28_26_rsp_in[2] = router_28_25_to_router_28_26_rsp; - assign router_28_26_rsp_in[3] = router_27_26_to_router_28_26_rsp; - assign router_28_26_rsp_in[4] = magia_tile_ni_28_26_to_router_28_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_26_req_in), - .floo_rsp_o (router_28_26_rsp_out), - .floo_req_o (router_28_26_req_out), - .floo_rsp_i (router_28_26_rsp_in) -); - - -floo_req_t [4:0] router_28_27_req_in; -floo_rsp_t [4:0] router_28_27_rsp_out; -floo_req_t [4:0] router_28_27_req_out; -floo_rsp_t [4:0] router_28_27_rsp_in; - - assign router_28_27_req_in[0] = router_28_28_to_router_28_27_req; - assign router_28_27_req_in[1] = router_29_27_to_router_28_27_req; - assign router_28_27_req_in[2] = router_28_26_to_router_28_27_req; - assign router_28_27_req_in[3] = router_27_27_to_router_28_27_req; - assign router_28_27_req_in[4] = magia_tile_ni_28_27_to_router_28_27_req; - - assign router_28_27_to_router_28_28_rsp = router_28_27_rsp_out[0]; - assign router_28_27_to_router_29_27_rsp = router_28_27_rsp_out[1]; - assign router_28_27_to_router_28_26_rsp = router_28_27_rsp_out[2]; - assign router_28_27_to_router_27_27_rsp = router_28_27_rsp_out[3]; - assign router_28_27_to_magia_tile_ni_28_27_rsp = router_28_27_rsp_out[4]; - - assign router_28_27_to_router_28_28_req = router_28_27_req_out[0]; - assign router_28_27_to_router_29_27_req = router_28_27_req_out[1]; - assign router_28_27_to_router_28_26_req = router_28_27_req_out[2]; - assign router_28_27_to_router_27_27_req = router_28_27_req_out[3]; - assign router_28_27_to_magia_tile_ni_28_27_req = router_28_27_req_out[4]; - - assign router_28_27_rsp_in[0] = router_28_28_to_router_28_27_rsp; - assign router_28_27_rsp_in[1] = router_29_27_to_router_28_27_rsp; - assign router_28_27_rsp_in[2] = router_28_26_to_router_28_27_rsp; - assign router_28_27_rsp_in[3] = router_27_27_to_router_28_27_rsp; - assign router_28_27_rsp_in[4] = magia_tile_ni_28_27_to_router_28_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_27_req_in), - .floo_rsp_o (router_28_27_rsp_out), - .floo_req_o (router_28_27_req_out), - .floo_rsp_i (router_28_27_rsp_in) -); - - -floo_req_t [4:0] router_28_28_req_in; -floo_rsp_t [4:0] router_28_28_rsp_out; -floo_req_t [4:0] router_28_28_req_out; -floo_rsp_t [4:0] router_28_28_rsp_in; - - assign router_28_28_req_in[0] = router_28_29_to_router_28_28_req; - assign router_28_28_req_in[1] = router_29_28_to_router_28_28_req; - assign router_28_28_req_in[2] = router_28_27_to_router_28_28_req; - assign router_28_28_req_in[3] = router_27_28_to_router_28_28_req; - assign router_28_28_req_in[4] = magia_tile_ni_28_28_to_router_28_28_req; - - assign router_28_28_to_router_28_29_rsp = router_28_28_rsp_out[0]; - assign router_28_28_to_router_29_28_rsp = router_28_28_rsp_out[1]; - assign router_28_28_to_router_28_27_rsp = router_28_28_rsp_out[2]; - assign router_28_28_to_router_27_28_rsp = router_28_28_rsp_out[3]; - assign router_28_28_to_magia_tile_ni_28_28_rsp = router_28_28_rsp_out[4]; - - assign router_28_28_to_router_28_29_req = router_28_28_req_out[0]; - assign router_28_28_to_router_29_28_req = router_28_28_req_out[1]; - assign router_28_28_to_router_28_27_req = router_28_28_req_out[2]; - assign router_28_28_to_router_27_28_req = router_28_28_req_out[3]; - assign router_28_28_to_magia_tile_ni_28_28_req = router_28_28_req_out[4]; - - assign router_28_28_rsp_in[0] = router_28_29_to_router_28_28_rsp; - assign router_28_28_rsp_in[1] = router_29_28_to_router_28_28_rsp; - assign router_28_28_rsp_in[2] = router_28_27_to_router_28_28_rsp; - assign router_28_28_rsp_in[3] = router_27_28_to_router_28_28_rsp; - assign router_28_28_rsp_in[4] = magia_tile_ni_28_28_to_router_28_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_28_req_in), - .floo_rsp_o (router_28_28_rsp_out), - .floo_req_o (router_28_28_req_out), - .floo_rsp_i (router_28_28_rsp_in) -); - - -floo_req_t [4:0] router_28_29_req_in; -floo_rsp_t [4:0] router_28_29_rsp_out; -floo_req_t [4:0] router_28_29_req_out; -floo_rsp_t [4:0] router_28_29_rsp_in; - - assign router_28_29_req_in[0] = router_28_30_to_router_28_29_req; - assign router_28_29_req_in[1] = router_29_29_to_router_28_29_req; - assign router_28_29_req_in[2] = router_28_28_to_router_28_29_req; - assign router_28_29_req_in[3] = router_27_29_to_router_28_29_req; - assign router_28_29_req_in[4] = magia_tile_ni_28_29_to_router_28_29_req; - - assign router_28_29_to_router_28_30_rsp = router_28_29_rsp_out[0]; - assign router_28_29_to_router_29_29_rsp = router_28_29_rsp_out[1]; - assign router_28_29_to_router_28_28_rsp = router_28_29_rsp_out[2]; - assign router_28_29_to_router_27_29_rsp = router_28_29_rsp_out[3]; - assign router_28_29_to_magia_tile_ni_28_29_rsp = router_28_29_rsp_out[4]; - - assign router_28_29_to_router_28_30_req = router_28_29_req_out[0]; - assign router_28_29_to_router_29_29_req = router_28_29_req_out[1]; - assign router_28_29_to_router_28_28_req = router_28_29_req_out[2]; - assign router_28_29_to_router_27_29_req = router_28_29_req_out[3]; - assign router_28_29_to_magia_tile_ni_28_29_req = router_28_29_req_out[4]; - - assign router_28_29_rsp_in[0] = router_28_30_to_router_28_29_rsp; - assign router_28_29_rsp_in[1] = router_29_29_to_router_28_29_rsp; - assign router_28_29_rsp_in[2] = router_28_28_to_router_28_29_rsp; - assign router_28_29_rsp_in[3] = router_27_29_to_router_28_29_rsp; - assign router_28_29_rsp_in[4] = magia_tile_ni_28_29_to_router_28_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_29_req_in), - .floo_rsp_o (router_28_29_rsp_out), - .floo_req_o (router_28_29_req_out), - .floo_rsp_i (router_28_29_rsp_in) -); - - -floo_req_t [4:0] router_28_30_req_in; -floo_rsp_t [4:0] router_28_30_rsp_out; -floo_req_t [4:0] router_28_30_req_out; -floo_rsp_t [4:0] router_28_30_rsp_in; - - assign router_28_30_req_in[0] = router_28_31_to_router_28_30_req; - assign router_28_30_req_in[1] = router_29_30_to_router_28_30_req; - assign router_28_30_req_in[2] = router_28_29_to_router_28_30_req; - assign router_28_30_req_in[3] = router_27_30_to_router_28_30_req; - assign router_28_30_req_in[4] = magia_tile_ni_28_30_to_router_28_30_req; - - assign router_28_30_to_router_28_31_rsp = router_28_30_rsp_out[0]; - assign router_28_30_to_router_29_30_rsp = router_28_30_rsp_out[1]; - assign router_28_30_to_router_28_29_rsp = router_28_30_rsp_out[2]; - assign router_28_30_to_router_27_30_rsp = router_28_30_rsp_out[3]; - assign router_28_30_to_magia_tile_ni_28_30_rsp = router_28_30_rsp_out[4]; - - assign router_28_30_to_router_28_31_req = router_28_30_req_out[0]; - assign router_28_30_to_router_29_30_req = router_28_30_req_out[1]; - assign router_28_30_to_router_28_29_req = router_28_30_req_out[2]; - assign router_28_30_to_router_27_30_req = router_28_30_req_out[3]; - assign router_28_30_to_magia_tile_ni_28_30_req = router_28_30_req_out[4]; - - assign router_28_30_rsp_in[0] = router_28_31_to_router_28_30_rsp; - assign router_28_30_rsp_in[1] = router_29_30_to_router_28_30_rsp; - assign router_28_30_rsp_in[2] = router_28_29_to_router_28_30_rsp; - assign router_28_30_rsp_in[3] = router_27_30_to_router_28_30_rsp; - assign router_28_30_rsp_in[4] = magia_tile_ni_28_30_to_router_28_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_30_req_in), - .floo_rsp_o (router_28_30_rsp_out), - .floo_req_o (router_28_30_req_out), - .floo_rsp_i (router_28_30_rsp_in) -); - - -floo_req_t [4:0] router_28_31_req_in; -floo_rsp_t [4:0] router_28_31_rsp_out; -floo_req_t [4:0] router_28_31_req_out; -floo_rsp_t [4:0] router_28_31_rsp_in; - - assign router_28_31_req_in[0] = '0; - assign router_28_31_req_in[1] = router_29_31_to_router_28_31_req; - assign router_28_31_req_in[2] = router_28_30_to_router_28_31_req; - assign router_28_31_req_in[3] = router_27_31_to_router_28_31_req; - assign router_28_31_req_in[4] = magia_tile_ni_28_31_to_router_28_31_req; - - assign router_28_31_to_router_29_31_rsp = router_28_31_rsp_out[1]; - assign router_28_31_to_router_28_30_rsp = router_28_31_rsp_out[2]; - assign router_28_31_to_router_27_31_rsp = router_28_31_rsp_out[3]; - assign router_28_31_to_magia_tile_ni_28_31_rsp = router_28_31_rsp_out[4]; - - assign router_28_31_to_router_29_31_req = router_28_31_req_out[1]; - assign router_28_31_to_router_28_30_req = router_28_31_req_out[2]; - assign router_28_31_to_router_27_31_req = router_28_31_req_out[3]; - assign router_28_31_to_magia_tile_ni_28_31_req = router_28_31_req_out[4]; - - assign router_28_31_rsp_in[0] = '0; - assign router_28_31_rsp_in[1] = router_29_31_to_router_28_31_rsp; - assign router_28_31_rsp_in[2] = router_28_30_to_router_28_31_rsp; - assign router_28_31_rsp_in[3] = router_27_31_to_router_28_31_rsp; - assign router_28_31_rsp_in[4] = magia_tile_ni_28_31_to_router_28_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_28_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 29, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_28_31_req_in), - .floo_rsp_o (router_28_31_rsp_out), - .floo_req_o (router_28_31_req_out), - .floo_rsp_i (router_28_31_rsp_in) -); - - -floo_req_t [4:0] router_29_0_req_in; -floo_rsp_t [4:0] router_29_0_rsp_out; -floo_req_t [4:0] router_29_0_req_out; -floo_rsp_t [4:0] router_29_0_rsp_in; - - assign router_29_0_req_in[0] = router_29_1_to_router_29_0_req; - assign router_29_0_req_in[1] = router_30_0_to_router_29_0_req; - assign router_29_0_req_in[2] = '0; - assign router_29_0_req_in[3] = router_28_0_to_router_29_0_req; - assign router_29_0_req_in[4] = magia_tile_ni_29_0_to_router_29_0_req; - - assign router_29_0_to_router_29_1_rsp = router_29_0_rsp_out[0]; - assign router_29_0_to_router_30_0_rsp = router_29_0_rsp_out[1]; - assign router_29_0_to_router_28_0_rsp = router_29_0_rsp_out[3]; - assign router_29_0_to_magia_tile_ni_29_0_rsp = router_29_0_rsp_out[4]; - - assign router_29_0_to_router_29_1_req = router_29_0_req_out[0]; - assign router_29_0_to_router_30_0_req = router_29_0_req_out[1]; - assign router_29_0_to_router_28_0_req = router_29_0_req_out[3]; - assign router_29_0_to_magia_tile_ni_29_0_req = router_29_0_req_out[4]; - - assign router_29_0_rsp_in[0] = router_29_1_to_router_29_0_rsp; - assign router_29_0_rsp_in[1] = router_30_0_to_router_29_0_rsp; - assign router_29_0_rsp_in[2] = '0; - assign router_29_0_rsp_in[3] = router_28_0_to_router_29_0_rsp; - assign router_29_0_rsp_in[4] = magia_tile_ni_29_0_to_router_29_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_0_req_in), - .floo_rsp_o (router_29_0_rsp_out), - .floo_req_o (router_29_0_req_out), - .floo_rsp_i (router_29_0_rsp_in) -); - - -floo_req_t [4:0] router_29_1_req_in; -floo_rsp_t [4:0] router_29_1_rsp_out; -floo_req_t [4:0] router_29_1_req_out; -floo_rsp_t [4:0] router_29_1_rsp_in; - - assign router_29_1_req_in[0] = router_29_2_to_router_29_1_req; - assign router_29_1_req_in[1] = router_30_1_to_router_29_1_req; - assign router_29_1_req_in[2] = router_29_0_to_router_29_1_req; - assign router_29_1_req_in[3] = router_28_1_to_router_29_1_req; - assign router_29_1_req_in[4] = magia_tile_ni_29_1_to_router_29_1_req; - - assign router_29_1_to_router_29_2_rsp = router_29_1_rsp_out[0]; - assign router_29_1_to_router_30_1_rsp = router_29_1_rsp_out[1]; - assign router_29_1_to_router_29_0_rsp = router_29_1_rsp_out[2]; - assign router_29_1_to_router_28_1_rsp = router_29_1_rsp_out[3]; - assign router_29_1_to_magia_tile_ni_29_1_rsp = router_29_1_rsp_out[4]; - - assign router_29_1_to_router_29_2_req = router_29_1_req_out[0]; - assign router_29_1_to_router_30_1_req = router_29_1_req_out[1]; - assign router_29_1_to_router_29_0_req = router_29_1_req_out[2]; - assign router_29_1_to_router_28_1_req = router_29_1_req_out[3]; - assign router_29_1_to_magia_tile_ni_29_1_req = router_29_1_req_out[4]; - - assign router_29_1_rsp_in[0] = router_29_2_to_router_29_1_rsp; - assign router_29_1_rsp_in[1] = router_30_1_to_router_29_1_rsp; - assign router_29_1_rsp_in[2] = router_29_0_to_router_29_1_rsp; - assign router_29_1_rsp_in[3] = router_28_1_to_router_29_1_rsp; - assign router_29_1_rsp_in[4] = magia_tile_ni_29_1_to_router_29_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_1_req_in), - .floo_rsp_o (router_29_1_rsp_out), - .floo_req_o (router_29_1_req_out), - .floo_rsp_i (router_29_1_rsp_in) -); - - -floo_req_t [4:0] router_29_2_req_in; -floo_rsp_t [4:0] router_29_2_rsp_out; -floo_req_t [4:0] router_29_2_req_out; -floo_rsp_t [4:0] router_29_2_rsp_in; - - assign router_29_2_req_in[0] = router_29_3_to_router_29_2_req; - assign router_29_2_req_in[1] = router_30_2_to_router_29_2_req; - assign router_29_2_req_in[2] = router_29_1_to_router_29_2_req; - assign router_29_2_req_in[3] = router_28_2_to_router_29_2_req; - assign router_29_2_req_in[4] = magia_tile_ni_29_2_to_router_29_2_req; - - assign router_29_2_to_router_29_3_rsp = router_29_2_rsp_out[0]; - assign router_29_2_to_router_30_2_rsp = router_29_2_rsp_out[1]; - assign router_29_2_to_router_29_1_rsp = router_29_2_rsp_out[2]; - assign router_29_2_to_router_28_2_rsp = router_29_2_rsp_out[3]; - assign router_29_2_to_magia_tile_ni_29_2_rsp = router_29_2_rsp_out[4]; - - assign router_29_2_to_router_29_3_req = router_29_2_req_out[0]; - assign router_29_2_to_router_30_2_req = router_29_2_req_out[1]; - assign router_29_2_to_router_29_1_req = router_29_2_req_out[2]; - assign router_29_2_to_router_28_2_req = router_29_2_req_out[3]; - assign router_29_2_to_magia_tile_ni_29_2_req = router_29_2_req_out[4]; - - assign router_29_2_rsp_in[0] = router_29_3_to_router_29_2_rsp; - assign router_29_2_rsp_in[1] = router_30_2_to_router_29_2_rsp; - assign router_29_2_rsp_in[2] = router_29_1_to_router_29_2_rsp; - assign router_29_2_rsp_in[3] = router_28_2_to_router_29_2_rsp; - assign router_29_2_rsp_in[4] = magia_tile_ni_29_2_to_router_29_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_2_req_in), - .floo_rsp_o (router_29_2_rsp_out), - .floo_req_o (router_29_2_req_out), - .floo_rsp_i (router_29_2_rsp_in) -); - - -floo_req_t [4:0] router_29_3_req_in; -floo_rsp_t [4:0] router_29_3_rsp_out; -floo_req_t [4:0] router_29_3_req_out; -floo_rsp_t [4:0] router_29_3_rsp_in; - - assign router_29_3_req_in[0] = router_29_4_to_router_29_3_req; - assign router_29_3_req_in[1] = router_30_3_to_router_29_3_req; - assign router_29_3_req_in[2] = router_29_2_to_router_29_3_req; - assign router_29_3_req_in[3] = router_28_3_to_router_29_3_req; - assign router_29_3_req_in[4] = magia_tile_ni_29_3_to_router_29_3_req; - - assign router_29_3_to_router_29_4_rsp = router_29_3_rsp_out[0]; - assign router_29_3_to_router_30_3_rsp = router_29_3_rsp_out[1]; - assign router_29_3_to_router_29_2_rsp = router_29_3_rsp_out[2]; - assign router_29_3_to_router_28_3_rsp = router_29_3_rsp_out[3]; - assign router_29_3_to_magia_tile_ni_29_3_rsp = router_29_3_rsp_out[4]; - - assign router_29_3_to_router_29_4_req = router_29_3_req_out[0]; - assign router_29_3_to_router_30_3_req = router_29_3_req_out[1]; - assign router_29_3_to_router_29_2_req = router_29_3_req_out[2]; - assign router_29_3_to_router_28_3_req = router_29_3_req_out[3]; - assign router_29_3_to_magia_tile_ni_29_3_req = router_29_3_req_out[4]; - - assign router_29_3_rsp_in[0] = router_29_4_to_router_29_3_rsp; - assign router_29_3_rsp_in[1] = router_30_3_to_router_29_3_rsp; - assign router_29_3_rsp_in[2] = router_29_2_to_router_29_3_rsp; - assign router_29_3_rsp_in[3] = router_28_3_to_router_29_3_rsp; - assign router_29_3_rsp_in[4] = magia_tile_ni_29_3_to_router_29_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_3_req_in), - .floo_rsp_o (router_29_3_rsp_out), - .floo_req_o (router_29_3_req_out), - .floo_rsp_i (router_29_3_rsp_in) -); - - -floo_req_t [4:0] router_29_4_req_in; -floo_rsp_t [4:0] router_29_4_rsp_out; -floo_req_t [4:0] router_29_4_req_out; -floo_rsp_t [4:0] router_29_4_rsp_in; - - assign router_29_4_req_in[0] = router_29_5_to_router_29_4_req; - assign router_29_4_req_in[1] = router_30_4_to_router_29_4_req; - assign router_29_4_req_in[2] = router_29_3_to_router_29_4_req; - assign router_29_4_req_in[3] = router_28_4_to_router_29_4_req; - assign router_29_4_req_in[4] = magia_tile_ni_29_4_to_router_29_4_req; - - assign router_29_4_to_router_29_5_rsp = router_29_4_rsp_out[0]; - assign router_29_4_to_router_30_4_rsp = router_29_4_rsp_out[1]; - assign router_29_4_to_router_29_3_rsp = router_29_4_rsp_out[2]; - assign router_29_4_to_router_28_4_rsp = router_29_4_rsp_out[3]; - assign router_29_4_to_magia_tile_ni_29_4_rsp = router_29_4_rsp_out[4]; - - assign router_29_4_to_router_29_5_req = router_29_4_req_out[0]; - assign router_29_4_to_router_30_4_req = router_29_4_req_out[1]; - assign router_29_4_to_router_29_3_req = router_29_4_req_out[2]; - assign router_29_4_to_router_28_4_req = router_29_4_req_out[3]; - assign router_29_4_to_magia_tile_ni_29_4_req = router_29_4_req_out[4]; - - assign router_29_4_rsp_in[0] = router_29_5_to_router_29_4_rsp; - assign router_29_4_rsp_in[1] = router_30_4_to_router_29_4_rsp; - assign router_29_4_rsp_in[2] = router_29_3_to_router_29_4_rsp; - assign router_29_4_rsp_in[3] = router_28_4_to_router_29_4_rsp; - assign router_29_4_rsp_in[4] = magia_tile_ni_29_4_to_router_29_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_4_req_in), - .floo_rsp_o (router_29_4_rsp_out), - .floo_req_o (router_29_4_req_out), - .floo_rsp_i (router_29_4_rsp_in) -); - - -floo_req_t [4:0] router_29_5_req_in; -floo_rsp_t [4:0] router_29_5_rsp_out; -floo_req_t [4:0] router_29_5_req_out; -floo_rsp_t [4:0] router_29_5_rsp_in; - - assign router_29_5_req_in[0] = router_29_6_to_router_29_5_req; - assign router_29_5_req_in[1] = router_30_5_to_router_29_5_req; - assign router_29_5_req_in[2] = router_29_4_to_router_29_5_req; - assign router_29_5_req_in[3] = router_28_5_to_router_29_5_req; - assign router_29_5_req_in[4] = magia_tile_ni_29_5_to_router_29_5_req; - - assign router_29_5_to_router_29_6_rsp = router_29_5_rsp_out[0]; - assign router_29_5_to_router_30_5_rsp = router_29_5_rsp_out[1]; - assign router_29_5_to_router_29_4_rsp = router_29_5_rsp_out[2]; - assign router_29_5_to_router_28_5_rsp = router_29_5_rsp_out[3]; - assign router_29_5_to_magia_tile_ni_29_5_rsp = router_29_5_rsp_out[4]; - - assign router_29_5_to_router_29_6_req = router_29_5_req_out[0]; - assign router_29_5_to_router_30_5_req = router_29_5_req_out[1]; - assign router_29_5_to_router_29_4_req = router_29_5_req_out[2]; - assign router_29_5_to_router_28_5_req = router_29_5_req_out[3]; - assign router_29_5_to_magia_tile_ni_29_5_req = router_29_5_req_out[4]; - - assign router_29_5_rsp_in[0] = router_29_6_to_router_29_5_rsp; - assign router_29_5_rsp_in[1] = router_30_5_to_router_29_5_rsp; - assign router_29_5_rsp_in[2] = router_29_4_to_router_29_5_rsp; - assign router_29_5_rsp_in[3] = router_28_5_to_router_29_5_rsp; - assign router_29_5_rsp_in[4] = magia_tile_ni_29_5_to_router_29_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_5_req_in), - .floo_rsp_o (router_29_5_rsp_out), - .floo_req_o (router_29_5_req_out), - .floo_rsp_i (router_29_5_rsp_in) -); - - -floo_req_t [4:0] router_29_6_req_in; -floo_rsp_t [4:0] router_29_6_rsp_out; -floo_req_t [4:0] router_29_6_req_out; -floo_rsp_t [4:0] router_29_6_rsp_in; - - assign router_29_6_req_in[0] = router_29_7_to_router_29_6_req; - assign router_29_6_req_in[1] = router_30_6_to_router_29_6_req; - assign router_29_6_req_in[2] = router_29_5_to_router_29_6_req; - assign router_29_6_req_in[3] = router_28_6_to_router_29_6_req; - assign router_29_6_req_in[4] = magia_tile_ni_29_6_to_router_29_6_req; - - assign router_29_6_to_router_29_7_rsp = router_29_6_rsp_out[0]; - assign router_29_6_to_router_30_6_rsp = router_29_6_rsp_out[1]; - assign router_29_6_to_router_29_5_rsp = router_29_6_rsp_out[2]; - assign router_29_6_to_router_28_6_rsp = router_29_6_rsp_out[3]; - assign router_29_6_to_magia_tile_ni_29_6_rsp = router_29_6_rsp_out[4]; - - assign router_29_6_to_router_29_7_req = router_29_6_req_out[0]; - assign router_29_6_to_router_30_6_req = router_29_6_req_out[1]; - assign router_29_6_to_router_29_5_req = router_29_6_req_out[2]; - assign router_29_6_to_router_28_6_req = router_29_6_req_out[3]; - assign router_29_6_to_magia_tile_ni_29_6_req = router_29_6_req_out[4]; - - assign router_29_6_rsp_in[0] = router_29_7_to_router_29_6_rsp; - assign router_29_6_rsp_in[1] = router_30_6_to_router_29_6_rsp; - assign router_29_6_rsp_in[2] = router_29_5_to_router_29_6_rsp; - assign router_29_6_rsp_in[3] = router_28_6_to_router_29_6_rsp; - assign router_29_6_rsp_in[4] = magia_tile_ni_29_6_to_router_29_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_6_req_in), - .floo_rsp_o (router_29_6_rsp_out), - .floo_req_o (router_29_6_req_out), - .floo_rsp_i (router_29_6_rsp_in) -); - - -floo_req_t [4:0] router_29_7_req_in; -floo_rsp_t [4:0] router_29_7_rsp_out; -floo_req_t [4:0] router_29_7_req_out; -floo_rsp_t [4:0] router_29_7_rsp_in; - - assign router_29_7_req_in[0] = router_29_8_to_router_29_7_req; - assign router_29_7_req_in[1] = router_30_7_to_router_29_7_req; - assign router_29_7_req_in[2] = router_29_6_to_router_29_7_req; - assign router_29_7_req_in[3] = router_28_7_to_router_29_7_req; - assign router_29_7_req_in[4] = magia_tile_ni_29_7_to_router_29_7_req; - - assign router_29_7_to_router_29_8_rsp = router_29_7_rsp_out[0]; - assign router_29_7_to_router_30_7_rsp = router_29_7_rsp_out[1]; - assign router_29_7_to_router_29_6_rsp = router_29_7_rsp_out[2]; - assign router_29_7_to_router_28_7_rsp = router_29_7_rsp_out[3]; - assign router_29_7_to_magia_tile_ni_29_7_rsp = router_29_7_rsp_out[4]; - - assign router_29_7_to_router_29_8_req = router_29_7_req_out[0]; - assign router_29_7_to_router_30_7_req = router_29_7_req_out[1]; - assign router_29_7_to_router_29_6_req = router_29_7_req_out[2]; - assign router_29_7_to_router_28_7_req = router_29_7_req_out[3]; - assign router_29_7_to_magia_tile_ni_29_7_req = router_29_7_req_out[4]; - - assign router_29_7_rsp_in[0] = router_29_8_to_router_29_7_rsp; - assign router_29_7_rsp_in[1] = router_30_7_to_router_29_7_rsp; - assign router_29_7_rsp_in[2] = router_29_6_to_router_29_7_rsp; - assign router_29_7_rsp_in[3] = router_28_7_to_router_29_7_rsp; - assign router_29_7_rsp_in[4] = magia_tile_ni_29_7_to_router_29_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_7_req_in), - .floo_rsp_o (router_29_7_rsp_out), - .floo_req_o (router_29_7_req_out), - .floo_rsp_i (router_29_7_rsp_in) -); - - -floo_req_t [4:0] router_29_8_req_in; -floo_rsp_t [4:0] router_29_8_rsp_out; -floo_req_t [4:0] router_29_8_req_out; -floo_rsp_t [4:0] router_29_8_rsp_in; - - assign router_29_8_req_in[0] = router_29_9_to_router_29_8_req; - assign router_29_8_req_in[1] = router_30_8_to_router_29_8_req; - assign router_29_8_req_in[2] = router_29_7_to_router_29_8_req; - assign router_29_8_req_in[3] = router_28_8_to_router_29_8_req; - assign router_29_8_req_in[4] = magia_tile_ni_29_8_to_router_29_8_req; - - assign router_29_8_to_router_29_9_rsp = router_29_8_rsp_out[0]; - assign router_29_8_to_router_30_8_rsp = router_29_8_rsp_out[1]; - assign router_29_8_to_router_29_7_rsp = router_29_8_rsp_out[2]; - assign router_29_8_to_router_28_8_rsp = router_29_8_rsp_out[3]; - assign router_29_8_to_magia_tile_ni_29_8_rsp = router_29_8_rsp_out[4]; - - assign router_29_8_to_router_29_9_req = router_29_8_req_out[0]; - assign router_29_8_to_router_30_8_req = router_29_8_req_out[1]; - assign router_29_8_to_router_29_7_req = router_29_8_req_out[2]; - assign router_29_8_to_router_28_8_req = router_29_8_req_out[3]; - assign router_29_8_to_magia_tile_ni_29_8_req = router_29_8_req_out[4]; - - assign router_29_8_rsp_in[0] = router_29_9_to_router_29_8_rsp; - assign router_29_8_rsp_in[1] = router_30_8_to_router_29_8_rsp; - assign router_29_8_rsp_in[2] = router_29_7_to_router_29_8_rsp; - assign router_29_8_rsp_in[3] = router_28_8_to_router_29_8_rsp; - assign router_29_8_rsp_in[4] = magia_tile_ni_29_8_to_router_29_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_8_req_in), - .floo_rsp_o (router_29_8_rsp_out), - .floo_req_o (router_29_8_req_out), - .floo_rsp_i (router_29_8_rsp_in) -); - - -floo_req_t [4:0] router_29_9_req_in; -floo_rsp_t [4:0] router_29_9_rsp_out; -floo_req_t [4:0] router_29_9_req_out; -floo_rsp_t [4:0] router_29_9_rsp_in; - - assign router_29_9_req_in[0] = router_29_10_to_router_29_9_req; - assign router_29_9_req_in[1] = router_30_9_to_router_29_9_req; - assign router_29_9_req_in[2] = router_29_8_to_router_29_9_req; - assign router_29_9_req_in[3] = router_28_9_to_router_29_9_req; - assign router_29_9_req_in[4] = magia_tile_ni_29_9_to_router_29_9_req; - - assign router_29_9_to_router_29_10_rsp = router_29_9_rsp_out[0]; - assign router_29_9_to_router_30_9_rsp = router_29_9_rsp_out[1]; - assign router_29_9_to_router_29_8_rsp = router_29_9_rsp_out[2]; - assign router_29_9_to_router_28_9_rsp = router_29_9_rsp_out[3]; - assign router_29_9_to_magia_tile_ni_29_9_rsp = router_29_9_rsp_out[4]; - - assign router_29_9_to_router_29_10_req = router_29_9_req_out[0]; - assign router_29_9_to_router_30_9_req = router_29_9_req_out[1]; - assign router_29_9_to_router_29_8_req = router_29_9_req_out[2]; - assign router_29_9_to_router_28_9_req = router_29_9_req_out[3]; - assign router_29_9_to_magia_tile_ni_29_9_req = router_29_9_req_out[4]; - - assign router_29_9_rsp_in[0] = router_29_10_to_router_29_9_rsp; - assign router_29_9_rsp_in[1] = router_30_9_to_router_29_9_rsp; - assign router_29_9_rsp_in[2] = router_29_8_to_router_29_9_rsp; - assign router_29_9_rsp_in[3] = router_28_9_to_router_29_9_rsp; - assign router_29_9_rsp_in[4] = magia_tile_ni_29_9_to_router_29_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_9_req_in), - .floo_rsp_o (router_29_9_rsp_out), - .floo_req_o (router_29_9_req_out), - .floo_rsp_i (router_29_9_rsp_in) -); - - -floo_req_t [4:0] router_29_10_req_in; -floo_rsp_t [4:0] router_29_10_rsp_out; -floo_req_t [4:0] router_29_10_req_out; -floo_rsp_t [4:0] router_29_10_rsp_in; - - assign router_29_10_req_in[0] = router_29_11_to_router_29_10_req; - assign router_29_10_req_in[1] = router_30_10_to_router_29_10_req; - assign router_29_10_req_in[2] = router_29_9_to_router_29_10_req; - assign router_29_10_req_in[3] = router_28_10_to_router_29_10_req; - assign router_29_10_req_in[4] = magia_tile_ni_29_10_to_router_29_10_req; - - assign router_29_10_to_router_29_11_rsp = router_29_10_rsp_out[0]; - assign router_29_10_to_router_30_10_rsp = router_29_10_rsp_out[1]; - assign router_29_10_to_router_29_9_rsp = router_29_10_rsp_out[2]; - assign router_29_10_to_router_28_10_rsp = router_29_10_rsp_out[3]; - assign router_29_10_to_magia_tile_ni_29_10_rsp = router_29_10_rsp_out[4]; - - assign router_29_10_to_router_29_11_req = router_29_10_req_out[0]; - assign router_29_10_to_router_30_10_req = router_29_10_req_out[1]; - assign router_29_10_to_router_29_9_req = router_29_10_req_out[2]; - assign router_29_10_to_router_28_10_req = router_29_10_req_out[3]; - assign router_29_10_to_magia_tile_ni_29_10_req = router_29_10_req_out[4]; - - assign router_29_10_rsp_in[0] = router_29_11_to_router_29_10_rsp; - assign router_29_10_rsp_in[1] = router_30_10_to_router_29_10_rsp; - assign router_29_10_rsp_in[2] = router_29_9_to_router_29_10_rsp; - assign router_29_10_rsp_in[3] = router_28_10_to_router_29_10_rsp; - assign router_29_10_rsp_in[4] = magia_tile_ni_29_10_to_router_29_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_10_req_in), - .floo_rsp_o (router_29_10_rsp_out), - .floo_req_o (router_29_10_req_out), - .floo_rsp_i (router_29_10_rsp_in) -); - - -floo_req_t [4:0] router_29_11_req_in; -floo_rsp_t [4:0] router_29_11_rsp_out; -floo_req_t [4:0] router_29_11_req_out; -floo_rsp_t [4:0] router_29_11_rsp_in; - - assign router_29_11_req_in[0] = router_29_12_to_router_29_11_req; - assign router_29_11_req_in[1] = router_30_11_to_router_29_11_req; - assign router_29_11_req_in[2] = router_29_10_to_router_29_11_req; - assign router_29_11_req_in[3] = router_28_11_to_router_29_11_req; - assign router_29_11_req_in[4] = magia_tile_ni_29_11_to_router_29_11_req; - - assign router_29_11_to_router_29_12_rsp = router_29_11_rsp_out[0]; - assign router_29_11_to_router_30_11_rsp = router_29_11_rsp_out[1]; - assign router_29_11_to_router_29_10_rsp = router_29_11_rsp_out[2]; - assign router_29_11_to_router_28_11_rsp = router_29_11_rsp_out[3]; - assign router_29_11_to_magia_tile_ni_29_11_rsp = router_29_11_rsp_out[4]; - - assign router_29_11_to_router_29_12_req = router_29_11_req_out[0]; - assign router_29_11_to_router_30_11_req = router_29_11_req_out[1]; - assign router_29_11_to_router_29_10_req = router_29_11_req_out[2]; - assign router_29_11_to_router_28_11_req = router_29_11_req_out[3]; - assign router_29_11_to_magia_tile_ni_29_11_req = router_29_11_req_out[4]; - - assign router_29_11_rsp_in[0] = router_29_12_to_router_29_11_rsp; - assign router_29_11_rsp_in[1] = router_30_11_to_router_29_11_rsp; - assign router_29_11_rsp_in[2] = router_29_10_to_router_29_11_rsp; - assign router_29_11_rsp_in[3] = router_28_11_to_router_29_11_rsp; - assign router_29_11_rsp_in[4] = magia_tile_ni_29_11_to_router_29_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_11_req_in), - .floo_rsp_o (router_29_11_rsp_out), - .floo_req_o (router_29_11_req_out), - .floo_rsp_i (router_29_11_rsp_in) -); - - -floo_req_t [4:0] router_29_12_req_in; -floo_rsp_t [4:0] router_29_12_rsp_out; -floo_req_t [4:0] router_29_12_req_out; -floo_rsp_t [4:0] router_29_12_rsp_in; - - assign router_29_12_req_in[0] = router_29_13_to_router_29_12_req; - assign router_29_12_req_in[1] = router_30_12_to_router_29_12_req; - assign router_29_12_req_in[2] = router_29_11_to_router_29_12_req; - assign router_29_12_req_in[3] = router_28_12_to_router_29_12_req; - assign router_29_12_req_in[4] = magia_tile_ni_29_12_to_router_29_12_req; - - assign router_29_12_to_router_29_13_rsp = router_29_12_rsp_out[0]; - assign router_29_12_to_router_30_12_rsp = router_29_12_rsp_out[1]; - assign router_29_12_to_router_29_11_rsp = router_29_12_rsp_out[2]; - assign router_29_12_to_router_28_12_rsp = router_29_12_rsp_out[3]; - assign router_29_12_to_magia_tile_ni_29_12_rsp = router_29_12_rsp_out[4]; - - assign router_29_12_to_router_29_13_req = router_29_12_req_out[0]; - assign router_29_12_to_router_30_12_req = router_29_12_req_out[1]; - assign router_29_12_to_router_29_11_req = router_29_12_req_out[2]; - assign router_29_12_to_router_28_12_req = router_29_12_req_out[3]; - assign router_29_12_to_magia_tile_ni_29_12_req = router_29_12_req_out[4]; - - assign router_29_12_rsp_in[0] = router_29_13_to_router_29_12_rsp; - assign router_29_12_rsp_in[1] = router_30_12_to_router_29_12_rsp; - assign router_29_12_rsp_in[2] = router_29_11_to_router_29_12_rsp; - assign router_29_12_rsp_in[3] = router_28_12_to_router_29_12_rsp; - assign router_29_12_rsp_in[4] = magia_tile_ni_29_12_to_router_29_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_12_req_in), - .floo_rsp_o (router_29_12_rsp_out), - .floo_req_o (router_29_12_req_out), - .floo_rsp_i (router_29_12_rsp_in) -); - - -floo_req_t [4:0] router_29_13_req_in; -floo_rsp_t [4:0] router_29_13_rsp_out; -floo_req_t [4:0] router_29_13_req_out; -floo_rsp_t [4:0] router_29_13_rsp_in; - - assign router_29_13_req_in[0] = router_29_14_to_router_29_13_req; - assign router_29_13_req_in[1] = router_30_13_to_router_29_13_req; - assign router_29_13_req_in[2] = router_29_12_to_router_29_13_req; - assign router_29_13_req_in[3] = router_28_13_to_router_29_13_req; - assign router_29_13_req_in[4] = magia_tile_ni_29_13_to_router_29_13_req; - - assign router_29_13_to_router_29_14_rsp = router_29_13_rsp_out[0]; - assign router_29_13_to_router_30_13_rsp = router_29_13_rsp_out[1]; - assign router_29_13_to_router_29_12_rsp = router_29_13_rsp_out[2]; - assign router_29_13_to_router_28_13_rsp = router_29_13_rsp_out[3]; - assign router_29_13_to_magia_tile_ni_29_13_rsp = router_29_13_rsp_out[4]; - - assign router_29_13_to_router_29_14_req = router_29_13_req_out[0]; - assign router_29_13_to_router_30_13_req = router_29_13_req_out[1]; - assign router_29_13_to_router_29_12_req = router_29_13_req_out[2]; - assign router_29_13_to_router_28_13_req = router_29_13_req_out[3]; - assign router_29_13_to_magia_tile_ni_29_13_req = router_29_13_req_out[4]; - - assign router_29_13_rsp_in[0] = router_29_14_to_router_29_13_rsp; - assign router_29_13_rsp_in[1] = router_30_13_to_router_29_13_rsp; - assign router_29_13_rsp_in[2] = router_29_12_to_router_29_13_rsp; - assign router_29_13_rsp_in[3] = router_28_13_to_router_29_13_rsp; - assign router_29_13_rsp_in[4] = magia_tile_ni_29_13_to_router_29_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_13_req_in), - .floo_rsp_o (router_29_13_rsp_out), - .floo_req_o (router_29_13_req_out), - .floo_rsp_i (router_29_13_rsp_in) -); - - -floo_req_t [4:0] router_29_14_req_in; -floo_rsp_t [4:0] router_29_14_rsp_out; -floo_req_t [4:0] router_29_14_req_out; -floo_rsp_t [4:0] router_29_14_rsp_in; - - assign router_29_14_req_in[0] = router_29_15_to_router_29_14_req; - assign router_29_14_req_in[1] = router_30_14_to_router_29_14_req; - assign router_29_14_req_in[2] = router_29_13_to_router_29_14_req; - assign router_29_14_req_in[3] = router_28_14_to_router_29_14_req; - assign router_29_14_req_in[4] = magia_tile_ni_29_14_to_router_29_14_req; - - assign router_29_14_to_router_29_15_rsp = router_29_14_rsp_out[0]; - assign router_29_14_to_router_30_14_rsp = router_29_14_rsp_out[1]; - assign router_29_14_to_router_29_13_rsp = router_29_14_rsp_out[2]; - assign router_29_14_to_router_28_14_rsp = router_29_14_rsp_out[3]; - assign router_29_14_to_magia_tile_ni_29_14_rsp = router_29_14_rsp_out[4]; - - assign router_29_14_to_router_29_15_req = router_29_14_req_out[0]; - assign router_29_14_to_router_30_14_req = router_29_14_req_out[1]; - assign router_29_14_to_router_29_13_req = router_29_14_req_out[2]; - assign router_29_14_to_router_28_14_req = router_29_14_req_out[3]; - assign router_29_14_to_magia_tile_ni_29_14_req = router_29_14_req_out[4]; - - assign router_29_14_rsp_in[0] = router_29_15_to_router_29_14_rsp; - assign router_29_14_rsp_in[1] = router_30_14_to_router_29_14_rsp; - assign router_29_14_rsp_in[2] = router_29_13_to_router_29_14_rsp; - assign router_29_14_rsp_in[3] = router_28_14_to_router_29_14_rsp; - assign router_29_14_rsp_in[4] = magia_tile_ni_29_14_to_router_29_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_14_req_in), - .floo_rsp_o (router_29_14_rsp_out), - .floo_req_o (router_29_14_req_out), - .floo_rsp_i (router_29_14_rsp_in) -); - - -floo_req_t [4:0] router_29_15_req_in; -floo_rsp_t [4:0] router_29_15_rsp_out; -floo_req_t [4:0] router_29_15_req_out; -floo_rsp_t [4:0] router_29_15_rsp_in; - - assign router_29_15_req_in[0] = router_29_16_to_router_29_15_req; - assign router_29_15_req_in[1] = router_30_15_to_router_29_15_req; - assign router_29_15_req_in[2] = router_29_14_to_router_29_15_req; - assign router_29_15_req_in[3] = router_28_15_to_router_29_15_req; - assign router_29_15_req_in[4] = magia_tile_ni_29_15_to_router_29_15_req; - - assign router_29_15_to_router_29_16_rsp = router_29_15_rsp_out[0]; - assign router_29_15_to_router_30_15_rsp = router_29_15_rsp_out[1]; - assign router_29_15_to_router_29_14_rsp = router_29_15_rsp_out[2]; - assign router_29_15_to_router_28_15_rsp = router_29_15_rsp_out[3]; - assign router_29_15_to_magia_tile_ni_29_15_rsp = router_29_15_rsp_out[4]; - - assign router_29_15_to_router_29_16_req = router_29_15_req_out[0]; - assign router_29_15_to_router_30_15_req = router_29_15_req_out[1]; - assign router_29_15_to_router_29_14_req = router_29_15_req_out[2]; - assign router_29_15_to_router_28_15_req = router_29_15_req_out[3]; - assign router_29_15_to_magia_tile_ni_29_15_req = router_29_15_req_out[4]; - - assign router_29_15_rsp_in[0] = router_29_16_to_router_29_15_rsp; - assign router_29_15_rsp_in[1] = router_30_15_to_router_29_15_rsp; - assign router_29_15_rsp_in[2] = router_29_14_to_router_29_15_rsp; - assign router_29_15_rsp_in[3] = router_28_15_to_router_29_15_rsp; - assign router_29_15_rsp_in[4] = magia_tile_ni_29_15_to_router_29_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_15_req_in), - .floo_rsp_o (router_29_15_rsp_out), - .floo_req_o (router_29_15_req_out), - .floo_rsp_i (router_29_15_rsp_in) -); - - -floo_req_t [4:0] router_29_16_req_in; -floo_rsp_t [4:0] router_29_16_rsp_out; -floo_req_t [4:0] router_29_16_req_out; -floo_rsp_t [4:0] router_29_16_rsp_in; - - assign router_29_16_req_in[0] = router_29_17_to_router_29_16_req; - assign router_29_16_req_in[1] = router_30_16_to_router_29_16_req; - assign router_29_16_req_in[2] = router_29_15_to_router_29_16_req; - assign router_29_16_req_in[3] = router_28_16_to_router_29_16_req; - assign router_29_16_req_in[4] = magia_tile_ni_29_16_to_router_29_16_req; - - assign router_29_16_to_router_29_17_rsp = router_29_16_rsp_out[0]; - assign router_29_16_to_router_30_16_rsp = router_29_16_rsp_out[1]; - assign router_29_16_to_router_29_15_rsp = router_29_16_rsp_out[2]; - assign router_29_16_to_router_28_16_rsp = router_29_16_rsp_out[3]; - assign router_29_16_to_magia_tile_ni_29_16_rsp = router_29_16_rsp_out[4]; - - assign router_29_16_to_router_29_17_req = router_29_16_req_out[0]; - assign router_29_16_to_router_30_16_req = router_29_16_req_out[1]; - assign router_29_16_to_router_29_15_req = router_29_16_req_out[2]; - assign router_29_16_to_router_28_16_req = router_29_16_req_out[3]; - assign router_29_16_to_magia_tile_ni_29_16_req = router_29_16_req_out[4]; - - assign router_29_16_rsp_in[0] = router_29_17_to_router_29_16_rsp; - assign router_29_16_rsp_in[1] = router_30_16_to_router_29_16_rsp; - assign router_29_16_rsp_in[2] = router_29_15_to_router_29_16_rsp; - assign router_29_16_rsp_in[3] = router_28_16_to_router_29_16_rsp; - assign router_29_16_rsp_in[4] = magia_tile_ni_29_16_to_router_29_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_16_req_in), - .floo_rsp_o (router_29_16_rsp_out), - .floo_req_o (router_29_16_req_out), - .floo_rsp_i (router_29_16_rsp_in) -); - - -floo_req_t [4:0] router_29_17_req_in; -floo_rsp_t [4:0] router_29_17_rsp_out; -floo_req_t [4:0] router_29_17_req_out; -floo_rsp_t [4:0] router_29_17_rsp_in; - - assign router_29_17_req_in[0] = router_29_18_to_router_29_17_req; - assign router_29_17_req_in[1] = router_30_17_to_router_29_17_req; - assign router_29_17_req_in[2] = router_29_16_to_router_29_17_req; - assign router_29_17_req_in[3] = router_28_17_to_router_29_17_req; - assign router_29_17_req_in[4] = magia_tile_ni_29_17_to_router_29_17_req; - - assign router_29_17_to_router_29_18_rsp = router_29_17_rsp_out[0]; - assign router_29_17_to_router_30_17_rsp = router_29_17_rsp_out[1]; - assign router_29_17_to_router_29_16_rsp = router_29_17_rsp_out[2]; - assign router_29_17_to_router_28_17_rsp = router_29_17_rsp_out[3]; - assign router_29_17_to_magia_tile_ni_29_17_rsp = router_29_17_rsp_out[4]; - - assign router_29_17_to_router_29_18_req = router_29_17_req_out[0]; - assign router_29_17_to_router_30_17_req = router_29_17_req_out[1]; - assign router_29_17_to_router_29_16_req = router_29_17_req_out[2]; - assign router_29_17_to_router_28_17_req = router_29_17_req_out[3]; - assign router_29_17_to_magia_tile_ni_29_17_req = router_29_17_req_out[4]; - - assign router_29_17_rsp_in[0] = router_29_18_to_router_29_17_rsp; - assign router_29_17_rsp_in[1] = router_30_17_to_router_29_17_rsp; - assign router_29_17_rsp_in[2] = router_29_16_to_router_29_17_rsp; - assign router_29_17_rsp_in[3] = router_28_17_to_router_29_17_rsp; - assign router_29_17_rsp_in[4] = magia_tile_ni_29_17_to_router_29_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_17_req_in), - .floo_rsp_o (router_29_17_rsp_out), - .floo_req_o (router_29_17_req_out), - .floo_rsp_i (router_29_17_rsp_in) -); - - -floo_req_t [4:0] router_29_18_req_in; -floo_rsp_t [4:0] router_29_18_rsp_out; -floo_req_t [4:0] router_29_18_req_out; -floo_rsp_t [4:0] router_29_18_rsp_in; - - assign router_29_18_req_in[0] = router_29_19_to_router_29_18_req; - assign router_29_18_req_in[1] = router_30_18_to_router_29_18_req; - assign router_29_18_req_in[2] = router_29_17_to_router_29_18_req; - assign router_29_18_req_in[3] = router_28_18_to_router_29_18_req; - assign router_29_18_req_in[4] = magia_tile_ni_29_18_to_router_29_18_req; - - assign router_29_18_to_router_29_19_rsp = router_29_18_rsp_out[0]; - assign router_29_18_to_router_30_18_rsp = router_29_18_rsp_out[1]; - assign router_29_18_to_router_29_17_rsp = router_29_18_rsp_out[2]; - assign router_29_18_to_router_28_18_rsp = router_29_18_rsp_out[3]; - assign router_29_18_to_magia_tile_ni_29_18_rsp = router_29_18_rsp_out[4]; - - assign router_29_18_to_router_29_19_req = router_29_18_req_out[0]; - assign router_29_18_to_router_30_18_req = router_29_18_req_out[1]; - assign router_29_18_to_router_29_17_req = router_29_18_req_out[2]; - assign router_29_18_to_router_28_18_req = router_29_18_req_out[3]; - assign router_29_18_to_magia_tile_ni_29_18_req = router_29_18_req_out[4]; - - assign router_29_18_rsp_in[0] = router_29_19_to_router_29_18_rsp; - assign router_29_18_rsp_in[1] = router_30_18_to_router_29_18_rsp; - assign router_29_18_rsp_in[2] = router_29_17_to_router_29_18_rsp; - assign router_29_18_rsp_in[3] = router_28_18_to_router_29_18_rsp; - assign router_29_18_rsp_in[4] = magia_tile_ni_29_18_to_router_29_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_18_req_in), - .floo_rsp_o (router_29_18_rsp_out), - .floo_req_o (router_29_18_req_out), - .floo_rsp_i (router_29_18_rsp_in) -); - - -floo_req_t [4:0] router_29_19_req_in; -floo_rsp_t [4:0] router_29_19_rsp_out; -floo_req_t [4:0] router_29_19_req_out; -floo_rsp_t [4:0] router_29_19_rsp_in; - - assign router_29_19_req_in[0] = router_29_20_to_router_29_19_req; - assign router_29_19_req_in[1] = router_30_19_to_router_29_19_req; - assign router_29_19_req_in[2] = router_29_18_to_router_29_19_req; - assign router_29_19_req_in[3] = router_28_19_to_router_29_19_req; - assign router_29_19_req_in[4] = magia_tile_ni_29_19_to_router_29_19_req; - - assign router_29_19_to_router_29_20_rsp = router_29_19_rsp_out[0]; - assign router_29_19_to_router_30_19_rsp = router_29_19_rsp_out[1]; - assign router_29_19_to_router_29_18_rsp = router_29_19_rsp_out[2]; - assign router_29_19_to_router_28_19_rsp = router_29_19_rsp_out[3]; - assign router_29_19_to_magia_tile_ni_29_19_rsp = router_29_19_rsp_out[4]; - - assign router_29_19_to_router_29_20_req = router_29_19_req_out[0]; - assign router_29_19_to_router_30_19_req = router_29_19_req_out[1]; - assign router_29_19_to_router_29_18_req = router_29_19_req_out[2]; - assign router_29_19_to_router_28_19_req = router_29_19_req_out[3]; - assign router_29_19_to_magia_tile_ni_29_19_req = router_29_19_req_out[4]; - - assign router_29_19_rsp_in[0] = router_29_20_to_router_29_19_rsp; - assign router_29_19_rsp_in[1] = router_30_19_to_router_29_19_rsp; - assign router_29_19_rsp_in[2] = router_29_18_to_router_29_19_rsp; - assign router_29_19_rsp_in[3] = router_28_19_to_router_29_19_rsp; - assign router_29_19_rsp_in[4] = magia_tile_ni_29_19_to_router_29_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_19_req_in), - .floo_rsp_o (router_29_19_rsp_out), - .floo_req_o (router_29_19_req_out), - .floo_rsp_i (router_29_19_rsp_in) -); - - -floo_req_t [4:0] router_29_20_req_in; -floo_rsp_t [4:0] router_29_20_rsp_out; -floo_req_t [4:0] router_29_20_req_out; -floo_rsp_t [4:0] router_29_20_rsp_in; - - assign router_29_20_req_in[0] = router_29_21_to_router_29_20_req; - assign router_29_20_req_in[1] = router_30_20_to_router_29_20_req; - assign router_29_20_req_in[2] = router_29_19_to_router_29_20_req; - assign router_29_20_req_in[3] = router_28_20_to_router_29_20_req; - assign router_29_20_req_in[4] = magia_tile_ni_29_20_to_router_29_20_req; - - assign router_29_20_to_router_29_21_rsp = router_29_20_rsp_out[0]; - assign router_29_20_to_router_30_20_rsp = router_29_20_rsp_out[1]; - assign router_29_20_to_router_29_19_rsp = router_29_20_rsp_out[2]; - assign router_29_20_to_router_28_20_rsp = router_29_20_rsp_out[3]; - assign router_29_20_to_magia_tile_ni_29_20_rsp = router_29_20_rsp_out[4]; - - assign router_29_20_to_router_29_21_req = router_29_20_req_out[0]; - assign router_29_20_to_router_30_20_req = router_29_20_req_out[1]; - assign router_29_20_to_router_29_19_req = router_29_20_req_out[2]; - assign router_29_20_to_router_28_20_req = router_29_20_req_out[3]; - assign router_29_20_to_magia_tile_ni_29_20_req = router_29_20_req_out[4]; - - assign router_29_20_rsp_in[0] = router_29_21_to_router_29_20_rsp; - assign router_29_20_rsp_in[1] = router_30_20_to_router_29_20_rsp; - assign router_29_20_rsp_in[2] = router_29_19_to_router_29_20_rsp; - assign router_29_20_rsp_in[3] = router_28_20_to_router_29_20_rsp; - assign router_29_20_rsp_in[4] = magia_tile_ni_29_20_to_router_29_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_20_req_in), - .floo_rsp_o (router_29_20_rsp_out), - .floo_req_o (router_29_20_req_out), - .floo_rsp_i (router_29_20_rsp_in) -); - - -floo_req_t [4:0] router_29_21_req_in; -floo_rsp_t [4:0] router_29_21_rsp_out; -floo_req_t [4:0] router_29_21_req_out; -floo_rsp_t [4:0] router_29_21_rsp_in; - - assign router_29_21_req_in[0] = router_29_22_to_router_29_21_req; - assign router_29_21_req_in[1] = router_30_21_to_router_29_21_req; - assign router_29_21_req_in[2] = router_29_20_to_router_29_21_req; - assign router_29_21_req_in[3] = router_28_21_to_router_29_21_req; - assign router_29_21_req_in[4] = magia_tile_ni_29_21_to_router_29_21_req; - - assign router_29_21_to_router_29_22_rsp = router_29_21_rsp_out[0]; - assign router_29_21_to_router_30_21_rsp = router_29_21_rsp_out[1]; - assign router_29_21_to_router_29_20_rsp = router_29_21_rsp_out[2]; - assign router_29_21_to_router_28_21_rsp = router_29_21_rsp_out[3]; - assign router_29_21_to_magia_tile_ni_29_21_rsp = router_29_21_rsp_out[4]; - - assign router_29_21_to_router_29_22_req = router_29_21_req_out[0]; - assign router_29_21_to_router_30_21_req = router_29_21_req_out[1]; - assign router_29_21_to_router_29_20_req = router_29_21_req_out[2]; - assign router_29_21_to_router_28_21_req = router_29_21_req_out[3]; - assign router_29_21_to_magia_tile_ni_29_21_req = router_29_21_req_out[4]; - - assign router_29_21_rsp_in[0] = router_29_22_to_router_29_21_rsp; - assign router_29_21_rsp_in[1] = router_30_21_to_router_29_21_rsp; - assign router_29_21_rsp_in[2] = router_29_20_to_router_29_21_rsp; - assign router_29_21_rsp_in[3] = router_28_21_to_router_29_21_rsp; - assign router_29_21_rsp_in[4] = magia_tile_ni_29_21_to_router_29_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_21_req_in), - .floo_rsp_o (router_29_21_rsp_out), - .floo_req_o (router_29_21_req_out), - .floo_rsp_i (router_29_21_rsp_in) -); - - -floo_req_t [4:0] router_29_22_req_in; -floo_rsp_t [4:0] router_29_22_rsp_out; -floo_req_t [4:0] router_29_22_req_out; -floo_rsp_t [4:0] router_29_22_rsp_in; - - assign router_29_22_req_in[0] = router_29_23_to_router_29_22_req; - assign router_29_22_req_in[1] = router_30_22_to_router_29_22_req; - assign router_29_22_req_in[2] = router_29_21_to_router_29_22_req; - assign router_29_22_req_in[3] = router_28_22_to_router_29_22_req; - assign router_29_22_req_in[4] = magia_tile_ni_29_22_to_router_29_22_req; - - assign router_29_22_to_router_29_23_rsp = router_29_22_rsp_out[0]; - assign router_29_22_to_router_30_22_rsp = router_29_22_rsp_out[1]; - assign router_29_22_to_router_29_21_rsp = router_29_22_rsp_out[2]; - assign router_29_22_to_router_28_22_rsp = router_29_22_rsp_out[3]; - assign router_29_22_to_magia_tile_ni_29_22_rsp = router_29_22_rsp_out[4]; - - assign router_29_22_to_router_29_23_req = router_29_22_req_out[0]; - assign router_29_22_to_router_30_22_req = router_29_22_req_out[1]; - assign router_29_22_to_router_29_21_req = router_29_22_req_out[2]; - assign router_29_22_to_router_28_22_req = router_29_22_req_out[3]; - assign router_29_22_to_magia_tile_ni_29_22_req = router_29_22_req_out[4]; - - assign router_29_22_rsp_in[0] = router_29_23_to_router_29_22_rsp; - assign router_29_22_rsp_in[1] = router_30_22_to_router_29_22_rsp; - assign router_29_22_rsp_in[2] = router_29_21_to_router_29_22_rsp; - assign router_29_22_rsp_in[3] = router_28_22_to_router_29_22_rsp; - assign router_29_22_rsp_in[4] = magia_tile_ni_29_22_to_router_29_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_22_req_in), - .floo_rsp_o (router_29_22_rsp_out), - .floo_req_o (router_29_22_req_out), - .floo_rsp_i (router_29_22_rsp_in) -); - - -floo_req_t [4:0] router_29_23_req_in; -floo_rsp_t [4:0] router_29_23_rsp_out; -floo_req_t [4:0] router_29_23_req_out; -floo_rsp_t [4:0] router_29_23_rsp_in; - - assign router_29_23_req_in[0] = router_29_24_to_router_29_23_req; - assign router_29_23_req_in[1] = router_30_23_to_router_29_23_req; - assign router_29_23_req_in[2] = router_29_22_to_router_29_23_req; - assign router_29_23_req_in[3] = router_28_23_to_router_29_23_req; - assign router_29_23_req_in[4] = magia_tile_ni_29_23_to_router_29_23_req; - - assign router_29_23_to_router_29_24_rsp = router_29_23_rsp_out[0]; - assign router_29_23_to_router_30_23_rsp = router_29_23_rsp_out[1]; - assign router_29_23_to_router_29_22_rsp = router_29_23_rsp_out[2]; - assign router_29_23_to_router_28_23_rsp = router_29_23_rsp_out[3]; - assign router_29_23_to_magia_tile_ni_29_23_rsp = router_29_23_rsp_out[4]; - - assign router_29_23_to_router_29_24_req = router_29_23_req_out[0]; - assign router_29_23_to_router_30_23_req = router_29_23_req_out[1]; - assign router_29_23_to_router_29_22_req = router_29_23_req_out[2]; - assign router_29_23_to_router_28_23_req = router_29_23_req_out[3]; - assign router_29_23_to_magia_tile_ni_29_23_req = router_29_23_req_out[4]; - - assign router_29_23_rsp_in[0] = router_29_24_to_router_29_23_rsp; - assign router_29_23_rsp_in[1] = router_30_23_to_router_29_23_rsp; - assign router_29_23_rsp_in[2] = router_29_22_to_router_29_23_rsp; - assign router_29_23_rsp_in[3] = router_28_23_to_router_29_23_rsp; - assign router_29_23_rsp_in[4] = magia_tile_ni_29_23_to_router_29_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_23_req_in), - .floo_rsp_o (router_29_23_rsp_out), - .floo_req_o (router_29_23_req_out), - .floo_rsp_i (router_29_23_rsp_in) -); - - -floo_req_t [4:0] router_29_24_req_in; -floo_rsp_t [4:0] router_29_24_rsp_out; -floo_req_t [4:0] router_29_24_req_out; -floo_rsp_t [4:0] router_29_24_rsp_in; - - assign router_29_24_req_in[0] = router_29_25_to_router_29_24_req; - assign router_29_24_req_in[1] = router_30_24_to_router_29_24_req; - assign router_29_24_req_in[2] = router_29_23_to_router_29_24_req; - assign router_29_24_req_in[3] = router_28_24_to_router_29_24_req; - assign router_29_24_req_in[4] = magia_tile_ni_29_24_to_router_29_24_req; - - assign router_29_24_to_router_29_25_rsp = router_29_24_rsp_out[0]; - assign router_29_24_to_router_30_24_rsp = router_29_24_rsp_out[1]; - assign router_29_24_to_router_29_23_rsp = router_29_24_rsp_out[2]; - assign router_29_24_to_router_28_24_rsp = router_29_24_rsp_out[3]; - assign router_29_24_to_magia_tile_ni_29_24_rsp = router_29_24_rsp_out[4]; - - assign router_29_24_to_router_29_25_req = router_29_24_req_out[0]; - assign router_29_24_to_router_30_24_req = router_29_24_req_out[1]; - assign router_29_24_to_router_29_23_req = router_29_24_req_out[2]; - assign router_29_24_to_router_28_24_req = router_29_24_req_out[3]; - assign router_29_24_to_magia_tile_ni_29_24_req = router_29_24_req_out[4]; - - assign router_29_24_rsp_in[0] = router_29_25_to_router_29_24_rsp; - assign router_29_24_rsp_in[1] = router_30_24_to_router_29_24_rsp; - assign router_29_24_rsp_in[2] = router_29_23_to_router_29_24_rsp; - assign router_29_24_rsp_in[3] = router_28_24_to_router_29_24_rsp; - assign router_29_24_rsp_in[4] = magia_tile_ni_29_24_to_router_29_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_24_req_in), - .floo_rsp_o (router_29_24_rsp_out), - .floo_req_o (router_29_24_req_out), - .floo_rsp_i (router_29_24_rsp_in) -); - - -floo_req_t [4:0] router_29_25_req_in; -floo_rsp_t [4:0] router_29_25_rsp_out; -floo_req_t [4:0] router_29_25_req_out; -floo_rsp_t [4:0] router_29_25_rsp_in; - - assign router_29_25_req_in[0] = router_29_26_to_router_29_25_req; - assign router_29_25_req_in[1] = router_30_25_to_router_29_25_req; - assign router_29_25_req_in[2] = router_29_24_to_router_29_25_req; - assign router_29_25_req_in[3] = router_28_25_to_router_29_25_req; - assign router_29_25_req_in[4] = magia_tile_ni_29_25_to_router_29_25_req; - - assign router_29_25_to_router_29_26_rsp = router_29_25_rsp_out[0]; - assign router_29_25_to_router_30_25_rsp = router_29_25_rsp_out[1]; - assign router_29_25_to_router_29_24_rsp = router_29_25_rsp_out[2]; - assign router_29_25_to_router_28_25_rsp = router_29_25_rsp_out[3]; - assign router_29_25_to_magia_tile_ni_29_25_rsp = router_29_25_rsp_out[4]; - - assign router_29_25_to_router_29_26_req = router_29_25_req_out[0]; - assign router_29_25_to_router_30_25_req = router_29_25_req_out[1]; - assign router_29_25_to_router_29_24_req = router_29_25_req_out[2]; - assign router_29_25_to_router_28_25_req = router_29_25_req_out[3]; - assign router_29_25_to_magia_tile_ni_29_25_req = router_29_25_req_out[4]; - - assign router_29_25_rsp_in[0] = router_29_26_to_router_29_25_rsp; - assign router_29_25_rsp_in[1] = router_30_25_to_router_29_25_rsp; - assign router_29_25_rsp_in[2] = router_29_24_to_router_29_25_rsp; - assign router_29_25_rsp_in[3] = router_28_25_to_router_29_25_rsp; - assign router_29_25_rsp_in[4] = magia_tile_ni_29_25_to_router_29_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_25_req_in), - .floo_rsp_o (router_29_25_rsp_out), - .floo_req_o (router_29_25_req_out), - .floo_rsp_i (router_29_25_rsp_in) -); - - -floo_req_t [4:0] router_29_26_req_in; -floo_rsp_t [4:0] router_29_26_rsp_out; -floo_req_t [4:0] router_29_26_req_out; -floo_rsp_t [4:0] router_29_26_rsp_in; - - assign router_29_26_req_in[0] = router_29_27_to_router_29_26_req; - assign router_29_26_req_in[1] = router_30_26_to_router_29_26_req; - assign router_29_26_req_in[2] = router_29_25_to_router_29_26_req; - assign router_29_26_req_in[3] = router_28_26_to_router_29_26_req; - assign router_29_26_req_in[4] = magia_tile_ni_29_26_to_router_29_26_req; - - assign router_29_26_to_router_29_27_rsp = router_29_26_rsp_out[0]; - assign router_29_26_to_router_30_26_rsp = router_29_26_rsp_out[1]; - assign router_29_26_to_router_29_25_rsp = router_29_26_rsp_out[2]; - assign router_29_26_to_router_28_26_rsp = router_29_26_rsp_out[3]; - assign router_29_26_to_magia_tile_ni_29_26_rsp = router_29_26_rsp_out[4]; - - assign router_29_26_to_router_29_27_req = router_29_26_req_out[0]; - assign router_29_26_to_router_30_26_req = router_29_26_req_out[1]; - assign router_29_26_to_router_29_25_req = router_29_26_req_out[2]; - assign router_29_26_to_router_28_26_req = router_29_26_req_out[3]; - assign router_29_26_to_magia_tile_ni_29_26_req = router_29_26_req_out[4]; - - assign router_29_26_rsp_in[0] = router_29_27_to_router_29_26_rsp; - assign router_29_26_rsp_in[1] = router_30_26_to_router_29_26_rsp; - assign router_29_26_rsp_in[2] = router_29_25_to_router_29_26_rsp; - assign router_29_26_rsp_in[3] = router_28_26_to_router_29_26_rsp; - assign router_29_26_rsp_in[4] = magia_tile_ni_29_26_to_router_29_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_26_req_in), - .floo_rsp_o (router_29_26_rsp_out), - .floo_req_o (router_29_26_req_out), - .floo_rsp_i (router_29_26_rsp_in) -); - - -floo_req_t [4:0] router_29_27_req_in; -floo_rsp_t [4:0] router_29_27_rsp_out; -floo_req_t [4:0] router_29_27_req_out; -floo_rsp_t [4:0] router_29_27_rsp_in; - - assign router_29_27_req_in[0] = router_29_28_to_router_29_27_req; - assign router_29_27_req_in[1] = router_30_27_to_router_29_27_req; - assign router_29_27_req_in[2] = router_29_26_to_router_29_27_req; - assign router_29_27_req_in[3] = router_28_27_to_router_29_27_req; - assign router_29_27_req_in[4] = magia_tile_ni_29_27_to_router_29_27_req; - - assign router_29_27_to_router_29_28_rsp = router_29_27_rsp_out[0]; - assign router_29_27_to_router_30_27_rsp = router_29_27_rsp_out[1]; - assign router_29_27_to_router_29_26_rsp = router_29_27_rsp_out[2]; - assign router_29_27_to_router_28_27_rsp = router_29_27_rsp_out[3]; - assign router_29_27_to_magia_tile_ni_29_27_rsp = router_29_27_rsp_out[4]; - - assign router_29_27_to_router_29_28_req = router_29_27_req_out[0]; - assign router_29_27_to_router_30_27_req = router_29_27_req_out[1]; - assign router_29_27_to_router_29_26_req = router_29_27_req_out[2]; - assign router_29_27_to_router_28_27_req = router_29_27_req_out[3]; - assign router_29_27_to_magia_tile_ni_29_27_req = router_29_27_req_out[4]; - - assign router_29_27_rsp_in[0] = router_29_28_to_router_29_27_rsp; - assign router_29_27_rsp_in[1] = router_30_27_to_router_29_27_rsp; - assign router_29_27_rsp_in[2] = router_29_26_to_router_29_27_rsp; - assign router_29_27_rsp_in[3] = router_28_27_to_router_29_27_rsp; - assign router_29_27_rsp_in[4] = magia_tile_ni_29_27_to_router_29_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_27_req_in), - .floo_rsp_o (router_29_27_rsp_out), - .floo_req_o (router_29_27_req_out), - .floo_rsp_i (router_29_27_rsp_in) -); - - -floo_req_t [4:0] router_29_28_req_in; -floo_rsp_t [4:0] router_29_28_rsp_out; -floo_req_t [4:0] router_29_28_req_out; -floo_rsp_t [4:0] router_29_28_rsp_in; - - assign router_29_28_req_in[0] = router_29_29_to_router_29_28_req; - assign router_29_28_req_in[1] = router_30_28_to_router_29_28_req; - assign router_29_28_req_in[2] = router_29_27_to_router_29_28_req; - assign router_29_28_req_in[3] = router_28_28_to_router_29_28_req; - assign router_29_28_req_in[4] = magia_tile_ni_29_28_to_router_29_28_req; - - assign router_29_28_to_router_29_29_rsp = router_29_28_rsp_out[0]; - assign router_29_28_to_router_30_28_rsp = router_29_28_rsp_out[1]; - assign router_29_28_to_router_29_27_rsp = router_29_28_rsp_out[2]; - assign router_29_28_to_router_28_28_rsp = router_29_28_rsp_out[3]; - assign router_29_28_to_magia_tile_ni_29_28_rsp = router_29_28_rsp_out[4]; - - assign router_29_28_to_router_29_29_req = router_29_28_req_out[0]; - assign router_29_28_to_router_30_28_req = router_29_28_req_out[1]; - assign router_29_28_to_router_29_27_req = router_29_28_req_out[2]; - assign router_29_28_to_router_28_28_req = router_29_28_req_out[3]; - assign router_29_28_to_magia_tile_ni_29_28_req = router_29_28_req_out[4]; - - assign router_29_28_rsp_in[0] = router_29_29_to_router_29_28_rsp; - assign router_29_28_rsp_in[1] = router_30_28_to_router_29_28_rsp; - assign router_29_28_rsp_in[2] = router_29_27_to_router_29_28_rsp; - assign router_29_28_rsp_in[3] = router_28_28_to_router_29_28_rsp; - assign router_29_28_rsp_in[4] = magia_tile_ni_29_28_to_router_29_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_28_req_in), - .floo_rsp_o (router_29_28_rsp_out), - .floo_req_o (router_29_28_req_out), - .floo_rsp_i (router_29_28_rsp_in) -); - - -floo_req_t [4:0] router_29_29_req_in; -floo_rsp_t [4:0] router_29_29_rsp_out; -floo_req_t [4:0] router_29_29_req_out; -floo_rsp_t [4:0] router_29_29_rsp_in; - - assign router_29_29_req_in[0] = router_29_30_to_router_29_29_req; - assign router_29_29_req_in[1] = router_30_29_to_router_29_29_req; - assign router_29_29_req_in[2] = router_29_28_to_router_29_29_req; - assign router_29_29_req_in[3] = router_28_29_to_router_29_29_req; - assign router_29_29_req_in[4] = magia_tile_ni_29_29_to_router_29_29_req; - - assign router_29_29_to_router_29_30_rsp = router_29_29_rsp_out[0]; - assign router_29_29_to_router_30_29_rsp = router_29_29_rsp_out[1]; - assign router_29_29_to_router_29_28_rsp = router_29_29_rsp_out[2]; - assign router_29_29_to_router_28_29_rsp = router_29_29_rsp_out[3]; - assign router_29_29_to_magia_tile_ni_29_29_rsp = router_29_29_rsp_out[4]; - - assign router_29_29_to_router_29_30_req = router_29_29_req_out[0]; - assign router_29_29_to_router_30_29_req = router_29_29_req_out[1]; - assign router_29_29_to_router_29_28_req = router_29_29_req_out[2]; - assign router_29_29_to_router_28_29_req = router_29_29_req_out[3]; - assign router_29_29_to_magia_tile_ni_29_29_req = router_29_29_req_out[4]; - - assign router_29_29_rsp_in[0] = router_29_30_to_router_29_29_rsp; - assign router_29_29_rsp_in[1] = router_30_29_to_router_29_29_rsp; - assign router_29_29_rsp_in[2] = router_29_28_to_router_29_29_rsp; - assign router_29_29_rsp_in[3] = router_28_29_to_router_29_29_rsp; - assign router_29_29_rsp_in[4] = magia_tile_ni_29_29_to_router_29_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_29_req_in), - .floo_rsp_o (router_29_29_rsp_out), - .floo_req_o (router_29_29_req_out), - .floo_rsp_i (router_29_29_rsp_in) -); - - -floo_req_t [4:0] router_29_30_req_in; -floo_rsp_t [4:0] router_29_30_rsp_out; -floo_req_t [4:0] router_29_30_req_out; -floo_rsp_t [4:0] router_29_30_rsp_in; - - assign router_29_30_req_in[0] = router_29_31_to_router_29_30_req; - assign router_29_30_req_in[1] = router_30_30_to_router_29_30_req; - assign router_29_30_req_in[2] = router_29_29_to_router_29_30_req; - assign router_29_30_req_in[3] = router_28_30_to_router_29_30_req; - assign router_29_30_req_in[4] = magia_tile_ni_29_30_to_router_29_30_req; - - assign router_29_30_to_router_29_31_rsp = router_29_30_rsp_out[0]; - assign router_29_30_to_router_30_30_rsp = router_29_30_rsp_out[1]; - assign router_29_30_to_router_29_29_rsp = router_29_30_rsp_out[2]; - assign router_29_30_to_router_28_30_rsp = router_29_30_rsp_out[3]; - assign router_29_30_to_magia_tile_ni_29_30_rsp = router_29_30_rsp_out[4]; - - assign router_29_30_to_router_29_31_req = router_29_30_req_out[0]; - assign router_29_30_to_router_30_30_req = router_29_30_req_out[1]; - assign router_29_30_to_router_29_29_req = router_29_30_req_out[2]; - assign router_29_30_to_router_28_30_req = router_29_30_req_out[3]; - assign router_29_30_to_magia_tile_ni_29_30_req = router_29_30_req_out[4]; - - assign router_29_30_rsp_in[0] = router_29_31_to_router_29_30_rsp; - assign router_29_30_rsp_in[1] = router_30_30_to_router_29_30_rsp; - assign router_29_30_rsp_in[2] = router_29_29_to_router_29_30_rsp; - assign router_29_30_rsp_in[3] = router_28_30_to_router_29_30_rsp; - assign router_29_30_rsp_in[4] = magia_tile_ni_29_30_to_router_29_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_30_req_in), - .floo_rsp_o (router_29_30_rsp_out), - .floo_req_o (router_29_30_req_out), - .floo_rsp_i (router_29_30_rsp_in) -); - - -floo_req_t [4:0] router_29_31_req_in; -floo_rsp_t [4:0] router_29_31_rsp_out; -floo_req_t [4:0] router_29_31_req_out; -floo_rsp_t [4:0] router_29_31_rsp_in; - - assign router_29_31_req_in[0] = '0; - assign router_29_31_req_in[1] = router_30_31_to_router_29_31_req; - assign router_29_31_req_in[2] = router_29_30_to_router_29_31_req; - assign router_29_31_req_in[3] = router_28_31_to_router_29_31_req; - assign router_29_31_req_in[4] = magia_tile_ni_29_31_to_router_29_31_req; - - assign router_29_31_to_router_30_31_rsp = router_29_31_rsp_out[1]; - assign router_29_31_to_router_29_30_rsp = router_29_31_rsp_out[2]; - assign router_29_31_to_router_28_31_rsp = router_29_31_rsp_out[3]; - assign router_29_31_to_magia_tile_ni_29_31_rsp = router_29_31_rsp_out[4]; - - assign router_29_31_to_router_30_31_req = router_29_31_req_out[1]; - assign router_29_31_to_router_29_30_req = router_29_31_req_out[2]; - assign router_29_31_to_router_28_31_req = router_29_31_req_out[3]; - assign router_29_31_to_magia_tile_ni_29_31_req = router_29_31_req_out[4]; - - assign router_29_31_rsp_in[0] = '0; - assign router_29_31_rsp_in[1] = router_30_31_to_router_29_31_rsp; - assign router_29_31_rsp_in[2] = router_29_30_to_router_29_31_rsp; - assign router_29_31_rsp_in[3] = router_28_31_to_router_29_31_rsp; - assign router_29_31_rsp_in[4] = magia_tile_ni_29_31_to_router_29_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_29_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 30, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_29_31_req_in), - .floo_rsp_o (router_29_31_rsp_out), - .floo_req_o (router_29_31_req_out), - .floo_rsp_i (router_29_31_rsp_in) -); - - -floo_req_t [4:0] router_30_0_req_in; -floo_rsp_t [4:0] router_30_0_rsp_out; -floo_req_t [4:0] router_30_0_req_out; -floo_rsp_t [4:0] router_30_0_rsp_in; - - assign router_30_0_req_in[0] = router_30_1_to_router_30_0_req; - assign router_30_0_req_in[1] = router_31_0_to_router_30_0_req; - assign router_30_0_req_in[2] = '0; - assign router_30_0_req_in[3] = router_29_0_to_router_30_0_req; - assign router_30_0_req_in[4] = magia_tile_ni_30_0_to_router_30_0_req; - - assign router_30_0_to_router_30_1_rsp = router_30_0_rsp_out[0]; - assign router_30_0_to_router_31_0_rsp = router_30_0_rsp_out[1]; - assign router_30_0_to_router_29_0_rsp = router_30_0_rsp_out[3]; - assign router_30_0_to_magia_tile_ni_30_0_rsp = router_30_0_rsp_out[4]; - - assign router_30_0_to_router_30_1_req = router_30_0_req_out[0]; - assign router_30_0_to_router_31_0_req = router_30_0_req_out[1]; - assign router_30_0_to_router_29_0_req = router_30_0_req_out[3]; - assign router_30_0_to_magia_tile_ni_30_0_req = router_30_0_req_out[4]; - - assign router_30_0_rsp_in[0] = router_30_1_to_router_30_0_rsp; - assign router_30_0_rsp_in[1] = router_31_0_to_router_30_0_rsp; - assign router_30_0_rsp_in[2] = '0; - assign router_30_0_rsp_in[3] = router_29_0_to_router_30_0_rsp; - assign router_30_0_rsp_in[4] = magia_tile_ni_30_0_to_router_30_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_0_req_in), - .floo_rsp_o (router_30_0_rsp_out), - .floo_req_o (router_30_0_req_out), - .floo_rsp_i (router_30_0_rsp_in) -); - - -floo_req_t [4:0] router_30_1_req_in; -floo_rsp_t [4:0] router_30_1_rsp_out; -floo_req_t [4:0] router_30_1_req_out; -floo_rsp_t [4:0] router_30_1_rsp_in; - - assign router_30_1_req_in[0] = router_30_2_to_router_30_1_req; - assign router_30_1_req_in[1] = router_31_1_to_router_30_1_req; - assign router_30_1_req_in[2] = router_30_0_to_router_30_1_req; - assign router_30_1_req_in[3] = router_29_1_to_router_30_1_req; - assign router_30_1_req_in[4] = magia_tile_ni_30_1_to_router_30_1_req; - - assign router_30_1_to_router_30_2_rsp = router_30_1_rsp_out[0]; - assign router_30_1_to_router_31_1_rsp = router_30_1_rsp_out[1]; - assign router_30_1_to_router_30_0_rsp = router_30_1_rsp_out[2]; - assign router_30_1_to_router_29_1_rsp = router_30_1_rsp_out[3]; - assign router_30_1_to_magia_tile_ni_30_1_rsp = router_30_1_rsp_out[4]; - - assign router_30_1_to_router_30_2_req = router_30_1_req_out[0]; - assign router_30_1_to_router_31_1_req = router_30_1_req_out[1]; - assign router_30_1_to_router_30_0_req = router_30_1_req_out[2]; - assign router_30_1_to_router_29_1_req = router_30_1_req_out[3]; - assign router_30_1_to_magia_tile_ni_30_1_req = router_30_1_req_out[4]; - - assign router_30_1_rsp_in[0] = router_30_2_to_router_30_1_rsp; - assign router_30_1_rsp_in[1] = router_31_1_to_router_30_1_rsp; - assign router_30_1_rsp_in[2] = router_30_0_to_router_30_1_rsp; - assign router_30_1_rsp_in[3] = router_29_1_to_router_30_1_rsp; - assign router_30_1_rsp_in[4] = magia_tile_ni_30_1_to_router_30_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_1_req_in), - .floo_rsp_o (router_30_1_rsp_out), - .floo_req_o (router_30_1_req_out), - .floo_rsp_i (router_30_1_rsp_in) -); - - -floo_req_t [4:0] router_30_2_req_in; -floo_rsp_t [4:0] router_30_2_rsp_out; -floo_req_t [4:0] router_30_2_req_out; -floo_rsp_t [4:0] router_30_2_rsp_in; - - assign router_30_2_req_in[0] = router_30_3_to_router_30_2_req; - assign router_30_2_req_in[1] = router_31_2_to_router_30_2_req; - assign router_30_2_req_in[2] = router_30_1_to_router_30_2_req; - assign router_30_2_req_in[3] = router_29_2_to_router_30_2_req; - assign router_30_2_req_in[4] = magia_tile_ni_30_2_to_router_30_2_req; - - assign router_30_2_to_router_30_3_rsp = router_30_2_rsp_out[0]; - assign router_30_2_to_router_31_2_rsp = router_30_2_rsp_out[1]; - assign router_30_2_to_router_30_1_rsp = router_30_2_rsp_out[2]; - assign router_30_2_to_router_29_2_rsp = router_30_2_rsp_out[3]; - assign router_30_2_to_magia_tile_ni_30_2_rsp = router_30_2_rsp_out[4]; - - assign router_30_2_to_router_30_3_req = router_30_2_req_out[0]; - assign router_30_2_to_router_31_2_req = router_30_2_req_out[1]; - assign router_30_2_to_router_30_1_req = router_30_2_req_out[2]; - assign router_30_2_to_router_29_2_req = router_30_2_req_out[3]; - assign router_30_2_to_magia_tile_ni_30_2_req = router_30_2_req_out[4]; - - assign router_30_2_rsp_in[0] = router_30_3_to_router_30_2_rsp; - assign router_30_2_rsp_in[1] = router_31_2_to_router_30_2_rsp; - assign router_30_2_rsp_in[2] = router_30_1_to_router_30_2_rsp; - assign router_30_2_rsp_in[3] = router_29_2_to_router_30_2_rsp; - assign router_30_2_rsp_in[4] = magia_tile_ni_30_2_to_router_30_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_2_req_in), - .floo_rsp_o (router_30_2_rsp_out), - .floo_req_o (router_30_2_req_out), - .floo_rsp_i (router_30_2_rsp_in) -); - - -floo_req_t [4:0] router_30_3_req_in; -floo_rsp_t [4:0] router_30_3_rsp_out; -floo_req_t [4:0] router_30_3_req_out; -floo_rsp_t [4:0] router_30_3_rsp_in; - - assign router_30_3_req_in[0] = router_30_4_to_router_30_3_req; - assign router_30_3_req_in[1] = router_31_3_to_router_30_3_req; - assign router_30_3_req_in[2] = router_30_2_to_router_30_3_req; - assign router_30_3_req_in[3] = router_29_3_to_router_30_3_req; - assign router_30_3_req_in[4] = magia_tile_ni_30_3_to_router_30_3_req; - - assign router_30_3_to_router_30_4_rsp = router_30_3_rsp_out[0]; - assign router_30_3_to_router_31_3_rsp = router_30_3_rsp_out[1]; - assign router_30_3_to_router_30_2_rsp = router_30_3_rsp_out[2]; - assign router_30_3_to_router_29_3_rsp = router_30_3_rsp_out[3]; - assign router_30_3_to_magia_tile_ni_30_3_rsp = router_30_3_rsp_out[4]; - - assign router_30_3_to_router_30_4_req = router_30_3_req_out[0]; - assign router_30_3_to_router_31_3_req = router_30_3_req_out[1]; - assign router_30_3_to_router_30_2_req = router_30_3_req_out[2]; - assign router_30_3_to_router_29_3_req = router_30_3_req_out[3]; - assign router_30_3_to_magia_tile_ni_30_3_req = router_30_3_req_out[4]; - - assign router_30_3_rsp_in[0] = router_30_4_to_router_30_3_rsp; - assign router_30_3_rsp_in[1] = router_31_3_to_router_30_3_rsp; - assign router_30_3_rsp_in[2] = router_30_2_to_router_30_3_rsp; - assign router_30_3_rsp_in[3] = router_29_3_to_router_30_3_rsp; - assign router_30_3_rsp_in[4] = magia_tile_ni_30_3_to_router_30_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_3_req_in), - .floo_rsp_o (router_30_3_rsp_out), - .floo_req_o (router_30_3_req_out), - .floo_rsp_i (router_30_3_rsp_in) -); - - -floo_req_t [4:0] router_30_4_req_in; -floo_rsp_t [4:0] router_30_4_rsp_out; -floo_req_t [4:0] router_30_4_req_out; -floo_rsp_t [4:0] router_30_4_rsp_in; - - assign router_30_4_req_in[0] = router_30_5_to_router_30_4_req; - assign router_30_4_req_in[1] = router_31_4_to_router_30_4_req; - assign router_30_4_req_in[2] = router_30_3_to_router_30_4_req; - assign router_30_4_req_in[3] = router_29_4_to_router_30_4_req; - assign router_30_4_req_in[4] = magia_tile_ni_30_4_to_router_30_4_req; - - assign router_30_4_to_router_30_5_rsp = router_30_4_rsp_out[0]; - assign router_30_4_to_router_31_4_rsp = router_30_4_rsp_out[1]; - assign router_30_4_to_router_30_3_rsp = router_30_4_rsp_out[2]; - assign router_30_4_to_router_29_4_rsp = router_30_4_rsp_out[3]; - assign router_30_4_to_magia_tile_ni_30_4_rsp = router_30_4_rsp_out[4]; - - assign router_30_4_to_router_30_5_req = router_30_4_req_out[0]; - assign router_30_4_to_router_31_4_req = router_30_4_req_out[1]; - assign router_30_4_to_router_30_3_req = router_30_4_req_out[2]; - assign router_30_4_to_router_29_4_req = router_30_4_req_out[3]; - assign router_30_4_to_magia_tile_ni_30_4_req = router_30_4_req_out[4]; - - assign router_30_4_rsp_in[0] = router_30_5_to_router_30_4_rsp; - assign router_30_4_rsp_in[1] = router_31_4_to_router_30_4_rsp; - assign router_30_4_rsp_in[2] = router_30_3_to_router_30_4_rsp; - assign router_30_4_rsp_in[3] = router_29_4_to_router_30_4_rsp; - assign router_30_4_rsp_in[4] = magia_tile_ni_30_4_to_router_30_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_4_req_in), - .floo_rsp_o (router_30_4_rsp_out), - .floo_req_o (router_30_4_req_out), - .floo_rsp_i (router_30_4_rsp_in) -); - - -floo_req_t [4:0] router_30_5_req_in; -floo_rsp_t [4:0] router_30_5_rsp_out; -floo_req_t [4:0] router_30_5_req_out; -floo_rsp_t [4:0] router_30_5_rsp_in; - - assign router_30_5_req_in[0] = router_30_6_to_router_30_5_req; - assign router_30_5_req_in[1] = router_31_5_to_router_30_5_req; - assign router_30_5_req_in[2] = router_30_4_to_router_30_5_req; - assign router_30_5_req_in[3] = router_29_5_to_router_30_5_req; - assign router_30_5_req_in[4] = magia_tile_ni_30_5_to_router_30_5_req; - - assign router_30_5_to_router_30_6_rsp = router_30_5_rsp_out[0]; - assign router_30_5_to_router_31_5_rsp = router_30_5_rsp_out[1]; - assign router_30_5_to_router_30_4_rsp = router_30_5_rsp_out[2]; - assign router_30_5_to_router_29_5_rsp = router_30_5_rsp_out[3]; - assign router_30_5_to_magia_tile_ni_30_5_rsp = router_30_5_rsp_out[4]; - - assign router_30_5_to_router_30_6_req = router_30_5_req_out[0]; - assign router_30_5_to_router_31_5_req = router_30_5_req_out[1]; - assign router_30_5_to_router_30_4_req = router_30_5_req_out[2]; - assign router_30_5_to_router_29_5_req = router_30_5_req_out[3]; - assign router_30_5_to_magia_tile_ni_30_5_req = router_30_5_req_out[4]; - - assign router_30_5_rsp_in[0] = router_30_6_to_router_30_5_rsp; - assign router_30_5_rsp_in[1] = router_31_5_to_router_30_5_rsp; - assign router_30_5_rsp_in[2] = router_30_4_to_router_30_5_rsp; - assign router_30_5_rsp_in[3] = router_29_5_to_router_30_5_rsp; - assign router_30_5_rsp_in[4] = magia_tile_ni_30_5_to_router_30_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_5_req_in), - .floo_rsp_o (router_30_5_rsp_out), - .floo_req_o (router_30_5_req_out), - .floo_rsp_i (router_30_5_rsp_in) -); - - -floo_req_t [4:0] router_30_6_req_in; -floo_rsp_t [4:0] router_30_6_rsp_out; -floo_req_t [4:0] router_30_6_req_out; -floo_rsp_t [4:0] router_30_6_rsp_in; - - assign router_30_6_req_in[0] = router_30_7_to_router_30_6_req; - assign router_30_6_req_in[1] = router_31_6_to_router_30_6_req; - assign router_30_6_req_in[2] = router_30_5_to_router_30_6_req; - assign router_30_6_req_in[3] = router_29_6_to_router_30_6_req; - assign router_30_6_req_in[4] = magia_tile_ni_30_6_to_router_30_6_req; - - assign router_30_6_to_router_30_7_rsp = router_30_6_rsp_out[0]; - assign router_30_6_to_router_31_6_rsp = router_30_6_rsp_out[1]; - assign router_30_6_to_router_30_5_rsp = router_30_6_rsp_out[2]; - assign router_30_6_to_router_29_6_rsp = router_30_6_rsp_out[3]; - assign router_30_6_to_magia_tile_ni_30_6_rsp = router_30_6_rsp_out[4]; - - assign router_30_6_to_router_30_7_req = router_30_6_req_out[0]; - assign router_30_6_to_router_31_6_req = router_30_6_req_out[1]; - assign router_30_6_to_router_30_5_req = router_30_6_req_out[2]; - assign router_30_6_to_router_29_6_req = router_30_6_req_out[3]; - assign router_30_6_to_magia_tile_ni_30_6_req = router_30_6_req_out[4]; - - assign router_30_6_rsp_in[0] = router_30_7_to_router_30_6_rsp; - assign router_30_6_rsp_in[1] = router_31_6_to_router_30_6_rsp; - assign router_30_6_rsp_in[2] = router_30_5_to_router_30_6_rsp; - assign router_30_6_rsp_in[3] = router_29_6_to_router_30_6_rsp; - assign router_30_6_rsp_in[4] = magia_tile_ni_30_6_to_router_30_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_6_req_in), - .floo_rsp_o (router_30_6_rsp_out), - .floo_req_o (router_30_6_req_out), - .floo_rsp_i (router_30_6_rsp_in) -); - - -floo_req_t [4:0] router_30_7_req_in; -floo_rsp_t [4:0] router_30_7_rsp_out; -floo_req_t [4:0] router_30_7_req_out; -floo_rsp_t [4:0] router_30_7_rsp_in; - - assign router_30_7_req_in[0] = router_30_8_to_router_30_7_req; - assign router_30_7_req_in[1] = router_31_7_to_router_30_7_req; - assign router_30_7_req_in[2] = router_30_6_to_router_30_7_req; - assign router_30_7_req_in[3] = router_29_7_to_router_30_7_req; - assign router_30_7_req_in[4] = magia_tile_ni_30_7_to_router_30_7_req; - - assign router_30_7_to_router_30_8_rsp = router_30_7_rsp_out[0]; - assign router_30_7_to_router_31_7_rsp = router_30_7_rsp_out[1]; - assign router_30_7_to_router_30_6_rsp = router_30_7_rsp_out[2]; - assign router_30_7_to_router_29_7_rsp = router_30_7_rsp_out[3]; - assign router_30_7_to_magia_tile_ni_30_7_rsp = router_30_7_rsp_out[4]; - - assign router_30_7_to_router_30_8_req = router_30_7_req_out[0]; - assign router_30_7_to_router_31_7_req = router_30_7_req_out[1]; - assign router_30_7_to_router_30_6_req = router_30_7_req_out[2]; - assign router_30_7_to_router_29_7_req = router_30_7_req_out[3]; - assign router_30_7_to_magia_tile_ni_30_7_req = router_30_7_req_out[4]; - - assign router_30_7_rsp_in[0] = router_30_8_to_router_30_7_rsp; - assign router_30_7_rsp_in[1] = router_31_7_to_router_30_7_rsp; - assign router_30_7_rsp_in[2] = router_30_6_to_router_30_7_rsp; - assign router_30_7_rsp_in[3] = router_29_7_to_router_30_7_rsp; - assign router_30_7_rsp_in[4] = magia_tile_ni_30_7_to_router_30_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_7_req_in), - .floo_rsp_o (router_30_7_rsp_out), - .floo_req_o (router_30_7_req_out), - .floo_rsp_i (router_30_7_rsp_in) -); - - -floo_req_t [4:0] router_30_8_req_in; -floo_rsp_t [4:0] router_30_8_rsp_out; -floo_req_t [4:0] router_30_8_req_out; -floo_rsp_t [4:0] router_30_8_rsp_in; - - assign router_30_8_req_in[0] = router_30_9_to_router_30_8_req; - assign router_30_8_req_in[1] = router_31_8_to_router_30_8_req; - assign router_30_8_req_in[2] = router_30_7_to_router_30_8_req; - assign router_30_8_req_in[3] = router_29_8_to_router_30_8_req; - assign router_30_8_req_in[4] = magia_tile_ni_30_8_to_router_30_8_req; - - assign router_30_8_to_router_30_9_rsp = router_30_8_rsp_out[0]; - assign router_30_8_to_router_31_8_rsp = router_30_8_rsp_out[1]; - assign router_30_8_to_router_30_7_rsp = router_30_8_rsp_out[2]; - assign router_30_8_to_router_29_8_rsp = router_30_8_rsp_out[3]; - assign router_30_8_to_magia_tile_ni_30_8_rsp = router_30_8_rsp_out[4]; - - assign router_30_8_to_router_30_9_req = router_30_8_req_out[0]; - assign router_30_8_to_router_31_8_req = router_30_8_req_out[1]; - assign router_30_8_to_router_30_7_req = router_30_8_req_out[2]; - assign router_30_8_to_router_29_8_req = router_30_8_req_out[3]; - assign router_30_8_to_magia_tile_ni_30_8_req = router_30_8_req_out[4]; - - assign router_30_8_rsp_in[0] = router_30_9_to_router_30_8_rsp; - assign router_30_8_rsp_in[1] = router_31_8_to_router_30_8_rsp; - assign router_30_8_rsp_in[2] = router_30_7_to_router_30_8_rsp; - assign router_30_8_rsp_in[3] = router_29_8_to_router_30_8_rsp; - assign router_30_8_rsp_in[4] = magia_tile_ni_30_8_to_router_30_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_8_req_in), - .floo_rsp_o (router_30_8_rsp_out), - .floo_req_o (router_30_8_req_out), - .floo_rsp_i (router_30_8_rsp_in) -); - - -floo_req_t [4:0] router_30_9_req_in; -floo_rsp_t [4:0] router_30_9_rsp_out; -floo_req_t [4:0] router_30_9_req_out; -floo_rsp_t [4:0] router_30_9_rsp_in; - - assign router_30_9_req_in[0] = router_30_10_to_router_30_9_req; - assign router_30_9_req_in[1] = router_31_9_to_router_30_9_req; - assign router_30_9_req_in[2] = router_30_8_to_router_30_9_req; - assign router_30_9_req_in[3] = router_29_9_to_router_30_9_req; - assign router_30_9_req_in[4] = magia_tile_ni_30_9_to_router_30_9_req; - - assign router_30_9_to_router_30_10_rsp = router_30_9_rsp_out[0]; - assign router_30_9_to_router_31_9_rsp = router_30_9_rsp_out[1]; - assign router_30_9_to_router_30_8_rsp = router_30_9_rsp_out[2]; - assign router_30_9_to_router_29_9_rsp = router_30_9_rsp_out[3]; - assign router_30_9_to_magia_tile_ni_30_9_rsp = router_30_9_rsp_out[4]; - - assign router_30_9_to_router_30_10_req = router_30_9_req_out[0]; - assign router_30_9_to_router_31_9_req = router_30_9_req_out[1]; - assign router_30_9_to_router_30_8_req = router_30_9_req_out[2]; - assign router_30_9_to_router_29_9_req = router_30_9_req_out[3]; - assign router_30_9_to_magia_tile_ni_30_9_req = router_30_9_req_out[4]; - - assign router_30_9_rsp_in[0] = router_30_10_to_router_30_9_rsp; - assign router_30_9_rsp_in[1] = router_31_9_to_router_30_9_rsp; - assign router_30_9_rsp_in[2] = router_30_8_to_router_30_9_rsp; - assign router_30_9_rsp_in[3] = router_29_9_to_router_30_9_rsp; - assign router_30_9_rsp_in[4] = magia_tile_ni_30_9_to_router_30_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_9_req_in), - .floo_rsp_o (router_30_9_rsp_out), - .floo_req_o (router_30_9_req_out), - .floo_rsp_i (router_30_9_rsp_in) -); - - -floo_req_t [4:0] router_30_10_req_in; -floo_rsp_t [4:0] router_30_10_rsp_out; -floo_req_t [4:0] router_30_10_req_out; -floo_rsp_t [4:0] router_30_10_rsp_in; - - assign router_30_10_req_in[0] = router_30_11_to_router_30_10_req; - assign router_30_10_req_in[1] = router_31_10_to_router_30_10_req; - assign router_30_10_req_in[2] = router_30_9_to_router_30_10_req; - assign router_30_10_req_in[3] = router_29_10_to_router_30_10_req; - assign router_30_10_req_in[4] = magia_tile_ni_30_10_to_router_30_10_req; - - assign router_30_10_to_router_30_11_rsp = router_30_10_rsp_out[0]; - assign router_30_10_to_router_31_10_rsp = router_30_10_rsp_out[1]; - assign router_30_10_to_router_30_9_rsp = router_30_10_rsp_out[2]; - assign router_30_10_to_router_29_10_rsp = router_30_10_rsp_out[3]; - assign router_30_10_to_magia_tile_ni_30_10_rsp = router_30_10_rsp_out[4]; - - assign router_30_10_to_router_30_11_req = router_30_10_req_out[0]; - assign router_30_10_to_router_31_10_req = router_30_10_req_out[1]; - assign router_30_10_to_router_30_9_req = router_30_10_req_out[2]; - assign router_30_10_to_router_29_10_req = router_30_10_req_out[3]; - assign router_30_10_to_magia_tile_ni_30_10_req = router_30_10_req_out[4]; - - assign router_30_10_rsp_in[0] = router_30_11_to_router_30_10_rsp; - assign router_30_10_rsp_in[1] = router_31_10_to_router_30_10_rsp; - assign router_30_10_rsp_in[2] = router_30_9_to_router_30_10_rsp; - assign router_30_10_rsp_in[3] = router_29_10_to_router_30_10_rsp; - assign router_30_10_rsp_in[4] = magia_tile_ni_30_10_to_router_30_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_10_req_in), - .floo_rsp_o (router_30_10_rsp_out), - .floo_req_o (router_30_10_req_out), - .floo_rsp_i (router_30_10_rsp_in) -); - - -floo_req_t [4:0] router_30_11_req_in; -floo_rsp_t [4:0] router_30_11_rsp_out; -floo_req_t [4:0] router_30_11_req_out; -floo_rsp_t [4:0] router_30_11_rsp_in; - - assign router_30_11_req_in[0] = router_30_12_to_router_30_11_req; - assign router_30_11_req_in[1] = router_31_11_to_router_30_11_req; - assign router_30_11_req_in[2] = router_30_10_to_router_30_11_req; - assign router_30_11_req_in[3] = router_29_11_to_router_30_11_req; - assign router_30_11_req_in[4] = magia_tile_ni_30_11_to_router_30_11_req; - - assign router_30_11_to_router_30_12_rsp = router_30_11_rsp_out[0]; - assign router_30_11_to_router_31_11_rsp = router_30_11_rsp_out[1]; - assign router_30_11_to_router_30_10_rsp = router_30_11_rsp_out[2]; - assign router_30_11_to_router_29_11_rsp = router_30_11_rsp_out[3]; - assign router_30_11_to_magia_tile_ni_30_11_rsp = router_30_11_rsp_out[4]; - - assign router_30_11_to_router_30_12_req = router_30_11_req_out[0]; - assign router_30_11_to_router_31_11_req = router_30_11_req_out[1]; - assign router_30_11_to_router_30_10_req = router_30_11_req_out[2]; - assign router_30_11_to_router_29_11_req = router_30_11_req_out[3]; - assign router_30_11_to_magia_tile_ni_30_11_req = router_30_11_req_out[4]; - - assign router_30_11_rsp_in[0] = router_30_12_to_router_30_11_rsp; - assign router_30_11_rsp_in[1] = router_31_11_to_router_30_11_rsp; - assign router_30_11_rsp_in[2] = router_30_10_to_router_30_11_rsp; - assign router_30_11_rsp_in[3] = router_29_11_to_router_30_11_rsp; - assign router_30_11_rsp_in[4] = magia_tile_ni_30_11_to_router_30_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_11_req_in), - .floo_rsp_o (router_30_11_rsp_out), - .floo_req_o (router_30_11_req_out), - .floo_rsp_i (router_30_11_rsp_in) -); - - -floo_req_t [4:0] router_30_12_req_in; -floo_rsp_t [4:0] router_30_12_rsp_out; -floo_req_t [4:0] router_30_12_req_out; -floo_rsp_t [4:0] router_30_12_rsp_in; - - assign router_30_12_req_in[0] = router_30_13_to_router_30_12_req; - assign router_30_12_req_in[1] = router_31_12_to_router_30_12_req; - assign router_30_12_req_in[2] = router_30_11_to_router_30_12_req; - assign router_30_12_req_in[3] = router_29_12_to_router_30_12_req; - assign router_30_12_req_in[4] = magia_tile_ni_30_12_to_router_30_12_req; - - assign router_30_12_to_router_30_13_rsp = router_30_12_rsp_out[0]; - assign router_30_12_to_router_31_12_rsp = router_30_12_rsp_out[1]; - assign router_30_12_to_router_30_11_rsp = router_30_12_rsp_out[2]; - assign router_30_12_to_router_29_12_rsp = router_30_12_rsp_out[3]; - assign router_30_12_to_magia_tile_ni_30_12_rsp = router_30_12_rsp_out[4]; - - assign router_30_12_to_router_30_13_req = router_30_12_req_out[0]; - assign router_30_12_to_router_31_12_req = router_30_12_req_out[1]; - assign router_30_12_to_router_30_11_req = router_30_12_req_out[2]; - assign router_30_12_to_router_29_12_req = router_30_12_req_out[3]; - assign router_30_12_to_magia_tile_ni_30_12_req = router_30_12_req_out[4]; - - assign router_30_12_rsp_in[0] = router_30_13_to_router_30_12_rsp; - assign router_30_12_rsp_in[1] = router_31_12_to_router_30_12_rsp; - assign router_30_12_rsp_in[2] = router_30_11_to_router_30_12_rsp; - assign router_30_12_rsp_in[3] = router_29_12_to_router_30_12_rsp; - assign router_30_12_rsp_in[4] = magia_tile_ni_30_12_to_router_30_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_12_req_in), - .floo_rsp_o (router_30_12_rsp_out), - .floo_req_o (router_30_12_req_out), - .floo_rsp_i (router_30_12_rsp_in) -); - - -floo_req_t [4:0] router_30_13_req_in; -floo_rsp_t [4:0] router_30_13_rsp_out; -floo_req_t [4:0] router_30_13_req_out; -floo_rsp_t [4:0] router_30_13_rsp_in; - - assign router_30_13_req_in[0] = router_30_14_to_router_30_13_req; - assign router_30_13_req_in[1] = router_31_13_to_router_30_13_req; - assign router_30_13_req_in[2] = router_30_12_to_router_30_13_req; - assign router_30_13_req_in[3] = router_29_13_to_router_30_13_req; - assign router_30_13_req_in[4] = magia_tile_ni_30_13_to_router_30_13_req; - - assign router_30_13_to_router_30_14_rsp = router_30_13_rsp_out[0]; - assign router_30_13_to_router_31_13_rsp = router_30_13_rsp_out[1]; - assign router_30_13_to_router_30_12_rsp = router_30_13_rsp_out[2]; - assign router_30_13_to_router_29_13_rsp = router_30_13_rsp_out[3]; - assign router_30_13_to_magia_tile_ni_30_13_rsp = router_30_13_rsp_out[4]; - - assign router_30_13_to_router_30_14_req = router_30_13_req_out[0]; - assign router_30_13_to_router_31_13_req = router_30_13_req_out[1]; - assign router_30_13_to_router_30_12_req = router_30_13_req_out[2]; - assign router_30_13_to_router_29_13_req = router_30_13_req_out[3]; - assign router_30_13_to_magia_tile_ni_30_13_req = router_30_13_req_out[4]; - - assign router_30_13_rsp_in[0] = router_30_14_to_router_30_13_rsp; - assign router_30_13_rsp_in[1] = router_31_13_to_router_30_13_rsp; - assign router_30_13_rsp_in[2] = router_30_12_to_router_30_13_rsp; - assign router_30_13_rsp_in[3] = router_29_13_to_router_30_13_rsp; - assign router_30_13_rsp_in[4] = magia_tile_ni_30_13_to_router_30_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_13_req_in), - .floo_rsp_o (router_30_13_rsp_out), - .floo_req_o (router_30_13_req_out), - .floo_rsp_i (router_30_13_rsp_in) -); - - -floo_req_t [4:0] router_30_14_req_in; -floo_rsp_t [4:0] router_30_14_rsp_out; -floo_req_t [4:0] router_30_14_req_out; -floo_rsp_t [4:0] router_30_14_rsp_in; - - assign router_30_14_req_in[0] = router_30_15_to_router_30_14_req; - assign router_30_14_req_in[1] = router_31_14_to_router_30_14_req; - assign router_30_14_req_in[2] = router_30_13_to_router_30_14_req; - assign router_30_14_req_in[3] = router_29_14_to_router_30_14_req; - assign router_30_14_req_in[4] = magia_tile_ni_30_14_to_router_30_14_req; - - assign router_30_14_to_router_30_15_rsp = router_30_14_rsp_out[0]; - assign router_30_14_to_router_31_14_rsp = router_30_14_rsp_out[1]; - assign router_30_14_to_router_30_13_rsp = router_30_14_rsp_out[2]; - assign router_30_14_to_router_29_14_rsp = router_30_14_rsp_out[3]; - assign router_30_14_to_magia_tile_ni_30_14_rsp = router_30_14_rsp_out[4]; - - assign router_30_14_to_router_30_15_req = router_30_14_req_out[0]; - assign router_30_14_to_router_31_14_req = router_30_14_req_out[1]; - assign router_30_14_to_router_30_13_req = router_30_14_req_out[2]; - assign router_30_14_to_router_29_14_req = router_30_14_req_out[3]; - assign router_30_14_to_magia_tile_ni_30_14_req = router_30_14_req_out[4]; - - assign router_30_14_rsp_in[0] = router_30_15_to_router_30_14_rsp; - assign router_30_14_rsp_in[1] = router_31_14_to_router_30_14_rsp; - assign router_30_14_rsp_in[2] = router_30_13_to_router_30_14_rsp; - assign router_30_14_rsp_in[3] = router_29_14_to_router_30_14_rsp; - assign router_30_14_rsp_in[4] = magia_tile_ni_30_14_to_router_30_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_14_req_in), - .floo_rsp_o (router_30_14_rsp_out), - .floo_req_o (router_30_14_req_out), - .floo_rsp_i (router_30_14_rsp_in) -); - - -floo_req_t [4:0] router_30_15_req_in; -floo_rsp_t [4:0] router_30_15_rsp_out; -floo_req_t [4:0] router_30_15_req_out; -floo_rsp_t [4:0] router_30_15_rsp_in; - - assign router_30_15_req_in[0] = router_30_16_to_router_30_15_req; - assign router_30_15_req_in[1] = router_31_15_to_router_30_15_req; - assign router_30_15_req_in[2] = router_30_14_to_router_30_15_req; - assign router_30_15_req_in[3] = router_29_15_to_router_30_15_req; - assign router_30_15_req_in[4] = magia_tile_ni_30_15_to_router_30_15_req; - - assign router_30_15_to_router_30_16_rsp = router_30_15_rsp_out[0]; - assign router_30_15_to_router_31_15_rsp = router_30_15_rsp_out[1]; - assign router_30_15_to_router_30_14_rsp = router_30_15_rsp_out[2]; - assign router_30_15_to_router_29_15_rsp = router_30_15_rsp_out[3]; - assign router_30_15_to_magia_tile_ni_30_15_rsp = router_30_15_rsp_out[4]; - - assign router_30_15_to_router_30_16_req = router_30_15_req_out[0]; - assign router_30_15_to_router_31_15_req = router_30_15_req_out[1]; - assign router_30_15_to_router_30_14_req = router_30_15_req_out[2]; - assign router_30_15_to_router_29_15_req = router_30_15_req_out[3]; - assign router_30_15_to_magia_tile_ni_30_15_req = router_30_15_req_out[4]; - - assign router_30_15_rsp_in[0] = router_30_16_to_router_30_15_rsp; - assign router_30_15_rsp_in[1] = router_31_15_to_router_30_15_rsp; - assign router_30_15_rsp_in[2] = router_30_14_to_router_30_15_rsp; - assign router_30_15_rsp_in[3] = router_29_15_to_router_30_15_rsp; - assign router_30_15_rsp_in[4] = magia_tile_ni_30_15_to_router_30_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_15_req_in), - .floo_rsp_o (router_30_15_rsp_out), - .floo_req_o (router_30_15_req_out), - .floo_rsp_i (router_30_15_rsp_in) -); - - -floo_req_t [4:0] router_30_16_req_in; -floo_rsp_t [4:0] router_30_16_rsp_out; -floo_req_t [4:0] router_30_16_req_out; -floo_rsp_t [4:0] router_30_16_rsp_in; - - assign router_30_16_req_in[0] = router_30_17_to_router_30_16_req; - assign router_30_16_req_in[1] = router_31_16_to_router_30_16_req; - assign router_30_16_req_in[2] = router_30_15_to_router_30_16_req; - assign router_30_16_req_in[3] = router_29_16_to_router_30_16_req; - assign router_30_16_req_in[4] = magia_tile_ni_30_16_to_router_30_16_req; - - assign router_30_16_to_router_30_17_rsp = router_30_16_rsp_out[0]; - assign router_30_16_to_router_31_16_rsp = router_30_16_rsp_out[1]; - assign router_30_16_to_router_30_15_rsp = router_30_16_rsp_out[2]; - assign router_30_16_to_router_29_16_rsp = router_30_16_rsp_out[3]; - assign router_30_16_to_magia_tile_ni_30_16_rsp = router_30_16_rsp_out[4]; - - assign router_30_16_to_router_30_17_req = router_30_16_req_out[0]; - assign router_30_16_to_router_31_16_req = router_30_16_req_out[1]; - assign router_30_16_to_router_30_15_req = router_30_16_req_out[2]; - assign router_30_16_to_router_29_16_req = router_30_16_req_out[3]; - assign router_30_16_to_magia_tile_ni_30_16_req = router_30_16_req_out[4]; - - assign router_30_16_rsp_in[0] = router_30_17_to_router_30_16_rsp; - assign router_30_16_rsp_in[1] = router_31_16_to_router_30_16_rsp; - assign router_30_16_rsp_in[2] = router_30_15_to_router_30_16_rsp; - assign router_30_16_rsp_in[3] = router_29_16_to_router_30_16_rsp; - assign router_30_16_rsp_in[4] = magia_tile_ni_30_16_to_router_30_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_16_req_in), - .floo_rsp_o (router_30_16_rsp_out), - .floo_req_o (router_30_16_req_out), - .floo_rsp_i (router_30_16_rsp_in) -); - - -floo_req_t [4:0] router_30_17_req_in; -floo_rsp_t [4:0] router_30_17_rsp_out; -floo_req_t [4:0] router_30_17_req_out; -floo_rsp_t [4:0] router_30_17_rsp_in; - - assign router_30_17_req_in[0] = router_30_18_to_router_30_17_req; - assign router_30_17_req_in[1] = router_31_17_to_router_30_17_req; - assign router_30_17_req_in[2] = router_30_16_to_router_30_17_req; - assign router_30_17_req_in[3] = router_29_17_to_router_30_17_req; - assign router_30_17_req_in[4] = magia_tile_ni_30_17_to_router_30_17_req; - - assign router_30_17_to_router_30_18_rsp = router_30_17_rsp_out[0]; - assign router_30_17_to_router_31_17_rsp = router_30_17_rsp_out[1]; - assign router_30_17_to_router_30_16_rsp = router_30_17_rsp_out[2]; - assign router_30_17_to_router_29_17_rsp = router_30_17_rsp_out[3]; - assign router_30_17_to_magia_tile_ni_30_17_rsp = router_30_17_rsp_out[4]; - - assign router_30_17_to_router_30_18_req = router_30_17_req_out[0]; - assign router_30_17_to_router_31_17_req = router_30_17_req_out[1]; - assign router_30_17_to_router_30_16_req = router_30_17_req_out[2]; - assign router_30_17_to_router_29_17_req = router_30_17_req_out[3]; - assign router_30_17_to_magia_tile_ni_30_17_req = router_30_17_req_out[4]; - - assign router_30_17_rsp_in[0] = router_30_18_to_router_30_17_rsp; - assign router_30_17_rsp_in[1] = router_31_17_to_router_30_17_rsp; - assign router_30_17_rsp_in[2] = router_30_16_to_router_30_17_rsp; - assign router_30_17_rsp_in[3] = router_29_17_to_router_30_17_rsp; - assign router_30_17_rsp_in[4] = magia_tile_ni_30_17_to_router_30_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_17_req_in), - .floo_rsp_o (router_30_17_rsp_out), - .floo_req_o (router_30_17_req_out), - .floo_rsp_i (router_30_17_rsp_in) -); - - -floo_req_t [4:0] router_30_18_req_in; -floo_rsp_t [4:0] router_30_18_rsp_out; -floo_req_t [4:0] router_30_18_req_out; -floo_rsp_t [4:0] router_30_18_rsp_in; - - assign router_30_18_req_in[0] = router_30_19_to_router_30_18_req; - assign router_30_18_req_in[1] = router_31_18_to_router_30_18_req; - assign router_30_18_req_in[2] = router_30_17_to_router_30_18_req; - assign router_30_18_req_in[3] = router_29_18_to_router_30_18_req; - assign router_30_18_req_in[4] = magia_tile_ni_30_18_to_router_30_18_req; - - assign router_30_18_to_router_30_19_rsp = router_30_18_rsp_out[0]; - assign router_30_18_to_router_31_18_rsp = router_30_18_rsp_out[1]; - assign router_30_18_to_router_30_17_rsp = router_30_18_rsp_out[2]; - assign router_30_18_to_router_29_18_rsp = router_30_18_rsp_out[3]; - assign router_30_18_to_magia_tile_ni_30_18_rsp = router_30_18_rsp_out[4]; - - assign router_30_18_to_router_30_19_req = router_30_18_req_out[0]; - assign router_30_18_to_router_31_18_req = router_30_18_req_out[1]; - assign router_30_18_to_router_30_17_req = router_30_18_req_out[2]; - assign router_30_18_to_router_29_18_req = router_30_18_req_out[3]; - assign router_30_18_to_magia_tile_ni_30_18_req = router_30_18_req_out[4]; - - assign router_30_18_rsp_in[0] = router_30_19_to_router_30_18_rsp; - assign router_30_18_rsp_in[1] = router_31_18_to_router_30_18_rsp; - assign router_30_18_rsp_in[2] = router_30_17_to_router_30_18_rsp; - assign router_30_18_rsp_in[3] = router_29_18_to_router_30_18_rsp; - assign router_30_18_rsp_in[4] = magia_tile_ni_30_18_to_router_30_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_18_req_in), - .floo_rsp_o (router_30_18_rsp_out), - .floo_req_o (router_30_18_req_out), - .floo_rsp_i (router_30_18_rsp_in) -); - - -floo_req_t [4:0] router_30_19_req_in; -floo_rsp_t [4:0] router_30_19_rsp_out; -floo_req_t [4:0] router_30_19_req_out; -floo_rsp_t [4:0] router_30_19_rsp_in; - - assign router_30_19_req_in[0] = router_30_20_to_router_30_19_req; - assign router_30_19_req_in[1] = router_31_19_to_router_30_19_req; - assign router_30_19_req_in[2] = router_30_18_to_router_30_19_req; - assign router_30_19_req_in[3] = router_29_19_to_router_30_19_req; - assign router_30_19_req_in[4] = magia_tile_ni_30_19_to_router_30_19_req; - - assign router_30_19_to_router_30_20_rsp = router_30_19_rsp_out[0]; - assign router_30_19_to_router_31_19_rsp = router_30_19_rsp_out[1]; - assign router_30_19_to_router_30_18_rsp = router_30_19_rsp_out[2]; - assign router_30_19_to_router_29_19_rsp = router_30_19_rsp_out[3]; - assign router_30_19_to_magia_tile_ni_30_19_rsp = router_30_19_rsp_out[4]; - - assign router_30_19_to_router_30_20_req = router_30_19_req_out[0]; - assign router_30_19_to_router_31_19_req = router_30_19_req_out[1]; - assign router_30_19_to_router_30_18_req = router_30_19_req_out[2]; - assign router_30_19_to_router_29_19_req = router_30_19_req_out[3]; - assign router_30_19_to_magia_tile_ni_30_19_req = router_30_19_req_out[4]; - - assign router_30_19_rsp_in[0] = router_30_20_to_router_30_19_rsp; - assign router_30_19_rsp_in[1] = router_31_19_to_router_30_19_rsp; - assign router_30_19_rsp_in[2] = router_30_18_to_router_30_19_rsp; - assign router_30_19_rsp_in[3] = router_29_19_to_router_30_19_rsp; - assign router_30_19_rsp_in[4] = magia_tile_ni_30_19_to_router_30_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_19_req_in), - .floo_rsp_o (router_30_19_rsp_out), - .floo_req_o (router_30_19_req_out), - .floo_rsp_i (router_30_19_rsp_in) -); - - -floo_req_t [4:0] router_30_20_req_in; -floo_rsp_t [4:0] router_30_20_rsp_out; -floo_req_t [4:0] router_30_20_req_out; -floo_rsp_t [4:0] router_30_20_rsp_in; - - assign router_30_20_req_in[0] = router_30_21_to_router_30_20_req; - assign router_30_20_req_in[1] = router_31_20_to_router_30_20_req; - assign router_30_20_req_in[2] = router_30_19_to_router_30_20_req; - assign router_30_20_req_in[3] = router_29_20_to_router_30_20_req; - assign router_30_20_req_in[4] = magia_tile_ni_30_20_to_router_30_20_req; - - assign router_30_20_to_router_30_21_rsp = router_30_20_rsp_out[0]; - assign router_30_20_to_router_31_20_rsp = router_30_20_rsp_out[1]; - assign router_30_20_to_router_30_19_rsp = router_30_20_rsp_out[2]; - assign router_30_20_to_router_29_20_rsp = router_30_20_rsp_out[3]; - assign router_30_20_to_magia_tile_ni_30_20_rsp = router_30_20_rsp_out[4]; - - assign router_30_20_to_router_30_21_req = router_30_20_req_out[0]; - assign router_30_20_to_router_31_20_req = router_30_20_req_out[1]; - assign router_30_20_to_router_30_19_req = router_30_20_req_out[2]; - assign router_30_20_to_router_29_20_req = router_30_20_req_out[3]; - assign router_30_20_to_magia_tile_ni_30_20_req = router_30_20_req_out[4]; - - assign router_30_20_rsp_in[0] = router_30_21_to_router_30_20_rsp; - assign router_30_20_rsp_in[1] = router_31_20_to_router_30_20_rsp; - assign router_30_20_rsp_in[2] = router_30_19_to_router_30_20_rsp; - assign router_30_20_rsp_in[3] = router_29_20_to_router_30_20_rsp; - assign router_30_20_rsp_in[4] = magia_tile_ni_30_20_to_router_30_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_20_req_in), - .floo_rsp_o (router_30_20_rsp_out), - .floo_req_o (router_30_20_req_out), - .floo_rsp_i (router_30_20_rsp_in) -); - - -floo_req_t [4:0] router_30_21_req_in; -floo_rsp_t [4:0] router_30_21_rsp_out; -floo_req_t [4:0] router_30_21_req_out; -floo_rsp_t [4:0] router_30_21_rsp_in; - - assign router_30_21_req_in[0] = router_30_22_to_router_30_21_req; - assign router_30_21_req_in[1] = router_31_21_to_router_30_21_req; - assign router_30_21_req_in[2] = router_30_20_to_router_30_21_req; - assign router_30_21_req_in[3] = router_29_21_to_router_30_21_req; - assign router_30_21_req_in[4] = magia_tile_ni_30_21_to_router_30_21_req; - - assign router_30_21_to_router_30_22_rsp = router_30_21_rsp_out[0]; - assign router_30_21_to_router_31_21_rsp = router_30_21_rsp_out[1]; - assign router_30_21_to_router_30_20_rsp = router_30_21_rsp_out[2]; - assign router_30_21_to_router_29_21_rsp = router_30_21_rsp_out[3]; - assign router_30_21_to_magia_tile_ni_30_21_rsp = router_30_21_rsp_out[4]; - - assign router_30_21_to_router_30_22_req = router_30_21_req_out[0]; - assign router_30_21_to_router_31_21_req = router_30_21_req_out[1]; - assign router_30_21_to_router_30_20_req = router_30_21_req_out[2]; - assign router_30_21_to_router_29_21_req = router_30_21_req_out[3]; - assign router_30_21_to_magia_tile_ni_30_21_req = router_30_21_req_out[4]; - - assign router_30_21_rsp_in[0] = router_30_22_to_router_30_21_rsp; - assign router_30_21_rsp_in[1] = router_31_21_to_router_30_21_rsp; - assign router_30_21_rsp_in[2] = router_30_20_to_router_30_21_rsp; - assign router_30_21_rsp_in[3] = router_29_21_to_router_30_21_rsp; - assign router_30_21_rsp_in[4] = magia_tile_ni_30_21_to_router_30_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_21_req_in), - .floo_rsp_o (router_30_21_rsp_out), - .floo_req_o (router_30_21_req_out), - .floo_rsp_i (router_30_21_rsp_in) -); - - -floo_req_t [4:0] router_30_22_req_in; -floo_rsp_t [4:0] router_30_22_rsp_out; -floo_req_t [4:0] router_30_22_req_out; -floo_rsp_t [4:0] router_30_22_rsp_in; - - assign router_30_22_req_in[0] = router_30_23_to_router_30_22_req; - assign router_30_22_req_in[1] = router_31_22_to_router_30_22_req; - assign router_30_22_req_in[2] = router_30_21_to_router_30_22_req; - assign router_30_22_req_in[3] = router_29_22_to_router_30_22_req; - assign router_30_22_req_in[4] = magia_tile_ni_30_22_to_router_30_22_req; - - assign router_30_22_to_router_30_23_rsp = router_30_22_rsp_out[0]; - assign router_30_22_to_router_31_22_rsp = router_30_22_rsp_out[1]; - assign router_30_22_to_router_30_21_rsp = router_30_22_rsp_out[2]; - assign router_30_22_to_router_29_22_rsp = router_30_22_rsp_out[3]; - assign router_30_22_to_magia_tile_ni_30_22_rsp = router_30_22_rsp_out[4]; - - assign router_30_22_to_router_30_23_req = router_30_22_req_out[0]; - assign router_30_22_to_router_31_22_req = router_30_22_req_out[1]; - assign router_30_22_to_router_30_21_req = router_30_22_req_out[2]; - assign router_30_22_to_router_29_22_req = router_30_22_req_out[3]; - assign router_30_22_to_magia_tile_ni_30_22_req = router_30_22_req_out[4]; - - assign router_30_22_rsp_in[0] = router_30_23_to_router_30_22_rsp; - assign router_30_22_rsp_in[1] = router_31_22_to_router_30_22_rsp; - assign router_30_22_rsp_in[2] = router_30_21_to_router_30_22_rsp; - assign router_30_22_rsp_in[3] = router_29_22_to_router_30_22_rsp; - assign router_30_22_rsp_in[4] = magia_tile_ni_30_22_to_router_30_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_22_req_in), - .floo_rsp_o (router_30_22_rsp_out), - .floo_req_o (router_30_22_req_out), - .floo_rsp_i (router_30_22_rsp_in) -); - - -floo_req_t [4:0] router_30_23_req_in; -floo_rsp_t [4:0] router_30_23_rsp_out; -floo_req_t [4:0] router_30_23_req_out; -floo_rsp_t [4:0] router_30_23_rsp_in; - - assign router_30_23_req_in[0] = router_30_24_to_router_30_23_req; - assign router_30_23_req_in[1] = router_31_23_to_router_30_23_req; - assign router_30_23_req_in[2] = router_30_22_to_router_30_23_req; - assign router_30_23_req_in[3] = router_29_23_to_router_30_23_req; - assign router_30_23_req_in[4] = magia_tile_ni_30_23_to_router_30_23_req; - - assign router_30_23_to_router_30_24_rsp = router_30_23_rsp_out[0]; - assign router_30_23_to_router_31_23_rsp = router_30_23_rsp_out[1]; - assign router_30_23_to_router_30_22_rsp = router_30_23_rsp_out[2]; - assign router_30_23_to_router_29_23_rsp = router_30_23_rsp_out[3]; - assign router_30_23_to_magia_tile_ni_30_23_rsp = router_30_23_rsp_out[4]; - - assign router_30_23_to_router_30_24_req = router_30_23_req_out[0]; - assign router_30_23_to_router_31_23_req = router_30_23_req_out[1]; - assign router_30_23_to_router_30_22_req = router_30_23_req_out[2]; - assign router_30_23_to_router_29_23_req = router_30_23_req_out[3]; - assign router_30_23_to_magia_tile_ni_30_23_req = router_30_23_req_out[4]; - - assign router_30_23_rsp_in[0] = router_30_24_to_router_30_23_rsp; - assign router_30_23_rsp_in[1] = router_31_23_to_router_30_23_rsp; - assign router_30_23_rsp_in[2] = router_30_22_to_router_30_23_rsp; - assign router_30_23_rsp_in[3] = router_29_23_to_router_30_23_rsp; - assign router_30_23_rsp_in[4] = magia_tile_ni_30_23_to_router_30_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_23_req_in), - .floo_rsp_o (router_30_23_rsp_out), - .floo_req_o (router_30_23_req_out), - .floo_rsp_i (router_30_23_rsp_in) -); - - -floo_req_t [4:0] router_30_24_req_in; -floo_rsp_t [4:0] router_30_24_rsp_out; -floo_req_t [4:0] router_30_24_req_out; -floo_rsp_t [4:0] router_30_24_rsp_in; - - assign router_30_24_req_in[0] = router_30_25_to_router_30_24_req; - assign router_30_24_req_in[1] = router_31_24_to_router_30_24_req; - assign router_30_24_req_in[2] = router_30_23_to_router_30_24_req; - assign router_30_24_req_in[3] = router_29_24_to_router_30_24_req; - assign router_30_24_req_in[4] = magia_tile_ni_30_24_to_router_30_24_req; - - assign router_30_24_to_router_30_25_rsp = router_30_24_rsp_out[0]; - assign router_30_24_to_router_31_24_rsp = router_30_24_rsp_out[1]; - assign router_30_24_to_router_30_23_rsp = router_30_24_rsp_out[2]; - assign router_30_24_to_router_29_24_rsp = router_30_24_rsp_out[3]; - assign router_30_24_to_magia_tile_ni_30_24_rsp = router_30_24_rsp_out[4]; - - assign router_30_24_to_router_30_25_req = router_30_24_req_out[0]; - assign router_30_24_to_router_31_24_req = router_30_24_req_out[1]; - assign router_30_24_to_router_30_23_req = router_30_24_req_out[2]; - assign router_30_24_to_router_29_24_req = router_30_24_req_out[3]; - assign router_30_24_to_magia_tile_ni_30_24_req = router_30_24_req_out[4]; - - assign router_30_24_rsp_in[0] = router_30_25_to_router_30_24_rsp; - assign router_30_24_rsp_in[1] = router_31_24_to_router_30_24_rsp; - assign router_30_24_rsp_in[2] = router_30_23_to_router_30_24_rsp; - assign router_30_24_rsp_in[3] = router_29_24_to_router_30_24_rsp; - assign router_30_24_rsp_in[4] = magia_tile_ni_30_24_to_router_30_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_24_req_in), - .floo_rsp_o (router_30_24_rsp_out), - .floo_req_o (router_30_24_req_out), - .floo_rsp_i (router_30_24_rsp_in) -); - - -floo_req_t [4:0] router_30_25_req_in; -floo_rsp_t [4:0] router_30_25_rsp_out; -floo_req_t [4:0] router_30_25_req_out; -floo_rsp_t [4:0] router_30_25_rsp_in; - - assign router_30_25_req_in[0] = router_30_26_to_router_30_25_req; - assign router_30_25_req_in[1] = router_31_25_to_router_30_25_req; - assign router_30_25_req_in[2] = router_30_24_to_router_30_25_req; - assign router_30_25_req_in[3] = router_29_25_to_router_30_25_req; - assign router_30_25_req_in[4] = magia_tile_ni_30_25_to_router_30_25_req; - - assign router_30_25_to_router_30_26_rsp = router_30_25_rsp_out[0]; - assign router_30_25_to_router_31_25_rsp = router_30_25_rsp_out[1]; - assign router_30_25_to_router_30_24_rsp = router_30_25_rsp_out[2]; - assign router_30_25_to_router_29_25_rsp = router_30_25_rsp_out[3]; - assign router_30_25_to_magia_tile_ni_30_25_rsp = router_30_25_rsp_out[4]; - - assign router_30_25_to_router_30_26_req = router_30_25_req_out[0]; - assign router_30_25_to_router_31_25_req = router_30_25_req_out[1]; - assign router_30_25_to_router_30_24_req = router_30_25_req_out[2]; - assign router_30_25_to_router_29_25_req = router_30_25_req_out[3]; - assign router_30_25_to_magia_tile_ni_30_25_req = router_30_25_req_out[4]; - - assign router_30_25_rsp_in[0] = router_30_26_to_router_30_25_rsp; - assign router_30_25_rsp_in[1] = router_31_25_to_router_30_25_rsp; - assign router_30_25_rsp_in[2] = router_30_24_to_router_30_25_rsp; - assign router_30_25_rsp_in[3] = router_29_25_to_router_30_25_rsp; - assign router_30_25_rsp_in[4] = magia_tile_ni_30_25_to_router_30_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_25_req_in), - .floo_rsp_o (router_30_25_rsp_out), - .floo_req_o (router_30_25_req_out), - .floo_rsp_i (router_30_25_rsp_in) -); - - -floo_req_t [4:0] router_30_26_req_in; -floo_rsp_t [4:0] router_30_26_rsp_out; -floo_req_t [4:0] router_30_26_req_out; -floo_rsp_t [4:0] router_30_26_rsp_in; - - assign router_30_26_req_in[0] = router_30_27_to_router_30_26_req; - assign router_30_26_req_in[1] = router_31_26_to_router_30_26_req; - assign router_30_26_req_in[2] = router_30_25_to_router_30_26_req; - assign router_30_26_req_in[3] = router_29_26_to_router_30_26_req; - assign router_30_26_req_in[4] = magia_tile_ni_30_26_to_router_30_26_req; - - assign router_30_26_to_router_30_27_rsp = router_30_26_rsp_out[0]; - assign router_30_26_to_router_31_26_rsp = router_30_26_rsp_out[1]; - assign router_30_26_to_router_30_25_rsp = router_30_26_rsp_out[2]; - assign router_30_26_to_router_29_26_rsp = router_30_26_rsp_out[3]; - assign router_30_26_to_magia_tile_ni_30_26_rsp = router_30_26_rsp_out[4]; - - assign router_30_26_to_router_30_27_req = router_30_26_req_out[0]; - assign router_30_26_to_router_31_26_req = router_30_26_req_out[1]; - assign router_30_26_to_router_30_25_req = router_30_26_req_out[2]; - assign router_30_26_to_router_29_26_req = router_30_26_req_out[3]; - assign router_30_26_to_magia_tile_ni_30_26_req = router_30_26_req_out[4]; - - assign router_30_26_rsp_in[0] = router_30_27_to_router_30_26_rsp; - assign router_30_26_rsp_in[1] = router_31_26_to_router_30_26_rsp; - assign router_30_26_rsp_in[2] = router_30_25_to_router_30_26_rsp; - assign router_30_26_rsp_in[3] = router_29_26_to_router_30_26_rsp; - assign router_30_26_rsp_in[4] = magia_tile_ni_30_26_to_router_30_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_26_req_in), - .floo_rsp_o (router_30_26_rsp_out), - .floo_req_o (router_30_26_req_out), - .floo_rsp_i (router_30_26_rsp_in) -); - - -floo_req_t [4:0] router_30_27_req_in; -floo_rsp_t [4:0] router_30_27_rsp_out; -floo_req_t [4:0] router_30_27_req_out; -floo_rsp_t [4:0] router_30_27_rsp_in; - - assign router_30_27_req_in[0] = router_30_28_to_router_30_27_req; - assign router_30_27_req_in[1] = router_31_27_to_router_30_27_req; - assign router_30_27_req_in[2] = router_30_26_to_router_30_27_req; - assign router_30_27_req_in[3] = router_29_27_to_router_30_27_req; - assign router_30_27_req_in[4] = magia_tile_ni_30_27_to_router_30_27_req; - - assign router_30_27_to_router_30_28_rsp = router_30_27_rsp_out[0]; - assign router_30_27_to_router_31_27_rsp = router_30_27_rsp_out[1]; - assign router_30_27_to_router_30_26_rsp = router_30_27_rsp_out[2]; - assign router_30_27_to_router_29_27_rsp = router_30_27_rsp_out[3]; - assign router_30_27_to_magia_tile_ni_30_27_rsp = router_30_27_rsp_out[4]; - - assign router_30_27_to_router_30_28_req = router_30_27_req_out[0]; - assign router_30_27_to_router_31_27_req = router_30_27_req_out[1]; - assign router_30_27_to_router_30_26_req = router_30_27_req_out[2]; - assign router_30_27_to_router_29_27_req = router_30_27_req_out[3]; - assign router_30_27_to_magia_tile_ni_30_27_req = router_30_27_req_out[4]; - - assign router_30_27_rsp_in[0] = router_30_28_to_router_30_27_rsp; - assign router_30_27_rsp_in[1] = router_31_27_to_router_30_27_rsp; - assign router_30_27_rsp_in[2] = router_30_26_to_router_30_27_rsp; - assign router_30_27_rsp_in[3] = router_29_27_to_router_30_27_rsp; - assign router_30_27_rsp_in[4] = magia_tile_ni_30_27_to_router_30_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_27_req_in), - .floo_rsp_o (router_30_27_rsp_out), - .floo_req_o (router_30_27_req_out), - .floo_rsp_i (router_30_27_rsp_in) -); - - -floo_req_t [4:0] router_30_28_req_in; -floo_rsp_t [4:0] router_30_28_rsp_out; -floo_req_t [4:0] router_30_28_req_out; -floo_rsp_t [4:0] router_30_28_rsp_in; - - assign router_30_28_req_in[0] = router_30_29_to_router_30_28_req; - assign router_30_28_req_in[1] = router_31_28_to_router_30_28_req; - assign router_30_28_req_in[2] = router_30_27_to_router_30_28_req; - assign router_30_28_req_in[3] = router_29_28_to_router_30_28_req; - assign router_30_28_req_in[4] = magia_tile_ni_30_28_to_router_30_28_req; - - assign router_30_28_to_router_30_29_rsp = router_30_28_rsp_out[0]; - assign router_30_28_to_router_31_28_rsp = router_30_28_rsp_out[1]; - assign router_30_28_to_router_30_27_rsp = router_30_28_rsp_out[2]; - assign router_30_28_to_router_29_28_rsp = router_30_28_rsp_out[3]; - assign router_30_28_to_magia_tile_ni_30_28_rsp = router_30_28_rsp_out[4]; - - assign router_30_28_to_router_30_29_req = router_30_28_req_out[0]; - assign router_30_28_to_router_31_28_req = router_30_28_req_out[1]; - assign router_30_28_to_router_30_27_req = router_30_28_req_out[2]; - assign router_30_28_to_router_29_28_req = router_30_28_req_out[3]; - assign router_30_28_to_magia_tile_ni_30_28_req = router_30_28_req_out[4]; - - assign router_30_28_rsp_in[0] = router_30_29_to_router_30_28_rsp; - assign router_30_28_rsp_in[1] = router_31_28_to_router_30_28_rsp; - assign router_30_28_rsp_in[2] = router_30_27_to_router_30_28_rsp; - assign router_30_28_rsp_in[3] = router_29_28_to_router_30_28_rsp; - assign router_30_28_rsp_in[4] = magia_tile_ni_30_28_to_router_30_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_28_req_in), - .floo_rsp_o (router_30_28_rsp_out), - .floo_req_o (router_30_28_req_out), - .floo_rsp_i (router_30_28_rsp_in) -); - - -floo_req_t [4:0] router_30_29_req_in; -floo_rsp_t [4:0] router_30_29_rsp_out; -floo_req_t [4:0] router_30_29_req_out; -floo_rsp_t [4:0] router_30_29_rsp_in; - - assign router_30_29_req_in[0] = router_30_30_to_router_30_29_req; - assign router_30_29_req_in[1] = router_31_29_to_router_30_29_req; - assign router_30_29_req_in[2] = router_30_28_to_router_30_29_req; - assign router_30_29_req_in[3] = router_29_29_to_router_30_29_req; - assign router_30_29_req_in[4] = magia_tile_ni_30_29_to_router_30_29_req; - - assign router_30_29_to_router_30_30_rsp = router_30_29_rsp_out[0]; - assign router_30_29_to_router_31_29_rsp = router_30_29_rsp_out[1]; - assign router_30_29_to_router_30_28_rsp = router_30_29_rsp_out[2]; - assign router_30_29_to_router_29_29_rsp = router_30_29_rsp_out[3]; - assign router_30_29_to_magia_tile_ni_30_29_rsp = router_30_29_rsp_out[4]; - - assign router_30_29_to_router_30_30_req = router_30_29_req_out[0]; - assign router_30_29_to_router_31_29_req = router_30_29_req_out[1]; - assign router_30_29_to_router_30_28_req = router_30_29_req_out[2]; - assign router_30_29_to_router_29_29_req = router_30_29_req_out[3]; - assign router_30_29_to_magia_tile_ni_30_29_req = router_30_29_req_out[4]; - - assign router_30_29_rsp_in[0] = router_30_30_to_router_30_29_rsp; - assign router_30_29_rsp_in[1] = router_31_29_to_router_30_29_rsp; - assign router_30_29_rsp_in[2] = router_30_28_to_router_30_29_rsp; - assign router_30_29_rsp_in[3] = router_29_29_to_router_30_29_rsp; - assign router_30_29_rsp_in[4] = magia_tile_ni_30_29_to_router_30_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_29_req_in), - .floo_rsp_o (router_30_29_rsp_out), - .floo_req_o (router_30_29_req_out), - .floo_rsp_i (router_30_29_rsp_in) -); - - -floo_req_t [4:0] router_30_30_req_in; -floo_rsp_t [4:0] router_30_30_rsp_out; -floo_req_t [4:0] router_30_30_req_out; -floo_rsp_t [4:0] router_30_30_rsp_in; - - assign router_30_30_req_in[0] = router_30_31_to_router_30_30_req; - assign router_30_30_req_in[1] = router_31_30_to_router_30_30_req; - assign router_30_30_req_in[2] = router_30_29_to_router_30_30_req; - assign router_30_30_req_in[3] = router_29_30_to_router_30_30_req; - assign router_30_30_req_in[4] = magia_tile_ni_30_30_to_router_30_30_req; - - assign router_30_30_to_router_30_31_rsp = router_30_30_rsp_out[0]; - assign router_30_30_to_router_31_30_rsp = router_30_30_rsp_out[1]; - assign router_30_30_to_router_30_29_rsp = router_30_30_rsp_out[2]; - assign router_30_30_to_router_29_30_rsp = router_30_30_rsp_out[3]; - assign router_30_30_to_magia_tile_ni_30_30_rsp = router_30_30_rsp_out[4]; - - assign router_30_30_to_router_30_31_req = router_30_30_req_out[0]; - assign router_30_30_to_router_31_30_req = router_30_30_req_out[1]; - assign router_30_30_to_router_30_29_req = router_30_30_req_out[2]; - assign router_30_30_to_router_29_30_req = router_30_30_req_out[3]; - assign router_30_30_to_magia_tile_ni_30_30_req = router_30_30_req_out[4]; - - assign router_30_30_rsp_in[0] = router_30_31_to_router_30_30_rsp; - assign router_30_30_rsp_in[1] = router_31_30_to_router_30_30_rsp; - assign router_30_30_rsp_in[2] = router_30_29_to_router_30_30_rsp; - assign router_30_30_rsp_in[3] = router_29_30_to_router_30_30_rsp; - assign router_30_30_rsp_in[4] = magia_tile_ni_30_30_to_router_30_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_30_req_in), - .floo_rsp_o (router_30_30_rsp_out), - .floo_req_o (router_30_30_req_out), - .floo_rsp_i (router_30_30_rsp_in) -); - - -floo_req_t [4:0] router_30_31_req_in; -floo_rsp_t [4:0] router_30_31_rsp_out; -floo_req_t [4:0] router_30_31_req_out; -floo_rsp_t [4:0] router_30_31_rsp_in; - - assign router_30_31_req_in[0] = '0; - assign router_30_31_req_in[1] = router_31_31_to_router_30_31_req; - assign router_30_31_req_in[2] = router_30_30_to_router_30_31_req; - assign router_30_31_req_in[3] = router_29_31_to_router_30_31_req; - assign router_30_31_req_in[4] = magia_tile_ni_30_31_to_router_30_31_req; - - assign router_30_31_to_router_31_31_rsp = router_30_31_rsp_out[1]; - assign router_30_31_to_router_30_30_rsp = router_30_31_rsp_out[2]; - assign router_30_31_to_router_29_31_rsp = router_30_31_rsp_out[3]; - assign router_30_31_to_magia_tile_ni_30_31_rsp = router_30_31_rsp_out[4]; - - assign router_30_31_to_router_31_31_req = router_30_31_req_out[1]; - assign router_30_31_to_router_30_30_req = router_30_31_req_out[2]; - assign router_30_31_to_router_29_31_req = router_30_31_req_out[3]; - assign router_30_31_to_magia_tile_ni_30_31_req = router_30_31_req_out[4]; - - assign router_30_31_rsp_in[0] = '0; - assign router_30_31_rsp_in[1] = router_31_31_to_router_30_31_rsp; - assign router_30_31_rsp_in[2] = router_30_30_to_router_30_31_rsp; - assign router_30_31_rsp_in[3] = router_29_31_to_router_30_31_rsp; - assign router_30_31_rsp_in[4] = magia_tile_ni_30_31_to_router_30_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_30_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 31, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_30_31_req_in), - .floo_rsp_o (router_30_31_rsp_out), - .floo_req_o (router_30_31_req_out), - .floo_rsp_i (router_30_31_rsp_in) -); - - -floo_req_t [4:0] router_31_0_req_in; -floo_rsp_t [4:0] router_31_0_rsp_out; -floo_req_t [4:0] router_31_0_req_out; -floo_rsp_t [4:0] router_31_0_rsp_in; - - assign router_31_0_req_in[0] = router_31_1_to_router_31_0_req; - assign router_31_0_req_in[1] = '0; - assign router_31_0_req_in[2] = '0; - assign router_31_0_req_in[3] = router_30_0_to_router_31_0_req; - assign router_31_0_req_in[4] = magia_tile_ni_31_0_to_router_31_0_req; - - assign router_31_0_to_router_31_1_rsp = router_31_0_rsp_out[0]; - assign router_31_0_to_router_30_0_rsp = router_31_0_rsp_out[3]; - assign router_31_0_to_magia_tile_ni_31_0_rsp = router_31_0_rsp_out[4]; - - assign router_31_0_to_router_31_1_req = router_31_0_req_out[0]; - assign router_31_0_to_router_30_0_req = router_31_0_req_out[3]; - assign router_31_0_to_magia_tile_ni_31_0_req = router_31_0_req_out[4]; - - assign router_31_0_rsp_in[0] = router_31_1_to_router_31_0_rsp; - assign router_31_0_rsp_in[1] = '0; - assign router_31_0_rsp_in[2] = '0; - assign router_31_0_rsp_in[3] = router_30_0_to_router_31_0_rsp; - assign router_31_0_rsp_in[4] = magia_tile_ni_31_0_to_router_31_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_0_req_in), - .floo_rsp_o (router_31_0_rsp_out), - .floo_req_o (router_31_0_req_out), - .floo_rsp_i (router_31_0_rsp_in) -); - - -floo_req_t [4:0] router_31_1_req_in; -floo_rsp_t [4:0] router_31_1_rsp_out; -floo_req_t [4:0] router_31_1_req_out; -floo_rsp_t [4:0] router_31_1_rsp_in; - - assign router_31_1_req_in[0] = router_31_2_to_router_31_1_req; - assign router_31_1_req_in[1] = '0; - assign router_31_1_req_in[2] = router_31_0_to_router_31_1_req; - assign router_31_1_req_in[3] = router_30_1_to_router_31_1_req; - assign router_31_1_req_in[4] = magia_tile_ni_31_1_to_router_31_1_req; - - assign router_31_1_to_router_31_2_rsp = router_31_1_rsp_out[0]; - assign router_31_1_to_router_31_0_rsp = router_31_1_rsp_out[2]; - assign router_31_1_to_router_30_1_rsp = router_31_1_rsp_out[3]; - assign router_31_1_to_magia_tile_ni_31_1_rsp = router_31_1_rsp_out[4]; - - assign router_31_1_to_router_31_2_req = router_31_1_req_out[0]; - assign router_31_1_to_router_31_0_req = router_31_1_req_out[2]; - assign router_31_1_to_router_30_1_req = router_31_1_req_out[3]; - assign router_31_1_to_magia_tile_ni_31_1_req = router_31_1_req_out[4]; - - assign router_31_1_rsp_in[0] = router_31_2_to_router_31_1_rsp; - assign router_31_1_rsp_in[1] = '0; - assign router_31_1_rsp_in[2] = router_31_0_to_router_31_1_rsp; - assign router_31_1_rsp_in[3] = router_30_1_to_router_31_1_rsp; - assign router_31_1_rsp_in[4] = magia_tile_ni_31_1_to_router_31_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_1_req_in), - .floo_rsp_o (router_31_1_rsp_out), - .floo_req_o (router_31_1_req_out), - .floo_rsp_i (router_31_1_rsp_in) -); - - -floo_req_t [4:0] router_31_2_req_in; -floo_rsp_t [4:0] router_31_2_rsp_out; -floo_req_t [4:0] router_31_2_req_out; -floo_rsp_t [4:0] router_31_2_rsp_in; - - assign router_31_2_req_in[0] = router_31_3_to_router_31_2_req; - assign router_31_2_req_in[1] = '0; - assign router_31_2_req_in[2] = router_31_1_to_router_31_2_req; - assign router_31_2_req_in[3] = router_30_2_to_router_31_2_req; - assign router_31_2_req_in[4] = magia_tile_ni_31_2_to_router_31_2_req; - - assign router_31_2_to_router_31_3_rsp = router_31_2_rsp_out[0]; - assign router_31_2_to_router_31_1_rsp = router_31_2_rsp_out[2]; - assign router_31_2_to_router_30_2_rsp = router_31_2_rsp_out[3]; - assign router_31_2_to_magia_tile_ni_31_2_rsp = router_31_2_rsp_out[4]; - - assign router_31_2_to_router_31_3_req = router_31_2_req_out[0]; - assign router_31_2_to_router_31_1_req = router_31_2_req_out[2]; - assign router_31_2_to_router_30_2_req = router_31_2_req_out[3]; - assign router_31_2_to_magia_tile_ni_31_2_req = router_31_2_req_out[4]; - - assign router_31_2_rsp_in[0] = router_31_3_to_router_31_2_rsp; - assign router_31_2_rsp_in[1] = '0; - assign router_31_2_rsp_in[2] = router_31_1_to_router_31_2_rsp; - assign router_31_2_rsp_in[3] = router_30_2_to_router_31_2_rsp; - assign router_31_2_rsp_in[4] = magia_tile_ni_31_2_to_router_31_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_2_req_in), - .floo_rsp_o (router_31_2_rsp_out), - .floo_req_o (router_31_2_req_out), - .floo_rsp_i (router_31_2_rsp_in) -); - - -floo_req_t [4:0] router_31_3_req_in; -floo_rsp_t [4:0] router_31_3_rsp_out; -floo_req_t [4:0] router_31_3_req_out; -floo_rsp_t [4:0] router_31_3_rsp_in; - - assign router_31_3_req_in[0] = router_31_4_to_router_31_3_req; - assign router_31_3_req_in[1] = '0; - assign router_31_3_req_in[2] = router_31_2_to_router_31_3_req; - assign router_31_3_req_in[3] = router_30_3_to_router_31_3_req; - assign router_31_3_req_in[4] = magia_tile_ni_31_3_to_router_31_3_req; - - assign router_31_3_to_router_31_4_rsp = router_31_3_rsp_out[0]; - assign router_31_3_to_router_31_2_rsp = router_31_3_rsp_out[2]; - assign router_31_3_to_router_30_3_rsp = router_31_3_rsp_out[3]; - assign router_31_3_to_magia_tile_ni_31_3_rsp = router_31_3_rsp_out[4]; - - assign router_31_3_to_router_31_4_req = router_31_3_req_out[0]; - assign router_31_3_to_router_31_2_req = router_31_3_req_out[2]; - assign router_31_3_to_router_30_3_req = router_31_3_req_out[3]; - assign router_31_3_to_magia_tile_ni_31_3_req = router_31_3_req_out[4]; - - assign router_31_3_rsp_in[0] = router_31_4_to_router_31_3_rsp; - assign router_31_3_rsp_in[1] = '0; - assign router_31_3_rsp_in[2] = router_31_2_to_router_31_3_rsp; - assign router_31_3_rsp_in[3] = router_30_3_to_router_31_3_rsp; - assign router_31_3_rsp_in[4] = magia_tile_ni_31_3_to_router_31_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_3_req_in), - .floo_rsp_o (router_31_3_rsp_out), - .floo_req_o (router_31_3_req_out), - .floo_rsp_i (router_31_3_rsp_in) -); - - -floo_req_t [4:0] router_31_4_req_in; -floo_rsp_t [4:0] router_31_4_rsp_out; -floo_req_t [4:0] router_31_4_req_out; -floo_rsp_t [4:0] router_31_4_rsp_in; - - assign router_31_4_req_in[0] = router_31_5_to_router_31_4_req; - assign router_31_4_req_in[1] = '0; - assign router_31_4_req_in[2] = router_31_3_to_router_31_4_req; - assign router_31_4_req_in[3] = router_30_4_to_router_31_4_req; - assign router_31_4_req_in[4] = magia_tile_ni_31_4_to_router_31_4_req; - - assign router_31_4_to_router_31_5_rsp = router_31_4_rsp_out[0]; - assign router_31_4_to_router_31_3_rsp = router_31_4_rsp_out[2]; - assign router_31_4_to_router_30_4_rsp = router_31_4_rsp_out[3]; - assign router_31_4_to_magia_tile_ni_31_4_rsp = router_31_4_rsp_out[4]; - - assign router_31_4_to_router_31_5_req = router_31_4_req_out[0]; - assign router_31_4_to_router_31_3_req = router_31_4_req_out[2]; - assign router_31_4_to_router_30_4_req = router_31_4_req_out[3]; - assign router_31_4_to_magia_tile_ni_31_4_req = router_31_4_req_out[4]; - - assign router_31_4_rsp_in[0] = router_31_5_to_router_31_4_rsp; - assign router_31_4_rsp_in[1] = '0; - assign router_31_4_rsp_in[2] = router_31_3_to_router_31_4_rsp; - assign router_31_4_rsp_in[3] = router_30_4_to_router_31_4_rsp; - assign router_31_4_rsp_in[4] = magia_tile_ni_31_4_to_router_31_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_4_req_in), - .floo_rsp_o (router_31_4_rsp_out), - .floo_req_o (router_31_4_req_out), - .floo_rsp_i (router_31_4_rsp_in) -); - - -floo_req_t [4:0] router_31_5_req_in; -floo_rsp_t [4:0] router_31_5_rsp_out; -floo_req_t [4:0] router_31_5_req_out; -floo_rsp_t [4:0] router_31_5_rsp_in; - - assign router_31_5_req_in[0] = router_31_6_to_router_31_5_req; - assign router_31_5_req_in[1] = '0; - assign router_31_5_req_in[2] = router_31_4_to_router_31_5_req; - assign router_31_5_req_in[3] = router_30_5_to_router_31_5_req; - assign router_31_5_req_in[4] = magia_tile_ni_31_5_to_router_31_5_req; - - assign router_31_5_to_router_31_6_rsp = router_31_5_rsp_out[0]; - assign router_31_5_to_router_31_4_rsp = router_31_5_rsp_out[2]; - assign router_31_5_to_router_30_5_rsp = router_31_5_rsp_out[3]; - assign router_31_5_to_magia_tile_ni_31_5_rsp = router_31_5_rsp_out[4]; - - assign router_31_5_to_router_31_6_req = router_31_5_req_out[0]; - assign router_31_5_to_router_31_4_req = router_31_5_req_out[2]; - assign router_31_5_to_router_30_5_req = router_31_5_req_out[3]; - assign router_31_5_to_magia_tile_ni_31_5_req = router_31_5_req_out[4]; - - assign router_31_5_rsp_in[0] = router_31_6_to_router_31_5_rsp; - assign router_31_5_rsp_in[1] = '0; - assign router_31_5_rsp_in[2] = router_31_4_to_router_31_5_rsp; - assign router_31_5_rsp_in[3] = router_30_5_to_router_31_5_rsp; - assign router_31_5_rsp_in[4] = magia_tile_ni_31_5_to_router_31_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_5_req_in), - .floo_rsp_o (router_31_5_rsp_out), - .floo_req_o (router_31_5_req_out), - .floo_rsp_i (router_31_5_rsp_in) -); - - -floo_req_t [4:0] router_31_6_req_in; -floo_rsp_t [4:0] router_31_6_rsp_out; -floo_req_t [4:0] router_31_6_req_out; -floo_rsp_t [4:0] router_31_6_rsp_in; - - assign router_31_6_req_in[0] = router_31_7_to_router_31_6_req; - assign router_31_6_req_in[1] = '0; - assign router_31_6_req_in[2] = router_31_5_to_router_31_6_req; - assign router_31_6_req_in[3] = router_30_6_to_router_31_6_req; - assign router_31_6_req_in[4] = magia_tile_ni_31_6_to_router_31_6_req; - - assign router_31_6_to_router_31_7_rsp = router_31_6_rsp_out[0]; - assign router_31_6_to_router_31_5_rsp = router_31_6_rsp_out[2]; - assign router_31_6_to_router_30_6_rsp = router_31_6_rsp_out[3]; - assign router_31_6_to_magia_tile_ni_31_6_rsp = router_31_6_rsp_out[4]; - - assign router_31_6_to_router_31_7_req = router_31_6_req_out[0]; - assign router_31_6_to_router_31_5_req = router_31_6_req_out[2]; - assign router_31_6_to_router_30_6_req = router_31_6_req_out[3]; - assign router_31_6_to_magia_tile_ni_31_6_req = router_31_6_req_out[4]; - - assign router_31_6_rsp_in[0] = router_31_7_to_router_31_6_rsp; - assign router_31_6_rsp_in[1] = '0; - assign router_31_6_rsp_in[2] = router_31_5_to_router_31_6_rsp; - assign router_31_6_rsp_in[3] = router_30_6_to_router_31_6_rsp; - assign router_31_6_rsp_in[4] = magia_tile_ni_31_6_to_router_31_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_6_req_in), - .floo_rsp_o (router_31_6_rsp_out), - .floo_req_o (router_31_6_req_out), - .floo_rsp_i (router_31_6_rsp_in) -); - - -floo_req_t [4:0] router_31_7_req_in; -floo_rsp_t [4:0] router_31_7_rsp_out; -floo_req_t [4:0] router_31_7_req_out; -floo_rsp_t [4:0] router_31_7_rsp_in; - - assign router_31_7_req_in[0] = router_31_8_to_router_31_7_req; - assign router_31_7_req_in[1] = '0; - assign router_31_7_req_in[2] = router_31_6_to_router_31_7_req; - assign router_31_7_req_in[3] = router_30_7_to_router_31_7_req; - assign router_31_7_req_in[4] = magia_tile_ni_31_7_to_router_31_7_req; - - assign router_31_7_to_router_31_8_rsp = router_31_7_rsp_out[0]; - assign router_31_7_to_router_31_6_rsp = router_31_7_rsp_out[2]; - assign router_31_7_to_router_30_7_rsp = router_31_7_rsp_out[3]; - assign router_31_7_to_magia_tile_ni_31_7_rsp = router_31_7_rsp_out[4]; - - assign router_31_7_to_router_31_8_req = router_31_7_req_out[0]; - assign router_31_7_to_router_31_6_req = router_31_7_req_out[2]; - assign router_31_7_to_router_30_7_req = router_31_7_req_out[3]; - assign router_31_7_to_magia_tile_ni_31_7_req = router_31_7_req_out[4]; - - assign router_31_7_rsp_in[0] = router_31_8_to_router_31_7_rsp; - assign router_31_7_rsp_in[1] = '0; - assign router_31_7_rsp_in[2] = router_31_6_to_router_31_7_rsp; - assign router_31_7_rsp_in[3] = router_30_7_to_router_31_7_rsp; - assign router_31_7_rsp_in[4] = magia_tile_ni_31_7_to_router_31_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_7_req_in), - .floo_rsp_o (router_31_7_rsp_out), - .floo_req_o (router_31_7_req_out), - .floo_rsp_i (router_31_7_rsp_in) -); - - -floo_req_t [4:0] router_31_8_req_in; -floo_rsp_t [4:0] router_31_8_rsp_out; -floo_req_t [4:0] router_31_8_req_out; -floo_rsp_t [4:0] router_31_8_rsp_in; - - assign router_31_8_req_in[0] = router_31_9_to_router_31_8_req; - assign router_31_8_req_in[1] = '0; - assign router_31_8_req_in[2] = router_31_7_to_router_31_8_req; - assign router_31_8_req_in[3] = router_30_8_to_router_31_8_req; - assign router_31_8_req_in[4] = magia_tile_ni_31_8_to_router_31_8_req; - - assign router_31_8_to_router_31_9_rsp = router_31_8_rsp_out[0]; - assign router_31_8_to_router_31_7_rsp = router_31_8_rsp_out[2]; - assign router_31_8_to_router_30_8_rsp = router_31_8_rsp_out[3]; - assign router_31_8_to_magia_tile_ni_31_8_rsp = router_31_8_rsp_out[4]; - - assign router_31_8_to_router_31_9_req = router_31_8_req_out[0]; - assign router_31_8_to_router_31_7_req = router_31_8_req_out[2]; - assign router_31_8_to_router_30_8_req = router_31_8_req_out[3]; - assign router_31_8_to_magia_tile_ni_31_8_req = router_31_8_req_out[4]; - - assign router_31_8_rsp_in[0] = router_31_9_to_router_31_8_rsp; - assign router_31_8_rsp_in[1] = '0; - assign router_31_8_rsp_in[2] = router_31_7_to_router_31_8_rsp; - assign router_31_8_rsp_in[3] = router_30_8_to_router_31_8_rsp; - assign router_31_8_rsp_in[4] = magia_tile_ni_31_8_to_router_31_8_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_8 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 8, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_8_req_in), - .floo_rsp_o (router_31_8_rsp_out), - .floo_req_o (router_31_8_req_out), - .floo_rsp_i (router_31_8_rsp_in) -); - - -floo_req_t [4:0] router_31_9_req_in; -floo_rsp_t [4:0] router_31_9_rsp_out; -floo_req_t [4:0] router_31_9_req_out; -floo_rsp_t [4:0] router_31_9_rsp_in; - - assign router_31_9_req_in[0] = router_31_10_to_router_31_9_req; - assign router_31_9_req_in[1] = '0; - assign router_31_9_req_in[2] = router_31_8_to_router_31_9_req; - assign router_31_9_req_in[3] = router_30_9_to_router_31_9_req; - assign router_31_9_req_in[4] = magia_tile_ni_31_9_to_router_31_9_req; - - assign router_31_9_to_router_31_10_rsp = router_31_9_rsp_out[0]; - assign router_31_9_to_router_31_8_rsp = router_31_9_rsp_out[2]; - assign router_31_9_to_router_30_9_rsp = router_31_9_rsp_out[3]; - assign router_31_9_to_magia_tile_ni_31_9_rsp = router_31_9_rsp_out[4]; - - assign router_31_9_to_router_31_10_req = router_31_9_req_out[0]; - assign router_31_9_to_router_31_8_req = router_31_9_req_out[2]; - assign router_31_9_to_router_30_9_req = router_31_9_req_out[3]; - assign router_31_9_to_magia_tile_ni_31_9_req = router_31_9_req_out[4]; - - assign router_31_9_rsp_in[0] = router_31_10_to_router_31_9_rsp; - assign router_31_9_rsp_in[1] = '0; - assign router_31_9_rsp_in[2] = router_31_8_to_router_31_9_rsp; - assign router_31_9_rsp_in[3] = router_30_9_to_router_31_9_rsp; - assign router_31_9_rsp_in[4] = magia_tile_ni_31_9_to_router_31_9_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_9 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 9, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_9_req_in), - .floo_rsp_o (router_31_9_rsp_out), - .floo_req_o (router_31_9_req_out), - .floo_rsp_i (router_31_9_rsp_in) -); - - -floo_req_t [4:0] router_31_10_req_in; -floo_rsp_t [4:0] router_31_10_rsp_out; -floo_req_t [4:0] router_31_10_req_out; -floo_rsp_t [4:0] router_31_10_rsp_in; - - assign router_31_10_req_in[0] = router_31_11_to_router_31_10_req; - assign router_31_10_req_in[1] = '0; - assign router_31_10_req_in[2] = router_31_9_to_router_31_10_req; - assign router_31_10_req_in[3] = router_30_10_to_router_31_10_req; - assign router_31_10_req_in[4] = magia_tile_ni_31_10_to_router_31_10_req; - - assign router_31_10_to_router_31_11_rsp = router_31_10_rsp_out[0]; - assign router_31_10_to_router_31_9_rsp = router_31_10_rsp_out[2]; - assign router_31_10_to_router_30_10_rsp = router_31_10_rsp_out[3]; - assign router_31_10_to_magia_tile_ni_31_10_rsp = router_31_10_rsp_out[4]; - - assign router_31_10_to_router_31_11_req = router_31_10_req_out[0]; - assign router_31_10_to_router_31_9_req = router_31_10_req_out[2]; - assign router_31_10_to_router_30_10_req = router_31_10_req_out[3]; - assign router_31_10_to_magia_tile_ni_31_10_req = router_31_10_req_out[4]; - - assign router_31_10_rsp_in[0] = router_31_11_to_router_31_10_rsp; - assign router_31_10_rsp_in[1] = '0; - assign router_31_10_rsp_in[2] = router_31_9_to_router_31_10_rsp; - assign router_31_10_rsp_in[3] = router_30_10_to_router_31_10_rsp; - assign router_31_10_rsp_in[4] = magia_tile_ni_31_10_to_router_31_10_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_10 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 10, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_10_req_in), - .floo_rsp_o (router_31_10_rsp_out), - .floo_req_o (router_31_10_req_out), - .floo_rsp_i (router_31_10_rsp_in) -); - - -floo_req_t [4:0] router_31_11_req_in; -floo_rsp_t [4:0] router_31_11_rsp_out; -floo_req_t [4:0] router_31_11_req_out; -floo_rsp_t [4:0] router_31_11_rsp_in; - - assign router_31_11_req_in[0] = router_31_12_to_router_31_11_req; - assign router_31_11_req_in[1] = '0; - assign router_31_11_req_in[2] = router_31_10_to_router_31_11_req; - assign router_31_11_req_in[3] = router_30_11_to_router_31_11_req; - assign router_31_11_req_in[4] = magia_tile_ni_31_11_to_router_31_11_req; - - assign router_31_11_to_router_31_12_rsp = router_31_11_rsp_out[0]; - assign router_31_11_to_router_31_10_rsp = router_31_11_rsp_out[2]; - assign router_31_11_to_router_30_11_rsp = router_31_11_rsp_out[3]; - assign router_31_11_to_magia_tile_ni_31_11_rsp = router_31_11_rsp_out[4]; - - assign router_31_11_to_router_31_12_req = router_31_11_req_out[0]; - assign router_31_11_to_router_31_10_req = router_31_11_req_out[2]; - assign router_31_11_to_router_30_11_req = router_31_11_req_out[3]; - assign router_31_11_to_magia_tile_ni_31_11_req = router_31_11_req_out[4]; - - assign router_31_11_rsp_in[0] = router_31_12_to_router_31_11_rsp; - assign router_31_11_rsp_in[1] = '0; - assign router_31_11_rsp_in[2] = router_31_10_to_router_31_11_rsp; - assign router_31_11_rsp_in[3] = router_30_11_to_router_31_11_rsp; - assign router_31_11_rsp_in[4] = magia_tile_ni_31_11_to_router_31_11_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_11 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 11, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_11_req_in), - .floo_rsp_o (router_31_11_rsp_out), - .floo_req_o (router_31_11_req_out), - .floo_rsp_i (router_31_11_rsp_in) -); - - -floo_req_t [4:0] router_31_12_req_in; -floo_rsp_t [4:0] router_31_12_rsp_out; -floo_req_t [4:0] router_31_12_req_out; -floo_rsp_t [4:0] router_31_12_rsp_in; - - assign router_31_12_req_in[0] = router_31_13_to_router_31_12_req; - assign router_31_12_req_in[1] = '0; - assign router_31_12_req_in[2] = router_31_11_to_router_31_12_req; - assign router_31_12_req_in[3] = router_30_12_to_router_31_12_req; - assign router_31_12_req_in[4] = magia_tile_ni_31_12_to_router_31_12_req; - - assign router_31_12_to_router_31_13_rsp = router_31_12_rsp_out[0]; - assign router_31_12_to_router_31_11_rsp = router_31_12_rsp_out[2]; - assign router_31_12_to_router_30_12_rsp = router_31_12_rsp_out[3]; - assign router_31_12_to_magia_tile_ni_31_12_rsp = router_31_12_rsp_out[4]; - - assign router_31_12_to_router_31_13_req = router_31_12_req_out[0]; - assign router_31_12_to_router_31_11_req = router_31_12_req_out[2]; - assign router_31_12_to_router_30_12_req = router_31_12_req_out[3]; - assign router_31_12_to_magia_tile_ni_31_12_req = router_31_12_req_out[4]; - - assign router_31_12_rsp_in[0] = router_31_13_to_router_31_12_rsp; - assign router_31_12_rsp_in[1] = '0; - assign router_31_12_rsp_in[2] = router_31_11_to_router_31_12_rsp; - assign router_31_12_rsp_in[3] = router_30_12_to_router_31_12_rsp; - assign router_31_12_rsp_in[4] = magia_tile_ni_31_12_to_router_31_12_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_12 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 12, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_12_req_in), - .floo_rsp_o (router_31_12_rsp_out), - .floo_req_o (router_31_12_req_out), - .floo_rsp_i (router_31_12_rsp_in) -); - - -floo_req_t [4:0] router_31_13_req_in; -floo_rsp_t [4:0] router_31_13_rsp_out; -floo_req_t [4:0] router_31_13_req_out; -floo_rsp_t [4:0] router_31_13_rsp_in; - - assign router_31_13_req_in[0] = router_31_14_to_router_31_13_req; - assign router_31_13_req_in[1] = '0; - assign router_31_13_req_in[2] = router_31_12_to_router_31_13_req; - assign router_31_13_req_in[3] = router_30_13_to_router_31_13_req; - assign router_31_13_req_in[4] = magia_tile_ni_31_13_to_router_31_13_req; - - assign router_31_13_to_router_31_14_rsp = router_31_13_rsp_out[0]; - assign router_31_13_to_router_31_12_rsp = router_31_13_rsp_out[2]; - assign router_31_13_to_router_30_13_rsp = router_31_13_rsp_out[3]; - assign router_31_13_to_magia_tile_ni_31_13_rsp = router_31_13_rsp_out[4]; - - assign router_31_13_to_router_31_14_req = router_31_13_req_out[0]; - assign router_31_13_to_router_31_12_req = router_31_13_req_out[2]; - assign router_31_13_to_router_30_13_req = router_31_13_req_out[3]; - assign router_31_13_to_magia_tile_ni_31_13_req = router_31_13_req_out[4]; - - assign router_31_13_rsp_in[0] = router_31_14_to_router_31_13_rsp; - assign router_31_13_rsp_in[1] = '0; - assign router_31_13_rsp_in[2] = router_31_12_to_router_31_13_rsp; - assign router_31_13_rsp_in[3] = router_30_13_to_router_31_13_rsp; - assign router_31_13_rsp_in[4] = magia_tile_ni_31_13_to_router_31_13_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_13 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 13, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_13_req_in), - .floo_rsp_o (router_31_13_rsp_out), - .floo_req_o (router_31_13_req_out), - .floo_rsp_i (router_31_13_rsp_in) -); - - -floo_req_t [4:0] router_31_14_req_in; -floo_rsp_t [4:0] router_31_14_rsp_out; -floo_req_t [4:0] router_31_14_req_out; -floo_rsp_t [4:0] router_31_14_rsp_in; - - assign router_31_14_req_in[0] = router_31_15_to_router_31_14_req; - assign router_31_14_req_in[1] = '0; - assign router_31_14_req_in[2] = router_31_13_to_router_31_14_req; - assign router_31_14_req_in[3] = router_30_14_to_router_31_14_req; - assign router_31_14_req_in[4] = magia_tile_ni_31_14_to_router_31_14_req; - - assign router_31_14_to_router_31_15_rsp = router_31_14_rsp_out[0]; - assign router_31_14_to_router_31_13_rsp = router_31_14_rsp_out[2]; - assign router_31_14_to_router_30_14_rsp = router_31_14_rsp_out[3]; - assign router_31_14_to_magia_tile_ni_31_14_rsp = router_31_14_rsp_out[4]; - - assign router_31_14_to_router_31_15_req = router_31_14_req_out[0]; - assign router_31_14_to_router_31_13_req = router_31_14_req_out[2]; - assign router_31_14_to_router_30_14_req = router_31_14_req_out[3]; - assign router_31_14_to_magia_tile_ni_31_14_req = router_31_14_req_out[4]; - - assign router_31_14_rsp_in[0] = router_31_15_to_router_31_14_rsp; - assign router_31_14_rsp_in[1] = '0; - assign router_31_14_rsp_in[2] = router_31_13_to_router_31_14_rsp; - assign router_31_14_rsp_in[3] = router_30_14_to_router_31_14_rsp; - assign router_31_14_rsp_in[4] = magia_tile_ni_31_14_to_router_31_14_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_14 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 14, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_14_req_in), - .floo_rsp_o (router_31_14_rsp_out), - .floo_req_o (router_31_14_req_out), - .floo_rsp_i (router_31_14_rsp_in) -); - - -floo_req_t [4:0] router_31_15_req_in; -floo_rsp_t [4:0] router_31_15_rsp_out; -floo_req_t [4:0] router_31_15_req_out; -floo_rsp_t [4:0] router_31_15_rsp_in; - - assign router_31_15_req_in[0] = router_31_16_to_router_31_15_req; - assign router_31_15_req_in[1] = '0; - assign router_31_15_req_in[2] = router_31_14_to_router_31_15_req; - assign router_31_15_req_in[3] = router_30_15_to_router_31_15_req; - assign router_31_15_req_in[4] = magia_tile_ni_31_15_to_router_31_15_req; - - assign router_31_15_to_router_31_16_rsp = router_31_15_rsp_out[0]; - assign router_31_15_to_router_31_14_rsp = router_31_15_rsp_out[2]; - assign router_31_15_to_router_30_15_rsp = router_31_15_rsp_out[3]; - assign router_31_15_to_magia_tile_ni_31_15_rsp = router_31_15_rsp_out[4]; - - assign router_31_15_to_router_31_16_req = router_31_15_req_out[0]; - assign router_31_15_to_router_31_14_req = router_31_15_req_out[2]; - assign router_31_15_to_router_30_15_req = router_31_15_req_out[3]; - assign router_31_15_to_magia_tile_ni_31_15_req = router_31_15_req_out[4]; - - assign router_31_15_rsp_in[0] = router_31_16_to_router_31_15_rsp; - assign router_31_15_rsp_in[1] = '0; - assign router_31_15_rsp_in[2] = router_31_14_to_router_31_15_rsp; - assign router_31_15_rsp_in[3] = router_30_15_to_router_31_15_rsp; - assign router_31_15_rsp_in[4] = magia_tile_ni_31_15_to_router_31_15_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_15 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 15, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_15_req_in), - .floo_rsp_o (router_31_15_rsp_out), - .floo_req_o (router_31_15_req_out), - .floo_rsp_i (router_31_15_rsp_in) -); - - -floo_req_t [4:0] router_31_16_req_in; -floo_rsp_t [4:0] router_31_16_rsp_out; -floo_req_t [4:0] router_31_16_req_out; -floo_rsp_t [4:0] router_31_16_rsp_in; - - assign router_31_16_req_in[0] = router_31_17_to_router_31_16_req; - assign router_31_16_req_in[1] = '0; - assign router_31_16_req_in[2] = router_31_15_to_router_31_16_req; - assign router_31_16_req_in[3] = router_30_16_to_router_31_16_req; - assign router_31_16_req_in[4] = magia_tile_ni_31_16_to_router_31_16_req; - - assign router_31_16_to_router_31_17_rsp = router_31_16_rsp_out[0]; - assign router_31_16_to_router_31_15_rsp = router_31_16_rsp_out[2]; - assign router_31_16_to_router_30_16_rsp = router_31_16_rsp_out[3]; - assign router_31_16_to_magia_tile_ni_31_16_rsp = router_31_16_rsp_out[4]; - - assign router_31_16_to_router_31_17_req = router_31_16_req_out[0]; - assign router_31_16_to_router_31_15_req = router_31_16_req_out[2]; - assign router_31_16_to_router_30_16_req = router_31_16_req_out[3]; - assign router_31_16_to_magia_tile_ni_31_16_req = router_31_16_req_out[4]; - - assign router_31_16_rsp_in[0] = router_31_17_to_router_31_16_rsp; - assign router_31_16_rsp_in[1] = '0; - assign router_31_16_rsp_in[2] = router_31_15_to_router_31_16_rsp; - assign router_31_16_rsp_in[3] = router_30_16_to_router_31_16_rsp; - assign router_31_16_rsp_in[4] = magia_tile_ni_31_16_to_router_31_16_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_16 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 16, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_16_req_in), - .floo_rsp_o (router_31_16_rsp_out), - .floo_req_o (router_31_16_req_out), - .floo_rsp_i (router_31_16_rsp_in) -); - - -floo_req_t [4:0] router_31_17_req_in; -floo_rsp_t [4:0] router_31_17_rsp_out; -floo_req_t [4:0] router_31_17_req_out; -floo_rsp_t [4:0] router_31_17_rsp_in; - - assign router_31_17_req_in[0] = router_31_18_to_router_31_17_req; - assign router_31_17_req_in[1] = '0; - assign router_31_17_req_in[2] = router_31_16_to_router_31_17_req; - assign router_31_17_req_in[3] = router_30_17_to_router_31_17_req; - assign router_31_17_req_in[4] = magia_tile_ni_31_17_to_router_31_17_req; - - assign router_31_17_to_router_31_18_rsp = router_31_17_rsp_out[0]; - assign router_31_17_to_router_31_16_rsp = router_31_17_rsp_out[2]; - assign router_31_17_to_router_30_17_rsp = router_31_17_rsp_out[3]; - assign router_31_17_to_magia_tile_ni_31_17_rsp = router_31_17_rsp_out[4]; - - assign router_31_17_to_router_31_18_req = router_31_17_req_out[0]; - assign router_31_17_to_router_31_16_req = router_31_17_req_out[2]; - assign router_31_17_to_router_30_17_req = router_31_17_req_out[3]; - assign router_31_17_to_magia_tile_ni_31_17_req = router_31_17_req_out[4]; - - assign router_31_17_rsp_in[0] = router_31_18_to_router_31_17_rsp; - assign router_31_17_rsp_in[1] = '0; - assign router_31_17_rsp_in[2] = router_31_16_to_router_31_17_rsp; - assign router_31_17_rsp_in[3] = router_30_17_to_router_31_17_rsp; - assign router_31_17_rsp_in[4] = magia_tile_ni_31_17_to_router_31_17_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_17 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 17, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_17_req_in), - .floo_rsp_o (router_31_17_rsp_out), - .floo_req_o (router_31_17_req_out), - .floo_rsp_i (router_31_17_rsp_in) -); - - -floo_req_t [4:0] router_31_18_req_in; -floo_rsp_t [4:0] router_31_18_rsp_out; -floo_req_t [4:0] router_31_18_req_out; -floo_rsp_t [4:0] router_31_18_rsp_in; - - assign router_31_18_req_in[0] = router_31_19_to_router_31_18_req; - assign router_31_18_req_in[1] = '0; - assign router_31_18_req_in[2] = router_31_17_to_router_31_18_req; - assign router_31_18_req_in[3] = router_30_18_to_router_31_18_req; - assign router_31_18_req_in[4] = magia_tile_ni_31_18_to_router_31_18_req; - - assign router_31_18_to_router_31_19_rsp = router_31_18_rsp_out[0]; - assign router_31_18_to_router_31_17_rsp = router_31_18_rsp_out[2]; - assign router_31_18_to_router_30_18_rsp = router_31_18_rsp_out[3]; - assign router_31_18_to_magia_tile_ni_31_18_rsp = router_31_18_rsp_out[4]; - - assign router_31_18_to_router_31_19_req = router_31_18_req_out[0]; - assign router_31_18_to_router_31_17_req = router_31_18_req_out[2]; - assign router_31_18_to_router_30_18_req = router_31_18_req_out[3]; - assign router_31_18_to_magia_tile_ni_31_18_req = router_31_18_req_out[4]; - - assign router_31_18_rsp_in[0] = router_31_19_to_router_31_18_rsp; - assign router_31_18_rsp_in[1] = '0; - assign router_31_18_rsp_in[2] = router_31_17_to_router_31_18_rsp; - assign router_31_18_rsp_in[3] = router_30_18_to_router_31_18_rsp; - assign router_31_18_rsp_in[4] = magia_tile_ni_31_18_to_router_31_18_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_18 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 18, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_18_req_in), - .floo_rsp_o (router_31_18_rsp_out), - .floo_req_o (router_31_18_req_out), - .floo_rsp_i (router_31_18_rsp_in) -); - - -floo_req_t [4:0] router_31_19_req_in; -floo_rsp_t [4:0] router_31_19_rsp_out; -floo_req_t [4:0] router_31_19_req_out; -floo_rsp_t [4:0] router_31_19_rsp_in; - - assign router_31_19_req_in[0] = router_31_20_to_router_31_19_req; - assign router_31_19_req_in[1] = '0; - assign router_31_19_req_in[2] = router_31_18_to_router_31_19_req; - assign router_31_19_req_in[3] = router_30_19_to_router_31_19_req; - assign router_31_19_req_in[4] = magia_tile_ni_31_19_to_router_31_19_req; - - assign router_31_19_to_router_31_20_rsp = router_31_19_rsp_out[0]; - assign router_31_19_to_router_31_18_rsp = router_31_19_rsp_out[2]; - assign router_31_19_to_router_30_19_rsp = router_31_19_rsp_out[3]; - assign router_31_19_to_magia_tile_ni_31_19_rsp = router_31_19_rsp_out[4]; - - assign router_31_19_to_router_31_20_req = router_31_19_req_out[0]; - assign router_31_19_to_router_31_18_req = router_31_19_req_out[2]; - assign router_31_19_to_router_30_19_req = router_31_19_req_out[3]; - assign router_31_19_to_magia_tile_ni_31_19_req = router_31_19_req_out[4]; - - assign router_31_19_rsp_in[0] = router_31_20_to_router_31_19_rsp; - assign router_31_19_rsp_in[1] = '0; - assign router_31_19_rsp_in[2] = router_31_18_to_router_31_19_rsp; - assign router_31_19_rsp_in[3] = router_30_19_to_router_31_19_rsp; - assign router_31_19_rsp_in[4] = magia_tile_ni_31_19_to_router_31_19_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_19 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 19, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_19_req_in), - .floo_rsp_o (router_31_19_rsp_out), - .floo_req_o (router_31_19_req_out), - .floo_rsp_i (router_31_19_rsp_in) -); - - -floo_req_t [4:0] router_31_20_req_in; -floo_rsp_t [4:0] router_31_20_rsp_out; -floo_req_t [4:0] router_31_20_req_out; -floo_rsp_t [4:0] router_31_20_rsp_in; - - assign router_31_20_req_in[0] = router_31_21_to_router_31_20_req; - assign router_31_20_req_in[1] = '0; - assign router_31_20_req_in[2] = router_31_19_to_router_31_20_req; - assign router_31_20_req_in[3] = router_30_20_to_router_31_20_req; - assign router_31_20_req_in[4] = magia_tile_ni_31_20_to_router_31_20_req; - - assign router_31_20_to_router_31_21_rsp = router_31_20_rsp_out[0]; - assign router_31_20_to_router_31_19_rsp = router_31_20_rsp_out[2]; - assign router_31_20_to_router_30_20_rsp = router_31_20_rsp_out[3]; - assign router_31_20_to_magia_tile_ni_31_20_rsp = router_31_20_rsp_out[4]; - - assign router_31_20_to_router_31_21_req = router_31_20_req_out[0]; - assign router_31_20_to_router_31_19_req = router_31_20_req_out[2]; - assign router_31_20_to_router_30_20_req = router_31_20_req_out[3]; - assign router_31_20_to_magia_tile_ni_31_20_req = router_31_20_req_out[4]; - - assign router_31_20_rsp_in[0] = router_31_21_to_router_31_20_rsp; - assign router_31_20_rsp_in[1] = '0; - assign router_31_20_rsp_in[2] = router_31_19_to_router_31_20_rsp; - assign router_31_20_rsp_in[3] = router_30_20_to_router_31_20_rsp; - assign router_31_20_rsp_in[4] = magia_tile_ni_31_20_to_router_31_20_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_20 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 20, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_20_req_in), - .floo_rsp_o (router_31_20_rsp_out), - .floo_req_o (router_31_20_req_out), - .floo_rsp_i (router_31_20_rsp_in) -); - - -floo_req_t [4:0] router_31_21_req_in; -floo_rsp_t [4:0] router_31_21_rsp_out; -floo_req_t [4:0] router_31_21_req_out; -floo_rsp_t [4:0] router_31_21_rsp_in; - - assign router_31_21_req_in[0] = router_31_22_to_router_31_21_req; - assign router_31_21_req_in[1] = '0; - assign router_31_21_req_in[2] = router_31_20_to_router_31_21_req; - assign router_31_21_req_in[3] = router_30_21_to_router_31_21_req; - assign router_31_21_req_in[4] = magia_tile_ni_31_21_to_router_31_21_req; - - assign router_31_21_to_router_31_22_rsp = router_31_21_rsp_out[0]; - assign router_31_21_to_router_31_20_rsp = router_31_21_rsp_out[2]; - assign router_31_21_to_router_30_21_rsp = router_31_21_rsp_out[3]; - assign router_31_21_to_magia_tile_ni_31_21_rsp = router_31_21_rsp_out[4]; - - assign router_31_21_to_router_31_22_req = router_31_21_req_out[0]; - assign router_31_21_to_router_31_20_req = router_31_21_req_out[2]; - assign router_31_21_to_router_30_21_req = router_31_21_req_out[3]; - assign router_31_21_to_magia_tile_ni_31_21_req = router_31_21_req_out[4]; - - assign router_31_21_rsp_in[0] = router_31_22_to_router_31_21_rsp; - assign router_31_21_rsp_in[1] = '0; - assign router_31_21_rsp_in[2] = router_31_20_to_router_31_21_rsp; - assign router_31_21_rsp_in[3] = router_30_21_to_router_31_21_rsp; - assign router_31_21_rsp_in[4] = magia_tile_ni_31_21_to_router_31_21_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_21 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 21, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_21_req_in), - .floo_rsp_o (router_31_21_rsp_out), - .floo_req_o (router_31_21_req_out), - .floo_rsp_i (router_31_21_rsp_in) -); - - -floo_req_t [4:0] router_31_22_req_in; -floo_rsp_t [4:0] router_31_22_rsp_out; -floo_req_t [4:0] router_31_22_req_out; -floo_rsp_t [4:0] router_31_22_rsp_in; - - assign router_31_22_req_in[0] = router_31_23_to_router_31_22_req; - assign router_31_22_req_in[1] = '0; - assign router_31_22_req_in[2] = router_31_21_to_router_31_22_req; - assign router_31_22_req_in[3] = router_30_22_to_router_31_22_req; - assign router_31_22_req_in[4] = magia_tile_ni_31_22_to_router_31_22_req; - - assign router_31_22_to_router_31_23_rsp = router_31_22_rsp_out[0]; - assign router_31_22_to_router_31_21_rsp = router_31_22_rsp_out[2]; - assign router_31_22_to_router_30_22_rsp = router_31_22_rsp_out[3]; - assign router_31_22_to_magia_tile_ni_31_22_rsp = router_31_22_rsp_out[4]; - - assign router_31_22_to_router_31_23_req = router_31_22_req_out[0]; - assign router_31_22_to_router_31_21_req = router_31_22_req_out[2]; - assign router_31_22_to_router_30_22_req = router_31_22_req_out[3]; - assign router_31_22_to_magia_tile_ni_31_22_req = router_31_22_req_out[4]; - - assign router_31_22_rsp_in[0] = router_31_23_to_router_31_22_rsp; - assign router_31_22_rsp_in[1] = '0; - assign router_31_22_rsp_in[2] = router_31_21_to_router_31_22_rsp; - assign router_31_22_rsp_in[3] = router_30_22_to_router_31_22_rsp; - assign router_31_22_rsp_in[4] = magia_tile_ni_31_22_to_router_31_22_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_22 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 22, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_22_req_in), - .floo_rsp_o (router_31_22_rsp_out), - .floo_req_o (router_31_22_req_out), - .floo_rsp_i (router_31_22_rsp_in) -); - - -floo_req_t [4:0] router_31_23_req_in; -floo_rsp_t [4:0] router_31_23_rsp_out; -floo_req_t [4:0] router_31_23_req_out; -floo_rsp_t [4:0] router_31_23_rsp_in; - - assign router_31_23_req_in[0] = router_31_24_to_router_31_23_req; - assign router_31_23_req_in[1] = '0; - assign router_31_23_req_in[2] = router_31_22_to_router_31_23_req; - assign router_31_23_req_in[3] = router_30_23_to_router_31_23_req; - assign router_31_23_req_in[4] = magia_tile_ni_31_23_to_router_31_23_req; - - assign router_31_23_to_router_31_24_rsp = router_31_23_rsp_out[0]; - assign router_31_23_to_router_31_22_rsp = router_31_23_rsp_out[2]; - assign router_31_23_to_router_30_23_rsp = router_31_23_rsp_out[3]; - assign router_31_23_to_magia_tile_ni_31_23_rsp = router_31_23_rsp_out[4]; - - assign router_31_23_to_router_31_24_req = router_31_23_req_out[0]; - assign router_31_23_to_router_31_22_req = router_31_23_req_out[2]; - assign router_31_23_to_router_30_23_req = router_31_23_req_out[3]; - assign router_31_23_to_magia_tile_ni_31_23_req = router_31_23_req_out[4]; - - assign router_31_23_rsp_in[0] = router_31_24_to_router_31_23_rsp; - assign router_31_23_rsp_in[1] = '0; - assign router_31_23_rsp_in[2] = router_31_22_to_router_31_23_rsp; - assign router_31_23_rsp_in[3] = router_30_23_to_router_31_23_rsp; - assign router_31_23_rsp_in[4] = magia_tile_ni_31_23_to_router_31_23_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_23 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 23, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_23_req_in), - .floo_rsp_o (router_31_23_rsp_out), - .floo_req_o (router_31_23_req_out), - .floo_rsp_i (router_31_23_rsp_in) -); - - -floo_req_t [4:0] router_31_24_req_in; -floo_rsp_t [4:0] router_31_24_rsp_out; -floo_req_t [4:0] router_31_24_req_out; -floo_rsp_t [4:0] router_31_24_rsp_in; - - assign router_31_24_req_in[0] = router_31_25_to_router_31_24_req; - assign router_31_24_req_in[1] = '0; - assign router_31_24_req_in[2] = router_31_23_to_router_31_24_req; - assign router_31_24_req_in[3] = router_30_24_to_router_31_24_req; - assign router_31_24_req_in[4] = magia_tile_ni_31_24_to_router_31_24_req; - - assign router_31_24_to_router_31_25_rsp = router_31_24_rsp_out[0]; - assign router_31_24_to_router_31_23_rsp = router_31_24_rsp_out[2]; - assign router_31_24_to_router_30_24_rsp = router_31_24_rsp_out[3]; - assign router_31_24_to_magia_tile_ni_31_24_rsp = router_31_24_rsp_out[4]; - - assign router_31_24_to_router_31_25_req = router_31_24_req_out[0]; - assign router_31_24_to_router_31_23_req = router_31_24_req_out[2]; - assign router_31_24_to_router_30_24_req = router_31_24_req_out[3]; - assign router_31_24_to_magia_tile_ni_31_24_req = router_31_24_req_out[4]; - - assign router_31_24_rsp_in[0] = router_31_25_to_router_31_24_rsp; - assign router_31_24_rsp_in[1] = '0; - assign router_31_24_rsp_in[2] = router_31_23_to_router_31_24_rsp; - assign router_31_24_rsp_in[3] = router_30_24_to_router_31_24_rsp; - assign router_31_24_rsp_in[4] = magia_tile_ni_31_24_to_router_31_24_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_24 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 24, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_24_req_in), - .floo_rsp_o (router_31_24_rsp_out), - .floo_req_o (router_31_24_req_out), - .floo_rsp_i (router_31_24_rsp_in) -); - - -floo_req_t [4:0] router_31_25_req_in; -floo_rsp_t [4:0] router_31_25_rsp_out; -floo_req_t [4:0] router_31_25_req_out; -floo_rsp_t [4:0] router_31_25_rsp_in; - - assign router_31_25_req_in[0] = router_31_26_to_router_31_25_req; - assign router_31_25_req_in[1] = '0; - assign router_31_25_req_in[2] = router_31_24_to_router_31_25_req; - assign router_31_25_req_in[3] = router_30_25_to_router_31_25_req; - assign router_31_25_req_in[4] = magia_tile_ni_31_25_to_router_31_25_req; - - assign router_31_25_to_router_31_26_rsp = router_31_25_rsp_out[0]; - assign router_31_25_to_router_31_24_rsp = router_31_25_rsp_out[2]; - assign router_31_25_to_router_30_25_rsp = router_31_25_rsp_out[3]; - assign router_31_25_to_magia_tile_ni_31_25_rsp = router_31_25_rsp_out[4]; - - assign router_31_25_to_router_31_26_req = router_31_25_req_out[0]; - assign router_31_25_to_router_31_24_req = router_31_25_req_out[2]; - assign router_31_25_to_router_30_25_req = router_31_25_req_out[3]; - assign router_31_25_to_magia_tile_ni_31_25_req = router_31_25_req_out[4]; - - assign router_31_25_rsp_in[0] = router_31_26_to_router_31_25_rsp; - assign router_31_25_rsp_in[1] = '0; - assign router_31_25_rsp_in[2] = router_31_24_to_router_31_25_rsp; - assign router_31_25_rsp_in[3] = router_30_25_to_router_31_25_rsp; - assign router_31_25_rsp_in[4] = magia_tile_ni_31_25_to_router_31_25_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_25 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 25, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_25_req_in), - .floo_rsp_o (router_31_25_rsp_out), - .floo_req_o (router_31_25_req_out), - .floo_rsp_i (router_31_25_rsp_in) -); - - -floo_req_t [4:0] router_31_26_req_in; -floo_rsp_t [4:0] router_31_26_rsp_out; -floo_req_t [4:0] router_31_26_req_out; -floo_rsp_t [4:0] router_31_26_rsp_in; - - assign router_31_26_req_in[0] = router_31_27_to_router_31_26_req; - assign router_31_26_req_in[1] = '0; - assign router_31_26_req_in[2] = router_31_25_to_router_31_26_req; - assign router_31_26_req_in[3] = router_30_26_to_router_31_26_req; - assign router_31_26_req_in[4] = magia_tile_ni_31_26_to_router_31_26_req; - - assign router_31_26_to_router_31_27_rsp = router_31_26_rsp_out[0]; - assign router_31_26_to_router_31_25_rsp = router_31_26_rsp_out[2]; - assign router_31_26_to_router_30_26_rsp = router_31_26_rsp_out[3]; - assign router_31_26_to_magia_tile_ni_31_26_rsp = router_31_26_rsp_out[4]; - - assign router_31_26_to_router_31_27_req = router_31_26_req_out[0]; - assign router_31_26_to_router_31_25_req = router_31_26_req_out[2]; - assign router_31_26_to_router_30_26_req = router_31_26_req_out[3]; - assign router_31_26_to_magia_tile_ni_31_26_req = router_31_26_req_out[4]; - - assign router_31_26_rsp_in[0] = router_31_27_to_router_31_26_rsp; - assign router_31_26_rsp_in[1] = '0; - assign router_31_26_rsp_in[2] = router_31_25_to_router_31_26_rsp; - assign router_31_26_rsp_in[3] = router_30_26_to_router_31_26_rsp; - assign router_31_26_rsp_in[4] = magia_tile_ni_31_26_to_router_31_26_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_26 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 26, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_26_req_in), - .floo_rsp_o (router_31_26_rsp_out), - .floo_req_o (router_31_26_req_out), - .floo_rsp_i (router_31_26_rsp_in) -); - - -floo_req_t [4:0] router_31_27_req_in; -floo_rsp_t [4:0] router_31_27_rsp_out; -floo_req_t [4:0] router_31_27_req_out; -floo_rsp_t [4:0] router_31_27_rsp_in; - - assign router_31_27_req_in[0] = router_31_28_to_router_31_27_req; - assign router_31_27_req_in[1] = '0; - assign router_31_27_req_in[2] = router_31_26_to_router_31_27_req; - assign router_31_27_req_in[3] = router_30_27_to_router_31_27_req; - assign router_31_27_req_in[4] = magia_tile_ni_31_27_to_router_31_27_req; - - assign router_31_27_to_router_31_28_rsp = router_31_27_rsp_out[0]; - assign router_31_27_to_router_31_26_rsp = router_31_27_rsp_out[2]; - assign router_31_27_to_router_30_27_rsp = router_31_27_rsp_out[3]; - assign router_31_27_to_magia_tile_ni_31_27_rsp = router_31_27_rsp_out[4]; - - assign router_31_27_to_router_31_28_req = router_31_27_req_out[0]; - assign router_31_27_to_router_31_26_req = router_31_27_req_out[2]; - assign router_31_27_to_router_30_27_req = router_31_27_req_out[3]; - assign router_31_27_to_magia_tile_ni_31_27_req = router_31_27_req_out[4]; - - assign router_31_27_rsp_in[0] = router_31_28_to_router_31_27_rsp; - assign router_31_27_rsp_in[1] = '0; - assign router_31_27_rsp_in[2] = router_31_26_to_router_31_27_rsp; - assign router_31_27_rsp_in[3] = router_30_27_to_router_31_27_rsp; - assign router_31_27_rsp_in[4] = magia_tile_ni_31_27_to_router_31_27_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_27 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 27, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_27_req_in), - .floo_rsp_o (router_31_27_rsp_out), - .floo_req_o (router_31_27_req_out), - .floo_rsp_i (router_31_27_rsp_in) -); - - -floo_req_t [4:0] router_31_28_req_in; -floo_rsp_t [4:0] router_31_28_rsp_out; -floo_req_t [4:0] router_31_28_req_out; -floo_rsp_t [4:0] router_31_28_rsp_in; - - assign router_31_28_req_in[0] = router_31_29_to_router_31_28_req; - assign router_31_28_req_in[1] = '0; - assign router_31_28_req_in[2] = router_31_27_to_router_31_28_req; - assign router_31_28_req_in[3] = router_30_28_to_router_31_28_req; - assign router_31_28_req_in[4] = magia_tile_ni_31_28_to_router_31_28_req; - - assign router_31_28_to_router_31_29_rsp = router_31_28_rsp_out[0]; - assign router_31_28_to_router_31_27_rsp = router_31_28_rsp_out[2]; - assign router_31_28_to_router_30_28_rsp = router_31_28_rsp_out[3]; - assign router_31_28_to_magia_tile_ni_31_28_rsp = router_31_28_rsp_out[4]; - - assign router_31_28_to_router_31_29_req = router_31_28_req_out[0]; - assign router_31_28_to_router_31_27_req = router_31_28_req_out[2]; - assign router_31_28_to_router_30_28_req = router_31_28_req_out[3]; - assign router_31_28_to_magia_tile_ni_31_28_req = router_31_28_req_out[4]; - - assign router_31_28_rsp_in[0] = router_31_29_to_router_31_28_rsp; - assign router_31_28_rsp_in[1] = '0; - assign router_31_28_rsp_in[2] = router_31_27_to_router_31_28_rsp; - assign router_31_28_rsp_in[3] = router_30_28_to_router_31_28_rsp; - assign router_31_28_rsp_in[4] = magia_tile_ni_31_28_to_router_31_28_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_28 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 28, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_28_req_in), - .floo_rsp_o (router_31_28_rsp_out), - .floo_req_o (router_31_28_req_out), - .floo_rsp_i (router_31_28_rsp_in) -); - - -floo_req_t [4:0] router_31_29_req_in; -floo_rsp_t [4:0] router_31_29_rsp_out; -floo_req_t [4:0] router_31_29_req_out; -floo_rsp_t [4:0] router_31_29_rsp_in; - - assign router_31_29_req_in[0] = router_31_30_to_router_31_29_req; - assign router_31_29_req_in[1] = '0; - assign router_31_29_req_in[2] = router_31_28_to_router_31_29_req; - assign router_31_29_req_in[3] = router_30_29_to_router_31_29_req; - assign router_31_29_req_in[4] = magia_tile_ni_31_29_to_router_31_29_req; - - assign router_31_29_to_router_31_30_rsp = router_31_29_rsp_out[0]; - assign router_31_29_to_router_31_28_rsp = router_31_29_rsp_out[2]; - assign router_31_29_to_router_30_29_rsp = router_31_29_rsp_out[3]; - assign router_31_29_to_magia_tile_ni_31_29_rsp = router_31_29_rsp_out[4]; - - assign router_31_29_to_router_31_30_req = router_31_29_req_out[0]; - assign router_31_29_to_router_31_28_req = router_31_29_req_out[2]; - assign router_31_29_to_router_30_29_req = router_31_29_req_out[3]; - assign router_31_29_to_magia_tile_ni_31_29_req = router_31_29_req_out[4]; - - assign router_31_29_rsp_in[0] = router_31_30_to_router_31_29_rsp; - assign router_31_29_rsp_in[1] = '0; - assign router_31_29_rsp_in[2] = router_31_28_to_router_31_29_rsp; - assign router_31_29_rsp_in[3] = router_30_29_to_router_31_29_rsp; - assign router_31_29_rsp_in[4] = magia_tile_ni_31_29_to_router_31_29_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_29 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 29, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_29_req_in), - .floo_rsp_o (router_31_29_rsp_out), - .floo_req_o (router_31_29_req_out), - .floo_rsp_i (router_31_29_rsp_in) -); - - -floo_req_t [4:0] router_31_30_req_in; -floo_rsp_t [4:0] router_31_30_rsp_out; -floo_req_t [4:0] router_31_30_req_out; -floo_rsp_t [4:0] router_31_30_rsp_in; - - assign router_31_30_req_in[0] = router_31_31_to_router_31_30_req; - assign router_31_30_req_in[1] = '0; - assign router_31_30_req_in[2] = router_31_29_to_router_31_30_req; - assign router_31_30_req_in[3] = router_30_30_to_router_31_30_req; - assign router_31_30_req_in[4] = magia_tile_ni_31_30_to_router_31_30_req; - - assign router_31_30_to_router_31_31_rsp = router_31_30_rsp_out[0]; - assign router_31_30_to_router_31_29_rsp = router_31_30_rsp_out[2]; - assign router_31_30_to_router_30_30_rsp = router_31_30_rsp_out[3]; - assign router_31_30_to_magia_tile_ni_31_30_rsp = router_31_30_rsp_out[4]; - - assign router_31_30_to_router_31_31_req = router_31_30_req_out[0]; - assign router_31_30_to_router_31_29_req = router_31_30_req_out[2]; - assign router_31_30_to_router_30_30_req = router_31_30_req_out[3]; - assign router_31_30_to_magia_tile_ni_31_30_req = router_31_30_req_out[4]; - - assign router_31_30_rsp_in[0] = router_31_31_to_router_31_30_rsp; - assign router_31_30_rsp_in[1] = '0; - assign router_31_30_rsp_in[2] = router_31_29_to_router_31_30_rsp; - assign router_31_30_rsp_in[3] = router_30_30_to_router_31_30_rsp; - assign router_31_30_rsp_in[4] = magia_tile_ni_31_30_to_router_31_30_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_30 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 30, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_30_req_in), - .floo_rsp_o (router_31_30_rsp_out), - .floo_req_o (router_31_30_req_out), - .floo_rsp_i (router_31_30_rsp_in) -); - - -floo_req_t [4:0] router_31_31_req_in; -floo_rsp_t [4:0] router_31_31_rsp_out; -floo_req_t [4:0] router_31_31_req_out; -floo_rsp_t [4:0] router_31_31_rsp_in; - - assign router_31_31_req_in[0] = '0; - assign router_31_31_req_in[1] = '0; - assign router_31_31_req_in[2] = router_31_30_to_router_31_31_req; - assign router_31_31_req_in[3] = router_30_31_to_router_31_31_req; - assign router_31_31_req_in[4] = magia_tile_ni_31_31_to_router_31_31_req; - - assign router_31_31_to_router_31_30_rsp = router_31_31_rsp_out[2]; - assign router_31_31_to_router_30_31_rsp = router_31_31_rsp_out[3]; - assign router_31_31_to_magia_tile_ni_31_31_rsp = router_31_31_rsp_out[4]; - - assign router_31_31_to_router_31_30_req = router_31_31_req_out[2]; - assign router_31_31_to_router_30_31_req = router_31_31_req_out[3]; - assign router_31_31_to_magia_tile_ni_31_31_req = router_31_31_req_out[4]; - - assign router_31_31_rsp_in[0] = '0; - assign router_31_31_rsp_in[1] = '0; - assign router_31_31_rsp_in[2] = router_31_30_to_router_31_31_rsp; - assign router_31_31_rsp_in[3] = router_30_31_to_router_31_31_rsp; - assign router_31_31_rsp_in[4] = magia_tile_ni_31_31_to_router_31_31_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_31_31 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 32, y: 31, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_31_31_req_in), - .floo_rsp_o (router_31_31_rsp_out), - .floo_req_o (router_31_31_req_out), - .floo_rsp_i (router_31_31_rsp_in) -); - - - -endmodule diff --git a/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv b/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv index 027159b..38b4156 100644 --- a/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv +++ b/hw/mesh/noc/floo_axi_mesh_4x4_noc.sv @@ -125,1769 +125,3 @@ typedef logic[0:0] axi_data_slv_user_t; endpackage - -module floo_axi_mesh_4x4_noc - import floo_pkg::*; - import floo_axi_mesh_4x4_noc_pkg::*; -( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input axi_data_slv_req_t [3:0][3:0] magia_tile_data_slv_req_i, - output axi_data_slv_rsp_t [3:0][3:0] magia_tile_data_slv_rsp_o, - output axi_data_mst_req_t [3:0][3:0] magia_tile_data_mst_req_o, - input axi_data_mst_rsp_t [3:0][3:0] magia_tile_data_mst_rsp_i, - output axi_data_mst_req_t [3:0] L2_data_mst_req_o, - input axi_data_mst_rsp_t [3:0] L2_data_mst_rsp_i - -); - -floo_req_t router_0_0_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_0_rsp; - -floo_req_t router_0_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_magia_tile_ni_0_0_req; -floo_rsp_t magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_L2_ni_0_req; -floo_rsp_t L2_ni_0_to_router_0_0_rsp; - -floo_req_t router_0_1_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_magia_tile_ni_0_1_req; -floo_rsp_t magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_L2_ni_1_req; -floo_rsp_t L2_ni_1_to_router_0_1_rsp; - -floo_req_t router_0_2_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_magia_tile_ni_0_2_req; -floo_rsp_t magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_L2_ni_2_req; -floo_rsp_t L2_ni_2_to_router_0_2_rsp; - -floo_req_t router_0_3_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_magia_tile_ni_0_3_req; -floo_rsp_t magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_L2_ni_3_req; -floo_rsp_t L2_ni_3_to_router_0_3_rsp; - -floo_req_t router_1_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_magia_tile_ni_1_0_req; -floo_rsp_t magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_req_t router_1_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_magia_tile_ni_1_1_req; -floo_rsp_t magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_req_t router_1_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_magia_tile_ni_1_2_req; -floo_rsp_t magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_req_t router_1_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_magia_tile_ni_1_3_req; -floo_rsp_t magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_req_t router_2_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_magia_tile_ni_2_0_req; -floo_rsp_t magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_req_t router_2_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_magia_tile_ni_2_1_req; -floo_rsp_t magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_req_t router_2_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_magia_tile_ni_2_2_req; -floo_rsp_t magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_req_t router_2_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_magia_tile_ni_2_3_req; -floo_rsp_t magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_req_t router_3_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_0_rsp; - -floo_req_t router_3_0_to_magia_tile_ni_3_0_req; -floo_rsp_t magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_req_t router_3_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_1_rsp; - -floo_req_t router_3_1_to_magia_tile_ni_3_1_req; -floo_rsp_t magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_req_t router_3_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_2_rsp; - -floo_req_t router_3_2_to_magia_tile_ni_3_2_req; -floo_rsp_t magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_req_t router_3_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_3_rsp; - -floo_req_t router_3_3_to_magia_tile_ni_3_3_req; -floo_rsp_t magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_req_t magia_tile_ni_0_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_magia_tile_ni_0_0_rsp; - -floo_req_t magia_tile_ni_0_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_magia_tile_ni_0_1_rsp; - -floo_req_t magia_tile_ni_0_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_magia_tile_ni_0_2_rsp; - -floo_req_t magia_tile_ni_0_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_magia_tile_ni_0_3_rsp; - -floo_req_t magia_tile_ni_1_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_magia_tile_ni_1_0_rsp; - -floo_req_t magia_tile_ni_1_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_magia_tile_ni_1_1_rsp; - -floo_req_t magia_tile_ni_1_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_magia_tile_ni_1_2_rsp; - -floo_req_t magia_tile_ni_1_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_magia_tile_ni_1_3_rsp; - -floo_req_t magia_tile_ni_2_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_magia_tile_ni_2_0_rsp; - -floo_req_t magia_tile_ni_2_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_magia_tile_ni_2_1_rsp; - -floo_req_t magia_tile_ni_2_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_magia_tile_ni_2_2_rsp; - -floo_req_t magia_tile_ni_2_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_magia_tile_ni_2_3_rsp; - -floo_req_t magia_tile_ni_3_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_magia_tile_ni_3_0_rsp; - -floo_req_t magia_tile_ni_3_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_magia_tile_ni_3_1_rsp; - -floo_req_t magia_tile_ni_3_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_magia_tile_ni_3_2_rsp; - -floo_req_t magia_tile_ni_3_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_magia_tile_ni_3_3_rsp; - -floo_req_t L2_ni_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_L2_ni_0_rsp; - -floo_req_t L2_ni_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_L2_ni_1_rsp; - -floo_req_t L2_ni_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_L2_ni_2_rsp; - -floo_req_t L2_ni_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_L2_ni_3_rsp; - - - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][0] ), - .id_i ( '{x: 1, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_magia_tile_ni_0_0_rsp ), - .floo_req_i ( router_0_0_to_magia_tile_ni_0_0_req ), - .floo_rsp_o ( magia_tile_ni_0_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][1] ), - .id_i ( '{x: 1, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_magia_tile_ni_0_1_rsp ), - .floo_req_i ( router_0_1_to_magia_tile_ni_0_1_req ), - .floo_rsp_o ( magia_tile_ni_0_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][2] ), - .id_i ( '{x: 1, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_magia_tile_ni_0_2_rsp ), - .floo_req_i ( router_0_2_to_magia_tile_ni_0_2_req ), - .floo_rsp_o ( magia_tile_ni_0_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][3] ), - .id_i ( '{x: 1, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_magia_tile_ni_0_3_rsp ), - .floo_req_i ( router_0_3_to_magia_tile_ni_0_3_req ), - .floo_rsp_o ( magia_tile_ni_0_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][0] ), - .id_i ( '{x: 2, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_0_to_router_1_0_req ), - .floo_rsp_i ( router_1_0_to_magia_tile_ni_1_0_rsp ), - .floo_req_i ( router_1_0_to_magia_tile_ni_1_0_req ), - .floo_rsp_o ( magia_tile_ni_1_0_to_router_1_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][1] ), - .id_i ( '{x: 2, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_1_to_router_1_1_req ), - .floo_rsp_i ( router_1_1_to_magia_tile_ni_1_1_rsp ), - .floo_req_i ( router_1_1_to_magia_tile_ni_1_1_req ), - .floo_rsp_o ( magia_tile_ni_1_1_to_router_1_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][2] ), - .id_i ( '{x: 2, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_2_to_router_1_2_req ), - .floo_rsp_i ( router_1_2_to_magia_tile_ni_1_2_rsp ), - .floo_req_i ( router_1_2_to_magia_tile_ni_1_2_req ), - .floo_rsp_o ( magia_tile_ni_1_2_to_router_1_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][3] ), - .id_i ( '{x: 2, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_3_to_router_1_3_req ), - .floo_rsp_i ( router_1_3_to_magia_tile_ni_1_3_rsp ), - .floo_req_i ( router_1_3_to_magia_tile_ni_1_3_req ), - .floo_rsp_o ( magia_tile_ni_1_3_to_router_1_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][0] ), - .id_i ( '{x: 3, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_0_to_router_2_0_req ), - .floo_rsp_i ( router_2_0_to_magia_tile_ni_2_0_rsp ), - .floo_req_i ( router_2_0_to_magia_tile_ni_2_0_req ), - .floo_rsp_o ( magia_tile_ni_2_0_to_router_2_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][1] ), - .id_i ( '{x: 3, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_1_to_router_2_1_req ), - .floo_rsp_i ( router_2_1_to_magia_tile_ni_2_1_rsp ), - .floo_req_i ( router_2_1_to_magia_tile_ni_2_1_req ), - .floo_rsp_o ( magia_tile_ni_2_1_to_router_2_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][2] ), - .id_i ( '{x: 3, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_2_to_router_2_2_req ), - .floo_rsp_i ( router_2_2_to_magia_tile_ni_2_2_rsp ), - .floo_req_i ( router_2_2_to_magia_tile_ni_2_2_req ), - .floo_rsp_o ( magia_tile_ni_2_2_to_router_2_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][3] ), - .id_i ( '{x: 3, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_3_to_router_2_3_req ), - .floo_rsp_i ( router_2_3_to_magia_tile_ni_2_3_rsp ), - .floo_req_i ( router_2_3_to_magia_tile_ni_2_3_req ), - .floo_rsp_o ( magia_tile_ni_2_3_to_router_2_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][0] ), - .id_i ( '{x: 4, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_0_to_router_3_0_req ), - .floo_rsp_i ( router_3_0_to_magia_tile_ni_3_0_rsp ), - .floo_req_i ( router_3_0_to_magia_tile_ni_3_0_req ), - .floo_rsp_o ( magia_tile_ni_3_0_to_router_3_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][1] ), - .id_i ( '{x: 4, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_1_to_router_3_1_req ), - .floo_rsp_i ( router_3_1_to_magia_tile_ni_3_1_rsp ), - .floo_req_i ( router_3_1_to_magia_tile_ni_3_1_req ), - .floo_rsp_o ( magia_tile_ni_3_1_to_router_3_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][2] ), - .id_i ( '{x: 4, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_2_to_router_3_2_req ), - .floo_rsp_i ( router_3_2_to_magia_tile_ni_3_2_rsp ), - .floo_req_i ( router_3_2_to_magia_tile_ni_3_2_req ), - .floo_rsp_o ( magia_tile_ni_3_2_to_router_3_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][3] ), - .id_i ( '{x: 4, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_3_to_router_3_3_req ), - .floo_rsp_i ( router_3_3_to_magia_tile_ni_3_3_rsp ), - .floo_req_i ( router_3_3_to_magia_tile_ni_3_3_req ), - .floo_rsp_o ( magia_tile_ni_3_3_to_router_3_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[0] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[0] ), - .id_i ( '{x: 0, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_L2_ni_0_rsp ), - .floo_req_i ( router_0_0_to_L2_ni_0_req ), - .floo_rsp_o ( L2_ni_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[1] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[1] ), - .id_i ( '{x: 0, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_L2_ni_1_rsp ), - .floo_req_i ( router_0_1_to_L2_ni_1_req ), - .floo_rsp_o ( L2_ni_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[2] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[2] ), - .id_i ( '{x: 0, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_L2_ni_2_rsp ), - .floo_req_i ( router_0_2_to_L2_ni_2_req ), - .floo_rsp_o ( L2_ni_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[3] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[3] ), - .id_i ( '{x: 0, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_L2_ni_3_rsp ), - .floo_req_i ( router_0_3_to_L2_ni_3_req ), - .floo_rsp_o ( L2_ni_3_to_router_0_3_rsp ) -); - - -floo_req_t [4:0] router_0_0_req_in; -floo_rsp_t [4:0] router_0_0_rsp_out; -floo_req_t [4:0] router_0_0_req_out; -floo_rsp_t [4:0] router_0_0_rsp_in; - - assign router_0_0_req_in[0] = router_0_1_to_router_0_0_req; - assign router_0_0_req_in[1] = router_1_0_to_router_0_0_req; - assign router_0_0_req_in[2] = '0; - assign router_0_0_req_in[3] = L2_ni_0_to_router_0_0_req; - assign router_0_0_req_in[4] = magia_tile_ni_0_0_to_router_0_0_req; - - assign router_0_0_to_router_0_1_rsp = router_0_0_rsp_out[0]; - assign router_0_0_to_router_1_0_rsp = router_0_0_rsp_out[1]; - assign router_0_0_to_L2_ni_0_rsp = router_0_0_rsp_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_rsp = router_0_0_rsp_out[4]; - - assign router_0_0_to_router_0_1_req = router_0_0_req_out[0]; - assign router_0_0_to_router_1_0_req = router_0_0_req_out[1]; - assign router_0_0_to_L2_ni_0_req = router_0_0_req_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_req = router_0_0_req_out[4]; - - assign router_0_0_rsp_in[0] = router_0_1_to_router_0_0_rsp; - assign router_0_0_rsp_in[1] = router_1_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[2] = '0; - assign router_0_0_rsp_in[3] = L2_ni_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[4] = magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_0_req_in), - .floo_rsp_o (router_0_0_rsp_out), - .floo_req_o (router_0_0_req_out), - .floo_rsp_i (router_0_0_rsp_in) -); - - -floo_req_t [4:0] router_0_1_req_in; -floo_rsp_t [4:0] router_0_1_rsp_out; -floo_req_t [4:0] router_0_1_req_out; -floo_rsp_t [4:0] router_0_1_rsp_in; - - assign router_0_1_req_in[0] = router_0_2_to_router_0_1_req; - assign router_0_1_req_in[1] = router_1_1_to_router_0_1_req; - assign router_0_1_req_in[2] = router_0_0_to_router_0_1_req; - assign router_0_1_req_in[3] = L2_ni_1_to_router_0_1_req; - assign router_0_1_req_in[4] = magia_tile_ni_0_1_to_router_0_1_req; - - assign router_0_1_to_router_0_2_rsp = router_0_1_rsp_out[0]; - assign router_0_1_to_router_1_1_rsp = router_0_1_rsp_out[1]; - assign router_0_1_to_router_0_0_rsp = router_0_1_rsp_out[2]; - assign router_0_1_to_L2_ni_1_rsp = router_0_1_rsp_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_rsp = router_0_1_rsp_out[4]; - - assign router_0_1_to_router_0_2_req = router_0_1_req_out[0]; - assign router_0_1_to_router_1_1_req = router_0_1_req_out[1]; - assign router_0_1_to_router_0_0_req = router_0_1_req_out[2]; - assign router_0_1_to_L2_ni_1_req = router_0_1_req_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_req = router_0_1_req_out[4]; - - assign router_0_1_rsp_in[0] = router_0_2_to_router_0_1_rsp; - assign router_0_1_rsp_in[1] = router_1_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[2] = router_0_0_to_router_0_1_rsp; - assign router_0_1_rsp_in[3] = L2_ni_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[4] = magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_1_req_in), - .floo_rsp_o (router_0_1_rsp_out), - .floo_req_o (router_0_1_req_out), - .floo_rsp_i (router_0_1_rsp_in) -); - - -floo_req_t [4:0] router_0_2_req_in; -floo_rsp_t [4:0] router_0_2_rsp_out; -floo_req_t [4:0] router_0_2_req_out; -floo_rsp_t [4:0] router_0_2_rsp_in; - - assign router_0_2_req_in[0] = router_0_3_to_router_0_2_req; - assign router_0_2_req_in[1] = router_1_2_to_router_0_2_req; - assign router_0_2_req_in[2] = router_0_1_to_router_0_2_req; - assign router_0_2_req_in[3] = L2_ni_2_to_router_0_2_req; - assign router_0_2_req_in[4] = magia_tile_ni_0_2_to_router_0_2_req; - - assign router_0_2_to_router_0_3_rsp = router_0_2_rsp_out[0]; - assign router_0_2_to_router_1_2_rsp = router_0_2_rsp_out[1]; - assign router_0_2_to_router_0_1_rsp = router_0_2_rsp_out[2]; - assign router_0_2_to_L2_ni_2_rsp = router_0_2_rsp_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_rsp = router_0_2_rsp_out[4]; - - assign router_0_2_to_router_0_3_req = router_0_2_req_out[0]; - assign router_0_2_to_router_1_2_req = router_0_2_req_out[1]; - assign router_0_2_to_router_0_1_req = router_0_2_req_out[2]; - assign router_0_2_to_L2_ni_2_req = router_0_2_req_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_req = router_0_2_req_out[4]; - - assign router_0_2_rsp_in[0] = router_0_3_to_router_0_2_rsp; - assign router_0_2_rsp_in[1] = router_1_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[2] = router_0_1_to_router_0_2_rsp; - assign router_0_2_rsp_in[3] = L2_ni_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[4] = magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_2_req_in), - .floo_rsp_o (router_0_2_rsp_out), - .floo_req_o (router_0_2_req_out), - .floo_rsp_i (router_0_2_rsp_in) -); - - -floo_req_t [4:0] router_0_3_req_in; -floo_rsp_t [4:0] router_0_3_rsp_out; -floo_req_t [4:0] router_0_3_req_out; -floo_rsp_t [4:0] router_0_3_rsp_in; - - assign router_0_3_req_in[0] = '0; - assign router_0_3_req_in[1] = router_1_3_to_router_0_3_req; - assign router_0_3_req_in[2] = router_0_2_to_router_0_3_req; - assign router_0_3_req_in[3] = L2_ni_3_to_router_0_3_req; - assign router_0_3_req_in[4] = magia_tile_ni_0_3_to_router_0_3_req; - - assign router_0_3_to_router_1_3_rsp = router_0_3_rsp_out[1]; - assign router_0_3_to_router_0_2_rsp = router_0_3_rsp_out[2]; - assign router_0_3_to_L2_ni_3_rsp = router_0_3_rsp_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_rsp = router_0_3_rsp_out[4]; - - assign router_0_3_to_router_1_3_req = router_0_3_req_out[1]; - assign router_0_3_to_router_0_2_req = router_0_3_req_out[2]; - assign router_0_3_to_L2_ni_3_req = router_0_3_req_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_req = router_0_3_req_out[4]; - - assign router_0_3_rsp_in[0] = '0; - assign router_0_3_rsp_in[1] = router_1_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[2] = router_0_2_to_router_0_3_rsp; - assign router_0_3_rsp_in[3] = L2_ni_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[4] = magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_3_req_in), - .floo_rsp_o (router_0_3_rsp_out), - .floo_req_o (router_0_3_req_out), - .floo_rsp_i (router_0_3_rsp_in) -); - - -floo_req_t [4:0] router_1_0_req_in; -floo_rsp_t [4:0] router_1_0_rsp_out; -floo_req_t [4:0] router_1_0_req_out; -floo_rsp_t [4:0] router_1_0_rsp_in; - - assign router_1_0_req_in[0] = router_1_1_to_router_1_0_req; - assign router_1_0_req_in[1] = router_2_0_to_router_1_0_req; - assign router_1_0_req_in[2] = '0; - assign router_1_0_req_in[3] = router_0_0_to_router_1_0_req; - assign router_1_0_req_in[4] = magia_tile_ni_1_0_to_router_1_0_req; - - assign router_1_0_to_router_1_1_rsp = router_1_0_rsp_out[0]; - assign router_1_0_to_router_2_0_rsp = router_1_0_rsp_out[1]; - assign router_1_0_to_router_0_0_rsp = router_1_0_rsp_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_rsp = router_1_0_rsp_out[4]; - - assign router_1_0_to_router_1_1_req = router_1_0_req_out[0]; - assign router_1_0_to_router_2_0_req = router_1_0_req_out[1]; - assign router_1_0_to_router_0_0_req = router_1_0_req_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_req = router_1_0_req_out[4]; - - assign router_1_0_rsp_in[0] = router_1_1_to_router_1_0_rsp; - assign router_1_0_rsp_in[1] = router_2_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[2] = '0; - assign router_1_0_rsp_in[3] = router_0_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[4] = magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_0_req_in), - .floo_rsp_o (router_1_0_rsp_out), - .floo_req_o (router_1_0_req_out), - .floo_rsp_i (router_1_0_rsp_in) -); - - -floo_req_t [4:0] router_1_1_req_in; -floo_rsp_t [4:0] router_1_1_rsp_out; -floo_req_t [4:0] router_1_1_req_out; -floo_rsp_t [4:0] router_1_1_rsp_in; - - assign router_1_1_req_in[0] = router_1_2_to_router_1_1_req; - assign router_1_1_req_in[1] = router_2_1_to_router_1_1_req; - assign router_1_1_req_in[2] = router_1_0_to_router_1_1_req; - assign router_1_1_req_in[3] = router_0_1_to_router_1_1_req; - assign router_1_1_req_in[4] = magia_tile_ni_1_1_to_router_1_1_req; - - assign router_1_1_to_router_1_2_rsp = router_1_1_rsp_out[0]; - assign router_1_1_to_router_2_1_rsp = router_1_1_rsp_out[1]; - assign router_1_1_to_router_1_0_rsp = router_1_1_rsp_out[2]; - assign router_1_1_to_router_0_1_rsp = router_1_1_rsp_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_rsp = router_1_1_rsp_out[4]; - - assign router_1_1_to_router_1_2_req = router_1_1_req_out[0]; - assign router_1_1_to_router_2_1_req = router_1_1_req_out[1]; - assign router_1_1_to_router_1_0_req = router_1_1_req_out[2]; - assign router_1_1_to_router_0_1_req = router_1_1_req_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_req = router_1_1_req_out[4]; - - assign router_1_1_rsp_in[0] = router_1_2_to_router_1_1_rsp; - assign router_1_1_rsp_in[1] = router_2_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[2] = router_1_0_to_router_1_1_rsp; - assign router_1_1_rsp_in[3] = router_0_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[4] = magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_1_req_in), - .floo_rsp_o (router_1_1_rsp_out), - .floo_req_o (router_1_1_req_out), - .floo_rsp_i (router_1_1_rsp_in) -); - - -floo_req_t [4:0] router_1_2_req_in; -floo_rsp_t [4:0] router_1_2_rsp_out; -floo_req_t [4:0] router_1_2_req_out; -floo_rsp_t [4:0] router_1_2_rsp_in; - - assign router_1_2_req_in[0] = router_1_3_to_router_1_2_req; - assign router_1_2_req_in[1] = router_2_2_to_router_1_2_req; - assign router_1_2_req_in[2] = router_1_1_to_router_1_2_req; - assign router_1_2_req_in[3] = router_0_2_to_router_1_2_req; - assign router_1_2_req_in[4] = magia_tile_ni_1_2_to_router_1_2_req; - - assign router_1_2_to_router_1_3_rsp = router_1_2_rsp_out[0]; - assign router_1_2_to_router_2_2_rsp = router_1_2_rsp_out[1]; - assign router_1_2_to_router_1_1_rsp = router_1_2_rsp_out[2]; - assign router_1_2_to_router_0_2_rsp = router_1_2_rsp_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_rsp = router_1_2_rsp_out[4]; - - assign router_1_2_to_router_1_3_req = router_1_2_req_out[0]; - assign router_1_2_to_router_2_2_req = router_1_2_req_out[1]; - assign router_1_2_to_router_1_1_req = router_1_2_req_out[2]; - assign router_1_2_to_router_0_2_req = router_1_2_req_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_req = router_1_2_req_out[4]; - - assign router_1_2_rsp_in[0] = router_1_3_to_router_1_2_rsp; - assign router_1_2_rsp_in[1] = router_2_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[2] = router_1_1_to_router_1_2_rsp; - assign router_1_2_rsp_in[3] = router_0_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[4] = magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_2_req_in), - .floo_rsp_o (router_1_2_rsp_out), - .floo_req_o (router_1_2_req_out), - .floo_rsp_i (router_1_2_rsp_in) -); - - -floo_req_t [4:0] router_1_3_req_in; -floo_rsp_t [4:0] router_1_3_rsp_out; -floo_req_t [4:0] router_1_3_req_out; -floo_rsp_t [4:0] router_1_3_rsp_in; - - assign router_1_3_req_in[0] = '0; - assign router_1_3_req_in[1] = router_2_3_to_router_1_3_req; - assign router_1_3_req_in[2] = router_1_2_to_router_1_3_req; - assign router_1_3_req_in[3] = router_0_3_to_router_1_3_req; - assign router_1_3_req_in[4] = magia_tile_ni_1_3_to_router_1_3_req; - - assign router_1_3_to_router_2_3_rsp = router_1_3_rsp_out[1]; - assign router_1_3_to_router_1_2_rsp = router_1_3_rsp_out[2]; - assign router_1_3_to_router_0_3_rsp = router_1_3_rsp_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_rsp = router_1_3_rsp_out[4]; - - assign router_1_3_to_router_2_3_req = router_1_3_req_out[1]; - assign router_1_3_to_router_1_2_req = router_1_3_req_out[2]; - assign router_1_3_to_router_0_3_req = router_1_3_req_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_req = router_1_3_req_out[4]; - - assign router_1_3_rsp_in[0] = '0; - assign router_1_3_rsp_in[1] = router_2_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[2] = router_1_2_to_router_1_3_rsp; - assign router_1_3_rsp_in[3] = router_0_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[4] = magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_3_req_in), - .floo_rsp_o (router_1_3_rsp_out), - .floo_req_o (router_1_3_req_out), - .floo_rsp_i (router_1_3_rsp_in) -); - - -floo_req_t [4:0] router_2_0_req_in; -floo_rsp_t [4:0] router_2_0_rsp_out; -floo_req_t [4:0] router_2_0_req_out; -floo_rsp_t [4:0] router_2_0_rsp_in; - - assign router_2_0_req_in[0] = router_2_1_to_router_2_0_req; - assign router_2_0_req_in[1] = router_3_0_to_router_2_0_req; - assign router_2_0_req_in[2] = '0; - assign router_2_0_req_in[3] = router_1_0_to_router_2_0_req; - assign router_2_0_req_in[4] = magia_tile_ni_2_0_to_router_2_0_req; - - assign router_2_0_to_router_2_1_rsp = router_2_0_rsp_out[0]; - assign router_2_0_to_router_3_0_rsp = router_2_0_rsp_out[1]; - assign router_2_0_to_router_1_0_rsp = router_2_0_rsp_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_rsp = router_2_0_rsp_out[4]; - - assign router_2_0_to_router_2_1_req = router_2_0_req_out[0]; - assign router_2_0_to_router_3_0_req = router_2_0_req_out[1]; - assign router_2_0_to_router_1_0_req = router_2_0_req_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_req = router_2_0_req_out[4]; - - assign router_2_0_rsp_in[0] = router_2_1_to_router_2_0_rsp; - assign router_2_0_rsp_in[1] = router_3_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[2] = '0; - assign router_2_0_rsp_in[3] = router_1_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[4] = magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_0_req_in), - .floo_rsp_o (router_2_0_rsp_out), - .floo_req_o (router_2_0_req_out), - .floo_rsp_i (router_2_0_rsp_in) -); - - -floo_req_t [4:0] router_2_1_req_in; -floo_rsp_t [4:0] router_2_1_rsp_out; -floo_req_t [4:0] router_2_1_req_out; -floo_rsp_t [4:0] router_2_1_rsp_in; - - assign router_2_1_req_in[0] = router_2_2_to_router_2_1_req; - assign router_2_1_req_in[1] = router_3_1_to_router_2_1_req; - assign router_2_1_req_in[2] = router_2_0_to_router_2_1_req; - assign router_2_1_req_in[3] = router_1_1_to_router_2_1_req; - assign router_2_1_req_in[4] = magia_tile_ni_2_1_to_router_2_1_req; - - assign router_2_1_to_router_2_2_rsp = router_2_1_rsp_out[0]; - assign router_2_1_to_router_3_1_rsp = router_2_1_rsp_out[1]; - assign router_2_1_to_router_2_0_rsp = router_2_1_rsp_out[2]; - assign router_2_1_to_router_1_1_rsp = router_2_1_rsp_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_rsp = router_2_1_rsp_out[4]; - - assign router_2_1_to_router_2_2_req = router_2_1_req_out[0]; - assign router_2_1_to_router_3_1_req = router_2_1_req_out[1]; - assign router_2_1_to_router_2_0_req = router_2_1_req_out[2]; - assign router_2_1_to_router_1_1_req = router_2_1_req_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_req = router_2_1_req_out[4]; - - assign router_2_1_rsp_in[0] = router_2_2_to_router_2_1_rsp; - assign router_2_1_rsp_in[1] = router_3_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[2] = router_2_0_to_router_2_1_rsp; - assign router_2_1_rsp_in[3] = router_1_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[4] = magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_1_req_in), - .floo_rsp_o (router_2_1_rsp_out), - .floo_req_o (router_2_1_req_out), - .floo_rsp_i (router_2_1_rsp_in) -); - - -floo_req_t [4:0] router_2_2_req_in; -floo_rsp_t [4:0] router_2_2_rsp_out; -floo_req_t [4:0] router_2_2_req_out; -floo_rsp_t [4:0] router_2_2_rsp_in; - - assign router_2_2_req_in[0] = router_2_3_to_router_2_2_req; - assign router_2_2_req_in[1] = router_3_2_to_router_2_2_req; - assign router_2_2_req_in[2] = router_2_1_to_router_2_2_req; - assign router_2_2_req_in[3] = router_1_2_to_router_2_2_req; - assign router_2_2_req_in[4] = magia_tile_ni_2_2_to_router_2_2_req; - - assign router_2_2_to_router_2_3_rsp = router_2_2_rsp_out[0]; - assign router_2_2_to_router_3_2_rsp = router_2_2_rsp_out[1]; - assign router_2_2_to_router_2_1_rsp = router_2_2_rsp_out[2]; - assign router_2_2_to_router_1_2_rsp = router_2_2_rsp_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_rsp = router_2_2_rsp_out[4]; - - assign router_2_2_to_router_2_3_req = router_2_2_req_out[0]; - assign router_2_2_to_router_3_2_req = router_2_2_req_out[1]; - assign router_2_2_to_router_2_1_req = router_2_2_req_out[2]; - assign router_2_2_to_router_1_2_req = router_2_2_req_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_req = router_2_2_req_out[4]; - - assign router_2_2_rsp_in[0] = router_2_3_to_router_2_2_rsp; - assign router_2_2_rsp_in[1] = router_3_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[2] = router_2_1_to_router_2_2_rsp; - assign router_2_2_rsp_in[3] = router_1_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[4] = magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_2_req_in), - .floo_rsp_o (router_2_2_rsp_out), - .floo_req_o (router_2_2_req_out), - .floo_rsp_i (router_2_2_rsp_in) -); - - -floo_req_t [4:0] router_2_3_req_in; -floo_rsp_t [4:0] router_2_3_rsp_out; -floo_req_t [4:0] router_2_3_req_out; -floo_rsp_t [4:0] router_2_3_rsp_in; - - assign router_2_3_req_in[0] = '0; - assign router_2_3_req_in[1] = router_3_3_to_router_2_3_req; - assign router_2_3_req_in[2] = router_2_2_to_router_2_3_req; - assign router_2_3_req_in[3] = router_1_3_to_router_2_3_req; - assign router_2_3_req_in[4] = magia_tile_ni_2_3_to_router_2_3_req; - - assign router_2_3_to_router_3_3_rsp = router_2_3_rsp_out[1]; - assign router_2_3_to_router_2_2_rsp = router_2_3_rsp_out[2]; - assign router_2_3_to_router_1_3_rsp = router_2_3_rsp_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_rsp = router_2_3_rsp_out[4]; - - assign router_2_3_to_router_3_3_req = router_2_3_req_out[1]; - assign router_2_3_to_router_2_2_req = router_2_3_req_out[2]; - assign router_2_3_to_router_1_3_req = router_2_3_req_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_req = router_2_3_req_out[4]; - - assign router_2_3_rsp_in[0] = '0; - assign router_2_3_rsp_in[1] = router_3_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[2] = router_2_2_to_router_2_3_rsp; - assign router_2_3_rsp_in[3] = router_1_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[4] = magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_3_req_in), - .floo_rsp_o (router_2_3_rsp_out), - .floo_req_o (router_2_3_req_out), - .floo_rsp_i (router_2_3_rsp_in) -); - - -floo_req_t [4:0] router_3_0_req_in; -floo_rsp_t [4:0] router_3_0_rsp_out; -floo_req_t [4:0] router_3_0_req_out; -floo_rsp_t [4:0] router_3_0_rsp_in; - - assign router_3_0_req_in[0] = router_3_1_to_router_3_0_req; - assign router_3_0_req_in[1] = '0; - assign router_3_0_req_in[2] = '0; - assign router_3_0_req_in[3] = router_2_0_to_router_3_0_req; - assign router_3_0_req_in[4] = magia_tile_ni_3_0_to_router_3_0_req; - - assign router_3_0_to_router_3_1_rsp = router_3_0_rsp_out[0]; - assign router_3_0_to_router_2_0_rsp = router_3_0_rsp_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_rsp = router_3_0_rsp_out[4]; - - assign router_3_0_to_router_3_1_req = router_3_0_req_out[0]; - assign router_3_0_to_router_2_0_req = router_3_0_req_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_req = router_3_0_req_out[4]; - - assign router_3_0_rsp_in[0] = router_3_1_to_router_3_0_rsp; - assign router_3_0_rsp_in[1] = '0; - assign router_3_0_rsp_in[2] = '0; - assign router_3_0_rsp_in[3] = router_2_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[4] = magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_0_req_in), - .floo_rsp_o (router_3_0_rsp_out), - .floo_req_o (router_3_0_req_out), - .floo_rsp_i (router_3_0_rsp_in) -); - - -floo_req_t [4:0] router_3_1_req_in; -floo_rsp_t [4:0] router_3_1_rsp_out; -floo_req_t [4:0] router_3_1_req_out; -floo_rsp_t [4:0] router_3_1_rsp_in; - - assign router_3_1_req_in[0] = router_3_2_to_router_3_1_req; - assign router_3_1_req_in[1] = '0; - assign router_3_1_req_in[2] = router_3_0_to_router_3_1_req; - assign router_3_1_req_in[3] = router_2_1_to_router_3_1_req; - assign router_3_1_req_in[4] = magia_tile_ni_3_1_to_router_3_1_req; - - assign router_3_1_to_router_3_2_rsp = router_3_1_rsp_out[0]; - assign router_3_1_to_router_3_0_rsp = router_3_1_rsp_out[2]; - assign router_3_1_to_router_2_1_rsp = router_3_1_rsp_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_rsp = router_3_1_rsp_out[4]; - - assign router_3_1_to_router_3_2_req = router_3_1_req_out[0]; - assign router_3_1_to_router_3_0_req = router_3_1_req_out[2]; - assign router_3_1_to_router_2_1_req = router_3_1_req_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_req = router_3_1_req_out[4]; - - assign router_3_1_rsp_in[0] = router_3_2_to_router_3_1_rsp; - assign router_3_1_rsp_in[1] = '0; - assign router_3_1_rsp_in[2] = router_3_0_to_router_3_1_rsp; - assign router_3_1_rsp_in[3] = router_2_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[4] = magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_1_req_in), - .floo_rsp_o (router_3_1_rsp_out), - .floo_req_o (router_3_1_req_out), - .floo_rsp_i (router_3_1_rsp_in) -); - - -floo_req_t [4:0] router_3_2_req_in; -floo_rsp_t [4:0] router_3_2_rsp_out; -floo_req_t [4:0] router_3_2_req_out; -floo_rsp_t [4:0] router_3_2_rsp_in; - - assign router_3_2_req_in[0] = router_3_3_to_router_3_2_req; - assign router_3_2_req_in[1] = '0; - assign router_3_2_req_in[2] = router_3_1_to_router_3_2_req; - assign router_3_2_req_in[3] = router_2_2_to_router_3_2_req; - assign router_3_2_req_in[4] = magia_tile_ni_3_2_to_router_3_2_req; - - assign router_3_2_to_router_3_3_rsp = router_3_2_rsp_out[0]; - assign router_3_2_to_router_3_1_rsp = router_3_2_rsp_out[2]; - assign router_3_2_to_router_2_2_rsp = router_3_2_rsp_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_rsp = router_3_2_rsp_out[4]; - - assign router_3_2_to_router_3_3_req = router_3_2_req_out[0]; - assign router_3_2_to_router_3_1_req = router_3_2_req_out[2]; - assign router_3_2_to_router_2_2_req = router_3_2_req_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_req = router_3_2_req_out[4]; - - assign router_3_2_rsp_in[0] = router_3_3_to_router_3_2_rsp; - assign router_3_2_rsp_in[1] = '0; - assign router_3_2_rsp_in[2] = router_3_1_to_router_3_2_rsp; - assign router_3_2_rsp_in[3] = router_2_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[4] = magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_2_req_in), - .floo_rsp_o (router_3_2_rsp_out), - .floo_req_o (router_3_2_req_out), - .floo_rsp_i (router_3_2_rsp_in) -); - - -floo_req_t [4:0] router_3_3_req_in; -floo_rsp_t [4:0] router_3_3_rsp_out; -floo_req_t [4:0] router_3_3_req_out; -floo_rsp_t [4:0] router_3_3_rsp_in; - - assign router_3_3_req_in[0] = '0; - assign router_3_3_req_in[1] = '0; - assign router_3_3_req_in[2] = router_3_2_to_router_3_3_req; - assign router_3_3_req_in[3] = router_2_3_to_router_3_3_req; - assign router_3_3_req_in[4] = magia_tile_ni_3_3_to_router_3_3_req; - - assign router_3_3_to_router_3_2_rsp = router_3_3_rsp_out[2]; - assign router_3_3_to_router_2_3_rsp = router_3_3_rsp_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_rsp = router_3_3_rsp_out[4]; - - assign router_3_3_to_router_3_2_req = router_3_3_req_out[2]; - assign router_3_3_to_router_2_3_req = router_3_3_req_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_req = router_3_3_req_out[4]; - - assign router_3_3_rsp_in[0] = '0; - assign router_3_3_rsp_in[1] = '0; - assign router_3_3_rsp_in[2] = router_3_2_to_router_3_3_rsp; - assign router_3_3_rsp_in[3] = router_2_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[4] = magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_3_req_in), - .floo_rsp_o (router_3_3_rsp_out), - .floo_req_o (router_3_3_req_out), - .floo_rsp_i (router_3_3_rsp_in) -); - - - -endmodule diff --git a/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv b/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv index 97db9a0..90483b5 100644 --- a/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv +++ b/hw/mesh/noc/floo_axi_mesh_8x8_noc.sv @@ -229,6841 +229,3 @@ typedef logic[0:0] axi_data_slv_user_t; endpackage - -module floo_axi_mesh_8x8_noc - import floo_pkg::*; - import floo_axi_mesh_8x8_noc_pkg::*; -( - input logic clk_i, - input logic rst_ni, - input logic test_enable_i, - input axi_data_slv_req_t [7:0][7:0] magia_tile_data_slv_req_i, - output axi_data_slv_rsp_t [7:0][7:0] magia_tile_data_slv_rsp_o, - output axi_data_mst_req_t [7:0][7:0] magia_tile_data_mst_req_o, - input axi_data_mst_rsp_t [7:0][7:0] magia_tile_data_mst_rsp_i, - output axi_data_mst_req_t [7:0] L2_data_mst_req_o, - input axi_data_mst_rsp_t [7:0] L2_data_mst_rsp_i - -); - -floo_req_t router_0_0_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_0_rsp; - -floo_req_t router_0_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_magia_tile_ni_0_0_req; -floo_rsp_t magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_req_t router_0_0_to_L2_ni_0_req; -floo_rsp_t L2_ni_0_to_router_0_0_rsp; - -floo_req_t router_0_1_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_1_rsp; - -floo_req_t router_0_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_magia_tile_ni_0_1_req; -floo_rsp_t magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_req_t router_0_1_to_L2_ni_1_req; -floo_rsp_t L2_ni_1_to_router_0_1_rsp; - -floo_req_t router_0_2_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_2_rsp; - -floo_req_t router_0_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_magia_tile_ni_0_2_req; -floo_rsp_t magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_req_t router_0_2_to_L2_ni_2_req; -floo_rsp_t L2_ni_2_to_router_0_2_rsp; - -floo_req_t router_0_3_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_3_rsp; - -floo_req_t router_0_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_magia_tile_ni_0_3_req; -floo_rsp_t magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_req_t router_0_3_to_L2_ni_3_req; -floo_rsp_t L2_ni_3_to_router_0_3_rsp; - -floo_req_t router_0_4_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_4_rsp; - -floo_req_t router_0_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_magia_tile_ni_0_4_req; -floo_rsp_t magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_req_t router_0_4_to_L2_ni_4_req; -floo_rsp_t L2_ni_4_to_router_0_4_rsp; - -floo_req_t router_0_5_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_5_rsp; - -floo_req_t router_0_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_magia_tile_ni_0_5_req; -floo_rsp_t magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_req_t router_0_5_to_L2_ni_5_req; -floo_rsp_t L2_ni_5_to_router_0_5_rsp; - -floo_req_t router_0_6_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_0_6_rsp; - -floo_req_t router_0_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_magia_tile_ni_0_6_req; -floo_rsp_t magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_req_t router_0_6_to_L2_ni_6_req; -floo_rsp_t L2_ni_6_to_router_0_6_rsp; - -floo_req_t router_0_7_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_0_7_rsp; - -floo_req_t router_0_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_magia_tile_ni_0_7_req; -floo_rsp_t magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_req_t router_0_7_to_L2_ni_7_req; -floo_rsp_t L2_ni_7_to_router_0_7_rsp; - -floo_req_t router_1_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_0_rsp; - -floo_req_t router_1_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_1_0_rsp; - -floo_req_t router_1_0_to_magia_tile_ni_1_0_req; -floo_rsp_t magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_req_t router_1_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_1_rsp; - -floo_req_t router_1_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_1_1_rsp; - -floo_req_t router_1_1_to_magia_tile_ni_1_1_req; -floo_rsp_t magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_req_t router_1_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_2_rsp; - -floo_req_t router_1_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_1_2_rsp; - -floo_req_t router_1_2_to_magia_tile_ni_1_2_req; -floo_rsp_t magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_req_t router_1_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_3_rsp; - -floo_req_t router_1_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_1_3_rsp; - -floo_req_t router_1_3_to_magia_tile_ni_1_3_req; -floo_rsp_t magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_req_t router_1_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_4_rsp; - -floo_req_t router_1_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_1_4_rsp; - -floo_req_t router_1_4_to_magia_tile_ni_1_4_req; -floo_rsp_t magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_req_t router_1_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_5_rsp; - -floo_req_t router_1_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_1_5_rsp; - -floo_req_t router_1_5_to_magia_tile_ni_1_5_req; -floo_rsp_t magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_req_t router_1_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_1_6_rsp; - -floo_req_t router_1_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_1_6_rsp; - -floo_req_t router_1_6_to_magia_tile_ni_1_6_req; -floo_rsp_t magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_req_t router_1_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_1_7_rsp; - -floo_req_t router_1_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_1_7_rsp; - -floo_req_t router_1_7_to_magia_tile_ni_1_7_req; -floo_rsp_t magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_req_t router_2_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_0_rsp; - -floo_req_t router_2_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_2_0_rsp; - -floo_req_t router_2_0_to_magia_tile_ni_2_0_req; -floo_rsp_t magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_req_t router_2_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_1_rsp; - -floo_req_t router_2_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_2_1_rsp; - -floo_req_t router_2_1_to_magia_tile_ni_2_1_req; -floo_rsp_t magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_req_t router_2_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_2_rsp; - -floo_req_t router_2_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_2_2_rsp; - -floo_req_t router_2_2_to_magia_tile_ni_2_2_req; -floo_rsp_t magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_req_t router_2_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_3_rsp; - -floo_req_t router_2_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_2_3_rsp; - -floo_req_t router_2_3_to_magia_tile_ni_2_3_req; -floo_rsp_t magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_req_t router_2_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_4_rsp; - -floo_req_t router_2_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_2_4_rsp; - -floo_req_t router_2_4_to_magia_tile_ni_2_4_req; -floo_rsp_t magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_req_t router_2_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_5_rsp; - -floo_req_t router_2_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_2_5_rsp; - -floo_req_t router_2_5_to_magia_tile_ni_2_5_req; -floo_rsp_t magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_req_t router_2_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_2_6_rsp; - -floo_req_t router_2_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_2_6_rsp; - -floo_req_t router_2_6_to_magia_tile_ni_2_6_req; -floo_rsp_t magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_req_t router_2_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_2_7_rsp; - -floo_req_t router_2_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_2_7_rsp; - -floo_req_t router_2_7_to_magia_tile_ni_2_7_req; -floo_rsp_t magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_req_t router_3_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_0_rsp; - -floo_req_t router_3_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_3_0_rsp; - -floo_req_t router_3_0_to_magia_tile_ni_3_0_req; -floo_rsp_t magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_req_t router_3_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_1_rsp; - -floo_req_t router_3_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_3_1_rsp; - -floo_req_t router_3_1_to_magia_tile_ni_3_1_req; -floo_rsp_t magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_req_t router_3_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_2_rsp; - -floo_req_t router_3_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_3_2_rsp; - -floo_req_t router_3_2_to_magia_tile_ni_3_2_req; -floo_rsp_t magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_req_t router_3_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_3_rsp; - -floo_req_t router_3_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_3_3_rsp; - -floo_req_t router_3_3_to_magia_tile_ni_3_3_req; -floo_rsp_t magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_req_t router_3_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_4_rsp; - -floo_req_t router_3_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_3_4_rsp; - -floo_req_t router_3_4_to_magia_tile_ni_3_4_req; -floo_rsp_t magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_req_t router_3_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_5_rsp; - -floo_req_t router_3_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_3_5_rsp; - -floo_req_t router_3_5_to_magia_tile_ni_3_5_req; -floo_rsp_t magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_req_t router_3_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_3_6_rsp; - -floo_req_t router_3_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_3_6_rsp; - -floo_req_t router_3_6_to_magia_tile_ni_3_6_req; -floo_rsp_t magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_req_t router_3_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_3_7_rsp; - -floo_req_t router_3_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_3_7_rsp; - -floo_req_t router_3_7_to_magia_tile_ni_3_7_req; -floo_rsp_t magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_req_t router_4_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_0_rsp; - -floo_req_t router_4_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_4_0_rsp; - -floo_req_t router_4_0_to_magia_tile_ni_4_0_req; -floo_rsp_t magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_req_t router_4_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_1_rsp; - -floo_req_t router_4_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_4_1_rsp; - -floo_req_t router_4_1_to_magia_tile_ni_4_1_req; -floo_rsp_t magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_req_t router_4_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_2_rsp; - -floo_req_t router_4_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_4_2_rsp; - -floo_req_t router_4_2_to_magia_tile_ni_4_2_req; -floo_rsp_t magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_req_t router_4_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_3_rsp; - -floo_req_t router_4_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_4_3_rsp; - -floo_req_t router_4_3_to_magia_tile_ni_4_3_req; -floo_rsp_t magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_req_t router_4_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_4_rsp; - -floo_req_t router_4_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_4_4_rsp; - -floo_req_t router_4_4_to_magia_tile_ni_4_4_req; -floo_rsp_t magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_req_t router_4_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_5_rsp; - -floo_req_t router_4_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_4_5_rsp; - -floo_req_t router_4_5_to_magia_tile_ni_4_5_req; -floo_rsp_t magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_req_t router_4_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_4_6_rsp; - -floo_req_t router_4_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_4_6_rsp; - -floo_req_t router_4_6_to_magia_tile_ni_4_6_req; -floo_rsp_t magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_req_t router_4_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_4_7_rsp; - -floo_req_t router_4_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_4_7_rsp; - -floo_req_t router_4_7_to_magia_tile_ni_4_7_req; -floo_rsp_t magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_req_t router_5_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_0_rsp; - -floo_req_t router_5_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_5_0_rsp; - -floo_req_t router_5_0_to_magia_tile_ni_5_0_req; -floo_rsp_t magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_req_t router_5_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_1_rsp; - -floo_req_t router_5_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_5_1_rsp; - -floo_req_t router_5_1_to_magia_tile_ni_5_1_req; -floo_rsp_t magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_req_t router_5_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_2_rsp; - -floo_req_t router_5_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_5_2_rsp; - -floo_req_t router_5_2_to_magia_tile_ni_5_2_req; -floo_rsp_t magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_req_t router_5_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_3_rsp; - -floo_req_t router_5_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_5_3_rsp; - -floo_req_t router_5_3_to_magia_tile_ni_5_3_req; -floo_rsp_t magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_req_t router_5_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_4_rsp; - -floo_req_t router_5_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_5_4_rsp; - -floo_req_t router_5_4_to_magia_tile_ni_5_4_req; -floo_rsp_t magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_req_t router_5_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_5_rsp; - -floo_req_t router_5_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_5_5_rsp; - -floo_req_t router_5_5_to_magia_tile_ni_5_5_req; -floo_rsp_t magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_req_t router_5_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_5_6_rsp; - -floo_req_t router_5_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_5_6_rsp; - -floo_req_t router_5_6_to_magia_tile_ni_5_6_req; -floo_rsp_t magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_req_t router_5_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_5_7_rsp; - -floo_req_t router_5_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_5_7_rsp; - -floo_req_t router_5_7_to_magia_tile_ni_5_7_req; -floo_rsp_t magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_req_t router_6_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_0_rsp; - -floo_req_t router_6_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_6_0_rsp; - -floo_req_t router_6_0_to_magia_tile_ni_6_0_req; -floo_rsp_t magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_req_t router_6_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_1_rsp; - -floo_req_t router_6_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_6_1_rsp; - -floo_req_t router_6_1_to_magia_tile_ni_6_1_req; -floo_rsp_t magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_req_t router_6_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_2_rsp; - -floo_req_t router_6_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_6_2_rsp; - -floo_req_t router_6_2_to_magia_tile_ni_6_2_req; -floo_rsp_t magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_req_t router_6_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_3_rsp; - -floo_req_t router_6_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_6_3_rsp; - -floo_req_t router_6_3_to_magia_tile_ni_6_3_req; -floo_rsp_t magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_req_t router_6_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_4_rsp; - -floo_req_t router_6_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_6_4_rsp; - -floo_req_t router_6_4_to_magia_tile_ni_6_4_req; -floo_rsp_t magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_req_t router_6_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_5_rsp; - -floo_req_t router_6_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_6_5_rsp; - -floo_req_t router_6_5_to_magia_tile_ni_6_5_req; -floo_rsp_t magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_req_t router_6_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_6_6_rsp; - -floo_req_t router_6_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_6_6_rsp; - -floo_req_t router_6_6_to_magia_tile_ni_6_6_req; -floo_rsp_t magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_req_t router_6_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_6_7_rsp; - -floo_req_t router_6_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_6_7_rsp; - -floo_req_t router_6_7_to_magia_tile_ni_6_7_req; -floo_rsp_t magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_req_t router_7_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_router_7_0_rsp; - -floo_req_t router_7_0_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_0_rsp; - -floo_req_t router_7_0_to_magia_tile_ni_7_0_req; -floo_rsp_t magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_req_t router_7_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_0_req; -floo_rsp_t router_7_0_to_router_7_1_rsp; - -floo_req_t router_7_1_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_1_rsp; - -floo_req_t router_7_1_to_magia_tile_ni_7_1_req; -floo_rsp_t magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_req_t router_7_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_1_req; -floo_rsp_t router_7_1_to_router_7_2_rsp; - -floo_req_t router_7_2_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_2_rsp; - -floo_req_t router_7_2_to_magia_tile_ni_7_2_req; -floo_rsp_t magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_req_t router_7_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_2_req; -floo_rsp_t router_7_2_to_router_7_3_rsp; - -floo_req_t router_7_3_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_3_rsp; - -floo_req_t router_7_3_to_magia_tile_ni_7_3_req; -floo_rsp_t magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_req_t router_7_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_3_req; -floo_rsp_t router_7_3_to_router_7_4_rsp; - -floo_req_t router_7_4_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_4_rsp; - -floo_req_t router_7_4_to_magia_tile_ni_7_4_req; -floo_rsp_t magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_req_t router_7_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_4_req; -floo_rsp_t router_7_4_to_router_7_5_rsp; - -floo_req_t router_7_5_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_5_rsp; - -floo_req_t router_7_5_to_magia_tile_ni_7_5_req; -floo_rsp_t magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_req_t router_7_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_5_req; -floo_rsp_t router_7_5_to_router_7_6_rsp; - -floo_req_t router_7_6_to_router_7_7_req; -floo_rsp_t router_7_7_to_router_7_6_rsp; - -floo_req_t router_7_6_to_magia_tile_ni_7_6_req; -floo_rsp_t magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_req_t router_7_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_router_7_7_rsp; - -floo_req_t router_7_7_to_router_7_6_req; -floo_rsp_t router_7_6_to_router_7_7_rsp; - -floo_req_t router_7_7_to_magia_tile_ni_7_7_req; -floo_rsp_t magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_req_t magia_tile_ni_0_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_magia_tile_ni_0_0_rsp; - -floo_req_t magia_tile_ni_0_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_magia_tile_ni_0_1_rsp; - -floo_req_t magia_tile_ni_0_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_magia_tile_ni_0_2_rsp; - -floo_req_t magia_tile_ni_0_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_magia_tile_ni_0_3_rsp; - -floo_req_t magia_tile_ni_0_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_magia_tile_ni_0_4_rsp; - -floo_req_t magia_tile_ni_0_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_magia_tile_ni_0_5_rsp; - -floo_req_t magia_tile_ni_0_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_magia_tile_ni_0_6_rsp; - -floo_req_t magia_tile_ni_0_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_magia_tile_ni_0_7_rsp; - -floo_req_t magia_tile_ni_1_0_to_router_1_0_req; -floo_rsp_t router_1_0_to_magia_tile_ni_1_0_rsp; - -floo_req_t magia_tile_ni_1_1_to_router_1_1_req; -floo_rsp_t router_1_1_to_magia_tile_ni_1_1_rsp; - -floo_req_t magia_tile_ni_1_2_to_router_1_2_req; -floo_rsp_t router_1_2_to_magia_tile_ni_1_2_rsp; - -floo_req_t magia_tile_ni_1_3_to_router_1_3_req; -floo_rsp_t router_1_3_to_magia_tile_ni_1_3_rsp; - -floo_req_t magia_tile_ni_1_4_to_router_1_4_req; -floo_rsp_t router_1_4_to_magia_tile_ni_1_4_rsp; - -floo_req_t magia_tile_ni_1_5_to_router_1_5_req; -floo_rsp_t router_1_5_to_magia_tile_ni_1_5_rsp; - -floo_req_t magia_tile_ni_1_6_to_router_1_6_req; -floo_rsp_t router_1_6_to_magia_tile_ni_1_6_rsp; - -floo_req_t magia_tile_ni_1_7_to_router_1_7_req; -floo_rsp_t router_1_7_to_magia_tile_ni_1_7_rsp; - -floo_req_t magia_tile_ni_2_0_to_router_2_0_req; -floo_rsp_t router_2_0_to_magia_tile_ni_2_0_rsp; - -floo_req_t magia_tile_ni_2_1_to_router_2_1_req; -floo_rsp_t router_2_1_to_magia_tile_ni_2_1_rsp; - -floo_req_t magia_tile_ni_2_2_to_router_2_2_req; -floo_rsp_t router_2_2_to_magia_tile_ni_2_2_rsp; - -floo_req_t magia_tile_ni_2_3_to_router_2_3_req; -floo_rsp_t router_2_3_to_magia_tile_ni_2_3_rsp; - -floo_req_t magia_tile_ni_2_4_to_router_2_4_req; -floo_rsp_t router_2_4_to_magia_tile_ni_2_4_rsp; - -floo_req_t magia_tile_ni_2_5_to_router_2_5_req; -floo_rsp_t router_2_5_to_magia_tile_ni_2_5_rsp; - -floo_req_t magia_tile_ni_2_6_to_router_2_6_req; -floo_rsp_t router_2_6_to_magia_tile_ni_2_6_rsp; - -floo_req_t magia_tile_ni_2_7_to_router_2_7_req; -floo_rsp_t router_2_7_to_magia_tile_ni_2_7_rsp; - -floo_req_t magia_tile_ni_3_0_to_router_3_0_req; -floo_rsp_t router_3_0_to_magia_tile_ni_3_0_rsp; - -floo_req_t magia_tile_ni_3_1_to_router_3_1_req; -floo_rsp_t router_3_1_to_magia_tile_ni_3_1_rsp; - -floo_req_t magia_tile_ni_3_2_to_router_3_2_req; -floo_rsp_t router_3_2_to_magia_tile_ni_3_2_rsp; - -floo_req_t magia_tile_ni_3_3_to_router_3_3_req; -floo_rsp_t router_3_3_to_magia_tile_ni_3_3_rsp; - -floo_req_t magia_tile_ni_3_4_to_router_3_4_req; -floo_rsp_t router_3_4_to_magia_tile_ni_3_4_rsp; - -floo_req_t magia_tile_ni_3_5_to_router_3_5_req; -floo_rsp_t router_3_5_to_magia_tile_ni_3_5_rsp; - -floo_req_t magia_tile_ni_3_6_to_router_3_6_req; -floo_rsp_t router_3_6_to_magia_tile_ni_3_6_rsp; - -floo_req_t magia_tile_ni_3_7_to_router_3_7_req; -floo_rsp_t router_3_7_to_magia_tile_ni_3_7_rsp; - -floo_req_t magia_tile_ni_4_0_to_router_4_0_req; -floo_rsp_t router_4_0_to_magia_tile_ni_4_0_rsp; - -floo_req_t magia_tile_ni_4_1_to_router_4_1_req; -floo_rsp_t router_4_1_to_magia_tile_ni_4_1_rsp; - -floo_req_t magia_tile_ni_4_2_to_router_4_2_req; -floo_rsp_t router_4_2_to_magia_tile_ni_4_2_rsp; - -floo_req_t magia_tile_ni_4_3_to_router_4_3_req; -floo_rsp_t router_4_3_to_magia_tile_ni_4_3_rsp; - -floo_req_t magia_tile_ni_4_4_to_router_4_4_req; -floo_rsp_t router_4_4_to_magia_tile_ni_4_4_rsp; - -floo_req_t magia_tile_ni_4_5_to_router_4_5_req; -floo_rsp_t router_4_5_to_magia_tile_ni_4_5_rsp; - -floo_req_t magia_tile_ni_4_6_to_router_4_6_req; -floo_rsp_t router_4_6_to_magia_tile_ni_4_6_rsp; - -floo_req_t magia_tile_ni_4_7_to_router_4_7_req; -floo_rsp_t router_4_7_to_magia_tile_ni_4_7_rsp; - -floo_req_t magia_tile_ni_5_0_to_router_5_0_req; -floo_rsp_t router_5_0_to_magia_tile_ni_5_0_rsp; - -floo_req_t magia_tile_ni_5_1_to_router_5_1_req; -floo_rsp_t router_5_1_to_magia_tile_ni_5_1_rsp; - -floo_req_t magia_tile_ni_5_2_to_router_5_2_req; -floo_rsp_t router_5_2_to_magia_tile_ni_5_2_rsp; - -floo_req_t magia_tile_ni_5_3_to_router_5_3_req; -floo_rsp_t router_5_3_to_magia_tile_ni_5_3_rsp; - -floo_req_t magia_tile_ni_5_4_to_router_5_4_req; -floo_rsp_t router_5_4_to_magia_tile_ni_5_4_rsp; - -floo_req_t magia_tile_ni_5_5_to_router_5_5_req; -floo_rsp_t router_5_5_to_magia_tile_ni_5_5_rsp; - -floo_req_t magia_tile_ni_5_6_to_router_5_6_req; -floo_rsp_t router_5_6_to_magia_tile_ni_5_6_rsp; - -floo_req_t magia_tile_ni_5_7_to_router_5_7_req; -floo_rsp_t router_5_7_to_magia_tile_ni_5_7_rsp; - -floo_req_t magia_tile_ni_6_0_to_router_6_0_req; -floo_rsp_t router_6_0_to_magia_tile_ni_6_0_rsp; - -floo_req_t magia_tile_ni_6_1_to_router_6_1_req; -floo_rsp_t router_6_1_to_magia_tile_ni_6_1_rsp; - -floo_req_t magia_tile_ni_6_2_to_router_6_2_req; -floo_rsp_t router_6_2_to_magia_tile_ni_6_2_rsp; - -floo_req_t magia_tile_ni_6_3_to_router_6_3_req; -floo_rsp_t router_6_3_to_magia_tile_ni_6_3_rsp; - -floo_req_t magia_tile_ni_6_4_to_router_6_4_req; -floo_rsp_t router_6_4_to_magia_tile_ni_6_4_rsp; - -floo_req_t magia_tile_ni_6_5_to_router_6_5_req; -floo_rsp_t router_6_5_to_magia_tile_ni_6_5_rsp; - -floo_req_t magia_tile_ni_6_6_to_router_6_6_req; -floo_rsp_t router_6_6_to_magia_tile_ni_6_6_rsp; - -floo_req_t magia_tile_ni_6_7_to_router_6_7_req; -floo_rsp_t router_6_7_to_magia_tile_ni_6_7_rsp; - -floo_req_t magia_tile_ni_7_0_to_router_7_0_req; -floo_rsp_t router_7_0_to_magia_tile_ni_7_0_rsp; - -floo_req_t magia_tile_ni_7_1_to_router_7_1_req; -floo_rsp_t router_7_1_to_magia_tile_ni_7_1_rsp; - -floo_req_t magia_tile_ni_7_2_to_router_7_2_req; -floo_rsp_t router_7_2_to_magia_tile_ni_7_2_rsp; - -floo_req_t magia_tile_ni_7_3_to_router_7_3_req; -floo_rsp_t router_7_3_to_magia_tile_ni_7_3_rsp; - -floo_req_t magia_tile_ni_7_4_to_router_7_4_req; -floo_rsp_t router_7_4_to_magia_tile_ni_7_4_rsp; - -floo_req_t magia_tile_ni_7_5_to_router_7_5_req; -floo_rsp_t router_7_5_to_magia_tile_ni_7_5_rsp; - -floo_req_t magia_tile_ni_7_6_to_router_7_6_req; -floo_rsp_t router_7_6_to_magia_tile_ni_7_6_rsp; - -floo_req_t magia_tile_ni_7_7_to_router_7_7_req; -floo_rsp_t router_7_7_to_magia_tile_ni_7_7_rsp; - -floo_req_t L2_ni_0_to_router_0_0_req; -floo_rsp_t router_0_0_to_L2_ni_0_rsp; - -floo_req_t L2_ni_1_to_router_0_1_req; -floo_rsp_t router_0_1_to_L2_ni_1_rsp; - -floo_req_t L2_ni_2_to_router_0_2_req; -floo_rsp_t router_0_2_to_L2_ni_2_rsp; - -floo_req_t L2_ni_3_to_router_0_3_req; -floo_rsp_t router_0_3_to_L2_ni_3_rsp; - -floo_req_t L2_ni_4_to_router_0_4_req; -floo_rsp_t router_0_4_to_L2_ni_4_rsp; - -floo_req_t L2_ni_5_to_router_0_5_req; -floo_rsp_t router_0_5_to_L2_ni_5_rsp; - -floo_req_t L2_ni_6_to_router_0_6_req; -floo_rsp_t router_0_6_to_L2_ni_6_rsp; - -floo_req_t L2_ni_7_to_router_0_7_req; -floo_rsp_t router_0_7_to_L2_ni_7_rsp; - - - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][0] ), - .id_i ( '{x: 1, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_magia_tile_ni_0_0_rsp ), - .floo_req_i ( router_0_0_to_magia_tile_ni_0_0_req ), - .floo_rsp_o ( magia_tile_ni_0_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][1] ), - .id_i ( '{x: 1, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_magia_tile_ni_0_1_rsp ), - .floo_req_i ( router_0_1_to_magia_tile_ni_0_1_req ), - .floo_rsp_o ( magia_tile_ni_0_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][2] ), - .id_i ( '{x: 1, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_magia_tile_ni_0_2_rsp ), - .floo_req_i ( router_0_2_to_magia_tile_ni_0_2_req ), - .floo_rsp_o ( magia_tile_ni_0_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][3] ), - .id_i ( '{x: 1, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_magia_tile_ni_0_3_rsp ), - .floo_req_i ( router_0_3_to_magia_tile_ni_0_3_req ), - .floo_rsp_o ( magia_tile_ni_0_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][4] ), - .id_i ( '{x: 1, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_magia_tile_ni_0_4_rsp ), - .floo_req_i ( router_0_4_to_magia_tile_ni_0_4_req ), - .floo_rsp_o ( magia_tile_ni_0_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][5] ), - .id_i ( '{x: 1, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_magia_tile_ni_0_5_rsp ), - .floo_req_i ( router_0_5_to_magia_tile_ni_0_5_req ), - .floo_rsp_o ( magia_tile_ni_0_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][6] ), - .id_i ( '{x: 1, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_magia_tile_ni_0_6_rsp ), - .floo_req_i ( router_0_6_to_magia_tile_ni_0_6_req ), - .floo_rsp_o ( magia_tile_ni_0_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[0][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[0][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[0][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[0][7] ), - .id_i ( '{x: 1, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_0_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_magia_tile_ni_0_7_rsp ), - .floo_req_i ( router_0_7_to_magia_tile_ni_0_7_req ), - .floo_rsp_o ( magia_tile_ni_0_7_to_router_0_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][0] ), - .id_i ( '{x: 2, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_0_to_router_1_0_req ), - .floo_rsp_i ( router_1_0_to_magia_tile_ni_1_0_rsp ), - .floo_req_i ( router_1_0_to_magia_tile_ni_1_0_req ), - .floo_rsp_o ( magia_tile_ni_1_0_to_router_1_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][1] ), - .id_i ( '{x: 2, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_1_to_router_1_1_req ), - .floo_rsp_i ( router_1_1_to_magia_tile_ni_1_1_rsp ), - .floo_req_i ( router_1_1_to_magia_tile_ni_1_1_req ), - .floo_rsp_o ( magia_tile_ni_1_1_to_router_1_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][2] ), - .id_i ( '{x: 2, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_2_to_router_1_2_req ), - .floo_rsp_i ( router_1_2_to_magia_tile_ni_1_2_rsp ), - .floo_req_i ( router_1_2_to_magia_tile_ni_1_2_req ), - .floo_rsp_o ( magia_tile_ni_1_2_to_router_1_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][3] ), - .id_i ( '{x: 2, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_3_to_router_1_3_req ), - .floo_rsp_i ( router_1_3_to_magia_tile_ni_1_3_rsp ), - .floo_req_i ( router_1_3_to_magia_tile_ni_1_3_req ), - .floo_rsp_o ( magia_tile_ni_1_3_to_router_1_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][4] ), - .id_i ( '{x: 2, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_4_to_router_1_4_req ), - .floo_rsp_i ( router_1_4_to_magia_tile_ni_1_4_rsp ), - .floo_req_i ( router_1_4_to_magia_tile_ni_1_4_req ), - .floo_rsp_o ( magia_tile_ni_1_4_to_router_1_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][5] ), - .id_i ( '{x: 2, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_5_to_router_1_5_req ), - .floo_rsp_i ( router_1_5_to_magia_tile_ni_1_5_rsp ), - .floo_req_i ( router_1_5_to_magia_tile_ni_1_5_req ), - .floo_rsp_o ( magia_tile_ni_1_5_to_router_1_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][6] ), - .id_i ( '{x: 2, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_6_to_router_1_6_req ), - .floo_rsp_i ( router_1_6_to_magia_tile_ni_1_6_rsp ), - .floo_req_i ( router_1_6_to_magia_tile_ni_1_6_req ), - .floo_rsp_o ( magia_tile_ni_1_6_to_router_1_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[1][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[1][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[1][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[1][7] ), - .id_i ( '{x: 2, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_1_7_to_router_1_7_req ), - .floo_rsp_i ( router_1_7_to_magia_tile_ni_1_7_rsp ), - .floo_req_i ( router_1_7_to_magia_tile_ni_1_7_req ), - .floo_rsp_o ( magia_tile_ni_1_7_to_router_1_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][0] ), - .id_i ( '{x: 3, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_0_to_router_2_0_req ), - .floo_rsp_i ( router_2_0_to_magia_tile_ni_2_0_rsp ), - .floo_req_i ( router_2_0_to_magia_tile_ni_2_0_req ), - .floo_rsp_o ( magia_tile_ni_2_0_to_router_2_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][1] ), - .id_i ( '{x: 3, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_1_to_router_2_1_req ), - .floo_rsp_i ( router_2_1_to_magia_tile_ni_2_1_rsp ), - .floo_req_i ( router_2_1_to_magia_tile_ni_2_1_req ), - .floo_rsp_o ( magia_tile_ni_2_1_to_router_2_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][2] ), - .id_i ( '{x: 3, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_2_to_router_2_2_req ), - .floo_rsp_i ( router_2_2_to_magia_tile_ni_2_2_rsp ), - .floo_req_i ( router_2_2_to_magia_tile_ni_2_2_req ), - .floo_rsp_o ( magia_tile_ni_2_2_to_router_2_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][3] ), - .id_i ( '{x: 3, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_3_to_router_2_3_req ), - .floo_rsp_i ( router_2_3_to_magia_tile_ni_2_3_rsp ), - .floo_req_i ( router_2_3_to_magia_tile_ni_2_3_req ), - .floo_rsp_o ( magia_tile_ni_2_3_to_router_2_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][4] ), - .id_i ( '{x: 3, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_4_to_router_2_4_req ), - .floo_rsp_i ( router_2_4_to_magia_tile_ni_2_4_rsp ), - .floo_req_i ( router_2_4_to_magia_tile_ni_2_4_req ), - .floo_rsp_o ( magia_tile_ni_2_4_to_router_2_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][5] ), - .id_i ( '{x: 3, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_5_to_router_2_5_req ), - .floo_rsp_i ( router_2_5_to_magia_tile_ni_2_5_rsp ), - .floo_req_i ( router_2_5_to_magia_tile_ni_2_5_req ), - .floo_rsp_o ( magia_tile_ni_2_5_to_router_2_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][6] ), - .id_i ( '{x: 3, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_6_to_router_2_6_req ), - .floo_rsp_i ( router_2_6_to_magia_tile_ni_2_6_rsp ), - .floo_req_i ( router_2_6_to_magia_tile_ni_2_6_req ), - .floo_rsp_o ( magia_tile_ni_2_6_to_router_2_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[2][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[2][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[2][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[2][7] ), - .id_i ( '{x: 3, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_2_7_to_router_2_7_req ), - .floo_rsp_i ( router_2_7_to_magia_tile_ni_2_7_rsp ), - .floo_req_i ( router_2_7_to_magia_tile_ni_2_7_req ), - .floo_rsp_o ( magia_tile_ni_2_7_to_router_2_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][0] ), - .id_i ( '{x: 4, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_0_to_router_3_0_req ), - .floo_rsp_i ( router_3_0_to_magia_tile_ni_3_0_rsp ), - .floo_req_i ( router_3_0_to_magia_tile_ni_3_0_req ), - .floo_rsp_o ( magia_tile_ni_3_0_to_router_3_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][1] ), - .id_i ( '{x: 4, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_1_to_router_3_1_req ), - .floo_rsp_i ( router_3_1_to_magia_tile_ni_3_1_rsp ), - .floo_req_i ( router_3_1_to_magia_tile_ni_3_1_req ), - .floo_rsp_o ( magia_tile_ni_3_1_to_router_3_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][2] ), - .id_i ( '{x: 4, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_2_to_router_3_2_req ), - .floo_rsp_i ( router_3_2_to_magia_tile_ni_3_2_rsp ), - .floo_req_i ( router_3_2_to_magia_tile_ni_3_2_req ), - .floo_rsp_o ( magia_tile_ni_3_2_to_router_3_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][3] ), - .id_i ( '{x: 4, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_3_to_router_3_3_req ), - .floo_rsp_i ( router_3_3_to_magia_tile_ni_3_3_rsp ), - .floo_req_i ( router_3_3_to_magia_tile_ni_3_3_req ), - .floo_rsp_o ( magia_tile_ni_3_3_to_router_3_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][4] ), - .id_i ( '{x: 4, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_4_to_router_3_4_req ), - .floo_rsp_i ( router_3_4_to_magia_tile_ni_3_4_rsp ), - .floo_req_i ( router_3_4_to_magia_tile_ni_3_4_req ), - .floo_rsp_o ( magia_tile_ni_3_4_to_router_3_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][5] ), - .id_i ( '{x: 4, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_5_to_router_3_5_req ), - .floo_rsp_i ( router_3_5_to_magia_tile_ni_3_5_rsp ), - .floo_req_i ( router_3_5_to_magia_tile_ni_3_5_req ), - .floo_rsp_o ( magia_tile_ni_3_5_to_router_3_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][6] ), - .id_i ( '{x: 4, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_6_to_router_3_6_req ), - .floo_rsp_i ( router_3_6_to_magia_tile_ni_3_6_rsp ), - .floo_req_i ( router_3_6_to_magia_tile_ni_3_6_req ), - .floo_rsp_o ( magia_tile_ni_3_6_to_router_3_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[3][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[3][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[3][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[3][7] ), - .id_i ( '{x: 4, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_3_7_to_router_3_7_req ), - .floo_rsp_i ( router_3_7_to_magia_tile_ni_3_7_rsp ), - .floo_req_i ( router_3_7_to_magia_tile_ni_3_7_req ), - .floo_rsp_o ( magia_tile_ni_3_7_to_router_3_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][0] ), - .id_i ( '{x: 5, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_0_to_router_4_0_req ), - .floo_rsp_i ( router_4_0_to_magia_tile_ni_4_0_rsp ), - .floo_req_i ( router_4_0_to_magia_tile_ni_4_0_req ), - .floo_rsp_o ( magia_tile_ni_4_0_to_router_4_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][1] ), - .id_i ( '{x: 5, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_1_to_router_4_1_req ), - .floo_rsp_i ( router_4_1_to_magia_tile_ni_4_1_rsp ), - .floo_req_i ( router_4_1_to_magia_tile_ni_4_1_req ), - .floo_rsp_o ( magia_tile_ni_4_1_to_router_4_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][2] ), - .id_i ( '{x: 5, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_2_to_router_4_2_req ), - .floo_rsp_i ( router_4_2_to_magia_tile_ni_4_2_rsp ), - .floo_req_i ( router_4_2_to_magia_tile_ni_4_2_req ), - .floo_rsp_o ( magia_tile_ni_4_2_to_router_4_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][3] ), - .id_i ( '{x: 5, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_3_to_router_4_3_req ), - .floo_rsp_i ( router_4_3_to_magia_tile_ni_4_3_rsp ), - .floo_req_i ( router_4_3_to_magia_tile_ni_4_3_req ), - .floo_rsp_o ( magia_tile_ni_4_3_to_router_4_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][4] ), - .id_i ( '{x: 5, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_4_to_router_4_4_req ), - .floo_rsp_i ( router_4_4_to_magia_tile_ni_4_4_rsp ), - .floo_req_i ( router_4_4_to_magia_tile_ni_4_4_req ), - .floo_rsp_o ( magia_tile_ni_4_4_to_router_4_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][5] ), - .id_i ( '{x: 5, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_5_to_router_4_5_req ), - .floo_rsp_i ( router_4_5_to_magia_tile_ni_4_5_rsp ), - .floo_req_i ( router_4_5_to_magia_tile_ni_4_5_req ), - .floo_rsp_o ( magia_tile_ni_4_5_to_router_4_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][6] ), - .id_i ( '{x: 5, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_6_to_router_4_6_req ), - .floo_rsp_i ( router_4_6_to_magia_tile_ni_4_6_rsp ), - .floo_req_i ( router_4_6_to_magia_tile_ni_4_6_req ), - .floo_rsp_o ( magia_tile_ni_4_6_to_router_4_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[4][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[4][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[4][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[4][7] ), - .id_i ( '{x: 5, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_4_7_to_router_4_7_req ), - .floo_rsp_i ( router_4_7_to_magia_tile_ni_4_7_rsp ), - .floo_req_i ( router_4_7_to_magia_tile_ni_4_7_req ), - .floo_rsp_o ( magia_tile_ni_4_7_to_router_4_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][0] ), - .id_i ( '{x: 6, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_0_to_router_5_0_req ), - .floo_rsp_i ( router_5_0_to_magia_tile_ni_5_0_rsp ), - .floo_req_i ( router_5_0_to_magia_tile_ni_5_0_req ), - .floo_rsp_o ( magia_tile_ni_5_0_to_router_5_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][1] ), - .id_i ( '{x: 6, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_1_to_router_5_1_req ), - .floo_rsp_i ( router_5_1_to_magia_tile_ni_5_1_rsp ), - .floo_req_i ( router_5_1_to_magia_tile_ni_5_1_req ), - .floo_rsp_o ( magia_tile_ni_5_1_to_router_5_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][2] ), - .id_i ( '{x: 6, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_2_to_router_5_2_req ), - .floo_rsp_i ( router_5_2_to_magia_tile_ni_5_2_rsp ), - .floo_req_i ( router_5_2_to_magia_tile_ni_5_2_req ), - .floo_rsp_o ( magia_tile_ni_5_2_to_router_5_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][3] ), - .id_i ( '{x: 6, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_3_to_router_5_3_req ), - .floo_rsp_i ( router_5_3_to_magia_tile_ni_5_3_rsp ), - .floo_req_i ( router_5_3_to_magia_tile_ni_5_3_req ), - .floo_rsp_o ( magia_tile_ni_5_3_to_router_5_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][4] ), - .id_i ( '{x: 6, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_4_to_router_5_4_req ), - .floo_rsp_i ( router_5_4_to_magia_tile_ni_5_4_rsp ), - .floo_req_i ( router_5_4_to_magia_tile_ni_5_4_req ), - .floo_rsp_o ( magia_tile_ni_5_4_to_router_5_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][5] ), - .id_i ( '{x: 6, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_5_to_router_5_5_req ), - .floo_rsp_i ( router_5_5_to_magia_tile_ni_5_5_rsp ), - .floo_req_i ( router_5_5_to_magia_tile_ni_5_5_req ), - .floo_rsp_o ( magia_tile_ni_5_5_to_router_5_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][6] ), - .id_i ( '{x: 6, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_6_to_router_5_6_req ), - .floo_rsp_i ( router_5_6_to_magia_tile_ni_5_6_rsp ), - .floo_req_i ( router_5_6_to_magia_tile_ni_5_6_req ), - .floo_rsp_o ( magia_tile_ni_5_6_to_router_5_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[5][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[5][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[5][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[5][7] ), - .id_i ( '{x: 6, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_5_7_to_router_5_7_req ), - .floo_rsp_i ( router_5_7_to_magia_tile_ni_5_7_rsp ), - .floo_req_i ( router_5_7_to_magia_tile_ni_5_7_req ), - .floo_rsp_o ( magia_tile_ni_5_7_to_router_5_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][0] ), - .id_i ( '{x: 7, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_0_to_router_6_0_req ), - .floo_rsp_i ( router_6_0_to_magia_tile_ni_6_0_rsp ), - .floo_req_i ( router_6_0_to_magia_tile_ni_6_0_req ), - .floo_rsp_o ( magia_tile_ni_6_0_to_router_6_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][1] ), - .id_i ( '{x: 7, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_1_to_router_6_1_req ), - .floo_rsp_i ( router_6_1_to_magia_tile_ni_6_1_rsp ), - .floo_req_i ( router_6_1_to_magia_tile_ni_6_1_req ), - .floo_rsp_o ( magia_tile_ni_6_1_to_router_6_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][2] ), - .id_i ( '{x: 7, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_2_to_router_6_2_req ), - .floo_rsp_i ( router_6_2_to_magia_tile_ni_6_2_rsp ), - .floo_req_i ( router_6_2_to_magia_tile_ni_6_2_req ), - .floo_rsp_o ( magia_tile_ni_6_2_to_router_6_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][3] ), - .id_i ( '{x: 7, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_3_to_router_6_3_req ), - .floo_rsp_i ( router_6_3_to_magia_tile_ni_6_3_rsp ), - .floo_req_i ( router_6_3_to_magia_tile_ni_6_3_req ), - .floo_rsp_o ( magia_tile_ni_6_3_to_router_6_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][4] ), - .id_i ( '{x: 7, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_4_to_router_6_4_req ), - .floo_rsp_i ( router_6_4_to_magia_tile_ni_6_4_rsp ), - .floo_req_i ( router_6_4_to_magia_tile_ni_6_4_req ), - .floo_rsp_o ( magia_tile_ni_6_4_to_router_6_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][5] ), - .id_i ( '{x: 7, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_5_to_router_6_5_req ), - .floo_rsp_i ( router_6_5_to_magia_tile_ni_6_5_rsp ), - .floo_req_i ( router_6_5_to_magia_tile_ni_6_5_req ), - .floo_rsp_o ( magia_tile_ni_6_5_to_router_6_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][6] ), - .id_i ( '{x: 7, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_6_to_router_6_6_req ), - .floo_rsp_i ( router_6_6_to_magia_tile_ni_6_6_rsp ), - .floo_req_i ( router_6_6_to_magia_tile_ni_6_6_req ), - .floo_rsp_o ( magia_tile_ni_6_6_to_router_6_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[6][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[6][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[6][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[6][7] ), - .id_i ( '{x: 7, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_6_7_to_router_6_7_req ), - .floo_rsp_i ( router_6_7_to_magia_tile_ni_6_7_rsp ), - .floo_req_i ( router_6_7_to_magia_tile_ni_6_7_req ), - .floo_rsp_o ( magia_tile_ni_6_7_to_router_6_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][0] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][0] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][0] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][0] ), - .id_i ( '{x: 8, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_0_to_router_7_0_req ), - .floo_rsp_i ( router_7_0_to_magia_tile_ni_7_0_rsp ), - .floo_req_i ( router_7_0_to_magia_tile_ni_7_0_req ), - .floo_rsp_o ( magia_tile_ni_7_0_to_router_7_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][1] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][1] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][1] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][1] ), - .id_i ( '{x: 8, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_1_to_router_7_1_req ), - .floo_rsp_i ( router_7_1_to_magia_tile_ni_7_1_rsp ), - .floo_req_i ( router_7_1_to_magia_tile_ni_7_1_req ), - .floo_rsp_o ( magia_tile_ni_7_1_to_router_7_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][2] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][2] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][2] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][2] ), - .id_i ( '{x: 8, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_2_to_router_7_2_req ), - .floo_rsp_i ( router_7_2_to_magia_tile_ni_7_2_rsp ), - .floo_req_i ( router_7_2_to_magia_tile_ni_7_2_req ), - .floo_rsp_o ( magia_tile_ni_7_2_to_router_7_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][3] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][3] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][3] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][3] ), - .id_i ( '{x: 8, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_3_to_router_7_3_req ), - .floo_rsp_i ( router_7_3_to_magia_tile_ni_7_3_rsp ), - .floo_req_i ( router_7_3_to_magia_tile_ni_7_3_req ), - .floo_rsp_o ( magia_tile_ni_7_3_to_router_7_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][4] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][4] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][4] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][4] ), - .id_i ( '{x: 8, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_4_to_router_7_4_req ), - .floo_rsp_i ( router_7_4_to_magia_tile_ni_7_4_rsp ), - .floo_req_i ( router_7_4_to_magia_tile_ni_7_4_req ), - .floo_rsp_o ( magia_tile_ni_7_4_to_router_7_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][5] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][5] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][5] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][5] ), - .id_i ( '{x: 8, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_5_to_router_7_5_req ), - .floo_rsp_i ( router_7_5_to_magia_tile_ni_7_5_rsp ), - .floo_req_i ( router_7_5_to_magia_tile_ni_7_5_req ), - .floo_rsp_o ( magia_tile_ni_7_5_to_router_7_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][6] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][6] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][6] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][6] ), - .id_i ( '{x: 8, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_6_to_router_7_6_req ), - .floo_rsp_i ( router_7_6_to_magia_tile_ni_7_6_rsp ), - .floo_req_i ( router_7_6_to_magia_tile_ni_7_6_req ), - .floo_rsp_o ( magia_tile_ni_7_6_to_router_7_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b1)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) magia_tile_ni_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( magia_tile_data_slv_req_i[7][7] ), - .axi_in_rsp_o ( magia_tile_data_slv_rsp_o[7][7] ), - .axi_out_req_o ( magia_tile_data_mst_req_o[7][7] ), - .axi_out_rsp_i ( magia_tile_data_mst_rsp_i[7][7] ), - .id_i ( '{x: 8, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( magia_tile_ni_7_7_to_router_7_7_req ), - .floo_rsp_i ( router_7_7_to_magia_tile_ni_7_7_rsp ), - .floo_req_i ( router_7_7_to_magia_tile_ni_7_7_req ), - .floo_rsp_o ( magia_tile_ni_7_7_to_router_7_7_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[0] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[0] ), - .id_i ( '{x: 0, y: 0, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_0_to_router_0_0_req ), - .floo_rsp_i ( router_0_0_to_L2_ni_0_rsp ), - .floo_req_i ( router_0_0_to_L2_ni_0_req ), - .floo_rsp_o ( L2_ni_0_to_router_0_0_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[1] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[1] ), - .id_i ( '{x: 0, y: 1, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_1_to_router_0_1_req ), - .floo_rsp_i ( router_0_1_to_L2_ni_1_rsp ), - .floo_req_i ( router_0_1_to_L2_ni_1_req ), - .floo_rsp_o ( L2_ni_1_to_router_0_1_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[2] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[2] ), - .id_i ( '{x: 0, y: 2, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_2_to_router_0_2_req ), - .floo_rsp_i ( router_0_2_to_L2_ni_2_rsp ), - .floo_req_i ( router_0_2_to_L2_ni_2_req ), - .floo_rsp_o ( L2_ni_2_to_router_0_2_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[3] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[3] ), - .id_i ( '{x: 0, y: 3, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_3_to_router_0_3_req ), - .floo_rsp_i ( router_0_3_to_L2_ni_3_rsp ), - .floo_req_i ( router_0_3_to_L2_ni_3_req ), - .floo_rsp_o ( L2_ni_3_to_router_0_3_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[4] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[4] ), - .id_i ( '{x: 0, y: 4, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_4_to_router_0_4_req ), - .floo_rsp_i ( router_0_4_to_L2_ni_4_rsp ), - .floo_req_i ( router_0_4_to_L2_ni_4_req ), - .floo_rsp_o ( L2_ni_4_to_router_0_4_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[5] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[5] ), - .id_i ( '{x: 0, y: 5, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_5_to_router_0_5_req ), - .floo_rsp_i ( router_0_5_to_L2_ni_5_rsp ), - .floo_req_i ( router_0_5_to_L2_ni_5_req ), - .floo_rsp_o ( L2_ni_5_to_router_0_5_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[6] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[6] ), - .id_i ( '{x: 0, y: 6, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_6_to_router_0_6_req ), - .floo_rsp_i ( router_0_6_to_L2_ni_6_rsp ), - .floo_req_i ( router_0_6_to_L2_ni_6_req ), - .floo_rsp_o ( L2_ni_6_to_router_0_6_rsp ) -); - -floo_axi_chimney #( - .AxiCfg(AxiCfg), - .ChimneyCfg(set_ports(ChimneyDefaultCfg, 1'b1, 1'b0)), - .RouteCfg(RouteCfg), - .id_t(id_t), - .rob_idx_t(rob_idx_t), - .hdr_t (hdr_t), - .sam_rule_t(sam_rule_t), - .Sam(Sam), - .axi_in_req_t(axi_data_slv_req_t), - .axi_in_rsp_t(axi_data_slv_rsp_t), - .axi_out_req_t(axi_data_mst_req_t), - .axi_out_rsp_t(axi_data_mst_rsp_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) L2_ni_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .sram_cfg_i ( '0 ), - .axi_in_req_i ( '0 ), - .axi_in_rsp_o ( ), - .axi_out_req_o ( L2_data_mst_req_o[7] ), - .axi_out_rsp_i ( L2_data_mst_rsp_i[7] ), - .id_i ( '{x: 0, y: 7, port_id: 0} ), - .route_table_i ( '0 ), - .floo_req_o ( L2_ni_7_to_router_0_7_req ), - .floo_rsp_i ( router_0_7_to_L2_ni_7_rsp ), - .floo_req_i ( router_0_7_to_L2_ni_7_req ), - .floo_rsp_o ( L2_ni_7_to_router_0_7_rsp ) -); - - -floo_req_t [4:0] router_0_0_req_in; -floo_rsp_t [4:0] router_0_0_rsp_out; -floo_req_t [4:0] router_0_0_req_out; -floo_rsp_t [4:0] router_0_0_rsp_in; - - assign router_0_0_req_in[0] = router_0_1_to_router_0_0_req; - assign router_0_0_req_in[1] = router_1_0_to_router_0_0_req; - assign router_0_0_req_in[2] = '0; - assign router_0_0_req_in[3] = L2_ni_0_to_router_0_0_req; - assign router_0_0_req_in[4] = magia_tile_ni_0_0_to_router_0_0_req; - - assign router_0_0_to_router_0_1_rsp = router_0_0_rsp_out[0]; - assign router_0_0_to_router_1_0_rsp = router_0_0_rsp_out[1]; - assign router_0_0_to_L2_ni_0_rsp = router_0_0_rsp_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_rsp = router_0_0_rsp_out[4]; - - assign router_0_0_to_router_0_1_req = router_0_0_req_out[0]; - assign router_0_0_to_router_1_0_req = router_0_0_req_out[1]; - assign router_0_0_to_L2_ni_0_req = router_0_0_req_out[3]; - assign router_0_0_to_magia_tile_ni_0_0_req = router_0_0_req_out[4]; - - assign router_0_0_rsp_in[0] = router_0_1_to_router_0_0_rsp; - assign router_0_0_rsp_in[1] = router_1_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[2] = '0; - assign router_0_0_rsp_in[3] = L2_ni_0_to_router_0_0_rsp; - assign router_0_0_rsp_in[4] = magia_tile_ni_0_0_to_router_0_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_0_req_in), - .floo_rsp_o (router_0_0_rsp_out), - .floo_req_o (router_0_0_req_out), - .floo_rsp_i (router_0_0_rsp_in) -); - - -floo_req_t [4:0] router_0_1_req_in; -floo_rsp_t [4:0] router_0_1_rsp_out; -floo_req_t [4:0] router_0_1_req_out; -floo_rsp_t [4:0] router_0_1_rsp_in; - - assign router_0_1_req_in[0] = router_0_2_to_router_0_1_req; - assign router_0_1_req_in[1] = router_1_1_to_router_0_1_req; - assign router_0_1_req_in[2] = router_0_0_to_router_0_1_req; - assign router_0_1_req_in[3] = L2_ni_1_to_router_0_1_req; - assign router_0_1_req_in[4] = magia_tile_ni_0_1_to_router_0_1_req; - - assign router_0_1_to_router_0_2_rsp = router_0_1_rsp_out[0]; - assign router_0_1_to_router_1_1_rsp = router_0_1_rsp_out[1]; - assign router_0_1_to_router_0_0_rsp = router_0_1_rsp_out[2]; - assign router_0_1_to_L2_ni_1_rsp = router_0_1_rsp_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_rsp = router_0_1_rsp_out[4]; - - assign router_0_1_to_router_0_2_req = router_0_1_req_out[0]; - assign router_0_1_to_router_1_1_req = router_0_1_req_out[1]; - assign router_0_1_to_router_0_0_req = router_0_1_req_out[2]; - assign router_0_1_to_L2_ni_1_req = router_0_1_req_out[3]; - assign router_0_1_to_magia_tile_ni_0_1_req = router_0_1_req_out[4]; - - assign router_0_1_rsp_in[0] = router_0_2_to_router_0_1_rsp; - assign router_0_1_rsp_in[1] = router_1_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[2] = router_0_0_to_router_0_1_rsp; - assign router_0_1_rsp_in[3] = L2_ni_1_to_router_0_1_rsp; - assign router_0_1_rsp_in[4] = magia_tile_ni_0_1_to_router_0_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_1_req_in), - .floo_rsp_o (router_0_1_rsp_out), - .floo_req_o (router_0_1_req_out), - .floo_rsp_i (router_0_1_rsp_in) -); - - -floo_req_t [4:0] router_0_2_req_in; -floo_rsp_t [4:0] router_0_2_rsp_out; -floo_req_t [4:0] router_0_2_req_out; -floo_rsp_t [4:0] router_0_2_rsp_in; - - assign router_0_2_req_in[0] = router_0_3_to_router_0_2_req; - assign router_0_2_req_in[1] = router_1_2_to_router_0_2_req; - assign router_0_2_req_in[2] = router_0_1_to_router_0_2_req; - assign router_0_2_req_in[3] = L2_ni_2_to_router_0_2_req; - assign router_0_2_req_in[4] = magia_tile_ni_0_2_to_router_0_2_req; - - assign router_0_2_to_router_0_3_rsp = router_0_2_rsp_out[0]; - assign router_0_2_to_router_1_2_rsp = router_0_2_rsp_out[1]; - assign router_0_2_to_router_0_1_rsp = router_0_2_rsp_out[2]; - assign router_0_2_to_L2_ni_2_rsp = router_0_2_rsp_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_rsp = router_0_2_rsp_out[4]; - - assign router_0_2_to_router_0_3_req = router_0_2_req_out[0]; - assign router_0_2_to_router_1_2_req = router_0_2_req_out[1]; - assign router_0_2_to_router_0_1_req = router_0_2_req_out[2]; - assign router_0_2_to_L2_ni_2_req = router_0_2_req_out[3]; - assign router_0_2_to_magia_tile_ni_0_2_req = router_0_2_req_out[4]; - - assign router_0_2_rsp_in[0] = router_0_3_to_router_0_2_rsp; - assign router_0_2_rsp_in[1] = router_1_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[2] = router_0_1_to_router_0_2_rsp; - assign router_0_2_rsp_in[3] = L2_ni_2_to_router_0_2_rsp; - assign router_0_2_rsp_in[4] = magia_tile_ni_0_2_to_router_0_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_2_req_in), - .floo_rsp_o (router_0_2_rsp_out), - .floo_req_o (router_0_2_req_out), - .floo_rsp_i (router_0_2_rsp_in) -); - - -floo_req_t [4:0] router_0_3_req_in; -floo_rsp_t [4:0] router_0_3_rsp_out; -floo_req_t [4:0] router_0_3_req_out; -floo_rsp_t [4:0] router_0_3_rsp_in; - - assign router_0_3_req_in[0] = router_0_4_to_router_0_3_req; - assign router_0_3_req_in[1] = router_1_3_to_router_0_3_req; - assign router_0_3_req_in[2] = router_0_2_to_router_0_3_req; - assign router_0_3_req_in[3] = L2_ni_3_to_router_0_3_req; - assign router_0_3_req_in[4] = magia_tile_ni_0_3_to_router_0_3_req; - - assign router_0_3_to_router_0_4_rsp = router_0_3_rsp_out[0]; - assign router_0_3_to_router_1_3_rsp = router_0_3_rsp_out[1]; - assign router_0_3_to_router_0_2_rsp = router_0_3_rsp_out[2]; - assign router_0_3_to_L2_ni_3_rsp = router_0_3_rsp_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_rsp = router_0_3_rsp_out[4]; - - assign router_0_3_to_router_0_4_req = router_0_3_req_out[0]; - assign router_0_3_to_router_1_3_req = router_0_3_req_out[1]; - assign router_0_3_to_router_0_2_req = router_0_3_req_out[2]; - assign router_0_3_to_L2_ni_3_req = router_0_3_req_out[3]; - assign router_0_3_to_magia_tile_ni_0_3_req = router_0_3_req_out[4]; - - assign router_0_3_rsp_in[0] = router_0_4_to_router_0_3_rsp; - assign router_0_3_rsp_in[1] = router_1_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[2] = router_0_2_to_router_0_3_rsp; - assign router_0_3_rsp_in[3] = L2_ni_3_to_router_0_3_rsp; - assign router_0_3_rsp_in[4] = magia_tile_ni_0_3_to_router_0_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_3_req_in), - .floo_rsp_o (router_0_3_rsp_out), - .floo_req_o (router_0_3_req_out), - .floo_rsp_i (router_0_3_rsp_in) -); - - -floo_req_t [4:0] router_0_4_req_in; -floo_rsp_t [4:0] router_0_4_rsp_out; -floo_req_t [4:0] router_0_4_req_out; -floo_rsp_t [4:0] router_0_4_rsp_in; - - assign router_0_4_req_in[0] = router_0_5_to_router_0_4_req; - assign router_0_4_req_in[1] = router_1_4_to_router_0_4_req; - assign router_0_4_req_in[2] = router_0_3_to_router_0_4_req; - assign router_0_4_req_in[3] = L2_ni_4_to_router_0_4_req; - assign router_0_4_req_in[4] = magia_tile_ni_0_4_to_router_0_4_req; - - assign router_0_4_to_router_0_5_rsp = router_0_4_rsp_out[0]; - assign router_0_4_to_router_1_4_rsp = router_0_4_rsp_out[1]; - assign router_0_4_to_router_0_3_rsp = router_0_4_rsp_out[2]; - assign router_0_4_to_L2_ni_4_rsp = router_0_4_rsp_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_rsp = router_0_4_rsp_out[4]; - - assign router_0_4_to_router_0_5_req = router_0_4_req_out[0]; - assign router_0_4_to_router_1_4_req = router_0_4_req_out[1]; - assign router_0_4_to_router_0_3_req = router_0_4_req_out[2]; - assign router_0_4_to_L2_ni_4_req = router_0_4_req_out[3]; - assign router_0_4_to_magia_tile_ni_0_4_req = router_0_4_req_out[4]; - - assign router_0_4_rsp_in[0] = router_0_5_to_router_0_4_rsp; - assign router_0_4_rsp_in[1] = router_1_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[2] = router_0_3_to_router_0_4_rsp; - assign router_0_4_rsp_in[3] = L2_ni_4_to_router_0_4_rsp; - assign router_0_4_rsp_in[4] = magia_tile_ni_0_4_to_router_0_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_4_req_in), - .floo_rsp_o (router_0_4_rsp_out), - .floo_req_o (router_0_4_req_out), - .floo_rsp_i (router_0_4_rsp_in) -); - - -floo_req_t [4:0] router_0_5_req_in; -floo_rsp_t [4:0] router_0_5_rsp_out; -floo_req_t [4:0] router_0_5_req_out; -floo_rsp_t [4:0] router_0_5_rsp_in; - - assign router_0_5_req_in[0] = router_0_6_to_router_0_5_req; - assign router_0_5_req_in[1] = router_1_5_to_router_0_5_req; - assign router_0_5_req_in[2] = router_0_4_to_router_0_5_req; - assign router_0_5_req_in[3] = L2_ni_5_to_router_0_5_req; - assign router_0_5_req_in[4] = magia_tile_ni_0_5_to_router_0_5_req; - - assign router_0_5_to_router_0_6_rsp = router_0_5_rsp_out[0]; - assign router_0_5_to_router_1_5_rsp = router_0_5_rsp_out[1]; - assign router_0_5_to_router_0_4_rsp = router_0_5_rsp_out[2]; - assign router_0_5_to_L2_ni_5_rsp = router_0_5_rsp_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_rsp = router_0_5_rsp_out[4]; - - assign router_0_5_to_router_0_6_req = router_0_5_req_out[0]; - assign router_0_5_to_router_1_5_req = router_0_5_req_out[1]; - assign router_0_5_to_router_0_4_req = router_0_5_req_out[2]; - assign router_0_5_to_L2_ni_5_req = router_0_5_req_out[3]; - assign router_0_5_to_magia_tile_ni_0_5_req = router_0_5_req_out[4]; - - assign router_0_5_rsp_in[0] = router_0_6_to_router_0_5_rsp; - assign router_0_5_rsp_in[1] = router_1_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[2] = router_0_4_to_router_0_5_rsp; - assign router_0_5_rsp_in[3] = L2_ni_5_to_router_0_5_rsp; - assign router_0_5_rsp_in[4] = magia_tile_ni_0_5_to_router_0_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_5_req_in), - .floo_rsp_o (router_0_5_rsp_out), - .floo_req_o (router_0_5_req_out), - .floo_rsp_i (router_0_5_rsp_in) -); - - -floo_req_t [4:0] router_0_6_req_in; -floo_rsp_t [4:0] router_0_6_rsp_out; -floo_req_t [4:0] router_0_6_req_out; -floo_rsp_t [4:0] router_0_6_rsp_in; - - assign router_0_6_req_in[0] = router_0_7_to_router_0_6_req; - assign router_0_6_req_in[1] = router_1_6_to_router_0_6_req; - assign router_0_6_req_in[2] = router_0_5_to_router_0_6_req; - assign router_0_6_req_in[3] = L2_ni_6_to_router_0_6_req; - assign router_0_6_req_in[4] = magia_tile_ni_0_6_to_router_0_6_req; - - assign router_0_6_to_router_0_7_rsp = router_0_6_rsp_out[0]; - assign router_0_6_to_router_1_6_rsp = router_0_6_rsp_out[1]; - assign router_0_6_to_router_0_5_rsp = router_0_6_rsp_out[2]; - assign router_0_6_to_L2_ni_6_rsp = router_0_6_rsp_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_rsp = router_0_6_rsp_out[4]; - - assign router_0_6_to_router_0_7_req = router_0_6_req_out[0]; - assign router_0_6_to_router_1_6_req = router_0_6_req_out[1]; - assign router_0_6_to_router_0_5_req = router_0_6_req_out[2]; - assign router_0_6_to_L2_ni_6_req = router_0_6_req_out[3]; - assign router_0_6_to_magia_tile_ni_0_6_req = router_0_6_req_out[4]; - - assign router_0_6_rsp_in[0] = router_0_7_to_router_0_6_rsp; - assign router_0_6_rsp_in[1] = router_1_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[2] = router_0_5_to_router_0_6_rsp; - assign router_0_6_rsp_in[3] = L2_ni_6_to_router_0_6_rsp; - assign router_0_6_rsp_in[4] = magia_tile_ni_0_6_to_router_0_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_6_req_in), - .floo_rsp_o (router_0_6_rsp_out), - .floo_req_o (router_0_6_req_out), - .floo_rsp_i (router_0_6_rsp_in) -); - - -floo_req_t [4:0] router_0_7_req_in; -floo_rsp_t [4:0] router_0_7_rsp_out; -floo_req_t [4:0] router_0_7_req_out; -floo_rsp_t [4:0] router_0_7_rsp_in; - - assign router_0_7_req_in[0] = '0; - assign router_0_7_req_in[1] = router_1_7_to_router_0_7_req; - assign router_0_7_req_in[2] = router_0_6_to_router_0_7_req; - assign router_0_7_req_in[3] = L2_ni_7_to_router_0_7_req; - assign router_0_7_req_in[4] = magia_tile_ni_0_7_to_router_0_7_req; - - assign router_0_7_to_router_1_7_rsp = router_0_7_rsp_out[1]; - assign router_0_7_to_router_0_6_rsp = router_0_7_rsp_out[2]; - assign router_0_7_to_L2_ni_7_rsp = router_0_7_rsp_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_rsp = router_0_7_rsp_out[4]; - - assign router_0_7_to_router_1_7_req = router_0_7_req_out[1]; - assign router_0_7_to_router_0_6_req = router_0_7_req_out[2]; - assign router_0_7_to_L2_ni_7_req = router_0_7_req_out[3]; - assign router_0_7_to_magia_tile_ni_0_7_req = router_0_7_req_out[4]; - - assign router_0_7_rsp_in[0] = '0; - assign router_0_7_rsp_in[1] = router_1_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[2] = router_0_6_to_router_0_7_rsp; - assign router_0_7_rsp_in[3] = L2_ni_7_to_router_0_7_rsp; - assign router_0_7_rsp_in[4] = magia_tile_ni_0_7_to_router_0_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_0_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 1, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_0_7_req_in), - .floo_rsp_o (router_0_7_rsp_out), - .floo_req_o (router_0_7_req_out), - .floo_rsp_i (router_0_7_rsp_in) -); - - -floo_req_t [4:0] router_1_0_req_in; -floo_rsp_t [4:0] router_1_0_rsp_out; -floo_req_t [4:0] router_1_0_req_out; -floo_rsp_t [4:0] router_1_0_rsp_in; - - assign router_1_0_req_in[0] = router_1_1_to_router_1_0_req; - assign router_1_0_req_in[1] = router_2_0_to_router_1_0_req; - assign router_1_0_req_in[2] = '0; - assign router_1_0_req_in[3] = router_0_0_to_router_1_0_req; - assign router_1_0_req_in[4] = magia_tile_ni_1_0_to_router_1_0_req; - - assign router_1_0_to_router_1_1_rsp = router_1_0_rsp_out[0]; - assign router_1_0_to_router_2_0_rsp = router_1_0_rsp_out[1]; - assign router_1_0_to_router_0_0_rsp = router_1_0_rsp_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_rsp = router_1_0_rsp_out[4]; - - assign router_1_0_to_router_1_1_req = router_1_0_req_out[0]; - assign router_1_0_to_router_2_0_req = router_1_0_req_out[1]; - assign router_1_0_to_router_0_0_req = router_1_0_req_out[3]; - assign router_1_0_to_magia_tile_ni_1_0_req = router_1_0_req_out[4]; - - assign router_1_0_rsp_in[0] = router_1_1_to_router_1_0_rsp; - assign router_1_0_rsp_in[1] = router_2_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[2] = '0; - assign router_1_0_rsp_in[3] = router_0_0_to_router_1_0_rsp; - assign router_1_0_rsp_in[4] = magia_tile_ni_1_0_to_router_1_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_0_req_in), - .floo_rsp_o (router_1_0_rsp_out), - .floo_req_o (router_1_0_req_out), - .floo_rsp_i (router_1_0_rsp_in) -); - - -floo_req_t [4:0] router_1_1_req_in; -floo_rsp_t [4:0] router_1_1_rsp_out; -floo_req_t [4:0] router_1_1_req_out; -floo_rsp_t [4:0] router_1_1_rsp_in; - - assign router_1_1_req_in[0] = router_1_2_to_router_1_1_req; - assign router_1_1_req_in[1] = router_2_1_to_router_1_1_req; - assign router_1_1_req_in[2] = router_1_0_to_router_1_1_req; - assign router_1_1_req_in[3] = router_0_1_to_router_1_1_req; - assign router_1_1_req_in[4] = magia_tile_ni_1_1_to_router_1_1_req; - - assign router_1_1_to_router_1_2_rsp = router_1_1_rsp_out[0]; - assign router_1_1_to_router_2_1_rsp = router_1_1_rsp_out[1]; - assign router_1_1_to_router_1_0_rsp = router_1_1_rsp_out[2]; - assign router_1_1_to_router_0_1_rsp = router_1_1_rsp_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_rsp = router_1_1_rsp_out[4]; - - assign router_1_1_to_router_1_2_req = router_1_1_req_out[0]; - assign router_1_1_to_router_2_1_req = router_1_1_req_out[1]; - assign router_1_1_to_router_1_0_req = router_1_1_req_out[2]; - assign router_1_1_to_router_0_1_req = router_1_1_req_out[3]; - assign router_1_1_to_magia_tile_ni_1_1_req = router_1_1_req_out[4]; - - assign router_1_1_rsp_in[0] = router_1_2_to_router_1_1_rsp; - assign router_1_1_rsp_in[1] = router_2_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[2] = router_1_0_to_router_1_1_rsp; - assign router_1_1_rsp_in[3] = router_0_1_to_router_1_1_rsp; - assign router_1_1_rsp_in[4] = magia_tile_ni_1_1_to_router_1_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_1_req_in), - .floo_rsp_o (router_1_1_rsp_out), - .floo_req_o (router_1_1_req_out), - .floo_rsp_i (router_1_1_rsp_in) -); - - -floo_req_t [4:0] router_1_2_req_in; -floo_rsp_t [4:0] router_1_2_rsp_out; -floo_req_t [4:0] router_1_2_req_out; -floo_rsp_t [4:0] router_1_2_rsp_in; - - assign router_1_2_req_in[0] = router_1_3_to_router_1_2_req; - assign router_1_2_req_in[1] = router_2_2_to_router_1_2_req; - assign router_1_2_req_in[2] = router_1_1_to_router_1_2_req; - assign router_1_2_req_in[3] = router_0_2_to_router_1_2_req; - assign router_1_2_req_in[4] = magia_tile_ni_1_2_to_router_1_2_req; - - assign router_1_2_to_router_1_3_rsp = router_1_2_rsp_out[0]; - assign router_1_2_to_router_2_2_rsp = router_1_2_rsp_out[1]; - assign router_1_2_to_router_1_1_rsp = router_1_2_rsp_out[2]; - assign router_1_2_to_router_0_2_rsp = router_1_2_rsp_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_rsp = router_1_2_rsp_out[4]; - - assign router_1_2_to_router_1_3_req = router_1_2_req_out[0]; - assign router_1_2_to_router_2_2_req = router_1_2_req_out[1]; - assign router_1_2_to_router_1_1_req = router_1_2_req_out[2]; - assign router_1_2_to_router_0_2_req = router_1_2_req_out[3]; - assign router_1_2_to_magia_tile_ni_1_2_req = router_1_2_req_out[4]; - - assign router_1_2_rsp_in[0] = router_1_3_to_router_1_2_rsp; - assign router_1_2_rsp_in[1] = router_2_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[2] = router_1_1_to_router_1_2_rsp; - assign router_1_2_rsp_in[3] = router_0_2_to_router_1_2_rsp; - assign router_1_2_rsp_in[4] = magia_tile_ni_1_2_to_router_1_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_2_req_in), - .floo_rsp_o (router_1_2_rsp_out), - .floo_req_o (router_1_2_req_out), - .floo_rsp_i (router_1_2_rsp_in) -); - - -floo_req_t [4:0] router_1_3_req_in; -floo_rsp_t [4:0] router_1_3_rsp_out; -floo_req_t [4:0] router_1_3_req_out; -floo_rsp_t [4:0] router_1_3_rsp_in; - - assign router_1_3_req_in[0] = router_1_4_to_router_1_3_req; - assign router_1_3_req_in[1] = router_2_3_to_router_1_3_req; - assign router_1_3_req_in[2] = router_1_2_to_router_1_3_req; - assign router_1_3_req_in[3] = router_0_3_to_router_1_3_req; - assign router_1_3_req_in[4] = magia_tile_ni_1_3_to_router_1_3_req; - - assign router_1_3_to_router_1_4_rsp = router_1_3_rsp_out[0]; - assign router_1_3_to_router_2_3_rsp = router_1_3_rsp_out[1]; - assign router_1_3_to_router_1_2_rsp = router_1_3_rsp_out[2]; - assign router_1_3_to_router_0_3_rsp = router_1_3_rsp_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_rsp = router_1_3_rsp_out[4]; - - assign router_1_3_to_router_1_4_req = router_1_3_req_out[0]; - assign router_1_3_to_router_2_3_req = router_1_3_req_out[1]; - assign router_1_3_to_router_1_2_req = router_1_3_req_out[2]; - assign router_1_3_to_router_0_3_req = router_1_3_req_out[3]; - assign router_1_3_to_magia_tile_ni_1_3_req = router_1_3_req_out[4]; - - assign router_1_3_rsp_in[0] = router_1_4_to_router_1_3_rsp; - assign router_1_3_rsp_in[1] = router_2_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[2] = router_1_2_to_router_1_3_rsp; - assign router_1_3_rsp_in[3] = router_0_3_to_router_1_3_rsp; - assign router_1_3_rsp_in[4] = magia_tile_ni_1_3_to_router_1_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_3_req_in), - .floo_rsp_o (router_1_3_rsp_out), - .floo_req_o (router_1_3_req_out), - .floo_rsp_i (router_1_3_rsp_in) -); - - -floo_req_t [4:0] router_1_4_req_in; -floo_rsp_t [4:0] router_1_4_rsp_out; -floo_req_t [4:0] router_1_4_req_out; -floo_rsp_t [4:0] router_1_4_rsp_in; - - assign router_1_4_req_in[0] = router_1_5_to_router_1_4_req; - assign router_1_4_req_in[1] = router_2_4_to_router_1_4_req; - assign router_1_4_req_in[2] = router_1_3_to_router_1_4_req; - assign router_1_4_req_in[3] = router_0_4_to_router_1_4_req; - assign router_1_4_req_in[4] = magia_tile_ni_1_4_to_router_1_4_req; - - assign router_1_4_to_router_1_5_rsp = router_1_4_rsp_out[0]; - assign router_1_4_to_router_2_4_rsp = router_1_4_rsp_out[1]; - assign router_1_4_to_router_1_3_rsp = router_1_4_rsp_out[2]; - assign router_1_4_to_router_0_4_rsp = router_1_4_rsp_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_rsp = router_1_4_rsp_out[4]; - - assign router_1_4_to_router_1_5_req = router_1_4_req_out[0]; - assign router_1_4_to_router_2_4_req = router_1_4_req_out[1]; - assign router_1_4_to_router_1_3_req = router_1_4_req_out[2]; - assign router_1_4_to_router_0_4_req = router_1_4_req_out[3]; - assign router_1_4_to_magia_tile_ni_1_4_req = router_1_4_req_out[4]; - - assign router_1_4_rsp_in[0] = router_1_5_to_router_1_4_rsp; - assign router_1_4_rsp_in[1] = router_2_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[2] = router_1_3_to_router_1_4_rsp; - assign router_1_4_rsp_in[3] = router_0_4_to_router_1_4_rsp; - assign router_1_4_rsp_in[4] = magia_tile_ni_1_4_to_router_1_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_4_req_in), - .floo_rsp_o (router_1_4_rsp_out), - .floo_req_o (router_1_4_req_out), - .floo_rsp_i (router_1_4_rsp_in) -); - - -floo_req_t [4:0] router_1_5_req_in; -floo_rsp_t [4:0] router_1_5_rsp_out; -floo_req_t [4:0] router_1_5_req_out; -floo_rsp_t [4:0] router_1_5_rsp_in; - - assign router_1_5_req_in[0] = router_1_6_to_router_1_5_req; - assign router_1_5_req_in[1] = router_2_5_to_router_1_5_req; - assign router_1_5_req_in[2] = router_1_4_to_router_1_5_req; - assign router_1_5_req_in[3] = router_0_5_to_router_1_5_req; - assign router_1_5_req_in[4] = magia_tile_ni_1_5_to_router_1_5_req; - - assign router_1_5_to_router_1_6_rsp = router_1_5_rsp_out[0]; - assign router_1_5_to_router_2_5_rsp = router_1_5_rsp_out[1]; - assign router_1_5_to_router_1_4_rsp = router_1_5_rsp_out[2]; - assign router_1_5_to_router_0_5_rsp = router_1_5_rsp_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_rsp = router_1_5_rsp_out[4]; - - assign router_1_5_to_router_1_6_req = router_1_5_req_out[0]; - assign router_1_5_to_router_2_5_req = router_1_5_req_out[1]; - assign router_1_5_to_router_1_4_req = router_1_5_req_out[2]; - assign router_1_5_to_router_0_5_req = router_1_5_req_out[3]; - assign router_1_5_to_magia_tile_ni_1_5_req = router_1_5_req_out[4]; - - assign router_1_5_rsp_in[0] = router_1_6_to_router_1_5_rsp; - assign router_1_5_rsp_in[1] = router_2_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[2] = router_1_4_to_router_1_5_rsp; - assign router_1_5_rsp_in[3] = router_0_5_to_router_1_5_rsp; - assign router_1_5_rsp_in[4] = magia_tile_ni_1_5_to_router_1_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_5_req_in), - .floo_rsp_o (router_1_5_rsp_out), - .floo_req_o (router_1_5_req_out), - .floo_rsp_i (router_1_5_rsp_in) -); - - -floo_req_t [4:0] router_1_6_req_in; -floo_rsp_t [4:0] router_1_6_rsp_out; -floo_req_t [4:0] router_1_6_req_out; -floo_rsp_t [4:0] router_1_6_rsp_in; - - assign router_1_6_req_in[0] = router_1_7_to_router_1_6_req; - assign router_1_6_req_in[1] = router_2_6_to_router_1_6_req; - assign router_1_6_req_in[2] = router_1_5_to_router_1_6_req; - assign router_1_6_req_in[3] = router_0_6_to_router_1_6_req; - assign router_1_6_req_in[4] = magia_tile_ni_1_6_to_router_1_6_req; - - assign router_1_6_to_router_1_7_rsp = router_1_6_rsp_out[0]; - assign router_1_6_to_router_2_6_rsp = router_1_6_rsp_out[1]; - assign router_1_6_to_router_1_5_rsp = router_1_6_rsp_out[2]; - assign router_1_6_to_router_0_6_rsp = router_1_6_rsp_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_rsp = router_1_6_rsp_out[4]; - - assign router_1_6_to_router_1_7_req = router_1_6_req_out[0]; - assign router_1_6_to_router_2_6_req = router_1_6_req_out[1]; - assign router_1_6_to_router_1_5_req = router_1_6_req_out[2]; - assign router_1_6_to_router_0_6_req = router_1_6_req_out[3]; - assign router_1_6_to_magia_tile_ni_1_6_req = router_1_6_req_out[4]; - - assign router_1_6_rsp_in[0] = router_1_7_to_router_1_6_rsp; - assign router_1_6_rsp_in[1] = router_2_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[2] = router_1_5_to_router_1_6_rsp; - assign router_1_6_rsp_in[3] = router_0_6_to_router_1_6_rsp; - assign router_1_6_rsp_in[4] = magia_tile_ni_1_6_to_router_1_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_6_req_in), - .floo_rsp_o (router_1_6_rsp_out), - .floo_req_o (router_1_6_req_out), - .floo_rsp_i (router_1_6_rsp_in) -); - - -floo_req_t [4:0] router_1_7_req_in; -floo_rsp_t [4:0] router_1_7_rsp_out; -floo_req_t [4:0] router_1_7_req_out; -floo_rsp_t [4:0] router_1_7_rsp_in; - - assign router_1_7_req_in[0] = '0; - assign router_1_7_req_in[1] = router_2_7_to_router_1_7_req; - assign router_1_7_req_in[2] = router_1_6_to_router_1_7_req; - assign router_1_7_req_in[3] = router_0_7_to_router_1_7_req; - assign router_1_7_req_in[4] = magia_tile_ni_1_7_to_router_1_7_req; - - assign router_1_7_to_router_2_7_rsp = router_1_7_rsp_out[1]; - assign router_1_7_to_router_1_6_rsp = router_1_7_rsp_out[2]; - assign router_1_7_to_router_0_7_rsp = router_1_7_rsp_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_rsp = router_1_7_rsp_out[4]; - - assign router_1_7_to_router_2_7_req = router_1_7_req_out[1]; - assign router_1_7_to_router_1_6_req = router_1_7_req_out[2]; - assign router_1_7_to_router_0_7_req = router_1_7_req_out[3]; - assign router_1_7_to_magia_tile_ni_1_7_req = router_1_7_req_out[4]; - - assign router_1_7_rsp_in[0] = '0; - assign router_1_7_rsp_in[1] = router_2_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[2] = router_1_6_to_router_1_7_rsp; - assign router_1_7_rsp_in[3] = router_0_7_to_router_1_7_rsp; - assign router_1_7_rsp_in[4] = magia_tile_ni_1_7_to_router_1_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_1_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 2, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_1_7_req_in), - .floo_rsp_o (router_1_7_rsp_out), - .floo_req_o (router_1_7_req_out), - .floo_rsp_i (router_1_7_rsp_in) -); - - -floo_req_t [4:0] router_2_0_req_in; -floo_rsp_t [4:0] router_2_0_rsp_out; -floo_req_t [4:0] router_2_0_req_out; -floo_rsp_t [4:0] router_2_0_rsp_in; - - assign router_2_0_req_in[0] = router_2_1_to_router_2_0_req; - assign router_2_0_req_in[1] = router_3_0_to_router_2_0_req; - assign router_2_0_req_in[2] = '0; - assign router_2_0_req_in[3] = router_1_0_to_router_2_0_req; - assign router_2_0_req_in[4] = magia_tile_ni_2_0_to_router_2_0_req; - - assign router_2_0_to_router_2_1_rsp = router_2_0_rsp_out[0]; - assign router_2_0_to_router_3_0_rsp = router_2_0_rsp_out[1]; - assign router_2_0_to_router_1_0_rsp = router_2_0_rsp_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_rsp = router_2_0_rsp_out[4]; - - assign router_2_0_to_router_2_1_req = router_2_0_req_out[0]; - assign router_2_0_to_router_3_0_req = router_2_0_req_out[1]; - assign router_2_0_to_router_1_0_req = router_2_0_req_out[3]; - assign router_2_0_to_magia_tile_ni_2_0_req = router_2_0_req_out[4]; - - assign router_2_0_rsp_in[0] = router_2_1_to_router_2_0_rsp; - assign router_2_0_rsp_in[1] = router_3_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[2] = '0; - assign router_2_0_rsp_in[3] = router_1_0_to_router_2_0_rsp; - assign router_2_0_rsp_in[4] = magia_tile_ni_2_0_to_router_2_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_0_req_in), - .floo_rsp_o (router_2_0_rsp_out), - .floo_req_o (router_2_0_req_out), - .floo_rsp_i (router_2_0_rsp_in) -); - - -floo_req_t [4:0] router_2_1_req_in; -floo_rsp_t [4:0] router_2_1_rsp_out; -floo_req_t [4:0] router_2_1_req_out; -floo_rsp_t [4:0] router_2_1_rsp_in; - - assign router_2_1_req_in[0] = router_2_2_to_router_2_1_req; - assign router_2_1_req_in[1] = router_3_1_to_router_2_1_req; - assign router_2_1_req_in[2] = router_2_0_to_router_2_1_req; - assign router_2_1_req_in[3] = router_1_1_to_router_2_1_req; - assign router_2_1_req_in[4] = magia_tile_ni_2_1_to_router_2_1_req; - - assign router_2_1_to_router_2_2_rsp = router_2_1_rsp_out[0]; - assign router_2_1_to_router_3_1_rsp = router_2_1_rsp_out[1]; - assign router_2_1_to_router_2_0_rsp = router_2_1_rsp_out[2]; - assign router_2_1_to_router_1_1_rsp = router_2_1_rsp_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_rsp = router_2_1_rsp_out[4]; - - assign router_2_1_to_router_2_2_req = router_2_1_req_out[0]; - assign router_2_1_to_router_3_1_req = router_2_1_req_out[1]; - assign router_2_1_to_router_2_0_req = router_2_1_req_out[2]; - assign router_2_1_to_router_1_1_req = router_2_1_req_out[3]; - assign router_2_1_to_magia_tile_ni_2_1_req = router_2_1_req_out[4]; - - assign router_2_1_rsp_in[0] = router_2_2_to_router_2_1_rsp; - assign router_2_1_rsp_in[1] = router_3_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[2] = router_2_0_to_router_2_1_rsp; - assign router_2_1_rsp_in[3] = router_1_1_to_router_2_1_rsp; - assign router_2_1_rsp_in[4] = magia_tile_ni_2_1_to_router_2_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_1_req_in), - .floo_rsp_o (router_2_1_rsp_out), - .floo_req_o (router_2_1_req_out), - .floo_rsp_i (router_2_1_rsp_in) -); - - -floo_req_t [4:0] router_2_2_req_in; -floo_rsp_t [4:0] router_2_2_rsp_out; -floo_req_t [4:0] router_2_2_req_out; -floo_rsp_t [4:0] router_2_2_rsp_in; - - assign router_2_2_req_in[0] = router_2_3_to_router_2_2_req; - assign router_2_2_req_in[1] = router_3_2_to_router_2_2_req; - assign router_2_2_req_in[2] = router_2_1_to_router_2_2_req; - assign router_2_2_req_in[3] = router_1_2_to_router_2_2_req; - assign router_2_2_req_in[4] = magia_tile_ni_2_2_to_router_2_2_req; - - assign router_2_2_to_router_2_3_rsp = router_2_2_rsp_out[0]; - assign router_2_2_to_router_3_2_rsp = router_2_2_rsp_out[1]; - assign router_2_2_to_router_2_1_rsp = router_2_2_rsp_out[2]; - assign router_2_2_to_router_1_2_rsp = router_2_2_rsp_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_rsp = router_2_2_rsp_out[4]; - - assign router_2_2_to_router_2_3_req = router_2_2_req_out[0]; - assign router_2_2_to_router_3_2_req = router_2_2_req_out[1]; - assign router_2_2_to_router_2_1_req = router_2_2_req_out[2]; - assign router_2_2_to_router_1_2_req = router_2_2_req_out[3]; - assign router_2_2_to_magia_tile_ni_2_2_req = router_2_2_req_out[4]; - - assign router_2_2_rsp_in[0] = router_2_3_to_router_2_2_rsp; - assign router_2_2_rsp_in[1] = router_3_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[2] = router_2_1_to_router_2_2_rsp; - assign router_2_2_rsp_in[3] = router_1_2_to_router_2_2_rsp; - assign router_2_2_rsp_in[4] = magia_tile_ni_2_2_to_router_2_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_2_req_in), - .floo_rsp_o (router_2_2_rsp_out), - .floo_req_o (router_2_2_req_out), - .floo_rsp_i (router_2_2_rsp_in) -); - - -floo_req_t [4:0] router_2_3_req_in; -floo_rsp_t [4:0] router_2_3_rsp_out; -floo_req_t [4:0] router_2_3_req_out; -floo_rsp_t [4:0] router_2_3_rsp_in; - - assign router_2_3_req_in[0] = router_2_4_to_router_2_3_req; - assign router_2_3_req_in[1] = router_3_3_to_router_2_3_req; - assign router_2_3_req_in[2] = router_2_2_to_router_2_3_req; - assign router_2_3_req_in[3] = router_1_3_to_router_2_3_req; - assign router_2_3_req_in[4] = magia_tile_ni_2_3_to_router_2_3_req; - - assign router_2_3_to_router_2_4_rsp = router_2_3_rsp_out[0]; - assign router_2_3_to_router_3_3_rsp = router_2_3_rsp_out[1]; - assign router_2_3_to_router_2_2_rsp = router_2_3_rsp_out[2]; - assign router_2_3_to_router_1_3_rsp = router_2_3_rsp_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_rsp = router_2_3_rsp_out[4]; - - assign router_2_3_to_router_2_4_req = router_2_3_req_out[0]; - assign router_2_3_to_router_3_3_req = router_2_3_req_out[1]; - assign router_2_3_to_router_2_2_req = router_2_3_req_out[2]; - assign router_2_3_to_router_1_3_req = router_2_3_req_out[3]; - assign router_2_3_to_magia_tile_ni_2_3_req = router_2_3_req_out[4]; - - assign router_2_3_rsp_in[0] = router_2_4_to_router_2_3_rsp; - assign router_2_3_rsp_in[1] = router_3_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[2] = router_2_2_to_router_2_3_rsp; - assign router_2_3_rsp_in[3] = router_1_3_to_router_2_3_rsp; - assign router_2_3_rsp_in[4] = magia_tile_ni_2_3_to_router_2_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_3_req_in), - .floo_rsp_o (router_2_3_rsp_out), - .floo_req_o (router_2_3_req_out), - .floo_rsp_i (router_2_3_rsp_in) -); - - -floo_req_t [4:0] router_2_4_req_in; -floo_rsp_t [4:0] router_2_4_rsp_out; -floo_req_t [4:0] router_2_4_req_out; -floo_rsp_t [4:0] router_2_4_rsp_in; - - assign router_2_4_req_in[0] = router_2_5_to_router_2_4_req; - assign router_2_4_req_in[1] = router_3_4_to_router_2_4_req; - assign router_2_4_req_in[2] = router_2_3_to_router_2_4_req; - assign router_2_4_req_in[3] = router_1_4_to_router_2_4_req; - assign router_2_4_req_in[4] = magia_tile_ni_2_4_to_router_2_4_req; - - assign router_2_4_to_router_2_5_rsp = router_2_4_rsp_out[0]; - assign router_2_4_to_router_3_4_rsp = router_2_4_rsp_out[1]; - assign router_2_4_to_router_2_3_rsp = router_2_4_rsp_out[2]; - assign router_2_4_to_router_1_4_rsp = router_2_4_rsp_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_rsp = router_2_4_rsp_out[4]; - - assign router_2_4_to_router_2_5_req = router_2_4_req_out[0]; - assign router_2_4_to_router_3_4_req = router_2_4_req_out[1]; - assign router_2_4_to_router_2_3_req = router_2_4_req_out[2]; - assign router_2_4_to_router_1_4_req = router_2_4_req_out[3]; - assign router_2_4_to_magia_tile_ni_2_4_req = router_2_4_req_out[4]; - - assign router_2_4_rsp_in[0] = router_2_5_to_router_2_4_rsp; - assign router_2_4_rsp_in[1] = router_3_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[2] = router_2_3_to_router_2_4_rsp; - assign router_2_4_rsp_in[3] = router_1_4_to_router_2_4_rsp; - assign router_2_4_rsp_in[4] = magia_tile_ni_2_4_to_router_2_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_4_req_in), - .floo_rsp_o (router_2_4_rsp_out), - .floo_req_o (router_2_4_req_out), - .floo_rsp_i (router_2_4_rsp_in) -); - - -floo_req_t [4:0] router_2_5_req_in; -floo_rsp_t [4:0] router_2_5_rsp_out; -floo_req_t [4:0] router_2_5_req_out; -floo_rsp_t [4:0] router_2_5_rsp_in; - - assign router_2_5_req_in[0] = router_2_6_to_router_2_5_req; - assign router_2_5_req_in[1] = router_3_5_to_router_2_5_req; - assign router_2_5_req_in[2] = router_2_4_to_router_2_5_req; - assign router_2_5_req_in[3] = router_1_5_to_router_2_5_req; - assign router_2_5_req_in[4] = magia_tile_ni_2_5_to_router_2_5_req; - - assign router_2_5_to_router_2_6_rsp = router_2_5_rsp_out[0]; - assign router_2_5_to_router_3_5_rsp = router_2_5_rsp_out[1]; - assign router_2_5_to_router_2_4_rsp = router_2_5_rsp_out[2]; - assign router_2_5_to_router_1_5_rsp = router_2_5_rsp_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_rsp = router_2_5_rsp_out[4]; - - assign router_2_5_to_router_2_6_req = router_2_5_req_out[0]; - assign router_2_5_to_router_3_5_req = router_2_5_req_out[1]; - assign router_2_5_to_router_2_4_req = router_2_5_req_out[2]; - assign router_2_5_to_router_1_5_req = router_2_5_req_out[3]; - assign router_2_5_to_magia_tile_ni_2_5_req = router_2_5_req_out[4]; - - assign router_2_5_rsp_in[0] = router_2_6_to_router_2_5_rsp; - assign router_2_5_rsp_in[1] = router_3_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[2] = router_2_4_to_router_2_5_rsp; - assign router_2_5_rsp_in[3] = router_1_5_to_router_2_5_rsp; - assign router_2_5_rsp_in[4] = magia_tile_ni_2_5_to_router_2_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_5_req_in), - .floo_rsp_o (router_2_5_rsp_out), - .floo_req_o (router_2_5_req_out), - .floo_rsp_i (router_2_5_rsp_in) -); - - -floo_req_t [4:0] router_2_6_req_in; -floo_rsp_t [4:0] router_2_6_rsp_out; -floo_req_t [4:0] router_2_6_req_out; -floo_rsp_t [4:0] router_2_6_rsp_in; - - assign router_2_6_req_in[0] = router_2_7_to_router_2_6_req; - assign router_2_6_req_in[1] = router_3_6_to_router_2_6_req; - assign router_2_6_req_in[2] = router_2_5_to_router_2_6_req; - assign router_2_6_req_in[3] = router_1_6_to_router_2_6_req; - assign router_2_6_req_in[4] = magia_tile_ni_2_6_to_router_2_6_req; - - assign router_2_6_to_router_2_7_rsp = router_2_6_rsp_out[0]; - assign router_2_6_to_router_3_6_rsp = router_2_6_rsp_out[1]; - assign router_2_6_to_router_2_5_rsp = router_2_6_rsp_out[2]; - assign router_2_6_to_router_1_6_rsp = router_2_6_rsp_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_rsp = router_2_6_rsp_out[4]; - - assign router_2_6_to_router_2_7_req = router_2_6_req_out[0]; - assign router_2_6_to_router_3_6_req = router_2_6_req_out[1]; - assign router_2_6_to_router_2_5_req = router_2_6_req_out[2]; - assign router_2_6_to_router_1_6_req = router_2_6_req_out[3]; - assign router_2_6_to_magia_tile_ni_2_6_req = router_2_6_req_out[4]; - - assign router_2_6_rsp_in[0] = router_2_7_to_router_2_6_rsp; - assign router_2_6_rsp_in[1] = router_3_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[2] = router_2_5_to_router_2_6_rsp; - assign router_2_6_rsp_in[3] = router_1_6_to_router_2_6_rsp; - assign router_2_6_rsp_in[4] = magia_tile_ni_2_6_to_router_2_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_6_req_in), - .floo_rsp_o (router_2_6_rsp_out), - .floo_req_o (router_2_6_req_out), - .floo_rsp_i (router_2_6_rsp_in) -); - - -floo_req_t [4:0] router_2_7_req_in; -floo_rsp_t [4:0] router_2_7_rsp_out; -floo_req_t [4:0] router_2_7_req_out; -floo_rsp_t [4:0] router_2_7_rsp_in; - - assign router_2_7_req_in[0] = '0; - assign router_2_7_req_in[1] = router_3_7_to_router_2_7_req; - assign router_2_7_req_in[2] = router_2_6_to_router_2_7_req; - assign router_2_7_req_in[3] = router_1_7_to_router_2_7_req; - assign router_2_7_req_in[4] = magia_tile_ni_2_7_to_router_2_7_req; - - assign router_2_7_to_router_3_7_rsp = router_2_7_rsp_out[1]; - assign router_2_7_to_router_2_6_rsp = router_2_7_rsp_out[2]; - assign router_2_7_to_router_1_7_rsp = router_2_7_rsp_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_rsp = router_2_7_rsp_out[4]; - - assign router_2_7_to_router_3_7_req = router_2_7_req_out[1]; - assign router_2_7_to_router_2_6_req = router_2_7_req_out[2]; - assign router_2_7_to_router_1_7_req = router_2_7_req_out[3]; - assign router_2_7_to_magia_tile_ni_2_7_req = router_2_7_req_out[4]; - - assign router_2_7_rsp_in[0] = '0; - assign router_2_7_rsp_in[1] = router_3_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[2] = router_2_6_to_router_2_7_rsp; - assign router_2_7_rsp_in[3] = router_1_7_to_router_2_7_rsp; - assign router_2_7_rsp_in[4] = magia_tile_ni_2_7_to_router_2_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_2_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 3, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_2_7_req_in), - .floo_rsp_o (router_2_7_rsp_out), - .floo_req_o (router_2_7_req_out), - .floo_rsp_i (router_2_7_rsp_in) -); - - -floo_req_t [4:0] router_3_0_req_in; -floo_rsp_t [4:0] router_3_0_rsp_out; -floo_req_t [4:0] router_3_0_req_out; -floo_rsp_t [4:0] router_3_0_rsp_in; - - assign router_3_0_req_in[0] = router_3_1_to_router_3_0_req; - assign router_3_0_req_in[1] = router_4_0_to_router_3_0_req; - assign router_3_0_req_in[2] = '0; - assign router_3_0_req_in[3] = router_2_0_to_router_3_0_req; - assign router_3_0_req_in[4] = magia_tile_ni_3_0_to_router_3_0_req; - - assign router_3_0_to_router_3_1_rsp = router_3_0_rsp_out[0]; - assign router_3_0_to_router_4_0_rsp = router_3_0_rsp_out[1]; - assign router_3_0_to_router_2_0_rsp = router_3_0_rsp_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_rsp = router_3_0_rsp_out[4]; - - assign router_3_0_to_router_3_1_req = router_3_0_req_out[0]; - assign router_3_0_to_router_4_0_req = router_3_0_req_out[1]; - assign router_3_0_to_router_2_0_req = router_3_0_req_out[3]; - assign router_3_0_to_magia_tile_ni_3_0_req = router_3_0_req_out[4]; - - assign router_3_0_rsp_in[0] = router_3_1_to_router_3_0_rsp; - assign router_3_0_rsp_in[1] = router_4_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[2] = '0; - assign router_3_0_rsp_in[3] = router_2_0_to_router_3_0_rsp; - assign router_3_0_rsp_in[4] = magia_tile_ni_3_0_to_router_3_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_0_req_in), - .floo_rsp_o (router_3_0_rsp_out), - .floo_req_o (router_3_0_req_out), - .floo_rsp_i (router_3_0_rsp_in) -); - - -floo_req_t [4:0] router_3_1_req_in; -floo_rsp_t [4:0] router_3_1_rsp_out; -floo_req_t [4:0] router_3_1_req_out; -floo_rsp_t [4:0] router_3_1_rsp_in; - - assign router_3_1_req_in[0] = router_3_2_to_router_3_1_req; - assign router_3_1_req_in[1] = router_4_1_to_router_3_1_req; - assign router_3_1_req_in[2] = router_3_0_to_router_3_1_req; - assign router_3_1_req_in[3] = router_2_1_to_router_3_1_req; - assign router_3_1_req_in[4] = magia_tile_ni_3_1_to_router_3_1_req; - - assign router_3_1_to_router_3_2_rsp = router_3_1_rsp_out[0]; - assign router_3_1_to_router_4_1_rsp = router_3_1_rsp_out[1]; - assign router_3_1_to_router_3_0_rsp = router_3_1_rsp_out[2]; - assign router_3_1_to_router_2_1_rsp = router_3_1_rsp_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_rsp = router_3_1_rsp_out[4]; - - assign router_3_1_to_router_3_2_req = router_3_1_req_out[0]; - assign router_3_1_to_router_4_1_req = router_3_1_req_out[1]; - assign router_3_1_to_router_3_0_req = router_3_1_req_out[2]; - assign router_3_1_to_router_2_1_req = router_3_1_req_out[3]; - assign router_3_1_to_magia_tile_ni_3_1_req = router_3_1_req_out[4]; - - assign router_3_1_rsp_in[0] = router_3_2_to_router_3_1_rsp; - assign router_3_1_rsp_in[1] = router_4_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[2] = router_3_0_to_router_3_1_rsp; - assign router_3_1_rsp_in[3] = router_2_1_to_router_3_1_rsp; - assign router_3_1_rsp_in[4] = magia_tile_ni_3_1_to_router_3_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_1_req_in), - .floo_rsp_o (router_3_1_rsp_out), - .floo_req_o (router_3_1_req_out), - .floo_rsp_i (router_3_1_rsp_in) -); - - -floo_req_t [4:0] router_3_2_req_in; -floo_rsp_t [4:0] router_3_2_rsp_out; -floo_req_t [4:0] router_3_2_req_out; -floo_rsp_t [4:0] router_3_2_rsp_in; - - assign router_3_2_req_in[0] = router_3_3_to_router_3_2_req; - assign router_3_2_req_in[1] = router_4_2_to_router_3_2_req; - assign router_3_2_req_in[2] = router_3_1_to_router_3_2_req; - assign router_3_2_req_in[3] = router_2_2_to_router_3_2_req; - assign router_3_2_req_in[4] = magia_tile_ni_3_2_to_router_3_2_req; - - assign router_3_2_to_router_3_3_rsp = router_3_2_rsp_out[0]; - assign router_3_2_to_router_4_2_rsp = router_3_2_rsp_out[1]; - assign router_3_2_to_router_3_1_rsp = router_3_2_rsp_out[2]; - assign router_3_2_to_router_2_2_rsp = router_3_2_rsp_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_rsp = router_3_2_rsp_out[4]; - - assign router_3_2_to_router_3_3_req = router_3_2_req_out[0]; - assign router_3_2_to_router_4_2_req = router_3_2_req_out[1]; - assign router_3_2_to_router_3_1_req = router_3_2_req_out[2]; - assign router_3_2_to_router_2_2_req = router_3_2_req_out[3]; - assign router_3_2_to_magia_tile_ni_3_2_req = router_3_2_req_out[4]; - - assign router_3_2_rsp_in[0] = router_3_3_to_router_3_2_rsp; - assign router_3_2_rsp_in[1] = router_4_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[2] = router_3_1_to_router_3_2_rsp; - assign router_3_2_rsp_in[3] = router_2_2_to_router_3_2_rsp; - assign router_3_2_rsp_in[4] = magia_tile_ni_3_2_to_router_3_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_2_req_in), - .floo_rsp_o (router_3_2_rsp_out), - .floo_req_o (router_3_2_req_out), - .floo_rsp_i (router_3_2_rsp_in) -); - - -floo_req_t [4:0] router_3_3_req_in; -floo_rsp_t [4:0] router_3_3_rsp_out; -floo_req_t [4:0] router_3_3_req_out; -floo_rsp_t [4:0] router_3_3_rsp_in; - - assign router_3_3_req_in[0] = router_3_4_to_router_3_3_req; - assign router_3_3_req_in[1] = router_4_3_to_router_3_3_req; - assign router_3_3_req_in[2] = router_3_2_to_router_3_3_req; - assign router_3_3_req_in[3] = router_2_3_to_router_3_3_req; - assign router_3_3_req_in[4] = magia_tile_ni_3_3_to_router_3_3_req; - - assign router_3_3_to_router_3_4_rsp = router_3_3_rsp_out[0]; - assign router_3_3_to_router_4_3_rsp = router_3_3_rsp_out[1]; - assign router_3_3_to_router_3_2_rsp = router_3_3_rsp_out[2]; - assign router_3_3_to_router_2_3_rsp = router_3_3_rsp_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_rsp = router_3_3_rsp_out[4]; - - assign router_3_3_to_router_3_4_req = router_3_3_req_out[0]; - assign router_3_3_to_router_4_3_req = router_3_3_req_out[1]; - assign router_3_3_to_router_3_2_req = router_3_3_req_out[2]; - assign router_3_3_to_router_2_3_req = router_3_3_req_out[3]; - assign router_3_3_to_magia_tile_ni_3_3_req = router_3_3_req_out[4]; - - assign router_3_3_rsp_in[0] = router_3_4_to_router_3_3_rsp; - assign router_3_3_rsp_in[1] = router_4_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[2] = router_3_2_to_router_3_3_rsp; - assign router_3_3_rsp_in[3] = router_2_3_to_router_3_3_rsp; - assign router_3_3_rsp_in[4] = magia_tile_ni_3_3_to_router_3_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_3_req_in), - .floo_rsp_o (router_3_3_rsp_out), - .floo_req_o (router_3_3_req_out), - .floo_rsp_i (router_3_3_rsp_in) -); - - -floo_req_t [4:0] router_3_4_req_in; -floo_rsp_t [4:0] router_3_4_rsp_out; -floo_req_t [4:0] router_3_4_req_out; -floo_rsp_t [4:0] router_3_4_rsp_in; - - assign router_3_4_req_in[0] = router_3_5_to_router_3_4_req; - assign router_3_4_req_in[1] = router_4_4_to_router_3_4_req; - assign router_3_4_req_in[2] = router_3_3_to_router_3_4_req; - assign router_3_4_req_in[3] = router_2_4_to_router_3_4_req; - assign router_3_4_req_in[4] = magia_tile_ni_3_4_to_router_3_4_req; - - assign router_3_4_to_router_3_5_rsp = router_3_4_rsp_out[0]; - assign router_3_4_to_router_4_4_rsp = router_3_4_rsp_out[1]; - assign router_3_4_to_router_3_3_rsp = router_3_4_rsp_out[2]; - assign router_3_4_to_router_2_4_rsp = router_3_4_rsp_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_rsp = router_3_4_rsp_out[4]; - - assign router_3_4_to_router_3_5_req = router_3_4_req_out[0]; - assign router_3_4_to_router_4_4_req = router_3_4_req_out[1]; - assign router_3_4_to_router_3_3_req = router_3_4_req_out[2]; - assign router_3_4_to_router_2_4_req = router_3_4_req_out[3]; - assign router_3_4_to_magia_tile_ni_3_4_req = router_3_4_req_out[4]; - - assign router_3_4_rsp_in[0] = router_3_5_to_router_3_4_rsp; - assign router_3_4_rsp_in[1] = router_4_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[2] = router_3_3_to_router_3_4_rsp; - assign router_3_4_rsp_in[3] = router_2_4_to_router_3_4_rsp; - assign router_3_4_rsp_in[4] = magia_tile_ni_3_4_to_router_3_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_4_req_in), - .floo_rsp_o (router_3_4_rsp_out), - .floo_req_o (router_3_4_req_out), - .floo_rsp_i (router_3_4_rsp_in) -); - - -floo_req_t [4:0] router_3_5_req_in; -floo_rsp_t [4:0] router_3_5_rsp_out; -floo_req_t [4:0] router_3_5_req_out; -floo_rsp_t [4:0] router_3_5_rsp_in; - - assign router_3_5_req_in[0] = router_3_6_to_router_3_5_req; - assign router_3_5_req_in[1] = router_4_5_to_router_3_5_req; - assign router_3_5_req_in[2] = router_3_4_to_router_3_5_req; - assign router_3_5_req_in[3] = router_2_5_to_router_3_5_req; - assign router_3_5_req_in[4] = magia_tile_ni_3_5_to_router_3_5_req; - - assign router_3_5_to_router_3_6_rsp = router_3_5_rsp_out[0]; - assign router_3_5_to_router_4_5_rsp = router_3_5_rsp_out[1]; - assign router_3_5_to_router_3_4_rsp = router_3_5_rsp_out[2]; - assign router_3_5_to_router_2_5_rsp = router_3_5_rsp_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_rsp = router_3_5_rsp_out[4]; - - assign router_3_5_to_router_3_6_req = router_3_5_req_out[0]; - assign router_3_5_to_router_4_5_req = router_3_5_req_out[1]; - assign router_3_5_to_router_3_4_req = router_3_5_req_out[2]; - assign router_3_5_to_router_2_5_req = router_3_5_req_out[3]; - assign router_3_5_to_magia_tile_ni_3_5_req = router_3_5_req_out[4]; - - assign router_3_5_rsp_in[0] = router_3_6_to_router_3_5_rsp; - assign router_3_5_rsp_in[1] = router_4_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[2] = router_3_4_to_router_3_5_rsp; - assign router_3_5_rsp_in[3] = router_2_5_to_router_3_5_rsp; - assign router_3_5_rsp_in[4] = magia_tile_ni_3_5_to_router_3_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_5_req_in), - .floo_rsp_o (router_3_5_rsp_out), - .floo_req_o (router_3_5_req_out), - .floo_rsp_i (router_3_5_rsp_in) -); - - -floo_req_t [4:0] router_3_6_req_in; -floo_rsp_t [4:0] router_3_6_rsp_out; -floo_req_t [4:0] router_3_6_req_out; -floo_rsp_t [4:0] router_3_6_rsp_in; - - assign router_3_6_req_in[0] = router_3_7_to_router_3_6_req; - assign router_3_6_req_in[1] = router_4_6_to_router_3_6_req; - assign router_3_6_req_in[2] = router_3_5_to_router_3_6_req; - assign router_3_6_req_in[3] = router_2_6_to_router_3_6_req; - assign router_3_6_req_in[4] = magia_tile_ni_3_6_to_router_3_6_req; - - assign router_3_6_to_router_3_7_rsp = router_3_6_rsp_out[0]; - assign router_3_6_to_router_4_6_rsp = router_3_6_rsp_out[1]; - assign router_3_6_to_router_3_5_rsp = router_3_6_rsp_out[2]; - assign router_3_6_to_router_2_6_rsp = router_3_6_rsp_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_rsp = router_3_6_rsp_out[4]; - - assign router_3_6_to_router_3_7_req = router_3_6_req_out[0]; - assign router_3_6_to_router_4_6_req = router_3_6_req_out[1]; - assign router_3_6_to_router_3_5_req = router_3_6_req_out[2]; - assign router_3_6_to_router_2_6_req = router_3_6_req_out[3]; - assign router_3_6_to_magia_tile_ni_3_6_req = router_3_6_req_out[4]; - - assign router_3_6_rsp_in[0] = router_3_7_to_router_3_6_rsp; - assign router_3_6_rsp_in[1] = router_4_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[2] = router_3_5_to_router_3_6_rsp; - assign router_3_6_rsp_in[3] = router_2_6_to_router_3_6_rsp; - assign router_3_6_rsp_in[4] = magia_tile_ni_3_6_to_router_3_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_6_req_in), - .floo_rsp_o (router_3_6_rsp_out), - .floo_req_o (router_3_6_req_out), - .floo_rsp_i (router_3_6_rsp_in) -); - - -floo_req_t [4:0] router_3_7_req_in; -floo_rsp_t [4:0] router_3_7_rsp_out; -floo_req_t [4:0] router_3_7_req_out; -floo_rsp_t [4:0] router_3_7_rsp_in; - - assign router_3_7_req_in[0] = '0; - assign router_3_7_req_in[1] = router_4_7_to_router_3_7_req; - assign router_3_7_req_in[2] = router_3_6_to_router_3_7_req; - assign router_3_7_req_in[3] = router_2_7_to_router_3_7_req; - assign router_3_7_req_in[4] = magia_tile_ni_3_7_to_router_3_7_req; - - assign router_3_7_to_router_4_7_rsp = router_3_7_rsp_out[1]; - assign router_3_7_to_router_3_6_rsp = router_3_7_rsp_out[2]; - assign router_3_7_to_router_2_7_rsp = router_3_7_rsp_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_rsp = router_3_7_rsp_out[4]; - - assign router_3_7_to_router_4_7_req = router_3_7_req_out[1]; - assign router_3_7_to_router_3_6_req = router_3_7_req_out[2]; - assign router_3_7_to_router_2_7_req = router_3_7_req_out[3]; - assign router_3_7_to_magia_tile_ni_3_7_req = router_3_7_req_out[4]; - - assign router_3_7_rsp_in[0] = '0; - assign router_3_7_rsp_in[1] = router_4_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[2] = router_3_6_to_router_3_7_rsp; - assign router_3_7_rsp_in[3] = router_2_7_to_router_3_7_rsp; - assign router_3_7_rsp_in[4] = magia_tile_ni_3_7_to_router_3_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_3_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 4, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_3_7_req_in), - .floo_rsp_o (router_3_7_rsp_out), - .floo_req_o (router_3_7_req_out), - .floo_rsp_i (router_3_7_rsp_in) -); - - -floo_req_t [4:0] router_4_0_req_in; -floo_rsp_t [4:0] router_4_0_rsp_out; -floo_req_t [4:0] router_4_0_req_out; -floo_rsp_t [4:0] router_4_0_rsp_in; - - assign router_4_0_req_in[0] = router_4_1_to_router_4_0_req; - assign router_4_0_req_in[1] = router_5_0_to_router_4_0_req; - assign router_4_0_req_in[2] = '0; - assign router_4_0_req_in[3] = router_3_0_to_router_4_0_req; - assign router_4_0_req_in[4] = magia_tile_ni_4_0_to_router_4_0_req; - - assign router_4_0_to_router_4_1_rsp = router_4_0_rsp_out[0]; - assign router_4_0_to_router_5_0_rsp = router_4_0_rsp_out[1]; - assign router_4_0_to_router_3_0_rsp = router_4_0_rsp_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_rsp = router_4_0_rsp_out[4]; - - assign router_4_0_to_router_4_1_req = router_4_0_req_out[0]; - assign router_4_0_to_router_5_0_req = router_4_0_req_out[1]; - assign router_4_0_to_router_3_0_req = router_4_0_req_out[3]; - assign router_4_0_to_magia_tile_ni_4_0_req = router_4_0_req_out[4]; - - assign router_4_0_rsp_in[0] = router_4_1_to_router_4_0_rsp; - assign router_4_0_rsp_in[1] = router_5_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[2] = '0; - assign router_4_0_rsp_in[3] = router_3_0_to_router_4_0_rsp; - assign router_4_0_rsp_in[4] = magia_tile_ni_4_0_to_router_4_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_0_req_in), - .floo_rsp_o (router_4_0_rsp_out), - .floo_req_o (router_4_0_req_out), - .floo_rsp_i (router_4_0_rsp_in) -); - - -floo_req_t [4:0] router_4_1_req_in; -floo_rsp_t [4:0] router_4_1_rsp_out; -floo_req_t [4:0] router_4_1_req_out; -floo_rsp_t [4:0] router_4_1_rsp_in; - - assign router_4_1_req_in[0] = router_4_2_to_router_4_1_req; - assign router_4_1_req_in[1] = router_5_1_to_router_4_1_req; - assign router_4_1_req_in[2] = router_4_0_to_router_4_1_req; - assign router_4_1_req_in[3] = router_3_1_to_router_4_1_req; - assign router_4_1_req_in[4] = magia_tile_ni_4_1_to_router_4_1_req; - - assign router_4_1_to_router_4_2_rsp = router_4_1_rsp_out[0]; - assign router_4_1_to_router_5_1_rsp = router_4_1_rsp_out[1]; - assign router_4_1_to_router_4_0_rsp = router_4_1_rsp_out[2]; - assign router_4_1_to_router_3_1_rsp = router_4_1_rsp_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_rsp = router_4_1_rsp_out[4]; - - assign router_4_1_to_router_4_2_req = router_4_1_req_out[0]; - assign router_4_1_to_router_5_1_req = router_4_1_req_out[1]; - assign router_4_1_to_router_4_0_req = router_4_1_req_out[2]; - assign router_4_1_to_router_3_1_req = router_4_1_req_out[3]; - assign router_4_1_to_magia_tile_ni_4_1_req = router_4_1_req_out[4]; - - assign router_4_1_rsp_in[0] = router_4_2_to_router_4_1_rsp; - assign router_4_1_rsp_in[1] = router_5_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[2] = router_4_0_to_router_4_1_rsp; - assign router_4_1_rsp_in[3] = router_3_1_to_router_4_1_rsp; - assign router_4_1_rsp_in[4] = magia_tile_ni_4_1_to_router_4_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_1_req_in), - .floo_rsp_o (router_4_1_rsp_out), - .floo_req_o (router_4_1_req_out), - .floo_rsp_i (router_4_1_rsp_in) -); - - -floo_req_t [4:0] router_4_2_req_in; -floo_rsp_t [4:0] router_4_2_rsp_out; -floo_req_t [4:0] router_4_2_req_out; -floo_rsp_t [4:0] router_4_2_rsp_in; - - assign router_4_2_req_in[0] = router_4_3_to_router_4_2_req; - assign router_4_2_req_in[1] = router_5_2_to_router_4_2_req; - assign router_4_2_req_in[2] = router_4_1_to_router_4_2_req; - assign router_4_2_req_in[3] = router_3_2_to_router_4_2_req; - assign router_4_2_req_in[4] = magia_tile_ni_4_2_to_router_4_2_req; - - assign router_4_2_to_router_4_3_rsp = router_4_2_rsp_out[0]; - assign router_4_2_to_router_5_2_rsp = router_4_2_rsp_out[1]; - assign router_4_2_to_router_4_1_rsp = router_4_2_rsp_out[2]; - assign router_4_2_to_router_3_2_rsp = router_4_2_rsp_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_rsp = router_4_2_rsp_out[4]; - - assign router_4_2_to_router_4_3_req = router_4_2_req_out[0]; - assign router_4_2_to_router_5_2_req = router_4_2_req_out[1]; - assign router_4_2_to_router_4_1_req = router_4_2_req_out[2]; - assign router_4_2_to_router_3_2_req = router_4_2_req_out[3]; - assign router_4_2_to_magia_tile_ni_4_2_req = router_4_2_req_out[4]; - - assign router_4_2_rsp_in[0] = router_4_3_to_router_4_2_rsp; - assign router_4_2_rsp_in[1] = router_5_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[2] = router_4_1_to_router_4_2_rsp; - assign router_4_2_rsp_in[3] = router_3_2_to_router_4_2_rsp; - assign router_4_2_rsp_in[4] = magia_tile_ni_4_2_to_router_4_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_2_req_in), - .floo_rsp_o (router_4_2_rsp_out), - .floo_req_o (router_4_2_req_out), - .floo_rsp_i (router_4_2_rsp_in) -); - - -floo_req_t [4:0] router_4_3_req_in; -floo_rsp_t [4:0] router_4_3_rsp_out; -floo_req_t [4:0] router_4_3_req_out; -floo_rsp_t [4:0] router_4_3_rsp_in; - - assign router_4_3_req_in[0] = router_4_4_to_router_4_3_req; - assign router_4_3_req_in[1] = router_5_3_to_router_4_3_req; - assign router_4_3_req_in[2] = router_4_2_to_router_4_3_req; - assign router_4_3_req_in[3] = router_3_3_to_router_4_3_req; - assign router_4_3_req_in[4] = magia_tile_ni_4_3_to_router_4_3_req; - - assign router_4_3_to_router_4_4_rsp = router_4_3_rsp_out[0]; - assign router_4_3_to_router_5_3_rsp = router_4_3_rsp_out[1]; - assign router_4_3_to_router_4_2_rsp = router_4_3_rsp_out[2]; - assign router_4_3_to_router_3_3_rsp = router_4_3_rsp_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_rsp = router_4_3_rsp_out[4]; - - assign router_4_3_to_router_4_4_req = router_4_3_req_out[0]; - assign router_4_3_to_router_5_3_req = router_4_3_req_out[1]; - assign router_4_3_to_router_4_2_req = router_4_3_req_out[2]; - assign router_4_3_to_router_3_3_req = router_4_3_req_out[3]; - assign router_4_3_to_magia_tile_ni_4_3_req = router_4_3_req_out[4]; - - assign router_4_3_rsp_in[0] = router_4_4_to_router_4_3_rsp; - assign router_4_3_rsp_in[1] = router_5_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[2] = router_4_2_to_router_4_3_rsp; - assign router_4_3_rsp_in[3] = router_3_3_to_router_4_3_rsp; - assign router_4_3_rsp_in[4] = magia_tile_ni_4_3_to_router_4_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_3_req_in), - .floo_rsp_o (router_4_3_rsp_out), - .floo_req_o (router_4_3_req_out), - .floo_rsp_i (router_4_3_rsp_in) -); - - -floo_req_t [4:0] router_4_4_req_in; -floo_rsp_t [4:0] router_4_4_rsp_out; -floo_req_t [4:0] router_4_4_req_out; -floo_rsp_t [4:0] router_4_4_rsp_in; - - assign router_4_4_req_in[0] = router_4_5_to_router_4_4_req; - assign router_4_4_req_in[1] = router_5_4_to_router_4_4_req; - assign router_4_4_req_in[2] = router_4_3_to_router_4_4_req; - assign router_4_4_req_in[3] = router_3_4_to_router_4_4_req; - assign router_4_4_req_in[4] = magia_tile_ni_4_4_to_router_4_4_req; - - assign router_4_4_to_router_4_5_rsp = router_4_4_rsp_out[0]; - assign router_4_4_to_router_5_4_rsp = router_4_4_rsp_out[1]; - assign router_4_4_to_router_4_3_rsp = router_4_4_rsp_out[2]; - assign router_4_4_to_router_3_4_rsp = router_4_4_rsp_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_rsp = router_4_4_rsp_out[4]; - - assign router_4_4_to_router_4_5_req = router_4_4_req_out[0]; - assign router_4_4_to_router_5_4_req = router_4_4_req_out[1]; - assign router_4_4_to_router_4_3_req = router_4_4_req_out[2]; - assign router_4_4_to_router_3_4_req = router_4_4_req_out[3]; - assign router_4_4_to_magia_tile_ni_4_4_req = router_4_4_req_out[4]; - - assign router_4_4_rsp_in[0] = router_4_5_to_router_4_4_rsp; - assign router_4_4_rsp_in[1] = router_5_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[2] = router_4_3_to_router_4_4_rsp; - assign router_4_4_rsp_in[3] = router_3_4_to_router_4_4_rsp; - assign router_4_4_rsp_in[4] = magia_tile_ni_4_4_to_router_4_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_4_req_in), - .floo_rsp_o (router_4_4_rsp_out), - .floo_req_o (router_4_4_req_out), - .floo_rsp_i (router_4_4_rsp_in) -); - - -floo_req_t [4:0] router_4_5_req_in; -floo_rsp_t [4:0] router_4_5_rsp_out; -floo_req_t [4:0] router_4_5_req_out; -floo_rsp_t [4:0] router_4_5_rsp_in; - - assign router_4_5_req_in[0] = router_4_6_to_router_4_5_req; - assign router_4_5_req_in[1] = router_5_5_to_router_4_5_req; - assign router_4_5_req_in[2] = router_4_4_to_router_4_5_req; - assign router_4_5_req_in[3] = router_3_5_to_router_4_5_req; - assign router_4_5_req_in[4] = magia_tile_ni_4_5_to_router_4_5_req; - - assign router_4_5_to_router_4_6_rsp = router_4_5_rsp_out[0]; - assign router_4_5_to_router_5_5_rsp = router_4_5_rsp_out[1]; - assign router_4_5_to_router_4_4_rsp = router_4_5_rsp_out[2]; - assign router_4_5_to_router_3_5_rsp = router_4_5_rsp_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_rsp = router_4_5_rsp_out[4]; - - assign router_4_5_to_router_4_6_req = router_4_5_req_out[0]; - assign router_4_5_to_router_5_5_req = router_4_5_req_out[1]; - assign router_4_5_to_router_4_4_req = router_4_5_req_out[2]; - assign router_4_5_to_router_3_5_req = router_4_5_req_out[3]; - assign router_4_5_to_magia_tile_ni_4_5_req = router_4_5_req_out[4]; - - assign router_4_5_rsp_in[0] = router_4_6_to_router_4_5_rsp; - assign router_4_5_rsp_in[1] = router_5_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[2] = router_4_4_to_router_4_5_rsp; - assign router_4_5_rsp_in[3] = router_3_5_to_router_4_5_rsp; - assign router_4_5_rsp_in[4] = magia_tile_ni_4_5_to_router_4_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_5_req_in), - .floo_rsp_o (router_4_5_rsp_out), - .floo_req_o (router_4_5_req_out), - .floo_rsp_i (router_4_5_rsp_in) -); - - -floo_req_t [4:0] router_4_6_req_in; -floo_rsp_t [4:0] router_4_6_rsp_out; -floo_req_t [4:0] router_4_6_req_out; -floo_rsp_t [4:0] router_4_6_rsp_in; - - assign router_4_6_req_in[0] = router_4_7_to_router_4_6_req; - assign router_4_6_req_in[1] = router_5_6_to_router_4_6_req; - assign router_4_6_req_in[2] = router_4_5_to_router_4_6_req; - assign router_4_6_req_in[3] = router_3_6_to_router_4_6_req; - assign router_4_6_req_in[4] = magia_tile_ni_4_6_to_router_4_6_req; - - assign router_4_6_to_router_4_7_rsp = router_4_6_rsp_out[0]; - assign router_4_6_to_router_5_6_rsp = router_4_6_rsp_out[1]; - assign router_4_6_to_router_4_5_rsp = router_4_6_rsp_out[2]; - assign router_4_6_to_router_3_6_rsp = router_4_6_rsp_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_rsp = router_4_6_rsp_out[4]; - - assign router_4_6_to_router_4_7_req = router_4_6_req_out[0]; - assign router_4_6_to_router_5_6_req = router_4_6_req_out[1]; - assign router_4_6_to_router_4_5_req = router_4_6_req_out[2]; - assign router_4_6_to_router_3_6_req = router_4_6_req_out[3]; - assign router_4_6_to_magia_tile_ni_4_6_req = router_4_6_req_out[4]; - - assign router_4_6_rsp_in[0] = router_4_7_to_router_4_6_rsp; - assign router_4_6_rsp_in[1] = router_5_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[2] = router_4_5_to_router_4_6_rsp; - assign router_4_6_rsp_in[3] = router_3_6_to_router_4_6_rsp; - assign router_4_6_rsp_in[4] = magia_tile_ni_4_6_to_router_4_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_6_req_in), - .floo_rsp_o (router_4_6_rsp_out), - .floo_req_o (router_4_6_req_out), - .floo_rsp_i (router_4_6_rsp_in) -); - - -floo_req_t [4:0] router_4_7_req_in; -floo_rsp_t [4:0] router_4_7_rsp_out; -floo_req_t [4:0] router_4_7_req_out; -floo_rsp_t [4:0] router_4_7_rsp_in; - - assign router_4_7_req_in[0] = '0; - assign router_4_7_req_in[1] = router_5_7_to_router_4_7_req; - assign router_4_7_req_in[2] = router_4_6_to_router_4_7_req; - assign router_4_7_req_in[3] = router_3_7_to_router_4_7_req; - assign router_4_7_req_in[4] = magia_tile_ni_4_7_to_router_4_7_req; - - assign router_4_7_to_router_5_7_rsp = router_4_7_rsp_out[1]; - assign router_4_7_to_router_4_6_rsp = router_4_7_rsp_out[2]; - assign router_4_7_to_router_3_7_rsp = router_4_7_rsp_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_rsp = router_4_7_rsp_out[4]; - - assign router_4_7_to_router_5_7_req = router_4_7_req_out[1]; - assign router_4_7_to_router_4_6_req = router_4_7_req_out[2]; - assign router_4_7_to_router_3_7_req = router_4_7_req_out[3]; - assign router_4_7_to_magia_tile_ni_4_7_req = router_4_7_req_out[4]; - - assign router_4_7_rsp_in[0] = '0; - assign router_4_7_rsp_in[1] = router_5_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[2] = router_4_6_to_router_4_7_rsp; - assign router_4_7_rsp_in[3] = router_3_7_to_router_4_7_rsp; - assign router_4_7_rsp_in[4] = magia_tile_ni_4_7_to_router_4_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_4_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 5, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_4_7_req_in), - .floo_rsp_o (router_4_7_rsp_out), - .floo_req_o (router_4_7_req_out), - .floo_rsp_i (router_4_7_rsp_in) -); - - -floo_req_t [4:0] router_5_0_req_in; -floo_rsp_t [4:0] router_5_0_rsp_out; -floo_req_t [4:0] router_5_0_req_out; -floo_rsp_t [4:0] router_5_0_rsp_in; - - assign router_5_0_req_in[0] = router_5_1_to_router_5_0_req; - assign router_5_0_req_in[1] = router_6_0_to_router_5_0_req; - assign router_5_0_req_in[2] = '0; - assign router_5_0_req_in[3] = router_4_0_to_router_5_0_req; - assign router_5_0_req_in[4] = magia_tile_ni_5_0_to_router_5_0_req; - - assign router_5_0_to_router_5_1_rsp = router_5_0_rsp_out[0]; - assign router_5_0_to_router_6_0_rsp = router_5_0_rsp_out[1]; - assign router_5_0_to_router_4_0_rsp = router_5_0_rsp_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_rsp = router_5_0_rsp_out[4]; - - assign router_5_0_to_router_5_1_req = router_5_0_req_out[0]; - assign router_5_0_to_router_6_0_req = router_5_0_req_out[1]; - assign router_5_0_to_router_4_0_req = router_5_0_req_out[3]; - assign router_5_0_to_magia_tile_ni_5_0_req = router_5_0_req_out[4]; - - assign router_5_0_rsp_in[0] = router_5_1_to_router_5_0_rsp; - assign router_5_0_rsp_in[1] = router_6_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[2] = '0; - assign router_5_0_rsp_in[3] = router_4_0_to_router_5_0_rsp; - assign router_5_0_rsp_in[4] = magia_tile_ni_5_0_to_router_5_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_0_req_in), - .floo_rsp_o (router_5_0_rsp_out), - .floo_req_o (router_5_0_req_out), - .floo_rsp_i (router_5_0_rsp_in) -); - - -floo_req_t [4:0] router_5_1_req_in; -floo_rsp_t [4:0] router_5_1_rsp_out; -floo_req_t [4:0] router_5_1_req_out; -floo_rsp_t [4:0] router_5_1_rsp_in; - - assign router_5_1_req_in[0] = router_5_2_to_router_5_1_req; - assign router_5_1_req_in[1] = router_6_1_to_router_5_1_req; - assign router_5_1_req_in[2] = router_5_0_to_router_5_1_req; - assign router_5_1_req_in[3] = router_4_1_to_router_5_1_req; - assign router_5_1_req_in[4] = magia_tile_ni_5_1_to_router_5_1_req; - - assign router_5_1_to_router_5_2_rsp = router_5_1_rsp_out[0]; - assign router_5_1_to_router_6_1_rsp = router_5_1_rsp_out[1]; - assign router_5_1_to_router_5_0_rsp = router_5_1_rsp_out[2]; - assign router_5_1_to_router_4_1_rsp = router_5_1_rsp_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_rsp = router_5_1_rsp_out[4]; - - assign router_5_1_to_router_5_2_req = router_5_1_req_out[0]; - assign router_5_1_to_router_6_1_req = router_5_1_req_out[1]; - assign router_5_1_to_router_5_0_req = router_5_1_req_out[2]; - assign router_5_1_to_router_4_1_req = router_5_1_req_out[3]; - assign router_5_1_to_magia_tile_ni_5_1_req = router_5_1_req_out[4]; - - assign router_5_1_rsp_in[0] = router_5_2_to_router_5_1_rsp; - assign router_5_1_rsp_in[1] = router_6_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[2] = router_5_0_to_router_5_1_rsp; - assign router_5_1_rsp_in[3] = router_4_1_to_router_5_1_rsp; - assign router_5_1_rsp_in[4] = magia_tile_ni_5_1_to_router_5_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_1_req_in), - .floo_rsp_o (router_5_1_rsp_out), - .floo_req_o (router_5_1_req_out), - .floo_rsp_i (router_5_1_rsp_in) -); - - -floo_req_t [4:0] router_5_2_req_in; -floo_rsp_t [4:0] router_5_2_rsp_out; -floo_req_t [4:0] router_5_2_req_out; -floo_rsp_t [4:0] router_5_2_rsp_in; - - assign router_5_2_req_in[0] = router_5_3_to_router_5_2_req; - assign router_5_2_req_in[1] = router_6_2_to_router_5_2_req; - assign router_5_2_req_in[2] = router_5_1_to_router_5_2_req; - assign router_5_2_req_in[3] = router_4_2_to_router_5_2_req; - assign router_5_2_req_in[4] = magia_tile_ni_5_2_to_router_5_2_req; - - assign router_5_2_to_router_5_3_rsp = router_5_2_rsp_out[0]; - assign router_5_2_to_router_6_2_rsp = router_5_2_rsp_out[1]; - assign router_5_2_to_router_5_1_rsp = router_5_2_rsp_out[2]; - assign router_5_2_to_router_4_2_rsp = router_5_2_rsp_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_rsp = router_5_2_rsp_out[4]; - - assign router_5_2_to_router_5_3_req = router_5_2_req_out[0]; - assign router_5_2_to_router_6_2_req = router_5_2_req_out[1]; - assign router_5_2_to_router_5_1_req = router_5_2_req_out[2]; - assign router_5_2_to_router_4_2_req = router_5_2_req_out[3]; - assign router_5_2_to_magia_tile_ni_5_2_req = router_5_2_req_out[4]; - - assign router_5_2_rsp_in[0] = router_5_3_to_router_5_2_rsp; - assign router_5_2_rsp_in[1] = router_6_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[2] = router_5_1_to_router_5_2_rsp; - assign router_5_2_rsp_in[3] = router_4_2_to_router_5_2_rsp; - assign router_5_2_rsp_in[4] = magia_tile_ni_5_2_to_router_5_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_2_req_in), - .floo_rsp_o (router_5_2_rsp_out), - .floo_req_o (router_5_2_req_out), - .floo_rsp_i (router_5_2_rsp_in) -); - - -floo_req_t [4:0] router_5_3_req_in; -floo_rsp_t [4:0] router_5_3_rsp_out; -floo_req_t [4:0] router_5_3_req_out; -floo_rsp_t [4:0] router_5_3_rsp_in; - - assign router_5_3_req_in[0] = router_5_4_to_router_5_3_req; - assign router_5_3_req_in[1] = router_6_3_to_router_5_3_req; - assign router_5_3_req_in[2] = router_5_2_to_router_5_3_req; - assign router_5_3_req_in[3] = router_4_3_to_router_5_3_req; - assign router_5_3_req_in[4] = magia_tile_ni_5_3_to_router_5_3_req; - - assign router_5_3_to_router_5_4_rsp = router_5_3_rsp_out[0]; - assign router_5_3_to_router_6_3_rsp = router_5_3_rsp_out[1]; - assign router_5_3_to_router_5_2_rsp = router_5_3_rsp_out[2]; - assign router_5_3_to_router_4_3_rsp = router_5_3_rsp_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_rsp = router_5_3_rsp_out[4]; - - assign router_5_3_to_router_5_4_req = router_5_3_req_out[0]; - assign router_5_3_to_router_6_3_req = router_5_3_req_out[1]; - assign router_5_3_to_router_5_2_req = router_5_3_req_out[2]; - assign router_5_3_to_router_4_3_req = router_5_3_req_out[3]; - assign router_5_3_to_magia_tile_ni_5_3_req = router_5_3_req_out[4]; - - assign router_5_3_rsp_in[0] = router_5_4_to_router_5_3_rsp; - assign router_5_3_rsp_in[1] = router_6_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[2] = router_5_2_to_router_5_3_rsp; - assign router_5_3_rsp_in[3] = router_4_3_to_router_5_3_rsp; - assign router_5_3_rsp_in[4] = magia_tile_ni_5_3_to_router_5_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_3_req_in), - .floo_rsp_o (router_5_3_rsp_out), - .floo_req_o (router_5_3_req_out), - .floo_rsp_i (router_5_3_rsp_in) -); - - -floo_req_t [4:0] router_5_4_req_in; -floo_rsp_t [4:0] router_5_4_rsp_out; -floo_req_t [4:0] router_5_4_req_out; -floo_rsp_t [4:0] router_5_4_rsp_in; - - assign router_5_4_req_in[0] = router_5_5_to_router_5_4_req; - assign router_5_4_req_in[1] = router_6_4_to_router_5_4_req; - assign router_5_4_req_in[2] = router_5_3_to_router_5_4_req; - assign router_5_4_req_in[3] = router_4_4_to_router_5_4_req; - assign router_5_4_req_in[4] = magia_tile_ni_5_4_to_router_5_4_req; - - assign router_5_4_to_router_5_5_rsp = router_5_4_rsp_out[0]; - assign router_5_4_to_router_6_4_rsp = router_5_4_rsp_out[1]; - assign router_5_4_to_router_5_3_rsp = router_5_4_rsp_out[2]; - assign router_5_4_to_router_4_4_rsp = router_5_4_rsp_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_rsp = router_5_4_rsp_out[4]; - - assign router_5_4_to_router_5_5_req = router_5_4_req_out[0]; - assign router_5_4_to_router_6_4_req = router_5_4_req_out[1]; - assign router_5_4_to_router_5_3_req = router_5_4_req_out[2]; - assign router_5_4_to_router_4_4_req = router_5_4_req_out[3]; - assign router_5_4_to_magia_tile_ni_5_4_req = router_5_4_req_out[4]; - - assign router_5_4_rsp_in[0] = router_5_5_to_router_5_4_rsp; - assign router_5_4_rsp_in[1] = router_6_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[2] = router_5_3_to_router_5_4_rsp; - assign router_5_4_rsp_in[3] = router_4_4_to_router_5_4_rsp; - assign router_5_4_rsp_in[4] = magia_tile_ni_5_4_to_router_5_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_4_req_in), - .floo_rsp_o (router_5_4_rsp_out), - .floo_req_o (router_5_4_req_out), - .floo_rsp_i (router_5_4_rsp_in) -); - - -floo_req_t [4:0] router_5_5_req_in; -floo_rsp_t [4:0] router_5_5_rsp_out; -floo_req_t [4:0] router_5_5_req_out; -floo_rsp_t [4:0] router_5_5_rsp_in; - - assign router_5_5_req_in[0] = router_5_6_to_router_5_5_req; - assign router_5_5_req_in[1] = router_6_5_to_router_5_5_req; - assign router_5_5_req_in[2] = router_5_4_to_router_5_5_req; - assign router_5_5_req_in[3] = router_4_5_to_router_5_5_req; - assign router_5_5_req_in[4] = magia_tile_ni_5_5_to_router_5_5_req; - - assign router_5_5_to_router_5_6_rsp = router_5_5_rsp_out[0]; - assign router_5_5_to_router_6_5_rsp = router_5_5_rsp_out[1]; - assign router_5_5_to_router_5_4_rsp = router_5_5_rsp_out[2]; - assign router_5_5_to_router_4_5_rsp = router_5_5_rsp_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_rsp = router_5_5_rsp_out[4]; - - assign router_5_5_to_router_5_6_req = router_5_5_req_out[0]; - assign router_5_5_to_router_6_5_req = router_5_5_req_out[1]; - assign router_5_5_to_router_5_4_req = router_5_5_req_out[2]; - assign router_5_5_to_router_4_5_req = router_5_5_req_out[3]; - assign router_5_5_to_magia_tile_ni_5_5_req = router_5_5_req_out[4]; - - assign router_5_5_rsp_in[0] = router_5_6_to_router_5_5_rsp; - assign router_5_5_rsp_in[1] = router_6_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[2] = router_5_4_to_router_5_5_rsp; - assign router_5_5_rsp_in[3] = router_4_5_to_router_5_5_rsp; - assign router_5_5_rsp_in[4] = magia_tile_ni_5_5_to_router_5_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_5_req_in), - .floo_rsp_o (router_5_5_rsp_out), - .floo_req_o (router_5_5_req_out), - .floo_rsp_i (router_5_5_rsp_in) -); - - -floo_req_t [4:0] router_5_6_req_in; -floo_rsp_t [4:0] router_5_6_rsp_out; -floo_req_t [4:0] router_5_6_req_out; -floo_rsp_t [4:0] router_5_6_rsp_in; - - assign router_5_6_req_in[0] = router_5_7_to_router_5_6_req; - assign router_5_6_req_in[1] = router_6_6_to_router_5_6_req; - assign router_5_6_req_in[2] = router_5_5_to_router_5_6_req; - assign router_5_6_req_in[3] = router_4_6_to_router_5_6_req; - assign router_5_6_req_in[4] = magia_tile_ni_5_6_to_router_5_6_req; - - assign router_5_6_to_router_5_7_rsp = router_5_6_rsp_out[0]; - assign router_5_6_to_router_6_6_rsp = router_5_6_rsp_out[1]; - assign router_5_6_to_router_5_5_rsp = router_5_6_rsp_out[2]; - assign router_5_6_to_router_4_6_rsp = router_5_6_rsp_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_rsp = router_5_6_rsp_out[4]; - - assign router_5_6_to_router_5_7_req = router_5_6_req_out[0]; - assign router_5_6_to_router_6_6_req = router_5_6_req_out[1]; - assign router_5_6_to_router_5_5_req = router_5_6_req_out[2]; - assign router_5_6_to_router_4_6_req = router_5_6_req_out[3]; - assign router_5_6_to_magia_tile_ni_5_6_req = router_5_6_req_out[4]; - - assign router_5_6_rsp_in[0] = router_5_7_to_router_5_6_rsp; - assign router_5_6_rsp_in[1] = router_6_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[2] = router_5_5_to_router_5_6_rsp; - assign router_5_6_rsp_in[3] = router_4_6_to_router_5_6_rsp; - assign router_5_6_rsp_in[4] = magia_tile_ni_5_6_to_router_5_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_6_req_in), - .floo_rsp_o (router_5_6_rsp_out), - .floo_req_o (router_5_6_req_out), - .floo_rsp_i (router_5_6_rsp_in) -); - - -floo_req_t [4:0] router_5_7_req_in; -floo_rsp_t [4:0] router_5_7_rsp_out; -floo_req_t [4:0] router_5_7_req_out; -floo_rsp_t [4:0] router_5_7_rsp_in; - - assign router_5_7_req_in[0] = '0; - assign router_5_7_req_in[1] = router_6_7_to_router_5_7_req; - assign router_5_7_req_in[2] = router_5_6_to_router_5_7_req; - assign router_5_7_req_in[3] = router_4_7_to_router_5_7_req; - assign router_5_7_req_in[4] = magia_tile_ni_5_7_to_router_5_7_req; - - assign router_5_7_to_router_6_7_rsp = router_5_7_rsp_out[1]; - assign router_5_7_to_router_5_6_rsp = router_5_7_rsp_out[2]; - assign router_5_7_to_router_4_7_rsp = router_5_7_rsp_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_rsp = router_5_7_rsp_out[4]; - - assign router_5_7_to_router_6_7_req = router_5_7_req_out[1]; - assign router_5_7_to_router_5_6_req = router_5_7_req_out[2]; - assign router_5_7_to_router_4_7_req = router_5_7_req_out[3]; - assign router_5_7_to_magia_tile_ni_5_7_req = router_5_7_req_out[4]; - - assign router_5_7_rsp_in[0] = '0; - assign router_5_7_rsp_in[1] = router_6_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[2] = router_5_6_to_router_5_7_rsp; - assign router_5_7_rsp_in[3] = router_4_7_to_router_5_7_rsp; - assign router_5_7_rsp_in[4] = magia_tile_ni_5_7_to_router_5_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_5_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 6, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_5_7_req_in), - .floo_rsp_o (router_5_7_rsp_out), - .floo_req_o (router_5_7_req_out), - .floo_rsp_i (router_5_7_rsp_in) -); - - -floo_req_t [4:0] router_6_0_req_in; -floo_rsp_t [4:0] router_6_0_rsp_out; -floo_req_t [4:0] router_6_0_req_out; -floo_rsp_t [4:0] router_6_0_rsp_in; - - assign router_6_0_req_in[0] = router_6_1_to_router_6_0_req; - assign router_6_0_req_in[1] = router_7_0_to_router_6_0_req; - assign router_6_0_req_in[2] = '0; - assign router_6_0_req_in[3] = router_5_0_to_router_6_0_req; - assign router_6_0_req_in[4] = magia_tile_ni_6_0_to_router_6_0_req; - - assign router_6_0_to_router_6_1_rsp = router_6_0_rsp_out[0]; - assign router_6_0_to_router_7_0_rsp = router_6_0_rsp_out[1]; - assign router_6_0_to_router_5_0_rsp = router_6_0_rsp_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_rsp = router_6_0_rsp_out[4]; - - assign router_6_0_to_router_6_1_req = router_6_0_req_out[0]; - assign router_6_0_to_router_7_0_req = router_6_0_req_out[1]; - assign router_6_0_to_router_5_0_req = router_6_0_req_out[3]; - assign router_6_0_to_magia_tile_ni_6_0_req = router_6_0_req_out[4]; - - assign router_6_0_rsp_in[0] = router_6_1_to_router_6_0_rsp; - assign router_6_0_rsp_in[1] = router_7_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[2] = '0; - assign router_6_0_rsp_in[3] = router_5_0_to_router_6_0_rsp; - assign router_6_0_rsp_in[4] = magia_tile_ni_6_0_to_router_6_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_0_req_in), - .floo_rsp_o (router_6_0_rsp_out), - .floo_req_o (router_6_0_req_out), - .floo_rsp_i (router_6_0_rsp_in) -); - - -floo_req_t [4:0] router_6_1_req_in; -floo_rsp_t [4:0] router_6_1_rsp_out; -floo_req_t [4:0] router_6_1_req_out; -floo_rsp_t [4:0] router_6_1_rsp_in; - - assign router_6_1_req_in[0] = router_6_2_to_router_6_1_req; - assign router_6_1_req_in[1] = router_7_1_to_router_6_1_req; - assign router_6_1_req_in[2] = router_6_0_to_router_6_1_req; - assign router_6_1_req_in[3] = router_5_1_to_router_6_1_req; - assign router_6_1_req_in[4] = magia_tile_ni_6_1_to_router_6_1_req; - - assign router_6_1_to_router_6_2_rsp = router_6_1_rsp_out[0]; - assign router_6_1_to_router_7_1_rsp = router_6_1_rsp_out[1]; - assign router_6_1_to_router_6_0_rsp = router_6_1_rsp_out[2]; - assign router_6_1_to_router_5_1_rsp = router_6_1_rsp_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_rsp = router_6_1_rsp_out[4]; - - assign router_6_1_to_router_6_2_req = router_6_1_req_out[0]; - assign router_6_1_to_router_7_1_req = router_6_1_req_out[1]; - assign router_6_1_to_router_6_0_req = router_6_1_req_out[2]; - assign router_6_1_to_router_5_1_req = router_6_1_req_out[3]; - assign router_6_1_to_magia_tile_ni_6_1_req = router_6_1_req_out[4]; - - assign router_6_1_rsp_in[0] = router_6_2_to_router_6_1_rsp; - assign router_6_1_rsp_in[1] = router_7_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[2] = router_6_0_to_router_6_1_rsp; - assign router_6_1_rsp_in[3] = router_5_1_to_router_6_1_rsp; - assign router_6_1_rsp_in[4] = magia_tile_ni_6_1_to_router_6_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_1_req_in), - .floo_rsp_o (router_6_1_rsp_out), - .floo_req_o (router_6_1_req_out), - .floo_rsp_i (router_6_1_rsp_in) -); - - -floo_req_t [4:0] router_6_2_req_in; -floo_rsp_t [4:0] router_6_2_rsp_out; -floo_req_t [4:0] router_6_2_req_out; -floo_rsp_t [4:0] router_6_2_rsp_in; - - assign router_6_2_req_in[0] = router_6_3_to_router_6_2_req; - assign router_6_2_req_in[1] = router_7_2_to_router_6_2_req; - assign router_6_2_req_in[2] = router_6_1_to_router_6_2_req; - assign router_6_2_req_in[3] = router_5_2_to_router_6_2_req; - assign router_6_2_req_in[4] = magia_tile_ni_6_2_to_router_6_2_req; - - assign router_6_2_to_router_6_3_rsp = router_6_2_rsp_out[0]; - assign router_6_2_to_router_7_2_rsp = router_6_2_rsp_out[1]; - assign router_6_2_to_router_6_1_rsp = router_6_2_rsp_out[2]; - assign router_6_2_to_router_5_2_rsp = router_6_2_rsp_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_rsp = router_6_2_rsp_out[4]; - - assign router_6_2_to_router_6_3_req = router_6_2_req_out[0]; - assign router_6_2_to_router_7_2_req = router_6_2_req_out[1]; - assign router_6_2_to_router_6_1_req = router_6_2_req_out[2]; - assign router_6_2_to_router_5_2_req = router_6_2_req_out[3]; - assign router_6_2_to_magia_tile_ni_6_2_req = router_6_2_req_out[4]; - - assign router_6_2_rsp_in[0] = router_6_3_to_router_6_2_rsp; - assign router_6_2_rsp_in[1] = router_7_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[2] = router_6_1_to_router_6_2_rsp; - assign router_6_2_rsp_in[3] = router_5_2_to_router_6_2_rsp; - assign router_6_2_rsp_in[4] = magia_tile_ni_6_2_to_router_6_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_2_req_in), - .floo_rsp_o (router_6_2_rsp_out), - .floo_req_o (router_6_2_req_out), - .floo_rsp_i (router_6_2_rsp_in) -); - - -floo_req_t [4:0] router_6_3_req_in; -floo_rsp_t [4:0] router_6_3_rsp_out; -floo_req_t [4:0] router_6_3_req_out; -floo_rsp_t [4:0] router_6_3_rsp_in; - - assign router_6_3_req_in[0] = router_6_4_to_router_6_3_req; - assign router_6_3_req_in[1] = router_7_3_to_router_6_3_req; - assign router_6_3_req_in[2] = router_6_2_to_router_6_3_req; - assign router_6_3_req_in[3] = router_5_3_to_router_6_3_req; - assign router_6_3_req_in[4] = magia_tile_ni_6_3_to_router_6_3_req; - - assign router_6_3_to_router_6_4_rsp = router_6_3_rsp_out[0]; - assign router_6_3_to_router_7_3_rsp = router_6_3_rsp_out[1]; - assign router_6_3_to_router_6_2_rsp = router_6_3_rsp_out[2]; - assign router_6_3_to_router_5_3_rsp = router_6_3_rsp_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_rsp = router_6_3_rsp_out[4]; - - assign router_6_3_to_router_6_4_req = router_6_3_req_out[0]; - assign router_6_3_to_router_7_3_req = router_6_3_req_out[1]; - assign router_6_3_to_router_6_2_req = router_6_3_req_out[2]; - assign router_6_3_to_router_5_3_req = router_6_3_req_out[3]; - assign router_6_3_to_magia_tile_ni_6_3_req = router_6_3_req_out[4]; - - assign router_6_3_rsp_in[0] = router_6_4_to_router_6_3_rsp; - assign router_6_3_rsp_in[1] = router_7_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[2] = router_6_2_to_router_6_3_rsp; - assign router_6_3_rsp_in[3] = router_5_3_to_router_6_3_rsp; - assign router_6_3_rsp_in[4] = magia_tile_ni_6_3_to_router_6_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_3_req_in), - .floo_rsp_o (router_6_3_rsp_out), - .floo_req_o (router_6_3_req_out), - .floo_rsp_i (router_6_3_rsp_in) -); - - -floo_req_t [4:0] router_6_4_req_in; -floo_rsp_t [4:0] router_6_4_rsp_out; -floo_req_t [4:0] router_6_4_req_out; -floo_rsp_t [4:0] router_6_4_rsp_in; - - assign router_6_4_req_in[0] = router_6_5_to_router_6_4_req; - assign router_6_4_req_in[1] = router_7_4_to_router_6_4_req; - assign router_6_4_req_in[2] = router_6_3_to_router_6_4_req; - assign router_6_4_req_in[3] = router_5_4_to_router_6_4_req; - assign router_6_4_req_in[4] = magia_tile_ni_6_4_to_router_6_4_req; - - assign router_6_4_to_router_6_5_rsp = router_6_4_rsp_out[0]; - assign router_6_4_to_router_7_4_rsp = router_6_4_rsp_out[1]; - assign router_6_4_to_router_6_3_rsp = router_6_4_rsp_out[2]; - assign router_6_4_to_router_5_4_rsp = router_6_4_rsp_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_rsp = router_6_4_rsp_out[4]; - - assign router_6_4_to_router_6_5_req = router_6_4_req_out[0]; - assign router_6_4_to_router_7_4_req = router_6_4_req_out[1]; - assign router_6_4_to_router_6_3_req = router_6_4_req_out[2]; - assign router_6_4_to_router_5_4_req = router_6_4_req_out[3]; - assign router_6_4_to_magia_tile_ni_6_4_req = router_6_4_req_out[4]; - - assign router_6_4_rsp_in[0] = router_6_5_to_router_6_4_rsp; - assign router_6_4_rsp_in[1] = router_7_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[2] = router_6_3_to_router_6_4_rsp; - assign router_6_4_rsp_in[3] = router_5_4_to_router_6_4_rsp; - assign router_6_4_rsp_in[4] = magia_tile_ni_6_4_to_router_6_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_4_req_in), - .floo_rsp_o (router_6_4_rsp_out), - .floo_req_o (router_6_4_req_out), - .floo_rsp_i (router_6_4_rsp_in) -); - - -floo_req_t [4:0] router_6_5_req_in; -floo_rsp_t [4:0] router_6_5_rsp_out; -floo_req_t [4:0] router_6_5_req_out; -floo_rsp_t [4:0] router_6_5_rsp_in; - - assign router_6_5_req_in[0] = router_6_6_to_router_6_5_req; - assign router_6_5_req_in[1] = router_7_5_to_router_6_5_req; - assign router_6_5_req_in[2] = router_6_4_to_router_6_5_req; - assign router_6_5_req_in[3] = router_5_5_to_router_6_5_req; - assign router_6_5_req_in[4] = magia_tile_ni_6_5_to_router_6_5_req; - - assign router_6_5_to_router_6_6_rsp = router_6_5_rsp_out[0]; - assign router_6_5_to_router_7_5_rsp = router_6_5_rsp_out[1]; - assign router_6_5_to_router_6_4_rsp = router_6_5_rsp_out[2]; - assign router_6_5_to_router_5_5_rsp = router_6_5_rsp_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_rsp = router_6_5_rsp_out[4]; - - assign router_6_5_to_router_6_6_req = router_6_5_req_out[0]; - assign router_6_5_to_router_7_5_req = router_6_5_req_out[1]; - assign router_6_5_to_router_6_4_req = router_6_5_req_out[2]; - assign router_6_5_to_router_5_5_req = router_6_5_req_out[3]; - assign router_6_5_to_magia_tile_ni_6_5_req = router_6_5_req_out[4]; - - assign router_6_5_rsp_in[0] = router_6_6_to_router_6_5_rsp; - assign router_6_5_rsp_in[1] = router_7_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[2] = router_6_4_to_router_6_5_rsp; - assign router_6_5_rsp_in[3] = router_5_5_to_router_6_5_rsp; - assign router_6_5_rsp_in[4] = magia_tile_ni_6_5_to_router_6_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_5_req_in), - .floo_rsp_o (router_6_5_rsp_out), - .floo_req_o (router_6_5_req_out), - .floo_rsp_i (router_6_5_rsp_in) -); - - -floo_req_t [4:0] router_6_6_req_in; -floo_rsp_t [4:0] router_6_6_rsp_out; -floo_req_t [4:0] router_6_6_req_out; -floo_rsp_t [4:0] router_6_6_rsp_in; - - assign router_6_6_req_in[0] = router_6_7_to_router_6_6_req; - assign router_6_6_req_in[1] = router_7_6_to_router_6_6_req; - assign router_6_6_req_in[2] = router_6_5_to_router_6_6_req; - assign router_6_6_req_in[3] = router_5_6_to_router_6_6_req; - assign router_6_6_req_in[4] = magia_tile_ni_6_6_to_router_6_6_req; - - assign router_6_6_to_router_6_7_rsp = router_6_6_rsp_out[0]; - assign router_6_6_to_router_7_6_rsp = router_6_6_rsp_out[1]; - assign router_6_6_to_router_6_5_rsp = router_6_6_rsp_out[2]; - assign router_6_6_to_router_5_6_rsp = router_6_6_rsp_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_rsp = router_6_6_rsp_out[4]; - - assign router_6_6_to_router_6_7_req = router_6_6_req_out[0]; - assign router_6_6_to_router_7_6_req = router_6_6_req_out[1]; - assign router_6_6_to_router_6_5_req = router_6_6_req_out[2]; - assign router_6_6_to_router_5_6_req = router_6_6_req_out[3]; - assign router_6_6_to_magia_tile_ni_6_6_req = router_6_6_req_out[4]; - - assign router_6_6_rsp_in[0] = router_6_7_to_router_6_6_rsp; - assign router_6_6_rsp_in[1] = router_7_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[2] = router_6_5_to_router_6_6_rsp; - assign router_6_6_rsp_in[3] = router_5_6_to_router_6_6_rsp; - assign router_6_6_rsp_in[4] = magia_tile_ni_6_6_to_router_6_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_6_req_in), - .floo_rsp_o (router_6_6_rsp_out), - .floo_req_o (router_6_6_req_out), - .floo_rsp_i (router_6_6_rsp_in) -); - - -floo_req_t [4:0] router_6_7_req_in; -floo_rsp_t [4:0] router_6_7_rsp_out; -floo_req_t [4:0] router_6_7_req_out; -floo_rsp_t [4:0] router_6_7_rsp_in; - - assign router_6_7_req_in[0] = '0; - assign router_6_7_req_in[1] = router_7_7_to_router_6_7_req; - assign router_6_7_req_in[2] = router_6_6_to_router_6_7_req; - assign router_6_7_req_in[3] = router_5_7_to_router_6_7_req; - assign router_6_7_req_in[4] = magia_tile_ni_6_7_to_router_6_7_req; - - assign router_6_7_to_router_7_7_rsp = router_6_7_rsp_out[1]; - assign router_6_7_to_router_6_6_rsp = router_6_7_rsp_out[2]; - assign router_6_7_to_router_5_7_rsp = router_6_7_rsp_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_rsp = router_6_7_rsp_out[4]; - - assign router_6_7_to_router_7_7_req = router_6_7_req_out[1]; - assign router_6_7_to_router_6_6_req = router_6_7_req_out[2]; - assign router_6_7_to_router_5_7_req = router_6_7_req_out[3]; - assign router_6_7_to_magia_tile_ni_6_7_req = router_6_7_req_out[4]; - - assign router_6_7_rsp_in[0] = '0; - assign router_6_7_rsp_in[1] = router_7_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[2] = router_6_6_to_router_6_7_rsp; - assign router_6_7_rsp_in[3] = router_5_7_to_router_6_7_rsp; - assign router_6_7_rsp_in[4] = magia_tile_ni_6_7_to_router_6_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_6_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 7, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_6_7_req_in), - .floo_rsp_o (router_6_7_rsp_out), - .floo_req_o (router_6_7_req_out), - .floo_rsp_i (router_6_7_rsp_in) -); - - -floo_req_t [4:0] router_7_0_req_in; -floo_rsp_t [4:0] router_7_0_rsp_out; -floo_req_t [4:0] router_7_0_req_out; -floo_rsp_t [4:0] router_7_0_rsp_in; - - assign router_7_0_req_in[0] = router_7_1_to_router_7_0_req; - assign router_7_0_req_in[1] = '0; - assign router_7_0_req_in[2] = '0; - assign router_7_0_req_in[3] = router_6_0_to_router_7_0_req; - assign router_7_0_req_in[4] = magia_tile_ni_7_0_to_router_7_0_req; - - assign router_7_0_to_router_7_1_rsp = router_7_0_rsp_out[0]; - assign router_7_0_to_router_6_0_rsp = router_7_0_rsp_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_rsp = router_7_0_rsp_out[4]; - - assign router_7_0_to_router_7_1_req = router_7_0_req_out[0]; - assign router_7_0_to_router_6_0_req = router_7_0_req_out[3]; - assign router_7_0_to_magia_tile_ni_7_0_req = router_7_0_req_out[4]; - - assign router_7_0_rsp_in[0] = router_7_1_to_router_7_0_rsp; - assign router_7_0_rsp_in[1] = '0; - assign router_7_0_rsp_in[2] = '0; - assign router_7_0_rsp_in[3] = router_6_0_to_router_7_0_rsp; - assign router_7_0_rsp_in[4] = magia_tile_ni_7_0_to_router_7_0_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_0 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 0, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_0_req_in), - .floo_rsp_o (router_7_0_rsp_out), - .floo_req_o (router_7_0_req_out), - .floo_rsp_i (router_7_0_rsp_in) -); - - -floo_req_t [4:0] router_7_1_req_in; -floo_rsp_t [4:0] router_7_1_rsp_out; -floo_req_t [4:0] router_7_1_req_out; -floo_rsp_t [4:0] router_7_1_rsp_in; - - assign router_7_1_req_in[0] = router_7_2_to_router_7_1_req; - assign router_7_1_req_in[1] = '0; - assign router_7_1_req_in[2] = router_7_0_to_router_7_1_req; - assign router_7_1_req_in[3] = router_6_1_to_router_7_1_req; - assign router_7_1_req_in[4] = magia_tile_ni_7_1_to_router_7_1_req; - - assign router_7_1_to_router_7_2_rsp = router_7_1_rsp_out[0]; - assign router_7_1_to_router_7_0_rsp = router_7_1_rsp_out[2]; - assign router_7_1_to_router_6_1_rsp = router_7_1_rsp_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_rsp = router_7_1_rsp_out[4]; - - assign router_7_1_to_router_7_2_req = router_7_1_req_out[0]; - assign router_7_1_to_router_7_0_req = router_7_1_req_out[2]; - assign router_7_1_to_router_6_1_req = router_7_1_req_out[3]; - assign router_7_1_to_magia_tile_ni_7_1_req = router_7_1_req_out[4]; - - assign router_7_1_rsp_in[0] = router_7_2_to_router_7_1_rsp; - assign router_7_1_rsp_in[1] = '0; - assign router_7_1_rsp_in[2] = router_7_0_to_router_7_1_rsp; - assign router_7_1_rsp_in[3] = router_6_1_to_router_7_1_rsp; - assign router_7_1_rsp_in[4] = magia_tile_ni_7_1_to_router_7_1_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_1 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 1, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_1_req_in), - .floo_rsp_o (router_7_1_rsp_out), - .floo_req_o (router_7_1_req_out), - .floo_rsp_i (router_7_1_rsp_in) -); - - -floo_req_t [4:0] router_7_2_req_in; -floo_rsp_t [4:0] router_7_2_rsp_out; -floo_req_t [4:0] router_7_2_req_out; -floo_rsp_t [4:0] router_7_2_rsp_in; - - assign router_7_2_req_in[0] = router_7_3_to_router_7_2_req; - assign router_7_2_req_in[1] = '0; - assign router_7_2_req_in[2] = router_7_1_to_router_7_2_req; - assign router_7_2_req_in[3] = router_6_2_to_router_7_2_req; - assign router_7_2_req_in[4] = magia_tile_ni_7_2_to_router_7_2_req; - - assign router_7_2_to_router_7_3_rsp = router_7_2_rsp_out[0]; - assign router_7_2_to_router_7_1_rsp = router_7_2_rsp_out[2]; - assign router_7_2_to_router_6_2_rsp = router_7_2_rsp_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_rsp = router_7_2_rsp_out[4]; - - assign router_7_2_to_router_7_3_req = router_7_2_req_out[0]; - assign router_7_2_to_router_7_1_req = router_7_2_req_out[2]; - assign router_7_2_to_router_6_2_req = router_7_2_req_out[3]; - assign router_7_2_to_magia_tile_ni_7_2_req = router_7_2_req_out[4]; - - assign router_7_2_rsp_in[0] = router_7_3_to_router_7_2_rsp; - assign router_7_2_rsp_in[1] = '0; - assign router_7_2_rsp_in[2] = router_7_1_to_router_7_2_rsp; - assign router_7_2_rsp_in[3] = router_6_2_to_router_7_2_rsp; - assign router_7_2_rsp_in[4] = magia_tile_ni_7_2_to_router_7_2_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_2 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 2, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_2_req_in), - .floo_rsp_o (router_7_2_rsp_out), - .floo_req_o (router_7_2_req_out), - .floo_rsp_i (router_7_2_rsp_in) -); - - -floo_req_t [4:0] router_7_3_req_in; -floo_rsp_t [4:0] router_7_3_rsp_out; -floo_req_t [4:0] router_7_3_req_out; -floo_rsp_t [4:0] router_7_3_rsp_in; - - assign router_7_3_req_in[0] = router_7_4_to_router_7_3_req; - assign router_7_3_req_in[1] = '0; - assign router_7_3_req_in[2] = router_7_2_to_router_7_3_req; - assign router_7_3_req_in[3] = router_6_3_to_router_7_3_req; - assign router_7_3_req_in[4] = magia_tile_ni_7_3_to_router_7_3_req; - - assign router_7_3_to_router_7_4_rsp = router_7_3_rsp_out[0]; - assign router_7_3_to_router_7_2_rsp = router_7_3_rsp_out[2]; - assign router_7_3_to_router_6_3_rsp = router_7_3_rsp_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_rsp = router_7_3_rsp_out[4]; - - assign router_7_3_to_router_7_4_req = router_7_3_req_out[0]; - assign router_7_3_to_router_7_2_req = router_7_3_req_out[2]; - assign router_7_3_to_router_6_3_req = router_7_3_req_out[3]; - assign router_7_3_to_magia_tile_ni_7_3_req = router_7_3_req_out[4]; - - assign router_7_3_rsp_in[0] = router_7_4_to_router_7_3_rsp; - assign router_7_3_rsp_in[1] = '0; - assign router_7_3_rsp_in[2] = router_7_2_to_router_7_3_rsp; - assign router_7_3_rsp_in[3] = router_6_3_to_router_7_3_rsp; - assign router_7_3_rsp_in[4] = magia_tile_ni_7_3_to_router_7_3_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_3 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 3, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_3_req_in), - .floo_rsp_o (router_7_3_rsp_out), - .floo_req_o (router_7_3_req_out), - .floo_rsp_i (router_7_3_rsp_in) -); - - -floo_req_t [4:0] router_7_4_req_in; -floo_rsp_t [4:0] router_7_4_rsp_out; -floo_req_t [4:0] router_7_4_req_out; -floo_rsp_t [4:0] router_7_4_rsp_in; - - assign router_7_4_req_in[0] = router_7_5_to_router_7_4_req; - assign router_7_4_req_in[1] = '0; - assign router_7_4_req_in[2] = router_7_3_to_router_7_4_req; - assign router_7_4_req_in[3] = router_6_4_to_router_7_4_req; - assign router_7_4_req_in[4] = magia_tile_ni_7_4_to_router_7_4_req; - - assign router_7_4_to_router_7_5_rsp = router_7_4_rsp_out[0]; - assign router_7_4_to_router_7_3_rsp = router_7_4_rsp_out[2]; - assign router_7_4_to_router_6_4_rsp = router_7_4_rsp_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_rsp = router_7_4_rsp_out[4]; - - assign router_7_4_to_router_7_5_req = router_7_4_req_out[0]; - assign router_7_4_to_router_7_3_req = router_7_4_req_out[2]; - assign router_7_4_to_router_6_4_req = router_7_4_req_out[3]; - assign router_7_4_to_magia_tile_ni_7_4_req = router_7_4_req_out[4]; - - assign router_7_4_rsp_in[0] = router_7_5_to_router_7_4_rsp; - assign router_7_4_rsp_in[1] = '0; - assign router_7_4_rsp_in[2] = router_7_3_to_router_7_4_rsp; - assign router_7_4_rsp_in[3] = router_6_4_to_router_7_4_rsp; - assign router_7_4_rsp_in[4] = magia_tile_ni_7_4_to_router_7_4_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_4 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 4, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_4_req_in), - .floo_rsp_o (router_7_4_rsp_out), - .floo_req_o (router_7_4_req_out), - .floo_rsp_i (router_7_4_rsp_in) -); - - -floo_req_t [4:0] router_7_5_req_in; -floo_rsp_t [4:0] router_7_5_rsp_out; -floo_req_t [4:0] router_7_5_req_out; -floo_rsp_t [4:0] router_7_5_rsp_in; - - assign router_7_5_req_in[0] = router_7_6_to_router_7_5_req; - assign router_7_5_req_in[1] = '0; - assign router_7_5_req_in[2] = router_7_4_to_router_7_5_req; - assign router_7_5_req_in[3] = router_6_5_to_router_7_5_req; - assign router_7_5_req_in[4] = magia_tile_ni_7_5_to_router_7_5_req; - - assign router_7_5_to_router_7_6_rsp = router_7_5_rsp_out[0]; - assign router_7_5_to_router_7_4_rsp = router_7_5_rsp_out[2]; - assign router_7_5_to_router_6_5_rsp = router_7_5_rsp_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_rsp = router_7_5_rsp_out[4]; - - assign router_7_5_to_router_7_6_req = router_7_5_req_out[0]; - assign router_7_5_to_router_7_4_req = router_7_5_req_out[2]; - assign router_7_5_to_router_6_5_req = router_7_5_req_out[3]; - assign router_7_5_to_magia_tile_ni_7_5_req = router_7_5_req_out[4]; - - assign router_7_5_rsp_in[0] = router_7_6_to_router_7_5_rsp; - assign router_7_5_rsp_in[1] = '0; - assign router_7_5_rsp_in[2] = router_7_4_to_router_7_5_rsp; - assign router_7_5_rsp_in[3] = router_6_5_to_router_7_5_rsp; - assign router_7_5_rsp_in[4] = magia_tile_ni_7_5_to_router_7_5_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_5 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 5, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_5_req_in), - .floo_rsp_o (router_7_5_rsp_out), - .floo_req_o (router_7_5_req_out), - .floo_rsp_i (router_7_5_rsp_in) -); - - -floo_req_t [4:0] router_7_6_req_in; -floo_rsp_t [4:0] router_7_6_rsp_out; -floo_req_t [4:0] router_7_6_req_out; -floo_rsp_t [4:0] router_7_6_rsp_in; - - assign router_7_6_req_in[0] = router_7_7_to_router_7_6_req; - assign router_7_6_req_in[1] = '0; - assign router_7_6_req_in[2] = router_7_5_to_router_7_6_req; - assign router_7_6_req_in[3] = router_6_6_to_router_7_6_req; - assign router_7_6_req_in[4] = magia_tile_ni_7_6_to_router_7_6_req; - - assign router_7_6_to_router_7_7_rsp = router_7_6_rsp_out[0]; - assign router_7_6_to_router_7_5_rsp = router_7_6_rsp_out[2]; - assign router_7_6_to_router_6_6_rsp = router_7_6_rsp_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_rsp = router_7_6_rsp_out[4]; - - assign router_7_6_to_router_7_7_req = router_7_6_req_out[0]; - assign router_7_6_to_router_7_5_req = router_7_6_req_out[2]; - assign router_7_6_to_router_6_6_req = router_7_6_req_out[3]; - assign router_7_6_to_magia_tile_ni_7_6_req = router_7_6_req_out[4]; - - assign router_7_6_rsp_in[0] = router_7_7_to_router_7_6_rsp; - assign router_7_6_rsp_in[1] = '0; - assign router_7_6_rsp_in[2] = router_7_5_to_router_7_6_rsp; - assign router_7_6_rsp_in[3] = router_6_6_to_router_7_6_rsp; - assign router_7_6_rsp_in[4] = magia_tile_ni_7_6_to_router_7_6_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_6 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 6, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_6_req_in), - .floo_rsp_o (router_7_6_rsp_out), - .floo_req_o (router_7_6_req_out), - .floo_rsp_i (router_7_6_rsp_in) -); - - -floo_req_t [4:0] router_7_7_req_in; -floo_rsp_t [4:0] router_7_7_rsp_out; -floo_req_t [4:0] router_7_7_req_out; -floo_rsp_t [4:0] router_7_7_rsp_in; - - assign router_7_7_req_in[0] = '0; - assign router_7_7_req_in[1] = '0; - assign router_7_7_req_in[2] = router_7_6_to_router_7_7_req; - assign router_7_7_req_in[3] = router_6_7_to_router_7_7_req; - assign router_7_7_req_in[4] = magia_tile_ni_7_7_to_router_7_7_req; - - assign router_7_7_to_router_7_6_rsp = router_7_7_rsp_out[2]; - assign router_7_7_to_router_6_7_rsp = router_7_7_rsp_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_rsp = router_7_7_rsp_out[4]; - - assign router_7_7_to_router_7_6_req = router_7_7_req_out[2]; - assign router_7_7_to_router_6_7_req = router_7_7_req_out[3]; - assign router_7_7_to_magia_tile_ni_7_7_req = router_7_7_req_out[4]; - - assign router_7_7_rsp_in[0] = '0; - assign router_7_7_rsp_in[1] = '0; - assign router_7_7_rsp_in[2] = router_7_6_to_router_7_7_rsp; - assign router_7_7_rsp_in[3] = router_6_7_to_router_7_7_rsp; - assign router_7_7_rsp_in[4] = magia_tile_ni_7_7_to_router_7_7_rsp; - -floo_axi_router #( - .AxiCfg(AxiCfg), - .RouteAlgo (XYRouting), - .NumRoutes (5), - .NumInputs (5), - .NumOutputs (5), - .InFifoDepth (2), - .OutFifoDepth (2), - .id_t(id_t), - .hdr_t(hdr_t), - .floo_req_t(floo_req_t), - .floo_rsp_t(floo_rsp_t) -) router_7_7 ( - .clk_i, - .rst_ni, - .test_enable_i, - .id_i ('{x: 8, y: 7, port_id: 0}), - .id_route_map_i ('0), - .floo_req_i (router_7_7_req_in), - .floo_rsp_o (router_7_7_rsp_out), - .floo_req_o (router_7_7_req_out), - .floo_rsp_i (router_7_7_rsp_in) -); - - - -endmodule diff --git a/hw/tile/magia_tile.sv b/hw/tile/magia_tile.sv index 8b4d1d2..822ada0 100644 --- a/hw/tile/magia_tile.sv +++ b/hw/tile/magia_tile.sv @@ -271,6 +271,8 @@ module magia_tile floo_rsp_t [4:0] floo_router_rsp_in; floo_req_t [4:0] floo_router_req_out; floo_rsp_t [4:0] floo_router_rsp_out; + + id_t floo_id; logic x_compressed_valid; logic x_compressed_ready; @@ -410,6 +412,8 @@ module magia_tile assign xif_redmule_if.mem_ready = 1'b0; assign xif_redmule_if.mem_resp = '0; + assign floo_id = '{x: (x_id_i+1), y: y_id_i, port_id: 0}; + /*******************************************************/ /** Hardwired Signals End **/ /*******************************************************/ @@ -841,7 +845,7 @@ module magia_tile .mgr_port_obi_a_optional_t ( magia_tile_pkg::core_data_obi_a_optional_t ), .mgr_port_obi_r_optional_t ( magia_tile_pkg::core_data_obi_r_optional_t ), .LrScEnable ( ), - .RegisterAmo ( ) + .RegisterAmo ( magia_tile_pkg::RegisterAmo ) ) i_obi_atomics ( .clk_i ( sys_clk ), .rst_ni ( rst_ni ), @@ -1169,7 +1173,7 @@ module magia_tile .axi_in_rsp_o ( axi_xbar_data_out_rsp ), .axi_out_req_o ( axi_xbar_data_in_req[magia_tile_pkg::AXI_EXT_IDX] ), .axi_out_rsp_i ( axi_xbar_data_in_rsp[magia_tile_pkg::AXI_EXT_IDX] ), - .id_i ( '{x: (x_id_i+1), y: y_id_i, port_id: 0} ), + .id_i ( floo_id ), .route_table_i ( '0 ), .floo_req_o ( floo_router_req_in[4] ), .floo_rsp_i ( floo_router_rsp_out[4] ), @@ -1190,15 +1194,15 @@ module magia_tile .floo_req_t ( floo_req_t ), .floo_rsp_t ( floo_rsp_t ) ) i_magia_tile_router ( - .clk_i ( sys_clk ), - .rst_ni ( rst_ni ), - .test_enable_i ( test_mode_i ), - .id_i ( '{x: (x_id_i+1), y: y_id_i, port_id: 0} ), - .id_route_map_i ( '0 ), - .floo_req_i ( floo_router_req_in ), - .floo_rsp_o ( floo_router_rsp_out ), - .floo_req_o ( floo_router_req_out ), - .floo_rsp_i ( floo_router_rsp_in ) + .clk_i ( sys_clk ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_mode_i ), + .id_i ( floo_id ), + .id_route_map_i ( '0 ), + .floo_req_i ( floo_router_req_in ), + .floo_rsp_o ( floo_router_rsp_out ), + .floo_req_o ( floo_router_req_out ), + .floo_rsp_i ( floo_router_rsp_in ) ); // Output requests @@ -1268,13 +1272,14 @@ module magia_tile /*******************************************************/ fpu_ss #( - .PULP_ZFINX ( magia_tile_pkg::FPU_ZFINX ), - .INPUT_BUFFER_DEPTH ( magia_tile_pkg::FPU_BUFFER_DEPTH ), - .OUT_OF_ORDER ( magia_tile_pkg::FPU_OOO ), - .FORWARDING ( magia_tile_pkg::FPU_FWD ), - .PulpDivsqrt ( magia_tile_pkg::FPU_DIVSQRT ), - .FPU_FEATURES ( magia_tile_pkg::FPU_FEATURES ), - .FPU_IMPLEMENTATION ( magia_tile_pkg::FPU_IMPLEMENTATION ) + .PULP_ZFINX ( magia_tile_pkg::FPU_ZFINX ), + .INPUT_BUFFER_DEPTH ( magia_tile_pkg::FPU_BUFFER_DEPTH ), + .INPUT_BUFFER_FALL_THROUGH ( magia_tile_pkg::FPU_BUFFER_FT ), + .OUT_OF_ORDER ( magia_tile_pkg::FPU_OOO ), + .FORWARDING ( magia_tile_pkg::FPU_FWD ), + .PulpDivsqrt ( magia_tile_pkg::FPU_DIVSQRT ), + .FPU_FEATURES ( magia_tile_pkg::FPU_FEATURES ), + .FPU_IMPLEMENTATION ( magia_tile_pkg::FPU_IMPLEMENTATION ) ) i_fpu ( .clk_i ( sys_clk ), .rst_ni ( rst_ni ), diff --git a/hw/tile/magia_tile_pkg.sv b/hw/tile/magia_tile_pkg.sv index ff85df5..bc676bd 100644 --- a/hw/tile/magia_tile_pkg.sv +++ b/hw/tile/magia_tile_pkg.sv @@ -286,6 +286,7 @@ package magia_tile_pkg; // Parameters used by the FPU parameter bit FPU_ZFINX = 0; // FPU use Zfinx extension instead of the F ISA extention parameter int unsigned FPU_BUFFER_DEPTH = 8; // FPU FIFO depth that buffers instructions coming from core + parameter bit FPU_BUFFER_FT = 0; // FPU FIFO fall through that buffers instructions coming from core parameter bit FPU_OOO = 1; // FPU enable out-of-order execution parameter bit FPU_FWD = 1; // FPU enable forwarding from output to input of FPnew parameter bit FPU_DIVSQRT = 0; // FPU disable FPnew T-head-based DivSqrt unit (supported only for FP32 unit) @@ -297,14 +298,14 @@ package magia_tile_pkg; IntFmtMask: 4'b0010 }; // FPU features: support only for FP32 and INT32 parameter fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ - PipeRegs: '{default: 1}, + PipeRegs: '{default: 2}, UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, '{default: fpnew_pkg::MERGED}, '{default: fpnew_pkg::PARALLEL}, '{default: fpnew_pkg::MERGED}, '{default: fpnew_pkg::DISABLED} }, - PipeConfig: fpnew_pkg::BEFORE + PipeConfig: fpnew_pkg::DISTRIBUTED }; // FPU implementation typedef struct packed { @@ -393,6 +394,7 @@ package magia_tile_pkg; localparam obi_pkg::obi_optional_cfg_t obi_amo_optional_cfg = obi_pkg::obi_all_optional_config(AUSER_WIDTH, WUSER_WIDTH, RUSER_WIDTH, MID_WIDTH, ACHK_WIDTH, RCHK_WIDTH); localparam obi_pkg::obi_cfg_t obi_amo_cfg = obi_pkg::obi_default_cfg(magia_pkg::ADDR_W, magia_pkg::DATA_W, OBI_ID_WIDTH, obi_amo_optional_cfg); + localparam bit RegisterAmo = 1; `OBI_TYPEDEF_ALL_A_OPTIONAL(core_data_obi_a_optional_t, AUSER_WIDTH, WUSER_WIDTH, MID_WIDTH, ACHK_WIDTH) `OBI_TYPEDEF_ALL_R_OPTIONAL(core_data_obi_r_optional_t, RUSER_WIDTH, RCHK_WIDTH)