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Commit 0b619a5

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lvyinrun
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QNN Backend: Enable QualComm SM8850 targets
Add SM8850 for QualComm Snapdragon 8 Elite Gen 5.
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-0
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backends/qualcomm/serialization/qc_compiler_spec.fbs

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@@ -40,6 +40,7 @@ enum QcomChipset: int {
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SM8550 = 43,
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SM8650 = 57,
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SM8750 = 69,
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SM8850 = 87,
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SSG2115P = 46,
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SSG2125P = 58,
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SXR1230P = 45,

backends/qualcomm/serialization/qc_schema.py

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@@ -46,6 +46,7 @@ class QcomChipset(IntEnum):
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SM8550 = 43 # v73
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SM8650 = 57 # v75
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SM8750 = 69 # v79
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SM8850 = 87 # v81
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SSG2115P = 46 # v73
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SSG2125P = 58 # v73
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SXR1230P = 45 # v73
@@ -71,6 +72,7 @@ class SocInfo:
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QcomChipset.SA8255: SocInfo(QcomChipset.SA8255, HtpInfo(HtpArch.V73, 8)),
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QcomChipset.SM8650: SocInfo(QcomChipset.SM8650, HtpInfo(HtpArch.V75, 8)),
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QcomChipset.SM8750: SocInfo(QcomChipset.SM8750, HtpInfo(HtpArch.V79, 8)),
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QcomChipset.SM8850: SocInfo(QcomChipset.SM8850, HtpInfo(HtpArch.V81, 8)),
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QcomChipset.SSG2115P: SocInfo(QcomChipset.SSG2115P, HtpInfo(HtpArch.V73, 2)),
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QcomChipset.SSG2125P: SocInfo(QcomChipset.SSG2125P, HtpInfo(HtpArch.V73, 2)),
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QcomChipset.SXR1230P: SocInfo(QcomChipset.SXR1230P, HtpInfo(HtpArch.V73, 2)),

backends/qualcomm/utils/utils.py

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@@ -1117,6 +1117,7 @@ def get_soc_to_chipset_map():
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"SA8255": QcomChipset.SA8255,
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"SM8650": QcomChipset.SM8650,
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"SM8750": QcomChipset.SM8750,
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"SM8850": QcomChipset.SM8850,
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"SSG2115P": QcomChipset.SSG2115P,
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"SSG2125P": QcomChipset.SSG2125P,
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"SXR1230P": QcomChipset.SXR1230P,

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