Added gorci to unsgn_rs1 in coverage.py

Added conditions to extract bs and rnum fields in rvopcodesdecoder.py
Removed zext.h from internaldecoder.py

Author: anku-anand

riscv_isac/coverage.py

@@ -37,7 +37,7 @@
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
-        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip']
+        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci']
 unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
         'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
         'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
@@ -720,7 +720,6 @@ def compute_per_line(queue, event, cgf_queue, stats_queue, cgf, xlen, addr_pairs
                 local_dict[i] = int(csr_regfile[i],16)
 
             local_dict['xlen'] = xlen
-            
             if enable :
                 for cov_labels,value in cgf.items():
                     if cov_labels != 'datasets':

riscv_isac/data/rvopcodesdecoder.py

@@ -395,6 +395,10 @@ def decode(self, instrObj_temp):
                     temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2)
                 if arg == 'csr':
                     temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'bs':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'rnum':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
                 if arg.find('imm') != -1:
                     if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']:
                         imm = get_arg_val(arg)(mcode)

riscv_isac/plugins/internaldecoder.py

@@ -1215,10 +1215,7 @@ def arith_ops(self, instrObj):
 # for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
 # then cannot distinguish from each other, hence using isa to differentiate.
 # zext.h is part of Zbb, pack is part of Zbkb
-                if (len(list (filter (lambda x: "Zbb" in x, self.isa)))==1):
-                    instrObj.instr_name = 'zext.h'
-                else:
-                    instrObj.instr_name = 'pack'
+                instrObj.instr_name = 'pack'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
@@ -1506,10 +1503,7 @@ def rv64i_arith_ops(self, instrObj):
 # for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
 # then cannot distinguish from each other, hence using isa to differentiate.
 # zext.h is part of Zbb, packw is part of Zbkb
-                if (len(list (filter (lambda x: "Zbb" in x, self.isa))) == 1):
-                        instrObj.instr_name = 'zext.h'
-                else:
-                    instrObj.instr_name = 'packw'
+                instrObj.instr_name = 'packw'
                 instrObj.rs1 = rs1
                 instrObj.rs2 = rs2
                 instrObj.rd = rd