diff --git a/p/riscv_test.h b/p/riscv_test.h
index fe14f08..447e162 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -23,6 +23,21 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV64MV                                                   \
+  .macro init;                                                          \
+  RVTEST_MVECTOR_ENABLE;                                                \
+  .endm
+
+#define RVTEST_RV64UFV                                                  \
+  .macro init;                                                          \
+  RVTEST_FP_VECTOR_ENABLE;                                              \
+  .endm
+
+#define RVTEST_RV64MFV                                                  \
+  .macro init;                                                          \
+  RVTEST_FP_MVECTOR_ENABLE;                                             \
+  .endm
+
 #define RVTEST_RV32U                                                    \
   .macro init;                                                          \
   .endm
@@ -37,6 +52,21 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV32MV                                                   \
+  .macro init;                                                          \
+  RVTEST_MVECTOR_ENABLE;                                                \
+  .endm
+
+#define RVTEST_RV32UFV                                                  \
+  .macro init;                                                          \
+  RVTEST_FP_VECTOR_ENABLE;                                              \
+  .endm
+
+#define RVTEST_RV32MFV                                                  \
+  .macro init;                                                          \
+  RVTEST_FP_MVECTOR_ENABLE;                                             \
+  .endm
+
 #define RVTEST_RV64M                                                    \
   .macro init;                                                          \
   RVTEST_ENABLE_MACHINE;                                                \
@@ -139,12 +169,31 @@
   csrwi fcsr, 0
 
 #define RVTEST_VECTOR_ENABLE                                            \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1));                              \
+  csrs mstatus, a0;                                                     \
+  csrwi vcsr, 0;
+
+#define RVTEST_MVECTOR_ENABLE                                           \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
+         (MSTATUS_MPP);                                                 \
+  csrs mstatus, a0;                                                     \
+  csrwi vcsr, 0;
+
+#define RVTEST_FP_VECTOR_ENABLE                                         \
   li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
          (MSTATUS_FS & (MSTATUS_FS >> 1));                              \
   csrs mstatus, a0;                                                     \
   csrwi fcsr, 0;                                                        \
   csrwi vcsr, 0;
 
+#define RVTEST_FP_MVECTOR_ENABLE                                        \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
+         (MSTATUS_FS & (MSTATUS_FS >> 1)) |                             \
+         (MSTATUS_MPP);                                                 \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0;                                                        \
+  csrwi vcsr, 0;
+
 #define RISCV_MULTICORE_DISABLE                                         \
   csrr a0, mhartid;                                                     \
   1: bnez a0, 1b