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riscvarchive/riscv-svadu
Integrate spec into privileged spec.

Note that I have issued a PR to pull this spec into the Privileged spec.
  • wmat
  • Opened 
    on Mar 19, 2024
  • #26

riscvarchive/riscv-svadu
ADUE should be under S-mode control

Currently ADUE lives in menvcfg, which means M-mode needs to decide what to set it to. M-mode itself does not care, because it is not subject to translation. What does care is S-mode, as it s the one that ...
  • jrtc27
  • 23
  • Opened 
    on Sep 27, 2023
  • #21

riscvarchive/riscv-svadu
PTE-Update text can be misleading

In the Hardware Updating of PTE A/D Bits section of the document, the description of what must be done atomically needs to be disambiguated. The PTE update must be atomic with respect to other accesses ...
  • kdockser
  • 21
  • Opened 
    on Sep 26, 2023
  • #20

riscvarchive/riscv-svadu
The non-normative text needs to be clearly demarcated from the normative text.

The spec starts off with an explanation of how the A/D bits are updated by hardware. However, this feature has already been detailed and ratified in the Privileged Specification - which also talks about ...
  • kdockser
  • 3
  • Opened 
    on Aug 29, 2023
  • #16

riscvarchive/riscv-svadu
What is the purpose of ordering the updating of the A/D bits by a FENCE.

The svadu spec states: The ordering on loads and stores provided by FENCE instructions and the acquire/release bits on atomic instructions also orders the PTE updates associated with those loads and stores ...
  • kdockser
  • 29
  • Opened 
    on Aug 22, 2023
  • #15

riscvarchive/riscv-svadu
Update of D bits based on speculative update of A bits

The Spec states When two-stage address translation is active, updates of the D bit in G-stage PTEs may be performed as a result of speculative updates of the A bit in VS-stage PTEs. However, nowhere does ...
  • kdockser
  • 15
  • Opened 
    on Aug 21, 2023
  • #14

riscvarchive/riscv-svadu
henvcfg.HADE vs mstatus.TVM

If mstatus.TVM=1, then the translation structures pointed to by satp and hgatp are logically owned by M-mode code (or a different HS-mode context, but definitely not this HS-mode context). If M-mode wishes ...
  • sorear
  • 4
  • Opened 
    on Nov 6, 2022
  • #11

riscvarchive/riscv-svadu
Enabling from S-mode in a RVA20/RVA22-compatible way

The current draft profiles spec requires HADE=0 behavior in both RVA20 and RVA22, at least in the initial environment, which means that a SEE/bootloader must initialize HADE to 0 before starting a supervisor ...
  • sorear
  • 8
  • Opened 
    on Nov 6, 2022
  • #10

riscvarchive/riscv-svadu
re-statement of translation process

The extension proposal says except that step 7 of the translation process is as follows: ... and then re-states the existing step 7 of the translation process. This is unnecessary, confusing, and misleading ...
  • ingallsj
  • 3
  • Opened 
    on Oct 29, 2022
  • #6

riscvarchive/riscv-svadu
"Svadu extension requires the page tables to be located in cacheable main memory PMA regions"

Is this a requirement on - hardware to check that page table walks are always to cacheable main memory, otherwise fault, or - software to place their page tables in cacheable main memory? I m hoping ...
  • ingallsj
  • 18
  • Opened 
    on Oct 29, 2022
  • #5
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