diff --git a/riscv-macros/CHANGELOG.md b/riscv-macros/CHANGELOG.md
index a47c1cf2..f1109e1a 100644
--- a/riscv-macros/CHANGELOG.md
+++ b/riscv-macros/CHANGELOG.md
@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Fix `cargo doc` errors.
 - Use fully qualified paths in generated code (i.e., `::riscv` instead of `riscv`)
 - Moved from `riscv/macros/` to `riscv-macros/`
 - Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
diff --git a/riscv-macros/src/lib.rs b/riscv-macros/src/lib.rs
index 40bf60dd..70830506 100644
--- a/riscv-macros/src/lib.rs
+++ b/riscv-macros/src/lib.rs
@@ -426,7 +426,7 @@ core::arch::global_asm!("
 ///
 /// # Example
 ///
-/// ```rust
+/// ```rust,ignore,no_run
 /// use riscv::*;
 ///
 /// #[repr(usize)]
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 1c455572..73e4174f 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Add features to documentation that were missing and fix `cargo doc` errors.
 - Update license to `MIT or Apache-2.0`
 - Fix clippy warnings in riscv_rt_macros::strip_type_path
 - Bump MSRV to 1.68 for latest syn 2.0 release
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 1faf4284..5766daca 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -156,7 +156,7 @@
 //!
 //! Our application would look like this:
 //!
-//! ```no_run
+//! ```ignore,no_run
 //! // src/main.rs
 //! #![no_main]
 //! #![no_std]
@@ -269,7 +269,7 @@
 //!
 //! ## Example
 //!
-//! ``` no_run
+//! ``` ignore,no_run
 //! extern crate some_allocator; // e.g., embedded_alloc::LlffHeap
 //!
 //! extern "C" {
@@ -357,7 +357,7 @@
 //!
 //! The following example shows how to implement the `_mp_hook` function in assembly.
 //!
-//! ``` no_run
+//! ``` ignore,no_run
 //! core::arch::global_asm!(
 //!     r#".section .init.mp_hook, "ax"
 //!     .global _mp_hook
@@ -433,7 +433,7 @@
 //!
 //! This function can be redefined in the following way:
 //!
-//! ``` no_run
+//! ``` ignore,no_run
 //! #[export_name = "ExceptionHandler"]
 //! fn custom_exception_handler(trap_frame: &riscv_rt::TrapFrame) -> ! {
 //!     // ...
@@ -542,7 +542,7 @@
 //!
 //! The following example shows how to implement the `__pre_init` function in assembly.
 //!
-//! ``` no_run
+//! ``` ignore,no_run
 //! core::arch::global_asm!(
 //!     r#".section .init.pre_init, "ax"
 //!     .global __pre_init
@@ -574,6 +574,20 @@
 //!
 //! Skips interrupts setup.
 //!
+//! ## `no-xie-xip`
+//!
+//! Skips disabling interrupts (to support chips without XIE/XIP CSRs).
+//!
+//! ## `no-interrupts`
+//!
+//! Opts out of the default implementation for `_dispatch_core_interrupt` to support platforms
+//! with custom core interrupt sources.
+//!
+//! ## `no-exceptions`
+//!
+//! Opts out of the default implementation for `_dispatch_exception` to support platforms
+//! with custom exception sources.
+//!
 //! ## `s-mode`
 //!
 //! Supervisor mode. While most registers/instructions have variants for both `mcause` and
@@ -622,7 +636,7 @@
 //!
 //! ### Example
 //!
-//! ```rust,no_run
+//! ```rust,ignore,no_run
 //! core::arch::global_asm!(
 //! r#"
 //!     .section .trap.start, "ax"
@@ -639,6 +653,20 @@
 //! "#
 //! );
 //! ```
+//!
+//! ## `device`
+//!
+//! Automatically includes `device.x` (typically provided by PACs to provide weak aliases to interrupt handlers)
+//! in the linker script.
+//!
+//! ## `memory`
+//!
+//! Automatically includes [`memory.x`](#memoryx) (typically provided by BSPs) in the linker script.
+//!
+//! ## `defmt`
+//!
+//! Implements `defmt::Format` on certain types.
+//!
 //! [attr-entry]: attr.entry.html
 //! [attr-exception]: attr.exception.html
 //! [attr-external-interrupt]: attr.external_interrupt.html
diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index d8c99330..bb73d637 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Fix broken links in register macro doc string.
 - Moved macros from `./macros/` to `../riscv-macros/`
 - Updated the license to `MIT or Apache-2.0`
 - Bump MSRV to 1.68 for latest version of syn 2.0
diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs
index ef291857..e9e9aabc 100644
--- a/riscv/src/register/macros.rs
+++ b/riscv/src/register/macros.rs
@@ -303,7 +303,7 @@ macro_rules! write_csr_as_usize_rv32 {
 
 /// Convenience macro to provide combined read/write of a CSR as a `usize`.
 ///
-/// This composes [`read_csr_as_usize`] and [`write_csr_as_usize`]. Use the
+/// This composes [read_csr_as_usize](crate::read_csr_as_usize) and [write_csr_as_usize](crate::write_csr_as_usize). Use the
 /// `safe` form to get safe wrappers instead of unsafe.
 #[macro_export]
 macro_rules! read_write_csr_as_usize {