diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index b06339f594257..2223c41237b0f 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1596,8 +1596,11 @@ supported_targets! {
     ("armebv7r-none-eabi", armebv7r_none_eabi),
     ("armebv7r-none-eabihf", armebv7r_none_eabihf),
     ("armv7r-none-eabi", armv7r_none_eabi),
+    ("thumbv7r-none-eabi", thumbv7r_none_eabi),
     ("armv7r-none-eabihf", armv7r_none_eabihf),
+    ("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
     ("armv8r-none-eabihf", armv8r_none_eabihf),
+    ("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
 
     ("armv7-rtems-eabihf", armv7_rtems_eabihf),
 
@@ -1649,7 +1652,9 @@ supported_targets! {
     ("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
 
     ("armv7a-none-eabi", armv7a_none_eabi),
+    ("thumbv7a-none-eabi", thumbv7a_none_eabi),
     ("armv7a-none-eabihf", armv7a_none_eabihf),
+    ("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
     ("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
     ("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
     ("armv7a-vex-v5", armv7a_vex_v5),
diff --git a/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs b/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs
index 6b7707a47390a..e8c5c16d8eb5e 100644
--- a/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs
+++ b/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs
@@ -1,40 +1,8 @@
-// Generic ARMv7-A target for bare-metal code - floating point disabled
-//
-// This is basically the `armv7-unknown-linux-gnueabi` target with some changes
-// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64`
-// targets:
-//
-// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned
-// memory access is disabled on boot on these cores
-// - linker changed to LLD. rationale: C is not strictly needed to build
-// bare-metal binaries (the `gcc` linker has the advantage that it knows where C
-// libraries and crt*.o are but it's not much of an advantage here); LLD is also
-// faster
-// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets
-// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic
-// linking. rationale: matches `thumb` targets
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
-    let opts = TargetOptions {
-        abi: Abi::Eabi,
-        llvm_floatabi: Some(FloatAbi::Soft),
-        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-        linker: Some("rust-lld".into()),
-        features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
-        relocation_model: RelocModel::Static,
-        disable_redzone: true,
-        max_atomic_width: Some(64),
-        panic_strategy: PanicStrategy::Abort,
-        emit_debug_gdb_scripts: false,
-        c_enum_min_bits: Some(8),
-        has_thumb_interworking: true,
-        ..Default::default()
-    };
     Target {
         llvm_target: "armv7a-none-eabi".into(),
         metadata: TargetMetadata {
@@ -46,6 +14,13 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-        options: opts,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            features: "+soft-float,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
     }
 }
diff --git a/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs
index 993390543b96d..32a79e346adcf 100644
--- a/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs
+++ b/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs
@@ -1,32 +1,8 @@
-// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes
-// FPU is present and emits FPU instructions)
-//
-// This is basically the `armv7-unknown-linux-gnueabihf` target with some
-// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal
-// `thumb` & `aarch64` targets.
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
-    let opts = TargetOptions {
-        abi: Abi::EabiHf,
-        llvm_floatabi: Some(FloatAbi::Hard),
-        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-        linker: Some("rust-lld".into()),
-        features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
-        relocation_model: RelocModel::Static,
-        disable_redzone: true,
-        max_atomic_width: Some(64),
-        panic_strategy: PanicStrategy::Abort,
-        emit_debug_gdb_scripts: false,
-        // GCC defaults to 8 for arm-none here.
-        c_enum_min_bits: Some(8),
-        has_thumb_interworking: true,
-        ..Default::default()
-    };
     Target {
         llvm_target: "armv7a-none-eabihf".into(),
         metadata: TargetMetadata {
@@ -38,6 +14,13 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-        options: opts,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
     }
 }
diff --git a/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs b/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs
index 551cbf4a589fa..114b079f360b7 100644
--- a/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs
+++ b/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs
@@ -1,15 +1,12 @@
 // Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
         llvm_target: "armv7r-none-eabi".into(),
         metadata: TargetMetadata {
-            description: Some("Armv7-R".into()),
+            description: Some("Bare Armv7-R".into()),
             tier: Some(2),
             host_tools: Some(false),
             std: Some(false),
@@ -17,20 +14,12 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-
         options: TargetOptions {
             abi: Abi::Eabi,
             llvm_floatabi: Some(FloatAbi::Soft),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }
diff --git a/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs
index 97c911ec80909..1c6114f9fc83a 100644
--- a/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs
+++ b/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs
@@ -1,15 +1,12 @@
 // Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
         llvm_target: "armv7r-none-eabihf".into(),
         metadata: TargetMetadata {
-            description: Some("Armv7-R, hardfloat".into()),
+            description: Some("Bare Armv7-R, hardfloat".into()),
             tier: Some(2),
             host_tools: Some(false),
             std: Some(false),
@@ -17,21 +14,13 @@ pub(crate) fn target() -> Target {
         pointer_width: 32,
         data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
         arch: Arch::Arm,
-
         options: TargetOptions {
             abi: Abi::EabiHf,
             llvm_floatabi: Some(FloatAbi::Hard),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             features: "+vfp3d16".into(),
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }
diff --git a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
index e36240b9c2234..16006e4c52cfb 100644
--- a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
+++ b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
@@ -1,9 +1,6 @@
 // Targets the Little-endian Cortex-R52 processor (ARMv8-R)
 
-use crate::spec::{
-    Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
-    TargetOptions,
-};
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
 
 pub(crate) fn target() -> Target {
     Target {
@@ -21,10 +18,6 @@ pub(crate) fn target() -> Target {
         options: TargetOptions {
             abi: Abi::EabiHf,
             llvm_floatabi: Some(FloatAbi::Hard),
-            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
-            linker: Some("rust-lld".into()),
-            relocation_model: RelocModel::Static,
-            panic_strategy: PanicStrategy::Abort,
             // Armv8-R requires a minimum set of floating-point features equivalent to:
             // fp-armv8, SP-only, with 16 DP (32 SP) registers
             // LLVM defines Armv8-R to include these features automatically.
@@ -36,11 +29,8 @@ pub(crate) fn target() -> Target {
             // Arm Cortex-R52 Processor Technical Reference Manual
             // - Chapter 15 Advanced SIMD and floating-point support
             max_atomic_width: Some(64),
-            emit_debug_gdb_scripts: false,
-            // GCC defaults to 8 for arm-none here.
-            c_enum_min_bits: Some(8),
             has_thumb_interworking: true,
-            ..Default::default()
+            ..base::arm_none::opts()
         },
     }
 }
diff --git a/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs
new file mode 100644
index 0000000000000..ce11e3f0875c9
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs
@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7a-none-eabi".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-A".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            features: "+soft-float,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs
new file mode 100644
index 0000000000000..12210e9c2b014
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs
@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7a-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16,-neon,+strict-align".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs
new file mode 100644
index 0000000000000..bf71d31a06ecf
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs
@@ -0,0 +1,25 @@
+// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7r-none-eabi".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-R".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::Eabi,
+            llvm_floatabi: Some(FloatAbi::Soft),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs
new file mode 100644
index 0000000000000..88b5e67644035
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs
@@ -0,0 +1,26 @@
+// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv7r-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            features: "+vfp3d16".into(),
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs
new file mode 100644
index 0000000000000..87434cd7353c0
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs
@@ -0,0 +1,36 @@
+// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
+
+use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
+
+pub(crate) fn target() -> Target {
+    Target {
+        llvm_target: "thumbv8r-none-eabihf".into(),
+        metadata: TargetMetadata {
+            description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
+            tier: Some(2),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
+        arch: Arch::Arm,
+
+        options: TargetOptions {
+            abi: Abi::EabiHf,
+            llvm_floatabi: Some(FloatAbi::Hard),
+            // Armv8-R requires a minimum set of floating-point features equivalent to:
+            // fp-armv8, SP-only, with 16 DP (32 SP) registers
+            // LLVM defines Armv8-R to include these features automatically.
+            //
+            // The Cortex-R52 supports these default features and optionally includes:
+            // neon-fp-armv8, SP+DP, with 32 DP registers
+            //
+            // Reference:
+            // Arm Cortex-R52 Processor Technical Reference Manual
+            // - Chapter 15 Advanced SIMD and floating-point support
+            max_atomic_width: Some(64),
+            has_thumb_interworking: true,
+            ..base::arm_none::opts()
+        },
+    }
+}
diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs
index 67f4eb37b2c11..27108dabe40f6 100644
--- a/src/bootstrap/src/core/sanity.rs
+++ b/src/bootstrap/src/core/sanity.rs
@@ -38,6 +38,11 @@ pub struct Finder {
 const STAGE0_MISSING_TARGETS: &[&str] = &[
     // just a dummy comment so the list doesn't get onelined
     "riscv64im-unknown-none-elf",
+    "thumbv7a-none-eabi",
+    "thumbv7a-none-eabihf",
+    "thumbv7r-none-eabi",
+    "thumbv7r-none-eabihf",
+    "thumbv8r-none-eabihf",
 ];
 
 /// Minimum version threshold for libstdc++ required when using prebuilt LLVM
diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md
index 3b8852f8ff9f7..c894f113962e7 100644
--- a/src/doc/rustc/src/SUMMARY.md
+++ b/src/doc/rustc/src/SUMMARY.md
@@ -56,15 +56,15 @@
     - [arm-none-eabi](platform-support/arm-none-eabi.md)
       - [{arm,thumb}v4t-none-eabi](platform-support/armv4t-none-eabi.md)
       - [{arm,thumb}v5te-none-eabi](platform-support/armv5te-none-eabi.md)
-      - [armv7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md)
-      - [armv7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md)
-      - [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md)
-      - [armv8r-none-eabihf](platform-support/armv8r-none-eabihf.md)
+      - [{arm,thumb}v7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md)
+      - [{arm,thumb}v7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md)
+      - [{arm,thumb}v8r-none-eabihf](platform-support/armv8r-none-eabihf.md)
       - [thumbv6m-none-eabi](./platform-support/thumbv6m-none-eabi.md)
       - [thumbv7em-none-eabi\*](./platform-support/thumbv7em-none-eabi.md)
       - [thumbv7m-none-eabi](./platform-support/thumbv7m-none-eabi.md)
       - [thumbv8m.base-none-eabi](./platform-support/thumbv8m.base-none-eabi.md)
       - [thumbv8m.main-none-eabi\*](./platform-support/thumbv8m.main-none-eabi.md)
+      - [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md)
     - [arm\*-unknown-linux-\*](./platform-support/arm-linux.md)
         - [armeb-unknown-linux-gnueabi](platform-support/armeb-unknown-linux-gnueabi.md)
         - [armv5te-unknown-linux-gnueabi](platform-support/armv5te-unknown-linux-gnueabi.md)
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
index 754d0c975ec36..ac9303dc92ba6 100644
--- a/src/doc/rustc/src/platform-support.md
+++ b/src/doc/rustc/src/platform-support.md
@@ -410,17 +410,22 @@ target | std | host | notes
 [`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * |  | Thumb-mode Bare Armv4T
 [`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * |  | Thumb-mode Bare Armv5TE
 [`thumbv6m-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv6M with NuttX
-`thumbv7a-pc-windows-msvc` |  |  |
-[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) |  |  |
+[`thumbv7a-none-eabi`](platform-support/armv7a-none-eabi.md) | * |  | Thumb-mode Bare Armv7-A
+[`thumbv7a-none-eabihf`](platform-support/armv7a-none-eabi.md) | * |  | Thumb-mode Bare Armv7-A, hardfloat
 [`thumbv7a-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv7-A with NuttX
 [`thumbv7a-nuttx-eabihf`](platform-support/nuttx.md) | ✓ |  | ARMv7-A with NuttX, hardfloat
+`thumbv7a-pc-windows-msvc` |  |  |
+[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) |  |  |
 [`thumbv7em-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv7EM with NuttX
 [`thumbv7em-nuttx-eabihf`](platform-support/nuttx.md) | ✓ |  | ARMv7EM with NuttX, hardfloat
 [`thumbv7m-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv7M with NuttX
 `thumbv7neon-unknown-linux-musleabihf` | ? |  | Thumb2-mode Armv7-A Linux with NEON, musl 1.2.5
+[`thumbv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * |  | Thumb-mode Bare Armv7-R
+[`thumbv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * |  | Thumb-mode Bare Armv7-R, hardfloat
 [`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv8M Baseline with NuttX
 [`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) | ✓ |  | ARMv8M Mainline with NuttX
 [`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) | ✓ |  | ARMv8M Mainline with NuttX, hardfloat
+[`thumbv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * |  | Thumb-mode Bare Armv8-R, hardfloat
 [`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? |  | WebAssembly
 [`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) | ? |  | WebAssembly with [WALI](https://github.com/arjunr2/WALI)
 [`wasm32-wasip3`](platform-support/wasm32-wasip3.md) | ✓ |  | WebAssembly with WASIp3
diff --git a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md
index 05afb4f4321be..6e08bbb26e466 100644
--- a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md
@@ -1,10 +1,12 @@
-# `armv7a-none-eabi` and `armv7a-none-eabihf`
+# `armv7a-none-eabi` and `thumbv7a-none-eabihf`
 
-* **Tier: 2**
+* **Tier: 2** (`armv7a-none-eabi`)
+* **Tier: 3** (`thumbv7a-none-eabi`)
 * **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
-Bare-metal target for CPUs in the Armv7-A architecture family, supporting
-dual ARM/Thumb mode, with ARM mode as the default.
+Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual
+ARM/Thumb mode. The `armv7a-none-eabi` target uses Arm mode by default and
+the `thumbv7a-none-eabihf` target uses Thumb mode by default.
 
 Note, this is for processors running in AArch32 mode. For the AArch64 mode
 added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead.
diff --git a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md
index 7f22a29f2ee68..16755ff8c520c 100644
--- a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md
@@ -1,10 +1,12 @@
 # `armv7r-none-eabi` and `armv7r-none-eabihf`
 
-* **Tier: 2**
+* **Tier: 2** (`armv7r-none-eabi`)
+* **Tier: 3** (`thumbv7r-none-eabi`)
 * **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
-Bare-metal target for CPUs in the Armv7-R architecture family, supporting
-dual ARM/Thumb mode, with ARM mode as the default.
+Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual
+ARM/Thumb mode. The `armv7r-none-eabi` target uses Arm mode by default and
+the `thumbv7r-none-eabihf` target uses Thumb mode by default.
 
 Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r].
 
diff --git a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
index 369e86dbfc7e8..ad4764122446e 100644
--- a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
+++ b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
@@ -1,10 +1,12 @@
-# `armv8r-none-eabihf`
+# `armv8r-none-eabihf` and `thumbv8r-none-eabihf`
 
-* **Tier: 2**
+* **Tier: 2**: `armv8r-none-eabihf`
+* **Tier: 3**: `thumbv8r-none-eabihf`
 * **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
-Bare-metal target for CPUs in the Armv8-R architecture family, supporting
-dual ARM/Thumb mode, with ARM mode as the default.
+Bare-metal target for CPUs in the Armv8-R architecture family, supporting dual
+ARM/Thumb mode. The `armv8r-none-eabi` target uses Arm mode by default and
+the `thumbv8r-none-eabihf` target uses Thumb mode by default.
 
 Processors in this family include the Arm [Cortex-R52][cortex-r52]
 and [Cortex-R52+][cortex-r52-plus].
diff --git a/tests/assembly-llvm/targets/targets-elf.rs b/tests/assembly-llvm/targets/targets-elf.rs
index c8b81cc858d6a..32652c52b163e 100644
--- a/tests/assembly-llvm/targets/targets-elf.rs
+++ b/tests/assembly-llvm/targets/targets-elf.rs
@@ -559,6 +559,21 @@
 //@ revisions: thumbv5te_none_eabi
 //@ [thumbv5te_none_eabi] compile-flags: --target thumbv5te-none-eabi
 //@ [thumbv5te_none_eabi] needs-llvm-components: arm
+//@ revisions: thumbv7a_none_eabi
+//@ [thumbv7a_none_eabi] compile-flags: --target thumbv7a-none-eabi
+//@ [thumbv7a_none_eabi] needs-llvm-components: arm
+//@ revisions: thumbv7a_none_eabihf
+//@ [thumbv7a_none_eabihf] compile-flags: --target thumbv7a-none-eabihf
+//@ [thumbv7a_none_eabihf] needs-llvm-components: arm
+//@ revisions: thumbv7r_none_eabi
+//@ [thumbv7r_none_eabi] compile-flags: --target thumbv7r-none-eabi
+//@ [thumbv7r_none_eabi] needs-llvm-components: arm
+//@ revisions: thumbv7r_none_eabihf
+//@ [thumbv7r_none_eabihf] compile-flags: --target thumbv7r-none-eabihf
+//@ [thumbv7r_none_eabihf] needs-llvm-components: arm
+//@ revisions: thumbv8r_none_eabihf
+//@ [thumbv8r_none_eabihf] compile-flags: --target thumbv8r-none-eabihf
+//@ [thumbv8r_none_eabihf] needs-llvm-components: arm
 //@ revisions: thumbv6m_none_eabi
 //@ [thumbv6m_none_eabi] compile-flags: --target thumbv6m-none-eabi
 //@ [thumbv6m_none_eabi] needs-llvm-components: arm