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Move register bitfield definitions to registers module.
1 parent ebeeec2 commit 331a851

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3 files changed

+171
-171
lines changed

3 files changed

+171
-171
lines changed

‎uart8250/src/lib.rs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,4 +11,5 @@ This crate provides a struct with many methods to operate an 8250 UART.
1111
pub mod registers;
1212
mod uart;
1313

14-
pub use uart::{ChipFifoInfo, InterruptType, MmioUart8250, Parity, FCR, IER, LCR, LSR, MCR, MSR};
14+
pub use registers::{FCR, IER, IIR, LCR, LSR, MCR, MSR};
15+
pub use uart::{ChipFifoInfo, InterruptType, MmioUart8250, Parity};

‎uart8250/src/registers.rs‎

Lines changed: 167 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
use crate::uart::{FCR, IER, IIR, LCR, LSR, MCR, MSR};
21
use core::u8;
32
use tock_registers::{
43
interfaces::{Readable, Writeable},
5-
register_structs,
4+
register_bitfields, register_structs,
65
registers::{Aliased, ReadOnly, ReadWrite},
76
};
87

@@ -40,6 +39,172 @@ register_structs! {
4039
}
4140
}
4241

42+
register_bitfields![
43+
u8,
44+
45+
/// Interrupt Enable Register
46+
pub IER [
47+
/// Enable Received Data Available Interrupt
48+
RDAI OFFSET(0) NUMBITS(1) [],
49+
/// Enable Transmitter Holding Register Empty Interrupt
50+
THREI OFFSET(1) NUMBITS(1) [],
51+
/// Enable Receiver Line Status Interrupt
52+
RLSI OFFSET(2) NUMBITS(1) [],
53+
/// Enable Modem Status Interrupt
54+
MSI OFFSET(3) NUMBITS(1) [],
55+
/// Enable Sleep Mode (16750)
56+
SM OFFSET(4) NUMBITS(1) [],
57+
/// Enable Low Power Mode (16750)
58+
LPM OFFSET(5) NUMBITS(1) [],
59+
],
60+
61+
/// Line Control Register
62+
pub LCR [
63+
/// Divisor Latch Access Bit
64+
DLAB OFFSET(7) NUMBITS(1) [],
65+
/// Set Break Enable
66+
SBE OFFSET(6) NUMBITS(1) [],
67+
/// Parity
68+
Parity OFFSET(3) NUMBITS(3) [
69+
/// No parity
70+
No = 0,
71+
/// Odd parity
72+
Odd = 1,
73+
/// Even parity
74+
Even = 3,
75+
/// Mark
76+
Mark = 5,
77+
/// Space
78+
Space = 7,
79+
],
80+
/// Number of stop bits
81+
STOP_BITS OFFSET(2) NUMBITS(1) [
82+
/// One stop bit
83+
One = 0,
84+
/// 1.5 or 2 stop bits
85+
Two = 1,
86+
],
87+
/// Word length
88+
WORD_LENGTH OFFSET(0) NUMBITS(2) [
89+
/// 5 bit word length
90+
Bits5 = 0,
91+
/// 6 bit word length
92+
Bits6 = 1,
93+
/// 7 bit word length
94+
Bits7 = 2,
95+
/// 8 bit word length
96+
Bits8 = 3,
97+
],
98+
],
99+
100+
/// Line Status Register
101+
pub LSR [
102+
/// Data Ready
103+
DR OFFSET(0) NUMBITS(1) [],
104+
/// Overrun Error
105+
OE OFFSET(1) NUMBITS(1) [],
106+
/// Parity Error
107+
PE OFFSET(2) NUMBITS(1) [],
108+
/// Framing Error
109+
FE OFFSET(3) NUMBITS(1) [],
110+
/// Break Interrupt
111+
BI OFFSET(4) NUMBITS(1) [],
112+
/// Transmitter Holding Register Empty
113+
THRE OFFSET(5) NUMBITS(1) [],
114+
/// Data Holding Regiters Empty
115+
DHRE OFFSET(6) NUMBITS(1) [],
116+
/// Error in Received FIFO
117+
RFE OFFSET(7) NUMBITS(1) [],
118+
],
119+
120+
/// Modem Status Register
121+
pub MSR [
122+
/// Delta Clear To Send
123+
DCTS OFFSET(0) NUMBITS(1) [],
124+
/// Delta Data Set Ready
125+
DDSR OFFSET(1) NUMBITS(1) [],
126+
/// Trailing Edge Ring Indicator
127+
TERI OFFSET(2) NUMBITS(1) [],
128+
/// Delta Data Carrier Detect
129+
DDCD OFFSET(3) NUMBITS(1) [],
130+
/// Clear To Send
131+
CTS OFFSET(4) NUMBITS(1) [],
132+
/// Data Set Ready
133+
DSR OFFSET(5) NUMBITS(1) [],
134+
/// Ring Indicator
135+
RI OFFSET(6) NUMBITS(1) [],
136+
/// Carrier Detect
137+
CD OFFSET(7) NUMBITS(1) [],
138+
],
139+
140+
/// FIFO Control Register
141+
pub FCR [
142+
/// Interrupt trigger level.
143+
InterruptTriggerLevel OFFSET(6) NUMBITS(2) [
144+
/// Interrupt trigger level is 1 byte.
145+
Bytes1 = 0,
146+
/// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively.
147+
Bytes4Or16 = 1,
148+
/// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively.
149+
Bytes8Or32 = 2,
150+
/// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively.
151+
Bytes14Or56 = 3,
152+
],
153+
/// Enable 64 byte FIFO (16750)
154+
Enable64Byte OFFSET(5) NUMBITS(1) [],
155+
/// DMA mode select
156+
DmaMode OFFSET(3) NUMBITS(1) [],
157+
/// Clear transmit FIFO
158+
ClearTx OFFSET(2) NUMBITS(1) [],
159+
/// Clear receive FIFO
160+
ClearRx OFFSET(1) NUMBITS(1) [],
161+
/// Enable FIFOs.
162+
Enable OFFSET(0) NUMBITS(1) [],
163+
],
164+
165+
/// Interrupt Identification Register
166+
pub IIR [
167+
FifoInfo OFFSET(6) NUMBITS(2) [
168+
/// No FIFO on chip.
169+
None = 0,
170+
/// Reserved value.
171+
Reserved = 1,
172+
/// FIFO enabled but not functioning.
173+
EnabledNotFunctioning = 2,
174+
/// FIFO enabled.
175+
Enabled = 3,
176+
],
177+
/// 64 byte FIFO enabled (16750 only).
178+
Fifo64Byte OFFSET(5) NUMBITS(1) [],
179+
InterruptType OFFSET(1) NUMBITS(3) [
180+
ModemStatus = 0,
181+
TransmitterHoldingRegisterEmpty = 1,
182+
ReceivedDataAvailable = 2,
183+
ReceiverLineStatus = 3,
184+
Reserved = 4,
185+
Timeout = 6,
186+
],
187+
/// Interrupt pending flag.
188+
InterruptPending OFFSET(0) NUMBITS(1) [],
189+
],
190+
191+
/// Modem Control Register (bitflags)
192+
pub MCR [
193+
/// Autoflow control enabled (16750)
194+
AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [],
195+
/// Loopback mode
196+
LOOPBACK_MODE OFFSET(4) NUMBITS(1) [],
197+
/// Auxiliary output 2
198+
AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [],
199+
/// Auxiliary output 1
200+
AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [],
201+
/// Request to Send
202+
RTS OFFSET(1) NUMBITS(1) [],
203+
/// Data Terminal Ready
204+
DTR OFFSET(0) NUMBITS(1) [],
205+
],
206+
];
207+
43208
impl Registers {
44209
/// Constructs a new instance of the UART registers starting at the given base address.
45210
pub fn from_base_address(base_address: usize) -> &'static mut Self {

‎uart8250/src/uart.rs‎

Lines changed: 2 additions & 168 deletions
Original file line numberDiff line numberDiff line change
@@ -3,176 +3,10 @@ use core::fmt;
33
use tock_registers::{
44
fields::{Field, FieldValue},
55
interfaces::{ReadWriteable, Readable, Writeable},
6-
register_bitfields, LocalRegisterCopy, RegisterLongName,
6+
LocalRegisterCopy, RegisterLongName,
77
};
88

9-
use crate::registers::Registers;
10-
11-
register_bitfields![
12-
u8,
13-
14-
/// Interrupt Enable Register
15-
pub IER [
16-
/// Enable Received Data Available Interrupt
17-
RDAI OFFSET(0) NUMBITS(1) [],
18-
/// Enable Transmitter Holding Register Empty Interrupt
19-
THREI OFFSET(1) NUMBITS(1) [],
20-
/// Enable Receiver Line Status Interrupt
21-
RLSI OFFSET(2) NUMBITS(1) [],
22-
/// Enable Modem Status Interrupt
23-
MSI OFFSET(3) NUMBITS(1) [],
24-
/// Enable Sleep Mode (16750)
25-
SM OFFSET(4) NUMBITS(1) [],
26-
/// Enable Low Power Mode (16750)
27-
LPM OFFSET(5) NUMBITS(1) [],
28-
],
29-
30-
/// Line Control Register
31-
pub LCR [
32-
/// Divisor Latch Access Bit
33-
DLAB OFFSET(7) NUMBITS(1) [],
34-
/// Set Break Enable
35-
SBE OFFSET(6) NUMBITS(1) [],
36-
/// Parity
37-
Parity OFFSET(3) NUMBITS(3) [
38-
/// No parity
39-
No = 0,
40-
/// Odd parity
41-
Odd = 1,
42-
/// Even parity
43-
Even = 3,
44-
/// Mark
45-
Mark = 5,
46-
/// Space
47-
Space = 7,
48-
],
49-
/// Number of stop bits
50-
STOP_BITS OFFSET(2) NUMBITS(1) [
51-
/// One stop bit
52-
One = 0,
53-
/// 1.5 or 2 stop bits
54-
Two = 1,
55-
],
56-
/// Word length
57-
WORD_LENGTH OFFSET(0) NUMBITS(2) [
58-
/// 5 bit word length
59-
Bits5 = 0,
60-
/// 6 bit word length
61-
Bits6 = 1,
62-
/// 7 bit word length
63-
Bits7 = 2,
64-
/// 8 bit word length
65-
Bits8 = 3,
66-
],
67-
],
68-
69-
/// Line Status Register
70-
pub LSR [
71-
/// Data Ready
72-
DR OFFSET(0) NUMBITS(1) [],
73-
/// Overrun Error
74-
OE OFFSET(1) NUMBITS(1) [],
75-
/// Parity Error
76-
PE OFFSET(2) NUMBITS(1) [],
77-
/// Framing Error
78-
FE OFFSET(3) NUMBITS(1) [],
79-
/// Break Interrupt
80-
BI OFFSET(4) NUMBITS(1) [],
81-
/// Transmitter Holding Register Empty
82-
THRE OFFSET(5) NUMBITS(1) [],
83-
/// Data Holding Regiters Empty
84-
DHRE OFFSET(6) NUMBITS(1) [],
85-
/// Error in Received FIFO
86-
RFE OFFSET(7) NUMBITS(1) [],
87-
],
88-
89-
/// Modem Status Register
90-
pub MSR [
91-
/// Delta Clear To Send
92-
DCTS OFFSET(0) NUMBITS(1) [],
93-
/// Delta Data Set Ready
94-
DDSR OFFSET(1) NUMBITS(1) [],
95-
/// Trailing Edge Ring Indicator
96-
TERI OFFSET(2) NUMBITS(1) [],
97-
/// Delta Data Carrier Detect
98-
DDCD OFFSET(3) NUMBITS(1) [],
99-
/// Clear To Send
100-
CTS OFFSET(4) NUMBITS(1) [],
101-
/// Data Set Ready
102-
DSR OFFSET(5) NUMBITS(1) [],
103-
/// Ring Indicator
104-
RI OFFSET(6) NUMBITS(1) [],
105-
/// Carrier Detect
106-
CD OFFSET(7) NUMBITS(1) [],
107-
],
108-
109-
/// FIFO Control Register
110-
pub FCR [
111-
/// Interrupt trigger level.
112-
InterruptTriggerLevel OFFSET(6) NUMBITS(2) [
113-
/// Interrupt trigger level is 1 byte.
114-
Bytes1 = 0,
115-
/// Interrupt trigger level is 4 or 16 bytes, for 16 or 64 byte FIFO respectively.
116-
Bytes4Or16 = 1,
117-
/// Interrupt trigger level is 8 or 32 bytes, for 16 or 64 byte FIFO respectively.
118-
Bytes8Or32 = 2,
119-
/// Interrupt trigger level is 14 or 56 bytes, for 16 or 64 byte FIFO respectively.
120-
Bytes14Or56 = 3,
121-
],
122-
/// Enable 64 byte FIFO (16750)
123-
Enable64Byte OFFSET(5) NUMBITS(1) [],
124-
/// DMA mode select
125-
DmaMode OFFSET(3) NUMBITS(1) [],
126-
/// Clear transmit FIFO
127-
ClearTx OFFSET(2) NUMBITS(1) [],
128-
/// Clear receive FIFO
129-
ClearRx OFFSET(1) NUMBITS(1) [],
130-
/// Enable FIFOs.
131-
Enable OFFSET(0) NUMBITS(1) [],
132-
],
133-
134-
/// Interrupt Identification Register
135-
pub IIR [
136-
FifoInfo OFFSET(6) NUMBITS(2) [
137-
/// No FIFO on chip.
138-
None = 0,
139-
/// Reserved value.
140-
Reserved = 1,
141-
/// FIFO enabled but not functioning.
142-
EnabledNotFunctioning = 2,
143-
/// FIFO enabled.
144-
Enabled = 3,
145-
],
146-
/// 64 byte FIFO enabled (16750 only).
147-
Fifo64Byte OFFSET(5) NUMBITS(1) [],
148-
InterruptType OFFSET(1) NUMBITS(3) [
149-
ModemStatus = 0,
150-
TransmitterHoldingRegisterEmpty = 1,
151-
ReceivedDataAvailable = 2,
152-
ReceiverLineStatus = 3,
153-
Reserved = 4,
154-
Timeout = 6,
155-
],
156-
/// Interrupt pending flag.
157-
InterruptPending OFFSET(0) NUMBITS(1) [],
158-
],
159-
160-
/// Modem Control Register (bitflags)
161-
pub MCR [
162-
/// Autoflow control enabled (16750)
163-
AUTOFLOW_CONTROL_ENABLED OFFSET(5) NUMBITS(1) [],
164-
/// Loopback mode
165-
LOOPBACK_MODE OFFSET(4) NUMBITS(1) [],
166-
/// Auxiliary output 2
167-
AUX_OUTPUT_2 OFFSET(3) NUMBITS(1) [],
168-
/// Auxiliary output 1
169-
AUX_OUTPUT_1 OFFSET(2) NUMBITS(1) [],
170-
/// Request to Send
171-
RTS OFFSET(1) NUMBITS(1) [],
172-
/// Data Terminal Ready
173-
DTR OFFSET(0) NUMBITS(1) [],
174-
],
175-
];
9+
use crate::registers::{Registers, FCR, IER, IIR, LCR, LSR, MCR, MSR};
17610

17711
pub type ChipFifoInfo = IIR::FifoInfo::Value;
17812
pub type InterruptType = IIR::InterruptType::Value;

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