@@ -31,7 +31,7 @@ impl<'a> MmioUart8250<'a> {
3131 ///
3232 /// More customised initialisation can be done using other methods below.
3333 pub fn init ( & self , clock : usize , baud_rate : usize ) {
34- // Enable DLAB and Set divisor
34+ // Enable DLAB and set divisor
3535 self . set_divisor ( clock, baud_rate) ;
3636
3737 // Disable DLAB and set word length 8 bits, no parity, 1 stop bit
@@ -421,3 +421,53 @@ fn toggle_field<R: RegisterLongName>(
421421 let toggled = !field_value;
422422 register. modify_no_read ( original, field. val ( u8:: from ( toggled) ) ) ;
423423}
424+
425+ #[ cfg( test) ]
426+ mod tests {
427+ use super :: * ;
428+
429+ // These tests treat normal memory as device memory, which is not necessarily guaranteed to
430+ // work, but it seems to for now.
431+
432+ #[ test]
433+ fn initialise ( ) {
434+ // Create a fake UART using an in-memory buffer, and check that it is initialised as
435+ // expected.
436+ let mut fake_registers: [ u8 ; 8 ] = [ 0xff ; 8 ] ;
437+ let uart = MmioUart8250 :: new ( & mut fake_registers as * mut u8 as usize ) ;
438+
439+ uart. init ( 11_059_200 , 115200 ) ;
440+
441+ assert ! ( matches!( uart. get_parity( ) , Parity :: No ) ) ;
442+ assert_eq ! ( uart. get_stop_bit( ) , 1 ) ;
443+ assert_eq ! ( uart. get_word_length( ) , 8 ) ;
444+ assert_eq ! ( uart. is_divisor_latch_accessible( ) , false ) ;
445+ }
446+
447+ #[ test]
448+ fn write ( ) {
449+ let mut fake_registers: [ u8 ; 8 ] = [ 0 ; 8 ] ;
450+ let uart = MmioUart8250 :: new ( & mut fake_registers as * mut u8 as usize ) ;
451+ uart. init ( 11_059_200 , 115200 ) ;
452+
453+ uart. write_byte ( 0x42 ) ;
454+
455+ assert_eq ! ( fake_registers[ 0 ] , 0x42 ) ;
456+ }
457+
458+ #[ test]
459+ fn read ( ) {
460+ let mut fake_registers: [ u8 ; 8 ] = [ 0 ; 8 ] ;
461+ let uart = MmioUart8250 :: new ( & mut fake_registers as * mut u8 as usize ) ;
462+ uart. init ( 11_059_200 , 115200 ) ;
463+
464+ // First try to read when there is nothing available.
465+ assert_eq ! ( uart. read_byte( ) , None ) ;
466+
467+ // Set the UART up to have a byte available to read and read it.
468+ fake_registers[ 0 ] = 0xab ;
469+ fake_registers[ 5 ] = 0x01 ;
470+
471+ assert_eq ! ( uart. read_byte( ) , Some ( 0xab ) ) ;
472+ }
473+ }
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