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Add some tests.
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uart8250/src/uart.rs

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ impl<'a> MmioUart8250<'a> {
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///
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/// More customised initialisation can be done using other methods below.
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pub fn init(&self, clock: usize, baud_rate: usize) {
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// Enable DLAB and Set divisor
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// Enable DLAB and set divisor
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self.set_divisor(clock, baud_rate);
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// Disable DLAB and set word length 8 bits, no parity, 1 stop bit
@@ -421,3 +421,53 @@ fn toggle_field<R: RegisterLongName>(
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let toggled = !field_value;
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register.modify_no_read(original, field.val(u8::from(toggled)));
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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// These tests treat normal memory as device memory, which is not necessarily guaranteed to
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// work, but it seems to for now.
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#[test]
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fn initialise() {
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// Create a fake UART using an in-memory buffer, and check that it is initialised as
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// expected.
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let mut fake_registers: [u8; 8] = [0xff; 8];
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let uart = MmioUart8250::new(&mut fake_registers as *mut u8 as usize);
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uart.init(11_059_200, 115200);
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assert!(matches!(uart.get_parity(), Parity::No));
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assert_eq!(uart.get_stop_bit(), 1);
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assert_eq!(uart.get_word_length(), 8);
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assert_eq!(uart.is_divisor_latch_accessible(), false);
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}
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#[test]
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fn write() {
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let mut fake_registers: [u8; 8] = [0; 8];
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let uart = MmioUart8250::new(&mut fake_registers as *mut u8 as usize);
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uart.init(11_059_200, 115200);
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uart.write_byte(0x42);
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assert_eq!(fake_registers[0], 0x42);
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}
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#[test]
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fn read() {
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let mut fake_registers: [u8; 8] = [0; 8];
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let uart = MmioUart8250::new(&mut fake_registers as *mut u8 as usize);
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uart.init(11_059_200, 115200);
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// First try to read when there is nothing available.
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assert_eq!(uart.read_byte(), None);
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// Set the UART up to have a byte available to read and read it.
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fake_registers[0] = 0xab;
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fake_registers[5] = 0x01;
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assert_eq!(uart.read_byte(), Some(0xab));
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}
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}

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