clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks

This enable the CLK_SET_RATE_PARENT flags for DP audio clock and
RPLL_TO_FPD. In this way, request for audio clock frequency will
propagate to the parent PLL clock.

Signed-off-by: Hyun Kwon <[email protected]>
Acked-by: Shubhrajyoti Datta <[email protected]>
Signed-off-by: Michal Simek <[email protected]>

Author: xlnx-hyunkwon

drivers/clk/zynqmp/clkc.c

@@ -551,7 +551,7 @@ static void __init zynqmp_clk_setup(struct device_node *np)
 			8, 6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO);
 
 	clks[rpll_to_fpd] = zynqmp_clk_register_divider(NULL, "rpll_to_fpd",
-			clk_output_name[rpll], 0,
+			clk_output_name[rpll], CLK_SET_RATE_PARENT,
 			(resource_size_t *)CRL_APB_RPLL_TO_FPD_CTRL, 8,
 			6, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO);
 
@@ -746,7 +746,7 @@ static void __init zynqmp_clk_setup(struct device_node *np)
 			CRF_APB_DP_VIDEO_REF_CTRL,
 			periph_parents[dp_video_ref], 1, 1, 24);
 
-	zynqmp_clk_register_periph_clk(0, dp_audio_ref,
+	zynqmp_clk_register_periph_clk(CLK_SET_RATE_PARENT, dp_audio_ref,
 			clk_output_name[dp_audio_ref],
 			CRF_APB_DP_AUDIO_REF_CTRL,
 			periph_parents[dp_audio_ref], 1, 1, 24);