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- Bug fixes to AnalogCore and Keras network conversion
- New Array circuit simulation interface for improved and more flexible parasitics simulation
- Improvement to torch gradient calculation and AnalogLayer interface changes to support new approach
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The optimized ADC limits are only valid for a specific combination of neural network and hardware settings. The ``adc_limits`` directory contains calibrated ADC limits for a number of neural networks that are part of the ``cross-sim-models`` submodule, but does not account for every possible simulation configuration with these models. The most extensive set of ADC limits we have generated are for the ResNet50-v1.5 network (part of the MLPerf Inference benchmark). These can be found inside the ``adc_limits/imagenet`` and ``adc_limits/imagenet_bitslicing`` folders. See ``interface/dnn_setup.py`` to see the simulation settings that are matched to these different calibrated ADC limits.
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[1] T. P. Xiao, B. Feinberg, C. H. Bennett, V. Prabhakar, P. Saxena, V. Agrawal, S. Agarwal, and M. J. Marinella, "On the accuracy of analog neural network inference accelerators," _IEEE Circuits and Systems Magazine_, 22(4), pp. 26-48, 2022.
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[1] T. P. Xiao, B. Feinberg, C. H. Bennett, V. Prabhakar, P. Saxena, V. Agrawal, S. Agarwal, and M. J. Marinella, "On the accuracy of analog neural network inference accelerators," _IEEE Circuits and Systems Magazine_, 22(4), pp. 26-48, 2022.
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