migrate shift opcode (#1025)

To close #1016


### stats
```diff
+---------------+---------------+---------+-------+-----------+--------+------------+---------------------+
| opcode_name   | num_instances | lookups | reads | witnesses | writes | 0_expr_deg | 0_expr_sumcheck_deg |
+---------------+---------------+---------+-------+-----------+--------+------------+---------------------+
-| SLL           | 0             | 15      | 4     | 29        | 4      | [1: 5]     | [2: 1]              |
+| SLL           | 0             | 17      | 4     | 47        | 4      | [1: 6]     | [3: 10,2: 27]       |
-| SLLI          | 0             | 9       | 3     | 20        | 3      | [1: 3]     | [2: 1]              |
+| SLLI          | 0             | 15      | 3     | 40        | 3      | [1: 5]     | [2: 27,3: 10]       |
-| SRA           | 0             | 16      | 4     | 30        | 4      | [1: 5]     | [2: 2]              |
+| SRA           | 0             | 18      | 4     | 47        | 4      | [1: 5]     | [3: 10,2: 27]       |
-| SRAI          | 0             | 10      | 3     | 21        | 3      | [1: 3]     | [2: 2]              |
+| SRAI          | 0             | 16      | 3     | 40        | 3      | [1: 4]     | [2: 27,3: 10]       |
-| SRL           | 0             | 15      | 4     | 29        | 4      | [1: 5]     | [2: 1]              |
+| SRL           | 0             | 17      | 4     | 47        | 4      | [1: 6]     | [2: 27,3: 10]       |
-| SRLI          | 0             | 9       | 3     | 20        | 3      | [1: 3]     | [2: 1]              |
+| SRLI          | 0             | 15      | 3     | 40        | 3      | [1: 5]     | [3: 10,2: 27]       |
+---------------+---------------+---------+-------+-----------+--------+------------+---------------------+
```

---------

Co-authored-by: Wu Sung-Ming <[email protected]>

Author: hero78119

ceno_zkvm/src/instructions/riscv/insn_base.rs

@@ -506,7 +506,6 @@ impl<E: ExtensionField> MemAddr<E> {
         // Range check the high limb.
         for i in 1..UINT_LIMBS {
             let high_u16 = (addr >> (i * 16)) & 0xffff;
-            println!("assignment max bit {}", (self.max_bits - i * 16).min(16));
             lkm.assert_ux_v2(high_u16 as u64, (self.max_bits - i * 16).min(16));
         }
 

ceno_zkvm/src/instructions/riscv/rv32im.rs

@@ -6,7 +6,6 @@ use super::{
 use crate::instructions::riscv::auipc::AuipcInstruction;
 #[cfg(feature = "u16limb_circuit")]
 use crate::instructions::riscv::lui::LuiInstruction;
-
 use crate::{
     error::ZKVMError,
     instructions::{