From 874ca2b5f77b6801e6723cc43d0c690bef65bb53 Mon Sep 17 00:00:00 2001 From: George Small Date: Mon, 14 Sep 2020 14:08:17 -0400 Subject: [PATCH] Fix flash latency for F4x5RG running full speed at 168MHz Change 2 instances: HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) --> HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) --- variants/Generic_F4x5RG/variant.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/Generic_F4x5RG/variant.cpp b/variants/Generic_F4x5RG/variant.cpp index 6ac8661d90..557d41e480 100644 --- a/variants/Generic_F4x5RG/variant.cpp +++ b/variants/Generic_F4x5RG/variant.cpp @@ -158,7 +158,7 @@ static uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL } @@ -208,7 +208,7 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { return 0; // FAIL }