Debugging / controlling the CPU via JTAG

[RoccoMatano]

I searched the NEORV32 data sheet but could not find any information about JTAG debugging. So my question is: Does the NEORV32 offer a JTAG-Debbuging module? If so: Does it adhere to the RISC-V Debug Specification?

[stnolting]

The NEORV32 does not provide any hardware in-circuit debugging module (yet).

When I started this project, I did not see any need for some kind of advanced in-circuit debugging. I mean, it is a soft-core processor that can be completely simulated giving you access to every single signal, right? 😉

However, as the software overheads are getting more and more complex, simulation takes quite some time and at some point it is not very productive anymore. Of course you can always do "in-circuit debugging" using printf and the NEORV32 runtime environment provides some help to check for asynchronous events (unexpected traps), but this is rather a hacky approach and far away from established debugging schemes.

The debugger is already on the CPU's ToDo list but unfortunately I haven't had the time to deal with it so far.

[RoccoMatano]

Thank you for your explanations. I am working on the microcontroller code for projects, some of which also use synthesized CPUs. In fact I do lots of debugging with printf. But as the code is quite large (>1MByte) and has lots of complicated interactions between microcontroller and IO-devices, there is no way of getting away without JTAG debugging (setting 'normal' breakpoints, using HW breakpoints, using single stepping, watching register and memory content etc.).
Right now there is an investigation if a Lattice FPGA with a RISC-V might be the right platform for a new project. During this I came across NEORV32. But I certainly don't want to work on this project without JTAG debugging.

[stnolting]

Just for the records: On-chip debugging via OpenOCD + gdb has been added with version 1.5.5.8 (#28).