Adding external memory for simulation #343
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There is no need to add that memory component to the You'll need some kind of top entity that instantiates the memory component and the NEORV32 itself. You can take the default testbench as an example, which also includes a Wishbone-coupled memory: https://github.com/stnolting/neorv32/blob/main/sim/simple/neorv32_tb.simple.vhd Btw, this is a Wishbone dummy I have written some time ago. It takes care of the address mapping itself and you can use this "skeleton" to build a Wishbone-compatible memory if you like. |
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VUnit's Verification Component Library provides VCs for RAM memories which can be interfaced through Wishbone VCs. See http://vunit.github.io/verification_components/user_guide.html. The infrastructure for using VUnit is available in this repo already. |
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In order to add a new memory module to connect throw wishbone as said in #342, all I have to do is add the new files to the neorv32 library and modify the top_inst file?
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