From 384e0ba4df9efa1bdbb3749e9914033465441a91 Mon Sep 17 00:00:00 2001 From: Guy Hutchison Date: Tue, 12 Apr 2016 17:10:41 -0700 Subject: [PATCH 1/4] Added blocks for input, output, and input-output timing closure --- src/main/scala/ChiselUtil.scala | 81 +++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala index e9077b45..44c10fb2 100644 --- a/src/main/scala/ChiselUtil.scala +++ b/src/main/scala/ChiselUtil.scala @@ -876,3 +876,84 @@ object DelayBetween { nodeShortestPathSearch(List(b), a) } } + +/** @param data The data type for the payload + * + * The DCInput module provides timing closure on the INPUT + * side of a module by registering the "ready" signal coming + * out of a larger design block. This is consistent with a + * registered-output design methodology. + */ +class DCInput[D <: Bits](data: D) extends Module { + val io = new Bundle { + val c = new DecoupledIO(data).flip + val p = new DecoupledIO(data) + } + val nxt_occupied = Bool() + val occupied = Reg(next = nxt_occupied, init = Bool(false)) + val nxt_hold = UInt() + val hold = Reg(next = nxt_hold) + val drain = occupied & io.p.ready + val load = io.c.valid & io.c.ready & (!io.p.ready | drain) + val nxt_c_drdy = (!occupied & !load) | (drain & !load) + val c_drdy = Reg(next = nxt_c_drdy, init = Bool(false)) + + when (occupied) + { io.p.bits := hold } + .otherwise + { io.p.bits := io.c.bits } + io.p.valid := (io.c.valid & io.c.ready) | occupied + nxt_hold := hold + when (load) { + nxt_hold := io.c.bits + nxt_occupied := Bool(true) + }.elsewhen (drain) { + nxt_occupied := Bool(false) + }.otherwise { + nxt_occupied := occupied + } + io.c.ready := c_drdy +} + +/** @param data The data type for the payload + * + * The DCOutput module provides timing closure on the output + * side of a module by registering the "valid" and "bits" signals coming + * out of a larger design block. This is consistent with a + * registered-output design methodology. + */ +class DCOutput[T <: Data](data: T) extends Module { + val io = new Bundle { + val c = new DecoupledIO(data).flip + val p = new DecoupledIO(data) + } + val nxt_p_valid = io.c.valid | (!io.p.ready & io.p.valid) + io.p.valid := Reg(next = nxt_p_valid, init=Bool(false)) + io.c.ready := io.p.ready | !io.p.valid + val load = io.c.valid & io.c.ready + //val nxt_p_data = UInt(io.c.bits) + val p_bits = Reg(io.c.bits) + when (load) { + p_bits := io.c.bits + } + io.p.bits := p_bits +} + +/** @param data The data type for the payload + * + * The DCFull module provides timing closure for either the INPUT + * or output side of a module by registering all inputs and outputs. + * This is consistent with a registered-input, registered-output + * design methodology. + */ +class DCFull[T <: Data](data: T) extends Module { + val io = new Bundle { + val c = new DecoupledIO(data).flip + val p = new DecoupledIO(data) + } + val dci = Module(new DCInput(type)) + val dco = Module(new DCOutput(type)) + io.c <> dci.io.c + dci.io.p <> dco.io.c + dco.io.p <> io.p +} From 7afc673c2108847546d82597a36e6fd0c78028ce Mon Sep 17 00:00:00 2001 From: Guy Hutchison Date: Tue, 12 Apr 2016 20:50:54 -0700 Subject: [PATCH 2/4] Removed DCFull class until syntax errors can be resolved --- src/main/scala/ChiselUtil.scala | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala index 44c10fb2..b3c24dee 100644 --- a/src/main/scala/ChiselUtil.scala +++ b/src/main/scala/ChiselUtil.scala @@ -884,7 +884,7 @@ object DelayBetween { * out of a larger design block. This is consistent with a * registered-output design methodology. */ -class DCInput[D <: Bits](data: D) extends Module { +class DCInput[T <: Bits](data: T) extends Module { val io = new Bundle { val c = new DecoupledIO(data).flip val p = new DecoupledIO(data) @@ -938,22 +938,3 @@ class DCOutput[T <: Data](data: T) extends Module { } io.p.bits := p_bits } - -/** @param data The data type for the payload - * - * The DCFull module provides timing closure for either the INPUT - * or output side of a module by registering all inputs and outputs. - * This is consistent with a registered-input, registered-output - * design methodology. - */ -class DCFull[T <: Data](data: T) extends Module { - val io = new Bundle { - val c = new DecoupledIO(data).flip - val p = new DecoupledIO(data) - } - val dci = Module(new DCInput(type)) - val dco = Module(new DCOutput(type)) - io.c <> dci.io.c - dci.io.p <> dco.io.c - dco.io.p <> io.p -} From bdfd20da815e2903c9874413cdd358c336567dfe Mon Sep 17 00:00:00 2001 From: Guy Hutchison Date: Thu, 14 Apr 2016 11:18:11 -0700 Subject: [PATCH 3/4] Replaced DCOutput implementation with single-entry Queue --- src/main/scala/ChiselUtil.scala | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala index b3c24dee..fb9178d7 100644 --- a/src/main/scala/ChiselUtil.scala +++ b/src/main/scala/ChiselUtil.scala @@ -917,24 +917,6 @@ class DCInput[T <: Bits](data: T) extends Module { /** @param data The data type for the payload * - * The DCOutput module provides timing closure on the output - * side of a module by registering the "valid" and "bits" signals coming - * out of a larger design block. This is consistent with a - * registered-output design methodology. + * Syntactic sugar for a single-entry queue which registers valid and bits. */ -class DCOutput[T <: Data](data: T) extends Module { - val io = new Bundle { - val c = new DecoupledIO(data).flip - val p = new DecoupledIO(data) - } - val nxt_p_valid = io.c.valid | (!io.p.ready & io.p.valid) - io.p.valid := Reg(next = nxt_p_valid, init=Bool(false)) - io.c.ready := io.p.ready | !io.p.valid - val load = io.c.valid & io.c.ready - //val nxt_p_data = UInt(io.c.bits) - val p_bits = Reg(io.c.bits) - when (load) { - p_bits := io.c.bits - } - io.p.bits := p_bits -} +class DCOutput[T <: Data](data: T) extends Queue(data, 1, false, false) From 52f7576b59a7a4d793846031a233d1d2c9e66036 Mon Sep 17 00:00:00 2001 From: Guy Hutchison Date: Thu, 14 Apr 2016 11:24:49 -0700 Subject: [PATCH 4/4] Changed to pipe=true for a full throughput queue --- src/main/scala/ChiselUtil.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/ChiselUtil.scala b/src/main/scala/ChiselUtil.scala index fb9178d7..464699a3 100644 --- a/src/main/scala/ChiselUtil.scala +++ b/src/main/scala/ChiselUtil.scala @@ -919,4 +919,4 @@ class DCInput[T <: Bits](data: T) extends Module { * * Syntactic sugar for a single-entry queue which registers valid and bits. */ -class DCOutput[T <: Data](data: T) extends Queue(data, 1, false, false) +class DCOutput[T <: Data](data: T) extends Queue(data, 1, true, false)