diff --git a/include/uc_priv.h b/include/uc_priv.h index f3a1c045e7..9e41f1cf57 100644 --- a/include/uc_priv.h +++ b/include/uc_priv.h @@ -31,6 +31,7 @@ #define UC_MODE_SPARC_MASK \ (UC_MODE_SPARC32 | UC_MODE_SPARC64 | UC_MODE_BIG_ENDIAN) #define UC_MODE_M68K_MASK (UC_MODE_BIG_ENDIAN) +#define UC_MODE_RH850_MASK (UC_MODE_LITTLE_ENDIAN) #define UC_MODE_RISCV_MASK \ (UC_MODE_RISCV32 | UC_MODE_RISCV64 | UC_MODE_LITTLE_ENDIAN) #define UC_MODE_S390X_MASK (UC_MODE_BIG_ENDIAN) diff --git a/include/unicorn/rh850.h b/include/unicorn/rh850.h index 963e0bc042..5f030a2b54 100644 --- a/include/unicorn/rh850.h +++ b/include/unicorn/rh850.h @@ -12,15 +12,6 @@ extern "C" { #pragma warning(disable : 4201) #endif -#define UC_RH850_SYSREG_SELID0 32 -#define UC_RH850_SYSREG_SELID1 64 -#define UC_RH850_SYSREG_SELID2 96 -#define UC_RH850_SYSREG_SELID3 128 -#define UC_RH850_SYSREG_SELID4 160 -#define UC_RH850_SYSREG_SELID5 192 -#define UC_RH850_SYSREG_SELID6 224 -#define UC_RH850_SYSREG_SELID7 256 - //> RH850 global purpose registers typedef enum uc_rh850_reg { UC_RH850_REG_R0 = 0, @@ -57,7 +48,7 @@ typedef enum uc_rh850_reg { UC_RH850_REG_R31, //> RH850 system registers, selection ID 0 - UC_RH850_REG_EIPC = UC_RH850_SYSREG_SELID0, + UC_RH850_REG_EIPC, UC_RH850_REG_EIPSW, UC_RH850_REG_FEPC, UC_RH850_REG_FEPSW, @@ -69,43 +60,43 @@ typedef enum uc_rh850_reg { UC_RH850_REG_FPCC, UC_RH850_REG_FPCFG, UC_RH850_REG_FPEC, - UC_RH850_REG_EIIC = UC_RH850_SYSREG_SELID0 + 13, + UC_RH850_REG_EIIC, UC_RH850_REG_FEIC, - UC_RH850_REG_CTPC = UC_RH850_SYSREG_SELID0 + 16, + UC_RH850_REG_CTPC, UC_RH850_REG_CTPSW, - UC_RH850_REG_CTBP = UC_RH850_SYSREG_SELID0 + 20, - UC_RH850_REG_EIWR = UC_RH850_SYSREG_SELID0 + 28, - UC_RH850_REG_FEWR = UC_RH850_SYSREG_SELID0 + 29, - UC_RH850_REG_BSEL = UC_RH850_SYSREG_SELID0 + 31, + UC_RH850_REG_CTBP, + UC_RH850_REG_EIWR, + UC_RH850_REG_FEWR, + UC_RH850_REG_BSEL, - //> RH850 system regusters, selection ID 1 - UC_RH850_REG_MCFG0 = UC_RH850_SYSREG_SELID1, + //> RH850 system registers, selection ID 1 + UC_RH850_REG_MCFG0, UC_RH850_REG_RBASE, UC_RH850_REG_EBASE, UC_RH850_REG_INTBP, UC_RH850_REG_MCTL, UC_RH850_REG_PID, - UC_RH850_REG_SCCFG = UC_RH850_SYSREG_SELID1 + 11, + UC_RH850_REG_SCCFG, UC_RH850_REG_SCBP, //> RH850 system registers, selection ID 2 - UC_RH850_REG_HTCFG0 = UC_RH850_SYSREG_SELID2, - UC_RH850_REG_MEA = UC_RH850_SYSREG_SELID2 + 6, + UC_RH850_REG_HTCFG0, + UC_RH850_REG_MEA, UC_RH850_REG_ASID, UC_RH850_REG_MEI, - UC_RH850_REG_PC = UC_RH850_SYSREG_SELID7 + 32, - UC_RH850_REG_ENDING -} uc_cpu_rh850; + UC_RH850_REG_PC, + UC_RH850_REG_ENDING, -//> RH8509 Registers aliases. -#define UC_RH850_REG_ZERO UC_RH850_REG_R0 -#define UC_RH850_REG_SP UC_RH850_REG_R3 -#define UC_RH850_REG_EP UC_RH850_REG_R30 -#define UC_RH850_REG_LP UC_RH850_REG_R31 + //> Alias registers + UC_RH850_REG_ZERO = UC_RH850_REG_R0, + UC_RH850_REG_SP = UC_RH850_REG_R3, + UC_RH850_REG_EP = UC_RH850_REG_R30, + UC_RH850_REG_LP = UC_RH850_REG_R31, +} uc_rh850_reg; #ifdef __cplusplus } #endif -#endif \ No newline at end of file +#endif diff --git a/qemu/include/tcg/tcg.h b/qemu/include/tcg/tcg.h index f1559fcde0..229cc61b64 100644 --- a/qemu/include/tcg/tcg.h +++ b/qemu/include/tcg/tcg.h @@ -837,6 +837,24 @@ struct TCGContext { TCGv cpu_eind; TCGv cpu_sp; TCGv cpu_skip; + + // target/rh850/translate.c + TCGv rh850_cpu_sys_reg[7][32]; + TCGv_i32 cpu_SF; + TCGv_i32 cpu_OVF; + TCGv_i32 cpu_CYF; + TCGv_i32 cpu_SATF; + TCGv_i32 cpu_ID; + TCGv_i32 cpu_EP; + TCGv_i32 cpu_NP; + TCGv_i32 cpu_EBV; + TCGv_i32 cpu_CU0; + TCGv_i32 cpu_CU1; + TCGv_i32 cpu_CU2; + TCGv_i32 cpu_UM; + TCGv cpu_LLbit; + TCGv cpu_LLAddress; + TCGv cpu_sys_databuf_reg; }; static inline size_t temp_idx(TCGContext *tcg_ctx, TCGTemp *ts) diff --git a/qemu/rh850.h b/qemu/rh850.h index f0ba0cabf3..81cb988a3c 100644 --- a/qemu/rh850.h +++ b/qemu/rh850.h @@ -1347,7 +1347,5 @@ #define helper_stqcx_le_parallel helper_stqcx_le_parallel_rh850 #define helper_stqcx_be_parallel helper_stqcx_be_parallel_rh850 #define restore_state_to_opc restore_state_to_opc_rh850 -#define helper_tlb_flush helper_tlb_flush_rh850 -#define helper_uc_rh850_exit helper_uc_rh850_exit_rh850 #define gen_intermediate_code gen_intermediate_code_rh850 #endif diff --git a/qemu/target/rh850/Makefile.objs b/qemu/target/rh850/Makefile.objs deleted file mode 100644 index aaa7c0cc64..0000000000 --- a/qemu/target/rh850/Makefile.objs +++ /dev/null @@ -1 +0,0 @@ -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o fpu_translate.o diff --git a/qemu/target/rh850/cpu-param.h b/qemu/target/rh850/cpu-param.h index 24231873c3..89a3c8d37c 100644 --- a/qemu/target/rh850/cpu-param.h +++ b/qemu/target/rh850/cpu-param.h @@ -1,11 +1,12 @@ -#pragma once +#ifndef RH850_CPU_PARAM_H +#define RH850_CPU_PARAM_H /* QEMU addressing/paging config */ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ - #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #define NB_MMU_MODES 4 +#endif diff --git a/qemu/target/rh850/cpu-qom.h b/qemu/target/rh850/cpu-qom.h new file mode 100644 index 0000000000..20b5bece68 --- /dev/null +++ b/qemu/target/rh850/cpu-qom.h @@ -0,0 +1,32 @@ +#ifndef QEMU_RH850_QOM_H +#define QEMU_RH850_QOM_H + +#include "hw/core/cpu.h" + +#define TYPE_RH850_CPU "rh850-cpu" + +#define RH850_CPU(obj) ((RH850CPU *)obj) +#define RH850_CPU_CLASS(klass) ((RH850CPUClass *)klass) +#define RH850_CPU_GET_CLASS(obj) (&((RH850CPU *)obj)->cc) + +typedef struct RH850CPUInfo { + const char *name; + void (*initfn)(CPUState *obj); +} RH850CPUInfo; + +/** + * RH850CPUClass: + * @parent_reset: The parent class' reset handler. + * + * An RH850 CPU model. + */ +typedef struct RH850CPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + const RH850CPUInfo *info; + void (*parent_reset)(CPUState *cpu); +} RH850CPUClass; + +#endif diff --git a/qemu/target/rh850/cpu.c b/qemu/target/rh850/cpu.c index b6b44b28d2..2c5893d998 100644 --- a/qemu/target/rh850/cpu.c +++ b/qemu/target/rh850/cpu.c @@ -17,15 +17,11 @@ * this program. If not, see . */ -#include "qemu/osdep.h" -#include "qemu/log.h" -#include "qemu/ctype.h" -#include "cpu.h" #include "exec/exec-all.h" /* RH850 CPU definitions */ -/* Program registers (rh850_prog_regnames): +/* Program registers: * r0 - zero * r1 - assembler reserved register * r2 - real-time OS register / address and data variable register @@ -37,187 +33,6 @@ * r31 - link pointer */ -const char * const rh850_gp_regnames[] = { - "r0-zero", "r1", "r2", "r3-sp", "r4", "r5", "r6", "r7", - "r8", "r9", "r10 ", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r2 ", - "r24", "r25", "r26", "r27", "r28", "r29", "r30-ep", "r31-lp" -}; - -// Basic system registers -const char * const rh850_sys_regnames[][MAX_SYS_REGS_IN_BANK] = { - -{ // SELECTION ID 0 [5] used to be psw, but now it is stored in flags only - "eipc", "eipsw", "fepc", "fepsw", NULL, NULL, "fpsr", "fpepc", "fpst", "fpcc", - "fpcfg", "fpec", NULL, "eiic", "feic", NULL, "ctpc", "ctpsw", NULL, NULL, - "ctbp", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "eiwr", "fewr", - NULL, "bsel"}, -{ // SELECTION ID 1 - "mcfg0", NULL, "rbase", "ebase", "intbp", "mctl", "pid", "fpipr", NULL, NULL, - NULL, "sccfg", "scbp", -}, -{ // SELECTION ID 2 - "htcfg0",NULL, NULL, NULL, NULL, NULL, "mea", "asid", "mei", NULL, - "ispr", "pmr", "icsr", "intcfg" -}, -{ // SELECTION ID 3 - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}, -{ // SELECTION ID 4 - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, "ictagl", "ictagh","icdatl","icdath", - NULL, NULL, NULL, NULL, "icctrl",NULL, "iccfg", NULL, "icerr", NULL -}, -{ // SELECTION ID 5 - "mpm", "mprc", NULL, NULL, "mpbrgn","mptrgn",NULL, NULL, "mca", "mcs" - "mcc", "mcr" -}, -{ // SELECTION ID 6 - "mpla0", "mpua0", "mpat0", NULL, "mpla1", "mpua1", "mpat1", NULL, "mpla2", "mpua2", - "mpat2", NULL, "mpla3", "mpua3", "mpat3", NULL, "mpla4", "mpua4", "mpat4", NULL, - "mpla5", "mpua5", "mpat5", NULL, "mpla6", "mpua6", "mpat6", NULL, "mpla7", "mpua7", - "mpat7", NULL -}, -{ // SELECTION ID 7 - /* MPU function system registers */ - "mpla8", "mpua8", "mpat8", NULL, "mpla9", "mpua9", "mpat9", NULL, "mpla10","mpua10", - "mpat10",NULL, "mpla11", "mpua11", "mpat11",NULL, "mpla12","mpua12","mpat12",NULL, - "mpla13","mpua13","mpat13", NULL, "mpla14","mpua14","mpat14",NULL, "mpla15","mpua15", - "mpat15",NULL -} -}; - -// Where bits are read only, mask is set to 0 -const uint32_t rh850_sys_reg_read_only_masks[][MAX_SYS_REGS_IN_BANK] = { - -{ //SELECTION ID 0 PSW - implemented as registers for each used bit, see cpu_ZF, ... - 0xFFFFFFFF, 0x40078EFF, 0xFFFFFFFF, 0x40078EFF, 0x0, /*0x40018EFF*/ 0, 0xFFEEFFFF, 0xFFFFFFFE, 0x00003F3F, 0x000000FF, - 0x0000031F, 0x00000001, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0x0000001F, 0x0, 0x0, - 0xFFFFFFFE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, - 0x0, 0x0 -}, -{ //SELECTION ID 1 - // for MCFG (idx = 0), byte 3 seems to not be writable, at least on devicee used for testing - 0x00000000, 0x0, 0x00000000, 0xFFFFFE01, 0xFFFFFE00, 0x00000003, 0x00000000, 0x0000001F, 0x0, 0x0, - 0x0, 0x000000FF, 0xFFFFFFFC -}, -{ //SELECTION ID 2 - 0x00000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFFFFFF, 0x000003FF, 0x001F073F, 0x0, - 0x00000000, 0x0000FFFF, 0x00000000, 0x00000001 -}, -{ //SELECTION ID 3 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 -}, -{ //SELECTION ID 4 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFFFA35, 0xF0FFFF00, 0xFFFFFFFF, 0xFFFFFFFF, - 0x0, 0x0, 0x0, 0x0, 0x00020107, 0x0, 0x00000000, 0x0, 0xBF3F7FFD, 0x0 -}, -{ //SELECTION ID 5 - 0x00000003, 0x0000FFFF, 0x0, 0x0, 0x00000000, 0x00000000, 0x0, 0x0, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0x0000013F -}, -{ //SELECTION ID 6 - 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFF, - 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, - 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, - 0x03FF00FF, 0x0 -}, -{ //SELECTION ID 7 - 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFF, - 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, - 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, - 0x03FF00FF, 0x0 -} -}; - - -const uint32_t rh850_sys_reg_read_only_values[][MAX_SYS_REGS_IN_BANK] = { -{ //SELECTION ID 0 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0 -}, -{ //SELECTION ID 1 - 0x4, 0x0, 0x0, 0x0, 0x0, 0x80000000, 0x12345678, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0 -}, -{ //SELECTION ID 2 - 0x00008000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0 -}, -{ //SELECTION ID 3 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 -}, -{ //SELECTION ID 4 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x00010000, 0x0, 0x00010000, 0x0, 0x0, 0x0 -}, -{ //SELECTION ID 5 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0 -}, -{ //SELECTION ID 6 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0 -}, -{ //SELECTION ID 7 - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0 -} -}; - - - -/*Data Buffer Operation Registers (rh850_sys_databuff_regnames): - * sr24, 13 - cbdcr */ -const char * const rh850_sys_databuff_regnames[] = { /* Data buffer operation registers */ - "cbdcr" -}; - -const char * const rh850_excp_names[] = { - "misaligned_fetch", - "fault_fetch", - "illegal_instruction", - "breakpoint", - "misaligned_load", - "fault_load", - "misaligned_store", - "fault_store", - "user_ecall", - "supervisor_ecall", - "hypervisor_ecall", - "machine_ecall", - "exec_page_fault", - "load_page_fault", - "reserved", - "store_page_fault" -}; - -const char * const rh850_intr_names[] = { - "u_software", - "s_software", - "h_software", - "m_software", - "u_timer", - "s_timer", - "h_timer", - "m_timer", - "u_external", - "s_external", - "h_external", - "m_external", - "coprocessor", - "host" -}; - - void rh850_cpu_set_pc(CPUState *cs, vaddr value) { RH850CPU *cpu = RH850_CPU(cs); @@ -232,12 +47,6 @@ vaddr rh850_cpu_get_pc(CPUState *cs) return env->pc; } -AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) -{ - return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); -} - - /* called by qemu's softmmu to fill the qemu tlb */ static bool rh850_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, @@ -263,11 +72,7 @@ static void rh850_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) static bool rh850_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY return true; -#else - return true; -#endif } void restore_state_to_opc(CPURH850State *env, TranslationBlock *tb, @@ -298,18 +103,11 @@ static void rh850_debug_excp_handler(CPUState *cs) if (wp_hit) { if (wp_hit->flags & BP_CPU) { - // bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; - // bool same_el = true; - cs->watchpoint_hit = NULL; - - // env->exception.fsr = arm_debug_exception_fsr(env); - // env->exception.vaddress = wp_hit->hitaddr; rh850_raise_exception(env, 0, 0, 0); } } else { uint64_t pc = env->pc; - // bool same_el = true; /* (1) GDB breakpoints should be handled first. * (2) Do not raise a CPU exception if no CPU breakpoint has fired, @@ -324,26 +122,8 @@ static void rh850_debug_excp_handler(CPUState *cs) } } -static bool check_watchpoints(RH850CPU *cpu) -{ - return true; -} - - -static bool rh850_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) -{ - /* Called by core code when a CPU watchpoint fires; need to check if this - * is also an architectural watchpoint match. - */ - RH850CPU *cpu = RH850_CPU(cs); - - return check_watchpoints(cpu); -} - - static void rh850_cpu_reset(CPUState *cs) { - RH850CPU *cpu = RH850_CPU(cs); RH850CPUClass *mcc = RH850_CPU_GET_CLASS(cpu); CPURH850State *env = &cpu->env; @@ -353,61 +133,56 @@ static void rh850_cpu_reset(CPUState *cs) set_default_nan_mode(1, &env->fp_status); env->pc = 0; // move to direct vector ? (always 0?) env->ID_flag = 1; // interrupts are disable on reset - env->systemRegs[BANK_ID_BASIC_0][EIPSW_IDX] = 0x20; - env->systemRegs[BANK_ID_BASIC_0][FEPSW_IDX] = 0x20; - env->systemRegs[BANK_ID_BASIC_0][EIIC_IDX] = 0x0; - env->systemRegs[BANK_ID_BASIC_0][FEIC_IDX] = 0x0; - env->systemRegs[BANK_ID_BASIC_0][PSW_IDX] = 0x20; // reset value of PSW - env->systemRegs[BANK_ID_BASIC_0][CTPSW_IDX] = 0; - env->systemRegs[BANK_ID_BASIC_0][CTBP_IDX] = 0; // only bit 0 must be set to 0 - env->systemRegs[BANK_ID_BASIC_2][ASID_IDX2] = 0; // only bits 31-10 must be set to 0 - env->systemRegs[BANK_ID_BASIC_2][HTCFG0_IDX2] = 0x00018000; // const value - env->systemRegs[BANK_ID_BASIC_2][MEI_IDX2] = 0; // only some bits must be 0 - env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1] = 0; - env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1] = 0; // only bits 8-1 must be 0 - env->systemRegs[BANK_ID_BASIC_1][INTBP_IDX1] = 0; // only bits 8-0 must be 0 - env->systemRegs[BANK_ID_BASIC_1][PID_IDX1] = 0x05000120; // const - env->systemRegs[BANK_ID_BASIC_1][SCCFG_IDX1] = 0; // bits 31-8 must be 0 - env->systemRegs[BANK_ID_BASIC_1][SCBP_IDX1] = 0; // bits 1-0 must be 0 - env->systemRegs[BANK_ID_BASIC_1][MCFG0_IDX1] = 0x4; // bits 31-8 must be 0 - env->systemRegs[BANK_ID_BASIC_1][MCTL_IDX1] = 0x80000000; // bits 31-8 must be 0 - - env->systemRegs[BANK_ID_BASIC_2][FPIPR_IDX1] = 0; - env->systemRegs[BANK_ID_BASIC_2][ISPR_IDX2] = 0; - env->systemRegs[BANK_ID_BASIC_2][PMR_IDX2] = 0; - env->systemRegs[BANK_ID_BASIC_2][ICSR_IDX2] = 0; - env->systemRegs[BANK_ID_BASIC_2][INTCFG_IDX2] = 0; -} - -static void rh850_cpu_realize(struct uc_struct *uc, CPUState *dev) + env->sys_reg[BANK_ID_BASIC_0][EIPSW_IDX] = 0x20; + env->sys_reg[BANK_ID_BASIC_0][FEPSW_IDX] = 0x20; + env->sys_reg[BANK_ID_BASIC_0][EIIC_IDX] = 0x0; + env->sys_reg[BANK_ID_BASIC_0][FEIC_IDX] = 0x0; + env->sys_reg[BANK_ID_BASIC_0][PSW_IDX] = 0x20; // reset value of PSW + env->sys_reg[BANK_ID_BASIC_0][CTPSW_IDX] = 0; + env->sys_reg[BANK_ID_BASIC_0][CTBP_IDX] = 0; // only bit 0 must be set to 0 + env->sys_reg[BANK_ID_BASIC_2][ASID_IDX2] = 0; // only bits 31-10 must be set to 0 + env->sys_reg[BANK_ID_BASIC_2][HTCFG0_IDX2] = 0x00018000; // const value + env->sys_reg[BANK_ID_BASIC_2][MEI_IDX2] = 0; // only some bits must be 0 + env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1] = 0; + env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1] = 0; // only bits 8-1 must be 0 + env->sys_reg[BANK_ID_BASIC_1][INTBP_IDX1] = 0; // only bits 8-0 must be 0 + env->sys_reg[BANK_ID_BASIC_1][PID_IDX1] = 0x05000120; // const + env->sys_reg[BANK_ID_BASIC_1][SCCFG_IDX1] = 0; // bits 31-8 must be 0 + env->sys_reg[BANK_ID_BASIC_1][SCBP_IDX1] = 0; // bits 1-0 must be 0 + env->sys_reg[BANK_ID_BASIC_1][MCFG0_IDX1] = 0x4; // bits 31-8 must be 0 + env->sys_reg[BANK_ID_BASIC_1][MCTL_IDX1] = 0x80000000; // bits 31-8 must be 0 + + env->sys_reg[BANK_ID_BASIC_2][FPIPR_IDX1] = 0; + env->sys_reg[BANK_ID_BASIC_2][ISPR_IDX2] = 0; + env->sys_reg[BANK_ID_BASIC_2][PMR_IDX2] = 0; + env->sys_reg[BANK_ID_BASIC_2][ICSR_IDX2] = 0; + env->sys_reg[BANK_ID_BASIC_2][INTCFG_IDX2] = 0; +} + +static void rh850_cpu_realize(CPUState *cs) { - CPUState *cs = CPU(dev); - cpu_exec_realizefn(cs); - qemu_init_vcpu(cs); - cpu_reset(cs); } -static void rh850_cpu_init(struct uc_struct *uc, CPUState *obj) +static void rh850_cpu_initfn(struct uc_struct *uc, CPUState *cs) { - CPUState *cs = CPU(obj); - RH850CPU *cpu = RH850_CPU(obj); + RH850CPU *cpu = RH850_CPU(cs); + CPURH850State *env = &cpu->env; - /* Set CPU pointers. */ + env->uc = uc; cpu_set_cpustate_pointers(cpu); - - cs->env_ptr = &cpu->env; - cpu->env.uc = uc; } -static void rh850_cpu_class_init(struct uc_struct *uc, CPUClass *c) +static void rh850_cpu_class_init(CPUClass *c) { RH850CPUClass *mcc = RH850_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); + /* parent class is CPUClass, parent_reset() is cpu_common_reset(). */ mcc->parent_reset = cc->reset; + /* overwrite the CPUClass->reset to arch reset: avr_cpu_reset(). */ cc->reset = rh850_cpu_reset; cc->has_work = rh850_cpu_has_work; @@ -417,29 +192,23 @@ static void rh850_cpu_class_init(struct uc_struct *uc, CPUClass *c) cc->tlb_fill = rh850_tlb_fill; cc->synchronize_from_tb = rh850_cpu_synchronize_from_tb; cc->debug_excp_handler = rh850_debug_excp_handler; - cc->debug_check_watchpoint = rh850_debug_check_watchpoint; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = rh850_cpu_handle_mmu_fault; -#else cc->do_unaligned_access = rh850_cpu_do_unaligned_access; cc->get_phys_page_debug = rh850_cpu_get_phys_page_debug; -#endif -#ifdef CONFIG_TCG cc->tcg_initialize = rh850_translate_init; -#endif } -RH850CPU *cpu_rh850_init(struct uc_struct *uc, const char *cpu_model) +RH850CPU *cpu_rh850_init(struct uc_struct *uc) { RH850CPU *cpu; CPUState *cs; CPUClass *cc; - cpu = calloc(1, sizeof(*cpu)); + cpu = qemu_memalign(8, sizeof(*cpu)); if (cpu == NULL) { return NULL; } + memset((void *)cpu, 0, sizeof(*cpu)); cs = (CPUState *)cpu; cc = (CPUClass *)&cpu->cc; @@ -450,24 +219,20 @@ RH850CPU *cpu_rh850_init(struct uc_struct *uc, const char *cpu_model) /* init CPUClass */ cpu_class_init(uc, cc); - /* init CPUClass */ - rh850_cpu_class_init(uc, cc); + /* init RH850CPUClass */ + rh850_cpu_class_init(cc); /* init CPUState */ cpu_common_initfn(uc, cs); - /* init CPU */ - rh850_cpu_init(uc, cs); + /* init RH850CPU */ + rh850_cpu_initfn(uc, cs); - /* realize CPU */ - rh850_cpu_realize(uc, cs); + /* realize RH850CPU */ + rh850_cpu_realize(cs); // init addresss space cpu_address_space_init(cs, 0, cs->memory); return cpu; } - - - - diff --git a/qemu/target/rh850/cpu.h b/qemu/target/rh850/cpu.h index c54ad11599..70737b358a 100644 --- a/qemu/target/rh850/cpu.h +++ b/qemu/target/rh850/cpu.h @@ -23,65 +23,27 @@ #define TCG_GUEST_DEFAULT_MO 0 -//#define TARGET_INSN_START_EXTRA_WORDS 2 +// #define TARGET_INSN_START_EXTRA_WORDS 2 #define ELF_MACHINE EM_RH850 #define CPUArchState struct CPURH850State -#include "qemu-common.h" -#include "hw/core/cpu.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" -#define TYPE_RH850_CPU "rh850-cpu" - #define RH850_CPU_TYPE_SUFFIX "-" TYPE_RH850_CPU #define RH850_CPU_TYPE_NAME(name) (name RH850_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_RH850_CPU -#define TYPE_RH850_CPU_ANY RH850_CPU_TYPE_NAME("any") - -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) - -#if defined(TARGET_RH850) -#define RVXLEN RV32 -#elif defined(TARGET_RH85064) -#define RVXLEN RV64 -#endif - -#define RV(x) ((target_ulong)1 << (x - 'A')) - -#define RVI RV('I') -#define RVM RV('M') -#define RVA RV('A') -#define RVF RV('F') -#define RVD RV('D') -#define RVC RV('C') -#define RVS RV('S') -#define RVU RV('U') - -/* S extension denotes that Supervisor mode exists, however it is possible - to have a core that support S mode but does not have an MMU and there - is currently no bit in misa to indicate whether an MMU exists or not - so a cpu features bitfield is required */ -enum { - RH850_FEATURE_MMU -}; - -#define USER_VERSION_2_02_0 0x00020200 -#define PRIV_VERSION_1_09_1 0x00010901 -#define PRIV_VERSION_1_10_0 0x00011000 +#define TYPE_RH850_CPU_ANY RH850_CPU_TYPE_NAME("any") #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 -#define MMU_USER_IDX 3 #define MAX_RH850_PMPS (16) typedef struct CPURH850State CPURH850State; -#include "pmp.h" - #include "register_indices.h" #define NUM_GP_REGS 32 @@ -92,17 +54,15 @@ typedef struct CPURH850State CPURH850State; #define BANK_ID_BASIC_2 2 struct CPURH850State { - - target_ulong gpRegs[NUM_GP_REGS]; target_ulong pc; - target_ulong sysDatabuffRegs[1]; - target_ulong systemRegs[NUM_SYS_REG_BANKS][MAX_SYS_REGS_IN_BANK]; - //target_ulong sysBasicRegs[31]; - //target_ulong sysInterruptRegs[5]; - //uint64_t sysFpuRegs[6]; //using rh850 basic system registers(sr6-sr11), 32-bit or 64-bit precision - //target_ulong sysMpuRegs[56]; - //target_ulong sysCacheRegs[7]; + target_ulong cpu_sys_databuf_reg; + target_ulong sys_reg[NUM_SYS_REG_BANKS][MAX_SYS_REGS_IN_BANK]; + // target_ulong sysBasicRegs[31]; + // target_ulong sysInterruptRegs[5]; + // uint64_t sysFpuRegs[6]; //using rh850 basic system registers(sr6-sr11), + // 32-bit or 64-bit precision target_ulong sysMpuRegs[56]; target_ulong + // sysCacheRegs[7]; // flags contained in PSW register uint32_t Z_flag; @@ -119,22 +79,23 @@ struct CPURH850State { uint32_t CU2_flag; uint32_t UM_flag; - uint32_t features; + uint32_t features; uint32_t badaddr; target_ulong cpu_LLbit; // register for mutual exclusion (LDL.W, STC.W) - target_ulong cpu_LLAddress; // register for mutual exclusion (LDL.W, STC.W) + target_ulong cpu_LLAddress; // register for mutual exclusion (LDL.W, STC.W) - target_ulong load_res; // inst addr for TCG - target_ulong load_val; // inst val for TCG + target_ulong load_res; // inst addr for TCG + target_ulong load_val; // inst val for TCG - float_status fp_status; // not used yet in rh850, left for floating-point support. + float_status + fp_status; // not used yet in rh850, left for floating-point support. - target_ulong fpsr; /* floating-point configuration/status register. */ + target_ulong fpsr; /* floating-point configuration/status register. */ uint32_t exception_cause; int exception_priority; - bool exception_dv; + bool exception_dv; // Unicorn engine struct uc_struct *uc; @@ -144,21 +105,6 @@ struct CPURH850State { #define RH850_CPU_CLASS(klass) ((RH850CPUClass *)klass) #define RH850_CPU_GET_CLASS(obj) (&((RH850CPU *)obj)->cc) - -/** - * RH850CPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. - * - * A RH850 CPU model. - */ -typedef struct RH850CPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - void (*parent_reset)(CPUState *cpu); -} RH850CPUClass; - /** * RH850CPU: * @env: #CPURH850State @@ -182,12 +128,6 @@ static inline RH850CPU *rh850_env_get_cpu(CPURH850State *env) return container_of(env, RH850CPU, env); } -static inline int rh850_has_ext(CPURH850State *env, target_ulong ext) -{ // TODO: what does value 'ext' represent?? - //return (env->misa & ext) != 0; - return true; -} - static inline bool rh850_feature(CPURH850State *env, int feature) { return env->features & (1ULL << feature); @@ -196,53 +136,32 @@ static inline bool rh850_feature(CPURH850State *env, int feature) #include "cpu_user.h" #include "cpu_bits.h" -extern const char * const rh850_gp_regnames[]; -extern const char * const rh850_sys_regnames[][MAX_SYS_REGS_IN_BANK]; -extern const char * const rh850_sys_databuff_regnames[]; - -extern const char * const rh850_excp_names[]; -extern const char * const rh850_intr_names[]; -extern const uint32_t rh850_sys_reg_read_only_values[][MAX_SYS_REGS_IN_BANK]; -extern const uint32_t rh850_sys_reg_read_only_masks[][MAX_SYS_REGS_IN_BANK]; - #define ENV_GET_CPU(e) CPU(rh850_env_get_cpu(e)) #define ENV_OFFSET offsetof(RH850CPU, env) void rh850_cpu_do_interrupt(CPUState *cpu); -int rh850_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int rh850_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool rh850_cpu_exec_interrupt(CPUState *cs, int interrupt_request); int rh850_cpu_mmu_index(CPURH850State *env, bool ifetch); hwaddr rh850_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void rh850_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr); -int rh850_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, - int rw, int mmu_idx); - -char *rh850_isa_string(RH850CPU *cpu); -void rh850_cpu_list(void); +void rh850_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr); +int rh850_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, + int mmu_idx); #define cpu_init(cpu_model) cpu_generic_init(TYPE_RH850_CPU, cpu_model) -#define cpu_signal_handler cpu_rh850_signal_handler #define cpu_list rh850_cpu_list #define cpu_mmu_index rh850_cpu_mmu_index -void rh850_set_mode(CPURH850State *env, target_ulong newpriv); - void rh850_translate_init(struct uc_struct *uc); -RH850CPU *cpu_rh850_init(struct uc_struct *uc, const char *cpu_model); -int cpu_rh850_signal_handler(int host_signum, void *pinfo, void *puc); void QEMU_NORETURN do_raise_exception_err(CPURH850State *env, uint32_t exception, uintptr_t pc); target_ulong cpu_rh850_get_fflags(CPURH850State *env); -void cpu_rh850_set_fflags(CPURH850State *env, target_ulong); void rh850_cpu_set_pc(CPUState *cs, vaddr value); vaddr rh850_cpu_get_pc(CPUState *cs); -AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs); -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 3 #define TB_FLAGS_FP_ENABLE MSTATUS_FS /* @@ -254,23 +173,9 @@ static inline void cpu_get_tb_cpu_state(CPURH850State *env, target_ulong *pc, { *pc = env->pc; *cs_base = 0; -#ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; -#else - *flags = cpu_mmu_index(env, 0); -#endif + *flags = 0; } -void csr_write_helper(CPURH850State *env, target_ulong val_to_write, - target_ulong csrno); -target_ulong csr_read_helper(CPURH850State *env, target_ulong csrno); - -#ifndef CONFIG_USER_ONLY -void rh850_set_local_interrupt(RH850CPU *cpu, target_ulong mask, int value); -#endif - -extern const int NUM_GDB_REGS; - #include "exec/cpu-all.h" #endif /* RH850_CPU_H */ diff --git a/qemu/target/rh850/fpu_helper.c b/qemu/target/rh850/fpu_helper.c index d99c8613dd..48a27f5bf6 100644 --- a/qemu/target/rh850/fpu_helper.c +++ b/qemu/target/rh850/fpu_helper.c @@ -16,11 +16,7 @@ * this program. If not, see . */ -#include "qemu/osdep.h" -#include #include "cpu.h" -#include "qemu/host-utils.h" -#include "exec/exec-all.h" #include "exec/helper-proto.h" target_ulong cpu_rh850_get_fflags(CPURH850State *env) @@ -37,50 +33,6 @@ target_ulong cpu_rh850_get_fflags(CPURH850State *env) return hard; } -void cpu_rh850_set_fflags(CPURH850State *env, target_ulong hard) -{ - int soft = 0; - - soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0; - soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0; - soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0; - soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; - soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0; - - set_float_exception_flags(soft, &env->fp_status); -} - -void helper_set_rounding_mode(CPURH850State *env, uint32_t rm) -{ - int softrm; - - if (rm == 7) { - rm = 0; //env->frm; - } - switch (rm) { - case 0: - softrm = float_round_nearest_even; - break; - case 1: - softrm = float_round_to_zero; - break; - case 2: - softrm = float_round_down; - break; - case 3: - softrm = float_round_up; - break; - case 4: - softrm = float_round_ties_away; - break; - default: - qemu_log_mask(CPU_LOG_INT, "%s\n", __func__); - do_raise_exception_err(env, RH850_EXCP_ILLEGAL_INST, GETPC()); - } - - set_float_rounding_mode(softrm, &env->fp_status); -} - /* Propagate softfloat flags into FPSR. */ void helper_f_sync_fflags(CPURH850State *env) { @@ -90,157 +42,61 @@ void helper_f_sync_fflags(CPURH850State *env) flags = cpu_rh850_get_fflags(env); /* Handle inexact flag. */ - if (flags & FPEXC_NX) - { - if (env->fpsr & (1 << 5)) - { + if (flags & FPEXC_NX) { + if (env->fpsr & (1 << 5)) { /* Inexact exception allowed, set cause bit. */ env->fpsr |= (1 << 10); - } - else - { + } else { /* Set preservation bit. */ flags |= 1 << 0; } } /* Handle underflow flag. */ - if (flags & FPEXC_UF) - { - if (env->fpsr & (1 << 6)) - { + if (flags & FPEXC_UF) { + if (env->fpsr & (1 << 6)) { /* Underflow exception allowed, set cause bit. */ env->fpsr |= (1 << 11); - } - else - { + } else { /* Set preservation bit. */ env->fpsr |= 1 << 1; } } /* Handle overflow flag. */ - if (flags & FPEXC_OF) - { - if (env->fpsr & (1 << 7)) - { + if (flags & FPEXC_OF) { + if (env->fpsr & (1 << 7)) { /* Overflow exception allowed, set cause bit. */ env->fpsr |= (1 << 12); - } - else - { + } else { /* Set preservation bit. */ env->fpsr |= 1 << 2; } } /* Handle div-by-zero flag. */ - if (flags & FPEXC_DZ) - { - if (env->fpsr & (1 << 8)) - { + if (flags & FPEXC_DZ) { + if (env->fpsr & (1 << 8)) { /* Div-by-zero exception allowed, set cause bit. */ env->fpsr |= (1 << 13); - } - else - { + } else { /* Set preservation bit. */ env->fpsr |= 1 << 3; } } /* Handle invalid flag. */ - if (flags & FPEXC_NV) - { - if (env->fpsr & (1 << 9)) - { + if (flags & FPEXC_NV) { + if (env->fpsr & (1 << 9)) { /* Div-by-zero exception allowed, set cause bit. */ env->fpsr |= (1 << 14); - } - else - { + } else { /* Set preservation bit. */ env->fpsr |= 1 << 4; } } } -/** - * FPU flags checks - **/ - -uint32_t HELPER(f32_is_normal)(CPURH850State *env, uint32_t frs1) -{ - return (uint32_t)float32_is_normal(frs1); -} - -uint32_t HELPER(f32_is_zero_or_normal)(CPURH850State *env, uint32_t frs1) -{ - return (uint32_t)float32_is_zero_or_normal(frs1); -} - -uint32_t HELPER(f32_is_infinity)(CPURH850State *env, uint32_t frs1) -{ - return (uint32_t)float32_is_infinity(frs1); -} - - - -uint64_t helper_fmadd_s(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status); -} - -uint64_t helper_fmadd_d(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status); -} - -uint64_t helper_fmsub_s(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c, - &env->fp_status); -} - -uint64_t helper_fmsub_d(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c, - &env->fp_status); -} - -uint64_t helper_fnmsub_s(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product, - &env->fp_status); -} - -uint64_t helper_fnmsub_d(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product, - &env->fp_status); -} - -uint64_t helper_fnmadd_s(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c | - float_muladd_negate_product, &env->fp_status); -} - -uint64_t helper_fnmadd_d(CPURH850State *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3) -{ - return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c | - float_muladd_negate_product, &env->fp_status); -} - - /** * Floating-point simple precision helpers. **/ @@ -436,22 +292,16 @@ uint32_t HELPER(f_is_nan_s)(CPURH850State *env, uint32_t frs1) return float32_is_any_nan(frs1); } -uint32_t helper_fle_s(CPURH850State *env, uint32_t frs1, uint32_t frs2) -{ - return float32_le(frs1, frs2, &env->fp_status); -} - -uint32_t helper_flt_s(CPURH850State *env, uint32_t frs1, uint32_t frs2) +uint32_t HELPER(flt_s)(CPURH850State *env, uint32_t frs1, uint32_t frs2) { return float32_lt(frs1, frs2, &env->fp_status); } -uint32_t helper_feq_s(CPURH850State *env, uint32_t frs1, uint32_t frs2) +uint32_t HELPER(feq_s)(CPURH850State *env, uint32_t frs1, uint32_t frs2) { return float32_eq_quiet(frs1, frs2, &env->fp_status); } - uint32_t HELPER(fmaf_s)(CPURH850State *env, uint32_t frs1, uint32_t frs2, uint32_t frs3) { /* Compute (frs1 * frs2) + frs3 */ @@ -476,71 +326,6 @@ uint32_t HELPER(fnmsf_s)(CPURH850State *env, uint32_t frs1, uint32_t frs2, uint3 return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c | float_muladd_negate_result, &env->fp_status); } - - -target_ulong helper_fcvt_w_s(CPURH850State *env, uint64_t frs1) -{ - return float32_to_int32(frs1, &env->fp_status); -} - -target_ulong helper_fcvt_wu_s(CPURH850State *env, uint64_t frs1) -{ - return (int32_t)float32_to_uint32(frs1, &env->fp_status); -} - -#if defined(TARGET_RH85064) -uint64_t helper_fcvt_l_s(CPURH850State *env, uint64_t frs1) -{ - return float32_to_int64(frs1, &env->fp_status); -} - -uint64_t helper_fcvt_lu_s(CPURH850State *env, uint64_t frs1) -{ - return float32_to_uint64(frs1, &env->fp_status); -} -#endif - -uint64_t helper_fcvt_s_w(CPURH850State *env, target_ulong rs1) -{ - return int32_to_float32((int32_t)rs1, &env->fp_status); -} - -uint64_t helper_fcvt_s_wu(CPURH850State *env, target_ulong rs1) -{ - return uint32_to_float32((uint32_t)rs1, &env->fp_status); -} - -#if defined(TARGET_RH85064) -uint64_t helper_fcvt_s_l(CPURH850State *env, uint64_t rs1) -{ - return int64_to_float32(rs1, &env->fp_status); -} - -uint64_t helper_fcvt_s_lu(CPURH850State *env, uint64_t rs1) -{ - return uint64_to_float32(rs1, &env->fp_status); -} -#endif - -target_ulong helper_fclass_s(uint64_t frs1) -{ - float32 f = frs1; - bool sign = float32_is_neg(f); - - if (float32_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float32_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float32_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float32_is_any_nan(f)) { - float_status s = { 0 }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } -} - /** * Floating-point double precision helpers. **/ @@ -661,8 +446,6 @@ uint64_t HELPER(fcvt_uld)(CPURH850State *env, uint64_t frs1) return uint64_to_float64(frs1, &env->fp_status); } - - uint64_t HELPER(ftrnc_dl)(CPURH850State *env, uint64_t frs1) { return float64_to_int64_round_to_zero(frs1, &env->fp_status); @@ -732,92 +515,12 @@ uint32_t HELPER(f_is_nan_d)(CPURH850State *env, uint64_t frs1) return float64_is_any_nan(frs1); } - - -uint64_t helper_fcvt_s_d(CPURH850State *env, uint64_t rs1) -{ - return float64_to_float32(rs1, &env->fp_status); -} - -uint64_t helper_fcvt_d_s(CPURH850State *env, uint64_t rs1) -{ - return float32_to_float64(rs1, &env->fp_status); -} - -uint32_t helper_fle_d(CPURH850State *env, uint64_t frs1, uint64_t frs2) -{ - return float64_le(frs1, frs2, &env->fp_status); -} - -uint32_t helper_flt_d(CPURH850State *env, uint64_t frs1, uint64_t frs2) +uint32_t HELPER(flt_d)(CPURH850State *env, uint64_t frs1, uint64_t frs2) { return float64_lt(frs1, frs2, &env->fp_status); } -uint32_t helper_feq_d(CPURH850State *env, uint64_t frs1, uint64_t frs2) +uint32_t HELPER(feq_d)(CPURH850State *env, uint64_t frs1, uint64_t frs2) { return float64_eq_quiet(frs1, frs2, &env->fp_status); } - -target_ulong helper_fcvt_w_d(CPURH850State *env, uint64_t frs1) -{ - return float64_to_int32(frs1, &env->fp_status); -} - -target_ulong helper_fcvt_wu_d(CPURH850State *env, uint64_t frs1) -{ - return (int32_t)float64_to_uint32(frs1, &env->fp_status); -} - -#if defined(TARGET_RH85064) -uint64_t helper_fcvt_l_d(CPURH850State *env, uint64_t frs1) -{ - return float64_to_int64(frs1, &env->fp_status); -} - -uint64_t helper_fcvt_lu_d(CPURH850State *env, uint64_t frs1) -{ - return float64_to_uint64(frs1, &env->fp_status); -} -#endif - -uint64_t helper_fcvt_d_w(CPURH850State *env, target_ulong rs1) -{ - return int32_to_float64((int32_t)rs1, &env->fp_status); -} - -uint64_t helper_fcvt_d_wu(CPURH850State *env, target_ulong rs1) -{ - return uint32_to_float64((uint32_t)rs1, &env->fp_status); -} - -#if defined(TARGET_RH85064) -uint64_t helper_fcvt_d_l(CPURH850State *env, uint64_t rs1) -{ - return int64_to_float64(rs1, &env->fp_status); -} - -uint64_t helper_fcvt_d_lu(CPURH850State *env, uint64_t rs1) -{ - return uint64_to_float64(rs1, &env->fp_status); -} -#endif - -target_ulong helper_fclass_d(uint64_t frs1) -{ - float64 f = frs1; - bool sign = float64_is_neg(f); - - if (float64_is_infinity(f)) { - return sign ? 1 << 0 : 1 << 7; - } else if (float64_is_zero(f)) { - return sign ? 1 << 3 : 1 << 4; - } else if (float64_is_zero_or_denormal(f)) { - return sign ? 1 << 2 : 1 << 5; - } else if (float64_is_any_nan(f)) { - float_status s = { 0 }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; - } else { - return sign ? 1 << 1 : 1 << 6; - } -} diff --git a/qemu/target/rh850/fpu_translate.c b/qemu/target/rh850/fpu_translate.c index 2fd008177b..8c2e1e8ce8 100644 --- a/qemu/target/rh850/fpu_translate.c +++ b/qemu/target/rh850/fpu_translate.c @@ -1,7 +1,6 @@ #include "fpu_translate.h" #include "instmap.h" - -extern TCGv_i32 cpu_ZF; +#include "tcg/tcg-op.h" /* Helpers */ void fpu_load_i64(TCGContext *tcg_ctx, TCGv_i64 dst, int reg_n); @@ -97,8 +96,7 @@ void fpu_gen_cat1_ir(CPURH850State *env, DisasContext *ctx, int op, int frs1, in gen_get_gpr(tcg_ctx, r2, frs2); gen_get_gpr(tcg_ctx, r3, frs3); - switch(op) - { + switch (op) { case OPC_RH850_FPU_FMAF_S: gen_helper_fmaf_s(tcg_ctx, r3, tcg_ctx->cpu_env, r1, r2, r3); break; @@ -106,7 +104,7 @@ void fpu_gen_cat1_ir(CPURH850State *env, DisasContext *ctx, int op, int frs1, in case OPC_RH850_FPU_FMSF_S: gen_helper_fmsf_s(tcg_ctx, r3, tcg_ctx->cpu_env, r1, r2, r3); break; - + case OPC_RH850_FPU_FNMAF_S: gen_helper_fnmaf_s(tcg_ctx, r3, tcg_ctx->cpu_env, r1, r2, r3); break; @@ -140,284 +138,225 @@ void fpu_gen_sp_ir_2(CPURH850State *env, DisasContext *ctx, int operands, int op TCGv_i64 r3_64 = tcg_temp_local_new_i64(tcg_ctx); /* Load contents from registers. */ - switch(operands) - { + switch (operands) { case FPU_TYPE_S: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_ABS: - gen_helper_fabs_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_NEG: - gen_helper_fneg_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_SQRT: - gen_helper_fsqrt_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_RECIP: - gen_helper_frecip_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_RSQRT: - gen_helper_frsqrt_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_ABS: + gen_helper_fabs_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_NEG: + gen_helper_fneg_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_SQRT: + gen_helper_fsqrt_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_RECIP: + gen_helper_frecip_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_RSQRT: + gen_helper_frsqrt_s(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_SL: - { - /* Load simple-precision float. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result as long. */ - fpu_store_i64(tcg_ctx, rs3, r3_64); + /* Load simple-precision float. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_sl(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; } + + /* Store result as long. */ + fpu_store_i64(tcg_ctx, rs3, r3_64); break; case FPU_TYPE_SUL: - { - /* Load simple-precision float. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result as long. */ - fpu_store_i64(tcg_ctx, rs3, r3_64); + /* Load simple-precision float. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_sul(tcg_ctx, r3_64, tcg_ctx->cpu_env, r2); + break; } + + /* Store result as long. */ + fpu_store_i64(tcg_ctx, rs3, r3_64); break; case FPU_TYPE_SW: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_sw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_SUW: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_suw(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_LS: - { - /* Load content from register. */ - fpu_load_i64(tcg_ctx, r3_64, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_ls(tcg_ctx, r3, tcg_ctx->cpu_env, r3_64); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Load content from register. */ + fpu_load_i64(tcg_ctx, r3_64, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_ls(tcg_ctx, r3, tcg_ctx->cpu_env, r3_64); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_HS: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_hs(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_hs(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_WS: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_ws(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_ws(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_SH: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_sh(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_sh(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_ULS: - { - /* Load content from register. */ - fpu_load_i64(tcg_ctx, r3_64, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_uls(tcg_ctx, r3, tcg_ctx->cpu_env, r3_64); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Load content from register. */ + fpu_load_i64(tcg_ctx, r3_64, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_uls(tcg_ctx, r3, tcg_ctx->cpu_env, r3_64); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; case FPU_TYPE_UWS: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_uws(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result into rs3. */ - gen_set_gpr(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_uws(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } + + /* Store result into rs3. */ + gen_set_gpr(tcg_ctx, rs3, r3); break; - } /* Mov softfloat flags into our register. */ @@ -443,20 +382,14 @@ void fpu_gen_sp_ir_3(CPURH850State *env, DisasContext *ctx, int operands, int op TCGv r3 = tcg_temp_local_new_i32(tcg_ctx); /* Load contents from registers. */ - switch(operands) - { - case FPU_TYPE_S: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r1, rs1); - gen_get_gpr(tcg_ctx, r2, rs2); - } - break; + if (operands == FPU_TYPE_S) { + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r1, rs1); + gen_get_gpr(tcg_ctx, r2, rs2); } /* Apply operation. */ - switch(op) - { + switch (op) { case FPU_OP_ADD: gen_helper_fadd_s(tcg_ctx, r3, tcg_ctx->cpu_env, r1, r2); break; @@ -483,14 +416,9 @@ void fpu_gen_sp_ir_3(CPURH850State *env, DisasContext *ctx, int operands, int op } /* Store result. */ - switch(operands) - { - case FPU_TYPE_S: - { - /* Set reg3. */ - gen_set_gpr(tcg_ctx, rs3, r3); - } - break; + if (operands == FPU_TYPE_S) { + /* Set reg3. */ + gen_set_gpr(tcg_ctx, rs3, r3); } /* Mov softfloat flags into our register. */ @@ -516,13 +444,13 @@ void fpu_gen_trfsr(CPURH850State *env, DisasContext *ctx, int fcbit) gen_get_spr(tcg_ctx, BANK_ID_BASIC_0, FPSR_IDX, fpsr); tcg_gen_movi_i32(tcg_ctx, shift, 24 + fcbit); tcg_gen_shl_i32(tcg_ctx, mask, one, shift); - + /* Extract CCn bit. */ tcg_gen_and_i32(tcg_ctx, value, fpsr, mask); tcg_gen_shr_i32(tcg_ctx, value, value, shift); /* Set Z flag. */ - tcg_gen_mov_i32(tcg_ctx, cpu_ZF, value); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_ZF, value); gen_set_gpr(tcg_ctx, 1, value); /* Free locals. */ @@ -545,7 +473,6 @@ void fpu_gen_cmov_s(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int end = gen_new_label(tcg_ctx); otherwise = gen_new_label(tcg_ctx); - /* Load register contents. */ gen_get_gpr(tcg_ctx, r1, rs1); @@ -624,8 +551,7 @@ void fpu_gen_cmpf_s(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int tcg_gen_movi_i32(tcg_ctx, less, 0); tcg_gen_movi_i32(tcg_ctx, equal, 0); tcg_gen_movi_i32(tcg_ctx, unordered, 1); - if (fcond & 0x8) - { + if (fcond & 0x8) { /* Invalid operation detected. */ /* TODO: raise exception ? */ } @@ -641,7 +567,7 @@ void fpu_gen_cmpf_s(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int tcg_gen_or_i32(tcg_ctx, res, res, equal); if (fcond & 4) tcg_gen_or_i32(tcg_ctx, res, res, less); - + /** * Set CCn bit into FPSR (with n=fcbit). * 1. Load FPSR into r1 @@ -684,270 +610,211 @@ void fpu_gen_dp_ir_2(CPURH850State *env, DisasContext *ctx, int operands, int op TCGv r3_32 = tcg_temp_local_new_i32(tcg_ctx); /* Load contents from registers. */ - switch(operands) - { + switch (operands) { case FPU_TYPE_D: - { - /* Extract value from register rs2. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_ABS: - gen_helper_fabs_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_NEG: - gen_helper_fneg_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_SQRT: - gen_helper_fsqrt_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_RECIP: - gen_helper_frecip_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_RSQRT: - gen_helper_frsqrt_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value from register rs2. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_ABS: + gen_helper_fabs_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_NEG: + gen_helper_fneg_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_SQRT: + gen_helper_fsqrt_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_RECIP: + gen_helper_frecip_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_RSQRT: + gen_helper_frsqrt_d(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_DL: - { - /* Extract value from register rs2. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value from register rs2. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_dl(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_DUL: - { - /* Extract value from register rs2. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - break; - - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value from register rs2. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_dul(tcg_ctx, r3, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_DW: - { - /* Extract value from register rs2. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - } - - /* Store result. */ - gen_set_gpr(tcg_ctx, rs3, r3_32); + /* Extract value from register rs2. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_dw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; } + + /* Store result. */ + gen_set_gpr(tcg_ctx, rs3, r3_32); break; case FPU_TYPE_DUW: - { - /* Extract value from register rs2. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - switch(op) - { - case FPU_OP_TRNC: - gen_helper_ftrnc_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CEIL: - gen_helper_fceil_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_FLOOR: - gen_helper_ffloor_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - case FPU_OP_CVT: - gen_helper_fcvt_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); - break; - - } - - /* Store result. */ - gen_set_gpr(tcg_ctx, rs3, r3_32); + /* Extract value from register rs2. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + switch (op) { + case FPU_OP_TRNC: + gen_helper_ftrnc_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CEIL: + gen_helper_fceil_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_FLOOR: + gen_helper_ffloor_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; + + case FPU_OP_CVT: + gen_helper_fcvt_duw(tcg_ctx, r3_32, tcg_ctx->cpu_env, r2); + break; } - break; + /* Store result. */ + gen_set_gpr(tcg_ctx, rs3, r3_32); + break; case FPU_TYPE_LD: - { - /* Load content from register. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_ld(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Load content from register. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_ld(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } - break; + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); + break; case FPU_TYPE_WD: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r3_32, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_wd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); - } - else - { - /* Unsupported operation. */ - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r3_32, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_wd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_SD: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r3_32, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_sd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); - } - else - { - /* Unsupported operation. */ - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r3_32, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_sd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_UWD: - { - /* Extract value of reg1 and reg2. */ - gen_get_gpr(tcg_ctx, r3_32, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_uwd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); - } - else - { - /* Unsupported operation. */ - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Extract value of reg1 and reg2. */ + gen_get_gpr(tcg_ctx, r3_32, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_uwd(tcg_ctx, r3, tcg_ctx->cpu_env, r3_32); } + + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; case FPU_TYPE_ULD: - { - /* Load content from register. */ - fpu_load_i64(tcg_ctx, r2, rs2); - - /* Apply operation. */ - if (op == FPU_OP_CVT) - { - gen_helper_fcvt_uld(tcg_ctx, r3, tcg_ctx->cpu_env, r2); - } - else - { - /* Unsupported operation. */ - } - - /* Store result. */ - fpu_store_i64(tcg_ctx, rs3, r3); + /* Load content from register. */ + fpu_load_i64(tcg_ctx, r2, rs2); + + /* Apply operation. */ + if (op == FPU_OP_CVT) { + gen_helper_fcvt_uld(tcg_ctx, r3, tcg_ctx->cpu_env, r2); } + /* Store result. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; - } /* Mov softfloat flags into our register. */ @@ -969,18 +836,14 @@ void fpu_gen_dp_ir_3(CPURH850State *env, DisasContext *ctx, int operands, int op TCGv_i64 r3 = tcg_temp_local_new_i64(tcg_ctx); /* Load contents from registers. */ - switch(operands) - { + switch (operands) { case FPU_TYPE_D: - { - /* Load float64 values from regpairs designed by rs1 and rs2. */ - fpu_load_i64_2(tcg_ctx, r1, r2, rs1, rs2); - } + /* Load float64 values from regpairs designed by rs1 and rs2. */ + fpu_load_i64_2(tcg_ctx, r1, r2, rs1, rs2); break; } - switch(op) - { + switch (op) { case FPU_OP_ADD: gen_helper_fadd_d(tcg_ctx, r3, tcg_ctx->cpu_env, r1, r2); break; @@ -1006,13 +869,10 @@ void fpu_gen_dp_ir_3(CPURH850State *env, DisasContext *ctx, int operands, int op break; } - switch(operands) - { + switch (operands) { case FPU_TYPE_D: - { - /* Store result as float64 in regpair designed by rs3. */ - fpu_store_i64(tcg_ctx, rs3, r3); - } + /* Store result as float64 in regpair designed by rs3. */ + fpu_store_i64(tcg_ctx, rs3, r3); break; } @@ -1070,8 +930,7 @@ void fpu_gen_cmpf_d(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int tcg_gen_movi_i32(tcg_ctx, less, 0); tcg_gen_movi_i32(tcg_ctx, equal, 0); tcg_gen_movi_i32(tcg_ctx, unordered, 1); - if (fcond & 0x8) - { + if (fcond & 0x8) { /* Invalid operation detected. */ /* TODO: raise exception ? */ } @@ -1087,7 +946,7 @@ void fpu_gen_cmpf_d(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int tcg_gen_or_i32(tcg_ctx, res, res, equal); if (fcond & 4) tcg_gen_or_i32(tcg_ctx, res, res, less); - + /** * Set CCn bit into FPSR (with n=fcbit). * 1. Load FPSR into r1 @@ -1128,7 +987,6 @@ void fpu_gen_cmov_d(CPURH850State *env, DisasContext *ctx, int rs1, int rs2, int end = gen_new_label(tcg_ctx); otherwise = gen_new_label(tcg_ctx); - /* Load register contents. */ fpu_load_i64(tcg_ctx, r1, rs1); @@ -1174,12 +1032,10 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) int rs1 = GET_RS1(ctx->opcode); int rs2 = GET_RS2(ctx->opcode); int rs3 = GET_RS3(ctx->opcode); - - switch(MASK_OP_FORMAT_FI(ctx->opcode)) - { + + switch (MASK_OP_FORMAT_FI(ctx->opcode)) { case OPC_RH850_FPU_GROUP_SW: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_TRNCF_SW: fpu_gen_sp_ir_2(env, ctx, FPU_TYPE_SW, FPU_OP_TRNC, rs2, rs3); break; @@ -1215,8 +1071,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_DS: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_CVTF_WS: fpu_gen_sp_ir_2(env, ctx, FPU_TYPE_WS, FPU_OP_CVT, rs2, rs3); break; @@ -1244,8 +1099,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_SL: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_TRNCF_SL: fpu_gen_sp_ir_2(env, ctx, FPU_TYPE_SL, FPU_OP_TRNC, rs2, rs3); break; @@ -1281,8 +1135,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_ABSS: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_ABSF_S: fpu_gen_sp_ir_2(env, ctx, FPU_TYPE_S, FPU_OP_ABS, rs2, rs3); break; @@ -1294,8 +1147,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_S: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_SQRTF_S: fpu_gen_sp_ir_2(env, ctx, FPU_TYPE_S, FPU_OP_SQRT, rs2, rs3); break; @@ -1311,8 +1163,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_DW: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_TRNCF_DW: fpu_gen_dp_ir_2(env, ctx, FPU_TYPE_DW, FPU_OP_TRNC, rs2, rs3); break; @@ -1348,8 +1199,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_DD: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_CVTF_WD: //fpu_gen_cvtf_wd(env, ctx, rs2, rs3); fpu_gen_dp_ir_2(env, ctx, FPU_TYPE_WD, FPU_OP_CVT, rs2, rs3); @@ -1378,8 +1228,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_DL: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_TRNCF_DL: fpu_gen_dp_ir_2(env, ctx, FPU_TYPE_DL, FPU_OP_TRNC, rs2, rs3); break; @@ -1415,8 +1264,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_ABSD: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_ABSF_D: fpu_gen_dp_ir_2(env, ctx, FPU_TYPE_D, FPU_OP_ABS, rs2, rs3); break; @@ -1428,8 +1276,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FPU_GROUP_D: - switch(rs1) - { + switch (rs1) { case OPC_RH850_FPU_SQRTF_D: fpu_gen_dp_ir_2(env, ctx, FPU_TYPE_D, FPU_OP_SQRT, rs2, rs3); break; @@ -1450,8 +1297,7 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) case OPC_RH850_FPU_ADDF_D: /* rs1, rs2 and rs3 must have bit 0 set to 0. */ - if ((rs1 & 1) || (rs2 & 1) || (rs3 & 1)) - { + if ((rs1 & 1) || (rs2 & 1) || (rs3 & 1)) { /* TODO: Invalid instruction, must trigger exception. */ } else @@ -1500,35 +1346,30 @@ void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx) default: - switch(ctx->opcode & (0x70 << 16)) - { + switch (ctx->opcode & (0x70 << 16)) { case OPC_RH850_FPU_CMOV_S_OR_TRFSR: - /* If reg1==reg2==reg3==0, then it is a TRSFR instruction. */ - if ((rs1 == 0) && (rs2 == 0) && (rs3 == 0)) - { - fpu_gen_trfsr(env, ctx, (ctx->opcode & (0xe << 16))>>17 ); - } - else - { + if ((rs1 == 0) && (rs2 == 0) && (rs3 == 0)) { + fpu_gen_trfsr(env, ctx, (ctx->opcode & (0xe << 16))>>17); + } else { /* Call generator with fcbit. */ - fpu_gen_cmov_s(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17 ); + fpu_gen_cmov_s(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17); } break; case OPC_RH850_FPU_CMOV_D: /* Call generator with fcbit. */ - fpu_gen_cmov_d(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17 ); + fpu_gen_cmov_d(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17); break; case OPC_RH850_FPU_CMP_S: /* Call generator with fcond (rs3) and fcbit. */ - fpu_gen_cmpf_s(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17 ); + fpu_gen_cmpf_s(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17); break; case OPC_RH850_FPU_CMP_D: /* Call generator with fcond (rs3) and fcbit. */ - fpu_gen_cmpf_d(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17 ); + fpu_gen_cmpf_d(env, ctx, rs1, rs2, rs3, (ctx->opcode & (0xe << 16))>>17); break; default: @@ -1547,11 +1388,3 @@ void fpu_decode_cat1_instn(CPURH850State *env, DisasContext *ctx) fpu_gen_cat1_ir(env, ctx, MASK_OP_FORMAT_FI(ctx->opcode), rs1, rs2, rs3); } - -/** - * Initialize FPU. - **/ - -void rh850_fpu_translate_init(void) -{ -} \ No newline at end of file diff --git a/qemu/target/rh850/fpu_translate.h b/qemu/target/rh850/fpu_translate.h index b21af6759f..02efc8aee5 100644 --- a/qemu/target/rh850/fpu_translate.h +++ b/qemu/target/rh850/fpu_translate.h @@ -20,22 +20,10 @@ #ifndef RH850_FPU_H #define RH850_FPU_H -#include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "translate.h" -#include "fpu_translate.h" -#include "exec/cpu_ldst.h" -#include "exec/exec-all.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" -#include "exec/translator.h" #include "translate.h" void fpu_decode_cat0_instn(CPURH850State *env, DisasContext *ctx); void fpu_decode_cat1_instn(CPURH850State *env, DisasContext *ctx); -void fpu_init(CPURH850State *env); -void rh850_fpu_translate_init(void); -#endif /* RH850_FPU_H */ \ No newline at end of file +#endif /* RH850_FPU_H */ diff --git a/qemu/target/rh850/gdbstub.c b/qemu/target/rh850/gdbstub.c deleted file mode 100644 index 2abc97fb64..0000000000 --- a/qemu/target/rh850/gdbstub.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * RH850 GDB Server Stub - * - * Copyright (c) 2019-2020 Marko Klopcic, iSYSTEM Labs - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "exec/gdbstub.h" -#include "cpu.h" - -/* Mapping of winIDEA register index to env->sysBasicRegs() index. (see mail - * from Matic 2019-05-06 and isystem/doc/v850-tdep.c) - QEMU idx wI idx - 32, // eipc 0 - 33, // eipsw 1 - 34, // fepc 2 - 35, // fepsw 3 - 37, // psw 4 - 128, // fpsr 5 - 129, // fpepc 6 - 130, // fpst 7 - 131, // fpcc 8 - 132, // fpcfg 9 - 133, // fpec 10 - 44, // SESR N/A - 45, // EIIC 11 - 46, // FEIC 12 - 48, // CTPC 13 - 49, // CTPSW 14 - 52, // CTBP 15 - 60, // EIWR 16 - 61, // FEWR 17 - 63, // BSEL 18 - 150, // mcfg0 19 - 152, // RBASE 20 - 153, // EBASE 21 - 154, // intbp 22 - 155, // mctl 23 - 156, // pid 24 - 161, // sccfg 25 - 162, // scbp 26 - 182, // htcfg0 27 - 188, // mea 28 - 189, // asid 29 - 190 // mei 30 -*/ -#define BANK_MASK 0xf0000 -#define BANK_SHIFT 16 -#define SRI(selID, regID) (((selID) << BANK_SHIFT) | (regID)) -#define SRI0(regID) (regID) -#define SRI1(regID) SRI(1, (regID)) -#define SRI2(regID) SRI(2, (regID)) - -typedef int IdxType; -const IdxType winIdeaRegIdx2qemuSysRegIdx[] = { -// 0 1 2 3 4 5 6 7 8 9 -// --------------------------------------------- --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 0 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 1 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 2 - --1, -1, SRI0(EIPC_IDX), SRI0(EIPSW_IDX),SRI0(FEPC_IDX),SRI0(FEPSW_IDX),-1, SRI0(PSW_IDX), -1, -1, // 3 --1, -1, -1, -1, -1, SRI0(EIIC_IDX),SRI0(FEIC_IDX),-1,SRI0(CTPC_IDX),SRI0(CTPSW_IDX), // 4 --1, -1, SRI0(CTBP_IDX), -1, -1, -1, -1, -1, -1, -1, // 5 - -SRI0(EIWR_IDX),SRI0(FEWR_IDX),-1,SRI0(BSEL_IDX), -1, -1, -1, -1, -1, -1, // 6 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 7 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 8 - --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 9 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 10 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 11 - --1, -1, -1, -1, -1, -1, -1, -1, SRI0(FPSR_IDX), SRI0(FEPC_IDX), // 12 -SRI0(FPST_IDX),SRI0(FPCC_IDX),SRI0(FPCFG_IDX),SRI0(FPEC_IDX), -1,-1, -1, -1, -1, -1, // 13 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 14 - -SRI1(MCFG0_IDX1),-1,SRI1(RBASE_IDX1),SRI1(EBASE_IDX1),SRI1(INTBP_IDX1),SRI1(MCTL_IDX1),SRI1(PID_IDX1),-1,-1, -1, // 15 --1, SRI1(SCCFG_IDX1), SRI1(SCBP_IDX1), -1, -1, -1, -1, -1, -1, -1, // 16 --1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // 17 - --1, -1,SRI2(HTCFG0_IDX2), -1, -1, -1, -1, -1,SRI2(MEA_IDX2),SRI2(ASID_IDX2), // 18 -SRI2(MEI_IDX2), -1, -1, -1, -1, -1, -1, -1, -1, -1, // 19 -}; - -const int NUM_GDB_REGS = sizeof(winIdeaRegIdx2qemuSysRegIdx) / sizeof(IdxType); - -int rh850_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) -{ - RH850CPU *cpu = RH850_CPU(cs); - CPURH850State *env = &cpu->env; - - if (n < 32) { - return gdb_get_regl(mem_buf, env->gpRegs[n]); //gpr is now supposed to be progRegs - } else if (n == 64) { - return gdb_get_regl(mem_buf, env->pc); - } else if (n < NUM_GDB_REGS) { - int sysRegIdx = winIdeaRegIdx2qemuSysRegIdx[n]; - if (sysRegIdx >= 0) { - int selID = sysRegIdx >> BANK_SHIFT; - int regID = sysRegIdx & ~BANK_MASK; - if (selID == BANK_ID_BASIC_0 && regID == PSW_IDX) { - int psw = env->Z_flag | (env->S_flag << 1) | (env->OV_flag << 2) | (env->CY_flag << 3); - psw |= (env->SAT_flag << 4) | (env->ID_flag << 5) | (env->EP_flag << 6); - psw |= (env->NP_flag << 7) | (env->EBV_flag << 15) | (env->CU0_flag << 16); - psw |= (env->CU1_flag << 17) | (env->CU2_flag << 18) | (env->UM_flag << 30); - return gdb_get_regl(mem_buf, psw); - } else { - return gdb_get_regl(mem_buf, env->systemRegs[selID][regID]); // eipc, eipsw, fepc, fepsw, psw, ... - } - } - } - - *((uint32_t *)mem_buf) = 0xBAD0BAD0; - return 4; // registers in slots not set above are ignored -} - -int rh850_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) -{ - RH850CPU *cpu = RH850_CPU(cs); - CPURH850State *env = &cpu->env; - // at the moment our GDB server has different indices for writing single register - // will fix this if batch write will have to be supported or interfacing - // to other GDB servers for RH850 will be needed. - if (n > 0 && n < 32) { // skip R0, because it is always 0 - env->gpRegs[n] = ldtul_p(mem_buf); - } else if (n == 64) { - env->pc = ldtul_p(mem_buf); - } else if (n < NUM_GDB_REGS) { - int sysRegIdx = winIdeaRegIdx2qemuSysRegIdx[n]; - if (sysRegIdx >= 0) { - int selID = sysRegIdx >> BANK_SHIFT; - int regID = sysRegIdx & ~BANK_MASK; - if (selID == BANK_ID_BASIC_0 && regID == PSW_IDX) { - int psw = ldtul_p(mem_buf); - env->Z_flag = psw & 1; - env->S_flag = (psw >> 1) & 1; - env->OV_flag = (psw >> 2) & 1; - env->CY_flag = (psw >> 3) & 1; - env->SAT_flag = (psw >> 4) & 1; - env->ID_flag = (psw >> 5) & 1; - env->EP_flag = (psw >> 6) & 1; - env->NP_flag = (psw >> 7) & 1; - env->EBV_flag = (psw >> 15) & 1; - env->CU0_flag = (psw >> 16) & 1; - env->CU1_flag = (psw >> 17) & 1; - env->CU2_flag = (psw >> 18) & 1; - env->UM_flag = (psw >> 30) & 1; - } else { - env->systemRegs[selID][regID] = ldtul_p(mem_buf); // eipc, eipsw, fepc, fepsw, psw, ... - } - } - } - - return sizeof(target_ulong); -} diff --git a/qemu/target/rh850/helper.c b/qemu/target/rh850/helper.c index ee171f0dbb..7c796eded7 100644 --- a/qemu/target/rh850/helper.c +++ b/qemu/target/rh850/helper.c @@ -18,42 +18,16 @@ * this program. If not, see . */ -#include "qemu/osdep.h" -#include "qemu/log.h" -#include "cpu.h" #include "exec/exec-all.h" -#define RH850_DEBUG_INTERRUPT 0 - int rh850_cpu_mmu_index(CPURH850State *env, bool ifetch) { return 0; } -#ifndef CONFIG_USER_ONLY -/* - * Return RH850 IRQ number if an interrupt should be taken, else -1. - * Used in cpu-exec.c - * - * Adapted from Spike's processor_t::take_interrupt() - */ - -#if 0 /* Not used */ -static int rh850_cpu_hw_interrupts_pending(CPURH850State *env) -{ - - return EXCP_NONE; -} -#endif -#endif - -uint32_t psw2int(CPURH850State * env); -uint32_t mem_deref_4(CPUState * cs, uint32_t addr); - - uint32_t psw2int(CPURH850State * env) { - uint32_t ret = 0; + uint32_t ret = 0; ret |= env->UM_flag<<30; ret |= env->CU0_flag<<16; ret |= env->CU1_flag<<17; @@ -61,12 +35,12 @@ uint32_t psw2int(CPURH850State * env) ret |= env->EBV_flag<<15; ret |= env->NP_flag<<7; ret |= env->EP_flag<<6; - ret |= env->ID_flag<<5; + ret |= env->ID_flag<<5; ret |= env->SAT_flag<<4; ret |= env->CY_flag<<3; ret |= env->OV_flag<<2; ret |= env->S_flag<<1; - ret |= env->Z_flag; + ret |= env->Z_flag; return ret; } @@ -77,15 +51,11 @@ uint32_t psw2int(CPURH850State * env) bool rh850_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) RH850CPU *cpu = RH850_CPU(cs); CPURH850State *env = &cpu->env; - //qemu_log("[cpu] exec_interrupt: got interrupt_req=%08x\n", interrupt_request); - /* Handle FENMI interrupt. */ - if (interrupt_request == RH850_INT_FENMI) - { + if (interrupt_request == RH850_INT_FENMI) { /* Set exception info. */ cs->exception_index = RH850_EXCP_FENMI; env->exception_cause = 0xE0; @@ -93,11 +63,8 @@ bool rh850_cpu_exec_interrupt(CPUState *cs, int interrupt_request) /* Acknowledge interrupt. */ rh850_cpu_do_interrupt(cs); - } - else if (interrupt_request == RH850_INT_FEINT) - { - if (!(env->systemRegs[BANK_ID_BASIC_2][PMR_IDX2] & (1<exception_priority))) - { + } else if (interrupt_request == RH850_INT_FEINT) { + if (!(env->sys_reg[BANK_ID_BASIC_2][PMR_IDX2] & (1<exception_priority))) { /* Set exception info. */ cs->exception_index = RH850_EXCP_FEINT; env->exception_cause = 0xF0; @@ -106,20 +73,13 @@ bool rh850_cpu_exec_interrupt(CPUState *cs, int interrupt_request) /* Acknowledge interrupt. */ rh850_cpu_do_interrupt(cs); } - } - else if (interrupt_request == RH850_EXCP_EIINT) - { - //qemu_log("exec_interrupt got RH850_EXCP_EIINT\n"); - + } else if (interrupt_request == RH850_EXCP_EIINT) { /* Get interrupt request number. */ //int intn = env->exception_cause & 0xfff; int priority = 4; - //qemu_log("[cpu] exec_interrupt: got interrupt_req=%08x\n", interrupt_request); - /* Check if interrupt priority is not masked (through PMR). */ - if (!(env->systemRegs[BANK_ID_BASIC_2][PMR_IDX2] & (1<sys_reg[BANK_ID_BASIC_2][PMR_IDX2] & (1<interrupt_request = 0; return false; } -#if !defined(CONFIG_USER_ONLY) - - static int get_physical_address(CPURH850State *env, hwaddr *physical, int *prot, target_ulong addr, int access_type, int mmu_idx) { - - /* - * There is no memory virtualization in RH850 (at least for the targeted SoC) - * Address resolution is straightforward - */ - *physical = addr; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - + /* + * There is no memory virtualization in RH850 (at least for the targeted SoC) + * Address resolution is straightforward + */ + *physical = addr; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; } static void raise_mmu_exception(CPURH850State *env, target_ulong address, MMUAccessType access_type) { CPUState *cs = CPU(rh850_env_get_cpu(env)); - int page_fault_exceptions = RH850_EXCP_INST_PAGE_FAULT; + int page_fault_exceptions = RH850_EXCP_INST_PAGE_FAULT; switch (access_type) { case MMU_INST_FETCH: cs->exception_index = page_fault_exceptions ? @@ -194,9 +144,8 @@ hwaddr rh850_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) RH850CPU *cpu = RH850_CPU(cs); hwaddr phys_addr; int prot; - int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, 0)) { return -1; } return phys_addr; @@ -222,97 +171,64 @@ void rh850_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; - //qemu_log_mask(CPU_LOG_INT, "%s\n", __func__); do_raise_exception_err(env, cs->exception_index, retaddr); } -#endif - int rh850_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { - - /* * TODO: Add check to system register concerning MPU configuratuon MPLA, MPUA * */ RH850CPU *cpu = RH850_CPU(cs); CPURH850State *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr pa = 0; int prot; -#endif int ret = TRANSLATE_FAIL; - qemu_log_mask(CPU_LOG_MMU, - "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ - %d\n", __func__, env->pc, address, rw, mmu_idx); - -#if !defined(CONFIG_USER_ONLY) - ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx); - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); } else if (ret == TRANSLATE_FAIL) { raise_mmu_exception(env, address, rw); } -#else - switch (rw) { - case MMU_INST_FETCH: - cs->exception_index = RH850_EXCP_INST_PAGE_FAULT; - break; - case MMU_DATA_LOAD: - cs->exception_index = RH850_EXCP_LOAD_PAGE_FAULT; - break; - case MMU_DATA_STORE: - cs->exception_index = RH850_EXCP_STORE_PAGE_FAULT; - break; - } -#endif return ret; } uint32_t mem_deref_4(CPUState * cs, uint32_t addr){ - uint8_t * buf = g_malloc(4); - uint32_t ret_dword = 0; - cpu_memory_rw_debug(cs, addr, buf, 4, false); - - ret_dword |= buf[3] << 24; - ret_dword |= buf[2] << 16; - ret_dword |= buf[1] << 8; - ret_dword |= buf[0]; - g_free(buf); - return ret_dword; + uint8_t * buf = g_malloc(4); + uint32_t ret_dword = 0; + cpu_memory_rw_debug(cs, addr, buf, 4, false); + + ret_dword |= buf[3] << 24; + ret_dword |= buf[2] << 16; + ret_dword |= buf[1] << 8; + ret_dword |= buf[0]; + g_free(buf); + return ret_dword; } void rh850_cpu_do_interrupt(CPUState *cs) { - - //qemu_log("[cpu] rh850_cpu_do_interrupt()\n"); - //qemu_log_mask(CPU_LOG_INT, "%s\n", __func__); -#if !defined(CONFIG_USER_ONLY) uint32_t intbp; RH850CPU *cpu = RH850_CPU(cs); CPURH850State *env = &cpu->env; - uint32_t direct_vector_ba; + uint32_t direct_vector_ba; qemu_log_mask(CPU_LOG_INT, "%s: entering switch\n", __func__); switch (cs->exception_index) { - case RH850_EXCP_FETRAP: + case RH850_EXCP_FETRAP: qemu_log_mask(CPU_LOG_INT, "%s: entering FETRAP handler\n", __func__); // store PSW to FEPSW (and update env->EBV_flag) - env->systemRegs[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); // store PC to FEPC - env->systemRegs[BANK_ID_BASIC_0][FEPC_IDX] = env->pc+2; + env->sys_reg[BANK_ID_BASIC_0][FEPC_IDX] = env->pc+2; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; qemu_log_mask(CPU_LOG_INT, "%s, saved pc : %x\n", __func__,env->pc); @@ -323,23 +239,23 @@ void rh850_cpu_do_interrupt(CPUState *cs) env->ID_flag = 1; // modify PC, keep RBASE or EBASE bits 9 to 31 (discard bits 0 to 8) - if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; + if (env->EBV_flag) + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; - + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; + qemu_log_mask(CPU_LOG_INT, "%s: direct vector addr : %x \n", __func__,direct_vector_ba); - env->pc = direct_vector_ba + 0x30; - break; - + env->pc = direct_vector_ba + 0x30; + break; + case RH850_EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "%s: entering TRAP handler\n", __func__); // store PSW to EIPSW - env->systemRegs[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); // store PC to EIPC - env->systemRegs[BANK_ID_BASIC_0][EIPC_IDX] = env->pc+4; + env->sys_reg[BANK_ID_BASIC_0][EIPC_IDX] = env->pc+4; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; env->UM_flag = 0; env->EP_flag = 1; @@ -347,26 +263,24 @@ void rh850_cpu_do_interrupt(CPUState *cs) // modify PC, keep RBASE or EBASE bits 9 to 31 (discard bits 0 to 8) if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; if (env->exception_cause < 0x50) { - env->pc = direct_vector_ba + 0x40; + env->pc = direct_vector_ba + 0x40; } else { - env->pc = direct_vector_ba + 0x50; + env->pc = direct_vector_ba + 0x50; } - break; + break; case RH850_EXCP_RIE: - //qemu_log("%s: entering RIE handler\n", __func__); // store PSW to FEPSW - env->systemRegs[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); // store PC to FEPC - env->systemRegs[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; + env->sys_reg[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; - //qemu_log("%s, saved pc : %x\n", __func__,env->pc); + env->sys_reg[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; // update PSW env->UM_flag = 0; @@ -375,62 +289,59 @@ void rh850_cpu_do_interrupt(CPUState *cs) env->ID_flag = 1; // modify PC, keep RBASE or EBASE bits 9 to 31 (discard bits 0 to 8) - if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; + if (env->EBV_flag) + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1] & 0xFFFFFE00; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1] & 0xFFFFFE00; - //qemu_log("%s: direct vector addr : %x \n", __func__,direct_vector_ba); env->pc = direct_vector_ba + 0x60; - //qemu_log("%s: pc : 0x%08x \n", __func__, direct_vector_ba+0x60); break; case RH850_EXCP_SYSCALL: qemu_log_mask(CPU_LOG_INT, "%s: entering SYSCALL handler\n", __func__); - uint32_t syscall_cfg = env->systemRegs[BANK_ID_BASIC_1][SCCFG_IDX1] & 0xff; - uint32_t syscall_number = env->exception_cause - 0x8000; - uint32_t syscall_bp = env->systemRegs[BANK_ID_BASIC_1][SCBP_IDX1]; + uint32_t syscall_cfg = env->sys_reg[BANK_ID_BASIC_1][SCCFG_IDX1] & 0xff; + uint32_t syscall_number = env->exception_cause - 0x8000; + uint32_t syscall_bp = env->sys_reg[BANK_ID_BASIC_1][SCBP_IDX1]; uint32_t handler_offset=0, deref_addr=0; - + if (syscall_number <= syscall_cfg) { - deref_addr = syscall_bp + (syscall_number<<2); + deref_addr = syscall_bp + (syscall_number<<2); } else { - deref_addr = syscall_bp; + deref_addr = syscall_bp; } qemu_log_mask(CPU_LOG_INT, "%s syscall_cfg_size = %d\n", __func__,syscall_cfg); qemu_log_mask(CPU_LOG_INT, "%s syscall_bp = %d\n", __func__,syscall_bp); qemu_log_mask(CPU_LOG_INT, "%s syscall_num = %d\n", __func__,syscall_number); qemu_log_mask(CPU_LOG_INT, "%s deref_addr = 0x%x\n", __func__,deref_addr); - handler_offset = mem_deref_4(cs,deref_addr); + handler_offset = mem_deref_4(cs,deref_addr); qemu_log_mask(CPU_LOG_INT, "%s handler offset = %x\n", __func__,handler_offset); // store PSW to EIPSW - env->systemRegs[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); // store PC to EIPC - env->systemRegs[BANK_ID_BASIC_0][EIPC_IDX] = env->pc+4; + env->sys_reg[BANK_ID_BASIC_0][EIPC_IDX] = env->pc+4; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; env->UM_flag = 0; env->EP_flag = 1; env->ID_flag = 1; - // modify PC - env->pc = syscall_bp + handler_offset; + // modify PC + env->pc = syscall_bp + handler_offset; qemu_log_mask(CPU_LOG_INT, "%s: moving pc to = 0x%x\n", __func__,env->pc); - - break; + + break; case RH850_EXCP_FEINT: - //qemu_log("[cpu] entering FEINT handler\n"); // store PSW to FEPSW - env->systemRegs[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); // store PC to FEPC - env->systemRegs[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; + env->sys_reg[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; /* Update PSW. */ env->UM_flag = 0; @@ -439,24 +350,21 @@ void rh850_cpu_do_interrupt(CPUState *cs) env->EP_flag = 0; /* Direct vector. */ - if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1]; + if (env->EBV_flag) + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1]; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1]; - + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1]; /* Redirect to FEINT exception handler. */ - env->pc = (direct_vector_ba & 0xFFFFFF00) + 0xF0; - //qemu_log("%s: moving pc to = 0x%x\n", __func__,env->pc); + env->pc = (direct_vector_ba & 0xFFFFFF00) + 0xF0; break; case RH850_EXCP_FENMI: - //qemu_log("[cpu] entering FENMI handler\n"); // store PSW to FEPSW - env->systemRegs[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][FEPSW_IDX] = psw2int(env); // store PC to FEPC - env->systemRegs[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; + env->sys_reg[BANK_ID_BASIC_0][FEPC_IDX] = env->pc; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][FEIC_IDX] = env->exception_cause; /* Update PSW. */ env->UM_flag = 0; @@ -465,27 +373,23 @@ void rh850_cpu_do_interrupt(CPUState *cs) env->EP_flag = 0; /* Direct vector. */ - if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1]; + if (env->EBV_flag) + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1]; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1]; - + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1]; /* Redirect to FENMI exception handler. */ - env->pc = (direct_vector_ba & 0xFFFFFF00) + 0xE0; + env->pc = (direct_vector_ba & 0xFFFFFF00) + 0xE0; break; case RH850_EXCP_EIINT: - //qemu_log("[cpu] entering EIINT handler\n"); - //qemu_log_mask(CPU_LOG_INT, "%s: entering EIINT handler\n", __func__); - // store PSW to EIPSW - env->systemRegs[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); + env->sys_reg[BANK_ID_BASIC_0][EIPSW_IDX] = psw2int(env); // store PC to EIPC - env->systemRegs[BANK_ID_BASIC_0][EIPC_IDX] = env->pc; + env->sys_reg[BANK_ID_BASIC_0][EIPC_IDX] = env->pc; // Set Exception Cause - env->systemRegs[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; + env->sys_reg[BANK_ID_BASIC_0][EIIC_IDX] = env->exception_cause; // Set priority to ISPR - env->systemRegs[BANK_ID_BASIC_2][ISPR_IDX2] |= (1 << env->exception_priority); + env->sys_reg[BANK_ID_BASIC_2][ISPR_IDX2] |= (1 << env->exception_priority); /* Set PSW.ID (disable further EI exceptions). */ env->ID_flag = 1; @@ -494,46 +398,29 @@ void rh850_cpu_do_interrupt(CPUState *cs) env->EP_flag = 0; /* Modify PC based on dispatch method (direct vector or table reference). */ - if (!env->exception_dv) - { - //qemu_log("[cpu] dispatch EIINT (table reference) for IRQ %d\n", env->exception_cause&0x1ff); + if (!env->exception_dv) { /* Table reference, first read INTBP value. */ - intbp = env->systemRegs[BANK_ID_BASIC_1][INTBP_IDX1]; - //qemu_log("[cpu] INTBP=0x%08x\n", intbp); + intbp = env->sys_reg[BANK_ID_BASIC_1][INTBP_IDX1]; /* Compute address of interrupt handler (based on channel). */ env->pc = mem_deref_4(cs, intbp + 4*(env->exception_cause & 0x1ff)); - //qemu_log("[cpu] PC=0x%08x\n", env->pc); - } - else - { - //qemu_log("[cpu] dispatch EIINT (direct vector) for IRQ %d\n", env->exception_cause&0x1ff); - //qemu_log("[cpu] exception priority=%d\n", env->exception_priority); + } else { /* Direct vector. */ - if (env->EBV_flag) - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][EBASE_IDX1]; + if (env->EBV_flag) + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][EBASE_IDX1]; else - direct_vector_ba = env->systemRegs[BANK_ID_BASIC_1][RBASE_IDX1]; - //qemu_log("[cpu] Direct vector Base Address = 0x%08x\n", direct_vector_ba); - + direct_vector_ba = env->sys_reg[BANK_ID_BASIC_1][RBASE_IDX1]; + /* Is RINT bit set ? */ - if (direct_vector_ba & 1) - { - //qemu_log("[cpu] RINT bit set\n"); + if (direct_vector_ba & 1) { /* Reduced vector (one handler for any priority). */ - env->pc = (direct_vector_ba & 0xFFFFFF00) + 0x100; - } - else - { - //qemu_log("[cpu] RINT bit NOT set\n"); + env->pc = (direct_vector_ba & 0xFFFFFF00) + 0x100; + } else { /* One handler per priority level. */ - env->pc = (direct_vector_ba & 0xFFFFFF00) + 0x100 + (env->exception_priority<<4); + env->pc = (direct_vector_ba & 0xFFFFFF00) + 0x100 + (env->exception_priority<<4); } - //qemu_log("[cpu] PC=0x%08x\n", env->pc); } break; } - -#endif cs->exception_index = EXCP_NONE; /* mark handled to qemu */ } diff --git a/qemu/target/rh850/helper.h b/qemu/target/rh850/helper.h index 24c9fa5865..f48af8ba55 100644 --- a/qemu/target/rh850/helper.h +++ b/qemu/target/rh850/helper.h @@ -1,29 +1,11 @@ DEF_HELPER_4(uc_tracecode, void, i32, i32, ptr, i64) DEF_HELPER_6(uc_traceopcode, void, ptr, i64, i64, i32, ptr, i64) -DEF_HELPER_1(uc_rh850_exit, void, env) /* Exceptions */ DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_3(raise_exception_with_cause, noreturn, env, i32, i32) - -/* Floating Point - rounding mode */ -DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) - -/* Floating Point - fused */ -DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) - /* Floating Point - Single Precision */ -DEF_HELPER_FLAGS_2(f32_is_normal, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(f32_is_zero_or_normal, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(f32_is_infinity, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_1(f_sync_fflags, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32) @@ -61,32 +43,14 @@ DEF_HELPER_FLAGS_2(frecip_s, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(frsqrt_s, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(f_is_nan_s, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64) DEF_HELPER_FLAGS_4(fmaf_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmsf_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fnmaf_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fnmsf_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) - - - -#if defined(TARGET_RH85064) -DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64) -#endif -DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) -#if defined(TARGET_RH85064) -DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) -#endif -DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64) - /* Floating Point - Double Precision */ DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -123,35 +87,5 @@ DEF_HELPER_FLAGS_2(frecip_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(frsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(f_is_nan_d, TCG_CALL_NO_RWG, i32, env, i64) -DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, i32, env, i64, i64) - - - -DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64) -#if defined(TARGET_RH85064) -DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64) -DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64) -#endif -DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl) -#if defined(TARGET_RH85064) -DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl) -#endif -DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) - -/* Special functions */ -//DEF_HELPER_3(csrrw, tl, env, tl, tl) -//DEF_HELPER_4(csrrs, tl, env, tl, tl, tl) -//DEF_HELPER_4(csrrc, tl, env, tl, tl, tl) -#ifndef CONFIG_USER_ONLY -//DEF_HELPER_2(sret, tl, env, tl) -//DEF_HELPER_2(mret, tl, env, tl) -//DEF_HELPER_1(wfi, void, env) -DEF_HELPER_1(tlb_flush, void, env) -#endif diff --git a/qemu/target/rh850/instmap.h b/qemu/target/rh850/instmap.h index 2cbf2aed2f..2c9c3e888b 100644 --- a/qemu/target/rh850/instmap.h +++ b/qemu/target/rh850/instmap.h @@ -16,37 +16,8 @@ * this program. If not, see . */ -#ifndef _RH850_INSTMAP_H -#define _RH850_INSTMAP_H - -enum{ - /*SIGNED INT*/ - COND_RH850_BGE = 1110, - COND_RH850_BGT = 1111, - COND_RH850_BLE = 0111, - COND_RH850_BLT = 0110, - /*UNSIGNED INT*/ - COND_RH850_BH = 1011, - COND_RH850_BL = 0001, - COND_RH850_BNH = 0011, - COND_RH850_BNL = 1001, - /*COMMON*/ - COND_RH850_BE = 0010, - COND_RH850_BNE = 1010, - /*OTHERS*/ - COND_RH850_BC = 0001, - COND_RH850_BF = 1010, - COND_RH850_BN = 0100, - COND_RH850_BNC = 1001, - COND_RH850_BNV = 1000, - COND_RH850_BNZ = 1010, - COND_RH850_BP = 1100, - COND_RH850_BR = 0101, - COND_RH850_BSA = 1101, - COND_RH850_BT = 0010, - COND_RH850_BV = 0000, - COND_RH850_BZ = 0010, -}; +#ifndef RH850_INSTMAP_H +#define RH850_INSTMAP_H #define MASK_OP_MAJOR(op) (op & (0x3F << 5)) // the major opcode in rh850 is at bits 10-5 enum { @@ -537,88 +508,10 @@ enum { operation_CLL = 2, }; - - -////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////// -////////////////////////////////////////////////////////// - - -#define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \ - | (extract32(inst, 25, 6) << 5) \ - | (extract32(inst, 7, 1) << 11) \ - | (sextract64(inst, 31, 1) << 12)) - -#define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \ - | (sextract64(inst, 25, 7) << 5)) - -#define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \ - | (extract32(inst, 20, 1) << 11) \ - | (extract32(inst, 12, 8) << 12) \ - | (sextract64(inst, 31, 1) << 20)) - - #define GET_RS1(inst) extract32(inst, 0, 5) //appropriate for RH850 #define GET_RS2(inst) extract32(inst, 11, 5) //appropriate for RH850 #define GET_RS3(inst) extract32(inst, 27, 5) //appropriate for RH850 -#define GET_DISP(inst) (extract32(inst, 20, 7) | (sextract32(inst, 32, 16) << 7 ) ) //b47-b32 + b26-b20 - -#define GET_RM(inst) extract32(inst, 12, 3) -#define GET_RD(inst) extract32(inst, 7, 5) -#define GET_IMM(inst) sextract64(inst, 20, 12) #define GET_IMM_32(inst) sextract64(inst, 16, 32) -/* RVC decoding macros */ -#define GET_C_IMM(inst) (extract32(inst, 2, 5) \ - | (sextract64(inst, 12, 1) << 5)) -#define GET_C_ZIMM(inst) (extract32(inst, 2, 5) \ - | (extract32(inst, 12, 1) << 5)) -#define GET_C_ADDI4SPN_IMM(inst) ((extract32(inst, 6, 1) << 2) \ - | (extract32(inst, 5, 1) << 3) \ - | (extract32(inst, 11, 2) << 4) \ - | (extract32(inst, 7, 4) << 6)) -#define GET_C_ADDI16SP_IMM(inst) ((extract32(inst, 6, 1) << 4) \ - | (extract32(inst, 2, 1) << 5) \ - | (extract32(inst, 5, 1) << 6) \ - | (extract32(inst, 3, 2) << 7) \ - | (sextract64(inst, 12, 1) << 9)) -#define GET_C_LWSP_IMM(inst) ((extract32(inst, 4, 3) << 2) \ - | (extract32(inst, 12, 1) << 5) \ - | (extract32(inst, 2, 2) << 6)) -#define GET_C_LDSP_IMM(inst) ((extract32(inst, 5, 2) << 3) \ - | (extract32(inst, 12, 1) << 5) \ - | (extract32(inst, 2, 3) << 6)) -#define GET_C_SWSP_IMM(inst) ((extract32(inst, 9, 4) << 2) \ - | (extract32(inst, 7, 2) << 6)) -#define GET_C_SDSP_IMM(inst) ((extract32(inst, 10, 3) << 3) \ - | (extract32(inst, 7, 3) << 6)) -#define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \ - | (extract32(inst, 10, 3) << 3) \ - | (extract32(inst, 5, 1) << 6)) -#define GET_C_LD_IMM(inst) ((extract32(inst, 10, 3) << 3) \ - | (extract32(inst, 5, 2) << 6)) -#define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ - | (extract32(inst, 11, 1) << 4) \ - | (extract32(inst, 2, 1) << 5) \ - | (extract32(inst, 7, 1) << 6) \ - | (extract32(inst, 6, 1) << 7) \ - | (extract32(inst, 9, 2) << 8) \ - | (extract32(inst, 8, 1) << 10) \ - | (sextract64(inst, 12, 1) << 11)) -#define GET_C_B_IMM(inst) ((extract32(inst, 3, 2) << 1) \ - | (extract32(inst, 10, 2) << 3) \ - | (extract32(inst, 2, 1) << 5) \ - | (extract32(inst, 5, 2) << 6) \ - | (sextract64(inst, 12, 1) << 8)) -#define GET_C_SIMM3(inst) extract32(inst, 10, 3) -#define GET_C_RD(inst) GET_RD(inst) -#define GET_C_RS1(inst) GET_RD(inst) -#define GET_C_RS2(inst) extract32(inst, 2, 5) -#define GET_C_RS1S(inst) (8 + extract32(inst, 7, 3)) -#define GET_C_RS2S(inst) (8 + extract32(inst, 2, 3)) - -#endif /* _RH850_INSTMAP_H */ \ No newline at end of file +#endif /* _RH850_INSTMAP_H */ diff --git a/qemu/target/rh850/op_helper.c b/qemu/target/rh850/op_helper.c index 36e272e7a0..af2fff29bd 100644 --- a/qemu/target/rh850/op_helper.c +++ b/qemu/target/rh850/op_helper.c @@ -17,11 +17,7 @@ * this program. If not, see . */ -#include "qemu/osdep.h" -#include "qemu/log.h" -#include "cpu.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" /* Exceptions processing helpers */ void QEMU_NORETURN do_raise_exception_err(CPURH850State *env, @@ -53,37 +49,3 @@ void helper_raise_exception_with_cause(CPURH850State *env, uint32_t exception, u { do_raise_exception_err_with_cause(env, exception, cause, 0); } - -target_ulong csr_read_helper(CPURH850State *env, target_ulong csrno) -{ - return 0; -} - -#ifndef CONFIG_USER_ONLY - -/* iothread_mutex must be held */ -void rh850_set_local_interrupt(RH850CPU *cpu, target_ulong mask, int value) -{ -} - -void rh850_set_mode(CPURH850State *env, target_ulong newpriv) -{ -} - -void helper_tlb_flush(CPURH850State *env) -{ - RH850CPU *cpu = rh850_env_get_cpu(env); - CPUState *cs = CPU(cpu); - tlb_flush(cs); -} - -void helper_uc_rh850_exit(CPURH850State *env) -{ - CPUState *cs = CPU(env); - - cs->exception_index = EXCP_HLT; - cs->halted = 1; - cpu_loop_exit(cs); -} - -#endif /* !CONFIG_USER_ONLY */ diff --git a/qemu/target/rh850/pmp.c b/qemu/target/rh850/pmp.c deleted file mode 100644 index 8f98659d3a..0000000000 --- a/qemu/target/rh850/pmp.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * QEMU RH850 PMP (Physical Memory Protection) - * - * Author: Daire McNamara, daire.mcnamara@emdalo.com - * Ivan Griffin, ivan.griffin@emdalo.com - * - * This provides a RH850 Physical Memory Protection implementation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/* - * PMP (Physical Memory Protection) is as-of-yet unused and needs testing. - */ - -#include "qemu/osdep.h" -#include "qemu/log.h" -#include "cpu.h" -#include "qemu-common.h" - -#ifndef CONFIG_USER_ONLY - -#define RH850_DEBUG_PMP 0 -#define PMP_DEBUG(fmt, ...) \ - do { \ - if (RH850_DEBUG_PMP) { \ - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ - } \ - } while (0) - -static void pmp_write_cfg(CPURH850State *env, uint32_t addr_index, - uint8_t val); -static uint8_t pmp_read_cfg(CPURH850State *env, uint32_t addr_index); -static void pmp_update_rule(CPURH850State *env, uint32_t pmp_index); - -/* - * Accessor method to extract address matching type 'a field' from cfg reg - */ -static inline uint8_t pmp_get_a_field(uint8_t cfg) -{ - uint8_t a = cfg >> 3; - return a & 0x3; -} - -/* - * Check whether a PMP is locked or not. - */ -static inline int pmp_is_locked(CPURH850State *env, uint32_t pmp_index) -{ - - if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { - return 1; - } - - /* Top PMP has no 'next' to check */ - if ((pmp_index + 1u) >= MAX_RH850_PMPS) { - return 0; - } - - /* In TOR mode, need to check the lock bit of the next pmp - * (if there is a next) - */ - const uint8_t a_field = - pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg); - if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) && - (PMP_AMATCH_TOR == a_field)) { - return 1; - } - - return 0; -} - -/* - * Count the number of active rules. - */ -static inline uint32_t pmp_get_num_rules(CPURH850State *env) -{ - return env->pmp_state.num_rules; -} - -/* - * Accessor to get the cfg reg for a specific PMP/HART - */ -static inline uint8_t pmp_read_cfg(CPURH850State *env, uint32_t pmp_index) -{ - if (pmp_index < MAX_RH850_PMPS) { - return env->pmp_state.pmp[pmp_index].cfg_reg; - } - - return 0; -} - - -/* - * Accessor to set the cfg reg for a specific PMP/HART - * Bounds checks and relevant lock bit. - */ -static void pmp_write_cfg(CPURH850State *env, uint32_t pmp_index, uint8_t val) -{ - if (pmp_index < MAX_RH850_PMPS) { - if (!pmp_is_locked(env, pmp_index)) { - env->pmp_state.pmp[pmp_index].cfg_reg = val; - pmp_update_rule(env, pmp_index); - } else { - PMP_DEBUG("ignoring write - locked"); - } - } else { - PMP_DEBUG("ignoring write - out of bounds"); - } -} - -static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) -{ - /* - aaaa...aaa0 8-byte NAPOT range - aaaa...aa01 16-byte NAPOT range - aaaa...a011 32-byte NAPOT range - ... - aa01...1111 2^XLEN-byte NAPOT range - a011...1111 2^(XLEN+1)-byte NAPOT range - 0111...1111 2^(XLEN+2)-byte NAPOT range - 1111...1111 Reserved - */ - if (a == -1) { - *sa = 0u; - *ea = -1; - return; - } else { - target_ulong t1 = ctz64(~a); - target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; - target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; - *sa = base; - *ea = base + range; - } -} - - -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' - * end address values. - * This function is called relatively infrequently whereas the check that - * an address is within a pmp rule is called often, so optimise that one - */ -static void pmp_update_rule(CPURH850State *env, uint32_t pmp_index) -{ - int i; - - env->pmp_state.num_rules = 0; - - uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; - target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; - target_ulong prev_addr = 0u; - target_ulong sa = 0u; - target_ulong ea = 0u; - - if (pmp_index >= 1u) { - prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg; - } - - switch (pmp_get_a_field(this_cfg)) { - case PMP_AMATCH_OFF: - sa = 0u; - ea = -1; - break; - - case PMP_AMATCH_TOR: - sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ - ea = (this_addr << 2) - 1u; - break; - - case PMP_AMATCH_NA4: - sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ - ea = (this_addr + 4u) - 1u; - break; - - case PMP_AMATCH_NAPOT: - pmp_decode_napot(this_addr, &sa, &ea); - break; - - default: - sa = 0u; - ea = 0u; - break; - } - - env->pmp_state.addr[pmp_index].sa = sa; - env->pmp_state.addr[pmp_index].ea = ea; - - for (i = 0; i < MAX_RH850_PMPS; i++) { - const uint8_t a_field = - pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); - if (PMP_AMATCH_OFF != a_field) { - env->pmp_state.num_rules++; - } - } -} - -static int pmp_is_in_range(CPURH850State *env, int pmp_index, target_ulong addr) -{ - int result = 0; - - if ((addr >= env->pmp_state.addr[pmp_index].sa) - && (addr <= env->pmp_state.addr[pmp_index].ea)) { - result = 1; - } else { - result = 0; - } - - return result; -} - - -/* - * Public Interface - */ - -/* - * Check if the address has required RWX privs to complete desired operation - */ -bool pmp_hart_has_privs(CPURH850State *env, target_ulong addr, - target_ulong size, pmp_priv_t privs) -{ - int i = 0; - int ret = -1; - target_ulong s = 0; - target_ulong e = 0; - pmp_priv_t allowed_privs = 0; - - /* Short cut if no rules */ - if (0 == pmp_get_num_rules(env)) { - return true; - } - - /* 1.10 draft priv spec states there is an implicit order - from low to high */ - for (i = 0; i < MAX_RH850_PMPS; i++) { - s = pmp_is_in_range(env, i, addr); - e = pmp_is_in_range(env, i, addr + size); - - /* partially inside */ - if ((s + e) == 1) { - PMP_DEBUG("pmp violation - access is partially inside"); - ret = 0; - break; - } - - /* fully inside */ - const uint8_t a_field = - pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); - if ((s + e) == 2) { - if (PMP_AMATCH_OFF == a_field) { - return 1; - } - - allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; - if ((env->priv != PRV_M) || pmp_is_locked(env, i)) { - allowed_privs &= env->pmp_state.pmp[i].cfg_reg; - } - - if ((privs & allowed_privs) == privs) { - ret = 1; - break; - } else { - ret = 0; - break; - } - } - } - - /* No rule matched */ - if (ret == -1) { - if (env->priv == PRV_M) { - ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an - * M-Mode access, the access succeeds */ - } else { - ret = 0; /* Other modes are not allowed to succeed if they don't - * match a rule, but there are rules. We've checked for - * no rule earlier in this function. */ - } - } - - return ret == 1 ? true : false; -} - - -/* - * Handle a write to a pmpcfg CSP - */ -void pmpcfg_csr_write(CPURH850State *env, uint32_t reg_index, - target_ulong val) -{ - int i; - uint8_t cfg_val; - - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, val); - - if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { - PMP_DEBUG("ignoring write - incorrect address"); - return; - } - - for (i = 0; i < sizeof(target_ulong); i++) { - cfg_val = (val >> 8 * i) & 0xff; - pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, - cfg_val); - } -} - - -/* - * Handle a read from a pmpcfg CSP - */ -target_ulong pmpcfg_csr_read(CPURH850State *env, uint32_t reg_index) -{ - int i; - target_ulong cfg_val = 0; - uint8_t val = 0; - - for (i = 0; i < sizeof(target_ulong); i++) { - val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); - cfg_val |= (val << (i * 8)); - } - - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, cfg_val); - - return cfg_val; -} - - -/* - * Handle a write to a pmpaddr CSP - */ -void pmpaddr_csr_write(CPURH850State *env, uint32_t addr_index, - target_ulong val) -{ - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, val); - - if (addr_index < MAX_RH850_PMPS) { - if (!pmp_is_locked(env, addr_index)) { - env->pmp_state.pmp[addr_index].addr_reg = val; - pmp_update_rule(env, addr_index); - } else { - PMP_DEBUG("ignoring write - locked"); - } - } else { - PMP_DEBUG("ignoring write - out of bounds"); - } -} - - -/* - * Handle a read from a pmpaddr CSP - */ -target_ulong pmpaddr_csr_read(CPURH850State *env, uint32_t addr_index) -{ - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, - env->pmp_state.pmp[addr_index].addr_reg); - if (addr_index < MAX_RH850_PMPS) { - return env->pmp_state.pmp[addr_index].addr_reg; - } else { - PMP_DEBUG("ignoring read - out of bounds"); - return 0; - } -} - -#endif diff --git a/qemu/target/rh850/pmp.h b/qemu/target/rh850/pmp.h deleted file mode 100644 index e6e43e8241..0000000000 --- a/qemu/target/rh850/pmp.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * QEMU RH850 PMP (Physical Memory Protection) - * - * Author: Daire McNamara, daire.mcnamara@emdalo.com - * Ivan Griffin, ivan.griffin@emdalo.com - * - * This provides a RH850 Physical Memory Protection interface - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef _RH850_PMP_H_ -#define _RH850_PMP_H_ - -typedef enum { - PMP_READ = 1 << 0, - PMP_WRITE = 1 << 1, - PMP_EXEC = 1 << 2, - PMP_LOCK = 1 << 7 -} pmp_priv_t; - -typedef enum { - PMP_AMATCH_OFF, /* Null (off) */ - PMP_AMATCH_TOR, /* Top of Range */ - PMP_AMATCH_NA4, /* Naturally aligned four-byte region */ - PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ -} pmp_am_t; - -typedef struct { - target_ulong addr_reg; - uint8_t cfg_reg; -} pmp_entry_t; - -typedef struct { - target_ulong sa; - target_ulong ea; -} pmp_addr_t; - -typedef struct { - pmp_entry_t pmp[MAX_RH850_PMPS]; - pmp_addr_t addr[MAX_RH850_PMPS]; - uint32_t num_rules; -} pmp_table_t; - -void pmpcfg_csr_write(CPURH850State *env, uint32_t reg_index, - target_ulong val); -target_ulong pmpcfg_csr_read(CPURH850State *env, uint32_t reg_index); -void pmpaddr_csr_write(CPURH850State *env, uint32_t addr_index, - target_ulong val); -target_ulong pmpaddr_csr_read(CPURH850State *env, uint32_t addr_index); -bool pmp_hart_has_privs(CPURH850State *env, target_ulong addr, - target_ulong size, pmp_priv_t priv); - -#endif diff --git a/qemu/target/rh850/translate.c b/qemu/target/rh850/translate.c index 7081656c95..04ac4b7627 100644 --- a/qemu/target/rh850/translate.c +++ b/qemu/target/rh850/translate.c @@ -61,23 +61,14 @@ #define DISAS_UNICORN_HALT DISAS_TARGET_11 -/* global register indices */ -static TCGv cpu_gpr[NUM_GP_REGS]; -static TCGv cpu_pc; -static TCGv cpu_sysRegs[NUM_SYS_REG_BANKS][MAX_SYS_REGS_IN_BANK]; -// static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ -static TCGv cpu_sysDatabuffRegs[1], cpu_LLbit, cpu_LLAddress; -static TCGv load_res; -static TCGv load_val; - // PSW register flags. These are for temporary use only during // calculations. Before usage they should be set from PSW and // stored back to PSW after changes. // TODO: since PSW as a register is rarely used - only when ld/str sys reg and // on some branches (TRAP, ...) it makes sense to compose/decompose PSW // on these occcasions and not have PSW stored in registers below. -TCGv_i32 cpu_ZF, cpu_SF, cpu_OVF, cpu_CYF, cpu_SATF, cpu_ID, cpu_EP, cpu_NP, - cpu_EBV, cpu_CU0, cpu_CU1, cpu_CU2, cpu_UM; +// TCGv_i32 tcg_ctx->cpu_ZF, tcg_ctx->cpu_SF, tcg_ctx->cpu_OVF, tcg_ctx->cpu_CYF, tcg_ctx->cpu_SATF, tcg_ctx->cpu_ID, tcg_ctx->cpu_EP, tcg_ctx->cpu_NP, +// cpu_EBV, tcg_ctx->cpu_CU0, tcg_ctx->cpu_CU1, tcg_ctx->cpu_CU2, tcg_ctx->cpu_UM; /** Const, RH850 does not have MMU. */ @@ -124,6 +115,108 @@ enum { OPC_RH850_BINS = 123456, }; +const char * const rh850_gp_regnames[] = { + "r0-zero", "r1", "r2", "r3-sp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10 ", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r2 ", + "r24", "r25", "r26", "r27", "r28", "r29", "r30-ep", "r31-lp" +}; + +// Basic system registers +const char *const rh850_sys_regnames[][MAX_SYS_REGS_IN_BANK] = { + // SELECTION ID 0 + {// [5] used to be psw, but now it is stored in flags only + "eipc", "eipsw", "fepc", "fepsw", NULL, NULL, "fpsr", "fpepc", + "fpst", "fpcc", "fpcfg", "fpec", NULL, "eiic", "feic", NULL, + "ctpc", "ctpsw", NULL, NULL, "ctbp", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, "eiwr", "fewr", NULL, "bsel"}, + + // SELECTION ID 1 + {"mcfg0", NULL, "rbase", "ebase", "intbp", "mctl", "pid", + "fpipr", NULL, NULL, NULL, "sccfg", "scbp"}, + + // SELECTION ID 2 + {"htcfg0", NULL, NULL, NULL, NULL, NULL, "mea", "asid", "mei", NULL, "ispr", + "pmr", "icsr", "intcfg"}, + + // SELECTION ID 3 + {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}, + + // SELECTION ID 4 + {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "ictagl", "ictagh", "icdatl", "icdath", NULL, NULL, NULL, NULL, + "icctrl", NULL, "iccfg", NULL, "icerr", NULL}, + + // SELECTION ID 5 + {"mpm", "mprc", NULL, NULL, "mpbrgn", "mptrgn", NULL, NULL, "mca", "mcs", + "mcc", "mcr"}, + + // SELECTION ID 6 + {"mpla0", "mpua0", "mpat0", NULL, "mpla1", "mpua1", "mpat1", NULL, + "mpla2", "mpua2", "mpat2", NULL, "mpla3", "mpua3", "mpat3", NULL, + "mpla4", "mpua4", "mpat4", NULL, "mpla5", "mpua5", "mpat5", NULL, + "mpla6", "mpua6", "mpat6", NULL, "mpla7", "mpua7", "mpat7", NULL}, + + // SELECTION ID 7 + {/* MPU function system registers */ + "mpla8", "mpua8", "mpat8", NULL, "mpla9", "mpua9", "mpat9", NULL, + "mpla10", "mpua10", "mpat10", NULL, "mpla11", "mpua11", "mpat11", NULL, + "mpla12", "mpua12", "mpat12", NULL, "mpla13", "mpua13", "mpat13", NULL, + "mpla14", "mpua14", "mpat14", NULL, "mpla15", "mpua15", "mpat15", NULL}}; + +// Where bits are read only, mask is set to 0 +const uint32_t rh850_sys_reg_read_only_masks[][MAX_SYS_REGS_IN_BANK] = { + + {// SELECTION ID 0 PSW - + // implemented as registers for each used bit, see cpu_ZF, ... + 0xFFFFFFFF, 0x40078EFF, 0xFFFFFFFF, + 0x40078EFF, 0x0, /*0x40018EFF*/ 0, + 0xFFEEFFFF, 0xFFFFFFFE, 0x00003F3F, + 0x000000FF, 0x0000031F, 0x00000001, + 0x0, 0xFFFFFFFF, 0xFFFFFFFF, + 0x0, 0xFFFFFFFF, 0x0000001F, + 0x0, 0x0, 0xFFFFFFFE, + 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, + 0x0, 0xFFFFFFFF, 0xFFFFFFFF, + 0x0, 0x0}, + {// SELECTION ID 1 + // for MCFG (idx = 0), byte 3 seems to not be writable, at least on + // devicee used for testing + 0x00000000, 0x0, 0x00000000, 0xFFFFFE01, 0xFFFFFE00, 0x00000003, + 0x00000000, 0x0000001F, 0x0, 0x0, 0x0, 0x000000FF, 0xFFFFFFFC}, + {// SELECTION ID 2 + 0x00000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0xFFFFFFFF, 0x000003FF, 0x001F073F, + 0x0, 0x00000000, 0x0000FFFF, 0x00000000, 0x00000001}, + {// SELECTION ID 3 + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + {// SELECTION ID 4 + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0xFFFFFA35, 0xF0FFFF00, 0xFFFFFFFF, 0xFFFFFFFF, 0x0, 0x0, 0x0, 0x0, + 0x00020107, 0x0, 0x00000000, 0x0, 0xBF3F7FFD, 0x0}, + {// SELECTION ID 5 + 0x00000003, 0x0000FFFF, 0x0, 0x0, 0x00000000, 0x00000000, 0x0, 0x0, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000013F}, + {// SELECTION ID 6 + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFF, 0x03FF00FF, 0x0, + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0}, + {// SELECTION ID 7 + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFF, 0x03FF00FF, 0x0, + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, + 0xFFFFFFFC, 0xFFFFFFFC, 0x03FF00FF, 0x0, 0xFFFFFFFC, 0xFFFFFFFC, + 0x03FF00FF, 0x0}}; + +/*Data Buffer Operation Registers: + * sr24, 13 - cbdcr */ +const char * const rh850_sys_databuf_regname = "cbdcr"; static void gen_exception_debug(DisasContext *dc) { @@ -153,25 +246,25 @@ static void gen_goto_tb_imm(DisasContext *ctx, int n, target_ulong dest) TCGContext *tcg_ctx = ctx->uc->tcg_ctx; if (unlikely(ctx->base.singlestep_enabled)) { - tcg_gen_movi_tl(tcg_ctx, cpu_pc, dest); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dest); gen_exception_debug(ctx); } else { tcg_gen_goto_tb(tcg_ctx, n); - tcg_gen_movi_tl(tcg_ctx, cpu_pc, dest); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dest); tcg_gen_exit_tb(tcg_ctx, ctx->base.tb, n); } } /* Wrapper for getting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated + * tcg_ctx->cpu_gpr[0] is not actually allocated */ void gen_get_gpr(TCGContext *tcg_ctx, TCGv t, int reg_num) { if (reg_num == 0) { tcg_gen_movi_tl(tcg_ctx, t, 0); } else { - tcg_gen_mov_tl(tcg_ctx, t, cpu_gpr[reg_num]); + tcg_gen_mov_tl(tcg_ctx, t, tcg_ctx->cpu_gpr[reg_num]); } } @@ -181,24 +274,24 @@ void gen_get_gpr(TCGContext *tcg_ctx, TCGv t, int reg_num) void gen_set_spr(TCGContext *tcg_ctx, int bank_id, int reg_id, TCGv t) { - tcg_gen_mov_tl(tcg_ctx, cpu_sysRegs[bank_id][reg_id], t); + tcg_gen_mov_tl(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[bank_id][reg_id], t); } /* Wrapper for gettint sysreg values. */ void gen_get_spr(TCGContext *tcg_ctx, int bank_id, int reg_id, TCGv t) { - tcg_gen_mov_tl(tcg_ctx, t, cpu_sysRegs[bank_id][reg_id]); + tcg_gen_mov_tl(tcg_ctx, t, tcg_ctx->rh850_cpu_sys_reg[bank_id][reg_id]); } /* Wrapper for setting reg values - need to check of reg is zero since - * cpu_gpr[0] is not actually allocated. this is more for safety purposes, + * tcg_ctx->cpu_gpr[0] is not actually allocated. this is more for safety purposes, * since we usually avoid calling the OP_TYPE_gen function if we see a write to * $zero */ void gen_set_gpr(TCGContext *tcg_ctx, int reg_num_dst, TCGv t) { if (reg_num_dst != 0) { - tcg_gen_mov_tl(tcg_ctx, cpu_gpr[reg_num_dst], t); + tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg_num_dst], t); } } @@ -209,13 +302,11 @@ void gen_set_gpr(TCGContext *tcg_ctx, int reg_num_dst, TCGv t) * work this way :). **/ -static void gen_goto_tb_rl(DisasContext *ctx, int n, int reg, int insn_size, uint32_t dest) -{ +static void gen_goto_tb_rl(DisasContext *ctx, int n, int reg, int insn_size, uint32_t dest) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGv reg_value = tcg_temp_new_i32(tcg_ctx); - if (unlikely(ctx->base.singlestep_enabled)) - { + if (unlikely(ctx->base.singlestep_enabled)) { /* GR[reg] <- PC + insn_size */ tcg_gen_movi_i32(tcg_ctx, reg_value, ctx->pc); @@ -223,15 +314,13 @@ static void gen_goto_tb_rl(DisasContext *ctx, int n, int reg, int insn_size, uin gen_set_gpr(tcg_ctx, reg, reg_value); /* PC <- dest */ - tcg_gen_movi_i32(tcg_ctx, cpu_pc, dest); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_pc, dest); tcg_temp_free_i32(tcg_ctx, reg_value); /* Generate exception. */ gen_exception_debug(ctx); - } - else - { + } else { tcg_gen_goto_tb(tcg_ctx, n); /* GR[reg] <- PC + insn_size */ @@ -240,7 +329,7 @@ static void gen_goto_tb_rl(DisasContext *ctx, int n, int reg, int insn_size, uin gen_set_gpr(tcg_ctx, reg, reg_value); /* PC <- dest */ - tcg_gen_movi_i32(tcg_ctx, cpu_pc, dest); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_pc, dest); tcg_temp_free_i32(tcg_ctx, reg_value); @@ -253,39 +342,39 @@ static inline void tcgv_to_flags(TCGContext *tcg_ctx, TCGv reg) { TCGv temp = tcg_temp_new_i32(tcg_ctx); tcg_gen_mov_i32(tcg_ctx, temp, reg); - tcg_gen_andi_i32(tcg_ctx, cpu_ZF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_ZF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_SF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_SF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_OVF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_OVF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_SATF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_SATF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_ID, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_ID, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_EP, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_EP, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_NP, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_NP, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x8); - tcg_gen_andi_i32(tcg_ctx, cpu_EBV, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_EBV, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_CU0, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CU0, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_CU1, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CU1, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_CU2, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CU2, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x12); - tcg_gen_andi_i32(tcg_ctx, cpu_UM, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_UM, temp, 0x1); tcg_temp_free(tcg_ctx, temp); } @@ -295,15 +384,15 @@ static void tcgv_to_flags_z_cy_ov_s_sat(TCGContext *tcg_ctx, TCGv reg) { TCGv temp = tcg_temp_new_i32(tcg_ctx); tcg_gen_mov_i32(tcg_ctx, temp, reg); - tcg_gen_andi_i32(tcg_ctx, cpu_ZF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_ZF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_SF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_SF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_OVF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_OVF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, temp, 0x1); tcg_gen_shri_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_andi_i32(tcg_ctx, cpu_SATF, temp, 0x1); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_SATF, temp, 0x1); tcg_temp_free(tcg_ctx, temp); } @@ -315,28 +404,28 @@ static void flags_to_tcgv_id_ep_np_ebv_cu_um(TCGContext *tcg_ctx, TCGv reg) TCGv temp = tcg_temp_new_i32(tcg_ctx); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_ID, 0x5); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_ID, 0x5); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_EP, 0x6); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_EP, 0x6); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_NP, 0x7); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_NP, 0x7); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_EBV, 0xF); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_EBV, 0xF); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_CU0, 0x10); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_CU0, 0x10); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_CU1, 0x11); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_CU1, 0x11); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_CU2, 0x12); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_CU2, 0x12); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_UM, 0x1E); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_UM, 0x1E); tcg_gen_or_i32(tcg_ctx, reg, reg,temp); tcg_temp_free(tcg_ctx, temp); @@ -348,14 +437,14 @@ static void flags_to_tcgv_z_cy_ov_s_sat(TCGContext *tcg_ctx, TCGv reg) // update psw register, first reset flags before ORing new values tcg_gen_andi_i32(tcg_ctx, reg, reg, 0xffffffe0); TCGv temp = tcg_temp_new_i32(tcg_ctx); - tcg_gen_or_i32(tcg_ctx, reg, reg, cpu_ZF); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_SF, 0x1); + tcg_gen_or_i32(tcg_ctx, reg, reg, tcg_ctx->cpu_ZF); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_SF, 0x1); tcg_gen_or_i32(tcg_ctx, reg,reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_OVF, 0x2); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_OVF, 0x2); tcg_gen_or_i32(tcg_ctx, reg,reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_CYF, 0x3); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_CYF, 0x3); tcg_gen_or_i32(tcg_ctx, reg,reg,temp); - tcg_gen_shli_i32(tcg_ctx, temp, cpu_SATF, 0x4); + tcg_gen_shli_i32(tcg_ctx, temp, tcg_ctx->cpu_SATF, 0x4); tcg_gen_or_i32(tcg_ctx, reg,reg,temp); tcg_temp_free(tcg_ctx, temp); } @@ -373,72 +462,72 @@ static TCGv condition_satisfied(TCGContext *tcg_ctx, int cond) TCGv condResult = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, condResult, 0x0); - switch(cond) { + switch (cond) { case GE_COND: - tcg_gen_xor_i32(tcg_ctx, condResult, cpu_SF, cpu_OVF); + tcg_gen_xor_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF, tcg_ctx->cpu_OVF); tcg_gen_not_i32(tcg_ctx, condResult, condResult); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case GT_COND: - tcg_gen_xor_i32(tcg_ctx, condResult, cpu_SF, cpu_OVF); - tcg_gen_or_i32(tcg_ctx, condResult, condResult, cpu_ZF); + tcg_gen_xor_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF, tcg_ctx->cpu_OVF); + tcg_gen_or_i32(tcg_ctx, condResult, condResult, tcg_ctx->cpu_ZF); tcg_gen_not_i32(tcg_ctx, condResult, condResult); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case LE_COND: - tcg_gen_xor_i32(tcg_ctx, condResult, cpu_SF, cpu_OVF); - tcg_gen_or_i32(tcg_ctx, condResult, condResult, cpu_ZF); + tcg_gen_xor_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF, tcg_ctx->cpu_OVF); + tcg_gen_or_i32(tcg_ctx, condResult, condResult, tcg_ctx->cpu_ZF); break; case LT_COND: - tcg_gen_xor_i32(tcg_ctx, condResult, cpu_SF, cpu_OVF); + tcg_gen_xor_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF, tcg_ctx->cpu_OVF); break; case H_COND: - tcg_gen_or_i32(tcg_ctx, condResult, cpu_CYF, cpu_ZF); + tcg_gen_or_i32(tcg_ctx, condResult, tcg_ctx->cpu_CYF, tcg_ctx->cpu_ZF); tcg_gen_not_i32(tcg_ctx, condResult, condResult); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case NH_COND: - tcg_gen_or_i32(tcg_ctx, condResult, cpu_CYF, cpu_ZF); + tcg_gen_or_i32(tcg_ctx, condResult, tcg_ctx->cpu_CYF, tcg_ctx->cpu_ZF); break; case NS_COND: - tcg_gen_not_i32(tcg_ctx, condResult, cpu_SF); + tcg_gen_not_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case S_COND: - tcg_gen_mov_i32(tcg_ctx, condResult, cpu_SF); + tcg_gen_mov_i32(tcg_ctx, condResult, tcg_ctx->cpu_SF); break; case C_COND: - tcg_gen_mov_i32(tcg_ctx, condResult, cpu_CYF); + tcg_gen_mov_i32(tcg_ctx, condResult, tcg_ctx->cpu_CYF); break; case NC_COND: - tcg_gen_not_i32(tcg_ctx, condResult, cpu_CYF); + tcg_gen_not_i32(tcg_ctx, condResult, tcg_ctx->cpu_CYF); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case NV_COND: - tcg_gen_not_i32(tcg_ctx, condResult, cpu_OVF); + tcg_gen_not_i32(tcg_ctx, condResult, tcg_ctx->cpu_OVF); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case NZ_COND: - tcg_gen_not_i32(tcg_ctx, condResult, cpu_ZF); + tcg_gen_not_i32(tcg_ctx, condResult, tcg_ctx->cpu_ZF); tcg_gen_andi_i32(tcg_ctx, condResult, condResult, 0x1); break; case SA_COND: - tcg_gen_mov_i32(tcg_ctx, condResult, cpu_SATF); + tcg_gen_mov_i32(tcg_ctx, condResult, tcg_ctx->cpu_SATF); break; case T_COND: tcg_gen_movi_i32(tcg_ctx, condResult, 0x1); break; case V_COND: - tcg_gen_mov_i32(tcg_ctx, condResult, cpu_OVF); + tcg_gen_mov_i32(tcg_ctx, condResult, tcg_ctx->cpu_OVF); break; case Z_COND: - tcg_gen_mov_i32(tcg_ctx, condResult, cpu_ZF); + tcg_gen_mov_i32(tcg_ctx, condResult, tcg_ctx->cpu_ZF); break; } @@ -456,27 +545,27 @@ static void gen_flags_on_add(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1) // [CYF : SF] = [tmp : t0] + [tmp : t1] // While CYF is 0 or 1, SF bit 15 contains sign, so it // must be shifted 31 bits to the right later. - tcg_gen_add2_i32(tcg_ctx, cpu_SF, cpu_CYF, t0, tmp, t1, tmp); - tcg_gen_mov_i32(tcg_ctx, cpu_ZF, cpu_SF); + tcg_gen_add2_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_ctx->cpu_CYF, t0, tmp, t1, tmp); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_SF); - tcg_gen_xor_i32(tcg_ctx, cpu_OVF, cpu_SF, t0); + tcg_gen_xor_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_SF, t0); tcg_gen_xor_i32(tcg_ctx, tmp, t0, t1); - tcg_gen_andc_i32(tcg_ctx, cpu_OVF, cpu_OVF, tmp); + tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, tmp); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, cpu_SF, 0x1f); - tcg_gen_shri_i32(tcg_ctx, cpu_OVF, cpu_OVF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_ctx->cpu_SF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, 0x1f); tcg_temp_free_i32(tcg_ctx, tmp); cont = gen_new_label(tcg_ctx); end = gen_new_label(tcg_ctx); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x1); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, 0x0, cont); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x0); gen_set_label(tcg_ctx, end); } @@ -489,41 +578,41 @@ static void gen_satadd_CC(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1, TCGv_i3 TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, tmp, 0); - tcg_gen_add2_i32(tcg_ctx, cpu_SF, cpu_CYF, t0, tmp, t1, tmp); - tcg_gen_mov_i32(tcg_ctx, cpu_ZF, cpu_SF); - tcg_gen_xor_i32(tcg_ctx, cpu_OVF, cpu_SF, t0); + tcg_gen_add2_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_ctx->cpu_CYF, t0, tmp, t1, tmp); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_SF); + tcg_gen_xor_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_SF, t0); tcg_gen_xor_i32(tcg_ctx, tmp, t0, t1); - tcg_gen_andc_i32(tcg_ctx, cpu_OVF, cpu_OVF, tmp); + tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, tmp); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, result, 0x1f); - tcg_gen_shri_i32(tcg_ctx, cpu_OVF, cpu_OVF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, result, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, 0x1f); tcg_temp_free_i32(tcg_ctx, tmp); cont = gen_new_label(tcg_ctx); end = gen_new_label(tcg_ctx); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x1); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, 0x0, cont); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x0); gen_set_label(tcg_ctx, end); } static void gen_flags_on_sub(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1) { - tcg_gen_sub_tl(tcg_ctx, cpu_SF, t0, t1); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_GTU, cpu_CYF, t1, t0); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, t0, t1); - tcg_gen_xor_i32(tcg_ctx, cpu_OVF, cpu_SF, t0); + tcg_gen_sub_tl(tcg_ctx, tcg_ctx->cpu_SF, t0, t1); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_GTU, tcg_ctx->cpu_CYF, t1, t0); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, t0, t1); + tcg_gen_xor_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_SF, t0); TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_xor_i32(tcg_ctx, tmp, t0, t1); - tcg_gen_and_i32(tcg_ctx, cpu_OVF, cpu_OVF, tmp); + tcg_gen_and_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, tmp); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, cpu_SF, 0x1f); - tcg_gen_shri_i32(tcg_ctx, cpu_OVF, cpu_OVF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_ctx->cpu_SF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, 0x1f); tcg_temp_free_i32(tcg_ctx, tmp); } @@ -533,49 +622,49 @@ static void gen_satsub_CC(TCGContext *tcg_ctx, TCGv_i32 t0, TCGv_i32 t1, TCGv_i3 TCGLabel *end; TCGv_i32 tmp; - tcg_gen_sub_tl(tcg_ctx, cpu_SF, t0, t1); + tcg_gen_sub_tl(tcg_ctx, tcg_ctx->cpu_SF, t0, t1); - tcg_gen_mov_i32(tcg_ctx, cpu_ZF, cpu_SF); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_GTU, cpu_CYF, t1, t0); - tcg_gen_xor_i32(tcg_ctx, cpu_OVF, cpu_SF, t0); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_SF); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_GTU, tcg_ctx->cpu_CYF, t1, t0); + tcg_gen_xor_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_SF, t0); tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_xor_i32(tcg_ctx, tmp, t0, t1); - tcg_gen_and_i32(tcg_ctx, cpu_OVF, cpu_OVF, tmp); + tcg_gen_and_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, tmp); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, result, 0x1f); - tcg_gen_shri_i32(tcg_ctx, cpu_OVF, cpu_OVF, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, result, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, 0x1f); tcg_temp_free_i32(tcg_ctx, tmp); cont = gen_new_label(tcg_ctx); end = gen_new_label(tcg_ctx); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x1); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, 0x0, cont); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x0); gen_set_label(tcg_ctx, end); } -static void gen_logic_CC(TCGContext *tcg_ctx, TCGv_i32 result){ +static void gen_logic_CC(TCGContext *tcg_ctx, TCGv_i32 result) { TCGLabel *cont; TCGLabel *end; - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, result, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, result, 0x1f); cont = gen_new_label(tcg_ctx); end = gen_new_label(tcg_ctx); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, result, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_ZF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ZF, 0x0); gen_set_label(tcg_ctx, end); } @@ -657,9 +746,9 @@ static void gen_store(DisasContext *ctx, int memop, int rs1, int rs2, // clear possible mutex TCGLabel *l = gen_new_label(tcg_ctx); - tcg_gen_brcond_i32(tcg_ctx, TCG_COND_NE, t0, cpu_LLAddress, l); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_LLbit, 0x1, l); - tcg_gen_movi_i32(tcg_ctx, cpu_LLbit, 0); + tcg_gen_brcond_i32(tcg_ctx, TCG_COND_NE, t0, tcg_ctx->cpu_LLAddress, l); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_LLbit, 0x1, l); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_LLbit, 0); gen_set_label(tcg_ctx, l); tcg_temp_free(tcg_ctx, t0); @@ -679,8 +768,7 @@ static void gen_mutual_exclusion(DisasContext *ctx, int rs3, int rs1, int operat Since we do not implement multicore CPU emulation, this implementation should be OK. */ TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - if (operation == operation_LDL_W) - { + if (operation == operation_LDL_W) { TCGv adr = tcg_temp_new(tcg_ctx); TCGv dat = tcg_temp_new(tcg_ctx); @@ -691,22 +779,21 @@ static void gen_mutual_exclusion(DisasContext *ctx, int rs3, int rs1, int operat tcg_temp_free(tcg_ctx, adr); tcg_temp_free(tcg_ctx, dat); - tcg_gen_movi_i32(tcg_ctx, cpu_LLbit, 1); - tcg_gen_mov_i32(tcg_ctx, cpu_LLAddress, adr); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_LLbit, 1); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_LLAddress, adr); } - else if (operation == operation_STC_W) - { + else if (operation == operation_STC_W) { TCGv adr = tcg_temp_local_new(tcg_ctx); TCGv dat = tcg_temp_local_new(tcg_ctx); TCGv token = tcg_temp_local_new(tcg_ctx); TCGLabel *l_fail = gen_new_label(tcg_ctx); TCGLabel *l_ok = gen_new_label(tcg_ctx); - tcg_gen_mov_i32(tcg_ctx, token, cpu_LLbit); + tcg_gen_mov_i32(tcg_ctx, token, tcg_ctx->cpu_LLbit); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, token, 0x1, l_fail); gen_get_gpr(tcg_ctx, adr, rs1); gen_get_gpr(tcg_ctx, dat, rs3); - tcg_gen_brcond_i32(tcg_ctx, TCG_COND_NE, adr, cpu_LLAddress, l_fail); + tcg_gen_brcond_i32(tcg_ctx, TCG_COND_NE, adr, tcg_ctx->cpu_LLAddress, l_fail); tcg_gen_qemu_st_tl(tcg_ctx, dat, adr, MEM_IDX, MO_TESL); tcg_gen_movi_i32(tcg_ctx, dat, 1); tcg_gen_br(tcg_ctx, l_ok); @@ -716,15 +803,14 @@ static void gen_mutual_exclusion(DisasContext *ctx, int rs3, int rs1, int operat gen_set_label(tcg_ctx, l_ok); gen_set_gpr(tcg_ctx, rs3, dat); - tcg_gen_movi_tl(tcg_ctx, cpu_LLbit, 0); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_LLbit, 0); tcg_temp_free(tcg_ctx, adr); tcg_temp_free(tcg_ctx, dat); tcg_temp_free(tcg_ctx, token); } - else if (operation == operation_CLL) - { - tcg_gen_movi_i32(tcg_ctx, cpu_LLbit, 0); + else if (operation == operation_CLL) { + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_LLbit, 0); } else printf("ERROR gen_mutual_exclusion \n"); @@ -749,13 +835,13 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) TCGv tcg_r3 = tcg_temp_new(tcg_ctx); TCGv tcg_temp = tcg_temp_new(tcg_ctx); - switch(operation){ + switch (operation) { case OPC_RH850_MUL_reg1_reg2_reg3: int_rs3 = extract32(ctx->opcode, 27, 5); gen_get_gpr(tcg_ctx, tcg_r3,int_rs3); tcg_gen_muls2_i32(tcg_ctx, r2, tcg_r3, r1, r2); - if(rs2!=int_rs3){ + if (rs2!=int_rs3) { gen_set_gpr(tcg_ctx, rs2, r2); } gen_set_gpr(tcg_ctx, int_rs3,tcg_r3); @@ -769,7 +855,7 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) imm_32 = imm | (imm_32 << 5); // sign extension - if((imm_32 & 0x100) == 0x100){ + if ((imm_32 & 0x100) == 0x100) { imm_32 = imm_32 | (0x7f << 9); } tcg_gen_movi_tl(tcg_ctx, tcg_imm32, imm_32); @@ -777,7 +863,7 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_muls2_i32(tcg_ctx, r2, tcg_r3, tcg_imm32, r2); - if(rs2!=int_rs3){ + if (rs2!=int_rs3) { gen_set_gpr(tcg_ctx, rs2, r2); } gen_set_gpr(tcg_ctx, int_rs3, tcg_r3); @@ -796,7 +882,7 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) case OPC_RH850_MULH_imm5_reg2: - if ((imm & 0x10) == 0x10){ + if ((imm & 0x10) == 0x10) { imm = imm | (0x7 << 5); } tcg_gen_andi_tl(tcg_ctx, r2, r2,0x0000FFFF); @@ -829,7 +915,7 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_mulu2_i32(tcg_ctx, r2, tcg_r3, r2, r1); - if(rs2!=int_rs3){ + if (rs2!=int_rs3) { gen_set_gpr(tcg_ctx, rs2, r2); } gen_set_gpr(tcg_ctx, int_rs3,tcg_r3); @@ -848,7 +934,7 @@ static void gen_multiply(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_mulu2_i32(tcg_ctx, r2, tcg_r3, tcg_imm32, r2); - if(rs2!=int_rs3){ + if (rs2!=int_rs3) { gen_set_gpr(tcg_ctx, rs2, r2); } gen_set_gpr(tcg_ctx, int_rs3,tcg_r3); @@ -888,7 +974,7 @@ static void gen_mul_accumulate(DisasContext *ctx, int rs1, int rs2, int operatio gen_get_gpr(tcg_ctx, addLo, rs3); gen_get_gpr(tcg_ctx, addHi, rs3+1); - switch(operation){ + switch (operation) { case OPC_RH850_MAC_reg1_reg2_reg3_reg4: tcg_gen_muls2_i32(tcg_ctx, resLo, resHi, r1, r2); @@ -935,7 +1021,7 @@ static void gen_arithmetic(DisasContext *ctx, int rs1, int rs2, int operation) TCGv tcg_r3 = tcg_temp_new(tcg_ctx); TCGv tcg_result = tcg_temp_new(tcg_ctx); - switch(operation) { + switch (operation) { case OPC_RH850_ADD_reg1_reg2: { @@ -947,7 +1033,7 @@ static void gen_arithmetic(DisasContext *ctx, int rs1, int rs2, int operation) } break; case OPC_RH850_ADD_imm5_reg2: - if((imm & 0x10) == 0x10){ + if ((imm & 0x10) == 0x10) { imm = imm | (0x7 << 5); } tcg_gen_movi_i32(tcg_ctx, tcg_imm, imm); @@ -976,7 +1062,7 @@ static void gen_arithmetic(DisasContext *ctx, int rs1, int rs2, int operation) case OPC_RH850_CMP_imm5_reg2: { - if ((imm & 0x10) == 0x10){ + if ((imm & 0x10) == 0x10) { imm = imm | (0x7 << 5); } tcg_gen_movi_tl(tcg_ctx, tcg_imm, imm); @@ -992,7 +1078,7 @@ static void gen_arithmetic(DisasContext *ctx, int rs1, int rs2, int operation) break; case OPC_RH850_MOV_imm5_reg2: - if ((imm & 0x10) == 0x10){ + if ((imm & 0x10) == 0x10) { imm = imm | (0x7 << 5); } tcg_gen_movi_tl(tcg_ctx, r2, imm); @@ -1063,7 +1149,7 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) int int_rs3; int int_cond; - switch(operation){ + switch (operation) { case OPC_RH850_ADF_cccc_reg1_reg2_reg3:{ @@ -1079,7 +1165,7 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) int_rs3 = extract32(ctx->opcode, 27, 5); int_cond = extract32(ctx->opcode, 17, 4); - if(int_cond == 0xd){ + if (int_cond == 0xd) { //throw exception/warning for inappropriate condition (SA) break; } @@ -1095,8 +1181,8 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, condResult, 0x1, cont); // calc and store CY and OV flags to be used to obtain final values gen_flags_on_add(tcg_ctx, r2_local, addIfCond); - tcg_gen_mov_tl(tcg_ctx, carry, cpu_CYF); - tcg_gen_mov_tl(tcg_ctx, overflow, cpu_OVF); + tcg_gen_mov_tl(tcg_ctx, carry, tcg_ctx->cpu_CYF); + tcg_gen_mov_tl(tcg_ctx, overflow, tcg_ctx->cpu_OVF); // on cond true, add 1 tcg_gen_add_tl(tcg_ctx, r2_local, r2_local, addIfCond); @@ -1105,8 +1191,8 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) gen_set_gpr(tcg_ctx, int_rs3, r3_local); gen_flags_on_add(tcg_ctx, r1_local, r2_local); - tcg_gen_or_tl(tcg_ctx, cpu_CYF, cpu_CYF, carry); - tcg_gen_or_tl(tcg_ctx, cpu_OVF, cpu_OVF, overflow); + tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_CYF, tcg_ctx->cpu_CYF, carry); + tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, overflow); tcg_temp_free(tcg_ctx, condResult); tcg_temp_free_i32(tcg_ctx, r1_local); @@ -1120,7 +1206,7 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) int_rs3 = extract32(ctx->opcode, 27, 5); int_cond = extract32(ctx->opcode, 17, 4); - if(int_cond == 0xd){ + if (int_cond == 0xd) { //throw exception/warning for inappropriate condition (SA) break; } @@ -1141,17 +1227,17 @@ static void gen_cond_arith(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_mov_tl(tcg_ctx, tmpReg, condResult); gen_flags_on_sub(tcg_ctx, r3_local, r1); - tcg_gen_mov_tl(tcg_ctx, carry, cpu_CYF); - tcg_gen_mov_tl(tcg_ctx, overflow, cpu_OVF); + tcg_gen_mov_tl(tcg_ctx, carry, tcg_ctx->cpu_CYF); + tcg_gen_mov_tl(tcg_ctx, overflow, tcg_ctx->cpu_OVF); tcg_gen_sub_tl(tcg_ctx, r3_local, r3_local, r1); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tmpReg, 0x1, cont); tcg_gen_movi_i32(tcg_ctx, tmpReg, 0x1); gen_flags_on_sub(tcg_ctx, r3_local, tmpReg); tcg_gen_subi_tl(tcg_ctx, r3_local, r3_local, 1); - tcg_gen_or_tl(tcg_ctx, cpu_CYF, cpu_CYF, carry); + tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_CYF, tcg_ctx->cpu_CYF, carry); // overflow twice means no overflow - tcg_gen_xor_tl(tcg_ctx, cpu_OVF, cpu_OVF, overflow); + tcg_gen_xor_tl(tcg_ctx, tcg_ctx->cpu_OVF, tcg_ctx->cpu_OVF, overflow); gen_set_label(tcg_ctx, cont); @@ -1188,7 +1274,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) TCGLabel *setMax; TCGLabel *dontChange; - switch(operation){ + switch (operation) { case OPC_RH850_SATADD_reg1_reg2: { @@ -1216,7 +1302,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, max, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1224,7 +1310,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1259,7 +1345,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) cont = gen_new_label(tcg_ctx); cont2 = gen_new_label(tcg_ctx); - if ((imm & 0x10) == 0x10){ + if ((imm & 0x10) == 0x10) { imm = imm | (0x7 << 5); } @@ -1273,7 +1359,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, max, imm_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1281,7 +1367,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, imm_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1325,7 +1411,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, max, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); //if (r2 > MAX-r1) tcg_gen_mov_i32(tcg_ctx, result, max); //return MAX; - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1333,7 +1419,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); //if (r2 < MIN-r1) tcg_gen_mov_i32(tcg_ctx, result, min); //return MIN; - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1396,7 +1482,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); gen_set_label(tcg_ctx, setMax); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1404,7 +1490,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1460,7 +1546,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); gen_set_label(tcg_ctx, setMax); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1468,7 +1554,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1483,7 +1569,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_temp_free(tcg_ctx, max); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); - tcg_temp_free(tcg_ctx, zero); + tcg_temp_free(tcg_ctx, zero); } break; @@ -1526,7 +1612,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, imm_local, check, end); gen_set_label(tcg_ctx, setMax); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1534,7 +1620,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, imm_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1598,7 +1684,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LE, r2_local, check, end); gen_set_label(tcg_ctx, setMax); tcg_gen_mov_i32(tcg_ctx, result, max); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); tcg_gen_br(tcg_ctx, end); //--------------------------------------------------------------------------------- @@ -1606,7 +1692,7 @@ static void gen_sat_op(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_sub_i32(tcg_ctx, check, min, r1_local); tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, r2_local, check, cont2); tcg_gen_mov_i32(tcg_ctx, result, min); - tcg_gen_movi_i32(tcg_ctx, cpu_SATF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SATF, 0x1); gen_set_label(tcg_ctx, cont2); gen_set_label(tcg_ctx, end); @@ -1643,7 +1729,7 @@ static void gen_logical(DisasContext *ctx, int rs1, int rs2, int operation) int imm_32; TCGv tcg_imm = tcg_temp_new(tcg_ctx); - switch(operation){ + switch (operation) { case OPC_RH850_AND_reg1_reg2: tcg_gen_and_tl(tcg_ctx, r2, r2, r1); @@ -1739,7 +1825,7 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera gen_get_gpr(tcg_ctx, tcg_r1, rs1); gen_get_gpr(tcg_ctx, tcg_r2, rs2); - switch(operation) { + switch (operation) { case OPC_RH850_BINS: @@ -1752,7 +1838,7 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera msb = extract32(ctx->opcode, 28, 4); width = extract32(ctx->opcode, 28, 4) - pos + 1; - switch(group){ + switch (group) { case 0: //bins0 pos += 16; break; @@ -1764,14 +1850,14 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera break; } - if(msbcpu_ZF, tcg_r2, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, tcg_r2, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); break; } - for(int i = 0; i < width; i++){ + for(int i = 0; i < width; i++) { mask = mask | (0x1 << i); } @@ -1786,9 +1872,9 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_or_i32(tcg_ctx, tcg_r2, tcg_r2, insert); //placing bits into reg2 gen_set_gpr(tcg_ctx, rs2, tcg_r2); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, tcg_r2, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, tcg_r2, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, tcg_r2, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, tcg_r2, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); break; case OPC_RH850_BSH_reg2_reg3: { @@ -1828,8 +1914,8 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera end = gen_new_label(tcg_ctx); set = gen_new_label(tcg_ctx); tcg_gen_andi_i32(tcg_ctx, temp_local, r3_local, 0x0000ffff); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, temp_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, temp_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); tcg_gen_movi_i32(tcg_ctx, count_local, 0x0); @@ -1838,14 +1924,14 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_andi_i32(tcg_ctx, temp_local, r3_local, 0x0000ff00); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, temp_local, 0x0, set); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, set);//// - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x1); gen_set_label(tcg_ctx, end);//// - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r2_local); tcg_temp_free(tcg_ctx, r3_local); @@ -1872,8 +1958,8 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_mov_i32(tcg_ctx, r2_local, tcg_r2); tcg_gen_mov_i32(tcg_ctx, r3_local, tcg_r3); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r3_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r3_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); tcg_gen_movi_i32(tcg_ctx, count_local, 0x0); @@ -1884,14 +1970,14 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_addi_i32(tcg_ctx, count_local, count_local, 0x1); tcg_gen_shri_i32(tcg_ctx, r3_local, r3_local, 0x8); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, count_local, 0x4, cont);//// - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, set); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x1); gen_set_label(tcg_ctx, end); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r2_local); tcg_temp_free(tcg_ctx, r3_local); @@ -1960,11 +2046,11 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera int_rs3 = extract32(ctx->opcode, 27, 5); gen_set_gpr(tcg_ctx, int_rs3, tcg_r2); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, tcg_r2, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_r2, 0x1f); tcg_gen_andi_i32(tcg_ctx, tcg_temp, tcg_r2, 0x0000ffff); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, tcg_temp, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_CYF, tcg_temp, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, tcg_temp, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_CYF, tcg_temp, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); break; case OPC_RH850_HSW_reg2_reg3: { @@ -1992,8 +2078,8 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_or_tl(tcg_ctx, r3_local, temp2_local, temp_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r3_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r3_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); tcg_gen_movi_i32(tcg_ctx, count_local, 0x0); @@ -2003,14 +2089,14 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, temp3_local, 0x0, set); tcg_gen_andi_i32(tcg_ctx, temp3_local, r3_local, 0xffff0000); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, temp3_local, 0x0, set); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, set);//// - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x1); gen_set_label(tcg_ctx, end);//// - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r2_local); tcg_temp_free(tcg_ctx, r3_local); @@ -2034,16 +2120,16 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_rotl_tl(tcg_ctx, tcg_r3, tcg_r2, tcg_imm); gen_set_gpr(tcg_ctx, int_rs3, tcg_r3); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, tcg_r3, 0x1); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, tcg_r3, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, tcg_r3, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, tcg_r3, 0x1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, tcg_r3, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_r3, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_gen_mov_i32(tcg_ctx, r3_local, tcg_r3); tcg_gen_mov_i32(tcg_ctx, imm_local, tcg_imm); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_imm, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, cont); tcg_temp_free(tcg_ctx, r3_local); @@ -2061,16 +2147,16 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_rotl_tl(tcg_ctx, tcg_r3, tcg_r2, tcg_r1); gen_set_gpr(tcg_ctx, int_rs3, tcg_r3); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, tcg_r3, 0x1); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, tcg_r3, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, tcg_r3, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, tcg_r3, 0x1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, tcg_r3, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, tcg_r3, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_gen_mov_i32(tcg_ctx, r3_local, tcg_r3); tcg_gen_mov_i32(tcg_ctx, r1_local, tcg_r1); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_r1, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, cont); tcg_temp_free(tcg_ctx, r3_local); @@ -2089,7 +2175,7 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_mov_i32(tcg_ctx, r2_local, tcg_r2); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, r1_local, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); @@ -2097,15 +2183,15 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, r1_local, r1_local, 0x1); //shift by r1-1 tcg_gen_sar_i32(tcg_ctx, r2_local, r2_local, r1_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r2_local, 0x1); //LSB here is the last bit to be shifted + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1); //LSB here is the last bit to be shifted tcg_gen_sari_i32(tcg_ctx, r2_local, r2_local, 0x1); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r2_local); tcg_temp_free(tcg_ctx, r1_local); @@ -2124,22 +2210,22 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_mov_i32(tcg_ctx, r2_local, tcg_r2); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, r1_local, 0x0, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); tcg_gen_subi_i32(tcg_ctx, r1_local, r1_local, 0x1); //shift by one less tcg_gen_sar_i32(tcg_ctx, r2_local, r2_local, r1_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r2_local, 0x1); //LSB here is the last bit to be shifted + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1); //LSB here is the last bit to be shifted tcg_gen_sari_i32(tcg_ctx, r2_local, r2_local, 0x1); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r2_local); tcg_temp_free(tcg_ctx, r1_local); @@ -2161,7 +2247,7 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera gen_get_gpr(tcg_ctx, r3_local, int_rs3); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, r1_local, 0x0, cont); //is non-shift? - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_mov_i32(tcg_ctx, r3_local, r2_local); tcg_gen_br(tcg_ctx, end); @@ -2170,15 +2256,15 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, r1_local, r1_local, 0x1); //shift by one less tcg_gen_sar_i32(tcg_ctx, r3_local, r2_local, r1_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r3_local, 0x1); //LSB here is the last bit to be shifted + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r3_local, 0x1); //LSB here is the last bit to be shifted tcg_gen_sari_i32(tcg_ctx, r3_local, r3_local, 0x1); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r3_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r3_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r3_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2253,19 +2339,19 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, temp_local, r1_local, 0x1); // shifting for [r1]-1 tcg_gen_shl_tl(tcg_ctx, r2_local, r2_local, temp_local); - tcg_gen_shri_i32(tcg_ctx, cpu_CYF, r2_local, 0x1f); // checking the last bit to shift + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1f); // checking the last bit to shift tcg_gen_shli_i32(tcg_ctx, r2_local, r2_local, 0x1); // shifting for that remaining 1 gen_set_gpr(tcg_ctx, rs2, r2_local); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, end); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2291,18 +2377,18 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, temp_local, r1_local, 0x1); tcg_gen_shl_tl(tcg_ctx, r2_local, r2_local, temp_local); - tcg_gen_shri_i32(tcg_ctx, cpu_CYF, r2_local, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1f); tcg_gen_shli_tl(tcg_ctx, r2_local, r2_local, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2332,19 +2418,19 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, temp_local, r1_local, 0x1); tcg_gen_shl_tl(tcg_ctx, r3_local, r2_local, temp_local); - tcg_gen_shri_i32(tcg_ctx, cpu_CYF, r3_local, 0x1f); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_CYF, r3_local, 0x1f); tcg_gen_shli_tl(tcg_ctx, r3_local, r3_local, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); tcg_gen_mov_i32(tcg_ctx, r3_local, r2_local); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r3_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r3_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2371,19 +2457,19 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_shr_tl(tcg_ctx, r2_local, r2_local, temp_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r2_local, 0x1); // checking the last bit to shift (LSB) + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1); // checking the last bit to shift (LSB) tcg_gen_shri_i32(tcg_ctx, r2_local, r2_local, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2410,19 +2496,19 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, temp_local, r1_local, 0x1); // shifting for [r1]-1 tcg_gen_shr_tl(tcg_ctx, r2_local, r2_local, temp_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r2_local, 0x1); // checking the last bit to shift (LSB) + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r2_local, 0x1); // checking the last bit to shift (LSB) tcg_gen_shri_i32(tcg_ctx, r2_local, r2_local, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r2_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r2_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2452,20 +2538,20 @@ static void gen_data_manipulation(DisasContext *ctx, int rs1, int rs2, int opera tcg_gen_subi_i32(tcg_ctx, temp_local, r1_local, 0x1); // shifting for [r1]-1 tcg_gen_shr_tl(tcg_ctx, r3_local, r2_local, temp_local); - tcg_gen_andi_i32(tcg_ctx, cpu_CYF, r3_local, 0x1); // checking the last bit to shift (LSB) + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->cpu_CYF, r3_local, 0x1); // checking the last bit to shift (LSB) tcg_gen_shri_i32(tcg_ctx, r3_local, r3_local, 0x1); tcg_gen_br(tcg_ctx, end); gen_set_label(tcg_ctx, cont); - tcg_gen_movi_i32(tcg_ctx, cpu_CYF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CYF, 0x0); tcg_gen_mov_i32(tcg_ctx, r3_local, r2_local); gen_set_label(tcg_ctx, end); gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r3_local, 0x0); - tcg_gen_shri_i32(tcg_ctx, cpu_SF, r3_local, 0x1f); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r3_local, 0x0); + tcg_gen_shri_i32(tcg_ctx, tcg_ctx->cpu_SF, r3_local, 0x1f); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); tcg_temp_free(tcg_ctx, r1_local); tcg_temp_free(tcg_ctx, r2_local); @@ -2524,9 +2610,8 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) TCGLabel *found; TCGLabel *loop; - switch(operation){ + switch (operation) { case OPC_RH850_SCH0L_reg2_reg3: { - TCGv foundFlag = tcg_temp_local_new(tcg_ctx); TCGv r2_local = tcg_temp_local_new(tcg_ctx); TCGv r3_local = tcg_temp_local_new(tcg_ctx); @@ -2562,10 +2647,10 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) gen_set_gpr(tcg_ctx, int_rs3, result); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, foundFlag, 0x1); //setting Z if not found - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_SF, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_CYF, r2_local, 0xfffffffe); //setting CY if found at the end + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, foundFlag, 0x1); //setting Z if not found + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_CYF, r2_local, 0xfffffffe); //setting CY if found at the end tcg_temp_free(tcg_ctx, foundFlag); tcg_temp_free(tcg_ctx, r2_local); @@ -2576,7 +2661,6 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) } break; case OPC_RH850_SCH0R_reg2_reg3: { - TCGv foundFlag = tcg_temp_local_new(tcg_ctx); TCGv r2_local = tcg_temp_local_new(tcg_ctx); TCGv r3_local = tcg_temp_local_new(tcg_ctx); @@ -2612,10 +2696,10 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) gen_set_gpr(tcg_ctx, int_rs3, result); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, foundFlag, 0x1); //setting Z if not found - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_SF, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_CYF, r2_local, 0x7fffffff); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, foundFlag, 0x1); //setting Z if not found + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_CYF, r2_local, 0x7fffffff); tcg_temp_free(tcg_ctx, foundFlag); tcg_temp_free(tcg_ctx, r2_local); @@ -2626,7 +2710,6 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) } break; case OPC_RH850_SCH1L_reg2_reg3: { - TCGv foundFlag = tcg_temp_local_new(tcg_ctx); TCGv r2_local = tcg_temp_local_new(tcg_ctx); TCGv r3_local = tcg_temp_local_new(tcg_ctx); @@ -2662,10 +2745,10 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) gen_set_gpr(tcg_ctx, int_rs3, result); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, foundFlag, 0x1); //setting Z if not found - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_SF, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_CYF, r2_local, 0x1); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, foundFlag, 0x1); //setting Z if not found + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_CYF, r2_local, 0x1); tcg_temp_free(tcg_ctx, foundFlag); tcg_temp_free(tcg_ctx, r2_local); @@ -2676,7 +2759,6 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) } break; case OPC_RH850_SCH1R_reg2_reg3: { - TCGv foundFlag = tcg_temp_local_new(tcg_ctx); TCGv r2_local = tcg_temp_local_new(tcg_ctx); TCGv r3_local = tcg_temp_local_new(tcg_ctx); @@ -2713,10 +2795,10 @@ static void gen_bit_search(DisasContext *ctx, int rs2, int operation) gen_set_gpr(tcg_ctx, int_rs3, result); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, foundFlag, 0x1); //setting Z if not found - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x0); - tcg_gen_movi_i32(tcg_ctx, cpu_SF, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_CYF, r2_local, 0x80000000); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, foundFlag, 0x1); //setting Z if not found + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_SF, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_CYF, r2_local, 0x80000000); tcg_temp_free(tcg_ctx, foundFlag); tcg_temp_free(tcg_ctx, r2_local); @@ -2745,10 +2827,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) TCGv tcg_r3 = tcg_temp_new(tcg_ctx); - switch(operation){ - + switch (operation) { case OPC_RH850_DIV_reg1_reg2_reg3:{ - TCGLabel *cont; TCGLabel *end; TCGLabel *fin; @@ -2770,8 +2850,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) end = gen_new_label(tcg_ctx); fin = gen_new_label(tcg_ctx); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, r1_local, 0x0); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, cont); //if r1=0 jump to end + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, r1_local, 0x0); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, cont); //if r1=0 jump to end tcg_gen_movi_i32(tcg_ctx, r2_local, 0x80000000); tcg_gen_br(tcg_ctx, fin); @@ -2782,14 +2862,14 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, overflowed2, r1_local, 0xffffffff); tcg_gen_and_i32(tcg_ctx, overflowed, overflowed, overflowed2); //if both - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, overflowed, 0x1); //are 1 - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, end); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, overflowed, 0x1); //are 1 + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, end); tcg_gen_movi_i32(tcg_ctx, r2_local, 0x80000000); //DO THIS tcg_gen_movi_i32(tcg_ctx, r3_local, 0x0000); gen_set_gpr(tcg_ctx, rs2, r2_local); //write zeros if undefined gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, end); @@ -2797,15 +2877,15 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_rem_i32(tcg_ctx, r3_local, r2_local, r1_local); tcg_gen_div_i32(tcg_ctx, r2_local, r2_local, r1_local); - if(rs2==int_rs3){ + if (rs2==int_rs3) { gen_set_gpr(tcg_ctx, rs2, r3_local); } else { gen_set_gpr(tcg_ctx, rs2, r2_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); } - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); gen_set_label(tcg_ctx, fin); @@ -2817,7 +2897,6 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) } break; case OPC_RH850_DIVH_reg1_reg2:{ - TCGLabel *cont; TCGLabel *end; TCGLabel *fin; @@ -2837,8 +2916,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) end = gen_new_label(tcg_ctx); fin = gen_new_label(tcg_ctx); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, r1_local, 0x0); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, cont); //if r1=0 jump to cont + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, r1_local, 0x0); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, cont); //if r1=0 jump to cont tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, cont); @@ -2847,13 +2926,13 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, overflowed2, r1_local, 0xffffffff); tcg_gen_and_i32(tcg_ctx, overflowed, overflowed, overflowed2); //if both - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, overflowed, 0x1); //are 1 - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, end); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, overflowed, 0x1); //are 1 + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, end); tcg_gen_movi_i32(tcg_ctx, r2_local, 0x80000000); //DO THIS - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x1); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, end); @@ -2861,8 +2940,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_div_i32(tcg_ctx, r2_local, r2_local, r1_local); gen_set_gpr(tcg_ctx, rs2, r2_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); gen_set_label(tcg_ctx, fin); @@ -2873,8 +2952,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) } break; case OPC_RH850_DIVH_reg1_reg2_reg3: { - // 0x80000000/0xffffffff=0x80000000; cpu_OVF=1, cpu_Z=1? - // reg2/0x0000=undefined; cpu_OVF=1 + // 0x80000000/0xffffffff=0x80000000; tcg_ctx->cpu_OVF=1, tcg_ctx->cpu_Z=1? + // reg2/0x0000=undefined; tcg_ctx->cpu_OVF=1 // if reg2==reg3; reg2=remainder TCGLabel *cont; @@ -2900,25 +2979,25 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) end = gen_new_label(tcg_ctx); fin = gen_new_label(tcg_ctx); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, r1_local, 0x0); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, cont); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, r1_local, 0x0); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, cont); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, cont); ///// tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, overflowed, r2_local, 0x80000000); tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, overflowed2, r1_local, 0xffffffff); - tcg_gen_and_i32(tcg_ctx, overflowed, overflowed, overflowed2); // if result is 1, cpu_OVF = 1 + tcg_gen_and_i32(tcg_ctx, overflowed, overflowed, overflowed2); // if result is 1, tcg_ctx->cpu_OVF = 1 - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, overflowed, 0x1); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, end); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, overflowed, 0x1); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, end); tcg_gen_movi_i32(tcg_ctx, r2_local, 0x80000000); tcg_gen_movi_i32(tcg_ctx, r3_local, 0x0000); - tcg_gen_movi_i32(tcg_ctx, cpu_OVF, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_OVF, 0x1); gen_set_gpr(tcg_ctx, rs2, r2_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, end); ///// @@ -2926,15 +3005,15 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_rem_i32(tcg_ctx, r3_local, r2_local, r1_local); tcg_gen_div_i32(tcg_ctx, r2_local, r2_local, r1_local); - if(rs2==int_rs3){ + if (rs2==int_rs3) { gen_set_gpr(tcg_ctx, rs2, r3_local); } else { gen_set_gpr(tcg_ctx, rs2, r2_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); } - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); gen_set_label(tcg_ctx, fin); ///// @@ -2946,7 +3025,6 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) } break; case OPC_RH850_DIVHU_reg1_reg2_reg3:{ - TCGLabel *cont; TCGLabel *fin; @@ -2967,23 +3045,23 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) cont = gen_new_label(tcg_ctx); fin = gen_new_label(tcg_ctx); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, r1_local, 0x0); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, cont); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, r1_local, 0x0); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, cont); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, cont); ///// tcg_gen_remu_i32(tcg_ctx, r3_local, r2_local, r1_local); tcg_gen_divu_i32(tcg_ctx, r2_local, r2_local, r1_local); - if(rs2==int_rs3){ + if (rs2==int_rs3) { gen_set_gpr(tcg_ctx, rs2, r3_local); } else { gen_set_gpr(tcg_ctx, rs2, r2_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); } - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, cpu_SF, r2_local, 0x0); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_LT, tcg_ctx->cpu_SF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); gen_set_label(tcg_ctx, fin); ///// @@ -2994,8 +3072,7 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) break; case OPC_RH850_DIVU_reg1_reg2_reg3:{ - - // reg2/0x0000=undefined; cpu_OVF=1 + // reg2/0x0000=undefined; tcg_ctx->cpu_OVF=1 // if reg2==reg3; reg2=remainder TCGLabel *cont; @@ -3016,8 +3093,8 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) cont = gen_new_label(tcg_ctx); fin = gen_new_label(tcg_ctx); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_OVF, r1_local, 0x0); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_OVF, 0x1, cont); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_OVF, r1_local, 0x0); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_OVF, 0x1, cont); tcg_gen_br(tcg_ctx, fin); gen_set_label(tcg_ctx, cont); ///// @@ -3025,16 +3102,16 @@ static void gen_divide(DisasContext *ctx, int rs1, int rs2, int operation) tcg_gen_remu_i32(tcg_ctx, r3_local, r2_local, r1_local); tcg_gen_divu_i32(tcg_ctx, r2_local, r2_local, r1_local); - if(rs2==int_rs3){ + if (rs2==int_rs3) { gen_set_gpr(tcg_ctx, rs2, r3_local); } else { gen_set_gpr(tcg_ctx, rs2, r2_local); gen_set_gpr(tcg_ctx, int_rs3, r3_local); } - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, r2_local, 0x0); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, r2_local, 0x0); tcg_gen_andi_i32(tcg_ctx, check, r2_local, 0x80000000); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_SF, check, 0x80000000); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_SF, check, 0x80000000); gen_set_label(tcg_ctx, fin); ///// @@ -3081,8 +3158,7 @@ static void gen_jmp(DisasContext *ctx, int rs1, uint32_t disp32, int operation) TCGv link_addr = tcg_temp_new(tcg_ctx); TCGv dest_addr = tcg_temp_new(tcg_ctx); - switch (operation) - { + switch (operation) { /** * Jump with immediate displacement. * PC and disp32 are fixed and won't change at @@ -3110,7 +3186,7 @@ static void gen_jmp(DisasContext *ctx, int rs1, uint32_t disp32, int operation) gen_set_gpr(tcg_ctx, rs2, link_addr); /* Update pc */ - tcg_gen_movi_i32(tcg_ctx, cpu_pc, ctx->pc + disp32); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_pc, ctx->pc + disp32); /* Goto corresponding TB (indirect jump). */ ctx->base.is_jmp = DISAS_INDIRECT_JUMP; @@ -3148,7 +3224,7 @@ static void gen_jmp(DisasContext *ctx, int rs1, uint32_t disp32, int operation) /* Update pc */ tcg_gen_andi_i32(tcg_ctx, dest_addr, dest_addr, 0xfffffffe); - tcg_gen_mov_i32(tcg_ctx, cpu_pc, dest_addr); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, dest_addr); /* Goto corresponding TB (indirect jump). */ ctx->base.is_jmp = DISAS_INDIRECT_JUMP; @@ -3161,14 +3237,13 @@ static void gen_jmp(DisasContext *ctx, int rs1, uint32_t disp32, int operation) gen_get_gpr(tcg_ctx, dest_addr, rs1); /* Apply displacement if provided. */ - if (disp32 != 0) - { + if (disp32 != 0) { tcg_gen_addi_i32(tcg_ctx, dest_addr, dest_addr, disp32); } /* Align and update PC. */ tcg_gen_andi_i32(tcg_ctx, dest_addr, dest_addr, 0xfffffffe); - tcg_gen_mov_i32(tcg_ctx, cpu_pc, dest_addr); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, dest_addr); /* Indirect jump. */ ctx->base.is_jmp = DISAS_INDIRECT_JUMP; @@ -3226,7 +3301,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat int bit; - switch(operation){ + switch (operation) { case OPC_RH850_SET1_reg2_reg1: gen_get_gpr(tcg_ctx, adr, rs1); @@ -3238,7 +3313,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_shl_i32(tcg_ctx, r2, one, r2); tcg_gen_and_i32(tcg_ctx, test, temp, r2); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, r2); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, r2); tcg_gen_or_i32(tcg_ctx, temp, temp, r2); @@ -3257,7 +3332,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_qemu_ld_i32(tcg_ctx, temp, adr, MEM_IDX, MO_UB); tcg_gen_andi_i32(tcg_ctx, test, temp, (0x1 << bit)); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, (0x1 << bit)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, (0x1 << bit)); tcg_gen_ori_i32(tcg_ctx, temp, temp, (0x1 << bit)); @@ -3275,7 +3350,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_shl_i32(tcg_ctx, r2, one, r2); // r2 = mask tcg_gen_and_i32(tcg_ctx, test, temp, r2); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, r2); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, r2); //test = temp & mask tcg_gen_and_i32(tcg_ctx, test, temp, r2); @@ -3303,7 +3378,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_qemu_ld_i32(tcg_ctx, temp, adr, MEM_IDX, MO_UB); tcg_gen_andi_i32(tcg_ctx, test, temp, (0x1 << bit)); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, (0x1 << bit)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, (0x1 << bit)); tcg_gen_movi_i32(tcg_ctx, r2, (0x1 << bit)); // r2 = mask @@ -3332,7 +3407,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_shl_i32(tcg_ctx, r2, one, r2); tcg_gen_and_i32(tcg_ctx, test, temp, r2); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, r2); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, r2); tcg_gen_not_i32(tcg_ctx, r2, r2); tcg_gen_and_i32(tcg_ctx, temp, temp, r2); @@ -3353,7 +3428,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_movi_i32(tcg_ctx, test, (0x1 << bit)); tcg_gen_andi_i32(tcg_ctx, test, temp, (0x1 << bit)); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, (0x1 << bit)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, (0x1 << bit)); tcg_gen_movi_i32(tcg_ctx, test, (0x1 << bit)); tcg_gen_not_i32(tcg_ctx, test, test); @@ -3373,7 +3448,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_shl_i32(tcg_ctx, r2, one, r2); tcg_gen_and_i32(tcg_ctx, test, temp, r2); - tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, r2); + tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, r2); break; case OPC_RH850_TST1_bit3_disp16_reg1: @@ -3389,7 +3464,7 @@ static void gen_bit_manipulation(DisasContext *ctx, int rs1, int rs2, int operat tcg_gen_movi_i32(tcg_ctx, test, (0x1 << bit)); tcg_gen_andi_i32(tcg_ctx, test, temp, (0x1 << bit)); - tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, cpu_ZF, test, (0x1 << bit)); + tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_ZF, test, (0x1 << bit)); break; } @@ -3415,7 +3490,7 @@ static void gen_update_ispr(DisasContext *ctx, CPURH850State *env) TCGv ispr = tcg_temp_local_new_i32(tcg_ctx); /* Move ISPR value into intcfg. */ - tcg_gen_mov_i32(tcg_ctx, temp, cpu_sysRegs[BANK_ID_BASIC_2][INTCFG_IDX2]); + tcg_gen_mov_i32(tcg_ctx, temp, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_2][INTCFG_IDX2]); /* And intcfg with 1. */ tcg_gen_andi_i32(tcg_ctx, temp, temp, 1); @@ -3424,7 +3499,7 @@ static void gen_update_ispr(DisasContext *ctx, CPURH850State *env) tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, temp, 0, do_not_update); /* INTCFG.ICSP = 0, now check EP (EP == 1 -> do not update ISRP) */ - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, cpu_EP, 0, do_not_update); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, tcg_ctx->cpu_EP, 0, do_not_update); /** * Okay, now update ISPR (clear the highest priority bit). @@ -3439,7 +3514,7 @@ static void gen_update_ispr(DisasContext *ctx, CPURH850State *env) gen_set_label(tcg_ctx, loop); /* Load ISPR. */ - tcg_gen_mov_i32(tcg_ctx, ispr, cpu_sysRegs[BANK_ID_BASIC_2][ISPR_IDX2]); + tcg_gen_mov_i32(tcg_ctx, ispr, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_2][ISPR_IDX2]); tcg_gen_and_i32(tcg_ctx, ispr, ispr, temp); tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, ispr, 1, clear_bit); @@ -3453,7 +3528,7 @@ static void gen_update_ispr(DisasContext *ctx, CPURH850State *env) /* Clear bit. */ gen_set_label(tcg_ctx, clear_bit); - tcg_gen_xor_i32(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_2][ISPR_IDX2], cpu_sysRegs[BANK_ID_BASIC_2][ISPR_IDX2], temp); + tcg_gen_xor_i32(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_2][ISPR_IDX2], tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_2][ISPR_IDX2], temp); /* Set label do_not_update here. */ gen_set_label(tcg_ctx, do_not_update); @@ -3474,25 +3549,25 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, int imm; int vector; - switch(operation){ + switch (operation) { case OPC_RH850_CALLT_imm6: { TCGv temp = tcg_temp_new_i32(tcg_ctx); TCGv adr = tcg_temp_new_i32(tcg_ctx); //setting CTPC to PC+2 - tcg_gen_addi_i32(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_0][CTPC_IDX], cpu_pc, 0x2); + tcg_gen_addi_i32(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTPC_IDX], tcg_ctx->cpu_pc, 0x2); //setting CPTSW bits 0:4 - flags_to_tcgv_z_cy_ov_s_sat(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_0][CTPSW_IDX]); + flags_to_tcgv_z_cy_ov_s_sat(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTPSW_IDX]); imm = extract32(ctx->opcode, 0, 6); tcg_gen_movi_i32(tcg_ctx, adr, imm); tcg_gen_shli_i32(tcg_ctx, adr, adr, 0x1); tcg_gen_ext8s_i32(tcg_ctx, adr, adr); - tcg_gen_add_i32(tcg_ctx, adr, cpu_sysRegs[BANK_ID_BASIC_0][CTBP_IDX], adr); + tcg_gen_add_i32(tcg_ctx, adr, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTBP_IDX], adr); tcg_gen_qemu_ld16u(tcg_ctx, temp, adr, 0); - tcg_gen_add_i32(tcg_ctx, cpu_pc, temp, cpu_sysRegs[BANK_ID_BASIC_0][CTBP_IDX]); + tcg_gen_add_i32(tcg_ctx, tcg_ctx->cpu_pc, temp, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTBP_IDX]); ctx->base.is_jmp = DISAS_EXIT_TB; tcg_temp_free(tcg_ctx, temp); @@ -3526,7 +3601,7 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, gen_flags_on_sub(tcg_ctx, local_r2, local_temp); - tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, cpu_ZF, 0x1, storeReg3); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_ZF, 0x1, storeReg3); tcg_gen_qemu_st_tl(tcg_ctx, local_temp, local_adr, MEM_IDX, MO_TESL); tcg_gen_br(tcg_ctx, cont); @@ -3546,8 +3621,8 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, case OPC_RH850_CTRET: { TCGv temp = tcg_temp_new_i32(tcg_ctx); - tcg_gen_mov_i32(tcg_ctx, cpu_pc, cpu_sysRegs[BANK_ID_BASIC_0][CTPC_IDX]); - tcgv_to_flags_z_cy_ov_s_sat(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_0][CTPSW_IDX]); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTPC_IDX]); + tcgv_to_flags_z_cy_ov_s_sat(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][CTPSW_IDX]); ctx->base.is_jmp = DISAS_EXIT_TB; @@ -3555,7 +3630,7 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, } break; case OPC_RH850_DI: - tcg_gen_movi_i32(tcg_ctx, cpu_ID, 0x1); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ID, 0x1); break; case OPC_RH850_DISPOSE_imm5_list12: { @@ -3564,7 +3639,7 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, int list [12] = {31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20}; int numOfListItems = sizeof(list) / sizeof(list[0]); - int list12 = extract32(ctx->opcode, 0, 1) | ( (extract32(ctx->opcode, 21, 11)) << 1); + int list12 = extract32(ctx->opcode, 0, 1) | ((extract32(ctx->opcode, 21, 11)) << 1); // reorganising bits that indicate the registers to load // doing this for easier looping in correct order @@ -3582,15 +3657,15 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, ((list12 & 0x1) << 1) ; int test = 0x1; - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer (sp) register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer (sp) register is tcg_ctx->cpu_gpr[3] tcg_gen_addi_i32(tcg_ctx, temp, temp, (extract32(ctx->opcode, 1, 5) << 2)); TCGv regToLoad = tcg_temp_new_i32(tcg_ctx); - for(int i=0; iopcode, 0, 1) | ( (extract32(ctx->opcode, 21, 11)) << 1); + int list12 = extract32(ctx->opcode, 0, 1) | ((extract32(ctx->opcode, 21, 11)) << 1); TCGv jmpAddr = tcg_temp_new_i32(tcg_ctx); // reorganising bits that indicate the registers to load @@ -3631,15 +3706,15 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, ((list12 & 0x1) << 1) ; int test = 0x1; - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer (sp) register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer (sp) register is tcg_ctx->cpu_gpr[3] tcg_gen_addi_i32(tcg_ctx, temp, temp, (extract32(ctx->opcode, 1, 5) << 2)); TCGv regToLoad = tcg_temp_new_i32(tcg_ctx); - for(int i=0; iopcode, 16, 5))); - tcg_gen_mov_i32(tcg_ctx, cpu_pc, jmpAddr); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, jmpAddr); gen_set_gpr(tcg_ctx, 3, temp); ctx->base.is_jmp = DISAS_EXIT_TB; @@ -3660,20 +3735,20 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, break; case OPC_RH850_EI: - tcg_gen_movi_i32(tcg_ctx, cpu_ID, 0x0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_ID, 0x0); break; case OPC_RH850_EIRET: /* Move EIPC to PC and EIPSW to PSW. */ - tcg_gen_mov_i32(tcg_ctx, cpu_pc, cpu_sysRegs[BANK_ID_BASIC_0][EIPC_IDX]); - tcgv_to_flags(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_0][EIPSW_IDX]); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][EIPC_IDX]); + tcgv_to_flags(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][EIPSW_IDX]); /* Update ISPR. */ gen_update_ispr(ctx, env); ctx->base.is_jmp = DISAS_EXIT_TB; break; case OPC_RH850_FERET: - tcg_gen_mov_i32(tcg_ctx, cpu_pc, cpu_sysRegs[BANK_ID_BASIC_0][FEPC_IDX]); - tcgv_to_flags(tcg_ctx, cpu_sysRegs[BANK_ID_BASIC_0][FEPSW_IDX]); + tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][FEPC_IDX]); + tcgv_to_flags(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[BANK_ID_BASIC_0][FEPSW_IDX]); ctx->base.is_jmp = DISAS_EXIT_TB; break; @@ -3700,19 +3775,19 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, // Modify only sytem regs, which exist. Real device executes instruction, but // value is not stored for system regs, which do not exist. No exception is // thrown. - if(cpu_sysRegs[selID][regID] != NULL || (selID == BANK_ID_BASIC_0 && regID == PSW_IDX)) { + if (tcg_ctx->rh850_cpu_sys_reg[selID][regID] != NULL || (selID == BANK_ID_BASIC_0 && regID == PSW_IDX)) { TCGv tmp = tcg_temp_new(tcg_ctx); gen_get_gpr(tcg_ctx, tmp, rs1); - if(selID == BANK_ID_BASIC_0 && regID == PSW_IDX){ + if (selID == BANK_ID_BASIC_0 && regID == PSW_IDX) { tcgv_to_flags(tcg_ctx, tmp); } else { // clear read-only bits in value, all other bits in sys reg. This way // read-only bits preserve their value given at reset tcg_gen_andi_i32(tcg_ctx, tmp, tmp, rh850_sys_reg_read_only_masks[selID][regID]); - tcg_gen_andi_i32(tcg_ctx, cpu_sysRegs[selID][regID], cpu_sysRegs[selID][regID], ~rh850_sys_reg_read_only_masks[selID][regID]); - tcg_gen_or_i32(tcg_ctx, cpu_sysRegs[selID][regID], cpu_sysRegs[selID][regID], tmp); + tcg_gen_andi_i32(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[selID][regID], tcg_ctx->rh850_cpu_sys_reg[selID][regID], ~rh850_sys_reg_read_only_masks[selID][regID]); + tcg_gen_or_i32(tcg_ctx, tcg_ctx->rh850_cpu_sys_reg[selID][regID], tcg_ctx->rh850_cpu_sys_reg[selID][regID], tmp); } tcg_temp_free(tcg_ctx, tmp); } @@ -3732,12 +3807,12 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, int numOfRegs = (rs3-rs1)+1; - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is tcg_ctx->cpu_gpr[3] TCGv regToLoad = tcg_temp_new_i32(tcg_ctx); - if(rs1<=rs3){ + if (rs1<=rs3) { - for(int i=0; iopcode, 21, 11) << 1) | (extract32(ctx->opcode, 0, 1) ) ) ; + int list12 = ((extract32(ctx->opcode, 21, 11) << 1) | (extract32(ctx->opcode, 0, 1) ) ) ; int numOfListItems = sizeof(list) / sizeof(list[0]); int prepList = ((list12 & 0x80) >> 7) | ((list12 & 0x40) >> 5) | @@ -3777,12 +3852,12 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, ((list12 & 0x1) << 10) ; int test = 0x1; - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is tcg_ctx->cpu_gpr[3] TCGv regToStore = tcg_temp_new_i32(tcg_ctx); - for(int i=0; iopcode, 0, 1) | ( (extract32(ctx->opcode, 21, 11)) << 1); + uint32_t list12 = extract32(ctx->opcode, 0, 1) | ((extract32(ctx->opcode, 21, 11)) << 1); int numOfListItems = sizeof(list) / sizeof(list[0]); int prepList = ((list12 & 0x80) >> 7) | ((list12 & 0x40) >> 5) | @@ -3822,12 +3897,12 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, int test = 0x1; int ff = extract32(ctx->opcode, 19, 2); - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is tcg_ctx->cpu_gpr[3] TCGv regToStore = tcg_temp_new_i32(tcg_ctx); - for(int i=0; icpu_gpr[30]) break; case 0x1: @@ -3886,11 +3961,11 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, int numOfRegs = (rs3-rs1)+1; - gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is cpu_gpr[3] + gen_get_gpr(tcg_ctx, temp, 3); // stack pointer register is tcg_ctx->cpu_gpr[3] TCGv regToStore = tcg_temp_new_i32(tcg_ctx); - if(rs1<=rs3){ + if (rs1<=rs3) { - for(int i=0; iopcode, 27, 5); - if(selID == BANK_ID_BASIC_0 && regID == PSW_IDX){ + if (selID == BANK_ID_BASIC_0 && regID == PSW_IDX) { TCGv tmp = tcg_temp_new_i32(tcg_ctx); tcg_gen_movi_tl(tcg_ctx, tmp, 0); flags_to_tcgv(tcg_ctx, tmp); gen_set_gpr(tcg_ctx, rs2, tmp); tcg_temp_free(tcg_ctx, tmp); } else { - if (cpu_sysRegs[selID][regID] != NULL) { - gen_set_gpr(tcg_ctx, rs2, cpu_sysRegs[selID][regID]); + if (tcg_ctx->rh850_cpu_sys_reg[selID][regID] != NULL) { + gen_set_gpr(tcg_ctx, rs2, tcg_ctx->rh850_cpu_sys_reg[selID][regID]); } else { TCGv dat = tcg_temp_local_new(tcg_ctx); tcg_gen_movi_i32(tcg_ctx, dat, 0); @@ -3949,14 +4024,14 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, gen_get_gpr(tcg_ctx, adr, rs1); tcg_gen_shli_i32(tcg_ctx, adr, adr, 0x1); - tcg_gen_add_i32(tcg_ctx, adr, adr, cpu_pc); + tcg_gen_add_i32(tcg_ctx, adr, adr, tcg_ctx->cpu_pc); tcg_gen_addi_i32(tcg_ctx, adr, adr, 0x2); - tcg_gen_addi_i32(tcg_ctx, cpu_pc, cpu_pc, 0x2); + tcg_gen_addi_i32(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_pc, 0x2); tcg_gen_qemu_ld16s(tcg_ctx, temp, adr, MEM_IDX); tcg_gen_ext16s_i32(tcg_ctx, temp, temp); tcg_gen_shli_i32(tcg_ctx, temp, temp, 0x1); - tcg_gen_add_i32(tcg_ctx, cpu_pc, cpu_pc, temp); + tcg_gen_add_i32(tcg_ctx, tcg_ctx->cpu_pc, tcg_ctx->cpu_pc, temp); ctx->base.is_jmp = DISAS_EXIT_TB; } break; @@ -3995,9 +4070,9 @@ static void gen_special(DisasContext *ctx, CPURH850State *env, int rs1, int rs2, } /* Cache operations are not supported on single core emulation. */ -static void gen_cache(DisasContext *ctx, int rs1, int rs2, int operation){ +static void gen_cache(DisasContext *ctx, int rs1, int rs2, int operation) { int cache_op = (extract32(ctx->opcode,11, 2) << 5 ) | (extract32(ctx->opcode, 27, 5)); - switch(cache_op){ + switch (cache_op) { case CHBII: // printf("CHBII\n"); break; @@ -4036,7 +4111,7 @@ static void decode_RH850_48(CPURH850State *env, DisasContext *ctx) uint32_t disp23 = (ctx->opcode1 << 7) | (extract32(ctx->opcode, 21, 6) << 1); uint32_t disp32 = (opcode48 >> 16); - switch(opcode20) { + switch (opcode20) { case OPC_RH850_LDB2: @@ -4077,7 +4152,7 @@ static void decode_RH850_48(CPURH850State *env, DisasContext *ctx) } else if (extract32(ctx->opcode, 5, 12) == 0x37) { gen_jmp(ctx, rs1, disp32, OPC_RH850_JMP_disp32_reg1); } else if (extract32(ctx->opcode, 5, 11) == 0x17) { - if (rs1 == 0x0){ + if (rs1 == 0x0) { gen_jmp(ctx, 0, disp32, OPC_RH850_JR_imm32); } else { @@ -4112,17 +4187,16 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) gen_get_gpr(tcg_ctx, r1, rs1); gen_get_gpr(tcg_ctx, r2, rs2); - switch(op){ + switch (op) { case OPC_RH850_LDB: gen_load(ctx, MO_SB, rs2, rs1, ld_imm, 0); break; case OPC_RH850_LDH_LDW: - if ( extract32(ctx->opcode, 16, 1) == 0 ){ + if (extract32(ctx->opcode, 16, 1) == 0 ) { gen_load(ctx, MO_TESW, rs2, rs1, ld_imm, 0); // LD.H - } - else{ + } else { gen_load(ctx, MO_TESL, rs2, rs1, ld_imm & 0xfffe, 0); // LD.W } break; @@ -4132,7 +4206,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_STH_STW: - if ( extract32(ctx->opcode, 16, 1)==1 ) { + if (extract32(ctx->opcode, 16, 1)==1 ) { gen_store(ctx, MO_TESL, rs1, rs2, ((extract32(ctx->opcode, 17, 15))) << 1, 0); //this is STORE WORD break; @@ -4150,7 +4224,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_MOVEA: - if ( extract32(ctx->opcode, 11, 5) == 0 ){ + if (extract32(ctx->opcode, 11, 5) == 0 ) { // This is 48bit MOV // This instruction should be reached first in decode_RH850_48 } else { @@ -4159,10 +4233,10 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_MOVHI_imm16_reg1_reg2: - if(extract32(ctx->opcode, 11, 5)!=0x0){ + if (extract32(ctx->opcode, 11, 5)!=0x0) { gen_arithmetic(ctx, rs1, rs2, OPC_RH850_MOVHI_imm16_reg1_reg2); } else { - if(extract32(ctx->opcode, 16, 5)==0x0){ + if (extract32(ctx->opcode, 16, 5)==0x0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_DISPOSE_imm5_list12); } else { gen_special(ctx, env, rs1, rs2, OPC_RH850_DISPOSE_imm5_list12_reg1); @@ -4175,10 +4249,10 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_SATSUBI_imm16_reg1_reg2: - if(extract32(ctx->opcode, 11, 5)!=0x0){ + if (extract32(ctx->opcode, 11, 5)!=0x0) { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATSUBI_imm16_reg1_reg2); } else { - if(extract32(ctx->opcode, 16, 5)==0x0){ + if (extract32(ctx->opcode, 16, 5)==0x0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_DISPOSE_imm5_list12); } else { gen_special(ctx, env, rs1, rs2, OPC_RH850_DISPOSE_imm5_list12_reg1); @@ -4198,7 +4272,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_BIT_MANIPULATION_2: - switch(extract32(ctx->opcode, 14, 2)){ + switch (extract32(ctx->opcode, 14, 2)) { case 0: gen_bit_manipulation(ctx, rs1, rs2, OPC_RH850_SET1_bit3_disp16_reg1); break; @@ -4216,8 +4290,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) case OPC_RH850_32bit_1: /* case for opcode = 111111 ; formats IX, X, XI, XII */ if (extract32(ctx->opcode, 16, 1) == 0x1 ) { /* BCOND disp17 */ - if (rs2 == 0x0) - { + if (rs2 == 0x0) { /* Get condition. */ cond = extract32(ctx->opcode, 0, 4); @@ -4225,34 +4298,29 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) imm_32 = ((extract32(ctx->opcode, 4, 1)<<16) | (extract32(ctx->opcode, 17, 15) << 1)); /* Sign-extend value to 32 bits. */ - if ((imm_32 & 0x10000) == 0x10000) - { + if ((imm_32 & 0x10000) == 0x10000) { imm_32 |= (0x7fff << 17); } gen_branch(env, ctx, cond, rs1, rs2, imm_32); break; - } - else - { + } else { /* LD.HU */ gen_load(ctx, MO_TEUW, rs2, rs1, ld_imm & 0xfffe, 0); break; } } formXop = MASK_OP_32BIT_SUB(ctx->opcode); //sub groups based on bits b23-b26 - switch(formXop){ + switch (formXop) { case OPC_RH850_LDSR_RIE_SETF_STSR: check32bitZERO = extract32(ctx->opcode, 21, 2); - switch(check32bitZERO){ + switch (check32bitZERO) { case 0: - if(extract32(ctx->opcode, 4, 1)==1) + if (extract32(ctx->opcode, 4, 1)==1) { gen_special(ctx, env, rs1, rs2, OPC_RH850_RIE); - } - else - { + } else { printf("gen SETF\r\n"); gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SETF_cccc_reg2); } @@ -4267,74 +4335,50 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_FORMAT_IX: //format IX instructions formXop = MASK_OP_FORMAT_IX(ctx->opcode); //mask on bits 21, 22 - switch(formXop) + switch (formXop) { case OPC_RH850_BINS_0: - if (extract32(ctx->opcode, 20, 1) == 1) - { + if (extract32(ctx->opcode, 20, 1) == 1) { //BINS0 gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_BINS); - } - else - { - if (extract32(ctx->opcode, 17, 1) == 0) - { + } else { + if (extract32(ctx->opcode, 17, 1) == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SHR_reg1_reg2); - } - else - { + } else { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SHR_reg1_reg2_reg3); } } break; case OPC_RH850_BINS_1: - if (extract32(ctx->opcode, 20, 1) == 1) - { + if (extract32(ctx->opcode, 20, 1) == 1) { //BINS1 gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_BINS); - } - else - { - if (extract32(ctx->opcode, 17, 1) == 0) - { + } else { + if (extract32(ctx->opcode, 17, 1) == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SAR_reg1_reg2); - } - else - { + } else { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SAR_reg1_reg2_reg3); } } break; case OPC_RH850_BINS_2: - if (extract32(ctx->opcode, 20, 1) == 1) - { + if (extract32(ctx->opcode, 20, 1) == 1) { //BINS2 gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_BINS); - } - else - { - if (extract32(ctx->opcode, 17, 1) == 0) - { - if (extract32(ctx->opcode, 18, 1) == 1) - { + } else { + if (extract32(ctx->opcode, 17, 1) == 0) { + if (extract32(ctx->opcode, 18, 1) == 1) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_ROTL_imm5_reg2_reg3); - } - else - { + } else { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SHL_reg1_reg2); } - } - else - { - if (extract32(ctx->opcode, 18, 1) == 1) - { + } else { + if (extract32(ctx->opcode, 18, 1) == 1) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_ROTL_reg1_reg2_reg3); - } - else - { + } else { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SHL_reg1_reg2_reg3); } @@ -4343,7 +4387,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_BIT_MANIPULATION: // in format IX check32bitZERO = extract32(ctx->opcode, 16, 3); - switch(check32bitZERO){ + switch (check32bitZERO) { case OPC_RH850_SET1_reg2_reg1: gen_bit_manipulation(ctx, rs1, rs2, OPC_RH850_SET1_reg2_reg1); break; @@ -4354,7 +4398,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) gen_bit_manipulation(ctx, rs1, rs2, OPC_RH850_CLR1_reg2_reg1); break; case OPC_RH850_TST1_reg2_reg1: - if (extract32(ctx->opcode, 19, 1) == 0){ + if (extract32(ctx->opcode, 19, 1) == 0) { gen_bit_manipulation(ctx, rs1, rs2, OPC_RH850_TST1_reg2_reg1); } else { gen_special(ctx, env, rs1, rs2, OPC_RH850_CAXI_reg1_reg2_reg3); @@ -4369,7 +4413,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) //(+JARL3 - added due to MASK_OP_FORMAT_X matching) formXop = MASK_OP_FORMAT_X(ctx->opcode); - switch(formXop){ + switch (formXop) { case OPC_RH850_CTRET: gen_special(ctx, env, rs1, rs2, OPC_RH850_CTRET); @@ -4411,8 +4455,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) gen_special(ctx, env, rs1, rs2, OPC_RH850_PUSHSP_rh_rt); break; default: - if ((extract32(ctx->opcode, 13, 12) == 0xB07)) - { + if ((extract32(ctx->opcode, 13, 12) == 0xB07)) { if ((extract32(ctx->opcode, 27, 5) == 0x1E) && (extract32(ctx->opcode, 0, 5) == 0x1F)) { @@ -4429,32 +4472,21 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) } break; case OPC_RH850_MUL_INSTS: - if (extract32(ctx->opcode, 22, 1) == 0) - { - if (extract32(ctx->opcode, 21, 1) == 0) - { + if (extract32(ctx->opcode, 22, 1) == 0) { + if (extract32(ctx->opcode, 21, 1) == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SASF_cccc_reg2); - } - else - { - if (extract32(ctx->opcode, 17, 1) == 1) - { + } else { + if (extract32(ctx->opcode, 17, 1) == 1) { gen_multiply(ctx, rs1, rs2, OPC_RH850_MULU_reg1_reg2_reg3); - } - else - { + } else { gen_multiply(ctx, rs1, rs2, OPC_RH850_MUL_reg1_reg2_reg3); } } break; - } else if (extract32(ctx->opcode, 22, 1) == 1) - { - if (extract32(ctx->opcode, 17, 1) == 1) - { + } else if (extract32(ctx->opcode, 22, 1) == 1) { + if (extract32(ctx->opcode, 17, 1) == 1) { gen_multiply(ctx, rs1, rs2, OPC_RH850_MULU_imm9_reg2_reg3); - } - else - { + } else { gen_multiply(ctx, rs1, rs2, OPC_RH850_MUL_imm9_reg2_reg3); } break; @@ -4463,7 +4495,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) case OPC_RH850_FORMAT_XI: // DIV instructions in format XI formXop = extract32(ctx->opcode, 16, 7); - switch(formXop){ + switch (formXop) { case OPC_RH850_DIV_reg1_reg2_reg3: gen_divide(ctx, rs1, rs2, OPC_RH850_DIV_reg1_reg2_reg3); @@ -4498,7 +4530,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) // also LDL.W and STC.W (Format VII) checkXII = extract32(ctx->opcode, 21, 2); - switch(checkXII) + switch (checkXII) { case 0: gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_CMOV_cccc_imm5_reg2_reg3); @@ -4509,7 +4541,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) case 2: formXop = extract32(ctx->opcode, 17, 2); - switch(formXop) + switch (formXop) { case OPC_RH850_BSW_reg2_reg3: gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_BSW_reg2_reg3); @@ -4529,7 +4561,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) break; case 3: //these are SCHOL, SCHOR, SCH1L, SCH1R. Also LDL.W formXop = extract32(ctx->opcode, 17, 2); - switch(formXop) + switch (formXop) { case OPC_RH850_SCH0R_reg2_reg3: if (extract32(ctx->opcode, 5, 11) == 0x3F && @@ -4540,8 +4572,7 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) gen_bit_search(ctx, rs2, OPC_RH850_SCH0R_reg2_reg3); break; case OPC_RH850_SCH1R_reg2_reg3: - if (extract32(ctx->opcode, 19, 2) == 0x0) - { + if (extract32(ctx->opcode, 19, 2) == 0x0) { gen_bit_search(ctx, rs2, OPC_RH850_SCH1R_reg2_reg3); } else if (extract32(ctx->opcode, 5, 11) == 0x3F && @@ -4562,26 +4593,20 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) case OPC_RH850_ADDIT_ARITH: formXop = extract32(ctx->opcode, 21, 2); - switch(formXop) + switch (formXop) { case OPC_RH850_ADF_SATADD3: - if (extract32(ctx->opcode, 16, 5) == 0x1A) - { + if (extract32(ctx->opcode, 16, 5) == 0x1A) { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATADD_reg1_reg2_reg3); - } - else - { + } else { gen_cond_arith(ctx, rs1, rs2, OPC_RH850_ADF_cccc_reg1_reg2_reg3); } break; case OPC_RH850_SBF_SATSUB: - if (extract32(ctx->opcode, 16, 5) == 0x1A) - { + if (extract32(ctx->opcode, 16, 5) == 0x1A) { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATSUB_reg1_reg2_reg3); - } - else - { + } else { gen_cond_arith(ctx, rs1, rs2, OPC_RH850_SBF_cccc_reg1_reg2_reg3); } break; @@ -4611,40 +4636,32 @@ static void decode_RH850_32(CPURH850State *env, DisasContext *ctx) } } - if (MASK_OP_FORMAT_V_FORMAT_XIII(ctx->opcode) == OPC_RH850_FORMAT_V_XIII){ - if(extract32(ctx->opcode, 16, 1) == 0) + if (MASK_OP_FORMAT_V_FORMAT_XIII(ctx->opcode) == OPC_RH850_FORMAT_V_XIII) { + if (extract32(ctx->opcode, 16, 1) == 0) { uint32_t disp22 = extract32(ctx->opcode, 16, 16) | (extract32(ctx->opcode, 0, 6) << 16 ); - if( (disp22 & 0x200000) == 0x200000) + if ((disp22 & 0x200000) == 0x200000) { disp22 = disp22 | (0x3ff << 22); } - if (extract32(ctx->opcode, 11, 5) == 0) - { + if (extract32(ctx->opcode, 11, 5) == 0) { gen_jmp(ctx, 0, disp22, OPC_RH850_JR_imm22); //JR disp22 - } - else - { + } else { gen_jmp(ctx, 0, disp22, OPC_RH850_JARL_disp22_reg2); } - } - else - { - if (extract32(ctx->opcode, 11, 5) != 0) - { + } else { + if (extract32(ctx->opcode, 11, 5) != 0) { //LD.BU gen_load(ctx, MO_UB, rs2, rs1, (ld_imm & 0xfffe) | extract32(ctx->opcode, 5, 1), 0); - } - else - { - if (extract32(ctx->opcode, 16, 3) == 0x3){ + } else { + if (extract32(ctx->opcode, 16, 3) == 0x3) { gen_special(ctx, env, rs1, rs2, OPC_RH850_PREPARE_list12_imm5_sp); //PREPARE2 } - else if (extract32(ctx->opcode, 16, 3) == 0x1){ + else if (extract32(ctx->opcode, 16, 3) == 0x1) { gen_special(ctx, env, rs1, rs2, OPC_RH850_PREPARE_list12_imm5); //PREPARE1 } @@ -4672,12 +4689,12 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) rs2 = GET_RS2(ctx->opcode); // rs2 at bits b11-b15; imm = rs1; - if((op & 0xf << 7) == OPC_RH850_BCOND ) + if ((op & 0xf << 7) == OPC_RH850_BCOND ) { // checking for 4 bit opcode for BCOND cond = extract32(ctx->opcode, 0, 4); - imm = ( extract32(ctx->opcode, 4, 3) | (extract32(ctx->opcode, 11, 5) << 3)) << 1 ; + imm = (extract32(ctx->opcode, 4, 3) | (extract32(ctx->opcode, 11, 5) << 3)) << 1 ; - if ( (imm & 0x100) == 0x100){ + if ((imm & 0x100) == 0x100) { imm |= (0x7fffff << 9); } gen_branch(env, ctx, cond, rs1, rs2, imm); @@ -4685,7 +4702,7 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) return; } - switch(op) + switch (op) { case OPC_RH850_16bit_0: if (rs2 != 0) { @@ -4693,7 +4710,7 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) break; } else { subOpCheck = MASK_OP_FORMAT_I_0(op); - switch(subOpCheck){ + switch (subOpCheck) { case OPC_RH850_NOP: break; case OPC_RH850_SYNCI: @@ -4709,28 +4726,19 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_16bit_2: - if (rs2 == 0) - { - if (rs1 == 0) - { + if (rs2 == 0) { + if (rs1 == 0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_RIE); break; - } - else - { + } else { gen_special(ctx, env, rs1, rs2, OPC_RH850_SWITCH_reg1); break; } - } - else - { - if (rs1 == 0) - { + } else { + if (rs1 == 0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_FETRAP_vector4); break; - } - else - { + } else { gen_divide(ctx, rs1, rs2, OPC_RH850_DIVH_reg1_reg2); break; } @@ -4738,49 +4746,37 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) break; case OPC_RH850_16bit_4: - if (rs2 == 0) - { + if (rs2 == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_ZXB_reg1); break; - } - else - { + } else { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATSUBR_reg1_reg2); break; } break; case OPC_RH850_16bit_5: - if (rs2 == 0) - { + if (rs2 == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SXB_reg1); break; - } - else - { + } else { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATSUB_reg1_reg2); break; } break; case OPC_RH850_16bit_6: - if (rs2 == 0) - { + if (rs2 == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_ZXH_reg1); break; - } - else - { + } else { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATADD_reg1_reg2); break; } break; case OPC_RH850_16bit_7: - if (rs2 == 0) - { + if (rs2 == 0) { gen_data_manipulation(ctx, rs1, rs2, OPC_RH850_SXH_reg1); break; - } - else - { + } else { gen_multiply(ctx, rs1, rs2, OPC_RH850_MULH_reg1_reg2); break; } @@ -4797,17 +4793,14 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) // this case is already handled in decode_RH850_48() case OPC_RH850_16bit_3: - if (rs2 == 0) - { // JMP + if (rs2 == 0) { // JMP gen_jmp(ctx, rs1, disp32, OPC_RH850_JMP_reg1); break; - } - else - { - if(extract32(rs1,4,1)==1){ + } else { + if (extract32(rs1,4,1)==1) { //SLD.HU gen_load(ctx, MO_TEUW, rs2, 30, extract32(ctx->opcode, 0, 4) << 1, 0); - }else{ + } else { //SLD.BU gen_load(ctx, MO_UB, rs2, 30, extract32(ctx->opcode, 0, 4), 0); } @@ -4839,25 +4832,19 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) gen_arithmetic(ctx, rs1, rs2, OPC_RH850_CMP_reg1_reg2); break; case OPC_RH850_16bit_16: - if (rs2 == 0) - { + if (rs2 == 0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_CALLT_imm6); break; - } - else - { + } else { gen_arithmetic(ctx, imm, rs2, OPC_RH850_MOV_imm5_reg2); break; } break; case OPC_RH850_16bit_17: - if (rs2 == 0) - { + if (rs2 == 0) { gen_special(ctx, env, rs1, rs2, OPC_RH850_CALLT_imm6); break; - } - else - { + } else { gen_sat_op(ctx, rs1, rs2, OPC_RH850_SATADD_imm5_reg2); break; } @@ -4886,7 +4873,7 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) uint32_t opIV = (op >> 7); opIV = opIV << 5; - switch(opIV) + switch (opIV) { case OPC_RH850_16bit_SLDB: gen_load(ctx, MO_SB, rs2, 30, extract32(ctx->opcode, 0, 7), 0); @@ -4895,13 +4882,12 @@ static void decode_RH850_16(CPURH850State *env, DisasContext *ctx) gen_load(ctx, MO_TESW, rs2, 30, extract32(ctx->opcode, 0, 7) << 1, 0); break; case OPC_RH850_16bit_IV10: - if ( extract32(rs1,0,1) == 1 ) { + if (extract32(rs1,0,1) == 1 ) { //SST.W gen_store(ctx, MO_TEUL, 30, rs2, (extract32(ctx->opcode, 1, 6)) << 2, 0); /// Note An MAE or MDP exception might occur /// depending on the result of address calculation. - } - else{ + } else { //SLD.W gen_load(ctx, MO_TESL, rs2, 30, extract32(ctx->opcode, 1, 6) << 2, 0); } @@ -4976,64 +4962,54 @@ static bool rh850_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, /* RH850 instruction translation callback. */ static void rh850_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext *dc = container_of(dcbase, DisasContext, base); - struct uc_struct *uc = dc->uc; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + struct uc_struct *uc = ctx->uc; TCGContext *tcg_ctx = uc->tcg_ctx; TCGOp *tcg_op, *prev_op = NULL; - CPURH850State *env = dc->env; - bool insn_hook = false; + CPURH850State *env = ctx->env; + target_ulong pc_start = ctx->base.pc_next; - if (uc_addr_is_exit(dc->uc, dc->base.pc_next)) { + // Unicorn: trace this instruction on request + bool insn_hook = false; + if (uc_addr_is_exit(ctx->uc, ctx->base.pc_next)) { // imitate PGM exception to halt emulation dcbase->is_jmp = DISAS_UNICORN_HALT; - } - else - { - #if 0 - // Unicorn: trace this instruction on request - if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, dc->pc)) { - + } else { + if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, ctx->pc)) { // Sync PC in advance - tcg_gen_movi_i32(tcg_ctx, cpu_pc, dc->pc); - + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_pc, ctx->pc); + // save the last operand prev_op = tcg_last_op(tcg_ctx); insn_hook = true; - - gen_uc_tracecode(tcg_ctx, 0xF1F1F1F1, UC_HOOK_CODE_IDX, env->uc, dc->pc); - + gen_uc_tracecode(tcg_ctx, 2, UC_HOOK_CODE_IDX, uc, ctx->pc); // the callback might want to stop emulation immediately check_exit_request(tcg_ctx); } - #endif - dc->opcode = cpu_lduw_code(env, dc->pc); // get opcode from memory + ctx->opcode = cpu_lduw_code(env, ctx->pc); // get opcode from memory - if ((extract32(dc->opcode, 9, 2) != 0x3) && (extract32(dc->opcode, 5, 11) != 0x17)) { - dc->base.pc_next = dc->pc + 2; - decode_RH850_16(env, dc); //this function includes 32-bit JR and JARL + if ((extract32(ctx->opcode, 9, 2) != 0x3) && (extract32(ctx->opcode, 5, 11) != 0x17)) { + ctx->base.pc_next = ctx->pc + 2; + decode_RH850_16(env, ctx); // this function includes 32-bit JR and JARL } else { - dc->opcode = (dc->opcode) | (cpu_lduw_code(env, dc->pc + 2) << 0x10); - if (((extract32(dc->opcode, 6, 11) == 0x41e) && ((extract32(dc->opcode, 17, 2) > 0x1) || - (extract32(dc->opcode, 17, 3) == 0x4))) || - (extract32(dc->opcode, 5, 11) == 0x31) || // 48-bit MOV - (extract32(dc->opcode, 5, 12) == 0x37) || // 48-bit JMP - (extract32(dc->opcode, 5, 11) == 0x17) || // 48-bit JARL & JR - ((extract32(dc->opcode, 5, 11) == 0x3D) && (extract32(dc->opcode, 16, 5) == 0x07)) // 48-bit LD.HU - ) - { - dc->opcode1 = cpu_lduw_code(env, dc->pc + 4); - dc->base.pc_next = dc->pc + 6; - decode_RH850_48(env, dc); - } - else - { - dc->base.pc_next = dc->pc + 4; - decode_RH850_32(env, dc); + ctx->opcode = (ctx->opcode) | (cpu_lduw_code(env, ctx->pc + 2) << 0x10); + if (((extract32(ctx->opcode, 6, 11) == 0x41e) && ((extract32(ctx->opcode, 17, 2) > 0x1) || + (extract32(ctx->opcode, 17, 3) == 0x4))) || + (extract32(ctx->opcode, 5, 11) == 0x31) || // 48-bit MOV + (extract32(ctx->opcode, 5, 12) == 0x37) || // 48-bit JMP + (extract32(ctx->opcode, 5, 11) == 0x17) || // 48-bit JARL & JR + ((extract32(ctx->opcode, 5, 11) == 0x3D) && (extract32(ctx->opcode, 16, 5) == 0x07)) // 48-bit LD.HU + ) { + ctx->opcode1 = cpu_lduw_code(env, ctx->pc + 4); + ctx->base.pc_next = ctx->pc + 6; + decode_RH850_48(env, ctx); + } else { + ctx->base.pc_next = ctx->pc + 4; + decode_RH850_32(env, ctx); } } - #if 0 if (insn_hook) { // Unicorn: patch the callback to have the proper instruction size. if (prev_op) { @@ -5048,17 +5024,16 @@ static void rh850_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) tcg_op = QTAILQ_FIRST(&tcg_ctx->ops); } - tcg_op->args[1] = dc->base.pc_next - dc->pc; + tcg_op->args[1] = ctx->base.pc_next - pc_start; } - #endif - dc->pc = dc->base.pc_next; + ctx->pc = ctx->base.pc_next; } } -static void update_pc_addr(DisasContext *s) +static void rh850_sync_pc(DisasContextBase *db, CPUState *cpu) { - /* psw.addr */ + DisasContext *s = container_of(db, DisasContext, base); TCGContext *tcg_ctx = s->uc->tcg_ctx; tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_pc, s->base.pc_next); } @@ -5069,29 +5044,27 @@ static void rh850_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); TCGContext *tcg_ctx = dc->uc->tcg_ctx; - if (dc->base.is_jmp == DISAS_NORETURN) - { + if (dc->base.is_jmp == DISAS_NORETURN) { return; } if (dc->base.singlestep_enabled) { if (dc->base.is_jmp == DISAS_NEXT || dc->base.is_jmp == DISAS_TOO_MANY) { // PC is not loaded inside TB, so we have to do it here in case of // single stepping - tcg_gen_movi_tl(tcg_ctx, cpu_pc, dc->pc); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dc->pc); } gen_exception_debug(dc); } - switch (dc->base.is_jmp) - { + switch (dc->base.is_jmp) { case DISAS_UNICORN_HALT: - tcg_gen_movi_tl(tcg_ctx, cpu_pc, dc->pc); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc, dc->pc); gen_exception_halt(dc); break; case DISAS_TOO_MANY: case DISAS_PC_STALE: case DISAS_PC_STALE_NOCHAIN: - update_pc_addr(dc); + rh850_sync_pc(dcbase, cpu); gen_goto_tb_imm(dc, 0, dc->pc); break; case DISAS_INDIRECT_JUMP: @@ -5116,6 +5089,7 @@ static const TranslatorOps rh850_tr_ops = { .breakpoint_check = rh850_tr_breakpoint_check, .translate_insn = rh850_tr_translate_insn, .tb_stop = rh850_tr_tb_stop, + .pc_sync = rh850_sync_pc, }; /** @@ -5138,12 +5112,12 @@ void rh850_translate_init(struct uc_struct *uc) TCGContext *tcg_ctx = uc->tcg_ctx; int i; - /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ + /* tcg_ctx->cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ /* registers, unless you specifically block writes to reg 0 */ for (i = 0; i < NUM_GP_REGS; i++) { - cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, + tcg_ctx->cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, gpRegs[i]), rh850_gp_regnames[i]); } @@ -5151,40 +5125,39 @@ void rh850_translate_init(struct uc_struct *uc) for (int regIdx = 0; regIdx < MAX_SYS_REGS_IN_BANK; regIdx++) { const char *regName = rh850_sys_regnames[bankIdx][regIdx]; if (regName != NULL) { - cpu_sysRegs[bankIdx][regIdx] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, - offsetof(CPURH850State, systemRegs[bankIdx][regIdx]), + tcg_ctx->rh850_cpu_sys_reg[bankIdx][regIdx] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, + offsetof(CPURH850State, sys_reg[bankIdx][regIdx]), regName); } else { - cpu_sysRegs[bankIdx][regIdx] = NULL; // mark register as not present + tcg_ctx->rh850_cpu_sys_reg[bankIdx][regIdx] = NULL; // mark register as not present } } } - for (i = 0; i < 1; i++) { - cpu_sysDatabuffRegs[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, - offsetof(CPURH850State, sysDatabuffRegs[i]), rh850_sys_databuff_regnames[i]); - } + tcg_ctx->cpu_sys_databuf_reg = tcg_global_mem_new( + tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, cpu_sys_databuf_reg), + rh850_sys_databuf_regname); // PSW register flags - cpu_ZF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, Z_flag), "ZF"); - cpu_SF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, S_flag), "SF"); - cpu_OVF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, OV_flag), "OVF"); - cpu_CYF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CY_flag), "CYF"); - cpu_SATF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, SAT_flag), "SAT"); - cpu_ID = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, ID_flag), "ID"); - cpu_EP = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, EP_flag), "EP"); - cpu_NP = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, NP_flag), "NP"); - cpu_EBV = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, EBV_flag), "EBV"); - cpu_CU0 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU0_flag), "CU0"); - cpu_CU1 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU1_flag), "CU1"); - cpu_CU2 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU2_flag), "CU2"); - cpu_UM = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, UM_flag), "UM"); - - cpu_pc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, pc), "pc"); - load_res = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, load_res), "load_res"); - load_val = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, load_val), "load_val"); - - cpu_LLbit = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, cpu_LLbit), "cpu_LLbit"); - cpu_LLAddress = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, cpu_LLAddress), "cpu_LLAddress"); + tcg_ctx->cpu_ZF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, Z_flag), "ZF"); + tcg_ctx->cpu_SF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, S_flag), "SF"); + tcg_ctx->cpu_OVF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, OV_flag), "OVF"); + tcg_ctx->cpu_CYF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CY_flag), "CYF"); + tcg_ctx->cpu_SATF = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, SAT_flag), "SAT"); + tcg_ctx->cpu_ID = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, ID_flag), "ID"); + tcg_ctx->cpu_EP = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, EP_flag), "EP"); + tcg_ctx->cpu_NP = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, NP_flag), "NP"); + tcg_ctx->cpu_EBV = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, EBV_flag), "EBV"); + tcg_ctx->cpu_CU0 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU0_flag), "CU0"); + tcg_ctx->cpu_CU1 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU1_flag), "CU1"); + tcg_ctx->cpu_CU2 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, CU2_flag), "CU2"); + tcg_ctx->cpu_UM = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, UM_flag), "UM"); + + tcg_ctx->cpu_pc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, pc), "pc"); + tcg_ctx->load_res = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, load_res), "load_res"); + tcg_ctx->load_val = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, load_val), "load_val"); + + tcg_ctx->cpu_LLbit = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, cpu_LLbit), "cpu_LLbit"); + tcg_ctx->cpu_LLAddress = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURH850State, cpu_LLAddress), "cpu_LLAddress"); } diff --git a/qemu/target/rh850/translate.h b/qemu/target/rh850/translate.h index a622c4ce58..e8bd230ddd 100644 --- a/qemu/target/rh850/translate.h +++ b/qemu/target/rh850/translate.h @@ -1,9 +1,7 @@ -#ifndef _RH850_TRANSLATE_H -#define _RH850_TRANSLATE_H +#ifndef RH850_TRANSLATE_H +#define RH850_TRANSLATE_H -#include "cpu.h" #include "exec/translator.h" -#include "tcg/tcg-op.h" /** * This structure contains data, which is needed to translate a @@ -32,4 +30,4 @@ void gen_set_gpr(TCGContext *tcg_ctx, int reg_num_dst, TCGv t); void gen_set_spr(TCGContext *tcg_ctx, int bank_id, int reg_id, TCGv t); void gen_get_spr(TCGContext *tcg_ctx, int bank_id, int reg_id, TCGv t); -#endif /* _RH850_TRANSLATE_H */ \ No newline at end of file +#endif /* _RH850_TRANSLATE_H */ diff --git a/qemu/target/rh850/unicorn.c b/qemu/target/rh850/unicorn.c index 362c92dc8c..485fe55724 100644 --- a/qemu/target/rh850/unicorn.c +++ b/qemu/target/rh850/unicorn.c @@ -1,14 +1,14 @@ /* Unicorn Emulator Engine */ /* By Nguyen Anh Quynh , 2015-2021 */ -/* Modified for Unicorn Engine by Damien Cauquil, 2020 */ +/* Modified for Unicorn Engine by Damien Cauquil, 2020 + */ -#include "sysemu/cpus.h" #include "cpu.h" #include "unicorn_common.h" #include "uc_priv.h" #include "unicorn.h" -RH850CPU *cpu_rh850_init(struct uc_struct *uc, const char *cpu_model); +RH850CPU *cpu_rh850_init(struct uc_struct *uc); static void rh850_set_pc(struct uc_struct *uc, uint64_t address) { @@ -49,66 +49,63 @@ static void reg_reset(struct uc_struct *uc) } DEFAULT_VISIBILITY -uc_err reg_read(void *_env, int mode, unsigned int regid, void *value, size_t *size) +uc_err reg_read(void *_env, int mode, unsigned int regid, void *value, + size_t *size) { int sel_id; CPURH850State *env = _env; uc_err ret = UC_ERR_ARG; /* PC */ - if (regid == UC_RH850_REG_PC) - { + if (regid == UC_RH850_REG_PC) { CHECK_REG_TYPE(uint32_t); *(uint32_t *)value = env->pc; } /* General purpose register. */ - if ((regid >= UC_RH850_REG_R0) && (regid <= UC_RH850_REG_R31)) - { + if ((regid >= UC_RH850_REG_R0) && (regid <= UC_RH850_REG_R31)) { CHECK_REG_TYPE(uint32_t); *(uint32_t *)value = env->gpRegs[regid]; } /* System registers. */ - if ((regid >= UC_RH850_SYSREG_SELID0) && (regid < (UC_RH850_SYSREG_SELID7 + 32))) - { + if ((regid >= UC_RH850_REG_EIPC) && + (regid < (UC_RH850_REG_PC))) { CHECK_REG_TYPE(uint32_t); - sel_id = (regid - 32)/32; - *(uint32_t *)value = env->systemRegs[sel_id][regid % 32]; + sel_id = (regid - 32) / 32; + *(uint32_t *)value = env->sys_reg[sel_id][regid % 32]; } return ret; } - DEFAULT_VISIBILITY -uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value, size_t *size, int *setpc) +uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value, + size_t *size, int *setpc) { int sel_id; CPURH850State *env = _env; uc_err ret = UC_ERR_ARG; /* PC */ - if (regid == UC_RH850_REG_PC) - { + if (regid == UC_RH850_REG_PC) { CHECK_REG_TYPE(uint32_t); env->pc = *(uint32_t *)value; *setpc = 1; } /* General purpose register. */ - if ((regid >= UC_RH850_REG_R0) && (regid <= UC_RH850_REG_R31)) - { + if ((regid >= UC_RH850_REG_R0) && (regid <= UC_RH850_REG_R31)) { CHECK_REG_TYPE(uint32_t); env->gpRegs[regid] = *(uint32_t *)value; } /* System registers. */ - if ((regid >= UC_RH850_SYSREG_SELID0) && (regid <= (UC_RH850_SYSREG_SELID7 + 32))) - { + if ((regid >= UC_RH850_REG_EIPC) && + (regid <= (UC_RH850_REG_PC))) { CHECK_REG_TYPE(uint32_t); - sel_id = (regid - 32)/32; - env->systemRegs[sel_id][regid % 32] = *(uint32_t *)value; + sel_id = (regid - 32) / 32; + env->sys_reg[sel_id][regid % 32] = *(uint32_t *)value; } return ret; @@ -118,7 +115,7 @@ static int rh850_cpus_init(struct uc_struct *uc, const char *cpu_model) { RH850CPU *cpu; - cpu = cpu_rh850_init(uc, cpu_model); + cpu = cpu_rh850_init(uc); if (cpu == NULL) { return -1; } @@ -126,7 +123,7 @@ static int rh850_cpus_init(struct uc_struct *uc, const char *cpu_model) } DEFAULT_VISIBILITY -void rh850_uc_init(struct uc_struct *uc) +void uc_init_rh850(struct uc_struct *uc) { uc->reg_read = reg_read; uc->reg_write = reg_write; diff --git a/qemu/target/rh850/unicorn.h b/qemu/target/rh850/unicorn.h index 7ce57301a4..c6ee4497fb 100644 --- a/qemu/target/rh850/unicorn.h +++ b/qemu/target/rh850/unicorn.h @@ -6,11 +6,11 @@ // functions to read & write registers uc_err reg_read_rh850(void *_env, int mode, unsigned int regid, void *value, - size_t *size); -uc_err reg_write_rh850(void *_env, int mode, unsigned int regid, const void *value, - size_t *size, int *setpc); + size_t *size); +uc_err reg_write_rh850(void *_env, int mode, unsigned int regid, + const void *value, size_t *size, int *setpc); void reg_reset_rh850(struct uc_struct *uc); -void rh850_uc_init(struct uc_struct *uc); +void uc_init_rh850(struct uc_struct *uc); #endif diff --git a/samples/sample_rh850.c b/samples/sample_rh850.c index 8f74bf5e77..188eb8df0d 100644 --- a/samples/sample_rh850.c +++ b/samples/sample_rh850.c @@ -1,13 +1,13 @@ /* Unicorn Emulator Engine */ /* By Nguyen Anh Quynh, 2021 */ -/* Sample code to demonstrate how to emulate S390X code */ +/* Sample code to demonstrate how to emulate RH850 code */ -#include #include +#include // code to be emulated -#define RH850_CODE "\x01\x0e\x06\x00\xc1\x11\x01\x1f\x00\x00\x41\x1f\x00\x00" +#define RH850_CODE "\x01\x0e\x06\x00" // memory address where emulation starts #define ADDRESS 0x10000 @@ -27,41 +27,16 @@ static void hook_code(uc_engine *uc, uint64_t address, uint32_t size, address, size); } -static void hook_mem64(uc_engine *uc, uc_mem_type type, uint64_t address, - int size, int64_t value, void *user_data) -{ - uint64_t pc; - switch (type) { - default: - break; - case UC_MEM_READ: - uc_reg_read(uc, UC_RH850_REG_PC, &pc); - printf(">>> Memory read operation at 0x%" PRIx64 "\n", pc); - printf(">>> Memory is being READ at 0x%" PRIx64 ", data size = %u\n", - address, size); - break; - case UC_MEM_WRITE: - uc_reg_read(uc, UC_RH850_REG_PC, &pc); - printf(">>> Memory write operation at 0x%" PRIx64 "\n", pc); - printf(">>> Memory is being WRITE at 0x%" PRIx64 - ", data size = %u, data value = 0x%" PRIx64 "\n", - address, size, value); - break; - } -} - - -static void test_rh850(void) -{ +static void test_rh850(void) { uc_engine *uc; - uc_hook trace1, trace2, trace3; + uc_hook trace1, trace2; uc_err err; - uint64_t r1 = 0x10000, r2 = 3, r3; + uint64_t r1 = 0x10000; printf("Emulate RH850 code\n"); - // Initialize emulator in S390X mode + // Initialize emulator in RH850 mode err = uc_open(UC_ARCH_RH850, UC_MODE_LITTLE_ENDIAN, &uc); if (err) { printf("Failed on uc_open() with error returned: %u (%s)\n", err, @@ -77,7 +52,6 @@ static void test_rh850(void) // initialize machine registers uc_reg_write(uc, UC_RH850_REG_R1, &r1); - uc_reg_write(uc, UC_RH850_REG_R2, &r2); // tracing all basic blocks with customized callback uc_hook_add(uc, &trace1, UC_HOOK_BLOCK, hook_block, NULL, 1, 0); @@ -85,10 +59,6 @@ static void test_rh850(void) // tracing all instruction uc_hook_add(uc, &trace2, UC_HOOK_CODE, hook_code, NULL, 1, 0); - // tracing mem read - uc_hook_add(uc, &trace3, UC_HOOK_MEM_READ, hook_mem64, NULL, 1, 0); - uc_hook_add(uc, &trace3, UC_HOOK_MEM_WRITE, hook_mem64, NULL, 1, 0); - // emulate machine code in infinite time (last param = 0), or when // finishing all the code. err = uc_emu_start(uc, ADDRESS, ADDRESS + sizeof(RH850_CODE) - 1, 0, 0); @@ -101,17 +71,13 @@ static void test_rh850(void) printf(">>> Emulation done. Below is the CPU context\n"); uc_reg_read(uc, UC_RH850_REG_R1, &r1); - uc_reg_read(uc, UC_RH850_REG_R2, &r2); - uc_reg_read(uc, UC_RH850_REG_R3, &r3); - printf(">>> R1 = 0x%" PRIx64 "\t\t>>> R2 = 0x%" PRIx64 "\n", r1, r2); - printf(">>> R3 = 0x%" PRIx64 "\n", r3); + printf(">>> R1 = 0x%" PRIx64 "\t\t", r1); uc_close(uc); } -int main(int argc, char **argv, char **envp) -{ +int main() { test_rh850(); return 0; diff --git a/symbols.sh b/symbols.sh index 1fb5cdfc7e..b744f71e9f 100755 --- a/symbols.sh +++ b/symbols.sh @@ -7747,8 +7747,6 @@ tcg_s390_data_exception \ " rh850_SYMBOLS="restore_state_to_opc \ -helper_tlb_flush \ -helper_uc_rh850_exit \ gen_intermediate_code \ " diff --git a/tests/unit/test_rh850.c b/tests/unit/test_rh850.c index e02e704167..856b087c76 100644 --- a/tests/unit/test_rh850.c +++ b/tests/unit/test_rh850.c @@ -13,7 +13,7 @@ static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode, static void test_rh850_add(void) { - char code[] = "\x01\x0e\x06\x00\xc1\x11"; + char code[] = "\x01\x0e\x06\x00\xc1\x11"; uint32_t r1 = 0x1234; uint32_t r2 = 0x7777; uint32_t pc; diff --git a/uc.c b/uc.c index ea415e2171..5475b16030 100644 --- a/uc.c +++ b/uc.c @@ -451,11 +451,11 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result) #endif #ifdef UNICORN_HAS_RH850 case UC_ARCH_RH850: - if (mode != UC_MODE_LITTLE_ENDIAN) { + if (mode & ~UC_MODE_RH850_MASK) { free(uc); return UC_ERR_MODE; } - uc->init_arch = rh850_uc_init; + uc->init_arch = uc_init_rh850; break; #endif #ifdef UNICORN_HAS_RISCV