simplified find_subtile_in_location, improved commenting and updated results.

Author: haydar-c

vpr/src/place/initial_placement.cpp

@@ -148,18 +148,17 @@ static bool is_loc_legal(const t_pl_loc& loc,
                          t_logical_block_type_ptr block_type);
 
 /**
- * @brief  Helper function to choose a subtile in specified location if compatible and available one exits.
+ * @brief  Helper function to choose a subtile in specified location if the type is compatible and an available one exists.
  *  
- *   @param centroid The centroid location at which the subtile will be selected using its x,y, and layer.
- *   @param block_type Logical block type of the macro head member.  
- *   @param block_loc_registry Placement block location information. To be filled with the location
- *   where pl_macro is placed.
- *   @param pr The PartitionRegion of the macro head member - represents its floorplanning constraints, is the size of
- *   the whole chip if the macro is not constrained.
- *   @param rng A random number generator to select subtile from available and compatible ones.
+ *   @param centroid The centroid location at which the subtile will be selected using its x, y, and layer.
+ *   @param block_type Logical block type we would like to place here.
+ *   @param block_loc_registry Information on where other blocks have been placed.
+ *   @param pr The PartitionRegion of the block we are trying to place - represents its floorplanning constraints; 
+ *   it is the size of the whole chip if the block is not constrained.
+ *   @param rng A random number generator to select a subtile from the available and compatible ones.
  *
- * @return False if location on chip, legal, but no available subtile found. True otherwise. False leads us to
- * neighbour placement currently. 
+ * @return True if the location is on the chip, legal, and at least one available subtile is found at that location;
+ * false otherwise.
  */
 static bool find_subtile_in_location(t_pl_loc& centroid, 
                              t_logical_block_type_ptr block_type,
@@ -367,13 +366,13 @@ bool find_subtile_in_location(t_pl_loc& centroid,
                              vtr::RngContainer& rng) {
     //check if the location is on chip and legal, if yes try to update subtile
     if (is_loc_on_chip({centroid.x, centroid.y, centroid.layer}) &&  is_loc_legal(centroid, pr, block_type)) {
-        //finding the subtile location
+        //find the compatible subtiles
         const auto& device_ctx = g_vpr_ctx.device();
         const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index];
         const auto& type = device_ctx.grid.get_physical_type({centroid.x, centroid.y, centroid.layer});
         const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index);
 
-        //filter out occupied subtiles
+        //filter out the occupied subtiles
         const GridBlock& grid_blocks = blk_loc_registry.grid_blocks();
         std::vector<int> available_sub_tiles;
         available_sub_tiles.reserve(compatible_sub_tiles.size());
@@ -384,16 +383,13 @@ bool find_subtile_in_location(t_pl_loc& centroid,
             }
         }
 
-        //If there is at least one available subtile, update the centroid. Otherwise, sincel location
-        //is legal and on chip but no subtile found, return false for trying neighbour placement.
         if (!available_sub_tiles.empty()) {
             centroid.sub_tile = available_sub_tiles[rng.irand((int)available_sub_tiles.size() - 1)];
-        } else {
-            return false;
+            return true;
         }
     }
 
-    return true;
+    return false;
 }
 
 static bool find_centroid_neighbor(t_pl_loc& centroid_loc,
@@ -607,14 +603,14 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
     t_pl_loc centroid_loc(OPEN, OPEN, OPEN, OPEN);
     std::vector<ClusterBlockId> unplaced_blocks_to_update_their_score;
 
-    bool try_neighbour_due_to_subtile = false;
+    bool found_legal_subtile = false;
 
     if (!flat_placement_info.valid) {
         // If a flat placement is not provided, use the centroid of connected
         // blocks which have already been placed.
         unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
-        if(!find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
-            try_neighbour_due_to_subtile = true;
+        if(find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
+            found_legal_subtile = true;
         }
     } else {
         // If a flat placement is provided, use the flat placement to get the
@@ -628,8 +624,8 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
         if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer}) ||
             !is_loc_legal(centroid_loc, pr, block_type)) {
             unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
-            if(!find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
-                try_neighbour_due_to_subtile = true;
+            if(find_subtile_in_location(centroid_loc, block_type, blk_loc_registry, pr, rng)) {
+                found_legal_subtile = true;
             }
         }
     }
@@ -641,7 +637,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
 
     //centroid suggestion was either occupied or does not match block type
     //try to find a near location that meet these requirements
-    if (!is_loc_legal(centroid_loc, pr, block_type) || try_neighbour_due_to_subtile) {
+    if (!found_legal_subtile) {
         bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, blk_loc_registry, rng);
         if (!neighbor_legal_loc) { //no neighbor candidate found
             return false;

vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/blanket/config/golden_results.txt

@@ -1,4 +1,4 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
- k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	  0.52	  vpr	  66.02 MiB	  	  0.02	  7040	  -1	  -1	  1	  0.06	  -1	  -1	  35596	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67604	  6	  1	  13	  14	  2	  8	  9	  4	  4	  16	  clb	  auto	  27.5 MiB	  0.01	  18	  27	  14	  11	  2	  66.0 MiB	  0.00	  0.00	  1.02737	  -3.59667	  -1.02737	  0.545	  0.01	  5.3292e-05	  4.5019e-05	  0.000306591	  0.000256921	  -1	  -1	  -1	  -1	  20	  15	  7	  107788	  107788	  10441.3	  652.579	  0.01	  0.00211307	  0.00189921	  742	  1670	  -1	  17	  14	  34	  34	  409	  236	  1.40641	  0.545	  -4.27839	  -1.40641	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00189972	  0.00171949	 
- k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	  0.61	  vpr	  65.82 MiB	  	  0.02	  6912	  -1	  -1	  1	  0.06	  -1	  -1	  35588	  -1	  -1	  2	  3	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67396	  3	  1	  25	  26	  2	  8	  6	  4	  4	  16	  clb	  auto	  27.5 MiB	  0.02	  20	  15	  4	  1	  10	  65.8 MiB	  0.00	  0.00	  0.620042	  -8.9502	  -0.620042	  0.557849	  0.01	  8.2682e-05	  6.9909e-05	  0.000633195	  0.000565801	  -1	  -1	  -1	  -1	  20	  22	  1	  107788	  107788	  10441.3	  652.579	  0.01	  0.00358735	  0.00333372	  742	  1670	  -1	  27	  6	  18	  18	  703	  470	  0.865467	  0.557849	  -9.14332	  -0.865467	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00327369	  0.00304055	 
- k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	  0.48	  vpr	  66.14 MiB	  	  0.02	  6912	  -1	  -1	  1	  0.02	  -1	  -1	  33640	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67724	  6	  2	  10	  12	  2	  8	  10	  4	  4	  16	  clb	  auto	  27.8 MiB	  0.00	  19	  30	  14	  9	  7	  66.1 MiB	  0.00	  0.00	  0.620297	  -2.13808	  -0.620297	  nan	  0.01	  4.1509e-05	  3.0578e-05	  0.000200894	  0.000157769	  -1	  -1	  -1	  -1	  20	  27	  14	  107788	  107788	  10441.3	  652.579	  0.01	  0.00213275	  0.00183214	  742	  1670	  -1	  19	  15	  33	  33	  727	  463	  0.716884	  nan	  -2.60018	  -0.716884	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00208972	  0.00189128	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	  0.52	  vpr	  312.19 MiB	  	  0.02	  7040	  -1	  -1	  1	  0.06	  -1	  -1	  35596	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67604	  6	  1	  13	  14	  2	  8	  9	  4	  4	  16	  clb	  auto	  27.5 MiB	  0.01	  18	  27	  14	  11	  2	  66.0 MiB	  0.00	  0.00	  1.02737	  -3.59667	  -1.02737	  0.545	  0.01	  5.3292e-05	  4.5019e-05	  0.000306591	  0.000256921	  -1	  -1	  -1	  -1	  20	  15	  7	  107788	  107788	  10441.3	  652.579	  0.01	  0.00211307	  0.00189921	  742	  1670	  -1	  17	  14	  34	  34	  409	  236	  1.40641	  0.545	  -4.27839	  -1.40641	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00189972	  0.00171949	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	  0.61	  vpr	  313.48 MiB	  	  0.02	  6912	  -1	  -1	  1	  0.06	  -1	  -1	  35588	  -1	  -1	  2	  3	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67396	  3	  1	  25	  26	  2	  8	  6	  4	  4	  16	  clb	  auto	  27.5 MiB	  0.02	  20	  15	  4	  1	  10	  65.8 MiB	  0.00	  0.00	  0.620042	  -8.9502	  -0.620042	  0.557849	  0.01	  8.2682e-05	  6.9909e-05	  0.000633195	  0.000565801	  -1	  -1	  -1	  -1	  20	  22	  1	  107788	  107788	  10441.3	  652.579	  0.01	  0.00358735	  0.00333372	  742	  1670	  -1	  27	  6	  18	  18	  703	  470	  0.865467	  0.557849	  -9.14332	  -0.865467	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00327369	  0.00304055	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	  0.48	  vpr	  312.78 MiB	  	  0.02	  6912	  -1	  -1	  1	  0.02	  -1	  -1	  33640	  -1	  -1	  2	  6	  0	  0	  success	  v8.0.0-12164-g463dd1c36-dirty	  Release VTR_ASSERT_LEVEL=2	  GNU 11.4.0 on Linux-6.8.0-51-generic x86_64	  2025-02-20T15:42:53	  haydar-Precision-5820-Tower	  /home/haydar/vtr-verilog-to-routing	  67724	  6	  2	  10	  12	  2	  8	  10	  4	  4	  16	  clb	  auto	  27.8 MiB	  0.00	  19	  30	  14	  9	  7	  66.1 MiB	  0.00	  0.00	  0.620297	  -2.13808	  -0.620297	  nan	  0.01	  4.1509e-05	  3.0578e-05	  0.000200894	  0.000157769	  -1	  -1	  -1	  -1	  20	  27	  14	  107788	  107788	  10441.3	  652.579	  0.01	  0.00213275	  0.00183214	  742	  1670	  -1	  19	  15	  33	  33	  727	  463	  0.716884	  nan	  -2.60018	  -0.716884	  0	  0	  13748.8	  859.301	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00208972	  0.00189128