add OPIN--CHANZ edges

Author: soheilshahrouz

vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp

@@ -1017,7 +1017,7 @@ static void dijkstra_flood_to_wires(int itile,
 
         e_rr_type curr_rr_type = rr_graph.node_type(curr.node);
         int curr_layer_num = rr_graph.node_layer_low(curr.node);
-        if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY || curr_rr_type == e_rr_type::SINK) {
+        if (curr_rr_type == e_rr_type::CHANX || curr_rr_type == e_rr_type::CHANY || curr_rr_type == e_rr_type::CHANZ || curr_rr_type == e_rr_type::SINK) {
             //We stop expansion at any CHANX/CHANY/SINK
             int seg_index;
             if (curr_rr_type != e_rr_type::SINK) {

vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp

@@ -276,7 +276,7 @@ std::vector<t_bottleneck_link> alloc_and_load_scatter_gather_connections(const s
                                   scatter_loc.layer_num, scatter_loc.x, scatter_loc.y,
                                   scatter_wire_candidates.size());
 
-                    continue;
+                    // continue;
                 }
 
                 const bool is_3d_link = (sg_link.z_offset != 0);

vpr/src/route/rr_graph_generation/rr_graph.cpp

@@ -3,6 +3,8 @@
 #include <algorithm>
 #include <utility>
 #include <vector>
+#include <ranges>
+
 #include "alloc_and_load_rr_indexed_data.h"
 #include "build_scatter_gathers.h"
 #include "get_parallel_segs.h"
@@ -84,6 +86,15 @@ static vtr::NdMatrix<std::vector<int>, 4> alloc_and_load_pin_to_track_map(const
                                                                           const e_directionality directionality,
                                                                           const std::vector<t_segment_inf>& seg_inf,
                                                                           const std::vector<int>& sets_per_seg_type);
+
+static void add_edges_opin_chanz(RRGraphBuilder& rr_graph_builder,
+                                 const RRGraphView& rr_graph,
+                                 int layer, int x, int y,
+                                 const std::vector<vtr::Matrix<int>>& Fc_out,
+                                 const t_unified_to_parallel_seg_index& seg_index_map,
+                                 int num_seg_types,
+                                 t_rr_edge_info_set& rr_edges_to_create,
+                                 const std::vector<t_bottleneck_link>& interdie_3d_links);
 /**
  * @brief This routine calculates pin connections to tracks for a specific type and a specific segment based on the Fc value 
  * defined for each pin in the architecture file. This routine is called twice for each combination of block type and segment 
@@ -1293,13 +1304,7 @@ std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physi
 
     *Fc_clipped = false;
 
-    // Unidir tracks formed in pairs, otherwise no effect.
-    int fac = 1;
-    if (UNI_DIRECTIONAL == directionality) {
-        fac = 2;
-    }
-
-    VTR_ASSERT((nodes_per_chan->x_max % fac) == 0 && (nodes_per_chan->y_max % fac) == 0);
+    // VTR_ASSERT((nodes_per_chan->x_max % fac) == 0 && (nodes_per_chan->y_max % fac) == 0);
 
     for (const t_physical_tile_type& type : types) { // Skip EMPTY
         int itype = type.index;
@@ -1316,63 +1321,72 @@ std::vector<vtr::Matrix<int>> alloc_and_load_actual_fc(const std::vector<t_physi
                 for (int ipin : fc_spec.pins) {
                     Fc[itype][ipin][iseg] = 0;
                 }
-            } else {
-                // General case indicating that this pin connects to general-purpose routing
-
-                // Calculate how many connections there should be across all the pins in this fc_spec
-                int total_connections = 0;
-                if (fc_spec.fc_value_type == e_fc_value_type::FRACTIONAL) {
-                    float conns_per_pin = fac * sets_per_seg_type[iseg] * fc_spec.fc_value;
-                    float flt_total_connections = conns_per_pin * fc_spec.pins.size();
-                    total_connections = vtr::nint(flt_total_connections); //Round to integer
-                } else {
-                    VTR_ASSERT(fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE);
+                continue;
+            }
 
-                    if (std::fmod(fc_spec.fc_value, fac) != 0. && segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
-                        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Absolute Fc value must be a multiple of %d (was %f) between block pin '%s' and wire segment '%s'",
-                                        fac, fc_spec.fc_value,
-                                        block_type_pin_index_to_name(&type, fc_spec.pins[0], is_flat).c_str(),
-                                        segment_inf[iseg].name.c_str());
-                    }
+            // General case indicating that this pin connects to general-purpose routing
 
-                    if (fc_spec.fc_value < fac && segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
-                        VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Absolute Fc value must be at least %d (was %f) between block pin '%s' to wire segment %s",
-                                        fac, fc_spec.fc_value,
-                                        block_type_pin_index_to_name(&type, fc_spec.pins[0], is_flat).c_str(),
-                                        segment_inf[iseg].name.c_str());
-                    }
+            // Unidir tracks formed in pairs, otherwise no effect.
+            int fac = 1;
+            if (directionality == UNI_DIRECTIONAL && segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
+                fac = 2;
+            }
+
+            // Calculate how many connections there should be across all the pins in this fc_spec
+            int total_connections = 0;
+            if (fc_spec.fc_value_type == e_fc_value_type::FRACTIONAL) {
+                float conns_per_pin = fac * sets_per_seg_type[iseg] * fc_spec.fc_value;
+                float flt_total_connections = conns_per_pin * fc_spec.pins.size();
+                total_connections = vtr::nint(flt_total_connections); //Round to integer
+            } else {
+                VTR_ASSERT(fc_spec.fc_value_type == e_fc_value_type::ABSOLUTE);
 
-                    total_connections = vtr::nint(fc_spec.fc_value) * fc_spec.pins.size();
+                if (std::fmod(fc_spec.fc_value, fac) != 0. && segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
+                    VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Absolute Fc value must be a multiple of %d (was %f) between block pin '%s' and wire segment '%s'",
+                                    fac, fc_spec.fc_value,
+                                    block_type_pin_index_to_name(&type, fc_spec.pins[0], is_flat).c_str(),
+                                    segment_inf[iseg].name.c_str());
                 }
 
-                // Ensure that there are at least fac connections, this ensures that low Fc ports
-                // targeting small sets of segs get connection(s), even if flt_total_connections < fac.
-                total_connections = std::max(total_connections, fac);
-
-                // Ensure total evenly divides fac by adding the remainder
-                total_connections += (total_connections % fac);
-
-                VTR_ASSERT(total_connections > 0);
-                VTR_ASSERT(total_connections % fac == 0);
-
-                // We walk through all the pins this fc_spec applies to, adding fac connections
-                // to each pin, until we run out of connections. This should distribute the connections
-                // as evenly as possible (if total_connections % pins.size() != 0, there will be
-                // some inevitable imbalance).
-                int connections_remaining = total_connections;
-                while (connections_remaining != 0) {
-                    // Add one set of connections to each pin
-                    for (int ipin : fc_spec.pins) {
-                        if (connections_remaining >= fac) {
-                            Fc[itype][ipin][iseg] += fac;
-                            connections_remaining -= fac;
-                        } else {
-                            VTR_ASSERT(connections_remaining == 0);
-                            break;
-                        }
+                if (fc_spec.fc_value < fac && segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
+                    VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Absolute Fc value must be at least %d (was %f) between block pin '%s' to wire segment %s",
+                                    fac, fc_spec.fc_value,
+                                    block_type_pin_index_to_name(&type, fc_spec.pins[0], is_flat).c_str(),
+                                    segment_inf[iseg].name.c_str());
+                }
+
+                total_connections = vtr::nint(fc_spec.fc_value) * fc_spec.pins.size();
+            }
+
+            // Ensure that there are at least fac connections, this ensures that low Fc ports
+            // targeting small sets of segs get connection(s), even if flt_total_connections < fac.
+            total_connections = std::max(total_connections, fac);
+
+            // Ensure total evenly divides fac by adding the remainder
+            total_connections += (total_connections % fac);
+
+            VTR_ASSERT(total_connections > 0);
+            VTR_ASSERT(total_connections % fac == 0);
+
+            // We walk through all the pins this fc_spec applies to, adding fac connections
+            // to each pin, until we run out of connections. This should distribute the connections
+            // as evenly as possible (if total_connections % pins.size() != 0, there will be
+            // some inevitable imbalance).
+            int connections_remaining = total_connections;
+            while (connections_remaining != 0) {
+                // Add one set of connections to each pin
+                for (int ipin : fc_spec.pins) {
+                    if (connections_remaining >= fac) {
+                        Fc[itype][ipin][iseg] += fac;
+                        connections_remaining -= fac;
+                    } else {
+                        VTR_ASSERT(connections_remaining == 0);
+                        break;
                     }
                 }
+            }
 
+            if (segment_inf[iseg].parallel_axis != e_parallel_axis::Z_AXIS) {
                 for (int ipin : fc_spec.pins) {
                     // It is possible that we may want more connections that wires of this type exist;
                     // clip to the maximum number of wires
@@ -1515,13 +1529,21 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
                             *Fc_clipped = true;
                         }
                     }
-
-                    // Create the actual OPIN->CHANX/CHANY edges
-                    uniquify_edges(rr_edges_to_create);
-                    alloc_and_load_edges(rr_graph_builder, rr_edges_to_create);
-                    num_edges += rr_edges_to_create.size();
-                    rr_edges_to_create.clear();
                 }
+
+                add_edges_opin_chanz(rr_graph_builder, rr_graph,
+                                 layer, i, j,
+                                 Fc_out,
+                                 seg_index_map,
+                                 num_seg_types,
+                                 rr_edges_to_create,
+                                 interdie_3d_links[i][j]);
+
+                // Create the actual OPIN->CHANX/CHANY edges
+                uniquify_edges(rr_edges_to_create);
+                alloc_and_load_edges(rr_graph_builder, rr_edges_to_create);
+                num_edges += rr_edges_to_create.size();
+                rr_edges_to_create.clear();
             }
         }
     }
@@ -2800,6 +2822,57 @@ static vtr::NdMatrix<std::vector<int>, 4> alloc_and_load_track_to_pin_lookup(vtr
     return track_to_pin_lookup;
 }
 
+static void add_edges_opin_chanz(RRGraphBuilder& rr_graph_builder,
+                                 const RRGraphView& rr_graph,
+                                 int layer, int x, int y,
+                                 const std::vector<vtr::Matrix<int>>& Fc_out,
+                                 const t_unified_to_parallel_seg_index& seg_index_map,
+                                 int num_seg_types,
+                                 t_rr_edge_info_set& rr_edges_to_create,
+                                 const std::vector<t_bottleneck_link>& interdie_3d_links) {
+    const RRSpatialLookup& node_lookup = rr_graph.node_lookup();
+    const DeviceGrid& grid = g_vpr_ctx.device().grid;
+
+    t_physical_tile_type_ptr type = grid.get_physical_type({x, y, layer});
+
+    std::vector<RRNodeId> opin_nodes = node_lookup.find_grid_nodes_at_all_sides(layer, x, y, e_rr_type::OPIN);
+    std::ranges::stable_sort(opin_nodes, std::less<>{}, [](RRNodeId id) noexcept { return size_t(id); });
+    // Remove adjacent duplicates
+    auto [unique_end, _] = std::ranges::unique(opin_nodes);
+    opin_nodes.erase(unique_end, opin_nodes.end());
+
+    std::vector<std::pair<RRNodeId, short>> selected_chanz_nodes;
+
+    for (int iseg = 0; iseg < num_seg_types; iseg++) {
+        int seg_index = get_parallel_seg_index(iseg, seg_index_map, e_parallel_axis::Z_AXIS);
+        if (seg_index < 0) {
+            continue;
+        }
+
+        selected_chanz_nodes.clear();
+        for (size_t track_num = 0; track_num < interdie_3d_links.size(); track_num++) {
+            const t_bottleneck_link& bottleneck_link = interdie_3d_links[track_num];
+            if (bottleneck_link.parallel_segment_index == seg_index && bottleneck_link.gather_loc.layer_num == layer) {
+                RRNodeId node_id = node_lookup.find_node(layer, x, y, e_rr_type::CHANZ, track_num);
+                selected_chanz_nodes.push_back({node_id, bottleneck_link.arch_wire_switch});
+            }
+        }
+
+        int chanz_idx = 0;
+        for (RRNodeId opin_node_id : opin_nodes) {
+            int pin_number = rr_graph.node_pin_num(opin_node_id);
+            int fc = Fc_out[type->index][pin_number][iseg];
+
+            for (int i = 0; i < fc; i++) {
+                RRNodeId chanz_node_id = selected_chanz_nodes[chanz_idx % selected_chanz_nodes.size()].first;
+                short switch_id = selected_chanz_nodes[chanz_idx % selected_chanz_nodes.size()].second;
+                chanz_idx++;
+                rr_edges_to_create.emplace_back(opin_node_id, chanz_node_id, switch_id, false);
+            }
+        }
+    }
+}
+
 static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
                                   const RRGraphView& rr_graph,
                                   const int layer,
@@ -2824,7 +2897,6 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder,
     *Fc_clipped = false;
 
     t_physical_tile_type_ptr type = grid.get_physical_type({i, j, layer});
-
     int width_offset = grid.get_width_offset({i, j, layer});
     int height_offset = grid.get_height_offset({i, j, layer});