File tree Expand file tree Collapse file tree 3 files changed +60
-1
lines changed
vtr_flow/tasks/regression_tests/vtr_reg_strong
strong_slang_parser/config Expand file tree Collapse file tree 3 files changed +60
-1
lines changed Original file line number Diff line number Diff line change 1+ #
2+ ############################################
3+ # Configuration file for running experiments
4+ ##############################################
5+
6+ # Path to directory of circuits to use
7+ circuits_dir=benchmarks/verilog
8+
9+ # Path to directory of architectures to use
10+ archs_dir=arch/timing
11+
12+ # Add circuits to list to sweep
13+ # circuit_list_add=arm_core.v
14+ circuit_list_add=boundtop_nolatches.v
15+ circuit_list_add=ch_intrinsics_nolatches.v
16+ circuit_list_add=diffeq1.v
17+ circuit_list_add=diffeq2.v
18+ # circuit_list_add=or1200.v
19+ circuit_list_add=raygentop_nolatches.v
20+ circuit_list_add=stereovision3.v
21+
22+ # Add architectures to list to sweep
23+ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
24+
25+ # Parse info and how to parse
26+ parse_file=vpr_fixed_chan_width.txt
27+
28+ # How to parse QoR info
29+ qor_parse_file=qor_fixed_chan_width.txt
30+
31+ # Pass requirements
32+ pass_requirements_file=pass_requirements_fixed_chan_width.txt
33+
34+ #Script parameters
35+ script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang --route_chan_width 128
36+
You can’t perform that action at this time.
0 commit comments