updated golden

Author: WhiteNinjaZ

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_xilinx_flagship/config/golden_results.txt

@@ -1,3 +1,3 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
-7series_BRAM_DSP_carry.xml	stereovision3.v	common	2.53	vpr	72.59 MiB		-1	-1	0.33	26408	4	0.08	-1	-1	36120	-1	-1	-1	11	0	-1	success	v8.0.0-13067-gda604502c-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-06-16T13:26:41	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	74336	11	2	303	283	2	114	35	7	7	49	CLB	auto	33.2 MiB	1.18	577.007	408	947	108	584	255	72.6 MiB	0.01	0.00	3.1717	3.1717	-180.982	-3.1717	2.89952	0.12	0.000171885	0.000143559	0.00458104	0.00401289	-1	-1	-1	-1	40	889	22	1.34735e+06	1.18567e+06	152291.	3107.98	0.22	0.0179847	0.0160687	6668	73471	-1	385	12	297	988	127228	60728	2.91111	2.8252	-221.503	-2.91111	-2.452	-0.04	215465.	4397.25	0.02	0.02	0.04	-1	-1	0.02	0.00962131	0.00895172	
+7series_BRAM_DSP_carry.xml	stereovision3.v	common	17.86	vpr	72.59 MiB		-1	-1	0.33	26408	4	0.08	-1	-1	36120	-1	-1	-1	11	0	-1	success	v8.0.0-13067-gda604502c-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-06-16T13:26:41	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	74336	11	2	303	283	2	114	35	7	7	49	CLB	auto	33.2 MiB	1.18	577.007	408	947	108	584	255	72.6 MiB	0.01	0.00	3.1717	3.1717	-180.982	-3.1717	2.89952	0.12	0.000171885	0.000143559	0.00458104	0.00401289	-1	-1	-1	-1	40	889	22	1.34735e+06	1.18567e+06	152291.	3107.98	0.22	0.0179847	0.0160687	6668	73471	-1	385	12	297	988	127228	60728	2.91111	2.8252	-221.503	-2.91111	-2.452	-0.04	215465.	4397.25	0.02	0.02	0.04	-1	-1	0.02	0.00962131	0.00895172	
 7series_BRAM_DSP_carry.xml	diffeq2.v	common	48.98	vpr	129.37 MiB		-1	-1	0.19	27844	5	0.09	-1	-1	38944	-1	-1	-1	66	0	-1	success	v8.0.0-13067-gda604502c-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-5.15.0-119-generic x86_64	2025-06-16T13:26:41	goeders10	/home/chem3000/GitClones/vtr_pulls/vtr_ccl/vtr-verilog-to-routing/vtr_flow/tasks	132476	66	96	1819	1080	1	1150	336	26	26	676	DSP	auto	40.6 MiB	2.77	20198.7	9188	64521	14520	45607	4394	119.7 MiB	0.65	0.01	22.6842	19.668	-1065.49	-19.668	19.668	3.45	0.000811128	0.000723384	0.0536543	0.0478746	-1	-1	-1	-1	74	12093	17	3.53732e+07	1.31407e+07	5.36197e+06	7931.91	33.65	0.395666	0.356239	133518	2720184	-1	10986	14	5828	10018	3165525	816384	19.4143	19.4143	-1210.49	-19.4143	-1.7	-0.034	6.54552e+06	9682.72	1.89	0.38	1.55	-1	-1	1.89	0.0458825	0.0428936