diff --git a/libs/libarchfpga/src/grid_types.h b/libs/libarchfpga/src/grid_types.h index 9929efbac1c..25237a85504 100644 --- a/libs/libarchfpga/src/grid_types.h +++ b/libs/libarchfpga/src/grid_types.h @@ -8,7 +8,7 @@ #include #include -// Forward declerations +// Forward declarations struct t_metadata_dict; @@ -112,7 +112,6 @@ struct t_grid_loc_def { * @brief When 1 metadata tag is split among multiple t_grid_loc_def, one * t_grid_loc_def is arbitrarily chosen to own the metadata, and the other * t_grid_loc_def point to the owned version. - * */ std::unique_ptr owned_meta; @@ -125,7 +124,7 @@ struct t_grid_loc_def { }; /** - * @brief Enum for specfying if the architecture grid specification is for an auto sized device (variable size) + * @brief Enum for specifying if the architecture grid specification is for an auto sized device (variable size) * or a fixed size device. */ enum class e_grid_def_type { diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 54e364b4b12..cc57490a520 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -2,6 +2,7 @@ #include "arch_types.h" #include "vtr_math.h" #include "vtr_util.h" +#include "vtr_assert.h" #include "arch_util.h" @@ -408,3 +409,13 @@ const t_physical_tile_port* t_sub_tile::get_port_by_pin(int pin) const { return nullptr; } + +const t_grid_def& t_arch::grid_layout() const { + for (const t_grid_def& layout : grid_layouts) { + if (layout.name == device_layout) { + return layout; + } + } + VTR_ASSERT_SAFE_MSG(false, "Device layout not found."); + return grid_layouts.front(); // unreachable, keeps compiler happy +} diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 1a529b1f2e2..84c8009b98d 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -2067,7 +2067,11 @@ struct t_arch { // types of connections requires a different switch, all names should correspond to a switch in Switches. std::vector ipin_cblock_switch_name; - std::vector grid_layouts; //Set of potential device layouts + /// Set of potential device layouts + std::vector grid_layouts; + + /// @brief Returns the grid layout specified by the --device command-line option. + const t_grid_def& grid_layout() const; // the layout that is chosen to be used with command line options // It is used to generate custom SB for a specific locations within the device diff --git a/libs/libarchfpga/src/scatter_gather_types.h b/libs/libarchfpga/src/scatter_gather_types.h index 5408cf560f0..f3da8ffd020 100644 --- a/libs/libarchfpga/src/scatter_gather_types.h +++ b/libs/libarchfpga/src/scatter_gather_types.h @@ -14,17 +14,20 @@ enum class e_scatter_gather_type { }; /** - * @brief Struct containing information of an tag. An tag instantiates the scatter-gather pattern in some switchblock locations around the device. + * @brief Struct containing information of an tag. + * An tag instantiates the scatter-gather pattern in some switchblock locations within the device. + * `region` is only valid if type == e_sb_location::E_XY_SPECIFIED. */ struct t_sg_location { e_sb_location type; ///< Type of locations that the pattern is instantiated at. + t_specified_loc region; ///< Specification of the region where gather is applied int num; ///< Number of scatter-gather pattern instantiations per location. std::string sg_link_name; ///< Name of scatter-gather link to be used. }; /** - * @brief Struct containing information of a tag. This tag describes how and where the scatter (fanout) happens relative to the gather (fanin). - * + * @brief Struct containing information of a tag. + * This tag describes how and where the scatter (fanout) happens relative to the gather (fanin). */ struct t_sg_link { std::string name; ///< Name of the sg_link. diff --git a/libs/libarchfpga/src/switchblock_types.h b/libs/libarchfpga/src/switchblock_types.h index 0e1255d5311..68e3624eaa7 100644 --- a/libs/libarchfpga/src/switchblock_types.h +++ b/libs/libarchfpga/src/switchblock_types.h @@ -81,9 +81,7 @@ inline const std::unordered_map SB_LOCATION_STRING_M {"FRINGE", e_sb_location::E_FRINGE}, {"XY_SPECIFIED", e_sb_location::E_XY_SPECIFIED}}; -/** - * @brief Describes regions that a specific switch block specifications should be applied to - */ +/// @brief Describes regions that a specific switch block specifications should be applied to struct t_sb_loc_spec { int start = -1; int repeat = -1; @@ -97,8 +95,8 @@ struct t_sb_loc_spec { class SBSideConnection { public: // Specify the two SB sides that form a connection - enum e_side from_side = TOP; - enum e_side to_side = TOP; + e_side from_side = TOP; + e_side to_side = TOP; void set_sides(enum e_side from, enum e_side to) { from_side = from; diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 6e14f81d233..c7dc208c5e3 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -556,7 +556,7 @@ void check_rr_node(const RRGraphView& rr_graph, float C = rr_graph.node_C(rr_node); float R = rr_graph.node_R(rr_node); - if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) { + if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY || rr_type == e_rr_type::CHANZ) { if (C < 0. || R < 0.) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: node %d of type %d has R = %g and C = %g.\n", inode, rr_type, R, C); diff --git a/libs/librrgraph/src/base/rr_rc_data.cpp b/libs/librrgraph/src/base/rr_rc_data.cpp index 438f4c0633c..0a402c754a3 100644 --- a/libs/librrgraph/src/base/rr_rc_data.cpp +++ b/libs/librrgraph/src/base/rr_rc_data.cpp @@ -4,24 +4,24 @@ t_rr_rc_data::t_rr_rc_data(float Rval, float Cval) noexcept : R(Rval) , C(Cval) {} -short find_create_rr_rc_data(const float R, const float C, std::vector& rr_rc_data) { +NodeRCIndex find_create_rr_rc_data(const float R, const float C, std::vector& rr_rc_data) { auto match = [&](const t_rr_rc_data& val) { return val.R == R && val.C == C; }; - //Just a linear search for now + // Just a linear search for now auto itr = std::find_if(rr_rc_data.begin(), rr_rc_data.end(), match); if (itr == rr_rc_data.end()) { - //Not found -> create it + // Not found -> create it rr_rc_data.emplace_back(R, C); - itr = --rr_rc_data.end(); //Iterator to inserted value + itr = --rr_rc_data.end(); // Iterator to inserted value } - return std::distance(rr_rc_data.begin(), itr); + return NodeRCIndex(std::distance(rr_rc_data.begin(), itr)); } diff --git a/libs/librrgraph/src/base/rr_rc_data.h b/libs/librrgraph/src/base/rr_rc_data.h index b545deb1c11..882682e270b 100644 --- a/libs/librrgraph/src/base/rr_rc_data.h +++ b/libs/librrgraph/src/base/rr_rc_data.h @@ -10,4 +10,4 @@ * * The returned indicies index into DeviceContext.rr_rc_data. */ -short find_create_rr_rc_data(const float R, const float C, std::vector& rr_rc_data); +NodeRCIndex find_create_rr_rc_data(const float R, const float C, std::vector& rr_rc_data); diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 629227fdffc..3f76fa47f25 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -806,7 +806,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline int init_node_timing(int& inode, float C, float R) final { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); - rr_graph_builder_->set_node_rc_index(node_id, NodeRCIndex(find_create_rr_rc_data(R, C, *rr_rc_data_))); + const NodeRCIndex rc_index = find_create_rr_rc_data(R, C, *rr_rc_data_); + rr_graph_builder_->set_node_rc_index(node_id, rc_index); return inode; } inline void finish_node_timing(int& /*inode*/) final {} @@ -934,7 +935,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { type); } - rr_graph_builder_->set_node_rc_index(node_id, NodeRCIndex(find_create_rr_rc_data(0, 0, *rr_rc_data_))); + rr_graph_builder_->set_node_rc_index(node_id, find_create_rr_rc_data(0, 0, *rr_rc_data_)); return id; } diff --git a/libs/libvtrutil/src/vtr_expr_eval.cpp b/libs/libvtrutil/src/vtr_expr_eval.cpp index c8185bf8d4b..1099065b5c0 100644 --- a/libs/libvtrutil/src/vtr_expr_eval.cpp +++ b/libs/libvtrutil/src/vtr_expr_eval.cpp @@ -8,7 +8,8 @@ /** global variables **/ -/** bp_state_globals is a variable that holds a member of type BreakpointState. This member is altered by the breakpoint class, the placer, and router and holds the most updated values for variables that can trigger breakpoints (e.g move_num, temp_num etc.) **/ +/// Holds a member of type BreakpointState. +/// This member is altered by the breakpoint class, the placer, and router and holds the most updated values for variables that can trigger breakpoints (e.g move_num, temp_num etc.) **/ BreakpointStateGlobals bp_state_globals; namespace vtr { diff --git a/vpr/src/draw/breakpoint_state_globals.h b/vpr/src/draw/breakpoint_state_globals.h index 7ca1a0c433e..bed25a5d680 100644 --- a/vpr/src/draw/breakpoint_state_globals.h +++ b/vpr/src/draw/breakpoint_state_globals.h @@ -3,19 +3,21 @@ #include #include -//the BreakpointState struct holds all values that could possibly trigger a breakpoint -//some variables such as move_num, from_block, temp_count, blocks_affected are related to the placer and router_iter and net_id are related to the router -//there is also a string that holds the breakpoint description that are displayed in the UI and printed to the terminal -//these values are updated in place.cpp and route.cpp and expr_eval.cpp and breakpoint.cpp use these values to look for breakpoints +/** + * @brief Holds all values that could possibly trigger a breakpoint. + * Some variables such as move_num, from_block, temp_count, blocks_affected are related to the placer and router_iter and net_id are related to the router. + * There is also a string that holds the breakpoint description that are displayed in the UI and printed to the terminal. + * These values are updated in place.cpp and route.cpp and expr_eval.cpp and breakpoint.cpp use these values to look for breakpoints. + */ struct BreakpointState { - int move_num = 0; //current number of completed placer moves - int from_block = -1; //first block moved in the current placement swap - int temp_count = 0; //number of temperature changes thus far - int block_affected = -1; //the block_id that was requested to be stopped at if in blocks_affected - std::vector blocks_affected_by_move; //vector giving the clb netlist block ids of all blocks moving in the current perturbation - int route_net_id = -1; //clb netlist id of net that was just routed - int router_iter = 0; //current rip-up and re-route iteration count of router - std::string bp_description; //the breakpoint description to appear in the breakpoint list in the GUI + int move_num = 0; ///< Current number of completed placer moves + int from_block = -1; ///< First block moved in the current placement swap + int temp_count = 0; ///< Number of temperature changes thus far + int block_affected = -1; ///< The block_id that was requested to be stopped at if in blocks_affected + std::vector blocks_affected_by_move; ///< Vector giving the clb netlist block ids of all blocks moving in the current perturbation + int route_net_id = -1; ///< clb netlist id of net that was just routed + int router_iter = 0; ///< Current rip-up and re-route iteration count of router + std::string bp_description; ///< The breakpoint description to appear in the breakpoint list in the GUI }; class BreakpointStateGlobals { diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 4e0cc414b4f..0dec7e8f1e9 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -66,9 +66,9 @@ #include "draw_rr.h" /****************************** Define Macros *******************************/ -#define DEFAULT_RR_NODE_COLOR ezgl::BLACK -#define OLD_BLK_LOC_COLOR blk_GOLD -#define NEW_BLK_LOC_COLOR blk_GREEN +static constexpr ezgl::color DEFAULT_RR_NODE_COLOR = ezgl::BLACK; +static constexpr ezgl::color OLD_BLK_LOC_COLOR = blk_GOLD; +static constexpr ezgl::color NEW_BLK_LOC_COLOR = blk_GREEN; //#define TIME_DRAWSCREEN /* Enable if want to track runtime for drawscreen() */ void act_on_key_press(ezgl::application* /*app*/, GdkEventKey* /*event*/, char* key_name); @@ -180,13 +180,13 @@ static void draw_main_canvas(ezgl::renderer* g) { g->set_font_size(14); if (draw_state->pic_on_screen != e_pic_type::ANALYTICAL_PLACEMENT) { draw_block_pin_util(); - drawplace(g); + draw_place(g); draw_internal_draw_subblk(g); draw_interposer_cuts(g); draw_block_pin_util(); - drawplace(g); + draw_place(g); draw_internal_draw_subblk(g); if (draw_state->pic_on_screen == e_pic_type::ROUTING) { // ROUTING on screen @@ -301,10 +301,11 @@ void update_screen(ScreenUpdatePriority priority, strcpy(draw_state->default_message, msg); - if (!draw_state->show_graphics) + if (!draw_state->show_graphics) { ezgl::set_disable_event_loop(true); - else + } else { ezgl::set_disable_event_loop(false); + } bool state_change = false; @@ -462,9 +463,9 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { const DeviceGrid& grid = device_ctx.grid; const RRGraphView& rr_graph = device_ctx.rr_graph; - /* Store a reference to block location variables so that other drawing - * functions can access block location information without accessing - * the global placement state, which is inaccessible during placement.*/ + // Store a reference to block location variables so that other drawing + // functions can access block location information without accessing + // the global placement state, which is inaccessible during placement. draw_state->set_graphics_blk_loc_registry_ref(blk_loc_registry); // do not initialize only if --disp off and --save_graphics off @@ -472,8 +473,8 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { return; } - /* Each time routing is on screen, need to reallocate the color of each * - * rr_node, as the number of rr_nodes may change. */ + // Each time routing is on screen, need to reallocate the color of each + // rr_node, as the number of rr_nodes may change. if (rr_graph.num_nodes() != 0) { draw_state->draw_rr_node.resize(rr_graph.num_nodes()); for (RRNodeId inode : rr_graph.nodes()) { @@ -481,35 +482,34 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { draw_state->draw_rr_node[inode].node_highlighted = false; } } + draw_coords->set_tile_width(clb_width); draw_coords->pin_size = 0.3; - for (const auto& type : device_ctx.physical_tile_types) { + for (const t_physical_tile_type& type : device_ctx.physical_tile_types) { int num_pins = type.num_pins; if (num_pins > 0) { draw_coords->pin_size = std::min(draw_coords->pin_size, - (draw_coords->get_tile_width() / (4.0F * num_pins))); + draw_coords->get_tile_width() / (4.0F * num_pins)); } } size_t j = 0; for (size_t i = 0; i < grid.width() - 1; i++) { - draw_coords->tile_x[i] = (i * draw_coords->get_tile_width()) + j; + draw_coords->tile_x[i] = i * draw_coords->get_tile_width() + j; j += device_ctx.rr_chany_width[i] + 1; // N wires need N+1 units of space } draw_coords->tile_x[grid.width() - 1] = (grid.width() - 1) * draw_coords->get_tile_width() + j; j = 0; - for (size_t i = 0; i < device_ctx.grid.height() - 1; ++i) { - draw_coords->tile_y[i] = (i * draw_coords->get_tile_width()) + j; + for (size_t i = 0; i < grid.height() - 1; ++i) { + draw_coords->tile_y[i] = i * draw_coords->get_tile_width() + j; j += device_ctx.rr_chanx_width[i] + 1; } draw_coords->tile_y[grid.height() - 1] = (grid.height() - 1) * draw_coords->get_tile_width() + j; - /* Load coordinates of sub-blocks inside the clbs */ + // Load coordinates of sub-blocks inside the clbs draw_internal_init_blk(); - //Margin beyond edge of the drawn device to extend the visible world - //Setting this to > 0.0 means 'Zoom Fit' leave some fraction of white - //space around the device edges + #else (void)clb_width; (void)blk_loc_registry; @@ -519,12 +519,16 @@ void init_draw_coords(float clb_width, const BlkLocRegistry& blk_loc_registry) { #ifndef NO_GRAPHICS void set_initial_world() { - constexpr float VISIBLE_MARGIN = 0.01; t_draw_coords* draw_coords = get_draw_coords_vars(); - const DeviceContext& device_ctx = g_vpr_ctx.device(); + const DeviceGrid& grid = g_vpr_ctx.device().grid; - float draw_width = draw_coords->tile_x[device_ctx.grid.width() - 1] + draw_coords->get_tile_width(); - float draw_height = draw_coords->tile_y[device_ctx.grid.height() - 1] + draw_coords->get_tile_width(); + // Margin beyond edge of the drawn device to extend the visible world + // Setting this to > 0.0 means 'Zoom Fit' leave some fraction of white + // space around the device edges + constexpr float VISIBLE_MARGIN = 0.01; + + float draw_width = draw_coords->tile_x[grid.width() - 1] + draw_coords->get_tile_width(); + float draw_height = draw_coords->tile_y[grid.height() - 1] + draw_coords->get_tile_width(); initial_world = ezgl::rectangle( {-VISIBLE_MARGIN * draw_width, -VISIBLE_MARGIN * draw_height}, @@ -549,8 +553,6 @@ void set_initial_world_ap() { int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vtr::OffsetMatrix& chany_track) { /* Returns the track number of this routing resource node. */ - - int i, j; e_rr_type rr_type; const DeviceContext& device_ctx = g_vpr_ctx.device(); const RRGraphView& rr_graph = device_ctx.rr_graph; @@ -562,8 +564,8 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt /* GLOBAL route stuff below. */ rr_type = rr_graph.node_type(rr_node); - i = rr_graph.node_xlow(rr_node); /* NB: Global rr graphs must have only unit */ - j = rr_graph.node_ylow(rr_node); /* length channel segments. */ + int i = rr_graph.node_xlow(rr_node); // Global rr graphs must have only unit + int j = rr_graph.node_ylow(rr_node); // length channel segments. switch (rr_type) { case e_rr_type::CHANX: @@ -1155,7 +1157,7 @@ static void set_force_pause(GtkWidget* /*widget*/, gint /*response_id*/, gpointe } static void run_graphics_commands(const std::string& commands) { - //A very simmple command interpreter for scripting graphics + // A very simple command interpreter for scripting graphics t_draw_state* draw_state = get_draw_state_vars(); t_draw_state backup_draw_state = *draw_state; @@ -1250,7 +1252,7 @@ static void run_graphics_commands(const std::string& commands) { } } - *draw_state = backup_draw_state; //Restor original draw state + *draw_state = backup_draw_state; // Restore original draw state //Advance the sequence number ++draw_state->sequence_number; diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index f120c6d5a0c..3634b846b81 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -8,7 +8,6 @@ #include #include #include -#include #include "physical_types_util.h" #include "vtr_assert.h" @@ -38,12 +37,9 @@ #include "route_utilization.h" #include "place_macro.h" -/****************************** Define Macros *******************************/ -#define DEFAULT_RR_NODE_COLOR ezgl::BLACK -#define OLD_BLK_LOC_COLOR blk_GOLD -#define NEW_BLK_LOC_COLOR blk_GREEN - -constexpr float EMPTY_BLOCK_LIGHTEN_FACTOR = 0.20; +// Constant values used in this file +static constexpr ezgl::color DEFAULT_RR_NODE_COLOR = ezgl::BLACK; +static constexpr float EMPTY_BLOCK_LIGHTEN_FACTOR = 0.20; const std::vector kelly_max_contrast_colors = { //ezgl::color(242, 243, 244), //white: skip white since it doesn't contrast well with VPR's light background @@ -70,119 +66,108 @@ const std::vector kelly_max_contrast_colors = { ezgl::color(43, 61, 38) //olive green }; -/* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * - * while empty ones are lighter colours and have a dashed border. */ -void drawplace(ezgl::renderer* g) { +/// @brief Determines the display color for a given block location. +/// @details If a placer breakpoint highlight applies, uses its color; otherwise, +/// derives the color from the block assignment or lightens the base tile color +/// for empty locations. +static void determine_block_color(const t_pl_loc& loc, + ClusterBlockId bnum, + t_physical_tile_type_ptr type, + t_draw_state* draw_state, + ezgl::color& block_color) { + // Highlight if breakpoint reached + if (placer_breakpoint_reached()) { + if (highlight_loc_with_specific_color(loc, block_color)) { + return; + } + } + + // Otherwise, use normal block or tile color + if (bnum) { + block_color = draw_state->block_color(bnum); + } else { + block_color = lighten_color(get_block_type_color(type), + EMPTY_BLOCK_LIGHTEN_FACTOR); + } +} + +void draw_place(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); t_draw_coords* draw_coords = get_draw_coords_vars(); const DeviceContext& device_ctx = g_vpr_ctx.device(); + const DeviceGrid& grid = device_ctx.grid; const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering(); - const auto& grid_blocks = draw_state->get_graphics_blk_loc_registry_ref().grid_blocks(); - - ClusterBlockId bnum; - int num_sub_tiles; + const GridBlock& grid_blocks = draw_state->get_graphics_blk_loc_registry_ref().grid_blocks(); - int total_num_layers = device_ctx.grid.get_num_layers(); + const int total_num_layers = grid.get_num_layers(); g->set_line_width(0); for (int layer_num = 0; layer_num < total_num_layers; layer_num++) { - if (draw_state->draw_layer_display[layer_num].visible) { - for (int i = 0; i < (int)device_ctx.grid.width(); i++) { - for (int j = 0; j < (int)device_ctx.grid.height(); j++) { - /* Only the first block of a group should control drawing */ - const auto& type = device_ctx.grid.get_physical_type({i, j, layer_num}); - int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num}); - int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num}); - - //The transparency level for the current layer being drawn (0-255) - // 0 - opaque, 255 - transparent - int transparency_factor = draw_state->draw_layer_display[layer_num].alpha; - - if (width_offset > 0 - || height_offset > 0) - continue; - - num_sub_tiles = type->capacity; - /* Don't draw if tile capacity is zero. eg-> corners. */ - if (num_sub_tiles == 0) { - continue; - } + if (!draw_state->draw_layer_display[layer_num].visible) { + continue; + } + // The transparency level for the current layer being drawn (0-255) + const int transparency_factor = draw_state->draw_layer_display[layer_num].alpha; - for (int k = 0; k < num_sub_tiles; ++k) { - /* Look at the tile at start of large block */ - bnum = grid_blocks.block_at_location({i, j, k, layer_num}); - /* Fill background for the clb. Do not fill if "show_blk_internal" - * is toggled. - */ - - //Determine the block color and logical type - ezgl::color block_color; - t_logical_block_type_ptr logical_block_type = nullptr; - - //flag whether the current location is highlighted with a special color or not - bool current_loc_is_highlighted = false; - - if (placer_breakpoint_reached()) { - t_pl_loc curr_loc; - curr_loc.x = i; - curr_loc.y = j; - curr_loc.layer = layer_num; - current_loc_is_highlighted = highlight_loc_with_specific_color(curr_loc, - block_color); - } - // No color specified at this location; use the block color. - if (!current_loc_is_highlighted) { - if (bnum) { - block_color = draw_state->block_color(bnum); - } else { - block_color = get_block_type_color(type); - block_color = lighten_color(block_color, - EMPTY_BLOCK_LIGHTEN_FACTOR); - } - } + for (int i = 0; i < (int)grid.width(); i++) { + for (int j = 0; j < (int)grid.height(); j++) { + if (!grid.is_root_location({i, j, layer_num})) { + continue; + } - logical_block_type = pick_logical_type(type); - g->set_color(block_color, transparency_factor); + // Only the first block of a group should control drawing + const t_physical_tile_type_ptr type = grid.get_physical_type({i, j, layer_num}); - /* Get coords of current sub_tile */ - ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(layer_num, - i, - j, - k, - logical_block_type); - ezgl::point2d center = abs_clb_bbox.center(); + int num_sub_tiles = type->capacity; + // Don't draw if tile capacity is zero. eg-> corners. + if (num_sub_tiles == 0) { + continue; + } - g->fill_rectangle(abs_clb_bbox); + for (int k = 0; k < num_sub_tiles; ++k) { + // Look at the tile at start of large block + ClusterBlockId bnum = grid_blocks.block_at_location({i, j, k, layer_num}); + // Fill background for the clb. Do not fill if "show_blk_internal" is toggled. - g->set_color(ezgl::BLACK, transparency_factor); + // Determine the block color and logical type + ezgl::color block_color; + t_pl_loc curr_loc{i, j, 0, layer_num}; + determine_block_color(curr_loc, bnum, type, draw_state, block_color); - g->set_line_dash((bnum == ClusterBlockId::INVALID()) ? ezgl::line_dash::asymmetric_5_3 : ezgl::line_dash::none); - if (draw_state->draw_block_outlines) { - g->draw_rectangle(abs_clb_bbox); - } + // Determine logical type + t_logical_block_type_ptr logical_block_type = pick_logical_type(type); + g->set_color(block_color, transparency_factor); + + // Get coords of current sub_tile + ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(layer_num, + i, + j, + k, + logical_block_type); + ezgl::point2d center = abs_clb_bbox.center(); - if (draw_state->draw_block_text) { - /* Draw text if the space has parts of the netlist */ - if (bnum) { - std::string name = cluster_ctx.clb_nlist.block_name(bnum) + vtr::string_fmt(" (#%zu)", size_t(bnum)); - - g->draw_text(center, name.c_str(), abs_clb_bbox.width(), - abs_clb_bbox.height()); - } - /* Draw text for block type so that user knows what block */ - if (width_offset == 0 - && height_offset == 0) { - std::string block_type_loc = type->name; - block_type_loc += vtr::string_fmt(" (%d,%d)", i, j); - - g->draw_text( - center - - ezgl::point2d(0, - abs_clb_bbox.height() / 4), - block_type_loc.c_str(), abs_clb_bbox.width(), - abs_clb_bbox.height()); - } + g->fill_rectangle(abs_clb_bbox); + + g->set_color(ezgl::BLACK, transparency_factor); + + g->set_line_dash((bnum == ClusterBlockId::INVALID()) ? ezgl::line_dash::asymmetric_5_3 : ezgl::line_dash::none); + if (draw_state->draw_block_outlines) { + g->draw_rectangle(abs_clb_bbox); + } + + if (draw_state->draw_block_text) { + // Draw text if the space has parts of the netlist + if (bnum) { + const std::string name = cluster_ctx.clb_nlist.block_name(bnum) + vtr::string_fmt(" (#%zu)", size_t(bnum)); + g->draw_text(center, name, abs_clb_bbox.width(), abs_clb_bbox.height()); } + + // Draw text for block type so that user knows what block + std::string block_type_loc = type->name; + block_type_loc += vtr::string_fmt(" (%d,%d)", i, j); + + g->draw_text(center - ezgl::point2d(0, abs_clb_bbox.height() / 4), + block_type_loc, abs_clb_bbox.width(), abs_clb_bbox.height()); } } } @@ -863,14 +848,12 @@ void draw_routing_util(ezgl::renderer* g) { if (draw_state->show_routing_util == DRAW_ROUTING_UTIL_WITH_VALUE) { g->draw_text(bb.center(), - vtr::string_fmt("%.2f", chanx_util).c_str(), + vtr::string_fmt("%.2f", chanx_util), bb.width(), bb.height()); } else if (draw_state->show_routing_util == DRAW_ROUTING_UTIL_WITH_FORMULA) { g->draw_text(bb.center(), - vtr::string_fmt("%.2f = %.0f / %.0f", chanx_util, - chanx_usage[x][y], chanx_avail[x][y]) - .c_str(), + vtr::string_fmt("%.2f = %.0f / %.0f", chanx_util, chanx_usage[x][y], chanx_avail[x][y]), bb.width(), bb.height()); } @@ -897,14 +880,12 @@ void draw_routing_util(ezgl::renderer* g) { if (draw_state->show_routing_util == DRAW_ROUTING_UTIL_WITH_VALUE) { g->draw_text(bb.center(), - vtr::string_fmt("%.2f", chany_util).c_str(), + vtr::string_fmt("%.2f", chany_util), bb.width(), bb.height()); } else if (draw_state->show_routing_util == DRAW_ROUTING_UTIL_WITH_FORMULA) { g->draw_text(bb.center(), - vtr::string_fmt("%.2f = %.0f / %.0f", chany_util, - chany_usage[x][y], chany_avail[x][y]) - .c_str(), + vtr::string_fmt("%.2f = %.0f / %.0f", chany_util, chany_usage[x][y], chany_avail[x][y]), bb.width(), bb.height()); } @@ -952,7 +933,7 @@ void draw_routing_util(ezgl::renderer* g) { || draw_state->show_routing_util == DRAW_ROUTING_UTIL_WITH_FORMULA) { g->draw_text(bb.center(), - vtr::string_fmt("%.2f", sb_util).c_str(), bb.width(), + vtr::string_fmt("%.2f", sb_util), bb.width(), bb.height()); } } @@ -1190,7 +1171,7 @@ void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr - 8 * cos(text_angle * (std::numbers::pi / 180)); ezgl::point2d offset_text_bbox(x_offset, y_offset); - g->draw_text(offset_text_bbox, incr_delay_str.c_str(), + g->draw_text(offset_text_bbox, incr_delay_str, text_bbox.width(), text_bbox.height()); g->set_font_size(14); @@ -1313,19 +1294,17 @@ void draw_color_map_legend(const vtr::ColorMap& cmap, //Min mark g->set_color(blk_SKYBLUE); // set to skyblue so its easier to see std::string str = vtr::string_fmt("%.3g", cmap.min()); - g->draw_text({legend.center_x(), legend.top() - TEXT_OFFSET}, - str.c_str()); + g->draw_text({legend.center_x(), legend.top() - TEXT_OFFSET}, str); //Mid marker g->set_color(ezgl::BLACK); str = vtr::string_fmt("%.3g", cmap.min() + (cmap.range() / 2.)); - g->draw_text({legend.center_x(), legend.center_y()}, str.c_str()); + g->draw_text({legend.center_x(), legend.center_y()}, str); //Max marker g->set_color(ezgl::BLACK); str = vtr::string_fmt("%.3g", cmap.max()); - g->draw_text({legend.center_x(), legend.bottom() + TEXT_OFFSET}, - str.c_str()); + g->draw_text({legend.center_x(), legend.bottom() + TEXT_OFFSET}, str); g->set_color(ezgl::BLACK); g->draw_rectangle(legend); diff --git a/vpr/src/draw/draw_basic.h b/vpr/src/draw/draw_basic.h index a0560c0be75..580f4d7783a 100644 --- a/vpr/src/draw/draw_basic.h +++ b/vpr/src/draw/draw_basic.h @@ -10,9 +10,7 @@ #ifndef NO_GRAPHICS #include -#include #include -#include #include "draw_types.h" #include "netlist_fwd.h" @@ -24,10 +22,13 @@ #include "ezgl/point.hpp" #include "ezgl/graphics.hpp" -/* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * - * while empty ones are lighter colours and have a dashed border. * - * Blocks are drawn in layer order (so that semi-transparent blocks/grids render well)*/ -void drawplace(ezgl::renderer* g); +/** + * @brief Draws all placed blocks on the device grid across visible layers. + * + * Occupied blocks are darker colours while empty ones are lighter colours and have a dashed border. + * Blocks are drawn in layer order (so that semi-transparent blocks/grids render well) + */ +void draw_place(ezgl::renderer* g); /** This function draws the analytical placement from the PartialPlacement object, it * also draws the architecture grid and the blocks from device_ctx. @@ -74,11 +75,6 @@ int get_timing_path_node_layer_num(tatum::NodeId node); * @brief Returns true if both the current_node and prev_node are on the same layer and it is visible, * or they're on different layers that are both visible and cross-layer connections are visible. * Otherwise returns false. - * - * @param current_node - * @param prev_node - * - * @return */ bool is_edge_valid_to_draw(RRNodeId current_node, RRNodeId prev_node); diff --git a/vpr/src/draw/draw_interposer.cpp b/vpr/src/draw/draw_interposer.cpp index 47fc758ce8e..d849db01339 100644 --- a/vpr/src/draw/draw_interposer.cpp +++ b/vpr/src/draw/draw_interposer.cpp @@ -26,10 +26,6 @@ void draw_interposer_cuts(ezgl::renderer* g) { {draw_coords->tile_x.back() + 2 * draw_coords->get_tile_width(), draw_coords->tile_y.back() + 2 * draw_coords->get_tile_height()}}; - g->set_color(ezgl::BLACK, 255); - g->set_line_dash(ezgl::line_dash::asymmetric_5_3); - g->set_line_width(2); - const std::vector>& horizontal_cuts = grid.get_horizontal_interposer_cuts(); const std::vector>& vertical_cuts = grid.get_vertical_interposer_cuts(); std::vector> lines_to_draw; @@ -74,6 +70,9 @@ void draw_interposer_cuts(ezgl::renderer* g) { } } + g->set_color(ezgl::BLACK, 255); + g->set_line_dash(ezgl::line_dash::asymmetric_5_3); + g->set_line_width(2); for (const auto& [start, end] : lines_to_draw) { g->draw_line(start, end); } diff --git a/vpr/src/draw/draw_rr_edges.cpp b/vpr/src/draw/draw_rr_edges.cpp index 98daecb13b0..5b6f1fea5e0 100644 --- a/vpr/src/draw/draw_rr_edges.cpp +++ b/vpr/src/draw/draw_rr_edges.cpp @@ -56,24 +56,32 @@ void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, RRSwitchId r else { if (rr_graph.node_direction(to_node) != Direction::BIDIR) { if (rr_graph.node_direction(to_node) == Direction::INC) { // INC wire starts at bottom edge - - y2 = to_chan.bottom(); - // since no U-turns from_tracks must be INC as well - y1 = draw_coords->tile_y[to_ylow - 1] - + draw_coords->get_tile_width(); + if (rr_graph.node_direction(from_node) == Direction::DEC) { + y2 = to_chan.bottom(); + y1 = draw_coords->tile_y[to_ylow] + 0.1 * draw_coords->get_tile_height(); + } else { + // since no U-turns from_tracks must be INC as well + VTR_ASSERT_SAFE(rr_graph.node_direction(from_node) == Direction::INC); + y2 = to_chan.bottom(); + y1 = draw_coords->tile_y[to_ylow - 1] + draw_coords->get_tile_height(); + } } else { // DEC wire starts at top edge - - y2 = to_chan.top(); - y1 = draw_coords->tile_y[to_yhigh + 1]; + VTR_ASSERT_SAFE(rr_graph.node_direction(to_node) == Direction::DEC); + if (rr_graph.node_direction(from_node) == Direction::INC) { + y2 = to_chan.top(); + y1 = draw_coords->tile_y[to_yhigh] + 0.9 * draw_coords->get_tile_height(); + } else { + VTR_ASSERT_SAFE(rr_graph.node_direction(from_node) == Direction::DEC); + y2 = to_chan.top(); + y1 = draw_coords->tile_y[to_yhigh + 1]; + } } } else { if (to_ylow < from_ylow) { // Draw from bottom edge of one to other. y1 = from_chan.bottom(); - y2 = draw_coords->tile_y[from_ylow - 1] - + draw_coords->get_tile_width(); + y2 = draw_coords->tile_y[from_ylow - 1] + draw_coords->get_tile_height(); } else if (from_ylow < to_ylow) { - y1 = draw_coords->tile_y[to_ylow - 1] - + draw_coords->get_tile_width(); + y1 = draw_coords->tile_y[to_ylow - 1] + draw_coords->get_tile_height(); y2 = to_chan.bottom(); } else if (to_yhigh > from_yhigh) { // Draw from top edge of one to other. y1 = from_chan.top(); @@ -83,7 +91,7 @@ void draw_chany_to_chany_edge(RRNodeId from_node, RRNodeId to_node, RRSwitchId r y2 = to_chan.top(); } else { // Complete overlap: start and end both align. Draw outside the sbox y1 = from_chan.bottom(); - y2 = from_chan.bottom() + draw_coords->get_tile_width(); + y2 = from_chan.bottom() + draw_coords->get_tile_height(); } } } @@ -113,40 +121,45 @@ void draw_chanx_to_chanx_edge(RRNodeId from_node, RRNodeId to_node, RRSwitchId r int from_xhigh = rr_graph.node_xhigh(from_node); int to_xlow = rr_graph.node_xlow(to_node); int to_xhigh = rr_graph.node_xhigh(to_node); - if (to_xhigh < from_xlow) { /* From right to left */ + if (to_xhigh < from_xlow) { // From right to left // Could never happen for INC wires, unless U-turn. For DEC wires this handles well x1 = from_chan.left(); x2 = to_chan.right(); - } else if (to_xlow > from_xhigh) { /* From left to right */ + } else if (to_xlow > from_xhigh) { // From left to right // Could never happen for DEC wires, unless U-turn. For INC wires this handles well x1 = from_chan.right(); x2 = to_chan.left(); } - /* Segments overlap in the channel. Figure out best way to draw. Have to * - * make sure the drawing is symmetric in the from rr and to rr so the edges * - * will be drawn on top of each other for bidirectional connections. */ + // Segments overlap in the channel. Figure out the best way to draw. Have to + // make sure the drawing is symmetric in the from rr and to rr so the edges + // will be drawn on top of each other for bidirectional connections. else { if (rr_graph.node_direction(to_node) != Direction::BIDIR) { // must connect to to_node's wire beginning at x2 if (rr_graph.node_direction(to_node) == Direction::INC) { // INC wire starts at leftmost edge - VTR_ASSERT(from_xlow < to_xlow); x2 = to_chan.left(); - // since no U-turns from_tracks must be INC as well - x1 = draw_coords->tile_x[to_xlow - 1] - + draw_coords->get_tile_width(); + if (rr_graph.node_direction(from_node) == Direction::DEC) { + x1 = draw_coords->tile_x[to_xlow] + 0.1 * draw_coords->get_tile_width(); + } else { + VTR_ASSERT_SAFE(rr_graph.node_direction(from_node) == Direction::INC); + x1 = draw_coords->tile_x[to_xlow - 1] + 0.9 * draw_coords->get_tile_width(); + } } else { // DEC wire starts at rightmost edge - VTR_ASSERT(from_xhigh > to_xhigh); + VTR_ASSERT_SAFE(rr_graph.node_direction(to_node) == Direction::DEC); x2 = to_chan.right(); - x1 = draw_coords->tile_x[to_xhigh + 1]; + if (rr_graph.node_direction(from_node) == Direction::INC) { + x1 = draw_coords->tile_x[to_xhigh] + 0.9 * draw_coords->get_tile_width(); + } else { + VTR_ASSERT_SAFE(rr_graph.node_direction(from_node) == Direction::DEC); + x1 = draw_coords->tile_x[to_xhigh + 1]; + } } } else { if (to_xlow < from_xlow) { // Draw from left edge of one to other x1 = from_chan.left(); - x2 = draw_coords->tile_x[from_xlow - 1] - + draw_coords->get_tile_width(); + x2 = draw_coords->tile_x[from_xlow - 1] + draw_coords->get_tile_width(); } else if (from_xlow < to_xlow) { - x1 = draw_coords->tile_x[to_xlow - 1] - + draw_coords->get_tile_width(); + x1 = draw_coords->tile_x[to_xlow - 1] + draw_coords->get_tile_width(); x2 = to_chan.left(); } // The following then is executed when from_xlow == to_xlow diff --git a/vpr/src/draw/draw_rr_edges.h b/vpr/src/draw/draw_rr_edges.h index a814a03c8d7..aabba92b6a9 100644 --- a/vpr/src/draw/draw_rr_edges.h +++ b/vpr/src/draw/draw_rr_edges.h @@ -84,7 +84,7 @@ void draw_pin_to_chan_edge(RRNodeId pin_node, RRNodeId chan_node, ezgl::renderer */ void draw_rr_edge(RRNodeId inode, RRNodeId prev_node, ezgl::color color, ezgl::renderer* g); -/** @brief Draws an edge between two rr_nodes, which are both intra-cluster nodes. +/** @brief Draws an edge between two rr_nodes, which are both inter-cluster nodes. * @param inode The current rr_node id * @param prev_node The previous rr_node id * @param g The ezgl renderer diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index ba140979105..447a84e61d9 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -33,33 +33,23 @@ * TODO: Fix this for global routing, currently for detailed only. */ ezgl::rectangle draw_get_rr_chan_bbox(RRNodeId inode) { - double left = 0, right = 0, top = 0, bottom = 0; t_draw_coords* draw_coords = get_draw_coords_vars(); const DeviceContext& device_ctx = g_vpr_ctx.device(); const RRGraphView& rr_graph = device_ctx.rr_graph; + double left = 0, right = 0, top = 0, bottom = 0; switch (rr_graph.node_type(inode)) { case e_rr_type::CHANX: left = draw_coords->tile_x[rr_graph.node_xlow(inode)]; - right = draw_coords->tile_x[rr_graph.node_xhigh(inode)] - + draw_coords->get_tile_width(); - bottom = draw_coords->tile_y[rr_graph.node_ylow(inode)] - + draw_coords->get_tile_width() - + (1. + rr_graph.node_track_num(inode)); - top = draw_coords->tile_y[rr_graph.node_ylow(inode)] - + draw_coords->get_tile_width() - + (1. + rr_graph.node_track_num(inode)); + right = draw_coords->tile_x[rr_graph.node_xhigh(inode)] + draw_coords->get_tile_width(); + bottom = draw_coords->tile_y[rr_graph.node_ylow(inode)] + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); + top = bottom; break; case e_rr_type::CHANY: - left = draw_coords->tile_x[rr_graph.node_xlow(inode)] - + draw_coords->get_tile_width() - + (1. + rr_graph.node_track_num(inode)); - right = draw_coords->tile_x[rr_graph.node_xlow(inode)] - + draw_coords->get_tile_width() - + (1. + rr_graph.node_track_num(inode)); + left = draw_coords->tile_x[rr_graph.node_xlow(inode)] + draw_coords->get_tile_width() + (1. + rr_graph.node_track_num(inode)); + right = left; bottom = draw_coords->tile_y[rr_graph.node_ylow(inode)]; - top = draw_coords->tile_y[rr_graph.node_yhigh(inode)] - + draw_coords->get_tile_width(); + top = draw_coords->tile_y[rr_graph.node_yhigh(inode)] + draw_coords->get_tile_width(); break; default: // a problem. leave at default value (ie. zeros) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index 6eba67368f3..bfc26b9bb78 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -11,10 +11,10 @@ #include "placer_state.h" #include "PlacerCriticalities.h" -//f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. +// f_placer_breakpoint_reached is used to stop the placer when a breakpoint is reached. // When this flag is true, it stops the placer after the current perturbation. Thus, when a breakpoint is reached, this flag is set to true. -//Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING -bool f_placer_breakpoint_reached = false; +// Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING +static bool f_placer_breakpoint_reached = false; /** * @brief Adjust the search range based on how many blocks are in the column. @@ -34,7 +34,7 @@ static void adjust_search_range(t_logical_block_type_ptr block_type, const bool is_range_fixed, t_bb& search_range); -//Accessor for f_placer_breakpoint_reached +// Accessor for f_placer_breakpoint_reached bool placer_breakpoint_reached() { return f_placer_breakpoint_reached; } diff --git a/vpr/src/place/placer_breakpoint.cpp b/vpr/src/place/placer_breakpoint.cpp index 0f4c1f0856f..d8fd1458583 100644 --- a/vpr/src/place/placer_breakpoint.cpp +++ b/vpr/src/place/placer_breakpoint.cpp @@ -10,13 +10,17 @@ std::map available_move_types = { {0, "Uniform"}}; #ifndef NO_GRAPHICS -//transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state -void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected) { + +/// Transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state +static void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); + +static void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected) { BreakpointState* bp_state = get_bp_state_globals()->get_glob_breakpoint_state(); bp_state->blocks_affected_by_move.clear(); for (const t_pl_moved_block& moved_block : blocksAffected.moved_blocks) { - //size_t conversion is required since block_num is of type ClusterBlockId and can't be cast to an int. And this vector has to be of type int to be recognized in expr_eval class + // size_t conversion is required since block_num is of type ClusterBlockId + // and can't be cast to an int. And this vector has to be of type int to be recognized in expr_eval class bp_state->blocks_affected_by_move.push_back(size_t(moved_block.block_num)); } } @@ -30,12 +34,12 @@ void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affect BreakpointState* bp_state = get_bp_state_globals()->get_glob_breakpoint_state(); if (!draw_state->list_of_breakpoints.empty()) { - //update current information + // update current information transform_blocks_affected(blocks_affected); bp_state->move_num++; bp_state->from_block = size_t(blocks_affected.moved_blocks[0].block_num); - //check for breakpoints + // check for breakpoints set_placer_breakpoint_reached(check_for_breakpoints(true)); // the passed flag is true as we are in the placer if (placer_breakpoint_reached()) { breakpoint_info_window(bp_state->bp_description, *bp_state, true); diff --git a/vpr/src/place/placer_breakpoint.h b/vpr/src/place/placer_breakpoint.h index 100440f1183..d4907ee769c 100644 --- a/vpr/src/place/placer_breakpoint.h +++ b/vpr/src/place/placer_breakpoint.h @@ -2,10 +2,7 @@ #include "move_utils.h" -//transforms the vector moved_blocks to a vector of ints and adds it in glob_breakpoint_state -void transform_blocks_affected(const t_pl_blocks_to_be_moved& blocksAffected); - -//checks the breakpoint and see whether one of them was reached and pause place,emt accordingly +/// Checks the breakpoint and see whether one of them was reached and pause placement accordingly. void stop_placement_and_check_breakpoints(t_pl_blocks_to_be_moved& blocks_affected, e_move_result move_outcome, double delta_c, diff --git a/vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp b/vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp index bbadf1d88e8..9b63e0a9103 100644 --- a/vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp +++ b/vpr/src/route/rr_graph_generation/build_scatter_gathers.cpp @@ -192,7 +192,7 @@ std::vector alloc_and_load_scatter_gather_connections(const s for (const t_sg_location& sg_loc_info : sg_pattern.sg_locations) { for (const t_physical_tile_loc gather_loc : grid.all_locations()) { - if (sb_not_here(grid, inter_cluster_rr, gather_loc, sg_loc_info.type)) { + if (sb_not_here(grid, inter_cluster_rr, gather_loc, sg_loc_info.type, sg_loc_info.region)) { continue; } @@ -306,6 +306,8 @@ std::vector alloc_and_load_scatter_gather_connections(const s bottleneck_link.chan_type = chan_type; bottleneck_link.parallel_segment_index = std::distance(segment_inf.begin(), seg_it); + bottleneck_link.R_metal = seg_it->Rmetal; + bottleneck_link.C_metal = seg_it->Cmetal; if (is_3d_link) { if (sg_link.z_offset < 0 && wire_segment.arch_wire_switch_dec != ARCH_FPGA_UNDEFINED_VAL) { @@ -330,3 +332,103 @@ std::vector alloc_and_load_scatter_gather_connections(const s return bottleneck_links; } + +void convert_interposer_cuts_to_sg_patterns(const std::vector& interposer_inf, + std::vector& sg_patterns) { + const DeviceContext& device_ctx = g_vpr_ctx.device(); + const DeviceGrid& grid = device_ctx.grid; + + const size_t num_layers = grid.get_num_layers(); + const size_t grid_width = grid.width(); + const size_t grid_height = grid.height(); + + VTR_ASSERT(interposer_inf.size() == num_layers); + + // Step 1: Iterate over all layers in the device grid + for (size_t layer = 0; layer < num_layers; layer++) { + + // Step 2: Process each interposer cut (vertical or horizontal) on this layer + for (const t_interposer_cut_inf& cut_inf : interposer_inf[layer].interposer_cuts) { + const int cut_loc = cut_inf.loc; + e_interposer_cut_type cut_type = cut_inf.dim; + + // Step 3: For each inter-die wire defined at this cut, compute its SG region + for (const t_interdie_wire_inf& wire_inf : cut_inf.interdie_wires) { + VTR_ASSERT(wire_inf.offset_definition.repeat_expr.empty()); + + // Parse offset expressions and compute absolute start/end positions of the region + const int start = std::stoi(wire_inf.offset_definition.start_expr) + cut_loc; + const int end = std::stoi(wire_inf.offset_definition.end_expr) + cut_loc; + const int incr = std::stoi(wire_inf.offset_definition.incr_expr); + + // Step 4: Find the corresponding SG pattern by name + auto sg_it = std::ranges::find_if(sg_patterns, [&wire_inf](const t_scatter_gather_pattern& sg) noexcept { + return wire_inf.sg_name == sg.name; + }); + // Must exist; SG pattern names must match between interposer XML and SG patterns + VTR_ASSERT(sg_it != sg_patterns.end()); + + // Step 5: Define the spatial region (X/Y span) for this SG link + t_specified_loc region; + + // For vertical cuts, X varies along the cut; Y covers full height + region.reg_x.start = (cut_type == e_interposer_cut_type::VERT) ? start : 0; + region.reg_x.end = (cut_type == e_interposer_cut_type::VERT) ? end : grid_width - 1; + region.reg_x.incr = (cut_type == e_interposer_cut_type::VERT) ? incr : 1; + region.reg_x.repeat = std::numeric_limits::max(); + + // For horizontal cuts, Y varies along the cut; X covers full width + region.reg_y.start = (cut_type == e_interposer_cut_type::HORZ) ? start : 0; + region.reg_y.end = (cut_type == e_interposer_cut_type::HORZ) ? end : grid_height - 1; + region.reg_y.incr = (cut_type == e_interposer_cut_type::HORZ) ? incr : 1; + region.reg_y.repeat = std::numeric_limits::max(); + + // Step 6: Build an SG location entry describing where to instantiate links + t_sg_location sg_location{.type = e_sb_location::E_XY_SPECIFIED, + .region = region, + .num = wire_inf.num, + .sg_link_name = wire_inf.sg_link}; + + // Step 7: Append this region definition to the matched SG pattern + sg_it->sg_locations.push_back(std::move(sg_location)); + } + } + } +} + +void compute_non_3d_sg_link_geometry(const t_physical_tile_loc& src_loc, + const t_physical_tile_loc& dst_loc, + e_rr_type& chan_type, + int& xlow, int& xhigh, + int& ylow, int& yhigh, + Direction& direction) { + VTR_ASSERT_SAFE(src_loc.layer_num == dst_loc.layer_num); + + if (dst_loc.x > src_loc.x) { + chan_type = e_rr_type::CHANX; + ylow = yhigh = dst_loc.y; + xlow = src_loc.x + 1; + xhigh = dst_loc.x; + direction = Direction::INC; + } else if (dst_loc.x < src_loc.x) { + chan_type = e_rr_type::CHANX; + ylow = yhigh = dst_loc.y; + xlow = dst_loc.x + 1; + xhigh = src_loc.x; + direction = Direction::DEC; + } else if (dst_loc.y > src_loc.y) { + chan_type = e_rr_type::CHANY; + xlow = xhigh = dst_loc.x; + ylow = src_loc.y + 1; + yhigh = dst_loc.y; + direction = Direction::INC; + } else if (dst_loc.y < src_loc.y) { + chan_type = e_rr_type::CHANY; + xlow = xhigh = dst_loc.x; + ylow = dst_loc.y + 1; + yhigh = src_loc.y; + direction = Direction::DEC; + } else { + VTR_ASSERT_MSG(false, "Source and destination locations cannot be identical"); + } +} \ No newline at end of file diff --git a/vpr/src/route/rr_graph_generation/build_scatter_gathers.h b/vpr/src/route/rr_graph_generation/build_scatter_gathers.h index e3b69c0582f..b4b087f0733 100644 --- a/vpr/src/route/rr_graph_generation/build_scatter_gathers.h +++ b/vpr/src/route/rr_graph_generation/build_scatter_gathers.h @@ -33,6 +33,8 @@ struct t_bottleneck_link { t_physical_tile_loc scatter_loc; ///< Destination switchblock location. int arch_wire_switch; ///< The switch (mux) used to drive the bottleneck wire. int parallel_segment_index; + float R_metal; + float C_metal; e_rr_type chan_type; std::vector gather_fanin_connections; ///< Wires driving the bottleneck link at `gather_loc` std::vector scatter_fanout_connections; ///< Wires driven by the bottleneck link at `scatter_loc` @@ -66,3 +68,22 @@ std::vector alloc_and_load_scatter_gather_connections(const s const t_chan_width& nodes_per_chan, vtr::RngContainer& rng, vtr::NdMatrix, 2>& interdie_3d_links); + +/** + * @brief Converts interposer cut definitions into scatter–gather (SG) specifications. + * @param interposer_inf Interposer cut specifications for each layer. + * @param sg_patterns SG pattern list to update with derived SG specifications. + */ +void convert_interposer_cuts_to_sg_patterns(const std::vector& interposer_inf, + std::vector& sg_patterns); + +/** +* @brief Computes the channel type, direction, and coordinate span between two locations +* on the same layer. Used by SG link construction routines to determine geometry. +*/ +void compute_non_3d_sg_link_geometry(const t_physical_tile_loc& src_loc, + const t_physical_tile_loc& dst_loc, + e_rr_type& chan_type, + int& xlow, int& xhigh, + int& ylow, int& yhigh, + Direction& direction); \ No newline at end of file diff --git a/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp b/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp index 905b47ff1fd..aa8cc097c4e 100644 --- a/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp +++ b/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp @@ -34,7 +34,7 @@ std::vector alloc_and_load_clb_to_clb_directs(const std::v t_physical_tile_port tile_port = find_tile_port_by_name(physical_tile, port_name); /* Find the sub tile indices */ - clb_to_clb_directs[i].from_sub_tiles = find_sub_tile_indices_by_port_name(physical_tile, port_name); + clb_to_clb_directs[i].from_sub_tiles = find_sub_tile_indices_by_port_name(physical_tile, port_name); if (clb_to_clb_directs[i].from_sub_tiles.empty()) { VPR_THROW(VPR_ERROR_ARCH, "Unable to find sub tile under tile '%s' which contains the port %s.\n", tile_name.c_str(), port_name.data()); } diff --git a/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp index e88051e1ba2..875b6479abd 100644 --- a/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_connection_builders.cpp @@ -114,9 +114,8 @@ RRNodeId RoutingToClockConnection::create_virtual_clock_network_sink_node(int la rr_graph_builder.set_node_capacity(node_index, 1); rr_graph_builder.set_node_cost_index(node_index, RRIndexedDataId(SINK_COST_INDEX)); - float R = 0.; - float C = 0.; - rr_graph_builder.set_node_rc_index(node_index, NodeRCIndex(find_create_rr_rc_data(R, C, rr_rc_data))); + const NodeRCIndex rc_index = find_create_rr_rc_data(0, 0, rr_rc_data); + rr_graph_builder.set_node_rc_index(node_index, rc_index); // Use a generic way when adding nodes to lookup. // However, since the SINK node has the same xhigh/xlow as well as yhigh/ylow, we can probably use a shortcut diff --git a/vpr/src/route/rr_graph_generation/clock_network_builders.cpp b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp index ee5eebd5595..02aebc6187c 100644 --- a/vpr/src/route/rr_graph_generation/clock_network_builders.cpp +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.cpp @@ -337,7 +337,7 @@ int ClockRib::create_chanx_wire(int layer, t_rr_graph_storage* rr_nodes, RRGraphBuilder& rr_graph_builder) { rr_nodes->emplace_back(); - auto node_index = rr_nodes->size() - 1; + size_t node_index = rr_nodes->size() - 1; RRNodeId chanx_node = RRNodeId(node_index); rr_graph_builder.set_node_type(chanx_node, e_rr_type::CHANX); @@ -345,8 +345,8 @@ int ClockRib::create_chanx_wire(int layer, rr_graph_builder.set_node_layer(chanx_node, layer, layer); rr_graph_builder.set_node_capacity(chanx_node, 1); rr_graph_builder.set_node_track_num(chanx_node, ptc_num); - rr_graph_builder.set_node_rc_index(chanx_node, NodeRCIndex(find_create_rr_rc_data( - x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data))); + const NodeRCIndex rc_index = find_create_rr_rc_data(x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data); + rr_graph_builder.set_node_rc_index(chanx_node, rc_index); rr_graph_builder.set_node_direction(chanx_node, direction); short seg_index = 0; @@ -686,8 +686,8 @@ int ClockSpine::create_chany_wire(int layer, rr_graph_builder.set_node_layer(chany_node, layer, layer); rr_graph_builder.set_node_capacity(chany_node, 1); rr_graph_builder.set_node_track_num(chany_node, ptc_num); - rr_graph_builder.set_node_rc_index(chany_node, NodeRCIndex(find_create_rr_rc_data( - y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data))); + const NodeRCIndex rc_index = find_create_rr_rc_data(y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data); + rr_graph_builder.set_node_rc_index(chany_node, rc_index); rr_graph_builder.set_node_direction(chany_node, direction); short seg_index = 0; diff --git a/vpr/src/route/rr_graph_generation/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp index 6afaff446b2..d53bff000ed 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph.cpp @@ -198,6 +198,8 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const t_track_to_pin_lookup& track_to_pin_lookup_y, const t_pin_to_track_lookup& opin_to_track_map, const vtr::NdMatrix, 2>& interdie_3d_links, + const std::vector& sg_links, + const std::vector>& sg_node_indices, const vtr::NdMatrix, 3>& switch_block_conn, t_sb_connection_map* sb_conn_map, const DeviceGrid& grid, @@ -214,7 +216,6 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const std::vector& clb_to_clb_directs, bool is_global_graph, const e_clock_modeling clock_modeling, - bool is_flat, const int route_verbosity); /** @@ -362,6 +363,7 @@ static void build_rr_graph(e_graph_type graph_type, const e_clock_modeling clock_modeling, const std::vector& directs, const std::vector& scatter_gather_patterns, + const std::vector& interposer_inf, RRSwitchId& wire_to_rr_ipin_switch, bool is_flat, int* Warnings, @@ -376,6 +378,30 @@ static void build_rr_graph(e_graph_type graph_type, static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph); +/** + * @brief Adds and connects non-3D scatter–gather (SG) links to the RR graph. + * + * For each bottleneck link, this function creates a corresponding RR node + * representing the non-3D SG link, and records edges between the node and + * gather and scatter wires. The edges are stored in `non_3d_sg_rr_edges_to_create` + * for deferred creation. + * + * @param rr_graph_builder Reference to the RR graph builder. + * @param sg_links List of scatter–gather bottleneck links. + * @param sg_node_indices RR node IDs and track numbers for SG links. + * @param chan_details_x Channel details for CHANX segments. + * @param chan_details_y Channel details for CHANY segments. + * @param num_seg_types_x Number of segment types in the X direction. + * @param non_3d_sg_rr_edges_to_create Set collecting RR edges to create later. + */ +static void add_and_connect_non_3d_sg_links(RRGraphBuilder& rr_graph_builder, + const std::vector& sg_links, + const std::vector>& sg_node_indices, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y, + size_t num_seg_types_x, + t_rr_edge_info_set& non_3d_sg_rr_edges_to_create); + /** * @brief Calculates the routing channel width at each grid location. * @@ -463,6 +489,7 @@ void create_rr_graph(e_graph_type graph_type, router_opts.clock_modeling, directs, device_ctx.arch->scatter_gather_patterns, + device_ctx.arch->grid_layout().layers, det_routing_arch.wire_to_rr_ipin_switch, is_flat, Warnings, @@ -663,6 +690,7 @@ static void build_rr_graph(e_graph_type graph_type, const e_clock_modeling clock_modeling, const std::vector& directs, const std::vector& scatter_gather_patterns, + const std::vector& interposer_inf, RRSwitchId& wire_to_rr_ipin_switch, bool is_flat, int* Warnings, @@ -921,7 +949,12 @@ static void build_rr_graph(e_graph_type graph_type, // END SB LOOKUP vtr::NdMatrix, 2> interdie_3d_links; - const std::vector bottleneck_links = alloc_and_load_scatter_gather_connections(scatter_gather_patterns, + + std::vector sg_patterns_copy = scatter_gather_patterns; + + convert_interposer_cuts_to_sg_patterns(interposer_inf, sg_patterns_copy); + + const std::vector bottleneck_links = alloc_and_load_scatter_gather_connections(sg_patterns_copy, inter_cluster_prog_rr, segment_inf_x, segment_inf_y, segment_inf_z, chan_details_x, chan_details_y, @@ -937,6 +970,12 @@ static void build_rr_graph(e_graph_type graph_type, device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); } + std::vector> non_3d_sg_nodes = alloc_and_load_non_3d_sg_pattern_rr_node_indices(device_ctx.rr_graph_builder, + bottleneck_links, + nodes_per_chan, + num_rr_nodes); + device_ctx.rr_graph_builder.resize_nodes(num_rr_nodes); + // START IPIN MAP // Create ipin map lookups @@ -1024,6 +1063,8 @@ static void build_rr_graph(e_graph_type graph_type, track_to_pin_lookup_x, track_to_pin_lookup_y, opin_to_track_map, interdie_3d_links, + bottleneck_links, + non_3d_sg_nodes, switch_block_conn, sb_conn_map, grid, Fs, unidir_sb_pattern, Fc_out, nodes_per_chan, @@ -1036,7 +1077,6 @@ static void build_rr_graph(e_graph_type graph_type, clb_to_clb_directs, is_global_graph, clock_modeling, - is_flat, route_verbosity); // Verify no incremental node allocation. @@ -1428,6 +1468,8 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const t_track_to_pin_lookup& track_to_pin_lookup_y, const t_pin_to_track_lookup& opin_to_track_map, const vtr::NdMatrix, 2>& interdie_3d_links, + const std::vector& sg_links, + const std::vector>& sg_node_indices, const vtr::NdMatrix, 3>& switch_block_conn, t_sb_connection_map* sb_conn_map, const DeviceGrid& grid, @@ -1444,7 +1486,6 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder const std::vector& clb_to_clb_directs, bool is_global_graph, const e_clock_modeling clock_modeling, - bool /*is_flat*/, const int route_verbosity) { // We take special care when creating RR graph edges (there are typically many more // edges than nodes in an RR graph). @@ -1606,11 +1647,10 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder wire_to_pin_between_dice_switch, directionality); - //Create the actual CHAN->CHAN edges + // Create the actual CHAN->CHAN edges uniquify_edges(rr_edges_to_create); alloc_and_load_edges(rr_graph_builder, rr_edges_to_create); num_edges += rr_edges_to_create.size(); - rr_edges_to_create.clear(); } } @@ -1627,6 +1667,12 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder } } + add_and_connect_non_3d_sg_links(rr_graph_builder, sg_links, sg_node_indices, chan_details_x, chan_details_y, num_seg_types_x, rr_edges_to_create); + uniquify_edges(rr_edges_to_create); + alloc_and_load_edges(rr_graph_builder, rr_edges_to_create); + num_edges += rr_edges_to_create.size(); + rr_edges_to_create.clear(); + VTR_LOGV(route_verbosity > 1, "CHAN->CHAN type edge count:%d\n", num_edges); num_edges = 0; @@ -2003,7 +2049,7 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, int length = end - start + 1; float R = length * seg_details[track].Rmetal(); float C = length * seg_details[track].Cmetal(); - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data)); rr_graph_builder.set_node_type(node, chan_type); rr_graph_builder.set_node_track_num(node, track); @@ -2011,6 +2057,92 @@ static void build_rr_chan(RRGraphBuilder& rr_graph_builder, } } +static void add_and_connect_non_3d_sg_links(RRGraphBuilder& rr_graph_builder, + const std::vector& sg_links, + const std::vector>& sg_node_indices, + const t_chan_details& chan_details_x, + const t_chan_details& chan_details_y, + size_t num_seg_types_x, + t_rr_edge_info_set& non_3d_sg_rr_edges_to_create) { + // Each SG link should have a corresponding RR node index + VTR_ASSERT(sg_links.size() == sg_node_indices.size()); + const size_t num_links = sg_links.size(); + + for (size_t i = 0; i < num_links; i++) { + + const t_bottleneck_link& link = sg_links[i]; + + int xlow, xhigh, ylow, yhigh; + Direction direction; + e_rr_type chan_type; + const t_physical_tile_loc& src_loc = link.gather_loc; + const t_physical_tile_loc& dst_loc = link.scatter_loc; + + // Step 1: Determine the link’s direction and its spatial span. + // SG links are confined to one layer (non-3D), but can run in X or Y. + VTR_ASSERT_SAFE(src_loc.layer_num == dst_loc.layer_num); + const int layer = src_loc.layer_num; + compute_non_3d_sg_link_geometry(src_loc, dst_loc, chan_type, xlow, xhigh, ylow, yhigh,direction); + + // Retrieve the node ID and track number allocated earlier + const RRNodeId node_id = sg_node_indices[i].first; + const int track_num = sg_node_indices[i].second; + + // Step 2: Assign coordinates + rr_graph_builder.set_node_layer(node_id, layer, layer); + rr_graph_builder.set_node_coordinates(node_id, xlow, ylow, xhigh, yhigh); + rr_graph_builder.set_node_capacity(node_id, 1); + + // Step 3: Set cost index based on segment type and orientation + const size_t cons_index = link.chan_type == e_rr_type::CHANX ? CHANX_COST_INDEX_START + link.parallel_segment_index + : CHANX_COST_INDEX_START + num_seg_types_x + link.parallel_segment_index; + rr_graph_builder.set_node_cost_index(node_id, RRIndexedDataId(cons_index)); + + // Step 4: Assign electrical characteristics + const NodeRCIndex rc_index = find_create_rr_rc_data(link.R_metal, link.C_metal, g_vpr_ctx.mutable_device().rr_rc_data); + rr_graph_builder.set_node_rc_index(node_id, rc_index); + // Step 5: Set node type, track number, and direction + rr_graph_builder.set_node_type(node_id, link.chan_type); + rr_graph_builder.set_node_track_num(node_id, track_num); + rr_graph_builder.set_node_direction(node_id, direction); + + // Step 6: Add incoming edges from gather (fanin) channel wires + // Each gather wire connects to this SG link node using the SG wire switch. + for (const t_sg_candidate& gather_wire : link.gather_fanin_connections) { + const t_physical_tile_loc& chan_loc = gather_wire.chan_loc.location; + e_rr_type gather_chan_type = gather_wire.chan_loc.chan_type; + + // Locate the source RR node for this gather wire + RRNodeId gather_node = rr_graph_builder.node_lookup().find_node(chan_loc.layer_num, + chan_loc.x, + chan_loc.y, + gather_chan_type, + gather_wire.wire_switchpoint.wire); + // Record deferred edge creation (gather_node --> sg_node) + non_3d_sg_rr_edges_to_create.emplace_back(gather_node, node_id, link.arch_wire_switch, false); + } + + // Step 7: Add outgoing edges to scatter (fanout) channel wires + // Each scatter wire connects from this SG link node outward. + for (const t_sg_candidate& scatter_wire : link.scatter_fanout_connections) { + const t_physical_tile_loc& chan_loc = scatter_wire.chan_loc.location; + e_rr_type scatter_chan_type = scatter_wire.chan_loc.chan_type; + const t_chan_details& chan_details = (scatter_chan_type == e_rr_type::CHANX) ? chan_details_x : chan_details_y; + + // Locate the destination RR node for this scatter wire + RRNodeId scatter_node = rr_graph_builder.node_lookup().find_node(chan_loc.layer_num, + chan_loc.x, + chan_loc.y, + scatter_chan_type, + scatter_wire.wire_switchpoint.wire); + // Determine which architecture switch this edge should use + int switch_index = chan_details[chan_loc.x][chan_loc.y][scatter_wire.wire_switchpoint.wire].arch_wire_switch(); + // Record deferred edge creation (sg_node --> scatter_node) + non_3d_sg_rr_edges_to_create.emplace_back(node_id, scatter_node, switch_index, false); + } + } +} + void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info_set& rr_edges_to_create) { rr_graph_builder.alloc_and_load_edges(&rr_edges_to_create); } @@ -2939,7 +3071,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, auto [z, relative_opin] = get_capacity_location_from_physical_pin(curr_type, opin); VTR_ASSERT(z >= 0 && z < curr_type->capacity); const int num_directs = directs.size(); - + // Iterate through all direct connections for (int i = 0; i < num_directs; i++) { // Find matching direct clb-to-clb connections with the same type as current grid location diff --git a/vpr/src/route/rr_graph_generation/rr_graph_3d.cpp b/vpr/src/route/rr_graph_generation/rr_graph_3d.cpp index 08223b9b78a..6ed0e9d61e5 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_3d.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_3d.cpp @@ -85,9 +85,8 @@ void build_inter_die_3d_rr_chan(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_coordinates(node, x_coord, y_coord, x_coord, y_coord); rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(const_index_offset + link.parallel_segment_index)); rr_graph_builder.set_node_capacity(node, 1); // GLOBAL routing handled elsewhere - float R = 0; - float C = 0; - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); + const NodeRCIndex rc_index = find_create_rr_rc_data(link.R_metal, link.C_metal, mutable_device_ctx.rr_rc_data); + rr_graph_builder.set_node_rc_index(node, rc_index); rr_graph_builder.set_node_type(node, e_rr_type::CHANZ); rr_graph_builder.set_node_track_num(node, track_num); diff --git a/vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.cpp b/vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.cpp index 0a8290de90d..dc3c01b0348 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.cpp @@ -34,9 +34,8 @@ void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_coordinates(class_inode, (short)root_loc.x, (short)root_loc.y, (short)(root_loc.x + physical_type->width - 1), (short)(root_loc.y + physical_type->height - 1)); VTR_ASSERT(root_loc.layer_num <= std::numeric_limits::max()); rr_graph_builder.set_node_layer(class_inode, root_loc.layer_num, root_loc.layer_num); - float R = 0.; - float C = 0.; - rr_graph_builder.set_node_rc_index(class_inode, NodeRCIndex(find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); + const NodeRCIndex rc_index = find_create_rr_rc_data(0, 0, mutable_device_ctx.rr_rc_data); + rr_graph_builder.set_node_rc_index(class_inode, rc_index); rr_graph_builder.set_node_class_num(class_inode, class_num); } } @@ -78,7 +77,7 @@ void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, rr_graph_builder.set_node_capacity(node_id, 1); float R = 0.; float C = 0.; - rr_graph_builder.set_node_rc_index(node_id, NodeRCIndex(find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data))); + rr_graph_builder.set_node_rc_index(node_id, find_create_rr_rc_data(R, C, mutable_device_ctx.rr_rc_data)); rr_graph_builder.set_node_pin_num(node_id, pin_num); // Note that we store the grid tile location and side where the pin is located, // which greatly simplifies the drawing code diff --git a/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp index 71316392626..48ca3a981ff 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_timing_params.cpp @@ -174,7 +174,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { Couts_to_add = new float[rr_graph.num_nodes()]; for (size_t i = 0; i < rr_graph.num_nodes(); i++) Couts_to_add[i] = 0; - for (const RRNodeId& inode : rr_graph.nodes()) { + for (const RRNodeId inode : rr_graph.nodes()) { for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(inode); iedge++) { switch_index = rr_graph.edge_switch(inode, iedge); to_node = size_t(rr_graph.edge_sink_node(inode, iedge)); @@ -187,13 +187,13 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) { } } } - for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { + for (const RRNodeId rr_id : device_ctx.rr_graph.nodes()) { rr_node_C[(size_t)rr_id] += Couts_to_add[(size_t)rr_id]; } - //Create the final flywieghted t_rr_rc_data - for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { - mutable_device_ctx.rr_graph_builder.set_node_rc_index(rr_id, NodeRCIndex(find_create_rr_rc_data(rr_graph.node_R(rr_id), rr_node_C[(size_t)rr_id], mutable_device_ctx.rr_rc_data))); + // Create the final flywieghted t_rr_rc_data + for (const RRNodeId rr_id : device_ctx.rr_graph.nodes()) { + mutable_device_ctx.rr_graph_builder.set_node_rc_index(rr_id, find_create_rr_rc_data(rr_graph.node_R(rr_id), rr_node_C[(size_t)rr_id], mutable_device_ctx.rr_rc_data)); } delete[] Couts_to_add; diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index 68c7adbbf0a..8aa8a375922 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -363,6 +363,66 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, } } +std::vector> alloc_and_load_non_3d_sg_pattern_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const std::vector& bottleneck_links, + const t_chan_width& chan_width_inf, + int& index) { + const DeviceContext& device_ctx = g_vpr_ctx.device(); + const DeviceGrid& grid = device_ctx.grid; + + // Initialize matrices tracking the next free track number (ptc) + vtr::NdMatrix chanx_ptc({grid.get_num_layers(), grid.width(), grid.height()}, chan_width_inf.x_max); + vtr::NdMatrix chany_ptc({grid.get_num_layers(), grid.width(), grid.height()}, chan_width_inf.y_max); + + std::vector> node_indices; + node_indices.reserve(bottleneck_links.size()); + + for (const t_bottleneck_link& link : bottleneck_links) { + int xlow, xhigh, ylow, yhigh; + e_rr_type chan_type; + Direction direction; + const t_physical_tile_loc& src_loc = link.gather_loc; + const t_physical_tile_loc& dst_loc = link.scatter_loc; + + // Step 1: Determine the channel type (CHANX/CHANY) and span coordinates + const int layer = src_loc.layer_num; + compute_non_3d_sg_link_geometry(src_loc, dst_loc, chan_type, xlow, xhigh, ylow, yhigh,direction); + + // Select the appropriate ptc matrix for this channel type + vtr::NdMatrix& ptc_matrix = (chan_type == e_rr_type::CHANX) ? chanx_ptc : chany_ptc; + + // Step 2: Find the maximum next-free ptc value across all (x,y) cells + // spanned by this SG link. We use the max to ensure that the chosen + // ptc number is free along the entire length of the node + int ptc = 0; + for (int x = xlow; x <= xhigh; x++) { + for (int y = ylow; y <= yhigh; y++) { + ptc = std::max(ptc, ptc_matrix[layer][x][y]); + } + } + + // Step 3: Sanity check: no existing node should occupy this (layer,x,y,ptc) + VTR_ASSERT(rr_graph_builder.node_lookup().find_nodes_in_range(layer, xlow, ylow, xhigh, yhigh, chan_type, ptc).empty()); + + // Step 4: Allocate a new RR node ID and record its (inode, ptc) + const RRNodeId inode = RRNodeId(index); + node_indices.push_back({inode, ptc}); + index++; + + // Step 5: Register this node in the spatial lookup for every (x,y) + // location it spans, and update ptc_matrix to mark this track as used. + for (int x = xlow; x <= xhigh; x++) { + for (int y = ylow; y <= yhigh; y++) { + rr_graph_builder.node_lookup().add_node(inode, layer, x, y, chan_type, ptc); + ptc_matrix[layer][x][y] = ptc + 1; + } + } + } + + // Later, another routine will use this info to add nodes and edges to RR graph + return node_indices; +} + void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder, t_physical_tile_type_ptr physical_tile, const t_physical_tile_loc& root_loc, diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.h b/vpr/src/route/rr_graph_generation/rr_node_indices.h index ef2b34ef1be..242524c8b9c 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.h +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.h @@ -41,6 +41,19 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder, const vtr::NdMatrix, 2>& interdie_3d_links, int* index); +/** + * @brief Allocates RR nodes for non-3D scatter–gather links. + * + * Creates RR node indices for each bottleneck link, assigns track numbers + * within CHANX/CHANY channels, and updates the RR graph lookup tables. + * + * @return A list of created RR node IDs paired with their track numbers. + */ +std::vector> alloc_and_load_non_3d_sg_pattern_rr_node_indices(RRGraphBuilder& rr_graph_builder, + const std::vector& bottleneck_links, + const t_chan_width& chan_width_inf, + int& index); + /** * @brief Allocates and loads RR node indices for a specific tile. * diff --git a/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.cpp b/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.cpp index c6cd2375e4c..c368e6e7725 100644 --- a/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.cpp +++ b/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.cpp @@ -258,7 +258,7 @@ bool sb_not_here(const DeviceGrid& grid, const std::vector& inter_cluster_rr, const t_physical_tile_loc& loc, e_sb_location sb_location, - const t_specified_loc& specified_loc /*=t_specified_loc()*/) { + const t_specified_loc& specified_loc) { if (!inter_cluster_rr[loc.layer_num]) { return true; } diff --git a/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.h b/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.h index a6b34036c2b..cec25477fcf 100644 --- a/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.h +++ b/vpr/src/route/rr_graph_generation/switchblock_scatter_gather_common_utils.h @@ -53,7 +53,7 @@ bool sb_not_here(const DeviceGrid& grid, const std::vector& inter_cluster_rr, const t_physical_tile_loc& loc, e_sb_location sb_location, - const t_specified_loc& specified_loc = t_specified_loc()); + const t_specified_loc& specified_loc); /** * @brief finds the correct channel (x or y), and the coordinates to index into it based on the diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 8b5305b51ef..042448e9252 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1756,14 +1756,14 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, */ std::vector opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x() + grid_type->pin_width_offset[opin], from_grid_coordinate.y() + grid_type->pin_height_offset[opin], opin); if (1 != opin_grid_side.size()) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] From pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, opin, directs[i].from_pin.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] From pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, opin, directs[i].from_pin.c_str()); } /* directs[i].sub_tile_offset is added to from_capacity(z) to get the target_capacity */ int to_subtile_cap = z + directs[i].sub_tile_offset; /* If the destination subtile is out of range, there is no qualified IPINs */ if (to_subtile_cap < 0 || to_subtile_cap >= to_grid_type->capacity) { - continue; + continue; } /* Iterate over all sub_tiles to get the sub_tile which the target_cap belongs to. */ const t_sub_tile* to_sub_tile = nullptr; @@ -1780,7 +1780,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, int ipin = get_physical_pin_from_capacity_location(to_grid_type, relative_ipin, to_subtile_cap); std::vector ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x() + to_grid_type->pin_width_offset[ipin], to_grid_coordinate.y() + to_grid_type->pin_height_offset[ipin], ipin); if (1 != ipin_grid_side.size()) { - VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] To pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, relative_ipin, directs[i].to_pin.c_str()); + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "[Arch LINE %d] To pin (index=%d) of direct connection '%s' does not exist on any side of the programmable block '%s'.\n", directs[i].line, relative_ipin, directs[i].to_pin.c_str()); } RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, @@ -1794,10 +1794,10 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, /* add edges to the opin_node */ if (!opin_node_id) { - VTR_ASSERT(opin_node_id); + VTR_ASSERT(opin_node_id); } if (!ipin_node_id) { - VTR_ASSERT(opin_node_id); + VTR_ASSERT(opin_node_id); } rr_graph_builder.create_edge_in_cache(opin_node_id, ipin_node_id, RRSwitchId(clb_to_clb_directs[i].switch_index), false); } diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index 9fc49b4e42f..03fe295edb5 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -487,7 +487,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches[node] = delayless_switch; // RC data - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(0., 0., rr_rc_data)); } // End of loading OPIN rr_nodes } // End of side enumeration @@ -540,7 +540,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches[node] = wire_to_ipin_switch; // RC data - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(0., 0., rr_rc_data)); } // End of loading IPIN rr_nodes } // End of side enumeration @@ -589,7 +589,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build rr_node_driver_switches[node] = delayless_switch; // RC data - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(0., 0., rr_rc_data)); } // End of class enumeration } @@ -637,7 +637,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder rr_node_driver_switches[node] = delayless_switch; // RC data - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(0., 0., rr_rc_data)); } // End of class enumeration } @@ -672,7 +672,7 @@ static void load_one_grid_mux_nodes_basic_info(RRGraphBuilder& rr_graph_builder, rr_node_driver_switches[node] = RRSwitchId(vib->get_switch_idx()); // RC data - rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + rr_graph_builder.set_node_rc_index(node, find_create_rr_rc_data(0., 0., rr_rc_data)); } } @@ -900,7 +900,7 @@ static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; - rr_graph_builder.set_node_rc_index(rr_node_id, NodeRCIndex(find_create_rr_rc_data(node_R, node_C, rr_rc_data))); + rr_graph_builder.set_node_rc_index(rr_node_id, find_create_rr_rc_data(node_R, node_C, rr_rc_data)); if (chan_details.is_track_start(itrack)) { rr_graph_builder.set_node_bend_start(rr_node_id, chan_details.get_track_bend_start(itrack)); diff --git a/vtr_flow/arch/interposer/k6_N10_40nm_interposer.xml b/vtr_flow/arch/interposer/k6_N10_40nm_interposer.xml index eec03e97c74..55263cc95bb 100644 --- a/vtr_flow/arch/interposer/k6_N10_40nm_interposer.xml +++ b/vtr_flow/arch/interposer/k6_N10_40nm_interposer.xml @@ -114,10 +114,16 @@ - - - + + + + + + + + + @@ -148,6 +154,7 @@ We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. --> + @@ -168,11 +175,15 @@ and changing the number of 1's (or 0's) in the - + 1 1 1 1 1 1 1 1 1 + + + + @@ -325,20 +336,22 @@ - + - - - + + + + + + + - - - - - - - - + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt index 2ecd91cf0e2..360b02379b6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/gen_mass_report/config/config.txt @@ -24,5 +24,5 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements_ap.txt # Script parameters -script_params_common=-track_memory_usage --analytical_place --route --ap_generate_mass_report on +script_params_common=-track_memory_usage --analytical_place --route --ap_generate_mass_report on --device unnamed_device diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/config.txt index 7724b2c889a..6681e64bbd5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/config.txt @@ -12,7 +12,6 @@ archs_dir=arch/custom_grid circuit_list_add=raygentop.v # Add architectures to list to sweep -arch_list_add=fixed_grid.xml arch_list_add=column_io.xml arch_list_add=multiwidth_blocks.xml arch_list_add=non_column.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 093676f609c..3beb6c1013d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,5 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 17.26 vpr 85.18 MiB -1 -1 1.99 42340 4 0.56 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87220 236 305 3177 2989 1 1517 675 25 25 625 -1 25x25 46.3 MiB 2.03 30552.8 14077 237395 78558 156700 2137 85.2 MiB 1.24 0.02 6.54728 4.56956 -2883.52 -4.56956 4.56956 0.59 0.00510036 0.0045553 0.478327 0.433095 -1 -1 -1 -1 56 26200 45 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 7.42 1.96901 1.80319 68115 457904 -1 22555 19 6811 19098 2015069 507374 4.83769 4.83769 -3127.42 -4.83769 0 0 2.89946e+06 4639.14 0.10 0.64 0.31 -1 -1 0.10 0.288232 0.270013 column_io.xml raygentop.v common 17.82 vpr 84.73 MiB -1 -1 1.83 42716 4 0.55 -1 -1 36980 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 86760 236 305 3177 2989 1 1517 675 25 25 625 io auto 45.9 MiB 2.03 28735.7 12823 269944 91841 150002 28101 84.7 MiB 1.31 0.02 6.40411 4.48404 -2791.58 -4.48404 4.48404 0.52 0.00521698 0.00467311 0.509336 0.461746 -1 -1 -1 -1 56 25953 39 2.82259e+07 9.76854e+06 2.10191e+06 3363.06 8.45 2.51155 2.29649 61008 409515 -1 22418 17 6198 16171 1634792 415988 4.80994 4.80994 -3067.42 -4.80994 0 0 2.68365e+06 4293.83 0.09 0.57 0.28 -1 -1 0.09 0.272003 0.256238 multiwidth_blocks.xml raygentop.v common 17.23 vpr 84.99 MiB -1 -1 1.90 42532 4 0.57 -1 -1 36716 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87028 236 305 3177 2989 1 1517 675 19 19 361 io clb auto 45.9 MiB 1.98 26256.7 13417 228518 71674 152513 4331 85.0 MiB 1.15 0.02 6.15992 4.61893 -2885.89 -4.61893 4.61893 0.26 0.0053293 0.00477846 0.433268 0.393945 -1 -1 -1 -1 64 25958 35 1.65001e+07 9.76854e+06 1.21492e+06 3365.43 8.56 2.43954 2.22189 35881 226057 -1 21615 21 6791 19110 2067703 557503 4.85645 4.85645 -3124.54 -4.85645 0 0 1.53033e+06 4239.13 0.05 0.64 0.16 -1 -1 0.05 0.302016 0.284216 non_column.xml raygentop.v common 18.43 vpr 98.71 MiB -1 -1 2.19 42532 4 0.55 -1 -1 36960 -1 -1 129 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 101080 236 305 3170 2982 1 1517 677 33 33 1089 io auto 47.8 MiB 2.08 37578.8 15176 276980 99233 136480 41267 97.2 MiB 1.29 0.02 7.54198 5.00926 -2873.75 -5.00926 5.00926 1.01 0.00471858 0.00431736 0.481962 0.436402 -1 -1 -1 -1 54 29848 41 5.44432e+07 9.87633e+06 3.30487e+06 3034.77 6.91 1.81197 1.64433 100302 649205 -1 25026 20 7001 18961 1915485 504481 5.15555 5.15555 -3132.11 -5.15555 0 0 4.28921e+06 3938.67 0.17 0.64 0.56 -1 -1 0.17 0.283887 0.264969 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/config.txt new file mode 100644 index 00000000000..fe3b37650a7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/config.txt @@ -0,0 +1,27 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/custom_grid + +# Add circuits to list to sweep +circuit_list_add=raygentop.v + +# Add architectures to list to sweep +arch_list_add=fixed_grid.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params =--device "25x25" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/golden_results.txt new file mode 100644 index 00000000000..de0f989f865 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid_fixed/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + fixed_grid.xml raygentop.v common 17.26 vpr 85.18 MiB -1 -1 1.99 42340 4 0.56 -1 -1 36976 -1 -1 127 236 1 6 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 87220 236 305 3177 2989 1 1517 675 25 25 625 -1 25x25 46.3 MiB 2.03 30552.8 14077 237395 78558 156700 2137 85.2 MiB 1.24 0.02 6.54728 4.56956 -2883.52 -4.56956 4.56956 0.59 0.00510036 0.0045553 0.478327 0.433095 -1 -1 -1 -1 56 26200 45 3.19446e+07 9.76854e+06 2.27235e+06 3635.76 7.42 1.96901 1.80319 68115 457904 -1 22555 19 6811 19098 2015069 507374 4.83769 4.83769 -3127.42 -4.83769 0 0 2.89946e+06 4639.14 0.10 0.64 0.31 -1 -1 0.10 0.288232 0.270013 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt index af567cfcfa4..2179581f62e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_modes/config/config.txt @@ -24,5 +24,4 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common = -starting_stage vpr -script_params = --pack +script_params_common = -starting_stage vpr --pack --device "32x32" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_report_router_lookahead/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_report_router_lookahead/config/config.txt index 84a5054444a..a99a64cea2d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_report_router_lookahead/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_report_router_lookahead/config/config.txt @@ -24,5 +24,5 @@ qor_parse_file=qor_standard.txt pass_requirements_file=pass_requirements.txt # Script parameters -script_params_common=-track_memory_usage --generate_router_lookahead_report on +script_params_common=-track_memory_usage --generate_router_lookahead_report on --device "unnamed_device" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index c7b9883e1bf..ce93cd79b9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -34,6 +34,7 @@ regression_tests/vtr_reg_strong/strong_clock_pll regression_tests/vtr_reg_strong/strong_cluster_seed_type regression_tests/vtr_reg_strong/strong_constant_outputs regression_tests/vtr_reg_strong/strong_custom_grid +regression_tests/vtr_reg_strong/strong_custom_grid_fixed regression_tests/vtr_reg_strong/strong_custom_pin_locs regression_tests/vtr_reg_strong/strong_custom_switch_block regression_tests/vtr_reg_strong/strong_custom_sb_loc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/config.txt index 828a9a80cf8..26a695fc243 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/config.txt @@ -12,7 +12,6 @@ archs_dir=arch/custom_grid circuit_list_add=raygentop.v # Add architectures to list to sweep -arch_list_add=fixed_grid.xml arch_list_add=column_io.xml arch_list_add=multiwidth_blocks.xml arch_list_add=non_column.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt index 1bdd513f244..7429d7c034f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,8 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - fixed_grid.xml raygentop.v common 18.46 vpr 87.04 MiB 0.27 31488 -1 -1 3 0.97 -1 -1 40040 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 89128 214 305 2963 2869 1 1441 650 25 25 625 -1 25x25 47.0 MiB 2.55 25907.4 12547 220142 66436 150269 3437 87.0 MiB 1.01 0.02 5.35403 4.41932 -2697.98 -4.41932 4.41932 0.58 0.00444414 0.00409095 0.381975 0.350292 -1 -1 -1 -1 48 25900 48 3.19446e+07 9.79696e+06 1.97188e+06 3155.02 9.57 1.81783 1.67396 64995 397836 -1 21571 17 6896 16934 2225922 559049 4.89967 4.89967 -3107.62 -4.89967 0 0 2.52596e+06 4041.53 0.08 0.52 0.25 -1 -1 0.08 0.21427 0.202465 column_io.xml raygentop.v common 14.58 vpr 86.57 MiB 0.26 31104 -1 -1 3 0.89 -1 -1 39900 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 88652 214 305 2963 2869 1 1441 650 25 25 625 io auto 46.7 MiB 2.49 25737.8 12044 245468 82104 140823 22541 86.6 MiB 1.10 0.02 5.96169 4.61982 -2725.2 -4.61982 4.61982 0.54 0.00452688 0.00417288 0.425843 0.390594 -1 -1 -1 -1 50 25560 24 2.82259e+07 9.79696e+06 1.88190e+06 3011.03 5.80 1.57579 1.44944 58512 365993 -1 21648 16 6081 14502 1687459 402383 4.72983 4.72983 -3044.61 -4.72983 0 0 2.41964e+06 3871.43 0.08 0.47 0.25 -1 -1 0.08 0.223716 0.211815 multiwidth_blocks.xml raygentop.v common 14.38 vpr 87.05 MiB 0.27 31488 -1 -1 3 0.93 -1 -1 39604 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 89140 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 47.0 MiB 2.48 24907.5 12260 231398 76314 148330 6754 87.1 MiB 1.13 0.02 5.20709 4.53139 -2725.59 -4.53139 4.53139 0.27 0.00449906 0.00415224 0.423529 0.389058 -1 -1 -1 -1 62 24216 32 1.65001e+07 9.79696e+06 1.17493e+06 3254.64 6.33 1.98624 1.82696 35161 215557 -1 20428 15 5742 14062 1580735 451792 4.94596 4.94596 -3038.74 -4.94596 0 0 1.46388e+06 4055.07 0.04 0.46 0.15 -1 -1 0.04 0.222959 0.211563 non_column.xml raygentop.v common 17.03 vpr 100.70 MiB 0.35 31872 -1 -1 3 0.99 -1 -1 39900 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 103116 214 305 2963 2869 1 1441 650 33 33 1089 io auto 48.4 MiB 2.64 32834.4 12755 267980 88868 135114 43998 99.6 MiB 1.15 0.02 6.75315 4.60291 -2726.15 -4.60291 4.60291 1.12 0.00446458 0.00410792 0.45853 0.420716 -1 -1 -1 -1 44 26432 44 5.44432e+07 9.79696e+06 2.74036e+06 2516.40 6.21 1.79343 1.64857 93774 543488 -1 21803 18 6226 15541 1720374 470085 4.99182 4.99182 -3024.45 -4.99182 0 0 3.56397e+06 3272.70 0.14 0.51 0.43 -1 -1 0.14 0.239616 0.225276 non_column_tall_aspect_ratio.xml raygentop.v common 15.82 vpr 99.49 MiB 0.37 31872 -1 -1 3 0.88 -1 -1 39884 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 101876 214 305 2963 2869 1 1441 650 23 46 1058 io auto 48.4 MiB 2.54 31907.6 12410 251096 85740 136677 28679 96.1 MiB 1.16 0.02 6.55506 4.68258 -2814.04 -4.68258 4.68258 0.98 0.00459635 0.00423049 0.452395 0.415808 -1 -1 -1 -1 52 23494 23 5.05849e+07 9.79696e+06 3.17293e+06 2998.99 5.07 1.59679 1.47145 97261 632982 -1 20696 16 5733 13978 1576274 434112 4.86141 4.86141 -3096.8 -4.86141 0 0 4.15960e+06 3931.57 0.20 0.58 0.51 -1 -1 0.20 0.275968 0.262225 non_column_wide_aspect_ratio.xml raygentop.v common 19.23 vpr 101.88 MiB 0.37 31872 -1 -1 3 0.90 -1 -1 39896 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 104324 214 305 2963 2869 1 1441 650 43 22 946 io auto 48.3 MiB 2.50 33702.5 13867 282050 98841 143573 39636 94.4 MiB 1.29 0.02 6.32754 4.9559 -2893.32 -4.9559 4.9559 0.87 0.00450797 0.00416286 0.528306 0.484543 -1 -1 -1 -1 50 24750 31 4.55909e+07 9.79696e+06 2.70028e+06 2854.41 9.13 2.30138 2.11561 84704 520009 -1 22155 16 5412 12820 1401514 376383 5.11908 5.11908 -3180.83 -5.11908 0 0 3.44953e+06 3646.44 0.12 0.42 0.41 -1 -1 0.12 0.212336 0.200865 custom_sbloc.xml raygentop.v common 12.43 vpr 86.75 MiB 0.27 31488 -1 -1 3 0.94 -1 -1 39508 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 88828 214 305 2963 2869 1 1441 650 19 19 361 io clb auto 47.0 MiB 2.56 24907.5 12293 225770 70817 148328 6625 86.7 MiB 1.11 0.02 5.21194 4.8033 -2758.45 -4.8033 4.8033 0.29 0.00449502 0.00412652 0.413606 0.379507 -1 -1 -1 -1 60 23435 27 1.65001e+07 9.79696e+06 1.11685e+06 3093.75 4.16 1.48655 1.37122 34801 214773 -1 20006 16 5631 13717 1408084 370803 4.96136 4.96136 -3017.4 -4.96136 0 0 1.41014e+06 3906.19 0.04 0.45 0.15 -1 -1 0.04 0.23404 0.221707 - multiple_io_types.xml raygentop.v common 68.41 vpr 472.32 MiB 0.27 31488 -1 -1 3 0.97 -1 -1 39732 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 483652 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 46.7 MiB 2.95 63663.1 26330 90698 3630 28163 58905 472.3 MiB 0.48 0.02 8.02054 4.60821 -3832.09 -4.60821 4.60821 13.04 0.00411404 0.00377571 0.166355 0.153309 -1 -1 -1 -1 50 42098 27 2.48753e+08 9.79696e+06 1.23326e+07 2747.29 40.78 2.11052 1.94491 397497 2315172 -1 37047 18 7970 19204 4037402 1017842 6.19704 6.19704 -4231.98 -6.19704 0 0 1.58642e+07 3534.01 0.61 0.86 1.76 -1 -1 0.61 0.229586 0.216267 + multiple_io_types.xml raygentop.v common 68.41 vpr 472.32 MiB 0.27 31488 -1 -1 3 0.97 -1 -1 39732 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 483652 214 305 2963 2869 1 1441 650 67 67 4489 io_left auto 46.7 MiB 2.95 63663.1 26330 90698 3630 28163 58905 472.3 MiB 0.48 0.02 8.02054 4.60821 -3832.09 -4.60821 4.60821 13.04 0.00411404 0.00377571 0.166355 0.153309 -1 -1 -1 -1 50 42098 27 2.48753e+08 9.79696e+06 1.23326e+07 2747.29 40.78 2.11052 1.94491 397497 2315172 -1 37047 18 7970 19204 4037402 1017842 6.19704 6.19704 -4231.98 -6.19704 0 0 1.58642e+07 3534.01 0.61 0.86 1.76 -1 -1 0.61 0.229586 0.216267 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/config.txt new file mode 100644 index 00000000000..3d17d127385 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/config.txt @@ -0,0 +1,27 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/custom_grid + +# Add circuits to list to sweep +circuit_list_add=raygentop.v + +# Add architectures to list to sweep +arch_list_add=fixed_grid.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params = -start odin --device "25x25" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/golden_results.txt new file mode 100644 index 00000000000..9a139360699 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + fixed_grid.xml raygentop.v common 18.46 vpr 87.04 MiB 0.27 31488 -1 -1 3 0.97 -1 -1 40040 -1 -1 123 214 0 8 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 89128 214 305 2963 2869 1 1441 650 25 25 625 -1 25x25 47.0 MiB 2.55 25907.4 12547 220142 66436 150269 3437 87.0 MiB 1.01 0.02 5.35403 4.41932 -2697.98 -4.41932 4.41932 0.58 0.00444414 0.00409095 0.381975 0.350292 -1 -1 -1 -1 48 25900 48 3.19446e+07 9.79696e+06 1.97188e+06 3155.02 9.57 1.81783 1.67396 64995 397836 -1 21571 17 6896 16934 2225922 559049 4.89967 4.89967 -3107.62 -4.89967 0 0 2.52596e+06 4041.53 0.08 0.52 0.25 -1 -1 0.08 0.21427 0.202465 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt index 2f20485a168..a71a85253ee 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt @@ -5,6 +5,7 @@ regression_tests/vtr_reg_strong_odin/strong_bounding_box regression_tests/vtr_reg_strong_odin/strong_cin_tie_off regression_tests/vtr_reg_strong_odin/strong_clock_modeling regression_tests/vtr_reg_strong_odin/strong_custom_grid +regression_tests/vtr_reg_strong_odin/strong_custom_grid_fixed regression_tests/vtr_reg_strong_odin/strong_custom_pin_locs regression_tests/vtr_reg_strong_odin/strong_custom_switch_block regression_tests/vtr_reg_strong_odin/strong_dedicated_clock